text stringlengths 9 39.2M | dir stringlengths 26 295 | lang stringclasses 185 values | created_date timestamp[us] | updated_date timestamp[us] | repo_name stringlengths 1 97 | repo_full_name stringlengths 7 106 | star int64 1k 183k | len_tokens int64 1 13.8M |
|---|---|---|---|---|---|---|---|---|
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* AT / PS/2 attached device emulation.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
#define HAVE_STDARG_H
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/ppi.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/machine.h>
#include <86box/m_at_t3100e.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sound.h>
#include <86box/snd_speaker.h>
#include <86box/video.h>
#include <86box/keyboard.h>
#include <86box/plat_fallthrough.h>
#ifdef ENABLE_KBC_AT_DEV_LOG
int kbc_at_dev_do_log = ENABLE_KBC_AT_DEV_LOG;
static void
kbc_at_dev_log(const char *fmt, ...)
{
va_list ap;
if (kbc_at_dev_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define kbc_at_dev_log(fmt, ...)
#endif
static void
kbc_at_dev_queue_reset(atkbc_dev_t *dev, uint8_t reset_main)
{
if (reset_main) {
dev->queue_start = dev->queue_end = 0;
memset(dev->queue, 0x00, sizeof(dev->queue));
}
dev->cmd_queue_start = dev->cmd_queue_end = 0;
memset(dev->cmd_queue, 0x00, sizeof(dev->cmd_queue));
}
uint8_t
kbc_at_dev_queue_pos(atkbc_dev_t *dev, uint8_t main)
{
uint8_t ret;
if (main)
ret = ((dev->queue_end - dev->queue_start) & dev->fifo_mask);
else
ret = ((dev->cmd_queue_end - dev->cmd_queue_start) & 0xf);
return ret;
}
void
kbc_at_dev_queue_add(atkbc_dev_t *dev, uint8_t val, uint8_t main)
{
if (main) {
kbc_at_dev_log("%s: dev->queue[%02X] = %02X;\n", dev->name, dev->queue_end, val);
dev->queue[dev->queue_end] = val;
dev->queue_end = (dev->queue_end + 1) & dev->fifo_mask;
} else {
kbc_at_dev_log("%s: dev->cmd_queue[%02X] = %02X;\n", dev->name, dev->cmd_queue_end, val);
dev->cmd_queue[dev->cmd_queue_end] = val;
dev->cmd_queue_end = (dev->cmd_queue_end + 1) & 0xf;
}
/* TODO: This should be done on actual send to host. */
if (val != 0xfe)
dev->last_scan_code = val;
}
static void
kbc_at_dev_poll(void *priv)
{
atkbc_dev_t *dev = (atkbc_dev_t *) priv;
switch (dev->state) {
case DEV_STATE_MAIN_1:
/* Process the command if needed and then return to main loop #2. */
if (dev->port->wantcmd) {
kbc_at_dev_log("%s: Processing keyboard command %02X...\n", dev->name, dev->port->dat);
kbc_at_dev_queue_reset(dev, 0);
dev->process_cmd(dev);
dev->port->wantcmd = 0;
} else
dev->state = DEV_STATE_MAIN_2;
break;
case DEV_STATE_MAIN_2:
/* Output from scan queue if needed and then return to main loop #1. */
if (!dev->ignore && *dev->scan && (dev->port->out_new == -1) &&
(dev->queue_start != dev->queue_end)) {
kbc_at_dev_log("%s: %02X (DATA) on channel 1\n", dev->name, dev->queue[dev->queue_start]);
dev->port->out_new = dev->queue[dev->queue_start];
dev->queue_start = (dev->queue_start + 1) & dev->fifo_mask;
}
if (dev->ignore || !(*dev->scan) || dev->port->wantcmd)
dev->state = DEV_STATE_MAIN_1;
break;
case DEV_STATE_MAIN_OUT:
/* If host wants to send command while we're sending a byte to host, process the command. */
if (dev->port->wantcmd) {
kbc_at_dev_log("%s: Processing keyboard command %02X...\n", dev->name, dev->port->dat);
kbc_at_dev_queue_reset(dev, 0);
dev->process_cmd(dev);
dev->port->wantcmd = 0;
break;
}
fallthrough;
case DEV_STATE_MAIN_WANT_IN:
/* Output command response and then return to main loop #2. */
if ((dev->port->out_new == -1) && (dev->cmd_queue_start != dev->cmd_queue_end)) {
kbc_at_dev_log("%s: %02X (CMD ) on channel 1\n", dev->name, dev->cmd_queue[dev->cmd_queue_start]);
dev->port->out_new = dev->cmd_queue[dev->cmd_queue_start];
dev->cmd_queue_start = (dev->cmd_queue_start + 1) & 0xf;
}
if (dev->cmd_queue_start == dev->cmd_queue_end)
dev->state++;
break;
case DEV_STATE_MAIN_IN:
/* Wait for host data. */
if (dev->port->wantcmd) {
kbc_at_dev_log("%s: Processing keyboard command %02X parameter %02X...\n", dev->name, dev->command, dev->port->dat);
kbc_at_dev_queue_reset(dev, 0);
dev->process_cmd(dev);
dev->port->wantcmd = 0;
}
break;
case DEV_STATE_EXECUTE_BAT:
dev->state = DEV_STATE_MAIN_OUT;
dev->execute_bat(dev);
break;
case DEV_STATE_MAIN_WANT_EXECUTE_BAT:
/* Output command response and then return to main loop #2. */
if ((dev->port->out_new == -1) && (dev->cmd_queue_start != dev->cmd_queue_end)) {
kbc_at_dev_log("%s: %02X (CMD ) on channel 1\n", dev->name, dev->cmd_queue[dev->cmd_queue_start]);
dev->port->out_new = dev->cmd_queue[dev->cmd_queue_start];
dev->cmd_queue_start = (dev->cmd_queue_start + 1) & 0xf;
}
if (dev->cmd_queue_start == dev->cmd_queue_end)
dev->state = DEV_STATE_EXECUTE_BAT;
break;
default:
break;
}
}
void
kbc_at_dev_reset(atkbc_dev_t *dev, int do_fa)
{
dev->port->out_new = -1;
dev->port->wantcmd = 0;
kbc_at_dev_queue_reset(dev, 1);
dev->last_scan_code = 0x00;
*dev->scan = 1;
if (do_fa) {
kbc_at_dev_queue_add(dev, 0xfa, 0);
dev->state = DEV_STATE_MAIN_WANT_EXECUTE_BAT;
} else
dev->state = DEV_STATE_EXECUTE_BAT;
}
atkbc_dev_t *
kbc_at_dev_init(uint8_t inst)
{
atkbc_dev_t *dev;
dev = (atkbc_dev_t *) calloc(1, sizeof(atkbc_dev_t));
dev->port = kbc_at_ports[inst];
if (dev->port != NULL) {
dev->port->priv = dev;
dev->port->poll = kbc_at_dev_poll;
}
/* Return our private data to the I/O layer. */
return dev;
}
``` | /content/code_sandbox/src/device/kbc_at_dev.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,902 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* General keyboard driver interface.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/machine.h>
#include <86box/keyboard.h>
#include <86box/plat.h>
#include "cpu.h"
int keyboard_scan;
#ifdef _WIN32
/* Windows: F8+F12 */
uint16_t key_prefix_1_1 = 0x042; /* F8 */
uint16_t key_prefix_1_2 = 0x000; /* Invalid */
uint16_t key_prefix_2_1 = 0x000; /* Invalid */
uint16_t key_prefix_2_2 = 0x000; /* Invalid */
uint16_t key_uncapture_1 = 0x058; /* F12 */
uint16_t key_uncapture_2 = 0x000; /* Invalid */
#else
/* WxWidgets cannot do two regular keys.. CTRL+END */
uint16_t key_prefix_1_1 = 0x01d; /* Left Ctrl */
uint16_t key_prefix_1_2 = 0x11d; /* Right Ctrl */
uint16_t key_prefix_2_1 = 0x000; /* Invalid */
uint16_t key_prefix_2_2 = 0x000; /* Invalid */
uint16_t key_uncapture_1 = 0x04f; /* Numpad End */
uint16_t key_uncapture_2 = 0x14f; /* End */
#endif
void (*keyboard_send)(uint16_t val);
static int recv_key[512] = { 0 }; /* keyboard input buffer */
static int recv_key_ui[512] = { 0 }; /* keyboard input buffer */
static int oldkey[512];
#if 0
static int keydelay[512];
#endif
static scancode *scan_table; /* scancode table for keyboard */
static uint8_t caps_lock = 0;
static uint8_t num_lock = 0;
static uint8_t scroll_lock = 0;
static uint8_t shift = 0;
void
keyboard_init(void)
{
memset(recv_key, 0x00, sizeof(recv_key));
keyboard_scan = 1;
scan_table = NULL;
memset(keyboard_set3_flags, 0x00, sizeof(keyboard_set3_flags));
keyboard_set3_all_repeat = 0;
keyboard_set3_all_break = 0;
}
void
keyboard_set_table(const scancode *ptr)
{
scan_table = (scancode *) ptr;
}
static uint8_t
fake_shift_needed(uint16_t scan)
{
switch (scan) {
case 0x137: /* Yes, Print Screen requires the fake shifts. */
case 0x147:
case 0x148:
case 0x149:
case 0x14a:
case 0x14b:
case 0x14d:
case 0x14f:
case 0x150:
case 0x151:
case 0x152:
case 0x153:
return 1;
default:
return 0;
}
}
void
key_process(uint16_t scan, int down)
{
const scancode *codes = scan_table;
int c;
if (!codes)
return;
if (!keyboard_scan || (keyboard_send == NULL))
return;
oldkey[scan] = down;
if (down && (codes[scan].mk[0] == 0))
return;
if (!down && (codes[scan].brk[0] == 0))
return;
/* TODO: The keyboard controller needs to report the AT flag to us here. */
if (is286 && ((keyboard_mode & 3) == 3)) {
if (!keyboard_set3_all_break && !down && !(keyboard_set3_flags[codes[scan].mk[0]] & 2))
return;
}
c = 0;
if (down) {
/* Send the special code indicating an opening fake shift might be needed. */
if (fake_shift_needed(scan))
keyboard_send(0x100);
while (codes[scan].mk[c] != 0)
keyboard_send(codes[scan].mk[c++]);
} else {
while (codes[scan].brk[c] != 0)
keyboard_send(codes[scan].brk[c++]);
/* Send the special code indicating a closing fake shift might be needed. */
if (fake_shift_needed(scan))
keyboard_send(0x101);
}
}
/* Handle a keystroke event from the UI layer. */
void
keyboard_input(int down, uint16_t scan)
{
/* Special case for E1 1D, translate it to 0100 - special case. */
if ((scan >> 8) == 0xe1) {
if ((scan & 0xff) == 0x1d)
scan = 0x0100;
/* Translate E0 xx scan codes to 01xx because we use 512-byte arrays for states
and scan code sets. */
} else if ((scan >> 8) == 0xe0) {
scan &= 0x00ff;
scan |= 0x0100; /* extended key code */
} else if ((scan >> 8) != 0x01)
scan &= 0x00ff; /* we can receive a scan code whose upper byte is 0x01,
this means we're the Win32 version running on windows
that already sends us preprocessed scan codes, which
means we then use the scan code as is, and need to
make sure we do not accidentally strip that upper byte */
if (recv_key[scan & 0x1ff] ^ down) {
if (down) {
switch (scan & 0x1ff) {
case 0x01d: /* Left Ctrl */
shift |= 0x01;
break;
case 0x11d: /* Right Ctrl */
shift |= 0x10;
break;
case 0x02a: /* Left Shift */
shift |= 0x02;
break;
case 0x036: /* Right Shift */
shift |= 0x20;
break;
case 0x038: /* Left Alt */
shift |= 0x04;
break;
case 0x138: /* Right Alt */
shift |= 0x40;
break;
case 0x15b: /* Left Windows */
shift |= 0x08;
break;
case 0x15c: /* Right Windows */
shift |= 0x80;
break;
default:
break;
}
} else {
switch (scan & 0x1ff) {
case 0x01d: /* Left Ctrl */
shift &= ~0x01;
break;
case 0x11d: /* Right Ctrl */
shift &= ~0x10;
break;
case 0x02a: /* Left Shift */
shift &= ~0x02;
break;
case 0x036: /* Right Shift */
shift &= ~0x20;
break;
case 0x038: /* Left Alt */
shift &= ~0x04;
break;
case 0x138: /* Right Alt */
shift &= ~0x40;
break;
case 0x15b: /* Left Windows */
shift &= ~0x08;
break;
case 0x15c: /* Right Windows */
shift &= ~0x80;
break;
case 0x03a: /* Caps Lock */
caps_lock ^= 1;
break;
case 0x045:
num_lock ^= 1;
break;
case 0x046:
scroll_lock ^= 1;
break;
default:
break;
}
}
}
/* pclog("Received scan code: %03X (%s)\n", scan & 0x1ff, down ? "down" : "up"); */
recv_key_ui[scan & 0x1ff] = down;
if (mouse_capture || !kbd_req_capture || video_fullscreen) {
recv_key[scan & 0x1ff] = down;
key_process(scan & 0x1ff, down);
}
}
static uint8_t
keyboard_do_break(uint16_t scan)
{
const scancode *codes = scan_table;
/* TODO: The keyboard controller needs to report the AT flag to us here. */
if (is286 && ((keyboard_mode & 3) == 3)) {
if (!keyboard_set3_all_break && !recv_key[scan] && !(keyboard_set3_flags[codes[scan].mk[0]] & 2))
return 0;
else
return 1;
} else
return 1;
}
/* Also called by the emulated keyboard controller to update the states of
Caps Lock, Num Lock, and Scroll Lock when receving the "Set keyboard LEDs"
command. */
void
keyboard_update_states(uint8_t cl, uint8_t nl, uint8_t sl)
{
caps_lock = cl;
num_lock = nl;
scroll_lock = sl;
}
uint8_t
keyboard_get_shift(void)
{
return shift;
}
void
keyboard_get_states(uint8_t *cl, uint8_t *nl, uint8_t *sl)
{
if (cl)
*cl = caps_lock;
if (nl)
*nl = num_lock;
if (sl)
*sl = scroll_lock;
}
/* Called by the UI to update the states of Caps Lock, Num Lock, and Scroll Lock. */
void
keyboard_set_states(uint8_t cl, uint8_t nl, uint8_t sl)
{
const scancode *codes = scan_table;
int i;
if (caps_lock != cl) {
i = 0;
while (codes[0x03a].mk[i] != 0)
keyboard_send(codes[0x03a].mk[i++]);
if (keyboard_do_break(0x03a)) {
i = 0;
while (codes[0x03a].brk[i] != 0)
keyboard_send(codes[0x03a].brk[i++]);
}
}
if (num_lock != nl) {
i = 0;
while (codes[0x045].mk[i] != 0)
keyboard_send(codes[0x045].mk[i++]);
if (keyboard_do_break(0x045)) {
i = 0;
while (codes[0x045].brk[i] != 0)
keyboard_send(codes[0x045].brk[i++]);
}
}
if (scroll_lock != sl) {
i = 0;
while (codes[0x046].mk[i] != 0)
keyboard_send(codes[0x046].mk[i++]);
if (keyboard_do_break(0x046)) {
i = 0;
while (codes[0x046].brk[i] != 0)
keyboard_send(codes[0x046].brk[i++]);
}
}
keyboard_update_states(cl, nl, sl);
}
int
keyboard_recv(uint16_t key)
{
return recv_key[key];
}
int
keyboard_recv_ui(uint16_t key)
{
return recv_key_ui[key];
}
/* Do we have Control-Alt-PgDn in the keyboard buffer? */
int
keyboard_isfsenter(void)
{
return ((recv_key_ui[0x01d] || recv_key_ui[0x11d]) && (recv_key_ui[0x038] || recv_key_ui[0x138]) && (recv_key_ui[0x049] || recv_key_ui[0x149]));
}
int
keyboard_isfsenter_up(void)
{
return (!recv_key_ui[0x01d] && !recv_key_ui[0x11d] && !recv_key_ui[0x038] && !recv_key_ui[0x138] && !recv_key_ui[0x049] && !recv_key_ui[0x149]);
}
/* Do we have Control-Alt-PgDn in the keyboard buffer? */
int
keyboard_isfsexit(void)
{
return ((recv_key_ui[0x01d] || recv_key_ui[0x11d]) && (recv_key_ui[0x038] || recv_key_ui[0x138]) && (recv_key_ui[0x051] || recv_key_ui[0x151]));
}
int
keyboard_isfsexit_up(void)
{
return (!recv_key_ui[0x01d] && !recv_key_ui[0x11d] && !recv_key_ui[0x038] && !recv_key_ui[0x138] && !recv_key_ui[0x051] && !recv_key_ui[0x151]);
}
/* Do we have the mouse uncapture combination in the keyboard buffer? */
int
keyboard_ismsexit(void)
{
if ((key_prefix_2_1 != 0x000) || (key_prefix_2_2 != 0x000))
return ((recv_key_ui[key_prefix_1_1] || recv_key_ui[key_prefix_1_2]) &&
(recv_key_ui[key_prefix_2_1] || recv_key_ui[key_prefix_2_2]) &&
(recv_key_ui[key_uncapture_1] || recv_key_ui[key_uncapture_2]));
else
return ((recv_key_ui[key_prefix_1_1] || recv_key_ui[key_prefix_1_2]) &&
(recv_key_ui[key_uncapture_1] || recv_key_ui[key_uncapture_2]));
}
``` | /content/code_sandbox/src/device/keyboard.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,133 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Intel 8042 (AT keyboard controller) emulation.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* EngiNerd, <webmaster.crrc@yahoo.it>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
#define HAVE_STDARG_H
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include "x86seg.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#include <86box/ppi.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/machine.h>
#include <86box/m_at_t3100e.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sound.h>
#include <86box/snd_speaker.h>
#include <86box/video.h>
#include <86box/keyboard.h>
#include <86box/dma.h>
#include <86box/pci.h>
#define STAT_PARITY 0x80
#define STAT_RTIMEOUT 0x40
#define STAT_TTIMEOUT 0x20
#define STAT_MFULL 0x20
#define STAT_UNLOCKED 0x10
#define STAT_CD 0x08
#define STAT_SYSFLAG 0x04
#define STAT_IFULL 0x02
#define STAT_OFULL 0x01
#define CCB_UNUSED 0x80
#define CCB_TRANSLATE 0x40
#define CCB_PCMODE 0x20
#define CCB_ENABLEKBD 0x10
#define CCB_IGNORELOCK 0x08
#define CCB_SYSTEM 0x04
#define CCB_ENABLEMINT 0x02
#define CCB_ENABLEKINT 0x01
#define CCB_MASK 0x68
#define MODE_MASK 0x6c
#define KBC_TYPE_ISA 0x00 /* AT ISA-based chips */
#define KBC_TYPE_PS2_1 0x01 /* PS2 on PS/2, type 1 */
#define KBC_TYPE_PS2_2 0x02 /* PS2 on PS/2, type 2 */
#define KBC_TYPE_GREEN 0x03 /* PS2 green controller */
#define KBC_TYPE_MASK 0x03
#define KBC_VEN_GENERIC 0x00
#define KBC_VEN_IBM_PS1 0x04
#define KBC_VEN_TOSHIBA 0x08
#define KBC_VEN_OLIVETTI 0x0c
#define KBC_VEN_AMI 0x10
#define KBC_VEN_TRIGEM_AMI 0x14
#define KBC_VEN_QUADTEL 0x18
#define KBC_VEN_PHOENIX 0x1c
#define KBC_VEN_ACER 0x20
#define KBC_VEN_NCR 0x24
#define KBC_VEN_ALI 0x28
#define KBC_VEN_SIEMENS 0x2c
#define KBC_VEN_COMPAQ 0x30
#define KBC_VEN_IBM 0x34
#define KBC_VEN_MASK 0x7c
#define KBC_FLAG_IS_ASIC 0x80000000
#define FLAG_CLOCK 0x01
#define FLAG_CACHE 0x02
#define FLAG_PS2 0x04
#define FLAG_PCI 0x08
enum {
STATE_RESET = 0, /* KBC reset state, only accepts command AA. */
STATE_KBC_DELAY_OUT, /* KBC is sending one single byte. */
STATE_KBC_AMI_OUT, /* KBC waiting for OBF - needed for AMIKey commands that require clearing of the output byte. */
STATE_MAIN_IBF, /* KBC checking if the input buffer is full. */
STATE_MAIN_KBD, /* KBC checking if the keyboard has anything to send. */
STATE_MAIN_AUX, /* KBC checking if the auxiliary has anything to send. */
STATE_MAIN_BOTH, /* KBC checking if either device has anything to send. */
STATE_KBC_OUT, /* KBC is sending multiple bytes. */
STATE_KBC_PARAM, /* KBC wants a parameter. */
STATE_SEND_KBD, /* KBC is sending command to the keyboard. */
STATE_SCAN_KBD, /* KBC is waiting for the keyboard command response. */
STATE_SEND_AUX, /* KBC is sending command to the auxiliary device. */
STATE_SCAN_AUX /* KBC is waiting for the auxiliary command response. */
};
typedef struct atkbc_t {
uint8_t state;
uint8_t command;
uint8_t command_phase;
uint8_t status;
uint8_t wantdata;
uint8_t ib;
uint8_t ob;
uint8_t sc_or;
uint8_t mem_addr;
uint8_t p1;
uint8_t p2;
uint8_t old_p2;
uint8_t misc_flags;
uint8_t ami_flags;
uint8_t key_ctrl_queue_start;
uint8_t key_ctrl_queue_end;
uint8_t val;
uint8_t channel;
uint8_t stat_hi;
uint8_t pending;
uint8_t irq_state;
uint8_t do_irq;
uint8_t is_asic;
uint8_t pad;
uint8_t mem[0x100];
/* Internal FIFO for the purpose of commands with multi-byte output. */
uint8_t key_ctrl_queue[64];
uint32_t flags;
/* Main timers. */
pc_timer_t kbc_poll_timer;
pc_timer_t kbc_dev_poll_timer;
/* P2 pulse callback timer. */
pc_timer_t pulse_cb;
/* Local copies of the pointers to both ports for easier swapping (AMI '5' MegaKey). */
kbc_at_port_t *ports[2];
uint8_t (*write60_ven)(void *priv, uint8_t val);
uint8_t (*write64_ven)(void *priv, uint8_t val);
} atkbc_t;
/* Keyboard controller ports. */
kbc_at_port_t *kbc_at_ports[2] = { NULL, NULL };
static uint8_t kbc_ami_revision = '8';
static uint8_t kbc_award_revision = 0x42;
static uint8_t kbc_handler_set = 0;
static void (*kbc_at_do_poll)(atkbc_t *dev);
/* Non-translated to translated scan codes. */
static const uint8_t nont_to_t[256] = {
0xff, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58,
0x64, 0x44, 0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59,
0x65, 0x38, 0x2a, 0x70, 0x1d, 0x10, 0x02, 0x5a,
0x66, 0x71, 0x2c, 0x1f, 0x1e, 0x11, 0x03, 0x5b,
0x67, 0x2e, 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c,
0x68, 0x39, 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d,
0x69, 0x31, 0x30, 0x23, 0x22, 0x15, 0x07, 0x5e,
0x6a, 0x72, 0x32, 0x24, 0x16, 0x08, 0x09, 0x5f,
0x6b, 0x33, 0x25, 0x17, 0x18, 0x0b, 0x0a, 0x60,
0x6c, 0x34, 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61,
0x6d, 0x73, 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e,
0x3a, 0x36, 0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76,
0x55, 0x56, 0x77, 0x78, 0x79, 0x7a, 0x0e, 0x7b,
0x7c, 0x4f, 0x7d, 0x4b, 0x47, 0x7e, 0x7f, 0x6f,
0x52, 0x53, 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45,
0x57, 0x4e, 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54,
0x80, 0x81, 0x82, 0x41, 0x54, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff
};
static const uint8_t multikey_vars[0x0b] = {
0x0a,
0x03, 0x1e, 0x27, 0x28, 0x29, 0x38, 0x39, 0x18, 0x19, 0x35
};
static uint8_t fast_reset = 0x00;
void
kbc_at_set_fast_reset(const uint8_t new_fast_reset)
{
fast_reset = new_fast_reset;
}
#ifdef ENABLE_KBC_AT_LOG
int kbc_at_do_log = ENABLE_KBC_AT_LOG;
static void
kbc_at_log(const char *fmt, ...)
{
va_list ap;
if (kbc_at_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define kbc_at_log(fmt, ...)
#endif
static void
kbc_at_queue_reset(atkbc_t *dev)
{
dev->key_ctrl_queue_start = dev->key_ctrl_queue_end = 0;
memset(dev->key_ctrl_queue, 0x00, sizeof(dev->key_ctrl_queue));
}
static void
kbc_at_queue_add(atkbc_t *dev, uint8_t val)
{
kbc_at_log("ATkbc: dev->key_ctrl_queue[%02X] = %02X;\n", dev->key_ctrl_queue_end, val);
dev->key_ctrl_queue[dev->key_ctrl_queue_end] = val;
dev->key_ctrl_queue_end = (dev->key_ctrl_queue_end + 1) & 0x3f;
dev->state = STATE_KBC_OUT;
}
static int
kbc_translate(atkbc_t *dev, uint8_t val)
{
int xt_mode = (dev->mem[0x20] & 0x20) && !(dev->misc_flags & FLAG_PS2);
/* The IBM AT keyboard controller firmware does not apply translation in XT mode. */
int translate = !xt_mode && ((dev->mem[0x20] & 0x40) || ((dev->flags & KBC_TYPE_MASK) == KBC_TYPE_PS2_2));
uint8_t kbc_ven = dev->flags & KBC_VEN_MASK;
int ret = - 1;
/* Allow for scan code translation. */
if (translate && (val == 0xf0)) {
kbc_at_log("ATkbc: translate is on, F0 prefix detected\n");
dev->sc_or = 0x80;
return ret;
}
/* Skip break code if translated make code has bit 7 set. */
if (translate && (dev->sc_or == 0x80) && (nont_to_t[val] & 0x80)) {
kbc_at_log("ATkbc: translate is on, skipping scan code: %02X (original: F0 %02X)\n", nont_to_t[val], val);
dev->sc_or = 0;
return ret;
}
/* Test for T3100E 'Fn' key (Right Alt / Right Ctrl) */
if ((dev != NULL) && (kbc_ven == KBC_VEN_TOSHIBA) &&
(keyboard_recv(0x138) || keyboard_recv(0x11d))) switch (val) {
case 0x4f:
t3100e_notify_set(0x01);
break; /* End */
case 0x50:
t3100e_notify_set(0x02);
break; /* Down */
case 0x51:
t3100e_notify_set(0x03);
break; /* PgDn */
case 0x52:
t3100e_notify_set(0x04);
break; /* Ins */
case 0x53:
t3100e_notify_set(0x05);
break; /* Del */
case 0x54:
t3100e_notify_set(0x06);
break; /* SysRQ */
case 0x45:
t3100e_notify_set(0x07);
break; /* NumLock */
case 0x46:
t3100e_notify_set(0x08);
break; /* ScrLock */
case 0x47:
t3100e_notify_set(0x09);
break; /* Home */
case 0x48:
t3100e_notify_set(0x0a);
break; /* Up */
case 0x49:
t3100e_notify_set(0x0b);
break; /* PgUp */
case 0x4a:
t3100e_notify_set(0x0c);
break; /* Keypad - */
case 0x4b:
t3100e_notify_set(0x0d);
break; /* Left */
case 0x4c:
t3100e_notify_set(0x0e);
break; /* KP 5 */
case 0x4d:
t3100e_notify_set(0x0f);
break; /* Right */
default:
break;
}
kbc_at_log("ATkbc: translate is %s, ", translate ? "on" : "off");
#ifdef ENABLE_KEYBOARD_AT_LOG
kbc_at_log("scan code: ");
if (translate) {
kbc_at_log("%02X (original: ", (nont_to_t[val] | dev->sc_or));
if (dev->sc_or == 0x80)
kbc_at_log("F0 ");
kbc_at_log("%02X)\n", val);
} else
kbc_at_log("%02X\n", val);
#endif
ret = translate ? (nont_to_t[val] | dev->sc_or) : val;
if (dev->sc_or == 0x80)
dev->sc_or = 0;
return ret;
}
static void
kbc_set_do_irq(atkbc_t *dev, uint8_t channel)
{
dev->channel = channel;
dev->do_irq = 1;
}
static void
kbc_do_irq(atkbc_t *dev)
{
if (dev->do_irq) {
/* WARNING: On PS/2, all IRQ's are level-triggered, but the IBM PS/2 KBC firmware is explicitly
written to pulse its P2 IRQ bits, so they should be kept as as edge-triggered here. */
picint_common(1 << 1, 0, 0, NULL);
picint_common(1 << 12, 0, 0, NULL);
if (dev->channel >= 2)
picint_common(1 << 12, 0, 1, NULL);
else
picint_common(1 << 1, 0, 1, NULL);
dev->do_irq = 0;
}
}
static void
kbc_send_to_ob(atkbc_t *dev, uint8_t val, uint8_t channel, uint8_t stat_hi)
{
uint8_t kbc_ven = dev->flags & KBC_VEN_MASK;
int temp = (channel == 1) ? kbc_translate(dev, val) : ((int) val);
if (temp == -1)
return;
if ((kbc_ven == KBC_VEN_AMI) || (kbc_ven == KBC_VEN_TRIGEM_AMI) ||
(dev->misc_flags & FLAG_PS2))
stat_hi |= ((dev->p1 & 0x80) ? 0x10 : 0x00);
else
stat_hi |= 0x10;
kbc_at_log("ATkbc: Sending %02X to the output buffer on channel %i...\n", temp, channel);
dev->status = (dev->status & ~0xf0) | STAT_OFULL | stat_hi;
dev->do_irq = 0;
/* WARNING: On PS/2, all IRQ's are level-triggered, but the IBM PS/2 KBC firmware is explicitly
written to pulse its P2 IRQ bits, so they should be kept as as edge-triggered here. */
if (dev->misc_flags & FLAG_PS2) {
if (channel >= 2) {
dev->status |= STAT_MFULL;
if (dev->mem[0x20] & 0x02)
kbc_set_do_irq(dev, channel);
} else if (dev->mem[0x20] & 0x01)
kbc_set_do_irq(dev, channel);
} else if (dev->mem[0x20] & 0x01)
picintlevel(1 << 1, &dev->irq_state); /* AT KBC: IRQ 1 is level-triggered because it is tied to OBF. */
#ifdef WRONG_CONDITION
if ((dev->channel > 0) || dev->is_asic || (kbc_ven == KBC_VEN_IBM_PS1) || (kbc_ven == KBC_VEN_IBM))
#endif
kbc_do_irq(dev);
dev->ob = temp;
}
static void
kbc_delay_to_ob(atkbc_t *dev, uint8_t val, uint8_t channel, uint8_t stat_hi)
{
dev->val = val;
dev->channel = channel;
dev->stat_hi = stat_hi;
dev->pending = 1;
dev->state = STATE_KBC_DELAY_OUT;
if (dev->is_asic && (channel == 0) && (dev->status & STAT_OFULL)) {
/* Expedite the sending to the output buffer to prevent the wrong
data from being accidentally read. */
kbc_send_to_ob(dev, dev->val, dev->channel, dev->stat_hi);
dev->state = STATE_MAIN_IBF;
dev->pending = 0;
}
}
static void kbc_at_process_cmd(void *priv);
static void
set_enable_kbd(atkbc_t *dev, uint8_t enable)
{
dev->mem[0x20] &= 0xef;
dev->mem[0x20] |= (enable ? 0x00 : 0x10);
}
static void
set_enable_aux(atkbc_t *dev, uint8_t enable)
{
dev->mem[0x20] &= 0xdf;
dev->mem[0x20] |= (enable ? 0x00 : 0x20);
}
static void
kbc_ibf_process(atkbc_t *dev)
{
/* IBF set, process both commands and data. */
dev->status &= ~STAT_IFULL;
dev->state = STATE_MAIN_IBF;
if (dev->status & STAT_CD)
kbc_at_process_cmd(dev);
else {
set_enable_kbd(dev, 1);
if ((dev->ports[0] != NULL) && (dev->ports[0]->priv != NULL)) {
dev->ports[0]->wantcmd = 1;
dev->ports[0]->dat = dev->ib;
dev->state = STATE_SEND_KBD;
} else
kbc_delay_to_ob(dev, 0xfe, 1, 0x40);
}
}
static void
kbc_scan_kbd_at(atkbc_t *dev)
{
if (!(dev->mem[0x20] & 0x10)) {
/* Both OBF and IBF clear and keyboard is enabled. */
/* XT mode. */
if (dev->mem[0x20] & 0x20) {
if ((dev->ports[0] != NULL) && (dev->ports[0]->out_new != -1)) {
kbc_send_to_ob(dev, dev->ports[0]->out_new, 1, 0x00);
dev->ports[0]->out_new = -1;
dev->state = STATE_MAIN_IBF;
} else if (dev->status & STAT_IFULL)
kbc_ibf_process(dev);
/* AT mode. */
} else {
#if 0
dev->t = dev->mem[0x28];
#endif
if (dev->mem[0x2e] != 0x00) {
#if 0
if (!(dev->t & 0x02))
return;
#endif
dev->mem[0x2e] = 0x00;
}
dev->p2 &= 0xbf;
if ((dev->ports[0] != NULL) && (dev->ports[0]->out_new != -1)) {
/* In our case, we never have noise on the line, so we can simplify this. */
/* Read data from the keyboard. */
if (dev->mem[0x20] & 0x40) {
if ((dev->mem[0x20] & 0x08) || (dev->p1 & 0x80))
kbc_send_to_ob(dev, dev->ports[0]->out_new, 1, 0x00);
dev->mem[0x2d] = (dev->ports[0]->out_new == 0xf0) ? 0x80 : 0x00;
} else
kbc_send_to_ob(dev, dev->ports[0]->out_new, 1, 0x00);
dev->ports[0]->out_new = -1;
dev->state = STATE_MAIN_IBF;
}
}
}
}
static void
write_p2(atkbc_t *dev, uint8_t val);
static void
kbc_at_poll_at(atkbc_t *dev)
{
switch (dev->state) {
case STATE_RESET:
if (dev->status & STAT_IFULL) {
dev->status = ((dev->status & 0x0f) | 0x10) & ~STAT_IFULL;
if ((dev->status & STAT_CD) && (dev->ib == 0xaa))
kbc_at_process_cmd(dev);
}
break;
case STATE_KBC_AMI_OUT:
if (dev->status & STAT_OFULL)
break;
fallthrough;
case STATE_MAIN_IBF:
default:
at_main_ibf:
if (dev->status & STAT_OFULL) {
/* OBF set, wait until it is cleared but still process commands. */
if ((dev->status & STAT_IFULL) && (dev->status & STAT_CD)) {
dev->status &= ~STAT_IFULL;
kbc_at_process_cmd(dev);
}
} else if (dev->status & STAT_IFULL)
kbc_ibf_process(dev);
else if (!(dev->mem[0x20] & 0x10))
dev->state = STATE_MAIN_KBD;
break;
case STATE_MAIN_KBD:
case STATE_MAIN_BOTH:
if (dev->status & STAT_IFULL)
kbc_ibf_process(dev);
else {
(void) kbc_scan_kbd_at(dev);
dev->state = STATE_MAIN_IBF;
}
break;
case STATE_KBC_DELAY_OUT:
/* Keyboard controller command want to output a single byte. */
kbc_at_log("ATkbc: %02X coming from channel %i with high status %02X\n", dev->val, dev->channel, dev->stat_hi);
kbc_send_to_ob(dev, dev->val, dev->channel, dev->stat_hi);
#if 0
dev->state = (dev->pending == 2) ? STATE_KBC_AMI_OUT : STATE_MAIN_IBF;
#endif
dev->state = STATE_MAIN_IBF;
dev->pending = 0;
goto at_main_ibf;
case STATE_KBC_OUT:
/* Keyboard controller command want to output multiple bytes. */
if (dev->status & STAT_IFULL) {
/* Data from host aborts dumping. */
dev->state = STATE_MAIN_IBF;
kbc_ibf_process(dev);
}
/* Do not continue dumping until OBF is clear. */
if (!(dev->status & STAT_OFULL)) {
kbc_at_log("ATkbc: %02X coming from channel 0\n", dev->key_ctrl_queue[dev->key_ctrl_queue_start]);
kbc_send_to_ob(dev, dev->key_ctrl_queue[dev->key_ctrl_queue_start], 0, 0x00);
dev->key_ctrl_queue_start = (dev->key_ctrl_queue_start + 1) & 0x3f;
if (dev->key_ctrl_queue_start == dev->key_ctrl_queue_end)
dev->state = STATE_MAIN_IBF;
}
break;
case STATE_KBC_PARAM:
/* Keyboard controller command wants data, wait for said data. */
if (dev->status & STAT_IFULL) {
/* Command written, abort current command. */
if (dev->status & STAT_CD)
dev->state = STATE_MAIN_IBF;
dev->status &= ~STAT_IFULL;
kbc_at_process_cmd(dev);
}
break;
case STATE_SEND_KBD:
if (!dev->ports[0]->wantcmd)
dev->state = STATE_SCAN_KBD;
break;
case STATE_SCAN_KBD:
kbc_scan_kbd_at(dev);
break;
}
}
/*
Correct Procedure:
1. Controller asks the device (keyboard or auxiliary device) for a byte.
2. The device, unless it's in the reset or command states, sees if there's anything to give it,
and if yes, begins the transfer.
3. The controller checks if there is a transfer, if yes, transfers the byte and sends it to the host,
otherwise, checks the next device, or if there is no device left to check, checks if IBF is full
and if yes, processes it.
*/
static int
kbc_scan_kbd_ps2(atkbc_t *dev)
{
if ((dev->ports[0] != NULL) && (dev->ports[0]->out_new != -1)) {
kbc_at_log("ATkbc: %02X coming from channel 1\n", dev->ports[0]->out_new & 0xff);
kbc_send_to_ob(dev, dev->ports[0]->out_new, 1, 0x00);
dev->ports[0]->out_new = -1;
dev->state = STATE_MAIN_IBF;
return 1;
}
return 0;
}
static int
kbc_scan_aux_ps2(atkbc_t *dev)
{
if ((dev->ports[1] != NULL) && (dev->ports[1]->out_new != -1)) {
kbc_at_log("ATkbc: %02X coming from channel 2\n", dev->ports[1]->out_new & 0xff);
kbc_send_to_ob(dev, dev->ports[1]->out_new, 2, 0x00);
dev->ports[1]->out_new = -1;
dev->state = STATE_MAIN_IBF;
return 1;
}
return 0;
}
static void
kbc_at_poll_ps2(atkbc_t *dev)
{
kbc_do_irq(dev);
switch (dev->state) {
case STATE_RESET:
if (dev->status & STAT_IFULL) {
dev->status = ((dev->status & 0x0f) | 0x10) & ~STAT_IFULL;
if ((dev->status & STAT_CD) && (dev->ib == 0xaa))
kbc_at_process_cmd(dev);
}
break;
case STATE_KBC_AMI_OUT:
if (dev->status & STAT_OFULL)
break;
fallthrough;
case STATE_MAIN_IBF:
default:
if (dev->status & STAT_IFULL)
kbc_ibf_process(dev);
else if (!(dev->status & STAT_OFULL)) {
if (dev->mem[0x20] & 0x20) {
if (!(dev->mem[0x20] & 0x10)) {
dev->p2 &= 0xbf;
dev->state = STATE_MAIN_KBD;
}
} else {
dev->p2 &= 0xf7;
if (dev->mem[0x20] & 0x10)
dev->state = STATE_MAIN_AUX;
else {
dev->p2 &= 0xbf;
dev->state = STATE_MAIN_BOTH;
}
}
}
break;
case STATE_MAIN_KBD:
if (dev->status & STAT_IFULL)
kbc_ibf_process(dev);
else {
(void) kbc_scan_kbd_ps2(dev);
dev->state = STATE_MAIN_IBF;
}
break;
case STATE_MAIN_AUX:
if (dev->status & STAT_IFULL)
kbc_ibf_process(dev);
else {
(void) kbc_scan_aux_ps2(dev);
dev->state = STATE_MAIN_IBF;
}
break;
case STATE_MAIN_BOTH:
if (kbc_scan_kbd_ps2(dev))
dev->state = STATE_MAIN_IBF;
else
dev->state = STATE_MAIN_AUX;
break;
case STATE_KBC_DELAY_OUT:
/* Keyboard controller command want to output a single byte. */
kbc_at_log("ATkbc: %02X coming from channel %i with high status %02X\n", dev->val, dev->channel, dev->stat_hi);
kbc_send_to_ob(dev, dev->val, dev->channel, dev->stat_hi);
#if 0
dev->state = (dev->pending == 2) ? STATE_KBC_AMI_OUT : STATE_MAIN_IBF;
#endif
dev->state = STATE_MAIN_IBF;
dev->pending = 0;
// goto ps2_main_ibf;
break;
case STATE_KBC_OUT:
/* Keyboard controller command want to output multiple bytes. */
if (dev->status & STAT_IFULL) {
/* Data from host aborts dumping. */
dev->state = STATE_MAIN_IBF;
kbc_ibf_process(dev);
}
/* Do not continue dumping until OBF is clear. */
if (!(dev->status & STAT_OFULL)) {
kbc_at_log("ATkbc: %02X coming from channel 0\n", dev->key_ctrl_queue[dev->key_ctrl_queue_start] & 0xff);
kbc_send_to_ob(dev, dev->key_ctrl_queue[dev->key_ctrl_queue_start], 0, 0x00);
dev->key_ctrl_queue_start = (dev->key_ctrl_queue_start + 1) & 0x3f;
if (dev->key_ctrl_queue_start == dev->key_ctrl_queue_end)
dev->state = STATE_MAIN_IBF;
}
break;
case STATE_KBC_PARAM:
/* Keyboard controller command wants data, wait for said data. */
if (dev->status & STAT_IFULL) {
/* Command written, abort current command. */
if (dev->status & STAT_CD)
dev->state = STATE_MAIN_IBF;
dev->status &= ~STAT_IFULL;
kbc_at_process_cmd(dev);
}
break;
case STATE_SEND_KBD:
if (!dev->ports[0]->wantcmd)
dev->state = STATE_SCAN_KBD;
break;
case STATE_SCAN_KBD:
(void) kbc_scan_kbd_ps2(dev);
break;
case STATE_SEND_AUX:
if (!dev->ports[1]->wantcmd)
dev->state = STATE_SCAN_AUX;
break;
case STATE_SCAN_AUX:
(void) kbc_scan_aux_ps2(dev);
break;
}
}
static void
kbc_at_poll(void *priv)
{
atkbc_t *dev = (atkbc_t *) priv;
timer_advance_u64(&dev->kbc_poll_timer, (100ULL * TIMER_USEC));
/* TODO: Implement the password security state. */
kbc_at_do_poll(dev);
}
static void
kbc_at_dev_poll(void *priv)
{
atkbc_t *dev = (atkbc_t *) priv;
timer_advance_u64(&dev->kbc_dev_poll_timer, (100ULL * TIMER_USEC));
if ((kbc_at_ports[0] != NULL) && (kbc_at_ports[0]->priv != NULL))
kbc_at_ports[0]->poll(kbc_at_ports[0]->priv);
if ((kbc_at_ports[1] != NULL) && (kbc_at_ports[1]->priv != NULL))
kbc_at_ports[1]->poll(kbc_at_ports[1]->priv);
}
static void
write_p2(atkbc_t *dev, uint8_t val)
{
uint8_t old = dev->p2;
kbc_at_log("ATkbc: write P2: %02X (old: %02X)\n", val, dev->p2);
uint8_t kbc_ven = dev->flags & KBC_VEN_MASK;
#if 0
/* PS/2: Handle IRQ's. */
if (dev->misc_flags & FLAG_PS2) {
/* IRQ 12 */
picint_common(1 << 12, 0, val & 0x20, NULL);
/* IRQ 1 */
picint_common(1 << 1, 0, val & 0x10, NULL);
}
#endif
/* AT, PS/2: Handle A20. */
if ((mem_a20_key ^ val) & 0x02) { /* A20 enable change */
mem_a20_key = val & 0x02;
mem_a20_recalc();
flushmmucache();
}
/* AT, PS/2: Handle reset. */
/* 0 holds the CPU in the RESET state, 1 releases it. To simplify this,
we just do everything on release. */
/* TODO: The fast reset flag's condition should be reversed - the BCM SQ-588
enables the flag and the CPURST on soft reset flag but expects this
to still soft reset instead. */
if ((fast_reset || !cpu_cpurst_on_sr) && ((old ^ val) & 0x01)) { /*Reset*/
if (!(val & 0x01)) { /* Pin 0 selected. */
/* Pin 0 selected. */
kbc_at_log("write_p2(): Pulse reset!\n");
if (machines[machine].flags & MACHINE_COREBOOT) {
/* The SeaBIOS hard reset code attempts a KBC reset if ACPI RESET_REG
is not available. However, the KBC reset is normally a soft reset, so
SeaBIOS gets caught in a soft reset loop as it tries to hard reset the
machine. Hack around this by making the KBC reset a hard reset only on
coreboot machines. */
pc_reset_hard();
} else {
softresetx86(); /* Pulse reset! */
cpu_set_edx();
flushmmucache();
if (kbc_ven == KBC_VEN_ALI)
smbase = 0x00030000;
/* Yes, this is a hack, but until someone gets ahold of the real PCD-2L
and can find out what they actually did to make it boot from FFFFF0
correctly despite A20 being gated when the CPU is reset, this will
have to do. */
if (kbc_ven == KBC_VEN_SIEMENS)
is486 ? loadcs(0xf000) : loadcs_2386(0xf000);
}
}
}
/* Do this here to avoid an infinite reset loop. */
dev->p2 = val;
if (!fast_reset && cpu_cpurst_on_sr && ((old ^ val) & 0x01)) { /*Reset*/
if (!(val & 0x01)) { /* Pin 0 selected. */
/* Pin 0 selected. */
kbc_at_log("write_p2(): Pulse reset!\n");
dma_reset();
dma_set_at(1);
device_reset_all(DEVICE_ALL);
cpu_alt_reset = 0;
pci_reset();
mem_a20_alt = 0;
mem_a20_recalc();
flushmmucache();
resetx86();
}
}
}
static void
write_p2_fast_a20(atkbc_t *dev, uint8_t val)
{
uint8_t old = dev->p2;
kbc_at_log("ATkbc: write P2 in fast A20 mode: %02X (old: %02X)\n", val, dev->p2);
/* AT, PS/2: Handle A20. */
if ((old ^ val) & 0x02) { /* A20 enable change */
mem_a20_key = val & 0x02;
mem_a20_recalc();
flushmmucache();
}
/* Do this here to avoid an infinite reset loop. */
dev->p2 = val;
}
static void
write_cmd(atkbc_t *dev, uint8_t val)
{
kbc_at_log("ATkbc: write command byte: %02X (old: %02X)\n", val, dev->mem[0x20]);
/* PS/2 type 2 keyboard controllers always force the XLAT bit to 0. */
if ((dev->flags & KBC_TYPE_MASK) == KBC_TYPE_PS2_2) {
val &= ~CCB_TRANSLATE;
dev->mem[0x20] &= ~CCB_TRANSLATE;
} else if (!(dev->misc_flags & FLAG_PS2)) {
if (val & 0x10)
dev->mem[0x2e] = 0x01;
}
kbc_at_log("ATkbc: keyboard interrupt is now %s\n", (val & 0x01) ? "enabled" : "disabled");
if (!(dev->misc_flags & FLAG_PS2)) {
/* Update P2 to mirror the IBF and OBF bits, if active. */
write_p2(dev, (dev->p2 & 0x0f) | ((val & 0x03) << 4) | ((val & 0x20) ? 0xc0 : 0x00));
}
kbc_at_log("ATkbc: Command byte now: %02X (%02X)\n", dev->mem[0x20], val);
dev->status = (dev->status & ~STAT_SYSFLAG) | (val & STAT_SYSFLAG);
}
static void
pulse_output(atkbc_t *dev, uint8_t mask)
{
if (mask != 0x0f) {
dev->old_p2 = dev->p2 & ~(0xf0 | mask);
kbc_at_log("ATkbc: pulse_output(): P2 now: %02X\n", dev->p2 & (0xf0 | mask));
write_p2(dev, dev->p2 & (0xf0 | mask));
timer_set_delay_u64(&dev->pulse_cb, 6ULL * TIMER_USEC);
}
}
static void
pulse_poll(void *priv)
{
atkbc_t *dev = (atkbc_t *) priv;
kbc_at_log("ATkbc: pulse_poll(): P2 now: %02X\n", dev->p2 | dev->old_p2);
write_p2(dev, dev->p2 | dev->old_p2);
}
static uint8_t
write64_generic(void *priv, uint8_t val)
{
atkbc_t *dev = (atkbc_t *) priv;
uint8_t current_drive;
uint8_t fixed_bits;
uint8_t kbc_ven = 0x0;
kbc_ven = dev->flags & KBC_VEN_MASK;
switch (val) {
case 0xa4: /* check if password installed */
if (dev->misc_flags & FLAG_PS2) {
kbc_at_log("ATkbc: check if password installed\n");
kbc_delay_to_ob(dev, 0xf1, 0, 0x00);
return 0;
}
break;
case 0xa5: /* load security */
kbc_at_log("ATkbc: load security\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xa7: /* disable auxiliary port */
if (dev->misc_flags & FLAG_PS2) {
kbc_at_log("ATkbc: disable auxiliary port\n");
set_enable_aux(dev, 0);
return 0;
}
break;
case 0xa8: /* Enable auxiliary port */
if (dev->misc_flags & FLAG_PS2) {
kbc_at_log("ATkbc: enable auxiliary port\n");
set_enable_aux(dev, 1);
return 0;
}
break;
case 0xa9: /* Test auxiliary port */
kbc_at_log("ATkbc: test auxiliary port\n");
if (dev->misc_flags & FLAG_PS2) {
kbc_delay_to_ob(dev, 0x00, 0, 0x00); /* no error, this is testing the channel 2 interface */
return 0;
}
break;
/* TODO: Make this command do nothing on the Regional HT6542,
or else, Efflixi's Award OPTi 495 BIOS gets a stuck key
in Norton Commander 3.0. */
case 0xaf: /* read keyboard version */
kbc_at_log("ATkbc: read keyboard version\n");
kbc_delay_to_ob(dev, kbc_award_revision, 0, 0x00);
return 0;
/*
P1 bits: 76543210
-----------------
IBM PS/1: xxxxxxxx
IBM PS/2 MCA: xxxxx1xx
Intel AMI Pentium BIOS'es with AMI MegaKey KB-5 keyboard controller: x1x1xxxx
Acer: xxxxx0xx
Packard Bell PB450: xxxxx1xx
P6RP4: xx1xx1xx
Epson Action Tower 2600: xxxx01xx
TriGem Hawk: xxxx11xx
Machine input based on current code: 11111111
Everything non-Green: Pull down bit 7 if not PS/2 and keyboard is inhibited.
Pull down bit 6 if primary display is CGA.
Xi8088: Pull down bit 6 if primary display is MDA.
Acer: Pull down bit 6 if primary display is MDA.
Pull down bit 2 always (must be so to enable CMOS Setup).
IBM PS/1: Pull down bit 6 if current floppy drive is 3.5".
Epson Action Tower 2600: Pull down bit 3 always (for Epson logo).
NCR: Pull down bit 5 always (power-on default speed = high).
Pull down bit 3 if there is no FPU.
Pull down bits 1 and 0 always?
Compaq: Pull down bit 6 if Compaq dual-scan display is in use.
Pull down bit 5 if system board DIP switch is ON.
Pull down bit 4 if CPU speed selected is auto.
Pull down bit 3 if CPU speed selected is slow (4 MHz).
Pull down bit 2 if FPU is present.
Pull down bits 1 and 0 always?
Bit 7: AT KBC only - keyboard inhibited (often physical lock): 0 = yes, 1 = no (also Compaq);
Bit 6: Mostly, display: 0 = CGA, 1 = MDA, inverted on Xi8088 and Acer KBC's;
Intel AMI MegaKey KB-5: Used for green features, SMM handler expects it to be set;
IBM PS/1 Model 2011: 0 = current FDD is 3.5", 1 = current FDD is 5.25";
Compaq: 0 = Compaq dual-scan display, 1 = non-Compaq display.
Bit 5: Mostly, manufacturing jumper: 0 = installed (infinite loop at POST), 1 = not installed;
NCR: power-on default speed: 0 = high, 1 = low;
Compaq: System board DIP switch 5: 0 = ON, 1 = OFF.
Bit 4: (Which board?): RAM on motherboard: 0 = 512 kB, 1 = 256 kB;
NCR: RAM on motherboard: 0 = unsupported, 1 = 512 kB;
Intel AMI MegaKey KB-5: Must be 1;
IBM PS/1: Ignored;
Compaq: 0 = Auto speed selected, 1 = High speed selected.
Bit 3: TriGem AMIKey: most significant bit of 2-bit OEM ID;
NCR: Coprocessor detect (1 = yes, 0 = no);
Compaq: 0 = Slow (4 MHz), 1 = Fast (8 MHz);
Sometimes configured for clock switching;
Bit 2: TriGem AMIKey: least significant bit of 2-bit OEM ID;
Bit 3, 2:
1, 1: TriGem logo;
1, 0: Garbled logo;
0, 1: Epson logo;
0, 0: Generic AMI logo.
NCR: Unused;
IBM PS/2: Keyboard power: 0 = no power (fuse error), 1 = OK
(for some reason, www.win.tue.nl has this in reverse);
Compaq: FPU: 0 = 80287, 1 = none;
Sometimes configured for clock switching;
Bit 1: PS/2: Auxiliary device data in;
Compaq: Reserved;
NCR: High/auto speed.
Bit 0: PS/2: Keyboard device data in;
Compaq: Reserved;
NCR: DMA mode.
*/
case 0xc0: /* read P1 */
kbc_at_log("ATkbc: read P1\n");
fixed_bits = 4;
/* The SMM handlers of Intel AMI Pentium BIOS'es expect bit 6 to be set. */
if ((kbc_ven == KBC_VEN_AMI) && ((dev->flags & KBC_TYPE_MASK) == KBC_TYPE_GREEN))
fixed_bits |= 0x40;
if (kbc_ven == KBC_VEN_IBM_PS1) {
current_drive = fdc_get_current_drive();
/* (B0 or F0) | (fdd_is_525(current_drive) on bit 6) */
kbc_delay_to_ob(dev, dev->p1 | fixed_bits | (fdd_is_525(current_drive) ? 0x40 : 0x00),
0, 0x00);
} else if (kbc_ven == KBC_VEN_NCR) {
/* switch settings
* bit 7: keyboard disable
* bit 6: display type (0 color, 1 mono)
* bit 5: power-on default speed (0 high, 1 low)
* bit 4: sense RAM size (0 unsupported, 1 512k on system board)
* bit 3: coprocessor detect
* bit 2: unused
* bit 1: high/auto speed
* bit 0: dma mode
*/
/* (B0 or F0) | 0x04 | (display on bit 6) | (fpu on bit 3) */
kbc_delay_to_ob(dev, (dev->p1 | fixed_bits | (video_is_mda() ? 0x40 : 0x00) | (hasfpu ? 0x08 : 0x00)) & 0xdf,
0, 0x00);
} else if (kbc_ven == KBC_VEN_TRIGEM_AMI) {
/* Bit 3, 2:
1, 1: TriGem logo;
1, 0: Garbled logo;
0, 1: Epson logo;
0, 0: Generic AMI logo. */
if (dev->misc_flags & FLAG_PCI)
fixed_bits |= 8;
/* (B0 or F0) | (0x04 or 0x0c) */
kbc_delay_to_ob(dev, dev->p1 | fixed_bits, 0, 0x00);
} else if (((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) && ((dev->flags & KBC_TYPE_MASK) < KBC_TYPE_GREEN))
/* (B0 or F0) | (0x08 or 0x0c) */
kbc_delay_to_ob(dev, ((dev->p1 | fixed_bits) & 0xf0) | (((dev->flags & KBC_VEN_MASK) == KBC_VEN_ACER) ? 0x08 : 0x0c), 0, 0x00);
else if (kbc_ven == KBC_VEN_COMPAQ)
kbc_delay_to_ob(dev, dev->p1 | (hasfpu ? 0x00 : 0x04), 0, 0x00);
else
/* (B0 or F0) | (0x04 or 0x44) */
kbc_delay_to_ob(dev, dev->p1 | fixed_bits, 0, 0x00);
dev->p1 = ((dev->p1 + 1) & 3) | (dev->p1 & 0xfc);
return 0;
case 0xc1: /*Copy bits 0 to 3 of P1 to status bits 4 to 7*/
if (dev->misc_flags & FLAG_PS2) {
kbc_at_log("ATkbc: copy bits 0 to 3 of P1 to status bits 4 to 7\n");
dev->status &= 0x0f;
dev->status |= (dev->p1 << 4);
return 0;
}
break;
case 0xc2: /*Copy bits 4 to 7 of P1 to status bits 4 to 7*/
if (dev->misc_flags & FLAG_PS2) {
kbc_at_log("ATkbc: copy bits 4 to 7 of P1 to status bits 4 to 7\n");
dev->status &= 0x0f;
dev->status |= (dev->p1 & 0xf0);
return 0;
}
break;
case 0xd3: /* write auxiliary output buffer */
if (dev->misc_flags & FLAG_PS2) {
kbc_at_log("ATkbc: write auxiliary output buffer\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
}
break;
case 0xd4: /* write to auxiliary port */
kbc_at_log("ATkbc: write to auxiliary port\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xf0 ... 0xff:
kbc_at_log("ATkbc: pulse %01X\n", val & 0x0f);
pulse_output(dev, val & 0x0f);
return 0;
default:
break;
}
kbc_at_log("ATkbc: bad command %02X\n", val);
return 1;
}
static uint8_t
write60_ami(void *priv, uint8_t val)
{
atkbc_t *dev = (atkbc_t *) priv;
switch (dev->command) {
/* 0x40 - 0x5F are aliases for 0x60-0x7F */
case 0x40 ... 0x5f:
kbc_at_log("ATkbc: AMI - alias write to %02X\n", dev->command & 0x1f);
dev->mem[(dev->command & 0x1f) + 0x20] = val;
if (dev->command == 0x60)
write_cmd(dev, val);
return 0;
case 0xaf: /* set extended controller RAM */
kbc_at_log("ATkbc: AMI - set extended controller RAM\n");
if (dev->command_phase == 1) {
dev->mem_addr = val;
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
dev->command_phase = 2;
} else if (dev->command_phase == 2) {
dev->mem[dev->mem_addr] = val;
dev->command_phase = 0;
}
return 0;
case 0xc1:
kbc_at_log("ATkbc: AMI MegaKey - write %02X to P1\n", val);
dev->p1 = val;
return 0;
case 0xcb: /* set keyboard mode */
kbc_at_log("ATkbc: AMI - set keyboard mode\n");
dev->ami_flags = val;
dev->misc_flags &= ~FLAG_PS2;
if (val & 0x01) {
kbc_at_log("ATkbc: AMI: Emulate PS/2 keyboard\n");
dev->misc_flags |= FLAG_PS2;
kbc_at_do_poll = kbc_at_poll_ps2;
} else {
kbc_at_log("ATkbc: AMI: Emulate AT keyboard\n");
kbc_at_do_poll = kbc_at_poll_at;
}
return 0;
default:
break;
}
return 1;
}
void
kbc_at_set_ps2(void *priv, const uint8_t ps2)
{
atkbc_t *dev = (atkbc_t *) priv;
dev->ami_flags = (dev->ami_flags & 0xfe) | (!!ps2);
dev->misc_flags &= ~FLAG_PS2;
if (ps2) {
dev->misc_flags |= FLAG_PS2;
kbc_at_do_poll = kbc_at_poll_ps2;
} else
kbc_at_do_poll = kbc_at_poll_at;
write_cmd(dev, ~dev->mem[0x20]);
write_cmd(dev, dev->mem[0x20]);
}
static uint8_t
write64_ami(void *priv, uint8_t val)
{
atkbc_t *dev = (atkbc_t *) priv;
uint8_t kbc_ven = dev->flags & KBC_VEN_MASK;
switch (val) {
case 0x00 ... 0x1f:
kbc_at_log("ATkbc: AMI - alias read from %08X\n", val);
kbc_delay_to_ob(dev, dev->mem[val + 0x20], 0, 0x00);
return 0;
case 0x40 ... 0x5f:
kbc_at_log("ATkbc: AMI - alias write to %08X\n", dev->command);
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xa0: /* copyright message */
kbc_at_queue_add(dev, 0x28);
kbc_at_queue_add(dev, 0x00);
return 0;
case 0xa1: /* get controller version */
kbc_at_log("ATkbc: AMI - get controller version\n");
kbc_delay_to_ob(dev, kbc_ami_revision, 0, 0x00);
return 0;
case 0xa2: /* clear keyboard controller lines P22/P23 */
if (!(dev->misc_flags & FLAG_PS2)) {
kbc_at_log("ATkbc: AMI - clear KBC lines P22 and P23\n");
write_p2(dev, dev->p2 & 0xf3);
kbc_delay_to_ob(dev, 0x00, 0, 0x00);
return 0;
}
break;
case 0xa3: /* set keyboard controller lines P22/P23 */
if (!(dev->misc_flags & FLAG_PS2)) {
kbc_at_log("ATkbc: AMI - set KBC lines P22 and P23\n");
write_p2(dev, dev->p2 | 0x0c);
kbc_delay_to_ob(dev, 0x00, 0, 0x00);
return 0;
}
break;
case 0xa4: /* write clock = low */
if (!(dev->misc_flags & FLAG_PS2)) {
kbc_at_log("ATkbc: AMI - write clock = low\n");
dev->misc_flags &= ~FLAG_CLOCK;
return 0;
}
break;
case 0xa5: /* write clock = high */
if (!(dev->misc_flags & FLAG_PS2)) {
kbc_at_log("ATkbc: AMI - write clock = high\n");
dev->misc_flags |= FLAG_CLOCK;
return 0;
}
case 0xa6: /* read clock */
if (!(dev->misc_flags & FLAG_PS2)) {
kbc_at_log("ATkbc: AMI - read clock\n");
kbc_delay_to_ob(dev, (dev->misc_flags & FLAG_CLOCK) ? 0xff : 0x00, 0, 0x00);
return 0;
}
break;
case 0xa7: /* write cache bad */
if (!(dev->misc_flags & FLAG_PS2)) {
kbc_at_log("ATkbc: AMI - write cache bad\n");
dev->misc_flags &= FLAG_CACHE;
return 0;
}
break;
case 0xa8: /* write cache good */
if (!(dev->misc_flags & FLAG_PS2)) {
kbc_at_log("ATkbc: AMI - write cache good\n");
dev->misc_flags |= FLAG_CACHE;
return 0;
}
break;
case 0xa9: /* read cache */
if (!(dev->misc_flags & FLAG_PS2)) {
kbc_at_log("ATkbc: AMI - read cache\n");
kbc_delay_to_ob(dev, (dev->misc_flags & FLAG_CACHE) ? 0xff : 0x00, 0, 0x00);
return 0;
}
break;
case 0xaf: /* set extended controller RAM */
if ((kbc_ven != KBC_VEN_SIEMENS) && (kbc_ven != KBC_VEN_ALI)) {
kbc_at_log("ATkbc: set extended controller RAM\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
dev->command_phase = 1;
return 0;
}
break;
case 0xb0 ... 0xb3:
/* set KBC lines P10-P13 (P1 bits 0-3) low */
kbc_at_log("ATkbc: set KBC lines P10-P13 (P1 bits 0-3) low\n");
if (!(dev->flags & DEVICE_PCI) || (val > 0xb1))
dev->p1 &= ~(1 << (val & 0x03));
kbc_delay_to_ob(dev, dev->ob, 0, 0x00);
dev->pending++;
return 0;
/* TODO: The ICS SB486PV sends command B4 but expects to read *TWO* bytes. */
case 0xb4: case 0xb5:
/* set KBC lines P22-P23 (P2 bits 2-3) low */
kbc_at_log("ATkbc: set KBC lines P22-P23 (P2 bits 2-3) low\n");
if (!(dev->flags & DEVICE_PCI))
write_p2(dev, dev->p2 & ~(4 << (val & 0x01)));
kbc_delay_to_ob(dev, dev->ob, 0, 0x00);
dev->pending++;
return 0;
case 0xb8 ... 0xbb:
/* set KBC lines P10-P13 (P1 bits 0-3) high */
kbc_at_log("ATkbc: set KBC lines P10-P13 (P1 bits 0-3) high\n");
if (!(dev->flags & DEVICE_PCI) || (val > 0xb9)) {
dev->p1 |= (1 << (val & 0x03));
kbc_delay_to_ob(dev, dev->ob, 0, 0x00);
dev->pending++;
}
return 0;
case 0xbc: case 0xbd:
/* set KBC lines P22-P23 (P2 bits 2-3) high */
kbc_at_log("ATkbc: set KBC lines P22-P23 (P2 bits 2-3) high\n");
if (!(dev->flags & DEVICE_PCI))
write_p2(dev, dev->p2 | (4 << (val & 0x01)));
kbc_delay_to_ob(dev, dev->ob, 0, 0x00);
dev->pending++;
return 0;
case 0xc1: /* write P1 */
kbc_at_log("ATkbc: AMI MegaKey - write P1\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xc4:
/* set KBC line P14 low */
kbc_at_log("ATkbc: set KBC line P14 (P1 bit 4) low\n");
dev->p1 &= 0xef;
kbc_delay_to_ob(dev, dev->ob, 0, 0x00);
dev->pending++;
return 0;
case 0xc5:
/* set KBC line P15 low */
kbc_at_log("ATkbc: set KBC line P15 (P1 bit 5) low\n");
dev->p1 &= 0xdf;
kbc_delay_to_ob(dev, dev->ob, 0, 0x00);
dev->pending++;
return 0;
case 0xc8:
/*
* unblock KBC lines P22/P23
* (allow command D1 to change bits 2/3 of P2)
*/
kbc_at_log("ATkbc: AMI - unblock KBC lines P22 and P23\n");
dev->ami_flags &= 0xfb;
return 0;
case 0xc9:
/*
* block KBC lines P22/P23
* (disallow command D1 from changing bits 2/3 of the port)
*/
kbc_at_log("ATkbc: AMI - block KBC lines P22 and P23\n");
dev->ami_flags |= 0x04;
return 0;
case 0xcc:
/* set KBC line P14 high */
kbc_at_log("ATkbc: set KBC line P14 (P1 bit 4) high\n");
dev->p1 |= 0x10;
kbc_delay_to_ob(dev, dev->ob, 0, 0x00);
dev->pending++;
return 0;
case 0xcd:
/* set KBC line P15 high */
kbc_at_log("ATkbc: set KBC line P15 (P1 bit 5) high\n");
dev->p1 |= 0x20;
kbc_delay_to_ob(dev, dev->ob, 0, 0x00);
dev->pending++;
return 0;
case 0xef: /* ??? - sent by AMI486 */
kbc_at_log("ATkbc: ??? - sent by AMI486\n");
return 0;
default:
break;
}
return write64_generic(dev, val);
}
static uint8_t
write60_phoenix(void *priv, uint8_t val)
{
atkbc_t *dev = (atkbc_t *) priv;
switch (dev->command) {
/* TODO: Make this actually load the password. */
case 0xa3: /* Load Extended Password */
kbc_at_log("ATkbc: Phoenix - Load Extended Password\n");
if (val == 0x00)
dev->command_phase = 0;
else {
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
}
return 0;
case 0xaf: /* Set Inactivity Timer */
kbc_at_log("ATkbc: Phoenix - Set Inactivity Timer\n");
dev->mem[0x3a] = val;
dev->command_phase = 0;
return 0;
case 0xb8: /* Set Extended Memory Access Index */
kbc_at_log("ATkbc: Phoenix - Set Extended Memory Access Index\n");
dev->mem_addr = val;
dev->command_phase = 0;
return 0;
case 0xbb: /* Set Extended Memory */
kbc_at_log("ATkbc: Phoenix - Set Extended Memory\n");
dev->mem[dev->mem_addr] = val;
dev->command_phase = 0;
return 0;
case 0xbd: /* Set MultiKey Variable */
kbc_at_log("ATkbc: Phoenix - Set MultiKey Variable\n");
if ((dev->mem_addr > 0) && (dev->mem_addr <= multikey_vars[0x00]))
dev->mem[multikey_vars[dev->mem_addr]] = val;
dev->command_phase = 0;
return 0;
case 0xc7: /* Set Port1 bits */
kbc_at_log("ATkbc: Phoenix - Set Port1 bits\n");
dev->p1 |= val;
dev->command_phase = 0;
return 0;
case 0xc8: /* Clear Port1 bits */
kbc_at_log("ATkbc: Phoenix - Clear Port1 bits\n");
dev->p1 &= ~val;
dev->command_phase = 0;
return 0;
case 0xc9: /* Set Port2 bits */
kbc_at_log("ATkbc: Phoenix - Set Port2 bits\n");
write_p2(dev, dev->p2 | val);
dev->command_phase = 0;
return 0;
case 0xca: /* Clear Port2 bits */
kbc_at_log("ATkbc: Phoenix - Clear Port2 bits\n");
write_p2(dev, dev->p2 & ~val);
dev->command_phase = 0;
return 0;
default:
break;
}
return 1;
}
static uint8_t
write64_phoenix(void *priv, uint8_t val)
{
atkbc_t *dev = (atkbc_t *) priv;
switch (val) {
case 0x00 ... 0x1f:
kbc_at_log("ATkbc: Phoenix - alias read from %08X\n", val);
kbc_delay_to_ob(dev, dev->mem[val + 0x20], 0, 0x00);
return 0;
case 0x40 ... 0x5f:
kbc_at_log("ATkbc: Phoenix - alias write to %08X\n", dev->command);
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xa2: /* Test Extended Password */
kbc_at_log("ATkbc: Phoenix - Test Extended Password\n");
kbc_at_queue_add(dev, 0xf1); /* Extended Password not loaded */
return 0;
/* TODO: Make this actually load the password. */
case 0xa3: /* Load Extended Password */
kbc_at_log("ATkbc: Phoenix - Load Extended Password\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xaf: /* Set Inactivity Timer */
kbc_at_log("ATkbc: Phoenix - Set Inactivity Timer\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xb8: /* Set Extended Memory Access Index */
kbc_at_log("ATkbc: Phoenix - Set Extended Memory Access Index\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xb9: /* Get Extended Memory Access Index */
kbc_at_log("ATkbc: Phoenix - Get Extended Memory Access Index\n");
kbc_at_queue_add(dev, dev->mem_addr);
return 0;
case 0xba: /* Get Extended Memory */
kbc_at_log("ATkbc: Phoenix - Get Extended Memory\n");
kbc_at_queue_add(dev, dev->mem[dev->mem_addr]);
return 0;
case 0xbb: /* Set Extended Memory */
kbc_at_log("ATkbc: Phoenix - Set Extended Memory\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xbc: /* Get MultiKey Variable */
kbc_at_log("ATkbc: Phoenix - Get MultiKey Variable\n");
if (dev->mem_addr == 0)
kbc_at_queue_add(dev, multikey_vars[dev->mem_addr]);
else if (dev->mem_addr <= multikey_vars[dev->mem_addr])
kbc_at_queue_add(dev, dev->mem[multikey_vars[dev->mem_addr]]);
else
kbc_at_queue_add(dev, 0xff);
return 0;
case 0xbd: /* Set MultiKey Variable */
kbc_at_log("ATkbc: Phoenix - Set MultiKey Variable\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xc7: /* Set Port1 bits */
kbc_at_log("ATkbc: Phoenix - Set Port1 bits\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xc8: /* Clear Port1 bits */
kbc_at_log("ATkbc: Phoenix - Clear Port1 bits\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xc9: /* Set Port2 bits */
kbc_at_log("ATkbc: Phoenix - Set Port2 bits\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
case 0xca: /* Clear Port2 bits */
kbc_at_log("ATkbc: Phoenix - Clear Port2 bits\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
/* TODO: Handle these three commands properly - configurable
revision level and proper CPU bits. */
case 0xd5: /* Read MultiKey code revision level */
kbc_at_log("ATkbc: Phoenix - Read MultiKey code revision level\n");
kbc_at_queue_add(dev, 0x04);
kbc_at_queue_add(dev, 0x16);
return 0;
case 0xd6: /* Read Version Information */
kbc_at_log("ATkbc: Phoenix - Read Version Information\n");
kbc_at_queue_add(dev, 0x81);
kbc_at_queue_add(dev, 0xac);
return 0;
case 0xd7: /* Read MultiKey model numbers */
kbc_at_log("ATkbc: Phoenix - Read MultiKey model numbers\n");
kbc_at_queue_add(dev, 0x02);
kbc_at_queue_add(dev, 0x87);
kbc_at_queue_add(dev, 0x02);
return 0;
default:
break;
}
return write64_generic(dev, val);
}
static uint8_t
write64_siemens(void *priv, uint8_t val)
{
atkbc_t *dev = (atkbc_t *) priv;
switch (val) {
case 0x92: /*Siemens Award - 92 sent by PCD-2L BIOS*/
kbc_at_log("Siemens Award - 92 sent by PCD-2L BIOS\n");
return 0;
case 0x94: /*Siemens Award - 94 sent by PCD-2L BIOS*/
kbc_at_log("Siemens Award - 94 sent by PCD-2L BIOS\n");
return 0;
case 0x9a: /*Siemens Award - 9A sent by PCD-2L BIOS*/
kbc_at_log("Siemens Award - 9A sent by PCD-2L BIOS\n");
return 0;
case 0x9c: /*Siemens Award - 9C sent by PCD-2L BIOS*/
kbc_at_log("Siemens Award - 9C sent by PCD-2L BIOS\n");
return 0;
case 0xa9: /*Siemens Award - A9 sent by PCD-2L BIOS*/
kbc_at_log("Siemens Award - A9 sent by PCD-2L BIOS\n");
return 0;
default:
break;
}
return write64_ami(dev, val);
}
static uint8_t
write60_quadtel(void *priv, UNUSED(uint8_t val))
{
const atkbc_t *dev = (atkbc_t *) priv;
switch (dev->command) {
case 0xcf: /*??? - sent by MegaPC BIOS*/
kbc_at_log("ATkbc: ??? - sent by MegaPC BIOS\n");
return 0;
default:
break;
}
return 1;
}
static uint8_t
write64_olivetti(void *priv, uint8_t val)
{
atkbc_t *dev = (atkbc_t *) priv;
switch (val) {
case 0x80: /* Olivetti-specific command */
/*
* bit 7: bus expansion board present (M300) / keyboard unlocked (M290)
* bits 4-6: ???
* bit 3: fast ram check (if inactive keyboard works erratically)
* bit 2: keyboard fuse present
* bits 0-1: ???
*/
kbc_delay_to_ob(dev, (0x0c | (is386 ? 0x00 : 0x80)) & 0xdf, 0, 0x00);
dev->p1 = ((dev->p1 + 1) & 3) | (dev->p1 & 0xfc);
return 0;
default:
break;
}
return write64_generic(dev, val);
}
static uint8_t
write64_quadtel(void *priv, uint8_t val)
{
atkbc_t *dev = (atkbc_t *) priv;
switch (val) {
case 0xaf:
kbc_at_log("ATkbc: bad KBC command AF\n");
return 1;
case 0xcf: /*??? - sent by MegaPC BIOS*/
kbc_at_log("ATkbc: ??? - sent by MegaPC BIOS\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
default:
break;
}
return write64_generic(dev, val);
}
static uint8_t
write60_toshiba(void *priv, uint8_t val)
{
const atkbc_t *dev = (atkbc_t *) priv;
switch (dev->command) {
case 0xb6: /* T3100e - set color/mono switch */
kbc_at_log("ATkbc: T3100e - set color/mono switch\n");
t3100e_mono_set(val);
return 0;
default:
break;
}
return 1;
}
static uint8_t
write64_toshiba(void *priv, uint8_t val)
{
atkbc_t *dev = (atkbc_t *) priv;
switch (val) {
case 0xaf:
kbc_at_log("ATkbc: bad KBC command AF\n");
return 1;
case 0xb0: /* T3100e: Turbo on */
kbc_at_log("ATkbc: T3100e: Turbo on\n");
t3100e_turbo_set(1);
return 0;
case 0xb1: /* T3100e: Turbo off */
kbc_at_log("ATkbc: T3100e: Turbo off\n");
t3100e_turbo_set(0);
return 0;
case 0xb2: /* T3100e: Select external display */
kbc_at_log("ATkbc: T3100e: Select external display\n");
t3100e_display_set(0x00);
return 0;
case 0xb3: /* T3100e: Select internal display */
kbc_at_log("ATkbc: T3100e: Select internal display\n");
t3100e_display_set(0x01);
return 0;
case 0xb4: /* T3100e: Get configuration / status */
kbc_at_log("ATkbc: T3100e: Get configuration / status\n");
kbc_delay_to_ob(dev, t3100e_config_get(), 0, 0x00);
return 0;
case 0xb5: /* T3100e: Get colour / mono byte */
kbc_at_log("ATkbc: T3100e: Get colour / mono byte\n");
kbc_delay_to_ob(dev, t3100e_mono_get(), 0, 0x00);
return 0;
case 0xb6: /* T3100e: Set colour / mono byte */
kbc_at_log("ATkbc: T3100e: Set colour / mono byte\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
/* TODO: Toshiba KBC mode switching. */
case 0xb7: /* T3100e: Emulate PS/2 keyboard */
case 0xb8: /* T3100e: Emulate AT keyboard */
dev->misc_flags &= ~FLAG_PS2;
if (val == 0xb7) {
kbc_at_log("ATkbc: T3100e: Emulate PS/2 keyboard\n");
dev->misc_flags |= FLAG_PS2;
kbc_at_do_poll = kbc_at_poll_ps2;
} else {
kbc_at_log("ATkbc: T3100e: Emulate AT keyboard\n");
kbc_at_do_poll = kbc_at_poll_at;
}
return 0;
case 0xbb: /* T3100e: Read 'Fn' key.
Return it for right Ctrl and right Alt; on the real
T3100e, these keystrokes could only be generated
using 'Fn'. */
kbc_at_log("ATkbc: T3100e: Read 'Fn' key\n");
if (keyboard_recv(0xb8) || /* Right Alt */
keyboard_recv(0x9d)) /* Right Ctrl */
kbc_delay_to_ob(dev, 0x04, 0, 0x00);
else
kbc_delay_to_ob(dev, 0x00, 0, 0x00);
return 0;
case 0xbc: /* T3100e: Reset Fn+Key notification */
kbc_at_log("ATkbc: T3100e: Reset Fn+Key notification\n");
t3100e_notify_set(0x00);
return 0;
case 0xc0: /* Read P1 */
kbc_at_log("ATkbc: read P1\n");
/* The T3100e returns all bits set except bit 6 which
* is set by t3100e_mono_set() */
dev->p1 = (t3100e_mono_get() & 1) ? 0xff : 0xbf;
kbc_delay_to_ob(dev, dev->p1, 0, 0x00);
return 0;
default:
break;
}
return write64_generic(dev, val);
}
static void
kbc_at_process_cmd(void *priv)
{
atkbc_t *dev = (atkbc_t *) priv;
int bad = 1;
uint8_t mask;
uint8_t kbc_ven = dev->flags & KBC_VEN_MASK;
uint8_t cmd_ac_conv[16] = { 0x0b, 2, 3, 4, 5, 6, 7, 8, 9, 0x0a, 0x1e, 0x30, 0x2e, 0x20, 0x12, 0x21 };
if (dev->status & STAT_CD) {
/* Controller command. */
dev->wantdata = 0;
dev->state = STATE_MAIN_IBF;
/* Clear the keyboard controller queue. */
kbc_at_queue_reset(dev);
switch (dev->ib) {
/* Read data from KBC memory. */
case 0x20 ... 0x3f:
kbc_delay_to_ob(dev, dev->mem[dev->ib], 0, 0x00);
if (dev->ib == 0x20)
dev->pending++;
break;
/* Write data to KBC memory. */
case 0x60 ... 0x7f:
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
break;
case 0xaa: /* self-test */
kbc_at_log("ATkbc: self-test\n");
if ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) {
if (dev->state != STATE_RESET) {
kbc_at_log("ATkbc: self-test reinitialization\n");
/* Yes, the firmware has an OR, but we need to make sure to keep any forcibly lowered bytes lowered. */
/* TODO: Proper P1 implementation, with OR and AND flags in the machine table. */
dev->p1 = dev->p1 & 0xff;
write_p2(dev, 0x4b);
picintc(0x1000);
picintc(0x0002);
}
dev->status = (dev->status & 0x0f) | 0x60;
dev->mem[0x20] = 0x30;
dev->mem[0x22] = 0x0b;
dev->mem[0x25] = 0x02;
dev->mem[0x27] = 0xf8;
dev->mem[0x28] = 0xce;
dev->mem[0x29] = 0x0b;
dev->mem[0x30] = 0x0b;
} else {
if (dev->state != STATE_RESET) {
kbc_at_log("ATkbc: self-test reinitialization\n");
/* Yes, the firmware has an OR, but we need to make sure to keep any forcibly lowered bytes lowered. */
/* TODO: Proper P1 implementation, with OR and AND flags in the machine table. */
dev->p1 = dev->p1 & 0xff;
write_p2(dev, 0xcf);
picintclevel(0x0002, &dev->irq_state);
dev->irq_state = 0;
}
dev->status = (dev->status & 0x0f) | 0x60;
dev->mem[0x20] = 0x10;
dev->mem[0x22] = 0x06;
dev->mem[0x25] = 0x01;
dev->mem[0x27] = 0xfb;
dev->mem[0x28] = 0xe0;
dev->mem[0x29] = 0x06;
}
dev->mem[0x21] = 0x01;
dev->mem[0x2a] = 0x10;
dev->mem[0x2b] = 0x20;
dev->mem[0x2c] = 0x15;
if (dev->ports[0] != NULL)
dev->ports[0]->out_new = -1;
if (dev->ports[1] != NULL)
dev->ports[1]->out_new = -1;
kbc_at_queue_reset(dev);
kbc_at_queue_add(dev, 0x55);
break;
case 0xab: /* interface test */
kbc_at_log("ATkbc: interface test\n");
kbc_delay_to_ob(dev, 0x00, 0, 0x00); /*no error*/
break;
case 0xac: /* diagnostic dump */
if (dev->misc_flags & FLAG_PS2) {
kbc_at_log("ATkbc: diagnostic dump\n");
dev->mem[0x30] = (dev->p1 & 0xf0) | 0x80;
dev->mem[0x31] = dev->p2;
dev->mem[0x32] = 0x00; /* T0 and T1. */
dev->mem[0x33] = 0x00; /* PSW - Program Status Word - always return 0x00 because we do not emulate this byte. */
/* 20 bytes in high nibble in set 1, low nibble in set 1, set 1 space format = 60 bytes. */
for (uint8_t i = 0; i < 20; i++) {
kbc_at_queue_add(dev, cmd_ac_conv[dev->mem[i + 0x20] >> 4]);
kbc_at_queue_add(dev, cmd_ac_conv[dev->mem[i + 0x20] & 0x0f]);
kbc_at_queue_add(dev, 0x39);
}
}
break;
case 0xad: /* disable keyboard */
kbc_at_log("ATkbc: disable keyboard\n");
set_enable_kbd(dev, 0);
break;
case 0xae: /* enable keyboard */
kbc_at_log("ATkbc: enable keyboard\n");
set_enable_kbd(dev, 1);
break;
case 0xc7: /* set port1 bits */
kbc_at_log("ATkbc: Phoenix - set port1 bits\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
break;
case 0xca: /* read keyboard mode */
kbc_at_log("ATkbc: AMI - read keyboard mode\n");
kbc_delay_to_ob(dev, dev->ami_flags, 0, 0x00);
break;
case 0xcb: /* set keyboard mode */
kbc_at_log("ATkbc: AMI - set keyboard mode\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
break;
case 0xd0: /* read P2 */
kbc_at_log("ATkbc: read P2\n");
mask = 0xff;
if ((kbc_ven != KBC_VEN_OLIVETTI) && !(dev->misc_flags & FLAG_PS2) && (dev->mem[0x20] & 0x10))
mask &= 0xbf;
kbc_delay_to_ob(dev, ((dev->p2 & 0xfd) | mem_a20_key) & mask, 0, 0x00);
break;
case 0xd1: /* write P2 */
kbc_at_log("ATkbc: write P2\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
break;
case 0xd2: /* write keyboard output buffer */
kbc_at_log("ATkbc: write keyboard output buffer\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
break;
case 0xdd: /* disable A20 address line */
case 0xdf: /* enable A20 address line */
kbc_at_log("ATkbc: %sable A20\n", (dev->ib == 0xdd) ? "dis" : "en");
write_p2_fast_a20(dev, (dev->p2 & 0xfd) | (dev->ib & 0x02));
break;
case 0xe0: /* read test inputs */
kbc_at_log("ATkbc: read test inputs\n");
kbc_delay_to_ob(dev, 0x00, 0, 0x00);
break;
default:
/*
* Unrecognized controller command.
*
* If we have a vendor-specific handler, run
* that. Otherwise, or if that handler fails,
* log a bad command.
*/
if (dev->write64_ven)
bad = dev->write64_ven(dev, dev->ib);
kbc_at_log(bad ? "ATkbc: bad controller command %02X\n" : "", dev->ib);
}
/* If the command needs data, remember the command. */
if (dev->wantdata)
dev->command = dev->ib;
} else if (dev->wantdata) {
/* Write data to controller. */
dev->wantdata = 0;
dev->state = STATE_MAIN_IBF;
switch (dev->command) {
case 0x60 ... 0x7f:
dev->mem[(dev->command & 0x1f) + 0x20] = dev->ib;
if (dev->command == 0x60)
write_cmd(dev, dev->ib);
break;
case 0xa5: /* load security */
if (dev->misc_flags & FLAG_PS2) {
kbc_at_log("ATkbc: load security (%02X)\n", dev->ib);
if (dev->ib != 0x00) {
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
}
}
break;
case 0xc7: /* set port1 bits */
kbc_at_log("ATkbc: Phoenix - set port1 bits\n");
dev->p1 |= dev->ib;
break;
case 0xd1: /* write P2 */
kbc_at_log("ATkbc: write P2\n");
/* Bit 2 of AMI flags is P22-P23 blocked (1 = yes, 0 = no),
discovered by reverse-engineering the AOpen Vi15G BIOS. */
if (dev->ami_flags & 0x04) {
/* If keyboard controller lines P22-P23 are blocked,
we force them to remain unchanged. */
dev->ib &= ~0x0c;
dev->ib |= (dev->p2 & 0x0c);
}
write_p2(dev, dev->ib | 0x01);
break;
case 0xd2: /* write to keyboard output buffer */
kbc_at_log("ATkbc: write to keyboard output buffer\n");
kbc_delay_to_ob(dev, dev->ib, 0, 0x00);
break;
case 0xd3: /* write to auxiliary output buffer */
kbc_at_log("ATkbc: write to auxiliary output buffer\n");
kbc_delay_to_ob(dev, dev->ib, 2, 0x00);
break;
case 0xd4: /* write to auxiliary port */
kbc_at_log("ATkbc: write to auxiliary port (%02X)\n", dev->ib);
if (dev->ib == 0xbb)
break;
if (strstr(machine_get_internal_name(), "pb41") != NULL)
cpu_override_dynarec = 1;
if (dev->misc_flags & FLAG_PS2) {
set_enable_aux(dev, 1);
if ((dev->ports[1] != NULL) && (dev->ports[1]->priv != NULL)) {
dev->ports[1]->wantcmd = 1;
dev->ports[1]->dat = dev->ib;
dev->state = STATE_SEND_AUX;
} else
kbc_delay_to_ob(dev, 0xfe, 2, 0x40);
}
break;
default:
/*
* Run the vendor-specific handler
* if we have one. Otherwise, or if
* it returns an error, log a bad
* controller command.
*/
if (dev->write60_ven)
bad = dev->write60_ven(dev, dev->ib);
if (bad) {
kbc_at_log("ATkbc: bad controller command %02x data %02x\n", dev->command, dev->ib);
}
}
}
}
static void
kbc_at_write(uint16_t port, uint8_t val, void *priv)
{
atkbc_t *dev = (atkbc_t *) priv;
uint8_t kbc_ven = dev->flags & KBC_VEN_MASK;
uint8_t fast_a20 = (kbc_ven != KBC_VEN_SIEMENS);
kbc_at_log("ATkbc: [%04X:%08X] write(%04X) = %02X\n", CS, cpu_state.pc, port, val);
switch (port) {
case 0x60:
dev->status &= ~STAT_CD;
if (fast_a20 && dev->wantdata && (dev->command == 0xd1)) {
kbc_at_log("ATkbc: write P2\n");
/* Fast A20 - ignore all other bits. */
write_p2_fast_a20(dev, (dev->p2 & 0xfd) | (val & 0x02));
dev->wantdata = 0;
dev->state = STATE_MAIN_IBF;
return;
}
break;
case 0x64:
dev->status |= STAT_CD;
if (fast_a20 && (val == 0xd1)) {
kbc_at_log("ATkbc: write P2\n");
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
dev->command = 0xd1;
return;
} else if (fast_reset && ((val & 0xf0) == 0xf0)) {
pulse_output(dev, val & 0x0f);
dev->state = STATE_MAIN_IBF;
return;
}
break;
default:
break;
}
dev->ib = val;
dev->status |= STAT_IFULL;
}
static uint8_t
kbc_at_read(uint16_t port, void *priv)
{
atkbc_t *dev = (atkbc_t *) priv;
uint8_t ret = 0xff;
if ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1)
cycles -= ISA_CYCLES(8);
switch (port) {
case 0x60:
ret = dev->ob;
dev->status &= ~STAT_OFULL;
/* TODO: IRQ is only tied to OBF on the AT KBC, on the PS/2 KBC, it is controlled by a P2 bit.
This also means that in AT mode, the IRQ is level-triggered. */
if (!(dev->misc_flags & FLAG_PS2))
picintclevel(1 << 1, &dev->irq_state);
if ((strstr(machine_get_internal_name(), "pb41") != NULL) && (cpu_override_dynarec == 1))
cpu_override_dynarec = 0;
break;
case 0x64:
ret = dev->status;
break;
default:
kbc_at_log("ATkbc: read(%04x) invalid!\n",port);
break;
}
kbc_at_log("ATkbc: [%04X:%08X] read (%04X) = %02X\n", CS, cpu_state.pc, port, ret);
return ret;
}
static void
kbc_at_reset(void *priv)
{
atkbc_t *dev = (atkbc_t *) priv;
uint8_t kbc_ven = dev->flags & KBC_VEN_MASK;
dev->status = STAT_UNLOCKED;
dev->mem[0x20] = 0x01;
dev->mem[0x20] |= CCB_TRANSLATE;
dev->command_phase = 0;
/* Set up the correct Video Type bits. */
if (!is286 || (kbc_ven == KBC_VEN_ACER))
dev->p1 = video_is_mda() ? 0xb0 : 0xf0;
else
dev->p1 = video_is_mda() ? 0xf0 : 0xb0;
kbc_at_log("ATkbc: P1 = %02x\n", dev->p1);
/* Disabled both the keyboard and auxiliary ports. */
set_enable_kbd(dev, 0);
set_enable_aux(dev, 0);
kbc_at_queue_reset(dev);
dev->sc_or = 0;
dev->ami_flags = ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) ? 0x01 : 0x00;
dev->misc_flags &= FLAG_PCI;
if ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) {
dev->misc_flags |= FLAG_PS2;
kbc_at_do_poll = kbc_at_poll_ps2;
picintc(0x1000);
picintc(0x0002);
} else {
kbc_at_do_poll = kbc_at_poll_at;
picintclevel(0x0002, &dev->irq_state);
dev->irq_state = 0;
}
dev->misc_flags |= FLAG_CACHE;
dev->p2 = 0xcd;
if ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) {
write_p2(dev, 0x4b);
} else {
/* The real thing writes CF and then AND's it with BF. */
write_p2(dev, 0x8f);
}
/* Stage 1. */
dev->status = (dev->status & 0x0f) | (dev->p1 & 0xf0);
}
static void
kbc_at_close(void *priv)
{
atkbc_t *dev = (atkbc_t *) priv;
#ifdef OLD_CODE
int max_ports = ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) ? 2 : 1;
#else
int max_ports = 2;
#endif
/* Stop timers. */
timer_disable(&dev->kbc_dev_poll_timer);
timer_disable(&dev->kbc_poll_timer);
for (int i = 0; i < max_ports; i++) {
if (kbc_at_ports[i] != NULL) {
free(kbc_at_ports[i]);
kbc_at_ports[i] = NULL;
}
}
free(dev);
}
void
kbc_at_handler(int set, void *priv)
{
if (kbc_handler_set) {
io_removehandler(0x0060, 1, kbc_at_read, NULL, NULL, kbc_at_write, NULL, NULL, priv);
io_removehandler(0x0064, 1, kbc_at_read, NULL, NULL, kbc_at_write, NULL, NULL, priv);
}
kbc_handler_set = set;
if (kbc_handler_set) {
io_sethandler(0x0060, 1, kbc_at_read, NULL, NULL, kbc_at_write, NULL, NULL, priv);
io_sethandler(0x0064, 1, kbc_at_read, NULL, NULL, kbc_at_write, NULL, NULL, priv);
}
}
static void *
kbc_at_init(const device_t *info)
{
atkbc_t *dev;
int max_ports;
dev = (atkbc_t *) malloc(sizeof(atkbc_t));
memset(dev, 0x00, sizeof(atkbc_t));
dev->flags = info->local;
dev->is_asic = !!(info->local & KBC_FLAG_IS_ASIC);
video_reset(gfxcard[0]);
kbc_at_reset(dev);
if (info->flags & DEVICE_PCI)
dev->misc_flags |= FLAG_PCI;
kbc_handler_set = 0;
kbc_at_handler(1, dev);
timer_add(&dev->kbc_poll_timer, kbc_at_poll, dev, 1);
timer_add(&dev->pulse_cb, pulse_poll, dev, 0);
timer_add(&dev->kbc_dev_poll_timer, kbc_at_dev_poll, dev, 1);
dev->write60_ven = NULL;
dev->write64_ven = NULL;
kbc_ami_revision = '8';
kbc_award_revision = 0x42;
switch (dev->flags & KBC_VEN_MASK) {
case KBC_VEN_SIEMENS:
kbc_ami_revision = '8';
kbc_award_revision = 0x42;
dev->write60_ven = write60_ami;
dev->write64_ven = write64_siemens;
break;
case KBC_VEN_ACER:
case KBC_VEN_GENERIC:
case KBC_VEN_NCR:
case KBC_VEN_IBM_PS1:
case KBC_VEN_IBM:
case KBC_VEN_COMPAQ:
dev->write64_ven = write64_generic;
break;
case KBC_VEN_OLIVETTI:
dev->write64_ven = write64_olivetti;
break;
case KBC_VEN_ALI:
kbc_ami_revision = 'F';
kbc_award_revision = 0x43;
dev->write60_ven = write60_ami;
dev->write64_ven = write64_ami;
break;
case KBC_VEN_TRIGEM_AMI:
kbc_ami_revision = 'Z';
dev->write60_ven = write60_ami;
dev->write64_ven = write64_ami;
break;
case KBC_VEN_AMI:
if ((dev->flags & KBC_TYPE_MASK) == KBC_TYPE_GREEN)
kbc_ami_revision = '5';
else if ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) {
if (cpu_64bitbus)
kbc_ami_revision = 'R';
else if (is486)
kbc_ami_revision = 'P';
else
kbc_ami_revision = 'H';
} else if (is386 && !is486) {
if (cpu_16bitbus)
kbc_ami_revision = 'D';
else
kbc_ami_revision = 'B';
} else if (!is386)
kbc_ami_revision = '8';
else
kbc_ami_revision = 'F';
dev->write60_ven = write60_ami;
dev->write64_ven = write64_ami;
break;
case KBC_VEN_PHOENIX:
dev->write60_ven = write60_phoenix;
dev->write64_ven = write64_phoenix;
break;
case KBC_VEN_QUADTEL:
dev->write60_ven = write60_quadtel;
dev->write64_ven = write64_quadtel;
break;
case KBC_VEN_TOSHIBA:
dev->write60_ven = write60_toshiba;
dev->write64_ven = write64_toshiba;
break;
default:
break;
}
#ifdef OLD_CODE
max_ports = ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) ? 2 : 1;
#else
max_ports = 2;
#endif
for (int i = 0; i < max_ports; i++) {
kbc_at_ports[i] = (kbc_at_port_t *) malloc(sizeof(kbc_at_port_t));
memset(kbc_at_ports[i], 0x00, sizeof(kbc_at_port_t));
kbc_at_ports[i]->out_new = -1;
}
dev->ports[0] = kbc_at_ports[0];
dev->ports[1] = kbc_at_ports[1];
/* The actual keyboard. */
device_add(&keyboard_at_generic_device);
fast_reset = 0x00;
return dev;
}
const device_t keyboard_at_device = {
.name = "PC/AT Keyboard",
.internal_name = "keyboard_at",
.flags = DEVICE_KBC,
.local = KBC_TYPE_ISA | KBC_VEN_GENERIC,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_at_siemens_device = {
.name = "PC/AT Keyboard",
.internal_name = "keyboard_at",
.flags = DEVICE_KBC,
.local = KBC_TYPE_ISA | KBC_VEN_SIEMENS,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_at_ami_device = {
.name = "PC/AT Keyboard (AMI)",
.internal_name = "keyboard_at_ami",
.flags = DEVICE_KBC,
.local = KBC_TYPE_ISA | KBC_VEN_AMI,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_at_tg_ami_device = {
.name = "PC/AT Keyboard (TriGem AMI)",
.internal_name = "keyboard_at_tg_ami",
.flags = DEVICE_KBC,
.local = KBC_TYPE_ISA | KBC_VEN_TRIGEM_AMI,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_at_toshiba_device = {
.name = "PC/AT Keyboard (Toshiba)",
.internal_name = "keyboard_at_toshiba",
.flags = DEVICE_KBC,
.local = KBC_TYPE_ISA | KBC_VEN_TOSHIBA,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_at_olivetti_device = {
.name = "PC/AT Keyboard (Olivetti)",
.internal_name = "keyboard_at_olivetti",
.flags = DEVICE_KBC,
.local = KBC_TYPE_ISA | KBC_VEN_OLIVETTI,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_at_ncr_device = {
.name = "PC/AT Keyboard (NCR)",
.internal_name = "keyboard_at_ncr",
.flags = DEVICE_KBC,
.local = KBC_TYPE_ISA | KBC_VEN_NCR,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_at_compaq_device = {
.name = "PC/AT Keyboard (Compaq)",
.internal_name = "keyboard_at_compaq",
.flags = DEVICE_KBC,
.local = KBC_TYPE_ISA | KBC_VEN_COMPAQ,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_device = {
.name = "PS/2 Keyboard",
.internal_name = "keyboard_ps2",
.flags = DEVICE_KBC,
.local = KBC_TYPE_PS2_1 | KBC_VEN_GENERIC,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_ps1_device = {
.name = "PS/2 Keyboard (IBM PS/1)",
.internal_name = "keyboard_ps2_ps1",
.flags = DEVICE_KBC,
.local = KBC_TYPE_PS2_1 | KBC_VEN_IBM_PS1,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_ps1_pci_device = {
.name = "PS/2 Keyboard (IBM PS/1)",
.internal_name = "keyboard_ps2_ps1_pci",
.flags = DEVICE_KBC | DEVICE_PCI,
.local = KBC_TYPE_PS2_1 | KBC_VEN_IBM_PS1,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_xi8088_device = {
.name = "PS/2 Keyboard (Xi8088)",
.internal_name = "keyboard_ps2_xi8088",
.flags = DEVICE_KBC,
.local = KBC_TYPE_PS2_1 | KBC_VEN_GENERIC,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_ami_device = {
.name = "PS/2 Keyboard (AMI)",
.internal_name = "keyboard_ps2_ami",
.flags = DEVICE_KBC,
.local = KBC_TYPE_PS2_1 | KBC_VEN_AMI,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_holtek_device = {
.name = "PS/2 Keyboard (Holtek)",
.internal_name = "keyboard_ps2_holtek",
.flags = DEVICE_KBC,
.local = KBC_TYPE_PS2_1 | KBC_VEN_AMI | KBC_FLAG_IS_ASIC,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_phoenix_device = {
.name = "PS/2 Keyboard (Phoenix)",
.internal_name = "keyboard_ps2_phoenix",
.flags = DEVICE_KBC,
.local = KBC_TYPE_PS2_1 | KBC_VEN_PHOENIX,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_tg_ami_device = {
.name = "PS/2 Keyboard (TriGem AMI)",
.internal_name = "keyboard_ps2_tg_ami",
.flags = DEVICE_KBC,
.local = KBC_TYPE_PS2_1 | KBC_VEN_TRIGEM_AMI,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_mca_1_device = {
.name = "PS/2 Keyboard (IBM PS/2 MCA Type 1)",
.internal_name = "keyboard_ps2_mca_1",
.flags = DEVICE_KBC,
.local = KBC_TYPE_PS2_1 | KBC_VEN_IBM,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_mca_2_device = {
.name = "PS/2 Keyboard (IBM PS/2 MCA Type 2)",
.internal_name = "keyboard_ps2_mca_2",
.flags = DEVICE_KBC,
.local = KBC_TYPE_PS2_2 | KBC_VEN_IBM,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_quadtel_device = {
.name = "PS/2 Keyboard (Quadtel/MegaPC)",
.internal_name = "keyboard_ps2_quadtel",
.flags = DEVICE_KBC,
.local = KBC_TYPE_PS2_1 | KBC_VEN_QUADTEL,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_pci_device = {
.name = "PS/2 Keyboard",
.internal_name = "keyboard_ps2_pci",
.flags = DEVICE_KBC | DEVICE_PCI,
.local = KBC_TYPE_PS2_1 | KBC_VEN_GENERIC,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_ami_pci_device = {
.name = "PS/2 Keyboard (AMI)",
.internal_name = "keyboard_ps2_ami_pci",
.flags = DEVICE_KBC | DEVICE_PCI,
.local = KBC_TYPE_PS2_1 | KBC_VEN_AMI,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_ali_pci_device = {
.name = "PS/2 Keyboard (ALi M5123/M1543C)",
.internal_name = "keyboard_ps2_ali_pci",
.flags = DEVICE_KBC | DEVICE_PCI,
.local = KBC_TYPE_PS2_1 | KBC_VEN_ALI,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_intel_ami_pci_device = {
.name = "PS/2 Keyboard (AMI)",
.internal_name = "keyboard_ps2_intel_ami_pci",
.flags = DEVICE_KBC | DEVICE_PCI,
.local = KBC_TYPE_GREEN | KBC_VEN_AMI,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_tg_ami_pci_device = {
.name = "PS/2 Keyboard (TriGem AMI)",
.internal_name = "keyboard_ps2_tg_ami_pci",
.flags = DEVICE_KBC | DEVICE_PCI,
.local = KBC_TYPE_PS2_1 | KBC_VEN_TRIGEM_AMI,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_ps2_acer_pci_device = {
.name = "PS/2 Keyboard (Acer 90M002A)",
.internal_name = "keyboard_ps2_acer_pci",
.flags = DEVICE_KBC | DEVICE_PCI,
.local = KBC_TYPE_PS2_1 | KBC_VEN_ACER,
.init = kbc_at_init,
.close = kbc_at_close,
.reset = kbc_at_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/device/kbc_at.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 27,837 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of a port 80h POST diagnostic card.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/machine.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/postcard.h>
#include "cpu.h"
uint8_t postcard_codes[POSTCARDS_NUM];
static uint16_t postcard_port;
static uint8_t postcard_written[POSTCARDS_NUM];
static uint8_t postcard_ports_num = 1;
static uint8_t postcard_prev_codes[POSTCARDS_NUM];
#define UISTR_LEN 32
static char postcard_str[UISTR_LEN]; /* UI output string */
extern void ui_sb_bugui(char *__str);
#ifdef ENABLE_POSTCARD_LOG
int postcard_do_log = ENABLE_POSTCARD_LOG;
static void
postcard_log(const char *fmt, ...)
{
va_list ap;
if (postcard_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
int postcard_do_log = 0;
# define postcard_log(fmt, ...)
#endif
static void
postcard_setui(void)
{
if (postcard_ports_num > 1) {
char ps[2][POSTCARDS_NUM][3] = { { { 0 },
{ 0 },
} };
for (uint8_t i = 0; i < POSTCARDS_NUM; i++) {
if (!postcard_written[i]) {
snprintf(ps[0][i], sizeof(ps[0][i]), "--");
snprintf(ps[1][i], sizeof(ps[1][i]), "--");
} else if (postcard_written[i] == 1) {
snprintf(ps[0][i], sizeof(ps[0][i]), "%02X", postcard_codes[i]);
snprintf(ps[1][i], sizeof(ps[1][i]), "--");
} else {
snprintf(ps[0][i], sizeof(ps[0][i]), "%02X", postcard_codes[i]);
snprintf(ps[1][i], sizeof(ps[1][i]), "%02X", postcard_prev_codes[i]);
}
}
switch (postcard_ports_num) {
default:
case 2:
snprintf(postcard_str, sizeof(postcard_str), "POST: %s%s %s%s",
ps[0][0], ps[0][1], ps[1][0], ps[1][1]);
break;
case 3:
snprintf(postcard_str, sizeof(postcard_str), "POST: %s/%s%s %s/%s%s",
ps[0][0], ps[0][1], ps[0][2], ps[1][0], ps[1][1], ps[1][2]);
break;
case 4:
snprintf(postcard_str, sizeof(postcard_str), "POST: %s%s/%s%s %s%s/%s%s",
ps[0][0], ps[0][1], ps[0][2], ps[0][3],
ps[1][0], ps[1][1], ps[1][2], ps[1][3]);
break;
}
} else {
if (!postcard_written[0])
snprintf(postcard_str, sizeof(postcard_str), "POST: -- --");
else if (postcard_written[0] == 1)
snprintf(postcard_str, sizeof(postcard_str), "POST: %02X --", postcard_codes[0]);
else
snprintf(postcard_str, sizeof(postcard_str), "POST: %02X %02X", postcard_codes[0], postcard_prev_codes[0]);
}
ui_sb_bugui(postcard_str);
if (postcard_do_log) {
/* log same string sent to the UI */
postcard_log("[%04X:%08X] %s\n", CS, cpu_state.pc, postcard_str);
}
}
static void
postcard_reset(void)
{
memset(postcard_written, 0x00, POSTCARDS_NUM * sizeof(uint8_t));
memset(postcard_codes, 0x00, POSTCARDS_NUM * sizeof(uint8_t));
memset(postcard_prev_codes, 0x00, POSTCARDS_NUM * sizeof(uint8_t));
postcard_setui();
}
static void
postcard_write(uint16_t port, uint8_t val, UNUSED(void *priv))
{
if (postcard_written[port & POSTCARD_MASK] &&
(val == postcard_codes[port & POSTCARD_MASK]))
return;
postcard_prev_codes[port & POSTCARD_MASK] = postcard_codes[port & POSTCARD_MASK];
postcard_codes[port & POSTCARD_MASK] = val;
if (postcard_written[port & POSTCARD_MASK] < 2)
postcard_written[port & POSTCARD_MASK]++;
postcard_setui();
}
static void *
postcard_init(UNUSED(const device_t *info))
{
postcard_ports_num = 1;
if (machine_has_bus(machine, MACHINE_BUS_MCA))
postcard_port = 0x680; /* MCA machines */
else if (strstr(machines[machine].name, " PS/2 ") || strstr(machine_getname_ex(machine), " PS/1 "))
postcard_port = 0x190; /* ISA PS/2 machines */
else if (strstr(machines[machine].name, " IBM XT "))
postcard_port = 0x60; /* IBM XT */
else if (strstr(machines[machine].name, " IBM PCjr")) {
postcard_port = 0x10; /* IBM PCjr */
postcard_ports_num = 3; /* IBM PCjr error ports 11h and 12h */
} else if (strstr(machines[machine].name, " Compaq ") && !machine_has_bus(machine, MACHINE_BUS_PCI))
postcard_port = 0x84; /* ISA Compaq machines */
else if (strstr(machines[machine].name, "Olivetti"))
postcard_port = 0x378; /* Olivetti machines */
else
postcard_port = 0x80; /* AT and clone machines */
postcard_log("POST card initializing on port %04Xh\n", postcard_port);
postcard_reset();
if (postcard_port)
io_sethandler(postcard_port, postcard_ports_num,
NULL, NULL, NULL, postcard_write, NULL, NULL, NULL);
return postcard_write;
}
static void
postcard_close(UNUSED(void *priv))
{
if (postcard_port)
io_removehandler(postcard_port, postcard_ports_num,
NULL, NULL, NULL, postcard_write, NULL, NULL, NULL);
}
const device_t postcard_device = {
.name = "POST Card",
.internal_name = "postcard",
.flags = DEVICE_ISA,
.local = 0,
.init = postcard_init,
.close = postcard_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/device/postcard.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,694 |
```c
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* Implementation of a memory expansion board for the ISA Bus.
*
* Although modern systems use direct-connect local buses to
* connect the CPU with its memory, originally the main system
* bus(es) were used for that. Memory expension cards could add
* memory to the system through the ISA bus, using a variety of
* techniques.
*
* The majority of these boards could provide some (additional)
* conventional (low) memory, extended (high) memory on 80286
* and higher systems, as well as EMS bank-switched memory.
*
* This implementation uses the LIM 3.2 specifications for EMS.
*
* With the EMS method, the system's standard memory is expanded
* by means of bank-switching. One or more 'frames' in the upper
* memory area (640K-1024K) are used as viewports into an array
* of RAM pages numbered 0 to N. Each page is defined to be 16KB
* in size, so, for a 1024KB board, 64 such pages are available.
* I/O control registers are used to set up the mappings. More
* modern boards even have multiple 'copies' of those registers,
* which can be switched very fast, to allow for multitasking.
*
* TODO: The EV159 is supposed to support 16b EMS transfers, but the
* EMM.sys driver for it doesn't seem to want to do that..
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Jasmine Iwanek <jriwanek@gmail.com>
*
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/machine.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/ui.h>
#include <86box/plat.h>
#include <86box/isamem.h>
#include "cpu.h"
#define ISAMEM_IBMXT_CARD 0
#define ISAMEM_GENXT_CARD 1
#define ISAMEM_RAMCARD_CARD 2
#define ISAMEM_SYSTEMCARD_CARD 3
#define ISAMEM_IBMAT_128K_CARD 4
#define ISAMEM_IBMAT_CARD 5
#define ISAMEM_GENAT_CARD 6
#define ISAMEM_P5PAK_CARD 7
#define ISAMEM_A6PAK_CARD 8
#define ISAMEM_EMS5150_CARD 9
#define ISAMEM_EV159_CARD 10
#define ISAMEM_RAMPAGEXT_CARD 11
#define ISAMEM_ABOVEBOARD_CARD 12
#define ISAMEM_BRXT_CARD 13
#define ISAMEM_BRAT_CARD 14
#define ISAMEM_EV165A_CARD 15
#define ISAMEM_LOTECH_CARD 16
#define ISAMEM_DEBUG 0
#define RAM_TOPMEM (640 << 10) /* end of low memory */
#define RAM_UMAMEM (384 << 10) /* upper memory block */
#define RAM_EXTMEM (1024 << 10) /* start of high memory */
#define EMS_MAXSIZE (2048 << 10) /* max EMS memory size */
#define EMS_EV159_MAXSIZE (3072 << 10) /* max EMS memory size for EV-159 cards */
#define EMS_LOTECH_MAXSIZE (4096 << 10) /* max EMS memory size for lotech cards */
#define EMS_PGSIZE (16 << 10) /* one page is this big */
#define EMS_MAXPAGE 4 /* number of viewport pages */
#define EXTRAM_CONVENTIONAL 0
#define EXTRAM_HIGH 1
#define EXTRAM_XMS 2
typedef struct emsreg_t {
int8_t enabled; /* 1=ENABLED */
uint8_t page; /* page# in EMS RAM */
uint8_t frame; /* (varies with board) */
char pad;
uint8_t *addr; /* start addr in EMS RAM */
mem_mapping_t mapping; /* mapping entry for page */
uint8_t *ram;
uint8_t *frame_val;
uint16_t *ems_size;
uint16_t *ems_pages;
uint32_t *frame_addr;
} emsreg_t;
typedef struct ext_ram_t {
uint32_t base;
uint8_t *ptr;
} ext_ram_t;
typedef struct memdev_t {
const char *name;
uint8_t board : 6; /* board type */
uint8_t reserved : 2;
uint8_t flags;
#define FLAG_CONFIG 0x01 /* card is configured */
#define FLAG_WIDE 0x10 /* card uses 16b mode */
#define FLAG_FAST 0x20 /* fast (<= 120ns) chips */
#define FLAG_EMS 0x40 /* card has EMS mode enabled */
uint8_t frame_val[2];
uint16_t total_size; /* configured size in KB */
uint16_t base_addr[2]; /* configured I/O address */
uint32_t start_addr; /* configured memory start */
uint32_t frame_addr[2]; /* configured frame address */
uint16_t ems_size[2]; /* EMS size in KB */
uint16_t ems_pages[2]; /* EMS size in pages */
uint32_t ems_start[2]; /* start of EMS in RAM */
uint8_t *ram; /* allocated RAM buffer */
ext_ram_t ext_ram[3]; /* structures for the mappings */
mem_mapping_t low_mapping; /* mapping for low mem */
mem_mapping_t high_mapping; /* mapping for high mem */
emsreg_t ems[EMS_MAXPAGE * 2]; /* EMS controller registers */
} memdev_t;
#ifdef ENABLE_ISAMEM_LOG
int isamem_do_log = ENABLE_ISAMEM_LOG;
static void
isamem_log(const char *fmt, ...)
{
va_list ap;
if (isamem_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define isamem_log(fmt, ...)
#endif
/* Why this convoluted setup with the mem_dev stuff when it's much simpler
to just pass the exec pointer as p as well, and then just use that. */
/* Read one byte from onboard RAM. */
static uint8_t
ram_readb(uint32_t addr, void *priv)
{
ext_ram_t *dev = (ext_ram_t *) priv;
uint8_t ret = 0xff;
/* Grab the data. */
ret = *(uint8_t *) (dev->ptr + (addr - dev->base));
return ret;
}
/* Read one word from onboard RAM. */
static uint16_t
ram_readw(uint32_t addr, void *priv)
{
ext_ram_t *dev = (ext_ram_t *) priv;
uint16_t ret = 0xffff;
/* Grab the data. */
ret = *(uint16_t *) (dev->ptr + (addr - dev->base));
return ret;
}
/* Write one byte to onboard RAM. */
static void
ram_writeb(uint32_t addr, uint8_t val, void *priv)
{
ext_ram_t *dev = (ext_ram_t *) priv;
/* Write the data. */
*(uint8_t *) (dev->ptr + (addr - dev->base)) = val;
}
/* Write one word to onboard RAM. */
static void
ram_writew(uint32_t addr, uint16_t val, void *priv)
{
ext_ram_t *dev = (ext_ram_t *) priv;
/* Write the data. */
*(uint16_t *) (dev->ptr + (addr - dev->base)) = val;
}
/* Read one byte from onboard paged RAM. */
static uint8_t
ems_readb(uint32_t addr, void *priv)
{
emsreg_t *dev = (emsreg_t *) priv;
uint8_t ret = 0xff;
/* Grab the data. */
ret = *(uint8_t *) (dev->addr + (addr & 0x3fff));
#if ISAMEM_DEBUG
if ((addr % 4096) == 0)
isamem_log("EMS readb(%06x) = %02x\n", addr & 0x3fff, ret);
#endif
return ret;
}
/* Read one word from onboard paged RAM. */
static uint16_t
ems_readw(uint32_t addr, void *priv)
{
emsreg_t *dev = (emsreg_t *) priv;
uint16_t ret = 0xffff;
/* Grab the data. */
ret = *(uint16_t *) (dev->addr + (addr & 0x3fff));
#if ISAMEM_DEBUG
if ((addr % 4096) == 0)
isamem_log("EMS readw(%06x) = %04x\n", addr & 0x3fff, ret);
#endif
return ret;
}
/* Write one byte to onboard paged RAM. */
static void
ems_writeb(uint32_t addr, uint8_t val, void *priv)
{
emsreg_t *dev = (emsreg_t *) priv;
/* Write the data. */
#if ISAMEM_DEBUG
if ((addr % 4096) == 0)
isamem_log("EMS writeb(%06x, %02x)\n", addr & 0x3fff, val);
#endif
*(uint8_t *) (dev->addr + (addr & 0x3fff)) = val;
}
/* Write one word to onboard paged RAM. */
static void
ems_writew(uint32_t addr, uint16_t val, void *priv)
{
emsreg_t *dev = (emsreg_t *) priv;
/* Write the data. */
#if ISAMEM_DEBUG
if ((addr % 4096) == 0)
isamem_log("EMS writew(%06x, %04x)\n", addr & 0x3fff, val);
#endif
*(uint16_t *) (dev->addr + (addr & 0x3fff)) = val;
}
/* Handle a READ operation from one of our registers. */
static uint8_t
ems_in(uint16_t port, void *priv)
{
const emsreg_t *dev = (emsreg_t *) priv;
uint8_t ret = 0xff;
#ifdef ENABLE_ISAMEM_LOG
int vpage;
#endif
/* Get the viewport page number. */
#ifdef ENABLE_ISAMEM_LOG
vpage = (port / EMS_PGSIZE);
#endif
port &= (EMS_PGSIZE - 1);
switch (port & 0x0001) {
case 0x0000: /* page number register */
ret = dev->page;
if (dev->enabled)
ret |= 0x80;
break;
case 0x0001: /* W/O */
break;
default:
break;
}
isamem_log("ISAMEM: read(%04x) = %02x) page=%d\n", port, ret, vpage);
return ret;
}
/* Handle a READ operation from one of our registers. */
static uint8_t
consecutive_ems_in(uint16_t port, void *priv)
{
const memdev_t *dev = (memdev_t *) priv;
uint8_t ret = 0xff;
int vpage;
/* Get the viewport page number. */
vpage = (port - dev->base_addr[0]);
ret = dev->ems[vpage].page;
if (dev->ems[vpage].enabled)
ret |= 0x80;
isamem_log("ISAMEM: read(%04x) = %02x) page=%d\n", port, ret, vpage);
return ret;
}
/* Handle a WRITE operation to one of our registers. */
static void
ems_out(uint16_t port, uint8_t val, void *priv)
{
emsreg_t *dev = (emsreg_t *) priv;
int vpage;
/* Get the viewport page number. */
vpage = (port / EMS_PGSIZE);
port &= (EMS_PGSIZE - 1);
switch (port & 0x0001) {
case 0x0000: /* page mapping registers */
/* Set the page number. */
dev->enabled = (val & 0x80);
dev->page = (val & 0x7f);
if (dev->enabled && (dev->page < *dev->ems_pages)) {
/* Pre-calculate the page address in EMS RAM. */
dev->addr = dev->ram + ((val & 0x7f) * EMS_PGSIZE);
isamem_log("ISAMEM: map port %04X, page %i, starting at %08X: %08X -> %08X\n", port,
vpage, *dev->frame_addr,
*dev->frame_addr + (EMS_PGSIZE * (vpage & 3)), dev->addr - dev->ram);
mem_mapping_set_addr(&dev->mapping, *dev->frame_addr + (EMS_PGSIZE * vpage), EMS_PGSIZE);
/* Update the EMS RAM address for this page. */
mem_mapping_set_exec(&dev->mapping, dev->addr);
/* Enable this page. */
mem_mapping_enable(&dev->mapping);
} else {
isamem_log("ISAMEM: map port %04X, page %i, starting at %08X: %08X -> N/A\n",
port, vpage, *dev->frame_addr, *dev->frame_addr + (EMS_PGSIZE * vpage));
/* Disable this page. */
mem_mapping_disable(&dev->mapping);
}
break;
case 0x0001: /* page frame registers */
/*
* The EV-159 EMM driver configures the frame address
* by setting bits in these registers. The information
* in their manual is unclear, but here is what was
* found out by repeatedly changing EMM's config:
*
* 08 04 00 Address
* -----------------
* 00 00 00 C4000
* 00 00 80 C8000
* 00 80 00 CC000
* 00 80 80 D0000
* 80 00 00 D4000
* 80 00 80 D8000
* 80 80 00 DC000
* 80 80 80 E0000
*/
dev->frame = val;
*dev->frame_val = (*dev->frame_val & ~(1 << vpage)) | ((val >> 7) << vpage);
*dev->frame_addr = 0x000c4000 + (*dev->frame_val << 14);
isamem_log("ISAMEM: map port %04X page %i: frame_addr = %08X\n", port, vpage, *dev->frame_addr);
/* Destroy the page registers. */
for (uint8_t i = 0; i < 4; i ++) {
isamem_log(" ");
outb((port & 0x3ffe) + (i << 14), 0x00);
}
break;
default:
break;
}
}
/* Handle a WRITE operation to one of our registers. */
static void
consecutive_ems_out(uint16_t port, uint8_t val, void *priv)
{
memdev_t *dev = (memdev_t *) priv;
int vpage;
/* Get the viewport page number. */
vpage = (port - dev->base_addr[0]);
isamem_log("ISAMEM: write(%04x, %02x) to page mapping registers! (page=%d)\n", port, val, vpage);
/* Set the page number. */
dev->ems[vpage].enabled = 1;
dev->ems[vpage].page = val;
/* Make sure we can do that.. */
if (dev->flags & FLAG_CONFIG) {
if (dev->ems[vpage].page < dev->ems_pages[0]) {
/* Pre-calculate the page address in EMS RAM. */
dev->ems[vpage].addr = dev->ram + dev->ems_start[0] + (val * EMS_PGSIZE);
} else {
/* That page does not exist. */
dev->ems[vpage].enabled = 0;
}
if (dev->ems[vpage].enabled) {
/* Update the EMS RAM address for this page. */
mem_mapping_set_exec(&dev->ems[vpage].mapping,
dev->ems[vpage].addr);
/* Enable this page. */
mem_mapping_enable(&dev->ems[vpage].mapping);
} else {
/* Disable this page. */
mem_mapping_disable(&dev->ems[vpage].mapping);
}
}
}
/* Initialize the device for use. */
static void *
isamem_init(const device_t *info)
{
memdev_t *dev;
uint32_t k;
uint32_t t;
uint32_t addr;
uint32_t tot;
/* EMS 3.2 cannot have more than 2048KB per board. */
uint32_t ems_max = EMS_MAXSIZE;
uint8_t *ptr;
/* Find our device and create an instance. */
dev = (memdev_t *) malloc(sizeof(memdev_t));
memset(dev, 0x00, sizeof(memdev_t));
dev->name = info->name;
dev->board = info->local;
dev->base_addr[1] = 0x0000;
dev->frame_addr[1] = 0x00000000;
/* Do per-board initialization. */
tot = 0;
switch (dev->board) {
case ISAMEM_IBMXT_CARD: /* IBM PC/XT Memory Expansion Card */
case ISAMEM_GENXT_CARD: /* Generic PC/XT Memory Expansion Card */
case ISAMEM_RAMCARD_CARD: /* Microsoft RAMCard for IBM PC */
case ISAMEM_SYSTEMCARD_CARD: /* Microsoft SystemCard */
case ISAMEM_P5PAK_CARD: /* Paradise Systems 5-PAK */
case ISAMEM_A6PAK_CARD: /* AST SixPakPlus */
dev->total_size = device_get_config_int("size");
dev->start_addr = device_get_config_int("start");
tot = dev->total_size;
break;
case ISAMEM_IBMAT_128K_CARD: /* IBM PC/AT 128K Memory Expansion Option */
dev->total_size = 128;
dev->start_addr = 512;
tot = dev->total_size;
dev->flags |= FLAG_WIDE;
break;
case ISAMEM_IBMAT_CARD: /* IBM PC/AT Memory Expansion Card */
case ISAMEM_GENAT_CARD: /* Generic PC/AT Memory Expansion Card */
dev->total_size = device_get_config_int("size");
dev->start_addr = device_get_config_int("start");
tot = dev->total_size;
dev->flags |= FLAG_WIDE;
break;
case ISAMEM_EMS5150_CARD: /* Micro Mainframe EMS-5150(T) */
dev->base_addr[0] = device_get_config_hex16("base");
dev->total_size = device_get_config_int("size");
dev->start_addr = 0;
dev->frame_addr[0] = 0xd0000;
dev->flags |= (FLAG_EMS | FLAG_CONFIG);
break;
case ISAMEM_EV159_CARD: /* Everex EV-159 RAM 3000 */
/* The EV-159 cannot have more than 3072KB per board. */
ems_max = EMS_EV159_MAXSIZE;
dev->base_addr[0] = device_get_config_hex16("base");
dev->base_addr[1] = device_get_config_hex16("base2");
dev->total_size = device_get_config_int("size");
dev->start_addr = device_get_config_int("start");
tot = device_get_config_int("length");
if (!!device_get_config_int("width"))
dev->flags |= FLAG_WIDE;
if (!!device_get_config_int("speed"))
dev->flags |= FLAG_FAST;
if (!!device_get_config_int("ems"))
dev->flags |= FLAG_EMS;
dev->frame_addr[0] = 0xd0000;
dev->frame_addr[1] = 0xe0000;
break;
case ISAMEM_EV165A_CARD: /* Everex Maxi Magic EV-165A */
dev->base_addr[0] = device_get_config_hex16("base");
dev->total_size = device_get_config_int("size");
dev->start_addr = device_get_config_int("start");
tot = device_get_config_int("length");
if (!!device_get_config_int("ems"))
dev->flags |= FLAG_EMS;
dev->frame_addr[0] = 0xe0000;
break;
case ISAMEM_RAMPAGEXT_CARD: /* AST RAMpage/XT */
dev->base_addr[0] = device_get_config_hex16("base");
dev->total_size = device_get_config_int("size");
dev->start_addr = device_get_config_int("start");
tot = dev->total_size;
dev->flags |= FLAG_EMS;
dev->frame_addr[0] = 0xe0000;
break;
case ISAMEM_ABOVEBOARD_CARD: /* Intel AboveBoard */
case ISAMEM_BRAT_CARD: /* BocaRAM/AT */
dev->base_addr[0] = device_get_config_hex16("base");
dev->total_size = device_get_config_int("size");
if (!!device_get_config_int("start"))
dev->start_addr = device_get_config_int("start");
dev->frame_addr[0] = device_get_config_hex20("frame");
dev->flags |= FLAG_EMS;
if (!!device_get_config_int("width"))
dev->flags |= FLAG_WIDE;
if (!!device_get_config_int("speed"))
dev->flags |= FLAG_FAST;
break;
case ISAMEM_LOTECH_CARD: /* Lotech EMS */
/* The Lotech EMS cannot have more than 4096KB per board. */
ems_max = EMS_LOTECH_MAXSIZE;
fallthrough;
case ISAMEM_BRXT_CARD: /* BocaRAM/XT */
dev->base_addr[0] = device_get_config_hex16("base");
dev->total_size = device_get_config_int("size");
dev->start_addr = 0;
dev->frame_addr[0] = device_get_config_hex20("frame");
dev->flags |= (FLAG_EMS | FLAG_CONFIG);
break;
default:
break;
}
/* Fix up the memory start address. */
dev->start_addr <<= 10;
/* Say hello! */
isamem_log("ISAMEM: %s (%iKB", info->name, dev->total_size);
if (tot && (dev->total_size != tot))
isamem_log(", %iKB for RAM", tot);
if (dev->flags & FLAG_FAST)
isamem_log(", FAST");
if (dev->flags & FLAG_WIDE)
isamem_log(", 16BIT");
isamem_log(")\n");
/* Force (back to) 8-bit bus if needed. */
if ((!is286) && (dev->flags & FLAG_WIDE)) {
isamem_log("ISAMEM: not AT+ system, forcing 8-bit mode!\n");
dev->flags &= ~FLAG_WIDE;
}
/* Allocate and initialize our RAM. */
k = dev->total_size << 10;
dev->ram = (uint8_t *) malloc(k);
memset(dev->ram, 0x00, k);
ptr = dev->ram;
/*
* The 'Memory Start Address' switch indicates at which address
* we should start adding memory. No memory is added if it is
* set to 0.
*/
tot <<= 10;
addr = dev->start_addr;
if (addr > 0 && tot > 0) {
/* Adjust K for the RAM we will use. */
k -= tot;
/*
* First, see if we have to expand the conventional
* (low) memory area. This can extend up to 640KB,
* so check this first.
*/
t = (addr < RAM_TOPMEM) ? RAM_TOPMEM - addr : 0;
if (t > 0) {
/*
* We need T bytes to extend that area.
*
* If the board doesn't have that much, grab
* as much as we can.
*/
if (t > tot)
t = tot;
isamem_log("ISAMEM: RAM at %05iKB (%iKB)\n", addr >> 10, t >> 10);
dev->ext_ram[EXTRAM_CONVENTIONAL].ptr = ptr;
dev->ext_ram[EXTRAM_CONVENTIONAL].base = addr;
/* Create, initialize and enable the low-memory mapping. */
mem_mapping_add(&dev->low_mapping, addr, t,
ram_readb,
(dev->flags & FLAG_WIDE) ? ram_readw : NULL,
NULL,
ram_writeb,
(dev->flags & FLAG_WIDE) ? ram_writew : NULL,
NULL,
ptr, MEM_MAPPING_EXTERNAL, &dev->ext_ram[EXTRAM_CONVENTIONAL]);
/* Tell the memory system this is external RAM. */
mem_set_mem_state(addr, t,
MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
/* Update pointers. */
ptr += t;
tot -= t;
addr += t;
}
/* Skip to high memory if needed. */
if ((addr == RAM_TOPMEM) && (tot >= RAM_UMAMEM)) {
/*
* We have more RAM available, but we are at the
* top of conventional RAM. So, the next 384K are
* skipped, and placed into different mappings so
* they can be re-mapped later.
*/
t = RAM_UMAMEM; /* 384KB */
isamem_log("ISAMEM: RAM at %05iKB (%iKB)\n", addr >> 10, t >> 10);
dev->ext_ram[EXTRAM_HIGH].ptr = ptr;
dev->ext_ram[EXTRAM_HIGH].base = addr + tot;
/* Update and enable the remap. */
mem_mapping_set(&ram_remapped_mapping,
addr + tot, t,
ram_readb, ram_readw, NULL,
ram_writeb, ram_writew, NULL,
ptr, MEM_MAPPING_EXTERNAL,
&dev->ext_ram[EXTRAM_HIGH]);
mem_mapping_disable(&ram_remapped_mapping);
/* Tell the memory system this is external RAM. */
mem_set_mem_state(addr + tot, t,
MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
/* Update pointers. */
ptr += t;
tot -= t;
addr += t;
}
}
/*
* Next, on systems that support it (80286 and up), we can add
* (some of) our RAM to the system as Extended Memory, that is,
* memory located above 1MB. This memory cannot be addressed in
* real mode (so, not by DOS, for example) but it can be used in
* protected mode.
*/
if (is286 && addr > 0 && tot > 0) {
t = tot;
isamem_log("ISAMEM: RAM at %05iKB (%iKB)\n", addr >> 10, t >> 10);
dev->ext_ram[EXTRAM_XMS].ptr = ptr;
dev->ext_ram[EXTRAM_XMS].base = addr;
/* Create, initialize and enable the high-memory mapping. */
mem_mapping_add(&dev->high_mapping, addr, t,
ram_readb, ram_readw, NULL,
ram_writeb, ram_writew, NULL,
ptr, MEM_MAPPING_EXTERNAL, &dev->ext_ram[EXTRAM_XMS]);
/* Tell the memory system this is external RAM. */
mem_set_mem_state(addr, t, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
/* Update pointers. */
ptr += t;
tot -= t;
addr += t;
}
isa_mem_size += dev->total_size - (k >> 10);
/* If EMS is enabled, use the remainder for EMS. */
if (dev->flags & FLAG_EMS) {
t = k;
if (t > ems_max)
t = ems_max;
/* Set up where EMS begins in local RAM, and how much we have. */
dev->ems_start[0] = ptr - dev->ram;
if ((dev->board == ISAMEM_EV159_CARD) && (t > (2 << 20))) {
dev->ems_size[0] = 2 << 10;
dev->ems_pages[0] = (2 << 20) / EMS_PGSIZE;
} else {
dev->ems_size[0] = t >> 10;
dev->ems_pages[0] = t / EMS_PGSIZE;
}
isamem_log("ISAMEM: EMS #1 enabled, I/O=%04XH, %iKB (%i pages)",
dev->base_addr[0], dev->ems_size[0], dev->ems_pages[0]);
if (dev->frame_addr[0] > 0)
isamem_log(", Frame[0]=%05XH", dev->frame_addr[0]);
isamem_log("\n");
if ((dev->board == ISAMEM_EV159_CARD) && (t > (2 << 20))) {
dev->ems_start[1] = dev->ems_start[0] + (2 << 20);
dev->ems_size[1] = (t - (2 << 20)) >> 10;
dev->ems_pages[1] = (t - (2 << 20)) / EMS_PGSIZE;
isamem_log("ISAMEM: EMS #2 enabled, I/O=%04XH, %iKB (%i pages)",
dev->base_addr[1], dev->ems_size[1], dev->ems_pages[1]);
if (dev->frame_addr[1] > 0)
isamem_log(", Frame[1]=%05XH", dev->frame_addr[1]);
isamem_log("\n");
}
/*
* For each supported page (we can have a maximum of 4),
* create, initialize and disable the mappings, and set
* up the I/O control handler.
*/
for (uint8_t i = 0; i < EMS_MAXPAGE; i++) {
dev->ems[i].ram = dev->ram + dev->ems_start[0];
dev->ems[i].frame_val = &dev->frame_val[0];
dev->ems[i].ems_size = &dev->ems_size[0];
dev->ems[i].ems_pages = &dev->ems_pages[0];
dev->ems[i].frame_addr = &dev->frame_addr[0];
/* Create and initialize a page mapping. */
mem_mapping_add(&dev->ems[i].mapping,
dev->frame_addr[0] + (EMS_PGSIZE * i), EMS_PGSIZE,
ems_readb,
(dev->flags & FLAG_WIDE) ? ems_readw : NULL,
NULL,
ems_writeb,
(dev->flags & FLAG_WIDE) ? ems_writew : NULL,
NULL,
ptr, MEM_MAPPING_EXTERNAL,
&(dev->ems[i]));
/* For now, disable it. */
mem_mapping_disable(&dev->ems[i].mapping);
/* Set up an I/O port handler. */
if (dev->board != ISAMEM_LOTECH_CARD)
io_sethandler(dev->base_addr[0] + (EMS_PGSIZE * i), 2,
ems_in, NULL, NULL, ems_out, NULL, NULL, &(dev->ems[i]));
if ((dev->board == ISAMEM_EV159_CARD) && (t > (2 << 20))) {
dev->ems[i | 4].ram = dev->ram + dev->ems_start[1];
dev->ems[i | 4].frame_val = &dev->frame_val[1];
dev->ems[i | 4].ems_size = &dev->ems_size[1];
dev->ems[i | 4].ems_pages = &dev->ems_pages[1];
dev->ems[i | 4].frame_addr = &dev->frame_addr[1];
/* Create and initialize a page mapping. */
mem_mapping_add(&dev->ems[i | 4].mapping,
dev->frame_addr[1] + (EMS_PGSIZE * i), EMS_PGSIZE,
ems_readb,
(dev->flags & FLAG_WIDE) ? ems_readw : NULL,
NULL,
ems_writeb,
(dev->flags & FLAG_WIDE) ? ems_writew : NULL,
NULL,
ptr + (2 << 20), MEM_MAPPING_EXTERNAL,
&(dev->ems[i | 4]));
/* For now, disable it. */
mem_mapping_disable(&dev->ems[i | 4].mapping);
io_sethandler(dev->base_addr[1] + (EMS_PGSIZE * i), 2,
ems_in, NULL, NULL, ems_out, NULL, NULL, &(dev->ems[i | 4]));
}
}
if (dev->board == ISAMEM_LOTECH_CARD)
io_sethandler(dev->base_addr[0], 4,
consecutive_ems_in, NULL, NULL, consecutive_ems_out, NULL, NULL, dev);
}
/* Let them know our device instance. */
return ((void *) dev);
}
/* Remove the device from the system. */
static void
isamem_close(void *priv)
{
memdev_t *dev = (memdev_t *) priv;
if (dev->ram != NULL)
free(dev->ram);
free(dev);
}
static const device_config_t ibmxt_32k_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 32,
.file_filter = "",
.spinner = {
.min = 32,
.max = 576,
.step = 32
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 64,
.file_filter = "",
.spinner = {
.min = 0,
.max = 608,
.step = 32
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t ibmxt_32k_device = {
.name = "IBM PC/XT 32K Memory Expansion Option",
.internal_name = "ibmxt_32k",
.flags = DEVICE_ISA,
.local = ISAMEM_IBMXT_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ibmxt_32k_config
};
static const device_config_t ibmxt_64k_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 64,
.file_filter = "",
.spinner = {
.min = 64,
.max = 576,
.step = 64
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 64,
.file_filter = "",
.spinner = {
.min = 0,
.max = 576,
.step = 64
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t ibmxt_64k_device = {
.name = "IBM PC/XT 64K Memory Expansion Option",
.internal_name = "ibmxt_64k",
.flags = DEVICE_ISA,
.local = ISAMEM_IBMXT_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ibmxt_64k_config
};
static const device_config_t ibmxt_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 128,
.file_filter = "",
.spinner = {
.min = 64,
.max = 576,
.step = 64
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 256,
.file_filter = "",
.spinner = {
.min = 0,
.max = 576,
.step = 64
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t ibmxt_device = {
.name = "IBM PC/XT 64/256K Memory Expansion Option",
.internal_name = "ibmxt",
.flags = DEVICE_ISA,
.local = ISAMEM_IBMXT_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ibmxt_config
};
static const device_config_t genericxt_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 16,
.file_filter = "",
.spinner = {
.min = 0,
.max = 640,
.step = 16
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = {
.min = 0,
.max = 624,
.step = 16
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t genericxt_device = {
.name = "Generic PC/XT Memory Expansion",
.internal_name = "genericxt",
.flags = DEVICE_ISA,
.local = ISAMEM_GENXT_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = genericxt_config
};
static const device_config_t msramcard_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 64,
.file_filter = "",
.spinner = {
.min = 0,
.max = 256,
.step = 64
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = {
.min = 0,
.max = 624,
.step = 64
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t msramcard_device = {
.name = "Microsoft RAMCard for IBM PC",
.internal_name = "msramcard",
.flags = DEVICE_ISA,
.local = ISAMEM_RAMCARD_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = msramcard_config
};
static const device_config_t mssystemcard_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 64,
.file_filter = "",
.spinner = {
.min = 0,
.max = 256,
.step = 64
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = {
.min = 0,
.max = 624,
.step = 64
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t mssystemcard_device = {
.name = "Microsoft SystemCard",
.internal_name = "mssystemcard",
.flags = DEVICE_ISA,
.local = ISAMEM_SYSTEMCARD_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = mssystemcard_config
};
static const device_t ibmat_128k_device = {
.name = "IBM PC/AT 128KB Memory Expansion Option",
.internal_name = "ibmat_128k",
.flags = DEVICE_ISA,
.local = ISAMEM_IBMAT_128K_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
static const device_config_t ibmat_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 512,
.file_filter = "",
.spinner = {
.min = 0,
.max = 12288,
.step = 512
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 1024,
.file_filter = "",
.spinner = {
.min = 0,
.max = 15872,
.step = 512
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t ibmat_device = {
.name = "IBM PC/AT Memory Expansion",
.internal_name = "ibmat",
.flags = DEVICE_ISA,
.local = ISAMEM_IBMAT_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ibmat_config
};
static const device_config_t genericat_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 512,
.file_filter = "",
.spinner = {
.min = 0,
.max = 16384,
.step = 128
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 1024,
.file_filter = "",
.spinner = {
.min = 0,
.max = 15872,
.step = 128
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t genericat_device = {
.name = "Generic PC/AT Memory Expansion",
.internal_name = "genericat",
.flags = DEVICE_ISA,
.local = ISAMEM_GENAT_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = genericat_config
};
static const device_config_t p5pak_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 128,
.file_filter = "",
.spinner = {
.min = 0,
.max = 384,
.step = 64
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 512,
.file_filter = "",
.spinner = {
.min = 64,
.max = 576,
.step = 64
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t p5pak_device = {
.name = "Paradise Systems 5-PAK",
.internal_name = "p5pak",
.flags = DEVICE_ISA,
.local = ISAMEM_P5PAK_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = p5pak_config
};
static const device_config_t a6pak_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 64,
.file_filter = "",
.spinner = {
.min = 0,
.max = 576,
.step = 64
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 256,
.file_filter = "",
.spinner = {
.min = 64,
.max = 512,
.step = 64
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t a6pak_device = {
.name = "AST SixPakPlus",
.internal_name = "a6pak",
.flags = DEVICE_ISA,
.local = ISAMEM_A6PAK_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = a6pak_config
};
static const device_config_t ems5150_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 256,
.file_filter = "",
.spinner = {
.min = 0,
.max = 2048,
.step = 64
},
.selection = { { 0 } }
},
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0x0000 },
{ .description = "Board 1", .value = 0x0208 },
{ .description = "Board 2", .value = 0x020a },
{ .description = "Board 3", .value = 0x020c },
{ .description = "Board 4", .value = 0x020e },
{ .description = "" }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t ems5150_device = {
.name = "Micro Mainframe EMS-5150(T)",
.internal_name = "ems5150",
.flags = DEVICE_ISA,
.local = ISAMEM_EMS5150_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ems5150_config
};
static const device_config_t ev159_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 512,
.file_filter = "",
.spinner = {
.min = 0,
.max = 3072,
.step = 512
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = {
.min = 0,
.max = 16128,
.step = 128
},
.selection = { { 0 } }
},
{
.name = "length",
.description = "Contiguous Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = {
.min = 0,
.max = 16384,
.step = 128
},
.selection = { { 0 } }
},
{
.name = "width",
.description = "I/O Width",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "8-bit", .value = 0 },
{ .description = "16-bit", .value = 1 },
{ .description = "" }
},
},
{
.name = "speed",
.description = "Transfer Speed",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Standard (150ns)", .value = 0 },
{ .description = "High-Speed (120ns)", .value = 1 },
{ .description = "" }
}
},
{
.name = "ems",
.description = "EMS mode",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0 },
{ .description = "Enabled", .value = 1 },
{ .description = "" }
},
},
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0258,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "208H", .value = 0x0208 },
{ .description = "218H", .value = 0x0218 },
{ .description = "258H", .value = 0x0258 },
{ .description = "268H", .value = 0x0268 },
{ .description = "2A8H", .value = 0x02A8 },
{ .description = "2B8H", .value = 0x02B8 },
{ .description = "2E8H", .value = 0x02E8 },
{ .description = "" }
},
},
{
.name = "base2",
.description = "Address for > 2 MB",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0268,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "208H", .value = 0x0208 },
{ .description = "218H", .value = 0x0218 },
{ .description = "258H", .value = 0x0258 },
{ .description = "268H", .value = 0x0268 },
{ .description = "2A8H", .value = 0x02A8 },
{ .description = "2B8H", .value = 0x02B8 },
{ .description = "2E8H", .value = 0x02E8 },
{ .description = "" }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t ev159_device = {
.name = "Everex EV-159 RAM 3000 Deluxe",
.internal_name = "ev159",
.flags = DEVICE_ISA,
.local = ISAMEM_EV159_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ev159_config
};
static const device_config_t ev165a_config[] = {
// clang-format off
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 512,
.file_filter = "",
.spinner = {
.min = 0,
.max = 2048,
.step = 512
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = {
.min = 0,
.max = 896,
.step = 128
},
.selection = { { 0 } }
},
{
.name = "length",
.description = "Contiguous Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = {
.min = 0,
.max = 16384,
.step = 128
},
.selection = { { 0 } }
},
{
.name = "ems",
.description = "EMS mode",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0 },
{ .description = "Enabled", .value = 1 },
{ .description = "" }
},
},
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0258,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "208H", .value = 0x0208 },
{ .description = "218H", .value = 0x0218 },
{ .description = "258H", .value = 0x0258 },
{ .description = "268H", .value = 0x0268 },
{ .description = "2A8H", .value = 0x02A8 },
{ .description = "2B8H", .value = 0x02B8 },
{ .description = "2E8H", .value = 0x02E8 },
{ .description = "" }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t ev165a_device = {
.name = "Everex Magi Magic EV-165A",
.internal_name = "ev165a",
.flags = DEVICE_ISA,
.local = ISAMEM_EV165A_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ev165a_config
};
static const device_config_t brxt_config[] = {
// clang-format off
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0268,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "208H", .value = 0x0208 },
{ .description = "218H", .value = 0x0218 },
{ .description = "258H", .value = 0x0258 },
{ .description = "268H", .value = 0x0268 },
{ .description = "" }
},
},
{
.name = "frame",
.description = "Frame Address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xD0000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "D000H", .value = 0xD0000 },
{ .description = "E000H", .value = 0xE0000 },
{ .description = "" }
},
},
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 512,
.file_filter = "",
.spinner = {
.min = 0,
.max = 2048,
.step = 512
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t brxt_device = {
.name = "BocaRAM/XT",
.internal_name = "brxt",
.flags = DEVICE_ISA,
.local = ISAMEM_BRXT_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = brxt_config
};
#ifdef USE_ISAMEM_BRAT
static const device_config_t brat_config[] = {
// clang-format off
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0268,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "208H", .value = 0x0208 },
{ .description = "218H", .value = 0x0218 },
{ .description = "258H", .value = 0x0258 },
{ .description = "268H", .value = 0x0268 },
{ .description = "" }
},
},
{
.name = "frame",
.description = "Frame Address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xD0000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "D000H", .value = 0xD0000 },
{ .description = "E000H", .value = 0xE0000 },
{ .description = "" }
},
},
{
.name = "width",
.description = "I/O Width",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 8,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "8-bit", .value = 8 },
{ .description = "16-bit", .value = 16 },
{ .description = "" }
},
},
{
.name = "speed",
.description = "Transfer Speed",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Standard", .value = 0 },
{ .description = "High-Speed", .value = 1 },
{ .description = "" }
}
},
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 512,
.file_filter = "",
.spinner = {
.min = 0,
.max = 4096,
.step = 512
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = {
.min = 0,
.max = 14336,
.step = 512
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t brat_device = {
.name = "BocaRAM/AT",
.internal_name = "brat",
.flags = DEVICE_ISA,
.local = ISAMEM_BRAT_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = brat_config
};
#endif /* USE_ISAMEM_BRAT */
static const device_config_t lotech_config[] = {
// clang-format off
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0260,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "260H", .value = 0x0260 },
{ .description = "264H", .value = 0x0264 },
{ .description = "268H", .value = 0x0268 },
{ .description = "26CH", .value = 0x026C },
{ .description = "" }
},
},
{
.name = "frame",
.description = "Frame Address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xe0000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "C000H", .value = 0xC0000 },
{ .description = "D000H", .value = 0xD0000 },
{ .description = "E000H", .value = 0xE0000 },
{ .description = "" }
},
},
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 2048,
.file_filter = "",
.spinner = {
.min = 512,
.max = 4096,
.step = 512
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t lotech_device = {
.name = "Lo-tech EMS Board",
.internal_name = "lotechems",
.flags = DEVICE_ISA,
.local = ISAMEM_LOTECH_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = lotech_config
};
#ifdef USE_ISAMEM_RAMPAGE
// TODO: Dual Paging support
// TODO: Conventional memory suppport
static const device_config_t rampage_config[] = {
// clang-format off
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0218,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "208H", .value = 0x0208 },
{ .description = "218H", .value = 0x0218 },
{ .description = "258H", .value = 0x0258 },
{ .description = "268H", .value = 0x0268 },
{ .description = "2A8H", .value = 0x02A8 },
{ .description = "2B8H", .value = 0x02B8 },
{ .description = "2E8H", .value = 0x02E8 },
{ .description = "" }
},
},
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 256, /* Technically 128k, but banks 2-7 must be 256, headaches elsewise */
.file_filter = "",
.spinner = {
.min = 256,
.max = 2048,
.step = 256
},
.selection = { { 0 } }
},
{
.name = "start",
.description = "Start Address",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 640,
.file_filter = "",
.spinner = {
.min = 0,
.max = 640,
.step = 64
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t rampage_device = {
.name = "AST RAMpage/XT",
.internal_name = "rampage",
.flags = DEVICE_ISA,
.local = ISAMEM_RAMPAGEXT_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = rampage_config
};
#endif /* USE_ISAMEM_RAMPAGE */
#ifdef USE_ISAMEM_IAB
static const device_config_t iab_config[] = {
// clang-format off
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0258,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "208H", .value = 0x0208 },
{ .description = "218H", .value = 0x0218 },
{ .description = "258H", .value = 0x0258 },
{ .description = "268H", .value = 0x0268 },
{ .description = "2A8H", .value = 0x02A8 },
{ .description = "2B8H", .value = 0x02B8 },
{ .description = "2E8H", .value = 0x02E8 },
{ .description = "" }
},
},
{
.name = "frame",
.description = "Frame Address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0x00000 },
{ .description = "C000H", .value = 0xC0000 },
{ .description = "D000H", .value = 0xD0000 },
{ .description = "E000H", .value = 0xE0000 },
{ .description = "" }
},
},
{
.name = "width",
.description = "I/O Width",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 8,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "8-bit", .value = 8 },
{ .description = "16-bit", .value = 16 },
{ .description = "" }
},
},
{
.name = "speed",
.description = "Transfer Speed",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Standard", .value = 0 },
{ .description = "High-Speed", .value = 1 },
{ .description = "" }
}
},
{
.name = "size",
.description = "Memory Size",
.type = CONFIG_SPINNER,
.default_string = "",
.default_int = 128,
.file_filter = "",
.spinner = {
.min = 0,
.max = 8192,
.step = 128
},
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_t iab_device = {
.name = "Intel AboveBoard",
.internal_name = "iab",
.flags = DEVICE_ISA,
.local = ISAMEM_ABOVEBOARD_CARD,
.init = isamem_init,
.close = isamem_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = iab_config
};
#endif /* USE_ISAMEM_IAB */
static const struct {
const device_t *dev;
} boards[] = {
// clang-format off
{ &device_none },
// XT Ram Expansion Cards
{ &ibmxt_32k_device },
{ &ibmxt_64k_device },
{ &ibmxt_device },
{ &genericxt_device },
{ &msramcard_device },
{ &mssystemcard_device },
// AT RAM Expansion Cards
{ &ibmat_128k_device },
{ &ibmat_device },
{ &genericat_device },
// EMS Cards
{ &p5pak_device },
{ &a6pak_device },
{ &ems5150_device },
{ &ev159_device },
{ &ev165a_device },
{ &brxt_device },
#ifdef USE_ISAMEM_BRAT
{ &brat_device },
#endif /* USE_ISAMEM_BRAT */
#ifdef USE_ISAMEM_RAMPAGE
{ &rampage_device },
#endif /* USE_ISAMEM_RAMPAGE */
#ifdef USE_ISAMEM_IAB
{ &iab_device },
#endif /* USE_ISAMEM_IAB */
{ &lotech_device },
{ NULL }
// clang-format on
};
void
isamem_reset(void)
{
int k;
/* We explicitly set to zero here or bad things happen */
isa_mem_size = 0;
for (uint8_t i = 0; i < ISAMEM_MAX; i++) {
k = isamem_type[i];
if (k == 0)
continue;
/* Add the instance to the system. */
device_add_inst(boards[k].dev, i + 1);
}
}
const char *
isamem_get_name(int board)
{
if (boards[board].dev == NULL)
return (NULL);
return (boards[board].dev->name);
}
const char *
isamem_get_internal_name(int board)
{
return device_get_internal_name(boards[board].dev);
}
int
isamem_get_from_internal_name(const char *s)
{
int c = 0;
while (boards[c].dev != NULL) {
if (!strcmp(boards[c].dev->internal_name, s))
return c;
c++;
}
/* Not found. */
return 0;
}
const device_t *
isamem_get_device(int board)
{
/* Add the instance to the system. */
return boards[board].dev;
}
int
isamem_has_config(int board)
{
if (boards[board].dev == NULL)
return 0;
return (boards[board].dev->config ? 1 : 0);
}
``` | /content/code_sandbox/src/device/isamem.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 17,642 |
```c
/*****************************************************************************
* pce *
*****************************************************************************/
/*****************************************************************************
* File name: src/arch/ibmpc/cassette.c *
* Created: 2008-11-25 by Hampa Hug <hampa@hampa.ch> *
*****************************************************************************/
/*****************************************************************************
* This program is free software. You can redistribute it and / or modify it *
* by the Free Software Foundation. *
* *
* This program is distributed in the hope that it will be useful, but *
* WITHOUT ANY WARRANTY, without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General *
*****************************************************************************/
#include <stdarg.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/cassette.h>
// #include <lib/console.h>
#define CAS_CLK 1193182
pc_cassette_t *cassette;
char cassette_fname[512];
char cassette_mode[512];
unsigned long cassette_pos;
unsigned long cassette_srate;
int cassette_enable;
int cassette_append;
int cassette_pcm;
int cassette_ui_writeprot;
static int cassette_cycles = -1;
static void pc_cas_reset(pc_cassette_t *cas);
#ifdef ENABLE_CASSETTE_LOG
int cassette_do_log = ENABLE_CASSETTE_LOG;
static void
cassette_log(const char *fmt, ...)
{
va_list ap;
if (cassette_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define cassette_log(fmt, ...)
#endif
void
pc_cas_init(pc_cassette_t *cas)
{
cas->save = 0;
cas->pcm = 0;
cas->motor = 0;
ui_sb_update_icon(SB_CASSETTE, 0);
cas->position = 0;
cas->position_save = 0;
cas->position_load = 0;
cas->data_out = 0;
cas->data_inp = 0;
cas->pcm_out_vol = 64;
cas->pcm_out_val = 0;
cas->cas_out_cnt = 0;
cas->cas_out_buf = 0;
cas->cas_inp_cnt = 0;
cas->cas_inp_buf = 0;
cas->cas_inp_bit = 0;
cas->clk = 0;
cas->clk_pcm = 0;
cas->clk_out = 0;
cas->clk_inp = 0;
cas->srate = 44100;
cas->close = 0;
cas->fname = NULL;
cas->fp = NULL;
pc_cas_reset(cas);
}
void
pc_cas_free(pc_cassette_t *cas)
{
free(cas->fname);
if (cas->close) {
fclose(cas->fp);
}
}
pc_cassette_t *
pc_cas_new(void)
{
pc_cassette_t *cas;
cas = malloc(sizeof(pc_cassette_t));
if (cas == NULL) {
return (NULL);
}
pc_cas_init(cas);
return cas;
}
void
pc_cas_del(pc_cassette_t *cas)
{
if (cas != NULL) {
pc_cas_free(cas);
free(cas);
}
}
int
pc_cas_set_fname(pc_cassette_t *cas, const char *fname)
{
unsigned n;
const char *ext;
if (cas->close)
fclose(cas->fp);
cas->close = 0;
cas->fp = NULL;
free(cas->fname);
cas->fname = NULL;
cas->position = 0;
cas->position_save = 0;
cas->position_load = 0;
if (fname == NULL) {
ui_sb_update_icon_state(SB_CASSETTE, 1);
return 0;
}
cas->fp = plat_fopen(fname, "r+b");
if (cas->fp == NULL)
cas->fp = plat_fopen(fname, "w+b");
if (cas->fp == NULL) {
ui_sb_update_icon_state(SB_CASSETTE, 1);
return 1;
}
cas->close = 1;
pc_cas_append(cas);
cas->position_save = cas->position;
if (cas->save == 0)
pc_cas_set_position(cas, 0);
n = strlen(fname);
cas->fname = malloc((n + 1) * sizeof(char));
if (cas->fname != NULL)
memcpy(cas->fname, fname, (n + 1) * sizeof(char));
if (n > 4) {
ext = fname + (n - 4);
/* Has to be 44.1 kHz, mono, 8-bit. */
if (stricmp(ext, ".pcm") == 0)
pc_cas_set_pcm(cas, 1);
else if (stricmp(ext, ".raw") == 0)
pc_cas_set_pcm(cas, 1);
else if (stricmp(ext, ".wav") == 0)
pc_cas_set_pcm(cas, 1);
else if (stricmp(ext, ".cas") == 0)
pc_cas_set_pcm(cas, 0);
}
return 0;
}
static void
pc_cas_reset(pc_cassette_t *cas)
{
cas->clk_pcm = 0;
cas->clk_out = cas->clk;
cas->clk_inp = 0;
cas->pcm_out_val = 0;
cas->cas_out_cnt = 0;
cas->cas_out_buf = 0;
cas->cas_inp_cnt = 0;
cas->cas_inp_buf = 0;
cas->cas_inp_bit = 0;
for (uint8_t i = 0; i < 3; i++) {
cas->pcm_inp_fir[i] = 0;
}
}
int
pc_cas_get_mode(const pc_cassette_t *cas)
{
return (cas->save);
}
void
pc_cas_set_mode(pc_cassette_t *cas, int save)
{
save = (save != 0);
if (cas->save == save) {
return;
}
if (cas->save) {
cas->position_save = cas->position;
cas->position = cas->position_load;
} else {
cas->position_load = cas->position;
cas->position = cas->position_save;
}
cas->save = save;
memset(cassette_mode, 0x00, sizeof(cassette_mode));
if (save)
memcpy(cassette_mode, "save", strlen("save") + 1);
else
memcpy(cassette_mode, "load", strlen("load") + 1);
if (cas->fp != NULL) {
fflush(cas->fp);
pc_cas_set_position(cas, cas->position);
}
pc_cas_reset(cas);
}
int
pc_cas_get_pcm(const pc_cassette_t *cas)
{
return (cas->pcm);
}
void
pc_cas_set_pcm(pc_cassette_t *cas, int pcm)
{
cas->pcm = (pcm != 0);
cassette_pcm = (pcm != 0);
pc_cas_reset(cas);
}
unsigned long
pc_cas_get_srate(const pc_cassette_t *cas)
{
return (cas->srate);
}
void
pc_cas_set_srate(pc_cassette_t *cas, unsigned long srate)
{
cas->srate = srate;
pc_cas_reset(cas);
}
void
pc_cas_rewind(pc_cassette_t *cas)
{
if (cas->fp != NULL) {
rewind(cas->fp);
cas->position = 0;
}
pc_cas_reset(cas);
}
void
pc_cas_append(pc_cassette_t *cas)
{
if (cas->fp != NULL) {
fseek(cas->fp, 0, SEEK_END);
cas->position = ftell(cas->fp);
}
pc_cas_reset(cas);
}
unsigned long
pc_cas_get_position(const pc_cassette_t *cas)
{
return (cas->position);
}
int
pc_cas_set_position(pc_cassette_t *cas, unsigned long pos)
{
if (cas->fp == NULL) {
return 1;
}
if (fseek(cas->fp, pos, SEEK_SET) != 0) {
return 1;
}
cas->position = pos;
pc_cas_reset(cas);
return 0;
}
static void
pc_cas_read_bit(pc_cassette_t *cas)
{
int val;
if (cas->cas_inp_cnt == 0) {
if (cas->fp == NULL) {
return;
}
if (feof(cas->fp)) {
return;
}
val = fgetc(cas->fp);
if (val == EOF) {
cassette_log("cassette EOF at %lu\n", cas->position);
return;
}
cas->position += 1;
cas->cas_inp_cnt = 8;
cas->cas_inp_buf = val;
}
cas->cas_inp_bit = ((cas->cas_inp_buf & 0x80) != 0);
cas->cas_inp_buf = (cas->cas_inp_buf << 1) & 0xff;
cas->cas_inp_cnt -= 1;
}
static int
pc_cas_read_smp(pc_cassette_t *cas)
{
int smp;
int *fir;
if (feof(cas->fp)) {
return 0;
}
smp = fgetc(cas->fp);
if (smp == EOF) {
cassette_log("cassette EOF at %lu\n", cas->position);
return 0;
}
cas->position += 1;
fir = cas->pcm_inp_fir;
fir[0] = fir[1];
fir[1] = fir[2];
fir[2] = (smp & 0x80) ? (smp - 256) : smp;
smp = (fir[0] + 2 * fir[1] + fir[2]) / 4;
return smp;
}
static void
pc_cas_write_bit(pc_cassette_t *cas, unsigned char val)
{
if (val && !cassette_ui_writeprot) {
cas->cas_out_buf |= (0x80 >> cas->cas_out_cnt);
}
cas->cas_out_cnt += 1;
if (cas->cas_out_cnt >= 8) {
if (cas->fp != NULL) {
if (!cassette_ui_writeprot)
fputc(cas->cas_out_buf, cas->fp);
cas->position += 1;
}
cas->cas_out_buf = 0;
cas->cas_out_cnt = 0;
}
}
static void
pc_cas_write_smp(pc_cassette_t *cas, int val)
{
unsigned char smp;
if (val < 0) {
smp = (val < -127) ? 0x80 : (val + 256);
} else {
smp = (val > 127) ? 0x7f : val;
}
if (!cassette_ui_writeprot)
fputc(smp, cas->fp);
cas->position += 1;
}
void
pc_cas_set_motor(pc_cassette_t *cas, unsigned char val)
{
val = (val != 0);
if (val == cas->motor) {
return;
}
if ((val == 0) && cas->save && cas->pcm) {
for (unsigned long i = 0; i < (cas->srate / 16); i++) {
pc_cas_write_smp(cas, 0);
}
}
cassette_log("cassette %S at %lu motor %s\n", (cas->fname != NULL) ? cas->fname : "<none>", cas->position, val ? "on" : "off");
cas->motor = val;
if (cas->fp != NULL) {
fflush(cas->fp);
pc_cas_set_position(cas, cas->position);
}
pc_cas_reset(cas);
if (cas->motor)
timer_set_delay_u64(&cas->timer, 8ULL * PITCONST);
else
timer_disable(&cas->timer);
ui_sb_update_icon(SB_CASSETTE, !!val);
}
unsigned char
pc_cas_get_inp(const pc_cassette_t *cas)
{
return (cas->data_inp);
}
void
pc_cas_set_out(pc_cassette_t *cas, unsigned char val)
{
unsigned long clk;
val = (val != 0);
if (cas->motor == 0) {
cas->data_inp = val;
return;
}
if (cas->data_out == val) {
return;
}
cas->data_out = val;
if (cas->pcm) {
cas->pcm_out_val = val ? -cas->pcm_out_vol : cas->pcm_out_vol;
return;
}
if (cas->save == 0) {
return;
}
if (val == 0) {
return;
}
clk = cas->clk - cas->clk_out;
cas->clk_out = cas->clk;
if (clk < (CAS_CLK / 4000)) {
;
} else if (clk < ((3 * CAS_CLK) / 4000)) {
pc_cas_write_bit(cas, 0);
} else if (clk < ((5 * CAS_CLK) / 4000)) {
pc_cas_write_bit(cas, 1);
}
}
void
pc_cas_print_state(UNUSED(const pc_cassette_t *cas))
{
cassette_log("%s %s %lu %s %lu\n", (cas->fname != NULL) ? cas->fname : "<none>", cas->pcm ? "pcm" : "cas", cas->srate, cas->save ? "save" : "load", cas->position);
}
static void
pc_cas_clock_pcm(pc_cassette_t *cas, unsigned long cnt)
{
uint64_t n;
int v = 0;
n = cas->srate * cnt + cas->clk_pcm;
cas->clk_pcm = n % CAS_CLK;
n = n / CAS_CLK;
if (n == 0) {
return;
}
if (cas->save) {
for (uint64_t i = 0; i < n; i++) {
pc_cas_write_smp(cas, cas->pcm_out_val);
}
} else {
for (uint64_t i = 0; i < n; i++) {
v = pc_cas_read_smp(cas);
}
cas->data_inp = (v < 0) ? 0 : 1;
}
}
void
pc_cas_clock(pc_cassette_t *cas, unsigned long cnt)
{
cas->clk += cnt;
if (cas->motor == 0) {
return;
}
if (cas->pcm) {
pc_cas_clock_pcm(cas, cnt);
return;
}
if (cas->save) {
return;
}
if (cas->clk_inp > cnt) {
cas->clk_inp -= cnt;
return;
}
cnt -= cas->clk_inp;
cas->data_inp = !cas->data_inp;
if (cas->data_inp) {
pc_cas_read_bit(cas);
}
if (cas->cas_inp_bit) {
cas->clk_inp = CAS_CLK / 2000;
} else {
cas->clk_inp = CAS_CLK / 4000;
}
if (cas->clk_inp > cnt) {
cas->clk_inp -= cnt;
}
}
void
pc_cas_advance(pc_cassette_t *cas)
{
int ticks;
cpu_s = (CPU *) &cpu_f->cpus[cpu_effective];
if (cas->motor == 0)
return;
if (cassette_cycles == -1)
cassette_cycles = cycles;
if (cycles <= cassette_cycles)
ticks = (cassette_cycles - cycles);
else
ticks = (cassette_cycles + (cpu_s->rspeed / 100) - cycles);
cassette_cycles = cycles;
pc_cas_clock(cas, ticks);
}
static void
cassette_close(UNUSED(void *priv))
{
if (cassette != NULL) {
free(cassette);
cassette = NULL;
}
}
static void
cassette_callback(void *priv)
{
pc_cassette_t *cas = (pc_cassette_t *) priv;
pc_cas_clock(cas, 8);
if (cas->motor)
ui_sb_update_icon(SB_CASSETTE, 1);
timer_advance_u64(&cas->timer, 8ULL * PITCONST);
}
static void *
cassette_init(UNUSED(const device_t *info))
{
cassette = NULL;
if (cassette_pcm == 1)
cassette_pcm = -1;
cassette_log("CASSETTE: file=%s mode=%s pcm=%d srate=%lu pos=%lu append=%d\n",
(cassette_fname != NULL) ? cassette_fname : "<none>", cassette_mode, cassette_pcm, cassette_srate, cassette_pos, cassette_append);
cassette = pc_cas_new();
if (cassette == NULL) {
cassette_log("ERROR: *** alloc failed\n");
return NULL;
}
if (strlen(cassette_fname) == 0) {
if (pc_cas_set_fname(cassette, NULL)) {
cassette_log("ERROR: *** opening file failed (%s)\n", cassette_fname);
}
} else {
if (pc_cas_set_fname(cassette, cassette_fname)) {
cassette_log("ERROR: *** opening file failed (%s)\n", cassette_fname);
}
}
if (strcmp(cassette_mode, "load") == 0)
pc_cas_set_mode(cassette, 0);
else if (strcmp(cassette_mode, "save") == 0)
pc_cas_set_mode(cassette, 1);
else {
cassette_log("ERROR: *** unknown cassette mode (%s)\n", cassette_mode);
}
if (cassette_append)
pc_cas_append(cassette);
else
pc_cas_set_position(cassette, cassette_pos);
if (cassette_pcm >= 0)
pc_cas_set_pcm(cassette, cassette_pcm);
pc_cas_set_srate(cassette, cassette_srate);
timer_add(&cassette->timer, cassette_callback, cassette, 0);
return cassette;
}
const device_t cassette_device = {
.name = "IBM PC/PCjr Cassette Device",
.internal_name = "cassette",
.flags = 0,
.local = 0,
.init = cassette_init,
.close = cassette_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/device/cassette.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,390 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the I2C bus and its operations.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/i2c.h>
#define NADDRS 128 /* I2C supports 128 addresses */
#define MAX(a, b) ((a) > (b) ? (a) : (b))
typedef struct _i2c_ {
uint8_t (*start)(void *bus, uint8_t addr, uint8_t read, void *priv);
uint8_t (*read)(void *bus, uint8_t addr, void *priv);
uint8_t (*write)(void *bus, uint8_t addr, uint8_t data, void *priv);
void (*stop)(void *bus, uint8_t addr, void *priv);
void *priv;
struct _i2c_ *prev, *next;
} i2c_t;
typedef struct i2c_bus_t {
char *name;
i2c_t *devices[NADDRS];
i2c_t *last[NADDRS];
} i2c_bus_t;
void *i2c_smbus;
#ifdef ENABLE_I2C_LOG
int i2c_do_log = ENABLE_I2C_LOG;
static void
i2c_log(const char *fmt, ...)
{
va_list ap;
if (i2c_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define i2c_log(fmt, ...)
#endif
void *
i2c_addbus(char *name)
{
i2c_bus_t *bus = (i2c_bus_t *) malloc(sizeof(i2c_bus_t));
memset(bus, 0, sizeof(i2c_bus_t));
bus->name = name;
return bus;
}
void
i2c_removebus(void *bus_handle)
{
i2c_t *p;
i2c_t *q;
i2c_bus_t *bus = (i2c_bus_t *) bus_handle;
if (!bus_handle)
return;
for (uint8_t c = 0; c < NADDRS; c++) {
p = bus->devices[c];
if (!p)
continue;
while (p) {
q = p->next;
free(p);
p = q;
}
}
free(bus);
}
char *
i2c_getbusname(void *bus_handle)
{
i2c_bus_t *bus = (i2c_bus_t *) bus_handle;
if (!bus_handle)
return (NULL);
return (bus->name);
}
void
i2c_sethandler(void *bus_handle, uint8_t base, int size,
uint8_t (*start)(void *bus, uint8_t addr, uint8_t read, void *priv),
uint8_t (*read)(void *bus, uint8_t addr, void *priv),
uint8_t (*write)(void *bus, uint8_t addr, uint8_t data, void *priv),
void (*stop)(void *bus, uint8_t addr, void *priv),
void *priv)
{
i2c_t *p;
i2c_t *q = NULL;
i2c_bus_t *bus = (i2c_bus_t *) bus_handle;
if (!bus_handle || ((base + size) > NADDRS))
return;
for (int c = 0; c < size; c++) {
p = bus->last[base + c];
q = (i2c_t *) malloc(sizeof(i2c_t));
memset(q, 0, sizeof(i2c_t));
if (p) {
p->next = q;
q->prev = p;
} else {
bus->devices[base + c] = q;
q->prev = NULL;
}
q->start = start;
q->read = read;
q->write = write;
q->stop = stop;
q->priv = priv;
q->next = NULL;
bus->last[base + c] = q;
}
}
void
i2c_removehandler(void *bus_handle, uint8_t base, int size,
uint8_t (*start)(void *bus, uint8_t addr, uint8_t read, void *priv),
uint8_t (*read)(void *bus, uint8_t addr, void *priv),
uint8_t (*write)(void *bus, uint8_t addr, uint8_t data, void *priv),
void (*stop)(void *bus, uint8_t addr, void *priv),
void *priv)
{
i2c_t *p;
i2c_t *q;
i2c_bus_t *bus = (i2c_bus_t *) bus_handle;
if (!bus_handle || ((base + size) > NADDRS))
return;
for (int c = 0; c < size; c++) {
p = bus->devices[base + c];
if (!p)
continue;
while (p) {
q = p->next;
if ((p->start == start) && (p->read == read) && (p->write == write) && (p->stop == stop) && (p->priv == priv)) {
if (p->prev)
p->prev->next = p->next;
else
bus->devices[base + c] = p->next;
if (p->next)
p->next->prev = p->prev;
else
bus->last[base + c] = p->prev;
free(p);
p = NULL;
break;
}
p = q;
}
}
}
void
i2c_handler(int set, void *bus_handle, uint8_t base, int size,
uint8_t (*start)(void *bus, uint8_t addr, uint8_t read, void *priv),
uint8_t (*read)(void *bus, uint8_t addr, void *priv),
uint8_t (*write)(void *bus, uint8_t addr, uint8_t data, void *priv),
void (*stop)(void *bus, uint8_t addr, void *priv),
void *priv)
{
if (set)
i2c_sethandler(bus_handle, base, size, start, read, write, stop, priv);
else
i2c_removehandler(bus_handle, base, size, start, read, write, stop, priv);
}
uint8_t
i2c_start(void *bus_handle, uint8_t addr, uint8_t read)
{
uint8_t ret = 0;
const i2c_bus_t *bus = (i2c_bus_t *) bus_handle;
i2c_t *p;
if (!bus)
return ret;
p = bus->devices[addr];
if (p) {
while (p) {
if (p->start) {
ret |= p->start(bus_handle, addr, read, p->priv);
}
p = p->next;
}
}
i2c_log("I2C %s: start(%02X) = %d\n", bus->name, addr, ret);
return ret;
}
uint8_t
i2c_read(void *bus_handle, uint8_t addr)
{
uint8_t ret = 0;
const i2c_bus_t *bus = (i2c_bus_t *) bus_handle;
i2c_t *p;
if (!bus)
return ret;
p = bus->devices[addr];
if (p) {
while (p) {
if (p->read) {
ret = p->read(bus_handle, addr, p->priv);
break;
}
p = p->next;
}
}
i2c_log("I2C %s: read(%02X) = %02X\n", bus->name, addr, ret);
return ret;
}
uint8_t
i2c_write(void *bus_handle, uint8_t addr, uint8_t data)
{
uint8_t ret = 0;
i2c_t *p;
const i2c_bus_t *bus = (i2c_bus_t *) bus_handle;
if (!bus)
return ret;
p = bus->devices[addr];
if (p) {
while (p) {
if (p->write) {
ret |= p->write(bus_handle, addr, data, p->priv);
}
p = p->next;
}
}
i2c_log("I2C %s: write(%02X, %02X) = %d\n", bus->name, addr, data, ret);
return ret;
}
void
i2c_stop(void *bus_handle, uint8_t addr)
{
const i2c_bus_t *bus = (i2c_bus_t *) bus_handle;
i2c_t *p;
if (!bus)
return;
p = bus->devices[addr];
if (p) {
while (p) {
if (p->stop) {
p->stop(bus_handle, addr, p->priv);
}
p = p->next;
}
}
i2c_log("I2C %s: stop(%02X)\n", bus->name, addr);
}
``` | /content/code_sandbox/src/device/i2c.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,188 |
```c
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* Implementation of a Clock/RTC Card for the ISA PC/XT.
*
* Systems starting with the PC/XT had, by default, a realtime
* clock and NVR chip on the mainboard. The BIOS stored config
* data in the NVR, and the system could maintain time and date
* using the RTC.
*
* Originally, PC systems did not have this, and they first did
* show up in non-IBM clone systems. Shortly after, expansion
* cards with this function became available for the PC's (ISA)
* bus, and they came in many forms and designs.
*
* This implementation offers some of those boards:
*
* Everex EV-170 (using NatSemi MM58167 chip)
* DTK PII-147 Hexa I/O Plus (using UMC 82C8167 chip)
*
* and more will follow as time permits.
*
* NOTE: The IRQ functionalities have been implemented, but not yet
* tested, as I need to write test software for them first :)
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/machine.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/nvr.h>
#include <86box/ui.h>
#include <86box/plat.h>
#include <86box/pic.h>
#include <86box/isartc.h>
#define ISARTC_EV170 0
#define ISARTC_DTK 1
#define ISARTC_P5PAK 2
#define ISARTC_A6PAK 3
#define ISARTC_VENDEX 4
#define ISARTC_DEBUG 0
typedef struct rtcdev_t {
const char *name; /* board name */
uint8_t board; /* board type */
uint8_t flags; /* various flags */
#define FLAG_YEAR80 0x01 /* YEAR byte is base-80 */
#define FLAG_YEARBCD 0x02 /* YEAR byte is in BCD */
int8_t irq; /* configured IRQ channel */
int8_t base_addrsz;
uint32_t base_addr; /* configured I/O address */
/* Fields for the specific driver. */
void (*f_wr)(uint16_t, uint8_t, void *);
uint8_t (*f_rd)(uint16_t, void *);
int8_t year; /* register for YEAR value */
char pad[3];
nvr_t nvr; /* RTC/NVR */
} rtcdev_t;
/************************************************************************
* *
* Driver for the NatSemi MM58167 chip. *
* *
************************************************************************/
#define MM67_REGS 32
/* Define the RTC chip registers - see datasheet, pg4. */
#define MM67_MSEC 0 /* milliseconds */
#define MM67_HUNTEN 1 /* hundredths/tenths of seconds */
#define MM67_SEC 2 /* seconds */
#define MM67_MIN 3 /* minutes */
#define MM67_HOUR 4 /* hours */
#define MM67_DOW 5 /* day of the week */
#define MM67_DOM 6 /* day of the month */
#define MM67_MON 7 /* month */
#define MM67_AL_MSEC 8 /* milliseconds */
#define MM67_AL_HUNTEN 9 /* hundredths/tenths of seconds */
#define MM67_AL_SEC 10 /* seconds */
#define MM67_AL_MIN 11 /* minutes */
#define MM67_AL_HOUR 12 /* hours */
#define MM67_AL_DOW 13 /* day of the week */
#define MM67_AL_DOM 14 /* day of the month */
#define MM67_AL_MON 15 /* month */
#define MM67_AL_DONTCARE 0xc0 /* always match in compare */
#define MM67_ISTAT 16 /* IRQ status */
#define MM67_ICTRL 17 /* IRQ control */
#define MM67INT_COMPARE 0x01 /* Compare */
#define MM67INT_TENTH 0x02 /* Tenth */
#define MM67INT_SEC 0x04 /* Second */
#define MM67INT_MIN 0x08 /* Minute */
#define MM67INT_HOUR 0x10 /* Hour */
#define MM67INT_DAY 0x20 /* Day */
#define MM67INT_WEEK 0x40 /* Week */
#define MM67INT_MON 0x80 /* Month */
#define MM67_RSTCTR 18 /* reset counters */
#define MM67_RSTRAM 19 /* reset RAM */
#define MM67_STATUS 20 /* status bit */
#define MM67_GOCMD 21 /* GO Command */
#define MM67_STBYIRQ 22 /* standby IRQ */
#define MM67_TEST 31 /* test mode */
#ifdef ENABLE_ISARTC_LOG
int isartc_do_log = ENABLE_ISARTC_LOG;
static void
isartc_log(const char *fmt, ...)
{
va_list ap;
if (isartc_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define isartc_log(fmt, ...)
#endif
/* Check if the current time matches a set alarm time. */
static int8_t
mm67_chkalrm(nvr_t *nvr, int8_t addr)
{
return ((nvr->regs[addr - MM67_AL_SEC + MM67_SEC] == nvr->regs[addr]) || ((nvr->regs[addr] & MM67_AL_DONTCARE) == MM67_AL_DONTCARE));
}
/*
* This is called every second through the NVR/RTC hook.
*
* We fake a 'running' RTC by updating its registers on
* each passing second. Not exactly accurate, but good
* enough.
*
* Note that this code looks nasty because of all the
* BCD to decimal vv going on.
*/
static void
mm67_tick(nvr_t *nvr)
{
const rtcdev_t *dev = (rtcdev_t *) nvr->data;
uint8_t *regs = nvr->regs;
int mon;
int year;
int f = 0;
/* Update and set interrupt if needed. */
regs[MM67_SEC] = RTC_BCDINC(nvr->regs[MM67_SEC], 1);
if (regs[MM67_ICTRL] & MM67INT_SEC)
f = MM67INT_SEC;
/* Roll over? */
if (regs[MM67_SEC] >= RTC_BCD(60)) {
/* Update and set interrupt if needed. */
regs[MM67_SEC] = RTC_BCD(0);
regs[MM67_MIN] = RTC_BCDINC(regs[MM67_MIN], 1);
if (regs[MM67_ICTRL] & MM67INT_MIN)
f = MM67INT_MIN;
/* Roll over? */
if (regs[MM67_MIN] >= RTC_BCD(60)) {
/* Update and set interrupt if needed. */
regs[MM67_MIN] = RTC_BCD(0);
regs[MM67_HOUR] = RTC_BCDINC(regs[MM67_HOUR], 1);
if (regs[MM67_ICTRL] & MM67INT_HOUR)
f = MM67INT_HOUR;
/* Roll over? */
if (regs[MM67_HOUR] >= RTC_BCD(24)) {
/* Update and set interrupt if needed. */
regs[MM67_HOUR] = RTC_BCD(0);
regs[MM67_DOW] = RTC_BCDINC(regs[MM67_DOW], 1);
if (regs[MM67_ICTRL] & MM67INT_DAY)
f = MM67INT_DAY;
/* Roll over? */
if (regs[MM67_DOW] > RTC_BCD(7)) {
/* Update and set interrupt if needed. */
regs[MM67_DOW] = RTC_BCD(1);
if (regs[MM67_ICTRL] & MM67INT_WEEK)
f = MM67INT_WEEK;
}
/* Roll over? */
regs[MM67_DOM] = RTC_BCDINC(regs[MM67_DOM], 1);
mon = RTC_DCB(regs[MM67_MON]);
if (dev->year != -1) {
if (dev->flags & FLAG_YEARBCD)
year = RTC_DCB(regs[dev->year]);
else
year = regs[dev->year];
if (dev->flags & FLAG_YEAR80)
year += 80;
} else
year = 80;
year += 1900;
if (RTC_DCB(regs[MM67_DOM]) > nvr_get_days(mon, year)) {
/* Update and set interrupt if needed. */
regs[MM67_DOM] = RTC_BCD(1);
regs[MM67_MON] = RTC_BCDINC(regs[MM67_MON], 1);
if (regs[MM67_ICTRL] & MM67INT_MON)
f = MM67INT_MON;
/* Roll over? */
if (regs[MM67_MON] > RTC_BCD(12)) {
/* Update. */
regs[MM67_MON] = RTC_BCD(1);
if (dev->year != -1) {
year++;
if (dev->flags & FLAG_YEAR80)
year -= 80;
if (dev->flags & FLAG_YEARBCD)
regs[dev->year] = RTC_BCD(year % 100);
else
regs[dev->year] = year % 100;
}
}
}
}
}
}
/* Check for programmed alarm interrupt. */
if (regs[MM67_ICTRL] & MM67INT_COMPARE) {
year = 1;
for (mon = MM67_AL_SEC; mon <= MM67_AL_MON; mon++)
if (mon != dev->year)
year &= mm67_chkalrm(nvr, mon);
f = year ? MM67INT_COMPARE : 0x00;
}
/* Raise the IRQ if needed (and if we have one..) */
if (f != 0) {
regs[MM67_ISTAT] = f;
if (nvr->irq != -1)
picint(1 << nvr->irq);
}
}
/* Get the current NVR time. */
static void
mm67_time_get(nvr_t *nvr, struct tm *tm)
{
const rtcdev_t *dev = (rtcdev_t *) nvr->data;
const uint8_t *regs = nvr->regs;
/* NVR is in BCD data mode. */
tm->tm_sec = RTC_DCB(regs[MM67_SEC]);
tm->tm_min = RTC_DCB(regs[MM67_MIN]);
tm->tm_hour = RTC_DCB(regs[MM67_HOUR]);
tm->tm_wday = (RTC_DCB(regs[MM67_DOW]) - 1);
tm->tm_mday = RTC_DCB(regs[MM67_DOM]);
tm->tm_mon = (RTC_DCB(regs[MM67_MON]) - 1);
if (dev->year != -1) {
if (dev->flags & FLAG_YEARBCD)
tm->tm_year = RTC_DCB(regs[dev->year]);
else
tm->tm_year = regs[dev->year];
if (dev->flags & FLAG_YEAR80)
tm->tm_year += 80;
#ifdef MM67_CENTURY
tm->tm_year += (regs[MM67_CENTURY] * 100) - 1900;
#endif
#if ISARTC_DEBUG > 1
isartc_log("ISARTC: get_time: year=%i [%02x]\n", tm->tm_year, regs[dev->year]);
#endif
}
}
/* Set the current NVR time. */
static void
mm67_time_set(nvr_t *nvr, struct tm *tm)
{
const rtcdev_t *dev = (rtcdev_t *) nvr->data;
uint8_t *regs = nvr->regs;
int year;
/* NVR is in BCD data mode. */
regs[MM67_SEC] = RTC_BCD(tm->tm_sec);
regs[MM67_MIN] = RTC_BCD(tm->tm_min);
regs[MM67_HOUR] = RTC_BCD(tm->tm_hour);
regs[MM67_DOW] = RTC_BCD(tm->tm_wday + 1);
regs[MM67_DOM] = RTC_BCD(tm->tm_mday);
regs[MM67_MON] = RTC_BCD(tm->tm_mon + 1);
if (dev->year != -1) {
year = tm->tm_year;
if (dev->flags & FLAG_YEAR80)
year -= 80;
if (dev->flags & FLAG_YEARBCD)
regs[dev->year] = RTC_BCD(year % 100);
else
regs[dev->year] = year % 100;
#ifdef MM67_CENTURY
regs[MM67_CENTURY] = (year + 1900) / 100;
#endif
#if ISARTC_DEBUG > 1
isartc_log("ISARTC: set_time: [%02x] year=%i (%i)\n", regs[dev->year], year, tm->tm_year);
#endif
}
}
static void
mm67_start(nvr_t *nvr)
{
struct tm tm;
/* Initialize the internal and chip times. */
if (time_sync) {
/* Use the internal clock's time. */
nvr_time_get(&tm);
mm67_time_set(nvr, &tm);
} else {
/* Set the internal clock from the chip time. */
mm67_time_get(nvr, &tm);
nvr_time_set(&tm);
}
}
/* Reset the RTC counters to a sane state. */
static void
mm67_reset(nvr_t *nvr)
{
/* Initialize the RTC to a known state. */
for (uint8_t i = MM67_MSEC; i <= MM67_MON; i++)
nvr->regs[i] = RTC_BCD(0);
nvr->regs[MM67_DOW] = RTC_BCD(1);
nvr->regs[MM67_DOM] = RTC_BCD(1);
nvr->regs[MM67_MON] = RTC_BCD(1);
}
/* Handle a READ operation from one of our registers. */
static uint8_t
mm67_read(uint16_t port, void *priv)
{
rtcdev_t *dev = (rtcdev_t *) priv;
int reg = port - dev->base_addr;
uint8_t ret = 0xff;
/* This chip is directly mapped on I/O. */
cycles -= ISA_CYCLES(4);
switch (reg) {
case MM67_ISTAT: /* IRQ status (RO) */
ret = dev->nvr.regs[reg];
dev->nvr.regs[reg] = 0x00;
if (dev->irq != -1)
picintc(1 << dev->irq);
break;
case MM67_AL_MSEC:
ret = dev->nvr.regs[reg] & 0xf0;
break;
case MM67_AL_DOW:
ret = dev->nvr.regs[reg] & 0x0f;
break;
default:
ret = dev->nvr.regs[reg];
break;
}
#if ISARTC_DEBUG
isartc_log("ISARTC: read(%04x) = %02x\n", port - dev->base_addr, ret);
#endif
return ret;
}
/* Handle a WRITE operation to one of our registers. */
static void
mm67_write(uint16_t port, uint8_t val, void *priv)
{
rtcdev_t *dev = (rtcdev_t *) priv;
int reg = port - dev->base_addr;
#if ISARTC_DEBUG
isartc_log("ISARTC: write(%04x, %02x)\n", port - dev->base_addr, val);
#endif
/* This chip is directly mapped on I/O. */
cycles -= ISA_CYCLES(4);
switch (reg) {
case MM67_ISTAT: /* intr status (RO) */
break;
case MM67_ICTRL: /* intr control */
dev->nvr.regs[MM67_ISTAT] = 0x00;
dev->nvr.regs[reg] = val;
break;
case MM67_RSTCTR:
if (val == 0xff)
mm67_reset(&dev->nvr);
break;
case MM67_RSTRAM:
if (val == 0xff) {
for (uint8_t i = MM67_AL_MSEC; i <= MM67_AL_MON; i++)
dev->nvr.regs[i] = RTC_BCD(0);
dev->nvr.regs[MM67_DOW] = RTC_BCD(1);
dev->nvr.regs[MM67_DOM] = RTC_BCD(1);
dev->nvr.regs[MM67_MON] = RTC_BCD(1);
if (dev->year != -1) {
val = (dev->flags & FLAG_YEAR80) ? 0 : 80;
if (dev->flags & FLAG_YEARBCD)
dev->nvr.regs[dev->year] = RTC_BCD(val);
else
dev->nvr.regs[dev->year] = val;
#ifdef MM67_CENTURY
dev->nvr.regs[MM67_CENTURY] = 19;
#endif
}
}
break;
case MM67_STATUS: /* STATUS (RO) */
break;
case MM67_GOCMD:
isartc_log("RTC: write gocmd=%02x\n", val);
break;
case MM67_STBYIRQ:
isartc_log("RTC: write stby=%02x\n", val);
break;
case MM67_TEST:
isartc_log("RTC: write test=%02x\n", val);
break;
case MM67_AL_MSEC:
dev->nvr.regs[reg] = val & 0xf0;
break;
case MM67_AL_DOW:
dev->nvr.regs[reg] = val & 0x0f;
break;
default:
dev->nvr.regs[reg] = val;
break;
}
}
/************************************************************************
* *
* Generic code for all supported chips. *
* *
************************************************************************/
/* Initialize the device for use. */
static void *
isartc_init(const device_t *info)
{
rtcdev_t *dev;
int is_at = IS_AT(machine);
is_at = is_at || !strcmp(machine_get_internal_name(), "xi8088");
/* Create a device instance. */
dev = (rtcdev_t *) malloc(sizeof(rtcdev_t));
memset(dev, 0x00, sizeof(rtcdev_t));
dev->name = info->name;
dev->board = info->local;
dev->irq = -1;
dev->year = -1;
dev->nvr.data = dev;
dev->nvr.size = 16;
/* Do per-board initialization. */
switch (dev->board) {
case ISARTC_EV170: /* Everex EV-170 Magic I/O */
dev->flags |= FLAG_YEAR80;
dev->base_addr = device_get_config_hex16("base");
dev->base_addrsz = 32;
dev->irq = device_get_config_int("irq");
dev->f_rd = mm67_read;
dev->f_wr = mm67_write;
dev->nvr.reset = mm67_reset;
dev->nvr.start = mm67_start;
dev->nvr.tick = mm67_tick;
dev->year = MM67_AL_DOM; /* year, NON STANDARD */
break;
case ISARTC_DTK: /* DTK PII-147 Hexa I/O Plus */
dev->flags |= FLAG_YEARBCD;
dev->base_addr = device_get_config_hex16("base");
dev->base_addrsz = 32;
dev->f_rd = mm67_read;
dev->f_wr = mm67_write;
dev->nvr.reset = mm67_reset;
dev->nvr.start = mm67_start;
dev->nvr.tick = mm67_tick;
dev->year = MM67_AL_HUNTEN; /* year, NON STANDARD */
break;
case ISARTC_P5PAK: /* Paradise Systems 5PAK */
case ISARTC_A6PAK: /* AST SixPakPlus */
dev->flags |= FLAG_YEAR80;
dev->base_addr = 0x02c0;
dev->base_addrsz = 32;
dev->irq = device_get_config_int("irq");
dev->f_rd = mm67_read;
dev->f_wr = mm67_write;
dev->nvr.reset = mm67_reset;
dev->nvr.start = mm67_start;
dev->nvr.tick = mm67_tick;
dev->year = MM67_AL_DOM; /* year, NON STANDARD */
break;
case ISARTC_VENDEX: /* Vendex HeadStart Turbo 888-XT RTC */
dev->flags |= FLAG_YEAR80 | FLAG_YEARBCD;
dev->base_addr = 0x0300;
dev->base_addrsz = 32;
dev->f_rd = mm67_read;
dev->f_wr = mm67_write;
dev->nvr.reset = mm67_reset;
dev->nvr.start = mm67_start;
dev->nvr.tick = mm67_tick;
dev->year = MM67_AL_DOM; /* year, NON STANDARD */
break;
default:
break;
}
/* Say hello! */
isartc_log("ISARTC: %s (I/O=%04XH", info->name, dev->base_addr);
if (dev->irq != -1)
isartc_log(", IRQ%i", dev->irq);
isartc_log(")\n");
/* Set up an I/O port handler. */
io_sethandler(dev->base_addr, dev->base_addrsz,
dev->f_rd, NULL, NULL, dev->f_wr, NULL, NULL, dev);
/* Hook into the NVR backend. */
dev->nvr.fn = (char *) info->internal_name;
dev->nvr.irq = dev->irq;
if (!is_at)
nvr_init(&dev->nvr);
/* Let them know our device instance. */
return ((void *) dev);
}
/* Remove the device from the system. */
static void
isartc_close(void *priv)
{
rtcdev_t *dev = (rtcdev_t *) priv;
io_removehandler(dev->base_addr, dev->base_addrsz,
dev->f_rd, NULL, NULL, dev->f_wr, NULL, NULL, dev);
free(dev);
}
static const device_config_t ev170_config[] = {
// clang-format off
{
"base", "Address", CONFIG_HEX16, "", 0x02C0, "", { 0 },
{
{ "240H", 0x0240 },
{ "2C0H", 0x02c0 },
{ "" }
},
},
{
"irq", "IRQ", CONFIG_SELECTION, "", -1, "", { 0 },
{
{ "Disabled", -1 },
{ "IRQ2", 2 },
{ "IRQ5", 5 },
{ "IRQ7", 7 },
{ "" }
},
},
{ "", "", -1 }
// clang-format on
};
static const device_t ev170_device = {
.name = "Everex EV-170 Magic I/O",
.internal_name = "ev170",
.flags = DEVICE_ISA,
.local = ISARTC_EV170,
.init = isartc_init,
.close = isartc_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ev170_config
};
static const device_config_t pii147_config[] = {
// clang-format off
{
"base", "Address", CONFIG_HEX16, "", 0x0240, "", { 0 },
{
{ "Clock 1", 0x0240 },
{ "Clock 2", 0x0340 },
{ "" }
},
},
{ "", "", -1 }
// clang-format on
};
static const device_t pii147_device = {
.name = "DTK PII-147 Hexa I/O Plus",
.internal_name = "pii147",
.flags = DEVICE_ISA,
.local = ISARTC_DTK,
.init = isartc_init,
.close = isartc_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = pii147_config
};
static const device_config_t p5pak_config[] = {
// clang-format off
{
"irq", "IRQ", CONFIG_SELECTION, "", -1, "", { 0 },
{
{ "Disabled", -1 },
{ "IRQ2", 2 },
{ "IRQ3", 3 },
{ "IRQ5", 5 },
{ "" }
},
},
{ "", "", -1 }
// clang-format on
};
static const device_t p5pak_device = {
.name = "Paradise Systems 5-PAK",
.internal_name = "p5pak",
.flags = DEVICE_ISA,
.local = ISARTC_P5PAK,
.init = isartc_init,
.close = isartc_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = p5pak_config
};
static const device_config_t a6pak_config[] = {
// clang-format off
{
"irq", "IRQ", CONFIG_SELECTION, "", -1, "", { 0 },
{
{ "Disabled", -1 },
{ "IRQ2", 2 },
{ "IRQ3", 3 },
{ "IRQ5", 5 },
{ "" }
},
},
{ "", "", -1 }
// clang-format on
};
static const device_t a6pak_device = {
.name = "AST SixPakPlus",
.internal_name = "a6pak",
.flags = DEVICE_ISA,
.local = ISARTC_A6PAK,
.init = isartc_init,
.close = isartc_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = a6pak_config
};
/* Onboard RTC devices */
const device_t vendex_xt_rtc_onboard_device = {
.name = "National Semiconductor MM58167 (Vendex)",
.internal_name = "vendex_xt_rtc",
.flags = DEVICE_ISA,
.local = ISARTC_VENDEX,
.init = isartc_init,
.close = isartc_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
static const struct {
const device_t *dev;
} boards[] = {
// clang-format off
{ &device_none },
{ &ev170_device },
{ &pii147_device },
{ &p5pak_device },
{ &a6pak_device },
{ NULL },
// clang-format on
};
void
isartc_reset(void)
{
if (isartc_type == 0)
return;
/* Add the device to the system. */
device_add(boards[isartc_type].dev);
}
const char *
isartc_get_internal_name(int board)
{
return device_get_internal_name(boards[board].dev);
}
int
isartc_get_from_internal_name(char *s)
{
int c = 0;
while (boards[c].dev != NULL) {
if (!strcmp(boards[c].dev->internal_name, s))
return c;
c++;
}
/* Not found. */
return 0;
}
const device_t *
isartc_get_device(int board)
{
return (boards[board].dev);
}
int
isartc_has_config(int board)
{
if (boards[board].dev == NULL)
return 0;
return (boards[board].dev->config ? 1 : 0);
}
``` | /content/code_sandbox/src/device/isartc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,997 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the NEC Mate NX MA30D/23D Unknown Readout.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
static uint8_t
nec_mate_unk_read(UNUSED(uint16_t addr), void *priv)
{
/* Expected by this NEC machine.
It writes something on ports 3D6C, 3D6D, and 3D6E, then expects to read
2Ah from port 3D6D. Then it repeats this with ports 6A, 6B, and 6C.
*/
return 0x2a;
}
static void
nec_mate_unk_close(void *priv)
{
uint8_t *dev = (uint8_t *) priv;
free(dev);
}
static void *
nec_mate_unk_init(const device_t *info)
{
/* We have to return something non-NULL. */
uint8_t *dev = (uint8_t *) calloc(1, sizeof(uint8_t));
io_sethandler(0x006b, 0x0001, nec_mate_unk_read, NULL, NULL, NULL, NULL, NULL, NULL);
io_sethandler(0x3d6d, 0x0001, nec_mate_unk_read, NULL, NULL, NULL, NULL, NULL, NULL);
return dev;
}
const device_t nec_mate_unk_device = {
.name = "NEC Mate NX MA30D/23D Unknown Readout",
.internal_name = "nec_mate_unk",
.flags = 0,
.local = 0,
.init = nec_mate_unk_init,
.close = nec_mate_unk_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/device/nec_mate_unk.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 588 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ISA Bus (de)Bugger expansion card
* sold as a DIY kit in the late 1980's in The Netherlands.
* This card was a assemble-yourself 8bit ISA addon card for
* PC and AT systems that had several tools to aid in low-
* level debugging (mostly for faulty BIOSes, bootloaders
* and system kernels...)
*
* The standard version had a total of 16 LEDs (8 RED, plus
* 8 GREEN), two 7-segment displays and one 8-position DIP
* switch block on board for use as debugging tools.
*
* The "Plus" version, added an extra 2 7-segment displays,
* as well as a very simple RS-232 serial interface that
* could be used as a mini-console terminal.
*
* Two I/O ports were used; one for control, at offset 0 in
* I/O space, and one for data, at offset 1 in I/O space.
* Both registers could be read from and written to. Although
* the author has a vague memory of a DIP switch to set the
* board's I/O address, comments in old software seems to
* indicate that it was actually fixed to 0x7A (and 0x7B.)
*
* A READ on the data register always returned the actual
* state of the DIP switch. Writing data to the LEDs was done
* in two steps.. first, the block number (RED or GREEN) was
* written to the CTRL register, and then the actual LED data
* was written to the DATA register. Likewise, data for the
* 7-segment displays was written.
*
* The serial port was a bit different, and its operation is
* not verified, but two extra bits in the control register
* were used to set up parameters, and also the actual data
* input and output.
*
* TODO: Still have to implement the RS232 Serial Port Parameters
* configuration register (CTRL_SPCFG bit set) but have to
* remember that stuff first...
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/bugger.h>
/* BugBugger registers. */
#define BUG_CTRL 0
#define CTRL_RLED 0x00 /* write to the RED LED block */
#define CTRL_GLED 0x01 /* write to the GREEN LED block */
#define CTRL_SEG1 0x02 /* write to the RIGHT 7SEG displays */
#define CTRL_SEG2 0x04 /* write to the LEFT 7SEG displays */
#define CTRL_SPORT 0x20 /* enable the serial port */
#define CTRL_SPCFG 0x40 /* set up the serial port */
#define CTRL_INIT 0x80 /* enable and reset the card */
#define CTRL_RESET 0xff /* this resets the board */
#define BUG_DATA 1
static uint8_t bug_ctrl; /* control register */
static uint8_t bug_data; /* data register */
static uint8_t bug_ledr; /* RED LEDs */
static uint8_t bug_ledg; /* GREEN LEDs */
static uint8_t bug_seg1;
static uint8_t bug_seg2; /* LEFT and RIGHT 7SEG displays */
static uint8_t bug_spcfg; /* serial port configuration */
#define FIFO_LEN 256
static uint8_t bug_buff[FIFO_LEN]; /* serial port data buffer */
static uint8_t *bug_bptr;
#define UISTR_LEN 24
static char bug_str[UISTR_LEN]; /* UI output string */
extern void ui_sb_bugui(char *__str);
#ifdef ENABLE_BUGGER_LOG
int bugger_do_log = ENABLE_BUGGER_LOG;
static void
bugger_log(const char *fmt, ...)
{
va_list ap;
if (bugger_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define bugger_log(fmt, ...)
#endif
/* Update the system's UI with the actual Bugger status. */
static void
bug_setui(void)
{
/* Format all current info in a string. */
sprintf(bug_str, "%02X:%02X %c%c%c%c%c%c%c%c-%c%c%c%c%c%c%c%c",
bug_seg2, bug_seg1,
(bug_ledg & 0x80) ? 'G' : 'g', (bug_ledg & 0x40) ? 'G' : 'g',
(bug_ledg & 0x20) ? 'G' : 'g', (bug_ledg & 0x10) ? 'G' : 'g',
(bug_ledg & 0x08) ? 'G' : 'g', (bug_ledg & 0x04) ? 'G' : 'g',
(bug_ledg & 0x02) ? 'G' : 'g', (bug_ledg & 0x01) ? 'G' : 'g',
(bug_ledr & 0x80) ? 'R' : 'r', (bug_ledr & 0x40) ? 'R' : 'r',
(bug_ledr & 0x20) ? 'R' : 'r', (bug_ledr & 0x10) ? 'R' : 'r',
(bug_ledr & 0x08) ? 'R' : 'r', (bug_ledr & 0x04) ? 'R' : 'r',
(bug_ledr & 0x02) ? 'R' : 'r', (bug_ledr & 0x01) ? 'R' : 'r');
/* Send formatted string to the UI. */
ui_sb_bugui(bug_str);
}
/* Flush the serial port. */
static void
bug_spflsh(void)
{
*bug_bptr = '\0';
bugger_log("BUGGER- serial port [%s]\n", bug_buff);
bug_bptr = bug_buff;
}
/* Handle a write to the Serial Port Data register. */
static void
bug_wsport(uint8_t val)
{
uint8_t old = bug_ctrl;
/* Clear the SPORT bit to indicate we are busy. */
bug_ctrl &= ~CTRL_SPORT;
/* Delay while processing byte.. */
if (bug_bptr == &bug_buff[FIFO_LEN - 1]) {
/* Buffer full, gotta flush. */
bug_spflsh();
}
/* Write (store) the byte. */
*bug_bptr++ = val;
/* Restore the SPORT bit. */
bug_ctrl |= (old & CTRL_SPORT);
bugger_log("BUGGER- sport %02x\n", val);
}
/* Handle a write to the Serial Port Configuration register. */
static void
bug_wspcfg(uint8_t val)
{
bug_spcfg = val;
bugger_log("BUGGER- spcfg %02x\n", bug_spcfg);
}
/* Handle a write to the control register. */
static void
bug_wctrl(uint8_t val)
{
if (val == CTRL_RESET) {
/* User wants us to reset. */
bug_ctrl = CTRL_INIT;
bug_spcfg = 0x00;
bug_bptr = NULL;
} else {
/* If turning off the serial port, flush it. */
if ((bug_ctrl & CTRL_SPORT) && !(val & CTRL_SPORT))
bug_spflsh();
/* FIXME: did they do this using an XOR of operation bits? --FvK */
if (val & CTRL_SPCFG) {
/* User wants to configure the serial port. */
bug_ctrl &= ~(CTRL_SPORT | CTRL_SEG2 | CTRL_SEG1 | CTRL_GLED);
bug_ctrl |= CTRL_SPCFG;
} else if (val & CTRL_SPORT) {
/* User wants to talk to the serial port. */
bug_ctrl &= ~(CTRL_SPCFG | CTRL_SEG2 | CTRL_SEG1 | CTRL_GLED);
bug_ctrl |= CTRL_SPORT;
if (bug_bptr == NULL)
bug_bptr = bug_buff;
} else if (val & CTRL_SEG2) {
/* User selected SEG2 (LEFT, Plus only) for output. */
bug_ctrl &= ~(CTRL_SPCFG | CTRL_SPORT | CTRL_SEG1 | CTRL_GLED);
bug_ctrl |= CTRL_SEG2;
} else if (val & CTRL_SEG1) {
/* User selected SEG1 (RIGHT) for output. */
bug_ctrl &= ~(CTRL_SPCFG | CTRL_SPORT | CTRL_SEG2 | CTRL_GLED);
bug_ctrl |= CTRL_SEG1;
} else if (val & CTRL_GLED) {
/* User selected the GREEN LEDs for output. */
bug_ctrl &= ~(CTRL_SPCFG | CTRL_SPORT | CTRL_SEG2 | CTRL_SEG1);
bug_ctrl |= CTRL_GLED;
} else {
/* User selected the RED LEDs for output. */
bug_ctrl &= ~(CTRL_SPCFG | CTRL_SPORT | CTRL_SEG2 | CTRL_SEG1 | CTRL_GLED);
}
}
/* Update the UI with active settings. */
bugger_log("BUGGER- ctrl %02x\n", bug_ctrl);
bug_setui();
}
/* Handle a write to the data register. */
static void
bug_wdata(uint8_t val)
{
bug_data = val;
if (bug_ctrl & CTRL_SPCFG)
bug_wspcfg(val);
else if (bug_ctrl & CTRL_SPORT)
bug_wsport(val);
else {
if (bug_ctrl & CTRL_SEG2)
bug_seg2 = val;
else if (bug_ctrl & CTRL_SEG1)
bug_seg1 = val;
else if (bug_ctrl & CTRL_GLED)
bug_ledg = val;
else
bug_ledr = val;
bugger_log("BUGGER- data %02x\n", bug_data);
}
/* Update the UI with active settings. */
bug_setui();
}
/* Reset the ISA BusBugger controller. */
static void
bug_reset(void)
{
/* Clear the data register. */
bug_data = 0x00;
/* Clear the RED and GREEN LEDs. */
bug_ledr = 0x00;
bug_ledg = 0x00;
/* Clear both 7SEG displays. */
bug_seg1 = 0x00;
bug_seg2 = 0x00;
/* Reset the control register (updates UI.) */
bug_wctrl(CTRL_RESET);
}
/* Handle a WRITE operation to one of our registers. */
static void
bug_write(uint16_t port, uint8_t val, UNUSED(void *priv))
{
switch (port - BUGGER_ADDR) {
case BUG_CTRL: /* control register */
if (val == CTRL_RESET) {
/* Perform a full reset. */
bug_reset();
} else if (bug_ctrl & CTRL_INIT) {
/* Only allow writes if initialized. */
bug_wctrl(val);
}
break;
case BUG_DATA: /* data register */
if (bug_ctrl & CTRL_INIT) {
bug_wdata(val);
}
break;
default:
break;
}
}
/* Handle a READ operation from one of our registers. */
static uint8_t
bug_read(uint16_t port, UNUSED(void *priv))
{
uint8_t ret = 0xff;
if (bug_ctrl & CTRL_INIT)
switch (port - BUGGER_ADDR) {
case BUG_CTRL: /* control register */
ret = bug_ctrl;
break;
case BUG_DATA: /* data register */
if (bug_ctrl & CTRL_SPCFG) {
ret = bug_spcfg;
} else if (bug_ctrl & CTRL_SPORT) {
ret = 0x00; /* input not supported */
} else {
/* Just read the DIP switch. */
ret = bug_data;
}
break;
default:
break;
}
return ret;
}
/* Initialize the ISA BusBugger emulator. */
static void *
bug_init(UNUSED(const device_t *info))
{
bugger_log("%s, I/O=%04x\n", info->name, BUGGER_ADDR);
/* Initialize local registers. */
bug_reset();
io_sethandler(BUGGER_ADDR, BUGGER_ADDRLEN,
bug_read, NULL, NULL, bug_write, NULL, NULL, NULL);
/* Just so its not NULL. */
return (&bug_ctrl);
}
/* Remove the ISA BusBugger emulator from the system. */
static void
bug_close(UNUSED(void *priv))
{
io_removehandler(BUGGER_ADDR, BUGGER_ADDRLEN,
bug_read, NULL, NULL, bug_write, NULL, NULL, NULL);
}
const device_t bugger_device = {
.name = "ISA/PCI Bus Bugger",
.internal_name = "bugger",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 0,
.init = bug_init,
.close = bug_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/device/bugger.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,030 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Phoenix 486 Jumper Readout.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Tiseno100,
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
/*
Bit 7 = Super I/O chip: 1 = enabled, 0 = disabled;
Bit 6 = Graphics card: 1 = standalone, 0 = on-board;
Bit 5 = ???? (if 1, siren and hangs);
Bit 4 = ????;
Bit 3 = ????;
Bit 2 = ????;
Bit 1 = ????;
Bit 0 = ????.
*/
typedef struct phoenix_486_jumper_t {
uint8_t type;
uint8_t jumper;
} phoenix_486_jumper_t;
#ifdef ENABLE_PHOENIX_486_JUMPER_LOG
int phoenix_486_jumper_do_log = ENABLE_PHOENIX_486_JUMPER_LOG;
static void
phoenix_486_jumper_log(const char *fmt, ...)
{
va_list ap;
if (phoenix_486_jumper_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define phoenix_486_jumper_log(fmt, ...)
#endif
static void
phoenix_486_jumper_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
phoenix_486_jumper_log("Phoenix 486 Jumper: Write %02x\n", val);
if (dev->type == 1)
dev->jumper = val & 0xbf;
else
dev->jumper = val;
}
static uint8_t
phoenix_486_jumper_read(UNUSED(uint16_t addr), void *priv)
{
const phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
phoenix_486_jumper_log("Phoenix 486 Jumper: Read %02x\n", dev->jumper);
return dev->jumper;
}
static void
phoenix_486_jumper_reset(void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
if (dev->type == 1)
dev->jumper = 0x00;
else {
dev->jumper = 0x9f;
if (gfxcard[0] != 0x01)
dev->jumper |= 0x40;
}
}
static void
phoenix_486_jumper_close(void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
free(dev);
}
static void *
phoenix_486_jumper_init(const device_t *info)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) malloc(sizeof(phoenix_486_jumper_t));
memset(dev, 0, sizeof(phoenix_486_jumper_t));
dev->type = info->local;
phoenix_486_jumper_reset(dev);
io_sethandler(0x0078, 0x0001, phoenix_486_jumper_read, NULL, NULL, phoenix_486_jumper_write, NULL, NULL, dev);
return dev;
}
const device_t phoenix_486_jumper_device = {
.name = "Phoenix 486 Jumper Readout",
.internal_name = "phoenix_486_jumper",
.flags = 0,
.local = 0,
.init = phoenix_486_jumper_init,
.close = phoenix_486_jumper_close,
.reset = phoenix_486_jumper_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t phoenix_486_jumper_pci_device = {
.name = "Phoenix 486 Jumper Readout (PCI machines)",
.internal_name = "phoenix_486_jumper_pci",
.flags = 0,
.local = 1,
.init = phoenix_486_jumper_init,
.close = phoenix_486_jumper_close,
.reset = phoenix_486_jumper_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/device/phoenix_486_jumper.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,133 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Debug device for assisting in unit testing.
* See doc/specifications/86box-unit-tester.md for more info.
* If modifying the protocol, you MUST modify the specification
* and increment the version number.
*
*
*
* Authors: GreaseMonkey, <thematrixeatsyou+86b@gmail.com>
*
*/
#include <stdarg.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/plat.h>
#include <86box/unittester.h>
#include <86box/video.h>
enum fsm1_value {
UT_FSM1_WAIT_8,
UT_FSM1_WAIT_6,
UT_FSM1_WAIT_B,
UT_FSM1_WAIT_o,
UT_FSM1_WAIT_x,
};
enum fsm2_value {
UT_FSM2_IDLE,
UT_FSM2_WAIT_IOBASE_0,
UT_FSM2_WAIT_IOBASE_1,
};
/* Status bit mask */
#define UT_STATUS_AWAITING_READ (1 << 0)
#define UT_STATUS_AWAITING_WRITE (1 << 1)
#define UT_STATUS_IDLE (1 << 2)
#define UT_STATUS_UNSUPPORTED_CMD (1 << 3)
/* Command list */
enum unittester_cmd {
UT_CMD_NOOP = 0x00,
UT_CMD_CAPTURE_SCREEN_SNAPSHOT = 0x01,
UT_CMD_READ_SCREEN_SNAPSHOT_RECTANGLE = 0x02,
UT_CMD_VERIFY_SCREEN_SNAPSHOT_RECTANGLE = 0x03,
UT_CMD_EXIT = 0x04,
};
struct unittester_state {
/* I/O port settings */
uint16_t trigger_port;
uint16_t iobase_port;
/* Trigger port finite state machines */
/* FSM1: "86Box" string detection */
enum fsm1_value fsm1;
/* FSM2: IOBASE port selection, once trigger is activated */
enum fsm2_value fsm2;
uint16_t fsm2_new_iobase;
/* Command and data handling state */
uint8_t status;
enum unittester_cmd cmd_id;
uint32_t write_offs;
uint32_t write_len;
uint64_t read_offs;
uint64_t read_len;
/* Screen snapshot state */
/* Monitor to take snapshot on */
uint8_t snap_monitor;
/* Main image width + height */
uint16_t snap_img_width;
uint16_t snap_img_height;
/* Fully overscanned image width + height */
uint16_t snap_overscan_width;
uint16_t snap_overscan_height;
/* Offset of actual image within overscanned area */
uint16_t snap_img_xoffs;
uint16_t snap_img_yoffs;
/* Command-specific state */
/* 0x02: Read Screen Snapshot Rectangle */
/* 0x03: Verify Screen Snapshot Rectangle */
uint16_t read_snap_width;
uint16_t read_snap_height;
int16_t read_snap_xoffs;
int16_t read_snap_yoffs;
uint32_t read_snap_crc;
/* 0x04: Exit */
uint8_t exit_code;
};
static struct unittester_state unittester;
static const struct unittester_state unittester_defaults = {
.trigger_port = 0x0080,
.iobase_port = 0xFFFF,
.fsm1 = UT_FSM1_WAIT_8,
.fsm2 = UT_FSM2_IDLE,
.status = UT_STATUS_IDLE,
.cmd_id = UT_CMD_NOOP,
};
static const device_config_t unittester_config[] = {
{ .name = "exit_enabled",
.description = "Enable 0x04 \"Exit 86Box\" command",
.type = CONFIG_BINARY,
.default_int = 1,
.default_string = "" },
{ .type = CONFIG_END }
};
/* Kept separate, as we will be reusing this object */
static bitmap_t *unittester_screen_buffer = NULL;
static bool unittester_exit_enabled = true;
#ifdef ENABLE_UNITTESTER_LOG
int unittester_do_log = ENABLE_UNITTESTER_LOG;
static void
unittester_log(const char *fmt, ...)
{
va_list ap;
if (unittester_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define unittester_log(fmt, ...)
#endif
static uint8_t
unittester_read_snap_rect_idx(uint64_t offs)
{
/* WARNING: If the width is somehow 0 and wasn't caught earlier, you'll probably get a divide by zero crash. */
uint32_t idx = (offs & 0x3);
int64_t x = (offs >> 2) % unittester.read_snap_width;
int64_t y = (offs >> 2) / unittester.read_snap_width;
x += unittester.read_snap_xoffs;
y += unittester.read_snap_yoffs;
if (x < 0 || y < 0 || x >= unittester.snap_overscan_width || y >= unittester.snap_overscan_height) {
/* Out of range! */
return (idx == 3 ? 0xFF : 0x00);
} else {
/* In range */
return (unittester_screen_buffer->line[y][x] & 0x00FFFFFF) >> (idx * 8);
}
}
static void
unittester_write(uint16_t port, uint8_t val, UNUSED(void *priv))
{
if (port == unittester.iobase_port + 0x00) {
/* Command port */
/* unittester_log("[UT] W %02X Command\n", val); */
unittester.write_offs = 0;
unittester.write_len = 0;
unittester.read_offs = 0;
unittester.read_len = 0;
switch (val) {
/* 0x00: No-op */
case UT_CMD_NOOP:
unittester.cmd_id = UT_CMD_NOOP;
unittester.status = UT_STATUS_IDLE;
break;
/* 0x01: Capture Screen Snapshot */
case UT_CMD_CAPTURE_SCREEN_SNAPSHOT:
unittester.cmd_id = UT_CMD_CAPTURE_SCREEN_SNAPSHOT;
unittester.status = UT_STATUS_AWAITING_WRITE;
unittester.write_len = 1;
break;
/* 0x02: Read Screen Snapshot Rectangle */
case UT_CMD_READ_SCREEN_SNAPSHOT_RECTANGLE:
unittester.cmd_id = UT_CMD_READ_SCREEN_SNAPSHOT_RECTANGLE;
unittester.status = UT_STATUS_AWAITING_WRITE;
unittester.write_len = 8;
break;
/* 0x03: Verify Screen Snapshot Rectangle */
case UT_CMD_VERIFY_SCREEN_SNAPSHOT_RECTANGLE:
unittester.cmd_id = UT_CMD_VERIFY_SCREEN_SNAPSHOT_RECTANGLE;
unittester.status = UT_STATUS_AWAITING_WRITE;
unittester.write_len = 8;
break;
/* 0x04: Exit */
case UT_CMD_EXIT:
unittester.cmd_id = UT_CMD_EXIT;
unittester.status = UT_STATUS_AWAITING_WRITE;
unittester.write_len = 1;
break;
/* Unsupported command - terminate here */
default:
unittester.cmd_id = UT_CMD_NOOP;
unittester.status = UT_STATUS_IDLE | UT_STATUS_UNSUPPORTED_CMD;
break;
}
} else if (port == unittester.iobase_port + 0x01) {
/* Data port */
/* unittester_log("[UT] W %02X Data\n", val); */
/* Skip if not awaiting */
if ((unittester.status & UT_STATUS_AWAITING_WRITE) == 0)
return;
switch (unittester.cmd_id) {
case UT_CMD_EXIT:
switch (unittester.write_offs) {
case 0:
unittester.exit_code = val;
break;
default:
break;
}
break;
case UT_CMD_CAPTURE_SCREEN_SNAPSHOT:
switch (unittester.write_offs) {
case 0:
unittester.snap_monitor = val;
break;
default:
break;
}
break;
case UT_CMD_READ_SCREEN_SNAPSHOT_RECTANGLE:
case UT_CMD_VERIFY_SCREEN_SNAPSHOT_RECTANGLE:
switch (unittester.write_offs) {
case 0:
unittester.read_snap_width = (uint16_t) val;
break;
case 1:
unittester.read_snap_width |= ((uint16_t) val) << 8;
break;
case 2:
unittester.read_snap_height = (uint16_t) val;
break;
case 3:
unittester.read_snap_height |= ((uint16_t) val) << 8;
break;
case 4:
unittester.read_snap_xoffs = (uint16_t) val;
break;
case 5:
unittester.read_snap_xoffs |= ((uint16_t) val) << 8;
break;
case 6:
unittester.read_snap_yoffs = (uint16_t) val;
break;
case 7:
unittester.read_snap_yoffs |= ((uint16_t) val) << 8;
break;
default:
break;
}
break;
/* This should not be reachable, but just in case... */
default:
break;
}
/* Advance write buffer */
unittester.write_offs += 1;
if (unittester.write_offs >= unittester.write_len) {
unittester.status &= ~UT_STATUS_AWAITING_WRITE;
/* Determine what we're doing here based on the command. */
switch (unittester.cmd_id) {
case UT_CMD_EXIT:
unittester_log("[UT] Exit received - code = %02X\n", unittester.exit_code);
/* CHECK: Do we actually exit? */
if (unittester_exit_enabled) {
/* Yes - call exit! */
/* Clamp exit code */
if (unittester.exit_code > 0x7F)
unittester.exit_code = 0x7F;
/* Exit somewhat quickly! */
unittester_log("[UT] Exit enabled, exiting with code %02X\n", unittester.exit_code);
exit(unittester.exit_code);
} else {
/* No - report successful command completion and continue program execution */
unittester_log("[UT] Exit disabled, continuing execution\n");
}
unittester.cmd_id = UT_CMD_NOOP;
unittester.status = UT_STATUS_IDLE;
break;
case UT_CMD_CAPTURE_SCREEN_SNAPSHOT:
/* Recompute screen */
unittester.snap_img_width = 0;
unittester.snap_img_height = 0;
unittester.snap_img_xoffs = 0;
unittester.snap_img_yoffs = 0;
unittester.snap_overscan_width = 0;
unittester.snap_overscan_height = 0;
if (unittester.snap_monitor < 0x01 || (unittester.snap_monitor - 1) > MONITORS_NUM) {
/* No monitor here - clear snapshot */
unittester.snap_monitor = 0x00;
} else if (video_get_type_monitor(unittester.snap_monitor - 1) == VIDEO_FLAG_TYPE_NONE) {
/* Monitor disabled - clear snapshot */
unittester.snap_monitor = 0x00;
} else {
/* Compute bounds for snapshot */
const monitor_t *m = &monitors[unittester.snap_monitor - 1];
unittester.snap_img_width = m->mon_xsize;
unittester.snap_img_height = m->mon_ysize;
unittester.snap_overscan_width = m->mon_xsize + m->mon_overscan_x;
unittester.snap_overscan_height = m->mon_ysize + m->mon_overscan_y;
unittester.snap_img_xoffs = (m->mon_overscan_x >> 1);
unittester.snap_img_yoffs = (m->mon_overscan_y >> 1);
/* Take snapshot */
for (size_t y = 0; y < unittester.snap_overscan_height; y++) {
for (size_t x = 0; x < unittester.snap_overscan_width; x++) {
unittester_screen_buffer->line[y][x] = m->target_buffer->line[y][x];
}
}
}
/* We have 12 bytes to read. */
unittester_log("[UT] Screen snapshot - image %d x %d @ (%d, %d) in overscan %d x %d\n",
unittester.snap_img_width,
unittester.snap_img_height,
unittester.snap_img_xoffs,
unittester.snap_img_yoffs,
unittester.snap_overscan_width,
unittester.snap_overscan_height);
unittester.status = UT_STATUS_AWAITING_READ;
unittester.read_len = 12;
break;
case UT_CMD_READ_SCREEN_SNAPSHOT_RECTANGLE:
case UT_CMD_VERIFY_SCREEN_SNAPSHOT_RECTANGLE:
/* Offset the X,Y offsets by the overscan offsets. */
unittester.read_snap_xoffs += (int16_t) unittester.snap_img_xoffs;
unittester.read_snap_yoffs += (int16_t) unittester.snap_img_yoffs;
/* NOTE: Width * Height * 4 can potentially exceed a 32-bit number.
So, we use 64-bit numbers instead.
In practice, this will only happen if someone decides to request e.g. a 65535 x 65535 image,
of which most of the pixels will be out of range anyway.
*/
unittester.read_len = ((uint64_t) unittester.read_snap_width) * ((uint64_t) unittester.read_snap_height) * 4;
unittester.read_snap_crc = 0xFFFFFFFF;
unittester_log("[UT] Screen rectangle analysis - %d x %d @ (%d, %d)\n",
unittester.read_snap_width,
unittester.read_snap_height,
unittester.read_snap_xoffs - (int16_t) unittester.snap_img_xoffs,
unittester.read_snap_yoffs - (int16_t) unittester.snap_img_yoffs);
if (unittester.cmd_id == UT_CMD_VERIFY_SCREEN_SNAPSHOT_RECTANGLE) {
/* Read everything and compute CRC */
uint32_t crc = 0xFFFFFFFF;
for (uint64_t i = 0; i < unittester.read_len; i++) {
crc ^= 0xFF & (uint32_t) unittester_read_snap_rect_idx(i);
/* Use some bit twiddling until we have a table-based fast CRC-32 implementation */
for (uint32_t j = 0; j < 8; j++) {
crc = (crc >> 1) ^ ((-(crc & 0x1)) & 0xEDB88320);
}
}
unittester.read_snap_crc = crc ^ 0xFFFFFFFF;
unittester_log("[UT] Screen rectangle analysis CRC = %08X\n",
unittester.read_snap_crc);
/* Set actual read length for CRC result */
unittester.read_len = 4;
unittester.status = UT_STATUS_AWAITING_READ;
} else {
/* Do we have anything to read? */
if (unittester.read_len >= 1) {
/* Yes - start reads! */
unittester.status = UT_STATUS_AWAITING_READ;
} else {
/* No - stop here. */
unittester.cmd_id = UT_CMD_NOOP;
unittester.status = UT_STATUS_IDLE;
}
}
break;
default:
/* Nothing to write? Stop here. */
unittester.cmd_id = UT_CMD_NOOP;
unittester.status = UT_STATUS_IDLE;
break;
}
}
} else {
/* Not handled here - possibly open bus! */
}
}
static uint8_t
unittester_read(uint16_t port, UNUSED(void *priv))
{
uint8_t outval = 0xFF;
if (port == unittester.iobase_port + 0x00) {
/* Status port */
/* unittester_log("[UT] R -- Status = %02X\n", unittester.status); */
return unittester.status;
} else if (port == unittester.iobase_port + 0x01) {
/* Data port */
/* unittester_log("[UT] R -- Data\n"); */
/* Skip if not awaiting */
if ((unittester.status & UT_STATUS_AWAITING_READ) == 0)
return 0xFF;
switch (unittester.cmd_id) {
case UT_CMD_CAPTURE_SCREEN_SNAPSHOT:
switch (unittester.read_offs) {
case 0:
outval = (uint8_t) (unittester.snap_img_width);
break;
case 1:
outval = (uint8_t) (unittester.snap_img_width >> 8);
break;
case 2:
outval = (uint8_t) (unittester.snap_img_height);
break;
case 3:
outval = (uint8_t) (unittester.snap_img_height >> 8);
break;
case 4:
outval = (uint8_t) (unittester.snap_overscan_width);
break;
case 5:
outval = (uint8_t) (unittester.snap_overscan_width >> 8);
break;
case 6:
outval = (uint8_t) (unittester.snap_overscan_height);
break;
case 7:
outval = (uint8_t) (unittester.snap_overscan_height >> 8);
break;
case 8:
outval = (uint8_t) (unittester.snap_img_xoffs);
break;
case 9:
outval = (uint8_t) (unittester.snap_img_xoffs >> 8);
break;
case 10:
outval = (uint8_t) (unittester.snap_img_yoffs);
break;
case 11:
outval = (uint8_t) (unittester.snap_img_yoffs >> 8);
break;
default:
break;
}
break;
case UT_CMD_READ_SCREEN_SNAPSHOT_RECTANGLE:
outval = unittester_read_snap_rect_idx(unittester.read_offs);
break;
case UT_CMD_VERIFY_SCREEN_SNAPSHOT_RECTANGLE:
outval = (uint8_t) (unittester.read_snap_crc >> (8 * unittester.read_offs));
break;
/* This should not be reachable, but just in case... */
default:
break;
}
/* Advance read buffer */
unittester.read_offs += 1;
if (unittester.read_offs >= unittester.read_len) {
/* Once fully read, we stop here. */
unittester.cmd_id = UT_CMD_NOOP;
unittester.status = UT_STATUS_IDLE;
}
return outval;
} else {
/* Not handled here - possibly open bus! */
return 0xFF;
}
}
static void
unittester_trigger_write(UNUSED(uint16_t port), uint8_t val, UNUSED(void *priv))
{
/* This one gets quite spammy. */
/* unittester_log("[UT] Trigger value %02X -> FSM1 = %02X, FSM2 = %02X, IOBASE = %04X\n", val, unittester.fsm1, unittester.fsm2, unittester.iobase_port); */
/* Update FSM2 */
switch (unittester.fsm2) {
/* IDLE: Do nothing - FSM1 will put us in the right state. */
case UT_FSM2_IDLE:
unittester.fsm2 = UT_FSM2_IDLE;
break;
/* WAIT IOBASE 0: Set low byte of temporary IOBASE. */
case UT_FSM2_WAIT_IOBASE_0:
unittester.fsm2_new_iobase = ((uint16_t) val);
unittester.fsm2 = UT_FSM2_WAIT_IOBASE_1;
break;
/* WAIT IOBASE 0: Set high byte of temporary IOBASE and commit to the real IOBASE. */
case UT_FSM2_WAIT_IOBASE_1:
unittester.fsm2_new_iobase |= ((uint16_t) val) << 8;
unittester_log("[UT] Remapping IOBASE: %04X -> %04X\n", unittester.iobase_port, unittester.fsm2_new_iobase);
/* Unmap old IOBASE */
if (unittester.iobase_port != 0xFFFF)
io_removehandler(unittester.iobase_port, 2, unittester_read, NULL, NULL, unittester_write, NULL, NULL, NULL);
unittester.iobase_port = 0xFFFF;
/* Map new IOBASE */
unittester.iobase_port = unittester.fsm2_new_iobase;
if (unittester.iobase_port != 0xFFFF)
io_sethandler(unittester.iobase_port, 2, unittester_read, NULL, NULL, unittester_write, NULL, NULL, NULL);
/* Reset FSM2 to IDLE */
unittester.fsm2 = UT_FSM2_IDLE;
break;
}
/* Update FSM1 */
switch (val) {
case '8':
unittester.fsm1 = UT_FSM1_WAIT_6;
break;
case '6':
if (unittester.fsm1 == UT_FSM1_WAIT_6)
unittester.fsm1 = UT_FSM1_WAIT_B;
else
unittester.fsm1 = UT_FSM1_WAIT_8;
break;
case 'B':
if (unittester.fsm1 == UT_FSM1_WAIT_B)
unittester.fsm1 = UT_FSM1_WAIT_o;
else
unittester.fsm1 = UT_FSM1_WAIT_8;
break;
case 'o':
if (unittester.fsm1 == UT_FSM1_WAIT_o)
unittester.fsm1 = UT_FSM1_WAIT_x;
else
unittester.fsm1 = UT_FSM1_WAIT_8;
break;
case 'x':
if (unittester.fsm1 == UT_FSM1_WAIT_x) {
unittester_log("[UT] Config activated, awaiting new IOBASE\n");
unittester.fsm2 = UT_FSM2_WAIT_IOBASE_0;
}
unittester.fsm1 = UT_FSM1_WAIT_8;
break;
default:
unittester.fsm1 = UT_FSM1_WAIT_8;
break;
}
}
static void *
unittester_init(UNUSED(const device_t *info))
{
unittester = (struct unittester_state) unittester_defaults;
unittester_exit_enabled = !!device_get_config_int("exit_enabled");
if (unittester_screen_buffer == NULL)
unittester_screen_buffer = create_bitmap(2048, 2048);
io_sethandler(unittester.trigger_port, 1, NULL, NULL, NULL, unittester_trigger_write, NULL, NULL, NULL);
unittester_log("[UT] 86Box Unit Tester initialised\n");
return &unittester; /* Dummy non-NULL value */
}
static void
unittester_close(UNUSED(void *priv))
{
io_removehandler(unittester.trigger_port, 1, NULL, NULL, NULL, unittester_trigger_write, NULL, NULL, NULL);
if (unittester.iobase_port != 0xFFFF)
io_removehandler(unittester.iobase_port, 2, unittester_read, NULL, NULL, unittester_write, NULL, NULL, NULL);
unittester.iobase_port = 0xFFFF;
if (unittester_screen_buffer != NULL) {
destroy_bitmap(unittester_screen_buffer);
unittester_screen_buffer = NULL;
}
unittester_log("[UT] 86Box Unit Tester closed\n");
}
const device_t unittester_device = {
.name = "86Box Unit Tester",
.internal_name = "unittester",
.flags = DEVICE_ISA,
.local = 0,
.init = unittester_init,
.close = unittester_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = unittester_config,
};
``` | /content/code_sandbox/src/device/unittester.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,633 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Common driver module for MOUSE devices.
*
* TODO: Add the Genius bus- and serial mouse.
* Remove the '3-button' flag from mouse types.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <math.h>
#include <stdarg.h>
#include <stdatomic.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/gdbstub.h>
#include <86box/mouse.h>
#include <86box/video.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
typedef struct mouse_t {
const device_t *device;
} mouse_t;
int mouse_type = 0;
int mouse_input_mode;
int mouse_timed = 1;
int mouse_tablet_in_proximity = 0;
int tablet_tool_type = 1; /* 0 = Puck/Cursor, 1 = Pen */
double mouse_x_abs;
double mouse_y_abs;
double mouse_sensitivity = 1.0;
pc_timer_t mouse_timer; /* mouse event timer */
static const device_t mouse_none_device = {
.name = "None",
.internal_name = "none",
.flags = 0,
.local = MOUSE_TYPE_NONE,
.init = NULL,
.close = NULL,
.reset = NULL,
{ .poll = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
static const device_t mouse_internal_device = {
.name = "Internal",
.internal_name = "internal",
.flags = 0,
.local = MOUSE_TYPE_INTERNAL,
.init = NULL,
.close = NULL,
.reset = NULL,
{ .poll = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
static mouse_t mouse_devices[] = {
// clang-format off
{ &mouse_none_device },
{ &mouse_internal_device },
{ &mouse_logibus_device },
{ &mouse_msinport_device },
#ifdef USE_GENIBUS
{ &mouse_genibus_device },
#endif
{ &mouse_mssystems_device },
{ &mouse_msserial_device },
{ &mouse_ltserial_device },
{ &mouse_ps2_device },
#ifdef USE_WACOM
{ &mouse_wacom_device },
{ &mouse_wacom_artpad_device },
#endif
{ &mouse_mtouch_device },
{ NULL }
// clang-format on
};
static _Atomic double mouse_x;
static _Atomic double mouse_y;
static atomic_int mouse_z;
static atomic_int mouse_buttons;
static int mouse_delta_b;
static int mouse_old_b;
static const device_t *mouse_curr;
static void *mouse_priv;
static int mouse_nbut;
static int mouse_raw;
static int (*mouse_dev_poll)(void *priv);
static void (*mouse_poll_ex)(void) = NULL;
static double sample_rate = 200.0;
#ifdef ENABLE_MOUSE_LOG
int mouse_do_log = ENABLE_MOUSE_LOG;
static void
mouse_log(const char *fmt, ...)
{
va_list ap;
if (mouse_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define mouse_log(fmt, ...)
#endif
void
mouse_clear_x(void)
{
mouse_x = 0.0;
}
void
mouse_clear_y(void)
{
mouse_y = 0.0;
}
void
mouse_clear_coords(void)
{
mouse_clear_x();
mouse_clear_y();
mouse_z = 0;
}
void
mouse_clear_buttons(void)
{
mouse_buttons = 0x00;
mouse_old_b = 0x00;
mouse_delta_b = 0x00;
}
static double
mouse_scale_coord_x(double x, int mul)
{
double ratio = 1.0;
if (!mouse_raw)
ratio = ((double) monitors[0].mon_unscaled_size_x) / monitors[0].mon_res_x;
if (mul)
x *= ratio;
else
x /= ratio;
return x;
}
static double
mouse_scale_coord_y(double y, int mul)
{
double ratio = 1.0;
if (!mouse_raw)
ratio = ((double) monitors[0].mon_efscrnsz_y) / monitors[0].mon_res_y;
if (mul)
y *= ratio;
else
y /= ratio;
return y;
}
void
mouse_subtract_x(int *delta_x, int *o_x, int min, int max, int abs)
{
double real_x = atomic_load(&mouse_x);
double smax_x;
double rsmin_x;
double smin_x;
int ds_x;
int scaled_x;
rsmin_x = mouse_scale_coord_x(min, 0);
if (abs) {
smax_x = mouse_scale_coord_x(max, 0) + ABS(rsmin_x);
max += ABSD(min);
real_x += rsmin_x;
smin_x = 0;
} else {
smax_x = mouse_scale_coord_x(max, 0);
smin_x = rsmin_x;
}
smax_x = floor(smax_x);
smin_x = ceil(smin_x);
/* Default the X overflow to 1. */
if (o_x != NULL)
*o_x = 1;
ds_x = mouse_scale_coord_x(real_x, 1);
if (ds_x >= 0.0)
scaled_x = (int) floor(mouse_scale_coord_x(real_x, 1));
else
scaled_x = (int) ceil(mouse_scale_coord_x(real_x, 1));
if (real_x > smax_x) {
if (abs) {
*delta_x = scaled_x;
real_x -= mouse_scale_coord_x((double) scaled_x, 0);
} else {
*delta_x = max;
real_x -= smax_x;
}
} else if (real_x < smin_x) {
if (abs) {
*delta_x = scaled_x;
real_x -= mouse_scale_coord_x((double) scaled_x, 0);
} else {
*delta_x = min;
real_x += ABSD(smin_x);
}
} else {
*delta_x = scaled_x;
real_x -= mouse_scale_coord_x((double) scaled_x, 0);
if (o_x != NULL)
*o_x = 0;
}
if (abs)
real_x -= rsmin_x;
atomic_store(&mouse_x, real_x);
}
/* It appears all host platforms give us y in the Microsoft format
(positive to the south), so for all non-Microsoft report formsts,
we have to invert that. */
void
mouse_subtract_y(int *delta_y, int *o_y, int min, int max, int invert, int abs)
{
double real_y = atomic_load(&mouse_y);
double smax_y;
double rsmin_y;
double smin_y;
int ds_y;
int scaled_y;
if (invert)
real_y = -real_y;
rsmin_y = mouse_scale_coord_y(min, 0);
if (abs) {
smax_y = mouse_scale_coord_y(max, 0) + ABS(rsmin_y);
max += ABSD(min);
real_y += rsmin_y;
smin_y = 0;
} else {
smax_y = mouse_scale_coord_y(max, 0);
smin_y = rsmin_y;
}
smax_y = floor(smax_y);
smin_y = ceil(smin_y);
/* Default Y overflow to 1. */
if (o_y != NULL)
*o_y = 1;
ds_y = mouse_scale_coord_x(real_y, 1);
if (ds_y >= 0.0)
scaled_y = (int) floor(mouse_scale_coord_x(real_y, 1));
else
scaled_y = (int) ceil(mouse_scale_coord_x(real_y, 1));
if (real_y > smax_y) {
if (abs) {
*delta_y = scaled_y;
real_y -= mouse_scale_coord_y((double) scaled_y, 0);
} else {
*delta_y = max;
real_y -= smax_y;
}
} else if (real_y < smin_y) {
if (abs) {
*delta_y = scaled_y;
real_y -= mouse_scale_coord_y((double) scaled_y, 0);
} else {
*delta_y = min;
real_y += ABSD(smin_y);
}
} else {
*delta_y = scaled_y;
real_y -= mouse_scale_coord_y((double) scaled_y, 0);
if (o_y != NULL)
*o_y = 0;
}
if (abs)
real_y -= rsmin_y;
if (invert)
real_y = -real_y;
atomic_store(&mouse_y, real_y);
}
/* It appears all host platforms give us y in the Microsoft format
(positive to the south), so for all non-Microsoft report formsts,
we have to invenrt that. */
void
mouse_subtract_coords(int *delta_x, int *delta_y, int *o_x, int *o_y,
int min, int max, int invert, int abs)
{
mouse_subtract_x(delta_x, o_x, min, max, abs);
mouse_subtract_y(delta_y, o_y, min, max, invert, abs);
}
int
mouse_wheel_moved(void)
{
int ret = !!(atomic_load(&mouse_z));
return ret;
}
int
mouse_moved(void)
{
int moved_x = !!((int) floor(ABSD(mouse_scale_coord_x(atomic_load(&mouse_x), 1))));
int moved_y = !!((int) floor(ABSD(mouse_scale_coord_y(atomic_load(&mouse_y), 1))));
/* Convert them to integer so we treat < 1.0 and > -1.0 as 0. */
int ret = (moved_x || moved_y);
return ret;
}
int
mouse_state_changed(void)
{
int b;
int b_mask = (1 << mouse_nbut) - 1;
int wheel = (mouse_nbut >= 4);
int ret;
b = atomic_load(&mouse_buttons);
mouse_delta_b = (b ^ mouse_old_b);
mouse_old_b = b;
ret = mouse_moved() || ((atomic_load(&mouse_z) != 0) && wheel) || (mouse_delta_b & b_mask);
return ret;
}
int
mouse_mbut_changed(void)
{
return !!(mouse_delta_b & 0x04);
}
static void
mouse_timer_poll(UNUSED(void *priv))
{
/* Poll at the specified sample rate. */
timer_on_auto(&mouse_timer, 1000000.0 / sample_rate);
#ifdef USE_GDBSTUB /* avoid a KBC FIFO overflow when CPU emulation is stalled */
if (gdbstub_step == GDBSTUB_EXEC) {
#endif
if (mouse_timed)
mouse_process();
#ifdef USE_GDBSTUB /* avoid a KBC FIFO overflow when CPU emulation is stalled */
}
#endif
}
static void
atomic_double_add(_Atomic double *var, double val)
{
double temp = atomic_load(var);
temp += val;
atomic_store(var, temp);
}
void
mouse_scale_fx(double x)
{
atomic_double_add(&mouse_x, ((double) x) * mouse_sensitivity);
}
void
mouse_scale_fy(double y)
{
atomic_double_add(&mouse_y, ((double) y) * mouse_sensitivity);
}
void
mouse_scale_x(int x)
{
atomic_double_add(&mouse_x, ((double) x) * mouse_sensitivity);
}
void
mouse_scale_y(int y)
{
atomic_double_add(&mouse_y, ((double) y) * mouse_sensitivity);
}
void
mouse_scalef(double x, double y)
{
mouse_scale_fx(x);
mouse_scale_fy(y);
}
void
mouse_scale(int x, int y)
{
mouse_scale_x(x);
mouse_scale_y(y);
}
void
mouse_scale_axis(int axis, int val)
{
if (axis == 1)
mouse_scale_y(val);
else if (axis == 0)
mouse_scale_x(val);
}
void
mouse_set_z(int z)
{
atomic_fetch_add(&mouse_z, z);
}
void
mouse_clear_z(void)
{
atomic_store(&mouse_z, 0);
}
void
mouse_subtract_z(int *delta_z, int min, int max, int invert)
{
int z = atomic_load(&mouse_z);
int real_z = invert ? -z : z;
if (mouse_z > max) {
*delta_z = max;
real_z -= max;
} else if (mouse_z < min) {
*delta_z = min;
real_z += ABS(min);
} else {
*delta_z = real_z;
real_z = 0;
}
atomic_store(&mouse_z, invert ? -real_z : real_z);
}
void
mouse_set_buttons_ex(int b)
{
atomic_store(&mouse_buttons, b);
}
int
mouse_get_buttons_ex(void)
{
return atomic_load(&mouse_buttons);
}
void
mouse_set_sample_rate(double new_rate)
{
mouse_timed = (new_rate > 0.0);
timer_stop(&mouse_timer);
sample_rate = new_rate;
if (mouse_timed)
timer_on_auto(&mouse_timer, 1000000.0 / sample_rate);
}
/* Callback from the hardware driver. */
void
mouse_set_buttons(int buttons)
{
mouse_nbut = buttons;
}
void
mouse_get_abs_coords(double *x_abs, double *y_abs)
{
*x_abs = mouse_x_abs;
*y_abs = mouse_y_abs;
}
void
mouse_process(void)
{
if (mouse_curr == NULL)
return;
if ((mouse_input_mode >= 1) && mouse_poll_ex)
mouse_poll_ex();
else if ((mouse_input_mode == 0) && ((mouse_dev_poll != NULL) || (mouse_curr->poll != NULL))) {
if (mouse_curr->poll != NULL)
mouse_curr->poll(mouse_priv);
else
mouse_dev_poll(mouse_priv);
}
}
void
mouse_set_poll_ex(void (*poll_ex)(void))
{
mouse_poll_ex = poll_ex;
}
void
mouse_set_poll(int (*func)(void *), void *arg)
{
if (mouse_type != MOUSE_TYPE_INTERNAL)
return;
mouse_dev_poll = func;
mouse_priv = arg;
}
const char *
mouse_get_name(int mouse)
{
return (mouse_devices[mouse].device->name);
}
const char *
mouse_get_internal_name(int mouse)
{
return device_get_internal_name(mouse_devices[mouse].device);
}
int
mouse_get_from_internal_name(char *s)
{
int c = 0;
while (mouse_devices[c].device != NULL) {
if (!strcmp((char *) mouse_devices[c].device->internal_name, s))
return c;
c++;
}
return 0;
}
int
mouse_has_config(int mouse)
{
if (mouse_devices[mouse].device == NULL)
return 0;
return (mouse_devices[mouse].device->config ? 1 : 0);
}
const device_t *
mouse_get_device(int mouse)
{
return (mouse_devices[mouse].device);
}
int
mouse_get_buttons(void)
{
return mouse_nbut;
}
/* Return number of MOUSE types we know about. */
int
mouse_get_ndev(void)
{
return ((sizeof(mouse_devices) / sizeof(mouse_t)) - 1);
}
void
mouse_set_raw(int raw)
{
mouse_raw = raw;
}
void
mouse_reset(void)
{
if (mouse_curr != NULL)
return; /* Mouse already initialized. */
mouse_log("MOUSE: reset(type=%d, '%s')\n",
mouse_type, mouse_devices[mouse_type].device->name);
/* Clear local data. */
mouse_clear_coords();
mouse_clear_buttons();
mouse_input_mode = 0;
mouse_timed = 1;
/* If no mouse configured, we're done. */
if (mouse_type == 0)
return;
timer_add(&mouse_timer, mouse_timer_poll, NULL, 0);
/* Poll at 100 Hz, the default of a PS/2 mouse. */
sample_rate = 100.0;
timer_on_auto(&mouse_timer, 1000000.0 / sample_rate);
mouse_curr = mouse_devices[mouse_type].device;
if ((mouse_type > 1) && (mouse_curr != NULL))
mouse_priv = device_add(mouse_curr);
}
void
mouse_close(void)
{
if (mouse_curr == NULL)
return;
mouse_curr = NULL;
mouse_priv = NULL;
mouse_nbut = 0;
mouse_dev_poll = NULL;
timer_stop(&mouse_timer);
}
/* Initialize the mouse module. */
void
mouse_init(void)
{
/* Initialize local data. */
mouse_clear_coords();
mouse_clear_buttons();
mouse_type = MOUSE_TYPE_NONE;
mouse_curr = NULL;
mouse_priv = NULL;
mouse_nbut = 0;
mouse_dev_poll = NULL;
}
``` | /content/code_sandbox/src/device/mouse.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,961 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* HASP parallel port copy protection dongle emulation.
*
* Based on the MAME driver for Savage Quest. This incomplete
* emulation is enough to satisfy that game, but not Aladdin's
* DiagnostiX utility.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
* Peter Ferrie
*
*/
#include <inttypes.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/lpt.h>
#include <86box/device.h>
#define HASP_BYTEARRAY(...) \
{ \
__VA_ARGS__ \
}
#define HASP_TYPE(type, password_arr, prodinfo_arr) [type] = { \
.password = (const uint8_t[]) password_arr, \
.prodinfo = (const uint8_t[]) prodinfo_arr, \
.password_size = sizeof((uint8_t[]) password_arr), \
.prodinfo_size = sizeof((uint8_t[]) prodinfo_arr) \
},
enum {
HASP_STATE_NONE = 0,
HASP_STATE_PASSWORD_BEGIN,
HASP_STATE_PASSWORD_END,
HASP_STATE_READ
};
enum {
HASP_TYPE_SAVQUEST = 0
};
typedef struct hasp_type_t {
const uint8_t *password;
const uint8_t *prodinfo;
const uint8_t password_size;
const uint8_t prodinfo_size;
} hasp_type_t;
typedef struct
{
void *lpt;
const hasp_type_t *type;
int index;
int state;
int passindex;
int passmode;
int prodindex;
uint8_t tmppass[0x29];
uint8_t status;
} hasp_t;
static const hasp_type_t hasp_types[] = {
HASP_TYPE(HASP_TYPE_SAVQUEST,
HASP_BYTEARRAY(0xc3, 0xd9, 0xd3, 0xfb, 0x9d, 0x89, 0xb9, 0xa1, 0xb3, 0xc1, 0xf1, 0xcd, 0xdf, 0x9d),
HASP_BYTEARRAY(0x51, 0x4c, 0x52, 0x4d, 0x53, 0x4e, 0x53, 0x4e, 0x53, 0x49, 0x53, 0x48, 0x53, 0x4b, 0x53, 0x4a,
0x53, 0x43, 0x53, 0x45, 0x52, 0x46, 0x53, 0x43, 0x53, 0x41, 0xac, 0x40, 0x53, 0xbc, 0x53, 0x42,
0x53, 0x57, 0x53, 0x5d, 0x52, 0x5e, 0x53, 0x5b, 0x53, 0x59, 0xac, 0x58, 0x53, 0xa4))
};
#ifdef ENABLE_HASP_LOG
int hasp_do_log = ENABLE_HASP_LOG;
static void
hasp_log(const char *fmt, ...)
{
va_list ap;
if (hasp_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define hasp_log(fmt, ...)
#endif
static void
hasp_write_data(uint8_t val, void *priv)
{
hasp_t *dev = (hasp_t *) priv;
hasp_log("HASP: write_data(%02X)\n", val);
switch (dev->index) {
case 0:
if (val == 0xc6)
dev->index++;
else
dev->index = 0;
break;
case 1:
if (val == 0xc7)
dev->index++;
else
dev->index = 0;
break;
case 2:
if (val == 0xc6) {
dev->index++;
} else {
dev->index = 0;
dev->state = HASP_STATE_NONE;
}
break;
case 3:
dev->index = 0;
if (val == 0x80) {
dev->state = HASP_STATE_PASSWORD_BEGIN;
dev->passindex = 0;
return;
}
break;
default:
break;
}
dev->status = 0;
if (dev->state == HASP_STATE_READ) {
/* different passwords cause different values to be returned
but there are really only two passwords of interest
passmode 2 is used to verify that the dongle is responding correctly */
if (dev->passmode == 2) {
switch (val) {
case 0x94:
case 0x9e:
case 0xa4:
case 0xb2:
case 0xbe:
case 0xd0:
return;
case 0x8a:
case 0x8e:
case 0xca:
case 0xd2:
case 0xe2:
case 0xf0:
case 0xfc:
/* someone with access to the actual dongle could dump the true values
I've never seen it so I just determined the relevant bits instead
from the disassembly of the software
some of the keys are verified explicitly, the others implicitly
I guessed the implicit ones with a bit of trial and error */
dev->status = 0x20;
return;
default:
break;
}
}
switch (val) {
/* in passmode 0, some values remain unknown: 8a, 8e (inconclusive), 94, 96, 9a, a4, b2, be, c4, d2, d4 (inconclusive), e2, ec, f8, fc
this is less of a concern since the contents seem to decrypt correctly */
case 0x88:
case 0x94:
case 0x98:
case 0x9c:
case 0x9e:
case 0xa0:
case 0xa4:
case 0xaa:
case 0xae:
case 0xb0:
case 0xb2:
case 0xbc:
case 0xbe:
case 0xc2:
case 0xc6:
case 0xc8:
case 0xce:
case 0xd0:
case 0xd6:
case 0xd8:
case 0xdc:
case 0xe0:
case 0xe6:
case 0xea:
case 0xee:
case 0xf2:
case 0xf6:
/* again, just the relevant bits instead of the true values */
dev->status = 0x20;
break;
default:
break;
}
} else if (dev->state == HASP_STATE_PASSWORD_END) {
if (val & 1) {
if ((dev->passmode == 1) && (val == 0x9d))
dev->passmode = 2;
dev->state = HASP_STATE_READ;
} else if (dev->passmode == 1) {
dev->tmppass[dev->passindex++] = val;
if (dev->passindex == sizeof(dev->tmppass)) {
if ((dev->tmppass[0] == 0x9c) && (dev->tmppass[1] == 0x9e)) {
int i = 2;
dev->prodindex = 0;
do {
dev->prodindex = (dev->prodindex << 1) + ((dev->tmppass[i] >> 6) & 1);
} while ((i += 3) < sizeof(dev->tmppass));
dev->prodindex = (dev->prodindex - 0xc08) << 4;
hasp_log("HASP: Password prodindex = %d\n", dev->prodindex);
if (dev->prodindex < (0x38 << 4))
dev->passmode = 3;
}
dev->state = HASP_STATE_READ;
}
}
} else if ((dev->state == HASP_STATE_PASSWORD_BEGIN) && (val & 1)) {
dev->tmppass[dev->passindex++] = val;
if (dev->passindex == dev->type->password_size) {
dev->state = HASP_STATE_PASSWORD_END;
dev->passindex = 0;
dev->passmode = (int) !memcmp(dev->tmppass, dev->type->password, dev->type->password_size);
hasp_log("HASP: Password comparison result = %d\n", dev->passmode);
}
}
}
static uint8_t
hasp_read_status(void *priv)
{
hasp_t *dev = (hasp_t *) priv;
if ((dev->state == HASP_STATE_READ) && (dev->passmode == 3)) {
/* passmode 3 is used to retrieve the product(s) information
it comes in two parts: header and product
the header has this format:
offset range purpose
00 01 header type
01 01-05 count of used product slots, must be 2
02 01-05 count of unused product slots
this is assumed to be 6-(count of used slots)
but it is not enforced here
however a total of 6 structures will be checked
03 01-02 unknown
04 01-46 country code
05-0f 00 reserved
the used product slots have this format:
(the unused product slots must be entirely zeroes)
00-01 0001-000a product ID, one must be 6, the other 0a
02 0001-0003 unknown but must be 0001
04 01-05 HASP plug country ID
05 01-02 unknown but must be 01
06 05 unknown
07-0a any unknown, not used
0b ff unknown
0c ff unknown
0d-0f 00 reserved
the read is performed by accessing an array of 16-bit big-endian values
and returning one bit at a time into bit 5 of the result
the 16-bit value is then XORed with 0x534d and the register index */
if (dev->prodindex <= (dev->type->prodinfo_size * 8))
dev->status = ((dev->type->prodinfo[(dev->prodindex - 1) >> 3] >> ((8 - dev->prodindex) & 7)) & 1) << 5; /* return defined info */
else
dev->status = (((0x534d ^ ((dev->prodindex - 1) >> 4)) >> ((16 - dev->prodindex) & 15)) & 1) << 5; /* then just alternate between the two key values */
hasp_log("HASP: Reading %02X from prodindex %d\n", dev->status, dev->prodindex);
dev->prodindex++;
}
hasp_log("HASP: read_status() = %02X\n", dev->status);
return dev->status;
}
static void *
hasp_init(void *lpt, int type)
{
hasp_t *dev = malloc(sizeof(hasp_t));
memset(dev, 0, sizeof(hasp_t));
hasp_log("HASP: init(%d)\n", type);
dev->lpt = lpt;
dev->type = &hasp_types[type];
dev->status = 0x80;
return dev;
}
static void *
hasp_init_savquest(void *lpt)
{
return hasp_init(lpt, HASP_TYPE_SAVQUEST);
}
static void
hasp_close(void *priv)
{
hasp_t *dev = (hasp_t *) priv;
hasp_log("HASP: close()\n");
free(dev);
}
const lpt_device_t lpt_hasp_savquest_device = {
.name = "Protection Dongle for Savage Quest",
.internal_name = "dongle_savquest",
.init = hasp_init_savquest,
.close = hasp_close,
.write_data = hasp_write_data,
.write_ctrl = NULL,
.read_data = NULL,
.read_status = hasp_read_status,
.read_ctrl = NULL
};
``` | /content/code_sandbox/src/device/hasp.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,009 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* NS8250/16450/16550 UART emulation.
*
* Now passes all the AMIDIAG tests.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/machine.h>
#include <86box/io.h>
#include <86box/pic.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/fifo.h>
#include <86box/serial.h>
#include <86box/mouse.h>
serial_port_t com_ports[SERIAL_MAX];
enum {
SERIAL_INT_LSR = 1,
SERIAL_INT_TIMEOUT = 2,
SERIAL_INT_RECEIVE = 4,
SERIAL_INT_TRANSMIT = 8,
SERIAL_INT_MSR = 16,
SERIAL_INT_RX_DMA_TC = 32,
SERIAL_INT_TX_DMA_TC = 64
};
void serial_update_ints(serial_t *dev);
static int next_inst = 0;
static serial_device_t serial_devices[SERIAL_MAX];
static void serial_xmit_d_empty_evt(void *priv);
#ifdef ENABLE_SERIAL_LOG
int serial_do_log = ENABLE_SERIAL_LOG;
static void
serial_log(const char *fmt, ...)
{
va_list ap;
if (serial_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define serial_log(fmt, ...)
#endif
void
serial_reset_port(serial_t *dev)
{
if (dev->type >= SERIAL_16550) {
if (dev->fifo_enabled)
fifo_reset_evt(dev->xmit_fifo);
else
fifo_reset(dev->xmit_fifo);
}
dev->lsr = 0x60; /* Mark that both THR/FIFO and TXSR are empty. */
dev->iir = dev->ier = dev->lcr = dev->fcr = 0;
dev->fifo_enabled = 0;
dev->baud_cycles = 0;
dev->out_new = 0xffff;
dev->txsr_empty = 1;
dev->thr_empty = 1;
serial_update_ints(dev);
dev->irq_state = 0;
}
void
serial_transmit_period(serial_t *dev)
{
double ddlab;
if (dev->dlab != 0x0000)
ddlab = (double) dev->dlab;
else
ddlab = 65536.0;
/* Bit period based on DLAB. */
dev->transmit_period = (16000000.0 * ddlab) / dev->clock_src;
if (dev->sd && dev->sd->transmit_period_callback)
dev->sd->transmit_period_callback(dev, dev->sd->priv, dev->transmit_period);
}
void
serial_do_irq(serial_t *dev, int set)
{
if (dev->irq != 0xff) {
if (set || (dev->irq_state != !!set))
picint_common(1 << dev->irq, !!(dev->type >= SERIAL_16450), set, &dev->irq_state);
if (dev->type < SERIAL_16450)
dev->irq_state = !!set;
}
}
void
serial_update_ints(serial_t *dev)
{
/* TODO: The IRQ priorities are 6 - we need to find a way to treat timeout and receive
as equal and still somehow distinguish them. */
uint8_t ier_map[7] = { 0x04, 0x01, 0x01, 0x02, 0x08, 0x40, 0x80 };
uint8_t iir_map[7] = { 0x06, 0x0c, 0x04, 0x02, 0x00, 0x0e, 0x0a };
dev->iir = (dev->iir & 0xf0) | 0x01;
for (uint8_t i = 0; i < 7; i++) {
if ((dev->ier & ier_map[i]) && (dev->int_status & (1 << i))) {
dev->iir = (dev->iir & 0xf0) | iir_map[i];
break;
}
}
serial_do_irq(dev, !(dev->iir & 0x01) && ((dev->mctrl & 8) || (dev->type == SERIAL_8250_PCJR)));
}
static void
serial_clear_timeout(serial_t *dev)
{
/* Disable timeout timer and clear timeout condition. */
timer_disable(&dev->timeout_timer);
dev->int_status &= ~SERIAL_INT_TIMEOUT;
serial_update_ints(dev);
}
static void
serial_receive_timer(void *priv)
{
serial_t *dev = (serial_t *) priv;
serial_log("serial_receive_timer()\n");
timer_on_auto(&dev->receive_timer, /* dev->bits * */ dev->transmit_period);
if (dev->fifo_enabled) {
/* FIFO mode. */
if (dev->out_new != 0xffff) {
/* We have received a byte into the RSR. */
/* Clear FIFO timeout. */
serial_clear_timeout(dev);
fifo_write_evt((uint8_t) (dev->out_new & 0xff), dev->rcvr_fifo);
dev->out_new = 0xffff;
#if 0
pclog("serial_receive_timer(): lsr = %02X, ier = %02X, iir = %02X, int_status = %02X\n",
dev->lsr, dev->ier, dev->iir, dev->int_status);
#endif
timer_on_auto(&dev->timeout_timer, 4.0 * dev->bits * dev->transmit_period);
}
} else {
/* Non-FIFO mode. */
if (dev->out_new != 0xffff) {
/* We have received a byte into the RSR. */
serial_log("Byte received: %04X\n", dev->out_new);
/* Indicate overrun. */
if (dev->lsr & 0x01)
dev->lsr |= 0x02;
dev->dat = (uint8_t) (dev->out_new & 0xff);
dev->out_new = 0xffff;
/* Raise Data Ready interrupt. */
dev->lsr |= 0x01;
dev->int_status |= SERIAL_INT_RECEIVE;
serial_update_ints(dev);
}
}
}
static void
write_fifo(serial_t *dev, uint8_t dat)
{
serial_log("write_fifo(%08X, %02X, %i, %i)\n", dev, dat,
(dev->type >= SERIAL_16550) && dev->fifo_enabled,
((dev->type >= SERIAL_16550) && dev->fifo_enabled) ?
fifo_get_count(dev->rcvr_fifo) : 0);
/* Do this here, because in non-FIFO mode, this is read directly. */
dev->out_new = (uint16_t) dat;
}
void
serial_write_fifo(serial_t *dev, uint8_t dat)
{
serial_log("serial_write_fifo(%08X, %02X, %i, %i)\n", dev, dat,
(dev->type >= SERIAL_16550) && dev->fifo_enabled,
((dev->type >= SERIAL_16550) && dev->fifo_enabled) ?
fifo_get_count(dev->rcvr_fifo) : 0);
if (!(dev->mctrl & 0x10))
write_fifo(dev, dat);
}
void
serial_transmit(serial_t *dev, uint8_t val)
{
if (dev->mctrl & 0x10)
write_fifo(dev, val);
else if (dev->sd->dev_write)
dev->sd->dev_write(dev, dev->sd->priv, val);
#ifdef ENABLE_SERIAL_CONSOLE
if ((val >= ' ' && val <= '~') || val == '\r' || val == '\n') {
fputc(val, stdout);
if (val == '\n')
fflush(stdout);
} else
fprintf(stdout, "[%02X]", val);
#endif
}
static void
serial_move_to_txsr(serial_t *dev)
{
dev->txsr_empty = 0;
if (dev->fifo_enabled)
dev->txsr = fifo_read_evt(dev->xmit_fifo);
else {
dev->txsr = dev->thr;
dev->thr = 0;
dev->thr_empty = 1;
serial_xmit_d_empty_evt(dev);
}
dev->lsr &= ~0x40;
serial_log("serial_move_to_txsr(): FIFO %sabled, FIFO pos = %i\n", dev->fifo_enabled ? "en" : "dis",
fifo_get_count(dev->xmit_fifo) & 0x0f);
if (!dev->fifo_enabled || (fifo_get_count(dev->xmit_fifo) == 0x0)) {
/* Update interrupts to signal THRE and that TXSR is no longer empty. */
serial_update_ints(dev);
}
if (dev->transmit_enabled & 2)
dev->baud_cycles++;
else
dev->baud_cycles = 0; /* If not moving while transmitting, reset BAUDOUT cycle count. */
if (!dev->fifo_enabled || (fifo_get_count(dev->xmit_fifo) == 0x0))
dev->transmit_enabled &= ~1; /* Stop moving. */
dev->transmit_enabled |= 2; /* Start transmitting. */
}
static void
serial_process_txsr(serial_t *dev)
{
serial_log("serial_process_txsr(): FIFO %sabled\n", dev->fifo_enabled ? "en" : "dis");
serial_transmit(dev, dev->txsr);
dev->txsr = 0;
dev->txsr_empty = 1;
serial_xmit_d_empty_evt(dev);
/* Reset BAUDOUT cycle count. */
dev->baud_cycles = 0;
/* If FIFO is enabled and there are bytes left to transmit,
continue with the FIFO, otherwise stop. */
if (dev->fifo_enabled && (fifo_get_count(dev->xmit_fifo) != 0x0))
dev->transmit_enabled |= 1;
/* Both FIFO/THR and TXSR are empty. */
else
dev->transmit_enabled &= ~2;
serial_update_ints(dev);
}
/* Transmit_enable flags:
Bit 0 = Do move if set;
Bit 1 = Do transmit if set. */
static void
serial_transmit_timer(void *priv)
{
serial_t *dev = (serial_t *) priv;
int delay = 8; /* STOP to THRE delay is 8 BAUDOUT cycles. */
if (dev->transmit_enabled & 3) {
if ((dev->transmit_enabled & 1) && (dev->transmit_enabled & 2))
delay = dev->data_bits; /* Delay by less if already transmitting. */
dev->baud_cycles++;
/* We have processed (total bits) BAUDOUT cycles, transmit the byte. */
if ((dev->baud_cycles == dev->bits) && (dev->transmit_enabled & 2))
serial_process_txsr(dev);
/* We have processed (data bits) BAUDOUT cycles. */
if ((dev->baud_cycles == delay) && (dev->transmit_enabled & 1))
serial_move_to_txsr(dev);
if (dev->transmit_enabled & 3)
timer_on_auto(&dev->transmit_timer, dev->transmit_period);
} else {
dev->baud_cycles = 0;
return;
}
}
static void
serial_timeout_timer(void *priv)
{
serial_t *dev = (serial_t *) priv;
serial_log("serial_timeout_timer()\n");
dev->lsr |= 0x01;
dev->int_status |= SERIAL_INT_TIMEOUT;
serial_update_ints(dev);
}
void
serial_device_timeout(void *priv)
{
serial_t *dev = (serial_t *) priv;
serial_log("serial_device_timeout()\n");
if (!dev->fifo_enabled) {
dev->lsr |= 0x10;
dev->int_status |= SERIAL_INT_LSR;
serial_update_ints(dev);
}
}
static void
serial_update_speed(serial_t *dev)
{
serial_log("serial_update_speed(%lf)\n", dev->transmit_period);
timer_on_auto(&dev->receive_timer, /* dev->bits * */ dev->transmit_period);
if (dev->transmit_enabled & 3)
timer_on_auto(&dev->transmit_timer, dev->transmit_period);
if (timer_is_on(&dev->timeout_timer))
timer_on_auto(&dev->timeout_timer, 4.0 * dev->bits * dev->transmit_period);
}
static void
serial_reset_fifo(serial_t *dev)
{
fifo_reset_evt(dev->xmit_fifo);
fifo_reset_evt(dev->rcvr_fifo);
serial_update_ints(dev);
}
void
serial_set_dsr(serial_t *dev, uint8_t enabled)
{
if (dev->mctrl & 0x10)
return;
dev->msr &= ~0x2;
dev->msr |= ((dev->msr & 0x20) ^ ((!!enabled) << 5)) >> 4;
dev->msr &= ~0x20;
dev->msr |= (!!enabled) << 5;
dev->msr_set &= ~0x20;
dev->msr_set |= (!!enabled) << 5;
if (dev->msr & 0x2) {
dev->int_status |= SERIAL_INT_MSR;
serial_update_ints(dev);
}
}
void
serial_set_cts(serial_t *dev, uint8_t enabled)
{
if (dev->mctrl & 0x10)
return;
dev->msr &= ~0x1;
dev->msr |= ((dev->msr & 0x10) ^ ((!!enabled) << 4)) >> 4;
dev->msr &= ~0x10;
dev->msr |= (!!enabled) << 4;
dev->msr_set &= ~0x10;
dev->msr_set |= (!!enabled) << 4;
if (dev->msr & 0x1) {
dev->int_status |= SERIAL_INT_MSR;
serial_update_ints(dev);
}
}
void
serial_set_dcd(serial_t *dev, uint8_t enabled)
{
if (dev->mctrl & 0x10)
return;
dev->msr &= ~0x8;
dev->msr |= ((dev->msr & 0x80) ^ ((!!enabled) << 7)) >> 4;
dev->msr &= ~0x80;
dev->msr |= (!!enabled) << 7;
dev->msr_set &= ~0x80;
dev->msr_set |= (!!enabled) << 7;
if (dev->msr & 0x8) {
dev->int_status |= SERIAL_INT_MSR;
serial_update_ints(dev);
}
}
void
serial_set_ri(serial_t *dev, uint8_t enabled)
{
uint8_t prev_state = !!(dev->msr & 0x40);
if (dev->mctrl & 0x10)
return;
dev->msr &= ~0x40;
dev->msr |= (!!enabled) << 6;
dev->msr_set &= ~0x40;
dev->msr_set |= (!!enabled) << 6;
if (prev_state == 0 && (!!enabled) == 1) {
dev->msr |= 0x4;
dev->int_status |= SERIAL_INT_MSR;
serial_update_ints(dev);
}
}
int
serial_get_ri(serial_t *dev)
{
return !!(dev->msr & (1 << 6));
}
void
serial_set_clock_src(serial_t *dev, double clock_src)
{
dev->clock_src = clock_src;
serial_transmit_period(dev);
serial_update_speed(dev);
}
void
serial_write(uint16_t addr, uint8_t val, void *priv)
{
serial_t *dev = (serial_t *) priv;
uint8_t new_msr;
uint8_t old;
serial_log("UART: [%04X:%08X] Write %02X to port %02X\n", CS, cpu_state.pc, val, addr);
cycles -= ISA_CYCLES(8);
switch (addr & 7) {
case 0:
if (dev->lcr & 0x80) {
dev->dlab = (dev->dlab & 0xff00) | val;
serial_transmit_period(dev);
serial_update_speed(dev);
return;
}
if (dev->fifo_enabled && (fifo_get_count(dev->xmit_fifo) < 16)) {
/* FIFO mode, begin transmitting. */
timer_on_auto(&dev->transmit_timer, dev->transmit_period);
dev->transmit_enabled |= 1; /* Start moving. */
fifo_write_evt(val, dev->xmit_fifo);
} else if (!dev->fifo_enabled) {
/* Indicate THR is no longer empty. */
dev->lsr &= 0x9f;
dev->int_status &= ~SERIAL_INT_TRANSMIT;
serial_update_ints(dev);
/* Non-FIFO mode, begin transmitting. */
timer_on_auto(&dev->transmit_timer, dev->transmit_period);
dev->transmit_enabled |= 1; /* Start moving. */
dev->thr = val;
dev->thr_empty = 0;
}
break;
case 1:
if (dev->lcr & 0x80) {
dev->dlab = (dev->dlab & 0x00ff) | (val << 8);
serial_transmit_period(dev);
serial_update_speed(dev);
return;
}
if ((val & 2) && (dev->lsr & 0x20))
dev->int_status |= SERIAL_INT_TRANSMIT;
dev->ier = val & 0xf;
serial_update_ints(dev);
break;
case 2:
if (dev->type >= SERIAL_16550) {
if ((val ^ dev->fcr) & 0x01)
serial_reset_fifo(dev);
dev->fcr = val & 0xf9;
dev->fifo_enabled = val & 0x01;
/* TODO: When switching modes, shouldn't we reset the LSR
based on the new conditions? */
if (!dev->fifo_enabled) {
fifo_reset(dev->xmit_fifo);
fifo_reset(dev->rcvr_fifo);
break;
}
if (val & 0x02) {
if (dev->fifo_enabled)
fifo_reset_evt(dev->rcvr_fifo);
else
fifo_reset(dev->rcvr_fifo);
}
if (val & 0x04) {
if (dev->fifo_enabled)
fifo_reset_evt(dev->xmit_fifo);
else
fifo_reset(dev->xmit_fifo);
}
switch ((val >> 6) & 0x03) {
case 0:
fifo_set_trigger_len(dev->rcvr_fifo, 1);
break;
case 1:
fifo_set_trigger_len(dev->rcvr_fifo, 4);
break;
case 2:
fifo_set_trigger_len(dev->rcvr_fifo, 8);
break;
case 3:
fifo_set_trigger_len(dev->rcvr_fifo, 14);
break;
default:
break;
}
fifo_set_trigger_len(dev->xmit_fifo, 16);
dev->out_new = 0xffff;
serial_log("FIFO now %sabled\n", dev->fifo_enabled ? "en" : "dis");
}
break;
case 3:
old = dev->lcr;
dev->lcr = val;
if ((old ^ val) & 0x3f) {
/* Data bits + start bit. */
dev->bits = ((dev->lcr & 0x03) + 5) + 1;
/* Stop bits. */
dev->bits++; /* First stop bit. */
if (dev->lcr & 0x04)
dev->bits++; /* Second stop bit. */
/* Parity bit. */
if (dev->lcr & 0x08)
dev->bits++;
serial_transmit_period(dev);
serial_update_speed(dev);
if (dev->sd && dev->sd->lcr_callback)
dev->sd->lcr_callback(dev, dev->sd->priv, dev->lcr);
}
break;
case 4:
if ((val & 2) && !(dev->mctrl & 2)) {
if (dev->sd && dev->sd->rcr_callback) {
serial_log("RTS toggle callback\n");
dev->sd->rcr_callback(dev, dev->sd->priv);
}
}
if (!(val & 8) && (dev->mctrl & 8))
serial_do_irq(dev, 0);
if ((val ^ dev->mctrl) & 0x10)
serial_reset_fifo(dev);
if (dev->sd && dev->sd->dtr_callback && (val ^ dev->mctrl) & 1)
dev->sd->dtr_callback(dev, val & 1, dev->sd->priv);
dev->mctrl = val & 0x1f;
if (val & 0x10) {
new_msr = (val & 0x0c) << 4;
new_msr |= (val & 0x02) ? 0x10 : 0;
new_msr |= (val & 0x01) ? 0x20 : 0;
if ((dev->msr ^ new_msr) & 0x10)
new_msr |= 0x01;
if ((dev->msr ^ new_msr) & 0x20)
new_msr |= 0x02;
if ((dev->msr ^ new_msr) & 0x80)
new_msr |= 0x08;
if ((dev->msr & 0x40) && !(new_msr & 0x40))
new_msr |= 0x04;
dev->msr = new_msr;
/* TODO: Why reset the FIFO's here?! */
fifo_reset(dev->xmit_fifo);
fifo_reset(dev->rcvr_fifo);
}
break;
case 5:
dev->lsr = (dev->lsr & 0xe0) | (val & 0x1f);
if (dev->lsr & 0x01)
dev->int_status |= SERIAL_INT_RECEIVE;
if (dev->lsr & 0x1e)
dev->int_status |= SERIAL_INT_LSR;
if (dev->lsr & 0x20)
dev->int_status |= SERIAL_INT_TRANSMIT;
serial_update_ints(dev);
break;
case 6:
#if 0
dev->msr = (val & 0xf0) | (dev->msr & 0x0f);
dev->msr = val;
#endif
/* The actual condition bits of the MSR are read-only, but the delta bits are
undocumentedly writable, and the PCjr BIOS uses them to raise MSR interrupts. */
dev->msr = (dev->msr & 0xf0) | (val & 0x0f);
if (dev->msr & 0x0f)
dev->int_status |= SERIAL_INT_MSR;
serial_update_ints(dev);
break;
case 7:
if (dev->type >= SERIAL_16450)
dev->scratch = val;
break;
default:
break;
}
}
uint8_t
serial_read(uint16_t addr, void *priv)
{
serial_t *dev = (serial_t *) priv;
uint8_t ret = 0;
cycles -= ISA_CYCLES(8);
switch (addr & 7) {
case 0:
if (dev->lcr & 0x80) {
ret = dev->dlab & 0xff;
break;
}
if (dev->fifo_enabled) {
/* FIFO mode. */
serial_clear_timeout(dev);
ret = fifo_read_evt(dev->rcvr_fifo);
if (dev->lsr & 0x01)
timer_on_auto(&dev->timeout_timer, 4.0 * dev->bits * dev->transmit_period);
} else {
/* Non-FIFO mode. */
ret = dev->dat;
/* Always clear Data Ready interrupt. */
dev->lsr &= 0xfe;
dev->int_status &= ~SERIAL_INT_RECEIVE;
serial_update_ints(dev);
}
serial_log("Read data: %02X\n", ret);
break;
case 1:
if (dev->lcr & 0x80)
ret = (dev->dlab >> 8) & 0xff;
else
ret = dev->ier;
break;
case 2:
ret = dev->iir;
if ((ret & 0xe) == 2) {
dev->int_status &= ~SERIAL_INT_TRANSMIT;
serial_update_ints(dev);
}
if (dev->fcr & 1)
ret |= 0xc0;
break;
case 3:
ret = dev->lcr;
break;
case 4:
ret = dev->mctrl;
break;
case 5:
ret = dev->lsr;
if (dev->lsr & 0x1f)
dev->lsr &= ~0x1e;
dev->int_status &= ~SERIAL_INT_LSR;
serial_update_ints(dev);
break;
case 6:
if (dev->mctrl & 0x10)
ret = dev->msr;
else
ret = dev->msr | dev->msr_set;
dev->msr &= ~0x0f;
dev->int_status &= ~SERIAL_INT_MSR;
serial_update_ints(dev);
break;
case 7:
ret = dev->scratch;
break;
default:
break;
}
serial_log("UART: [%04X:%08X] Read %02X from port %02X\n", CS, cpu_state.pc, ret, addr);
return ret;
}
void
serial_remove(serial_t *dev)
{
if (dev == NULL)
return;
if (!com_ports[dev->inst].enabled)
return;
if (!dev->base_address)
return;
serial_log("Removing serial port %i at %04X...\n", dev->inst, dev->base_address);
io_removehandler(dev->base_address, 0x0008,
serial_read, NULL, NULL, serial_write, NULL, NULL, dev);
dev->base_address = 0x0000;
}
void
serial_setup(serial_t *dev, uint16_t addr, uint8_t irq)
{
serial_log("Adding serial port %i at %04X...\n", dev->inst, addr);
if (dev == NULL)
return;
if (!com_ports[dev->inst].enabled)
return;
if (dev->base_address != 0x0000)
serial_remove(dev);
dev->base_address = addr;
if (addr != 0x0000)
io_sethandler(addr, 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, dev);
dev->irq = irq;
}
static void
serial_rcvr_d_empty_evt(void *priv)
{
serial_t *dev = (serial_t *) priv;
dev->lsr = (dev->lsr & 0xfe) | (fifo_get_empty(dev->rcvr_fifo) ? 0 : 1);
}
static void
serial_rcvr_d_overrun_evt(void *priv)
{
serial_t *dev = (serial_t *) priv;
dev->lsr = (dev->lsr & 0xfd) | (fifo_get_overrun(dev->rcvr_fifo) << 1);
}
static void
serial_rcvr_d_ready_evt(void *priv)
{
serial_t *dev = (serial_t *) priv;
dev->int_status = (dev->int_status & ~SERIAL_INT_RECEIVE) |
(fifo_get_ready(dev->rcvr_fifo) ? SERIAL_INT_RECEIVE : 0);
serial_update_ints(dev);
}
static void
serial_xmit_d_empty_evt(void *priv)
{
serial_t *dev = (serial_t *) priv;
uint8_t is_empty = dev->fifo_enabled ? fifo_get_empty(dev->xmit_fifo) : dev->thr_empty;
dev->lsr = (dev->lsr & 0x9f) | (is_empty << 5) | ((dev->txsr_empty && is_empty) << 6);
dev->int_status = (dev->int_status & ~SERIAL_INT_TRANSMIT) | (is_empty ? SERIAL_INT_TRANSMIT : 0);
}
serial_t *
serial_attach_ex(int port,
void (*rcr_callback)(struct serial_s *serial, void *priv),
void (*dev_write)(struct serial_s *serial, void *priv, uint8_t data),
void (*transmit_period_callback)(struct serial_s *serial, void *priv, double transmit_period),
void (*lcr_callback)(struct serial_s *serial, void *priv, uint8_t data_bits),
void *priv)
{
serial_device_t *sd = &serial_devices[port];
sd->rcr_callback = rcr_callback;
sd->dev_write = dev_write;
sd->transmit_period_callback = transmit_period_callback;
sd->lcr_callback = lcr_callback;
sd->priv = priv;
return sd->serial;
}
serial_t *
serial_attach_ex_2(int port,
void (*rcr_callback)(struct serial_s *serial, void *priv),
void (*dev_write)(struct serial_s *serial, void *priv, uint8_t data),
void (*dtr_callback)(struct serial_s *serial, int status, void *priv),
void *priv)
{
serial_device_t *sd = &serial_devices[port];
sd->rcr_callback = rcr_callback;
sd->dtr_callback = dtr_callback;
sd->dev_write = dev_write;
sd->transmit_period_callback = NULL;
sd->lcr_callback = NULL;
sd->priv = priv;
return sd->serial;
}
static void
serial_speed_changed(void *priv)
{
serial_t *dev = (serial_t *) priv;
serial_update_speed(dev);
}
static void
serial_close(void *priv)
{
serial_t *dev = (serial_t *) priv;
next_inst--;
if (com_ports[dev->inst].enabled)
fifo_close(dev->rcvr_fifo);
free(dev);
}
static void
serial_reset(void *priv)
{
serial_t *dev = (serial_t *) priv;
if (com_ports[dev->inst].enabled) {
timer_disable(&dev->transmit_timer);
timer_disable(&dev->timeout_timer);
timer_disable(&dev->receive_timer);
dev->lsr = dev->thr = dev->mctrl = dev->rcr = 0x00;
dev->iir = dev->ier = dev->lcr = dev->msr = 0x00;
dev->dat = dev->int_status = dev->scratch = dev->fcr = 0x00;
dev->fifo_enabled = dev->bits = 0x000;
dev->data_bits = dev->baud_cycles = 0x00;
dev->txsr = 0x00;
dev->txsr_empty = 0x01;
dev->thr_empty = 0x0001;
dev->dlab = dev->out_new = 0x0000;
if (dev->rcvr_fifo != NULL)
fifo_reset(dev->rcvr_fifo);
serial_reset_port(dev);
dev->dlab = 96;
dev->fcr = 0x06;
serial_transmit_period(dev);
serial_update_speed(dev);
}
}
static void *
serial_init(const device_t *info)
{
serial_t *dev = (serial_t *) malloc(sizeof(serial_t));
memset(dev, 0, sizeof(serial_t));
dev->inst = next_inst;
if (com_ports[next_inst].enabled) {
serial_log("Adding serial port %i...\n", next_inst);
dev->type = info->local;
memset(&(serial_devices[next_inst]), 0, sizeof(serial_device_t));
dev->sd = &(serial_devices[next_inst]);
dev->sd->serial = dev;
if (next_inst == 6)
serial_setup(dev, COM7_ADDR, COM7_IRQ);
else if (next_inst == 5)
serial_setup(dev, COM6_ADDR, COM6_IRQ);
else if (next_inst == 4)
serial_setup(dev, COM5_ADDR, COM5_IRQ);
else if (next_inst == 3)
serial_setup(dev, COM4_ADDR, COM4_IRQ);
else if (next_inst == 2)
serial_setup(dev, COM3_ADDR, COM3_IRQ);
else if ((next_inst == 1) || (info->flags & DEVICE_PCJR))
serial_setup(dev, COM2_ADDR, COM2_IRQ);
else if (next_inst == 0)
serial_setup(dev, COM1_ADDR, COM1_IRQ);
/* Default to 1200,N,7. */
dev->dlab = 96;
dev->fcr = 0x06;
if (info->local == SERIAL_8250_PCJR)
dev->clock_src = 1789500.0;
else
dev->clock_src = 1843200.0;
timer_add(&dev->transmit_timer, serial_transmit_timer, dev, 0);
timer_add(&dev->timeout_timer, serial_timeout_timer, dev, 0);
timer_add(&dev->receive_timer, serial_receive_timer, dev, 0);
serial_transmit_period(dev);
serial_update_speed(dev);
dev->rcvr_fifo = fifo64_init();
fifo_set_priv(dev->rcvr_fifo, dev);
fifo_set_d_empty_evt(dev->rcvr_fifo, serial_rcvr_d_empty_evt);
fifo_set_d_overrun_evt(dev->rcvr_fifo, serial_rcvr_d_overrun_evt);
fifo_set_d_ready_evt(dev->rcvr_fifo, serial_rcvr_d_ready_evt);
fifo_reset_evt(dev->rcvr_fifo);
fifo_set_len(dev->rcvr_fifo, 16);
dev->xmit_fifo = fifo64_init();
fifo_set_priv(dev->xmit_fifo, dev);
fifo_set_d_empty_evt(dev->xmit_fifo, serial_xmit_d_empty_evt);
fifo_reset_evt(dev->xmit_fifo);
fifo_set_len(dev->xmit_fifo, 16);
serial_reset_port(dev);
}
next_inst++;
return dev;
}
void
serial_set_next_inst(int ni)
{
next_inst = ni;
}
void
serial_standalone_init(void)
{
while (next_inst < SERIAL_MAX)
device_add_inst(&ns8250_device, next_inst + 1);
};
const device_t ns8250_device = {
.name = "National Semiconductor 8250(-compatible) UART",
.internal_name = "ns8250",
.flags = 0,
.local = SERIAL_8250,
.init = serial_init,
.close = serial_close,
.reset = serial_reset,
{ .available = NULL },
.speed_changed = serial_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t ns8250_pcjr_device = {
.name = "National Semiconductor 8250(-compatible) UART for PCjr",
.internal_name = "ns8250_pcjr",
.flags = DEVICE_PCJR,
.local = SERIAL_8250_PCJR,
.init = serial_init,
.close = serial_close,
.reset = serial_reset,
{ .available = NULL },
.speed_changed = serial_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t ns16450_device = {
.name = "National Semiconductor NS16450(-compatible) UART",
.internal_name = "ns16450",
.flags = 0,
.local = SERIAL_16450,
.init = serial_init,
.close = serial_close,
.reset = serial_reset,
{ .available = NULL },
.speed_changed = serial_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t ns16550_device = {
.name = "National Semiconductor NS16550(-compatible) UART",
.internal_name = "ns16550",
.flags = 0,
.local = SERIAL_16550,
.init = serial_init,
.close = serial_close,
.reset = serial_reset,
{ .available = NULL },
.speed_changed = serial_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t ns16650_device = {
.name = "Startech Semiconductor 16650(-compatible) UART",
.internal_name = "ns16650",
.flags = 0,
.local = SERIAL_16650,
.init = serial_init,
.close = serial_close,
.reset = serial_reset,
{ .available = NULL },
.speed_changed = serial_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t ns16750_device = {
.name = "Texas Instruments 16750(-compatible) UART",
.internal_name = "ns16750",
.flags = 0,
.local = SERIAL_16750,
.init = serial_init,
.close = serial_close,
.reset = serial_reset,
{ .available = NULL },
.speed_changed = serial_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t ns16850_device = {
.name = "Exar Corporation NS16850(-compatible) UART",
.internal_name = "ns16850",
.flags = 0,
.local = SERIAL_16850,
.init = serial_init,
.close = serial_close,
.reset = serial_reset,
{ .available = NULL },
.speed_changed = serial_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t ns16950_device = {
.name = "Oxford Semiconductor NS16950(-compatible) UART",
.internal_name = "ns16950",
.flags = 0,
.local = SERIAL_16950,
.init = serial_init,
.close = serial_close,
.reset = serial_reset,
{ .available = NULL },
.speed_changed = serial_speed_changed,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/device/serial.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,888 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 3M MicroTouch SMT3 emulation.
*
*
*
* Authors: Cacodemon345, mourix
*
*/
/* Reference: path_to_url */
/* TODO:
- Properly implement GP/SP commands (formats are not documented at all, like anywhere; no dumps yet).
- Decouple serial packet generation from mouse poll rate.
- Dynamic baud rate selection from software following this.
- Add additional SMT2/3 formats as we currently only support Tablet, Hex and Dec.
- Add additional SMT2/3 modes as we currently hardcode Mode Stream.
*/
#include <ctype.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/mouse.h>
#include <86box/serial.h>
#include <86box/plat.h>
#include <86box/fifo8.h>
#include <86box/fifo.h>
#include <86box/video.h> /* Needed to account for overscan. */
enum mtouch_formats {
FORMAT_DEC = 1,
FORMAT_HEX = 2,
FORMAT_RAW = 3,
FORMAT_TABLET = 4
};
const char* mtouch_identity[] = {
"A30100", /* SMT2 Serial / SMT3(R)V */
"A40100", /* SMT2 PCBus */
"P50100", /* TouchPen 4(+) */
"Q10100", /* SMT3(R) Serial */
};
typedef struct mouse_microtouch_t {
double baud_rate;
unsigned int abs_x_int, abs_y_int;
int b;
char cmd[256];
int cmd_pos;
uint8_t format;
bool mode_status;
uint8_t id, cal_cntr, pen_mode;
bool soh;
bool in_reset;
serial_t *serial;
Fifo8 resp;
pc_timer_t host_to_serial_timer;
pc_timer_t reset_timer;
} mouse_microtouch_t;
static mouse_microtouch_t *mtouch_inst = NULL;
void
microtouch_reset_complete(void *priv)
{
mouse_microtouch_t *mtouch = (mouse_microtouch_t *) priv;
mtouch->in_reset = false;
fifo8_push_all(&mtouch->resp, (uint8_t *) "\x01\x30\x0D", 3); /* <SOH>0<CR> */
}
void
microtouch_calibrate_timer(void *priv)
{
mouse_microtouch_t *mtouch = (mouse_microtouch_t *) priv;
if (!fifo8_num_used(&mtouch->resp)) {
mtouch->cal_cntr--;
fifo8_push_all(&mtouch->resp, (uint8_t *) "\x01\x31\x0D", 3); /* <SOH>1<CR> */
}
}
void
microtouch_process_commands(mouse_microtouch_t *mtouch)
{
mtouch->cmd[strcspn(mtouch->cmd, "\r")] = '\0';
pclog("MT Command: %s\n", mtouch->cmd);
if (mtouch->cmd[0] == 'C' && (mtouch->cmd[1] == 'N' || mtouch->cmd[1] == 'X')) { /* Calibrate New/Extended */
mtouch->cal_cntr = 2;
}
if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'D') { /* Format Decimal */
mouse_set_sample_rate(106);
mtouch->format = FORMAT_DEC;
}
if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'O') { /* Finger Only */
mtouch->pen_mode = 1;
}
if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'H') { /* Format Hexadecimal */
mouse_set_sample_rate(106);
mtouch->format = FORMAT_HEX;
}
if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'R') { /* Format Raw */
mouse_set_sample_rate(106);
mtouch->format = FORMAT_RAW;
mtouch->cal_cntr = 0;
}
if (mtouch->cmd[0] == 'F' && mtouch->cmd[1] == 'T') { /* Format Tablet */
mouse_set_sample_rate(192);
mtouch->format = FORMAT_TABLET;
}
if (mtouch->cmd[0] == 'G' && mtouch->cmd[1] == 'P' && mtouch->cmd[2] == '1') { /* Get Parameter Block 1 */
fifo8_push_all(&mtouch->resp, (uint8_t *) "\x01\x41\x0D", 3); /* <SOH>A<CR> */
fifo8_push_all(&mtouch->resp, (uint8_t *) "0000000000000000000000000\r", 26);
}
if (mtouch->cmd[0] == 'M' && mtouch->cmd[1] == 'T') { /* Mode Status */
mtouch->mode_status = true;
}
if (mtouch->cmd[0] == 'O' && mtouch->cmd[1] == 'I') { /* Output Identity */
fifo8_push(&mtouch->resp, 0x01);
fifo8_push_all(&mtouch->resp, (uint8_t *) mtouch_identity[mtouch->id], 6);
fifo8_push(&mtouch->resp, 0x0D);
return;
}
if (mtouch->cmd[0] == 'P') {
if (mtouch->cmd[1] == 'F') mtouch->pen_mode = 3; /* Pen or Finger */
else if (mtouch->cmd[1] == 'O') mtouch->pen_mode = 2; /* Pen Only */
}
if (mtouch->cmd[0] == 'R') { /* Reset */
mtouch->in_reset = true;
mtouch->cal_cntr = 0;
mtouch->pen_mode = 3;
mtouch->mode_status = false;
if (mtouch->id < 2) {
mouse_set_sample_rate(106);
mtouch->format = FORMAT_DEC;
} else {
mouse_set_sample_rate(192);
mtouch->format = FORMAT_TABLET;
}
timer_on_auto(&mtouch->reset_timer, 500. * 1000.);
return;
}
if (mtouch->cmd[0] == 'S' && mtouch->cmd[1] == 'P' && mtouch->cmd[2] == '1') { /* Set Parameter Block 1 */
fifo8_push_all(&mtouch->resp, (uint8_t *) "\x01\x41\x0D", 3); /* <SOH>A<CR> */
return;
}
if (mtouch->cmd[0] == 'U' && mtouch->cmd[1] == 'T') { /* Unit Type */
fifo8_push(&mtouch->resp, 0x01);
if (mtouch->id == 2) {
fifo8_push_all(&mtouch->resp, (uint8_t *) "TP****00", 8);
} else {
fifo8_push_all(&mtouch->resp, (uint8_t *) "QM****00", 8);
}
fifo8_push(&mtouch->resp, 0x0D);
return;
}
fifo8_push_all(&mtouch->resp, (uint8_t *) "\x01\x30\x0D", 3); /* <SOH>0<CR> */
}
void
mtouch_write_to_host(void *priv)
{
mouse_microtouch_t *dev = (mouse_microtouch_t *) priv;
if ((dev->serial->type >= SERIAL_16550) && dev->serial->fifo_enabled) {
if (fifo_get_full(dev->serial->rcvr_fifo)) {
goto no_write_to_machine;
}
} else {
if (dev->serial->lsr & 1) {
goto no_write_to_machine;
}
}
if (dev->in_reset) {
goto no_write_to_machine;
}
if (fifo8_num_used(&dev->resp)) {
serial_write_fifo(dev->serial, fifo8_pop(&dev->resp));
}
no_write_to_machine:
timer_on_auto(&dev->host_to_serial_timer, (1000000.0 / (double) dev->baud_rate) * (double) (1 + 8 + 1));
}
void
mtouch_write(serial_t *serial, void *priv, uint8_t data)
{
mouse_microtouch_t *dev = (mouse_microtouch_t *) priv;
if (data == '\x1') {
dev->soh = 1;
} else if (dev->soh) {
if (data != '\r') {
dev->cmd[dev->cmd_pos++] = data;
} else {
dev->soh = 0;
if (!dev->cmd_pos) {
return;
}
dev->cmd[dev->cmd_pos++] = data;
dev->cmd_pos = 0;
microtouch_process_commands(dev);
}
}
}
static int
mtouch_poll(void *priv)
{
mouse_microtouch_t *dev = (mouse_microtouch_t *) priv;
if (fifo8_num_free(&dev->resp) <= 256 - 10 || dev->format == FORMAT_RAW) {
return 0;
}
unsigned int abs_x_int = 0, abs_y_int = 0;
double abs_x;
double abs_y;
int b = mouse_get_buttons_ex();
mouse_get_abs_coords(&abs_x, &abs_y);
if (abs_x >= 1.0)
abs_x = 1.0;
if (abs_y >= 1.0)
abs_y = 1.0;
if (abs_x <= 0.0)
abs_x = 0.0;
if (abs_y <= 0.0)
abs_y = 0.0;
if (enable_overscan) {
int index = mouse_tablet_in_proximity - 1;
if (mouse_tablet_in_proximity == -1) {
mouse_tablet_in_proximity = 0;
}
abs_x *= monitors[index].mon_unscaled_size_x - 1;
abs_y *= monitors[index].mon_efscrnsz_y - 1;
if (abs_x <= (monitors[index].mon_overscan_x / 2.)) {
abs_x = (monitors[index].mon_overscan_x / 2.);
}
if (abs_y <= (monitors[index].mon_overscan_y / 2.)) {
abs_y = (monitors[index].mon_overscan_y / 2.);
}
abs_x -= (monitors[index].mon_overscan_x / 2.);
abs_y -= (monitors[index].mon_overscan_y / 2.);
abs_x = abs_x / (double) monitors[index].mon_xsize;
abs_y = abs_y / (double) monitors[index].mon_ysize;
if (abs_x >= 1.0)
abs_x = 1.0;
if (abs_y >= 1.0)
abs_y = 1.0;
}
if (dev->cal_cntr || (!b && !dev->b)) { /* Calibration or no buttonpress */
if (!b && dev->b) {
microtouch_calibrate_timer(dev);
}
dev->b = b; /* Save buttonpress */
return 0;
}
if (dev->format == FORMAT_DEC) {
abs_x_int = abs_x * 999;
abs_y_int = 999 - (abs_y * 999);
char buffer[10];
if (!dev->mode_status) {
if (b) { // Touch
snprintf(buffer, sizeof(buffer), "\x1%03d,%03d\r", abs_x_int, abs_y_int);
fifo8_push_all(&dev->resp, (uint8_t *)buffer, strlen(buffer));
}
} else {
if (b) {
if (!dev->b) { /* Touchdown Status */
snprintf(buffer, sizeof(buffer), "\x19%03d,%03d\r", abs_x_int, abs_y_int);
} else { /* Touch Continuation Status */
snprintf(buffer, sizeof(buffer), "\x1c%03d,%03d\r", abs_x_int, abs_y_int);
}
} else if (dev->b) { /* Liftoff Status */
snprintf(buffer, sizeof(buffer), "\x18%03d,%03d\r", dev->abs_x_int, dev->abs_y_int);
}
fifo8_push_all(&dev->resp, (uint8_t *)buffer, strlen(buffer));
}
}
else if (dev->format == FORMAT_HEX) {
abs_x_int = abs_x * 1023;
abs_y_int = 1023 - (abs_y * 1023);
char buffer[10];
if (!dev->mode_status) {
if (b) { // Touch
snprintf(buffer, sizeof(buffer), "\x1%03X,%03X\r", abs_x_int, abs_y_int);
fifo8_push_all(&dev->resp, (uint8_t *)buffer, strlen(buffer));
}
} else {
if (b) {
if (!dev->b) { /* Touchdown Status */
snprintf(buffer, sizeof(buffer), "\x19%03X,%03X\r", abs_x_int, abs_y_int);
} else { /* Touch Continuation Status */
snprintf(buffer, sizeof(buffer), "\x1c%03X,%03X\r", abs_x_int, abs_y_int);
}
} else if (dev->b) { /* Liftoff Status */
snprintf(buffer, sizeof(buffer), "\x18%03X,%03X\r", dev->abs_x_int, dev->abs_y_int);
}
fifo8_push_all(&dev->resp, (uint8_t *)buffer, strlen(buffer));
}
}
else if (dev->format == FORMAT_TABLET) {
abs_x_int = abs_x * 16383;
abs_y_int = 16383 - abs_y * 16383;
if (b) { /* Touchdown/Continuation */
fifo8_push(&dev->resp, 0b11000000 | ((dev->pen_mode == 2) ? ((1 << 5) | ((b & 3))) : 0));
fifo8_push(&dev->resp, abs_x_int & 0b1111111);
fifo8_push(&dev->resp, (abs_x_int >> 7) & 0b1111111);
fifo8_push(&dev->resp, abs_y_int & 0b1111111);
fifo8_push(&dev->resp, (abs_y_int >> 7) & 0b1111111);
} else if (dev->b) { /* Liftoff */
fifo8_push(&dev->resp, 0b10000000 | ((dev->pen_mode == 2) ? ((1 << 5)) : 0));
fifo8_push(&dev->resp, dev->abs_x_int & 0b1111111);
fifo8_push(&dev->resp, (dev->abs_x_int >> 7) & 0b1111111);
fifo8_push(&dev->resp, dev->abs_y_int & 0b1111111);
fifo8_push(&dev->resp, (dev->abs_y_int >> 7) & 0b1111111);
}
}
/* Save old states*/
dev->abs_x_int = abs_x_int;
dev->abs_y_int = abs_y_int;
dev->b = b;
return 0;
}
static void
mtouch_poll_global(void)
{
mtouch_poll(mtouch_inst);
}
void *
mtouch_init(const device_t *info)
{
mouse_microtouch_t *dev = calloc(1, sizeof(mouse_microtouch_t));
dev->serial = serial_attach(device_get_config_int("port"), NULL, mtouch_write, dev);
dev->baud_rate = device_get_config_int("baudrate");
serial_set_cts(dev->serial, 1);
serial_set_dsr(dev->serial, 1);
serial_set_dcd(dev->serial, 1);
fifo8_create(&dev->resp, 256);
timer_add(&dev->host_to_serial_timer, mtouch_write_to_host, dev, 0);
timer_add(&dev->reset_timer, microtouch_reset_complete, dev, 0);
timer_on_auto(&dev->host_to_serial_timer, (1000000. / dev->baud_rate) * 10);
dev->id = device_get_config_int("identity");
dev->pen_mode = 3;
dev->mode_status = false;
if (dev->id < 2) { /* legacy controllers */
dev->format = FORMAT_DEC;
mouse_set_sample_rate(106);
}
else {
dev->format = FORMAT_TABLET;
mouse_set_sample_rate(192);
}
mouse_input_mode = device_get_config_int("crosshair") + 1;
mouse_set_buttons(2);
mouse_set_poll_ex(mtouch_poll_global);
mtouch_inst = dev;
return dev;
}
void
mtouch_close(void *priv)
{
mouse_microtouch_t *dev = (mouse_microtouch_t *) priv;
fifo8_destroy(&dev->resp);
/* Detach serial port from the mouse. */
if (dev && dev->serial && dev->serial->sd)
memset(dev->serial->sd, 0, sizeof(serial_device_t));
free(dev);
mtouch_inst = NULL;
}
static const device_config_t mtouch_config[] = {
// clang-format off
{
.name = "port",
.description = "Serial Port",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "COM1", .value = 0 },
{ .description = "COM2", .value = 1 },
{ .description = "COM3", .value = 2 },
{ .description = "COM4", .value = 3 },
{ .description = "" }
}
},
{
.name = "baudrate",
.description = "Baud Rate",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 9600,
.file_filter = NULL,
.spinner = { 0 },
.selection = {
{ .description = "19200", .value = 19200 },
{ .description = "9600", .value = 9600 },
{ .description = "4800", .value = 4800 },
{ .description = "2400", .value = 2400 },
{ .description = "1200", .value = 1200 }
}
},
{
.name = "identity",
.description = "Controller",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = NULL,
.spinner = { 0 },
.selection = {
{ .description = "A3 - SMT2 Serial / SMT3(R)V", .value = 0 },
{ .description = "A4 - SMT2 PCBus", .value = 1 },
{ .description = "P5 - TouchPen 4(+)", .value = 2 },
{ .description = "Q1 - SMT3(R) Serial", .value = 3 }
}
},
{
.name = "crosshair",
.description = "Show Crosshair",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 1
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t mouse_mtouch_device = {
.name = "3M MicroTouch (Serial)",
.internal_name = "microtouch_touchpen",
.flags = DEVICE_COM,
.local = 0,
.init = mtouch_init,
.close = mtouch_close,
.reset = NULL,
{ .poll = mtouch_poll },
.speed_changed = NULL,
.force_redraw = NULL,
.config = mtouch_config
};
``` | /content/code_sandbox/src/device/mouse_microtouch_touchscreen.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,711 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Genesys Logic GL518SM hardware monitoring chip.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <math.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#define HAVE_STDARG_H
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/i2c.h>
#include <86box/hwm.h>
#include <86box/plat_unused.h>
#define CLAMP(a, min, max) (((a) < (min)) ? (min) : (((a) > (max)) ? (max) : (a)))
/* Formulas and factors derived from Linux's gl518sm.c and gl520sm.c drivers. */
#define GL518SM_RPM_TO_REG(r, d) ((r) ? (480000 / (CLAMP((r), (480000 >> (d)) / 255, (480000 >> (d))) << (d))) : 0)
#define GL518SM_VOLTAGE_TO_REG(v) ((uint8_t) round((v) / 19.0))
#define GL518SM_VDD_TO_REG(v) ((uint8_t) (((v) *4) / 95.0))
#define GL520SM 0x100
typedef struct gl518sm_t {
uint32_t local;
hwm_values_t *values;
uint16_t regs[32];
uint8_t addr_register : 5;
uint8_t i2c_addr : 7;
uint8_t i2c_state : 2;
uint8_t i2c_enabled : 1;
} gl518sm_t;
static uint8_t gl518sm_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv);
static uint8_t gl518sm_i2c_read(void *bus, uint8_t addr, void *priv);
static uint16_t gl518sm_read(gl518sm_t *dev, uint8_t reg);
static uint8_t gl518sm_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv);
static uint8_t gl518sm_write(gl518sm_t *dev, uint8_t reg, uint16_t val);
static void gl518sm_reset(gl518sm_t *dev);
#ifdef ENABLE_GL518SM_LOG
int gl518sm_do_log = ENABLE_GL518SM_LOG;
static void
gl518sm_log(const char *fmt, ...)
{
va_list ap;
if (gl518sm_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define gl518sm_log(fmt, ...)
#endif
static void
gl518sm_remap(gl518sm_t *dev, uint8_t addr)
{
gl518sm_log("GL518SM: remapping to SMBus %02Xh\n", addr);
if (dev->i2c_enabled)
i2c_removehandler(i2c_smbus, dev->i2c_addr, 1, gl518sm_i2c_start, gl518sm_i2c_read, gl518sm_i2c_write, NULL, dev);
if (addr < 0x80)
i2c_sethandler(i2c_smbus, addr, 1, gl518sm_i2c_start, gl518sm_i2c_read, gl518sm_i2c_write, NULL, dev);
dev->i2c_addr = addr & 0x7f;
dev->i2c_enabled = !(addr & 0x80);
}
static uint8_t
gl518sm_i2c_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
{
gl518sm_t *dev = (gl518sm_t *) priv;
dev->i2c_state = 0;
return 1;
}
static uint8_t
gl518sm_i2c_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
{
gl518sm_t *dev = (gl518sm_t *) priv;
uint16_t read = gl518sm_read(dev, dev->addr_register);
uint8_t ret = 0;
if (dev->i2c_state == 0)
dev->i2c_state = 1;
if ((dev->i2c_state == 1) && (dev->addr_register >= 0x07) && (dev->addr_register <= 0x0c)) { /* two-byte registers: read MSB first */
dev->i2c_state = 2;
ret = read >> 8;
} else {
ret = read;
dev->addr_register++;
}
return ret;
}
static uint16_t
gl518sm_read(gl518sm_t *dev, uint8_t reg)
{
uint16_t ret;
reg &= 0x1f;
switch (reg) {
case 0x04: /* temperature */
ret = (dev->values->temperatures[0] + ((dev->local & GL520SM) ? 130 : 119)) & 0xff;
break;
case 0x07: /* fan speeds */
ret = GL518SM_RPM_TO_REG(dev->values->fans[0], (dev->regs[0x0f] >> 6) & 0x3) << 8;
ret |= GL518SM_RPM_TO_REG(dev->values->fans[1], (dev->regs[0x0f] >> 4) & 0x3);
break;
case 0x0d: /* VIN3 */
ret = GL518SM_VOLTAGE_TO_REG(dev->values->voltages[2]);
break;
case 0x0e: /* temperature 2 */
ret = (dev->local & GL520SM) ? ((dev->values->temperatures[1] + 130) & 0xff) : dev->regs[reg];
break;
case 0x13: /* VIN2 */
ret = GL518SM_VOLTAGE_TO_REG(dev->values->voltages[1]);
break;
case 0x14: /* VIN1 */
ret = GL518SM_VOLTAGE_TO_REG(dev->values->voltages[0]);
break;
case 0x15: /* VDD */
ret = GL518SM_VDD_TO_REG(dev->values->voltages[3]);
break;
default: /* other registers */
ret = dev->regs[reg];
break;
}
gl518sm_log("GL518SM: read(%02X) = %04X\n", reg, ret);
return ret;
}
static uint8_t
gl518sm_i2c_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t data, void *priv)
{
gl518sm_t *dev = (gl518sm_t *) priv;
switch (dev->i2c_state++) {
case 0:
dev->addr_register = data;
break;
case 1:
gl518sm_write(dev, dev->addr_register, (gl518sm_read(dev, dev->addr_register) & 0xff00) | data);
break;
case 2:
gl518sm_write(dev, dev->addr_register, (gl518sm_read(dev, dev->addr_register) << 8) | data);
break;
default:
dev->i2c_state = 3;
return 0;
}
return 1;
}
static uint8_t
gl518sm_write(gl518sm_t *dev, uint8_t reg, uint16_t val)
{
gl518sm_log("GL518SM: write(%02X, %04X)\n", reg, val);
switch (reg) {
case 0x00:
case 0x01:
case 0x04:
case 0x07:
case 0x0d:
case 0x12:
case 0x13:
case 0x14:
case 0x15:
/* read-only registers */
return 0;
case 0x0a:
dev->regs[0x13] = val & 0xff;
break;
case 0x03:
dev->regs[reg] = val & 0xfc;
if (val & 0x80) /* Init */
gl518sm_reset(dev);
break;
case 0x0e:
if (dev->local & GL520SM)
return 0;
break;
case 0x0f:
dev->regs[reg] = val & 0xf8;
break;
case 0x11:
dev->regs[reg] = val & 0x7f;
break;
default:
dev->regs[reg] = val;
break;
}
return 1;
}
static void
gl518sm_reset(gl518sm_t *dev)
{
memset(dev->regs, 0, sizeof(dev->regs));
if (dev->local & GL520SM) {
dev->regs[0x00] = 0x20;
dev->regs[0x01] = 0x00;
dev->regs[0x03] = 0x04;
} else {
dev->regs[0x00] = 0x80;
dev->regs[0x01] = 0x80; /* revision 0x80 can read all voltages */
dev->regs[0x05] = 0xc7;
dev->regs[0x06] = 0xc2;
}
dev->regs[0x08] = 0x6464;
dev->regs[0x09] = 0xdac5;
dev->regs[0x0a] = 0xdac5;
dev->regs[0x0b] = 0xdac5;
dev->regs[0x0c] = 0xdac5;
dev->regs[0x0f] = 0x00;
gl518sm_remap(dev, dev->i2c_addr | (dev->i2c_enabled ? 0x00 : 0x80));
}
static void
gl518sm_close(void *priv)
{
gl518sm_t *dev = (gl518sm_t *) priv;
gl518sm_remap(dev, 0);
free(dev);
}
static void *
gl518sm_init(const device_t *info)
{
gl518sm_t *dev = (gl518sm_t *) malloc(sizeof(gl518sm_t));
memset(dev, 0, sizeof(gl518sm_t));
dev->local = info->local;
/* Set default values. */
hwm_values_t defaults = {
{
/* fan speeds */
3000, /* usually Chassis */
3000 /* usually CPU */
},
{
/* temperatures */
30, /* usually CPU */
30 /* GL520SM only: usually System */
},
{
/* voltages */
hwm_get_vcore(), /* Vcore */
RESISTOR_DIVIDER(12000, 150, 47), /* +12V (15K/4.7K divider suggested in the datasheet) */
3300, /* +3.3V */
5000 /* +5V */
}
};
hwm_values = defaults;
dev->values = &hwm_values;
gl518sm_reset(dev);
gl518sm_remap(dev, dev->local & 0x7f);
return dev;
}
/* GL518SM on SMBus address 2Ch */
const device_t gl518sm_2c_device = {
.name = "Genesys Logic GL518SM Hardware Monitor",
.internal_name = "gl518sm_2c",
.flags = DEVICE_ISA,
.local = 0x2c,
.init = gl518sm_init,
.close = gl518sm_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
/* GL518SM on SMBus address 2Dh */
const device_t gl518sm_2d_device = {
.name = "Genesys Logic GL518SM Hardware Monitor",
.internal_name = "gl518sm_2d",
.flags = DEVICE_ISA,
.local = 0x2d,
.init = gl518sm_init,
.close = gl518sm_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
/* GL520SM on SMBus address 2Ch */
const device_t gl520sm_2c_device = {
.name = "Genesys Logic GL520SM Hardware Monitor",
.internal_name = "gl520sm_2c",
.flags = DEVICE_ISA,
.local = GL520SM | 0x2c,
.init = gl518sm_init,
.close = gl518sm_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
/* GL520SM on SMBus address 2Dh */
const device_t gl520sm_2d_device = {
.name = "Genesys Logic GL520SM Hardware Monitor",
.internal_name = "gl520sm_2d",
.flags = DEVICE_ISA,
.local = GL520SM | 0x2d,
.init = gl518sm_init,
.close = gl518sm_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/device/hwm_gl518sm.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,188 |
```c
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/mouse.h>
#include <86box/serial.h>
#include <86box/plat.h>
#include <86box/fifo8.h>
#define FLAG_3BTN 0x20 /* enable 3-button mode */
enum wacom_modes {
WACOM_MODE_SUPPRESSED = 0,
WACOM_MODE_POINT = 1,
WACOM_MODE_STREAM = 2,
WACOM_MODE_SWITCH = 3,
};
enum wacom_handshake_modes {
WACOM_HANDSHAKE_NONE = 0,
WACOM_HANDSHAKE_CTS = 1,
WACOM_HANDSHAKE_DTS = 2,
WACOM_HANDSHAKE_BOTH = 3,
};
enum wacom_cmd_set {
WACOM_CMDSET_BITPAD = 0,
WACOM_CMDSET_MM1201 = 1,
WACOM_CMDSET_IIS = 2,
WACOM_CMDSET_IV = 3
};
enum wacom_tablet_type {
WACOM_TYPE_IISONLY = 0,
WACOM_TYPE_IV,
};
enum {
REPORT_PHASE_PREPARE,
REPORT_PHASE_TRANSMIT
};
typedef struct wacom_tablet_id {
char id[64];
int type;
} wacom_tablet_id;
static const wacom_tablet_id sd510_id = {
.id = "~#SD51C V3.2.1.01\r",
.type = WACOM_TYPE_IISONLY
};
static const wacom_tablet_id artpad_id = {
.id = "~#KT-0405-R00 V1.1-0\r",
.type = WACOM_TYPE_IV
};
static const uint32_t wacom_resolution_values[4] = {
500,
508,
1000,
1270
};
typedef struct mouse_wacom_t {
const char *name; /* name of this device */
int8_t type; /* type of this device */
int8_t port;
uint8_t flags; /* device flags */
uint8_t but;
uint8_t status;
uint8_t bits;
uint8_t data_rec[0x200];
int abs_x;
int abs_y;
int rel_x;
int rel_y;
int oldb;
int b;
Fifo8 data;
int data_rec_pos;
int mode;
int interval;
int increment;
int suppressed_increment;
int transmission_stopped;
int reset;
int transmit_id;
int transmit_id_pending;
int pressure_mode;
int suppressed;
int measurement;
int remote_req;
uint32_t x_res;
uint32_t y_res;
const wacom_tablet_id *tablet_type;
int last_abs_x; /* Suppressed/Increment Mode. */
int last_abs_y; /* Suppressed/Increment Mode. */
union {
uint32_t settings; /* Settings DWORD */
/* We don't target any architectures except x86/x64/ARM32/ARM64.
(The ABIs for those are explicit in little-endian bit ordering) */
struct settings_bits {
uint8_t remote_mode : 1;
uint8_t bitpad_two_cursor_data : 1;
uint8_t mm961_orientation : 1;
uint8_t mm_command_set : 1;
uint8_t tilt : 1;
uint8_t multi_device : 1;
uint8_t reading_height : 1;
uint8_t pressure_sensitivity : 1;
uint8_t pnp : 1; /* Unused. */
uint8_t dummy : 1;
uint8_t terminator : 2;
uint8_t out_of_range_data : 1;
uint8_t origin_location : 1;
uint8_t resolution : 2;
uint8_t transfer_rate : 2;
uint8_t coord_sys : 1;
uint8_t output_format : 1;
uint8_t transfer_mode : 2;
uint8_t handshake : 2;
uint8_t stop_bits_conf : 1;
uint8_t data_bits_conf : 1;
uint8_t parity : 2;
uint8_t baud_rate : 2;
uint8_t cmd_set : 2;
} settings_bits;
};
double transmit_period;
double old_tsc;
double reset_tsc;
pc_timer_t report_timer;
serial_t *serial;
} mouse_wacom_t;
/* TODO: What is this needed for? */
#if 0
static unsigned int
reverse(register unsigned int x)
{
x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
return ((x >> 16) | (x << 16));
}
#endif
static double
wacom_transmit_period(mouse_wacom_t *dev, int bps, int rps)
{
double dbps = (double) bps;
double temp = 0.0;
int word_len = dev->bits;
if (rps == -1)
temp = (double) word_len;
else {
temp = (double) rps;
temp = (9600.0 - (temp * 33.0));
temp /= rps;
}
temp = (1000000.0 / dbps) * temp;
return temp;
}
static void
wacom_process_settings_dword(mouse_wacom_t *wacom, uint32_t dword)
{
wacom->settings = dword;
wacom->mode = wacom->settings_bits.transfer_mode;
wacom->bits = 1 + 7 + wacom->settings_bits.data_bits_conf;
wacom->bits += 1 + wacom->settings_bits.stop_bits_conf;
if (wacom->settings_bits.parity == 2 && !(wacom->bits % 2)) {
wacom->bits++;
} else if (wacom->settings_bits.parity == 3 && (wacom->bits % 2)) {
wacom->bits++;
}
switch(wacom->settings_bits.baud_rate) {
case 0:
wacom->transmit_period = wacom_transmit_period(wacom, 2400, -1);
break;
case 1:
wacom->transmit_period = wacom_transmit_period(wacom, 4800, -1);
break;
case 2:
wacom->transmit_period = wacom_transmit_period(wacom, 9600, -1);
break;
case 3:
wacom->transmit_period = wacom_transmit_period(wacom, 19200, -1);
break;
default:
break;
}
mouse_input_mode = !wacom->settings_bits.coord_sys;
wacom->x_res = wacom->y_res = wacom_resolution_values[wacom->settings_bits.resolution];
}
static void
wacom_reset(mouse_wacom_t *wacom)
{
wacom->transmit_period = wacom_transmit_period(wacom, 9600, -1);
wacom->mode = WACOM_MODE_POINT;
wacom->transmission_stopped = 0;
wacom->interval = 0;
wacom->transmit_id = 0;
wacom->settings_bits.output_format = 1; /* ASCII */
wacom->settings_bits.cmd_set = 1;
wacom->measurement = 1;
wacom->increment = wacom->suppressed_increment = 0;
wacom->reset_tsc = tsc;
wacom->settings_bits.remote_mode = wacom->remote_req = 0;
wacom->settings_bits.out_of_range_data = 0;
mouse_input_mode = 1;
wacom_process_settings_dword(wacom, 0xA21BC800);
}
static void
wacom_reset_artpad(mouse_wacom_t *wacom)
{
wacom->transmit_period = wacom_transmit_period(wacom, 9600, -1);
wacom->mode = WACOM_MODE_SUPPRESSED;
wacom->transmission_stopped = 0;
wacom->interval = 0;
wacom->transmit_id = 0;
wacom->settings_bits.output_format = 0; /* Binary */
wacom->measurement = 1;
wacom->increment = 0;
wacom->suppressed_increment = 1;
wacom->reset_tsc = tsc;
wacom->settings_bits.remote_mode = 0;
wacom->remote_req = 0;
wacom->settings_bits.out_of_range_data = 0;
wacom_process_settings_dword(wacom, 0xE203C000);
mouse_input_mode = 1;
}
static void
wacom_callback(UNUSED(struct serial_s *serial), void *priv)
{
mouse_wacom_t *wacom = (mouse_wacom_t *) priv;
switch(wacom->settings_bits.baud_rate) {
case 0:
wacom->transmit_period = wacom_transmit_period(wacom, 2400, -1);
break;
case 1:
wacom->transmit_period = wacom_transmit_period(wacom, 4800, -1);
break;
case 2:
wacom->transmit_period = wacom_transmit_period(wacom, 9600, -1);
break;
case 3:
wacom->transmit_period = wacom_transmit_period(wacom, 19200, -1);
break;
default:
break;
}
timer_stop(&wacom->report_timer);
timer_on_auto(&wacom->report_timer, wacom->transmit_period);
}
static void
wacom_write(UNUSED(struct serial_s *serial), void *priv, uint8_t data)
{
mouse_wacom_t *wacom = (mouse_wacom_t *) priv;
static int special_command = 0;
if (data == '~') {
special_command = 1;
return;
}
if (special_command) {
switch (data) {
case '#':
{
wacom->transmit_id = 1;
break;
}
case 'C':
case '*':
case 'R':
{
wacom->data_rec[wacom->data_rec_pos++] = '~';
wacom->data_rec[wacom->data_rec_pos++] = data;
break;
}
default:
break;
}
special_command = 0;
return;
}
if (data == '@') {
wacom->remote_req = 1;
wacom->settings_bits.remote_mode = 1;
return;
}
if (data == '#' && wacom->tablet_type->type == WACOM_TYPE_IV) {
wacom_reset_artpad(wacom);
return;
}
if (data == '$') {
wacom_reset(wacom);
return;
}
if (data == 0x13) {
wacom->transmission_stopped = 1;
return;
}
if (data == 0x11) {
wacom->transmission_stopped = 0;
wacom->settings_bits.remote_mode = wacom->remote_req = 0;
return;
}
wacom->data_rec[wacom->data_rec_pos++] = data;
if (data == '\r' || data == '\n') {
wacom->data_rec[wacom->data_rec_pos] = 0;
wacom->data_rec_pos = 0;
if (data == '\n')
pclog("Wacom: written %s", wacom->data_rec);
else
pclog("Wacom: written %s\n", wacom->data_rec);
if (!memcmp(wacom->data_rec, "AS", 2) && wacom->settings_bits.cmd_set == WACOM_CMDSET_IIS) {
wacom->settings_bits.output_format = !(wacom->data_rec[2] == '1');
} else if (!memcmp(wacom->data_rec, "SR", 2)) {
wacom->mode = WACOM_MODE_STREAM;
} else if (!memcmp(wacom->data_rec, "IN", 2)) {
sscanf((const char *) wacom->data_rec, "IN%d", &wacom->increment);
} else if (!memcmp(wacom->data_rec, "RE", 2)) {
if (wacom->tablet_type->type == WACOM_TYPE_IV) wacom_reset_artpad(wacom);
else wacom_reset(wacom);
} else if (!memcmp(wacom->data_rec, "IT", 2)) {
sscanf((const char *) wacom->data_rec, "IT%d", &wacom->interval);
} else if (!memcmp(wacom->data_rec, "DE", 2) && wacom->settings_bits.cmd_set == WACOM_CMDSET_IIS) {
sscanf((const char *) wacom->data_rec, "DE%d", &mouse_input_mode);
mouse_input_mode = !mouse_input_mode;
plat_mouse_capture(0);
} else if (!memcmp(wacom->data_rec, "SU", 2)) {
sscanf((const char *) wacom->data_rec, "SU%d", &wacom->suppressed_increment);
wacom->settings_bits.transfer_mode = wacom->mode = WACOM_MODE_SUPPRESSED;
} else if (!memcmp(wacom->data_rec, "PH", 2) && wacom->settings_bits.cmd_set == WACOM_CMDSET_IIS) {
sscanf((const char *) wacom->data_rec, "PH%d", &wacom->pressure_mode);
} else if (!memcmp(wacom->data_rec, "IC", 2)) {
sscanf((const char *) wacom->data_rec, "IC%d", &wacom->measurement);
} else if (!memcmp(wacom->data_rec, "SW", 2)) {
wacom->mode = WACOM_MODE_SWITCH;
} else if (!memcmp(wacom->data_rec, "AL", 2)) {
uint8_t out_of_range_data = wacom->settings_bits.out_of_range_data;
wacom->settings_bits.out_of_range_data = !!out_of_range_data;
} else if (!memcmp(wacom->data_rec, "RQ", 2)) {
int remote_mode = 0;
sscanf((const char *) wacom->data_rec, "RQ%d", &remote_mode);
wacom->settings_bits.remote_mode = !!remote_mode;
if (wacom->settings_bits.remote_mode)
wacom->remote_req = 1;
} else if (!memcmp(wacom->data_rec, "SP", 2)) {
wacom->transmission_stopped = 1;
} else if (!memcmp(wacom->data_rec, "ST", 2)) {
wacom->transmission_stopped = 0;
wacom->settings_bits.remote_mode = wacom->remote_req = 0;
} else if (!memcmp(wacom->data_rec, "NR", 2)) {
sscanf((const char *) wacom->data_rec, "NR%d", &wacom->x_res);
wacom->y_res = wacom->x_res;
} else if (wacom->tablet_type->type == WACOM_TYPE_IV && wacom->data_rec[0] == '~') {
if (!memcmp(wacom->data_rec, "~*", 2)) {
uint32_t settings_dword = wacom->settings;
if (strstr((const char *) wacom->data_rec, ",")) {
uint32_t x_res = wacom->x_res;
uint32_t y_res = wacom->y_res;
uint32_t increment = wacom->increment;
uint32_t interval = wacom->interval;
sscanf((const char *) wacom->data_rec, "~*%08X,%d,%d,%d,%d", &settings_dword, &increment, &interval, &x_res, &y_res);
wacom->interval = interval;
wacom->increment = increment;
wacom->x_res = x_res;
wacom->y_res = y_res;
} else {
sscanf((const char *) wacom->data_rec, "~*%X", &settings_dword);
}
wacom_process_settings_dword(wacom, settings_dword);
} else if (!memcmp(wacom->data_rec, "~C", 2)) {
fifo8_push_all(&wacom->data, (const uint8_t *) "~C5039,3779\r", sizeof("~C5039,3779\r") - 1);
} else if (!memcmp(wacom->data_rec, "~R", 2)) {
uint8_t data[256] = { 0 };
snprintf((char *)data, sizeof(data), (const char *) "~*%08X,%d,%d,%d,%d\r", wacom->settings, wacom->increment, wacom->interval, wacom->x_res, wacom->y_res);
fifo8_push_all(&wacom->data, data, strlen((const char *) data));
}
}
}
}
static int
wacom_poll(void *priv)
{
mouse_wacom_t *wacom = (mouse_wacom_t *) priv;
int delta_x;
int delta_y;
int b = mouse_get_buttons_ex();
double abs_x;
double abs_y;
mouse_subtract_coords(&delta_x, &delta_y, NULL, NULL, -32768, 32767, 0, 0);
mouse_get_abs_coords(&abs_x, &abs_y);
if (wacom->settings_bits.cmd_set == WACOM_CMDSET_IV) {
wacom->abs_x = abs_x * 5039. * (wacom->x_res / 1000.);
wacom->abs_y = abs_y * 3779. * (wacom->y_res / 1000.);
} else {
wacom->abs_x = abs_x * (wacom->measurement ? 4566. : 5800.);
wacom->abs_y = abs_y * (wacom->measurement ? 2972. : 3774.);
if (wacom->abs_x > (wacom->measurement ? 4566 : 5800))
wacom->abs_x = (wacom->measurement ? 4566 : 5800);
if (wacom->abs_y > (wacom->measurement ? 2972 : 3774))
wacom->abs_x = (wacom->measurement ? 2972 : 3774);
if (wacom->abs_x < 0)
wacom->abs_x = 0;
if (wacom->abs_y < 0)
wacom->abs_y = 0;
wacom->rel_x = delta_x;
wacom->rel_y = delta_y;
}
if (wacom->b != b)
wacom->oldb = wacom->b;
wacom->b = b;
return 0;
}
static int
wacom_switch_off_to_on(int b, int oldb)
{
if (!(oldb & 0x1) && (b & 1))
return 1;
if (!(oldb & 0x2) && (b & 2))
return 1;
if (!(oldb & 0x4) && (b & 4))
return 1;
return 0;
}
static uint8_t
wacom_get_switch(int b)
{
if (b & 0x4)
return 0x23;
if (b & 0x2)
return 0x22;
if (b & 0x1)
return 0x21;
return 0x00;
}
static void
wacom_transmit_prepare(mouse_wacom_t *wacom, int x, int y)
{
if (wacom->transmit_id) {
uint8_t data[128] = { 0 };
snprintf((char *) data, sizeof(data), "%s", wacom->tablet_type->id);
fifo8_push_all(&wacom->data, data, strlen((char *)data));
wacom->transmit_id = 0;
return;
}
wacom->last_abs_x = wacom->abs_x;
wacom->last_abs_y = wacom->abs_y;
wacom->remote_req = 0;
wacom->oldb = wacom->b;
if (wacom->settings_bits.output_format == 0) {
uint8_t data[7];
data[0] = 0xC0;
if (wacom->settings_bits.cmd_set == WACOM_CMDSET_IV) {
if (tablet_tool_type == 0)
data[6] = ((wacom->b & 0x1) ? (uint8_t) 31 : (uint8_t) -1);
else
data[6] = ((wacom->b & 0x1) ? (uint8_t) 63 : (uint8_t) -63);
}
else
data[6] = (wacom->pressure_mode || wacom->settings_bits.cmd_set == WACOM_CMDSET_IV) ? ((wacom->b & 0x1) ? (uint8_t) 31 : (uint8_t) -31) : wacom_get_switch(wacom->b);
data[5] = (y & 0x7F);
data[4] = ((y & 0x3F80) >> 7) & 0x7F;
data[3] = (((y & 0xC000) >> 14) & 3);
data[2] = (x & 0x7F);
data[1] = ((x & 0x3F80) >> 7) & 0x7F;
data[0] |= (((x & 0xC000) >> 14) & 3);
if (mouse_input_mode == 0 && wacom->settings_bits.cmd_set == WACOM_CMDSET_IIS) {
data[0] |= (!!(x < 0)) << 2;
data[3] |= (!!(y < 0)) << 2;
}
if (wacom->settings_bits.cmd_set == WACOM_CMDSET_IV) {
data[6] &= 0x7F;
data[3] &= 0x3;
if (wacom_get_switch(wacom->b) != 0x21) {
data[3] |= (wacom_get_switch(wacom->b) & 0xF) << 3;
data[0] |= 0x8;
}
}
if (wacom->pressure_mode && wacom->settings_bits.cmd_set == WACOM_CMDSET_IIS) {
data[0] |= 0x10;
data[6] &= 0x7F;
}
if (tablet_tool_type == 1) {
data[0] |= 0x20;
}
if (!mouse_tablet_in_proximity) {
data[0] &= ~0x40;
}
fifo8_push_all(&wacom->data, data, 7);
} else {
uint8_t data[128];
data[0] = 0;
snprintf((char *) data, sizeof(data), "*,%05d,%05d,%d\r\n",
wacom->abs_x, wacom->abs_y,
wacom->pressure_mode ? ((wacom->b & 0x1) ? (uint8_t) -31 : (uint8_t) 15) : ((wacom->b & 0x1) ? 21 : 00));
fifo8_push_all(&wacom->data, data, strlen((char *)data));
}
}
extern double cpuclock;
static void
wacom_report_timer(void *priv)
{
mouse_wacom_t *wacom = (mouse_wacom_t *) priv;
double milisecond_diff = ((double) (tsc - wacom->old_tsc)) / cpuclock * 1000.0;
int relative_mode = (mouse_input_mode == 0);
int x = (relative_mode ? wacom->rel_x : wacom->abs_x);
int y = (relative_mode ? wacom->rel_y : wacom->abs_y);
int x_diff = abs(relative_mode ? wacom->rel_x : (wacom->abs_x - wacom->last_abs_x));
int y_diff = abs(relative_mode ? wacom->rel_y : (wacom->abs_y - wacom->last_abs_y));
int increment = wacom->suppressed_increment ? wacom->suppressed_increment : wacom->increment;
timer_on_auto(&wacom->report_timer, wacom->transmit_period);
if ((((double) (tsc - wacom->reset_tsc)) / cpuclock * 1000.0) <= 10)
return;
if (wacom->transmit_id)
goto transmit_prepare;
if (fifo8_num_used(&wacom->data))
goto transmit;
else if (wacom->settings_bits.remote_mode && !wacom->remote_req)
return;
else {
if (wacom->settings_bits.remote_mode && wacom->remote_req) {
goto transmit_prepare;
}
if (wacom->transmission_stopped || (!mouse_tablet_in_proximity && !wacom->settings_bits.out_of_range_data))
return;
if (milisecond_diff >= (wacom->interval * 5)) {
wacom->old_tsc = tsc;
} else
return;
switch (wacom->mode) {
default:
case WACOM_MODE_STREAM:
break;
case WACOM_MODE_POINT:
{
if (wacom->suppressed_increment)
break;
if (!(wacom_switch_off_to_on(wacom->b, wacom->oldb)))
return;
break;
}
case WACOM_MODE_SWITCH:
{
if (!wacom->b)
return;
break;
}
}
if (increment && !mouse_tablet_in_proximity)
return;
if (increment && !(x_diff > increment || y_diff > increment)) {
if (wacom->suppressed_increment && (wacom->b == wacom->oldb))
return;
if (wacom->increment && !wacom_switch_off_to_on(wacom->b, wacom->oldb))
return;
}
}
transmit_prepare:
wacom_transmit_prepare(wacom, x, y);
transmit:
serial_write_fifo(wacom->serial, fifo8_pop(&wacom->data));
if (fifo8_num_used(&wacom->data) == 0) {
wacom->old_tsc = tsc;
}
return;
}
static void *
wacom_init(const device_t *info)
{
mouse_wacom_t *dev;
dev = (mouse_wacom_t *) calloc(1, sizeof(mouse_wacom_t));
dev->name = info->name;
dev->but = 3;
dev->bits = 10;
if (info->local == 0) {
dev->tablet_type = &sd510_id;
} else
dev->tablet_type = (wacom_tablet_id*)info->local;
fifo8_create(&dev->data, 512);
dev->port = device_get_config_int("port");
dev->serial = serial_attach(dev->port, wacom_callback, wacom_write, dev);
timer_add(&dev->report_timer, wacom_report_timer, dev, 0);
mouse_set_buttons(dev->but);
if (dev->tablet_type->type == WACOM_TYPE_IV) {
wacom_reset_artpad(dev);
wacom_process_settings_dword(dev, 0xE2018000);
}
else wacom_reset(dev);
return dev;
}
static void
wacom_speed_changed(void *priv)
{
mouse_wacom_t *dev = (mouse_wacom_t *) priv;
wacom_callback(dev->serial, dev);
}
static void
wacom_close(void *priv)
{
mouse_wacom_t *dev = (mouse_wacom_t *) priv;
fifo8_destroy(&dev->data);
/* Detach serial port from the mouse. */
if (dev && dev->serial && dev->serial->sd)
memset(dev->serial->sd, 0, sizeof(serial_device_t));
free(dev);
}
static const device_config_t wacom_config[] = {
// clang-format off
{
.name = "port",
.description = "Serial Port",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "COM1", .value = 0 },
{ .description = "COM2", .value = 1 },
{ .description = "COM3", .value = 2 },
{ .description = "COM4", .value = 3 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t mouse_wacom_device = {
.name = "Wacom SD-510C",
.internal_name = "wacom_serial",
.flags = DEVICE_COM,
.local = 0,
.init = wacom_init,
.close = wacom_close,
.reset = NULL,
{ .poll = wacom_poll },
.speed_changed = wacom_speed_changed,
.force_redraw = NULL,
.config = wacom_config
};
const device_t mouse_wacom_artpad_device = {
.name = "Wacom ArtPad",
.internal_name = "wacom_serial_artpad",
.flags = DEVICE_COM,
.local = (uintptr_t)&artpad_id,
.init = wacom_init,
.close = wacom_close,
.reset = NULL,
{ .poll = wacom_poll },
.speed_changed = wacom_speed_changed,
.force_redraw = NULL,
.config = wacom_config
};
``` | /content/code_sandbox/src/device/mouse_wacom_tablet.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,921 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the IBM Expansion Unit (5161).
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/apm.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/machine.h>
typedef struct ibm_5161_t {
uint8_t regs[8];
} ibm_5161_t;
static void
ibm_5161_out(uint16_t port, uint8_t val, void *priv)
{
ibm_5161_t *dev = (ibm_5161_t *) priv;
dev->regs[port & 0x0007] = val;
}
static uint8_t
ibm_5161_in(uint16_t port, void *priv)
{
const ibm_5161_t *dev = (ibm_5161_t *) priv;
uint8_t ret = 0xff;
ret = dev->regs[port & 0x0007];
switch (port) {
case 0x210: /* Write to latch expansion bus data (ED0-ED7) */
/* Read to verify expansion bus data (ED0-ED7) */
break;
case 0x214: /* Write to latch data bus bits (DO - 07) */
/* Read data bus bits (DO - D7) */
break;
case 0x211: /* Read high-order address bits (A8 - A 15) */
case 0x215: /* Read high-order address bits (A8 - A 15) */
ret = (get_last_addr() >> 8) & 0xff;
break;
case 0x212: /* Read low-order address bits (A0 - A7) */
case 0x216: /* Read low-order address bits (A0 - A7) */
ret = get_last_addr() & 0xff;
break;
case 0x213: /* Write 00 to disable expansion unit */
/* Write 01 to enable expansion unit */
/* Read status of expansion unit
00 = enable/disable
01 = wait-state request flag
02-03 = not used
04-07 = switch position
1 = Off
0 = On */
ret = (dev->regs[3] & 0x01) | (((~(0xf - ((mem_size + isa_mem_size) >> 6))) & 0xf) << 4);
break;
default:
break;
}
return ret;
}
static void
ibm_5161_close(void *priv)
{
ibm_5161_t *dev = (ibm_5161_t *) priv;
free(dev);
}
static void *
ibm_5161_init(UNUSED(const device_t *info))
{
ibm_5161_t *dev = (ibm_5161_t *) calloc(1, sizeof(ibm_5161_t));
/* Extender Card Registers */
io_sethandler(0x0210, 0x0004,
ibm_5161_in, NULL, NULL, ibm_5161_out, NULL, NULL, dev);
/* Receiver Card Registers */
io_sethandler(0x0214, 0x0003,
ibm_5161_in, NULL, NULL, ibm_5161_out, NULL, NULL, dev);
return dev;
}
const device_t ibm_5161_device = {
.name = "IBM Expansion Unit (5161)",
.internal_name = "ibm_5161",
.flags = DEVICE_ISA,
.local = 0,
.init = ibm_5161_init,
.close = ibm_5161_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/device/ibm_5161.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,013 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the ICS9xxx series of clock generators.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#define HAVE_STDARG_H
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/i2c.h>
#include "cpu.h"
#include <86box/clock.h>
#include <86box/plat_unused.h>
#ifdef ENABLE_ICS9xxx_LOG
int ics9xxx_do_log = ENABLE_ICS9xxx_LOG;
static void
ics9xxx_log(const char *fmt, ...)
{
va_list ap;
if (ics9xxx_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
# define ICS9xxx_MODEL(model) [model] = { .name = # model,
#else
# define ics9xxx_log(fmt, ...)
# define ICS9xxx_MODEL(model) [model] = {
#endif
#define ICS9xxx_MODEL_END() \
} \
,
#define agp_div ram_mult /* temporarily saves space while neither field matters */
typedef struct ics9xxx_frequency_t {
uint16_t bus : 15;
uint8_t ram_mult : 2; /* change to full float when this becomes useful */
uint8_t pci_div : 3;
} ics9xxx_frequency_t;
typedef struct ics9xxx_model_t {
#if defined(ENABLE_ICS9xxx_LOG) || defined(ENABLE_ICS9xxx_DETECT)
const char *name; /* populated by macro */
#endif
uint8_t max_reg : 3; /* largest register index */
uint8_t regs[7]; /* default registers */
struct fs_regs { /* for each hardware frequency select bit [FS0:FS4]: */
uint8_t normal_reg : 3; /* which register (or -1) for non-inverted input (FSn) */
uint8_t normal_bit : 3; /* which bit (0-7) for non-inverted input (FSn) */
uint8_t inv_reg : 3; /* which register (or -1) for inverted input (FSn#) */
uint8_t inv_bit : 3; /* which bit (0-7) for inverted input (FSn#) */
} fs_regs[5];
uint8_t normal_bits_fixed : 1; /* set to 1 if the non-inverted bits are straps (hardware select only) */
struct hw_select { /* hardware select bit, which should be cleared for hardware select (latched inputs), or set for programming */
uint8_t normal_reg : 3; /* which register (or -1) */
uint8_t normal_bit : 3; /* which bit (0-7) */
} hw_select;
uint8_t frequencies_ref; /* which other model to use the frequency table from (or 0) */
const ics9xxx_frequency_t *frequencies; /* frequency table, if not using another model's table */
} ics9xxx_model_t;
typedef struct ics9xxx_t {
uint8_t model_idx;
ics9xxx_model_t *model;
device_t *dyn_device;
ics9xxx_frequency_t *frequencies_ptr;
uint8_t regs[7];
int8_t addr_register : 4;
uint8_t relevant_regs : 7;
uint8_t bus_match : 5;
} ics9xxx_t;
static const ics9xxx_model_t ics9xxx_models[] = {
#ifdef ENABLE_ICS9xxx_DETECT
ICS9xxx_MODEL(ICS9xxx_xx)
.max_reg
= 6 ICS9xxx_MODEL_END()
#endif
ICS9xxx_MODEL(ICS9150_08)
.max_reg = 5,
.regs = {0x00, 0xff, 0xff, 0xff, 0x6f, 0xbf},
.fs_regs = {{0, 4, 4, 7}, {0, 5, 4, 4}, {0, 6, 5, 6}, {0, 7, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 5000, .pci_div = 2},
{.bus = 7500, .pci_div = 2},
{.bus = 8333, .pci_div = 2},
{.bus = 6680, .pci_div = 2},
{.bus = 10300, .pci_div = 3},
{.bus = 11200, .pci_div = 3},
{.bus = 13333, .pci_div = 4},
{.bus = 10020, .pci_div = 3},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_39)
.max_reg = 5,
.regs = {0x00, 0x7f, 0xff, 0xbf, 0xf5, 0xff},
.fs_regs = {{0, 4, 3, 6}, {0, 5, 4, 3}, {0, 6, 1, 7}, {0, 7, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies_ref = ICS9250_08
ICS9xxx_MODEL_END()
#ifdef ENABLE_ICS9xxx_DETECT
ICS9xxx_MODEL(ICS9248_81)
.max_reg = 5,
.regs = {0x82, 0xfe, 0x7f, 0xff, 0xff, 0xb7},
.fs_regs = {{0, 4, 1, 0}, {0, 5, 2, 7}, {0, 6, 5, 6}, {0, 2, 5, 3}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 9000, .ram_mult = 1, .pci_div = 3},
{.bus = 6670, .ram_mult = 1.5, .pci_div = 2},
{.bus = 9500, .ram_mult = 2.0/3.0, .pci_div = 3},
{.bus = 10000, .ram_mult = 2.0/3.0, .pci_div = 3},
{.bus = 10000, .ram_mult = 0.75, .pci_div = 3},
{.bus = 11200, .ram_mult = 2.0/3.0, .pci_div = 3},
{.bus = 12400, .ram_mult = 2.0/3.0, .pci_div = 4},
{.bus = 13330, .ram_mult = 2.0/3.0, .pci_div = 4},
{.bus = 6670, .ram_mult = 1, .pci_div = 2},
{.bus = 7500, .ram_mult = 1, .pci_div = 3},
{.bus = 8330, .ram_mult = 1, .pci_div = 3},
{.bus = 9500, .ram_mult = 1, .pci_div = 3},
{.bus = 10000, .ram_mult = 1, .pci_div = 3},
{.bus = 11200, .ram_mult = 1, .pci_div = 3},
{.bus = 12400, .ram_mult = 1, .pci_div = 4},
{.bus = 13330, .ram_mult = 1, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_95)
.max_reg = 5,
.regs = {0x82, 0xff, 0xff, 0xff, 0xd5, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 2, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .pci_div = 2},
{.bus = 10000, .pci_div = 3},
{.bus = 10030, .pci_div = 3},
{.bus = 13333, .pci_div = 4},
{.bus = 10500, .pci_div = 3},
{.bus = 13337, .pci_div = 4},
{.bus = 13700, .pci_div = 4},
{.bus = 7500, .pci_div = 2},
{.bus = 10000, .pci_div = 3},
{.bus = 9500, .pci_div = 2},
{.bus = 9700, .pci_div = 3},
{.bus = 13333, .pci_div = 4},
{.bus = 9000, .pci_div = 3},
{.bus = 9622, .pci_div = 3},
{.bus = 6681, .pci_div = 2},
{.bus = 9150, .pci_div = 3},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_98)
.max_reg = 6,
.regs = {0x00, 0x7f, 0xff, 0xbf, 0xf5, 0xff, 0x06},
.fs_regs = {{0, 4, 3, 6}, {0, 5, 4, 3}, {0, 6, 1, 7}, {0, 7, 4, 1}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 8000, .pci_div = 2},
{.bus = 7500, .pci_div = 2},
{.bus = 8331, .pci_div = 2},
{.bus = 6682, .pci_div = 2},
{.bus = 10300, .pci_div = 3},
{.bus = 11201, .pci_div = 3},
{.bus = 6801, .pci_div = 2},
{.bus = 10023, .pci_div = 3},
{.bus = 12000, .pci_div = 3},
{.bus = 11499, .pci_div = 3},
{.bus = 10999, .pci_div = 3},
{.bus = 10500, .pci_div = 3},
{.bus = 14000, .pci_div = 4},
{.bus = 15000, .pci_div = 4},
{.bus = 12400, .pci_div = 4},
{.bus = 13299, .pci_div = 4},
{.bus = 13500, .pci_div = 4},
{.bus = 12999, .pci_div = 4},
{.bus = 12600, .pci_div = 4},
{.bus = 11800, .pci_div = 3},
{.bus = 11598, .pci_div = 3},
{.bus = 9500, .pci_div = 3},
{.bus = 9000, .pci_div = 3},
{.bus = 8501, .pci_div = 3},
{.bus = 16600, .pci_div = 4},
{.bus = 16001, .pci_div = 4},
{.bus = 15499, .pci_div = 4},
{.bus = 14795, .pci_div = 4},
{.bus = 14598, .pci_div = 4},
{.bus = 14398, .pci_div = 4},
{.bus = 14199, .pci_div = 4},
{.bus = 13801, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_101)
.max_reg = 5,
.regs = {0x82, 0xff, 0xff, 0xff, 0xf5, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 2, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 12400, .pci_div = 3},
{.bus = 12000, .pci_div = 3},
{.bus = 11499, .pci_div = 3},
{.bus = 10999, .pci_div = 3},
{.bus = 10500, .pci_div = 3},
{.bus = 8331, .pci_div = 2},
{.bus = 13700, .pci_div = 4},
{.bus = 7500, .pci_div = 2},
{.bus = 10000, .pci_div = 3},
{.bus = 9500, .pci_div = 3},
{.bus = 8331, .pci_div = 3},
{.bus = 13333, .pci_div = 4},
{.bus = 9000, .pci_div = 3},
{.bus = 9622, .pci_div = 3},
{.bus = 6682, .pci_div = 2},
{.bus = 9150, .pci_div = 3},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_103)
.max_reg = 5,
.regs = {0x82, 0xff, 0xff, 0xff, 0xf5, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 2, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies_ref = ICS9248_101
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_107)
.max_reg = 6,
.regs = {0x02, 0xff, 0xff, 0xec, 0xde, 0xff, 0x06},
.fs_regs = {{0, 4, 4, 5}, {0, 5, 3, 4}, {0, 6, 3, 0}, {0, 7, 3, 1}, {0, 2, 4, 0}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 10300, .pci_div = 3},
{.bus = 10000, .pci_div = 3},
{.bus = 10045, .pci_div = 3},
{.bus = 10090, .pci_div = 3},
{.bus = 10710, .pci_div = 2},
{.bus = 10900, .pci_div = 3},
{.bus = 11200, .pci_div = 3},
{.bus = 11400, .pci_div = 4},
{.bus = 11600, .pci_div = 4},
{.bus = 11800, .pci_div = 4},
{.bus = 13330, .pci_div = 3},
{.bus = 12000, .pci_div = 4},
{.bus = 12200, .pci_div = 4},
{.bus = 12500, .pci_div = 4},
{.bus = 5000, .pci_div = 2},
{.bus = 6670, .pci_div = 4},
{.bus = 13330, .pci_div = 3},
{.bus = 13390, .pci_div = 3},
{.bus = 13800, .pci_div = 4},
{.bus = 14200, .pci_div = 4},
{.bus = 14600, .pci_div = 4},
{.bus = 15000, .pci_div = 4},
{.bus = 15300, .pci_div = 4},
{.bus = 15600, .pci_div = 4},
{.bus = 15910, .pci_div = 3},
{.bus = 16200, .pci_div = 4},
{.bus = 16670, .pci_div = 4},
{.bus = 16800, .pci_div = 4},
{.bus = 17100, .pci_div = 4},
{.bus = 17400, .pci_div = 4},
{.bus = 17700, .pci_div = 4},
{.bus = 18000, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_112)
.max_reg = 6,
.regs = {0x02, 0x1f, 0xff, 0xff, 0xfb, 0xff, 0x06},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6680, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6800, .ram_mult = 1.5, .pci_div = 2},
{.bus = 10030, .ram_mult = 1, .pci_div = 3},
{.bus = 10300, .ram_mult = 1, .pci_div = 3},
{.bus = 13372, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14500, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13372, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13733, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14000, .ram_mult = 1, .pci_div = 2},
{.bus = 11800, .ram_mult = 1, .pci_div = 3},
{.bus = 12400, .ram_mult = 1, .pci_div = 3},
{.bus = 13369, .ram_mult = 1, .pci_div = 2},
{.bus = 13700, .ram_mult = 1, .pci_div = 2},
{.bus = 15000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 7250, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7500, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8300, .ram_mult = 1, .pci_div = 6},
{.bus = 11000, .ram_mult = 1, .pci_div = 2},
{.bus = 12000, .ram_mult = 1, .pci_div = 3},
{.bus = 12500, .ram_mult = 1, .pci_div = 2},
{.bus = 6925, .ram_mult = 1.5, .pci_div = 1},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 14500, .ram_mult = 1, .pci_div = 3},
{.bus = 6650, .ram_mult = 1.5, .pci_div = 2},
{.bus = 15000, .ram_mult = 1, .pci_div = 3},
{.bus = 9975, .ram_mult = 1, .pci_div = 3},
{.bus = 15500, .ram_mult = 1, .pci_div = 2},
{.bus = 16650, .ram_mult = 1, .pci_div = 3},
{.bus = 15333, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13300, .ram_mult = 0.75, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_138)
.max_reg = 6,
.regs = {0x02, 0x3f, 0x7f, 0x6f, 0xff, 0xff, 0x06},
.fs_regs = {{0, 4, 2, 7}, {0, 5, 1, 6}, {0, 6, 1, 7}, {0, 7, 3, 4}, {0, 2, 3, 7}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6687, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6867, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7134, .ram_mult = 1.5, .pci_div = 2},
{.bus = 10000, .ram_mult = 1, .pci_div = 3},
{.bus = 10030, .ram_mult = 1, .pci_div = 3},
{.bus = 10300, .ram_mult = 1, .pci_div = 3},
{.bus = 10700, .ram_mult = 1, .pci_div = 2},
{.bus = 13333, .ram_mult = 1, .pci_div = 4},
{.bus = 13372, .ram_mult = 1, .pci_div = 4},
{.bus = 13733, .ram_mult = 1, .pci_div = 4},
{.bus = 12000, .ram_mult = 1, .pci_div = 4},
{.bus = 13333, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13372, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13733, .ram_mult = 0.75, .pci_div = 4},
{.bus = 12000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13600, .ram_mult = 1, .pci_div = 4},
{.bus = 14000, .ram_mult = 1, .pci_div = 4},
{.bus = 14266, .ram_mult = 1, .pci_div = 3},
{.bus = 14533, .ram_mult = 1, .pci_div = 4},
{.bus = 13600, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14266, .ram_mult = 0.75, .pci_div = 3},
{.bus = 14533, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14666, .ram_mult = 1, .pci_div = 3},
{.bus = 15333, .ram_mult = 1, .pci_div = 4},
{.bus = 16000, .ram_mult = 1, .pci_div = 4},
{.bus = 16667, .ram_mult = 1, .pci_div = 3},
{.bus = 14666, .ram_mult = 0.75, .pci_div = 3},
{.bus = 16000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 16667, .ram_mult = 0.75, .pci_div = 3},
{.bus = 20000, .ram_mult = 1, .pci_div = 6},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_141)
.max_reg = 6,
.regs = {0x02, 0x6b, 0x7f, 0xff, 0xff, 0xe7, 0x06},
.fs_regs = {{0, 4, 2, 7}, {0, 5, 5, 3}, {0, 6, 1, 7}, {0, 7, 1, 4}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 9000, .pci_div = 3},
{.bus = 9500, .pci_div = 2},
{.bus = 10100, .pci_div = 2},
{.bus = 10200, .pci_div = 3},
{.bus = 10090, .pci_div = 3},
{.bus = 10300, .pci_div = 3},
{.bus = 10500, .pci_div = 3},
{.bus = 10000, .pci_div = 3},
{.bus = 10700, .pci_div = 2},
{.bus = 10900, .pci_div = 3},
{.bus = 11000, .pci_div = 2},
{.bus = 11100, .pci_div = 3},
{.bus = 11300, .pci_div = 2},
{.bus = 11500, .pci_div = 3},
{.bus = 11700, .pci_div = 3},
{.bus = 13330, .pci_div = 3},
{.bus = 12000, .pci_div = 3},
{.bus = 12500, .pci_div = 4},
{.bus = 13000, .pci_div = 4},
{.bus = 13372, .pci_div = 4},
{.bus = 13500, .pci_div = 4},
{.bus = 13700, .pci_div = 4},
{.bus = 13900, .pci_div = 4},
{.bus = 10000, .pci_div = 3},
{.bus = 14000, .pci_div = 4},
{.bus = 14300, .pci_div = 4},
{.bus = 14500, .pci_div = 4},
{.bus = 14800, .pci_div = 4},
{.bus = 15000, .pci_div = 4},
{.bus = 15500, .pci_div = 4},
{.bus = 16666, .pci_div = 3},
{.bus = 13333, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_143)
.max_reg = 5,
.regs = {0x82, 0xff, 0xff, 0xff, 0xd5, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 2, 4, 1}, {-1, -1, -1, -1}},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .pci_div = 2},
{.bus = 10000, .pci_div = 3},
{.bus = 10030, .pci_div = 3},
{.bus = 13333, .pci_div = 4},
{.bus = 10500, .pci_div = 3},
{.bus = 13337, .pci_div = 4},
{.bus = 13700, .pci_div = 4},
{.bus = 7500, .pci_div = 2},
{.bus = 10000, .pci_div = 3},
{.bus = 9500, .pci_div = 2},
{.bus = 9700, .pci_div = 3},
{.bus = 13333, .pci_div = 4},
{.bus = 9000, .pci_div = 3},
{.bus = 9622, .pci_div = 3},
{.bus = 6681, .pci_div = 2},
{.bus = 9150, .pci_div = 3},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_151)
.max_reg = 6,
.regs = {0x80, 0x4f, 0xff, 0x3f, 0xff, 0xff, 0x06},
.fs_regs = {{0, 4, -1, -1}, {0, 5, -1, -1}, {0, 6, 3, 7}, {0, 1, 1, 4}, {0, 2, 1, 5}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 20000, .pci_div = 5, .agp_div = 2.5},
{.bus = 19000, .pci_div = 5, .agp_div = 2.5},
{.bus = 18000, .pci_div = 5, .agp_div = 2.5},
{.bus = 17000, .pci_div = 5, .agp_div = 2.5},
{.bus = 16600, .pci_div = 5, .agp_div = 2.5},
{.bus = 16000, .pci_div = 5, .agp_div = 2.5},
{.bus = 15000, .pci_div = 4, .agp_div = 2},
{.bus = 14500, .pci_div = 4, .agp_div = 2},
{.bus = 14000, .pci_div = 4, .agp_div = 2},
{.bus = 13600, .pci_div = 4, .agp_div = 2},
{.bus = 13000, .pci_div = 4, .agp_div = 2},
{.bus = 12400, .pci_div = 4, .agp_div = 2},
{.bus = 6667, .pci_div = 1, .agp_div = 1},
{.bus = 10000, .pci_div = 3, .agp_div = 1.5},
{.bus = 11800, .pci_div = 3, .agp_div = 1.5},
{.bus = 13333, .pci_div = 3, .agp_div = 2},
{.bus = 6680, .pci_div = 2, .agp_div = 1},
{.bus = 10020, .pci_div = 3, .agp_div = 1.5},
{.bus = 11500, .pci_div = 3, .agp_div = 1.5},
{.bus = 13340, .pci_div = 4, .agp_div = 2},
{.bus = 6680, .pci_div = 2, .agp_div = 1},
{.bus = 10020, .pci_div = 3, .agp_div = 1.5},
{.bus = 11000, .pci_div = 2, .agp_div = 1.5},
{.bus = 13340, .pci_div = 4, .agp_div = 2},
{.bus = 10500, .pci_div = 3, .agp_div = 1.5},
{.bus = 9000, .pci_div = 3, .agp_div = 1.5},
{.bus = 8500, .pci_div = 3, .agp_div = 1.5},
{.bus = 7800, .pci_div = 2, .agp_div = 1},
{.bus = 6667, .pci_div = 1, .agp_div = 1},
{.bus = 10000, .pci_div = 3, .agp_div = 1.5},
{.bus = 7500, .pci_div = 2, .agp_div = 1},
{.bus = 13333, .pci_div = 3, .agp_div = 2},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9248_192)
.max_reg = 6,
.regs = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 7, -1, -1}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6000, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
{.bus = 6659, .pci_div = 2},
{.bus = 6659, .pci_div = 2},
{.bus = 6659, .pci_div = 2},
{.bus = 6659, .pci_div = 2},
{.bus = 6731, .pci_div = 2},
{.bus = 6864, .pci_div = 2},
{.bus = 6995, .pci_div = 2},
{.bus = 7259, .pci_div = 2},
{.bus = 6150, .pci_div = 2},
{.bus = 6300, .pci_div = 2},
{.bus = 6400, .pci_div = 2},
{.bus = 6500, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
{.bus = 6659, .pci_div = 2},
{.bus = 5000, .pci_div = 2},
{.bus = 4800, .pci_div = 2},
{.bus = 5880, .pci_div = 2},
{.bus = 5760, .pci_div = 2},
{.bus = 5640, .pci_div = 2},
{.bus = 5400, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
{.bus = 6659, .pci_div = 2},
{.bus = 6659, .pci_div = 2},
{.bus = 6659, .pci_div = 2},
{.bus = 6659, .pci_div = 2},
{0}
}
ICS9xxx_MODEL_END()
#endif
ICS9xxx_MODEL(ICS9250_08)
.max_reg = 5,
.regs = {0x00, 0xff, 0xff, 0xff, 0x6d, 0xbf},
.fs_regs = {{0, 4, 4, 7}, {0, 5, 4, 4}, {0, 6, 5, 6}, {0, 2, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 12400, .pci_div = 3},
{.bus = 7500, .pci_div = 2},
{.bus = 8333, .pci_div = 2},
{.bus = 6680, .pci_div = 2},
{.bus = 10300, .pci_div = 3},
{.bus = 11200, .pci_div = 3},
{.bus = 13300, .pci_div = 3},
{.bus = 10030, .pci_div = 3},
{.bus = 12000, .pci_div = 3},
{.bus = 11500, .pci_div = 3},
{.bus = 11000, .pci_div = 3},
{.bus = 10500, .pci_div = 3},
{.bus = 14000, .pci_div = 4},
{.bus = 15000, .pci_div = 4},
{.bus = 12400, .pci_div = 4},
{.bus = 13300, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
#ifdef ENABLE_ICS9xxx_DETECT
ICS9xxx_MODEL(ICS9250_10)
.max_reg = 5,
.regs = {0x1f, 0xff, 0xfe, 0x00, 0x00, 0x06},
.fs_regs = {{5, 0, -1, -1}, {5, 3, -1, -1}, {5, 4, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7067, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7466, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8266, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6350, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6867, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7267, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8866, .ram_mult = 1.5, .pci_div = 2},
{.bus = 10000, .ram_mult = 1, .pci_div = 3},
{.bus = 10600, .ram_mult = 1, .pci_div = 3},
{.bus = 11200, .ram_mult = 1, .pci_div = 3},
{.bus = 12400, .ram_mult = 1, .pci_div = 3},
{.bus = 9525, .ram_mult = 1, .pci_div = 3},
{.bus = 10300, .ram_mult = 1, .pci_div = 3},
{.bus = 10900, .ram_mult = 1, .pci_div = 3},
{.bus = 13300, .ram_mult = 1, .pci_div = 3},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_13)
.max_reg = 5,
.regs = {0x82, 0xcf, 0x7f, 0xff, 0xff, 0xf7},
.fs_regs = {{0, 4, 1, 4}, {0, 5, 5, 7}, {0, 6, 1, 5}, {0, 2, 2, 7}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 9000, .ram_mult = 1, .pci_div = 2},
{.bus = 8901, .ram_mult = 1, .pci_div = 2},
{.bus = 8800, .ram_mult = 1, .pci_div = 2},
{.bus = 8699, .ram_mult = 1, .pci_div = 2},
{.bus = 8591, .ram_mult = 1, .pci_div = 2},
{.bus = 8501, .ram_mult = 1, .pci_div = 2},
{.bus = 8400, .ram_mult = 1, .pci_div = 2},
{.bus = 8200, .ram_mult = 1, .pci_div = 2},
{.bus = 8101, .ram_mult = 1, .pci_div = 2},
{.bus = 8000, .ram_mult = 1, .pci_div = 2},
{.bus = 8331, .ram_mult = 1, .pci_div = 2},
{.bus = 6849, .ram_mult = 1, .pci_div = 2},
{.bus = 7800, .ram_mult = 1, .pci_div = 2},
{.bus = 7500, .ram_mult = 1, .pci_div = 2},
{.bus = 7199, .ram_mult = 1, .pci_div = 2},
{.bus = 6682, .ram_mult = 1, .pci_div = 2},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_14)
.max_reg = 5,
.regs = {0x02, 0x1f, 0xff, 0xff, 0xeb, 0xff},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6781, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7201, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7301, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7500, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7700, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7801, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8300, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8449, .ram_mult = 1.5, .pci_div = 2},
{.bus = 10000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8608, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8800, .ram_mult = 1.5, .pci_div = 2},
{.bus = 9000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 9500, .ram_mult = 1.5, .pci_div = 2},
{.bus = 4990, .ram_mult = 1, .pci_div = 3},
{.bus = 10000, .ram_mult = 1, .pci_div = 3},
{.bus = 7485, .ram_mult = 1, .pci_div = 3},
{.bus = 6658, .ram_mult = 1, .pci_div = 3},
{.bus = 8284, .ram_mult = 1, .pci_div = 3},
{.bus = 8981, .ram_mult = 1, .pci_div = 3},
{.bus = 9480, .ram_mult = 1, .pci_div = 3},
{.bus = 10050, .ram_mult = 1, .pci_div = 3},
{.bus = 10478, .ram_mult = 1, .pci_div = 3},
{.bus = 11177, .ram_mult = 1, .pci_div = 3},
{.bus = 11477, .ram_mult = 1, .pci_div = 3},
{.bus = 10000, .ram_mult = 1, .pci_div = 3},
{.bus = 12375, .ram_mult = 1, .pci_div = 3},
{.bus = 13274, .ram_mult = 1, .pci_div = 3},
{.bus = 13975, .ram_mult = 1, .pci_div = 3},
{.bus = 14969, .ram_mult = 1, .pci_div = 3},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_16)
.max_reg = 5,
.regs = {0x1f, 0xff, 0xff, 0x00, 0x00, 0x06},
.fs_regs = {{5, 0, -1, -1}, {5, 3, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7267, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7467, .ram_mult = 1.5, .pci_div = 2},
{.bus = 10000, .ram_mult = 1, .pci_div = 3},
{.bus = 10500, .ram_mult = 1, .pci_div = 3},
{.bus = 10900, .ram_mult = 1, .pci_div = 3},
{.bus = 11201, .ram_mult = 1, .pci_div = 3},
{.bus = 13334, .ram_mult = 1, .pci_div = 3},
{.bus = 14000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 12000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 12400, .ram_mult = 1, .pci_div = 3},
{.bus = 13334, .ram_mult = 0.75, .pci_div = 4},
{.bus = 15000, .ram_mult = 1, .pci_div = 4},
{.bus = 14000, .ram_mult = 1, .pci_div = 4},
{.bus = 13299, .ram_mult = 1, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
#endif
ICS9xxx_MODEL(ICS9250_18)
.max_reg = 5,
.regs = {0x02, 0xff, 0xff, 0xff, 0x6d, 0xbf},
.fs_regs = {{0, 4, 4, 7}, {0, 5, 4, 4}, {0, 6, 5, 6}, {0, 7, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 8000, .pci_div = 2},
{.bus = 7500, .pci_div = 2},
{.bus = 8331, .pci_div = 2},
{.bus = 6690, .pci_div = 2},
{.bus = 10300, .pci_div = 3},
{.bus = 11201, .pci_div = 3},
{.bus = 6801, .pci_div = 2},
{.bus = 10070, .pci_div = 3},
{.bus = 12000, .pci_div = 3},
{.bus = 11499, .pci_div = 3},
{.bus = 10999, .pci_div = 3},
{.bus = 10500, .pci_div = 3},
{.bus = 14000, .pci_div = 4},
{.bus = 15000, .pci_div = 4},
{.bus = 12400, .pci_div = 4},
{.bus = 13390, .pci_div = 4},
{.bus = 13500, .pci_div = 4},
{.bus = 12999, .pci_div = 4},
{.bus = 12600, .pci_div = 4},
{.bus = 11800, .pci_div = 4},
{.bus = 11598, .pci_div = 4},
{.bus = 9500, .pci_div = 3},
{.bus = 9000, .pci_div = 3},
{.bus = 8501, .pci_div = 3},
{.bus = 16600, .pci_div = 4},
{.bus = 16001, .pci_div = 4},
{.bus = 15499, .pci_div = 4},
{.bus = 14795, .pci_div = 4},
{.bus = 14598, .pci_div = 4},
{.bus = 14398, .pci_div = 4},
{.bus = 14199, .pci_div = 4},
{.bus = 13801, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
#ifdef ENABLE_ICS9xxx_DETECT
ICS9xxx_MODEL(ICS9250_19)
.max_reg = 5,
.regs = {0x02, 0xff, 0xff, 0xff, 0x6d, 0xbf},
.fs_regs = {{0, 4, 4, 7}, {0, 5, 4, 4}, {0, 6, 5, 6}, {0, 7, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies_ref = ICS9250_08
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_23)
.max_reg = 5,
.regs = {0x02, 0x1f, 0xff, 0xff, 0xeb, 0xff},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6900, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7100, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6690, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7200, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7500, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7660, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8500, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6800, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7400, .ram_mult = 1.5, .pci_div = 2},
{.bus = 14000, .ram_mult = 1, .pci_div = 4},
{.bus = 13333, .ram_mult = 1, .pci_div = 4},
{.bus = 15000, .ram_mult = 1, .pci_div = 4},
{.bus = 15500, .ram_mult = 1, .pci_div = 4},
{.bus = 16600, .ram_mult = 1, .pci_div = 4},
{.bus = 16600, .ram_mult = 1, .pci_div = 3},
{.bus = 11177, .ram_mult = 1, .pci_div = 3},
{.bus = 10478, .ram_mult = 1, .pci_div = 3},
{.bus = 10951, .ram_mult = 1, .pci_div = 3},
{.bus = 10090, .ram_mult = 1, .pci_div = 3},
{.bus = 11700, .ram_mult = 1, .pci_div = 3},
{.bus = 12375, .ram_mult = 1, .pci_div = 3},
{.bus = 13333, .ram_mult = 1, .pci_div = 3},
{.bus = 14250, .ram_mult = 1, .pci_div = 3},
{.bus = 13600, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14300, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13390, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14667, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14933, .ram_mult = 0.75, .pci_div = 4},
{.bus = 15330, .ram_mult = 0.75, .pci_div = 4},
{.bus = 16667, .ram_mult = 0.75, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_25)
.max_reg = 6,
.regs = {0x02, 0x1f, 0xff, 0xff, 0xeb, 0xff, 0x06},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 5500, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6680, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6833, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7200, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7500, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7700, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8330, .ram_mult = 1, .pci_div = 3},
{.bus = 9000, .ram_mult = 1, .pci_div = 3},
{.bus = 10030, .ram_mult = 1, .pci_div = 3},
{.bus = 10300, .ram_mult = 1, .pci_div = 3},
{.bus = 11250, .ram_mult = 1, .pci_div = 3},
{.bus = 11500, .ram_mult = 1, .pci_div = 3},
{.bus = 12000, .ram_mult = 1, .pci_div = 3},
{.bus = 12500, .ram_mult = 1, .pci_div = 3},
{.bus = 12800, .ram_mult = 1, .pci_div = 4},
{.bus = 13000, .ram_mult = 1, .pci_div = 4},
{.bus = 13370, .ram_mult = 1, .pci_div = 4},
{.bus = 13700, .ram_mult = 1, .pci_div = 4},
{.bus = 14000, .ram_mult = 1, .pci_div = 4},
{.bus = 14500, .ram_mult = 1, .pci_div = 4},
{.bus = 15000, .ram_mult = 1, .pci_div = 4},
{.bus = 15333, .ram_mult = 1, .pci_div = 4},
{.bus = 12500, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13370, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13700, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14500, .ram_mult = 0.75, .pci_div = 4},
{.bus = 15000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 15333, .ram_mult = 0.75, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_26)
.max_reg = 5,
.regs = {0x1e, 0xff, 0xff, 0x00, 0x00, 0x06},
.fs_regs = {{5, 0, -1, -1}, {5, 3, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies_ref = ICS9250_16
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_27)
.max_reg = 5,
.regs = {0x0f, 0xff, 0xfe, 0x00, 0x00, 0x00},
.fs_regs = {{-1, -1, -1, -1}, {-1, -1, -1, -1}, {3, 0, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6666, .ram_mult = 1.5, .pci_div = 2},
{.bus = 13332, .ram_mult = 1, .pci_div = 4},
{.bus = 10000, .ram_mult = 1, .pci_div = 3},
{.bus = 13332, .ram_mult = 0.75, .pci_div = 4},
{.bus = 6666, .ram_mult = 1.5, .pci_div = 2},
{.bus = 13332, .ram_mult = 1, .pci_div = 4},
{.bus = 10000, .ram_mult = 1, .pci_div = 3},
{.bus = 13332, .ram_mult = 1, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_28)
.max_reg = 4,
.regs = {0x1e, 0xff, 0xfe, 0x00, 0x00},
.fs_regs = {{-1, -1, -1, -1}, {-1, -1, -1, -1}, {3, 0, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies_ref = ICS9250_27
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_29)
.max_reg = 5,
.regs = {0x16, 0xff, 0xfe, 0x00, 0x00, 0x00},
.fs_regs = {{-1, -1, -1, -1}, {-1, -1, -1, -1}, {3, 0, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies_ref = ICS9250_27
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_30)
.max_reg = 6,
.regs = {0x02, 0x0f, 0xff, 0xff, 0xeb, 0xff, 0x06},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6680, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6833, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7500, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 8300, .ram_mult = 1.5, .pci_div = 2},
{.bus = 10000, .ram_mult = 1, .pci_div = 3},
{.bus = 9000, .ram_mult = 1, .pci_div = 3},
{.bus = 10030, .ram_mult = 1, .pci_div = 3},
{.bus = 10300, .ram_mult = 1, .pci_div = 3},
{.bus = 10500, .ram_mult = 1, .pci_div = 3},
{.bus = 11000, .ram_mult = 1, .pci_div = 3},
{.bus = 11500, .ram_mult = 1, .pci_div = 3},
{.bus = 20000, .ram_mult = 1, .pci_div = 6},
{.bus = 13333, .ram_mult = 1, .pci_div = 4},
{.bus = 16667, .ram_mult = 1, .pci_div = 4},
{.bus = 13370, .ram_mult = 1, .pci_div = 4},
{.bus = 13700, .ram_mult = 1, .pci_div = 4},
{.bus = 14000, .ram_mult = 1, .pci_div = 4},
{.bus = 14500, .ram_mult = 1, .pci_div = 4},
{.bus = 15000, .ram_mult = 1, .pci_div = 4},
{.bus = 16000, .ram_mult = 1, .pci_div = 4},
{.bus = 13333, .ram_mult = 0.75, .pci_div = 4},
{.bus = 16667, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13370, .ram_mult = 0.75, .pci_div = 4},
{.bus = 13700, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 14500, .ram_mult = 0.75, .pci_div = 4},
{.bus = 15000, .ram_mult = 0.75, .pci_div = 4},
{.bus = 16000, .ram_mult = 0.75, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_32)
.max_reg = 4,
.regs = {0x07, 0xff, 0xff, 0x00, 0x00},
.fs_regs = {{-1, -1, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_38)
.max_reg = 6,
.regs = {0x18, 0x07, 0xfe, 0xc7, 0xfc, 0x00, 0x80},
.fs_regs = {{0, 0, -1, -1}, {0, 1, -1, -1}, {0, 2, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.normal_bits_fixed = 1,
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6666, .ram_mult = 1, .pci_div = 1},
{.bus = 10000, .ram_mult = 2.0/3.0, .pci_div = 3},
{.bus = 20000, .ram_mult = 1.0/3.0, .pci_div = 6},
{.bus = 13333, .ram_mult = 0.5, .pci_div = 2},
{.bus = 6666, .ram_mult = 1, .pci_div = 1},
{.bus = 10000, .ram_mult = 2.0/3.0, .pci_div = 3},
{.bus = 20000, .ram_mult = 1.0/3.0, .pci_div = 6},
{.bus = 13333, .ram_mult = 0.5, .pci_div = 2},
{0}
}
ICS9xxx_MODEL_END()
ICS9xxx_MODEL(ICS9250_50)
.max_reg = 6,
.regs = {0x02, 0x6f, 0xff, 0xff, 0xef, 0xff, 0x06},
.fs_regs = {{-1, -1, 1, 6}, {-1, -1, 4, 2}, {-1, -1, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (const ics9xxx_frequency_t[]) {
[0 ... 7] = {.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
[8 ... 15] = {.bus = 10000, .ram_mult = 1, .pci_div = 3},
[16 ... 23] = {.bus = 13333, .ram_mult = 1, .pci_div = 4},
[24 ... 31] = {.bus = 13333, .ram_mult = 0.75, .pci_div = 4},
{0}
}
ICS9xxx_MODEL_END()
#endif
};
/* Don't enable the detection device here. Enable it further up near logging. */
#ifdef ENABLE_ICS9xxx_DETECT
static uint16_t detect_bus = 0;
static uint8_t detect_reg = 0;
static uint8_t discarded[ICS9xxx_MAX] = { 0 };
static void
ics9xxx_detect_reset(void *priv)
{
pclog("Please enter the frequency set in the BIOS (7500 for 75.00 MHz)\nAnswer 0 if unsure or set to auto, I'll ask again next reset.\n");
scanf("%hu", &detect_bus);
if ((detect_bus > 0) && (detect_bus < 1000))
detect_bus *= 100;
pclog("Frequency interpreted as %d\n", detect_bus);
}
static void
ics9xxx_detect(ics9xxx_t *dev)
{
if (!detect_bus) {
pclog("Frequency not entered on this reset, ignoring change.\n");
return;
}
if ((detect_reg == 0) && (dev->regs[detect_reg] >= 0xfe)) {
pclog("Register %d set to %02X, probably not it, trying %d instead\n", detect_reg, dev->regs[detect_reg], 3);
detect_reg = 3;
dev->relevant_regs = 1 << detect_reg;
return;
}
if (!(dev->regs[detect_reg] & 0x40))
pclog("Bit 3 of register %d is clear, probably in hardware select mode!\n", detect_reg);
uint8_t i = 0;
uint8_t matches = 0;
uint8_t val;
uint8_t bitmask;
ics9xxx_frequency_t *frequencies_ptr;
uint32_t delta;
for (uint8_t j = 0; j < ICS9xxx_MAX; j++) {
if (discarded[j])
continue;
discarded[j] = 1;
frequencies_ptr = (ics9xxx_frequency_t *) ics9xxx_models[ics9xxx_models[j].frequencies_ref ? ics9xxx_models[j].frequencies_ref : j].frequencies;
if (!frequencies_ptr)
continue;
while (frequencies_ptr[i].bus) {
delta = ABS((int32_t) (detect_bus - frequencies_ptr[i].bus));
if (delta <= 100) {
val = bitmask = 0;
for (uint8_t k = 0; k < sizeof(ics9xxx_models[j].fs_regs) / sizeof(ics9xxx_models[j].fs_regs[0]); k++) {
if (ics9xxx_models[j].fs_regs[k].normal_reg == detect_reg) {
bitmask |= 1 << k;
val |= (1 << k) * !!(dev->regs[detect_reg] & (1 << ics9xxx_models[j].fs_regs[k].normal_bit));
}
}
if (bitmask && (val == (i & bitmask))) {
matches++;
discarded[j] = 0;
pclog("> Potential match for %s (frequency %d index %d)\n", ics9xxx_models[j].name, frequencies_ptr[i].bus, val);
}
}
i++;
}
}
pclog("Found a total of %d matches for register %d value %02X and bus frequency %d\n", matches, detect_reg, dev->regs[detect_reg], detect_bus);
if (matches == 0) {
pclog("Resetting list of discarded models since there were no matches.\n");
memset(discarded, 0, sizeof(discarded));
}
}
#endif
static uint8_t
ics9xxx_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
{
ics9xxx_t *dev = (ics9xxx_t *) priv;
ics9xxx_log("ICS9xxx: start()\n");
dev->addr_register = -2; /* -2 = command; -1 = SMBus block length; 0+ = registers */
return 1;
}
static uint8_t
ics9xxx_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
{
ics9xxx_t *dev = (ics9xxx_t *) priv;
uint8_t ret = 0xff;
if (dev->addr_register < 0) {
dev->addr_register = -1;
ret = dev->model->max_reg + 1;
}
#if 0
else if ((dev->model_idx == ICS9250_50) && (dev->addr_register == 0))
ret = dev->regs[dev->addr_register] & 0x0b; /* -50 reads back revision ID instead */
#endif
else
ret = dev->regs[dev->addr_register];
#ifdef ENABLE_ICS9xxx_LOG
if (dev->addr_register < 0)
ics9xxx_log("ICS9xxx: read(%s) = %02X\n", (dev->addr_register == -1) ? "blocklen" : "command", ret);
else
ics9xxx_log("ICS9xxx: read(%x) = %02X\n", dev->addr_register, ret);
#endif
if (dev->addr_register >= dev->model->max_reg)
dev->addr_register = 0; /* roll-over */
else
dev->addr_register++;
return ret;
}
static void
ics9xxx_set(ics9xxx_t *dev, uint8_t val)
{
/* Get the active mode, which determines what to add to the static frequency bits we were passed. */
uint8_t hw_select = (dev->model->hw_select.normal_reg < 7) && !(dev->regs[dev->model->hw_select.normal_reg] & (1 << dev->model->hw_select.normal_bit));
if (hw_select) {
/* Hardware select mode: add strapped frequency bits. */
val |= dev->bus_match;
} else {
/* Programmable mode: add register-defined frequency bits. */
for (uint8_t i = 0; i < sizeof(dev->model->fs_regs) / sizeof(dev->model->fs_regs[0]); i++) {
if ((dev->model->fs_regs[i].normal_reg < 7) && (dev->regs[dev->model->fs_regs[i].normal_reg] & (1 << dev->model->fs_regs[i].normal_bit)))
val |= 1 << i;
}
}
uint16_t bus = dev->frequencies_ptr[val].bus;
uint32_t pci = bus / dev->frequencies_ptr[val].pci_div;
cpu_set_pci_speed(pci * 10000);
ics9xxx_log("ICS9xxx: set(%d) = hw=%d bus=%d ram=%d pci=%d\n", val, hw_select, bus, bus * dev->frequencies_ptr[val].ram_mult, pci);
}
static uint8_t
ics9xxx_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t data, void *priv)
{
ics9xxx_t *dev = (ics9xxx_t *) priv;
#ifdef ENABLE_ICS9xxx_LOG
if (dev->addr_register < 0)
ics9xxx_log("ICS9xxx: write(%s, %02X)\n", (dev->addr_register == -1) ? "blocklen" : "command", data);
else
ics9xxx_log("ICS9xxx: write(%x, %02X)\n", dev->addr_register, data);
#endif
if (dev->addr_register >= 0) {
/* Preserve fixed bits. */
#ifdef ENABLE_ICS9xxx_DETECT
if (dev->model != ICS9xxx_xx)
#endif
{
for (uint8_t i = 0; i < sizeof(dev->model->fs_regs) / sizeof(dev->model->fs_regs[0]); i++) {
if (dev->model->normal_bits_fixed && (dev->model->fs_regs[i].normal_reg == dev->addr_register))
data = (dev->regs[dev->addr_register] & (1 << dev->model->fs_regs[i].normal_bit)) | (data & ~(1 << dev->model->fs_regs[i].normal_bit));
if (dev->model->fs_regs[i].inv_reg == dev->addr_register)
data = (dev->regs[dev->addr_register] & (1 << dev->model->fs_regs[i].inv_bit)) | (data & ~(1 << dev->model->fs_regs[i].inv_bit));
}
}
#if 0
switch (dev->addr_register) {
case 0:
if (dev->model_idx == ICS9250_38)
data = (dev->regs[dev->addr_register] & ~0xe8) | (data & 0xe8);
break;
case 1:
if (dev->model_idx == ICS9250_38)
data = (dev->regs[dev->addr_register] & ~0xfe) | (data & 0xfe);
break;
case 3:
if (dev->model_idx == ICS9250_32)
data ^= 0x70;
break;
case 4:
if (dev->model_idx == ICS9250_38)
data = (dev->regs[dev->addr_register] & ~0xfc) | (data & 0xfc);
break;
case 6:
if (dev->model_idx == ICS9250_38) /* read-only */
data = dev->regs[dev->addr_register];
break;
}
#endif
dev->regs[dev->addr_register] = data;
/* Update frequency if a relevant register was written to. */
if (dev->relevant_regs & (1 << dev->addr_register)) {
switch (dev->model_idx) {
#ifdef ENABLE_ICS9xxx_DETECT
case ICS9xxx_xx:
ics9xxx_detect(dev);
break;
#endif
#if 0
case ICS9250_10:
ics9xxx_set(dev, (cpu_busspeed >= 100000000) * 0x08);
break;
case ICS9250_16:
case ICS9250_26:
ics9xxx_set(dev, ((cpu_busspeed >= 120000000) * 0x08) | ((((cpu_busspeed >= 100000000) && (cpu_busspeed < 120000000)) || (cpu_busspeed == 150000000) || (cpu_busspeed == 132999999)) * 0x04));
break;
case ICS9250_27:
case ICS9250_28:
case ICS9250_29:
ics9xxx_set(dev, ((cpu_busspeed == 100000000) * 0x02) | ((cpu_busspeed > 100000000) * 0x01));
break;
#endif
default:
ics9xxx_set(dev, 0x00);
break;
}
}
}
if (dev->addr_register >= dev->model->max_reg)
dev->addr_register = 0; /* roll-over */
else
dev->addr_register++;
return 1;
}
static uint8_t
ics9xxx_find_bus_match(ics9xxx_t *dev, uint32_t bus, uint8_t preset_mask, uint8_t preset)
{
uint8_t best_match = 0;
uint32_t delta;
uint32_t best_delta = -1;
#ifdef ENABLE_ICS9xxx_DETECT
if (dev->model_idx == ICS9xxx_xx)
return 0;
#endif
bus /= 10000;
uint8_t i = 0;
while (dev->frequencies_ptr[i].bus) {
if ((i & preset_mask) == preset) {
delta = ABS((int32_t) (bus - dev->frequencies_ptr[i].bus));
if (delta < best_delta) {
best_match = i;
best_delta = delta;
}
}
i++;
}
ics9xxx_log("ICS9xxx: find_match(%s, %d) = match=%d bus=%d\n", dev->model->name, bus, best_match, dev->frequencies_ptr[best_match].bus);
return best_match;
}
static void *
ics9xxx_init(const device_t *info)
{
ics9xxx_t *dev = (ics9xxx_t *) malloc(sizeof(ics9xxx_t));
memset(dev, 0, sizeof(ics9xxx_t));
dev->model_idx = info->local;
dev->model = (ics9xxx_model_t *) &ics9xxx_models[dev->model_idx];
dev->dyn_device = (device_t *) info;
memcpy(&dev->regs, &dev->model->regs, dev->model->max_reg + 1);
ics9xxx_log("ICS9xxx: init(%s)\n", dev->model->name);
uint8_t i;
#ifdef ENABLE_ICS9xxx_DETECT
for (i = ICS9xxx_xx + 1; i < ICS9xxx_MAX; i++) {
if (ics9xxx_models[i].frequencies_ref || !ics9xxx_models[i].name)
continue;
for (uint8_t j = 0; j < i; j++) {
if (ics9xxx_models[j].frequencies_ref || !ics9xxx_models[j].name)
continue;
if (!memcmp(&ics9xxx_models[i].frequencies, &ics9xxx_models[j].frequencies, sizeof(ics9xxx_models[i].frequencies)))
pclog("Optimization warning: %s and %s have duplicate tables\n", ics9xxx_models[j].name, ics9xxx_models[i].name);
}
}
if (dev->model_idx == ICS9xxx_xx) { /* detection device */
dev->relevant_regs = 1 << 0; /* register 0 matters the most on the detection device */
ics9xxx_detect_reset(dev);
} else
#endif
{ /* regular device */
dev->frequencies_ptr = (ics9xxx_frequency_t *) (dev->model->frequencies_ref ? ics9xxx_models[dev->model->frequencies_ref].frequencies : dev->model->frequencies);
if (!dev->frequencies_ptr)
fatal("ICS9xxx: NULL frequency table\n");
/* Determine which frequency bits cannot be strapped (register only). */
uint8_t register_only_bits = 0x00;
for (i = 0; i < sizeof(dev->model->fs_regs) / sizeof(dev->model->fs_regs[0]); i++) {
if (!dev->model->normal_bits_fixed && (dev->model->fs_regs[i].normal_reg < 7)) /* mark a normal, programmable bit as relevant */
dev->relevant_regs |= 1 << dev->model->fs_regs[i].normal_reg;
if ((dev->model->fs_regs[i].normal_reg == 7) && (dev->model->fs_regs[i].inv_reg == 7)) /* mark as register only */
register_only_bits |= 1 << i;
}
/* Mark the hardware select bit's register as relevant, if there's one. */
if (dev->model->hw_select.normal_reg < 7)
dev->relevant_regs |= 1 << dev->model->hw_select.normal_reg;
/* Find bus speed match and set default register bits accordingly. */
dev->bus_match = ics9xxx_find_bus_match(dev, cpu_busspeed, register_only_bits, 0x00);
for (i = 0; i < sizeof(dev->model->fs_regs) / sizeof(dev->model->fs_regs[0]); i++) {
if (dev->model->fs_regs[i].normal_reg < 7) {
if (dev->bus_match & (1 << i))
dev->regs[dev->model->fs_regs[i].normal_reg] |= 1 << dev->model->fs_regs[i].normal_bit;
else
dev->regs[dev->model->fs_regs[i].normal_reg] &= ~(1 << dev->model->fs_regs[i].normal_bit);
}
if (dev->model->fs_regs[i].inv_reg < 7) {
if (dev->bus_match & (1 << i))
dev->regs[dev->model->fs_regs[i].inv_reg] &= ~(1 << dev->model->fs_regs[i].inv_bit);
else
dev->regs[dev->model->fs_regs[i].inv_reg] |= 1 << dev->model->fs_regs[i].inv_bit;
}
}
}
i2c_sethandler(i2c_smbus, 0x69, 1, ics9xxx_start, ics9xxx_read, ics9xxx_write, NULL, dev);
return dev;
}
static void
ics9xxx_close(void *priv)
{
ics9xxx_t *dev = (ics9xxx_t *) priv;
ics9xxx_log("ICS9xxx: close()\n");
i2c_removehandler(i2c_smbus, 0x69, 1, ics9xxx_start, ics9xxx_read, ics9xxx_write, NULL, dev);
free(dev->dyn_device);
free(dev);
}
device_t *
ics9xxx_get(uint8_t model)
{
device_t *dev = (device_t *) malloc(sizeof(device_t));
memset(dev, 0, sizeof(device_t));
dev->name = "ICS9xxx-xx Clock Generator";
dev->local = model;
dev->flags = DEVICE_ISA;
#ifdef ENABLE_ICS9xxx_DETECT
if (model == ICS9xxx_xx)
dev->reset = ics9xxx_detect_reset;
#endif
dev->init = ics9xxx_init;
dev->close = ics9xxx_close;
return dev;
}
``` | /content/code_sandbox/src/device/clock_ics9xxx.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 20,752 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Bus Mouse devices.
*
* These devices were made by both Microsoft and Logitech. At
* first, Microsoft used the same protocol as Logitech, but did
* switch to their new protocol for their InPort interface. So,
* although alike enough to be handled in the same driver, they
* are not the same.
*
* NOTES: Ported from Bochs with extensive modifications per testing
* of the real hardware, testing of drivers, and the old code.
*
* Logitech Bus Mouse verified with:
* Linux Slackware 3.0
* Logitech LMouse.com 3.12
* Logitech LMouse.com 3.30
* Logitech LMouse.com 3.41
* Logitech LMouse.com 3.42
* Logitech LMouse.com 4.00
* Logitech LMouse.com 5.00
* Logitech LMouse.com 6.00
* Logitech LMouse.com 6.02 Beta
* Logitech LMouse.com 6.02
* Logitech LMouse.com 6.12
* Logitech LMouse.com 6.20
* Logitech LMouse.com 6.23
* Logitech LMouse.com 6.30
* Logitech LMouse.com 6.31E
* Logitech LMouse.com 6.34
* Logitech Mouse.exe 6.40
* Logitech Mouse.exe 6.41
* Logitech Mouse.exe 6.44
* Logitech Mouse.exe 6.46
* Logitech Mouse.exe 6.50
* Microsoft Mouse.com 2.00
* Microsoft Mouse.sys 3.00
* Microsoft Mouse.com 7.04
* Microsoft Mouse.com 8.21J
* Microsoft Windows 1.00 DR5
* Microsoft Windows 3.10.026
* Microsoft Windows 3.10.068 both MOUSE.DRV and LMOUSE.DRV
* Microsoft Windows NT 3.1
* Microsoft Windows 95
*
* InPort verified with:
* Linux Slackware 3.0
* Logitech LMouse.com 6.12
* Logitech LMouse.com 6.41
* Microsoft Windows 3.10.068 both MOUSE.DRV and LMOUSE.DRV
* Microsoft Windows NT 3.1
* Microsoft Windows 98 SE
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdatomic.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/mouse.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/random.h>
#define IRQ_MASK ((1 << 5) >> dev->irq)
/* MS Inport Bus Mouse Adapter */
#define INP_PORT_CONTROL 0x0000
#define INP_PORT_DATA 0x0001
#define INP_PORT_SIGNATURE 0x0002
#define INP_PORT_CONFIG 0x0003
#define INP_CTRL_READ_BUTTONS 0x00
#define INP_CTRL_READ_X 0x01
#define INP_CTRL_READ_Y 0x02
#define INP_CTRL_COMMAND 0x07
#define INP_CTRL_RAISE_IRQ 0x16
#define INP_CTRL_RESET 0x80
#define INP_HOLD_COUNTER (1 << 5)
#define INP_ENABLE_TIMER_IRQ (1 << 4)
#define INP_ENABLE_DATA_IRQ (1 << 3)
#define INP_PERIOD_MASK 0x07
/* MS/Logictech Standard Bus Mouse Adapter */
#define BUSM_PORT_DATA 0x0000
#define BUSM_PORT_SIGNATURE 0x0001
#define BUSM_PORT_CONTROL 0x0002
#define BUSM_PORT_CONFIG 0x0003
#define HOLD_COUNTER (1 << 7)
#define READ_X (0 << 6)
#define READ_Y (1 << 6)
#define READ_LOW (0 << 5)
#define READ_HIGH (1 << 5)
#define DISABLE_IRQ (1 << 4)
#define DEVICE_ACTIVE (1 << 7)
#define READ_X_LOW (READ_X | READ_LOW)
#define READ_X_HIGH (READ_X | READ_HIGH)
#define READ_Y_LOW (READ_Y | READ_LOW)
#define READ_Y_HIGH (READ_Y | READ_HIGH)
#define FLAG_INPORT (1 << 0)
#define FLAG_ENABLED (1 << 1)
#define FLAG_HOLD (1 << 2)
#define FLAG_TIMER_INT (1 << 3)
#define FLAG_DATA_INT (1 << 4)
static const uint8_t periods[4] = { 30, 50, 100, 200 };
/* Our mouse device. */
typedef struct mouse {
uint8_t current_b;
uint8_t control_val;
uint8_t config_val;
uint8_t sig_val;
uint8_t command_val;
uint8_t pad;
int8_t current_x;
int8_t current_y;
int base;
int irq;
int bn;
int flags;
int mouse_buttons;
int mouse_buttons_last;
int toggle_counter;
int timer_enabled;
double period;
pc_timer_t timer; /* mouse event timer */
} mouse_t;
#ifdef ENABLE_MOUSE_BUS_LOG
int bm_do_log = ENABLE_MOUSE_BUS_LOG;
static void
bm_log(const char *fmt, ...)
{
va_list ap;
if (bm_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define bm_log(fmt, ...)
#endif
/* Handle a READ operation from one of our registers. */
static uint8_t
lt_read(uint16_t port, void *priv)
{
mouse_t *dev = (mouse_t *) priv;
uint8_t value = 0xff;
switch (port & 0x03) {
case BUSM_PORT_DATA:
/* Testing and another source confirm that the buttons are
*ALWAYS* present, so I'm going to change this a bit. */
switch (dev->control_val & 0x60) {
case READ_X_LOW:
value = dev->current_x & 0x0F;
dev->current_x &= ~0x0F;
break;
case READ_X_HIGH:
value = (dev->current_x >> 4) & 0x0F;
dev->current_x &= ~0xF0;
break;
case READ_Y_LOW:
value = dev->current_y & 0x0F;
dev->current_y &= ~0x0F;
break;
case READ_Y_HIGH:
value = (dev->current_y >> 4) & 0x0F;
dev->current_y &= ~0xF0;
break;
default:
bm_log("ERROR: Reading data port in unsupported mode 0x%02x\n", dev->control_val);
}
value |= ((dev->current_b ^ 7) << 5);
break;
case BUSM_PORT_SIGNATURE:
value = dev->sig_val;
break;
case BUSM_PORT_CONTROL:
value = dev->control_val;
dev->control_val |= 0x0F;
/* If the conditions are right, simulate the flakiness of the correct IRQ bit. */
if (dev->flags & FLAG_TIMER_INT)
dev->control_val = (dev->control_val & ~IRQ_MASK) | (random_generate() & IRQ_MASK);
break;
case BUSM_PORT_CONFIG:
/* Read from config port returns control_val in the upper 4 bits when enabled,
possibly solid interrupt readout in the lower 4 bits, 0xff when not (at power-up). */
if (dev->flags & FLAG_ENABLED)
return (dev->control_val | 0x0F) & ~IRQ_MASK;
else
return 0xff;
default:
break;
}
bm_log("DEBUG: read from address 0x%04x, value = 0x%02x\n", port, value);
return value;
}
static uint8_t
ms_read(uint16_t port, void *priv)
{
mouse_t *dev = (mouse_t *) priv;
uint8_t value = 0xff;
switch (port & 0x03) {
case INP_PORT_CONTROL:
value = dev->control_val;
break;
case INP_PORT_DATA:
switch (dev->command_val) {
case INP_CTRL_READ_BUTTONS:
value = dev->current_b;
break;
case INP_CTRL_READ_X:
value = dev->current_x;
dev->current_x = 0;
break;
case INP_CTRL_READ_Y:
value = dev->current_y;
dev->current_y = 0;
break;
case INP_CTRL_COMMAND:
value = dev->control_val;
break;
default:
bm_log("ERROR: Reading data port in unsupported mode 0x%02x\n", dev->control_val);
}
break;
case INP_PORT_SIGNATURE:
if (dev->toggle_counter)
value = 0x12;
else
value = 0xDE;
dev->toggle_counter ^= 1;
break;
case INP_PORT_CONFIG:
bm_log("ERROR: Unsupported read from port 0x%04x\n", port);
break;
default:
break;
}
bm_log("DEBUG: read from address 0x%04x, value = 0x%02x\n", port, value);
return value;
}
/* Handle a WRITE operation to one of our registers. */
static void
lt_write(uint16_t port, uint8_t val, void *priv)
{
mouse_t *dev = (mouse_t *) priv;
uint8_t bit;
bm_log("DEBUG: write to address 0x%04x, value = 0x%02x\n", port, val);
switch (port & 0x03) {
case BUSM_PORT_DATA:
bm_log("ERROR: Unsupported write to port 0x%04x (value = 0x%02x)\n", port, val);
break;
case BUSM_PORT_SIGNATURE:
dev->sig_val = val;
break;
case BUSM_PORT_CONTROL:
dev->control_val = val | 0x0F;
if (!(val & DISABLE_IRQ))
dev->flags |= FLAG_TIMER_INT;
else
dev->flags &= ~FLAG_TIMER_INT;
if (val & HOLD_COUNTER)
dev->flags |= FLAG_HOLD;
else
dev->flags &= ~FLAG_HOLD;
if (dev->irq != -1)
picintc(1 << dev->irq);
break;
case BUSM_PORT_CONFIG:
/*
* The original Logitech design was based on using a
* 8255 parallel I/O chip. This chip has to be set up
* for proper operation, and this configuration data
* is what is programmed into this register.
*
* A snippet of code found in the FreeBSD kernel source
* explains the value:
*
* D7 = Mode set flag (1 = active)
* This indicates the mode of operation of D7:
* 1 = Mode set, 0 = Bit set/reset
* D6,D5 = Mode selection (port A)
* 00 = Mode 0 = Basic I/O
* 01 = Mode 1 = Strobed I/O
* 10 = Mode 2 = Bi-dir bus
* D4 = Port A direction (1 = input)
* D3 = Port C (upper 4 bits) direction. (1 = input)
* D2 = Mode selection (port B & C)
* 0 = Mode 0 = Basic I/O
* 1 = Mode 1 = Strobed I/O
* D1 = Port B direction (1 = input)
* D0 = Port C (lower 4 bits) direction. (1 = input)
*
* So 91 means Basic I/O on all 3 ports, Port A is an input
* port, B is an output port, C is split with upper 4 bits
* being an output port and lower 4 bits an input port, and
* enable the sucker. Courtesy Intel 8255 databook. Lars
*
* 1001 1011 9B 1111 Default state
* 1001 0001 91 1001 Driver-initialized state
* The only difference is - port C upper and port B go from
* input to output.
*/
if (val & DEVICE_ACTIVE) {
/* Mode set/reset - enable this */
dev->config_val = val;
if (dev->timer_enabled)
dev->flags |= (FLAG_ENABLED | FLAG_TIMER_INT);
else
dev->flags |= FLAG_ENABLED;
dev->control_val = 0x0F & ~IRQ_MASK;
} else {
/* Single bit set/reset */
bit = 1 << ((val >> 1) & 0x07); /* Bits 3-1 specify the target bit */
if (val & 1)
dev->control_val |= bit; /* Set */
else
dev->control_val &= ~bit; /* Reset */
}
break;
default:
break;
}
}
/* Handle a WRITE operation to one of our registers. */
static void
ms_write(uint16_t port, uint8_t val, void *priv)
{
mouse_t *dev = (mouse_t *) priv;
bm_log("DEBUG: write to address 0x%04x, value = 0x%02x\n", port, val);
switch (port & 0x03) {
case INP_PORT_CONTROL:
/* Bit 7 is reset. */
if (val & INP_CTRL_RESET)
dev->control_val = 0;
/* Bits 0-2 are the internal register index. */
switch (val & 0x07) {
case INP_CTRL_COMMAND:
case INP_CTRL_READ_BUTTONS:
case INP_CTRL_READ_X:
case INP_CTRL_READ_Y:
dev->command_val = val & 0x07;
break;
default:
bm_log("ERROR: Unsupported command written to port 0x%04x (value = 0x%02x)\n", port, val);
}
break;
case INP_PORT_DATA:
if (dev->irq != -1)
picintc(1 << dev->irq);
switch (dev->command_val) {
case INP_CTRL_COMMAND:
if (val & INP_HOLD_COUNTER)
dev->flags |= FLAG_HOLD;
else
dev->flags &= ~FLAG_HOLD;
if (val & INP_ENABLE_TIMER_IRQ)
dev->flags |= FLAG_TIMER_INT;
else
dev->flags &= ~FLAG_TIMER_INT;
if (val & INP_ENABLE_DATA_IRQ)
dev->flags |= FLAG_DATA_INT;
else
dev->flags &= ~FLAG_DATA_INT;
switch (val & INP_PERIOD_MASK) {
case 0:
dev->period = 0.0;
timer_disable(&dev->timer);
dev->timer_enabled = 0;
break;
case 1:
case 2:
case 3:
case 4:
dev->period = (1000000.0 / (double) periods[(val & INP_PERIOD_MASK) - 1]);
dev->timer_enabled = (val & INP_ENABLE_TIMER_IRQ) ? 1 : 0;
timer_disable(&dev->timer);
if (dev->timer_enabled)
timer_set_delay_u64(&dev->timer, (uint64_t) (dev->period * (double) TIMER_USEC));
bm_log("DEBUG: Timer is now %sabled at period %i\n", (val & INP_ENABLE_TIMER_IRQ) ? "en" : "dis", (int32_t) dev->period);
break;
case 6:
if ((val & INP_ENABLE_TIMER_IRQ) && (dev->irq != -1))
picint(1 << dev->irq);
dev->control_val &= INP_PERIOD_MASK;
dev->control_val |= (val & ~INP_PERIOD_MASK);
return;
default:
bm_log("ERROR: Unsupported period written to port 0x%04x (value = 0x%02x)\n", port, val);
}
dev->control_val = val;
break;
default:
bm_log("ERROR: Unsupported write to port 0x%04x (value = 0x%02x)\n", port, val);
}
break;
case INP_PORT_SIGNATURE:
case INP_PORT_CONFIG:
bm_log("ERROR: Unsupported write to port 0x%04x (value = 0x%02x)\n", port, val);
break;
default:
break;
}
}
/* The emulator calls us with an update on the host mouse device. */
static int
bm_poll(void *priv)
{
mouse_t *dev = (mouse_t *) priv;
int delta_x;
int delta_y;
int xor;
int b = mouse_get_buttons_ex();
if (!mouse_capture && !video_fullscreen)
return 1;
if (!(dev->flags & FLAG_ENABLED))
return 1; /* Mouse is disabled, do nothing. */
if (!mouse_state_changed()) {
dev->mouse_buttons_last = 0x00;
return 1; /* State has not changed, do nothing. */
}
/* Converts button states from MRL to LMR. */
dev->mouse_buttons = (uint8_t) (((b & 1) << 2) | ((b & 2) >> 1));
if (dev->bn == 3)
dev->mouse_buttons |= ((b & 4) >> 1);
if ((dev->flags & FLAG_INPORT) && !dev->timer_enabled) {
/* This is an InPort mouse in data interrupt mode,
so update bits 6-3 here. */
/* If the mouse has moved, set bit 6. */
if (mouse_moved())
dev->mouse_buttons |= 0x40;
/* Set bits 3-5 according to button state changes. */
xor = ((dev->current_b ^ mouse_get_buttons_ex()) & 0x07) << 3;
dev->mouse_buttons |= xor;
}
dev->mouse_buttons_last = b;
if (!dev->timer_enabled) {
/* If the counters are not frozen, update them. */
if (!(dev->flags & FLAG_HOLD)) {
mouse_subtract_coords(&delta_x, &delta_y, NULL, NULL, -128, 127, 0, 0);
dev->current_x = (int8_t) delta_x;
dev->current_y = (int8_t) delta_y;
dev->current_b = dev->mouse_buttons;
}
/* Send interrupt. */
if ((dev->flags & FLAG_DATA_INT) && (dev->irq != -1)) {
picint(1 << dev->irq);
bm_log("DEBUG: Data Interrupt Fired...\n");
}
}
return 0;
}
/* The timer calls us on every tick if the mouse is in timer mode
(InPort mouse is so configured, MS/Logitech Bus mouse always). */
static void
bm_update_data(mouse_t *dev)
{
int delta_x;
int delta_y;
int xor;
/* If the counters are not frozen, update them. */
if ((mouse_capture || video_fullscreen) && !(dev->flags & FLAG_HOLD)) {
/* Update the deltas and the delays. */
mouse_subtract_coords(&delta_x, &delta_y, NULL, NULL, -128, 127, 0, 0);
dev->current_x = (int8_t) delta_x;
dev->current_y = (int8_t) delta_y;
} else
delta_x = delta_y = 0;
if (dev->flags & FLAG_INPORT) {
/* This is an InPort mouse in timer mode, so update current_b always,
and update bits 6-3 (mouse moved and button state changed) here. */
xor = ((dev->current_b ^ dev->mouse_buttons) & 0x07) << 3;
dev->current_b = (dev->mouse_buttons & 0x87) | xor;
if (delta_x || delta_y)
dev->current_b |= 0x40;
} else if (!(dev->flags & FLAG_HOLD)) {
/* This is a MS/Logitech Bus Mouse, so only update current_b if the
counters are frozen. */
dev->current_b = dev->mouse_buttons;
}
}
/* Called at the configured period (InPort mouse) or 45 times per second (MS/Logitech Bus mouse). */
static void
bm_timer(void *priv)
{
mouse_t *dev = (mouse_t *) priv;
bm_log("DEBUG: Timer Tick (flags=%08X)...\n", dev->flags);
/* The period is configured either via emulator settings (for MS/Logitech Bus mouse)
or via software (for InPort mouse). */
timer_advance_u64(&dev->timer, (uint64_t) (dev->period * (double) TIMER_USEC));
if ((dev->flags & FLAG_TIMER_INT) && (dev->irq != -1)) {
picint(1 << dev->irq);
bm_log("DEBUG: Timer Interrupt Fired...\n");
}
bm_update_data(dev);
}
/* Release all resources held by the device. */
static void
bm_close(void *priv)
{
mouse_t *dev = (mouse_t *) priv;
if (dev)
free(dev);
}
/* Set the mouse's IRQ. */
void
mouse_bus_set_irq(void *priv, int irq)
{
mouse_t *dev = (mouse_t *) priv;
dev->irq = irq;
}
/* Initialize the device for use by the user. */
static void *
bm_init(const device_t *info)
{
mouse_t *dev;
int hz;
dev = (mouse_t *) malloc(sizeof(mouse_t));
memset(dev, 0x00, sizeof(mouse_t));
if ((info->local & ~MOUSE_TYPE_ONBOARD) == MOUSE_TYPE_INPORT)
dev->flags = FLAG_INPORT;
else
dev->flags = 0;
if (info->local & MOUSE_TYPE_ONBOARD) {
dev->base = 0x023c;
dev->irq = -1;
dev->bn = 2;
} else {
dev->base = device_get_config_hex16("base");
dev->irq = device_get_config_int("irq");
dev->bn = device_get_config_int("buttons");
}
mouse_set_buttons(dev->bn);
dev->mouse_buttons = 0;
dev->mouse_buttons_last = 0;
dev->sig_val = 0; /* the signature port value */
dev->current_x = dev->current_y = 0;
dev->current_b = 0;
dev->command_val = 0; /* command byte */
dev->toggle_counter = 0; /* signature byte / IRQ bit toggle */
dev->period = 0.0;
timer_add(&dev->timer, bm_timer, dev, 0);
if (dev->flags & FLAG_INPORT) {
dev->control_val = 0; /* the control port value */
dev->flags |= FLAG_ENABLED;
io_sethandler(dev->base, 4,
ms_read, NULL, NULL, ms_write, NULL, NULL, dev);
dev->timer_enabled = 0;
} else {
dev->control_val = 0x0f; /* the control port value */
dev->config_val = 0x9b; /* the config port value - 0x9b is the
default state of the 8255: all ports
are set to input */
hz = device_get_config_int("hz");
if (hz > 0)
dev->period = (1000000.0 / (double) hz);
io_sethandler(dev->base, 4,
lt_read, NULL, NULL, lt_write, NULL, NULL, dev);
if (hz > 0) {
timer_set_delay_u64(&dev->timer, (uint64_t) (dev->period * (double) TIMER_USEC));
dev->timer_enabled = 1;
} else {
dev->flags |= FLAG_DATA_INT;
dev->timer_enabled = 0;
}
}
if (dev->flags & FLAG_INPORT)
bm_log("MS Inport BusMouse initialized\n");
else
bm_log("Standard MS/Logitech BusMouse initialized\n");
mouse_set_sample_rate(0.0);
return dev;
}
static const device_config_t lt_config[] = {
// clang-format off
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x23c,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "0x230", .value = 0x230 },
{ .description = "0x234", .value = 0x234 },
{ .description = "0x238", .value = 0x238 },
{ .description = "0x23C", .value = 0x23c },
{ .description = "" }
}
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 5,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "" }
}
},
{
.name = "hz",
.description = "Hz",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 45,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Non-timed (original)", .value = 0 },
{ .description = "30 Hz (JMP2 = 1)", .value = 30 },
{ .description = "45 Hz (JMP2 not populated)", .value = 45 },
{ .description = "60 Hz (JMP 2 = 2)", .value = 60 },
{ .description = "" }
}
},
{
.name = "buttons",
.description = "Buttons",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 2,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Two", .value = 2 },
{ .description = "Three", .value = 3 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_config_t ms_config[] = {
// clang-format off
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x23c,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "0x230", .value = 0x230 },
{ .description = "0x234", .value = 0x234 },
{ .description = "0x238", .value = 0x238 },
{ .description = "0x23C", .value = 0x23c },
{ .description = "" }
}
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 5,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "" }
}
},
{
.name = "buttons",
.description = "Buttons",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 2,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Two", .value = 2 },
{ .description = "Three", .value = 3 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t mouse_logibus_device = {
.name = "Logitech/Microsoft Bus Mouse",
.internal_name = "logibus",
.flags = DEVICE_ISA,
.local = MOUSE_TYPE_LOGIBUS,
.init = bm_init,
.close = bm_close,
.reset = NULL,
{ .poll = bm_poll },
.speed_changed = NULL,
.force_redraw = NULL,
.config = lt_config
};
const device_t mouse_logibus_onboard_device = {
.name = "Logitech Bus Mouse (On-Board)",
.internal_name = "logibus_onboard",
.flags = DEVICE_ISA,
.local = MOUSE_TYPE_LOGIBUS | MOUSE_TYPE_ONBOARD,
.init = bm_init,
.close = bm_close,
.reset = NULL,
{ .poll = bm_poll },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t mouse_msinport_device = {
.name = "Microsoft Bus Mouse (InPort)",
.internal_name = "msbus",
.flags = DEVICE_ISA,
.local = MOUSE_TYPE_INPORT,
.init = bm_init,
.close = bm_close,
.reset = NULL,
{ .poll = bm_poll },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ms_config
};
``` | /content/code_sandbox/src/device/mouse_bus.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 7,017 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Common functions for hardware monitoring chips.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/hwm.h>
/* Refer to specific hardware monitor implementations for the meaning of hwm_values. */
hwm_values_t hwm_values;
uint16_t
hwm_get_vcore(void)
{
/* Determine Vcore for the active CPU. */
return cpu_s->voltage;
}
``` | /content/code_sandbox/src/device/hwm.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 223 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Novell NetWare 2.x Key Card, which
* was used for anti-piracy protection.
*
*
* Authors: Cacodemon345
*
*/
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/plat.h>
#include <86box/novell_cardkey.h>
typedef struct novell_cardkey_t
{
char serial_number_str[13];
} novell_cardkey_t;
static uint8_t
novell_cardkey_read(uint16_t port, void *priv)
{
novell_cardkey_t* cardkey = (novell_cardkey_t*)priv;
uint8_t val = 0x00;
switch (port) {
case 0x23A:
val = (((cardkey->serial_number_str[11] > 'A') ? ((cardkey->serial_number_str[11] - 'A') + 10) : (cardkey->serial_number_str[11] - '0')) << 4) | (((cardkey->serial_number_str[9] > 'A') ? ((cardkey->serial_number_str[9] - 'A') + 10) : (cardkey->serial_number_str[9] - '0')) << 4);
break;
case 0x23B:
val = (((cardkey->serial_number_str[10] > 'A') ? ((cardkey->serial_number_str[10] - 'A') + 10) : (cardkey->serial_number_str[10] - '0')) << 4) | (((cardkey->serial_number_str[8] > 'A') ? ((cardkey->serial_number_str[8] - 'A') + 10) : (cardkey->serial_number_str[8] - '0')) << 4);
break;
case 0x23C:
val = ((cardkey->serial_number_str[4] - '0') << 4) | ((cardkey->serial_number_str[2] - '0'));
break;
case 0x23D:
val = ((cardkey->serial_number_str[1] - '0') << 4) | ((cardkey->serial_number_str[6] - '0'));
break;
case 0x23E:
val = ((cardkey->serial_number_str[0] - '0') << 4) | ((cardkey->serial_number_str[7] - '0'));
break;
case 0x23F:
val = ((cardkey->serial_number_str[3] - '0') << 4) | ((cardkey->serial_number_str[5] - '0'));
break;
}
return val ^ 0xFF;
}
void* novell_cardkey_init(const device_t* info)
{
char sernumstr[13] = { '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', 0 };
int i = 0;
novell_cardkey_t* cardkey = calloc(1, sizeof(novell_cardkey_t));
strncpy(sernumstr, device_get_config_string("serial_number"), sizeof(sernumstr) - 1);
for (i = 0; i < sizeof(sernumstr) - 4; i++) {
if (sernumstr[i] > '8' || sernumstr[i] < '0')
sernumstr[i] = '0';
}
if (sernumstr[8] > 'F' || sernumstr[8] < '0')
sernumstr[8] = '0';
if (sernumstr[9] > 'F' || sernumstr[9] < '0')
sernumstr[9] = '0';
if (sernumstr[10] > 'F' || sernumstr[10] < '0')
sernumstr[10] = '0';
if (sernumstr[11] > 'F' || sernumstr[11] < '0')
sernumstr[11] = '0';
sernumstr[12] = 0;
strncpy(cardkey->serial_number_str, sernumstr, sizeof(sernumstr));
io_sethandler(NOVELL_KEYCARD_ADDR, NOVELL_KEYCARD_ADDRLEN, novell_cardkey_read, NULL, NULL, NULL, NULL, NULL, cardkey);
return cardkey;
}
void novell_cardkey_close(void* priv)
{
free(priv);
}
static const device_config_t keycard_config[] = {
// clang-format off
{
.name = "serial_number",
.description = "Serial Number",
.type = CONFIG_STRING,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t novell_keycard_device = {
.name = "Novell Netware 2.x Key Card",
.internal_name = "mssystems",
.flags = DEVICE_ISA,
.local = 0,
.init = novell_cardkey_init,
.close = novell_cardkey_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = keycard_config
};
``` | /content/code_sandbox/src/device/novell_cardkey.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,343 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of a GPIO-based I2C host controller.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#define HAVE_STDARG_H
#include <wchar.h>
#include <86box/86box.h>
#include <86box/i2c.h>
typedef struct i2c_gpio_t {
char *bus_name;
void *i2c;
uint8_t prev_scl;
uint8_t prev_sda;
uint8_t slave_sda;
uint8_t started;
uint8_t slave_addr_received;
uint8_t slave_addr;
uint8_t slave_read;
uint8_t pos;
uint8_t byte;
} i2c_gpio_t;
#ifdef ENABLE_I2C_GPIO_LOG
int i2c_gpio_do_log = ENABLE_I2C_GPIO_LOG;
static void
i2c_gpio_log(int level, const char *fmt, ...)
{
va_list ap;
if (i2c_gpio_do_log >= level) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define i2c_gpio_log(fmt, ...)
#endif
void *
i2c_gpio_init(char *bus_name)
{
i2c_gpio_t *dev = (i2c_gpio_t *) malloc(sizeof(i2c_gpio_t));
memset(dev, 0, sizeof(i2c_gpio_t));
i2c_gpio_log(1, "I2C GPIO %s: init()\n", bus_name);
dev->bus_name = bus_name;
dev->i2c = i2c_addbus(dev->bus_name);
dev->prev_scl = dev->prev_sda = dev->slave_sda = 1;
dev->slave_addr = 0xff;
return dev;
}
void
i2c_gpio_close(void *dev_handle)
{
i2c_gpio_t *dev = (i2c_gpio_t *) dev_handle;
i2c_gpio_log(1, "I2C GPIO %s: close()\n", dev->bus_name);
i2c_removebus(dev->i2c);
free(dev);
}
void
i2c_gpio_set(void *dev_handle, uint8_t scl, uint8_t sda)
{
i2c_gpio_t *dev = (i2c_gpio_t *) dev_handle;
i2c_gpio_log(3, "I2C GPIO %s: write scl=%d->%d sda=%d->%d read=%d\n", dev->bus_name, dev->prev_scl, scl, dev->prev_sda, sda, dev->slave_read);
if (dev->prev_scl && scl) {
if (dev->prev_sda && !sda) {
i2c_gpio_log(2, "I2C GPIO %s: Start condition\n", dev->bus_name);
dev->started = 1;
dev->pos = 0;
dev->slave_addr = 0xff;
dev->slave_read = 2; /* start with address transfer */
dev->slave_sda = 1;
} else if (!dev->prev_sda && sda) {
i2c_gpio_log(2, "I2C GPIO %s: Stop condition\n", dev->bus_name);
dev->started = 0;
if (dev->slave_addr != 0xff)
i2c_stop(dev->i2c, dev->slave_addr);
dev->slave_addr = 0xff;
dev->slave_sda = 1;
}
} else if (!dev->prev_scl && scl && dev->started) {
if (dev->pos++ < 8) {
if (dev->slave_read == 1) {
dev->slave_sda = !!(dev->byte & 0x80);
dev->byte <<= 1;
} else {
dev->byte <<= 1;
dev->byte |= sda;
}
i2c_gpio_log(2, "I2C GPIO %s: Bit %d = %d\n", dev->bus_name, 8 - dev->pos, (dev->slave_read == 1) ? dev->slave_sda : sda);
}
if (dev->pos == 8) {
i2c_gpio_log(2, "I2C GPIO %s: Byte = %02X\n", dev->bus_name, dev->byte);
/* (N)ACKing here instead of at the 9th bit may sound odd, but is required by the Matrox Mystique Windows drivers. */
switch (dev->slave_read) {
case 2: /* address transfer */
dev->slave_addr = dev->byte >> 1;
dev->slave_read = dev->byte & 1;
/* slave ACKs? */
dev->slave_sda = !i2c_start(dev->i2c, dev->slave_addr, dev->slave_read);
i2c_gpio_log(2, "I2C GPIO %s: Slave %02X %s %sACK\n", dev->bus_name, dev->slave_addr, dev->slave_read ? "read" : "write", dev->slave_sda ? "N" : "");
if (!dev->slave_sda && dev->slave_read) /* read first byte on an ACKed read transfer */
dev->byte = i2c_read(dev->i2c, dev->slave_addr);
dev->slave_read |= 0x80; /* slave_read was overwritten; stop the master ACK read logic from running at the 9th bit if we're reading */
break;
case 0: /* write transfer */
dev->slave_sda = !i2c_write(dev->i2c, dev->slave_addr, dev->byte);
i2c_gpio_log(2, "I2C GPIO %s: Write %02X %sACK\n", dev->bus_name, dev->byte, dev->slave_sda ? "N" : "");
break;
default:
break;
}
} else if (dev->pos == 9) {
switch (dev->slave_read) {
case 1: /* read transfer (unless we're in an address transfer) */
if (!sda) /* master ACKs? */
dev->byte = i2c_read(dev->i2c, dev->slave_addr);
i2c_gpio_log(2, "I2C GPIO %s: Read %02X %sACK\n", dev->bus_name, dev->byte, sda ? "N" : "");
break;
default:
dev->slave_read &= 1; /* if we're in an address transfer, clear it */
}
dev->pos = 0; /* start over */
}
} else if (dev->prev_scl && !scl && (dev->pos != 8)) { /* keep (N)ACK computed at the 8th bit when transitioning to the 9th bit */
dev->slave_sda = 1;
}
dev->prev_scl = scl;
dev->prev_sda = sda;
}
uint8_t
i2c_gpio_get_scl(void *dev_handle)
{
const i2c_gpio_t *dev = (i2c_gpio_t *) dev_handle;
return dev->prev_scl;
}
uint8_t
i2c_gpio_get_sda(void *dev_handle)
{
const i2c_gpio_t *dev = (i2c_gpio_t *) dev_handle;
i2c_gpio_log(3, "I2C GPIO %s: read myscl=%d mysda=%d slavesda=%d\n", dev->bus_name, dev->prev_scl, dev->prev_sda, dev->slave_sda);
return dev->prev_sda && dev->slave_sda;
}
void *
i2c_gpio_get_bus(void *dev_handle)
{
i2c_gpio_t *dev = (i2c_gpio_t *) dev_handle;
return dev->i2c;
}
``` | /content/code_sandbox/src/device/i2c_gpio.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,851 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Serial passthrough device.
*
*
* Authors: Andreas J. Reichel <webmaster@6th-dimension.com>,
* Jasmine Iwanek <jasmine@iwanek.co.uk>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/fifo.h>
#include <86box/timer.h>
#include <86box/serial.h>
#include <86box/serial_passthrough.h>
#include <86box/plat_serial_passthrough.h>
#include <86box/plat_unused.h>
#define ENABLE_SERIAL_PASSTHROUGH_LOG 1
#ifdef ENABLE_SERIAL_PASSTHROUGH_LOG
int serial_passthrough_do_log = ENABLE_SERIAL_PASSTHROUGH_LOG;
static void
serial_passthrough_log(const char *fmt, ...)
{
va_list ap;
if (serial_passthrough_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define serial_passthrough_log(fmt, ...)
#endif
void
serial_passthrough_init(void)
{
for (uint8_t c = 0; c < SERIAL_MAX; c++) {
if (serial_passthrough_enabled[c]) {
/* Instance n for COM n */
device_add_inst(&serial_passthrough_device, c + 1);
}
}
}
static void
serial_passthrough_write(UNUSED(serial_t *s), void *priv, uint8_t val)
{
plat_serpt_write(priv, val);
}
static void
host_to_serial_cb(void *priv)
{
serial_passthrough_t *dev = (serial_passthrough_t *) priv;
uint8_t byte;
/* write_fifo has no failure indication, but if we write to fast, the host
* can never fetch the bytes in time, so check if the fifo is full if in
* fifo mode or if lsr has bit 0 set if not in fifo mode */
if ((dev->serial->type >= SERIAL_16550) && dev->serial->fifo_enabled) {
if (fifo_get_full(dev->serial->rcvr_fifo)) {
goto no_write_to_machine;
}
} else {
if (dev->serial->lsr & 1) {
goto no_write_to_machine;
}
}
if (plat_serpt_read(dev, &byte)) {
#if 0
printf("got byte %02X\n", byte);
#endif
serial_write_fifo(dev->serial, byte);
#if 0
serial_set_dsr(dev->serial, 1);
#endif
}
no_write_to_machine:
#if 0
serial_device_timeout(dev->serial);
#endif
timer_on_auto(&dev->host_to_serial_timer, (1000000.0 / dev->baudrate) * (double) dev->bits);
}
static void
serial_passthrough_rcr_cb(UNUSED(struct serial_s *serial), void *priv)
{
serial_passthrough_t *dev = (serial_passthrough_t *) priv;
timer_stop(&dev->host_to_serial_timer);
/* FIXME: do something to dev->baudrate */
timer_on_auto(&dev->host_to_serial_timer, (1000000.0 / dev->baudrate) * (double) dev->bits);
#if 0
serial_clear_fifo(dev->serial);
#endif
}
static void
serial_passthrough_speed_changed(void *priv)
{
serial_passthrough_t *dev = (serial_passthrough_t *) priv;
if (!dev)
return;
timer_stop(&dev->host_to_serial_timer);
/* FIXME: do something to dev->baudrate */
timer_on_auto(&dev->host_to_serial_timer, (1000000.0 / dev->baudrate) * (double) dev->bits);
#if 0
serial_clear_fifo(dev->serial);
#endif
}
static void
serial_passthrough_dev_close(void *priv)
{
serial_passthrough_t *dev = (serial_passthrough_t *) priv;
if (!dev)
return;
/* Detach passthrough device from COM port */
if (dev->serial && dev->serial->sd)
memset(dev->serial->sd, 0, sizeof(serial_device_t));
plat_serpt_close(dev);
free(dev);
}
void
serial_passthrough_transmit_period(UNUSED(serial_t *serial), void *priv, double transmit_period)
{
serial_passthrough_t *dev = (serial_passthrough_t *) priv;
if (dev->mode != SERPT_MODE_HOSTSER)
return;
dev->baudrate = 1000000.0 / transmit_period;
serial_passthrough_speed_changed(priv);
plat_serpt_set_params(dev);
}
void
serial_passthrough_lcr_callback(serial_t *serial, void *priv, uint8_t lcr)
{
serial_passthrough_t *dev = (serial_passthrough_t *) priv;
if (dev->mode != SERPT_MODE_HOSTSER)
return;
dev->bits = serial->bits;
dev->data_bits = ((lcr & 0x03) + 5);
serial_passthrough_speed_changed(priv);
plat_serpt_set_params(dev);
}
/* Initialize the device for use by the user. */
static void *
serial_passthrough_dev_init(const device_t *info)
{
serial_passthrough_t *dev;
dev = (serial_passthrough_t *) malloc(sizeof(serial_passthrough_t));
memset(dev, 0, sizeof(serial_passthrough_t));
dev->mode = device_get_config_int("mode");
dev->port = device_get_instance() - 1;
dev->baudrate = device_get_config_int("baudrate");
dev->data_bits = device_get_config_int("data_bits");
/* Attach passthrough device to a COM port */
dev->serial = serial_attach_ex(dev->port, serial_passthrough_rcr_cb,
serial_passthrough_write, serial_passthrough_transmit_period, serial_passthrough_lcr_callback, dev);
if (!dev->serial) {
free(dev);
return NULL;
}
strncpy(dev->host_serial_path, device_get_config_string("host_serial_path"), 1023);
#ifdef _WIN32
strncpy(dev->named_pipe, device_get_config_string("named_pipe"), 1023);
#endif
serial_passthrough_log("%s: port=COM%d\n", info->name, dev->port + 1);
serial_passthrough_log("%s: baud=%f\n", info->name, dev->baudrate);
serial_passthrough_log("%s: mode=%s\n", info->name, serpt_mode_names[dev->mode]);
if (plat_serpt_open_device(dev)) {
serial_passthrough_log("%s: not running\n", info->name);
return NULL;
}
serial_passthrough_log("%s: running\n", info->name);
memset(&dev->host_to_serial_timer, 0, sizeof(pc_timer_t));
timer_add(&dev->host_to_serial_timer, host_to_serial_cb, dev, 1);
serial_set_cts(dev->serial, 1);
serial_set_dsr(dev->serial, 1);
serial_set_dcd(dev->serial, 1);
/* 1 start bit + data bits + stop bits (no parity assumed) */
dev->bits = 1 + device_get_config_int("data_bits") + device_get_config_int("stop_bits");
/* Return our private data to the I/O layer. */
return dev;
}
const char *serpt_mode_names[SERPT_MODES_MAX] = {
[SERPT_MODE_VCON] = "vcon",
[SERPT_MODE_TCPSRV] = "tcpsrv",
[SERPT_MODE_TCPCLNT] = "tcpclnt",
[SERPT_MODE_HOSTSER] = "hostser",
};
// clang-format off
static const device_config_t serial_passthrough_config[] = {
{
.name = "mode",
.description = "Passthrough Mode",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
#ifdef _WIN32
{
.description = "Named Pipe (Server)",
.value = SERPT_MODE_VCON
},
#if 0 /* TODO */
{
.description = "Named Pipe (Client)",
.value = SERPT_MODE_VCON
},
#endif
#else
{
.description = "Pseudo Terminal/Virtual Console",
.value = SERPT_MODE_VCON
},
#endif
#if 0 /* TODO */
{
.description = "TCP Server",
.value = SERPT_MODE_TCPSRV
},
{
.description = "TCP Client",
.value = SERPT_MODE_TCPCLNT
},
#endif
{
.description = "Host Serial Passthrough",
.value = SERPT_MODE_HOSTSER
},
{
.description = ""
}
}
},
{
.name = "host_serial_path",
.description = "Host Serial Device",
.type = CONFIG_SERPORT,
.default_string = "",
.file_filter = NULL,
.spinner = {},
.selection = {}
},
#ifdef _WIN32
{
.name = "named_pipe",
.description = "Name of pipe",
.type = CONFIG_STRING,
.default_string = "\\\\.\\pipe\\86Box\\test",
.file_filter = NULL,
.spinner = {},
.selection = {}
},
#endif
{
.name = "data_bits",
.description = "Data bits",
.type = CONFIG_SELECTION,
.default_string = "8",
.default_int = 8,
.file_filter = NULL,
.spinner = { 0 },
.selection = {
#if 0 /* Mentioned by WFW 3.1x, not supported, atleast on Linux */
{ .description = "4", .value = 4 },
#endif
{ .description = "5", .value = 5 },
{ .description = "6", .value = 6 },
{ .description = "7", .value = 7 },
{ .description = "8", .value = 8 }
}
},
{
.name = "stop_bits",
.description = "Stop bits",
.type = CONFIG_SELECTION,
.default_string = "1",
.default_int = 1,
.file_filter = NULL,
.spinner = { 0 },
.selection = {
{ .description = "1", .value = 1 },
#if 0
{ .description = "1.5", .value = 1.5 },
#endif
{ .description = "2", .value = 2 }
}
},
{
.name = "baudrate",
.description = "Baud Rate of Passthrough",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 115200,
.file_filter = NULL,
.spinner = { 0 },
.selection = {
#if 0
{ .description = "256000", .value = 256000 },
{ .description = "128000", .value = 128000 },
#endif
{ .description = "115200", .value = 115200 },
{ .description = "57600", .value = 57600 },
{ .description = "56000", .value = 56000 },
{ .description = "38400", .value = 38400 },
{ .description = "19200", .value = 19200 },
{ .description = "14400", .value = 14400 },
{ .description = "9600", .value = 9600 },
{ .description = "7200", .value = 7200 },
{ .description = "4800", .value = 4800 },
{ .description = "2400", .value = 2400 },
{ .description = "1800", .value = 1800 },
{ .description = "1200", .value = 1200 },
{ .description = "600", .value = 600 },
{ .description = "300", .value = 300 },
{ .description = "150", .value = 150 },
#if 0
{ .description = "134.5", .value = 134.5 },
#endif
{ .description = "110", .value = 110 },
{ .description = "75", .value = 75 }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t serial_passthrough_device = {
.name = "Serial Passthrough Device",
.flags = 0,
.local = 0,
.init = serial_passthrough_dev_init,
.close = serial_passthrough_dev_close,
.reset = NULL,
{ .poll = NULL },
.speed_changed = serial_passthrough_speed_changed,
.force_redraw = NULL,
.config = serial_passthrough_config
};
``` | /content/code_sandbox/src/device/serial_passthrough.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,987 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the National Semiconductor LM75 temperature sensor chip.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#define HAVE_STDARG_H
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/i2c.h>
#include <86box/hwm.h>
#include <86box/plat_unused.h>
#define LM75_TEMP_TO_REG(t) ((t) << 8)
#ifdef ENABLE_LM75_LOG
int lm75_do_log = ENABLE_LM75_LOG;
static void
lm75_log(const char *fmt, ...)
{
va_list ap;
if (lm75_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define lm75_log(fmt, ...)
#endif
static uint8_t
lm75_i2c_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
{
lm75_t *dev = (lm75_t *) priv;
dev->i2c_state = 0;
return 1;
}
uint8_t
lm75_read(lm75_t *dev, uint8_t reg)
{
uint8_t ret;
if ((reg & 0x7) == 0x0) /* temperature high byte */
ret = LM75_TEMP_TO_REG(dev->values->temperatures[dev->local >> 8]) >> 8;
else if ((reg & 0x7) == 0x1) /* temperature low byte */
ret = LM75_TEMP_TO_REG(dev->values->temperatures[dev->local >> 8]);
else
ret = dev->regs[reg & 0x7];
lm75_log("LM75: read(%02X) = %02X\n", reg, ret);
return ret;
}
static uint8_t
lm75_i2c_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
{
lm75_t *dev = (lm75_t *) priv;
uint8_t ret = 0;
if (dev->i2c_state == 0)
dev->i2c_state = 1;
/* The AS99127F hardware monitor uses its primary LM75 device's
address to access some of its proprietary registers. Pass this
operation on to the main monitor code, if necessary. */
if ((dev->addr_register & 0x80) && dev->as99127f) {
ret = lm78_as99127f_read(dev->as99127f, dev->addr_register);
} else {
switch (dev->addr_register & 0x3) {
case 0x0: /* temperature */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x0 : 0x1);
break;
case 0x1: /* configuration */
ret = lm75_read(dev, 0x2);
break;
case 0x2: /* Thyst */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x3 : 0x4);
break;
case 0x3: /* Tos */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x5 : 0x6);
break;
default:
break;
}
}
if (dev->i2c_state < 2)
dev->i2c_state++;
return ret;
}
uint8_t
lm75_write(lm75_t *dev, uint8_t reg, uint8_t val)
{
lm75_log("LM75: write(%02X, %02X)\n", reg, val);
uint8_t reg_idx = (reg & 0x7);
if ((reg_idx <= 0x1) || (reg_idx == 0x7))
return 0; /* read-only registers */
dev->regs[reg_idx] = val;
return 1;
}
static uint8_t
lm75_i2c_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t data, void *priv)
{
lm75_t *dev = (lm75_t *) priv;
if ((dev->i2c_state > 2) || ((dev->i2c_state == 2) && ((dev->addr_register & 0x3) == 0x1))) {
return 0;
} else if (dev->i2c_state == 0) {
dev->i2c_state = 1;
/* Linux lm75.c driver relies on the address register not changing if bit 2 is set. */
if (((dev->addr_register & 0x80) && dev->as99127f) || !(data & 0x04))
dev->addr_register = data;
return 1;
}
/* The AS99127F hardware monitor uses its primary LM75 device's
address to access some of its proprietary registers. Pass this
operation on to the main monitor code, if necessary. */
if ((dev->addr_register & 0x80) && dev->as99127f) {
return lm78_as99127f_write(dev->as99127f, dev->addr_register, data);
} else {
switch (dev->addr_register & 0x3) {
case 0x0: /* temperature */
lm75_write(dev, (dev->i2c_state == 1) ? 0x0 : 0x1, data);
break;
case 0x1: /* configuration */
lm75_write(dev, 0x2, data);
break;
case 0x2: /* Thyst */
lm75_write(dev, (dev->i2c_state == 1) ? 0x3 : 0x4, data);
break;
case 0x3: /* Tos */
lm75_write(dev, (dev->i2c_state == 1) ? 0x5 : 0x6, data);
break;
default:
break;
}
}
if (dev->i2c_state == 1)
dev->i2c_state = 2;
return 1;
}
void
lm75_remap(lm75_t *dev, uint8_t addr)
{
lm75_log("LM75: remapping to SMBus %02Xh\n", addr);
if (dev->i2c_enabled)
i2c_removehandler(i2c_smbus, dev->i2c_addr, 1, lm75_i2c_start, lm75_i2c_read, lm75_i2c_write, NULL, dev);
if (addr < 0x80)
i2c_sethandler(i2c_smbus, addr, 1, lm75_i2c_start, lm75_i2c_read, lm75_i2c_write, NULL, dev);
dev->i2c_addr = addr & 0x7f;
dev->i2c_enabled = !(addr & 0x80);
}
static void
lm75_reset(lm75_t *dev)
{
dev->regs[0x3] = 0x4b;
dev->regs[0x5] = 0x50;
lm75_remap(dev, dev->i2c_addr | (dev->i2c_enabled ? 0x00 : 0x80));
}
static void
lm75_close(void *priv)
{
lm75_t *dev = (lm75_t *) priv;
lm75_remap(dev, 0);
free(dev);
}
static void *
lm75_init(const device_t *info)
{
lm75_t *dev = (lm75_t *) malloc(sizeof(lm75_t));
memset(dev, 0, sizeof(lm75_t));
dev->local = info->local;
/* Set default value. */
if (dev->local)
hwm_values.temperatures[dev->local >> 8] = 30;
dev->values = &hwm_values;
dev->i2c_addr = dev->local & 0x7f;
dev->i2c_enabled = 1;
lm75_reset(dev);
return dev;
}
/* LM75 on SMBus address 4Ah, reporting temperatures[1]. */
const device_t lm75_1_4a_device = {
.name = "National Semiconductor LM75 Temperature Sensor",
.internal_name = "lm75_1_4a",
.flags = DEVICE_ISA,
.local = 0x14a,
.init = lm75_init,
.close = lm75_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
/* LM75 secondary/tertiary temperature sensors built into
the Winbond W83781D family. Not to be used stand-alone. */
const device_t lm75_w83781d_device = {
.name = "Winbond W83781D Secondary Temperature Sensor",
.internal_name = "lm75_w83781d",
.flags = DEVICE_ISA,
.local = 0,
.init = lm75_init,
.close = lm75_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/device/hwm_lm75.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,203 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of PS/2 series Mouse devices.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mouse.h>
#define FLAG_PS2 0x08 /* dev is AT or PS/2 */
#define FLAG_AT 0x00 /* dev is AT or PS/2 */
#define FLAG_TYPE_MASK 0x07 /* mask for type */
#define FIFO_SIZE 16
#define BAT_COUNT 1000
enum {
KBD_84_KEY = 0,
KBD_101_KEY,
KBD_102_KEY,
KBD_JIS,
KBD_KOREAN
};
#define FLAG_ENABLED 0x10 /* dev is enabled for use */
#define FLAG_CTRLDAT 0x08 /* ctrl or data mode */
const uint8_t id_bytes[16][4] = { { 0x00, 0x00, 0x00, 0x00 }, /* AT 84-key */
{ 0x00, 0x00, 0x00, 0x00 }, /* AT 101/102/106-key */
{ 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00 }, /* AT Korean */
{ 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00 },
{ 0xab, 0x83, 0x00, 0x00 }, /* PS/2 101-key */
{ 0xab, 0x83, 0x00, 0x00 }, /* PS/2 102-key */
{ 0xab, 0x90, 0x00, 0x00 }, /* PS/2 106-key JIS */
/* Japanese keyboard ID - TODO: Find the actual Korean one. */
{ 0xab, 0x90, 0x00, 0x00 }, /* PS/2 Korean */
{ 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00 } };
/* Global keyboard flags for scan code set 3:
bit 0 = repeat, bit 1 = makes break code? */
uint8_t keyboard_set3_flags[512];
uint8_t keyboard_set3_all_repeat;
uint8_t keyboard_set3_all_break;
/* Global keyboard mode:
Bits 0 - 1 = scan code set. */
uint8_t keyboard_mode = 0x02;
static atkbc_dev_t *SavedKbd = NULL;
static uint8_t inv_cmd_response = 0xfa;
static uint16_t bat_counter = 0;
static const scancode scancode_set1[512] = {
// clang-format off
{ .mk = { 0 }, .brk = { 0 } }, /* 000 */
{ .mk = { 0x01, 0 }, .brk = { 0x81, 0 } }, /* 001 */
{ .mk = { 0x02, 0 }, .brk = { 0x82, 0 } }, /* 002 */
{ .mk = { 0x03, 0 }, .brk = { 0x83, 0 } }, /* 003 */
{ .mk = { 0x04, 0 }, .brk = { 0x84, 0 } }, /* 004 */
{ .mk = { 0x05, 0 }, .brk = { 0x85, 0 } }, /* 005 */
{ .mk = { 0x06, 0 }, .brk = { 0x86, 0 } }, /* 006 */
{ .mk = { 0x07, 0 }, .brk = { 0x87, 0 } }, /* 007 */
{ .mk = { 0x08, 0 }, .brk = { 0x88, 0 } }, /* 008 */
{ .mk = { 0x09, 0 }, .brk = { 0x89, 0 } }, /* 009 */
{ .mk = { 0x0a, 0 }, .brk = { 0x8a, 0 } }, /* 00a */
{ .mk = { 0x0b, 0 }, .brk = { 0x8b, 0 } }, /* 00b */
{ .mk = { 0x0c, 0 }, .brk = { 0x8c, 0 } }, /* 00c */
{ .mk = { 0x0d, 0 }, .brk = { 0x8d, 0 } }, /* 00d */
{ .mk = { 0x0e, 0 }, .brk = { 0x8e, 0 } }, /* 00e */
{ .mk = { 0x0f, 0 }, .brk = { 0x8f, 0 } }, /* 00f */
{ .mk = { 0x10, 0 }, .brk = { 0x90, 0 } }, /* 010 */
{ .mk = { 0x11, 0 }, .brk = { 0x91, 0 } }, /* 011 */
{ .mk = { 0x12, 0 }, .brk = { 0x92, 0 } }, /* 012 */
{ .mk = { 0x13, 0 }, .brk = { 0x93, 0 } }, /* 013 */
{ .mk = { 0x14, 0 }, .brk = { 0x94, 0 } }, /* 014 */
{ .mk = { 0x15, 0 }, .brk = { 0x95, 0 } }, /* 015 */
{ .mk = { 0x16, 0 }, .brk = { 0x96, 0 } }, /* 016 */
{ .mk = { 0x17, 0 }, .brk = { 0x97, 0 } }, /* 017 */
{ .mk = { 0x18, 0 }, .brk = { 0x98, 0 } }, /* 018 */
{ .mk = { 0x19, 0 }, .brk = { 0x99, 0 } }, /* 019 */
{ .mk = { 0x1a, 0 }, .brk = { 0x9a, 0 } }, /* 01a */
{ .mk = { 0x1b, 0 }, .brk = { 0x9b, 0 } }, /* 01b */
{ .mk = { 0x1c, 0 }, .brk = { 0x9c, 0 } }, /* 01c */
{ .mk = { 0x1d, 0 }, .brk = { 0x9d, 0 } }, /* 01d */
{ .mk = { 0x1e, 0 }, .brk = { 0x9e, 0 } }, /* 01e */
{ .mk = { 0x1f, 0 }, .brk = { 0x9f, 0 } }, /* 01f */
{ .mk = { 0x20, 0 }, .brk = { 0xa0, 0 } }, /* 020 */
{ .mk = { 0x21, 0 }, .brk = { 0xa1, 0 } }, /* 021 */
{ .mk = { 0x22, 0 }, .brk = { 0xa2, 0 } }, /* 022 */
{ .mk = { 0x23, 0 }, .brk = { 0xa3, 0 } }, /* 023 */
{ .mk = { 0x24, 0 }, .brk = { 0xa4, 0 } }, /* 024 */
{ .mk = { 0x25, 0 }, .brk = { 0xa5, 0 } }, /* 025 */
{ .mk = { 0x26, 0 }, .brk = { 0xa6, 0 } }, /* 026 */
{ .mk = { 0x27, 0 }, .brk = { 0xa7, 0 } }, /* 027 */
{ .mk = { 0x28, 0 }, .brk = { 0xa8, 0 } }, /* 028 */
{ .mk = { 0x29, 0 }, .brk = { 0xa9, 0 } }, /* 029 */
{ .mk = { 0x2a, 0 }, .brk = { 0xaa, 0 } }, /* 02a */
{ .mk = { 0x2b, 0 }, .brk = { 0xab, 0 } }, /* 02b */
{ .mk = { 0x2c, 0 }, .brk = { 0xac, 0 } }, /* 02c */
{ .mk = { 0x2d, 0 }, .brk = { 0xad, 0 } }, /* 02d */
{ .mk = { 0x2e, 0 }, .brk = { 0xae, 0 } }, /* 02e */
{ .mk = { 0x2f, 0 }, .brk = { 0xaf, 0 } }, /* 02f */
{ .mk = { 0x30, 0 }, .brk = { 0xb0, 0 } }, /* 030 */
{ .mk = { 0x31, 0 }, .brk = { 0xb1, 0 } }, /* 031 */
{ .mk = { 0x32, 0 }, .brk = { 0xb2, 0 } }, /* 032 */
{ .mk = { 0x33, 0 }, .brk = { 0xb3, 0 } }, /* 033 */
{ .mk = { 0x34, 0 }, .brk = { 0xb4, 0 } }, /* 034 */
{ .mk = { 0x35, 0 }, .brk = { 0xb5, 0 } }, /* 035 */
{ .mk = { 0x36, 0 }, .brk = { 0xb6, 0 } }, /* 036 */
{ .mk = { 0x37, 0 }, .brk = { 0xb7, 0 } }, /* 037 */
{ .mk = { 0x38, 0 }, .brk = { 0xb8, 0 } }, /* 038 */
{ .mk = { 0x39, 0 }, .brk = { 0xb9, 0 } }, /* 039 */
{ .mk = { 0x3a, 0 }, .brk = { 0xba, 0 } }, /* 03a */
{ .mk = { 0x3b, 0 }, .brk = { 0xbb, 0 } }, /* 03b */
{ .mk = { 0x3c, 0 }, .brk = { 0xbc, 0 } }, /* 03c */
{ .mk = { 0x3d, 0 }, .brk = { 0xbd, 0 } }, /* 03d */
{ .mk = { 0x3e, 0 }, .brk = { 0xbe, 0 } }, /* 03e */
{ .mk = { 0x3f, 0 }, .brk = { 0xbf, 0 } }, /* 03f */
{ .mk = { 0x40, 0 }, .brk = { 0xc0, 0 } }, /* 040 */
{ .mk = { 0x41, 0 }, .brk = { 0xc1, 0 } }, /* 041 */
{ .mk = { 0x42, 0 }, .brk = { 0xc2, 0 } }, /* 042 */
{ .mk = { 0x43, 0 }, .brk = { 0xc3, 0 } }, /* 043 */
{ .mk = { 0x44, 0 }, .brk = { 0xc4, 0 } }, /* 044 */
{ .mk = { 0x45, 0 }, .brk = { 0xc5, 0 } }, /* 045 */
{ .mk = { 0x46, 0 }, .brk = { 0xc6, 0 } }, /* 046 */
{ .mk = { 0x47, 0 }, .brk = { 0xc7, 0 } }, /* 047 */
{ .mk = { 0x48, 0 }, .brk = { 0xc8, 0 } }, /* 048 */
{ .mk = { 0x49, 0 }, .brk = { 0xc9, 0 } }, /* 049 */
{ .mk = { 0x4a, 0 }, .brk = { 0xca, 0 } }, /* 04a */
{ .mk = { 0x4b, 0 }, .brk = { 0xcb, 0 } }, /* 04b */
{ .mk = { 0x4c, 0 }, .brk = { 0xcc, 0 } }, /* 04c */
{ .mk = { 0x4d, 0 }, .brk = { 0xcd, 0 } }, /* 04d */
{ .mk = { 0x4e, 0 }, .brk = { 0xce, 0 } }, /* 04e */
{ .mk = { 0x4f, 0 }, .brk = { 0xcf, 0 } }, /* 04f */
{ .mk = { 0x50, 0 }, .brk = { 0xd0, 0 } }, /* 050 */
{ .mk = { 0x51, 0 }, .brk = { 0xd1, 0 } }, /* 051 */
{ .mk = { 0x52, 0 }, .brk = { 0xd2, 0 } }, /* 052 */
{ .mk = { 0x53, 0 }, .brk = { 0xd3, 0 } }, /* 053 */
{ .mk = { 0x54, 0 }, .brk = { 0xd4, 0 } }, /* 054 */
{ .mk = { 0x55, 0 }, .brk = { 0xd5, 0 } }, /* 055 */
{ .mk = { 0x56, 0 }, .brk = { 0xd6, 0 } }, /* 056 */
{ .mk = { 0x57, 0 }, .brk = { 0xd7, 0 } }, /* 057 */
{ .mk = { 0x58, 0 }, .brk = { 0xd8, 0 } }, /* 058 */
{ .mk = { 0x59, 0 }, .brk = { 0xd9, 0 } }, /* 059 */
{ .mk = { 0x5a, 0 }, .brk = { 0xda, 0 } }, /* 05a */
{ .mk = { 0x5b, 0 }, .brk = { 0xdb, 0 } }, /* 05b */
{ .mk = { 0x5c, 0 }, .brk = { 0xdc, 0 } }, /* 05c */
{ .mk = { 0x5d, 0 }, .brk = { 0xdd, 0 } }, /* 05d */
{ .mk = { 0x5e, 0 }, .brk = { 0xde, 0 } }, /* 05e */
{ .mk = { 0x5f, 0 }, .brk = { 0xdf, 0 } }, /* 05f */
{ .mk = { 0x60, 0 }, .brk = { 0xe0, 0 } }, /* 060 */
{ .mk = { 0x61, 0 }, .brk = { 0xe1, 0 } }, /* 061 */
{ .mk = { 0x62, 0 }, .brk = { 0xe2, 0 } }, /* 062 */
{ .mk = { 0x63, 0 }, .brk = { 0xe3, 0 } }, /* 063 */
{ .mk = { 0x64, 0 }, .brk = { 0xe4, 0 } }, /* 064 */
{ .mk = { 0x65, 0 }, .brk = { 0xe5, 0 } }, /* 065 */
{ .mk = { 0x66, 0 }, .brk = { 0xe6, 0 } }, /* 066 */
{ .mk = { 0x67, 0 }, .brk = { 0xe7, 0 } }, /* 067 */
{ .mk = { 0x68, 0 }, .brk = { 0xe8, 0 } }, /* 068 */
{ .mk = { 0x69, 0 }, .brk = { 0xe9, 0 } }, /* 069 */
{ .mk = { 0x6a, 0 }, .brk = { 0xea, 0 } }, /* 06a */
{ .mk = { 0x6b, 0 }, .brk = { 0xeb, 0 } }, /* 06b */
{ .mk = { 0x6c, 0 }, .brk = { 0xec, 0 } }, /* 06c */
{ .mk = { 0x6d, 0 }, .brk = { 0xed, 0 } }, /* 06d */
{ .mk = { 0x6e, 0 }, .brk = { 0xee, 0 } }, /* 06e */
{ .mk = { 0x6f, 0 }, .brk = { 0xef, 0 } }, /* 06f */
{ .mk = { 0x70, 0 }, .brk = { 0xf0, 0 } }, /* 070 */
{ .mk = { 0x71, 0 }, .brk = { 0xf1, 0 } }, /* 071 */
{ .mk = { 0x72, 0 }, .brk = { 0xf2, 0 } }, /* 072 */
{ .mk = { 0x73, 0 }, .brk = { 0xf3, 0 } }, /* 073 */
{ .mk = { 0x74, 0 }, .brk = { 0xf4, 0 } }, /* 074 */
{ .mk = { 0x75, 0 }, .brk = { 0xf5, 0 } }, /* 075 */
{ .mk = { 0x76, 0 }, .brk = { 0xf6, 0 } }, /* 076 */
{ .mk = { 0x77, 0 }, .brk = { 0xf7, 0 } }, /* 077 */
{ .mk = { 0x78, 0 }, .brk = { 0xf8, 0 } }, /* 078 */
{ .mk = { 0x79, 0 }, .brk = { 0xf9, 0 } }, /* 079 */
{ .mk = { 0x7a, 0 }, .brk = { 0xfa, 0 } }, /* 07a */
{ .mk = { 0x7b, 0 }, .brk = { 0xfb, 0 } }, /* 07b */
{ .mk = { 0x7c, 0 }, .brk = { 0xfc, 0 } }, /* 07c */
{ .mk = { 0x7d, 0 }, .brk = { 0xfd, 0 } }, /* 07d */
{ .mk = { 0x7e, 0 }, .brk = { 0xfe, 0 } }, /* 07e */
{ .mk = { 0x7f, 0 }, .brk = { 0xff, 0 } }, /* 07f */
{ .mk = { 0x80, 0 }, .brk = { 0 } }, /* 080 */
{ .mk = { 0x81, 0 }, .brk = { 0 } }, /* 081 */
{ .mk = { 0x82, 0 }, .brk = { 0 } }, /* 082 */
{ .mk = { 0 }, .brk = { 0 } }, /* 083 */
{ .mk = { 0 }, .brk = { 0 } }, /* 084 */
{ .mk = { 0x85, 0 }, .brk = { 0 } }, /* 085 */
{ .mk = { 0x86, 0 }, .brk = { 0 } }, /* 086 */
{ .mk = { 0x87, 0 }, .brk = { 0 } }, /* 087 */
{ .mk = { 0x88, 0 }, .brk = { 0 } }, /* 088 */
{ .mk = { 0x89, 0 }, .brk = { 0 } }, /* 089 */
{ .mk = { 0x8a, 0 }, .brk = { 0 } }, /* 08a */
{ .mk = { 0x8b, 0 }, .brk = { 0 } }, /* 08b */
{ .mk = { 0x8c, 0 }, .brk = { 0 } }, /* 08c */
{ .mk = { 0x8d, 0 }, .brk = { 0 } }, /* 08d */
{ .mk = { 0x8e, 0 }, .brk = { 0 } }, /* 08e */
{ .mk = { 0x8f, 0 }, .brk = { 0 } }, /* 08f */
{ .mk = { 0x90, 0 }, .brk = { 0 } }, /* 090 */
{ .mk = { 0x91, 0 }, .brk = { 0 } }, /* 091 */
{ .mk = { 0x92, 0 }, .brk = { 0 } }, /* 092 */
{ .mk = { 0x93, 0 }, .brk = { 0 } }, /* 093 */
{ .mk = { 0x94, 0 }, .brk = { 0 } }, /* 094 */
{ .mk = { 0x95, 0 }, .brk = { 0 } }, /* 095 */
{ .mk = { 0x96, 0 }, .brk = { 0 } }, /* 096 */
{ .mk = { 0x97, 0 }, .brk = { 0 } }, /* 097 */
{ .mk = { 0x98, 0 }, .brk = { 0 } }, /* 098 */
{ .mk = { 0x99, 0 }, .brk = { 0 } }, /* 099 */
{ .mk = { 0x9a, 0 }, .brk = { 0 } }, /* 09a */
{ .mk = { 0x9b, 0 }, .brk = { 0 } }, /* 09b */
{ .mk = { 0x9c, 0 }, .brk = { 0 } }, /* 09c */
{ .mk = { 0x9d, 0 }, .brk = { 0 } }, /* 09d */
{ .mk = { 0x9e, 0 }, .brk = { 0 } }, /* 09e */
{ .mk = { 0x9f, 0 }, .brk = { 0 } }, /* 09f */
{ .mk = { 0xa0, 0 }, .brk = { 0 } }, /* 0a0 */
{ .mk = { 0xa1, 0 }, .brk = { 0 } }, /* 0a1 */
{ .mk = { 0xa2, 0 }, .brk = { 0 } }, /* 0a2 */
{ .mk = { 0xa3, 0 }, .brk = { 0 } }, /* 0a3 */
{ .mk = { 0xa4, 0 }, .brk = { 0 } }, /* 0a4 */
{ .mk = { 0xa5, 0 }, .brk = { 0 } }, /* 0a5 */
{ .mk = { 0xa6, 0 }, .brk = { 0 } }, /* 0a6 */
{ .mk = { 0xa7, 0 }, .brk = { 0 } }, /* 0a7 */
{ .mk = { 0xa8, 0 }, .brk = { 0 } }, /* 0a8 */
{ .mk = { 0xa9, 0 }, .brk = { 0 } }, /* 0a9 */
{ .mk = { 0xaa, 0 }, .brk = { 0 } }, /* 0aa */
{ .mk = { 0xab, 0 }, .brk = { 0 } }, /* 0ab */
{ .mk = { 0xac, 0 }, .brk = { 0 } }, /* 0ac */
{ .mk = { 0xad, 0 }, .brk = { 0 } }, /* 0ad */
{ .mk = { 0xae, 0 }, .brk = { 0 } }, /* 0ae */
{ .mk = { 0xaf, 0 }, .brk = { 0 } }, /* 0af */
{ .mk = { 0xb0, 0 }, .brk = { 0 } }, /* 0b0 */
{ .mk = { 0xb1, 0 }, .brk = { 0 } }, /* 0b1 */
{ .mk = { 0xb2, 0 }, .brk = { 0 } }, /* 0b2 */
{ .mk = { 0xb3, 0 }, .brk = { 0 } }, /* 0b3 */
{ .mk = { 0xb4, 0 }, .brk = { 0 } }, /* 0b4 */
{ .mk = { 0xb5, 0 }, .brk = { 0 } }, /* 0b5 */
{ .mk = { 0xb6, 0 }, .brk = { 0 } }, /* 0b6 */
{ .mk = { 0xb7, 0 }, .brk = { 0 } }, /* 0b7 */
{ .mk = { 0xb8, 0 }, .brk = { 0 } }, /* 0b8 */
{ .mk = { 0xb9, 0 }, .brk = { 0 } }, /* 0b9 */
{ .mk = { 0xba, 0 }, .brk = { 0 } }, /* 0ba */
{ .mk = { 0xbb, 0 }, .brk = { 0 } }, /* 0bb */
{ .mk = { 0xbc, 0 }, .brk = { 0 } }, /* 0bc */
{ .mk = { 0xbd, 0 }, .brk = { 0 } }, /* 0bd */
{ .mk = { 0xbe, 0 }, .brk = { 0 } }, /* 0be */
{ .mk = { 0xbf, 0 }, .brk = { 0 } }, /* 0bf */
{ .mk = { 0xc0, 0 }, .brk = { 0 } }, /* 0c0 */
{ .mk = { 0xc1, 0 }, .brk = { 0 } }, /* 0c1 */
{ .mk = { 0xc2, 0 }, .brk = { 0 } }, /* 0c2 */
{ .mk = { 0xc3, 0 }, .brk = { 0 } }, /* 0c3 */
{ .mk = { 0xc4, 0 }, .brk = { 0 } }, /* 0c4 */
{ .mk = { 0xc5, 0 }, .brk = { 0 } }, /* 0c5 */
{ .mk = { 0xc6, 0 }, .brk = { 0 } }, /* 0c6 */
{ .mk = { 0xc7, 0 }, .brk = { 0 } }, /* 0c7 */
{ .mk = { 0xc8, 0 }, .brk = { 0 } }, /* 0c8 */
{ .mk = { 0xc9, 0 }, .brk = { 0 } }, /* 0c9 */
{ .mk = { 0xca, 0 }, .brk = { 0 } }, /* 0ca */
{ .mk = { 0xcb, 0 }, .brk = { 0 } }, /* 0cb */
{ .mk = { 0xcc, 0 }, .brk = { 0 } }, /* 0cc */
{ .mk = { 0xcd, 0 }, .brk = { 0 } }, /* 0cd */
{ .mk = { 0xce, 0 }, .brk = { 0 } }, /* 0ce */
{ .mk = { 0xcf, 0 }, .brk = { 0 } }, /* 0cf */
{ .mk = { 0xd0, 0 }, .brk = { 0 } }, /* 0d0 */
{ .mk = { 0xd1, 0 }, .brk = { 0 } }, /* 0d1 */
{ .mk = { 0xd2, 0 }, .brk = { 0 } }, /* 0d2 */
{ .mk = { 0xd3, 0 }, .brk = { 0 } }, /* 0d3 */
{ .mk = { 0xd4, 0 }, .brk = { 0 } }, /* 0d4 */
{ .mk = { 0xd5, 0 }, .brk = { 0 } }, /* 0d5 */
{ .mk = { 0xd6, 0 }, .brk = { 0 } }, /* 0d6 */
{ .mk = { 0xd7, 0 }, .brk = { 0 } }, /* 0d7 */
{ .mk = { 0xd8, 0 }, .brk = { 0 } }, /* 0d8 */
{ .mk = { 0xd9, 0 }, .brk = { 0 } }, /* 0d9 */
{ .mk = { 0xda, 0 }, .brk = { 0 } }, /* 0da */
{ .mk = { 0xdb, 0 }, .brk = { 0 } }, /* 0db */
{ .mk = { 0xdc, 0 }, .brk = { 0 } }, /* 0dc */
{ .mk = { 0xdd, 0 }, .brk = { 0 } }, /* 0dd */
{ .mk = { 0xde, 0 }, .brk = { 0 } }, /* 0de */
{ .mk = { 0xdf, 0 }, .brk = { 0 } }, /* 0df */
{ .mk = { 0xe0, 0 }, .brk = { 0 } }, /* 0e0 */
{ .mk = { 0xe1, 0 }, .brk = { 0 } }, /* 0e1 */
{ .mk = { 0xe2, 0 }, .brk = { 0 } }, /* 0e2 */
{ .mk = { 0xe3, 0 }, .brk = { 0 } }, /* 0e3 */
{ .mk = { 0xe4, 0 }, .brk = { 0 } }, /* 0e4 */
{ .mk = { 0xe5, 0 }, .brk = { 0 } }, /* 0e5 */
{ .mk = { 0xe6, 0 }, .brk = { 0 } }, /* 0e6 */
{ .mk = { 0xe7, 0 }, .brk = { 0 } }, /* 0e7 */
{ .mk = { 0xe8, 0 }, .brk = { 0 } }, /* 0e8 */
{ .mk = { 0xe9, 0 }, .brk = { 0 } }, /* 0e9 */
{ .mk = { 0xea, 0 }, .brk = { 0 } }, /* 0ea */
{ .mk = { 0xeb, 0 }, .brk = { 0 } }, /* 0eb */
{ .mk = { 0xec, 0 }, .brk = { 0 } }, /* 0ec */
{ .mk = { 0xed, 0 }, .brk = { 0 } }, /* 0ed */
{ .mk = { 0xee, 0 }, .brk = { 0 } }, /* 0ee */
{ .mk = { 0xef, 0 }, .brk = { 0 } }, /* 0ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f0 */
{ .mk = { 0xf1, 0 }, .brk = { 0 } }, /* 0f1 */
{ .mk = { 0xf2, 0 }, .brk = { 0 } }, /* 0f2 */
{ .mk = { 0xf3, 0 }, .brk = { 0 } }, /* 0f3 */
{ .mk = { 0xf4, 0 }, .brk = { 0 } }, /* 0f4 */
{ .mk = { 0xf5, 0 }, .brk = { 0 } }, /* 0f5 */
{ .mk = { 0xf6, 0 }, .brk = { 0 } }, /* 0f6 */
{ .mk = { 0xf7, 0 }, .brk = { 0 } }, /* 0f7 */
{ .mk = { 0xf8, 0 }, .brk = { 0 } }, /* 0f8 */
{ .mk = { 0xf9, 0 }, .brk = { 0 } }, /* 0f9 */
{ .mk = { 0xfa, 0 }, .brk = { 0 } }, /* 0fa */
{ .mk = { 0xfb, 0 }, .brk = { 0 } }, /* 0fb */
{ .mk = { 0xfc, 0 }, .brk = { 0 } }, /* 0fc */
{ .mk = { 0xfd, 0 }, .brk = { 0 } }, /* 0fd */
{ .mk = { 0xfe, 0 }, .brk = { 0 } }, /* 0fe */
{ .mk = { 0xff, 0 }, .brk = { 0 } }, /* 0ff */
{ .mk = {0xe1, 0x1d, 0 }, .brk = { 0xe1, 0x9d, 0 } }, /* 100 */
{ .mk = {0xe0, 0x01, 0 }, .brk = { 0xe0, 0x81, 0 } }, /* 101 */
{ .mk = {0xe0, 0x02, 0 }, .brk = { 0xe0, 0x82, 0 } }, /* 102 */
{ .mk = {0xe0, 0x03, 0 }, .brk = { 0xe0, 0x83, 0 } }, /* 103 */
{ .mk = {0xe0, 0x04, 0 }, .brk = { 0xe0, 0x84, 0 } }, /* 104 */
{ .mk = {0xe0, 0x05, 0 }, .brk = { 0xe0, 0x85, 0 } }, /* 105 */
{ .mk = {0xe0, 0x06, 0 }, .brk = { 0xe0, 0x86, 0 } }, /* 106 */
{ .mk = {0xe0, 0x07, 0 }, .brk = { 0xe0, 0x87, 0 } }, /* 107 */
{ .mk = {0xe0, 0x08, 0 }, .brk = { 0xe0, 0x88, 0 } }, /* 108 */
{ .mk = {0xe0, 0x09, 0 }, .brk = { 0xe0, 0x89, 0 } }, /* 109 */
{ .mk = {0xe0, 0x0a, 0 }, .brk = { 0xe0, 0x8a, 0 } }, /* 10a */
{ .mk = {0xe0, 0x0b, 0 }, .brk = { 0xe0, 0x8b, 0 } }, /* 10b */
{ .mk = {0xe0, 0x0c, 0 }, .brk = { 0xe0, 0x8c, 0 } }, /* 10c */
{ .mk = { 0 }, .brk = { 0 } }, /* 10d */
{ .mk = {0xe0, 0x0e, 0 }, .brk = { 0xe0, 0x8e, 0 } }, /* 10e */
{ .mk = {0xe0, 0x0f, 0 }, .brk = { 0xe0, 0x8f, 0 } }, /* 10f */
{ .mk = {0xe0, 0x10, 0 }, .brk = { 0xe0, 0x90, 0 } }, /* 110 */
{ .mk = {0xe0, 0x11, 0 }, .brk = { 0xe0, 0x91, 0 } }, /* 111 */
{ .mk = {0xe0, 0x12, 0 }, .brk = { 0xe0, 0x92, 0 } }, /* 112 */
{ .mk = {0xe0, 0x13, 0 }, .brk = { 0xe0, 0x93, 0 } }, /* 113 */
{ .mk = {0xe0, 0x14, 0 }, .brk = { 0xe0, 0x94, 0 } }, /* 114 */
{ .mk = {0xe0, 0x15, 0 }, .brk = { 0xe0, 0x95, 0 } }, /* 115 */
{ .mk = {0xe0, 0x16, 0 }, .brk = { 0xe0, 0x96, 0 } }, /* 116 */
{ .mk = {0xe0, 0x17, 0 }, .brk = { 0xe0, 0x97, 0 } }, /* 117 */
{ .mk = {0xe0, 0x18, 0 }, .brk = { 0xe0, 0x98, 0 } }, /* 118 */
{ .mk = {0xe0, 0x19, 0 }, .brk = { 0xe0, 0x99, 0 } }, /* 119 */
{ .mk = {0xe0, 0x1a, 0 }, .brk = { 0xe0, 0x9a, 0 } }, /* 11a */
{ .mk = {0xe0, 0x1b, 0 }, .brk = { 0xe0, 0x9b, 0 } }, /* 11b */
{ .mk = {0xe0, 0x1c, 0 }, .brk = { 0xe0, 0x9c, 0 } }, /* 11c */
{ .mk = {0xe0, 0x1d, 0 }, .brk = { 0xe0, 0x9d, 0 } }, /* 11d */
{ .mk = {0xe0, 0x1e, 0 }, .brk = { 0xe0, 0x9e, 0 } }, /* 11e */
{ .mk = {0xe0, 0x1f, 0 }, .brk = { 0xe0, 0x9f, 0 } }, /* 11f */
{ .mk = {0xe0, 0x20, 0 }, .brk = { 0xe0, 0xa0, 0 } }, /* 120 */
{ .mk = {0xe0, 0x21, 0 }, .brk = { 0xe0, 0xa1, 0 } }, /* 121 */
{ .mk = {0xe0, 0x22, 0 }, .brk = { 0xe0, 0xa2, 0 } }, /* 122 */
{ .mk = {0xe0, 0x23, 0 }, .brk = { 0xe0, 0xa3, 0 } }, /* 123 */
{ .mk = {0xe0, 0x24, 0 }, .brk = { 0xe0, 0xa4, 0 } }, /* 124 */
{ .mk = {0xe0, 0x25, 0 }, .brk = { 0xe0, 0xa5, 0 } }, /* 125 */
{ .mk = {0xe0, 0x26, 0 }, .brk = { 0xe0, 0xa6, 0 } }, /* 126 */
{ .mk = { 0 }, .brk = { 0 } }, /* 127 */
{ .mk = { 0 }, .brk = { 0 } }, /* 128 */
{ .mk = { 0 }, .brk = { 0 } }, /* 129 */
{ .mk = { 0 }, .brk = { 0 } }, /* 12a */
{ .mk = { 0 }, .brk = { 0 } }, /* 12b */
{ .mk = {0xe0, 0x2c, 0 }, .brk = { 0xe0, 0xac, 0 } }, /* 12c */
{ .mk = {0xe0, 0x2d, 0 }, .brk = { 0xe0, 0xad, 0 } }, /* 12d */
{ .mk = {0xe0, 0x2e, 0 }, .brk = { 0xe0, 0xae, 0 } }, /* 12e */
{ .mk = {0xe0, 0x2f, 0 }, .brk = { 0xe0, 0xaf, 0 } }, /* 12f */
{ .mk = {0xe0, 0x30, 0 }, .brk = { 0xe0, 0xb0, 0 } }, /* 130 */
{ .mk = {0xe0, 0x31, 0 }, .brk = { 0xe0, 0xb1, 0 } }, /* 131 */
{ .mk = {0xe0, 0x32, 0 }, .brk = { 0xe0, 0xb2, 0 } }, /* 132 */
{ .mk = { 0 }, .brk = { 0 } }, /* 133 */
{ .mk = {0xe0, 0x34, 0 }, .brk = { 0xe0, 0xb4, 0 } }, /* 134 */
{ .mk = {0xe0, 0x35, 0 }, .brk = { 0xe0, 0xb5, 0 } }, /* 135 */
{ .mk = { 0 }, .brk = { 0 } }, /* 136 */
{ .mk = {0xe0, 0x37, 0 }, .brk = { 0xe0, 0xb7, 0 } }, /* 137 */
{ .mk = {0xe0, 0x38, 0 }, .brk = { 0xe0, 0xb8, 0 } }, /* 138 */
{ .mk = { 0 }, .brk = { 0 } }, /* 139 */
{ .mk = {0xe0, 0x3a, 0 }, .brk = { 0xe0, 0xba, 0 } }, /* 13a */
{ .mk = {0xe0, 0x3b, 0 }, .brk = { 0xe0, 0xbb, 0 } }, /* 13b */
{ .mk = {0xe0, 0x3c, 0 }, .brk = { 0xe0, 0xbc, 0 } }, /* 13c */
{ .mk = {0xe0, 0x3d, 0 }, .brk = { 0xe0, 0xbd, 0 } }, /* 13d */
{ .mk = {0xe0, 0x3e, 0 }, .brk = { 0xe0, 0xbe, 0 } }, /* 13e */
{ .mk = {0xe0, 0x3f, 0 }, .brk = { 0xe0, 0xbf, 0 } }, /* 13f */
{ .mk = {0xe0, 0x40, 0 }, .brk = { 0xe0, 0xc0, 0 } }, /* 140 */
{ .mk = {0xe0, 0x41, 0 }, .brk = { 0xe0, 0xc1, 0 } }, /* 141 */
{ .mk = {0xe0, 0x42, 0 }, .brk = { 0xe0, 0xc2, 0 } }, /* 142 */
{ .mk = {0xe0, 0x43, 0 }, .brk = { 0xe0, 0xc3, 0 } }, /* 143 */
{ .mk = {0xe0, 0x44, 0 }, .brk = { 0xe0, 0xc4, 0 } }, /* 144 */
{ .mk = { 0 }, .brk = { 0 } }, /* 145 */
{ .mk = {0xe0, 0x46, 0 }, .brk = { 0xe0, 0xc6, 0 } }, /* 146 */
{ .mk = {0xe0, 0x47, 0 }, .brk = { 0xe0, 0xc7, 0 } }, /* 147 */
{ .mk = {0xe0, 0x48, 0 }, .brk = { 0xe0, 0xc8, 0 } }, /* 148 */
{ .mk = {0xe0, 0x49, 0 }, .brk = { 0xe0, 0xc9, 0 } }, /* 149 */
{ .mk = { 0 }, .brk = { 0 } }, /* 14a */
{ .mk = {0xe0, 0x4b, 0 }, .brk = { 0xe0, 0xcb, 0 } }, /* 14b */
{ .mk = {0xe0, 0x4c, 0 }, .brk = { 0xe0, 0xcc, 0 } }, /* 14c */
{ .mk = {0xe0, 0x4d, 0 }, .brk = { 0xe0, 0xcd, 0 } }, /* 14d */
{ .mk = {0xe0, 0x4e, 0 }, .brk = { 0xe0, 0xce, 0 } }, /* 14e */
{ .mk = {0xe0, 0x4f, 0 }, .brk = { 0xe0, 0xcf, 0 } }, /* 14f */
{ .mk = {0xe0, 0x50, 0 }, .brk = { 0xe0, 0xd0, 0 } }, /* 150 */
{ .mk = {0xe0, 0x51, 0 }, .brk = { 0xe0, 0xd1, 0 } }, /* 151 */
{ .mk = {0xe0, 0x52, 0 }, .brk = { 0xe0, 0xd2, 0 } }, /* 152 */
{ .mk = {0xe0, 0x53, 0 }, .brk = { 0xe0, 0xd3, 0 } }, /* 153 */
{ .mk = { 0 }, .brk = { 0 } }, /* 154 */
{ .mk = {0xe0, 0x55, 0 }, .brk = { 0xe0, 0xd5, 0 } }, /* 155 */
{ .mk = { 0 }, .brk = { 0 } }, /* 156 */
{ .mk = {0xe0, 0x57, 0 }, .brk = { 0xe0, 0xd7, 0 } }, /* 157 */
{ .mk = {0xe0, 0x58, 0 }, .brk = { 0xe0, 0xd8, 0 } }, /* 158 */
{ .mk = {0xe0, 0x59, 0 }, .brk = { 0xe0, 0xd9, 0 } }, /* 159 */
{ .mk = {0xe0, 0x5a, 0 }, .brk = { 0xe0, 0xaa, 0 } }, /* 15a */
{ .mk = {0xe0, 0x5b, 0 }, .brk = { 0xe0, 0xdb, 0 } }, /* 15b */
{ .mk = {0xe0, 0x5c, 0 }, .brk = { 0xe0, 0xdc, 0 } }, /* 15c */
{ .mk = {0xe0, 0x5d, 0 }, .brk = { 0xe0, 0xdd, 0 } }, /* 15d */
{ .mk = {0xe0, 0x5e, 0 }, .brk = { 0xe0, 0xee, 0 } }, /* 15e */
{ .mk = {0xe0, 0x5f, 0 }, .brk = { 0xe0, 0xdf, 0 } }, /* 15f */
{ .mk = { 0 }, .brk = { 0 } }, /* 160 */
{ .mk = {0xe0, 0x61, 0 }, .brk = { 0xe0, 0xe1, 0 } }, /* 161 */
{ .mk = {0xe0, 0x62, 0 }, .brk = { 0xe0, 0xe2, 0 } }, /* 162 */
{ .mk = {0xe0, 0x63, 0 }, .brk = { 0xe0, 0xe3, 0 } }, /* 163 */
{ .mk = {0xe0, 0x64, 0 }, .brk = { 0xe0, 0xe4, 0 } }, /* 164 */
{ .mk = {0xe0, 0x65, 0 }, .brk = { 0xe0, 0xe5, 0 } }, /* 165 */
{ .mk = {0xe0, 0x66, 0 }, .brk = { 0xe0, 0xe6, 0 } }, /* 166 */
{ .mk = {0xe0, 0x67, 0 }, .brk = { 0xe0, 0xe7, 0 } }, /* 167 */
{ .mk = {0xe0, 0x68, 0 }, .brk = { 0xe0, 0xe8, 0 } }, /* 168 */
{ .mk = {0xe0, 0x69, 0 }, .brk = { 0xe0, 0xe9, 0 } }, /* 169 */
{ .mk = {0xe0, 0x6a, 0 }, .brk = { 0xe0, 0xea, 0 } }, /* 16a */
{ .mk = {0xe0, 0x6b, 0 }, .brk = { 0xe0, 0xeb, 0 } }, /* 16b */
{ .mk = {0xe0, 0x6c, 0 }, .brk = { 0xe0, 0xec, 0 } }, /* 16c */
{ .mk = {0xe0, 0x6d, 0 }, .brk = { 0xe0, 0xed, 0 } }, /* 16d */
{ .mk = {0xe0, 0x6e, 0 }, .brk = { 0xe0, 0xee, 0 } }, /* 16e */
{ .mk = { 0 }, .brk = { 0 } }, /* 16f */
{ .mk = {0xe0, 0x70, 0 }, .brk = { 0xe0, 0xf0, 0 } }, /* 170 */
{ .mk = {0xe0, 0x71, 0 }, .brk = { 0xe0, 0xf1, 0 } }, /* 171 */
{ .mk = {0xe0, 0x72, 0 }, .brk = { 0xe0, 0xf2, 0 } }, /* 172 */
{ .mk = {0xe0, 0x73, 0 }, .brk = { 0xe0, 0xf3, 0 } }, /* 173 */
{ .mk = {0xe0, 0x74, 0 }, .brk = { 0xe0, 0xf4, 0 } }, /* 174 */
{ .mk = {0xe0, 0x75, 0 }, .brk = { 0xe0, 0xf5, 0 } }, /* 175 */
{ .mk = { 0 }, .brk = { 0 } }, /* 176 */
{ .mk = {0xe0, 0x77, 0 }, .brk = { 0xe0, 0xf7, 0 } }, /* 177 */
{ .mk = {0xe0, 0x78, 0 }, .brk = { 0xe0, 0xf8, 0 } }, /* 178 */
{ .mk = {0xe0, 0x79, 0 }, .brk = { 0xe0, 0xf9, 0 } }, /* 179 */
{ .mk = {0xe0, 0x7a, 0 }, .brk = { 0xe0, 0xfa, 0 } }, /* 17a */
{ .mk = {0xe0, 0x7b, 0 }, .brk = { 0xe0, 0xfb, 0 } }, /* 17b */
{ .mk = {0xe0, 0x7c, 0 }, .brk = { 0xe0, 0xfc, 0 } }, /* 17c */
{ .mk = {0xe0, 0x7d, 0 }, .brk = { 0xe0, 0xfd, 0 } }, /* 17d */
{ .mk = {0xe0, 0x7e, 0 }, .brk = { 0xe0, 0xfe, 0 } }, /* 17e */
{ .mk = {0xe0, 0x7f, 0 }, .brk = { 0xe0, 0xff, 0 } }, /* 17f */
{ .mk = { 0 }, .brk = { 0 } }, /* 180 */
{ .mk = { 0 }, .brk = { 0 } }, /* 181 */
{ .mk = { 0 }, .brk = { 0 } }, /* 182 */
{ .mk = { 0 }, .brk = { 0 } }, /* 183 */
{ .mk = { 0 }, .brk = { 0 } }, /* 184 */
{ .mk = { 0 }, .brk = { 0 } }, /* 185 */
{ .mk = { 0 }, .brk = { 0 } }, /* 186 */
{ .mk = { 0 }, .brk = { 0 } }, /* 187 */
{ .mk = { 0 }, .brk = { 0 } }, /* 188 */
{ .mk = { 0 }, .brk = { 0 } }, /* 189 */
{ .mk = { 0 }, .brk = { 0 } }, /* 18a */
{ .mk = { 0 }, .brk = { 0 } }, /* 18b */
{ .mk = { 0 }, .brk = { 0 } }, /* 18c */
{ .mk = { 0 }, .brk = { 0 } }, /* 18d */
{ .mk = { 0 }, .brk = { 0 } }, /* 18e */
{ .mk = { 0 }, .brk = { 0 } }, /* 18f */
{ .mk = { 0 }, .brk = { 0 } }, /* 190 */
{ .mk = { 0 }, .brk = { 0 } }, /* 191 */
{ .mk = { 0 }, .brk = { 0 } }, /* 192 */
{ .mk = { 0 }, .brk = { 0 } }, /* 193 */
{ .mk = { 0 }, .brk = { 0 } }, /* 194 */
{ .mk = { 0 }, .brk = { 0 } }, /* 195 */
{ .mk = { 0 }, .brk = { 0 } }, /* 196 */
{ .mk = { 0 }, .brk = { 0 } }, /* 197 */
{ .mk = { 0 }, .brk = { 0 } }, /* 198 */
{ .mk = { 0 }, .brk = { 0 } }, /* 199 */
{ .mk = { 0 }, .brk = { 0 } }, /* 19a */
{ .mk = { 0 }, .brk = { 0 } }, /* 19b */
{ .mk = { 0 }, .brk = { 0 } }, /* 19c */
{ .mk = { 0 }, .brk = { 0 } }, /* 19d */
{ .mk = { 0 }, .brk = { 0 } }, /* 19e */
{ .mk = { 0 }, .brk = { 0 } }, /* 19f */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 1af */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1be */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1da */
{ .mk = { 0 }, .brk = { 0 } }, /* 1db */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1de */
{ .mk = { 0 }, .brk = { 0 } }, /* 1df */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e0 */
{ .mk = {0xe0, 0xe1, 0 }, .brk = { 0 } }, /* 1e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 1eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ed */
{ .mk = {0xe0, 0xee, 0 }, .brk = { 0 } }, /* 1ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f0 */
{ .mk = {0xe0, 0xf1, 0 }, .brk = { 0 } }, /* 1f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fd */
{ .mk = {0xe0, 0xfe, 0 }, .brk = { 0 } }, /* 1fe */
{ .mk = {0xe0, 0xff, 0 }, .brk = { 0 } } /* 1ff */
// clang-format on
};
static const scancode scancode_set2[512] = {
// clang-format off
{ .mk = { 0 }, .brk = { 0 } }, /* 000 */
{ .mk = { 0x76, 0 }, .brk = { 0xF0, 0x76, 0 } }, /* 001 */
{ .mk = { 0x16, 0 }, .brk = { 0xF0, 0x16, 0 } }, /* 002 */
{ .mk = { 0x1E, 0 }, .brk = { 0xF0, 0x1E, 0 } }, /* 003 */
{ .mk = { 0x26, 0 }, .brk = { 0xF0, 0x26, 0 } }, /* 004 */
{ .mk = { 0x25, 0 }, .brk = { 0xF0, 0x25, 0 } }, /* 005 */
{ .mk = { 0x2E, 0 }, .brk = { 0xF0, 0x2E, 0 } }, /* 006 */
{ .mk = { 0x36, 0 }, .brk = { 0xF0, 0x36, 0 } }, /* 007 */
{ .mk = { 0x3D, 0 }, .brk = { 0xF0, 0x3D, 0 } }, /* 008 */
{ .mk = { 0x3E, 0 }, .brk = { 0xF0, 0x3E, 0 } }, /* 009 */
{ .mk = { 0x46, 0 }, .brk = { 0xF0, 0x46, 0 } }, /* 00a */
{ .mk = { 0x45, 0 }, .brk = { 0xF0, 0x45, 0 } }, /* 00b */
{ .mk = { 0x4E, 0 }, .brk = { 0xF0, 0x4E, 0 } }, /* 00c */
{ .mk = { 0x55, 0 }, .brk = { 0xF0, 0x55, 0 } }, /* 00d */
{ .mk = { 0x66, 0 }, .brk = { 0xF0, 0x66, 0 } }, /* 00e */
{ .mk = { 0x0D, 0 }, .brk = { 0xF0, 0x0D, 0 } }, /* 00f */
{ .mk = { 0x15, 0 }, .brk = { 0xF0, 0x15, 0 } }, /* 010 */
{ .mk = { 0x1D, 0 }, .brk = { 0xF0, 0x1D, 0 } }, /* 011 */
{ .mk = { 0x24, 0 }, .brk = { 0xF0, 0x24, 0 } }, /* 012 */
{ .mk = { 0x2D, 0 }, .brk = { 0xF0, 0x2D, 0 } }, /* 013 */
{ .mk = { 0x2C, 0 }, .brk = { 0xF0, 0x2C, 0 } }, /* 014 */
{ .mk = { 0x35, 0 }, .brk = { 0xF0, 0x35, 0 } }, /* 015 */
{ .mk = { 0x3C, 0 }, .brk = { 0xF0, 0x3C, 0 } }, /* 016 */
{ .mk = { 0x43, 0 }, .brk = { 0xF0, 0x43, 0 } }, /* 017 */
{ .mk = { 0x44, 0 }, .brk = { 0xF0, 0x44, 0 } }, /* 018 */
{ .mk = { 0x4D, 0 }, .brk = { 0xF0, 0x4D, 0 } }, /* 019 */
{ .mk = { 0x54, 0 }, .brk = { 0xF0, 0x54, 0 } }, /* 01a */
{ .mk = { 0x5B, 0 }, .brk = { 0xF0, 0x5B, 0 } }, /* 01b */
{ .mk = { 0x5A, 0 }, .brk = { 0xF0, 0x5A, 0 } }, /* 01c */
{ .mk = { 0x14, 0 }, .brk = { 0xF0, 0x14, 0 } }, /* 01d */
{ .mk = { 0x1C, 0 }, .brk = { 0xF0, 0x1C, 0 } }, /* 01e */
{ .mk = { 0x1B, 0 }, .brk = { 0xF0, 0x1B, 0 } }, /* 01f */
{ .mk = { 0x23, 0 }, .brk = { 0xF0, 0x23, 0 } }, /* 020 */
{ .mk = { 0x2B, 0 }, .brk = { 0xF0, 0x2B, 0 } }, /* 021 */
{ .mk = { 0x34, 0 }, .brk = { 0xF0, 0x34, 0 } }, /* 022 */
{ .mk = { 0x33, 0 }, .brk = { 0xF0, 0x33, 0 } }, /* 023 */
{ .mk = { 0x3B, 0 }, .brk = { 0xF0, 0x3B, 0 } }, /* 024 */
{ .mk = { 0x42, 0 }, .brk = { 0xF0, 0x42, 0 } }, /* 025 */
{ .mk = { 0x4B, 0 }, .brk = { 0xF0, 0x4B, 0 } }, /* 026 */
{ .mk = { 0x4C, 0 }, .brk = { 0xF0, 0x4C, 0 } }, /* 027 */
{ .mk = { 0x52, 0 }, .brk = { 0xF0, 0x52, 0 } }, /* 028 */
{ .mk = { 0x0E, 0 }, .brk = { 0xF0, 0x0E, 0 } }, /* 029 */
{ .mk = { 0x12, 0 }, .brk = { 0xF0, 0x12, 0 } }, /* 02a */
{ .mk = { 0x5D, 0 }, .brk = { 0xF0, 0x5D, 0 } }, /* 02b */
{ .mk = { 0x1A, 0 }, .brk = { 0xF0, 0x1A, 0 } }, /* 02c */
{ .mk = { 0x22, 0 }, .brk = { 0xF0, 0x22, 0 } }, /* 02d */
{ .mk = { 0x21, 0 }, .brk = { 0xF0, 0x21, 0 } }, /* 02e */
{ .mk = { 0x2A, 0 }, .brk = { 0xF0, 0x2A, 0 } }, /* 02f */
{ .mk = { 0x32, 0 }, .brk = { 0xF0, 0x32, 0 } }, /* 030 */
{ .mk = { 0x31, 0 }, .brk = { 0xF0, 0x31, 0 } }, /* 031 */
{ .mk = { 0x3A, 0 }, .brk = { 0xF0, 0x3A, 0 } }, /* 032 */
{ .mk = { 0x41, 0 }, .brk = { 0xF0, 0x41, 0 } }, /* 033 */
{ .mk = { 0x49, 0 }, .brk = { 0xF0, 0x49, 0 } }, /* 034 */
{ .mk = { 0x4A, 0 }, .brk = { 0xF0, 0x4A, 0 } }, /* 035 */
{ .mk = { 0x59, 0 }, .brk = { 0xF0, 0x59, 0 } }, /* 036 */
{ .mk = { 0x7C, 0 }, .brk = { 0xF0, 0x7C, 0 } }, /* 037 */
{ .mk = { 0x11, 0 }, .brk = { 0xF0, 0x11, 0 } }, /* 038 */
{ .mk = { 0x29, 0 }, .brk = { 0xF0, 0x29, 0 } }, /* 039 */
{ .mk = { 0x58, 0 }, .brk = { 0xF0, 0x58, 0 } }, /* 03a */
{ .mk = { 0x05, 0 }, .brk = { 0xF0, 0x05, 0 } }, /* 03b */
{ .mk = { 0x06, 0 }, .brk = { 0xF0, 0x06, 0 } }, /* 03c */
{ .mk = { 0x04, 0 }, .brk = { 0xF0, 0x04, 0 } }, /* 03d */
{ .mk = { 0x0C, 0 }, .brk = { 0xF0, 0x0C, 0 } }, /* 03e */
{ .mk = { 0x03, 0 }, .brk = { 0xF0, 0x03, 0 } }, /* 03f */
{ .mk = { 0x0B, 0 }, .brk = { 0xF0, 0x0B, 0 } }, /* 040 */
{ .mk = { 0x83, 0 }, .brk = { 0xF0, 0x83, 0 } }, /* 041 */
{ .mk = { 0x0A, 0 }, .brk = { 0xF0, 0x0A, 0 } }, /* 042 */
{ .mk = { 0x01, 0 }, .brk = { 0xF0, 0x01, 0 } }, /* 043 */
{ .mk = { 0x09, 0 }, .brk = { 0xF0, 0x09, 0 } }, /* 044 */
{ .mk = { 0x77, 0 }, .brk = { 0xF0, 0x77, 0 } }, /* 045 */
{ .mk = { 0x7E, 0 }, .brk = { 0xF0, 0x7E, 0 } }, /* 046 */
{ .mk = { 0x6C, 0 }, .brk = { 0xF0, 0x6C, 0 } }, /* 047 */
{ .mk = { 0x75, 0 }, .brk = { 0xF0, 0x75, 0 } }, /* 048 */
{ .mk = { 0x7D, 0 }, .brk = { 0xF0, 0x7D, 0 } }, /* 049 */
{ .mk = { 0x7B, 0 }, .brk = { 0xF0, 0x7B, 0 } }, /* 04a */
{ .mk = { 0x6B, 0 }, .brk = { 0xF0, 0x6B, 0 } }, /* 04b */
{ .mk = { 0x73, 0 }, .brk = { 0xF0, 0x73, 0 } }, /* 04c */
{ .mk = { 0x74, 0 }, .brk = { 0xF0, 0x74, 0 } }, /* 04d */
{ .mk = { 0x79, 0 }, .brk = { 0xF0, 0x79, 0 } }, /* 04e */
{ .mk = { 0x69, 0 }, .brk = { 0xF0, 0x69, 0 } }, /* 04f */
{ .mk = { 0x72, 0 }, .brk = { 0xF0, 0x72, 0 } }, /* 050 */
{ .mk = { 0x7A, 0 }, .brk = { 0xF0, 0x7A, 0 } }, /* 051 */
{ .mk = { 0x70, 0 }, .brk = { 0xF0, 0x70, 0 } }, /* 052 */
{ .mk = { 0x71, 0 }, .brk = { 0xF0, 0x71, 0 } }, /* 053 */
{ .mk = { 0x84, 0 }, .brk = { 0xF0, 0x84, 0 } }, /* 054 */
{ .mk = { 0x60, 0 }, .brk = { 0xF0, 0x60, 0 } }, /* 055 */
{ .mk = { 0x61, 0 }, .brk = { 0xF0, 0x61, 0 } }, /* 056 */
{ .mk = { 0x78, 0 }, .brk = { 0xF0, 0x78, 0 } }, /* 057 */
{ .mk = { 0x07, 0 }, .brk = { 0xF0, 0x07, 0 } }, /* 058 */
{ .mk = { 0x0F, 0 }, .brk = { 0xF0, 0x0F, 0 } }, /* 059 */
{ .mk = { 0x17, 0 }, .brk = { 0xF0, 0x17, 0 } }, /* 05a */
{ .mk = { 0x1F, 0 }, .brk = { 0xF0, 0x1F, 0 } }, /* 05b */
{ .mk = { 0x27, 0 }, .brk = { 0xF0, 0x27, 0 } }, /* 05c */
{ .mk = { 0x2F, 0 }, .brk = { 0xF0, 0x2F, 0 } }, /* 05d */
{ .mk = { 0x37, 0 }, .brk = { 0xF0, 0x37, 0 } }, /* 05e */
{ .mk = { 0x3F, 0 }, .brk = { 0xF0, 0x3F, 0 } }, /* 05f */
{ .mk = { 0x47, 0 }, .brk = { 0xF0, 0x47, 0 } }, /* 060 */
{ .mk = { 0x4F, 0 }, .brk = { 0xF0, 0x4F, 0 } }, /* 061 */
{ .mk = { 0x56, 0 }, .brk = { 0xF0, 0x56, 0 } }, /* 062 */
{ .mk = { 0x5E, 0 }, .brk = { 0xF0, 0x5E, 0 } }, /* 063 */
{ .mk = { 0x08, 0 }, .brk = { 0xF0, 0x08, 0 } }, /* 064 */
{ .mk = { 0x10, 0 }, .brk = { 0xF0, 0x10, 0 } }, /* 065 */
{ .mk = { 0x18, 0 }, .brk = { 0xF0, 0x18, 0 } }, /* 066 */
{ .mk = { 0x20, 0 }, .brk = { 0xF0, 0x20, 0 } }, /* 067 */
{ .mk = { 0x28, 0 }, .brk = { 0xF0, 0x28, 0 } }, /* 068 */
{ .mk = { 0x30, 0 }, .brk = { 0xF0, 0x30, 0 } }, /* 069 */
{ .mk = { 0x38, 0 }, .brk = { 0xF0, 0x38, 0 } }, /* 06a */
{ .mk = { 0x40, 0 }, .brk = { 0xF0, 0x40, 0 } }, /* 06b */
{ .mk = { 0x48, 0 }, .brk = { 0xF0, 0x48, 0 } }, /* 06c */
{ .mk = { 0x50, 0 }, .brk = { 0xF0, 0x50, 0 } }, /* 06d */
{ .mk = { 0x57, 0 }, .brk = { 0xF0, 0x57, 0 } }, /* 06e */
{ .mk = { 0x6F, 0 }, .brk = { 0xF0, 0x6F, 0 } }, /* 06f */
{ .mk = { 0x13, 0 }, .brk = { 0xF0, 0x13, 0 } }, /* 070 */
{ .mk = { 0x19, 0 }, .brk = { 0xF0, 0x19, 0 } }, /* 071 */
{ .mk = { 0x39, 0 }, .brk = { 0xF0, 0x39, 0 } }, /* 072 */
{ .mk = { 0x51, 0 }, .brk = { 0xF0, 0x51, 0 } }, /* 073 */
{ .mk = { 0x53, 0 }, .brk = { 0xF0, 0x53, 0 } }, /* 074 */
{ .mk = { 0x5C, 0 }, .brk = { 0xF0, 0x5C, 0 } }, /* 075 */
{ .mk = { 0x5F, 0 }, .brk = { 0xF0, 0x5F, 0 } }, /* 076 */
{ .mk = { 0x62, 0 }, .brk = { 0xF0, 0x62, 0 } }, /* 077 */
{ .mk = { 0x63, 0 }, .brk = { 0xF0, 0x63, 0 } }, /* 078 */
{ .mk = { 0x64, 0 }, .brk = { 0xF0, 0x64, 0 } }, /* 079 */
{ .mk = { 0x65, 0 }, .brk = { 0xF0, 0x65, 0 } }, /* 07a */
{ .mk = { 0x67, 0 }, .brk = { 0xF0, 0x67, 0 } }, /* 07b */
{ .mk = { 0x68, 0 }, .brk = { 0xF0, 0x68, 0 } }, /* 07c */
{ .mk = { 0x6A, 0 }, .brk = { 0xF0, 0x6A, 0 } }, /* 07d */
{ .mk = { 0x6D, 0 }, .brk = { 0xF0, 0x6D, 0 } }, /* 07e */
{ .mk = { 0x6E, 0 }, .brk = { 0xF0, 0x6E, 0 } }, /* 07f */
{ .mk = { 0x80, 0 }, .brk = { 0xf0, 0x80, 0 } }, /* 080 */
{ .mk = { 0x81, 0 }, .brk = { 0xf0, 0x81, 0 } }, /* 081 */
{ .mk = { 0x82, 0 }, .brk = { 0xf0, 0x82, 0 } }, /* 082 */
{ .mk = { 0 }, .brk = { 0 } }, /* 083 */
{ .mk = { 0 }, .brk = { 0 } }, /* 084 */
{ .mk = { 0x85, 0 }, .brk = { 0xf0, 0x54, 0 } }, /* 085 */
{ .mk = { 0x86, 0 }, .brk = { 0xf0, 0x86, 0 } }, /* 086 */
{ .mk = { 0x87, 0 }, .brk = { 0xf0, 0x87, 0 } }, /* 087 */
{ .mk = { 0x88, 0 }, .brk = { 0xf0, 0x88, 0 } }, /* 088 */
{ .mk = { 0x89, 0 }, .brk = { 0xf0, 0x89, 0 } }, /* 089 */
{ .mk = { 0x8a, 0 }, .brk = { 0xf0, 0x8a, 0 } }, /* 08a */
{ .mk = { 0x8b, 0 }, .brk = { 0xf0, 0x8b, 0 } }, /* 08b */
{ .mk = { 0x8c, 0 }, .brk = { 0xf0, 0x8c, 0 } }, /* 08c */
{ .mk = { 0x8d, 0 }, .brk = { 0xf0, 0x8d, 0 } }, /* 08d */
{ .mk = { 0x8e, 0 }, .brk = { 0xf0, 0x8e, 0 } }, /* 08e */
{ .mk = { 0x8f, 0 }, .brk = { 0xf0, 0x8f, 0 } }, /* 08f */
{ .mk = { 0x90, 0 }, .brk = { 0xf0, 0x90, 0 } }, /* 090 */
{ .mk = { 0x91, 0 }, .brk = { 0xf0, 0x91, 0 } }, /* 091 */
{ .mk = { 0x92, 0 }, .brk = { 0xf0, 0x92, 0 } }, /* 092 */
{ .mk = { 0x93, 0 }, .brk = { 0xf0, 0x93, 0 } }, /* 093 */
{ .mk = { 0x94, 0 }, .brk = { 0xf0, 0x94, 0 } }, /* 094 */
{ .mk = { 0x95, 0 }, .brk = { 0xf0, 0x95, 0 } }, /* 095 */
{ .mk = { 0x96, 0 }, .brk = { 0xf0, 0x96, 0 } }, /* 096 */
{ .mk = { 0x97, 0 }, .brk = { 0xf0, 0x97, 0 } }, /* 097 */
{ .mk = { 0x98, 0 }, .brk = { 0xf0, 0x98, 0 } }, /* 098 */
{ .mk = { 0x99, 0 }, .brk = { 0xf0, 0x99, 0 } }, /* 099 */
{ .mk = { 0x9a, 0 }, .brk = { 0xf0, 0x9a, 0 } }, /* 09a */
{ .mk = { 0x9b, 0 }, .brk = { 0xf0, 0x9b, 0 } }, /* 09b */
{ .mk = { 0x9c, 0 }, .brk = { 0xf0, 0x9c, 0 } }, /* 09c */
{ .mk = { 0x9d, 0 }, .brk = { 0xf0, 0x9d, 0 } }, /* 09d */
{ .mk = { 0x9e, 0 }, .brk = { 0xf0, 0x9e, 0 } }, /* 09e */
{ .mk = { 0x9f, 0 }, .brk = { 0xf0, 0x9f, 0 } }, /* 09f */
{ .mk = { 0xa0, 0 }, .brk = { 0xf0, 0xa0, 0 } }, /* 0a0 */
{ .mk = { 0xa1, 0 }, .brk = { 0xf0, 0xa1, 0 } }, /* 0a1 */
{ .mk = { 0xa2, 0 }, .brk = { 0xf0, 0xa2, 0 } }, /* 0a2 */
{ .mk = { 0xa3, 0 }, .brk = { 0xf0, 0xa3, 0 } }, /* 0a3 */
{ .mk = { 0xa4, 0 }, .brk = { 0xf0, 0xa4, 0 } }, /* 0a4 */
{ .mk = { 0xa5, 0 }, .brk = { 0xf0, 0xa5, 0 } }, /* 0a5 */
{ .mk = { 0xa6, 0 }, .brk = { 0xf0, 0xa6, 0 } }, /* 0a6 */
{ .mk = { 0xa7, 0 }, .brk = { 0xf0, 0xa7, 0 } }, /* 0a7 */
{ .mk = { 0xa8, 0 }, .brk = { 0xf0, 0xa8, 0 } }, /* 0a8 */
{ .mk = { 0xa9, 0 }, .brk = { 0xf0, 0xa9, 0 } }, /* 0a9 */
{ .mk = { 0xaa, 0 }, .brk = { 0xf0, 0xaa, 0 } }, /* 0aa */
{ .mk = { 0xab, 0 }, .brk = { 0xf0, 0xab, 0 } }, /* 0ab */
{ .mk = { 0xac, 0 }, .brk = { 0xf0, 0xac, 0 } }, /* 0ac */
{ .mk = { 0xad, 0 }, .brk = { 0xf0, 0xad, 0 } }, /* 0ad */
{ .mk = { 0xae, 0 }, .brk = { 0xf0, 0xae, 0 } }, /* 0ae */
{ .mk = { 0xaf, 0 }, .brk = { 0xf0, 0xaf, 0 } }, /* 0af */
{ .mk = { 0xb0, 0 }, .brk = { 0xf0, 0xb0, 0 } }, /* 0b0 */
{ .mk = { 0xb1, 0 }, .brk = { 0xf0, 0xb1, 0 } }, /* 0b1 */
{ .mk = { 0xb2, 0 }, .brk = { 0xf0, 0xb2, 0 } }, /* 0b2 */
{ .mk = { 0xb3, 0 }, .brk = { 0xf0, 0xb3, 0 } }, /* 0b3 */
{ .mk = { 0xb4, 0 }, .brk = { 0xf0, 0xb4, 0 } }, /* 0b4 */
{ .mk = { 0xb5, 0 }, .brk = { 0xf0, 0xb5, 0 } }, /* 0b5 */
{ .mk = { 0xb6, 0 }, .brk = { 0xf0, 0xb6, 0 } }, /* 0b6 */
{ .mk = { 0xb7, 0 }, .brk = { 0xf0, 0xb7, 0 } }, /* 0b7 */
{ .mk = { 0xb8, 0 }, .brk = { 0xf0, 0xb8, 0 } }, /* 0b8 */
{ .mk = { 0xb9, 0 }, .brk = { 0xf0, 0xb9, 0 } }, /* 0b9 */
{ .mk = { 0xba, 0 }, .brk = { 0xf0, 0xba, 0 } }, /* 0ba */
{ .mk = { 0xbb, 0 }, .brk = { 0xf0, 0xbb, 0 } }, /* 0bb */
{ .mk = { 0xbc, 0 }, .brk = { 0xf0, 0xbc, 0 } }, /* 0bc */
{ .mk = { 0xbd, 0 }, .brk = { 0xf0, 0xbd, 0 } }, /* 0bd */
{ .mk = { 0xbe, 0 }, .brk = { 0xf0, 0xbe, 0 } }, /* 0be */
{ .mk = { 0xbf, 0 }, .brk = { 0xf0, 0xbf, 0 } }, /* 0bf */
{ .mk = { 0xc0, 0 }, .brk = { 0xf0, 0xc0, 0 } }, /* 0c0 */
{ .mk = { 0xc1, 0 }, .brk = { 0xf0, 0xc1, 0 } }, /* 0c1 */
{ .mk = { 0xc2, 0 }, .brk = { 0xf0, 0xc2, 0 } }, /* 0c2 */
{ .mk = { 0xc3, 0 }, .brk = { 0xf0, 0xc3, 0 } }, /* 0c3 */
{ .mk = { 0xc4, 0 }, .brk = { 0xf0, 0xc4, 0 } }, /* 0c4 */
{ .mk = { 0xc5, 0 }, .brk = { 0xf0, 0xc5, 0 } }, /* 0c5 */
{ .mk = { 0xc6, 0 }, .brk = { 0xf0, 0xc6, 0 } }, /* 0c6 */
{ .mk = { 0xc7, 0 }, .brk = { 0xf0, 0xc7, 0 } }, /* 0c7 */
{ .mk = { 0xc8, 0 }, .brk = { 0xf0, 0xc8, 0 } }, /* 0c8 */
{ .mk = { 0xc9, 0 }, .brk = { 0xf0, 0xc9, 0 } }, /* 0c9 */
{ .mk = { 0xca, 0 }, .brk = { 0xf0, 0xca, 0 } }, /* 0ca */
{ .mk = { 0xcb, 0 }, .brk = { 0xf0, 0xcb, 0 } }, /* 0cb */
{ .mk = { 0xcc, 0 }, .brk = { 0xf0, 0xcc, 0 } }, /* 0cc */
{ .mk = { 0xcd, 0 }, .brk = { 0xf0, 0xcd, 0 } }, /* 0cd */
{ .mk = { 0xce, 0 }, .brk = { 0xf0, 0xce, 0 } }, /* 0ce */
{ .mk = { 0xcf, 0 }, .brk = { 0xf0, 0xcf, 0 } }, /* 0cf */
{ .mk = { 0xd0, 0 }, .brk = { 0xf0, 0xd0, 0 } }, /* 0d0 */
{ .mk = { 0xd1, 0 }, .brk = { 0xf0, 0xd0, 0 } }, /* 0d1 */
{ .mk = { 0xd2, 0 }, .brk = { 0xf0, 0xd2, 0 } }, /* 0d2 */
{ .mk = { 0xd3, 0 }, .brk = { 0xf0, 0xd3, 0 } }, /* 0d3 */
{ .mk = { 0xd4, 0 }, .brk = { 0xf0, 0xd4, 0 } }, /* 0d4 */
{ .mk = { 0xd5, 0 }, .brk = { 0xf0, 0xd5, 0 } }, /* 0d5 */
{ .mk = { 0xd6, 0 }, .brk = { 0xf0, 0xd6, 0 } }, /* 0d6 */
{ .mk = { 0xd7, 0 }, .brk = { 0xf0, 0xd7, 0 } }, /* 0d7 */
{ .mk = { 0xd8, 0 }, .brk = { 0xf0, 0xd8, 0 } }, /* 0d8 */
{ .mk = { 0xd9, 0 }, .brk = { 0xf0, 0xd9, 0 } }, /* 0d9 */
{ .mk = { 0xda, 0 }, .brk = { 0xf0, 0xda, 0 } }, /* 0da */
{ .mk = { 0xdb, 0 }, .brk = { 0xf0, 0xdb, 0 } }, /* 0db */
{ .mk = { 0xdc, 0 }, .brk = { 0xf0, 0xdc, 0 } }, /* 0dc */
{ .mk = { 0xdd, 0 }, .brk = { 0xf0, 0xdd, 0 } }, /* 0dd */
{ .mk = { 0xde, 0 }, .brk = { 0xf0, 0xde, 0 } }, /* 0de */
{ .mk = { 0xdf, 0 }, .brk = { 0xf0, 0xdf, 0 } }, /* 0df */
{ .mk = { 0xe0, 0 }, .brk = { 0xf0, 0xe0, 0 } }, /* 0e0 */
{ .mk = { 0xe1, 0 }, .brk = { 0xf0, 0xe1, 0 } }, /* 0e1 */
{ .mk = { 0xe2, 0 }, .brk = { 0xf0, 0xe2, 0 } }, /* 0e2 */
{ .mk = { 0xe3, 0 }, .brk = { 0xf0, 0xe3, 0 } }, /* 0e3 */
{ .mk = { 0xe4, 0 }, .brk = { 0xf0, 0xe4, 0 } }, /* 0e4 */
{ .mk = { 0xe5, 0 }, .brk = { 0xf0, 0xe5, 0 } }, /* 0e5 */
{ .mk = { 0xe6, 0 }, .brk = { 0xf0, 0xe6, 0 } }, /* 0e6 */
{ .mk = { 0xe7, 0 }, .brk = { 0xf0, 0xe7, 0 } }, /* 0e7 */
{ .mk = { 0xe8, 0 }, .brk = { 0xf0, 0xe8, 0 } }, /* 0e8 */
{ .mk = { 0xe9, 0 }, .brk = { 0xf0, 0xe9, 0 } }, /* 0e9 */
{ .mk = { 0xea, 0 }, .brk = { 0xf0, 0xea, 0 } }, /* 0ea */
{ .mk = { 0xeb, 0 }, .brk = { 0xf0, 0xeb, 0 } }, /* 0eb */
{ .mk = { 0xec, 0 }, .brk = { 0xf0, 0xec, 0 } }, /* 0ec */
{ .mk = { 0xed, 0 }, .brk = { 0xf0, 0xed, 0 } }, /* 0ed */
{ .mk = { 0xee, 0 }, .brk = { 0xf0, 0xee, 0 } }, /* 0ee */
{ .mk = { 0xef, 0 }, .brk = { 0xf0, 0xef, 0 } }, /* 0ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f0 */
{ .mk = { 0xf1, 0 }, .brk = { 0xf0, 0xf1, 0 } }, /* 0f1 */
{ .mk = { 0xf2, 0 }, .brk = { 0xf0, 0xf2, 0 } }, /* 0f2 */
{ .mk = { 0xf3, 0 }, .brk = { 0xf0, 0xf3, 0 } }, /* 0f3 */
{ .mk = { 0xf4, 0 }, .brk = { 0xf0, 0xf4, 0 } }, /* 0f4 */
{ .mk = { 0xf5, 0 }, .brk = { 0xf0, 0xf5, 0 } }, /* 0f5 */
{ .mk = { 0xf6, 0 }, .brk = { 0xf0, 0xf6, 0 } }, /* 0f6 */
{ .mk = { 0xf7, 0 }, .brk = { 0xf0, 0xf7, 0 } }, /* 0f7 */
{ .mk = { 0xf8, 0 }, .brk = { 0xf0, 0xf8, 0 } }, /* 0f8 */
{ .mk = { 0xf9, 0 }, .brk = { 0xf0, 0xf9, 0 } }, /* 0f9 */
{ .mk = { 0xfa, 0 }, .brk = { 0xf0, 0xfa, 0 } }, /* 0fa */
{ .mk = { 0xfb, 0 }, .brk = { 0xf0, 0xfb, 0 } }, /* 0fb */
{ .mk = { 0xfc, 0 }, .brk = { 0xf0, 0xfc, 0 } }, /* 0fc */
{ .mk = { 0xfd, 0 }, .brk = { 0xf0, 0xfd, 0 } }, /* 0fd */
{ .mk = { 0xfe, 0 }, .brk = { 0xf0, 0xfe, 0 } }, /* 0fe */
{ .mk = { 0xff, 0 }, .brk = { 0xf0, 0xff, 0 } }, /* 0ff */
{ .mk = {0xe1, 0x14, 0 }, .brk = { 0xe1, 0xf0, 0x14, 0 } }, /* 100 */
{ .mk = {0xe0, 0x76, 0 }, .brk = { 0xe0, 0xF0, 0x76, 0 } }, /* 101 */
{ .mk = {0xe0, 0x16, 0 }, .brk = { 0xe0, 0xF0, 0x16, 0 } }, /* 102 */
{ .mk = {0xe0, 0x1E, 0 }, .brk = { 0xe0, 0xF0, 0x1E, 0 } }, /* 103 */
{ .mk = {0xe0, 0x26, 0 }, .brk = { 0xe0, 0xF0, 0x26, 0 } }, /* 104 */
{ .mk = {0xe0, 0x25, 0 }, .brk = { 0xe0, 0xF0, 0x25, 0 } }, /* 105 */
{ .mk = {0xe0, 0x2E, 0 }, .brk = { 0xe0, 0xF0, 0x2E, 0 } }, /* 106 */
{ .mk = {0xe0, 0x36, 0 }, .brk = { 0xe0, 0xF0, 0x36, 0 } }, /* 107 */
{ .mk = {0xe0, 0x3D, 0 }, .brk = { 0xe0, 0xF0, 0x3D, 0 } }, /* 108 */
{ .mk = {0xe0, 0x3E, 0 }, .brk = { 0xe0, 0xF0, 0x3E, 0 } }, /* 109 */
{ .mk = {0xe0, 0x46, 0 }, .brk = { 0xe0, 0xF0, 0x46, 0 } }, /* 10a */
{ .mk = {0xe0, 0x45, 0 }, .brk = { 0xe0, 0xF0, 0x45, 0 } }, /* 10b */
{ .mk = {0xe0, 0x4E, 0 }, .brk = { 0xe0, 0xF0, 0x4E, 0 } }, /* 10c */
{ .mk = { 0 }, .brk = { 0 } }, /* 10d */
{ .mk = {0xe0, 0x66, 0 }, .brk = { 0xe0, 0xF0, 0x66, 0 } }, /* 10e */
{ .mk = {0xe0, 0x0D, 0 }, .brk = { 0xe0, 0xF0, 0x0D, 0 } }, /* 10f */
{ .mk = {0xe0, 0x15, 0 }, .brk = { 0xe0, 0xF0, 0x15, 0 } }, /* 110 */
{ .mk = {0xe0, 0x1D, 0 }, .brk = { 0xe0, 0xF0, 0x1D, 0 } }, /* 112 */
{ .mk = {0xe0, 0x24, 0 }, .brk = { 0xe0, 0xF0, 0x24, 0 } }, /* 113 */
{ .mk = {0xe0, 0x2D, 0 }, .brk = { 0xe0, 0xF0, 0x2D, 0 } }, /* 113 */
{ .mk = {0xe0, 0x2C, 0 }, .brk = { 0xe0, 0xF0, 0x2C, 0 } }, /* 114 */
{ .mk = {0xe0, 0x35, 0 }, .brk = { 0xe0, 0xF0, 0x35, 0 } }, /* 115 */
{ .mk = {0xe0, 0x3C, 0 }, .brk = { 0xe0, 0xF0, 0x3C, 0 } }, /* 116 */
{ .mk = {0xe0, 0x43, 0 }, .brk = { 0xe0, 0xF0, 0x43, 0 } }, /* 117 */
{ .mk = {0xe0, 0x44, 0 }, .brk = { 0xe0, 0xF0, 0x44, 0 } }, /* 118 */
{ .mk = {0xe0, 0x4D, 0 }, .brk = { 0xe0, 0xF0, 0x4D, 0 } }, /* 119 */
{ .mk = {0xe0, 0x54, 0 }, .brk = { 0xe0, 0xF0, 0x54, 0 } }, /* 11a */
{ .mk = {0xe0, 0x5B, 0 }, .brk = { 0xe0, 0xF0, 0x5B, 0 } }, /* 11b */
{ .mk = {0xe0, 0x5A, 0 }, .brk = { 0xe0, 0xF0, 0x5A, 0 } }, /* 11c */
{ .mk = {0xe0, 0x14, 0 }, .brk = { 0xe0, 0xF0, 0x14, 0 } }, /* 11d */
{ .mk = {0xe0, 0x1C, 0 }, .brk = { 0xe0, 0xF0, 0x1C, 0 } }, /* 11e */
{ .mk = {0xe0, 0x1B, 0 }, .brk = { 0xe0, 0xF0, 0x1B, 0 } }, /* 11f */
{ .mk = {0xe0, 0x23, 0 }, .brk = { 0xe0, 0xF0, 0x23, 0 } }, /* 120 */
{ .mk = {0xe0, 0x2B, 0 }, .brk = { 0xe0, 0xF0, 0x2B, 0 } }, /* 121 */
{ .mk = {0xe0, 0x34, 0 }, .brk = { 0xe0, 0xF0, 0x34, 0 } }, /* 122 */
{ .mk = {0xe0, 0x33, 0 }, .brk = { 0xe0, 0xF0, 0x33, 0 } }, /* 123 */
{ .mk = {0xe0, 0x3B, 0 }, .brk = { 0xe0, 0xF0, 0x3B, 0 } }, /* 124 */
{ .mk = {0xe0, 0x42, 0 }, .brk = { 0xe0, 0xF0, 0x42, 0 } }, /* 125 */
{ .mk = {0xe0, 0x4B, 0 }, .brk = { 0xe0, 0xF0, 0x4B, 0 } }, /* 126 */
{ .mk = { 0 }, .brk = { 0 } }, /* 127 */
{ .mk = { 0 }, .brk = { 0 } }, /* 128 */
{ .mk = { 0 }, .brk = { 0 } }, /* 129 */
{ .mk = { 0 }, .brk = { 0 } }, /* 12a */
{ .mk = { 0 }, .brk = { 0 } }, /* 12b */
{ .mk = {0xe0, 0x1A, 0 }, .brk = { 0xe0, 0xF0, 0x1A, 0 } }, /* 12c */
{ .mk = {0xe0, 0x22, 0 }, .brk = { 0xe0, 0xF0, 0x22, 0 } }, /* 12d */
{ .mk = {0xe0, 0x21, 0 }, .brk = { 0xe0, 0xF0, 0x21, 0 } }, /* 12e */
{ .mk = {0xe0, 0x2A, 0 }, .brk = { 0xe0, 0xF0, 0x2A, 0 } }, /* 12f */
{ .mk = {0xe0, 0x32, 0 }, .brk = { 0xe0, 0xF0, 0x32, 0 } }, /* 130 */
{ .mk = {0xe0, 0x31, 0 }, .brk = { 0xe0, 0xF0, 0x31, 0 } }, /* 131 */
{ .mk = {0xe0, 0x3A, 0 }, .brk = { 0xe0, 0xF0, 0x3A, 0 } }, /* 132 */
{ .mk = { 0 }, .brk = { 0 } }, /* 133 */
{ .mk = {0xe0, 0x49, 0 }, .brk = { 0xe0, 0xF0, 0x49, 0 } }, /* 134 */
{ .mk = {0xe0, 0x4A, 0 }, .brk = { 0xe0, 0xF0, 0x4A, 0 } }, /* 135 */
{ .mk = { 0 }, .brk = { 0 } }, /* 136 */
{ .mk = {0xe0, 0x7C, 0 }, .brk = { 0xe0, 0xF0, 0x7C, 0 } }, /* 137 */
{ .mk = {0xe0, 0x11, 0 }, .brk = { 0xe0, 0xF0, 0x11, 0 } }, /* 138 */
{ .mk = { 0 }, .brk = { 0 } }, /* 139 */
{ .mk = {0xe0, 0x58, 0 }, .brk = { 0xe0, 0xF0, 0x58, 0 } }, /* 13a */
{ .mk = {0xe0, 0x05, 0 }, .brk = { 0xe0, 0xF0, 0x05, 0 } }, /* 13b */
{ .mk = {0xe0, 0x06, 0 }, .brk = { 0xe0, 0xF0, 0x06, 0 } }, /* 13c */
{ .mk = {0xe0, 0x04, 0 }, .brk = { 0xe0, 0xF0, 0x04, 0 } }, /* 13d */
{ .mk = {0xe0, 0x0C, 0 }, .brk = { 0xe0, 0xF0, 0x0C, 0 } }, /* 13e */
{ .mk = {0xe0, 0x03, 0 }, .brk = { 0xe0, 0xF0, 0x03, 0 } }, /* 13f */
{ .mk = {0xe0, 0x0B, 0 }, .brk = { 0xe0, 0xF0, 0x0B, 0 } }, /* 140 */
{ .mk = {0xe0, 0x02, 0 }, .brk = { 0xe0, 0xF0, 0x02, 0 } }, /* 141 */
{ .mk = {0xe0, 0x0A, 0 }, .brk = { 0xe0, 0xF0, 0x0A, 0 } }, /* 142 */
{ .mk = {0xe0, 0x01, 0 }, .brk = { 0xe0, 0xF0, 0x01, 0 } }, /* 143 */
{ .mk = {0xe0, 0x09, 0 }, .brk = { 0xe0, 0xF0, 0x09, 0 } }, /* 144 */
{ .mk = { 0 }, .brk = { 0 } }, /* 145 */
{ .mk = {0xe0, 0x7E, 0 }, .brk = { 0xe0, 0xF0, 0x7E, 0 } }, /* 146 */
{ .mk = {0xe0, 0x6C, 0 }, .brk = { 0xe0, 0xF0, 0x6C, 0 } }, /* 147 */
{ .mk = {0xe0, 0x75, 0 }, .brk = { 0xe0, 0xF0, 0x75, 0 } }, /* 148 */
{ .mk = {0xe0, 0x7D, 0 }, .brk = { 0xe0, 0xF0, 0x7D, 0 } }, /* 149 */
{ .mk = { 0 }, .brk = { 0 } }, /* 14a */
{ .mk = {0xe0, 0x6B, 0 }, .brk = { 0xe0, 0xF0, 0x6B, 0 } }, /* 14b */
{ .mk = {0xe0, 0x73, 0 }, .brk = { 0xe0, 0xF0, 0x73, 0 } }, /* 14c */
{ .mk = {0xe0, 0x74, 0 }, .brk = { 0xe0, 0xF0, 0x74, 0 } }, /* 14d */
{ .mk = {0xe0, 0x79, 0 }, .brk = { 0xe0, 0xF0, 0x79, 0 } }, /* 14e */
{ .mk = {0xe0, 0x69, 0 }, .brk = { 0xe0, 0xF0, 0x69, 0 } }, /* 14f */
{ .mk = {0xe0, 0x72, 0 }, .brk = { 0xe0, 0xF0, 0x72, 0 } }, /* 150 */
{ .mk = {0xe0, 0x7A, 0 }, .brk = { 0xe0, 0xF0, 0x7A, 0 } }, /* 151 */
{ .mk = {0xe0, 0x70, 0 }, .brk = { 0xe0, 0xF0, 0x70, 0 } }, /* 152 */
{ .mk = {0xe0, 0x71, 0 }, .brk = { 0xe0, 0xF0, 0x71, 0 } }, /* 153 */
{ .mk = { 0 }, .brk = { 0 } }, /* 154 */
{ .mk = {0xe0, 0x60, 0 }, .brk = { 0xe0, 0xF0, 0x60, 0 } }, /* 155 */
{ .mk = { 0 }, .brk = { 0 } }, /* 156 */
{ .mk = {0xe0, 0x78, 0 }, .brk = { 0xe0, 0xF0, 0x78, 0 } }, /* 157 */
{ .mk = {0xe0, 0x07, 0 }, .brk = { 0xe0, 0xF0, 0x07, 0 } }, /* 158 */
{ .mk = {0xe0, 0x0F, 0 }, .brk = { 0xe0, 0xF0, 0x0F, 0 } }, /* 159 */
{ .mk = {0xe0, 0x17, 0 }, .brk = { 0xe0, 0xF0, 0x17, 0 } }, /* 15a */
{ .mk = {0xe0, 0x1F, 0 }, .brk = { 0xe0, 0xF0, 0x1F, 0 } }, /* 15b */
{ .mk = {0xe0, 0x27, 0 }, .brk = { 0xe0, 0xF0, 0x27, 0 } }, /* 15c */
{ .mk = {0xe0, 0x2F, 0 }, .brk = { 0xe0, 0xF0, 0x2F, 0 } }, /* 15d */
{ .mk = {0xe0, 0x37, 0 }, .brk = { 0xe0, 0xF0, 0x37, 0 } }, /* 15e */
{ .mk = {0xe0, 0x3F, 0 }, .brk = { 0xe0, 0xF0, 0x3F, 0 } }, /* 15f */
{ .mk = { 0 }, .brk = { 0 } }, /* 160 */
{ .mk = {0xe0, 0x4F, 0 }, .brk = { 0xe0, 0xF0, 0x4F, 0 } }, /* 161 */
{ .mk = {0xe0, 0x56, 0 }, .brk = { 0xe0, 0xF0, 0x56, 0 } }, /* 162 */
{ .mk = {0xe0, 0x5E, 0 }, .brk = { 0xe0, 0xF0, 0x5E, 0 } }, /* 163 */
{ .mk = {0xe0, 0x08, 0 }, .brk = { 0xe0, 0xF0, 0x08, 0 } }, /* 164 */
{ .mk = {0xe0, 0x10, 0 }, .brk = { 0xe0, 0xF0, 0x10, 0 } }, /* 165 */
{ .mk = {0xe0, 0x18, 0 }, .brk = { 0xe0, 0xF0, 0x18, 0 } }, /* 166 */
{ .mk = {0xe0, 0x20, 0 }, .brk = { 0xe0, 0xF0, 0x20, 0 } }, /* 167 */
{ .mk = {0xe0, 0x28, 0 }, .brk = { 0xe0, 0xF0, 0x28, 0 } }, /* 168 */
{ .mk = {0xe0, 0x30, 0 }, .brk = { 0xe0, 0xF0, 0x30, 0 } }, /* 169 */
{ .mk = {0xe0, 0x38, 0 }, .brk = { 0xe0, 0xF0, 0x38, 0 } }, /* 16a */
{ .mk = {0xe0, 0x40, 0 }, .brk = { 0xe0, 0xF0, 0x40, 0 } }, /* 16b */
{ .mk = {0xe0, 0x48, 0 }, .brk = { 0xe0, 0xF0, 0x48, 0 } }, /* 16c */
{ .mk = {0xe0, 0x50, 0 }, .brk = { 0xe0, 0xF0, 0x50, 0 } }, /* 16d */
{ .mk = {0xe0, 0x57, 0 }, .brk = { 0xe0, 0xF0, 0x57, 0 } }, /* 16e */
{ .mk = { 0 }, .brk = { 0 } }, /* 16f */
{ .mk = {0xe0, 0x13, 0 }, .brk = { 0xe0, 0xF0, 0x13, 0 } }, /* 170 */
{ .mk = {0xe0, 0x19, 0 }, .brk = { 0xe0, 0xF0, 0x19, 0 } }, /* 171 */
{ .mk = {0xe0, 0x39, 0 }, .brk = { 0xe0, 0xF0, 0x39, 0 } }, /* 172 */
{ .mk = {0xe0, 0x51, 0 }, .brk = { 0xe0, 0xF0, 0x51, 0 } }, /* 173 */
{ .mk = {0xe0, 0x53, 0 }, .brk = { 0xe0, 0xF0, 0x53, 0 } }, /* 174 */
{ .mk = {0xe0, 0x5C, 0 }, .brk = { 0xe0, 0xF0, 0x5C, 0 } }, /* 175 */
{ .mk = { 0 }, .brk = { 0 } }, /* 176 */
{ .mk = {0xe0, 0x62, 0 }, .brk = { 0xe0, 0xF0, 0x62, 0 } }, /* 177 */
{ .mk = {0xe0, 0x63, 0 }, .brk = { 0xe0, 0xF0, 0x63, 0 } }, /* 178 */
{ .mk = {0xe0, 0x64, 0 }, .brk = { 0xe0, 0xF0, 0x64, 0 } }, /* 179 */
{ .mk = {0xe0, 0x65, 0 }, .brk = { 0xe0, 0xF0, 0x65, 0 } }, /* 17a */
{ .mk = {0xe0, 0x67, 0 }, .brk = { 0xe0, 0xF0, 0x67, 0 } }, /* 17b */
{ .mk = {0xe0, 0x68, 0 }, .brk = { 0xe0, 0xF0, 0x68, 0 } }, /* 17c */
{ .mk = {0xe0, 0x6A, 0 }, .brk = { 0xe0, 0xF0, 0x6A, 0 } }, /* 17d */
{ .mk = {0xe0, 0x6D, 0 }, .brk = { 0xe0, 0xF0, 0x6D, 0 } }, /* 17e */
{ .mk = {0xe0, 0x6E, 0 }, .brk = { 0xe0, 0xF0, 0x6E, 0 } }, /* 17f */
{ .mk = { 0 }, .brk = { 0 } }, /* 180 */
{ .mk = { 0 }, .brk = { 0 } }, /* 181 */
{ .mk = { 0 }, .brk = { 0 } }, /* 182 */
{ .mk = { 0 }, .brk = { 0 } }, /* 183 */
{ .mk = { 0 }, .brk = { 0 } }, /* 184 */
{ .mk = { 0 }, .brk = { 0 } }, /* 185 */
{ .mk = { 0 }, .brk = { 0 } }, /* 186 */
{ .mk = { 0 }, .brk = { 0 } }, /* 187 */
{ .mk = { 0 }, .brk = { 0 } }, /* 188 */
{ .mk = { 0 }, .brk = { 0 } }, /* 189 */
{ .mk = { 0 }, .brk = { 0 } }, /* 18a */
{ .mk = { 0 }, .brk = { 0 } }, /* 18b */
{ .mk = { 0 }, .brk = { 0 } }, /* 18c */
{ .mk = { 0 }, .brk = { 0 } }, /* 18d */
{ .mk = { 0 }, .brk = { 0 } }, /* 18e */
{ .mk = { 0 }, .brk = { 0 } }, /* 18f */
{ .mk = { 0 }, .brk = { 0 } }, /* 190 */
{ .mk = { 0 }, .brk = { 0 } }, /* 191 */
{ .mk = { 0 }, .brk = { 0 } }, /* 192 */
{ .mk = { 0 }, .brk = { 0 } }, /* 193 */
{ .mk = { 0 }, .brk = { 0 } }, /* 194 */
{ .mk = { 0 }, .brk = { 0 } }, /* 195 */
{ .mk = { 0 }, .brk = { 0 } }, /* 196 */
{ .mk = { 0 }, .brk = { 0 } }, /* 197 */
{ .mk = { 0 }, .brk = { 0 } }, /* 198 */
{ .mk = { 0 }, .brk = { 0 } }, /* 199 */
{ .mk = { 0 }, .brk = { 0 } }, /* 19a */
{ .mk = { 0 }, .brk = { 0 } }, /* 19b */
{ .mk = { 0 }, .brk = { 0 } }, /* 19c */
{ .mk = { 0 }, .brk = { 0 } }, /* 19d */
{ .mk = { 0 }, .brk = { 0 } }, /* 19e */
{ .mk = { 0 }, .brk = { 0 } }, /* 19f */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 1af */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1be */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cv */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1da */
{ .mk = { 0 }, .brk = { 0 } }, /* 1db */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1de */
{ .mk = { 0 }, .brk = { 0 } }, /* 1df */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e0 */
{ .mk = {0xe0, 0xe1, 0 }, .brk = { 0xe0, 0xF0, 0xE1, 0 } }, /* 1e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 1eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ed */
{ .mk = {0xe0, 0xee, 0 }, .brk = { 0xe0, 0xF0, 0xEE, 0 } }, /* 1ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f0 */
{ .mk = {0xe0, 0xf1, 0 }, .brk = { 0xe0, 0xF0, 0xF1, 0 } }, /* 1f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fd */
{ .mk = {0xe0, 0xfe, 0 }, .brk = { 0xe0, 0xF0, 0xFE, 0 } }, /* 1fe */
{ .mk = {0xe0, 0xff, 0 }, .brk = { 0xe0, 0xF0, 0xFF, 0 } } /* 1ff */
// clang-format on
};
static const scancode scancode_set3[512] = {
// clang-format off
{ .mk = { 0 }, .brk = { 0 } }, /* 000 */
{ .mk = { 0x08, 0 }, .brk = { 0xf0, 0x08, 0 } }, /* 001 */
{ .mk = { 0x16, 0 }, .brk = { 0xf0, 0x16, 0 } }, /* 002 */
{ .mk = { 0x1E, 0 }, .brk = { 0xf0, 0x1E, 0 } }, /* 003 */
{ .mk = { 0x26, 0 }, .brk = { 0xf0, 0x26, 0 } }, /* 004 */
{ .mk = { 0x25, 0 }, .brk = { 0xf0, 0x25, 0 } }, /* 005 */
{ .mk = { 0x2E, 0 }, .brk = { 0xf0, 0x2E, 0 } }, /* 006 */
{ .mk = { 0x36, 0 }, .brk = { 0xf0, 0x36, 0 } }, /* 007 */
{ .mk = { 0x3D, 0 }, .brk = { 0xf0, 0x3D, 0 } }, /* 008 */
{ .mk = { 0x3E, 0 }, .brk = { 0xf0, 0x3E, 0 } }, /* 009 */
{ .mk = { 0x46, 0 }, .brk = { 0xf0, 0x46, 0 } }, /* 00a */
{ .mk = { 0x45, 0 }, .brk = { 0xf0, 0x45, 0 } }, /* 00b */
{ .mk = { 0x4E, 0 }, .brk = { 0xf0, 0x4E, 0 } }, /* 00c */
{ .mk = { 0x55, 0 }, .brk = { 0xf0, 0x55, 0 } }, /* 00d */
{ .mk = { 0x66, 0 }, .brk = { 0xf0, 0x66, 0 } }, /* 00e */
{ .mk = { 0x0D, 0 }, .brk = { 0xf0, 0x0D, 0 } }, /* 00f */
{ .mk = { 0x15, 0 }, .brk = { 0xf0, 0x15, 0 } }, /* 010 */
{ .mk = { 0x1D, 0 }, .brk = { 0xf0, 0x1D, 0 } }, /* 011 */
{ .mk = { 0x24, 0 }, .brk = { 0xf0, 0x24, 0 } }, /* 012 */
{ .mk = { 0x2D, 0 }, .brk = { 0xf0, 0x2D, 0 } }, /* 013 */
{ .mk = { 0x2C, 0 }, .brk = { 0xf0, 0x2C, 0 } }, /* 014 */
{ .mk = { 0x35, 0 }, .brk = { 0xf0, 0x35, 0 } }, /* 015 */
{ .mk = { 0x3C, 0 }, .brk = { 0xf0, 0x3C, 0 } }, /* 016 */
{ .mk = { 0x43, 0 }, .brk = { 0xf0, 0x43, 0 } }, /* 017 */
{ .mk = { 0x44, 0 }, .brk = { 0xf0, 0x44, 0 } }, /* 018 */
{ .mk = { 0x4D, 0 }, .brk = { 0xf0, 0x4D, 0 } }, /* 019 */
{ .mk = { 0x54, 0 }, .brk = { 0xf0, 0x54, 0 } }, /* 01a */
{ .mk = { 0x5B, 0 }, .brk = { 0xf0, 0x5B, 0 } }, /* 01b */
{ .mk = { 0x5A, 0 }, .brk = { 0xf0, 0x5A, 0 } }, /* 01c */
{ .mk = { 0x11, 0 }, .brk = { 0xf0, 0x11, 0 } }, /* 01d */
{ .mk = { 0x1C, 0 }, .brk = { 0xf0, 0x1C, 0 } }, /* 01e */
{ .mk = { 0x1B, 0 }, .brk = { 0xf0, 0x1B, 0 } }, /* 01f */
{ .mk = { 0x23, 0 }, .brk = { 0xf0, 0x23, 0 } }, /* 020 */
{ .mk = { 0x2B, 0 }, .brk = { 0xf0, 0x2B, 0 } }, /* 021 */
{ .mk = { 0x34, 0 }, .brk = { 0xf0, 0x34, 0 } }, /* 022 */
{ .mk = { 0x33, 0 }, .brk = { 0xf0, 0x33, 0 } }, /* 023 */
{ .mk = { 0x3B, 0 }, .brk = { 0xf0, 0x3B, 0 } }, /* 024 */
{ .mk = { 0x42, 0 }, .brk = { 0xf0, 0x42, 0 } }, /* 025 */
{ .mk = { 0x4B, 0 }, .brk = { 0xf0, 0x4B, 0 } }, /* 026 */
{ .mk = { 0x4C, 0 }, .brk = { 0xf0, 0x4C, 0 } }, /* 027 */
{ .mk = { 0x52, 0 }, .brk = { 0xf0, 0x52, 0 } }, /* 028 */
{ .mk = { 0x0E, 0 }, .brk = { 0xf0, 0x0E, 0 } }, /* 029 */
{ .mk = { 0x12, 0 }, .brk = { 0xf0, 0x12, 0 } }, /* 02a */
{ .mk = { 0x5C, 0 }, .brk = { 0xf0, 0x5C, 0 } }, /* 02b */
{ .mk = { 0x1A, 0 }, .brk = { 0xf0, 0x1A, 0 } }, /* 02c */
{ .mk = { 0x22, 0 }, .brk = { 0xf0, 0x22, 0 } }, /* 02d */
{ .mk = { 0x21, 0 }, .brk = { 0xf0, 0x21, 0 } }, /* 02e */
{ .mk = { 0x2A, 0 }, .brk = { 0xf0, 0x2A, 0 } }, /* 02f */
{ .mk = { 0x32, 0 }, .brk = { 0xf0, 0x32, 0 } }, /* 030 */
{ .mk = { 0x31, 0 }, .brk = { 0xf0, 0x31, 0 } }, /* 031 */
{ .mk = { 0x3A, 0 }, .brk = { 0xf0, 0x3A, 0 } }, /* 032 */
{ .mk = { 0x41, 0 }, .brk = { 0xf0, 0x41, 0 } }, /* 033 */
{ .mk = { 0x49, 0 }, .brk = { 0xf0, 0x49, 0 } }, /* 034 */
{ .mk = { 0x4A, 0 }, .brk = { 0xf0, 0x4A, 0 } }, /* 035 */
{ .mk = { 0x59, 0 }, .brk = { 0xf0, 0x59, 0 } }, /* 036 */
{ .mk = { 0x7E, 0 }, .brk = { 0xf0, 0x7E, 0 } }, /* 037 */
{ .mk = { 0x19, 0 }, .brk = { 0xf0, 0x19, 0 } }, /* 038 */
{ .mk = { 0x29, 0 }, .brk = { 0xf0, 0x29, 0 } }, /* 039 */
{ .mk = { 0x14, 0 }, .brk = { 0xf0, 0x14, 0 } }, /* 03a */
{ .mk = { 0x07, 0 }, .brk = { 0xf0, 0x07, 0 } }, /* 03b */
{ .mk = { 0x0F, 0 }, .brk = { 0xf0, 0x0F, 0 } }, /* 03c */
{ .mk = { 0x17, 0 }, .brk = { 0xf0, 0x17, 0 } }, /* 03d */
{ .mk = { 0x1F, 0 }, .brk = { 0xf0, 0x1F, 0 } }, /* 03e */
{ .mk = { 0x27, 0 }, .brk = { 0xf0, 0x27, 0 } }, /* 03f */
{ .mk = { 0x2F, 0 }, .brk = { 0xf0, 0x2F, 0 } }, /* 040 */
{ .mk = { 0x37, 0 }, .brk = { 0xf0, 0x37, 0 } }, /* 041 */
{ .mk = { 0x3F, 0 }, .brk = { 0xf0, 0x3F, 0 } }, /* 042 */
{ .mk = { 0x47, 0 }, .brk = { 0xf0, 0x47, 0 } }, /* 043 */
{ .mk = { 0x4F, 0 }, .brk = { 0xf0, 0x4F, 0 } }, /* 044 */
{ .mk = { 0x76, 0 }, .brk = { 0xf0, 0x76, 0 } }, /* 045 */
{ .mk = { 0x5F, 0 }, .brk = { 0xf0, 0x5F, 0 } }, /* 046 */
{ .mk = { 0x6C, 0 }, .brk = { 0xf0, 0x6C, 0 } }, /* 047 */
{ .mk = { 0x75, 0 }, .brk = { 0xf0, 0x75, 0 } }, /* 048 */
{ .mk = { 0x7D, 0 }, .brk = { 0xf0, 0x7D, 0 } }, /* 049 */
{ .mk = { 0x84, 0 }, .brk = { 0xf0, 0x84, 0 } }, /* 04a */
{ .mk = { 0x6B, 0 }, .brk = { 0xf0, 0x6B, 0 } }, /* 04b */
{ .mk = { 0x73, 0 }, .brk = { 0xf0, 0x73, 0 } }, /* 04c */
{ .mk = { 0x74, 0 }, .brk = { 0xf0, 0x74, 0 } }, /* 04d */
{ .mk = { 0x7C, 0 }, .brk = { 0xf0, 0x7C, 0 } }, /* 04e */
{ .mk = { 0x69, 0 }, .brk = { 0xf0, 0x69, 0 } }, /* 04f */
{ .mk = { 0x72, 0 }, .brk = { 0xf0, 0x72, 0 } }, /* 050 */
{ .mk = { 0x7A, 0 }, .brk = { 0xf0, 0x7A, 0 } }, /* 051 */
{ .mk = { 0x70, 0 }, .brk = { 0xf0, 0x70, 0 } }, /* 052 */
{ .mk = { 0x71, 0 }, .brk = { 0xf0, 0x71, 0 } }, /* 053 */
{ .mk = { 0x57, 0 }, .brk = { 0xf0, 0x57, 0 } }, /* 054 */
{ .mk = { 0x60, 0 }, .brk = { 0xf0, 0x60, 0 } }, /* 055 */
{ .mk = { 0 }, .brk = { 0 } }, /* 056 */
{ .mk = { 0x56, 0 }, .brk = { 0xf0, 0x56, 0 } }, /* 057 */
{ .mk = { 0x5E, 0 }, .brk = { 0xf0, 0x5E, 0 } }, /* 058 */
{ .mk = { 0 }, .brk = { 0 } }, /* 059 */
{ .mk = { 0 }, .brk = { 0 } }, /* 05a */
{ .mk = { 0 }, .brk = { 0 } }, /* 05b */
{ .mk = { 0 }, .brk = { 0 } }, /* 05c */
{ .mk = { 0 }, .brk = { 0 } }, /* 05d */
{ .mk = { 0 }, .brk = { 0 } }, /* 05e */
{ .mk = { 0 }, .brk = { 0 } }, /* 05f */
{ .mk = { 0 }, .brk = { 0 } }, /* 060 */
{ .mk = { 0 }, .brk = { 0 } }, /* 061 */
{ .mk = { 0 }, .brk = { 0 } }, /* 062 */
{ .mk = { 0 }, .brk = { 0 } }, /* 063 */
{ .mk = { 0 }, .brk = { 0 } }, /* 064 */
{ .mk = { 0x10, 0 }, .brk = { 0xf0, 0x10, 0 } }, /* 065 */
{ .mk = { 0x18, 0 }, .brk = { 0xf0, 0x18, 0 } }, /* 066 */
{ .mk = { 0x20, 0 }, .brk = { 0xf0, 0x20, 0 } }, /* 067 */
{ .mk = { 0x28, 0 }, .brk = { 0xf0, 0x28, 0 } }, /* 068 */
{ .mk = { 0x30, 0 }, .brk = { 0xf0, 0x30, 0 } }, /* 069 */
{ .mk = { 0x38, 0 }, .brk = { 0xf0, 0x38, 0 } }, /* 06a */
{ .mk = { 0x40, 0 }, .brk = { 0xf0, 0x40, 0 } }, /* 06b */
{ .mk = { 0x48, 0 }, .brk = { 0xf0, 0x48, 0 } }, /* 06c */
{ .mk = { 0x50, 0 }, .brk = { 0xf0, 0x50, 0 } }, /* 06d */
{ .mk = { 0 }, .brk = { 0 } }, /* 06e */
{ .mk = { 0 }, .brk = { 0 } }, /* 06f */
{ .mk = { 0x87, 0 }, .brk = { 0xf0, 0x87, 0 } }, /* 070 */
{ .mk = { 0 }, .brk = { 0 } }, /* 071 */
{ .mk = { 0 }, .brk = { 0 } }, /* 072 */
{ .mk = { 0x51, 0 }, .brk = { 0xf0, 0x51, 0 } }, /* 073 */
{ .mk = { 0x53, 0 }, .brk = { 0xf0, 0x53, 0 } }, /* 074 */
{ .mk = { 0x5C, 0 }, .brk = { 0xf0, 0x5C, 0 } }, /* 075 */
{ .mk = { 0 }, .brk = { 0 } }, /* 076 */
{ .mk = { 0x62, 0 }, .brk = { 0xf0, 0x62, 0 } }, /* 077 */
{ .mk = { 0x63, 0 }, .brk = { 0xf0, 0x63, 0 } }, /* 078 */
{ .mk = { 0x86, 0 }, .brk = { 0xf0, 0x86, 0 } }, /* 079 */
{ .mk = { 0 }, .brk = { 0 } }, /* 07a */
{ .mk = { 0x85, 0 }, .brk = { 0xf0, 0x85, 0 } }, /* 07b */
{ .mk = { 0x68, 0 }, .brk = { 0xf0, 0x68, 0 } }, /* 07c */
{ .mk = { 0x13, 0 }, .brk = { 0xf0, 0x13, 0 } }, /* 07d */
{ .mk = { 0 }, .brk = { 0 } }, /* 07e */
{ .mk = { 0 }, .brk = { 0 } }, /* 07f */
{ .mk = { 0x80, 0 }, .brk = { 0xf0, 0x80, 0 } }, /* 080 */
{ .mk = { 0x81, 0 }, .brk = { 0xf0, 0x81, 0 } }, /* 081 */
{ .mk = { 0x82, 0 }, .brk = { 0xf0, 0x82, 0 } }, /* 082 */
{ .mk = { 0 }, .brk = { 0 } }, /* 083 */
{ .mk = { 0 }, .brk = { 0 } }, /* 084 */
{ .mk = { 0x85, 0 }, .brk = { 0xf0, 0x54, 0 } }, /* 085 */
{ .mk = { 0x86, 0 }, .brk = { 0xf0, 0x86, 0 } }, /* 086 */
{ .mk = { 0x87, 0 }, .brk = { 0xf0, 0x87, 0 } }, /* 087 */
{ .mk = { 0x88, 0 }, .brk = { 0xf0, 0x88, 0 } }, /* 087 */
{ .mk = { 0x89, 0 }, .brk = { 0xf0, 0x89, 0 } }, /* 088 */
{ .mk = { 0x8a, 0 }, .brk = { 0xf0, 0x8a, 0 } }, /* 089 */
{ .mk = { 0x8b, 0 }, .brk = { 0xf0, 0x8b, 0 } }, /* 08b */
{ .mk = { 0 }, .brk = { 0 } }, /* 08c */
{ .mk = { 0 }, .brk = { 0 } }, /* 08d */
{ .mk = { 0x8e, 0 }, .brk = { 0xf0, 0x8e, 0 } }, /* 08e */
{ .mk = { 0x8f, 0 }, .brk = { 0xf0, 0x8f, 0 } }, /* 08f */
{ .mk = { 0x90, 0 }, .brk = { 0xf0, 0x90, 0 } }, /* 090 */
{ .mk = { 0x91, 0 }, .brk = { 0xf0, 0x91, 0 } }, /* 091 */
{ .mk = { 0x92, 0 }, .brk = { 0xf0, 0x92, 0 } }, /* 092 */
{ .mk = { 0x93, 0 }, .brk = { 0xf0, 0x93, 0 } }, /* 093 */
{ .mk = { 0x94, 0 }, .brk = { 0xf0, 0x94, 0 } }, /* 094 */
{ .mk = { 0x95, 0 }, .brk = { 0xf0, 0x95, 0 } }, /* 095 */
{ .mk = { 0x96, 0 }, .brk = { 0xf0, 0x96, 0 } }, /* 096 */
{ .mk = { 0x97, 0 }, .brk = { 0xf0, 0x97, 0 } }, /* 097 */
{ .mk = { 0x98, 0 }, .brk = { 0xf0, 0x98, 0 } }, /* 098 */
{ .mk = { 0x99, 0 }, .brk = { 0xf0, 0x99, 0 } }, /* 099 */
{ .mk = { 0x9a, 0 }, .brk = { 0xf0, 0x9a, 0 } }, /* 09a */
{ .mk = { 0x9b, 0 }, .brk = { 0xf0, 0x9b, 0 } }, /* 09b */
{ .mk = { 0x9c, 0 }, .brk = { 0xf0, 0x9c, 0 } }, /* 09c */
{ .mk = { 0x9d, 0 }, .brk = { 0xf0, 0x9d, 0 } }, /* 09d */
{ .mk = { 0x9e, 0 }, .brk = { 0xf0, 0x9e, 0 } }, /* 09e */
{ .mk = { 0x9f, 0 }, .brk = { 0xf0, 0x9f, 0 } }, /* 09f */
{ .mk = { 0xa0, 0 }, .brk = { 0xf0, 0xa0, 0 } }, /* 0a0 */
{ .mk = { 0xa1, 0 }, .brk = { 0xf0, 0xa1, 0 } }, /* 0a1 */
{ .mk = { 0xa2, 0 }, .brk = { 0xf0, 0xa2, 0 } }, /* 0a2 */
{ .mk = { 0xa3, 0 }, .brk = { 0xf0, 0xa3, 0 } }, /* 0a3 */
{ .mk = { 0xa4, 0 }, .brk = { 0xf0, 0xa4, 0 } }, /* 0a4 */
{ .mk = { 0xa5, 0 }, .brk = { 0xf0, 0xa5, 0 } }, /* 0a5 */
{ .mk = { 0xa6, 0 }, .brk = { 0xf0, 0xa6, 0 } }, /* 0a6 */
{ .mk = { 0xa7, 0 }, .brk = { 0xf0, 0xa7, 0 } }, /* 0a7 */
{ .mk = { 0xa8, 0 }, .brk = { 0xf0, 0xa8, 0 } }, /* 0a8 */
{ .mk = { 0xa9, 0 }, .brk = { 0xf0, 0xa9, 0 } }, /* 0a9 */
{ .mk = { 0xaa, 0 }, .brk = { 0xf0, 0xaa, 0 } }, /* 0aa */
{ .mk = { 0xab, 0 }, .brk = { 0xf0, 0xab, 0 } }, /* 0ab */
{ .mk = { 0xac, 0 }, .brk = { 0xf0, 0xac, 0 } }, /* 0ac */
{ .mk = { 0xad, 0 }, .brk = { 0xf0, 0xad, 0 } }, /* 0ad */
{ .mk = { 0xae, 0 }, .brk = { 0xf0, 0xae, 0 } }, /* 0ae */
{ .mk = { 0xaf, 0 }, .brk = { 0xf0, 0xaf, 0 } }, /* 0af */
{ .mk = { 0xb0, 0 }, .brk = { 0xf0, 0xb0, 0 } }, /* 0b0 */
{ .mk = { 0xb1, 0 }, .brk = { 0xf0, 0xb1, 0 } }, /* 0b1 */
{ .mk = { 0xb2, 0 }, .brk = { 0xf0, 0xb2, 0 } }, /* 0b2 */
{ .mk = { 0xb3, 0 }, .brk = { 0xf0, 0xb3, 0 } }, /* 0b3 */
{ .mk = { 0xb4, 0 }, .brk = { 0xf0, 0xb4, 0 } }, /* 0b4 */
{ .mk = { 0xb5, 0 }, .brk = { 0xf0, 0xb5, 0 } }, /* 0b5 */
{ .mk = { 0xb6, 0 }, .brk = { 0xf0, 0xb6, 0 } }, /* 0b6 */
{ .mk = { 0xb7, 0 }, .brk = { 0xf0, 0xb7, 0 } }, /* 0b7 */
{ .mk = { 0xb8, 0 }, .brk = { 0xf0, 0xb8, 0 } }, /* 0b8 */
{ .mk = { 0xb9, 0 }, .brk = { 0xf0, 0xb9, 0 } }, /* 0b9 */
{ .mk = { 0xba, 0 }, .brk = { 0xf0, 0xba, 0 } }, /* 0ba */
{ .mk = { 0xbb, 0 }, .brk = { 0xf0, 0xbb, 0 } }, /* 0bb */
{ .mk = { 0xbc, 0 }, .brk = { 0xf0, 0xbc, 0 } }, /* 0bc */
{ .mk = { 0xbd, 0 }, .brk = { 0xf0, 0xbd, 0 } }, /* 0bd */
{ .mk = { 0xbe, 0 }, .brk = { 0xf0, 0xbe, 0 } }, /* 0be */
{ .mk = { 0xbf, 0 }, .brk = { 0xf0, 0xbf, 0 } }, /* 0bf */
{ .mk = { 0xc0, 0 }, .brk = { 0xf0, 0xc0, 0 } }, /* 0c0 */
{ .mk = { 0xc1, 0 }, .brk = { 0xf0, 0xc1, 0 } }, /* 0c1 */
{ .mk = { 0xc2, 0 }, .brk = { 0xf0, 0xc2, 0 } }, /* 0c2 */
{ .mk = { 0xc3, 0 }, .brk = { 0xf0, 0xc3, 0 } }, /* 0c3 */
{ .mk = { 0xc4, 0 }, .brk = { 0xf0, 0xc4, 0 } }, /* 0c4 */
{ .mk = { 0xc5, 0 }, .brk = { 0xf0, 0xc5, 0 } }, /* 0c5 */
{ .mk = { 0xc6, 0 }, .brk = { 0xf0, 0xc6, 0 } }, /* 0c6 */
{ .mk = { 0xc7, 0 }, .brk = { 0xf0, 0xc7, 0 } }, /* 0c7 */
{ .mk = { 0xc8, 0 }, .brk = { 0xf0, 0xc8, 0 } }, /* 0c8 */
{ .mk = { 0xc9, 0 }, .brk = { 0xf0, 0xc9, 0 } }, /* 0c9 */
{ .mk = { 0xca, 0 }, .brk = { 0xf0, 0xca, 0 } }, /* 0ca */
{ .mk = { 0xcb, 0 }, .brk = { 0xf0, 0xcb, 0 } }, /* 0cb */
{ .mk = { 0xcc, 0 }, .brk = { 0xf0, 0xcc, 0 } }, /* 0cc */
{ .mk = { 0xcd, 0 }, .brk = { 0xf0, 0xcd, 0 } }, /* 0cd */
{ .mk = { 0xce, 0 }, .brk = { 0xf0, 0xce, 0 } }, /* 0ce */
{ .mk = { 0xcf, 0 }, .brk = { 0xf0, 0xcf, 0 } }, /* 0cf */
{ .mk = { 0xd0, 0 }, .brk = { 0xf0, 0xd0, 0 } }, /* 0d0 */
{ .mk = { 0xd1, 0 }, .brk = { 0xf0, 0xd0, 0 } }, /* 0d1 */
{ .mk = { 0xd2, 0 }, .brk = { 0xf0, 0xd2, 0 } }, /* 0d2 */
{ .mk = { 0xd3, 0 }, .brk = { 0xf0, 0xd3, 0 } }, /* 0d3 */
{ .mk = { 0xd4, 0 }, .brk = { 0xf0, 0xd4, 0 } }, /* 0d4 */
{ .mk = { 0xd5, 0 }, .brk = { 0xf0, 0xd5, 0 } }, /* 0d5 */
{ .mk = { 0xd6, 0 }, .brk = { 0xf0, 0xd6, 0 } }, /* 0d6 */
{ .mk = { 0xd7, 0 }, .brk = { 0xf0, 0xd7, 0 } }, /* 0d7 */
{ .mk = { 0xd8, 0 }, .brk = { 0xf0, 0xd8, 0 } }, /* 0d8 */
{ .mk = { 0xd9, 0 }, .brk = { 0xf0, 0xd9, 0 } }, /* 0d9 */
{ .mk = { 0xda, 0 }, .brk = { 0xf0, 0xda, 0 } }, /* 0da */
{ .mk = { 0xdb, 0 }, .brk = { 0xf0, 0xdb, 0 } }, /* 0db */
{ .mk = { 0xdc, 0 }, .brk = { 0xf0, 0xdc, 0 } }, /* 0dc */
{ .mk = { 0xdd, 0 }, .brk = { 0xf0, 0xdd, 0 } }, /* 0dd */
{ .mk = { 0xde, 0 }, .brk = { 0xf0, 0xde, 0 } }, /* 0de */
{ .mk = { 0xdf, 0 }, .brk = { 0xf0, 0xdf, 0 } }, /* 0df */
{ .mk = { 0xe0, 0 }, .brk = { 0xf0, 0xe0, 0 } }, /* 0e0 */
{ .mk = { 0xe1, 0 }, .brk = { 0xf0, 0xe1, 0 } }, /* 0e1 */
{ .mk = { 0xe2, 0 }, .brk = { 0xf0, 0xe2, 0 } }, /* 0e2 */
{ .mk = { 0xe3, 0 }, .brk = { 0xf0, 0xe3, 0 } }, /* 0e3 */
{ .mk = { 0xe4, 0 }, .brk = { 0xf0, 0xe4, 0 } }, /* 0e4 */
{ .mk = { 0xe5, 0 }, .brk = { 0xf0, 0xe5, 0 } }, /* 0e5 */
{ .mk = { 0xe6, 0 }, .brk = { 0xf0, 0xe6, 0 } }, /* 0e6 */
{ .mk = { 0xe7, 0 }, .brk = { 0xf0, 0xe7, 0 } }, /* 0e7 */
{ .mk = { 0xe8, 0 }, .brk = { 0xf0, 0xe8, 0 } }, /* 0e7 */
{ .mk = { 0xe9, 0 }, .brk = { 0xf0, 0xe9, 0 } }, /* 0e8 */
{ .mk = { 0xea, 0 }, .brk = { 0xf0, 0xea, 0 } }, /* 0e9 */
{ .mk = { 0xeb, 0 }, .brk = { 0xf0, 0xeb, 0 } }, /* 0eb */
{ .mk = { 0xec, 0 }, .brk = { 0xf0, 0xec, 0 } }, /* 0ec */
{ .mk = { 0xed, 0 }, .brk = { 0xf0, 0xed, 0 } }, /* 0ed */
{ .mk = { 0xee, 0 }, .brk = { 0xf0, 0xee, 0 } }, /* 0ee */
{ .mk = { 0xef, 0 }, .brk = { 0xf0, 0xef, 0 } }, /* 0ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f0 */
{ .mk = { 0xf1, 0 }, .brk = { 0xf0, 0xf1, 0 } }, /* 0f1 */
{ .mk = { 0xf2, 0 }, .brk = { 0xf0, 0xf2, 0 } }, /* 0f2 */
{ .mk = { 0xf3, 0 }, .brk = { 0xf0, 0xf3, 0 } }, /* 0f3 */
{ .mk = { 0xf4, 0 }, .brk = { 0xf0, 0xf4, 0 } }, /* 0f4 */
{ .mk = { 0xf5, 0 }, .brk = { 0xf0, 0xf5, 0 } }, /* 0f5 */
{ .mk = { 0xf6, 0 }, .brk = { 0xf0, 0xf6, 0 } }, /* 0f6 */
{ .mk = { 0xf7, 0 }, .brk = { 0xf0, 0xf7, 0 } }, /* 0f7 */
{ .mk = { 0xf8, 0 }, .brk = { 0xf0, 0xf8, 0 } }, /* 0f8 */
{ .mk = { 0xf9, 0 }, .brk = { 0xf0, 0xf9, 0 } }, /* 0f9 */
{ .mk = { 0xfa, 0 }, .brk = { 0xf0, 0xfa, 0 } }, /* 0fa */
{ .mk = { 0xfb, 0 }, .brk = { 0xf0, 0xfb, 0 } }, /* 0fb */
{ .mk = { 0xfc, 0 }, .brk = { 0xf0, 0xfc, 0 } }, /* 0fc */
{ .mk = { 0xfd, 0 }, .brk = { 0xf0, 0xfd, 0 } }, /* 0fd */
{ .mk = { 0xfe, 0 }, .brk = { 0xf0, 0xfe, 0 } }, /* 0fe */
{ .mk = { 0xff, 0 }, .brk = { 0xf0, 0xff, 0 } }, /* 0ff */
{ .mk = { 0x62, 0 }, .brk = { 0xF0, 0x62, 0 } }, /* 100 */
{ .mk = {0xe0, 0x76, 0 }, .brk = { 0xe0, 0xF0, 0x76, 0 } }, /* 101 */
{ .mk = {0xe0, 0x16, 0 }, .brk = { 0xe0, 0xF0, 0x16, 0 } }, /* 102 */
{ .mk = {0xe0, 0x1E, 0 }, .brk = { 0xe0, 0xF0, 0x1E, 0 } }, /* 103 */
{ .mk = {0xe0, 0x26, 0 }, .brk = { 0xe0, 0xF0, 0x26, 0 } }, /* 104 */
{ .mk = {0xe0, 0x25, 0 }, .brk = { 0xe0, 0xF0, 0x25, 0 } }, /* 105 */
{ .mk = {0xe0, 0x2E, 0 }, .brk = { 0xe0, 0xF0, 0x2E, 0 } }, /* 106 */
{ .mk = {0xe0, 0x36, 0 }, .brk = { 0xe0, 0xF0, 0x36, 0 } }, /* 107 */
{ .mk = {0xe0, 0x3D, 0 }, .brk = { 0xe0, 0xF0, 0x3D, 0 } }, /* 108 */
{ .mk = {0xe0, 0x3E, 0 }, .brk = { 0xe0, 0xF0, 0x3E, 0 } }, /* 109 */
{ .mk = {0xe0, 0x46, 0 }, .brk = { 0xe0, 0xF0, 0x46, 0 } }, /* 10a */
{ .mk = {0xe0, 0x45, 0 }, .brk = { 0xe0, 0xF0, 0x45, 0 } }, /* 10b */
{ .mk = {0xe0, 0x4E, 0 }, .brk = { 0xe0, 0xF0, 0x4E, 0 } }, /* 10c */
{ .mk = { 0 }, .brk = { 0 } }, /* 10d */
{ .mk = {0xe0, 0x66, 0 }, .brk = { 0xe0, 0xF0, 0x66, 0 } }, /* 10e */
{ .mk = {0xe0, 0x0D, 0 }, .brk = { 0xe0, 0xF0, 0x0D, 0 } }, /* 10f */
{ .mk = {0xe0, 0x15, 0 }, .brk = { 0xe0, 0xF0, 0x15, 0 } }, /* 110 */
{ .mk = {0xe0, 0x1D, 0 }, .brk = { 0xe0, 0xF0, 0x1D, 0 } }, /* 111 */
{ .mk = {0xe0, 0x24, 0 }, .brk = { 0xe0, 0xF0, 0x24, 0 } }, /* 112 */
{ .mk = {0xe0, 0x2D, 0 }, .brk = { 0xe0, 0xF0, 0x2D, 0 } }, /* 113 */
{ .mk = {0xe0, 0x2C, 0 }, .brk = { 0xe0, 0xF0, 0x2C, 0 } }, /* 114 */
{ .mk = {0xe0, 0x35, 0 }, .brk = { 0xe0, 0xF0, 0x35, 0 } }, /* 115 */
{ .mk = {0xe0, 0x3C, 0 }, .brk = { 0xe0, 0xF0, 0x3C, 0 } }, /* 116 */
{ .mk = {0xe0, 0x43, 0 }, .brk = { 0xe0, 0xF0, 0x43, 0 } }, /* 117 */
{ .mk = {0xe0, 0x44, 0 }, .brk = { 0xe0, 0xF0, 0x44, 0 } }, /* 118 */
{ .mk = {0xe0, 0x4D, 0 }, .brk = { 0xe0, 0xF0, 0x4D, 0 } }, /* 119 */
{ .mk = {0xe0, 0x54, 0 }, .brk = { 0xe0, 0xF0, 0x54, 0 } }, /* 11a */
{ .mk = {0xe0, 0x5B, 0 }, .brk = { 0xe0, 0xF0, 0x5B, 0 } }, /* 11b */
{ .mk = { 0x79, 0 }, .brk = { 0xf0, 0x79, 0 } }, /* 11c */
{ .mk = { 0x58, 0 }, .brk = { 0xf0, 0x58, 0 } }, /* 11d */
{ .mk = {0xe0, 0x1C, 0 }, .brk = { 0xe0, 0xF0, 0x1C, 0 } }, /* 11e */
{ .mk = {0xe0, 0x1B, 0 }, .brk = { 0xe0, 0xF0, 0x1B, 0 } }, /* 11f */
{ .mk = {0xe0, 0x23, 0 }, .brk = { 0xe0, 0xF0, 0x23, 0 } }, /* 120 */
{ .mk = {0xe0, 0x2B, 0 }, .brk = { 0xe0, 0xF0, 0x2B, 0 } }, /* 121 */
{ .mk = {0xe0, 0x34, 0 }, .brk = { 0xe0, 0xF0, 0x34, 0 } }, /* 122 */
{ .mk = {0xe0, 0x33, 0 }, .brk = { 0xe0, 0xF0, 0x33, 0 } }, /* 123 */
{ .mk = {0xe0, 0x3B, 0 }, .brk = { 0xe0, 0xF0, 0x3B, 0 } }, /* 124 */
{ .mk = {0xe0, 0x42, 0 }, .brk = { 0xe0, 0xF0, 0x42, 0 } }, /* 125 */
{ .mk = {0xe0, 0x4B, 0 }, .brk = { 0xe0, 0xF0, 0x4B, 0 } }, /* 126 */
{ .mk = { 0 }, .brk = { 0 } }, /* 127 */
{ .mk = { 0 }, .brk = { 0 } }, /* 128 */
{ .mk = { 0 }, .brk = { 0 } }, /* 129 */
{ .mk = { 0 }, .brk = { 0 } }, /* 12a */
{ .mk = { 0 }, .brk = { 0 } }, /* 12b */
{ .mk = {0xe0, 0x1A, 0 }, .brk = { 0xe0, 0xF0, 0x1A, 0 } }, /* 12c */
{ .mk = {0xe0, 0x22, 0 }, .brk = { 0xe0, 0xF0, 0x22, 0 } }, /* 12d */
{ .mk = {0xe0, 0x21, 0 }, .brk = { 0xe0, 0xF0, 0x21, 0 } }, /* 12e */
{ .mk = {0xe0, 0x2A, 0 }, .brk = { 0xe0, 0xF0, 0x2A, 0 } }, /* 12f */
{ .mk = {0xe0, 0x32, 0 }, .brk = { 0xe0, 0xF0, 0x32, 0 } }, /* 130 */
{ .mk = {0xe0, 0x31, 0 }, .brk = { 0xe0, 0xF0, 0x31, 0 } }, /* 131 */
{ .mk = {0xe0, 0x3A, 0 }, .brk = { 0xe0, 0xF0, 0x3A, 0 } }, /* 132 */
{ .mk = { 0 }, .brk = { 0 } }, /* 133 */
{ .mk = {0xe0, 0x49, 0 }, .brk = { 0xe0, 0xF0, 0x49, 0 } }, /* 134 */
{ .mk = { 0x77, 0 }, .brk = { 0xf0, 0x77, 0 } }, /* 135 */
{ .mk = { 0 }, .brk = { 0 } }, /* 136 */
{ .mk = { 0x57, 0 }, .brk = { 0xf0, 0x57, 0 } }, /* 137 */
{ .mk = { 0x39, 0 }, .brk = { 0xf0, 0x39, 0 } }, /* 138 */
{ .mk = { 0 }, .brk = { 0 } }, /* 139 */
{ .mk = {0xe0, 0x58, 0 }, .brk = { 0xe0, 0xF0, 0x58, 0 } }, /* 13a */
{ .mk = {0xe0, 0x05, 0 }, .brk = { 0xe0, 0xF0, 0x05, 0 } }, /* 13b */
{ .mk = {0xe0, 0x06, 0 }, .brk = { 0xe0, 0xF0, 0x06, 0 } }, /* 13c */
{ .mk = {0xe0, 0x04, 0 }, .brk = { 0xe0, 0xF0, 0x04, 0 } }, /* 13d */
{ .mk = {0xe0, 0x0C, 0 }, .brk = { 0xe0, 0xF0, 0x0C, 0 } }, /* 13e */
{ .mk = {0xe0, 0x03, 0 }, .brk = { 0xe0, 0xF0, 0x03, 0 } }, /* 13f */
{ .mk = {0xe0, 0x0B, 0 }, .brk = { 0xe0, 0xF0, 0x0B, 0 } }, /* 140 */
{ .mk = {0xe0, 0x02, 0 }, .brk = { 0xe0, 0xF0, 0x02, 0 } }, /* 141 */
{ .mk = {0xe0, 0x0A, 0 }, .brk = { 0xe0, 0xF0, 0x0A, 0 } }, /* 142 */
{ .mk = {0xe0, 0x01, 0 }, .brk = { 0xe0, 0xF0, 0x01, 0 } }, /* 143 */
{ .mk = {0xe0, 0x09, 0 }, .brk = { 0xe0, 0xF0, 0x09, 0 } }, /* 144 */
{ .mk = { 0 }, .brk = { 0 } }, /* 145 */
{ .mk = {0xe0, 0x7E, 0 }, .brk = { 0xe0, 0xF0, 0x7E, 0 } }, /* 146 */
{ .mk = { 0x6E, 0 }, .brk = { 0xf0, 0x6E, 0 } }, /* 147 */
{ .mk = { 0x63, 0 }, .brk = { 0xf0, 0x63, 0 } }, /* 148 */
{ .mk = { 0x6F, 0 }, .brk = { 0xf0, 0x6F, 0 } }, /* 149 */
{ .mk = { 0 }, .brk = { 0 } }, /* 14a */
{ .mk = { 0x61, 0 }, .brk = { 0xf0, 0x61, 0 } }, /* 14b */
{ .mk = {0xe0, 0x73, 0 }, .brk = { 0xe0, 0xF0, 0x73, 0 } }, /* 14c */
{ .mk = { 0x6A, 0 }, .brk = { 0xf0, 0x6A, 0 } }, /* 14d */
{ .mk = {0xe0, 0x79, 0 }, .brk = { 0xe0, 0xF0, 0x79, 0 } }, /* 14e */
{ .mk = { 0x65, 0 }, .brk = { 0xf0, 0x65, 0 } }, /* 14f */
{ .mk = { 0x60, 0 }, .brk = { 0xf0, 0x60, 0 } }, /* 150 */
{ .mk = { 0x6D, 0 }, .brk = { 0xf0, 0x6D, 0 } }, /* 151 */
{ .mk = { 0x67, 0 }, .brk = { 0xf0, 0x67, 0 } }, /* 152 */
{ .mk = { 0x64, 0 }, .brk = { 0xf0, 0x64, 0 } }, /* 153 */
{ .mk = { 0xd4, 0 }, .brk = { 0xf0, 0xD4, 0 } }, /* 154 */
{ .mk = {0xe0, 0x60, 0 }, .brk = { 0xe0, 0xF0, 0x60, 0 } }, /* 155 */
{ .mk = { 0 }, .brk = { 0 } }, /* 156 */
{ .mk = {0xe0, 0x78, 0 }, .brk = { 0xe0, 0xF0, 0x78, 0 } }, /* 157 */
{ .mk = {0xe0, 0x07, 0 }, .brk = { 0xe0, 0xF0, 0x07, 0 } }, /* 158 */
{ .mk = {0xe0, 0x0F, 0 }, .brk = { 0xe0, 0xF0, 0x0F, 0 } }, /* 159 */
{ .mk = {0xe0, 0x17, 0 }, .brk = { 0xe0, 0xF0, 0x17, 0 } }, /* 15a */
{ .mk = { 0x8B, 0 }, .brk = { 0xf0, 0x8B, 0 } }, /* 15b */
{ .mk = { 0x8C, 0 }, .brk = { 0xf0, 0x8C, 0 } }, /* 15c */
{ .mk = { 0x8D, 0 }, .brk = { 0xf0, 0x8D, 0 } }, /* 15d */
{ .mk = { 0 }, .brk = { 0 } }, /* 15e */
{ .mk = { 0x7F, 0 }, .brk = { 0xf0, 0x7F, 0 } }, /* 15f */
{ .mk = { 0 }, .brk = { 0 } }, /* 160 */
{ .mk = {0xe0, 0x4F, 0 }, .brk = { 0xe0, 0xF0, 0x4F, 0 } }, /* 161 */
{ .mk = {0xe0, 0x56, 0 }, .brk = { 0xe0, 0xF0, 0x56, 0 } }, /* 162 */
{ .mk = { 0 }, .brk = { 0 } }, /* 163 */
{ .mk = {0xe0, 0x08, 0 }, .brk = { 0xe0, 0xF0, 0x08, 0 } }, /* 164 */
{ .mk = {0xe0, 0x10, 0 }, .brk = { 0xe0, 0xF0, 0x10, 0 } }, /* 165 */
{ .mk = {0xe0, 0x18, 0 }, .brk = { 0xe0, 0xF0, 0x18, 0 } }, /* 166 */
{ .mk = {0xe0, 0x20, 0 }, .brk = { 0xe0, 0xF0, 0x20, 0 } }, /* 167 */
{ .mk = {0xe0, 0x28, 0 }, .brk = { 0xe0, 0xF0, 0x28, 0 } }, /* 168 */
{ .mk = {0xe0, 0x30, 0 }, .brk = { 0xe0, 0xF0, 0x30, 0 } }, /* 169 */
{ .mk = {0xe0, 0x38, 0 }, .brk = { 0xe0, 0xF0, 0x38, 0 } }, /* 16a */
{ .mk = {0xe0, 0x40, 0 }, .brk = { 0xe0, 0xF0, 0x40, 0 } }, /* 16b */
{ .mk = {0xe0, 0x48, 0 }, .brk = { 0xe0, 0xF0, 0x48, 0 } }, /* 16c */
{ .mk = {0xe0, 0x50, 0 }, .brk = { 0xe0, 0xF0, 0x50, 0 } }, /* 16d */
{ .mk = {0xe0, 0x57, 0 }, .brk = { 0xe0, 0xF0, 0x57, 0 } }, /* 16e */
{ .mk = { 0 }, .brk = { 0 } }, /* 16f */
{ .mk = {0xe0, 0x13, 0 }, .brk = { 0xe0, 0xF0, 0x13, 0 } }, /* 170 */
{ .mk = {0xe0, 0x19, 0 }, .brk = { 0xe0, 0xF0, 0x19, 0 } }, /* 171 */
{ .mk = {0xe0, 0x39, 0 }, .brk = { 0xe0, 0xF0, 0x39, 0 } }, /* 172 */
{ .mk = {0xe0, 0x51, 0 }, .brk = { 0xe0, 0xF0, 0x51, 0 } }, /* 173 */
{ .mk = {0xe0, 0x53, 0 }, .brk = { 0xe0, 0xF0, 0x53, 0 } }, /* 174 */
{ .mk = {0xe0, 0x5C, 0 }, .brk = { 0xe0, 0xF0, 0x5C, 0 } }, /* 175 */
{ .mk = { 0 }, .brk = { 0 } }, /* 176 */
{ .mk = {0xe0, 0x62, 0 }, .brk = { 0xe0, 0xF0, 0x62, 0 } }, /* 177 */
{ .mk = {0xe0, 0x63, 0 }, .brk = { 0xe0, 0xF0, 0x63, 0 } }, /* 178 */
{ .mk = {0xe0, 0x64, 0 }, .brk = { 0xe0, 0xF0, 0x64, 0 } }, /* 179 */
{ .mk = {0xe0, 0x65, 0 }, .brk = { 0xe0, 0xF0, 0x65, 0 } }, /* 17a */
{ .mk = {0xe0, 0x67, 0 }, .brk = { 0xe0, 0xF0, 0x67, 0 } }, /* 17b */
{ .mk = {0xe0, 0x68, 0 }, .brk = { 0xe0, 0xF0, 0x68, 0 } }, /* 17c */
{ .mk = {0xe0, 0x6A, 0 }, .brk = { 0xe0, 0xF0, 0x6A, 0 } }, /* 17d */
{ .mk = {0xe0, 0x6D, 0 }, .brk = { 0xe0, 0xF0, 0x6D, 0 } }, /* 17e */
{ .mk = {0xe0, 0x6E, 0 }, .brk = { 0xe0, 0xF0, 0x6E, 0 } }, /* 17f */
{ .mk = { 0 }, .brk = { 0 } }, /* 180 */
{ .mk = { 0 }, .brk = { 0 } }, /* 181 */
{ .mk = { 0 }, .brk = { 0 } }, /* 182 */
{ .mk = { 0 }, .brk = { 0 } }, /* 183 */
{ .mk = { 0 }, .brk = { 0 } }, /* 184 */
{ .mk = { 0 }, .brk = { 0 } }, /* 185 */
{ .mk = { 0 }, .brk = { 0 } }, /* 186 */
{ .mk = { 0 }, .brk = { 0 } }, /* 187 */
{ .mk = { 0 }, .brk = { 0 } }, /* 188 */
{ .mk = { 0 }, .brk = { 0 } }, /* 189 */
{ .mk = { 0 }, .brk = { 0 } }, /* 18a */
{ .mk = { 0 }, .brk = { 0 } }, /* 18b */
{ .mk = { 0 }, .brk = { 0 } }, /* 18c */
{ .mk = { 0 }, .brk = { 0 } }, /* 18d */
{ .mk = { 0 }, .brk = { 0 } }, /* 18e */
{ .mk = { 0 }, .brk = { 0 } }, /* 18f */
{ .mk = { 0 }, .brk = { 0 } }, /* 190 */
{ .mk = { 0 }, .brk = { 0 } }, /* 191 */
{ .mk = { 0 }, .brk = { 0 } }, /* 192 */
{ .mk = { 0 }, .brk = { 0 } }, /* 193 */
{ .mk = { 0 }, .brk = { 0 } }, /* 194 */
{ .mk = { 0 }, .brk = { 0 } }, /* 195 */
{ .mk = { 0 }, .brk = { 0 } }, /* 196 */
{ .mk = { 0 }, .brk = { 0 } }, /* 197 */
{ .mk = { 0 }, .brk = { 0 } }, /* 198 */
{ .mk = { 0 }, .brk = { 0 } }, /* 199 */
{ .mk = { 0 }, .brk = { 0 } }, /* 19a */
{ .mk = { 0 }, .brk = { 0 } }, /* 19b */
{ .mk = { 0 }, .brk = { 0 } }, /* 19c */
{ .mk = { 0 }, .brk = { 0 } }, /* 19d */
{ .mk = { 0 }, .brk = { 0 } }, /* 19e */
{ .mk = { 0 }, .brk = { 0 } }, /* 19f */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 1af */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1be */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1da */
{ .mk = { 0 }, .brk = { 0 } }, /* 1db */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1de */
{ .mk = { 0 }, .brk = { 0 } }, /* 1df */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e0 */
{ .mk = {0xe0, 0xe1, 0 }, .brk = { 0xe0, 0xF0, 0xE1, 0 } }, /* 1e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 1eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ed */
{ .mk = {0xe0, 0xee, 0 }, .brk = { 0xe0, 0xF0, 0xEE, 0 } }, /* 1ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f0 */
{ .mk = {0xe0, 0xf1, 0 }, .brk = { 0xe0, 0xF0, 0xF1, 0 } }, /* 1f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fd */
{ .mk = {0xe0, 0xfe, 0 }, .brk = { 0xe0, 0xF0, 0xFE, 0 } }, /* 1fe */
{ .mk = {0xe0, 0xff, 0 }, .brk = { 0xe0, 0xF0, 0xFF, 0 } } /* 1ff */
// clang-format on
};
#ifdef ENABLE_KEYBOARD_AT_LOG
int keyboard_at_do_log = ENABLE_KEYBOARD_AT_LOG;
static void
keyboard_at_log(const char *fmt, ...)
{
va_list ap;
if (keyboard_at_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define keyboard_at_log(fmt, ...)
#endif
static void
keyboard_at_set_scancode_set(void)
{
switch (keyboard_mode) {
default:
case 0x01:
keyboard_set_table(scancode_set1);
break;
case 0x02:
keyboard_set_table(scancode_set2);
break;
case 0x03:
keyboard_set_table(scancode_set3);
break;
}
}
static void
add_data_vals(atkbc_dev_t *dev, uint8_t *val, uint8_t len)
{
for (uint8_t i = 0; i < len; i++)
kbc_at_dev_queue_add(dev, val[i], 1);
}
static void
add_data_kbd(uint16_t val)
{
atkbc_dev_t *dev = SavedKbd;
uint8_t fake_shift[4] = { 0 };
uint8_t num_lock = 0;
uint8_t shift_states = 0;
dev->ignore = 1;
keyboard_get_states(NULL, &num_lock, NULL);
shift_states = keyboard_get_shift() & STATE_SHIFT_MASK;
switch (val) {
case FAKE_LSHIFT_ON:
keyboard_at_log("%s: Fake left shift on, scan code: ", dev->name);
if (num_lock) {
if (shift_states) {
keyboard_at_log("N/A (one or both shifts on)\n");
break;
} else {
/* Num lock on and no shifts are pressed, send non-inverted fake shift. */
switch (keyboard_mode & 0x02) {
case 1:
keyboard_at_log("E0 2A\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0x2a;
add_data_vals(dev, fake_shift, 2);
break;
case 2:
keyboard_at_log("E0 12\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0x12;
add_data_vals(dev, fake_shift, 2);
break;
default:
keyboard_at_log("N/A (scan code set %i)\n", keyboard_mode & 0x02);
break;
}
}
} else {
if (shift_states & STATE_LSHIFT) {
/* Num lock off and left shift pressed. */
switch (keyboard_mode & 0x02) {
case 1:
keyboard_at_log("E0 AA\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0xaa;
add_data_vals(dev, fake_shift, 2);
break;
case 2:
keyboard_at_log("E0 F0 12\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0xf0;
fake_shift[2] = 0x12;
add_data_vals(dev, fake_shift, 3);
break;
default:
keyboard_at_log("N/A (scan code set %i)\n", keyboard_mode & 0x02);
break;
}
}
if (shift_states & STATE_RSHIFT) {
/* Num lock off and right shift pressed. */
switch (keyboard_mode & 0x02) {
case 1:
keyboard_at_log("E0 B6\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0xb6;
add_data_vals(dev, fake_shift, 2);
break;
case 2:
keyboard_at_log("E0 F0 59\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0xf0;
fake_shift[2] = 0x59;
add_data_vals(dev, fake_shift, 3);
break;
default:
keyboard_at_log("N/A (scan code set %i)\n", keyboard_mode & 0x02);
break;
}
}
keyboard_at_log(shift_states ? "" : "N/A (both shifts off)\n");
}
break;
case FAKE_LSHIFT_OFF:
keyboard_at_log("%s: Fake left shift on, scan code: ", dev->name);
if (num_lock) {
if (shift_states) {
keyboard_at_log("N/A (one or both shifts on)\n");
break;
} else {
/* Num lock on and no shifts are pressed, send non-inverted fake shift. */
switch (keyboard_mode & 0x02) {
case 1:
keyboard_at_log("E0 AA\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0xaa;
add_data_vals(dev, fake_shift, 2);
break;
case 2:
keyboard_at_log("E0 F0 12\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0xf0;
fake_shift[2] = 0x12;
add_data_vals(dev, fake_shift, 3);
break;
default:
keyboard_at_log("N/A (scan code set %i)\n", keyboard_mode & 0x02);
break;
}
}
} else {
if (shift_states & STATE_LSHIFT) {
/* Num lock off and left shift pressed. */
switch (keyboard_mode & 0x02) {
case 1:
keyboard_at_log("E0 2A\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0x2a;
add_data_vals(dev, fake_shift, 2);
break;
case 2:
keyboard_at_log("E0 12\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0x12;
add_data_vals(dev, fake_shift, 2);
break;
default:
keyboard_at_log("N/A (scan code set %i)\n", keyboard_mode & 0x02);
break;
}
}
if (shift_states & STATE_RSHIFT) {
/* Num lock off and right shift pressed. */
switch (keyboard_mode & 0x02) {
case 1:
keyboard_at_log("E0 36\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0x36;
add_data_vals(dev, fake_shift, 2);
break;
case 2:
keyboard_at_log("E0 59\n");
fake_shift[0] = 0xe0;
fake_shift[1] = 0x59;
add_data_vals(dev, fake_shift, 2);
break;
default:
keyboard_at_log("N/A (scan code set %i)\n", keyboard_mode & 0x02);
break;
}
}
keyboard_at_log(shift_states ? "" : "N/A (both shifts off)\n");
}
break;
default:
kbc_at_dev_queue_add(dev, val, 1);
break;
}
dev->ignore = 0;
}
void
keyboard_at_clear_data(void *priv)
{
atkbc_dev_t *dev = (atkbc_dev_t *) priv;
dev->flags &= ~FLAG_CTRLDAT;
}
static void
keyboard_at_set_defaults(atkbc_dev_t *dev)
{
dev->rate = 1;
keyboard_set3_all_break = 0;
keyboard_set3_all_repeat = 0;
memset(keyboard_set3_flags, 0, 512);
keyboard_mode = 0x02;
keyboard_at_set_scancode_set();
}
static void
keyboard_at_bat(void *priv)
{
atkbc_dev_t *dev = (atkbc_dev_t *) priv;
if (bat_counter == 0x0000) {
keyboard_at_set_defaults(dev);
keyboard_scan = 1;
kbc_at_dev_queue_add(dev, 0xaa, 0);
} else {
bat_counter--;
dev->state = DEV_STATE_EXECUTE_BAT;
}
}
static void
keyboard_at_invalid_cmd(atkbc_dev_t *dev)
{
keyboard_at_log("%s: Invalid command [%02X]\n", dev->name, dev->port->dat);
kbc_at_dev_queue_add(dev, inv_cmd_response, 0);
}
static void
keyboard_at_write(void *priv)
{
atkbc_dev_t *dev = (atkbc_dev_t *) priv;
uint8_t val;
if (dev->port == NULL)
return;
val = dev->port->dat;
dev->state = DEV_STATE_MAIN_OUT;
if ((val < 0xed) && (dev->flags & FLAG_CTRLDAT)) {
dev->flags &= ~FLAG_CTRLDAT;
switch (dev->command) {
case 0xed: /* Set/reset LEDs */
kbc_at_dev_queue_add(dev, 0xfa, 0);
keyboard_at_log("%s: Set/reset LEDs [%02X]\n", dev->name, val);
break;
case 0xf0: /* Get/set scancode set */
kbc_at_dev_queue_add(dev, (val > 3) ? 0xfe : 0xfa, 0);
switch (val) {
case 0x00:
keyboard_at_log("%s: Get scan code set [%02X]\n", dev->name, keyboard_mode);
kbc_at_dev_queue_add(dev, keyboard_mode, 0);
break;
case 0x01 ... 0x03:
keyboard_mode = val;
keyboard_at_log("%s: Set scan code set [%02X]\n", dev->name, keyboard_mode);
keyboard_at_set_scancode_set();
break;
default:
/* Fatal so any instance of anything attempting to set scan code > 3 can be reported to us. */
fatal("%s: Scan code set [%02X] invalid, resend\n", dev->name, val);
dev->flags |= FLAG_CTRLDAT;
dev->state = DEV_STATE_MAIN_WANT_IN;
break;
}
break;
case 0xf3: /* set typematic rate/delay */
if (val & 0x80) {
keyboard_at_log("%s: Set typematic rate/delay [%02X] has bit 7 set - invalid\n", dev->name, val);
dev->flags |= FLAG_CTRLDAT; /* Resend = keep waiting for parameter. */
kbc_at_dev_queue_add(dev, 0xfe, 0); /* Command response */
dev->state = DEV_STATE_MAIN_WANT_IN;
} else {
dev->rate = val;
kbc_at_dev_queue_add(dev, 0xfa, 0); /* Command response */
keyboard_at_log("%s: Set typematic rate/delay [%02X]\n", dev->name, val);
}
break;
default:
fatal("%s: Parameter [%02X] for invalid command [%02X] - possibly memory corruption!\n", dev->name, val, dev->command);
kbc_at_dev_queue_add(dev, 0xfe, 0);
}
} else {
if (dev->flags & FLAG_CTRLDAT) {
/* Special case - another command during another command that wants input - proceed
as normal but do not cancel the command (so keep waiting for input), unless the
command in progress is ED (Set/reset LEDs). */
if (val == 0xed) {
keyboard_scan = 1;
dev->flags &= ~FLAG_CTRLDAT;
} else
dev->state = DEV_STATE_MAIN_WANT_IN;
}
switch (val) {
case 0xed: /* set/reset LEDs */
dev->command = val;
keyboard_at_log("%s: set/reset LEDs\n", dev->name);
dev->flags |= FLAG_CTRLDAT;
kbc_at_dev_queue_add(dev, 0xfa, 0); /* ACK for command byte */
dev->state = DEV_STATE_MAIN_WANT_IN;
break;
case 0xee: /* diagnostic echo */
keyboard_at_log("%s: ECHO\n", dev->name);
kbc_at_dev_queue_add(dev, 0xee, 0);
break;
case 0xef: /* Invalid command */
case 0xf1: /* Invalid command */
keyboard_at_log("%s: Invalid command [%02X]\n", dev->name, dev->port->dat);
kbc_at_dev_queue_add(dev, inv_cmd_response, 0);
break;
case 0xf0: /* get/set scan code set */
if (dev->type & FLAG_PS2) {
dev->command = val;
keyboard_at_log("%s: scan code set\n", dev->name);
dev->flags |= FLAG_CTRLDAT;
kbc_at_dev_queue_add(dev, 0xfa, 0); /* ACK for command byte */
dev->state = DEV_STATE_MAIN_WANT_IN;
} else
keyboard_at_invalid_cmd(dev);
break;
case 0xf2: /* read ID */
keyboard_at_log("%s: read keyboard id\n", dev->name);
/* TODO: After keyboard type selection is implemented, make this
return the correct keyboard ID for the selected type. */
kbc_at_dev_queue_add(dev, 0xfa, 0);
for (uint8_t i = 0; i < 4; i++) {
if (id_bytes[dev->type][i] == 0)
break;
kbc_at_dev_queue_add(dev, id_bytes[dev->type][i], 0);
}
break;
case 0xf3: /* set command mode */
dev->command = val;
keyboard_at_log("%s: set typematic rate/delay\n", dev->name);
dev->flags |= FLAG_CTRLDAT;
kbc_at_dev_queue_add(dev, 0xfa, 0); /* ACK for command byte */
dev->state = DEV_STATE_MAIN_WANT_IN;
break;
case 0xf4: /* enable */
keyboard_at_log("%s: enable keyboard\n", dev->name);
keyboard_scan = 1;
kbc_at_dev_queue_add(dev, 0xfa, 0);
break;
case 0xf5: /* set defaults and disable keyboard */
case 0xf6: /* set defaults */
keyboard_at_log("%s: set defaults%s\n",
dev->name, (val == 0xf6) ? "" : " and disable keyboard");
keyboard_scan = !(val & 0x01);
keyboard_at_log("%s: val = %02X, keyboard_scan = %i\n",
dev->name, val, keyboard_scan);
kbc_at_dev_queue_add(dev, 0xfa, 0);
keyboard_set3_all_break = 0;
keyboard_set3_all_repeat = 0;
memset(keyboard_set3_flags, 0, 512);
keyboard_mode = 0x02;
keyboard_at_set_scancode_set();
break;
case 0xf7: /* set all keys to repeat */
if (dev->type & FLAG_PS2) {
keyboard_at_log("%s: set all keys to repeat\n", dev->name);
kbc_at_dev_queue_add(dev, 0xfa, 0);
keyboard_set3_all_break = 1;
} else
keyboard_at_invalid_cmd(dev);
break;
case 0xf8: /* set all keys to give make/break codes */
if (dev->type & FLAG_PS2) {
keyboard_at_log("%s: set all keys to give make/break codes\n", dev->name);
kbc_at_dev_queue_add(dev, 0xfa, 0);
keyboard_set3_all_break = 1;
} else
keyboard_at_invalid_cmd(dev);
break;
case 0xf9: /* set all keys to give make codes only */
if (dev->type & FLAG_PS2) {
keyboard_at_log("%s: set all keys to give make codes only\n", dev->name);
kbc_at_dev_queue_add(dev, 0xfa, 0);
keyboard_set3_all_break = 0;
} else
keyboard_at_invalid_cmd(dev);
break;
case 0xfa: /* set all keys to repeat and give make/break codes */
if (dev->type & FLAG_PS2) {
keyboard_at_log("%s: set all keys to repeat and give make/break codes\n", dev->name);
kbc_at_dev_queue_add(dev, 0xfa, 0);
keyboard_set3_all_repeat = 1;
keyboard_set3_all_break = 1;
} else
keyboard_at_invalid_cmd(dev);
break;
/* TODO: Actually implement these commands. */
case 0xfb: /* set some keys to repeat */
keyboard_at_log("%s: set some keys to repeat\n", dev->name);
kbc_at_dev_queue_add(dev, inv_cmd_response, 0);
break;
case 0xfc: /* set some keys to give make/break codes */
keyboard_at_log("%s: set some keys to give make/break codes\n", dev->name);
kbc_at_dev_queue_add(dev, inv_cmd_response, 0);
break;
case 0xfd: /* set some keys to give make codes only */
keyboard_at_log("%s: set some keys to give make codes only\n", dev->name);
kbc_at_dev_queue_add(dev, inv_cmd_response, 0);
break;
/* TODO: This is supposed to resend multiple bytes after some commands. */
case 0xfe: /* resend last scan code */
keyboard_at_log("%s: resend last scan code\n", dev->name);
kbc_at_dev_queue_add(dev, 0xfa, 0);
kbc_at_dev_queue_add(dev, dev->last_scan_code, 0);
break;
case 0xff: /* reset */
kbc_at_dev_reset(dev, 1);
bat_counter = 1000;
break;
default:
kbc_at_dev_queue_add(dev, 0xfe, 0);
}
}
}
/*
* Initialize the device for use by the user.
*
* We also get called from the various machines.
*/
void *
keyboard_at_init(const device_t *info)
{
atkbc_dev_t *dev = kbc_at_dev_init(DEV_KBD);
dev->name = info->name;
/* Key 14 = Japanese key next to backspace, scan code: 13 (Yen 7D);
Key 29 = US backslash, scan code: 5C (Backslash 2B);
Key 42 = European backslash, scan code: 53 (Backslash 2B);
Key 45 = European key next to left shift, scan code: 13 (Key 56);
Key 56 = Japanese key next to right shift, scan code: 5C (Backslash 73);
Key 59 = Japanese key between left Ctrl and left Alt, scan code: 85 (Muhenkan 7B);
Key 63 = Japanese key between right Ctrl and right Alt, scan code: 86 (Henkan/Zenkouho 79);
Key 65? = Japanese key between right Ctrl and right Alt, scan code: 87 (Hiragana/Katakana 70).
*/
dev->type = FLAG_PS2 | KBD_102_KEY /* device_get_config_int("type") */;
keyboard_at_log("%s: type=%d\n", dev->name, dev->type);
dev->process_cmd = keyboard_at_write;
dev->execute_bat = keyboard_at_bat;
dev->scan = &keyboard_scan;
dev->fifo_mask = FIFO_SIZE - 1;
if (dev->port != NULL) {
kbc_at_dev_reset(dev, 0);
bat_counter = 0x0000;
}
keyboard_send = add_data_kbd;
SavedKbd = dev;
inv_cmd_response = (dev->type & FLAG_PS2) ? 0xfe : 0xfa;
/* Return our private data to the I/O layer. */
return dev;
}
static void
keyboard_at_close(void *priv)
{
atkbc_dev_t *dev = (atkbc_dev_t *) priv;
keyboard_scan = 0;
keyboard_send = NULL;
/* Disable the scancode maps. */
keyboard_set_table(NULL);
SavedKbd = NULL;
free(dev);
}
static const device_config_t keyboard_at_config[] = {
// clang-format off
{
.name = "type",
.description = "Type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 1,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "AT 84-key", .value = FLAG_AT | KBD_84_KEY },
{ .description = "AT 101/102/106-key", .value = FLAG_AT | KBD_101_KEY },
{ .description = "AT Korean", .value = FLAG_AT | KBD_KOREAN },
{ .description = "PS/2 101-key", .value = FLAG_PS2 | KBD_101_KEY },
{ .description = "PS/2 102-key", .value = FLAG_PS2 | KBD_102_KEY },
{ .description = "PS/2 106-key JIS", .value = FLAG_PS2 | KBD_JIS },
{ .description = "PS/2 Korean", .value = FLAG_PS2 | KBD_KOREAN },
{ .description = "" }
}
},
{
.name = "", .description = "", .type = CONFIG_END
}
// clang-format on
};
/* TODO: Add more keyboard types. */
const device_t keyboard_at_generic_device = {
.name = "Standard AT or PS/2 Keyboard",
.internal_name = "ps2",
.flags = DEVICE_PS2,
.local = 0,
.init = keyboard_at_init,
.close = keyboard_at_close,
.reset = NULL,
{ .poll = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = keyboard_at_config
};
``` | /content/code_sandbox/src/device/keyboard_at.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 60,518 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the NatSemi PC87310 Super I/O chip.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* EngiNerd, <webmaster.crrc@yahoo.it>
* Tiseno100,
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#define FLAG_IDE 0x00000001
#define FLAG_ALI 0x00000002
#ifdef ENABLE_PC87310_LOG
int pc87310_do_log = ENABLE_PC87310_LOG;
static void
pc87310_log(const char *fmt, ...)
{
va_list ap;
if (pc87310_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define pc87310_log(fmt, ...)
#endif
typedef struct pc87310_t {
uint8_t tries;
uint8_t flags;
uint8_t regs[2];
fdc_t *fdc;
serial_t *uart[2];
} pc87310_t;
static void
lpt1_handler(pc87310_t *dev)
{
int temp;
uint16_t lpt_port = LPT1_ADDR;
uint8_t lpt_irq = LPT1_IRQ;
/* bits 0-1:
* 00 378h
* 01 3bch
* 10 278h
* 11 disabled
*/
temp = dev->regs[1] & 0x03;
lpt1_remove();
switch (temp) {
case 0:
lpt_port = LPT1_ADDR;
break;
case 1:
lpt_port = LPT_MDA_ADDR;
break;
case 2:
lpt_port = LPT2_ADDR;
break;
case 3:
lpt_port = 0x000;
lpt_irq = 0xff;
break;
default:
break;
}
if (lpt_port)
lpt1_init(lpt_port);
lpt1_irq(lpt_irq);
}
static void
serial_handler(pc87310_t *dev)
{
uint8_t temp, temp2 = 0x00;
uint16_t base1 = 0x0000, base2 = 0x0000;
uint8_t irq1, irq2;
/* - Bit 2: Disable serial port 1;
* - Bit 3: Disable serial port 2;
* - Bit 4: Swap serial ports.
*/
temp = (dev->regs[1] >> 2) & 0x07;
/* - Bits 1, 0: 0, 0 = Normal (3F8 and 2F8);
* 0, 1 = 2E8 instead of 2F8;
* 1, 0 = 3E8 instead of 3F8 and 2E8 instead of 2F8;
* 1, 1 = 3E8 instead of 3F8.
*
* If we XOR bit 0 with bit 1, we get this:
* 0, 0 = Normal (3F8 and 2F8);
* 0, 1 = 2E8 instead of 2F8;
* 1, 0 = 3E8 instead of 3F8;
* 1, 1 = 3E8 instead of 3F8 and 2E8 instead of 2F8.
*
* Then they become simple toggle bits.
* Therefore, we do this for easier operation.
*/
if (dev->flags & FLAG_ALI) {
temp2 = dev->regs[0] & 0x03;
temp2 ^= ((temp2 & 0x02) >> 1);
}
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
if (!(temp & 0x01)) {
base1 = (temp & 0x04) ? COM2_ADDR : COM1_ADDR;
if ((base1 == COM1_ADDR) && (temp2 & 0x02))
base1 = 0x03e8;
else if ((base1 == COM2_ADDR) && (temp2 & 0x01))
base1 = 0x02e8;
irq1 = (temp & 0x04) ? COM2_IRQ : COM1_IRQ;
serial_setup(dev->uart[0], base1, irq1);
pc87310_log("UART 1 at %04X, IRQ %i\n", base1, irq1);
}
if (!(temp & 0x02)) {
base2 = (temp & 0x04) ? COM1_ADDR : COM2_ADDR;
if ((base2 == COM1_ADDR) && (temp2 & 0x02))
base2 = 0x03e8;
else if ((base2 == COM2_ADDR) && (temp2 & 0x01))
base2 = 0x02e8;
irq2 = (temp & 0x04) ? COM1_IRQ : COM2_IRQ;
serial_setup(dev->uart[1], base2, irq2);
pc87310_log("UART 2 at %04X, IRQ %i\n", base2, irq2);
}
}
static void
pc87310_write(UNUSED(uint16_t port), uint8_t val, void *priv)
{
pc87310_t *dev = (pc87310_t *) priv;
uint8_t valxor;
uint8_t idx = (uint8_t) ((port & 0x0002) >> 1);
pc87310_log("[%04X:%08X] [W] %02X = %02X (%i)\n", CS, cpu_state.pc, port, val, dev->tries);
if (dev->tries) {
/* Second write to config register. */
valxor = val ^ dev->regs[idx];
dev->tries = 0;
dev->regs[idx] = val;
if (idx) {
/* Register, common to both PC87310 and ALi M5105. */
pc87310_log("SIO: Common register written %02X\n", val);
/* Reconfigure parallel port. */
if (valxor & 0x03)
/* Bits 1, 0: 1, 1 = Disable parallel port. */
lpt1_handler(dev);
/* Reconfigure serial ports. */
if (valxor & 0x1c)
serial_handler(dev);
/* Reconfigure IDE controller. */
if ((dev->flags & FLAG_IDE) && (valxor & 0x20)) {
pc87310_log("SIO: HDC disabled\n");
ide_pri_disable();
/* Bit 5: 1 = Disable IDE controller. */
if (!(val & 0x20)) {
pc87310_log("SIO: HDC enabled\n");
ide_set_base(0, 0x1f0);
ide_set_side(0, 0x3f6);
ide_pri_enable();
}
}
/* Reconfigure floppy disk controller. */
if (valxor & 0x40) {
pc87310_log("SIO: FDC disabled\n");
fdc_remove(dev->fdc);
/* Bit 6: 1 = Disable FDC. */
if (!(val & 0x40)) {
pc87310_log("SIO: FDC enabled\n");
fdc_set_base(dev->fdc, FDC_PRIMARY_ADDR);
}
}
} else {
/* ALi M5105 extension register. */
pc87310_log("SIO: M5105 extension register written %02X\n", val);
/* Reconfigure serial ports. */
if (valxor & 0x03)
serial_handler(dev);
}
} else
/* First write to config register. */
dev->tries++;
}
uint8_t
pc87310_read(UNUSED(uint16_t port), void *priv)
{
pc87310_t *dev = (pc87310_t *) priv;
uint8_t ret = 0xff;
uint8_t idx = (uint8_t) ((port & 0x0002) >> 1);
dev->tries = 0;
ret = dev->regs[idx];
pc87310_log("[%04X:%08X] [R] %02X = %02X\n", CS, cpu_state.pc, port, ret);
return ret;
}
void
pc87310_reset(pc87310_t *dev)
{
dev->regs[0] = 0x00;
dev->regs[1] = 0x00;
dev->tries = 0;
lpt1_handler(dev);
serial_handler(dev);
if (dev->flags & FLAG_IDE) {
ide_pri_disable();
ide_pri_enable();
}
fdc_reset(dev->fdc);
}
static void
pc87310_close(void *priv)
{
pc87310_t *dev = (pc87310_t *) priv;
free(dev);
}
static void *
pc87310_init(const device_t *info)
{
pc87310_t *dev = (pc87310_t *) calloc(1, sizeof(pc87310_t));
/* Avoid conflicting with machines that make no use of the PC87310 Internal IDE */
dev->flags = info->local;
dev->fdc = device_add(&fdc_at_nsc_device);
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
if (dev->flags & FLAG_IDE)
device_add((dev->flags & FLAG_ALI) ? &ide_vlb_device : &ide_isa_device);
pc87310_reset(dev);
io_sethandler(0x3f3, 0x0001,
pc87310_read, NULL, NULL, pc87310_write, NULL, NULL, dev);
if (dev->flags & FLAG_ALI)
io_sethandler(0x3f1, 0x0001,
pc87310_read, NULL, NULL, pc87310_write, NULL, NULL, dev);
return dev;
}
const device_t pc87310_device = {
.name = "National Semiconductor PC87310 Super I/O",
.internal_name = "pc87310",
.flags = 0,
.local = 0,
.init = pc87310_init,
.close = pc87310_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t pc87310_ide_device = {
.name = "National Semiconductor PC87310 Super I/O with IDE functionality",
.internal_name = "pc87310_ide",
.flags = 0,
.local = FLAG_IDE,
.init = pc87310_init,
.close = pc87310_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ali5105_device = {
.name = "ALi M5105 Super I/O",
.internal_name = "ali5105",
.flags = 0,
.local = FLAG_ALI,
.init = pc87310_init,
.close = pc87310_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_pc87310.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,846 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Intel 82091AA Super I/O chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct i82091aa_t {
uint8_t cur_reg;
uint8_t has_ide;
uint8_t regs[81];
uint16_t base_address;
fdc_t *fdc;
serial_t *uart[2];
} i82091aa_t;
static void
fdc_handler(i82091aa_t *dev)
{
fdc_remove(dev->fdc);
if (dev->regs[0x10] & 0x01)
fdc_set_base(dev->fdc, (dev->regs[0x10] & 0x02) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
}
static void
lpt1_handler(i82091aa_t *dev)
{
uint16_t lpt_port = LPT1_ADDR;
lpt1_remove();
switch ((dev->regs[0x20] >> 1) & 0x03) {
case 0x00:
lpt_port = LPT1_ADDR;
break;
case 1:
lpt_port = LPT2_ADDR;
break;
case 2:
lpt_port = LPT_MDA_ADDR;
break;
case 3:
lpt_port = 0x000;
break;
default:
break;
}
if ((dev->regs[0x20] & 0x01) && lpt_port)
lpt1_init(lpt_port);
lpt1_irq((dev->regs[0x20] & 0x08) ? LPT1_IRQ : LPT2_IRQ);
}
static void
serial_handler(i82091aa_t *dev, int uart)
{
int reg = (0x30 + (uart << 4));
uint16_t uart_port = COM1_ADDR;
serial_remove(dev->uart[uart]);
switch ((dev->regs[reg] >> 1) & 0x07) {
case 0x00:
uart_port = COM1_ADDR;
break;
case 0x01:
uart_port = COM2_ADDR;
break;
case 0x02:
uart_port = 0x220;
break;
case 0x03:
uart_port = 0x228;
break;
case 0x04:
uart_port = 0x238;
break;
case 0x05:
uart_port = COM4_ADDR;
break;
case 0x06:
uart_port = 0x338;
break;
case 0x07:
uart_port = COM3_ADDR;
break;
default:
break;
}
if (dev->regs[reg] & 0x01)
serial_setup(dev->uart[uart], uart_port, (dev->regs[reg] & 0x10) ? COM1_IRQ : COM2_IRQ);
}
static void
ide_handler(i82091aa_t *dev)
{
int board = dev->has_ide - 1;
ide_remove_handlers(board);
ide_set_base(board, (dev->regs[0x50] & 0x02) ? 0x170 : 0x1f0);
ide_set_side(board, (dev->regs[0x50] & 0x02) ? 0x376 : 0x3f6);
if (dev->regs[0x50] & 0x01)
ide_set_handlers(board);
}
static void
i82091aa_write(uint16_t port, uint8_t val, void *priv)
{
i82091aa_t *dev = (i82091aa_t *) priv;
uint8_t index;
uint8_t valxor = 0;
uint8_t uart = (dev->cur_reg >> 4) - 0x03;
uint8_t *reg = &(dev->regs[dev->cur_reg]);
index = (port & 1) ? 0 : 1;
if (index) {
dev->cur_reg = val;
return;
} else if (dev->cur_reg < 0x51)
valxor = val ^ *reg;
else if (dev->cur_reg >= 0x51)
return;
switch (dev->cur_reg) {
case 0x02:
*reg = (*reg & 0x78) | (val & 0x01);
break;
case 0x03:
*reg = (val & 0xf8);
break;
case 0x10:
*reg = (val & 0x83);
if (valxor & 0x03)
fdc_handler(dev);
break;
case 0x11:
*reg = (val & 0x0f);
if ((valxor & 0x04) && (val & 0x04))
fdc_reset(dev->fdc);
break;
case 0x20:
*reg = (val & 0xef);
if (valxor & 0x07)
lpt1_handler(dev);
break;
case 0x21:
*reg = (val & 0x2f);
break;
case 0x30:
case 0x40:
*reg = (val & 0x9f);
if (valxor & 0x1f)
serial_handler(dev, uart);
if (valxor & 0x80)
serial_set_clock_src(dev->uart[uart], (val & 0x80) ? 2000000.0 : (24000000.0 / 13.0));
break;
case 0x31:
case 0x41:
*reg = (val & 0x1f);
if ((valxor & 0x04) && (val & 0x04))
serial_reset_port(dev->uart[uart]);
break;
case 0x50:
*reg = (val & 0x07);
if (dev->has_ide && (valxor & 0x03))
ide_handler(dev);
break;
default:
break;
}
}
uint8_t
i82091aa_read(uint16_t port, void *priv)
{
const i82091aa_t *dev = (i82091aa_t *) priv;
uint8_t ret = 0xff;
uint8_t index;
index = (port & 1) ? 0 : 1;
if (index)
ret = dev->cur_reg;
else if (dev->cur_reg < 0x51)
ret = dev->regs[dev->cur_reg];
return ret;
}
void
i82091aa_reset(i82091aa_t *dev)
{
memset(dev->regs, 0x00, 81);
dev->regs[0x00] = 0xa0;
dev->regs[0x10] = 0x01;
dev->regs[0x31] = dev->regs[0x41] = 0x02;
dev->regs[0x50] = 0x01;
fdc_reset(dev->fdc);
fdc_handler(dev);
lpt1_handler(dev);
serial_handler(dev, 0);
serial_handler(dev, 1);
serial_set_clock_src(dev->uart[0], (24000000.0 / 13.0));
serial_set_clock_src(dev->uart[1], (24000000.0 / 13.0));
if (dev->has_ide)
ide_handler(dev);
}
static void
i82091aa_close(void *priv)
{
i82091aa_t *dev = (i82091aa_t *) priv;
free(dev);
}
static void *
i82091aa_init(const device_t *info)
{
i82091aa_t *dev = (i82091aa_t *) malloc(sizeof(i82091aa_t));
memset(dev, 0, sizeof(i82091aa_t));
dev->fdc = device_add(&fdc_at_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->has_ide = (info->local >> 9) & 0x03;
i82091aa_reset(dev);
dev->regs[0x02] = info->local & 0xff;
if (info->local & 0x08)
dev->base_address = (info->local & 0x100) ? 0x0398 : 0x0024;
else
dev->base_address = (info->local & 0x100) ? 0x026e : 0x0022;
io_sethandler(dev->base_address, 0x0002,
i82091aa_read, NULL, NULL, i82091aa_write, NULL, NULL, dev);
return dev;
}
const device_t i82091aa_device = {
.name = "Intel 82091AA Super I/O",
.internal_name = "i82091aa",
.flags = 0,
.local = 0x40,
.init = i82091aa_init,
.close = i82091aa_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i82091aa_398_device = {
.name = "Intel 82091AA Super I/O (Port 398h)",
.internal_name = "i82091aa_398",
.flags = 0,
.local = 0x148,
.init = i82091aa_init,
.close = i82091aa_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i82091aa_ide_pri_device = {
.name = "Intel 82091AA Super I/O (With Primary IDE)",
.internal_name = "i82091aa_ide",
.flags = 0,
.local = 0x240,
.init = i82091aa_init,
.close = i82091aa_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i82091aa_ide_device = {
.name = "Intel 82091AA Super I/O (With IDE)",
.internal_name = "i82091aa_ide",
.flags = 0,
.local = 0x440,
.init = i82091aa_init,
.close = i82091aa_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_82091aa.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,703 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Super I/O chip detection code.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
typedef struct sio_detect_t {
uint8_t regs[2];
} sio_detect_t;
static void
sio_detect_write(uint16_t port, uint8_t val, void *priv)
{
sio_detect_t *dev = (sio_detect_t *) priv;
pclog("sio_detect_write : port=%04x = %02X\n", port, val);
dev->regs[port & 1] = val;
return;
}
static uint8_t
sio_detect_read(uint16_t port, void *priv)
{
const sio_detect_t *dev = (sio_detect_t *) priv;
pclog("sio_detect_read : port=%04x = %02X\n", port, dev->regs[port & 1]);
return 0xff /*dev->regs[port & 1]*/;
}
static void
sio_detect_close(void *priv)
{
sio_detect_t *dev = (sio_detect_t *) priv;
free(dev);
}
static void *
sio_detect_init(UNUSED(const device_t *info))
{
sio_detect_t *dev = (sio_detect_t *) malloc(sizeof(sio_detect_t));
memset(dev, 0, sizeof(sio_detect_t));
device_add(&fdc_at_smc_device);
io_sethandler(0x0022, 0x0006,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(0x002e, 0x0002,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(0x0044, 0x0004,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(0x004e, 0x0002,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(0x0108, 0x0002,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(0x015c, 0x0002,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(0x0250, 0x0003,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(0x026e, 0x0002,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(0x0279, 0x0001,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(FDC_SECONDARY_ADDR, 0x0002,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(0x0398, 0x0002,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(0x03e3, 0x0001,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(FDC_PRIMARY_ADDR, 0x0002,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
io_sethandler(0x0a79, 0x0001,
sio_detect_read, NULL, NULL, sio_detect_write, NULL, NULL, dev);
return dev;
}
const device_t sio_detect_device = {
.name = "Super I/O Detection Helper",
.internal_name = "sio_detect",
.flags = 0,
.local = 0,
.init = sio_detect_init,
.close = sio_detect_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_detect.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,105 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C663 and FDC37C665 Super
* I/O Chips.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct fdc37c6xx_t {
uint8_t max_reg;
uint8_t chip_id;
uint8_t tries;
uint8_t has_ide;
uint8_t regs[16];
int cur_reg;
int com3_addr;
int com4_addr;
fdc_t *fdc;
serial_t *uart[2];
} fdc37c6xx_t;
static void
set_com34_addr(fdc37c6xx_t *dev)
{
switch (dev->regs[1] & 0x60) {
case 0x00:
dev->com3_addr = 0x338;
dev->com4_addr = 0x238;
break;
case 0x20:
dev->com3_addr = COM3_ADDR;
dev->com4_addr = COM4_ADDR;
break;
case 0x40:
dev->com3_addr = COM3_ADDR;
dev->com4_addr = 0x2e0;
break;
case 0x60:
dev->com3_addr = 0x220;
dev->com4_addr = 0x228;
break;
default:
break;
}
}
static void
set_serial_addr(fdc37c6xx_t *dev, int port)
{
uint8_t shift = (port << 2);
double clock_src = 24000000.0 / 13.0;
if (dev->regs[4] & (1 << (4 + port)))
clock_src = 24000000.0 / 12.0;
serial_remove(dev->uart[port]);
if (dev->regs[2] & (4 << shift)) {
switch ((dev->regs[2] >> shift) & 3) {
case 0:
serial_setup(dev->uart[port], COM1_ADDR, COM1_IRQ);
break;
case 1:
serial_setup(dev->uart[port], COM2_ADDR, COM2_IRQ);
break;
case 2:
serial_setup(dev->uart[port], dev->com3_addr, COM3_IRQ);
break;
case 3:
serial_setup(dev->uart[port], dev->com4_addr, COM4_IRQ);
break;
default:
break;
}
}
serial_set_clock_src(dev->uart[port], clock_src);
}
static void
lpt1_handler(fdc37c6xx_t *dev)
{
lpt1_remove();
switch (dev->regs[1] & 3) {
case 1:
lpt1_init(LPT_MDA_ADDR);
lpt1_irq(7);
break;
case 2:
lpt1_init(LPT1_ADDR);
lpt1_irq(7 /*5*/);
break;
case 3:
lpt1_init(LPT2_ADDR);
lpt1_irq(7 /*5*/);
break;
default:
break;
}
}
static void
fdc_handler(fdc37c6xx_t *dev)
{
fdc_remove(dev->fdc);
if (dev->regs[0] & 0x10)
fdc_set_base(dev->fdc, (dev->regs[5] & 0x01) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
}
static void
ide_handler(fdc37c6xx_t *dev)
{
/* TODO: Make an ide_disable(channel) and ide_enable(channel) so we can simplify this. */
if (dev->has_ide == 2) {
ide_sec_disable();
ide_set_base(1, (dev->regs[0x05] & 0x02) ? 0x170 : 0x1f0);
ide_set_side(1, (dev->regs[0x05] & 0x02) ? 0x376 : 0x3f6);
if (dev->regs[0x00] & 0x01)
ide_sec_enable();
} else if (dev->has_ide == 1) {
ide_pri_disable();
ide_set_base(0, (dev->regs[0x05] & 0x02) ? 0x170 : 0x1f0);
ide_set_side(0, (dev->regs[0x05] & 0x02) ? 0x376 : 0x3f6);
if (dev->regs[0x00] & 0x01)
ide_pri_enable();
}
}
static void
fdc37c6xx_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c6xx_t *dev = (fdc37c6xx_t *) priv;
uint8_t valxor = 0;
if (dev->tries == 2) {
if (port == FDC_PRIMARY_ADDR) {
if (val == 0xaa)
dev->tries = 0;
else
dev->cur_reg = val;
} else {
if (dev->cur_reg > dev->max_reg)
return;
valxor = val ^ dev->regs[dev->cur_reg];
dev->regs[dev->cur_reg] = val;
switch (dev->cur_reg) {
case 0:
if (dev->has_ide && (valxor & 0x01))
ide_handler(dev);
if (valxor & 0x10)
fdc_handler(dev);
break;
case 1:
if (valxor & 3)
lpt1_handler(dev);
if (valxor & 0x60) {
set_com34_addr(dev);
set_serial_addr(dev, 0);
set_serial_addr(dev, 1);
}
break;
case 2:
if (valxor & 7)
set_serial_addr(dev, 0);
if (valxor & 0x70)
set_serial_addr(dev, 1);
break;
case 3:
if (valxor & 2)
fdc_update_enh_mode(dev->fdc, (dev->regs[3] & 2) ? 1 : 0);
break;
case 4:
if (valxor & 0x10)
set_serial_addr(dev, 0);
if (valxor & 0x20)
set_serial_addr(dev, 1);
break;
case 5:
if (valxor & 0x01)
fdc_handler(dev);
if (dev->has_ide && (valxor & 0x02))
ide_handler(dev);
if (valxor & 0x18)
fdc_update_densel_force(dev->fdc, (dev->regs[5] & 0x18) >> 3);
if (valxor & 0x20)
fdc_set_swap(dev->fdc, (dev->regs[5] & 0x20) >> 5);
break;
default:
break;
}
}
} else if ((port == FDC_PRIMARY_ADDR) && (val == 0x55))
dev->tries++;
}
static uint8_t
fdc37c6xx_read(uint16_t port, void *priv)
{
const fdc37c6xx_t *dev = (fdc37c6xx_t *) priv;
uint8_t ret = 0xff;
if (dev->tries == 2) {
if (port == 0x3f1)
ret = dev->regs[dev->cur_reg];
}
return ret;
}
static void
fdc37c6xx_reset(fdc37c6xx_t *dev)
{
dev->com3_addr = 0x338;
dev->com4_addr = 0x238;
serial_remove(dev->uart[0]);
serial_setup(dev->uart[0], COM1_ADDR, COM1_IRQ);
serial_remove(dev->uart[1]);
serial_setup(dev->uart[1], COM2_ADDR, COM2_IRQ);
lpt1_remove();
lpt1_init(LPT1_ADDR);
fdc_reset(dev->fdc);
fdc_remove(dev->fdc);
dev->tries = 0;
memset(dev->regs, 0, 16);
switch (dev->chip_id) {
case 0x63:
case 0x65:
dev->max_reg = 0x0f;
dev->regs[0x0] = 0x3b;
break;
case 0x64:
case 0x66:
dev->max_reg = 0x0f;
dev->regs[0x0] = 0x2b;
break;
default:
dev->max_reg = (dev->chip_id >= 0x61) ? 0x03 : 0x02;
dev->regs[0x0] = 0x3f;
break;
}
dev->regs[0x1] = 0x9f;
dev->regs[0x2] = 0xdc;
dev->regs[0x3] = 0x78;
if (dev->chip_id >= 0x63) {
dev->regs[0x6] = 0xff;
dev->regs[0xd] = dev->chip_id;
if (dev->chip_id >= 0x65)
dev->regs[0xe] = 0x02;
else
dev->regs[0xe] = 0x01;
}
set_serial_addr(dev, 0);
set_serial_addr(dev, 1);
lpt1_handler(dev);
fdc_handler(dev);
if (dev->has_ide)
ide_handler(dev);
}
static void
fdc37c6xx_close(void *priv)
{
fdc37c6xx_t *dev = (fdc37c6xx_t *) priv;
free(dev);
}
static void *
fdc37c6xx_init(const device_t *info)
{
fdc37c6xx_t *dev = (fdc37c6xx_t *) malloc(sizeof(fdc37c6xx_t));
memset(dev, 0, sizeof(fdc37c6xx_t));
dev->fdc = device_add(&fdc_at_smc_device);
dev->chip_id = info->local & 0xff;
dev->has_ide = (info->local >> 8) & 0xff;
if (dev->chip_id >= 0x63) {
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
} else {
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
}
io_sethandler(FDC_PRIMARY_ADDR, 0x0002,
fdc37c6xx_read, NULL, NULL, fdc37c6xx_write, NULL, NULL, dev);
fdc37c6xx_reset(dev);
return dev;
}
/* The three appear to differ only in the chip ID, if I
understood their datasheets correctly. */
const device_t fdc37c651_device = {
.name = "SMC FDC37C651 Super I/O",
.internal_name = "fdc37c651",
.flags = 0,
.local = 0x51,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c651_ide_device = {
.name = "SMC FDC37C651 Super I/O (With IDE)",
.internal_name = "fdc37c651_ide",
.flags = 0,
.local = 0x151,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c661_device = {
.name = "SMC FDC37C661 Super I/O",
.internal_name = "fdc37c661",
.flags = 0,
.local = 0x61,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c661_ide_device = {
.name = "SMC FDC37C661 Super I/O (With IDE)",
.internal_name = "fdc37c661_ide",
.flags = 0,
.local = 0x161,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c661_ide_sec_device = {
.name = "SMC FDC37C661 Super I/O (With Secondary IDE)",
.internal_name = "fdc37c661_ide_sec",
.flags = 0,
.local = 0x261,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c663_device = {
.name = "SMC FDC37C663 Super I/O",
.internal_name = "fdc37c663",
.flags = 0,
.local = 0x63,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c663_ide_device = {
.name = "SMC FDC37C663 Super I/O (With IDE)",
.internal_name = "fdc37c663_ide",
.flags = 0,
.local = 0x163,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c665_device = {
.name = "SMC FDC37C665 Super I/O",
.internal_name = "fdc37c665",
.flags = 0,
.local = 0x65,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c665_ide_device = {
.name = "SMC FDC37C665 Super I/O (With IDE)",
.internal_name = "fdc37c665_ide",
.flags = 0,
.local = 0x265,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c665_ide_pri_device = {
.name = "SMC FDC37C665 Super I/O (With Primary IDE)",
.internal_name = "fdc37c665_ide_pri",
.flags = 0,
.local = 0x165,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c665_ide_sec_device = {
.name = "SMC FDC37C665 Super I/O (With Secondary IDE)",
.internal_name = "fdc37c665_ide_sec",
.flags = 0,
.local = 0x265,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c666_device = {
.name = "SMC FDC37C666 Super I/O",
.internal_name = "fdc37c666",
.flags = 0,
.local = 0x66,
.init = fdc37c6xx_init,
.close = fdc37c6xx_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_fdc37c6xx.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,227 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Goldstar Prime3B Super I/O
*
*
*
* Authors: Tiseno100
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#define FSR dev->regs[0xa0]
#define ASR dev->regs[0xa1]
#define PDR dev->regs[0xa2]
#define HAS_IDE_FUNCTIONALITY dev->ide_function
#ifdef ENABLE_PRIME3B_LOG
int prime3b_do_log = ENABLE_PRIME3B_LOG;
static void
prime3b_log(const char *fmt, ...)
{
va_list ap;
if (prime3b_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define prime3b_log(fmt, ...)
#endif
typedef struct prime3b_t {
uint8_t index;
uint8_t regs[256];
uint8_t cfg_lock;
uint8_t ide_function;
uint16_t com3_addr;
uint16_t com4_addr;
fdc_t *fdc_controller;
serial_t *uart[2];
} prime3b_t;
void prime3b_fdc_handler(prime3b_t *dev);
void prime3b_uart_handler(uint8_t num, prime3b_t *dev);
void prime3b_lpt_handler(prime3b_t *dev);
void prime3b_ide_handler(prime3b_t *dev);
void prime3b_enable(prime3b_t *dev);
void prime3b_powerdown(prime3b_t *dev);
static void
prime3b_write(uint16_t addr, uint8_t val, void *priv)
{
prime3b_t *dev = (prime3b_t *) priv;
if (addr == 0x398) {
dev->index = val;
/* Enter/Escape Configuration Mode */
if (val == 0x33)
dev->cfg_lock = 0;
else if (val == 0xcc)
dev->cfg_lock = 1;
} else if ((addr == 0x399) && !dev->cfg_lock) {
switch (dev->index) {
case 0xa0: /* Function Selection Register (FSR) */
FSR = val;
prime3b_enable(dev);
break;
case 0xa1: /* Address Selection Register (ASR) */
ASR = val;
prime3b_enable(dev);
break;
case 0xa2: /* Power Down Register (PDR) */
dev->regs[0xa2] = val;
break;
case 0xa3: /* Test Mode Register (TMR) */
dev->regs[0xa3] = val;
break;
case 0xa4: /* Miscellaneous Function Register */
dev->regs[0xa4] = val;
switch ((dev->regs[0xa4] >> 6) & 3) {
case 0:
dev->com3_addr = COM3_ADDR;
dev->com4_addr = COM4_ADDR;
break;
case 1:
dev->com3_addr = 0x338;
dev->com4_addr = 0x238;
break;
case 2:
dev->com3_addr = COM4_ADDR;
dev->com4_addr = 0x2e0;
break;
case 3:
dev->com3_addr = 0x220;
dev->com4_addr = 0x228;
break;
default:
break;
}
break;
case 0xa5: /* ECP Register */
dev->regs[0xa5] = val;
break;
default:
break;
}
}
}
static uint8_t
prime3b_read(UNUSED(uint16_t addr), void *priv)
{
const prime3b_t *dev = (prime3b_t *) priv;
return dev->regs[dev->index];
}
void
prime3b_fdc_handler(prime3b_t *dev)
{
uint16_t fdc_base = !(ASR & 0x40) ? FDC_PRIMARY_ADDR : FDC_SECONDARY_ADDR;
fdc_remove(dev->fdc_controller);
fdc_set_base(dev->fdc_controller, fdc_base);
prime3b_log("Prime3B-FDC: Enabled with base %03x\n", fdc_base);
}
void
prime3b_uart_handler(uint8_t num, prime3b_t *dev)
{
uint16_t uart_base;
if ((ASR >> (3 + 2 * num)) & 1)
uart_base = !((ASR >> (2 + 2 * num)) & 1) ? dev->com3_addr : dev->com4_addr;
else
uart_base = !((ASR >> (2 + 2 * num)) & 1) ? COM1_ADDR : COM2_ADDR;
serial_remove(dev->uart[num]);
serial_setup(dev->uart[num], uart_base, 4 - num);
prime3b_log("Prime3B-UART%d: Enabled with base %03x\n", num, uart_base);
}
void
prime3b_lpt_handler(prime3b_t *dev)
{
uint16_t lpt_base = (ASR & 2) ? LPT_MDA_ADDR : (!(ASR & 1) ? LPT1_ADDR : LPT2_ADDR);
lpt1_remove();
lpt1_init(lpt_base);
lpt1_irq(LPT1_IRQ);
prime3b_log("Prime3B-LPT: Enabled with base %03x\n", lpt_base);
}
void
prime3b_ide_handler(prime3b_t *dev)
{
ide_pri_disable();
uint16_t ide_base = !(ASR & 0x80) ? 0x1f0 : 0x170;
uint16_t ide_side = ide_base + 0x206;
ide_set_base(0, ide_base);
ide_set_side(0, ide_side);
prime3b_log("Prime3B-IDE: Enabled with base %03x and side %03x\n", ide_base, ide_side);
}
void
prime3b_enable(prime3b_t *dev)
{
/*
Simulate a device enable/disable scenario
Register A0: Function Selection Register (FSR)
Bit 7: Gameport
Bit 6: 4 FDD Enable
Bit 5: IDE
Bit 4: FDC
Bit 3: UART 2
Bit 2: UART 1
Bit 1/0: PIO (0/0 Bidirectional , 0/1 ECP, 1/0 EPP, 1/1 Disabled)
Note: 86Box LPT is simplistic and can't do ECP or EPP.
*/
!(FSR & 3) ? prime3b_lpt_handler(dev) : lpt1_remove();
(FSR & 4) ? prime3b_uart_handler(0, dev) : serial_remove(dev->uart[0]);
(FSR & 8) ? prime3b_uart_handler(1, dev) : serial_remove(dev->uart[1]);
(FSR & 0x10) ? prime3b_fdc_handler(dev) : fdc_remove(dev->fdc_controller);
if (HAS_IDE_FUNCTIONALITY)
(FSR & 0x20) ? prime3b_ide_handler(dev) : ide_pri_disable();
}
void
prime3b_powerdown(prime3b_t *dev)
{
/* Note: It can be done more efficiently for sure */
uint8_t old_base = PDR;
if (PDR & 1)
PDR |= 0x1e;
if (PDR & 0x40)
io_removehandler(0x0398, 0x0002, prime3b_read, NULL, NULL, prime3b_write, NULL, NULL, dev);
if (PDR & 2)
fdc_remove(dev->fdc_controller);
if (PDR & 4)
serial_remove(dev->uart[0]);
if (PDR & 8)
serial_remove(dev->uart[1]);
if (PDR & 0x10)
lpt1_remove();
if (PDR & 1)
PDR = old_base;
}
static void
prime3b_close(void *priv)
{
prime3b_t *dev = (prime3b_t *) priv;
free(dev);
}
static void *
prime3b_init(const device_t *info)
{
prime3b_t *dev = (prime3b_t *) malloc(sizeof(prime3b_t));
memset(dev, 0, sizeof(prime3b_t));
/* Avoid conflicting with machines that make no use of the Prime3B Internal IDE */
HAS_IDE_FUNCTIONALITY = info->local;
dev->regs[0xa0] = 3;
dev->fdc_controller = device_add(&fdc_at_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
if (HAS_IDE_FUNCTIONALITY)
device_add(&ide_isa_device);
dev->com3_addr = COM3_ADDR;
dev->com4_addr = COM4_ADDR;
fdc_reset(dev->fdc_controller);
prime3b_enable(dev);
io_sethandler(0x0398, 0x0002, prime3b_read, NULL, NULL, prime3b_write, NULL, NULL, dev);
return dev;
}
const device_t prime3b_device = {
.name = "Goldstar Prime3B",
.internal_name = "prime3b",
.flags = 0,
.local = 0,
.init = prime3b_init,
.close = prime3b_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t prime3b_ide_device = {
.name = "Goldstar Prime3B with IDE functionality",
.internal_name = "prime3b_ide",
.flags = 0,
.local = 1,
.init = prime3b_init,
.close = prime3b_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_prime3b.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,523 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the XT-style keyboard.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
* EngiNerd, <webmaster.crrc@yahoo.it>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
#define HAVE_STDARG_H
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/machine.h>
#include <86box/m_xt_t1000.h>
#include <86box/cassette.h>
#include <86box/io.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/ppi.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/sound.h>
#include <86box/snd_speaker.h>
#include <86box/video.h>
#include <86box/keyboard.h>
#define STAT_PARITY 0x80
#define STAT_RTIMEOUT 0x40
#define STAT_TTIMEOUT 0x20
#define STAT_LOCK 0x10
#define STAT_CD 0x08
#define STAT_SYSFLAG 0x04
#define STAT_IFULL 0x02
#define STAT_OFULL 0x01
/* Keyboard Types */
enum {
KBD_TYPE_PC81 = 0,
KBD_TYPE_PC82,
KBD_TYPE_XT82,
KBD_TYPE_XT86,
KBD_TYPE_COMPAQ,
KBD_TYPE_TANDY,
KBD_TYPE_TOSHIBA,
KBD_TYPE_VTECH,
KBD_TYPE_OLIVETTI,
KBD_TYPE_ZENITH,
KBD_TYPE_PRAVETZ,
KBD_TYPE_HYUNDAI,
KBD_TYPE_XTCLONE
};
typedef struct xtkbd_t {
int want_irq;
int blocked;
int tandy;
uint8_t pa;
uint8_t pb;
uint8_t pd;
uint8_t clock;
uint8_t key_waiting;
uint8_t type;
uint8_t pravetz_flags;
pc_timer_t send_delay_timer;
} xtkbd_t;
/*XT keyboard has no escape scancodes, and no scancodes beyond 53*/
const scancode scancode_xt[512] = {
// clang-format off
{ .mk = { 0 }, .brk = { 0 } }, /* 000 */
{ .mk = { 0x01, 0 }, .brk = { 0x81, 0 } }, /* 001 */
{ .mk = { 0x02, 0 }, .brk = { 0x82, 0 } }, /* 002 */
{ .mk = { 0x03, 0 }, .brk = { 0x83, 0 } }, /* 003 */
{ .mk = { 0x04, 0 }, .brk = { 0x84, 0 } }, /* 004 */
{ .mk = { 0x05, 0 }, .brk = { 0x85, 0 } }, /* 005 */
{ .mk = { 0x06, 0 }, .brk = { 0x86, 0 } }, /* 006 */
{ .mk = { 0x07, 0 }, .brk = { 0x87, 0 } }, /* 007 */
{ .mk = { 0x08, 0 }, .brk = { 0x88, 0 } }, /* 008 */
{ .mk = { 0x09, 0 }, .brk = { 0x89, 0 } }, /* 009 */
{ .mk = { 0x0a, 0 }, .brk = { 0x8a, 0 } }, /* 00a */
{ .mk = { 0x0b, 0 }, .brk = { 0x8b, 0 } }, /* 00b */
{ .mk = { 0x0c, 0 }, .brk = { 0x8c, 0 } }, /* 00c */
{ .mk = { 0x0d, 0 }, .brk = { 0x8d, 0 } }, /* 00d */
{ .mk = { 0x0e, 0 }, .brk = { 0x8e, 0 } }, /* 00e */
{ .mk = { 0x0f, 0 }, .brk = { 0x8f, 0 } }, /* 00f */
{ .mk = { 0x10, 0 }, .brk = { 0x90, 0 } }, /* 010 */
{ .mk = { 0x11, 0 }, .brk = { 0x91, 0 } }, /* 011 */
{ .mk = { 0x12, 0 }, .brk = { 0x92, 0 } }, /* 012 */
{ .mk = { 0x13, 0 }, .brk = { 0x93, 0 } }, /* 013 */
{ .mk = { 0x14, 0 }, .brk = { 0x94, 0 } }, /* 014 */
{ .mk = { 0x15, 0 }, .brk = { 0x95, 0 } }, /* 015 */
{ .mk = { 0x16, 0 }, .brk = { 0x96, 0 } }, /* 016 */
{ .mk = { 0x17, 0 }, .brk = { 0x97, 0 } }, /* 017 */
{ .mk = { 0x18, 0 }, .brk = { 0x98, 0 } }, /* 018 */
{ .mk = { 0x19, 0 }, .brk = { 0x99, 0 } }, /* 019 */
{ .mk = { 0x1a, 0 }, .brk = { 0x9a, 0 } }, /* 01a */
{ .mk = { 0x1b, 0 }, .brk = { 0x9b, 0 } }, /* 01b */
{ .mk = { 0x1c, 0 }, .brk = { 0x9c, 0 } }, /* 01c */
{ .mk = { 0x1d, 0 }, .brk = { 0x9d, 0 } }, /* 01d */
{ .mk = { 0x1e, 0 }, .brk = { 0x9e, 0 } }, /* 01e */
{ .mk = { 0x1f, 0 }, .brk = { 0x9f, 0 } }, /* 01f */
{ .mk = { 0x20, 0 }, .brk = { 0xa0, 0 } }, /* 020 */
{ .mk = { 0x21, 0 }, .brk = { 0xa1, 0 } }, /* 021 */
{ .mk = { 0x22, 0 }, .brk = { 0xa2, 0 } }, /* 022 */
{ .mk = { 0x23, 0 }, .brk = { 0xa3, 0 } }, /* 023 */
{ .mk = { 0x24, 0 }, .brk = { 0xa4, 0 } }, /* 024 */
{ .mk = { 0x25, 0 }, .brk = { 0xa5, 0 } }, /* 025 */
{ .mk = { 0x26, 0 }, .brk = { 0xa6, 0 } }, /* 026 */
{ .mk = { 0x27, 0 }, .brk = { 0xa7, 0 } }, /* 027 */
{ .mk = { 0x28, 0 }, .brk = { 0xa8, 0 } }, /* 028 */
{ .mk = { 0x29, 0 }, .brk = { 0xa9, 0 } }, /* 029 */
{ .mk = { 0x2a, 0 }, .brk = { 0xaa, 0 } }, /* 02a */
{ .mk = { 0x2b, 0 }, .brk = { 0xab, 0 } }, /* 02b */
{ .mk = { 0x2c, 0 }, .brk = { 0xac, 0 } }, /* 02c */
{ .mk = { 0x2d, 0 }, .brk = { 0xad, 0 } }, /* 02d */
{ .mk = { 0x2e, 0 }, .brk = { 0xae, 0 } }, /* 02e */
{ .mk = { 0x2f, 0 }, .brk = { 0xaf, 0 } }, /* 02f */
{ .mk = { 0x30, 0 }, .brk = { 0xb0, 0 } }, /* 030 */
{ .mk = { 0x31, 0 }, .brk = { 0xb1, 0 } }, /* 031 */
{ .mk = { 0x32, 0 }, .brk = { 0xb2, 0 } }, /* 032 */
{ .mk = { 0x33, 0 }, .brk = { 0xb3, 0 } }, /* 033 */
{ .mk = { 0x34, 0 }, .brk = { 0xb4, 0 } }, /* 034 */
{ .mk = { 0x35, 0 }, .brk = { 0xb5, 0 } }, /* 035 */
{ .mk = { 0x36, 0 }, .brk = { 0xb6, 0 } }, /* 036 */
{ .mk = { 0x37, 0 }, .brk = { 0xb7, 0 } }, /* 037 */
{ .mk = { 0x38, 0 }, .brk = { 0xb8, 0 } }, /* 038 */
{ .mk = { 0x39, 0 }, .brk = { 0xb9, 0 } }, /* 039 */
{ .mk = { 0x3a, 0 }, .brk = { 0xba, 0 } }, /* 03a */
{ .mk = { 0x3b, 0 }, .brk = { 0xbb, 0 } }, /* 03b */
{ .mk = { 0x3c, 0 }, .brk = { 0xbc, 0 } }, /* 03c */
{ .mk = { 0x3d, 0 }, .brk = { 0xbd, 0 } }, /* 03d */
{ .mk = { 0x3e, 0 }, .brk = { 0xbe, 0 } }, /* 03e */
{ .mk = { 0x3f, 0 }, .brk = { 0xbf, 0 } }, /* 03f */
{ .mk = { 0x40, 0 }, .brk = { 0xc0, 0 } }, /* 040 */
{ .mk = { 0x41, 0 }, .brk = { 0xc1, 0 } }, /* 041 */
{ .mk = { 0x42, 0 }, .brk = { 0xc2, 0 } }, /* 042 */
{ .mk = { 0x43, 0 }, .brk = { 0xc3, 0 } }, /* 043 */
{ .mk = { 0x44, 0 }, .brk = { 0xc4, 0 } }, /* 044 */
{ .mk = { 0x45, 0 }, .brk = { 0xc5, 0 } }, /* 045 */
{ .mk = { 0x46, 0 }, .brk = { 0xc6, 0 } }, /* 046 */
{ .mk = { 0x47, 0 }, .brk = { 0xc7, 0 } }, /* 047 */
{ .mk = { 0x48, 0 }, .brk = { 0xc8, 0 } }, /* 048 */
{ .mk = { 0x49, 0 }, .brk = { 0xc9, 0 } }, /* 049 */
{ .mk = { 0x4a, 0 }, .brk = { 0xca, 0 } }, /* 04a */
{ .mk = { 0x4b, 0 }, .brk = { 0xcb, 0 } }, /* 04b */
{ .mk = { 0x4c, 0 }, .brk = { 0xcc, 0 } }, /* 04c */
{ .mk = { 0x4d, 0 }, .brk = { 0xcd, 0 } }, /* 04d */
{ .mk = { 0x4e, 0 }, .brk = { 0xce, 0 } }, /* 04e */
{ .mk = { 0x4f, 0 }, .brk = { 0xcf, 0 } }, /* 04f */
{ .mk = { 0x50, 0 }, .brk = { 0xd0, 0 } }, /* 050 */
{ .mk = { 0x51, 0 }, .brk = { 0xd1, 0 } }, /* 051 */
{ .mk = { 0x52, 0 }, .brk = { 0xd2, 0 } }, /* 052 */
{ .mk = { 0x53, 0 }, .brk = { 0xd3, 0 } }, /* 053 */
{ .mk = { 0 }, .brk = { 0 } }, /* 054 */
{ .mk = { 0 }, .brk = { 0 } }, /* 055 */
{ .mk = { 0 }, .brk = { 0 } }, /* 056 */
{ .mk = { 0 }, .brk = { 0 } }, /* 057 */
{ .mk = { 0 }, .brk = { 0 } }, /* 058 */
{ .mk = { 0 }, .brk = { 0 } }, /* 059 */
{ .mk = { 0 }, .brk = { 0 } }, /* 05a */
{ .mk = { 0 }, .brk = { 0 } }, /* 05b */
{ .mk = { 0 }, .brk = { 0 } }, /* 05c */
{ .mk = { 0 }, .brk = { 0 } }, /* 05d */
{ .mk = { 0 }, .brk = { 0 } }, /* 05e */
{ .mk = { 0 }, .brk = { 0 } }, /* 05f */
{ .mk = { 0 }, .brk = { 0 } }, /* 060 */
{ .mk = { 0 }, .brk = { 0 } }, /* 061 */
{ .mk = { 0 }, .brk = { 0 } }, /* 062 */
{ .mk = { 0 }, .brk = { 0 } }, /* 063 */
{ .mk = { 0 }, .brk = { 0 } }, /* 064 */
{ .mk = { 0 }, .brk = { 0 } }, /* 065 */
{ .mk = { 0 }, .brk = { 0 } }, /* 066 */
{ .mk = { 0 }, .brk = { 0 } }, /* 067 */
{ .mk = { 0 }, .brk = { 0 } }, /* 068 */
{ .mk = { 0 }, .brk = { 0 } }, /* 069 */
{ .mk = { 0 }, .brk = { 0 } }, /* 06a */
{ .mk = { 0 }, .brk = { 0 } }, /* 06b */
{ .mk = { 0 }, .brk = { 0 } }, /* 06c */
{ .mk = { 0 }, .brk = { 0 } }, /* 06d */
{ .mk = { 0 }, .brk = { 0 } }, /* 06e */
{ .mk = { 0 }, .brk = { 0 } }, /* 06f */
{ .mk = { 0 }, .brk = { 0 } }, /* 070 */
{ .mk = { 0 }, .brk = { 0 } }, /* 071 */
{ .mk = { 0 }, .brk = { 0 } }, /* 072 */
{ .mk = { 0 }, .brk = { 0 } }, /* 073 */
{ .mk = { 0 }, .brk = { 0 } }, /* 074 */
{ .mk = { 0 }, .brk = { 0 } }, /* 075 */
{ .mk = { 0 }, .brk = { 0 } }, /* 076 */
{ .mk = { 0 }, .brk = { 0 } }, /* 077 */
{ .mk = { 0 }, .brk = { 0 } }, /* 078 */
{ .mk = { 0 }, .brk = { 0 } }, /* 079 */
{ .mk = { 0 }, .brk = { 0 } }, /* 07a */
{ .mk = { 0 }, .brk = { 0 } }, /* 07b */
{ .mk = { 0 }, .brk = { 0 } }, /* 07c */
{ .mk = { 0 }, .brk = { 0 } }, /* 07d */
{ .mk = { 0 }, .brk = { 0 } }, /* 07e */
{ .mk = { 0 }, .brk = { 0 } }, /* 07f */
{ .mk = { 0 }, .brk = { 0 } }, /* 080 */
{ .mk = { 0 }, .brk = { 0 } }, /* 081 */
{ .mk = { 0 }, .brk = { 0 } }, /* 082 */
{ .mk = { 0 }, .brk = { 0 } }, /* 083 */
{ .mk = { 0 }, .brk = { 0 } }, /* 084 */
{ .mk = { 0 }, .brk = { 0 } }, /* 085 */
{ .mk = { 0 }, .brk = { 0 } }, /* 086 */
{ .mk = { 0 }, .brk = { 0 } }, /* 087 */
{ .mk = { 0 }, .brk = { 0 } }, /* 088 */
{ .mk = { 0 }, .brk = { 0 } }, /* 089 */
{ .mk = { 0 }, .brk = { 0 } }, /* 08a */
{ .mk = { 0 }, .brk = { 0 } }, /* 08b */
{ .mk = { 0 }, .brk = { 0 } }, /* 08c */
{ .mk = { 0 }, .brk = { 0 } }, /* 08d */
{ .mk = { 0 }, .brk = { 0 } }, /* 08e */
{ .mk = { 0 }, .brk = { 0 } }, /* 08f */
{ .mk = { 0 }, .brk = { 0 } }, /* 090 */
{ .mk = { 0 }, .brk = { 0 } }, /* 091 */
{ .mk = { 0 }, .brk = { 0 } }, /* 092 */
{ .mk = { 0 }, .brk = { 0 } }, /* 093 */
{ .mk = { 0 }, .brk = { 0 } }, /* 094 */
{ .mk = { 0 }, .brk = { 0 } }, /* 095 */
{ .mk = { 0 }, .brk = { 0 } }, /* 096 */
{ .mk = { 0 }, .brk = { 0 } }, /* 097 */
{ .mk = { 0 }, .brk = { 0 } }, /* 098 */
{ .mk = { 0 }, .brk = { 0 } }, /* 099 */
{ .mk = { 0 }, .brk = { 0 } }, /* 09a */
{ .mk = { 0 }, .brk = { 0 } }, /* 09b */
{ .mk = { 0 }, .brk = { 0 } }, /* 09c */
{ .mk = { 0 }, .brk = { 0 } }, /* 09d */
{ .mk = { 0 }, .brk = { 0 } }, /* 09e */
{ .mk = { 0 }, .brk = { 0 } }, /* 09f */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 0af */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0be */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0da */
{ .mk = { 0 }, .brk = { 0 } }, /* 0db */
{ .mk = { 0 }, .brk = { 0 } }, /* 0dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0de */
{ .mk = { 0 }, .brk = { 0 } }, /* 0df */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 0eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ed */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fe */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ff */
{ .mk = { 0 }, .brk = { 0 } }, /* 100 */
{ .mk = { 0 }, .brk = { 0 } }, /* 101 */
{ .mk = { 0 }, .brk = { 0 } }, /* 102 */
{ .mk = { 0 }, .brk = { 0 } }, /* 103 */
{ .mk = { 0 }, .brk = { 0 } }, /* 104 */
{ .mk = { 0 }, .brk = { 0 } }, /* 105 */
{ .mk = { 0 }, .brk = { 0 } }, /* 106 */
{ .mk = { 0 }, .brk = { 0 } }, /* 107 */
{ .mk = { 0 }, .brk = { 0 } }, /* 108 */
{ .mk = { 0 }, .brk = { 0 } }, /* 109 */
{ .mk = { 0 }, .brk = { 0 } }, /* 10a */
{ .mk = { 0 }, .brk = { 0 } }, /* 10b */
{ .mk = { 0 }, .brk = { 0 } }, /* 10c */
{ .mk = { 0 }, .brk = { 0 } }, /* 10d */
{ .mk = { 0 }, .brk = { 0 } }, /* 10e */
{ .mk = { 0 }, .brk = { 0 } }, /* 10f */
{ .mk = { 0 }, .brk = { 0 } }, /* 110 */
{ .mk = { 0 }, .brk = { 0 } }, /* 111 */
{ .mk = { 0 }, .brk = { 0 } }, /* 112 */
{ .mk = { 0 }, .brk = { 0 } }, /* 113 */
{ .mk = { 0 }, .brk = { 0 } }, /* 114 */
{ .mk = { 0 }, .brk = { 0 } }, /* 115 */
{ .mk = { 0 }, .brk = { 0 } }, /* 116 */
{ .mk = { 0 }, .brk = { 0 } }, /* 117 */
{ .mk = { 0 }, .brk = { 0 } }, /* 118 */
{ .mk = { 0 }, .brk = { 0 } }, /* 119 */
{ .mk = { 0 }, .brk = { 0 } }, /* 11a */
{ .mk = { 0 }, .brk = { 0 } }, /* 11b */
{ .mk = { 0x1c, 0 }, .brk = { 0x9c, 0 } }, /* 11c */
{ .mk = { 0x1d, 0 }, .brk = { 0x9d, 0 } }, /* 11d */
{ .mk = { 0 }, .brk = { 0 } }, /* 11e */
{ .mk = { 0 }, .brk = { 0 } }, /* 11f */
{ .mk = { 0 }, .brk = { 0 } }, /* 120 */
{ .mk = { 0 }, .brk = { 0 } }, /* 121 */
{ .mk = { 0 }, .brk = { 0 } }, /* 122 */
{ .mk = { 0 }, .brk = { 0 } }, /* 123 */
{ .mk = { 0 }, .brk = { 0 } }, /* 124 */
{ .mk = { 0 }, .brk = { 0 } }, /* 125 */
{ .mk = { 0 }, .brk = { 0 } }, /* 126 */
{ .mk = { 0 }, .brk = { 0 } }, /* 127 */
{ .mk = { 0 }, .brk = { 0 } }, /* 128 */
{ .mk = { 0 }, .brk = { 0 } }, /* 129 */
{ .mk = { 0 }, .brk = { 0 } }, /* 12a */
{ .mk = { 0 }, .brk = { 0 } }, /* 12b */
{ .mk = { 0 }, .brk = { 0 } }, /* 12c */
{ .mk = { 0 }, .brk = { 0 } }, /* 12d */
{ .mk = { 0 }, .brk = { 0 } }, /* 12e */
{ .mk = { 0 }, .brk = { 0 } }, /* 12f */
{ .mk = { 0 }, .brk = { 0 } }, /* 130 */
{ .mk = { 0 }, .brk = { 0 } }, /* 131 */
{ .mk = { 0 }, .brk = { 0 } }, /* 132 */
{ .mk = { 0 }, .brk = { 0 } }, /* 133 */
{ .mk = { 0 }, .brk = { 0 } }, /* 134 */
{ .mk = { 0x35, 0 }, .brk = { 0xb5, 0 } }, /* 135 */
{ .mk = { 0 }, .brk = { 0 } }, /* 136 */
{ .mk = { 0x37, 0 }, .brk = { 0xb7, 0 } }, /* 137 */
{ .mk = { 0x38, 0 }, .brk = { 0xb8, 0 } }, /* 138 */
{ .mk = { 0 }, .brk = { 0 } }, /* 139 */
{ .mk = { 0 }, .brk = { 0 } }, /* 13a */
{ .mk = { 0 }, .brk = { 0 } }, /* 13b */
{ .mk = { 0 }, .brk = { 0 } }, /* 13c */
{ .mk = { 0 }, .brk = { 0 } }, /* 13d */
{ .mk = { 0 }, .brk = { 0 } }, /* 13e */
{ .mk = { 0 }, .brk = { 0 } }, /* 13f */
{ .mk = { 0 }, .brk = { 0 } }, /* 140 */
{ .mk = { 0 }, .brk = { 0 } }, /* 141 */
{ .mk = { 0 }, .brk = { 0 } }, /* 142 */
{ .mk = { 0 }, .brk = { 0 } }, /* 143 */
{ .mk = { 0 }, .brk = { 0 } }, /* 144 */
{ .mk = { 0 }, .brk = { 0 } }, /* 145 */
{ .mk = { 0x46, 0 }, .brk = { 0xc6, 0 } }, /* 146 */
{ .mk = { 0x47, 0 }, .brk = { 0xc7, 0 } }, /* 147 */
{ .mk = { 0x48, 0 }, .brk = { 0xc8, 0 } }, /* 148 */
{ .mk = { 0x49, 0 }, .brk = { 0xc9, 0 } }, /* 149 */
{ .mk = { 0 }, .brk = { 0 } }, /* 14a */
{ .mk = { 0x4b, 0 }, .brk = { 0xcb, 0 } }, /* 14b */
{ .mk = { 0 }, .brk = { 0 } }, /* 14c */
{ .mk = { 0x4d, 0 }, .brk = { 0xcd, 0 } }, /* 14d */
{ .mk = { 0 }, .brk = { 0 } }, /* 14e */
{ .mk = { 0x4f, 0 }, .brk = { 0xcf, 0 } }, /* 14f */
{ .mk = { 0x50, 0 }, .brk = { 0xd0, 0 } }, /* 150 */
{ .mk = { 0x51, 0 }, .brk = { 0xd1, 0 } }, /* 151 */
{ .mk = { 0x52, 0 }, .brk = { 0xd2, 0 } }, /* 152 */
{ .mk = { 0x53, 0 }, .brk = { 0xd3, 0 } }, /* 153 */
{ .mk = { 0 }, .brk = { 0 } }, /* 154 */
{ .mk = { 0 }, .brk = { 0 } }, /* 155 */
{ .mk = { 0 }, .brk = { 0 } }, /* 156 */
{ .mk = { 0 }, .brk = { 0 } }, /* 157 */
{ .mk = { 0 }, .brk = { 0 } }, /* 158 */
{ .mk = { 0 }, .brk = { 0 } }, /* 159 */
{ .mk = { 0 }, .brk = { 0 } }, /* 15a */
{ .mk = { 0 }, .brk = { 0 } }, /* 15b */
{ .mk = { 0 }, .brk = { 0 } }, /* 15c */
{ .mk = { 0 }, .brk = { 0 } }, /* 15d */
{ .mk = { 0 }, .brk = { 0 } }, /* 15e */
{ .mk = { 0 }, .brk = { 0 } }, /* 15f */
{ .mk = { 0 }, .brk = { 0 } }, /* 160 */
{ .mk = { 0 }, .brk = { 0 } }, /* 161 */
{ .mk = { 0 }, .brk = { 0 } }, /* 162 */
{ .mk = { 0 }, .brk = { 0 } }, /* 163 */
{ .mk = { 0 }, .brk = { 0 } }, /* 164 */
{ .mk = { 0 }, .brk = { 0 } }, /* 165 */
{ .mk = { 0 }, .brk = { 0 } }, /* 166 */
{ .mk = { 0 }, .brk = { 0 } }, /* 167 */
{ .mk = { 0 }, .brk = { 0 } }, /* 168 */
{ .mk = { 0 }, .brk = { 0 } }, /* 169 */
{ .mk = { 0 }, .brk = { 0 } }, /* 16a */
{ .mk = { 0 }, .brk = { 0 } }, /* 16b */
{ .mk = { 0 }, .brk = { 0 } }, /* 16c */
{ .mk = { 0 }, .brk = { 0 } }, /* 16d */
{ .mk = { 0 }, .brk = { 0 } }, /* 16e */
{ .mk = { 0 }, .brk = { 0 } }, /* 16f */
{ .mk = { 0 }, .brk = { 0 } }, /* 170 */
{ .mk = { 0 }, .brk = { 0 } }, /* 171 */
{ .mk = { 0 }, .brk = { 0 } }, /* 172 */
{ .mk = { 0 }, .brk = { 0 } }, /* 173 */
{ .mk = { 0 }, .brk = { 0 } }, /* 174 */
{ .mk = { 0 }, .brk = { 0 } }, /* 175 */
{ .mk = { 0 }, .brk = { 0 } }, /* 176 */
{ .mk = { 0 }, .brk = { 0 } }, /* 177 */
{ .mk = { 0 }, .brk = { 0 } }, /* 178 */
{ .mk = { 0 }, .brk = { 0 } }, /* 179 */
{ .mk = { 0 }, .brk = { 0 } }, /* 17a */
{ .mk = { 0 }, .brk = { 0 } }, /* 17b */
{ .mk = { 0 }, .brk = { 0 } }, /* 17c */
{ .mk = { 0 }, .brk = { 0 } }, /* 17d */
{ .mk = { 0 }, .brk = { 0 } }, /* 17e */
{ .mk = { 0 }, .brk = { 0 } }, /* 17f */
{ .mk = { 0 }, .brk = { 0 } }, /* 180 */
{ .mk = { 0 }, .brk = { 0 } }, /* 181 */
{ .mk = { 0 }, .brk = { 0 } }, /* 182 */
{ .mk = { 0 }, .brk = { 0 } }, /* 183 */
{ .mk = { 0 }, .brk = { 0 } }, /* 184 */
{ .mk = { 0 }, .brk = { 0 } }, /* 185 */
{ .mk = { 0 }, .brk = { 0 } }, /* 186 */
{ .mk = { 0 }, .brk = { 0 } }, /* 187 */
{ .mk = { 0 }, .brk = { 0 } }, /* 188 */
{ .mk = { 0 }, .brk = { 0 } }, /* 189 */
{ .mk = { 0 }, .brk = { 0 } }, /* 18a */
{ .mk = { 0 }, .brk = { 0 } }, /* 18b */
{ .mk = { 0 }, .brk = { 0 } }, /* 18c */
{ .mk = { 0 }, .brk = { 0 } }, /* 18d */
{ .mk = { 0 }, .brk = { 0 } }, /* 18e */
{ .mk = { 0 }, .brk = { 0 } }, /* 18f */
{ .mk = { 0 }, .brk = { 0 } }, /* 190 */
{ .mk = { 0 }, .brk = { 0 } }, /* 191 */
{ .mk = { 0 }, .brk = { 0 } }, /* 192 */
{ .mk = { 0 }, .brk = { 0 } }, /* 193 */
{ .mk = { 0 }, .brk = { 0 } }, /* 194 */
{ .mk = { 0 }, .brk = { 0 } }, /* 195 */
{ .mk = { 0 }, .brk = { 0 } }, /* 196 */
{ .mk = { 0 }, .brk = { 0 } }, /* 197 */
{ .mk = { 0 }, .brk = { 0 } }, /* 198 */
{ .mk = { 0 }, .brk = { 0 } }, /* 199 */
{ .mk = { 0 }, .brk = { 0 } }, /* 19a */
{ .mk = { 0 }, .brk = { 0 } }, /* 19b */
{ .mk = { 0 }, .brk = { 0 } }, /* 19c */
{ .mk = { 0 }, .brk = { 0 } }, /* 19d */
{ .mk = { 0 }, .brk = { 0 } }, /* 19e */
{ .mk = { 0 }, .brk = { 0 } }, /* 19f */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 1af */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1be */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1da */
{ .mk = { 0 }, .brk = { 0 } }, /* 1db */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1de */
{ .mk = { 0 }, .brk = { 0 } }, /* 1df */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 1eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ed */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fe */
{ .mk = { 0 }, .brk = { 0 } } /* 1ff */
// clang-format on
};
static uint8_t key_queue[16];
static int key_queue_start = 0;
static int key_queue_end = 0;
static int is_tandy = 0;
static int is_t1x00 = 0;
static int is_amstrad = 0;
#ifdef ENABLE_KEYBOARD_XT_LOG
int keyboard_xt_do_log = ENABLE_KEYBOARD_XT_LOG;
static void
kbd_log(const char *fmt, ...)
{
va_list ap;
if (keyboard_xt_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define kbd_log(fmt, ...)
#endif
static uint8_t
get_fdd_switch_settings(void)
{
uint8_t fdd_count = 0;
for (uint8_t i = 0; i < FDD_NUM; i++) {
if (fdd_get_flags(i))
fdd_count++;
}
if (!fdd_count)
return 0x00;
else
return ((fdd_count - 1) << 6) | 0x01;
}
static uint8_t
get_videomode_switch_settings(void)
{
if (video_is_mda())
return 0x30;
else if (video_is_cga())
return 0x20; /* 0x10 would be 40x25 */
else
return 0x00;
}
static void
kbd_poll(void *priv)
{
xtkbd_t *kbd = (xtkbd_t *) priv;
timer_advance_u64(&kbd->send_delay_timer, 1000 * TIMER_USEC);
if (!(kbd->pb & 0x40) && (kbd->type != KBD_TYPE_TANDY))
return;
if (kbd->want_irq) {
kbd->want_irq = 0;
kbd->pa = kbd->key_waiting;
kbd->blocked = 1;
picint(2);
#ifdef ENABLE_KEYBOARD_XT_LOG
kbd_log("XTkbd: kbd_poll(): keyboard_xt : take IRQ\n");
#endif
}
if ((key_queue_start != key_queue_end) && !kbd->blocked) {
kbd->key_waiting = key_queue[key_queue_start];
kbd_log("XTkbd: reading %02X from the key queue at %i\n",
kbd->key_waiting, key_queue_start);
key_queue_start = (key_queue_start + 1) & 0x0f;
kbd->want_irq = 1;
}
}
static void
kbd_adddata(uint16_t val)
{
/* Test for T1000 'Fn' key (Right Alt / Right Ctrl) */
if (is_t1x00) {
if (keyboard_recv(0x138) || keyboard_recv(0x11d)) { /* 'Fn' pressed */
t1000_syskey(0x00, 0x04, 0x00); /* Set 'Fn' indicator */
switch (val) {
case 0x45: /* Num Lock => toggle numpad */
t1000_syskey(0x00, 0x00, 0x10);
break;
case 0x47: /* Home => internal display */
t1000_syskey(0x40, 0x00, 0x00);
break;
case 0x49: /* PgDn => turbo on */
t1000_syskey(0x80, 0x00, 0x00);
break;
case 0x4D: /* Right => toggle LCD font */
t1000_syskey(0x00, 0x00, 0x20);
break;
case 0x4F: /* End => external display */
t1000_syskey(0x00, 0x40, 0x00);
break;
case 0x51: /* PgDn => turbo off */
t1000_syskey(0x00, 0x80, 0x00);
break;
case 0x54: /* SysRQ => toggle window */
t1000_syskey(0x00, 0x00, 0x08);
break;
default:
break;
}
} else
t1000_syskey(0x04, 0x00, 0x00); /* Reset 'Fn' indicator */
}
key_queue[key_queue_end] = val;
kbd_log("XTkbd: %02X added to key queue at %i\n",
val, key_queue_end);
key_queue_end = (key_queue_end + 1) & 0x0f;
}
void
kbd_adddata_process(uint16_t val, void (*adddata)(uint16_t val))
{
uint8_t num_lock = 0;
uint8_t shift_states = 0;
if (!adddata)
return;
keyboard_get_states(NULL, &num_lock, NULL);
shift_states = keyboard_get_shift() & STATE_LSHIFT;
if (is_amstrad)
num_lock = !num_lock;
/* If NumLock is on, invert the left shift state so we can always check for
the the same way flag being set (and with NumLock on that then means it
is actually *NOT* set). */
if (num_lock)
shift_states ^= STATE_LSHIFT;
switch (val) {
case FAKE_LSHIFT_ON:
/* If NumLock is on, fake shifts are sent when shift is *NOT* presed,
if NumLock is off, fake shifts are sent when shift is pressed. */
if (shift_states) {
/* Send fake shift. */
adddata(num_lock ? 0x2a : 0xaa);
}
break;
case FAKE_LSHIFT_OFF:
if (shift_states) {
/* Send fake shift. */
adddata(num_lock ? 0xaa : 0x2a);
}
break;
default:
adddata(val);
break;
}
}
static void
kbd_adddata_ex(uint16_t val)
{
kbd_adddata_process(val, kbd_adddata);
}
static void
kbd_write(uint16_t port, uint8_t val, void *priv)
{
xtkbd_t *kbd = (xtkbd_t *) priv;
uint8_t bit;
uint8_t set;
uint8_t new_clock;
switch (port) {
case 0x61: /* Keyboard Control Register (aka Port B) */
if (!(val & 0x80) || (kbd->type == KBD_TYPE_HYUNDAI)) {
new_clock = !!(val & 0x40);
if (!kbd->clock && new_clock) {
key_queue_start = key_queue_end = 0;
kbd->want_irq = 0;
kbd->blocked = 0;
kbd_adddata(0xaa);
}
}
kbd->pb = val;
if (!(kbd->pb & 0x80) || (kbd->type == KBD_TYPE_HYUNDAI))
kbd->clock = !!(kbd->pb & 0x40);
ppi.pb = val;
timer_process();
if (((kbd->type == KBD_TYPE_PC81) || (kbd->type == KBD_TYPE_PC82) ||
(kbd->type == KBD_TYPE_PRAVETZ)) && (cassette != NULL))
pc_cas_set_motor(cassette, (kbd->pb & 0x08) == 0);
speaker_update();
speaker_gated = val & 1;
speaker_enable = val & 2;
if (speaker_enable)
was_speaker_enable = 1;
pit_devs[0].set_gate(pit_devs[0].data, 2, val & 1);
if (val & 0x80) {
kbd->pa = 0;
kbd->blocked = 0;
picintc(2);
}
#ifdef ENABLE_KEYBOARD_XT_LOG
if ((kbd->type == KBD_TYPE_PC81) || (kbd->type == KBD_TYPE_PC82) || (kbd->type == KBD_TYPE_PRAVETZ))
kbd_log("XTkbd: Cassette motor is %s\n", !(val & 0x08) ? "ON" : "OFF");
#endif
break;
#ifdef ENABLE_KEYBOARD_XT_LOG
case 0x62: /* Switch Register (aka Port C) */
if ((kbd->type == KBD_TYPE_PC81) || (kbd->type == KBD_TYPE_PC82) || (kbd->type == KBD_TYPE_PRAVETZ))
kbd_log("XTkbd: Cassette IN is %i\n", !!(val & 0x10));
break;
#endif
case 0xc0 ... 0xcf: /* Pravetz Flags */
kbd_log("XTkbd: Port %02X out: %02X\n", port, val);
if (kbd->type == KBD_TYPE_PRAVETZ) {
bit = (port >> 1) & 0x07;
set = (port & 0x01) << bit;
kbd->pravetz_flags = (kbd->pravetz_flags & ~(1 << bit)) | set;
}
break;
default:
break;
}
}
static uint8_t
kbd_read(uint16_t port, void *priv)
{
const xtkbd_t *kbd = (xtkbd_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x60: /* Keyboard Data Register (aka Port A) */
if ((kbd->pb & 0x80) && ((kbd->type == KBD_TYPE_PC81) ||
(kbd->type == KBD_TYPE_PC82) || (kbd->type == KBD_TYPE_PRAVETZ) ||
(kbd->type == KBD_TYPE_XT82) || (kbd->type == KBD_TYPE_XT86) ||
(kbd->type == KBD_TYPE_XTCLONE) || (kbd->type == KBD_TYPE_COMPAQ) ||
(kbd->type == KBD_TYPE_ZENITH) || (kbd->type == KBD_TYPE_HYUNDAI))) {
if ((kbd->type == KBD_TYPE_PC81) || (kbd->type == KBD_TYPE_PC82) ||
(kbd->type == KBD_TYPE_XTCLONE) || (kbd->type == KBD_TYPE_COMPAQ) ||
(kbd->type == KBD_TYPE_PRAVETZ) || (kbd->type == KBD_TYPE_HYUNDAI))
ret = (kbd->pd & ~0x02) | (hasfpu ? 0x02 : 0x00);
else if ((kbd->type == KBD_TYPE_XT82) || (kbd->type == KBD_TYPE_XT86))
/* According to Ruud on the PCem forum, this is supposed to
return 0xFF on the XT. */
ret = 0xff;
else if (kbd->type == KBD_TYPE_ZENITH) {
/* Zenith Data Systems Z-151
* SW1 switch settings:
* bits 6-7: floppy drive number
* bits 4-5: video mode
* bit 2-3: base memory size
* bit 1: fpu enable
* bit 0: fdc enable
*/
ret = get_fdd_switch_settings();
ret |= get_videomode_switch_settings();
/* Base memory size should always be 64k */
ret |= 0x0c;
if (hasfpu)
ret |= 0x02;
}
} else
ret = kbd->pa;
break;
case 0x61: /* Keyboard Control Register (aka Port B) */
ret = kbd->pb;
break;
case 0x62: /* Switch Register (aka Port C) */
if ((kbd->type == KBD_TYPE_PC81) || (kbd->type == KBD_TYPE_PC82) ||
(kbd->type == KBD_TYPE_PRAVETZ)) {
if (kbd->pb & 0x04) /* PB2 */
switch (mem_size + isa_mem_size) {
case 64:
case 48:
case 32:
case 16:
ret = 0x00;
break;
default:
ret = (((mem_size + isa_mem_size) - 64) / 32) & 0x0f;
break;
}
else
ret = (((mem_size + isa_mem_size) - 64) / 32) >> 4;
} else if ((kbd->type == KBD_TYPE_OLIVETTI) ||
(kbd->type == KBD_TYPE_ZENITH)) {
/* Olivetti M19 or Zenith Data Systems Z-151 */
if (kbd->pb & 0x04) /* PB2 */
ret = kbd->pd & 0xbf;
else
ret = kbd->pd >> 4;
} else {
if (kbd->pb & 0x08) /* PB3 */
ret = kbd->pd >> 4;
else {
/* LaserXT = Always 512k RAM;
LaserXT/3 = Bit 0: set = 512k, clear = 256k. */
#ifdef USE_LASERXT
if (kbd->type == KBD_TYPE_VTECH)
ret = ((mem_size == 512) ? 0x0d : 0x0c) | (hasfpu ? 0x02 : 0x00);
else
#endif /* USE_LASERXT */
ret = (kbd->pd & 0x0d) | (hasfpu ? 0x02 : 0x00);
}
}
ret |= (ppispeakon ? 0x20 : 0);
/* This is needed to avoid error 131 (cassette error).
This is serial read: bit 5 = clock, bit 4 = data, cassette header is 256 x 0xff. */
if ((kbd->type == KBD_TYPE_PC81) || (kbd->type == KBD_TYPE_PC82) ||
(kbd->type == KBD_TYPE_PRAVETZ)) {
if (cassette == NULL)
ret |= (ppispeakon ? 0x10 : 0);
else
ret |= (pc_cas_get_inp(cassette) ? 0x10 : 0);
}
if (kbd->type == KBD_TYPE_TANDY)
ret |= (tandy1k_eeprom_read() ? 0x10 : 0);
break;
case 0x63: /* Keyboard Configuration Register (aka Port D) */
if ((kbd->type == KBD_TYPE_XT82) || (kbd->type == KBD_TYPE_XT86) ||
(kbd->type == KBD_TYPE_XTCLONE) || (kbd->type == KBD_TYPE_COMPAQ) ||
(kbd->type == KBD_TYPE_TOSHIBA) || (kbd->type == KBD_TYPE_HYUNDAI))
ret = kbd->pd;
break;
case 0xc0: /* Pravetz Flags */
if (kbd->type == KBD_TYPE_PRAVETZ)
ret = kbd->pravetz_flags;
kbd_log("XTkbd: Port %02X in : %02X\n", port, ret);
break;
default:
break;
}
return ret;
}
static void
kbd_reset(void *priv)
{
xtkbd_t *kbd = (xtkbd_t *) priv;
kbd->want_irq = 0;
kbd->blocked = 0;
kbd->pa = 0x00;
kbd->pb = 0x00;
kbd->pravetz_flags = 0x00;
keyboard_scan = 1;
key_queue_start = 0;
key_queue_end = 0;
}
void
keyboard_set_is_amstrad(int ams)
{
is_amstrad = ams;
}
static void *
kbd_init(const device_t *info)
{
xtkbd_t *kbd;
kbd = (xtkbd_t *) malloc(sizeof(xtkbd_t));
memset(kbd, 0x00, sizeof(xtkbd_t));
io_sethandler(0x0060, 4,
kbd_read, NULL, NULL, kbd_write, NULL, NULL, kbd);
keyboard_send = kbd_adddata_ex;
kbd_reset(kbd);
kbd->type = info->local;
if (kbd->type == KBD_TYPE_PRAVETZ) {
io_sethandler(0x00c0, 16,
kbd_read, NULL, NULL, kbd_write, NULL, NULL, kbd);
}
key_queue_start = key_queue_end = 0;
video_reset(gfxcard[0]);
if ((kbd->type == KBD_TYPE_PC81) || (kbd->type == KBD_TYPE_PC82) ||
(kbd->type == KBD_TYPE_PRAVETZ) || (kbd->type == KBD_TYPE_XT82) ||
(kbd->type <= KBD_TYPE_XT86) || (kbd->type == KBD_TYPE_XTCLONE) ||
(kbd->type == KBD_TYPE_COMPAQ) || (kbd->type == KBD_TYPE_TOSHIBA) ||
(kbd->type == KBD_TYPE_OLIVETTI) || (kbd->type == KBD_TYPE_HYUNDAI)) {
/* DIP switch readout: bit set = OFF, clear = ON. */
if (kbd->type == KBD_TYPE_OLIVETTI)
/* Olivetti M19
* Jumpers J1, J2 - monitor type.
* 01 - mono (high-res)
* 10 - color (low-res, disables 640x400x2 mode)
* 00 - autoswitching
*/
kbd->pd |= 0x00;
else
/* Switches 7, 8 - floppy drives. */
kbd->pd = get_fdd_switch_settings();
/* Siitches 5, 6 - video card type */
kbd->pd |= get_videomode_switch_settings();
/* Switches 3, 4 - memory size. */
if ((kbd->type == KBD_TYPE_XT86) || (kbd->type == KBD_TYPE_XTCLONE) ||
(kbd->type == KBD_TYPE_HYUNDAI) || (kbd->type == KBD_TYPE_COMPAQ) ||
(kbd->type == KBD_TYPE_TOSHIBA)) {
switch (mem_size) {
case 256:
kbd->pd |= 0x00;
break;
case 512:
kbd->pd |= 0x04;
break;
case 576:
kbd->pd |= 0x08;
break;
case 640:
default:
kbd->pd |= 0x0c;
break;
}
} else if (kbd->type == KBD_TYPE_XT82) {
switch (mem_size) {
case 64: /* 1x64k */
kbd->pd |= 0x00;
break;
case 128: /* 2x64k */
kbd->pd |= 0x04;
break;
case 192: /* 3x64k */
kbd->pd |= 0x08;
break;
case 256: /* 4x64k */
default:
kbd->pd |= 0x0c;
break;
}
} else if (kbd->type == KBD_TYPE_PC82) {
switch (mem_size) {
case 192: /* 3x64k, not supported by stock BIOS due to bugs */
kbd->pd |= 0x08;
break;
case 64: /* 4x16k */
case 96: /* 2x32k + 2x16k */
case 128: /* 4x32k */
case 160: /* 2x64k + 2x16k */
case 224: /* 3x64k + 1x32k */
case 256: /* 4x64k */
default:
kbd->pd |= 0x0c;
break;
}
} else { /* really just the PC '81 */
switch (mem_size) {
case 16: /* 1x16k */
kbd->pd |= 0x00;
break;
case 32: /* 2x16k */
kbd->pd |= 0x04;
break;
case 48: /* 3x16k */
kbd->pd |= 0x08;
break;
case 64: /* 4x16k */
default:
kbd->pd |= 0x0c;
break;
}
}
/* Switch 2 - 8087 FPU. */
if (hasfpu)
kbd->pd |= 0x02;
} else if (kbd->type == KBD_TYPE_ZENITH) {
/* Zenith Data Systems Z-151
* SW2 switch settings:
* bit 7: monitor frequency
* bits 5-6: autoboot (00-11 resident monitor, 10 hdd, 01 fdd)
* bits 0-4: installed memory
*/
kbd->pd = 0x20;
switch (mem_size) {
case 128:
kbd->pd |= 0x02;
break;
case 192:
kbd->pd |= 0x04;
break;
case 256:
kbd->pd |= 0x06;
break;
case 320:
kbd->pd |= 0x08;
break;
case 384:
kbd->pd |= 0x0a;
break;
case 448:
kbd->pd |= 0x0c;
break;
case 512:
kbd->pd |= 0x0e;
break;
case 576:
kbd->pd |= 0x10;
break;
case 640:
default:
kbd->pd |= 0x12;
break;
}
}
timer_add(&kbd->send_delay_timer, kbd_poll, kbd, 1);
keyboard_set_table(scancode_xt);
is_tandy = (kbd->type == KBD_TYPE_TANDY);
is_t1x00 = (kbd->type == KBD_TYPE_TOSHIBA);
is_amstrad = 0;
return kbd;
}
static void
kbd_close(void *priv)
{
xtkbd_t *kbd = (xtkbd_t *) priv;
/* Stop the timer. */
timer_disable(&kbd->send_delay_timer);
/* Disable scanning. */
keyboard_scan = 0;
keyboard_send = NULL;
io_removehandler(0x0060, 4,
kbd_read, NULL, NULL, kbd_write, NULL, NULL, kbd);
free(kbd);
}
const device_t keyboard_pc_device = {
.name = "IBM PC Keyboard (1981)",
.internal_name = "keyboard_pc",
.flags = 0,
.local = KBD_TYPE_PC81,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_pc82_device = {
.name = "IBM PC Keyboard (1982)",
.internal_name = "keyboard_pc82",
.flags = 0,
.local = KBD_TYPE_PC82,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_pravetz_device = {
.name = "Pravetz Keyboard",
.internal_name = "keyboard_pravetz",
.flags = 0,
.local = KBD_TYPE_PRAVETZ,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_xt_device = {
.name = "XT (1982) Keyboard",
.internal_name = "keyboard_xt",
.flags = 0,
.local = KBD_TYPE_XT82,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_xt86_device = {
.name = "XT (1986) Keyboard",
.internal_name = "keyboard_xt86",
.flags = 0,
.local = KBD_TYPE_XT86,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_xt_compaq_device = {
.name = "Compaq Portable Keyboard",
.internal_name = "keyboard_xt_compaq",
.flags = 0,
.local = KBD_TYPE_COMPAQ,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_tandy_device = {
.name = "Tandy 1000 Keyboard",
.internal_name = "keyboard_tandy",
.flags = 0,
.local = KBD_TYPE_TANDY,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_xt_t1x00_device = {
.name = "Toshiba T1x00 Keyboard",
.internal_name = "keyboard_xt_t1x00",
.flags = 0,
.local = KBD_TYPE_TOSHIBA,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
#ifdef USE_LASERXT
const device_t keyboard_xt_lxt3_device = {
.name = "VTech Laser XT3 Keyboard",
.internal_name = "keyboard_xt_lxt3",
.flags = 0,
.local = KBD_TYPE_VTECH,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
#endif /* USE_LASERXT */
const device_t keyboard_xt_olivetti_device = {
.name = "Olivetti XT Keyboard",
.internal_name = "keyboard_xt_olivetti",
.flags = 0,
.local = KBD_TYPE_OLIVETTI,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_xt_zenith_device = {
.name = "Zenith XT Keyboard",
.internal_name = "keyboard_xt_zenith",
.flags = 0,
.local = KBD_TYPE_ZENITH,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_xt_hyundai_device = {
.name = "Hyundai XT Keyboard",
.internal_name = "keyboard_x_hyundai",
.flags = 0,
.local = KBD_TYPE_HYUNDAI,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t keyboard_xtclone_device = {
.name = "XT (Clone) Keyboard",
.internal_name = "keyboard_xtclone",
.flags = 0,
.local = KBD_TYPE_XTCLONE,
.init = kbd_init,
.close = kbd_close,
.reset = kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/device/keyboard_xt.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 21,055 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the NatSemi PC87306 Super I/O chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#include <86box/machine.h>
typedef struct pc87306_t {
uint8_t tries;
uint8_t regs[29];
uint8_t gpio[2];
uint16_t gpioba;
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
nvr_t *nvr;
} pc87306_t;
static void
pc87306_gpio_write(uint16_t port, uint8_t val, void *priv)
{
pc87306_t *dev = (pc87306_t *) priv;
uint32_t gpio = 0xffff0000;
dev->gpio[port & 0x0001] = val;
if (port & 0x0001) {
gpio |= ((uint32_t) val) << 8;
gpio |= dev->gpio[0];
} else {
gpio |= ((uint32_t) dev->gpio[1]) << 8;
gpio |= val;
}
(void) machine_handle_gpio(1, gpio);
}
uint8_t
pc87306_gpio_read(uint16_t port, void *priv)
{
uint32_t ret = machine_handle_gpio(0, 0xffffffff);
if (port & 0x0001)
ret = (ret >> 8) & 0xff;
else
ret &= 0xff;
return ret;
}
static void
pc87306_gpio_remove(pc87306_t *dev)
{
if (dev->gpioba != 0x0000) {
io_removehandler(dev->gpioba, 0x0001,
pc87306_gpio_read, NULL, NULL, pc87306_gpio_write, NULL, NULL, dev);
io_removehandler(dev->gpioba + 1, 0x0001,
pc87306_gpio_read, NULL, NULL, pc87306_gpio_write, NULL, NULL, dev);
}
}
static void
pc87306_gpio_init(pc87306_t *dev)
{
dev->gpioba = ((uint16_t) dev->regs[0x0f]) << 2;
if (dev->gpioba != 0x0000) {
if ((dev->regs[0x12]) & 0x10)
io_sethandler(dev->gpioba, 0x0001,
pc87306_gpio_read, NULL, NULL, pc87306_gpio_write, NULL, NULL, dev);
if ((dev->regs[0x12]) & 0x20)
io_sethandler(dev->gpioba + 1, 0x0001,
pc87306_gpio_read, NULL, NULL, pc87306_gpio_write, NULL, NULL, dev);
}
}
static void
pc87306_gpio_handler(pc87306_t *dev)
{
pc87306_gpio_remove(dev);
pc87306_gpio_init(dev);
}
static void
lpt1_handler(pc87306_t *dev)
{
int temp;
uint16_t lptba;
uint16_t lpt_port = LPT1_ADDR;
uint8_t lpt_irq = LPT2_IRQ;
temp = dev->regs[0x01] & 3;
lptba = ((uint16_t) dev->regs[0x19]) << 2;
switch (temp) {
case 0:
lpt_port = LPT1_ADDR;
lpt_irq = (dev->regs[0x02] & 0x08) ? LPT1_IRQ : LPT2_IRQ;
break;
case 1:
if (dev->regs[0x1b] & 0x40)
lpt_port = lptba;
else
lpt_port = LPT_MDA_ADDR;
lpt_irq = LPT_MDA_IRQ;
break;
case 2:
lpt_port = LPT2_ADDR;
lpt_irq = LPT2_IRQ;
break;
case 3:
lpt_port = 0x000;
lpt_irq = 0xff;
break;
default:
break;
}
if (dev->regs[0x1b] & 0x10)
lpt_irq = (dev->regs[0x1b] & 0x20) ? 7 : 5;
if (lpt_port)
lpt1_init(lpt_port);
lpt1_irq(lpt_irq);
}
static void
serial_handler(pc87306_t *dev, int uart)
{
int temp;
uint8_t fer_irq;
uint8_t pnp1_irq;
uint8_t fer_shift;
uint8_t pnp_shift;
uint8_t irq;
temp = (dev->regs[1] >> (2 << uart)) & 3;
fer_shift = 2 << uart; /* 2 for UART 1, 4 for UART 2 */
pnp_shift = 2 + (uart << 2); /* 2 for UART 1, 6 for UART 2 */
/* 0 = COM1 (IRQ 4), 1 = COM2 (IRQ 3), 2 = COM3 (IRQ 4), 3 = COM4 (IRQ 3) */
fer_irq = ((dev->regs[1] >> fer_shift) & 1) ? 3 : 4;
pnp1_irq = ((dev->regs[0x1c] >> pnp_shift) & 1) ? 4 : 3;
irq = (dev->regs[0x1c] & 1) ? pnp1_irq : fer_irq;
switch (temp) {
case 0:
serial_setup(dev->uart[uart], COM1_ADDR, irq);
break;
case 1:
serial_setup(dev->uart[uart], COM2_ADDR, irq);
break;
case 2:
switch ((dev->regs[1] >> 6) & 3) {
case 0:
serial_setup(dev->uart[uart], COM3_ADDR, irq);
break;
case 1:
serial_setup(dev->uart[uart], 0x338, irq);
break;
case 2:
serial_setup(dev->uart[uart], COM4_ADDR, irq);
break;
case 3:
serial_setup(dev->uart[uart], 0x220, irq);
break;
default:
break;
}
break;
case 3:
switch ((dev->regs[1] >> 6) & 3) {
case 0:
serial_setup(dev->uart[uart], COM4_ADDR, irq);
break;
case 1:
serial_setup(dev->uart[uart], 0x238, irq);
break;
case 2:
serial_setup(dev->uart[uart], 0x2e0, irq);
break;
case 3:
serial_setup(dev->uart[uart], 0x228, irq);
break;
default:
break;
}
break;
default:
break;
}
}
static void
pc87306_write(uint16_t port, uint8_t val, void *priv)
{
pc87306_t *dev = (pc87306_t *) priv;
uint8_t index;
uint8_t valxor;
index = (port & 1) ? 0 : 1;
if (index) {
dev->cur_reg = val & 0x1f;
dev->tries = 0;
return;
} else {
if (dev->tries) {
if ((dev->cur_reg == 0) && (val == 8))
val = 0x4b;
valxor = val ^ dev->regs[dev->cur_reg];
dev->tries = 0;
if ((dev->cur_reg <= 28) && (dev->cur_reg != 8)) {
if (dev->cur_reg == 0)
val &= 0x5f;
dev->regs[dev->cur_reg] = val;
} else
return;
} else {
dev->tries++;
return;
}
}
switch (dev->cur_reg) {
case 0x00:
if (valxor & 1) {
lpt1_remove();
if ((val & 1) && !(dev->regs[2] & 1))
lpt1_handler(dev);
}
if (valxor & 2) {
serial_remove(dev->uart[0]);
if ((val & 2) && !(dev->regs[2] & 1))
serial_handler(dev, 0);
}
if (valxor & 4) {
serial_remove(dev->uart[1]);
if ((val & 4) && !(dev->regs[2] & 1))
serial_handler(dev, 1);
}
if (valxor & 0x28) {
fdc_remove(dev->fdc);
if ((val & 8) && !(dev->regs[2] & 1))
fdc_set_base(dev->fdc, (val & 0x20) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
}
break;
case 0x01:
if (valxor & 3) {
lpt1_remove();
if ((dev->regs[0] & 1) && !(dev->regs[2] & 1))
lpt1_handler(dev);
}
if (valxor & 0xcc) {
serial_remove(dev->uart[0]);
if ((dev->regs[0] & 2) && !(dev->regs[2] & 1))
serial_handler(dev, 0);
}
if (valxor & 0xf0) {
serial_remove(dev->uart[1]);
if ((dev->regs[0] & 4) && !(dev->regs[2] & 1))
serial_handler(dev, 1);
}
break;
case 0x02:
if (valxor & 1) {
lpt1_remove();
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
fdc_remove(dev->fdc);
if (!(val & 1)) {
if (dev->regs[0] & 1)
lpt1_handler(dev);
if (dev->regs[0] & 2)
serial_handler(dev, 0);
if (dev->regs[0] & 4)
serial_handler(dev, 1);
if (dev->regs[0] & 8)
fdc_set_base(dev->fdc, (dev->regs[0] & 0x20) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
}
}
if (valxor & 8) {
lpt1_remove();
if ((dev->regs[0] & 1) && !(dev->regs[2] & 1))
lpt1_handler(dev);
}
break;
case 0x04:
if (valxor & 0x80)
nvr_lock_set(0x00, 256, !!(val & 0x80), dev->nvr);
break;
case 0x05:
if (valxor & 0x08)
nvr_at_handler(!!(val & 0x08), 0x0070, dev->nvr);
if (valxor & 0x20)
nvr_bank_set(0, !!(val & 0x20), dev->nvr);
break;
case 0x09:
if (valxor & 0x44) {
fdc_update_enh_mode(dev->fdc, (val & 4) ? 1 : 0);
fdc_update_densel_polarity(dev->fdc, (val & 0x40) ? 1 : 0);
}
break;
case 0x0f:
if (valxor)
pc87306_gpio_handler(dev);
break;
case 0x12:
if (valxor & 0x01)
nvr_wp_set(!!(val & 0x01), 0, dev->nvr);
if (valxor & 0x30)
pc87306_gpio_handler(dev);
break;
case 0x19:
if (valxor) {
lpt1_remove();
if ((dev->regs[0] & 1) && !(dev->regs[2] & 1))
lpt1_handler(dev);
}
break;
case 0x1B:
if (valxor & 0x70) {
lpt1_remove();
if (!(val & 0x40))
dev->regs[0x19] = 0xEF;
if ((dev->regs[0] & 1) && !(dev->regs[2] & 1))
lpt1_handler(dev);
}
break;
case 0x1C:
if (valxor) {
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
if ((dev->regs[0] & 2) && !(dev->regs[2] & 1))
serial_handler(dev, 0);
if ((dev->regs[0] & 4) && !(dev->regs[2] & 1))
serial_handler(dev, 1);
}
break;
default:
break;
}
}
uint8_t
pc87306_read(uint16_t port, void *priv)
{
pc87306_t *dev = (pc87306_t *) priv;
uint8_t ret = 0xff;
uint8_t index;
index = (port & 1) ? 0 : 1;
dev->tries = 0;
if (index)
ret = dev->cur_reg & 0x1f;
else {
if (dev->cur_reg == 8)
ret = 0x70;
else if (dev->cur_reg < 28)
ret = dev->regs[dev->cur_reg];
}
return ret;
}
void
pc87306_reset_common(void *priv)
{
pc87306_t *dev = (pc87306_t *) priv;
memset(dev->regs, 0, 29);
dev->regs[0x00] = 0x0B;
dev->regs[0x01] = 0x01;
dev->regs[0x03] = 0x01;
dev->regs[0x05] = 0x0D;
dev->regs[0x08] = 0x70;
dev->regs[0x09] = 0xC0;
dev->regs[0x0b] = 0x80;
dev->regs[0x0f] = 0x1E;
dev->regs[0x12] = 0x30;
dev->regs[0x19] = 0xEF;
/*
0 = 360 rpm @ 500 kbps for 3.5"
1 = Default, 300 rpm @ 500, 300, 250, 1000 kbps for 3.5"
*/
lpt1_remove();
lpt1_handler(dev);
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
serial_handler(dev, 0);
serial_handler(dev, 1);
fdc_reset(dev->fdc);
pc87306_gpio_init(dev);
nvr_lock_set(0x00, 256, 0, dev->nvr);
nvr_at_handler(0, 0x0070, dev->nvr);
nvr_at_handler(1, 0x0070, dev->nvr);
nvr_bank_set(0, 0, dev->nvr);
nvr_wp_set(0, 0, dev->nvr);
}
void
pc87306_reset(void *priv)
{
pc87306_t *dev = (pc87306_t *) priv;
pc87306_gpio_write(0x0000, 0xff, dev);
pc87306_gpio_write(0x0001, 0xff, dev);
pc87306_reset_common(dev);
}
static void
pc87306_close(void *priv)
{
pc87306_t *dev = (pc87306_t *) priv;
free(dev);
}
static void *
pc87306_init(UNUSED(const device_t *info))
{
pc87306_t *dev = (pc87306_t *) malloc(sizeof(pc87306_t));
memset(dev, 0, sizeof(pc87306_t));
dev->fdc = device_add(&fdc_at_nsc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->nvr = device_add(&at_mb_nvr_device);
dev->gpio[0] = dev->gpio[1] = 0xff;
pc87306_reset_common(dev);
io_sethandler(0x02e, 0x0002,
pc87306_read, NULL, NULL, pc87306_write, NULL, NULL, dev);
return dev;
}
const device_t pc87306_device = {
.name = "National Semiconductor PC87306 Super I/O",
.internal_name = "pc87306",
.flags = 0,
.local = 0,
.init = pc87306_init,
.close = pc87306_close,
.reset = pc87306_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_pc87306.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,192 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the UMC UMF8663F Super I/O chip.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pci.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/gameport.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/sio.h>
#include <86box/random.h>
#include <86box/plat_unused.h>
#ifdef ENABLE_UM8663F_LOG
int um8663f_do_log = ENABLE_UM8663F_LOG;
static void
um8663f_log(const char *fmt, ...)
{
va_list ap;
if (um8663f_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define um8663f_log(fmt, ...)
#endif
typedef struct um8663f_t {
uint8_t max_reg;
uint8_t ide;
uint8_t locked;
uint8_t cur_reg;
uint8_t regs[5];
fdc_t *fdc;
serial_t *uart[2];
} um8663f_t;
static void
um8663f_fdc_handler(um8663f_t *dev)
{
fdc_remove(dev->fdc);
if (dev->regs[0] & 0x01)
fdc_set_base(dev->fdc, (dev->regs[1] & 0x01) ? FDC_PRIMARY_ADDR : FDC_SECONDARY_ADDR);
}
static void
um8663f_uart_handler(um8663f_t *dev, int port)
{
uint8_t shift = (port + 1);
serial_remove(dev->uart[port]);
if (dev->regs[0] & (2 << port)) {
switch ((dev->regs[1] >> shift) & 0x01) {
case 0x00:
if (port == 1)
serial_setup(dev->uart[port], COM4_ADDR, COM4_IRQ);
else
serial_setup(dev->uart[port], COM3_ADDR, COM1_IRQ);
break;
case 0x01:
if (port == 1)
serial_setup(dev->uart[port], COM2_ADDR, COM2_IRQ);
else
serial_setup(dev->uart[port], COM1_ADDR, COM1_IRQ);
break;
default:
break;
}
}
}
static void
um8663f_lpt_handler(um8663f_t *dev)
{
lpt1_remove();
if (dev->regs[0] & 0x08) {
switch ((dev->regs[1] >> 3) & 0x01) {
case 0x01:
lpt1_init(LPT1_ADDR);
lpt1_irq(7);
break;
case 0x00:
lpt1_init(LPT2_ADDR);
lpt1_irq(5);
break;
default:
break;
}
}
}
static void
um8663f_ide_handler(um8663f_t *dev)
{
int board = dev->ide - 1;
if (dev->ide > 0) {
ide_handlers(board, 0);
ide_set_base(board, (dev->regs[1] & 0x10) ? 0x01f0 : 0x0170);
ide_set_side(board, (dev->regs[1] & 0x10) ? 0x03f6 : 0x0376);
if (dev->regs[0] & 0x10)
ide_handlers(board, 1);
}
}
static void
um8663f_write(uint16_t port, uint8_t val, void *priv)
{
um8663f_t *dev = (um8663f_t *) priv;
uint8_t valxor;
um8663f_log("UM8663F: write(%04X, %02X)\n", port, val);
if (dev->locked) {
if ((port == 0x108) && (val == 0xaa))
dev->locked = 0;
} else {
if (port == 0x108) {
if (val == 0x55)
dev->locked = 1;
else
dev->cur_reg = val;
} else if ((dev->cur_reg >= 0xc0) && (dev->cur_reg <= dev->max_reg)) {
valxor = (dev->regs[dev->cur_reg - 0xc0] ^ val);
dev->regs[dev->cur_reg - 0xc0] = val;
switch (dev->cur_reg - 0xc0) {
/* Port enable register. */
case 0x00:
if (valxor & 0x10)
um8663f_ide_handler(dev);
if (valxor & 0x08)
um8663f_lpt_handler(dev);
if (valxor & 0x04)
um8663f_uart_handler(dev, 1);
if (valxor & 0x02)
um8663f_uart_handler(dev, 0);
if (valxor & 0x01)
um8663f_fdc_handler(dev);
break;
/*
Port configuration register:
- Bits 7, 6:
- 0, 0 = LPT 1 is none;
- 0, 1 = LPT 1 is EPP;
- 1, 0 = LPT 1 is SPP;
- 1, 1 = LPT 1 is ECP;
- Bit 4 = 0 = IDE is secondary, 1 = IDE is primary;
- Bit 3 = 0 = LPT 1 is 278h, 1 = LPT 1 is 378h;
- Bit 2 = 0 = UART 2 is COM4, 1 = UART 2 is COM2;
- Bit 1 = 0 = UART 1 is COM3, 1 = UART 2 is COM1;
- Bit 0 = 0 = FDC is 370h, 1 = UART 2 is 3f0h.
*/
case 0x01:
if (valxor & 0x10)
um8663f_ide_handler(dev);
if (valxor & 0x08)
um8663f_lpt_handler(dev);
if (valxor & 0x04)
um8663f_uart_handler(dev, 1);
if (valxor & 0x02)
um8663f_uart_handler(dev, 0);
if (valxor & 0x01)
um8663f_fdc_handler(dev);
break;
}
}
}
}
static uint8_t
um8663f_read(uint16_t port, void *priv)
{
const um8663f_t *dev = (um8663f_t *) priv;
uint8_t ret = 0xff;
if (!dev->locked) {
if (port == 0x108)
ret = dev->cur_reg; /* ??? */
else if ((dev->cur_reg >= 0xc0) && (dev->cur_reg <= dev->max_reg)) {
ret = dev->regs[dev->cur_reg - 0xc0];
if (dev->cur_reg == 0xc0)
ret = (ret & 0x1f) | ((random_generate() & 0x07) << 5);
}
}
um8663f_log("UM8663F: read(%04X) = %02X\n", port, ret);
return ret;
}
static void
um8663f_reset(void *priv)
{
um8663f_t *dev = (um8663f_t *) priv;
serial_remove(dev->uart[0]);
serial_setup(dev->uart[0], COM1_ADDR, COM1_IRQ);
serial_remove(dev->uart[1]);
serial_setup(dev->uart[1], COM2_ADDR, COM2_IRQ);
lpt1_remove();
lpt1_init(LPT1_ADDR);
fdc_reset(dev->fdc);
fdc_remove(dev->fdc);
memset(dev->regs, 0x00, sizeof(dev->regs));
dev->regs[0x00] = (dev->ide > 0) ? 0x1f : 0x0f;
dev->regs[0x01] = (dev->ide == 2) ? 0x0f : 0x1f;
um8663f_fdc_handler(dev);
um8663f_uart_handler(dev, 0);
um8663f_uart_handler(dev, 1);
um8663f_lpt_handler(dev);
um8663f_ide_handler(dev);
dev->locked = 1;
}
static void
um8663f_close(void *priv)
{
um8663f_t *dev = (um8663f_t *) priv;
free(dev);
}
static void *
um8663f_init(UNUSED(const device_t *info))
{
um8663f_t *dev = (um8663f_t *) calloc(1, sizeof(um8663f_t));
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->ide = info->local & 0xff;
if (dev->ide < IDE_BUS_MAX)
device_add(&ide_isa_device);
dev->max_reg = info->local >> 8;
io_sethandler(0x0108, 0x0002, um8663f_read, NULL, NULL, um8663f_write, NULL, NULL, dev);
um8663f_reset(dev);
return dev;
}
const device_t um8663af_device = {
.name = "UMC UM8663AF Super I/O",
.internal_name = "um8663af",
.flags = 0,
.local = 0xc300,
.init = um8663f_init,
.close = um8663f_close,
.reset = um8663f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t um8663af_ide_device = {
.name = "UMC UM8663AF Super I/O (With IDE)",
.internal_name = "um8663af_ide",
.flags = 0,
.local = 0xc301,
.init = um8663f_init,
.close = um8663f_close,
.reset = um8663f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t um8663af_ide_sec_device = {
.name = "UMC UM8663AF Super I/O (With Secondary IDE)",
.internal_name = "um8663af_ide_sec",
.flags = 0,
.local = 0xc302,
.init = um8663f_init,
.close = um8663f_close,
.reset = um8663f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t um8663bf_device = {
.name = "UMC UM8663BF Super I/O",
.internal_name = "um8663bf",
.flags = 0,
.local = 0xc400,
.init = um8663f_init,
.close = um8663f_close,
.reset = um8663f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t um8663bf_ide_device = {
.name = "UMC UM8663BF Super I/O (With IDE)",
.internal_name = "um8663bf_ide",
.flags = 0,
.local = 0xc401,
.init = um8663f_init,
.close = um8663f_close,
.reset = um8663f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t um8663bf_ide_sec_device = {
.name = "UMC UM8663BF Super I/O (With Secondary IDE)",
.internal_name = "um8663bf_ide_sec",
.flags = 0,
.local = 0xc402,
.init = um8663f_init,
.close = um8663f_close,
.reset = um8663f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_um8663f.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,101 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Winbond W83977F Super I/O Chip.
*
* Winbond W83977F Super I/O Chip
* Used by the Award 430TX
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pci.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#define HEFRAS (dev->regs[0x26] & 0x40)
typedef struct w83977f_t {
uint8_t id;
uint8_t tries;
uint8_t regs[48];
uint8_t dev_regs[256][208];
int locked;
int rw_locked;
int cur_reg;
int base_address;
int type;
int hefras;
fdc_t *fdc;
serial_t *uart[2];
} w83977f_t;
static int next_id = 0;
static void w83977f_write(uint16_t port, uint8_t val, void *priv);
static uint8_t w83977f_read(uint16_t port, void *priv);
static void
w83977f_remap(w83977f_t *dev)
{
io_removehandler(FDC_PRIMARY_ADDR, 0x0002,
w83977f_read, NULL, NULL, w83977f_write, NULL, NULL, dev);
io_removehandler(FDC_SECONDARY_ADDR, 0x0002,
w83977f_read, NULL, NULL, w83977f_write, NULL, NULL, dev);
dev->base_address = (HEFRAS ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
io_sethandler(dev->base_address, 0x0002,
w83977f_read, NULL, NULL, w83977f_write, NULL, NULL, dev);
}
static uint8_t
get_lpt_length(w83977f_t *dev)
{
uint8_t length = 4;
if (((dev->dev_regs[1][0xc0] & 0x07) != 0x00) && ((dev->dev_regs[1][0xc0] & 0x07) != 0x02) && ((dev->dev_regs[1][0xc0] & 0x07) != 0x04))
length = 8;
return length;
}
static void
w83977f_fdc_handler(w83977f_t *dev)
{
uint16_t io_base = (dev->dev_regs[0][0x30] << 8) | dev->dev_regs[0][0x31];
if (dev->id == 1)
return;
fdc_remove(dev->fdc);
if ((dev->dev_regs[0][0x00] & 0x01) && (dev->regs[0x22] & 0x01) && (io_base >= 0x100) && (io_base <= 0xff8))
fdc_set_base(dev->fdc, io_base);
fdc_set_irq(dev->fdc, dev->dev_regs[0][0x40] & 0x0f);
}
static void
w83977f_lpt_handler(w83977f_t *dev)
{
uint16_t io_mask;
uint16_t io_base = (dev->dev_regs[1][0x30] << 8) | dev->dev_regs[1][0x31];
int io_len = get_lpt_length(dev);
io_base &= (0xff8 | io_len);
io_mask = 0xffc;
if (io_len == 8)
io_mask = 0xff8;
if (dev->id == 1) {
lpt2_remove();
if ((dev->dev_regs[1][0x00] & 0x01) && (dev->regs[0x22] & 0x08) && (io_base >= 0x100) && (io_base <= io_mask))
lpt2_init(io_base);
lpt2_irq(dev->dev_regs[1][0x40] & 0x0f);
} else {
lpt1_remove();
if ((dev->dev_regs[1][0x00] & 0x01) && (dev->regs[0x22] & 0x08) && (io_base >= 0x100) && (io_base <= io_mask))
lpt1_init(io_base);
lpt1_irq(dev->dev_regs[1][0x40] & 0x0f);
}
}
static void
w83977f_serial_handler(w83977f_t *dev, int uart)
{
uint16_t io_base = (dev->dev_regs[2 + uart][0x30] << 8) | dev->dev_regs[2 + uart][0x31];
double clock_src = 24000000.0 / 13.0;
serial_remove(dev->uart[uart]);
if ((dev->dev_regs[2 + uart][0x00] & 0x01) && (dev->regs[0x22] & (0x10 << uart)) && (io_base >= 0x100) && (io_base <= 0xff8))
serial_setup(dev->uart[uart], io_base, dev->dev_regs[2 + uart][0x40] & 0x0f);
switch (dev->dev_regs[2 + uart][0xc0] & 0x03) {
case 0x00:
clock_src = 24000000.0 / 13.0;
break;
case 0x01:
clock_src = 24000000.0 / 12.0;
break;
case 0x02:
clock_src = 24000000.0 / 1.0;
break;
case 0x03:
clock_src = 24000000.0 / 1.625;
break;
default:
break;
}
serial_set_clock_src(dev->uart[uart], clock_src);
}
static void
w83977f_write(uint16_t port, uint8_t val, void *priv)
{
w83977f_t *dev = (w83977f_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t valxor = 0;
uint8_t ld = dev->regs[7];
if (index) {
if ((val == 0x87) && !dev->locked) {
if (dev->tries) {
dev->locked = 1;
dev->tries = 0;
} else
dev->tries++;
} else {
if (dev->locked) {
if (val == 0xaa)
dev->locked = 0;
else
dev->cur_reg = val;
} else {
if (dev->tries)
dev->tries = 0;
}
}
return;
} else {
if (dev->locked) {
if (dev->rw_locked)
return;
if (dev->cur_reg >= 0x30) {
valxor = val ^ dev->dev_regs[ld][dev->cur_reg - 0x30];
dev->dev_regs[ld][dev->cur_reg - 0x30] = val;
} else {
valxor = val ^ dev->regs[dev->cur_reg];
dev->regs[dev->cur_reg] = val;
}
} else
return;
}
switch (dev->cur_reg) {
case 0x02:
#if 0
if (valxor & 0x02)
softresetx86();
#endif
break;
case 0x22:
if (valxor & 0x20)
w83977f_serial_handler(dev, 1);
if (valxor & 0x10)
w83977f_serial_handler(dev, 0);
if (valxor & 0x08)
w83977f_lpt_handler(dev);
if (valxor & 0x01)
w83977f_fdc_handler(dev);
break;
case 0x26:
if (valxor & 0x40)
w83977f_remap(dev);
if (valxor & 0x20)
dev->rw_locked = (val & 0x20) ? 1 : 0;
break;
case 0x30:
if (valxor & 0x01)
switch (ld) {
case 0x00:
w83977f_fdc_handler(dev);
break;
case 0x01:
w83977f_lpt_handler(dev);
break;
case 0x02:
case 0x03:
w83977f_serial_handler(dev, ld - 2);
break;
default:
break;
}
break;
case 0x60:
case 0x61:
if (valxor & 0xff)
switch (ld) {
case 0x00:
w83977f_fdc_handler(dev);
break;
case 0x01:
w83977f_lpt_handler(dev);
break;
case 0x02:
case 0x03:
w83977f_serial_handler(dev, ld - 2);
break;
default:
break;
}
break;
case 0x70:
if (valxor & 0x0f)
switch (ld) {
case 0x00:
w83977f_fdc_handler(dev);
break;
case 0x01:
w83977f_lpt_handler(dev);
break;
case 0x02:
case 0x03:
w83977f_serial_handler(dev, ld - 2);
break;
default:
break;
}
break;
case 0xf0:
switch (ld) {
case 0x00:
if (dev->id == 1)
break;
if (!dev->id && (valxor & 0x20))
fdc_update_drv2en(dev->fdc, (val & 0x20) ? 0 : 1);
if (!dev->id && (valxor & 0x10))
fdc_set_swap(dev->fdc, (val & 0x10) ? 1 : 0);
if (!dev->id && (valxor & 0x01))
fdc_update_enh_mode(dev->fdc, (val & 0x01) ? 1 : 0);
break;
case 0x01:
if (valxor & 0x07)
w83977f_lpt_handler(dev);
break;
case 0x02:
case 0x03:
if (valxor & 0x03)
w83977f_serial_handler(dev, ld - 2);
break;
default:
break;
}
break;
case 0xf1:
switch (ld) {
case 0x00:
if (dev->id == 1)
break;
if (!dev->id && (valxor & 0xc0))
fdc_update_boot_drive(dev->fdc, (val & 0xc0) >> 6);
if (!dev->id && (valxor & 0x0c))
fdc_update_densel_force(dev->fdc, (val & 0x0c) >> 2);
if (!dev->id && (valxor & 0x02))
fdc_set_diswr(dev->fdc, (val & 0x02) ? 1 : 0);
if (!dev->id && (valxor & 0x01))
fdc_set_swwp(dev->fdc, (val & 0x01) ? 1 : 0);
break;
default:
break;
}
break;
case 0xf2:
switch (ld) {
case 0x00:
if (dev->id == 1)
break;
if (!dev->id && (valxor & 0xc0))
fdc_update_rwc(dev->fdc, 3, (val & 0xc0) >> 6);
if (!dev->id && (valxor & 0x30))
fdc_update_rwc(dev->fdc, 2, (val & 0x30) >> 4);
if (!dev->id && (valxor & 0x0c))
fdc_update_rwc(dev->fdc, 1, (val & 0x0c) >> 2);
if (!dev->id && (valxor & 0x03))
fdc_update_rwc(dev->fdc, 0, val & 0x03);
break;
default:
break;
}
break;
case 0xf4:
case 0xf5:
case 0xf6:
case 0xf7:
switch (ld) {
case 0x00:
if (dev->id == 1)
break;
if (!dev->id && (valxor & 0x18))
fdc_update_drvrate(dev->fdc, dev->cur_reg & 0x03, (val & 0x18) >> 3);
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
w83977f_read(uint16_t port, void *priv)
{
w83977f_t *dev = (w83977f_t *) priv;
uint8_t ret = 0xff;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t ld = dev->regs[7];
if (dev->locked) {
if (index)
ret = dev->cur_reg;
else {
if (!dev->rw_locked) {
if (!dev->id && ((dev->cur_reg == 0xf2) && (ld == 0x00)))
ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) | (fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6));
else if (dev->cur_reg >= 0x30)
ret = dev->dev_regs[ld][dev->cur_reg - 0x30];
else
ret = dev->regs[dev->cur_reg];
}
}
}
return ret;
}
static void
w83977f_reset(w83977f_t *dev)
{
memset(dev->regs, 0, 48);
for (uint16_t i = 0; i < 256; i++)
memset(dev->dev_regs[i], 0, 208);
if (dev->type < 2) {
dev->regs[0x20] = 0x97;
dev->regs[0x21] = dev->type ? 0x73 : 0x71;
} else {
dev->regs[0x20] = 0x52;
dev->regs[0x21] = 0xf0;
}
dev->regs[0x22] = 0xff;
dev->regs[0x24] = dev->type ? 0x84 : 0xa4;
dev->regs[0x26] = dev->hefras;
/* WARNING: Array elements are register - 0x30. */
/* Logical Device 0 (FDC) */
dev->dev_regs[0][0x00] = 0x01;
if (!dev->type)
dev->dev_regs[0][0x01] = 0x02;
if (next_id == 1) {
dev->dev_regs[0][0x30] = 0x03;
dev->dev_regs[0][0x31] = 0x70;
} else {
dev->dev_regs[0][0x30] = 0x03;
dev->dev_regs[0][0x31] = 0xf0;
}
dev->dev_regs[0][0x40] = 0x06;
if (!dev->type)
dev->dev_regs[0][0x41] = 0x02; /* Read-only */
dev->dev_regs[0][0x44] = 0x02;
dev->dev_regs[0][0xc0] = 0x0e;
/* Logical Device 1 (Parallel Port) */
dev->dev_regs[1][0x00] = 0x01;
if (!dev->type)
dev->dev_regs[1][0x01] = 0x02;
if (next_id == 1) {
dev->dev_regs[1][0x30] = 0x02;
dev->dev_regs[1][0x31] = 0x78;
dev->dev_regs[1][0x40] = 0x05;
} else {
dev->dev_regs[1][0x30] = 0x03;
dev->dev_regs[1][0x31] = 0x78;
dev->dev_regs[1][0x40] = 0x07;
}
if (!dev->type)
dev->dev_regs[1][0x41] = 0x01 /*0x02*/; /* Read-only */
dev->dev_regs[1][0x44] = 0x04;
dev->dev_regs[1][0xc0] = 0x3c; /* The datasheet says default is 3f, but also default is printer mode. */
/* Logical Device 2 (UART A) */
dev->dev_regs[2][0x00] = 0x01;
if (!dev->type)
dev->dev_regs[2][0x01] = 0x02;
if (next_id == 1) {
dev->dev_regs[2][0x30] = 0x03;
dev->dev_regs[2][0x31] = 0xe8;
} else {
dev->dev_regs[2][0x30] = 0x03;
dev->dev_regs[2][0x31] = 0xf8;
}
dev->dev_regs[2][0x40] = 0x04;
if (!dev->type)
dev->dev_regs[2][0x41] = 0x02; /* Read-only */
/* Logical Device 3 (UART B) */
dev->dev_regs[3][0x00] = 0x01;
if (!dev->type)
dev->dev_regs[3][0x01] = 0x02;
if (next_id == 1) {
dev->dev_regs[3][0x30] = 0x02;
dev->dev_regs[3][0x31] = 0xe8;
} else {
dev->dev_regs[3][0x30] = 0x02;
dev->dev_regs[3][0x31] = 0xf8;
}
dev->dev_regs[3][0x40] = 0x03;
if (!dev->type)
dev->dev_regs[3][0x41] = 0x02; /* Read-only */
/* Logical Device 4 (RTC) */
if (!dev->type) {
dev->dev_regs[4][0x00] = 0x01;
dev->dev_regs[4][0x01] = 0x02;
dev->dev_regs[4][0x30] = 0x00;
dev->dev_regs[4][0x31] = 0x70;
dev->dev_regs[4][0x40] = 0x08;
dev->dev_regs[4][0x41] = 0x02; /* Read-only */
}
/* Logical Device 5 (KBC) */
dev->dev_regs[5][0x00] = 0x01;
if (!dev->type)
dev->dev_regs[5][0x01] = 0x02;
dev->dev_regs[5][0x30] = 0x00;
dev->dev_regs[5][0x31] = 0x60;
dev->dev_regs[5][0x32] = 0x00;
dev->dev_regs[5][0x33] = 0x64;
dev->dev_regs[5][0x40] = 0x01;
if (!dev->type)
dev->dev_regs[5][0x41] = 0x02; /* Read-only */
dev->dev_regs[5][0x42] = 0x0c;
if (!dev->type)
dev->dev_regs[5][0x43] = 0x02; /* Read-only? */
dev->dev_regs[5][0xc0] = dev->type ? 0x83 : 0x40;
/* Logical Device 6 (IR) = UART C */
if (!dev->type) {
dev->dev_regs[6][0x01] = 0x02;
dev->dev_regs[6][0x41] = 0x02; /* Read-only */
dev->dev_regs[6][0x44] = 0x04;
dev->dev_regs[6][0x45] = 0x04;
}
/* Logical Device 7 (Auxiliary I/O Part I) */
if (!dev->type)
dev->dev_regs[7][0x01] = 0x02;
if (!dev->type)
dev->dev_regs[7][0x41] = 0x02; /* Read-only */
if (!dev->type)
dev->dev_regs[7][0x43] = 0x02; /* Read-only? */
dev->dev_regs[7][0xb0] = 0x01;
dev->dev_regs[7][0xb1] = 0x01;
dev->dev_regs[7][0xb2] = 0x01;
dev->dev_regs[7][0xb3] = 0x01;
dev->dev_regs[7][0xb4] = 0x01;
dev->dev_regs[7][0xb5] = 0x01;
dev->dev_regs[7][0xb6] = 0x01;
if (dev->type)
dev->dev_regs[7][0xb7] = 0x01;
/* Logical Device 8 (Auxiliary I/O Part II) */
if (!dev->type)
dev->dev_regs[8][0x01] = 0x02;
if (!dev->type)
dev->dev_regs[8][0x41] = 0x02; /* Read-only */
if (!dev->type)
dev->dev_regs[8][0x43] = 0x02; /* Read-only? */
dev->dev_regs[8][0xb8] = 0x01;
dev->dev_regs[8][0xb9] = 0x01;
dev->dev_regs[8][0xba] = 0x01;
dev->dev_regs[8][0xbb] = 0x01;
dev->dev_regs[8][0xbc] = 0x01;
dev->dev_regs[8][0xbd] = 0x01;
dev->dev_regs[8][0xbe] = 0x01;
dev->dev_regs[8][0xbf] = 0x01;
/* Logical Device 9 (Auxiliary I/O Part III) */
if (dev->type) {
dev->dev_regs[9][0xb0] = 0x01;
dev->dev_regs[9][0xb1] = 0x01;
dev->dev_regs[9][0xb2] = 0x01;
dev->dev_regs[9][0xb3] = 0x01;
dev->dev_regs[9][0xb4] = 0x01;
dev->dev_regs[9][0xb5] = 0x01;
dev->dev_regs[9][0xb6] = 0x01;
dev->dev_regs[9][0xb7] = 0x01;
dev->dev_regs[10][0xc0] = 0x8f;
}
if (dev->id == 1) {
serial_setup(dev->uart[0], COM3_ADDR, COM3_IRQ);
serial_setup(dev->uart[1], COM4_ADDR, COM4_IRQ);
} else {
fdc_reset(dev->fdc);
serial_setup(dev->uart[0], COM1_ADDR, COM1_IRQ);
serial_setup(dev->uart[1], COM2_ADDR, COM2_IRQ);
w83977f_fdc_handler(dev);
}
w83977f_lpt_handler(dev);
w83977f_serial_handler(dev, 0);
w83977f_serial_handler(dev, 1);
w83977f_remap(dev);
dev->locked = 0;
dev->rw_locked = 0;
}
static void
w83977f_close(void *priv)
{
w83977f_t *dev = (w83977f_t *) priv;
next_id = 0;
free(dev);
}
static void *
w83977f_init(const device_t *info)
{
w83977f_t *dev = (w83977f_t *) malloc(sizeof(w83977f_t));
memset(dev, 0, sizeof(w83977f_t));
dev->type = info->local & 0x0f;
dev->hefras = info->local & 0x40;
dev->id = next_id;
if (next_id == 1)
dev->hefras ^= 0x40;
else
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, (next_id << 1) + 1);
dev->uart[1] = device_add_inst(&ns16550_device, (next_id << 1) + 2);
w83977f_reset(dev);
next_id++;
return dev;
}
const device_t w83977f_device = {
.name = "Winbond W83977F Super I/O",
.internal_name = "w83977f",
.flags = 0,
.local = 0,
.init = w83977f_init,
.close = w83977f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t w83977f_370_device = {
.name = "Winbond W83977F Super I/O (Port 370h)",
.internal_name = "w83977f_370",
.flags = 0,
.local = 0x40,
.init = w83977f_init,
.close = w83977f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t w83977tf_device = {
.name = "Winbond W83977TF Super I/O",
.internal_name = "w83977tf",
.flags = 0,
.local = 1,
.init = w83977f_init,
.close = w83977f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t w83977ef_device = {
.name = "Winbond W83977TF Super I/O",
.internal_name = "w83977ef",
.flags = 0,
.local = 2,
.init = w83977f_init,
.close = w83977f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t w83977ef_370_device = {
.name = "Winbond W83977TF Super I/O (Port 370h)",
.internal_name = "w83977ef_370",
.flags = 0,
.local = 0x42,
.init = w83977f_init,
.close = w83977f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_w83977f.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,667 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the VLSI VL82c113 Combination I/O Chip.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/nvr.h>
#include <86box/sio.h>
typedef struct vl82c113_t {
uint8_t index;
uint8_t nvr_enabled;
uint8_t regs[3];
uint8_t pad;
uint16_t nvr_base;
int cur_reg;
nvr_t *nvr;
void *kbc;
} vl82c113_t;
static void
vl82c113_nvr_handler(vl82c113_t *dev)
{
const uint8_t nvr_enabled = (dev->regs[0x00]) & 0x01;
const uint16_t nvr_base = ((dev->regs[0x01] << 8) | dev->regs[0x00]) & 0xfffe;
if ((nvr_enabled != dev->nvr_enabled) || (nvr_base != dev->nvr_base)) {
if (dev->nvr_enabled && (dev->nvr_base != 0x0000))
nvr_at_handler(0, dev->nvr_base, dev->nvr);
dev->nvr_enabled = nvr_enabled;
dev->nvr_base = nvr_base;
if (dev->nvr_enabled && (dev->nvr_base != 0x0000))
nvr_at_handler(1, dev->nvr_base, dev->nvr);
}
}
static void
vl82c113_out(uint16_t port, uint8_t val, void *priv)
{
vl82c113_t *dev = (vl82c113_t *) priv;
if (port == 0xec)
dev->index = val;
else if ((dev->index >= 0x1b) && (dev->index <= 0x1d)) {
const uint8_t index = dev->index - 0x1b;
const uint8_t valxor = dev->regs[index] ^ val;
dev->regs[index] = val;
switch (index) {
default:
break;
case 0x00:
case 0x01:
if (valxor)
vl82c113_nvr_handler(dev);
break;
case 0x02:
if (valxor & 0x02)
kbc_at_set_ps2(dev->kbc, !(val & 0x02));
break;
}
}
}
static uint8_t
vl82c113_in(uint16_t port, void *priv)
{
const vl82c113_t *dev = (vl82c113_t *) priv;
uint8_t ret = 0xff;
if (port == 0xed) {
if ((dev->index >= 0x1b) && (dev->index <= 0x1d))
ret = dev->regs[dev->index - 0x1b];
else if (dev->index == 0x1f)
/* REVID */
ret = 0xc0;
}
return ret;
}
static void
vl82c113_reset(void *priv)
{
vl82c113_t *dev = (vl82c113_t *) priv;
memset(dev->regs, 0x00, sizeof(dev->regs));
dev->regs[0x00] = 0x71;
dev->regs[0x01] = 0x00;
dev->regs[0x02] = 0xc3;
kbc_at_set_ps2(dev->kbc, 0);
vl82c113_nvr_handler(dev);
}
static void
vl82c113_close(void *priv)
{
vl82c113_t *dev = (vl82c113_t *) priv;
free(dev);
}
static void *
vl82c113_init(const device_t *info)
{
vl82c113_t *dev = (vl82c113_t *) calloc(1, sizeof(vl82c113_t));
dev->nvr = device_add(&at_nvr_device);
dev->nvr_enabled = 1;
dev->nvr_base = 0x0070;
/* Commands are standard. */
dev->kbc = device_add(&keyboard_at_device);
vl82c113_reset(dev);
io_sethandler(0x00ec, 0x0002, vl82c113_in, NULL, NULL, vl82c113_out, NULL, NULL, dev);
return dev;
}
const device_t vl82c113_device = {
.name = "VLSI VL82c113 Combination I/O",
.internal_name = "vl82c113",
.flags = 0,
.local = 0,
.init = vl82c113_init,
.close = vl82c113_close,
.reset = vl82c113_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_vl82c113.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,264 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the NatSemi PC87309 Super I/O chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct pc87309_t {
uint8_t id;
uint8_t pm_idx;
uint8_t regs[48];
uint8_t ld_regs[256][208];
uint8_t pm[8];
uint16_t pm_base;
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
} pc87309_t;
static void fdc_handler(pc87309_t *dev);
static void lpt1_handler(pc87309_t *dev);
static void serial_handler(pc87309_t *dev, int uart);
static void
pc87309_pm_write(uint16_t port, uint8_t val, void *priv)
{
pc87309_t *dev = (pc87309_t *) priv;
if (port & 1) {
dev->pm[dev->pm_idx] = val;
switch (dev->pm_idx) {
case 0x00:
fdc_handler(dev);
lpt1_handler(dev);
serial_handler(dev, 1);
serial_handler(dev, 0);
break;
default:
break;
}
} else
dev->pm_idx = val & 0x07;
}
uint8_t
pc87309_pm_read(uint16_t port, void *priv)
{
const pc87309_t *dev = (pc87309_t *) priv;
if (port & 1)
return dev->pm[dev->pm_idx];
else
return dev->pm_idx;
}
static void
pc87309_pm_remove(pc87309_t *dev)
{
if (dev->pm_base != 0xffff) {
io_removehandler(dev->pm_base, 0x0008,
pc87309_pm_read, NULL, NULL, pc87309_pm_write, NULL, NULL, dev);
dev->pm_base = 0xffff;
}
}
static void
pc87309_pm_init(pc87309_t *dev, uint16_t addr)
{
dev->pm_base = addr;
io_sethandler(dev->pm_base, 0x0008,
pc87309_pm_read, NULL, NULL, pc87309_pm_write, NULL, NULL, dev);
}
static void
fdc_handler(pc87309_t *dev)
{
uint8_t irq;
uint8_t active;
uint16_t addr;
fdc_remove(dev->fdc);
active = (dev->ld_regs[0x00][0x00] & 0x01) && (dev->pm[0x00] & 0x08);
addr = ((dev->ld_regs[0x00][0x30] << 8) | dev->ld_regs[0x00][0x31]) - 0x0002;
irq = (dev->ld_regs[0x00][0x40] & 0x0f);
if (active) {
fdc_set_base(dev->fdc, addr);
fdc_set_irq(dev->fdc, irq);
}
}
static void
lpt1_handler(pc87309_t *dev)
{
uint8_t irq;
uint8_t active;
uint16_t addr;
lpt1_remove();
active = (dev->ld_regs[0x01][0x00] & 0x01) && (dev->pm[0x00] & 0x10);
addr = (dev->ld_regs[0x01][0x30] << 8) | dev->ld_regs[0x01][0x31];
irq = (dev->ld_regs[0x01][0x40] & 0x0f);
if (active) {
lpt1_init(addr);
lpt1_irq(irq);
}
}
static void
serial_handler(pc87309_t *dev, int uart)
{
uint8_t irq;
uint8_t active;
uint16_t addr;
serial_remove(dev->uart[uart]);
active = (dev->ld_regs[0x03 - uart][0x00] & 0x01) && (dev->pm[0x00] & (1 << (6 - uart)));
addr = (dev->ld_regs[0x03 - uart][0x30] << 8) | dev->ld_regs[0x03 - uart][0x31];
irq = (dev->ld_regs[0x03 - uart][0x40] & 0x0f);
if (active)
serial_setup(dev->uart[uart], addr, irq);
}
static void
pm_handler(pc87309_t *dev)
{
uint8_t active;
uint16_t addr;
pc87309_pm_remove(dev);
active = (dev->ld_regs[0x04][0x00] & 0x01);
addr = (dev->ld_regs[0x04][0x30] << 8) | dev->ld_regs[0x04][0x31];
if (active)
pc87309_pm_init(dev, addr);
}
static void
pc87309_write(uint16_t port, uint8_t val, void *priv)
{
pc87309_t *dev = (pc87309_t *) priv;
uint8_t index;
index = (port & 1) ? 0 : 1;
if (index) {
dev->cur_reg = val;
return;
} else {
switch (dev->cur_reg) {
case 0x00:
case 0x02:
case 0x03:
case 0x06:
case 0x07:
case 0x21:
dev->regs[dev->cur_reg] = val;
break;
case 0x22:
dev->regs[dev->cur_reg] = val & 0x7f;
break;
default:
if (dev->cur_reg >= 0x30) {
if ((dev->regs[0x07] != 0x06) || !(dev->regs[0x21] & 0x10))
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val;
}
break;
}
}
switch (dev->cur_reg) {
case 0x30:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x01;
switch (dev->regs[0x07]) {
case 0x00:
fdc_handler(dev);
break;
case 0x01:
lpt1_handler(dev);
break;
case 0x02:
serial_handler(dev, 1);
break;
case 0x03:
serial_handler(dev, 0);
break;
case 0x04:
pm_handler(dev);
break;
default:
break;
}
break;
case 0x60:
case 0x62:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x07;
if (dev->cur_reg == 0x62)
break;
switch (dev->regs[0x07]) {
case 0x00:
fdc_handler(dev);
break;
case 0x01:
lpt1_handler(dev);
break;
case 0x02:
serial_handler(dev, 1);
break;
case 0x03:
serial_handler(dev, 0);
break;
case 0x04:
pm_handler(dev);
break;
default:
break;
}
break;
case 0x63:
if (dev->regs[0x07] == 0x06)
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = (val & 0xf8) | 0x04;
break;
case 0x61:
switch (dev->regs[0x07]) {
case 0x00:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = (val & 0xfa) | 0x02;
fdc_handler(dev);
break;
case 0x01:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xfc;
lpt1_handler(dev);
break;
case 0x02:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xf8;
serial_handler(dev, 1);
break;
case 0x03:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xf8;
serial_handler(dev, 0);
break;
case 0x04:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xfe;
pm_handler(dev);
break;
case 0x06:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xf8;
break;
default:
break;
}
break;
case 0x70:
case 0x74:
case 0x75:
switch (dev->regs[0x07]) {
case 0x00:
fdc_handler(dev);
break;
case 0x01:
lpt1_handler(dev);
break;
case 0x02:
serial_handler(dev, 1);
break;
case 0x03:
serial_handler(dev, 0);
break;
case 0x04:
pm_handler(dev);
break;
default:
break;
}
break;
case 0xf0:
switch (dev->regs[0x07]) {
case 0x00:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xe1;
fdc_update_densel_polarity(dev->fdc, (val & 0x20) ? 1 : 0);
fdc_update_enh_mode(dev->fdc, (val & 0x40) ? 1 : 0);
break;
case 0x01:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xf3;
lpt1_handler(dev);
break;
case 0x02:
case 0x03:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x87;
break;
case 0x06:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xc1;
break;
default:
break;
}
break;
case 0xf1:
if (dev->regs[0x07] == 0x00)
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x0f;
break;
default:
break;
}
}
uint8_t
pc87309_read(uint16_t port, void *priv)
{
const pc87309_t *dev = (pc87309_t *) priv;
uint8_t ret = 0xff;
uint8_t index;
index = (port & 1) ? 0 : 1;
if (index)
ret = dev->cur_reg & 0x1f;
else {
if (dev->cur_reg >= 0x30)
ret = dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30];
else
ret = dev->regs[dev->cur_reg];
}
return ret;
}
void
pc87309_reset(pc87309_t *dev)
{
memset(dev->regs, 0x00, 0x30);
for (uint16_t i = 0; i < 256; i++)
memset(dev->ld_regs[i], 0x00, 0xd0);
memset(dev->pm, 0x00, 0x08);
dev->regs[0x20] = dev->id;
dev->regs[0x21] = 0x04;
dev->ld_regs[0x00][0x01] = 0x01;
dev->ld_regs[0x00][0x30] = 0x03;
dev->ld_regs[0x00][0x31] = 0xf2;
dev->ld_regs[0x00][0x40] = 0x06;
dev->ld_regs[0x00][0x41] = 0x03;
dev->ld_regs[0x00][0x44] = 0x02;
dev->ld_regs[0x00][0x45] = 0x04;
dev->ld_regs[0x00][0xc0] = 0x02;
dev->ld_regs[0x01][0x30] = 0x02;
dev->ld_regs[0x01][0x31] = 0x78;
dev->ld_regs[0x01][0x40] = 0x07;
dev->ld_regs[0x01][0x44] = 0x04;
dev->ld_regs[0x01][0x45] = 0x04;
dev->ld_regs[0x01][0xc0] = 0xf2;
dev->ld_regs[0x02][0x30] = 0x02;
dev->ld_regs[0x02][0x31] = 0xf8;
dev->ld_regs[0x02][0x40] = 0x03;
dev->ld_regs[0x02][0x41] = 0x03;
dev->ld_regs[0x02][0x44] = 0x04;
dev->ld_regs[0x02][0x45] = 0x04;
dev->ld_regs[0x02][0xc0] = 0x02;
dev->ld_regs[0x03][0x30] = 0x03;
dev->ld_regs[0x03][0x31] = 0xf8;
dev->ld_regs[0x03][0x40] = 0x04;
dev->ld_regs[0x03][0x41] = 0x03;
dev->ld_regs[0x03][0x44] = 0x04;
dev->ld_regs[0x03][0x45] = 0x04;
dev->ld_regs[0x03][0xc0] = 0x02;
dev->ld_regs[0x04][0x44] = 0x04;
dev->ld_regs[0x04][0x45] = 0x04;
dev->ld_regs[0x05][0x40] = 0x0c;
dev->ld_regs[0x05][0x41] = 0x02;
dev->ld_regs[0x05][0x44] = 0x04;
dev->ld_regs[0x05][0x45] = 0x04;
dev->ld_regs[0x06][0x01] = 0x01;
dev->ld_regs[0x06][0x31] = 0x60;
dev->ld_regs[0x06][0x33] = 0x64;
dev->ld_regs[0x06][0x40] = 0x01;
dev->ld_regs[0x06][0x41] = 0x02;
dev->ld_regs[0x06][0x44] = 0x04;
dev->ld_regs[0x06][0x45] = 0x04;
dev->ld_regs[0x06][0xc0] = 0x40;
dev->regs[0x00] = 0x0B;
dev->regs[0x01] = 0x01;
dev->regs[0x03] = 0x01;
dev->regs[0x05] = 0x0D;
dev->regs[0x08] = 0x70;
dev->regs[0x09] = 0xC0;
dev->regs[0x0b] = 0x80;
dev->regs[0x0f] = 0x1E;
dev->regs[0x12] = 0x30;
dev->regs[0x19] = 0xEF;
dev->pm[0] = 0x79;
dev->pm[4] = 0x0e;
dev->pm_base = 0xffff;
/*
0 = 360 rpm @ 500 kbps for 3.5"
1 = Default, 300 rpm @ 500, 300, 250, 1000 kbps for 3.5"
*/
lpt1_remove();
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
fdc_reset(dev->fdc);
}
static void
pc87309_close(void *priv)
{
pc87309_t *dev = (pc87309_t *) priv;
free(dev);
}
static void *
pc87309_init(const device_t *info)
{
pc87309_t *dev = (pc87309_t *) malloc(sizeof(pc87309_t));
memset(dev, 0, sizeof(pc87309_t));
dev->id = info->local & 0xff;
dev->fdc = device_add(&fdc_at_nsc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
pc87309_reset(dev);
if (info->local & 0x100) {
io_sethandler(0x15c, 0x0002,
pc87309_read, NULL, NULL, pc87309_write, NULL, NULL, dev);
} else {
io_sethandler(0x02e, 0x0002,
pc87309_read, NULL, NULL, pc87309_write, NULL, NULL, dev);
}
return dev;
}
const device_t pc87309_device = {
.name = "National Semiconductor PC87309 Super I/O",
.internal_name = "pc87309",
.flags = 0,
.local = 0xe0,
.init = pc87309_init,
.close = pc87309_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t pc87309_15c_device = {
.name = "National Semiconductor PC87309 Super I/O (Port 15Ch)",
.internal_name = "pc87309_15c",
.flags = 0,
.local = 0x1e0,
.init = pc87309_init,
.close = pc87309_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_pc87309.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,664 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the UMC UM8669F Super I/O chip.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* RichardG, <richardg867@gmail.com>
*
*/
/*
UMC UM8669F non-PnP register definitions
C0:
[7] Infrared half duplex
[4:3] LPT mode:
00 SPP
01 EPP
10 ECP
11 ECP + EPP
C1:
[7] Enable PnP access
[6:0] Always set regardless of PnP access enabled/disabled
C2:
[6:5] Potentially pin muxing mode: (names from AMI "IR group" setup option)
00 Reserved
01 A (no IDE)
10 B (no IDE)
11 C
[4:3] Infrared mode:
00 Reserved
01 HPSIR
10 ASKIR
11 Disabled
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pci.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/gameport.h>
#include <86box/hdc.h>
#include <86box/isapnp.h>
#include <86box/hdc_ide.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
/* Real chips don't have a PnP ROM and instead rely on the BIOS going in blind.
We create a fake ROM here (with values based on the IT8671F) to delegate
all the logical device register handling over to the ISAPnP subsystem. */
static uint8_t um8669f_pnp_rom[] = {
0x55, 0xa3, 0x86, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, /* UMC8669, dummy checksum (filled in by isapnp_add_card) */
0x0a, 0x10, 0x10, /* PnP version 1.0, vendor version 1.0 */
0x15, 0x41, 0xd0, 0x07, 0x00, 0x01, /* logical device PNP0700, can participate in boot */
0x22, 0xfa, 0x1f, /* IRQ 1/3/4/5/6/7/8/9/10/11/12 */
0x2a, 0x0f, 0x0c, /* DMA 0/1/2/3, compatibility, no count by word, count by byte, is bus master, 8-bit only */
0x47, 0x00, 0x00, 0x01, 0xf8, 0x03, 0x08, 0x08, /* I/O 0x100-0x3F8, decodes 10-bit, 8-byte alignment, 8 addresses */
0x15, 0x41, 0xd0, 0x05, 0x01, 0x01, /* logical device PNP0501, can participate in boot */
0x22, 0xfa, 0x1f, /* IRQ 1/3/4/5/6/7/8/9/10/11/12 */
0x47, 0x00, 0x00, 0x01, 0xf8, 0x03, 0x08, 0x08, /* I/O 0x100-0x3F8, decodes 10-bit, 8-byte alignment, 8 addresses */
0x15, 0x41, 0xd0, 0x05, 0x01, 0x01, /* logical device PNP0501, can participate in boot */
0x22, 0xfa, 0x1f, /* IRQ 1/3/4/5/6/7/8/9/10/11/12 */
0x47, 0x00, 0x00, 0x01, 0xf8, 0x03, 0x08, 0x08, /* I/O 0x100-0x3F8, decodes 10-bit, 8-byte alignment, 8 addresses */
0x15, 0x41, 0xd0, 0x04, 0x00, 0x01, /* logical device PNP0400, can participate in boot */
0x22, 0xfa, 0x1f, /* IRQ 1/3/4/5/6/7/8/9/10/11/12 */
0x47, 0x00, 0x00, 0x01, 0xf8, 0x03, 0x08, 0x08, /* I/O 0x100-0x3F8, decodes 10-bit, 8-byte alignment, 8 addresses */
0x15, 0x41, 0xd0, 0x06, 0x00, 0x01, /* logical device PNP0600, can participate in boot */
0x22, 0xfa, 0x1f, /* IRQ 1/3/4/5/6/7/8/9/10/11/12 */
0x47, 0x00, 0x00, 0x01, 0xf8, 0x03, 0x08, 0x08, /* I/O 0x100-0x3F8, decodes 10-bit, 8-byte alignment, 8 addresses */
0x15, 0x41, 0xd0, 0xb0, 0x2f, 0x01, /* logical device PNPB02F, can participate in boot */
0x47, 0x00, 0x00, 0x01, 0xf8, 0x03, 0x08, 0x08, /* I/O 0x100-0x3F8, decodes 10-bit, 8-byte alignment, 8 addresses */
0x79, 0x00 /* end tag, dummy checksum (filled in by isapnp_add_card) */
};
static const isapnp_device_config_t um8669f_pnp_defaults[] = {
{
.activate = 1,
.io = { { .base = FDC_PRIMARY_ADDR }, },
.irq = { { .irq = FDC_PRIMARY_IRQ }, },
.dma = { { .dma = FDC_PRIMARY_DMA }, }
}, {
.activate = 1,
.io = { { .base = COM1_ADDR }, },
.irq = { { .irq = COM1_IRQ }, }
}, {
.activate = 1,
.io = { { .base = COM2_ADDR }, },
.irq = { { .irq = COM2_IRQ }, }
}, {
.activate = 1,
.io = { { .base = LPT1_ADDR }, },
.irq = { { .irq = LPT1_IRQ }, }
}, {
.activate = 0,
.io = { { .base = 0x1f0 }, },
.irq = { { .irq = 14 }, }
}, {
.activate = 0,
.io = { { .base = 0x200 }, }
}
};
#ifdef ENABLE_UM8669F_LOG
int um8669f_do_log = ENABLE_UM8669F_LOG;
static void
um8669f_log(const char *fmt, ...)
{
va_list ap;
if (um8669f_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define um8669f_log(fmt, ...)
#endif
typedef struct um8669f_t {
uint8_t locked;
uint8_t cur_reg;
void *pnp_card;
uint8_t regs[3];
fdc_t *fdc;
serial_t *uart[2];
uint8_t ide;
void *gameport;
} um8669f_t;
static void
um8669f_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
{
if (ld > 5) {
um8669f_log("UM8669F: Unknown logical device %d\n", ld);
return;
}
um8669f_t *dev = (um8669f_t *) priv;
switch (ld) {
case 0:
fdc_remove(dev->fdc);
if (config->activate) {
um8669f_log("UM8669F: FDC enabled at port %04X IRQ %d DMA %d\n", config->io[0].base, config->irq[0].irq, (config->dma[0].dma == ISAPNP_DMA_DISABLED) ? -1 : config->dma[0].dma);
if (config->io[0].base != ISAPNP_IO_DISABLED)
fdc_set_base(dev->fdc, config->io[0].base);
fdc_set_irq(dev->fdc, config->irq[0].irq);
fdc_set_dma_ch(dev->fdc, (config->dma[0].dma == ISAPNP_DMA_DISABLED) ? -1 : config->dma[0].dma);
} else {
um8669f_log("UM8669F: FDC disabled\n");
}
break;
case 1:
case 2:
serial_remove(dev->uart[ld - 1]);
if (config->activate && (config->io[0].base != ISAPNP_IO_DISABLED)) {
um8669f_log("UM8669F: UART %d enabled at port %04X IRQ %d\n", ld - 1, config->io[0].base, config->irq[0].irq);
serial_setup(dev->uart[ld - 1], config->io[0].base, config->irq[0].irq);
} else {
um8669f_log("UM8669F: UART %d disabled\n", ld - 1);
}
break;
case 3:
lpt1_remove();
if (config->activate && (config->io[0].base != ISAPNP_IO_DISABLED)) {
um8669f_log("UM8669F: LPT enabled at port %04X IRQ %d\n", config->io[0].base, config->irq[0].irq);
lpt1_init(config->io[0].base);
} else {
um8669f_log("UM8669F: LPT disabled\n");
}
break;
case 4:
if (config->activate && (config->io[0].base != ISAPNP_IO_DISABLED))
um8669f_log("UM8669F: IDE enabled at port %04X IRQ %d\n", config->io[0].base, config->irq[0].irq);
else
um8669f_log("UM8669F: IDE disabled\n");
if (dev->ide < IDE_BUS_MAX) {
config->io[1].base = config->io[0].base + 0x206; /* status port apparently fixed */
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
ide_pnp_config_changed(0, config, (void *) (int64_t) dev->ide);
#else
ide_pnp_config_changed(0, config, (void *) (int) dev->ide);
#endif
}
break;
case 5:
if (config->activate && (config->io[0].base != ISAPNP_IO_DISABLED)) {
um8669f_log("UM8669F: Game port enabled at port %04X\n", config->io[0].base);
gameport_remap(dev->gameport, config->io[0].base);
} else {
um8669f_log("UM8669F: Game port disabled\n");
gameport_remap(dev->gameport, 0);
}
break;
default:
break;
}
}
void
um8669f_write(uint16_t port, uint8_t val, void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
um8669f_log("UM8669F: write(%04X, %02X)\n", port, val);
if (dev->locked) {
if ((port == 0x108) && (val == 0xaa))
dev->locked = 0;
} else {
if (port == 0x108) {
if (val == 0x55)
dev->locked = 1;
else
dev->cur_reg = val;
} else if ((dev->cur_reg >= 0xc0) && (dev->cur_reg <= 0xc2)) {
dev->regs[dev->cur_reg & 3] = val;
if (dev->cur_reg == 0xc1) {
um8669f_log("UM8669F: ISAPnP %sabled\n", (val & 0x80) ? "en" : "dis");
isapnp_enable_card(dev->pnp_card, (val & 0x80) ? ISAPNP_CARD_FORCE_CONFIG : ISAPNP_CARD_DISABLE);
}
}
}
}
uint8_t
um8669f_read(uint16_t port, void *priv)
{
const um8669f_t *dev = (um8669f_t *) priv;
uint8_t ret = 0xff;
if (!dev->locked) {
if (port == 0x108)
ret = dev->cur_reg; /* ??? */
else if ((dev->cur_reg >= 0xc0) && (dev->cur_reg <= 0xc2))
ret = dev->regs[dev->cur_reg & 3];
}
um8669f_log("UM8669F: read(%04X) = %02X\n", port, ret);
return ret;
}
void
um8669f_reset(um8669f_t *dev)
{
um8669f_log("UM8669F: reset()\n");
fdc_reset(dev->fdc);
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
lpt1_remove();
if (dev->ide < IDE_BUS_MAX)
ide_remove_handlers(dev->ide);
isapnp_enable_card(dev->pnp_card, ISAPNP_CARD_DISABLE);
dev->locked = 1;
isapnp_reset_card(dev->pnp_card);
}
static void
um8669f_close(void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
um8669f_log("UM8669F: close()\n");
free(dev);
}
static void *
um8669f_init(const device_t *info)
{
um8669f_log("UM8669F: init(%02X)\n", info->local);
um8669f_t *dev = (um8669f_t *) malloc(sizeof(um8669f_t));
memset(dev, 0, sizeof(um8669f_t));
dev->pnp_card = isapnp_add_card(um8669f_pnp_rom, sizeof(um8669f_pnp_rom), um8669f_pnp_config_changed, NULL, NULL, NULL, dev);
for (uint8_t i = 0; i < (sizeof(um8669f_pnp_defaults) / sizeof(isapnp_device_config_t)); i++)
isapnp_set_device_defaults(dev->pnp_card, i, &um8669f_pnp_defaults[i]);
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->ide = info->local;
if (dev->ide < IDE_BUS_MAX)
device_add(&ide_isa_device);
dev->gameport = gameport_add(&gameport_sio_device);
io_sethandler(0x0108, 0x0002,
um8669f_read, NULL, NULL, um8669f_write, NULL, NULL, dev);
um8669f_reset(dev);
return dev;
}
const device_t um8669f_device = {
.name = "UMC UM8669F Super I/O",
.internal_name = "um8669f",
.flags = 0,
.local = 0xff,
.init = um8669f_init,
.close = um8669f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t um8669f_ide_device = {
.name = "UMC UM8669F Super I/O (With IDE)",
.internal_name = "um8669f_ide",
.flags = 0,
.local = 0,
.init = um8669f_init,
.close = um8669f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t um8669f_ide_sec_device = {
.name = "UMC UM8669F Super I/O (With Secondary IDE)",
.internal_name = "um8669f_ide_sec",
.flags = 0,
.local = 1,
.init = um8669f_init,
.close = um8669f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_um8669f.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,243 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the ITE IT86x1F Super I/O chips.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pci.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/gameport.h>
#include <86box/sio.h>
#include <86box/isapnp.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
enum {
ITE_IT8661F = 0x8661,
ITE_IT8671F = 0x8681
};
#define CHIP_ID *((uint16_t *) &dev->global_regs[0])
static void it8671f_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv);
static void it8661f_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv);
static const struct {
uint16_t chip_id;
uint16_t unlock_id;
uint8_t gpio_ldn;
/* Fake ROMs to delegate all the logical device register handling over to the ISAPnP subsystem.
The actual ROMs/IDs used by real chips when those are set to ISAPnP mode remain to be seen. */
uint8_t *pnp_rom;
const isapnp_device_config_t *pnp_defaults;
void (*pnp_config_changed)(uint8_t ld, isapnp_device_config_t *config, void *priv);
} it86x1f_models[] = {
{
.chip_id = ITE_IT8661F,
.unlock_id = 0x8661,
.gpio_ldn = 0x05,
.pnp_rom = (uint8_t[]) {
0x26, 0x85, 0x86, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, /* ITE8661, dummy checksum (filled in by isapnp_add_card) */
0x0a, 0x10, 0x10, /* PnP version 1.0, vendor version 1.0 */
0x15, 0x41, 0xd0, 0x07, 0x00, 0x01, /* logical device PNP0700, can participate in boot */
0x23, 0xf8, 0x0f, 0x02, /* IRQ 3/4/5/6/7/8/9/10/11, low true edge sensitive */
0x2a, 0x0f, 0x0c, /* DMA 0/1/2/3, compatibility, no count by word, count by byte, is bus master, 8-bit only */
0x47, 0x01, 0x00, 0x01, 0xf8, 0x0f, 0x08, 0x08, /* I/O 0x100-0xFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x15, 0x41, 0xd0, 0x05, 0x01, 0x01, /* logical device PNP0501, can participate in boot */
0x23, 0xf8, 0x0f, 0x02, /* IRQ 3/4/5/6/7/8/9/10/11, low true edge sensitive */
0x47, 0x01, 0x00, 0x01, 0xf8, 0x0f, 0x08, 0x08, /* I/O 0x100-0xFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x15, 0x41, 0xd0, 0x05, 0x01, 0x01, /* logical device PNP0501, can participate in boot */
0x23, 0xf8, 0x0f, 0x02, /* IRQ 3/4/5/6/7/8/9/10/11, low true edge sensitive */
0x47, 0x01, 0x00, 0x01, 0xf8, 0x0f, 0x08, 0x08, /* I/O 0x100-0xFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x15, 0x41, 0xd0, 0x04, 0x00, 0x01, /* logical device PNP0400, can participate in boot */
0x23, 0xf8, 0x0f, 0x02, /* IRQ 3/4/5/6/7/8/9/10/11, low true edge sensitive */
0x2a, 0x0f, 0x0c, /* DMA 0/1/2/3, compatibility, no count by word, count by byte, is bus master, 8-bit only */
0x47, 0x01, 0x00, 0x01, 0xf8, 0x0f, 0x08, 0x08, /* I/O 0x100-0xFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x47, 0x01, 0x00, 0x01, 0xfc, 0x0f, 0x04, 0x04, /* I/O 0x100-0xFFC, decodes 16-bit, 4-byte alignment, 4 addresses */
0x15, 0x41, 0xd0, 0x05, 0x10, 0x01, /* logical device PNP0510, can participate in boot */
0x23, 0xf8, 0x0f, 0x02, /* IRQ 3/4/5/6/7/8/9/10/11, low true edge sensitive */
0x23, 0xf8, 0x0f, 0x02, /* IRQ 3/4/5/6/7/8/9/10/11, low true edge sensitive */
0x2a, 0x0f, 0x0c, /* DMA 0/1/2/3, compatibility, no count by word, count by byte, is bus master, 8-bit only */
0x2a, 0x0f, 0x0c, /* DMA 0/1/2/3, compatibility, no count by word, count by byte, is bus master, 8-bit only */
0x47, 0x01, 0x00, 0x01, 0xf8, 0x0f, 0x08, 0x08, /* I/O 0x100-0xFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x47, 0x01, 0x00, 0x01, 0xf8, 0x0f, 0x08, 0x08, /* I/O 0x100-0xFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x79, 0x00 /* end tag, dummy checksum (filled in by isapnp_add_card) */
},
.pnp_defaults = (const isapnp_device_config_t[]) {
{
.activate = 0,
.io = { { .base = FDC_PRIMARY_ADDR }, },
.irq = { { .irq = FDC_PRIMARY_IRQ }, },
.dma = { { .dma = FDC_PRIMARY_DMA }, }
}, {
.activate = 0,
.io = { { .base = COM1_ADDR }, },
.irq = { { .irq = COM1_IRQ }, }
}, {
.activate = 0,
.io = { { .base = COM2_ADDR }, },
.irq = { { .irq = COM2_IRQ }, }
}, {
.activate = 0,
.io = { { .base = LPT1_ADDR }, { .base = 0x778 }, },
.irq = { { .irq = LPT1_IRQ }, },
.dma = { { .dma = 3 }, }
}, {
.activate = 0,
.io = { { .base = COM4_ADDR }, { .base = 0x300 }, },
.irq = { { .irq = 10 }, { .irq = 11 }, },
.dma = { { .dma = 1 }, { .dma = 0 }, }
}, {
.activate = -1
}
},
.pnp_config_changed = it8661f_pnp_config_changed
}, {
.chip_id = ITE_IT8671F,
.unlock_id = 0x8680,
.gpio_ldn = 0x07,
.pnp_rom = (uint8_t[]) {
0x26, 0x85, 0x86, 0x71, 0x00, 0x00, 0x00, 0x00, 0x00, /* ITE8671, dummy checksum (filled in by isapnp_add_card) */
0x0a, 0x10, 0x10, /* PnP version 1.0, vendor version 1.0 */
0x15, 0x41, 0xd0, 0x07, 0x00, 0x01, /* logical device PNP0700, can participate in boot */
0x23, 0xfa, 0x1f, 0x02, /* IRQ 1/3/4/5/6/7/8/9/10/11/12, low true edge sensitive */
0x2a, 0x0f, 0x0c, /* DMA 0/1/2/3, compatibility, no count by word, count by byte, is bus master, 8-bit only */
0x47, 0x01, 0x00, 0x01, 0xf8, 0x0f, 0x08, 0x08, /* I/O 0x100-0xFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x15, 0x41, 0xd0, 0x05, 0x01, 0x01, /* logical device PNP0501, can participate in boot */
0x23, 0xfa, 0x1f, 0x02, /* IRQ 1/3/4/5/6/7/8/9/10/11/12, low true edge sensitive */
0x47, 0x01, 0x00, 0x01, 0xf8, 0x0f, 0x08, 0x08, /* I/O 0x100-0xFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x15, 0x41, 0xd0, 0x05, 0x10, 0x01, /* logical device PNP0510, can participate in boot */
0x23, 0xfa, 0x1f, 0x02, /* IRQ 1/3/4/5/6/7/8/9/10/11/12, low true edge sensitive */
0x23, 0xfa, 0x1f, 0x02, /* IRQ 1/3/4/5/6/7/8/9/10/11/12, low true edge sensitive */
0x2a, 0x0f, 0x0c, /* DMA 0/1/2/3, compatibility, no count by word, count by byte, is bus master, 8-bit only */
0x2a, 0x0f, 0x0c, /* DMA 0/1/2/3, compatibility, no count by word, count by byte, is bus master, 8-bit only */
0x47, 0x01, 0x00, 0x01, 0xf8, 0x0f, 0x08, 0x08, /* I/O 0x100-0xFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x47, 0x01, 0x00, 0x01, 0xf8, 0x0f, 0x08, 0x08, /* I/O 0x100-0xFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x15, 0x41, 0xd0, 0x04, 0x00, 0x01, /* logical device PNP0400, can participate in boot */
0x23, 0xfa, 0x1f, 0x02, /* IRQ 1/3/4/5/6/7/8/9/10/11/12, low true edge sensitive */
0x2a, 0x0f, 0x0c, /* DMA 0/1/2/3, compatibility, no count by word, count by byte, is bus master, 8-bit only */
0x47, 0x01, 0x00, 0x01, 0xf8, 0x0f, 0x08, 0x08, /* I/O 0x100-0xFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x47, 0x01, 0x00, 0x01, 0xfc, 0x0f, 0x04, 0x04, /* I/O 0x100-0xFFC, decodes 16-bit, 4-byte alignment, 4 addresses */
0x15, 0x41, 0xd0, 0xff, 0xff, 0x00, /* logical device PNPFFFF (dummy to create APC gap in LDNs) */
0x15, 0x41, 0xd0, 0x03, 0x03, 0x01, /* logical device PNP0303, can participate in boot */
0x23, 0xfa, 0x1f, 0x02, /* IRQ 1/3/4/5/6/7/8/9/10/11/12, low true edge sensitive */
0x47, 0x01, 0x00, 0x00, 0xff, 0x0f, 0x01, 0x01, /* I/O 0x0-0xFFF, decodes 16-bit, 1-byte alignment, 1 address */
0x47, 0x01, 0x00, 0x00, 0xff, 0x0f, 0x01, 0x01, /* I/O 0x0-0xFFF, decodes 16-bit, 1-byte alignment, 1 address */
0x15, 0x41, 0xd0, 0x0f, 0x13, 0x01, /* logical device PNP0F13, can participate in boot */
0x23, 0xfa, 0x1f, 0x02, /* IRQ 1/3/4/5/6/7/8/9/10/11/12, low true edge sensitive */
0x79, 0x00 /* end tag, dummy checksum (filled in by isapnp_add_card) */
},
.pnp_defaults = (const isapnp_device_config_t[]) {
{
.activate = 0,
.io = { { .base = FDC_PRIMARY_ADDR }, },
.irq = { { .irq = FDC_PRIMARY_IRQ }, },
.dma = { { .dma = FDC_PRIMARY_DMA }, }
}, {
.activate = 0,
.io = { { .base = COM1_ADDR }, },
.irq = { { .irq = COM1_IRQ }, }
}, {
.activate = 0,
.io = { { .base = COM2_ADDR }, { .base = 0x300 }, },
.irq = { { .irq = COM2_IRQ }, { .irq = 10 }, },
.dma = { { .dma = 0 }, { .dma = 1 }, }
}, {
.activate = 0,
.io = { { .base = LPT1_ADDR }, { .base = 0x778 }, },
.irq = { { .irq = LPT1_IRQ }, },
.dma = { { .dma = 3 }, }
}, {
.activate = 0
}, {
.activate = 1,
.io = { { .base = 0x60 }, { .base = 0x64 }, },
.irq = { { .irq = 1 }, }
}, {
.activate = 0,
.irq = { { .irq = 12 }, }
}, {
.activate = -1
}
},
.pnp_config_changed = it8671f_pnp_config_changed
}
};
#ifdef ENABLE_IT86X1F_LOG
int it86x1f_do_log = ENABLE_IT86X1F_LOG;
static void
it86x1f_log(const char *fmt, ...)
{
va_list ap;
if (it86x1f_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define it86x1f_log(fmt, ...)
#endif
typedef struct it86x1f_t {
uint8_t instance;
uint8_t locked;
uint8_t cur_ldn;
uint8_t cur_reg;
void *pnp_card;
uint8_t global_regs[16]; /* [0x20:0x2f] */
uint8_t ldn_regs[8][16]; /* [0xf0:0xff] */
uint8_t gpio_regs[36]; /* [0x60:0x7f] then [0xe0:0xe3] */
uint8_t gpio_ldn;
uint16_t unlock_id;
uint16_t addr_port;
uint16_t data_port;
uint8_t unlock_val;
uint8_t unlock_pos : 2;
uint8_t key_pos : 5;
fdc_t *fdc;
serial_t *uart[2];
void *gameport;
} it86x1f_t;
static void it86x1f_remap(it86x1f_t *dev, uint16_t addr_port, uint16_t data_port);
static void
it8661f_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
{
if (ld > 5) {
it86x1f_log("IT86x1F: Unknown logical device %d\n", ld);
return;
}
it86x1f_t *dev = (it86x1f_t *) priv;
switch (ld) {
case 0:
fdc_remove(dev->fdc);
if (config->activate) {
it86x1f_log("IT86x1F: FDC enabled at port %04X IRQ %d DMA %d\n", config->io[0].base, config->irq[0].irq, (config->dma[0].dma == ISAPNP_DMA_DISABLED) ? -1 : config->dma[0].dma);
if (config->io[0].base != ISAPNP_IO_DISABLED)
fdc_set_base(dev->fdc, config->io[0].base);
fdc_set_irq(dev->fdc, config->irq[0].irq);
fdc_set_dma_ch(dev->fdc, (config->dma[0].dma == ISAPNP_DMA_DISABLED) ? -1 : config->dma[0].dma);
} else {
it86x1f_log("IT86x1F: FDC disabled\n");
}
break;
case 1:
case 2:
serial_remove(dev->uart[ld - 1]);
if (config->activate && (config->io[0].base != ISAPNP_IO_DISABLED)) {
it86x1f_log("IT86x1F: UART %d enabled at port %04X IRQ %d\n", ld - 1, config->io[0].base, config->irq[0].irq);
serial_setup(dev->uart[ld - 1], config->io[0].base, config->irq[0].irq);
} else {
it86x1f_log("IT86x1F: UART %d disabled\n", ld - 1);
}
break;
case 3:
lpt1_remove();
if (config->activate && (config->io[0].base != ISAPNP_IO_DISABLED)) {
it86x1f_log("IT86x1F: LPT enabled at port %04X IRQ %d\n", config->io[0].base, config->irq[0].irq);
lpt1_init(config->io[0].base);
} else {
it86x1f_log("IT86x1F: LPT disabled\n");
}
break;
case 4:
if (config->activate && (config->io[0].base != ISAPNP_IO_DISABLED)) {
it86x1f_log("IT86x1F: IR enabled at ports %04X %04X IRQs %d %d DMAs %d %d\n", config->io[0].base, config->io[1].base, config->irq[0].irq, config->irq[1].irq, (config->dma[0].dma == ISAPNP_DMA_DISABLED) ? -1 : config->dma[0].dma, (config->dma[1].dma == ISAPNP_DMA_DISABLED) ? -1 : config->dma[1].dma);
} else {
it86x1f_log("IT86x1F: IR disabled\n");
}
break;
default:
break;
}
}
static void
it8671f_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
{
it86x1f_t *dev = (it86x1f_t *) priv;
switch (ld) {
case 2:
it8661f_pnp_config_changed(4, config, dev); /* just for logging, should change if IR UART is implemented */
fallthrough;
case 0 ... 1:
case 3:
it8661f_pnp_config_changed(ld, config, dev);
break;
case 5:
if (config->activate && (config->io[0].base != ISAPNP_IO_DISABLED) && (config->io[1].base != ISAPNP_IO_DISABLED)) {
it86x1f_log("IT86x1F: KBC enabled at ports %04X %04X IRQ %d\n", config->io[0].base, config->io[1].base, config->irq[0].irq);
} else {
it86x1f_log("IT86x1F: KBC disabled\n");
}
break;
case 6:
if (config->activate) {
it86x1f_log("IT86x1F: KBC mouse enabled at IRQ %d\n", config->irq[0].irq);
} else {
it86x1f_log("IT86x1F: KBC mouse disabled\n");
}
break;
default:
break;
}
}
static uint8_t
it86x1f_pnp_read_vendor_reg(uint8_t ld, uint8_t reg, void *priv)
{
it86x1f_t *dev = (it86x1f_t *) priv;
uint8_t ret = 0xff;
switch (reg) {
case 0x20 ... 0x2f:
ret = dev->global_regs[reg & 0x0f];
break;
case 0x60 ... 0x7f:
if (ld != dev->gpio_ldn)
break;
ret = dev->gpio_regs[reg & 0x1f];
break;
case 0xe0 ... 0xe3:
if (ld != dev->gpio_ldn)
break;
ret = dev->gpio_regs[0x20 | (reg & 0x03)];
break;
case 0xf0 ... 0xff:
if (ld > dev->gpio_ldn)
break;
ret = dev->ldn_regs[ld][reg & 0x0f];
break;
default:
break;
}
it86x1f_log("IT86x1F: read_vendor_reg(%X, %02X) = %02X\n", ld, reg, ret);
return ret;
}
static void
it86x1f_pnp_write_vendor_reg(uint8_t ld, uint8_t reg, uint8_t val, void *priv)
{
it86x1f_t *dev = (it86x1f_t *) priv;
uint8_t effective_ldn;
it86x1f_log("IT86x1F: write_vendor_reg(%X, %02X, %02X)\n", ld, reg, val);
switch (reg) {
case 0x22:
if (CHIP_ID == ITE_IT8661F) {
dev->global_regs[reg & 0x0f] = (val & 0x30) | (dev->global_regs[reg & 0x0f] & ~0x30);
uint8_t mcc = (val & 0x30) >> 4;
if (mcc != dev->instance) {
it86x1f_log("IT86x1F: Instance %d unmapping as ID %d was written\n", dev->instance, mcc);
it86x1f_remap(dev, 0, 0);
}
}
break;
case 0x23:
val &= (1 << dev->gpio_ldn) - 1;
dev->global_regs[reg & 0x0f] = val;
#ifdef ENABLE_IT86X1F_LOG
if (val)
it86x1f_log("IT86x1F: Warning: ISAPnP mode enabled.\n");
#endif
break;
case 0x24:
dev->global_regs[reg & 0x0f] = val & ((CHIP_ID == ITE_IT8661F) ? 0x03 : 0x5f);
break;
case 0x25:
val &= (CHIP_ID == ITE_IT8661F) ? 0x1f : 0xf0;
fallthrough;
case 0x26:
if (ld == dev->gpio_ldn)
dev->global_regs[reg & 0x0f] = val;
break;
case 0x2e ... 0x2f:
if ((CHIP_ID == ITE_IT8671F) && (ld == 0xf4))
dev->global_regs[reg & 0x0f] = val;
break;
case 0x60 ... 0x7f:
if (ld != dev->gpio_ldn)
break;
dev->gpio_regs[reg & 0x1f] = val;
break;
case 0xe0 ... 0xe3:
if (ld != dev->gpio_ldn)
break;
dev->gpio_regs[0x20 | (reg & 0x0f)] = val;
break;
case 0xf0 ... 0xff:
/* Translate GPIO LDN to 7 for the switch block. */
if (ld == dev->gpio_ldn)
effective_ldn = 7;
else if (ld == 7)
effective_ldn = 8; /* dummy */
else
effective_ldn = ld;
switch ((effective_ldn << 8) | reg) {
case 0x0f0:
dev->ldn_regs[ld][reg & 0x0f] = val & 0x0f;
fdc_set_swwp(dev->fdc, !!(val & 0x01));
fdc_set_swap(dev->fdc, !!(val & 0x04));
break;
case 0x1f0:
dev->ldn_regs[ld][reg & 0x0f] = val & 0x03;
break;
case 0x2f0:
dev->ldn_regs[ld][reg & 0x0f] = val & ((CHIP_ID == ITE_IT8661F) ? 0x03 : 0xf3);
break;
case 0x2f1:
if (CHIP_ID == ITE_IT8671F)
dev->ldn_regs[ld][reg & 0x0f] = val & 0xb7;
break;
case 0x3f0:
dev->ldn_regs[ld][reg & 0x0f] = val & 0x07;
break;
case 0x4f0:
if (CHIP_ID == ITE_IT8661F)
val &= 0x3f;
dev->ldn_regs[ld][reg & 0x0f] = val;
break;
case 0x4f1:
if (CHIP_ID == ITE_IT8671F)
dev->ldn_regs[ld][reg & 0x0f] = val & 0x7f;
break;
case 0x4f2:
case 0x4f6:
if (CHIP_ID == ITE_IT8671F)
dev->ldn_regs[ld][reg & 0x0f] = val;
break;
case 0x4f7:
if (CHIP_ID == ITE_IT8671F)
dev->ldn_regs[ld][reg & 0x0f] = val & 0x7f;
break;
case 0x4f8:
if (CHIP_ID == ITE_IT8671F)
dev->ldn_regs[ld][reg & 0x0f] = val & 0x07;
break;
case 0x5f0:
dev->ldn_regs[ld][reg & 0x0f] = val & 0x1f;
break;
case 0x6f0:
if (CHIP_ID == ITE_IT8671F)
dev->ldn_regs[ld][reg & 0x0f] = val & 0x03;
break;
case 0x760:
case 0x762:
case 0x764:
case 0x766:
dev->gpio_regs[reg & 0x1f] = val & 0x0f;
break;
case 0x772:
if (CHIP_ID != ITE_IT8671F)
break;
fallthrough;
case 0x761:
case 0x763:
case 0x765:
case 0x767:
case 0x770:
dev->gpio_regs[reg & 0x1f] = val;
case 0x771:
if (CHIP_ID == ITE_IT8671F)
dev->gpio_regs[reg & 0x1f] = val & 0xde;
break;
case 0x7e0:
if (CHIP_ID == ITE_IT8671F)
dev->gpio_regs[0x20 | (reg & 0x03)] = val & 0xef;
break;
case 0x7e1:
if (CHIP_ID == ITE_IT8671F)
dev->gpio_regs[0x20 | (reg & 0x03)] = val & 0x7f;
break;
case 0x7e3:
if ((CHIP_ID == ITE_IT8671F) && (val & 0x80))
*((uint16_t *) &dev->gpio_regs[0x22]) = 0x0000;
break;
case 0x7fb:
if (CHIP_ID == ITE_IT8671F)
val &= 0x7f;
fallthrough;
case 0x7f0 ... 0x7f5:
dev->ldn_regs[ld][reg & 0x0f] = val;
break;
case 0x7f6:
dev->ldn_regs[ld][reg & 0x0f] = val & ((CHIP_ID == ITE_IT8661F) ? 0x3f : 0xcf);
break;
case 0x7f7:
dev->ldn_regs[ld][reg & 0x0f] = val & ((CHIP_ID == ITE_IT8661F) ? 0x9f : 0xdf);
break;
case 0x7f8 ... 0x7fa:
dev->ldn_regs[ld][reg & 0x0f] = val & ((CHIP_ID == ITE_IT8661F) ? 0x1f : 0x0f);
break;
case 0x7fc:
if (CHIP_ID == ITE_IT8661F)
dev->ldn_regs[ld][reg & 0x0f] = val;
break;
case 0x7ff:
if (CHIP_ID == ITE_IT8671F)
dev->ldn_regs[ld][reg & 0x0f] = val & 0x2f;
break;
default:
break;
}
break;
default:
break;
}
}
static void
it86x1f_write_addr(uint16_t port, uint8_t val, void *priv)
{
it86x1f_t *dev = (it86x1f_t *) priv;
it86x1f_log("IT86x1F: write_addr(%04X, %02X)\n", port, val);
if (dev->locked) {
if (val == isapnp_init_key[dev->key_pos]) {
if (++dev->key_pos == 0) {
it86x1f_log("IT86x1F: Unlocked\n");
dev->locked = 0;
}
} else {
dev->key_pos = 0;
}
} else {
dev->cur_reg = val;
}
}
static void
it86x1f_write_data(uint16_t port, uint8_t val, void *priv)
{
it86x1f_t *dev = (it86x1f_t *) priv;
it86x1f_log("IT86x1F: write_data(%04X, %02X)\n", port, val);
if (dev->locked)
return;
switch (dev->cur_reg) {
case 0x00 ... 0x01:
case 0x03 ... 0x06:
case 0x31:
case 0x71:
case 0x73:
break; /* ISAPnP-only */
case 0x07:
dev->cur_ldn = val;
break;
case 0x02:
if (val & 0x02) {
it86x1f_log("IT86x1F: Locked => ");
dev->locked = 1;
it86x1f_remap(dev, 0, 0);
}
fallthrough;
default:
isapnp_write_reg(dev->pnp_card, dev->cur_ldn, dev->cur_reg, val);
break;
}
}
static uint8_t
it86x1f_read_addr(uint16_t port, void *priv)
{
it86x1f_t *dev = (it86x1f_t *) priv;
uint8_t ret = dev->locked ? 0xff : dev->cur_reg;
it86x1f_log("IT86x1F: read_addr(%04X) = %02X\n", port, ret);
return ret;
}
static uint8_t
it86x1f_read_data(uint16_t port, void *priv)
{
it86x1f_t *dev = (it86x1f_t *) priv;
uint8_t ret = 0xff;
switch (dev->cur_reg) {
case 0x00 ... 0x01:
case 0x03 ... 0x06:
case 0x31:
case 0x71:
case 0x73:
break; /* ISAPnP-only */
case 0x07:
ret = dev->cur_ldn;
break;
default:
ret = isapnp_read_reg(dev->pnp_card, dev->cur_ldn, dev->cur_reg);
break;
}
it86x1f_log("IT86x1F: read_data(%04X) = %02X\n", port, ret);
return ret;
}
static void
it86x1f_remap(it86x1f_t *dev, uint16_t addr_port, uint16_t data_port)
{
if (dev->addr_port)
io_removehandler(dev->addr_port, 1, it86x1f_read_addr, NULL, NULL, it86x1f_write_addr, NULL, NULL, dev);
if (dev->data_port)
io_removehandler(dev->data_port, 1, it86x1f_read_data, NULL, NULL, it86x1f_write_data, NULL, NULL, dev);
it86x1f_log("IT86x1F: remap(%04X, %04X)\n", addr_port, data_port);
dev->addr_port = addr_port;
dev->data_port = data_port;
if (dev->addr_port)
io_sethandler(dev->addr_port, 1, it86x1f_read_addr, NULL, NULL, it86x1f_write_addr, NULL, NULL, dev);
if (dev->data_port)
io_sethandler(dev->data_port, 1, it86x1f_read_data, NULL, NULL, it86x1f_write_data, NULL, NULL, dev);
}
static void
it86x1f_write_unlock(UNUSED(uint16_t port), uint8_t val, void *priv)
{
it86x1f_t *dev = (it86x1f_t *) priv;
it86x1f_log("IT86x1F: write_unlock(%04X, %02X)\n", port, val);
if (!dev->locked)
dev->unlock_pos = 0;
switch (dev->unlock_pos++) {
case 0:
if (val != (dev->unlock_id >> 8))
dev->unlock_pos = 0;
break;
case 1:
if (val != (dev->unlock_id & 0xff))
dev->unlock_pos = 0;
break;
case 2:
if ((val != 0x55) && (val != 0xaa))
dev->unlock_pos = 0;
else
dev->unlock_val = val;
break;
case 3:
switch ((dev->unlock_val << 8) | val) {
case 0x5555:
it86x1f_remap(dev, 0x3f0, 0x3f1);
break;
case 0x55aa:
it86x1f_remap(dev, 0x3bd, 0x3bf);
break;
case 0xaa55:
it86x1f_remap(dev, 0x370, 0x371);
break;
default:
it86x1f_remap(dev, 0, 0);
break;
}
dev->unlock_pos = 0;
break;
}
}
void
it86x1f_reset(it86x1f_t *dev)
{
it86x1f_log("IT86x1F: reset()\n");
fdc_reset(dev->fdc);
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
lpt1_remove();
isapnp_enable_card(dev->pnp_card, ISAPNP_CARD_DISABLE);
dev->locked = 1;
isapnp_reset_card(dev->pnp_card);
}
static void
it86x1f_close(void *priv)
{
it86x1f_t *dev = (it86x1f_t *) priv;
it86x1f_log("IT86x1F: close()\n");
free(dev);
}
static void *
it86x1f_init(UNUSED(const device_t *info))
{
it86x1f_t *dev = (it86x1f_t *) malloc(sizeof(it86x1f_t));
memset(dev, 0, sizeof(it86x1f_t));
uint8_t i;
for (i = 0; i < (sizeof(it86x1f_models) / sizeof(it86x1f_models[0])); i++) {
if (it86x1f_models[i].chip_id == info->local)
break;
}
if (i >= (sizeof(it86x1f_models) / sizeof(it86x1f_models[0]))) {
fatal("IT86x1F: Unknown type %04" PRIXPTR " selected\n", info->local);
return NULL;
}
it86x1f_log("IT86x1F: init(%04" PRIXPTR ")\n", info->local);
/* Let the resource data parser figure out the ROM size. */
dev->pnp_card = isapnp_add_card(it86x1f_models[i].pnp_rom, -1, it86x1f_models[i].pnp_config_changed, NULL, it86x1f_pnp_read_vendor_reg, it86x1f_pnp_write_vendor_reg, dev);
for (uint8_t j = 0; it86x1f_models[i].pnp_defaults[j].activate != (uint8_t) -1; j++)
isapnp_set_device_defaults(dev->pnp_card, j, &it86x1f_models[i].pnp_defaults[j]);
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->gameport = gameport_add(&gameport_sio_device);
dev->instance = device_get_instance();
dev->gpio_ldn = it86x1f_models[i].gpio_ldn;
CHIP_ID = it86x1f_models[i].chip_id;
dev->unlock_id = it86x1f_models[i].unlock_id;
io_sethandler(0x279, 1, NULL, NULL, NULL, it86x1f_write_unlock, NULL, NULL, dev);
it86x1f_reset(dev);
return dev;
}
const device_t it8661f_device = {
.name = "ITE IT8661F Super I/O",
.internal_name = "it8661f",
.flags = 0,
.local = ITE_IT8661F,
.init = it86x1f_init,
.close = it86x1f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t it8671f_device = {
.name = "ITE IT8671F Super I/O",
.internal_name = "it8671f",
.flags = 0,
.local = ITE_IT8671F,
.init = it86x1f_init,
.close = it86x1f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_it86x1f.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,154 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M5123/1543C Super I/O Chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include "cpu.h"
#include <86box/sio.h>
#define AB_RST 0x80
typedef struct ali5123_t {
uint8_t chip_id;
uint8_t is_apm;
uint8_t tries;
uint8_t regs[48];
uint8_t ld_regs[13][256];
int locked;
int cur_reg;
fdc_t *fdc;
serial_t *uart[3];
} ali5123_t;
static void ali5123_write(uint16_t port, uint8_t val, void *priv);
static uint8_t ali5123_read(uint16_t port, void *priv);
static uint16_t
make_port(ali5123_t *dev, uint8_t ld)
{
uint16_t r0 = dev->ld_regs[ld][0x60];
uint16_t r1 = dev->ld_regs[ld][0x61];
uint16_t p = (r0 << 8) + r1;
return p;
}
static void
ali5123_fdc_handler(ali5123_t *dev)
{
uint16_t ld_port = 0;
uint8_t global_enable = !(dev->regs[0x22] & (1 << 0));
uint8_t local_enable = !!dev->ld_regs[0][0x30];
fdc_remove(dev->fdc);
if (global_enable && local_enable) {
ld_port = make_port(dev, 0) & 0xFFF8;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
fdc_set_base(dev->fdc, ld_port);
}
}
static void
ali5123_lpt_handler(ali5123_t *dev)
{
uint16_t ld_port = 0;
uint8_t global_enable = !(dev->regs[0x22] & (1 << 3));
uint8_t local_enable = !!dev->ld_regs[3][0x30];
uint8_t lpt_irq = dev->ld_regs[3][0x70];
if (lpt_irq > 15)
lpt_irq = 0xff;
lpt1_remove();
if (global_enable && local_enable) {
ld_port = make_port(dev, 3) & 0xFFFC;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FFC))
lpt1_init(ld_port);
}
lpt1_irq(lpt_irq);
}
static void
ali5123_serial_handler(ali5123_t *dev, int uart)
{
uint8_t uart_nos[2][3]= { { 4, 5, 0xb }, { 4, 0xb, 5 } };
uint16_t ld_port = 0;
uint8_t uart_no = uart_nos[!!(dev->regs[0x2d] & 0x20)][uart];
uint8_t global_enable = !(dev->regs[0x22] & (1 << (4 + uart)));
uint8_t local_enable = !!dev->ld_regs[uart_no][0x30];
uint8_t mask = (uart == 1) ? 0x04 : 0x05;
serial_remove(dev->uart[uart]);
if (global_enable && local_enable) {
ld_port = make_port(dev, uart_no) & 0xFFF8;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
serial_setup(dev->uart[uart], ld_port, dev->ld_regs[uart_no][0x70]);
}
switch (dev->ld_regs[uart_no][0xf0] & mask) {
case 0x00:
serial_set_clock_src(dev->uart[uart], 1843200.0);
break;
case 0x04:
serial_set_clock_src(dev->uart[uart], 8000000.0);
break;
case 0x01:
case 0x05:
serial_set_clock_src(dev->uart[uart], 2000000.0);
break;
default:
break;
}
}
static void
ali5123_reset(ali5123_t *dev)
{
memset(dev->regs, 0, 48);
dev->regs[0x20] = 0x43;
dev->regs[0x21] = 0x15;
dev->regs[0x2d] = 0x20;
for (uint8_t i = 0; i < 13; i++)
memset(dev->ld_regs[i], 0, 256);
/* Logical device 0: FDD */
dev->ld_regs[0][0x60] = 3;
dev->ld_regs[0][0x61] = 0xf0;
dev->ld_regs[0][0x70] = 6;
dev->ld_regs[0][0x74] = 2;
dev->ld_regs[0][0xf0] = 0x08;
dev->ld_regs[0][0xf2] = 0xff;
/* Logical device 3: Parallel Port */
dev->ld_regs[3][0x60] = 3;
dev->ld_regs[3][0x61] = 0x78;
dev->ld_regs[3][0x70] = 5;
dev->ld_regs[3][0x74] = 4;
dev->ld_regs[3][0xf0] = 0x8c;
dev->ld_regs[3][0xf1] = 0x85;
/* Logical device 4: Serial Port 1 */
dev->ld_regs[4][0x60] = 3;
dev->ld_regs[4][0x61] = 0xf8;
dev->ld_regs[4][0x70] = 4;
dev->ld_regs[4][0xf2] = 0x0c;
serial_setup(dev->uart[0], COM1_ADDR, dev->ld_regs[4][0x70]);
/* Logical device 5: Serial Port 2 - HP like module */
dev->ld_regs[5][0x60] = 3;
dev->ld_regs[5][0x61] = 0xe8;
dev->ld_regs[5][0x70] = 9;
dev->ld_regs[5][0xf0] = 0x80;
dev->ld_regs[4][0xf2] = 0x0c;
serial_setup(dev->uart[1], 0x03e8, dev->ld_regs[5][0x70]);
/* Logical device 7: Keyboard */
dev->ld_regs[7][0x30] = 1;
dev->ld_regs[7][0x70] = 1;
/* TODO: Register F0 bit 6: 0 = PS/2, 1 = AT */
/* Logical device B: Serial Port 2 - HP like module */
dev->ld_regs[0x0b][0x60] = 2;
dev->ld_regs[0x0b][0x61] = 0xf8;
dev->ld_regs[0x0b][0x70] = 3;
dev->ld_regs[0x0b][0xf0] = 0x00;
dev->ld_regs[0x0b][0xf2] = 0x0c;
serial_setup(dev->uart[2], COM2_ADDR, dev->ld_regs[0x0b][0x70]);
/* Logical device C: Hotkey */
dev->ld_regs[0x0c][0xf0] = 0x35;
dev->ld_regs[0x0c][0xf1] = 0x14;
dev->ld_regs[0x0c][0xf2] = 0x11;
dev->ld_regs[0x0c][0xf3] = 0x71;
dev->ld_regs[0x0c][0xf4] = 0x42;
ali5123_lpt_handler(dev);
ali5123_serial_handler(dev, 0);
ali5123_serial_handler(dev, 1);
ali5123_serial_handler(dev, 2);
fdc_reset(dev->fdc);
ali5123_fdc_handler(dev);
dev->locked = 0;
}
static void
ali5123_write(uint16_t port, uint8_t val, void *priv)
{
ali5123_t *dev = (ali5123_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t valxor = 0x00;
uint8_t cur_ld = dev->regs[7];
if (index) {
if (((val == 0x51) && (!dev->tries) && (!dev->locked)) || ((val == 0x23) && (dev->tries) && (!dev->locked))) {
if (dev->tries) {
dev->locked = 1;
fdc_3f1_enable(dev->fdc, 0);
dev->tries = 0;
} else
dev->tries++;
} else {
if (dev->locked) {
if (val == 0xbb) {
dev->locked = 0;
fdc_3f1_enable(dev->fdc, 1);
return;
}
dev->cur_reg = val;
} else {
if (dev->tries)
dev->tries = 0;
}
}
return;
} else {
if (dev->locked) {
if (dev->cur_reg < 48) {
valxor = val ^ dev->regs[dev->cur_reg];
if ((val >= 0x1f) && (val <= 0x21))
return;
dev->regs[dev->cur_reg] = val;
} else {
valxor = val ^ dev->ld_regs[cur_ld][dev->cur_reg];
if (((dev->cur_reg & 0xf0) == 0x70) && (cur_ld < 4))
return;
/* Block writes to some logical devices. */
if (cur_ld > 0x0c)
return;
else
switch (cur_ld) {
case 0x01:
case 0x02:
case 0x06:
case 0x08 ... 0x0a:
return;
case 0x07:
if (dev->cur_reg == 0xf0)
val &= 0xbf;
break;
default:
break;
}
dev->ld_regs[cur_ld][dev->cur_reg] = val;
}
} else
return;
}
if (dev->cur_reg < 48) {
switch (dev->cur_reg) {
case 0x02:
if (val & 0x01)
ali5123_reset(dev);
dev->regs[0x02] = 0x00;
break;
case 0x22:
if (valxor & 0x01)
ali5123_fdc_handler(dev);
if (valxor & 0x08)
ali5123_lpt_handler(dev);
if (valxor & 0x10)
ali5123_serial_handler(dev, 0);
if (valxor & 0x20)
ali5123_serial_handler(dev, 1);
if (valxor & 0x40)
ali5123_serial_handler(dev, 2);
break;
case 0x2d:
if (valxor & 0x20) {
ali5123_serial_handler(dev, 1);
ali5123_serial_handler(dev, 2);
}
break;
default:
break;
}
return;
}
cur_ld = dev->regs[7];
switch (cur_ld) {
case 0:
/* FDD */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] &= ~0x01;
if (valxor)
ali5123_fdc_handler(dev);
break;
case 0xf0:
if (valxor & 0x08)
fdc_update_enh_mode(dev->fdc, !(val & 0x08));
if (valxor & 0x10)
fdc_set_swap(dev->fdc, (val & 0x10) >> 4);
break;
case 0xf1:
if (valxor & 0xc)
fdc_update_densel_force(dev->fdc, (val & 0xc) >> 2);
break;
case 0xf4:
if (valxor & 0x08)
fdc_update_drvrate(dev->fdc, 0, (val & 0x08) >> 3);
break;
case 0xf5:
if (valxor & 0x08)
fdc_update_drvrate(dev->fdc, 1, (val & 0x08) >> 3);
break;
case 0xf6:
if (valxor & 0x08)
fdc_update_drvrate(dev->fdc, 2, (val & 0x08) >> 3);
break;
case 0xf7:
if (valxor & 0x08)
fdc_update_drvrate(dev->fdc, 3, (val & 0x08) >> 3);
break;
default:
break;
}
break;
case 3:
/* Parallel port */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] &= ~0x08;
if (valxor)
ali5123_lpt_handler(dev);
break;
default:
break;
}
break;
case 4:
/* Serial port 1 */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
case 0xf0:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] &= ~0x10;
if (valxor)
ali5123_serial_handler(dev, 0);
break;
default:
break;
}
break;
case 5:
/* Serial port 2 - HP like module */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
case 0xf0:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] &= ~((dev->regs[0x2d] & 0x20) ? 0x40 : 0x20);
if (valxor)
ali5123_serial_handler(dev, (dev->regs[0x2d] & 0x20) ? 2 : 1);
break;
default:
break;
}
break;
case 0x0b:
/* Serial port 3 */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
case 0xf0:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] &= ~((dev->regs[0x2d] & 0x20) ? 0x20 : 0x40);
if (valxor)
ali5123_serial_handler(dev, (dev->regs[0x2d] & 0x20) ? 1 : 2);
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
ali5123_read(uint16_t port, void *priv)
{
const ali5123_t *dev = (ali5123_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t ret = 0xff;
uint8_t cur_ld;
if (dev->locked) {
if (index)
ret = dev->cur_reg;
else {
if (dev->cur_reg < 0x30) {
if (dev->cur_reg == 0x20)
ret = dev->chip_id;
else
ret = dev->regs[dev->cur_reg];
} else {
cur_ld = dev->regs[7];
ret = dev->ld_regs[cur_ld][dev->cur_reg];
}
}
}
return ret;
}
static void
ali5123_close(void *priv)
{
ali5123_t *dev = (ali5123_t *) priv;
free(dev);
}
static void *
ali5123_init(const device_t *info)
{
ali5123_t *dev = (ali5123_t *) malloc(sizeof(ali5123_t));
memset(dev, 0, sizeof(ali5123_t));
dev->fdc = device_add(&fdc_at_ali_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->uart[2] = device_add_inst(&ns16550_device, 3);
dev->chip_id = info->local & 0xff;
ali5123_reset(dev);
io_sethandler(FDC_PRIMARY_ADDR, 0x0002,
ali5123_read, NULL, NULL, ali5123_write, NULL, NULL, dev);
device_add(&keyboard_ps2_ali_pci_device);
return dev;
}
const device_t ali5123_device = {
.name = "ALi M5123/M1543C Super I/O",
.internal_name = "ali5123",
.flags = 0,
.local = 0x40,
.init = ali5123_init,
.close = ali5123_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_ali5123.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,454 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the VIA VT82C686A/B integrated Super I/O.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pci.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
typedef struct vt82c686_t {
uint8_t cur_reg;
uint8_t last_val;
uint8_t regs[25];
uint8_t fdc_dma;
uint8_t fdc_irq;
uint8_t uart_irq[2];
uint8_t lpt_dma;
uint8_t lpt_irq;
fdc_t *fdc;
serial_t *uart[2];
} vt82c686_t;
static uint8_t
get_lpt_length(vt82c686_t *dev)
{
uint8_t length = 4; /* non-EPP */
if ((dev->regs[0x02] & 0x03) == 0x02)
length = 8; /* EPP */
return length;
}
static void
vt82c686_fdc_handler(vt82c686_t *dev)
{
uint16_t io_base = (dev->regs[0x03] & 0xfc) << 2;
fdc_remove(dev->fdc);
if ((dev->regs[0x02] & 0x10) && !(dev->regs[0x0f] & 0x03))
fdc_set_base(dev->fdc, io_base);
fdc_set_dma_ch(dev->fdc, dev->fdc_dma);
fdc_set_irq(dev->fdc, dev->fdc_irq);
fdc_set_swap(dev->fdc, dev->regs[0x16] & 0x01);
}
static void
vt82c686_lpt_handler(vt82c686_t *dev)
{
uint16_t io_mask;
uint16_t io_base = dev->regs[0x06] << 2;
int io_len = get_lpt_length(dev);
io_base &= (0xff8 | io_len);
io_mask = 0x3fc; /* non-EPP */
if (io_len == 8)
io_mask = 0x3f8; /* EPP */
lpt1_remove();
if (((dev->regs[0x02] & 0x03) != 0x03) && !(dev->regs[0x0f] & 0x11) && (io_base >= 0x100) && (io_base <= io_mask))
lpt1_init(io_base);
if (dev->lpt_irq) {
lpt1_irq(dev->lpt_irq);
} else {
lpt1_irq(0xff);
}
}
static void
vt82c686_serial_handler(vt82c686_t *dev, int uart)
{
serial_remove(dev->uart[uart]);
if ((dev->regs[0x02] & (0x04 << uart)) && !(dev->regs[0x0f] & ((0x04 << uart) | 0x01)))
serial_setup(dev->uart[uart], dev->regs[0x07 + uart] << 2, dev->uart_irq[uart]);
}
static void
vt82c686_write(uint16_t port, uint8_t val, void *priv)
{
vt82c686_t *dev = (vt82c686_t *) priv;
/* Store last written value for echo (see comment on read). */
dev->last_val = val;
/* Write current register index on port 0. */
if (!(port & 1)) {
dev->cur_reg = val;
return;
}
/* NOTE: Registers are [0xE0:0xF8] but we store them as [0x00:0x18]. */
if ((dev->cur_reg < 0xe0) || (dev->cur_reg > 0xf8))
return;
uint8_t reg = dev->cur_reg & 0x1f;
/* Read-only registers. */
if ((reg < 0x02) || (reg == 0x0c))
return;
/* Write current register value on port 1. */
dev->regs[reg] = val;
/* Update device state. */
switch (reg) {
case 0x02:
dev->regs[reg] &= 0xbf;
vt82c686_lpt_handler(dev);
vt82c686_serial_handler(dev, 0);
vt82c686_serial_handler(dev, 1);
vt82c686_fdc_handler(dev);
break;
case 0x03:
dev->regs[reg] &= 0xfc;
vt82c686_fdc_handler(dev);
break;
case 0x04:
dev->regs[reg] &= 0xfc;
break;
case 0x05:
dev->regs[reg] |= 0x03;
break;
case 0x06:
vt82c686_lpt_handler(dev);
break;
case 0x07:
case 0x08:
dev->regs[reg] &= 0xfe;
vt82c686_serial_handler(dev, reg == 0x08);
break;
case 0x0d:
dev->regs[reg] &= 0x0f;
break;
case 0x0f:
dev->regs[reg] &= 0x7f;
vt82c686_lpt_handler(dev);
vt82c686_serial_handler(dev, 0);
vt82c686_serial_handler(dev, 1);
vt82c686_fdc_handler(dev);
break;
case 0x10:
dev->regs[reg] &= 0xf4;
break;
case 0x11:
dev->regs[reg] &= 0x3f;
break;
case 0x13:
dev->regs[reg] &= 0xfb;
break;
case 0x14:
case 0x17:
dev->regs[reg] &= 0xfe;
break;
case 0x16:
dev->regs[reg] &= 0xf7;
vt82c686_fdc_handler(dev);
break;
default:
break;
}
}
static uint8_t
vt82c686_read(uint16_t port, void *priv)
{
vt82c686_t *dev = (vt82c686_t *) priv;
/* NOTE: Registers are [0xE0:0xF8] but we store them as [0x00:0x18].
Real 686B echoes the last read/written value when reading from
registers outside that range. */
if (!(port & 1))
dev->last_val = dev->cur_reg;
else if ((dev->cur_reg >= 0xe0) && (dev->cur_reg <= 0xf8))
dev->last_val = dev->regs[dev->cur_reg & 0x1f];
return dev->last_val;
}
/* Writes to Super I/O-related configuration space registers
of the VT82C686 PCI-ISA bridge are sent here by via_pipc.c */
void
vt82c686_sio_write(uint8_t addr, uint8_t val, void *priv)
{
vt82c686_t *dev = (vt82c686_t *) priv;
switch (addr) {
case 0x50:
dev->fdc_dma = val & 0x03;
vt82c686_fdc_handler(dev);
dev->lpt_dma = (val >> 2) & 0x03;
vt82c686_lpt_handler(dev);
break;
case 0x51:
dev->fdc_irq = val & 0x0f;
vt82c686_fdc_handler(dev);
dev->lpt_irq = val >> 4;
vt82c686_lpt_handler(dev);
break;
case 0x52:
dev->uart_irq[0] = val & 0x0f;
vt82c686_serial_handler(dev, 0);
dev->uart_irq[1] = val >> 4;
vt82c686_serial_handler(dev, 1);
break;
case 0x85:
io_removehandler(FDC_PRIMARY_ADDR, 2, vt82c686_read, NULL, NULL, vt82c686_write, NULL, NULL, dev);
if (val & 0x02)
io_sethandler(FDC_PRIMARY_ADDR, 2, vt82c686_read, NULL, NULL, vt82c686_write, NULL, NULL, dev);
break;
default:
break;
}
}
static void
vt82c686_reset(vt82c686_t *dev)
{
memset(dev->regs, 0, 21);
dev->regs[0x00] = 0x3c;
dev->regs[0x02] = 0x03;
fdc_reset(dev->fdc);
vt82c686_lpt_handler(dev);
vt82c686_serial_handler(dev, 0);
vt82c686_serial_handler(dev, 1);
vt82c686_fdc_handler(dev);
vt82c686_sio_write(0x85, 0x00, dev);
}
static void
vt82c686_close(void *priv)
{
vt82c686_t *dev = (vt82c686_t *) priv;
free(dev);
}
static void *
vt82c686_init(UNUSED(const device_t *info))
{
vt82c686_t *dev = (vt82c686_t *) malloc(sizeof(vt82c686_t));
memset(dev, 0, sizeof(vt82c686_t));
dev->fdc = device_add(&fdc_at_smc_device);
dev->fdc_dma = 2;
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->lpt_dma = 3;
vt82c686_reset(dev);
return dev;
}
const device_t via_vt82c686_sio_device = {
.name = "VIA VT82C686 Integrated Super I/O",
.internal_name = "via_vt82c686_sio",
.flags = 0,
.local = 0,
.init = vt82c686_init,
.close = vt82c686_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_vt82c686.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,526 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the LG Prime3C Super I/O
*
*
*
* Authors: Tiseno100
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#ifdef ENABLE_PRIME3C_LOG
int prime3c_do_log = ENABLE_PRIME3C_LOG;
static void
prime3c_log(const char *fmt, ...)
{
va_list ap;
if (prime3c_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define prime3c_log(fmt, ...)
#endif
/* Function Select(Note on prime3c_enable) */
#define FUNCTION_SELECT dev->regs[0xc2]
/* Base Address Registers */
#define FDC_BASE_ADDRESS dev->regs[0xc3]
#define IDE_BASE_ADDRESS dev->regs[0xc4]
#define IDE_SIDE_ADDRESS dev->regs[0xc5]
#define LPT_BASE_ADDRESS dev->regs[0xc6]
#define UART1_BASE_ADDRESS dev->regs[0xc7]
#define UART2_BASE_ADDRESS dev->regs[0xc8]
/* FDC/LPT Configuration */
#define FDC_LPT_DMA dev->regs[0xc9]
#define FDC_LPT_IRQ dev->regs[0xca]
/* UART 1/2 Configuration */
#define UART_IRQ dev->regs[0xcb]
/* Miscellaneous Configuration*/
#define FDC_SWAP (dev->regs[0xd6] & 0x01)
/* IDE functionality(Note on Init) */
#define HAS_IDE_FUNCTIONALITY dev->ide_function
typedef struct prime3c_t {
uint8_t index;
uint8_t regs[256];
uint8_t cfg_lock;
uint8_t ide_function;
fdc_t *fdc_controller;
serial_t *uart[2];
} prime3c_t;
void prime3c_fdc_handler(prime3c_t *dev);
void prime3c_uart_handler(uint8_t num, prime3c_t *dev);
void prime3c_lpt_handler(prime3c_t *dev);
void prime3c_ide_handler(prime3c_t *dev);
void prime3c_enable(prime3c_t *dev);
static void
prime3c_write(uint16_t addr, uint8_t val, void *priv)
{
prime3c_t *dev = (prime3c_t *) priv;
switch (addr) {
case 0x398:
dev->index = val;
/* Enter/Escape Configuration Mode */
if (val == 0x33)
dev->cfg_lock = 0;
else if (val == 0x55)
dev->cfg_lock = 1;
break;
case 0x399:
if (!dev->cfg_lock) {
switch (dev->index) {
case 0xc2:
FUNCTION_SELECT = val & 0xbf;
prime3c_enable(dev);
break;
case 0xc3:
FDC_BASE_ADDRESS = val & 0xfc;
prime3c_fdc_handler(dev);
break;
case 0xc4:
IDE_BASE_ADDRESS = val & 0xfc;
if (HAS_IDE_FUNCTIONALITY)
prime3c_ide_handler(dev);
break;
case 0xc5:
IDE_SIDE_ADDRESS = (val & 0xfc) | 0x02;
if (HAS_IDE_FUNCTIONALITY)
prime3c_ide_handler(dev);
break;
case 0xc6:
LPT_BASE_ADDRESS = val;
break;
case 0xc7:
UART1_BASE_ADDRESS = val & 0xfe;
prime3c_uart_handler(0, dev);
break;
case 0xc8:
UART2_BASE_ADDRESS = val & 0xfe;
prime3c_uart_handler(1, dev);
break;
case 0xc9:
FDC_LPT_DMA = val;
prime3c_fdc_handler(dev);
break;
case 0xca:
FDC_LPT_IRQ = val;
prime3c_fdc_handler(dev);
prime3c_lpt_handler(dev);
break;
case 0xcb:
UART_IRQ = val;
prime3c_uart_handler(0, dev);
prime3c_uart_handler(1, dev);
break;
case 0xcd:
case 0xce:
dev->regs[dev->index] = val;
break;
case 0xcf:
dev->regs[dev->index] = val & 0x3f;
break;
case 0xd0:
dev->regs[dev->index] = val & 0xfc;
break;
case 0xd1:
dev->regs[dev->index] = val & 0x3f;
break;
case 0xd3:
dev->regs[dev->index] = val & 0x7c;
break;
case 0xd5:
case 0xd6:
case 0xd7:
case 0xd8:
dev->regs[dev->index] = val;
break;
default:
break;
}
}
break;
default:
break;
}
}
static uint8_t
prime3c_read(UNUSED(uint16_t addr), void *priv)
{
const prime3c_t *dev = (prime3c_t *) priv;
return dev->regs[dev->index];
}
void
prime3c_fdc_handler(prime3c_t *dev)
{
fdc_remove(dev->fdc_controller);
if (FUNCTION_SELECT & 0x10) {
fdc_set_base(dev->fdc_controller, FDC_BASE_ADDRESS << 2);
fdc_set_irq(dev->fdc_controller, (FDC_LPT_IRQ >> 4) & 0xf);
fdc_set_dma_ch(dev->fdc_controller, (FDC_LPT_DMA >> 4) & 0xf);
fdc_set_swap(dev->fdc_controller, FDC_SWAP);
prime3c_log("Prime3C-FDC: BASE %04x IRQ %01x DMA %01x\n", FDC_BASE_ADDRESS << 2, (FDC_LPT_IRQ >> 4) & 0xf, (FDC_LPT_DMA >> 4) & 0xf);
}
}
void
prime3c_uart_handler(uint8_t num, prime3c_t *dev)
{
serial_remove(dev->uart[num & 1]);
if (FUNCTION_SELECT & (!(num & 1) ? 0x04 : 0x08)) {
serial_setup(dev->uart[num & 1], (!(num & 1) ? UART1_BASE_ADDRESS : UART2_BASE_ADDRESS) << 2, (UART_IRQ >> (!(num & 1) ? 4 : 0)) & 0xf);
prime3c_log("Prime3C-UART%01x: BASE %04x IRQ %01x\n", num & 1, (!(num & 1) ? UART1_BASE_ADDRESS : UART2_BASE_ADDRESS) << 2, (UART_IRQ >> (!(num & 1) ? 4 : 0)) & 0xf);
}
}
void
prime3c_lpt_handler(prime3c_t *dev)
{
lpt1_remove();
if (!(FUNCTION_SELECT & 0x03)) {
lpt1_init(LPT_BASE_ADDRESS << 2);
lpt1_irq(FDC_LPT_IRQ & 0xf);
prime3c_log("Prime3C-LPT: BASE %04x IRQ %02x\n", LPT_BASE_ADDRESS << 2, FDC_LPT_IRQ & 0xf);
}
}
void
prime3c_ide_handler(prime3c_t *dev)
{
ide_pri_disable();
if (FUNCTION_SELECT & 0x20) {
ide_set_base(0, IDE_BASE_ADDRESS << 2);
ide_set_side(0, IDE_SIDE_ADDRESS << 2);
ide_pri_enable();
prime3c_log("Prime3C-IDE: BASE %04x SIDE %04x\n", IDE_BASE_ADDRESS << 2, IDE_SIDE_ADDRESS << 2);
}
}
void
prime3c_enable(prime3c_t *dev)
{
/*
Simulate a device enable/disable scenario
Register C2: Function Select
Bit 7: Gameport
Bit 6: Reserved
Bit 5: IDE
Bit 4: FDC
Bit 3: UART 2
Bit 2: UART 1
Bit 1/0: PIO (0/0 Unidirectional , 0/1 ECP, 1/0 EPP, 1/1 Disabled)
Note: 86Box LPT is simplistic and can't do ECP or EPP.
*/
!(FUNCTION_SELECT & 0x03) ? prime3c_lpt_handler(dev) : lpt1_remove();
(FUNCTION_SELECT & 0x04) ? prime3c_uart_handler(0, dev) : serial_remove(dev->uart[0]);
(FUNCTION_SELECT & 0x08) ? prime3c_uart_handler(1, dev) : serial_remove(dev->uart[1]);
(FUNCTION_SELECT & 0x10) ? prime3c_fdc_handler(dev) : fdc_remove(dev->fdc_controller);
if (HAS_IDE_FUNCTIONALITY)
(FUNCTION_SELECT & 0x20) ? prime3c_ide_handler(dev) : ide_pri_disable();
}
static void
prime3c_close(void *priv)
{
prime3c_t *dev = (prime3c_t *) priv;
free(dev);
}
static void *
prime3c_init(const device_t *info)
{
prime3c_t *dev = (prime3c_t *) malloc(sizeof(prime3c_t));
memset(dev, 0, sizeof(prime3c_t));
/* Avoid conflicting with machines that make no use of the Prime3C Internal IDE */
HAS_IDE_FUNCTIONALITY = info->local;
dev->regs[0xc0] = 0x3c;
dev->regs[0xc2] = 0x03;
dev->regs[0xc3] = 0x3c;
dev->regs[0xc4] = 0x3c;
dev->regs[0xc5] = 0x3d;
dev->regs[0xd5] = 0x3c;
dev->fdc_controller = device_add(&fdc_at_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
if (HAS_IDE_FUNCTIONALITY)
device_add(&ide_isa_device);
prime3c_fdc_handler(dev);
prime3c_uart_handler(0, dev);
prime3c_uart_handler(1, dev);
prime3c_lpt_handler(dev);
if (HAS_IDE_FUNCTIONALITY)
prime3c_ide_handler(dev);
io_sethandler(0x0398, 0x0002, prime3c_read, NULL, NULL, prime3c_write, NULL, NULL, dev);
return dev;
}
const device_t prime3c_device = {
.name = "Goldstar Prime3C",
.internal_name = "prime3c",
.flags = 0,
.local = 0,
.init = prime3c_init,
.close = prime3c_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t prime3c_ide_device = {
.name = "Goldstar Prime3C with IDE functionality",
.internal_name = "prime3c_ide",
.flags = 0,
.local = 1,
.init = prime3c_init,
.close = prime3c_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_prime3c.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,841 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Chips & Technologies F82C710 Universal Peripheral
* Controller (UPC) and 82C606 CHIPSpak Multifunction Controller.
*
* Relevant literature:
*
* [1] Chips and Technologies, Inc.,
* 82C605/82C606 CHIPSpak/CHIPSport MULTIFUNCTION CONTROLLERS,
* PRELIMINARY Data Sheet, Revision 1, May 1987.
* <path_to_url
*
*
*
* Authors: Eluan Costa Miranda <eluancm@gmail.com>
* Lubomir Rintel <lkundrak@v3.sk>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/gameport.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/nvr.h>
#include <86box/sio.h>
typedef struct upc_t {
uint32_t local;
int configuration_state; /* state of algorithm to enter configuration mode */
int configuration_mode;
uint16_t cri_addr; /* cri = configuration index register, addr is even */
uint16_t cap_addr; /* cap = configuration access port, addr is odd and is cri_addr + 1 */
uint8_t cri; /* currently indexed register */
uint8_t last_write;
/* these regs are not affected by reset */
uint8_t regs[15]; /* there are 16 indexes, but there is no need to store the last one which is: R = cri_addr / 4, W = exit config mode */
fdc_t *fdc;
nvr_t *nvr;
void *gameport;
serial_t *uart[2];
} upc_t;
#ifdef ENABLE_F82C710_LOG
int f82c710_do_log = ENABLE_F82C710_LOG;
static void
f82c710_log(const char *fmt, ...)
{
va_list ap;
if (f82c710_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define f82c710_log(fmt, ...)
#endif
static void
f82c710_update_ports(upc_t *dev, int set)
{
uint16_t com_addr = 0;
uint16_t lpt_addr = 0;
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
lpt1_remove();
lpt2_remove();
fdc_remove(dev->fdc);
ide_pri_disable();
if (!set)
return;
if (dev->regs[0] & 4) {
com_addr = dev->regs[4] * 4;
if (com_addr == COM1_ADDR)
serial_setup(dev->uart[0], com_addr, COM1_IRQ);
else if (com_addr == COM2_ADDR)
serial_setup(dev->uart[1], com_addr, COM2_IRQ);
}
if (dev->regs[0] & 8) {
lpt_addr = dev->regs[6] * 4;
lpt1_init(lpt_addr);
if ((lpt_addr == LPT1_ADDR) || (lpt_addr == LPT_MDA_ADDR))
lpt1_irq(LPT1_IRQ);
else if (lpt_addr == LPT2_ADDR)
lpt1_irq(LPT2_IRQ);
}
if (dev->regs[12] & 0x80)
ide_pri_enable();
if (dev->regs[12] & 0x20)
fdc_set_base(dev->fdc, FDC_PRIMARY_ADDR);
}
static void
f82c606_update_ports(upc_t *dev, int set)
{
uint8_t uart1_int = 0xff;
uint8_t uart2_int = 0xff;
uint8_t lpt1_int = 0xff;
int nvr_int = -1;
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
lpt1_remove();
lpt2_remove();
nvr_at_handler(0, ((uint16_t) dev->regs[3]) << 2, dev->nvr);
nvr_at_handler(0, 0x70, dev->nvr);
gameport_remap(dev->gameport, 0);
if (!set)
return;
switch (dev->regs[8] & 0xc0) {
case 0x40:
nvr_int = 3;
break;
case 0x80:
uart1_int = COM2_IRQ;
break;
case 0xc0:
uart2_int = COM2_IRQ;
break;
default:
break;
}
switch (dev->regs[8] & 0x30) {
case 0x10:
nvr_int = 4;
break;
case 0x20:
uart1_int = COM1_IRQ;
break;
case 0x30:
uart2_int = COM1_IRQ;
break;
default:
break;
}
switch (dev->regs[8] & 0x0c) {
case 0x04:
nvr_int = 5;
break;
case 0x08:
uart1_int = 5;
break;
case 0x0c:
lpt1_int = LPT2_IRQ;
break;
default:
break;
}
switch (dev->regs[8] & 0x03) {
case 0x01:
nvr_int = 7;
break;
case 0x02:
uart2_int = 7;
break;
case 0x03:
lpt1_int = LPT1_IRQ;
break;
default:
break;
}
if (dev->regs[0] & 1) {
gameport_remap(dev->gameport, ((uint16_t) dev->regs[7]) << 2);
f82c710_log("Game port at %04X\n", ((uint16_t) dev->regs[7]) << 2);
}
if (dev->regs[0] & 2) {
serial_setup(dev->uart[0], ((uint16_t) dev->regs[4]) << 2, uart1_int);
f82c710_log("UART 1 at %04X, IRQ %i\n", ((uint16_t) dev->regs[4]) << 2, uart1_int);
}
if (dev->regs[0] & 4) {
serial_setup(dev->uart[1], ((uint16_t) dev->regs[5]) << 2, uart2_int);
f82c710_log("UART 2 at %04X, IRQ %i\n", ((uint16_t) dev->regs[5]) << 2, uart2_int);
}
if (dev->regs[0] & 8) {
lpt1_init(((uint16_t) dev->regs[6]) << 2);
lpt1_irq(lpt1_int);
f82c710_log("LPT1 at %04X, IRQ %i\n", ((uint16_t) dev->regs[6]) << 2, lpt1_int);
}
nvr_at_handler(1, ((uint16_t) dev->regs[3]) << 2, dev->nvr);
nvr_irq_set(nvr_int, dev->nvr);
f82c710_log("RTC at %04X, IRQ %i\n", ((uint16_t) dev->regs[3]) << 2, nvr_int);
}
static uint8_t
f82c710_config_read(uint16_t port, void *priv)
{
const upc_t *dev = (upc_t *) priv;
uint8_t temp = 0xff;
if (dev->configuration_mode) {
if (port == dev->cri_addr) {
temp = dev->cri;
} else if (port == dev->cap_addr) {
if (dev->cri == 0xf)
temp = dev->cri_addr / 4;
else
temp = dev->regs[dev->cri];
}
}
return temp;
}
static void
f82c710_config_write(uint16_t port, uint8_t val, void *priv)
{
upc_t *dev = (upc_t *) priv;
int configuration_state_event = 0;
switch (port) {
case 0x2fa:
if ((dev->configuration_state == 0) && (val != 0x00) && (val != 0xff) && (dev->local == 606)) {
configuration_state_event = 1;
dev->last_write = val;
} else if ((dev->configuration_state == 0) && (val == 0x55) && (dev->local == 710))
configuration_state_event = 1;
else if (dev->configuration_state == 4) {
if ((val | dev->last_write) == 0xff) {
dev->cri_addr = ((uint16_t) dev->last_write) << 2;
dev->cap_addr = dev->cri_addr + 1;
dev->configuration_mode = 1;
if (dev->local == 606)
f82c606_update_ports(dev, 0);
else if (dev->local == 710)
f82c710_update_ports(dev, 0);
/* TODO: is the value of cri reset here or when exiting configuration mode? */
io_sethandler(dev->cri_addr, 0x0002, f82c710_config_read, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
} else
dev->configuration_mode = 0;
}
break;
case 0x3fa:
if ((dev->configuration_state == 1) && ((val | dev->last_write) == 0xff) && (dev->local == 606))
configuration_state_event = 1;
else if ((dev->configuration_state == 1) && (val == 0xaa) && (dev->local == 710))
configuration_state_event = 1;
else if ((dev->configuration_state == 2) && (val == 0x36))
configuration_state_event = 1;
else if (dev->configuration_state == 3) {
dev->last_write = val;
configuration_state_event = 1;
}
break;
default:
break;
}
if (dev->configuration_mode) {
if (port == dev->cri_addr) {
dev->cri = val & 0xf;
} else if (port == dev->cap_addr) {
if (dev->cri == 0xf) {
dev->configuration_mode = 0;
io_removehandler(dev->cri_addr, 0x0002, f82c710_config_read, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
/* TODO: any benefit in updating at each register write instead of when exiting config mode? */
if (dev->local == 606)
f82c606_update_ports(dev, 1);
else if (dev->local == 710)
f82c710_update_ports(dev, 1);
} else
dev->regs[dev->cri] = val;
}
}
/* TODO: is the state only reset when accessing 0x2fa and 0x3fa wrongly? */
if ((port == 0x2fa || port == 0x3fa) && configuration_state_event)
dev->configuration_state++;
else
dev->configuration_state = 0;
}
static void
f82c710_reset(void *priv)
{
upc_t *dev = (upc_t *) priv;
/* Set power-on defaults. */
if (dev->local == 606) {
dev->regs[0] = 0x00; /* Enable */
dev->regs[1] = 0x00; /* Configuration Register */
dev->regs[2] = 0x00; /* Ext Baud Rate Select */
dev->regs[3] = 0xb0; /* RTC Base */
dev->regs[4] = 0xfe; /* UART1 Base */
dev->regs[5] = 0xbe; /* UART2 Base */
dev->regs[6] = 0x9e; /* Parallel Base */
dev->regs[7] = 0x80; /* Game Base */
dev->regs[8] = 0xec; /* Interrupt Select */
} else if (dev->local == 710) {
dev->regs[0] = 0x0c;
dev->regs[1] = 0x00;
dev->regs[2] = 0x00;
dev->regs[3] = 0x00;
dev->regs[4] = 0xfe;
dev->regs[5] = 0x00;
dev->regs[6] = 0x9e;
dev->regs[7] = 0x00;
dev->regs[8] = 0x00;
dev->regs[9] = 0xb0;
dev->regs[10] = 0x00;
dev->regs[11] = 0x00;
dev->regs[12] = 0xa0;
dev->regs[13] = 0x00;
dev->regs[14] = 0x00;
}
if (dev->local == 606)
f82c606_update_ports(dev, 1);
else if (dev->local == 710)
f82c710_update_ports(dev, 1);
}
static void
f82c710_close(void *priv)
{
upc_t *dev = (upc_t *) priv;
free(dev);
}
static void *
f82c710_init(const device_t *info)
{
upc_t *dev = (upc_t *) malloc(sizeof(upc_t));
memset(dev, 0, sizeof(upc_t));
dev->local = info->local;
if (dev->local == 606) {
dev->nvr = device_add(&at_nvr_old_device);
dev->gameport = gameport_add(&gameport_sio_device);
} else if (dev->local == 710)
dev->fdc = device_add(&fdc_at_device);
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
io_sethandler(0x02fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
io_sethandler(0x03fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
f82c710_reset(dev);
return dev;
}
const device_t f82c606_device = {
.name = "82C606 CHIPSpak Multifunction Controller",
.internal_name = "f82c606",
.flags = 0,
.local = 606,
.init = f82c710_init,
.close = f82c710_close,
.reset = f82c710_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t f82c710_device = {
.name = "F82C710 UPC Super I/O",
.internal_name = "f82c710",
.flags = 0,
.local = 710,
.init = f82c710_init,
.close = f82c710_close,
.reset = f82c710_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_f82c710.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,711 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C932FR and FDC37C935 Super
* I/O Chips.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/keyboard.h>
#include <86box/nvr.h>
#include <86box/apm.h>
#include <86box/acpi.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#define AB_RST 0x80
typedef struct access_bus_t {
uint8_t control;
uint8_t status;
uint8_t own_addr;
uint8_t data;
uint8_t clock;
uint16_t base;
} access_bus_t;
typedef struct fdc37c93x_t {
uint8_t chip_id;
uint8_t is_apm;
uint8_t has_nvr;
uint8_t tries;
uint8_t port_370;
uint8_t gpio_regs[2];
uint8_t auxio_reg;
uint8_t regs[48];
uint8_t ld_regs[11][256];
uint16_t superio_base;
uint16_t gpio_base; /* Set to EA */
uint16_t auxio_base;
uint16_t nvr_sec_base;
int locked;
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
access_bus_t *access_bus;
nvr_t *nvr;
acpi_t *acpi;
void *kbc;
} fdc37c93x_t;
static void fdc37c93x_write(uint16_t port, uint8_t val, void *priv);
static uint8_t fdc37c93x_read(uint16_t port, void *priv);
static uint16_t
make_port_superio(fdc37c93x_t *dev)
{
uint16_t r0 = dev->regs[0x26];
uint16_t r1 = dev->regs[0x27];
uint16_t p = (r1 << 8) + r0;
return p;
}
static uint16_t
make_port(fdc37c93x_t *dev, uint8_t ld)
{
uint16_t r0 = dev->ld_regs[ld][0x60];
uint16_t r1 = dev->ld_regs[ld][0x61];
uint16_t p = (r0 << 8) + r1;
return p;
}
static uint16_t
make_port_sec(fdc37c93x_t *dev, uint8_t ld)
{
uint16_t r0 = dev->ld_regs[ld][0x62];
uint16_t r1 = dev->ld_regs[ld][0x63];
uint16_t p = (r0 << 8) + r1;
return p;
}
static uint8_t
fdc37c93x_auxio_read(UNUSED(uint16_t port), void *priv)
{
const fdc37c93x_t *dev = (fdc37c93x_t *) priv;
return dev->auxio_reg;
}
static void
fdc37c93x_auxio_write(UNUSED(uint16_t port), uint8_t val, void *priv)
{
fdc37c93x_t *dev = (fdc37c93x_t *) priv;
dev->auxio_reg = val;
}
static uint8_t
fdc37c93x_gpio_read(uint16_t port, void *priv)
{
const fdc37c93x_t *dev = (fdc37c93x_t *) priv;
uint8_t ret = 0xff;
ret = dev->gpio_regs[port & 1];
return ret;
}
static void
fdc37c93x_gpio_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c93x_t *dev = (fdc37c93x_t *) priv;
if (!(port & 1))
dev->gpio_regs[0] = (dev->gpio_regs[0] & 0xfc) | (val & 0x03);
}
static void
fdc37c93x_superio_handler(fdc37c93x_t *dev)
{
io_removehandler(dev->superio_base, 0x0002,
fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev);
dev->superio_base = make_port_superio(dev);
io_sethandler(dev->superio_base, 0x0002,
fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev);
}
static void
fdc37c93x_fdc_handler(fdc37c93x_t *dev)
{
uint16_t ld_port = 0;
uint8_t global_enable = !!(dev->regs[0x22] & (1 << 0));
uint8_t local_enable = !!dev->ld_regs[0][0x30];
fdc_remove(dev->fdc);
if (global_enable && local_enable) {
ld_port = make_port(dev, 0) & 0xFFF8;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
fdc_set_base(dev->fdc, ld_port);
}
}
static void
fdc37c93x_lpt_handler(fdc37c93x_t *dev)
{
uint16_t ld_port = 0;
uint8_t global_enable = !!(dev->regs[0x22] & (1 << 3));
uint8_t local_enable = !!dev->ld_regs[3][0x30];
uint8_t lpt_irq = dev->ld_regs[3][0x70];
if (lpt_irq > 15)
lpt_irq = 0xff;
lpt1_remove();
if (global_enable && local_enable) {
ld_port = make_port(dev, 3) & 0xFFFC;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FFC))
lpt1_init(ld_port);
}
lpt1_irq(lpt_irq);
}
static void
fdc37c93x_serial_handler(fdc37c93x_t *dev, int uart)
{
uint16_t ld_port = 0;
uint8_t uart_no = 4 + uart;
uint8_t global_enable = !!(dev->regs[0x22] & (1 << uart_no));
uint8_t local_enable = !!dev->ld_regs[uart_no][0x30];
serial_remove(dev->uart[uart]);
if (global_enable && local_enable) {
ld_port = make_port(dev, uart_no) & 0xFFF8;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
serial_setup(dev->uart[uart], ld_port, dev->ld_regs[uart_no][0x70]);
}
}
static void
fdc37c93x_nvr_pri_handler(fdc37c93x_t *dev)
{
uint8_t local_enable = !!dev->ld_regs[6][0x30];
if (dev->chip_id != 0x02)
local_enable &= ((dev->ld_regs[6][0xf0] & 0x90) != 0x80);
nvr_at_handler(0, 0x70, dev->nvr);
if (local_enable)
nvr_at_handler(1, 0x70, dev->nvr);
}
static void
fdc37c93x_nvr_sec_handler(fdc37c93x_t *dev)
{
uint16_t ld_port = 0;
uint8_t local_enable = !!dev->ld_regs[6][0x30];
local_enable &= (((dev->ld_regs[6][0xf0] & 0xe0) == 0x80) ||
((dev->ld_regs[6][0xf0] & 0xe0) == 0xe0));
nvr_at_sec_handler(0, dev->nvr_sec_base, dev->nvr);
if (local_enable) {
dev->nvr_sec_base = ld_port = make_port_sec(dev, 6) & 0xFFFE;
/* Datasheet erratum: First it says minimum address is 0x0100, but later implies that it's 0x0000
and that default is 0x0070, same as (unrelocatable) primary NVR. */
if (ld_port <= 0x0FFE)
nvr_at_sec_handler(1, dev->nvr_sec_base, dev->nvr);
}
}
static void
fdc37c93x_kbc_handler(fdc37c93x_t *dev)
{
uint8_t local_enable = !!dev->ld_regs[7][0x30];
kbc_at_handler(local_enable, dev->kbc);
}
static void
fdc37c93x_auxio_handler(fdc37c93x_t *dev)
{
uint16_t ld_port = 0;
uint8_t local_enable = !!dev->ld_regs[8][0x30];
io_removehandler(dev->auxio_base, 0x0001,
fdc37c93x_auxio_read, NULL, NULL, fdc37c93x_auxio_write, NULL, NULL, dev);
if (local_enable) {
dev->auxio_base = ld_port = make_port(dev, 8);
if ((ld_port >= 0x0100) && (ld_port <= 0x0FFF))
io_sethandler(dev->auxio_base, 0x0001,
fdc37c93x_auxio_read, NULL, NULL, fdc37c93x_auxio_write, NULL, NULL, dev);
}
}
static void
fdc37c93x_gpio_handler(fdc37c93x_t *dev)
{
uint16_t ld_port = 0;
uint8_t local_enable;
local_enable = !!(dev->regs[0x03] & 0x80);
io_removehandler(dev->gpio_base, 0x0002,
fdc37c93x_gpio_read, NULL, NULL, fdc37c93x_gpio_write, NULL, NULL, dev);
if (local_enable) {
switch (dev->regs[0x03] & 0x03) {
case 0:
ld_port = 0xe0;
break;
case 1:
ld_port = 0xe2;
break;
case 2:
ld_port = 0xe4;
break;
case 3:
ld_port = 0xea; /* Default */
break;
default:
break;
}
dev->gpio_base = ld_port;
if (ld_port > 0x0000)
io_sethandler(dev->gpio_base, 0x0002,
fdc37c93x_gpio_read, NULL, NULL, fdc37c93x_gpio_write, NULL, NULL, dev);
}
}
static uint8_t
fdc37c93x_access_bus_read(uint16_t port, void *priv)
{
const access_bus_t *dev = (access_bus_t *) priv;
uint8_t ret = 0xff;
switch (port & 3) {
case 0:
ret = (dev->status & 0xBF);
break;
case 1:
ret = (dev->own_addr & 0x7F);
break;
case 2:
ret = dev->data;
break;
case 3:
ret = (dev->clock & 0x87);
break;
default:
break;
}
return ret;
}
static void
fdc37c93x_access_bus_write(uint16_t port, uint8_t val, void *priv)
{
access_bus_t *dev = (access_bus_t *) priv;
switch (port & 3) {
case 0:
dev->control = (val & 0xCF);
break;
case 1:
dev->own_addr = (val & 0x7F);
break;
case 2:
dev->data = val;
break;
case 3:
dev->clock &= 0x80;
dev->clock |= (val & 0x07);
break;
default:
break;
}
}
static void
fdc37c93x_access_bus_handler(fdc37c93x_t *dev)
{
uint16_t ld_port = 0;
uint8_t global_enable = !!(dev->regs[0x22] & (1 << 6));
uint8_t local_enable = !!dev->ld_regs[9][0x30];
io_removehandler(dev->access_bus->base, 0x0004,
fdc37c93x_access_bus_read, NULL, NULL, fdc37c93x_access_bus_write, NULL, NULL, dev->access_bus);
if (global_enable && local_enable) {
dev->access_bus->base = ld_port = make_port(dev, 9);
if ((ld_port >= 0x0100) && (ld_port <= 0x0FFC))
io_sethandler(dev->access_bus->base, 0x0004,
fdc37c93x_access_bus_read, NULL, NULL, fdc37c93x_access_bus_write, NULL, NULL, dev->access_bus);
}
}
static void
fdc37c93x_acpi_handler(fdc37c93x_t *dev)
{
uint16_t ld_port = 0;
uint8_t local_enable = !!dev->ld_regs[0x0a][0x30];
uint8_t sci_irq = dev->ld_regs[0x0a][0x70];
acpi_update_io_mapping(dev->acpi, 0x0000, local_enable);
if (local_enable) {
ld_port = make_port(dev, 0x0a) & 0xFFF0;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF0))
acpi_update_io_mapping(dev->acpi, ld_port, local_enable);
}
acpi_update_aux_io_mapping(dev->acpi, 0x0000, local_enable);
if (local_enable) {
ld_port = make_port_sec(dev, 0x0a) & 0xFFF8;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
acpi_update_aux_io_mapping(dev->acpi, ld_port, local_enable);
}
acpi_set_irq_line(dev->acpi, sci_irq);
}
static void
fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c93x_t *dev = (fdc37c93x_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t valxor = 0x00;
uint8_t keep = 0x00;
/* Compaq Presario 4500: Unlock at FB, Register at EA, Data at EB, Lock at F9. */
if ((port == 0xea) || (port == 0xf9) || (port == 0xfb))
index = 1;
else if (port == 0xeb)
index = 0;
if (index) {
if ((val == 0x55) && !dev->locked) {
if (dev->tries) {
dev->locked = 1;
fdc_3f1_enable(dev->fdc, 0);
dev->tries = 0;
} else
dev->tries++;
} else {
if (dev->locked) {
if (val == 0xaa) {
dev->locked = 0;
fdc_3f1_enable(dev->fdc, 1);
return;
}
dev->cur_reg = val;
} else {
if (dev->tries)
dev->tries = 0;
}
}
return;
} else {
if (dev->locked) {
if (dev->cur_reg < 48) {
valxor = val ^ dev->regs[dev->cur_reg];
if ((val == 0x20) || (val == 0x21))
return;
dev->regs[dev->cur_reg] = val;
} else {
valxor = val ^ dev->ld_regs[dev->regs[7]][dev->cur_reg];
if (((dev->cur_reg & 0xF0) == 0x70) && (dev->regs[7] < 4))
return;
/* Block writes to some logical devices. */
if (dev->regs[7] > 0x0a)
return;
else
switch (dev->regs[7]) {
// case 0x01:
// case 0x02:
// return;
case 0x06:
if (!dev->has_nvr)
return;
/* Bits 0 to 3 of logical device 6 (RTC) register F0h must stay set
once they are set. */
else if (dev->cur_reg == 0xf0)
keep = dev->ld_regs[dev->regs[7]][dev->cur_reg] & 0x0f;
break;
case 0x09:
/* If we're on the FDC37C935, return as this is not a valid
logical device there. */
if (!dev->is_apm && (dev->chip_id == 0x02))
return;
break;
case 0x0a:
/* If we're not on the FDC37C931APM, return as this is not a
valid logical device there. */
if (!dev->is_apm)
return;
break;
default:
break;
}
dev->ld_regs[dev->regs[7]][dev->cur_reg] = val | keep;
}
} else
return;
}
if (dev->cur_reg < 48) {
switch (dev->cur_reg) {
case 0x03:
if (valxor & 0x83)
fdc37c93x_gpio_handler(dev);
dev->regs[0x03] &= 0x83;
break;
case 0x22:
if (valxor & 0x01)
fdc37c93x_fdc_handler(dev);
if (valxor & 0x08)
fdc37c93x_lpt_handler(dev);
if (valxor & 0x10)
fdc37c93x_serial_handler(dev, 0);
if (valxor & 0x20)
fdc37c93x_serial_handler(dev, 1);
if ((valxor & 0x40) && (dev->chip_id != 0x02))
fdc37c93x_access_bus_handler(dev);
break;
case 0x27:
if (dev->chip_id != 0x02)
fdc37c93x_superio_handler(dev);
break;
default:
break;
}
return;
}
switch (dev->regs[7]) {
case 0:
/* FDD */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x01;
if (valxor)
fdc37c93x_fdc_handler(dev);
break;
case 0xF0:
if (valxor & 0x01)
fdc_update_enh_mode(dev->fdc, val & 0x01);
if (valxor & 0x10)
fdc_set_swap(dev->fdc, (val & 0x10) >> 4);
break;
case 0xF1:
if (valxor & 0xC)
fdc_update_densel_force(dev->fdc, (val & 0xc) >> 2);
break;
case 0xF2:
if (valxor & 0xC0)
fdc_update_rwc(dev->fdc, 3, (val & 0xc0) >> 6);
if (valxor & 0x30)
fdc_update_rwc(dev->fdc, 2, (val & 0x30) >> 4);
if (valxor & 0x0C)
fdc_update_rwc(dev->fdc, 1, (val & 0x0c) >> 2);
if (valxor & 0x03)
fdc_update_rwc(dev->fdc, 0, (val & 0x03));
break;
case 0xF4:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 0, (val & 0x18) >> 3);
break;
case 0xF5:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 1, (val & 0x18) >> 3);
break;
case 0xF6:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 2, (val & 0x18) >> 3);
break;
case 0xF7:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 3, (val & 0x18) >> 3);
break;
default:
break;
}
break;
case 3:
/* Parallel port */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x08;
if (valxor)
fdc37c93x_lpt_handler(dev);
break;
default:
break;
}
break;
case 4:
/* Serial port 1 */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x10;
if (valxor)
fdc37c93x_serial_handler(dev, 0);
break;
default:
break;
}
break;
case 5:
/* Serial port 2 */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x20;
if (valxor)
fdc37c93x_serial_handler(dev, 1);
break;
default:
break;
}
break;
case 6:
/* RTC/NVR */
if (!dev->has_nvr)
return;
switch (dev->cur_reg) {
case 0x30:
if (valxor) {
fdc37c93x_nvr_pri_handler(dev);
if (dev->chip_id != 0x02)
fdc37c93x_nvr_sec_handler(dev);
}
break;
case 0x62:
case 0x63:
if ((dev->chip_id != 0x02) && valxor)
fdc37c93x_nvr_sec_handler(dev);
break;
case 0xf0:
if (valxor) {
nvr_lock_set(0x80, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x01), dev->nvr);
nvr_lock_set(0xa0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x02), dev->nvr);
nvr_lock_set(0xc0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x04), dev->nvr);
nvr_lock_set(0xe0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x08), dev->nvr);
if ((dev->chip_id == 0x02) && (dev->ld_regs[6][dev->cur_reg] & 0x80))
nvr_bank_set(0, 1, dev->nvr);
else if ((dev->chip_id != 0x02) && (dev->ld_regs[6][dev->cur_reg] & 0x80))
switch ((dev->ld_regs[6][dev->cur_reg] >> 4) & 0x07) {
default:
case 0x00:
nvr_bank_set(0, 0xff, dev->nvr);
nvr_bank_set(1, 1, dev->nvr);
break;
case 0x01:
nvr_bank_set(0, 0, dev->nvr);
nvr_bank_set(1, 1, dev->nvr);
break;
case 0x02:
case 0x04:
nvr_bank_set(0, 0xff, dev->nvr);
nvr_bank_set(1, 0xff, dev->nvr);
break;
case 0x03:
case 0x05:
nvr_bank_set(0, 0, dev->nvr);
nvr_bank_set(1, 0xff, dev->nvr);
break;
case 0x06:
nvr_bank_set(0, 0xff, dev->nvr);
nvr_bank_set(1, 2, dev->nvr);
break;
case 0x07:
nvr_bank_set(0, 0, dev->nvr);
nvr_bank_set(1, 2, dev->nvr);
break;
}
else {
nvr_bank_set(0, 0, dev->nvr);
if (dev->chip_id != 0x02)
nvr_bank_set(1, 0xff, dev->nvr);
}
fdc37c93x_nvr_pri_handler(dev);
if (dev->chip_id != 0x02)
fdc37c93x_nvr_sec_handler(dev);
}
break;
default:
break;
}
break;
case 7:
/* Keyboard */
switch (dev->cur_reg) {
case 0x30:
if (valxor)
fdc37c93x_kbc_handler(dev);
break;
default:
break;
}
break;
case 8:
/* Auxiliary I/O */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if (valxor)
fdc37c93x_auxio_handler(dev);
break;
default:
break;
}
break;
case 9:
/* Access bus (FDC37C932FR and FDC37C931APM only) */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x40;
if (valxor)
fdc37c93x_access_bus_handler(dev);
break;
default:
break;
}
break;
case 10:
/* Access bus (FDC37C931APM only) */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x62:
case 0x63:
case 0x70:
if (valxor)
fdc37c93x_acpi_handler(dev);
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
fdc37c93x_read(uint16_t port, void *priv)
{
fdc37c93x_t *dev = (fdc37c93x_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t ret = 0xff;
/* Compaq Presario 4500: Unlock at FB, Register at EA, Data at EB, Lock at F9. */
if ((port == 0xea) || (port == 0xf9) || (port == 0xfb))
index = 1;
else if (port == 0xeb)
index = 0;
if (dev->locked) {
if (index)
ret = dev->cur_reg;
else {
if (dev->cur_reg < 0x30) {
if (dev->cur_reg == 0x20)
ret = dev->chip_id;
else
ret = dev->regs[dev->cur_reg];
} else {
if ((dev->regs[7] == 0) && (dev->cur_reg == 0xF2)) {
ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) | (fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6));
} else
ret = dev->ld_regs[dev->regs[7]][dev->cur_reg];
}
}
}
return ret;
}
static void
fdc37c93x_reset(fdc37c93x_t *dev)
{
memset(dev->regs, 0, 48);
dev->regs[0x03] = 0x03;
dev->regs[0x20] = dev->chip_id;
dev->regs[0x21] = 0x01;
dev->regs[0x22] = 0x39;
dev->regs[0x24] = 0x04;
if (dev->chip_id != 0x02) {
dev->regs[0x26] = dev->port_370 ? 0x70 : 0xF0;
dev->regs[0x27] = 0x03;
}
for (uint8_t i = 0; i < 11; i++)
memset(dev->ld_regs[i], 0, 256);
/* Logical device 0: FDD */
dev->ld_regs[0][0x30] = 0;
dev->ld_regs[0][0x60] = 3;
dev->ld_regs[0][0x61] = 0xF0;
dev->ld_regs[0][0x70] = 6;
dev->ld_regs[0][0x74] = 2;
dev->ld_regs[0][0xF0] = 0xE;
dev->ld_regs[0][0xF2] = 0xFF;
/* Logical device 1: IDE1 */
dev->ld_regs[1][0x30] = 0;
dev->ld_regs[1][0x60] = 1;
dev->ld_regs[1][0x61] = 0xF0;
dev->ld_regs[1][0x62] = 3;
dev->ld_regs[1][0x63] = 0xF6;
dev->ld_regs[1][0x70] = 0xE;
dev->ld_regs[1][0xF0] = 0xC;
/* Logical device 2: IDE2 */
dev->ld_regs[2][0x30] = 0;
dev->ld_regs[2][0x60] = 1;
dev->ld_regs[2][0x61] = 0x70;
dev->ld_regs[2][0x62] = 3;
dev->ld_regs[2][0x63] = 0x76;
dev->ld_regs[2][0x70] = 0xF;
/* Logical device 3: Parallel Port */
dev->ld_regs[3][0x30] = 0;
dev->ld_regs[3][0x60] = 3;
dev->ld_regs[3][0x61] = 0x78;
dev->ld_regs[3][0x70] = 7;
dev->ld_regs[3][0x74] = 4;
dev->ld_regs[3][0xF0] = 0x3C;
/* Logical device 4: Serial Port 1 */
dev->ld_regs[4][0x30] = 0;
dev->ld_regs[4][0x60] = 3;
dev->ld_regs[4][0x61] = 0xf8;
dev->ld_regs[4][0x70] = 4;
dev->ld_regs[4][0xF0] = 3;
serial_setup(dev->uart[0], COM1_ADDR, dev->ld_regs[4][0x70]);
/* Logical device 5: Serial Port 2 */
dev->ld_regs[5][0x30] = 0;
dev->ld_regs[5][0x60] = 2;
dev->ld_regs[5][0x61] = 0xf8;
dev->ld_regs[5][0x70] = 3;
dev->ld_regs[5][0x74] = 4;
dev->ld_regs[5][0xF1] = 2;
dev->ld_regs[5][0xF2] = 3;
serial_setup(dev->uart[1], COM2_ADDR, dev->ld_regs[5][0x70]);
/* Logical device 6: RTC */
dev->ld_regs[6][0x30] = 0;
dev->ld_regs[6][0x60] = 0x70;
if (dev->chip_id != 0x02)
dev->ld_regs[6][0x63] = (dev->has_nvr) ? 0x70 : 0x00;
dev->ld_regs[6][0xF0] = 0;
dev->ld_regs[6][0xF4] = 3;
/* Logical device 7: Keyboard */
dev->ld_regs[7][0x30] = 0;
dev->ld_regs[7][0x61] = 0x60;
dev->ld_regs[7][0x70] = 1;
/* Logical device 8: Auxiliary I/O */
/* Logical device 9: ACCESS.bus */
/* Logical device A: ACPI */
fdc37c93x_gpio_handler(dev);
fdc37c93x_lpt_handler(dev);
fdc37c93x_serial_handler(dev, 0);
fdc37c93x_serial_handler(dev, 1);
fdc37c93x_auxio_handler(dev);
if (dev->is_apm || (dev->chip_id == 0x03))
fdc37c93x_access_bus_handler(dev);
if (dev->is_apm)
fdc37c93x_acpi_handler(dev);
fdc_reset(dev->fdc);
fdc37c93x_fdc_handler(dev);
if (dev->has_nvr) {
fdc37c93x_nvr_pri_handler(dev);
fdc37c93x_nvr_sec_handler(dev);
nvr_bank_set(0, 0, dev->nvr);
nvr_bank_set(1, 0xff, dev->nvr);
nvr_lock_set(0x80, 0x20, 0, dev->nvr);
nvr_lock_set(0xa0, 0x20, 0, dev->nvr);
nvr_lock_set(0xc0, 0x20, 0, dev->nvr);
nvr_lock_set(0xe0, 0x20, 0, dev->nvr);
}
fdc37c93x_kbc_handler(dev);
if (dev->chip_id != 0x02)
fdc37c93x_superio_handler(dev);
dev->locked = 0;
}
static void
access_bus_close(void *priv)
{
access_bus_t *dev = (access_bus_t *) priv;
free(dev);
}
static void *
access_bus_init(UNUSED(const device_t *info))
{
access_bus_t *dev = (access_bus_t *) malloc(sizeof(access_bus_t));
memset(dev, 0, sizeof(access_bus_t));
return dev;
}
static const device_t access_bus_device = {
.name = "SMC FDC37C932FR ACCESS.bus",
.internal_name = "access_bus",
.flags = 0,
.local = 0x03,
.init = access_bus_init,
.close = access_bus_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
static void
fdc37c93x_close(void *priv)
{
fdc37c93x_t *dev = (fdc37c93x_t *) priv;
free(dev);
}
static void *
fdc37c93x_init(const device_t *info)
{
int is_compaq;
fdc37c93x_t *dev = (fdc37c93x_t *) malloc(sizeof(fdc37c93x_t));
memset(dev, 0, sizeof(fdc37c93x_t));
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->chip_id = info->local & 0xff;
dev->is_apm = (info->local >> 8) & 0x01;
is_compaq = (info->local >> 8) & 0x02;
dev->has_nvr = !((info->local >> 8) & 0x04);
dev->port_370 = ((info->local >> 8) & 0x08);
dev->gpio_regs[0] = 0xff;
#if 0
dev->gpio_regs[1] = (info->local == 0x0030) ? 0xff : 0xfd;
#endif
dev->gpio_regs[1] = (dev->chip_id == 0x30) ? 0xff : 0xfd;
if (dev->has_nvr) {
dev->nvr = device_add(&at_nvr_device);
nvr_bank_set(0, 0, dev->nvr);
nvr_bank_set(1, 0xff, dev->nvr);
}
if (dev->is_apm || (dev->chip_id == 0x03))
dev->access_bus = device_add(&access_bus_device);
if (dev->is_apm)
dev->acpi = device_add(&acpi_smc_device);
if (is_compaq) {
io_sethandler(0x0ea, 0x0002,
fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev);
io_sethandler(0x0f9, 0x0001,
fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev);
io_sethandler(0x0fb, 0x0001,
fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev);
}
dev->kbc = device_add(&keyboard_ps2_ami_pci_device);
fdc37c93x_reset(dev);
if (dev->chip_id == 0x02) {
io_sethandler(0x03f0, 0x0002,
fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev);
io_sethandler(0x0370, 0x0002,
fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev);
}
return dev;
}
const device_t fdc37c931apm_device = {
.name = "SMC FDC37C931APM Super I/O",
.internal_name = "fdc37c931apm",
.flags = 0,
.local = 0x130, /* Share the same ID with the 932QF. */
.init = fdc37c93x_init,
.close = fdc37c93x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c931apm_compaq_device = {
.name = "SMC FDC37C931APM Super I/O (Compaq Presario 4500)",
.internal_name = "fdc37c931apm_compaq",
.flags = 0,
.local = 0x330, /* Share the same ID with the 932QF. */
.init = fdc37c93x_init,
.close = fdc37c93x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c932_device = {
.name = "SMC FDC37C932 Super I/O",
.internal_name = "fdc37c932",
.flags = 0,
.local = 0x02,
.init = fdc37c93x_init,
.close = fdc37c93x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c932fr_device = {
.name = "SMC FDC37C932FR Super I/O",
.internal_name = "fdc37c932fr",
.flags = 0,
.local = 0x03,
.init = fdc37c93x_init,
.close = fdc37c93x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c932qf_device = {
.name = "SMC FDC37C932QF Super I/O",
.internal_name = "fdc37c932qf",
.flags = 0,
.local = 0x30,
.init = fdc37c93x_init,
.close = fdc37c93x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c935_device = {
.name = "SMC FDC37C935 Super I/O",
.internal_name = "fdc37c935",
.flags = 0,
.local = 0x02,
.init = fdc37c93x_init,
.close = fdc37c93x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c935_370_device = {
.name = "SMC FDC37C935 Super I/O (Port 370h)",
.internal_name = "fdc37c935_370",
.flags = 0,
.local = 0x802,
.init = fdc37c93x_init,
.close = fdc37c93x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c935_no_nvr_device = {
.name = "SMC FDC37C935 Super I/O",
.internal_name = "fdc37c935",
.flags = 0,
.local = 0x402,
.init = fdc37c93x_init,
.close = fdc37c93x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_fdc37c93x.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,425 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the SMSC FDC37M60x Super I/O
*
*
*
* Authors: Tiseno100
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#define SIO_INDEX_PORT dev->sio_index_port
#define INDEX dev->index
/* Current Logical Device Number */
#define CURRENT_LOGICAL_DEVICE dev->regs[0x07]
/* Global Device Configuration */
#define ENABLED(ld) dev->device_regs[ld][0x30]
#define BASE_ADDRESS(ld) ((dev->device_regs[ld][0x60] << 8) | (dev->device_regs[ld][0x61]))
#define IRQ(ld) dev->device_regs[ld][0x70]
#define DMA(ld) dev->device_regs[ld][0x74]
/* Miscellaneous Chip Functionality */
#define SOFT_RESET (val & 0x01)
#define POWER_CONTROL dev->regs[0x22]
#ifdef ENABLE_FDC37M60X_LOG
int fdc37m60x_do_log = ENABLE_FDC37M60X_LOG;
static void
fdc37m60x_log(const char *fmt, ...)
{
va_list ap;
if (fdc37m60x_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define fdc37m60x_log(fmt, ...)
#endif
typedef struct fdc37m60x_t {
uint8_t index;
uint8_t regs[256];
uint8_t device_regs[10][256];
uint8_t cfg_lock;
uint8_t ide_function;
uint16_t sio_index_port;
fdc_t *fdc;
serial_t *uart[2];
} fdc37m60x_t;
static void fdc37m60x_fdc_handler(fdc37m60x_t *dev);
static void fdc37m60x_uart_handler(uint8_t num, fdc37m60x_t *dev);
static void fdc37m60x_lpt_handler(fdc37m60x_t *dev);
static void fdc37m60x_logical_device_handler(fdc37m60x_t *dev);
static void fdc37m60x_reset(void *priv);
static void
fdc37m60x_write(uint16_t addr, uint8_t val, void *priv)
{
fdc37m60x_t *dev = (fdc37m60x_t *) priv;
if (addr & 1) {
if (!dev->cfg_lock) {
switch (INDEX) {
/* Global Configuration */
case 0x02:
dev->regs[INDEX] = val;
if (SOFT_RESET)
fdc37m60x_reset(dev);
break;
case 0x07:
CURRENT_LOGICAL_DEVICE = val;
break;
case 0x22:
POWER_CONTROL = val & 0x3f;
break;
case 0x23:
dev->regs[INDEX] = val & 0x3f;
break;
case 0x24:
dev->regs[INDEX] = val & 0x4e;
break;
case 0x2b:
case 0x2c:
case 0x2d:
case 0x2e:
case 0x2f:
dev->regs[INDEX] = val;
break;
/* Device Configuration */
case 0x30:
case 0x60:
case 0x61:
case 0x70:
case 0x74:
case 0xf0:
case 0xf1:
case 0xf2:
case 0xf3:
case 0xf4:
case 0xf5:
case 0xf6:
case 0xf7:
if (CURRENT_LOGICAL_DEVICE <= 0x81) /* Avoid Overflow */
dev->device_regs[CURRENT_LOGICAL_DEVICE][INDEX] = (INDEX == 0x30) ? (val & 1) : val;
fdc37m60x_logical_device_handler(dev);
break;
default:
break;
}
}
} else {
/* Enter/Escape Configuration Mode */
if (val == 0x55)
dev->cfg_lock = 0;
else if (!dev->cfg_lock && (val == 0xaa))
dev->cfg_lock = 1;
else if (!dev->cfg_lock)
INDEX = val;
}
}
static uint8_t
fdc37m60x_read(uint16_t addr, void *priv)
{
const fdc37m60x_t *dev = (fdc37m60x_t *) priv;
uint8_t ret = 0xff;
if (addr & 1)
ret = (INDEX >= 0x30) ? dev->device_regs[CURRENT_LOGICAL_DEVICE][INDEX] : dev->regs[INDEX];
return ret;
}
static void
fdc37m60x_fdc_handler(fdc37m60x_t *dev)
{
fdc_remove(dev->fdc);
if (ENABLED(0) || (POWER_CONTROL & 0x01)) {
fdc_set_base(dev->fdc, BASE_ADDRESS(0));
fdc_set_irq(dev->fdc, IRQ(0) & 0xf);
fdc_set_dma_ch(dev->fdc, DMA(0) & 0x07);
fdc37m60x_log("SMC60x-FDC: BASE %04x IRQ %d DMA %d\n", BASE_ADDRESS(0), IRQ(0) & 0xf, DMA(0) & 0x07);
}
fdc_update_enh_mode(dev->fdc, dev->device_regs[0][0xf0] & 0x01);
fdc_update_densel_force(dev->fdc, (dev->device_regs[0][0xf1] & 0xc) >> 2);
fdc_update_rwc(dev->fdc, 3, (dev->device_regs[0][0xf2] & 0xc0) >> 6);
fdc_update_rwc(dev->fdc, 2, (dev->device_regs[0][0xf2] & 0x30) >> 4);
fdc_update_rwc(dev->fdc, 1, (dev->device_regs[0][0xf2] & 0x0c) >> 2);
fdc_update_rwc(dev->fdc, 0, (dev->device_regs[0][0xf2] & 0x03));
fdc_update_drvrate(dev->fdc, 0, (dev->device_regs[0][0xf4] & 0x18) >> 3);
fdc_update_drvrate(dev->fdc, 1, (dev->device_regs[0][0xf5] & 0x18) >> 3);
fdc_update_drvrate(dev->fdc, 2, (dev->device_regs[0][0xf6] & 0x18) >> 3);
fdc_update_drvrate(dev->fdc, 3, (dev->device_regs[0][0xf7] & 0x18) >> 3);
}
static void
fdc37m60x_uart_handler(uint8_t num, fdc37m60x_t *dev)
{
serial_remove(dev->uart[num & 1]);
if (ENABLED(4 + (num & 1)) || (POWER_CONTROL & (1 << (4 + (num & 1))))) {
serial_setup(dev->uart[num & 1], BASE_ADDRESS(4 + (num & 1)), IRQ(4 + (num & 1)) & 0xf);
fdc37m60x_log("SMC60x-UART%d: BASE %04x IRQ %d\n", num & 1, BASE_ADDRESS(4 + (num & 1)), IRQ(4 + (num & 1)) & 0xf);
}
}
void
fdc37m60x_lpt_handler(fdc37m60x_t *dev)
{
lpt1_remove();
if (ENABLED(3) || (POWER_CONTROL & 0x08)) {
lpt1_init(BASE_ADDRESS(3));
lpt1_irq(IRQ(3) & 0xf);
fdc37m60x_log("SMC60x-LPT: BASE %04x IRQ %d\n", BASE_ADDRESS(3), IRQ(3) & 0xf);
}
}
void
fdc37m60x_logical_device_handler(fdc37m60x_t *dev)
{
/* Register 07h:
Device 0: FDC
Device 3: LPT
Device 4: UART1
Device 5: UART2
*/
switch (CURRENT_LOGICAL_DEVICE) {
case 0x00:
fdc37m60x_fdc_handler(dev);
break;
case 0x03:
fdc37m60x_lpt_handler(dev);
break;
case 0x04:
fdc37m60x_uart_handler(0, dev);
break;
case 0x05:
fdc37m60x_uart_handler(1, dev);
break;
default:
break;
}
}
static void
fdc37m60x_reset(void *priv)
{
fdc37m60x_t *dev = (fdc37m60x_t *) priv;
memset(dev->regs, 0, sizeof(dev->regs));
for (uint8_t i = 0; i < 10; i++)
memset(dev->device_regs[i], 0, sizeof(dev->device_regs[i]));
dev->regs[0x20] = 0x47;
dev->regs[0x24] = 0x04;
dev->regs[0x26] = SIO_INDEX_PORT & 0xf;
dev->regs[0x27] = (SIO_INDEX_PORT >> 4) & 0xf;
/* FDC Registers */
dev->device_regs[0][0x60] = 0x03; /* Base Address */
dev->device_regs[0][0x61] = 0xf0;
dev->device_regs[0][0x70] = 0x06;
dev->device_regs[0][0x74] = 0x02;
dev->device_regs[0][0xf0] = 0x0e;
dev->device_regs[0][0xf2] = 0xff;
/* LPT Port */
dev->device_regs[3][0x74] = 0x04;
dev->device_regs[3][0xf0] = 0x3c;
/* UART1 */
dev->device_regs[4][0x74] = 0x04;
dev->device_regs[4][0xf1] = 0x02;
dev->device_regs[4][0xf2] = 0x03;
/* AUX */
dev->device_regs[8][0xc0] = 0x06;
dev->device_regs[8][0xc1] = 0x03;
fdc37m60x_fdc_handler(dev);
fdc37m60x_uart_handler(0, dev);
fdc37m60x_uart_handler(1, dev);
fdc37m60x_lpt_handler(dev);
}
static void
fdc37m60x_close(void *priv)
{
fdc37m60x_t *dev = (fdc37m60x_t *) priv;
free(dev);
}
static void *
fdc37m60x_init(const device_t *info)
{
fdc37m60x_t *dev = (fdc37m60x_t *) malloc(sizeof(fdc37m60x_t));
memset(dev, 0, sizeof(fdc37m60x_t));
SIO_INDEX_PORT = info->local;
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
io_sethandler(SIO_INDEX_PORT, 0x0002, fdc37m60x_read, NULL, NULL, fdc37m60x_write, NULL, NULL, dev);
fdc37m60x_reset(dev);
return dev;
}
const device_t fdc37m60x_device = {
.name = "SMSC FDC37M60X",
.internal_name = "fdc37m60x",
.flags = 0,
.local = FDC_PRIMARY_ADDR,
.init = fdc37m60x_init,
.close = fdc37m60x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37m60x_370_device = {
.name = "SMSC FDC37M60X with 10K Pull Up Resistor",
.internal_name = "fdc37m60x_370",
.flags = 0,
.local = FDC_SECONDARY_ADDR,
.init = fdc37m60x_init,
.close = fdc37m60x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_fdc37m60x.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,174 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Winbond W83787F/IF Super I/O Chip.
*
* Winbond W83787F Super I/O Chip
* Used by the Award 430HX
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/gameport.h>
#include <86box/sio.h>
#ifdef ENABLE_W83787_LOG
int w83787_do_log = ENABLE_W83787_LOG;
static void
w83787_log(const char *fmt, ...)
{
va_list ap;
if (w83787_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define w83787_log(fmt, ...)
#endif
#define FDDA_TYPE (dev->regs[7] & 3)
#define FDDB_TYPE ((dev->regs[7] >> 2) & 3)
#define FDDC_TYPE ((dev->regs[7] >> 4) & 3)
#define FDDD_TYPE ((dev->regs[7] >> 6) & 3)
#define FD_BOOT (dev->regs[8] & 3)
#define SWWP ((dev->regs[8] >> 4) & 1)
#define DISFDDWR ((dev->regs[8] >> 5) & 1)
#define EN3MODE ((dev->regs[9] >> 5) & 1)
#define DRV2EN_NEG (dev->regs[0xB] & 1) /* 0 = drive 2 installed */
#define INVERTZ ((dev->regs[0xB] >> 1) & 1) /* 0 = invert DENSEL polarity */
#define IDENT ((dev->regs[0xB] >> 3) & 1)
#define HEFERE ((dev->regs[0xC] >> 5) & 1)
#define HAS_IDE_FUNCTIONALITY dev->ide_function
typedef struct w83787f_t {
uint8_t tries;
uint8_t regs[42];
uint16_t reg_init;
int locked;
int rw_locked;
int cur_reg;
int key;
int ide_function;
int ide_start;
fdc_t *fdc;
serial_t *uart[2];
void *gameport;
} w83787f_t;
static void w83787f_write(uint16_t port, uint8_t val, void *priv);
static uint8_t w83787f_read(uint16_t port, void *priv);
static void
w83787f_remap(w83787f_t *dev)
{
io_removehandler(0x250, 0x0004,
w83787f_read, NULL, NULL, w83787f_write, NULL, NULL, dev);
io_sethandler(0x250, 0x0004,
w83787f_read, NULL, NULL, w83787f_write, NULL, NULL, dev);
dev->key = 0x88 | HEFERE;
}
#ifdef FIXME
/* FIXME: Implement EPP (and ECP) parallel port modes. */
static uint8_t
get_lpt_length(w83787f_t *dev)
{
uint8_t length = 4;
if (dev->regs[9] & 0x80) {
if (dev->regs[0] & 0x04)
length = 8; /* EPP mode. */
if (dev->regs[0] & 0x08)
length |= 0x80; /* ECP mode. */
}
return length;
}
#endif
static void
w83787f_serial_handler(w83787f_t *dev, int uart)
{
int urs0 = !!(dev->regs[1] & (1 << uart));
int urs1 = !!(dev->regs[1] & (4 << uart));
int urs2 = !!(dev->regs[3] & (8 >> uart));
int urs;
int irq = COM1_IRQ;
uint16_t addr = COM1_ADDR;
uint16_t enable = 1;
urs = (urs1 << 1) | urs0;
if (urs2) {
addr = uart ? COM1_ADDR : COM2_ADDR;
irq = uart ? COM1_IRQ : COM2_IRQ;
} else {
switch (urs) {
case 0:
addr = uart ? COM3_ADDR : COM4_ADDR;
irq = uart ? COM3_IRQ : COM4_IRQ;
break;
case 1:
addr = uart ? COM4_ADDR : COM3_ADDR;
irq = uart ? COM4_IRQ : COM3_IRQ;
break;
case 2:
addr = uart ? COM2_ADDR : COM1_ADDR;
irq = uart ? COM2_IRQ : COM1_IRQ;
break;
case 3:
default:
enable = 0;
break;
}
}
if (dev->regs[4] & (0x20 >> uart))
enable = 0;
serial_remove(dev->uart[uart]);
if (enable)
serial_setup(dev->uart[uart], addr, irq);
}
static void
w83787f_lpt_handler(w83787f_t *dev)
{
int ptras = (dev->regs[1] >> 4) & 0x03;
int irq = LPT1_IRQ;
uint16_t addr = LPT1_ADDR;
uint16_t enable = 1;
switch (ptras) {
case 0x00:
addr = LPT_MDA_ADDR;
irq = LPT_MDA_IRQ;
break;
case 0x01:
addr = LPT2_ADDR;
irq = LPT2_IRQ;
break;
case 0x02:
addr = LPT1_ADDR;
irq = LPT1_IRQ;
break;
case 0x03:
default:
enable = 0;
break;
}
if (dev->regs[4] & 0x80)
enable = 0;
lpt1_remove();
if (enable) {
lpt1_init(addr);
lpt1_irq(irq);
}
}
static void
w83787f_gameport_handler(w83787f_t *dev)
{
if (!(dev->regs[3] & 0x40) && !(dev->regs[4] & 0x40))
gameport_remap(dev->gameport, 0x201);
else
gameport_remap(dev->gameport, 0);
}
static void
w83787f_fdc_handler(w83787f_t *dev)
{
fdc_remove(dev->fdc);
if (!(dev->regs[0] & 0x20))
fdc_set_base(dev->fdc, (dev->regs[0] & 0x10) ? FDC_PRIMARY_ADDR : FDC_SECONDARY_ADDR);
fdc_set_power_down(dev->fdc, !!(dev->regs[6] & 0x08));
}
static void
w83787f_ide_handler(w83787f_t *dev)
{
if (dev->ide_function & 0x20) {
ide_sec_disable();
if (!(dev->regs[0] & 0x80)) {
ide_set_base(1, (dev->regs[0] & 0x40) ? 0x1f0 : 0x170);
ide_set_side(1, (dev->regs[0] & 0x40) ? 0x3f6 : 0x376);
ide_sec_enable();
}
} else {
ide_pri_disable();
if (!(dev->regs[0] & 0x80)) {
ide_set_base(0, (dev->regs[0] & 0x40) ? 0x1f0 : 0x170);
ide_set_side(0, (dev->regs[0] & 0x40) ? 0x3f6 : 0x376);
ide_pri_enable();
}
}
}
static void
w83787f_write(uint16_t port, uint8_t val, void *priv)
{
w83787f_t *dev = (w83787f_t *) priv;
uint8_t valxor = 0;
uint8_t max = 0x15;
if (port == 0x250) {
if (val == dev->key)
dev->locked = 1;
else
dev->locked = 0;
return;
} else if (port == 0x251) {
if (val <= max)
dev->cur_reg = val;
return;
} else {
if (dev->locked) {
if (dev->rw_locked && (dev->cur_reg <= 0x0b))
return;
if (dev->cur_reg == 6)
val &= 0xFB;
valxor = val ^ dev->regs[dev->cur_reg];
dev->regs[dev->cur_reg] = val;
} else
return;
}
switch (dev->cur_reg) {
case 0:
w83787_log("REG 00: %02X\n", val);
if ((valxor & 0xc0) && (HAS_IDE_FUNCTIONALITY))
w83787f_ide_handler(dev);
if (valxor & 0x30)
w83787f_fdc_handler(dev);
if (valxor & 0x0c)
w83787f_lpt_handler(dev);
break;
case 1:
if (valxor & 0x80)
fdc_set_swap(dev->fdc, (dev->regs[1] & 0x80) ? 1 : 0);
if (valxor & 0x30)
w83787f_lpt_handler(dev);
if (valxor & 0x0a)
w83787f_serial_handler(dev, 1);
if (valxor & 0x05)
w83787f_serial_handler(dev, 0);
break;
case 3:
if (valxor & 0x80)
w83787f_lpt_handler(dev);
if (valxor & 0x40)
w83787f_gameport_handler(dev);
if (valxor & 0x08)
w83787f_serial_handler(dev, 0);
if (valxor & 0x04)
w83787f_serial_handler(dev, 1);
break;
case 4:
if (valxor & 0x10)
w83787f_serial_handler(dev, 1);
if (valxor & 0x20)
w83787f_serial_handler(dev, 0);
if (valxor & 0x80)
w83787f_lpt_handler(dev);
if (valxor & 0x40)
w83787f_gameport_handler(dev);
break;
case 6:
if (valxor & 0x08)
w83787f_fdc_handler(dev);
break;
case 7:
if (valxor & 0x03)
fdc_update_rwc(dev->fdc, 0, FDDA_TYPE);
if (valxor & 0x0c)
fdc_update_rwc(dev->fdc, 1, FDDB_TYPE);
if (valxor & 0x30)
fdc_update_rwc(dev->fdc, 2, FDDC_TYPE);
if (valxor & 0xc0)
fdc_update_rwc(dev->fdc, 3, FDDD_TYPE);
break;
case 8:
if (valxor & 0x03)
fdc_update_boot_drive(dev->fdc, FD_BOOT);
if (valxor & 0x10)
fdc_set_swwp(dev->fdc, SWWP ? 1 : 0);
if (valxor & 0x20)
fdc_set_diswr(dev->fdc, DISFDDWR ? 1 : 0);
break;
case 9:
if (valxor & 0x20)
fdc_update_enh_mode(dev->fdc, EN3MODE ? 1 : 0);
if (valxor & 0x40)
dev->rw_locked = (val & 0x40) ? 1 : 0;
if (valxor & 0x80)
w83787f_lpt_handler(dev);
break;
case 0xB:
w83787_log("Writing %02X to CRB\n", val);
break;
case 0xC:
if (valxor & 0x20)
w83787f_remap(dev);
break;
default:
break;
}
}
static uint8_t
w83787f_read(uint16_t port, void *priv)
{
w83787f_t *dev = (w83787f_t *) priv;
uint8_t ret = 0xff;
if (dev->locked) {
if (port == 0x251)
ret = dev->cur_reg;
else if (port == 0x252) {
if (dev->cur_reg == 7)
ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2));
else if (!dev->rw_locked || (dev->cur_reg > 0x0b))
ret = dev->regs[dev->cur_reg];
}
}
return ret;
}
static void
w83787f_reset(w83787f_t *dev)
{
uint16_t hefere = dev->reg_init & 0x0100;
lpt1_remove();
lpt1_init(LPT1_ADDR);
lpt1_irq(LPT1_IRQ);
memset(dev->regs, 0, 0x2A);
if (HAS_IDE_FUNCTIONALITY) {
if (dev->ide_function & 0x20) {
dev->regs[0x00] = 0x90;
ide_sec_disable();
ide_set_base(1, 0x170);
ide_set_side(1, 0x376);
} else {
dev->regs[0x00] = 0xd0;
ide_pri_disable();
ide_set_base(0, 0x1f0);
ide_set_side(0, 0x3f6);
}
if (dev->ide_start) {
dev->regs[0x00] &= 0x7f;
if (dev->ide_function & 0x20)
ide_sec_enable();
else
ide_pri_enable();
}
} else
dev->regs[0x00] = 0xd0;
fdc_reset(dev->fdc);
w83787f_fdc_handler(dev);
dev->regs[0x01] = 0x2C;
dev->regs[0x03] = 0x70;
dev->regs[0x07] = 0xF5;
dev->regs[0x09] = dev->reg_init & 0xff;
dev->regs[0x0a] = 0x1F;
dev->regs[0x0c] = 0x0C | (hefere >> 3);
dev->regs[0x0d] = 0xA3;
gameport_remap(dev->gameport, 0);
serial_setup(dev->uart[0], COM1_ADDR, COM1_IRQ);
serial_setup(dev->uart[1], COM2_ADDR, COM2_IRQ);
w83787f_lpt_handler(dev);
dev->key = 0x88 | (hefere >> 8);
w83787f_remap(dev);
dev->locked = 0;
dev->rw_locked = 0;
}
static void
w83787f_close(void *priv)
{
w83787f_t *dev = (w83787f_t *) priv;
free(dev);
}
static void *
w83787f_init(const device_t *info)
{
w83787f_t *dev = (w83787f_t *) malloc(sizeof(w83787f_t));
memset(dev, 0, sizeof(w83787f_t));
HAS_IDE_FUNCTIONALITY = (info->local & 0x30);
dev->fdc = device_add(&fdc_at_winbond_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->gameport = gameport_add(&gameport_sio_1io_device);
if ((dev->ide_function & 0x30) == 0x10)
device_add(&ide_isa_device);
dev->ide_start = !!(info->local & 0x40);
dev->reg_init = info->local & 0x010f;
w83787f_reset(dev);
return dev;
}
const device_t w83787f_88h_device = {
.name = "Winbond W83787F/IF Super I/O",
.internal_name = "w83787f",
.flags = 0,
.local = 0x0009,
.init = w83787f_init,
.close = w83787f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t w83787f_device = {
.name = "Winbond W83787F/IF Super I/O",
.internal_name = "w83787f",
.flags = 0,
.local = 0x0109,
.init = w83787f_init,
.close = w83787f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t w83787f_ide_device = {
.name = "Winbond W83787F/IF Super I/O (With IDE)",
.internal_name = "w83787f_ide",
.flags = 0,
.local = 0x0119,
.init = w83787f_init,
.close = w83787f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t w83787f_ide_en_device = {
.name = "Winbond W83787F/IF Super I/O (With IDE Enabled)",
.internal_name = "w83787f_ide_en",
.flags = 0,
.local = 0x0159,
.init = w83787f_init,
.close = w83787f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t w83787f_ide_sec_device = {
.name = "Winbond W83787F/IF Super I/O (With Secondary IDE)",
.internal_name = "w83787f_ide_sec",
.flags = 0,
.local = 0x0139,
.init = w83787f_init,
.close = w83787f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_w83787f.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,606 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the National Semiconductor PC87311 Super I/O
*
*
*
* Authors: Tiseno100
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#define HAS_IDE_FUNCTIONALITY dev->ide_function
/* Basic Functionalities */
#define FUNCTION_ENABLE dev->regs[0x00]
#define FUNCTION_ADDRESS dev->regs[0x01]
#define POWER_TEST dev->regs[0x02]
/* Base Addresses */
#define LPT_BA (FUNCTION_ADDRESS & 0x03)
#define UART1_BA ((FUNCTION_ADDRESS >> 2) & 0x03)
#define UART2_BA ((FUNCTION_ADDRESS >> 4) & 0x03)
#define COM_BA ((FUNCTION_ADDRESS >> 6) & 0x03)
#ifdef ENABLE_PC87311_LOG
int pc87311_do_log = ENABLE_PC87311_LOG;
static void
pc87311_log(const char *fmt, ...)
{
va_list ap;
if (pc87311_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define pc87311_log(fmt, ...)
#endif
typedef struct pc87311_t {
uint8_t index;
uint8_t regs[256];
uint8_t cfg_lock;
uint8_t ide_function;
uint16_t base;
uint16_t irq;
fdc_t *fdc_controller;
serial_t *uart[2];
} pc87311_t;
void pc87311_fdc_handler(pc87311_t *dev);
void pc87311_uart_handler(uint8_t num, pc87311_t *dev);
void pc87311_lpt_handler(pc87311_t *dev);
void pc87311_ide_handler(pc87311_t *dev);
void pc87311_enable(pc87311_t *dev);
static void
pc87311_write(uint16_t addr, uint8_t val, void *priv)
{
pc87311_t *dev = (pc87311_t *) priv;
switch (addr) {
case 0x398:
case 0x26e:
dev->index = val;
break;
case 0x399:
case 0x26f:
switch (dev->index) {
case 0x00:
FUNCTION_ENABLE = val;
break;
case 0x01:
FUNCTION_ADDRESS = val;
break;
case 0x02:
POWER_TEST = val;
break;
default:
break;
}
break;
default:
break;
}
pc87311_enable(dev);
}
static uint8_t
pc87311_read(UNUSED(uint16_t addr), void *priv)
{
const pc87311_t *dev = (pc87311_t *) priv;
return dev->regs[dev->index];
}
void
pc87311_fdc_handler(pc87311_t *dev)
{
fdc_remove(dev->fdc_controller);
fdc_set_base(dev->fdc_controller, (FUNCTION_ENABLE & 0x20) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
pc87311_log("PC87311-FDC: BASE %04x\n", (FUNCTION_ENABLE & 0x20) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
}
uint16_t
com3(pc87311_t *dev)
{
switch (COM_BA) {
case 0:
return COM3_ADDR;
case 1:
return 0x0338;
case 2:
return COM4_ADDR;
case 3:
return 0x0220;
default:
return COM3_ADDR;
}
}
uint16_t
com4(pc87311_t *dev)
{
switch (COM_BA) {
case 0:
return COM4_ADDR;
case 1:
return 0x0238;
case 2:
return 0x02e0;
case 3:
return 0x0228;
default:
return COM4_ADDR;
}
}
void
pc87311_uart_handler(uint8_t num, pc87311_t *dev)
{
serial_remove(dev->uart[num & 1]);
switch (!(num & 1) ? UART1_BA : UART2_BA) {
case 0:
dev->base = COM1_ADDR;
dev->irq = COM1_IRQ;
break;
case 1:
dev->base = COM2_ADDR;
dev->irq = COM2_IRQ;
break;
case 2:
dev->base = com3(dev);
dev->irq = COM3_IRQ;
break;
case 3:
dev->base = com4(dev);
dev->irq = COM4_IRQ;
break;
default:
break;
}
serial_setup(dev->uart[num & 1], dev->base, dev->irq);
pc87311_log("PC87311-UART%01x: BASE %04x IRQ %01x\n", num & 1, dev->base, dev->irq);
}
void
pc87311_lpt_handler(pc87311_t *dev)
{
lpt1_remove();
switch (LPT_BA) {
case 0:
dev->base = LPT1_ADDR;
dev->irq = (POWER_TEST & 0x08) ? LPT1_IRQ : LPT2_IRQ;
break;
case 1:
dev->base = LPT_MDA_ADDR;
dev->irq = LPT_MDA_IRQ;
break;
case 2:
dev->base = LPT2_ADDR;
dev->irq = LPT2_IRQ;
break;
default:
break;
}
lpt1_init(dev->base);
lpt1_irq(dev->irq);
pc87311_log("PC87311-LPT: BASE %04x IRQ %01x\n", dev->base, dev->irq);
}
void
pc87311_ide_handler(pc87311_t *dev)
{
ide_pri_disable();
ide_sec_disable();
ide_set_base(0, 0x1f0);
ide_set_side(0, 0x3f6);
ide_pri_enable();
if (FUNCTION_ENABLE & 0x80) {
ide_set_base(1, 0x170);
ide_set_side(1, 0x376);
ide_sec_enable();
}
pc87311_log("PC87311-IDE: PRI %01x SEC %01x\n", (FUNCTION_ENABLE >> 6) & 1, (FUNCTION_ENABLE >> 7) & 1);
}
void
pc87311_enable(pc87311_t *dev)
{
(FUNCTION_ENABLE & 0x01) ? pc87311_lpt_handler(dev) : lpt1_remove();
(FUNCTION_ENABLE & 0x02) ? pc87311_uart_handler(0, dev) : serial_remove(dev->uart[0]);
(FUNCTION_ENABLE & 0x04) ? pc87311_uart_handler(1, dev) : serial_remove(dev->uart[1]);
(FUNCTION_ENABLE & 0x08) ? pc87311_fdc_handler(dev) : fdc_remove(dev->fdc_controller);
if (FUNCTION_ENABLE & 0x20)
pc87311_fdc_handler(dev);
if (HAS_IDE_FUNCTIONALITY) {
(FUNCTION_ENABLE & 0x40) ? pc87311_ide_handler(dev) : ide_pri_disable();
(FUNCTION_ADDRESS & 0x80) ? pc87311_ide_handler(dev) : ide_sec_disable();
}
}
static void
pc87311_close(void *priv)
{
pc87311_t *dev = (pc87311_t *) priv;
free(dev);
}
static void *
pc87311_init(const device_t *info)
{
pc87311_t *dev = (pc87311_t *) malloc(sizeof(pc87311_t));
memset(dev, 0, sizeof(pc87311_t));
/* Avoid conflicting with machines that make no use of the PC87311 Internal IDE */
HAS_IDE_FUNCTIONALITY = info->local;
dev->fdc_controller = device_add(&fdc_at_nsc_device);
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
if (HAS_IDE_FUNCTIONALITY)
device_add(&ide_isa_2ch_device);
io_sethandler(0x0398, 0x0002, pc87311_read, NULL, NULL, pc87311_write, NULL, NULL, dev);
io_sethandler(0x026e, 0x0002, pc87311_read, NULL, NULL, pc87311_write, NULL, NULL, dev);
pc87311_enable(dev);
return dev;
}
const device_t pc87311_device = {
.name = "National Semiconductor PC87311",
.internal_name = "pc87311",
.flags = 0,
.local = 0,
.init = pc87311_init,
.close = pc87311_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t pc87311_ide_device = {
.name = "National Semiconductor PC87311 with IDE functionality",
.internal_name = "pc87311_ide",
.flags = 0,
.local = 1,
.init = pc87311_init,
.close = pc87311_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_pc87311.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,337 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C67X Super I/O Chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include "cpu.h"
#include <86box/sio.h>
#include <86box/plat_unused.h>
#define AB_RST 0x80
typedef struct fdc37c67x_t {
uint8_t chip_id;
uint8_t is_apm;
uint8_t tries;
uint8_t gpio_regs[2];
uint8_t auxio_reg;
uint8_t regs[48];
uint8_t ld_regs[11][256];
uint16_t gpio_base; /* Set to EA */
uint16_t auxio_base;
uint16_t sio_base;
int locked;
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
} fdc37c67x_t;
static void fdc37c67x_write(uint16_t port, uint8_t val, void *priv);
static uint8_t fdc37c67x_read(uint16_t port, void *priv);
static uint16_t
make_port(fdc37c67x_t *dev, uint8_t ld)
{
uint16_t r0 = dev->ld_regs[ld][0x60];
uint16_t r1 = dev->ld_regs[ld][0x61];
uint16_t p = (r0 << 8) + r1;
return p;
}
static uint8_t
fdc37c67x_auxio_read(UNUSED(uint16_t port), void *priv)
{
const fdc37c67x_t *dev = (fdc37c67x_t *) priv;
return dev->auxio_reg;
}
static void
fdc37c67x_auxio_write(UNUSED(uint16_t port), uint8_t val, void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
dev->auxio_reg = val;
}
static uint8_t
fdc37c67x_gpio_read(uint16_t port, void *priv)
{
const fdc37c67x_t *dev = (fdc37c67x_t *) priv;
uint8_t ret = 0xff;
ret = dev->gpio_regs[port & 1];
return ret;
}
static void
fdc37c67x_gpio_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
if (!(port & 1))
dev->gpio_regs[0] = (dev->gpio_regs[0] & 0xfc) | (val & 0x03);
}
static void
fdc37c67x_fdc_handler(fdc37c67x_t *dev)
{
uint16_t ld_port = 0;
uint8_t global_enable = !!(dev->regs[0x22] & (1 << 0));
uint8_t local_enable = !!dev->ld_regs[0][0x30];
fdc_remove(dev->fdc);
if (global_enable && local_enable) {
ld_port = make_port(dev, 0) & 0xFFF8;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
fdc_set_base(dev->fdc, ld_port);
}
}
static void
fdc37c67x_lpt_handler(fdc37c67x_t *dev)
{
uint16_t ld_port = 0;
uint8_t global_enable = !!(dev->regs[0x22] & (1 << 3));
uint8_t local_enable = !!dev->ld_regs[3][0x30];
uint8_t lpt_irq = dev->ld_regs[3][0x70];
if (lpt_irq > 15)
lpt_irq = 0xff;
lpt1_remove();
if (global_enable && local_enable) {
ld_port = make_port(dev, 3) & 0xFFFC;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FFC))
lpt1_init(ld_port);
}
lpt1_irq(lpt_irq);
}
static void
fdc37c67x_serial_handler(fdc37c67x_t *dev, int uart)
{
uint16_t ld_port = 0;
uint8_t uart_no = 4 + uart;
uint8_t global_enable = !!(dev->regs[0x22] & (1 << uart_no));
uint8_t local_enable = !!dev->ld_regs[uart_no][0x30];
serial_remove(dev->uart[uart]);
if (global_enable && local_enable) {
ld_port = make_port(dev, uart_no) & 0xFFF8;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
serial_setup(dev->uart[uart], ld_port, dev->ld_regs[uart_no][0x70]);
}
}
static void
fdc37c67x_auxio_handler(fdc37c67x_t *dev)
{
uint16_t ld_port = 0;
uint8_t local_enable = !!dev->ld_regs[8][0x30];
io_removehandler(dev->auxio_base, 0x0001,
fdc37c67x_auxio_read, NULL, NULL, fdc37c67x_auxio_write, NULL, NULL, dev);
if (local_enable) {
dev->auxio_base = ld_port = make_port(dev, 8);
if ((ld_port >= 0x0100) && (ld_port <= 0x0FFF))
io_sethandler(dev->auxio_base, 0x0001,
fdc37c67x_auxio_read, NULL, NULL, fdc37c67x_auxio_write, NULL, NULL, dev);
}
}
static void
fdc37c67x_sio_handler(UNUSED(fdc37c67x_t *dev))
{
#if 0
if (dev->sio_base) {
io_removehandler(dev->sio_base, 0x0002,
fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
}
dev->sio_base = (((uint16_t) dev->regs[0x27]) << 8) | dev->regs[0x26];
if (dev->sio_base) {
io_sethandler(dev->sio_base, 0x0002,
fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
}
#endif
}
static void
fdc37c67x_gpio_handler(fdc37c67x_t *dev)
{
uint16_t ld_port = 0;
uint8_t local_enable;
local_enable = !!(dev->regs[0x03] & 0x80);
io_removehandler(dev->gpio_base, 0x0002,
fdc37c67x_gpio_read, NULL, NULL, fdc37c67x_gpio_write, NULL, NULL, dev);
if (local_enable) {
switch (dev->regs[0x03] & 0x03) {
case 0:
ld_port = 0xe0;
break;
case 1:
ld_port = 0xe2;
break;
case 2:
ld_port = 0xe4;
break;
case 3:
ld_port = 0xea; /* Default */
break;
default:
break;
}
dev->gpio_base = ld_port;
if (ld_port > 0x0000)
io_sethandler(dev->gpio_base, 0x0002,
fdc37c67x_gpio_read, NULL, NULL, fdc37c67x_gpio_write, NULL, NULL, dev);
}
}
static void
fdc37c67x_smi_handler(fdc37c67x_t *dev)
{
/* TODO: 8042 P1.2 SMI#. */
pic_reset_smi_irq_mask();
pic_set_smi_irq_mask(dev->ld_regs[3][0x70], dev->ld_regs[8][0xb4] & 0x02);
pic_set_smi_irq_mask(dev->ld_regs[5][0x70], dev->ld_regs[8][0xb4] & 0x04);
pic_set_smi_irq_mask(dev->ld_regs[4][0x70], dev->ld_regs[8][0xb4] & 0x08);
pic_set_smi_irq_mask(dev->ld_regs[0][0x70], dev->ld_regs[8][0xb4] & 0x10);
pic_set_smi_irq_mask(12, dev->ld_regs[8][0xb5] & 0x01);
pic_set_smi_irq_mask(1, dev->ld_regs[8][0xb5] & 0x02);
pic_set_smi_irq_mask(10, dev->ld_regs[8][0xb5] & 0x80);
}
static void
fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t valxor = 0x00;
uint8_t keep = 0x00;
if (index) {
if ((val == 0x55) && !dev->locked) {
if (dev->tries) {
dev->locked = 1;
fdc_3f1_enable(dev->fdc, 0);
dev->tries = 0;
} else
dev->tries++;
} else {
if (dev->locked) {
if (val == 0xaa) {
dev->locked = 0;
fdc_3f1_enable(dev->fdc, 1);
return;
}
dev->cur_reg = val;
} else {
if (dev->tries)
dev->tries = 0;
}
}
return;
} else {
if (dev->locked) {
if (dev->cur_reg < 48) {
valxor = val ^ dev->regs[dev->cur_reg];
if ((val == 0x20) || (val == 0x21))
return;
dev->regs[dev->cur_reg] = val;
} else {
valxor = val ^ dev->ld_regs[dev->regs[7]][dev->cur_reg];
if (((dev->cur_reg & 0xF0) == 0x70) && (dev->regs[7] < 4))
return;
/* Block writes to some logical devices. */
if (dev->regs[7] > 0x0a)
return;
else
switch (dev->regs[7]) {
case 0x01:
case 0x02:
case 0x07:
return;
default:
break;
}
dev->ld_regs[dev->regs[7]][dev->cur_reg] = val | keep;
}
} else
return;
}
if (dev->cur_reg < 48) {
switch (dev->cur_reg) {
case 0x03:
if (valxor & 0x83)
fdc37c67x_gpio_handler(dev);
dev->regs[0x03] &= 0x83;
break;
case 0x22:
if (valxor & 0x01)
fdc37c67x_fdc_handler(dev);
if (valxor & 0x08)
fdc37c67x_lpt_handler(dev);
if (valxor & 0x10)
fdc37c67x_serial_handler(dev, 0);
if (valxor & 0x20)
fdc37c67x_serial_handler(dev, 1);
break;
case 0x26:
case 0x27:
fdc37c67x_sio_handler(dev);
break;
default:
break;
}
return;
}
switch (dev->regs[7]) {
case 0:
/* FDD */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x01;
if (valxor)
fdc37c67x_fdc_handler(dev);
break;
case 0xF0:
if (valxor & 0x01)
fdc_update_enh_mode(dev->fdc, val & 0x01);
if (valxor & 0x10)
fdc_set_swap(dev->fdc, (val & 0x10) >> 4);
break;
case 0xF1:
if (valxor & 0xC)
fdc_update_densel_force(dev->fdc, (val & 0xc) >> 2);
break;
case 0xF2:
if (valxor & 0xC0)
fdc_update_rwc(dev->fdc, 3, (val & 0xc0) >> 6);
if (valxor & 0x30)
fdc_update_rwc(dev->fdc, 2, (val & 0x30) >> 4);
if (valxor & 0x0C)
fdc_update_rwc(dev->fdc, 1, (val & 0x0c) >> 2);
if (valxor & 0x03)
fdc_update_rwc(dev->fdc, 0, (val & 0x03));
break;
case 0xF4:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 0, (val & 0x18) >> 3);
break;
case 0xF5:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 1, (val & 0x18) >> 3);
break;
case 0xF6:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 2, (val & 0x18) >> 3);
break;
case 0xF7:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 3, (val & 0x18) >> 3);
break;
default:
break;
}
break;
case 3:
/* Parallel port */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x08;
if (valxor)
fdc37c67x_lpt_handler(dev);
if (dev->cur_reg == 0x70)
fdc37c67x_smi_handler(dev);
break;
default:
break;
}
break;
case 4:
/* Serial port 1 */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x10;
if (valxor)
fdc37c67x_serial_handler(dev, 0);
if (dev->cur_reg == 0x70)
fdc37c67x_smi_handler(dev);
break;
default:
break;
}
break;
case 5:
/* Serial port 2 */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x20;
if (valxor)
fdc37c67x_serial_handler(dev, 1);
if (dev->cur_reg == 0x70)
fdc37c67x_smi_handler(dev);
break;
default:
break;
}
break;
case 8:
/* Auxiliary I/O */
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if (valxor)
fdc37c67x_auxio_handler(dev);
break;
case 0xb4:
case 0xb5:
fdc37c67x_smi_handler(dev);
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
fdc37c67x_read(uint16_t port, void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t ret = 0xff;
uint16_t smi_stat = pic_get_smi_irq_status();
int f_irq = dev->ld_regs[0][0x70];
int p_irq = dev->ld_regs[3][0x70];
int s1_irq = dev->ld_regs[4][0x70];
int s2_irq = dev->ld_regs[5][0x70];
if (dev->locked) {
if (index)
ret = dev->cur_reg;
else {
if (dev->cur_reg < 0x30) {
if (dev->cur_reg == 0x20)
ret = dev->chip_id;
else
ret = dev->regs[dev->cur_reg];
} else {
if ((dev->regs[7] == 0) && (dev->cur_reg == 0xF2)) {
ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) | (fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6));
} else
ret = dev->ld_regs[dev->regs[7]][dev->cur_reg];
/* TODO: 8042 P1.2 SMI#. */
if ((dev->regs[7] == 8) && (dev->cur_reg == 0xb6)) {
ret = dev->ld_regs[dev->regs[7]][dev->cur_reg] & 0xe1;
ret |= ((!!(smi_stat & (1 << p_irq))) << 1);
ret |= ((!!(smi_stat & (1 << s2_irq))) << 2);
ret |= ((!!(smi_stat & (1 << s1_irq))) << 3);
ret |= ((!!(smi_stat & (1 << f_irq))) << 4);
} else if ((dev->regs[7] == 8) && (dev->cur_reg == 0xb7)) {
ret = dev->ld_regs[dev->regs[7]][dev->cur_reg] & 0xec;
ret |= ((!!(smi_stat & (1 << 12))) << 0);
ret |= ((!!(smi_stat & (1 << 1))) << 1);
ret |= ((!!(smi_stat & (1 << 10))) << 4);
}
}
}
}
return ret;
}
static void
fdc37c67x_reset(fdc37c67x_t *dev)
{
memset(dev->regs, 0, 48);
dev->regs[0x03] = 0x03;
dev->regs[0x20] = dev->chip_id;
dev->regs[0x22] = 0x39;
dev->regs[0x24] = 0x04;
dev->regs[0x26] = 0xf0;
dev->regs[0x27] = 0x03;
for (uint8_t i = 0; i < 11; i++)
memset(dev->ld_regs[i], 0, 256);
/* Logical device 0: FDD */
dev->ld_regs[0][0x30] = 1;
dev->ld_regs[0][0x60] = 3;
dev->ld_regs[0][0x61] = 0xf0;
dev->ld_regs[0][0x70] = 6;
dev->ld_regs[0][0x74] = 2;
dev->ld_regs[0][0xf0] = 0x0e;
dev->ld_regs[0][0xf2] = 0xff;
/* Logical device 3: Parallel Port */
dev->ld_regs[3][0x30] = 1;
dev->ld_regs[3][0x60] = 3;
dev->ld_regs[3][0x61] = 0x78;
dev->ld_regs[3][0x70] = 7;
dev->ld_regs[3][0x74] = 4;
dev->ld_regs[3][0xf0] = 0x3c;
/* Logical device 4: Serial Port 1 */
dev->ld_regs[4][0x30] = 1;
dev->ld_regs[4][0x60] = 3;
dev->ld_regs[4][0x61] = 0xf8;
dev->ld_regs[4][0x70] = 4;
dev->ld_regs[4][0xf0] = 3;
serial_setup(dev->uart[0], COM1_ADDR, dev->ld_regs[4][0x70]);
/* Logical device 5: Serial Port 2 */
dev->ld_regs[5][0x30] = 1;
dev->ld_regs[5][0x60] = 2;
dev->ld_regs[5][0x61] = 0xf8;
dev->ld_regs[5][0x70] = 3;
dev->ld_regs[5][0x74] = 4;
dev->ld_regs[5][0xf1] = 2;
dev->ld_regs[5][0xf2] = 3;
serial_setup(dev->uart[1], COM2_ADDR, dev->ld_regs[5][0x70]);
/* Logical device 7: Keyboard */
dev->ld_regs[7][0x30] = 1;
dev->ld_regs[7][0x61] = 0x60;
dev->ld_regs[7][0x70] = 1;
dev->ld_regs[7][0x72] = 12;
/* Logical device 8: Auxiliary I/O */
dev->ld_regs[8][0xc0] = 6;
dev->ld_regs[8][0xc1] = 3;
fdc37c67x_gpio_handler(dev);
fdc37c67x_lpt_handler(dev);
fdc37c67x_serial_handler(dev, 0);
fdc37c67x_serial_handler(dev, 1);
fdc37c67x_auxio_handler(dev);
fdc37c67x_sio_handler(dev);
fdc_reset(dev->fdc);
fdc37c67x_fdc_handler(dev);
dev->locked = 0;
}
static void
fdc37c67x_close(void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
free(dev);
}
static void *
fdc37c67x_init(const device_t *info)
{
fdc37c67x_t *dev = (fdc37c67x_t *) malloc(sizeof(fdc37c67x_t));
memset(dev, 0, sizeof(fdc37c67x_t));
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->chip_id = info->local & 0xff;
dev->gpio_regs[0] = 0xff;
#if 0
dev->gpio_regs[1] = (info->local == 0x0030) ? 0xff : 0xfd;
#endif
dev->gpio_regs[1] = (dev->chip_id == 0x30) ? 0xff : 0xfd;
fdc37c67x_reset(dev);
io_sethandler(FDC_SECONDARY_ADDR, 0x0002,
fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
io_sethandler(FDC_PRIMARY_ADDR, 0x0002,
fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
return dev;
}
const device_t fdc37c67x_device = {
.name = "SMC FDC37C67X Super I/O",
.internal_name = "fdc37c67x",
.flags = 0,
.local = 0x40,
.init = fdc37c67x_init,
.close = fdc37c67x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_fdc37c67x.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,057 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the NatSemi PC87332 Super I/O chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct pc87332_t {
uint8_t tries;
uint8_t has_ide;
uint8_t fdc_on;
uint8_t regs[15];
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
} pc87332_t;
static void
lpt1_handler(pc87332_t *dev)
{
int temp;
uint16_t lpt_port = LPT1_ADDR;
uint8_t lpt_irq = LPT2_IRQ;
temp = dev->regs[0x01] & 3;
switch (temp) {
case 0:
lpt_port = LPT1_ADDR;
lpt_irq = (dev->regs[0x02] & 0x08) ? LPT1_IRQ : LPT2_IRQ;
break;
case 1:
lpt_port = LPT_MDA_ADDR;
lpt_irq = LPT_MDA_IRQ;
break;
case 2:
lpt_port = LPT2_ADDR;
lpt_irq = LPT2_IRQ;
break;
case 3:
lpt_port = 0x000;
lpt_irq = 0xff;
break;
default:
break;
}
if (lpt_port)
lpt1_init(lpt_port);
lpt1_irq(lpt_irq);
}
static void
serial_handler(pc87332_t *dev, int uart)
{
int temp;
temp = (dev->regs[1] >> (2 << uart)) & 3;
switch (temp) {
case 0:
serial_setup(dev->uart[uart], COM1_ADDR, 4);
break;
case 1:
serial_setup(dev->uart[uart], COM2_ADDR, 3);
break;
case 2:
switch ((dev->regs[1] >> 6) & 3) {
case 0:
serial_setup(dev->uart[uart], COM3_ADDR, COM3_IRQ);
break;
case 1:
serial_setup(dev->uart[uart], 0x338, COM3_IRQ);
break;
case 2:
serial_setup(dev->uart[uart], COM4_ADDR, COM3_IRQ);
break;
case 3:
serial_setup(dev->uart[uart], 0x220, COM3_IRQ);
break;
default:
break;
}
break;
case 3:
switch ((dev->regs[1] >> 6) & 3) {
case 0:
serial_setup(dev->uart[uart], COM4_ADDR, COM4_IRQ);
break;
case 1:
serial_setup(dev->uart[uart], 0x238, COM4_IRQ);
break;
case 2:
serial_setup(dev->uart[uart], 0x2e0, COM4_IRQ);
break;
case 3:
serial_setup(dev->uart[uart], 0x228, COM4_IRQ);
break;
default:
break;
}
break;
default:
break;
}
}
static void
ide_handler(pc87332_t *dev)
{
/* TODO: Make an ide_disable(channel) and ide_enable(channel) so we can simplify this. */
if (dev->has_ide == 2) {
ide_sec_disable();
ide_set_base(1, (dev->regs[0x00] & 0x80) ? 0x170 : 0x1f0);
ide_set_side(1, (dev->regs[0x00] & 0x80) ? 0x376 : 0x3f6);
if (dev->regs[0x00] & 0x40)
ide_sec_enable();
} else if (dev->has_ide == 1) {
ide_pri_disable();
ide_set_base(0, (dev->regs[0x00] & 0x80) ? 0x170 : 0x1f0);
ide_set_side(0, (dev->regs[0x00] & 0x80) ? 0x376 : 0x3f6);
if (dev->regs[0x00] & 0x40)
ide_pri_enable();
}
}
static void
pc87332_write(uint16_t port, uint8_t val, void *priv)
{
pc87332_t *dev = (pc87332_t *) priv;
uint8_t index;
uint8_t valxor;
index = (port & 1) ? 0 : 1;
if (index) {
dev->cur_reg = val & 0x1f;
dev->tries = 0;
return;
} else {
if (dev->tries) {
valxor = val ^ dev->regs[dev->cur_reg];
dev->tries = 0;
if ((dev->cur_reg <= 14) && (dev->cur_reg != 8))
dev->regs[dev->cur_reg] = val;
else
return;
} else {
dev->tries++;
return;
}
}
switch (dev->cur_reg) {
case 0:
if (valxor & 1) {
lpt1_remove();
if ((val & 1) && !(dev->regs[2] & 1))
lpt1_handler(dev);
}
if (valxor & 2) {
serial_remove(dev->uart[0]);
if ((val & 2) && !(dev->regs[2] & 1))
serial_handler(dev, 0);
}
if (valxor & 4) {
serial_remove(dev->uart[1]);
if ((val & 4) && !(dev->regs[2] & 1))
serial_handler(dev, 1);
}
if (valxor & 0x28) {
fdc_remove(dev->fdc);
if ((val & 8) && !(dev->regs[2] & 1))
fdc_set_base(dev->fdc, (val & 0x20) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
}
if (dev->has_ide && (valxor & 0xc0))
ide_handler(dev);
break;
case 1:
if (valxor & 3) {
lpt1_remove();
if ((dev->regs[0] & 1) && !(dev->regs[2] & 1))
lpt1_handler(dev);
}
if (valxor & 0xcc) {
serial_remove(dev->uart[0]);
if ((dev->regs[0] & 2) && !(dev->regs[2] & 1))
serial_handler(dev, 0);
}
if (valxor & 0xf0) {
serial_remove(dev->uart[1]);
if ((dev->regs[0] & 4) && !(dev->regs[2] & 1))
serial_handler(dev, 1);
}
break;
case 2:
if (valxor & 1) {
lpt1_remove();
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
fdc_remove(dev->fdc);
if (!(val & 1)) {
if (dev->regs[0] & 1)
lpt1_handler(dev);
if (dev->regs[0] & 2)
serial_handler(dev, 0);
if (dev->regs[0] & 4)
serial_handler(dev, 1);
if (dev->regs[0] & 8)
fdc_set_base(dev->fdc, (dev->regs[0] & 0x20) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
}
}
if (valxor & 8) {
lpt1_remove();
if ((dev->regs[0] & 1) && !(dev->regs[2] & 1))
lpt1_handler(dev);
}
break;
default:
break;
}
}
uint8_t
pc87332_read(uint16_t port, void *priv)
{
pc87332_t *dev = (pc87332_t *) priv;
uint8_t ret = 0xff;
uint8_t index;
index = (port & 1) ? 0 : 1;
dev->tries = 0;
if (index)
ret = dev->cur_reg & 0x1f;
else {
if (dev->cur_reg == 8)
ret = 0x10;
else if (dev->cur_reg < 14)
ret = dev->regs[dev->cur_reg];
}
return ret;
}
void
pc87332_reset(pc87332_t *dev)
{
memset(dev->regs, 0, 15);
dev->regs[0x00] = dev->fdc_on ? 0x4f : 0x07;
if (dev->has_ide == 2)
dev->regs[0x00] |= 0x80;
dev->regs[0x01] = 0x10;
dev->regs[0x03] = 0x01;
dev->regs[0x05] = 0x0D;
dev->regs[0x08] = 0x70;
/*
0 = 360 rpm @ 500 kbps for 3.5"
1 = Default, 300 rpm @ 500, 300, 250, 1000 kbps for 3.5"
*/
lpt1_remove();
lpt1_handler(dev);
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
serial_handler(dev, 0);
serial_handler(dev, 1);
fdc_reset(dev->fdc);
if (!dev->fdc_on)
fdc_remove(dev->fdc);
if (dev->has_ide)
ide_handler(dev);
}
static void
pc87332_close(void *priv)
{
pc87332_t *dev = (pc87332_t *) priv;
free(dev);
}
static void *
pc87332_init(const device_t *info)
{
pc87332_t *dev = (pc87332_t *) malloc(sizeof(pc87332_t));
memset(dev, 0, sizeof(pc87332_t));
dev->fdc = device_add(&fdc_at_nsc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->has_ide = (info->local >> 8) & 0xff;
dev->fdc_on = (info->local >> 16) & 0xff;
pc87332_reset(dev);
if ((info->local & 0xff) == 0x01) {
io_sethandler(0x398, 0x0002,
pc87332_read, NULL, NULL, pc87332_write, NULL, NULL, dev);
} else {
io_sethandler(0x02e, 0x0002,
pc87332_read, NULL, NULL, pc87332_write, NULL, NULL, dev);
}
return dev;
}
const device_t pc87332_device = {
.name = "National Semiconductor PC87332 Super I/O",
.internal_name = "pc87332",
.flags = 0,
.local = 0x00,
.init = pc87332_init,
.close = pc87332_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t pc87332_398_device = {
.name = "National Semiconductor PC87332 Super I/O (Port 398h)",
.internal_name = "pc87332_398",
.flags = 0,
.local = 0x01,
.init = pc87332_init,
.close = pc87332_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t pc87332_398_ide_device = {
.name = "National Semiconductor PC87332 Super I/O (Port 398h) (With IDE)",
.internal_name = "pc87332_398_ide",
.flags = 0,
.local = 0x101,
.init = pc87332_init,
.close = pc87332_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t pc87332_398_ide_sec_device = {
.name = "National Semiconductor PC87332 Super I/O (Port 398h) (With Secondary IDE)",
.internal_name = "pc87332_398_ide_sec",
.flags = 0,
.local = 0x201,
.init = pc87332_init,
.close = pc87332_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t pc87332_398_ide_fdcon_device = {
.name = "National Semiconductor PC87332 Super I/O (Port 398h) (With IDE and FDC on)",
.internal_name = "pc87332_398_ide_fdcon",
.flags = 0,
.local = 0x10101,
.init = pc87332_init,
.close = pc87332_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_pc87332.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,383 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C669 Super I/O Chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct fdc37c669_t {
uint8_t id;
uint8_t tries;
uint8_t regs[42];
int locked;
int rw_locked;
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
} fdc37c669_t;
static int next_id = 0;
#ifdef ENABLE_FDC37C669_LOG
int fdc37c669_do_log = ENABLE_FDC37C669_LOG;
static void
fdc37c669_log(const char *fmt, ...)
{
va_list ap;
if (fdc37c669_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define fdc37c669_log(fmt, ...)
#endif
static void
fdc37c669_fdc_handler(fdc37c669_t *dev)
{
fdc_remove(dev->fdc);
if (dev->regs[0x20] & 0xc0)
fdc_set_base(dev->fdc, ((uint16_t) dev->regs[0x20]) << 2);
}
static void
fdc37c669_uart_handler(fdc37c669_t *dev, uint8_t uart)
{
uint8_t uart_reg = 0x24 + uart;
uint8_t pwrdn_mask = 0x08 << (uart << 2);
uint8_t uart_shift = ((uart ^ 1) << 2);
serial_remove(dev->uart[uart]);
if ((dev->regs[0x02] & pwrdn_mask) && (dev->regs[uart_reg] & 0xc0))
serial_setup(dev->uart[0], ((uint16_t) dev->regs[0x24]) << 2,
(dev->regs[0x28] >> uart_shift) & 0x0f);
}
static double
fdc37c669_uart_get_clock_src(fdc37c669_t *dev, uint8_t uart)
{
double clock_srcs[4] = { 24000000.0 / 13.0, 24000000.0 / 12.0, 24000000.0 / 3.0, 24000000.0 / 3.0 };
double ret;
uint8_t clock_src_0 = !!(dev->regs[0x04] & (0x10 << uart));
uint8_t clock_src_1 = !!(dev->regs[0x0c] & (0x40 << uart));
uint8_t clock_src = clock_src_0 | (clock_src_1 << 1);
ret = clock_srcs[clock_src];
return ret;
}
static void
fdc37c669_lpt_handler(fdc37c669_t *dev)
{
uint8_t mask = ~(dev->regs[0x04] & 0x01);
lpt_port_remove(dev->id);
if ((dev->regs[0x01] & 0x04) && (dev->regs[0x23] >= 0x40))
lpt_port_init(dev->id, ((uint16_t) (dev->regs[0x23] & mask)) << 2);
}
static void
fdc37c669_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c669_t *dev = (fdc37c669_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t valxor = val ^ dev->regs[dev->cur_reg];
fdc37c669_log("[%04X:%08X] [W] %04X = %02X (%i, %i)\n", CS, cpu_state.pc, port, val,
dev->tries, dev->locked);
if (index) {
if ((val == 0x55) && !dev->locked) {
dev->tries = (dev->tries + 1) & 1;
if (!dev->tries)
dev->locked = 1;
} else {
if (dev->locked) {
if (val == 0xaa)
dev->locked = 0;
else
dev->cur_reg = val;
} else
dev->tries = 0;
}
} else if (!dev->rw_locked || (dev->cur_reg > 0x0f)) switch (dev->cur_reg) {
case 0x00:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x74) | (val & 0x8b);
if (!dev->id && (valxor & 8))
fdc_set_power_down(dev->fdc, !(val & 0x08));
break;
case 0x01:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x73) | (val & 0x8c);
if (valxor & 0x04)
fdc37c669_lpt_handler(dev);
if (valxor & 0x80)
dev->rw_locked = !(val & 0x80);
break;
case 0x02:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x77) | (val & 0x88);
if (valxor & 0x08)
fdc37c669_uart_handler(dev, 0);
if (valxor & 0x80)
fdc37c669_uart_handler(dev, 1);
break;
case 0x03:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x08) | (val & 0xf7);
if (!dev->id && (valxor & 0x02))
fdc_update_enh_mode(dev->fdc, !!(val & 0x02));
break;
case 0x04:
dev->regs[dev->cur_reg] = val;
if (valxor & 0x03)
fdc37c669_lpt_handler(dev);
if (valxor & 0x10)
serial_set_clock_src(dev->uart[0], fdc37c669_uart_get_clock_src(dev, 0));
if (valxor & 0x20)
serial_set_clock_src(dev->uart[1], fdc37c669_uart_get_clock_src(dev, 1));
break;
case 0x05:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x83) | (val & 0x7c);
if (!dev->id && (valxor & 0x18))
fdc_update_densel_force(dev->fdc, (val & 0x18) >> 3);
if (!dev->id && (valxor & 0x20))
fdc_set_swap(dev->fdc, (val & 0x20) >> 5);
break;
case 0x06:
dev->regs[dev->cur_reg] = val;
break;
case 0x07:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x06) | (val & 0xf9);
break;
case 0x08:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x0f) | (val & 0xf0);
break;
case 0x09:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x38) | (val & 0xc7);
break;
case 0x0a:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0xf0) | (val & 0x0f);
break;
case 0x0b:
dev->regs[dev->cur_reg] = val;
if (!dev->id && (valxor & 0x03))
fdc_update_rwc(dev->fdc, 0, val & 0x03);
if (!dev->id && (valxor & 0x0c))
fdc_update_rwc(dev->fdc, 1, (val & 0x0c) >> 2);
break;
case 0x0c:
dev->regs[dev->cur_reg] = val;
if (valxor & 0x40)
serial_set_clock_src(dev->uart[0], fdc37c669_uart_get_clock_src(dev, 0));
if (valxor & 0x80)
serial_set_clock_src(dev->uart[1], fdc37c669_uart_get_clock_src(dev, 1));
break;
case 0x0f:
case 0x12 ... 0x1f:
dev->regs[dev->cur_reg] = val;
break;
case 0x10:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x07) | (val & 0xf8);
break;
case 0x11:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0xfc) | (val & 0x03);
break;
case 0x20:
dev->regs[dev->cur_reg] = val & 0xfc;
if (!dev->id && (valxor & 0xfc))
fdc37c669_fdc_handler(dev);
break;
case 0x21:
dev->regs[dev->cur_reg] = val & 0xfc;
break;
case 0x22:
dev->regs[dev->cur_reg] = (dev->regs[dev->cur_reg] & 0x03) | (val & 0xfc);
break;
case 0x23:
dev->regs[dev->cur_reg] = val;
if (valxor)
fdc37c669_lpt_handler(dev);
break;
case 0x24:
dev->regs[dev->cur_reg] = val & 0xfe;
if (valxor & 0xfe)
fdc37c669_uart_handler(dev, 0);
break;
case 0x25:
dev->regs[dev->cur_reg] = val & 0xfe;
if (valxor & 0xfe)
fdc37c669_uart_handler(dev, 1);
break;
case 0x26:
dev->regs[dev->cur_reg] = val;
if (valxor & 0xf0)
fdc_set_dma_ch(dev->fdc, val >> 4);
break;
case 0x27:
dev->regs[dev->cur_reg] = val;
if (valxor & 0xf0)
fdc_set_irq(dev->fdc, val >> 4);
if (valxor & 0x0f)
lpt_port_irq(dev->id, val & 0x0f);
break;
case 0x28:
dev->regs[dev->cur_reg] = val;
if (valxor & 0xf0)
fdc37c669_uart_handler(dev, 0);
if (valxor & 0x0f)
fdc37c669_uart_handler(dev, 1);
break;
case 0x29:
dev->regs[dev->cur_reg] = val & 0x0f;
break;
}
}
static uint8_t
fdc37c669_read(uint16_t port, void *priv)
{
const fdc37c669_t *dev = (fdc37c669_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t ret = 0xff;
if (dev->locked) {
if (index)
ret = dev->cur_reg;
else if (!dev->rw_locked || (dev->cur_reg > 0x0f))
ret = dev->regs[dev->cur_reg];
}
fdc37c669_log("[%04X:%08X] [R] %04X = %02X (%i, %i)\n", CS, cpu_state.pc, port, ret,
dev->tries, dev->locked);
return ret;
}
static void
fdc37c669_reset(void *priv)
{
fdc37c669_t *dev = (fdc37c669_t *) priv;
memset(dev->regs, 0x00, 42);
dev->regs[0x00] = 0x28;
dev->regs[0x01] = 0x9c;
dev->regs[0x02] = 0x88;
dev->regs[0x03] = 0x78;
dev->regs[0x06] = 0xff;
dev->regs[0x0d] = 0x03;
dev->regs[0x0e] = 0x02;
dev->regs[0x1e] = 0x3c; /* Gameport controller. */
dev->regs[0x20] = 0x3c;
dev->regs[0x21] = 0x3c;
dev->regs[0x22] = 0x3d;
if (dev->id != 1) {
fdc_reset(dev->fdc);
fdc37c669_fdc_handler(dev);
}
fdc37c669_uart_handler(dev, 0);
serial_set_clock_src(dev->uart[0], fdc37c669_uart_get_clock_src(dev, 0));
fdc37c669_uart_handler(dev, 1);
serial_set_clock_src(dev->uart[1], fdc37c669_uart_get_clock_src(dev, 1));
fdc37c669_lpt_handler(dev);
dev->locked = 0;
dev->rw_locked = 0;
}
static void
fdc37c669_close(void *priv)
{
fdc37c669_t *dev = (fdc37c669_t *) priv;
next_id = 0;
free(dev);
}
static void *
fdc37c669_init(const device_t *info)
{
fdc37c669_t *dev = (fdc37c669_t *) malloc(sizeof(fdc37c669_t));
memset(dev, 0, sizeof(fdc37c669_t));
dev->id = next_id;
if (next_id != 1)
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, (next_id << 1) + 1);
dev->uart[1] = device_add_inst(&ns16550_device, (next_id << 1) + 2);
io_sethandler(info->local ? FDC_SECONDARY_ADDR : (next_id ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR),
0x0002, fdc37c669_read, NULL, NULL, fdc37c669_write, NULL, NULL, dev);
fdc37c669_reset(dev);
next_id++;
return dev;
}
const device_t fdc37c669_device = {
.name = "SMC FDC37C669 Super I/O",
.internal_name = "fdc37c669",
.flags = 0,
.local = 0,
.init = fdc37c669_init,
.close = fdc37c669_close,
.reset = fdc37c669_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc37c669_370_device = {
.name = "SMC FDC37C669 Super I/O (Port 370h)",
.internal_name = "fdc37c669_370",
.flags = 0,
.local = 1,
.init = fdc37c669_init,
.close = fdc37c669_close,
.reset = fdc37c669_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_fdc37c669.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,911 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the NatSemi PC87307 Super I/O chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct pc87307_t {
uint8_t id;
uint8_t pm_idx;
uint8_t regs[48];
uint8_t ld_regs[256][208];
uint8_t pcregs[16];
uint8_t gpio[2][4];
uint8_t pm[8];
uint16_t gpio_base;
uint16_t gpio_base2;
uint16_t pm_base;
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
} pc87307_t;
static void fdc_handler(pc87307_t *dev);
static void lpt1_handler(pc87307_t *dev);
static void serial_handler(pc87307_t *dev, int uart);
static void
pc87307_gpio_write(uint16_t port, uint8_t val, void *priv)
{
pc87307_t *dev = (pc87307_t *) priv;
uint8_t bank = ((port & 0xfffc) == dev->gpio_base2);
dev->gpio[bank][port & 3] = val;
}
uint8_t
pc87307_gpio_read(uint16_t port, void *priv)
{
const pc87307_t *dev = (pc87307_t *) priv;
uint8_t pins = 0xff;
uint8_t bank = ((port & 0xfffc) == dev->gpio_base2);
uint8_t mask;
uint8_t ret = dev->gpio[bank][port & 0x0003];
switch (port & 0x0003) {
case 0x0000:
mask = dev->gpio[bank][0x0001];
ret = (ret & mask) | (pins & ~mask);
break;
default:
break;
}
return ret;
}
static void
pc87307_gpio_remove(pc87307_t *dev)
{
if (dev->gpio_base != 0xffff) {
io_removehandler(dev->gpio_base, 0x0002,
pc87307_gpio_read, NULL, NULL, pc87307_gpio_write, NULL, NULL, dev);
dev->gpio_base = 0xffff;
}
if (dev->gpio_base2 != 0xffff) {
io_removehandler(dev->gpio_base2, 0x0002,
pc87307_gpio_read, NULL, NULL, pc87307_gpio_write, NULL, NULL, dev);
dev->gpio_base2 = 0xffff;
}
}
static void
pc87307_gpio_init(pc87307_t *dev, int bank, uint16_t addr)
{
uint16_t *bank_base = bank ? &(dev->gpio_base2) : &(dev->gpio_base);
*bank_base = addr;
io_sethandler(*bank_base, 0x0002,
pc87307_gpio_read, NULL, NULL, pc87307_gpio_write, NULL, NULL, dev);
}
static void
pc87307_pm_write(uint16_t port, uint8_t val, void *priv)
{
pc87307_t *dev = (pc87307_t *) priv;
if (port & 1)
dev->pm[dev->pm_idx] = val;
else {
dev->pm_idx = val & 0x07;
switch (dev->pm_idx) {
case 0x00:
fdc_handler(dev);
lpt1_handler(dev);
serial_handler(dev, 1);
serial_handler(dev, 0);
break;
default:
break;
}
}
}
uint8_t
pc87307_pm_read(uint16_t port, void *priv)
{
const pc87307_t *dev = (pc87307_t *) priv;
if (port & 1)
return dev->pm[dev->pm_idx];
else
return dev->pm_idx;
}
static void
pc87307_pm_remove(pc87307_t *dev)
{
if (dev->pm_base != 0xffff) {
io_removehandler(dev->pm_base, 0x0008,
pc87307_pm_read, NULL, NULL, pc87307_pm_write, NULL, NULL, dev);
dev->pm_base = 0xffff;
}
}
static void
pc87307_pm_init(pc87307_t *dev, uint16_t addr)
{
dev->pm_base = addr;
io_sethandler(dev->pm_base, 0x0008,
pc87307_pm_read, NULL, NULL, pc87307_pm_write, NULL, NULL, dev);
}
static void
fdc_handler(pc87307_t *dev)
{
uint8_t irq;
uint8_t active;
uint16_t addr;
fdc_remove(dev->fdc);
active = (dev->ld_regs[0x03][0x00] & 0x01) && (dev->pm[0x00] & 0x08);
addr = ((dev->ld_regs[0x03][0x30] << 8) | dev->ld_regs[0x03][0x31]) - 0x0002;
irq = (dev->ld_regs[0x03][0x40] & 0x0f);
if (active && (addr <= 0xfff8)) {
fdc_set_base(dev->fdc, addr);
fdc_set_irq(dev->fdc, irq);
}
}
static void
lpt1_handler(pc87307_t *dev)
{
uint8_t irq;
uint8_t active;
uint16_t addr;
lpt1_remove();
active = (dev->ld_regs[0x04][0x00] & 0x01) && (dev->pm[0x00] & 0x10);
addr = (dev->ld_regs[0x04][0x30] << 8) | dev->ld_regs[0x04][0x31];
irq = (dev->ld_regs[0x04][0x40] & 0x0f);
if (active && (addr <= 0xfffc)) {
lpt1_init(addr);
lpt1_irq(irq);
}
}
static void
serial_handler(pc87307_t *dev, int uart)
{
uint8_t irq;
uint8_t active;
uint16_t addr;
serial_remove(dev->uart[uart]);
active = (dev->ld_regs[0x06 - uart][0x00] & 0x01) && (dev->pm[0x00] & (1 << (6 - uart)));
addr = (dev->ld_regs[0x06 - uart][0x30] << 8) | dev->ld_regs[0x06 - uart][0x31];
irq = (dev->ld_regs[0x06 - uart][0x40] & 0x0f);
if (active && (addr <= 0xfff8))
serial_setup(dev->uart[uart], addr, irq);
}
static void
gpio_handler(pc87307_t *dev)
{
uint8_t active;
uint16_t addr;
pc87307_gpio_remove(dev);
active = (dev->ld_regs[0x07][0x00] & 0x01);
addr = (dev->ld_regs[0x07][0x30] << 8) | dev->ld_regs[0x07][0x31];
if (active)
pc87307_gpio_init(dev, 0, addr);
addr = (dev->ld_regs[0x07][0x32] << 8) | dev->ld_regs[0x07][0x33];
if (active)
pc87307_gpio_init(dev, 1, addr);
}
static void
pm_handler(pc87307_t *dev)
{
uint8_t active;
uint16_t addr;
pc87307_pm_remove(dev);
active = (dev->ld_regs[0x08][0x00] & 0x01);
addr = (dev->ld_regs[0x08][0x30] << 8) | dev->ld_regs[0x08][0x31];
if (active)
pc87307_pm_init(dev, addr);
}
static void
pc87307_write(uint16_t port, uint8_t val, void *priv)
{
pc87307_t *dev = (pc87307_t *) priv;
uint8_t index;
index = (port & 1) ? 0 : 1;
if (index) {
dev->cur_reg = val;
return;
} else {
switch (dev->cur_reg) {
case 0x00:
case 0x02:
case 0x03:
case 0x06:
case 0x07:
case 0x21:
dev->regs[dev->cur_reg] = val;
break;
case 0x22:
dev->regs[dev->cur_reg] = val & 0x7f;
break;
case 0x23:
dev->regs[dev->cur_reg] = val & 0x0f;
break;
case 0x24:
dev->pcregs[dev->regs[0x23]] = val;
break;
default:
if (dev->cur_reg >= 0x30) {
if ((dev->regs[0x07] != 0x06) || !(dev->regs[0x21] & 0x10))
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val;
}
break;
}
}
switch (dev->cur_reg) {
case 0x30:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x01;
switch (dev->regs[0x07]) {
case 0x03:
fdc_handler(dev);
break;
case 0x04:
lpt1_handler(dev);
break;
case 0x05:
serial_handler(dev, 1);
break;
case 0x06:
serial_handler(dev, 0);
break;
case 0x07:
gpio_handler(dev);
break;
case 0x08:
pm_handler(dev);
break;
default:
break;
}
break;
case 0x60:
case 0x62:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x07;
if ((dev->cur_reg == 0x62) && (dev->regs[0x07] != 0x07))
break;
switch (dev->regs[0x07]) {
case 0x03:
fdc_handler(dev);
break;
case 0x04:
lpt1_handler(dev);
break;
case 0x05:
serial_handler(dev, 1);
break;
case 0x06:
serial_handler(dev, 0);
break;
case 0x07:
gpio_handler(dev);
break;
case 0x08:
pm_handler(dev);
break;
default:
break;
}
break;
case 0x61:
switch (dev->regs[0x07]) {
case 0x00:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xfb;
break;
case 0x03:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = (val & 0xfa) | 0x02;
fdc_handler(dev);
break;
case 0x04:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xfc;
lpt1_handler(dev);
break;
case 0x05:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xf8;
serial_handler(dev, 1);
break;
case 0x06:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xf8;
serial_handler(dev, 0);
break;
case 0x07:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xf8;
gpio_handler(dev);
break;
case 0x08:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xfe;
pm_handler(dev);
break;
default:
break;
}
break;
case 0x63:
if (dev->regs[0x07] == 0x00)
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = (val & 0xfb) | 0x04;
else if (dev->regs[0x07] == 0x07) {
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xfe;
gpio_handler(dev);
}
break;
case 0x70:
case 0x74:
case 0x75:
switch (dev->regs[0x07]) {
case 0x03:
fdc_handler(dev);
break;
case 0x04:
lpt1_handler(dev);
break;
case 0x05:
serial_handler(dev, 1);
break;
case 0x06:
serial_handler(dev, 0);
break;
case 0x07:
gpio_handler(dev);
break;
case 0x08:
pm_handler(dev);
break;
default:
break;
}
break;
case 0xf0:
switch (dev->regs[0x07]) {
case 0x00:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xc1;
break;
case 0x03:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xe1;
fdc_update_densel_polarity(dev->fdc, (val & 0x20) ? 1 : 0);
fdc_update_enh_mode(dev->fdc, (val & 0x40) ? 1 : 0);
break;
case 0x04:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xf3;
lpt1_handler(dev);
break;
case 0x05:
case 0x06:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x87;
break;
default:
break;
}
break;
case 0xf1:
if (dev->regs[0x07] == 0x03)
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x0f;
break;
default:
break;
}
}
uint8_t
pc87307_read(uint16_t port, void *priv)
{
const pc87307_t *dev = (pc87307_t *) priv;
uint8_t ret = 0xff;
uint8_t index;
index = (port & 1) ? 0 : 1;
if (index)
ret = dev->cur_reg;
else {
if (dev->cur_reg >= 0x30)
ret = dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30];
else if (dev->cur_reg == 0x24)
ret = dev->pcregs[dev->regs[0x23]];
else
ret = dev->regs[dev->cur_reg];
}
return ret;
}
void
pc87307_reset(pc87307_t *dev)
{
memset(dev->regs, 0x00, 0x30);
for (uint16_t i = 0; i < 256; i++)
memset(dev->ld_regs[i], 0x00, 0xd0);
memset(dev->pcregs, 0x00, 0x10);
memset(dev->gpio, 0xff, 0x08);
memset(dev->pm, 0x00, 0x08);
dev->regs[0x20] = dev->id;
dev->regs[0x21] = 0x04;
dev->ld_regs[0x00][0x01] = 0x01;
dev->ld_regs[0x00][0x31] = 0x60;
dev->ld_regs[0x00][0x33] = 0x64;
dev->ld_regs[0x00][0x40] = 0x01;
dev->ld_regs[0x00][0x41] = 0x02;
dev->ld_regs[0x00][0x44] = 0x04;
dev->ld_regs[0x00][0x45] = 0x04;
dev->ld_regs[0x00][0xc0] = 0x40;
dev->ld_regs[0x01][0x40] = 0x0c;
dev->ld_regs[0x01][0x41] = 0x02;
dev->ld_regs[0x01][0x44] = 0x04;
dev->ld_regs[0x01][0x45] = 0x04;
dev->ld_regs[0x02][0x00] = 0x01;
dev->ld_regs[0x02][0x31] = 0x70;
dev->ld_regs[0x02][0x40] = 0x08;
dev->ld_regs[0x02][0x44] = 0x04;
dev->ld_regs[0x02][0x45] = 0x04;
dev->ld_regs[0x03][0x01] = 0x01;
dev->ld_regs[0x03][0x30] = 0x03;
dev->ld_regs[0x03][0x31] = 0xf2;
dev->ld_regs[0x03][0x40] = 0x06;
dev->ld_regs[0x03][0x41] = 0x03;
dev->ld_regs[0x03][0x44] = 0x02;
dev->ld_regs[0x03][0x45] = 0x04;
dev->ld_regs[0x03][0xc0] = 0x02;
dev->ld_regs[0x04][0x30] = 0x02;
dev->ld_regs[0x04][0x31] = 0x78;
dev->ld_regs[0x04][0x40] = 0x07;
dev->ld_regs[0x04][0x44] = 0x04;
dev->ld_regs[0x04][0x45] = 0x04;
dev->ld_regs[0x04][0xc0] = 0xf2;
dev->ld_regs[0x05][0x30] = 0x02;
dev->ld_regs[0x05][0x31] = 0xf8;
dev->ld_regs[0x05][0x40] = 0x03;
dev->ld_regs[0x05][0x41] = 0x03;
dev->ld_regs[0x05][0x44] = 0x04;
dev->ld_regs[0x05][0x45] = 0x04;
dev->ld_regs[0x05][0xc0] = 0x02;
dev->ld_regs[0x06][0x30] = 0x03;
dev->ld_regs[0x06][0x31] = 0xf8;
dev->ld_regs[0x06][0x40] = 0x04;
dev->ld_regs[0x06][0x41] = 0x03;
dev->ld_regs[0x06][0x44] = 0x04;
dev->ld_regs[0x06][0x45] = 0x04;
dev->ld_regs[0x06][0xc0] = 0x02;
dev->ld_regs[0x07][0x44] = 0x04;
dev->ld_regs[0x07][0x45] = 0x04;
dev->ld_regs[0x08][0x44] = 0x04;
dev->ld_regs[0x08][0x45] = 0x04;
#if 0
dev->gpio[0] = 0xff;
dev->gpio[1] = 0xfb;
#endif
dev->gpio[0][0] = 0xff;
dev->gpio[0][1] = 0x00;
dev->gpio[0][2] = 0x00;
dev->gpio[0][3] = 0xff;
dev->gpio[1][0] = 0xff;
dev->gpio[1][1] = 0x00;
dev->gpio[1][2] = 0x00;
dev->gpio[1][3] = 0xff;
dev->pm[0] = 0xff;
dev->pm[1] = 0xff;
dev->pm[4] = 0x0e;
dev->pm[7] = 0x01;
dev->gpio_base = dev->pm_base = 0xffff;
/*
0 = 360 rpm @ 500 kbps for 3.5"
1 = Default, 300 rpm @ 500, 300, 250, 1000 kbps for 3.5"
*/
lpt1_remove();
serial_remove(dev->uart[0]);
serial_remove(dev->uart[1]);
fdc_reset(dev->fdc);
}
static void
pc87307_close(void *priv)
{
pc87307_t *dev = (pc87307_t *) priv;
free(dev);
}
static void *
pc87307_init(const device_t *info)
{
pc87307_t *dev = (pc87307_t *) malloc(sizeof(pc87307_t));
memset(dev, 0, sizeof(pc87307_t));
dev->id = info->local & 0xff;
dev->fdc = device_add(&fdc_at_nsc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
pc87307_reset(dev);
if (info->local & 0x100) {
io_sethandler(0x02e, 0x0002,
pc87307_read, NULL, NULL, pc87307_write, NULL, NULL, dev);
}
if (info->local & 0x200) {
io_sethandler(0x15c, 0x0002,
pc87307_read, NULL, NULL, pc87307_write, NULL, NULL, dev);
}
return dev;
}
const device_t pc87307_device = {
.name = "National Semiconductor PC87307 Super I/O",
.internal_name = "pc87307",
.flags = 0,
.local = 0x1c0,
.init = pc87307_init,
.close = pc87307_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t pc87307_15c_device = {
.name = "National Semiconductor PC87307 Super I/O (Port 15Ch)",
.internal_name = "pc87307_15c",
.flags = 0,
.local = 0x2c0,
.init = pc87307_init,
.close = pc87307_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t pc87307_both_device = {
.name = "National Semiconductor PC87307 Super I/O (Ports 2Eh and 15Ch)",
.internal_name = "pc87307_both",
.flags = 0,
.local = 0x3c0,
.init = pc87307_init,
.close = pc87307_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t pc97307_device = {
.name = "National Semiconductor PC97307 Super I/O",
.internal_name = "pc97307",
.flags = 0,
.local = 0x1cf,
.init = pc87307_init,
.close = pc87307_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_pc87307.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,062 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ACC 3221-SP Super I/O Chip.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
typedef struct acc3221_t {
int reg_idx;
uint8_t regs[256];
fdc_t *fdc;
serial_t *uart[2];
} acc3221_t;
/* Configuration Register Index, BE (R/W):
Bit Function
7 PIRQ 5 polarity.
1 = active high, default
0 = active low
6 PIRQ 7 polarity.
1 = active high, default
0 = active low
5 Primary Parallel Port Extended Mode
0 = Compatible mode, default
1 = Extended/Bidirectional mode.
4 Primary Parallel Port Disable
1 = Disable, 0 = Enable
Power Up Default is set by pin 120
(3221-DP)/pin 96 (3221-SP)
3 Primary Parallel Port Power Down
1 = Power Down, default = 0
2** Secondary Parallel Port Extended
Mode
0 = Compatible mode, default
1 = Extended/Bidirectional mode.
1** Secondary Parallel Port Disable
1 = Disable, 0 = Enable
Power Up Default is set by pin 77
(3221-DP)
0** Secondary Parallel Port Power Down
1 = Power Down
0 = Enable, default
Note: Power Up not applicable to 3221-EP. */
#define REG_BE_LPT1_DISABLE (3 << 3)
#define REG_BE_LPT2_DISABLE (3 << 0) /* 3221-DP/EP only */
/* Configuration Register Index, BF (R/W):
Bit Function
7-0 The 8 most significant address bits of
the primary parallel port (A9-2)
Default 9E (LPT2, at 278-27B) */
/* Configuration Register Index, DA (R/W)**:
Bit Function
7-0 The 8 most significant address bits of
the secondary parallel port (A9-2)
Default DE (LPT1, at 378-37B) */
/* Configuration Register Index, DB (R/W):
Bit Function
7 SIRQ4 polarity.
1 = active high; default
0 = active low
6 SIRQ3 polarity.
1 = active high; default
0 = active low
5 SXTAL clock off. 1 = SCLK off,
0 = SCKL on, default
4 Primary serial port disable
1 = Disable, 0 = Enable
Power Up default is set by pin 116
(3221-DP)/pin 93 (3221-SP)
3 Primary serial port power down
1 = Power down, 0 = Enable
Power Up default is set by pin 116
(3221-DP)/pin 93 (3221-SP)
2 Reserved
1 Secondary serial port disable
1 = Disable, 0 = Enable
Power Up default is set by pin 121
(3221-DP)/pin 97 (3221-SP)
0 Secondary serial port power down
1 = Power down, 0 = Enable
Power Up default is set by pin 121
(3221-DP)/pin 97 (3221-SP)
Note: Power Up not applicable to 3221-EP. */
#define REG_DB_SERIAL1_DISABLE (3 << 3)
#define REG_DB_SERIAL2_DISABLE (3 << 0)
/* Configuration Register Index, DC (R/W):
Bit Function
7-1 The MSB of the Primary Serial Port
Address (bits A9-3).
Default = 7F (COM1, at 3F8-3FF).
0 When this bit is set to 1, bit A2 of
primary parallel port is decoded.
Default is 0. */
/* Configuration Register Index, DD (R/W):
Bit Function
7-1 The MSB of the Secondary Serial Port
Address (bits A9-3).
Default = 5F (COM2, at 2F8-2FF).
0** When this bit is set to 1, bit A2 of
secondary parallel port is decoded.
Default is 0. */
/* Configuration Register Index, DE (R/W):
Bit Function
7-6 SIRQ3 source
b7 b6
0 0 Disabled, tri-stated
0 1 Disabled, tri-stated**
1 0 Primary serial port
1 1 Secondary serial port,
default
5-4 SIRQ4 source
b5 b4
0 0 Disabled, tri-stated
0 1 Disabled, tri-stated**
1 0 Primary serial port,
default
1 1 Secondary serial port
3-2** PIRQ7 source
b3 b2
0 0 Diabled, tri-stated,
default
0 1 Primary serial port
1 0 Primary parallel port
1 1 Secondary parallel
port
Note: Bits 3-2 are reserved in 3221-SP.
1-0 PIRQ5 source
b1 b0
0 0 Disabled, tri-stated
0 1 Secondary serial port
1 0 Primary parallel port,
default
1 1 Secondary parallel
port** */
#define REG_DE_SIRQ3_SOURCE (3 << 6)
#define REG_DE_SIRQ3_SERIAL1 (1 << 6)
#define REG_DE_SIRQ3_SERIAL2 (3 << 6)
#define REG_DE_SIRQ4_SOURCE (3 << 4)
#define REG_DE_SIRQ4_SERIAL1 (1 << 4)
#define REG_DE_SIRQ4_SERIAL2 (3 << 4)
#define REG_DE_PIRQ7_SOURCE (3 << 2)
#define REG_DE_PIRQ7_SERIAL1 (1 << 2)
#define REG_DE_PIRQ7_LPT1 (2 << 2)
#define REG_DE_PIRQ7_LPT2 (3 << 2)
#define REG_DE_PIRQ5_SOURCE (3 << 0)
#define REG_DE_PIRQ5_SERIAL2 (1 << 0)
#define REG_DE_PIRQ5_LPT1 (2 << 0)
#define REG_DE_PIRQ5_LPT2 (3 << 0)
/* Configuration Register Index, DF (R/W)**:
Bit Function
7-6 Reserved
5 RTC interface disable
1 = /RTCCS disabled
0 = /RTCCS enabled, default
4 Disable Modem Select
1 = Moden CS disabled, default
0 = Modem CS enabled
3-2
b3 b2
1 1 Reserved
1 0 Modem port address
= 3E8-3EF (default)
0 1 Modem port address:
2F8-2FF
0 0 Modem port address:
3F8-3FF
1-0
b1 b0
1 1 Reserved
1 0 Mode 2, EISA Mode
0 1 Mode 1, AT BUS,
0 0 Mode 0, Two parallel
ports, default */
/* Configuration Register Index, FA (R/W)**:
Bit Function
7 General purpose I/O register, Bit 7
6 General purpose I/O register, Bit 6
5 General purpose I/O register, Bit 5
4 General purpose I/O register, Bit 4
3 General purpose I/O register, Bit 3
2 General purpose I/O register, Bit 2
1 General purpose I/O register, Bit 1
0 General purpose I/O register, Bit 0 */
/* Configuration Register Index, FB (R/W)**:
Bit Function
7 Reserved
6** 0/2 EXG (Read Only)
In mode 1 and mode 2
operation, when the third
floppy drive is installed, pin
EXTFDD should be pulled
high to enable the third floppy
drive or be pulled low to
disable the third floppy drive.
1 = Third floppy drive enabled
0 = Third floppy drive disabled
5** EXTFDD (Read Only)
In mode 1 and mode 2
operation, when the third
floppy drive is installed and
pin 0/2 EXG is pulled high,
the third floppy drive becomes
the bootable drive (drive 0).
When pi 0/2 EXG is pulled low,
the third floppy drive acts as
drive 2.
1 = Third floppy drive as drive 0 (bootable)
0 = Third floppy drive as drive 2
4** MS
In mode 1 and mode 2, t his bit is to
control the output pin MS to support a
special 3 1/2", 1.2M drive. When this
bit is set to high (1), the MS pin sends
a low signal. When this bit is set to
low (0), the MS pin sends a high
signal to support a 3 1/2", 1.2M drive.
3 FDC, Clock disable
0 = enable, default
1 = disable
2 Reserved
1 FDC disable
0 = enable, 1= disable
Power Upd efault set by pin 117 (3221-
DP)/pin 94 (3221-SP)
0 FDC address
0 = Primary, default
1 = Secondary
Note: Bits 6-4 are reserved in 3221-SP. */
#define REG_FB_FDC_DISABLE (1 << 1)
/* Configuration Register Index, FB (R/W)**:
Bit Function
7** Disable general chip select 1
1 = disable, default
0 = enable
6** Disable general chip select 2
1 = disable, default
0 = enable
5** Enable SA2 decoding for general chip
select 1
1 = enable
0 = disable, default
4** Enable SA2 decoding for general chip
select 2
1 = enable
0 = disable, default
3 Reserved
2 IDE XT selected
0 = IDE AT interface, default
1 = IDE XT interface
1 IDE disable, 1 = IDE disable
0 = IDE enable
Power Up default set by pin 13 (3221-
DP)/pin 13 (3221-SP)
0 Secondary IDE
1 = secondary
0 = primary, default
Note: Bits 6-4 are reserved in 3221-SP. */
#define REG_FE_IDE_DISABLE (1 << 1)
static void
acc3221_lpt_handle(acc3221_t *dev)
{
lpt1_remove();
if (!(dev->regs[0xbe] & REG_BE_LPT1_DISABLE))
lpt1_init(dev->regs[0xbf] << 2);
}
static void
acc3221_serial1_handler(acc3221_t *dev)
{
uint16_t com_addr = 0;
serial_remove(dev->uart[0]);
if (!(dev->regs[0xdb] & REG_DB_SERIAL1_DISABLE)) {
com_addr = ((dev->regs[0xdc] & 0xfe) << 2);
if ((dev->regs[0xde] & REG_DE_SIRQ3_SOURCE) == REG_DE_SIRQ3_SERIAL1)
serial_setup(dev->uart[0], com_addr, 3);
else if ((dev->regs[0xde] & REG_DE_SIRQ4_SOURCE) == REG_DE_SIRQ4_SERIAL1)
serial_setup(dev->uart[0], com_addr, 4);
}
}
static void
acc3221_serial2_handler(acc3221_t *dev)
{
uint16_t com_addr = 0;
serial_remove(dev->uart[1]);
if (!(dev->regs[0xdb] & REG_DB_SERIAL2_DISABLE)) {
com_addr = ((dev->regs[0xdd] & 0xfe) << 2);
if ((dev->regs[0xde] & REG_DE_SIRQ3_SOURCE) == REG_DE_SIRQ3_SERIAL2)
serial_setup(dev->uart[1], com_addr, 3);
else if ((dev->regs[0xde] & REG_DE_SIRQ4_SOURCE) == REG_DE_SIRQ4_SERIAL2)
serial_setup(dev->uart[1], com_addr, 4);
else if ((dev->regs[0xde] & REG_DE_PIRQ5_SOURCE) == REG_DE_PIRQ5_SERIAL2)
serial_setup(dev->uart[1], com_addr, 5);
}
}
static void
acc3221_write(uint16_t addr, uint8_t val, void *priv)
{
acc3221_t *dev = (acc3221_t *) priv;
uint8_t old;
if (!(addr & 1))
dev->reg_idx = val;
else {
old = dev->regs[dev->reg_idx];
dev->regs[dev->reg_idx] = val;
switch (dev->reg_idx) {
case 0xbe:
if ((old ^ val) & REG_BE_LPT1_DISABLE)
acc3221_lpt_handle(dev);
break;
case 0xbf:
if (old != val)
acc3221_lpt_handle(dev);
break;
case 0xdb:
if ((old ^ val) & REG_DB_SERIAL2_DISABLE)
acc3221_serial2_handler(dev);
if ((old ^ val) & REG_DB_SERIAL1_DISABLE)
acc3221_serial1_handler(dev);
break;
case 0xdc:
if (old != val)
acc3221_serial1_handler(dev);
break;
case 0xdd:
if (old != val)
acc3221_serial2_handler(dev);
break;
case 0xde:
if ((old ^ val) & (REG_DE_SIRQ3_SOURCE | REG_DE_SIRQ4_SOURCE)) {
acc3221_serial2_handler(dev);
acc3221_serial1_handler(dev);
}
break;
case 0xfb:
if ((old ^ val) & REG_FB_FDC_DISABLE) {
fdc_remove(dev->fdc);
if (!(dev->regs[0xfb] & REG_FB_FDC_DISABLE))
fdc_set_base(dev->fdc, FDC_PRIMARY_ADDR);
}
break;
case 0xfe:
if ((old ^ val) & REG_FE_IDE_DISABLE) {
ide_pri_disable();
if (!(dev->regs[0xfe] & REG_FE_IDE_DISABLE))
ide_pri_enable();
}
break;
default:
break;
}
}
}
static uint8_t
acc3221_read(uint16_t addr, void *priv)
{
const acc3221_t *dev = (acc3221_t *) priv;
if (!(addr & 1))
return dev->reg_idx;
if (dev->reg_idx < 0xbc)
return 0xff;
return dev->regs[dev->reg_idx];
}
static void
acc3221_reset(acc3221_t *dev)
{
serial_remove(dev->uart[0]);
serial_setup(dev->uart[0], COM1_ADDR, COM1_IRQ);
serial_remove(dev->uart[1]);
serial_setup(dev->uart[1], COM2_ADDR, COM2_IRQ);
lpt1_remove();
lpt1_init(LPT1_ADDR);
lpt1_irq(LPT1_IRQ);
fdc_reset(dev->fdc);
}
static void
acc3221_close(void *priv)
{
acc3221_t *dev = (acc3221_t *) priv;
free(dev);
}
static void *
acc3221_init(UNUSED(const device_t *info))
{
acc3221_t *dev = (acc3221_t *) malloc(sizeof(acc3221_t));
memset(dev, 0, sizeof(acc3221_t));
dev->fdc = device_add(&fdc_at_device);
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
io_sethandler(0x00f2, 0x0002, acc3221_read, NULL, NULL, acc3221_write, NULL, NULL, dev);
acc3221_reset(dev);
return dev;
}
const device_t acc3221_device = {
.name = "ACC 3221-SP Super I/O",
.internal_name = "acc3221",
.flags = 0,
.local = 0,
.init = acc3221_init,
.close = acc3221_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_acc3221.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,178 |
```objective-c
enum {
ACCREG_cycles = 0,
ACCREG_COUNT
};
struct ir_data_t;
void codegen_accumulate(int acc_reg, int delta);
void codegen_accumulate_flush(void);
void codegen_accumulate_reset(void);
``` | /content/code_sandbox/src/codegen/codegen_accumulate.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 50 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Winbond W83877F Super I/O Chip.
*
* Winbond W83877F Super I/O Chip
* Used by the Award 430HX
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pci.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#define FDDA_TYPE (dev->regs[7] & 3)
#define FDDB_TYPE ((dev->regs[7] >> 2) & 3)
#define FDDC_TYPE ((dev->regs[7] >> 4) & 3)
#define FDDD_TYPE ((dev->regs[7] >> 6) & 3)
#define FD_BOOT (dev->regs[8] & 3)
#define SWWP ((dev->regs[8] >> 4) & 1)
#define DISFDDWR ((dev->regs[8] >> 5) & 1)
#define EN3MODE ((dev->regs[9] >> 5) & 1)
#define DRV2EN_NEG (dev->regs[0xB] & 1) /* 0 = drive 2 installed */
#define INVERTZ ((dev->regs[0xB] >> 1) & 1) /* 0 = invert DENSEL polarity */
#define IDENT ((dev->regs[0xB] >> 3) & 1)
#define HEFERE ((dev->regs[0xC] >> 5) & 1)
#define HEFRAS (dev->regs[0x16] & 1)
#define PRTIQS (dev->regs[0x27] & 0x0f)
#define ECPIRQ ((dev->regs[0x27] >> 5) & 0x07)
typedef struct w83877f_t {
uint8_t tries;
uint8_t regs[42];
uint16_t reg_init;
int locked;
int rw_locked;
int cur_reg;
int base_address;
int key;
int key_times;
fdc_t *fdc;
serial_t *uart[2];
} w83877f_t;
static void w83877f_write(uint16_t port, uint8_t val, void *priv);
static uint8_t w83877f_read(uint16_t port, void *priv);
static void
w83877f_remap(w83877f_t *dev)
{
uint8_t hefras = HEFRAS;
io_removehandler(0x250, 0x0003,
w83877f_read, NULL, NULL, w83877f_write, NULL, NULL, dev);
io_removehandler(FDC_PRIMARY_ADDR, 0x0002,
w83877f_read, NULL, NULL, w83877f_write, NULL, NULL, dev);
dev->base_address = (hefras ? FDC_PRIMARY_ADDR : 0x250);
io_sethandler(dev->base_address, hefras ? 0x0002 : 0x0003,
w83877f_read, NULL, NULL, w83877f_write, NULL, NULL, dev);
dev->key_times = hefras + 1;
dev->key = (hefras ? 0x86 : 0x88) | HEFERE;
}
static uint8_t
get_lpt_length(w83877f_t *dev)
{
uint8_t length = 4;
if (dev->regs[9] & 0x80) {
if (dev->regs[0] & 0x04)
length = 8; /* EPP mode. */
if (dev->regs[0] & 0x08)
length |= 0x80; /* ECP mode. */
}
return length;
}
static uint16_t
make_port(w83877f_t *dev, uint8_t reg)
{
uint16_t p = 0;
uint8_t l;
switch (reg) {
case 0x20:
p = ((uint16_t) (dev->regs[reg] & 0xfc)) << 2;
p &= 0xFF0;
if ((p < 0x100) || (p > 0x3F0))
p = 0x3F0;
break;
case 0x23:
l = get_lpt_length(dev);
p = ((uint16_t) (dev->regs[reg] & 0xff)) << 2;
/* 8 ports in EPP mode, 4 in non-EPP mode. */
if ((l & 0x0f) == 8)
p &= 0x3F8;
else
p &= 0x3FC;
if ((p < 0x100) || (p > 0x3FF))
p = LPT1_ADDR;
/* In ECP mode, A10 is active. */
if (l & 0x80)
p |= 0x400;
break;
case 0x24:
p = ((uint16_t) (dev->regs[reg] & 0xfe)) << 2;
p &= 0xFF8;
if ((p < 0x100) || (p > 0x3F8))
p = COM1_ADDR;
break;
case 0x25:
p = ((uint16_t) (dev->regs[reg] & 0xfe)) << 2;
p &= 0xFF8;
if ((p < 0x100) || (p > 0x3F8))
p = COM2_ADDR;
break;
default:
break;
}
return p;
}
static void
w83877f_fdc_handler(w83877f_t *dev)
{
fdc_remove(dev->fdc);
if (dev->regs[0x20] & 0xc0)
fdc_set_base(dev->fdc, make_port(dev, 0x20));
fdc_set_power_down(dev->fdc, !!(dev->regs[6] & 0x08));
}
static void
w83877f_lpt_handler(w83877f_t *dev)
{
uint8_t lpt_irq;
uint8_t lpt_irqs[8] = { 0, 7, 9, 10, 11, 14, 15, 5 };
lpt1_remove();
if (!(dev->regs[4] & 0x80) && (dev->regs[0x23] & 0xc0))
lpt1_init(make_port(dev, 0x23));
lpt_irq = 0xff;
lpt_irq = lpt_irqs[ECPIRQ];
if (lpt_irq == 0)
lpt_irq = PRTIQS;
lpt1_irq(lpt_irq);
}
static void
w83877f_serial_handler(w83877f_t *dev, int uart)
{
int reg_mask = uart ? 0x10 : 0x20;
int reg_id = uart ? 0x25 : 0x24;
int irq_mask = uart ? 0x0f : 0xf0;
int irq_shift = uart ? 0 : 4;
double clock_src = 24000000.0 / 13.0;
serial_remove(dev->uart[uart]);
if (!(dev->regs[4] & reg_mask) && (dev->regs[reg_id] & 0xc0))
serial_setup(dev->uart[uart], make_port(dev, reg_id), (dev->regs[0x28] & irq_mask) >> irq_shift);
if (dev->regs[0x19] & (0x02 >> uart)) {
clock_src = 14769000.0;
} else if (dev->regs[0x03] & (0x02 >> uart)) {
clock_src = 24000000.0 / 12.0;
} else {
clock_src = 24000000.0 / 13.0;
}
serial_set_clock_src(dev->uart[uart], clock_src);
}
static void
w83877f_write(uint16_t port, uint8_t val, void *priv)
{
w83877f_t *dev = (w83877f_t *) priv;
uint8_t valxor = 0;
uint8_t max = 0x2A;
if (port == 0x250) {
if (val == dev->key)
dev->locked = 1;
else
dev->locked = 0;
return;
} else if (port == 0x251) {
if (val <= max)
dev->cur_reg = val;
return;
} else if (port == FDC_PRIMARY_ADDR) {
if ((val == dev->key) && !dev->locked) {
if (dev->key_times == 2) {
if (dev->tries) {
dev->locked = 1;
dev->tries = 0;
} else
dev->tries++;
} else {
dev->locked = 1;
dev->tries = 0;
}
} else {
if (dev->locked) {
if (val < max)
dev->cur_reg = val;
if (val == 0xaa)
dev->locked = 0;
} else {
if (dev->tries)
dev->tries = 0;
}
}
return;
} else if ((port == 0x252) || (port == 0x3f1)) {
if (dev->locked) {
if (dev->rw_locked)
return;
if ((dev->cur_reg >= 0x26) && (dev->cur_reg <= 0x27))
return;
if (dev->cur_reg == 0x29)
return;
if (dev->cur_reg == 6)
val &= 0xFB;
valxor = val ^ dev->regs[dev->cur_reg];
dev->regs[dev->cur_reg] = val;
} else
return;
}
switch (dev->cur_reg) {
case 0:
if (valxor & 0x0c)
w83877f_lpt_handler(dev);
break;
case 1:
if (valxor & 0x80)
fdc_set_swap(dev->fdc, (dev->regs[1] & 0x80) ? 1 : 0);
break;
case 3:
if (valxor & 0x02)
w83877f_serial_handler(dev, 0);
if (valxor & 0x01)
w83877f_serial_handler(dev, 1);
break;
case 4:
if (valxor & 0x10)
w83877f_serial_handler(dev, 1);
if (valxor & 0x20)
w83877f_serial_handler(dev, 0);
if (valxor & 0x80)
w83877f_lpt_handler(dev);
break;
case 6:
if (valxor & 0x08)
w83877f_fdc_handler(dev);
break;
case 7:
if (valxor & 0x03)
fdc_update_rwc(dev->fdc, 0, FDDA_TYPE);
if (valxor & 0x0c)
fdc_update_rwc(dev->fdc, 1, FDDB_TYPE);
if (valxor & 0x30)
fdc_update_rwc(dev->fdc, 2, FDDC_TYPE);
if (valxor & 0xc0)
fdc_update_rwc(dev->fdc, 3, FDDD_TYPE);
break;
case 8:
if (valxor & 0x03)
fdc_update_boot_drive(dev->fdc, FD_BOOT);
if (valxor & 0x10)
fdc_set_swwp(dev->fdc, SWWP ? 1 : 0);
if (valxor & 0x20)
fdc_set_diswr(dev->fdc, DISFDDWR ? 1 : 0);
break;
case 9:
if (valxor & 0x20)
fdc_update_enh_mode(dev->fdc, EN3MODE ? 1 : 0);
if (valxor & 0x40)
dev->rw_locked = (val & 0x40) ? 1 : 0;
if (valxor & 0x80)
w83877f_lpt_handler(dev);
break;
case 0xB:
if (valxor & 1)
fdc_update_drv2en(dev->fdc, DRV2EN_NEG ? 0 : 1);
if (valxor & 2)
fdc_update_densel_polarity(dev->fdc, INVERTZ ? 1 : 0);
break;
case 0xC:
if (valxor & 0x20)
w83877f_remap(dev);
break;
case 0x16:
if (valxor & 1)
w83877f_remap(dev);
break;
case 0x19:
if (valxor & 0x02)
w83877f_serial_handler(dev, 0);
if (valxor & 0x01)
w83877f_serial_handler(dev, 1);
break;
case 0x20:
if (valxor)
w83877f_fdc_handler(dev);
break;
case 0x23:
if (valxor)
w83877f_lpt_handler(dev);
break;
case 0x24:
if (valxor & 0xfe)
w83877f_serial_handler(dev, 0);
break;
case 0x25:
if (valxor & 0xfe)
w83877f_serial_handler(dev, 1);
break;
case 0x27:
if (valxor & 0xef)
w83877f_lpt_handler(dev);
break;
case 0x28:
if (valxor & 0xf) {
if ((dev->regs[0x28] & 0x0f) == 0)
dev->regs[0x28] |= 0x03;
w83877f_serial_handler(dev, 1);
}
if (valxor & 0xf0) {
if ((dev->regs[0x28] & 0xf0) == 0)
dev->regs[0x28] |= 0x40;
w83877f_serial_handler(dev, 0);
}
break;
default:
break;
}
}
static uint8_t
w83877f_read(uint16_t port, void *priv)
{
w83877f_t *dev = (w83877f_t *) priv;
uint8_t ret = 0xff;
if (dev->locked) {
if ((port == FDC_PRIMARY_ADDR) || (port == 0x251))
ret = dev->cur_reg;
else if ((port == 0x3f1) || (port == 0x252)) {
if (dev->cur_reg == 7)
ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) | (fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6));
else if ((dev->cur_reg >= 0x18) || !dev->rw_locked)
ret = dev->regs[dev->cur_reg];
}
}
return ret;
}
static void
w83877f_reset(w83877f_t *dev)
{
fdc_reset(dev->fdc);
memset(dev->regs, 0, 0x2A);
dev->regs[0x03] = 0x30;
dev->regs[0x07] = 0xF5;
dev->regs[0x09] = (dev->reg_init >> 8) & 0xff;
dev->regs[0x0a] = 0x1F;
dev->regs[0x0c] = 0x28;
dev->regs[0x0d] = 0xA3;
dev->regs[0x16] = dev->reg_init & 0xff;
dev->regs[0x1e] = 0x81;
dev->regs[0x20] = (FDC_PRIMARY_ADDR >> 2) & 0xfc;
dev->regs[0x21] = (0x1f0 >> 2) & 0xfc;
dev->regs[0x22] = ((0x3f6 >> 2) & 0xfc) | 1;
dev->regs[0x23] = (LPT1_ADDR >> 2);
dev->regs[0x24] = (COM1_ADDR >> 2) & 0xfe;
dev->regs[0x25] = (COM2_ADDR >> 2) & 0xfe;
dev->regs[0x26] = (2 << 4) | 4;
dev->regs[0x27] = (2 << 4) | 5;
dev->regs[0x28] = (4 << 4) | 3;
dev->regs[0x29] = 0x62;
w83877f_fdc_handler(dev);
w83877f_lpt_handler(dev);
w83877f_serial_handler(dev, 0);
w83877f_serial_handler(dev, 1);
dev->base_address = FDC_PRIMARY_ADDR;
dev->key = 0x89;
dev->key_times = 1;
w83877f_remap(dev);
dev->locked = 0;
dev->rw_locked = 0;
}
static void
w83877f_close(void *priv)
{
w83877f_t *dev = (w83877f_t *) priv;
free(dev);
}
static void *
w83877f_init(const device_t *info)
{
w83877f_t *dev = (w83877f_t *) malloc(sizeof(w83877f_t));
memset(dev, 0, sizeof(w83877f_t));
dev->fdc = device_add(&fdc_at_winbond_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->reg_init = info->local;
w83877f_reset(dev);
return dev;
}
const device_t w83877f_device = {
.name = "Winbond W83877F Super I/O",
.internal_name = "w83877f",
.flags = 0,
.local = 0x0a05,
.init = w83877f_init,
.close = w83877f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t w83877f_president_device = {
.name = "Winbond W83877F Super I/O (President)",
.internal_name = "w83877f_president",
.flags = 0,
.local = 0x0a04,
.init = w83877f_init,
.close = w83877f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t w83877tf_device = {
.name = "Winbond W83877TF Super I/O",
.internal_name = "w83877tf",
.flags = 0,
.local = 0x0c04,
.init = w83877f_init,
.close = w83877f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t w83877tf_acorp_device = {
.name = "Winbond W83877TF Super I/O",
.internal_name = "w83877tf_acorp",
.flags = 0,
.local = 0x0c05,
.init = w83877f_init,
.close = w83877f_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sio/sio_w83877f.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,838 |
```objective-c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Definitions for the code generator.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#ifndef _CODEGEN_H_
#define _CODEGEN_H_
#include <86box/mem.h>
#include "x86_ops.h"
#ifdef __amd64__
# include "codegen_x86-64.h"
#elif defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64
# include "codegen_x86.h"
#else
# error Dynamic recompiler not implemented on your platform
#endif
/*Handling self-modifying code (of which there is a lot on x86) :
PCem tracks a 'dirty mask' for each physical page, in which each bit
represents 64 bytes. This is only tracked for pages that have code in - when a
page first has a codeblock generated, it is evicted from the writelookup and
added to the page_lookup for this purpose. When in the page_lookup, each write
will go through the mem_write_ram*_page() functions and set the dirty mask
appropriately.
Each codeblock also contains a code mask (actually two masks, one for each
page the block is/may be in), again with each bit representing 64 bytes.
Each page has a list of codeblocks present in it. As each codeblock can span
up to two pages, two lists are present.
When a codeblock is about to be executed, the code masks are compared with the
dirty masks for the relevant pages. If either intersect, then
codegen_check_flush() is called on the affected page(s), and all affected
blocks are evicted.
The 64 byte granularity appears to work reasonably well for most cases,
avoiding most unnecessary evictions (eg when code & data are stored in the
same page).
*/
typedef struct codeblock_t {
uint64_t page_mask;
uint64_t page_mask2;
uint64_t *dirty_mask;
uint64_t *dirty_mask2;
uint64_t cmp;
/*Previous and next pointers, for the codeblock list associated with
each physical page. Two sets of pointers, as a codeblock can be
present in two pages.*/
struct codeblock_t *prev;
struct codeblock_t *next;
struct codeblock_t *prev_2;
struct codeblock_t *next_2;
/*Pointers for codeblock tree, used to search for blocks when hash lookup
fails.*/
struct codeblock_t *parent;
struct codeblock_t *left;
struct codeblock_t *right;
int pnt;
int ins;
int valid;
int was_recompiled;
int TOP;
uint32_t pc;
uint32_t _cs;
uint32_t endpc;
uint32_t phys, phys_2;
uint32_t status;
uint32_t flags;
uint8_t data[2048];
} codeblock_t;
/*Code block uses FPU*/
#define CODEBLOCK_HAS_FPU 1
/*Code block is always entered with the same FPU top-of-stack*/
#define CODEBLOCK_STATIC_TOP 2
static inline codeblock_t *
codeblock_tree_find(uint32_t phys, uint32_t _cs)
{
codeblock_t *block = pages[phys >> 12].head;
uint64_t a = _cs | ((uint64_t) phys << 32);
while (block) {
if (a == block->cmp) {
if (!((block->status ^ cpu_cur_status) & CPU_STATUS_FLAGS) && ((block->status & cpu_cur_status & CPU_STATUS_MASK) == (cpu_cur_status & CPU_STATUS_MASK)))
break;
}
if (a < block->cmp)
block = block->left;
else
block = block->right;
}
return block;
}
static inline void
codeblock_tree_add(codeblock_t *new_block)
{
codeblock_t *block = pages[new_block->phys >> 12].head;
uint64_t a = new_block->_cs | ((uint64_t) new_block->phys << 32);
new_block->cmp = a;
if (!block) {
pages[new_block->phys >> 12].head = new_block;
new_block->parent = new_block->left = new_block->right = NULL;
} else {
codeblock_t *old_block = NULL;
while (block) {
old_block = block;
if (a < old_block->cmp)
block = block->left;
else
block = block->right;
}
if (a < old_block->cmp)
old_block->left = new_block;
else
old_block->right = new_block;
new_block->parent = old_block;
new_block->left = new_block->right = NULL;
}
}
static inline void
codeblock_tree_delete(codeblock_t *block)
{
codeblock_t *parent = block->parent;
if (!block->left && !block->right) {
/*Easy case - remove from parent*/
if (!parent)
pages[block->phys >> 12].head = NULL;
else {
if (parent->left == block)
parent->left = NULL;
if (parent->right == block)
parent->right = NULL;
}
return;
} else if (!block->left) {
/*Only right node*/
if (!parent) {
pages[block->phys >> 12].head = block->right;
pages[block->phys >> 12].head->parent = NULL;
} else {
if (parent->left == block) {
parent->left = block->right;
parent->left->parent = parent;
}
if (parent->right == block) {
parent->right = block->right;
parent->right->parent = parent;
}
}
return;
} else if (!block->right) {
/*Only left node*/
if (!parent) {
pages[block->phys >> 12].head = block->left;
pages[block->phys >> 12].head->parent = NULL;
} else {
if (parent->left == block) {
parent->left = block->left;
parent->left->parent = parent;
}
if (parent->right == block) {
parent->right = block->left;
parent->right->parent = parent;
}
}
return;
} else {
/*Difficult case - node has two children. Walk right child to find lowest node*/
codeblock_t *lowest = block->right;
codeblock_t *highest;
codeblock_t *old_parent;
while (lowest->left)
lowest = lowest->left;
old_parent = lowest->parent;
/*Replace deleted node with lowest node*/
if (!parent)
pages[block->phys >> 12].head = lowest;
else {
if (parent->left == block)
parent->left = lowest;
if (parent->right == block)
parent->right = lowest;
}
lowest->parent = parent;
lowest->left = block->left;
if (lowest->left)
lowest->left->parent = lowest;
old_parent->left = NULL;
highest = lowest->right;
if (!highest) {
if (lowest != block->right) {
lowest->right = block->right;
block->right->parent = lowest;
}
return;
}
while (highest->right)
highest = highest->right;
if (block->right && block->right != lowest) {
highest->right = block->right;
block->right->parent = highest;
}
}
}
#define PAGE_MASK_INDEX_MASK 3
#define PAGE_MASK_INDEX_SHIFT 10
#define PAGE_MASK_MASK 63
#define PAGE_MASK_SHIFT 4
extern codeblock_t *codeblock;
extern codeblock_t **codeblock_hash;
extern void codegen_init(void);
extern void codegen_reset(void);
extern void codegen_block_init(uint32_t phys_addr);
extern void codegen_block_remove(void);
extern void codegen_block_start_recompile(codeblock_t *block);
extern void codegen_block_end_recompile(codeblock_t *block);
extern void codegen_block_end(void);
extern void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_pc, uint32_t old_pc);
extern void codegen_generate_seg_restore(void);
extern void codegen_set_op32(void);
extern void codegen_flush(void);
extern void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr);
extern int cpu_block_end;
extern uint32_t codegen_endpc;
extern int codegen_block_cycles;
extern void (*codegen_timing_start)(void);
extern void (*codegen_timing_prefix)(uint8_t prefix, uint32_t fetchdat);
extern void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
extern void (*codegen_timing_block_start)(void);
extern void (*codegen_timing_block_end)(void);
extern int (*codegen_timing_jump_cycles)(void);
typedef struct codegen_timing_t {
void (*start)(void);
void (*prefix)(uint8_t prefix, uint32_t fetchdat);
void (*opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
void (*block_start)(void);
void (*block_end)(void);
int (*jump_cycles)(void);
} codegen_timing_t;
extern codegen_timing_t codegen_timing_pentium;
extern codegen_timing_t codegen_timing_686;
extern codegen_timing_t codegen_timing_486;
extern codegen_timing_t codegen_timing_winchip;
extern codegen_timing_t codegen_timing_winchip2;
extern codegen_timing_t codegen_timing_k5;
extern codegen_timing_t codegen_timing_k6;
extern codegen_timing_t codegen_timing_p6;
void codegen_timing_set(codegen_timing_t *timing);
extern int block_current;
extern int block_pos;
#define CPU_BLOCK_END() cpu_block_end = 1
static inline void
addbyte(uint8_t val)
{
codeblock[block_current].data[block_pos++] = val;
if (block_pos >= BLOCK_MAX) {
CPU_BLOCK_END();
}
}
static inline void
addword(uint16_t val)
{
uint16_t *p = (uint16_t *) &codeblock[block_current].data[block_pos];
*p = val;
block_pos += 2;
if (block_pos >= BLOCK_MAX) {
CPU_BLOCK_END();
}
}
static inline void
addlong(uint32_t val)
{
uint32_t *p = (uint32_t *) &codeblock[block_current].data[block_pos];
*p = val;
block_pos += 4;
if (block_pos >= BLOCK_MAX) {
CPU_BLOCK_END();
}
}
static inline void
addquad(uint64_t val)
{
uint64_t *p = (uint64_t *) &codeblock[block_current].data[block_pos];
*p = val;
block_pos += 8;
if (block_pos >= BLOCK_MAX) {
CPU_BLOCK_END();
}
}
/*Current physical page of block being recompiled. -1 if no recompilation taking place */
extern uint32_t recomp_page;
extern x86seg *op_ea_seg;
extern int op_ssegs;
extern uint32_t op_old_pc;
/*Set to 1 if flags have been changed in the block being recompiled, and hence
flags_op is known and can be relied on */
extern int codegen_flags_changed;
extern int codegen_fpu_entered;
extern int codegen_mmx_entered;
extern int codegen_fpu_loaded_iq[8];
extern int codegen_reg_loaded[8];
extern int codegen_in_recompile;
#endif
``` | /content/code_sandbox/src/codegen/codegen.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,813 |
```objective-c
#define ROP_LOGIC(name, op, writeback) \
static uint32_t \
rop##name##_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
dst_reg = LOAD_REG_B(fetchdat & 7); \
} else { \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN8); \
src_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
op##_HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) { \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_B_RELEASE(dst_reg); \
else { \
LOAD_EA(); \
MEM_STORE_ADDR_EA_B_NO_ABRT(target_seg, dst_reg); \
} \
} else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
return op_pc + 1; \
} \
static uint32_t \
rop##name##_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
dst_reg = LOAD_REG_W(fetchdat & 7); \
} else { \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE_W(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16); \
src_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
op##_HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) { \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_W_RELEASE(dst_reg); \
else { \
LOAD_EA(); \
MEM_STORE_ADDR_EA_W_NO_ABRT(target_seg, dst_reg); \
} \
} else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
return op_pc + 1; \
} \
static uint32_t \
rop##name##_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
dst_reg = LOAD_REG_L(fetchdat & 7); \
} else { \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE_L(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32); \
src_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
op##_HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) { \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_L_RELEASE(dst_reg); \
else { \
LOAD_EA(); \
MEM_STORE_ADDR_EA_L_NO_ABRT(target_seg, dst_reg); \
} \
} else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
return op_pc + 1; \
} \
static uint32_t \
rop##name##_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
src_reg = LOAD_REG_B(fetchdat & 7); \
} else { \
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
MEM_LOAD_ADDR_EA_B(target_seg); \
src_reg = 0; \
} \
\
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN8); \
op##_HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) \
STORE_REG_B_RELEASE(dst_reg); \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
return op_pc + 1; \
} \
static uint32_t \
rop##name##_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
src_reg = LOAD_REG_W(fetchdat & 7); \
} else { \
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
MEM_LOAD_ADDR_EA_W(target_seg); \
src_reg = 0; \
} \
\
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16); \
op##_HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) \
STORE_REG_W_RELEASE(dst_reg); \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
return op_pc + 1; \
} \
static uint32_t \
rop##name##_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
src_reg = LOAD_REG_L(fetchdat & 7); \
} else { \
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
MEM_LOAD_ADDR_EA_L(target_seg); \
src_reg = 0; \
} \
\
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32); \
op##_HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) \
STORE_REG_L_RELEASE(dst_reg); \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
return op_pc + 1; \
}
ROP_LOGIC(AND, AND, 1)
ROP_LOGIC(OR, OR, 1)
ROP_LOGIC(XOR, XOR, 1)
static uint32_t
ropTEST_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
if ((fetchdat & 0xc0) == 0xc0) {
src_reg = LOAD_REG_B(fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_B(target_seg);
src_reg = 0;
}
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN8);
dst_reg = TEST_HOST_REG_B(dst_reg, src_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
return op_pc + 1;
}
static uint32_t
ropTEST_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
if ((fetchdat & 0xc0) == 0xc0) {
src_reg = LOAD_REG_W(fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_W(target_seg);
src_reg = 0;
}
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
dst_reg = TEST_HOST_REG_W(dst_reg, src_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
return op_pc + 1;
}
static uint32_t
ropTEST_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
if ((fetchdat & 0xc0) == 0xc0) {
src_reg = LOAD_REG_L(fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_L(target_seg);
src_reg = 0;
}
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
dst_reg = TEST_HOST_REG_L(dst_reg, src_reg);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
return op_pc + 1;
}
static uint32_t
ropAND_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_B(REG_AL);
AND_HOST_REG_IMM(host_reg, (fetchdat & 0xff) | 0xffffff00);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
}
static uint32_t
ropAND_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W(REG_AX);
AND_HOST_REG_IMM(host_reg, (fetchdat & 0xffff) | 0xffff0000);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
}
static uint32_t
ropAND_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_L(REG_EAX);
fetchdat = fastreadl(cs + op_pc);
AND_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
}
static uint32_t
ropOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_B(REG_AL);
OR_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
}
static uint32_t
ropOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W(REG_AX);
OR_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
}
static uint32_t
ropOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_L(REG_EAX);
fetchdat = fastreadl(cs + op_pc);
OR_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
}
static uint32_t
ropTEST_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_B(REG_AL);
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 1;
}
static uint32_t
ropTEST_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W(REG_AX);
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 2;
}
static uint32_t
ropTEST_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_L(REG_EAX);
fetchdat = fastreadl(cs + op_pc);
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 4;
}
static uint32_t
ropXOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_B(REG_AL);
XOR_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
}
static uint32_t
ropXOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W(REG_AX);
XOR_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
}
static uint32_t
ropXOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_L(REG_EAX);
fetchdat = fastreadl(cs + op_pc);
XOR_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
}
static uint32_t
ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
int host_reg;
uint8_t imm;
switch (fetchdat & 0x38) {
case 0x00: /*TEST b,#8*/
if ((fetchdat & 0xc0) == 0xc0) {
host_reg = LOAD_REG_B(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
} else {
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
imm = fastreadb(cs + op_pc + 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_B(target_seg);
host_reg = 0;
}
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN8);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 2;
case 0x10: /*NOT b*/
if ((fetchdat & 0xc0) != 0xc0)
return 0;
host_reg = LOAD_REG_B(fetchdat & 7);
XOR_HOST_REG_IMM(host_reg, 0xff);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
case 0x18: /*NEG b*/
if ((fetchdat & 0xc0) != 0xc0)
return 0;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB8);
host_reg = LOAD_REG_B(fetchdat & 7);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op2, host_reg);
NEG_HOST_REG_B(host_reg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op1, 0);
STORE_REG_B_RELEASE(host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, host_reg);
return op_pc + 1;
}
return 0;
}
static uint32_t
ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
int host_reg;
uint16_t imm;
switch (fetchdat & 0x38) {
case 0x00: /*TEST w,#*/
if ((fetchdat & 0xc0) == 0xc0) {
host_reg = LOAD_REG_W(fetchdat & 7);
imm = (fetchdat >> 8) & 0xffff;
} else {
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
imm = fastreadw(cs + op_pc + 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_W(target_seg);
host_reg = 0;
}
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 3;
case 0x10: /*NOT w*/
if ((fetchdat & 0xc0) != 0xc0)
return 0;
host_reg = LOAD_REG_W(fetchdat & 7);
XOR_HOST_REG_IMM(host_reg, 0xffff);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 1;
case 0x18: /*NEG w*/
if ((fetchdat & 0xc0) != 0xc0)
return 0;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB16);
host_reg = LOAD_REG_W(fetchdat & 7);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op2, host_reg);
NEG_HOST_REG_W(host_reg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op1, 0);
STORE_REG_W_RELEASE(host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
return op_pc + 1;
}
return 0;
}
static uint32_t
ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
int host_reg;
uint32_t imm;
switch (fetchdat & 0x38) {
case 0x00: /*TEST l,#*/
if ((fetchdat & 0xc0) == 0xc0) {
host_reg = LOAD_REG_L(fetchdat & 7);
imm = fastreadl(cs + op_pc + 1);
} else {
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
imm = fastreadl(cs + op_pc + 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_L(target_seg);
host_reg = 0;
}
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 5;
case 0x10: /*NOT l*/
if ((fetchdat & 0xc0) != 0xc0)
return 0;
host_reg = LOAD_REG_L(fetchdat & 7);
XOR_HOST_REG_IMM(host_reg, 0xffffffff);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 1;
case 0x18: /*NEG l*/
if ((fetchdat & 0xc0) != 0xc0)
return 0;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB32);
host_reg = LOAD_REG_L(fetchdat & 7);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op2, host_reg);
NEG_HOST_REG_L(host_reg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op1, 0);
STORE_REG_L_RELEASE(host_reg);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
return op_pc + 1;
}
return 0;
}
``` | /content/code_sandbox/src/codegen/codegen_ops_logic.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,067 |
```objective-c
#define SHIFT(size, size2, res_store, immediate) \
if ((fetchdat & 0xc0) == 0xc0) { \
reg = LOAD_REG_##size(fetchdat & 7); \
if (immediate) \
count = (fetchdat >> 8) & 0x1f; \
} else { \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE_##size(target_seg); \
reg = MEM_LOAD_ADDR_EA_##size##_NO_ABRT(target_seg); \
if (immediate) \
count = fastreadb(cs + op_pc + 1) & 0x1f; \
} \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, count); \
\
res_store((uintptr_t) &cpu_state.flags_op1, reg); \
\
switch (fetchdat & 0x38) { \
case 0x20: \
case 0x30: /*SHL*/ \
SHL_##size##_IMM(reg, count); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SHL##size2); \
break; \
\
case 0x28: /*SHR*/ \
SHR_##size##_IMM(reg, count); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SHR##size2); \
break; \
\
case 0x38: /*SAR*/ \
SAR_##size##_IMM(reg, count); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SAR##size2); \
break; \
} \
\
res_store((uintptr_t) &cpu_state.flags_res, reg); \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_##size##_RELEASE(reg); \
else { \
LOAD_EA(); \
MEM_STORE_ADDR_EA_##size##_NO_ABRT(target_seg, reg); \
}
static uint32_t
ropC0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg = NULL;
int count;
int reg;
if ((fetchdat & 0x38) < 0x20)
return 0;
SHIFT(B, 8, STORE_HOST_REG_ADDR_BL, 1);
return op_pc + 2;
}
static uint32_t
ropC1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg = NULL;
int count;
int reg;
if ((fetchdat & 0x38) < 0x20)
return 0;
SHIFT(W, 16, STORE_HOST_REG_ADDR_WL, 1);
return op_pc + 2;
}
static uint32_t
ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg = NULL;
int count;
int reg;
if ((fetchdat & 0x38) < 0x20)
return 0;
SHIFT(L, 32, STORE_HOST_REG_ADDR, 1);
return op_pc + 2;
}
static uint32_t
ropD0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg = NULL;
int count = 1;
int reg;
if ((fetchdat & 0x38) < 0x20)
return 0;
SHIFT(B, 8, STORE_HOST_REG_ADDR_BL, 0);
return op_pc + 1;
}
static uint32_t
ropD1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg = NULL;
int count = 1;
int reg;
if ((fetchdat & 0x38) < 0x20)
return 0;
SHIFT(W, 16, STORE_HOST_REG_ADDR_WL, 0);
return op_pc + 1;
}
static uint32_t
ropD1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg = NULL;
int count = 1;
int reg;
if ((fetchdat & 0x38) < 0x20)
return 0;
SHIFT(L, 32, STORE_HOST_REG_ADDR, 0);
return op_pc + 1;
}
``` | /content/code_sandbox/src/codegen/codegen_ops_shift.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,176 |
```c
#include <stdint.h>
#include <stdio.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include "codegen.h"
#include "codegen_accumulate.h"
static struct
{
int count;
uintptr_t dest_reg;
} acc_regs[] = {
[ACCREG_cycles] = {0, (uintptr_t) & (cycles)}
};
void
codegen_accumulate(int acc_reg, int delta)
{
acc_regs[acc_reg].count += delta;
#ifdef USE_ACYCS
if ((acc_reg == ACCREG_cycles) && (delta != 0)) {
if (delta == -1) {
/* -delta = 1 */
addbyte(0xff); /*inc dword ptr[&acycs]*/
addbyte(0x05);
addlong((uint32_t) (uintptr_t) & (acycs));
} else if (delta == 1) {
/* -delta = -1 */
addbyte(0xff); /*dec dword ptr[&acycs]*/
addbyte(0x0d);
addlong((uint32_t) (uintptr_t) & (acycs));
} else {
addbyte(0x81); /*ADD $acc_regs[c].count,acc_regs[c].dest*/
addbyte(0x05);
addlong((uint32_t) (uintptr_t) & (acycs));
addlong((uintptr_t) -delta);
}
}
#endif
}
void
codegen_accumulate_flush(void)
{
if (acc_regs[0].count) {
/* To reduce the size of the generated code, we take advantage of
the fact that the target offset points to _cycles within cpu_state,
so we can just use our existing infrastracture for variables
relative to cpu_state. */
addbyte(0x81); /*MOVL $acc_regs[0].count,(_cycles)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(_cycles));
addlong(acc_regs[0].count);
}
acc_regs[0].count = 0;
}
void
codegen_accumulate_reset(void)
{
acc_regs[0].count = 0;
}
``` | /content/code_sandbox/src/codegen/codegen_accumulate_x86.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 485 |
```objective-c
#define BLOCK_SIZE 0x4000
#define BLOCK_MASK 0x3fff
#define BLOCK_START 0
#define HASH_SIZE 0x20000
#define HASH_MASK 0x1ffff
#define HASH(l) ((l) &0x1ffff)
#define BLOCK_EXIT_OFFSET 0x7e0
#ifdef OLD_GPF
# define BLOCK_GPF_OFFSET (BLOCK_EXIT_OFFSET - 20)
#else
# define BLOCK_GPF_OFFSET (BLOCK_EXIT_OFFSET - 12)
#endif
#define BLOCK_MAX 1620
enum {
OP_RET = 0xc3
};
#define NR_HOST_REGS 4
extern int host_reg_mapping[NR_HOST_REGS];
#define NR_HOST_XMM_REGS 8
extern int host_reg_xmm_mapping[NR_HOST_XMM_REGS];
``` | /content/code_sandbox/src/codegen/codegen_x86-64.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 171 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Dynamic Recompiler for Intel 32-bit systems.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
# include <stdio.h>
# include <stdint.h>
# include <string.h>
# include <stdlib.h>
# include <wchar.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include "x86.h"
# include "x86_flags.h"
# include "x86_ops.h"
# include "x86seg_common.h"
# include "x86seg.h"
# include "x87_sf.h"
# include "x87.h"
/*ex*/
# include <86box/nmi.h>
# include <86box/pic.h>
# include "386_common.h"
# include "codegen.h"
# include "codegen_accumulate.h"
# include "codegen_ops.h"
# include "codegen_ops_x86.h"
# ifdef __unix__
# include <sys/mman.h>
# include <unistd.h>
# endif
# if defined _WIN32
# include <windows.h>
# endif
int codegen_flat_ds;
int codegen_flat_ss;
int mmx_ebx_ecx_loaded;
int codegen_flags_changed = 0;
int codegen_fpu_entered = 0;
int codegen_mmx_entered = 0;
int codegen_fpu_loaded_iq[8];
x86seg *op_ea_seg;
int op_ssegs;
uint32_t op_old_pc;
uint32_t recomp_page = -1;
int host_reg_mapping[NR_HOST_REGS];
int host_reg_xmm_mapping[NR_HOST_XMM_REGS];
codeblock_t *codeblock;
codeblock_t **codeblock_hash;
int block_current = 0;
static int block_num;
int block_pos;
uint32_t codegen_endpc;
int codegen_block_cycles;
static int codegen_block_ins;
static int codegen_block_full_ins;
static uint32_t last_op32;
static x86seg *last_ea_seg;
static int last_ssegs;
static uint32_t mem_abrt_rout;
uint32_t mem_load_addr_ea_b;
uint32_t mem_load_addr_ea_w;
uint32_t mem_load_addr_ea_l;
uint32_t mem_load_addr_ea_q;
uint32_t mem_store_addr_ea_b;
uint32_t mem_store_addr_ea_w;
uint32_t mem_store_addr_ea_l;
uint32_t mem_store_addr_ea_q;
uint32_t mem_load_addr_ea_b_no_abrt;
uint32_t mem_store_addr_ea_b_no_abrt;
uint32_t mem_load_addr_ea_w_no_abrt;
uint32_t mem_store_addr_ea_w_no_abrt;
uint32_t mem_load_addr_ea_l_no_abrt;
uint32_t mem_store_addr_ea_l_no_abrt;
uint32_t mem_check_write;
uint32_t mem_check_write_w;
uint32_t mem_check_write_l;
static uint32_t
gen_MEM_LOAD_ADDR_EA_B(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
addbyte(0xc2);
addbyte(0x89); /*MOV EDI, EDX*/
addbyte(0xd7);
addbyte(0xc1); /*SHR EDX, 12*/
addbyte(0xea);
addbyte(12);
addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
addbyte(0x14);
addbyte(0x95);
addlong((uint32_t) readlookup2);
addbyte(0x83); /*CMP EDX, -1*/
addbyte(0xfa);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4 + 1);
addbyte(0x0f); /*MOVZX EAX, B[EDX+EDI]*/
addbyte(0xb6);
addbyte(0x04);
addbyte(0x3a);
addbyte(0xc3); /*RET*/
addbyte(0x01); /*slowpath: ADD ESI,EAX*/
addbyte(0xc6);
addbyte(0x56); /*PUSH ESI*/
addbyte(0xe8); /*CALL readmembl*/
addlong((uint32_t) readmembl - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
addbyte(4);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*MOVZX EAX, AL*/
addbyte(0xb6);
addbyte(0xc0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t) (&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t
gen_MEM_LOAD_ADDR_EA_W(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
addbyte(0xc2);
addbyte(0x89); /*MOV EDI, EDX*/
addbyte(0xd7);
addbyte(0xc1); /*SHR EDX, 12*/
addbyte(0xea);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 1*/
addbyte(0xc7);
addlong(1);
addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
addbyte(0x14);
addbyte(0x95);
addlong((uint32_t) readlookup2);
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 4 + 1);
addbyte(0x83); /*CMP EDX, -1*/
addbyte(0xfa);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4 + 1);
addbyte(0x0f); /*MOVZX EAX, [EDX+EDI]W*/
addbyte(0xb7);
addbyte(0x04);
addbyte(0x3a);
addbyte(0xc3); /*RET*/
addbyte(0x01); /*slowpath: ADD ESI,EAX*/
addbyte(0xc6);
addbyte(0x56); /*PUSH ESI*/
addbyte(0xe8); /*CALL readmemwl*/
addlong((uint32_t) readmemwl - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
addbyte(4);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*MOVZX EAX, AX*/
addbyte(0xb7);
addbyte(0xc0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t) (&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t
gen_MEM_LOAD_ADDR_EA_L(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
addbyte(0xc2);
addbyte(0x89); /*MOV EDI, EDX*/
addbyte(0xd7);
addbyte(0xc1); /*SHR EDX, 12*/
addbyte(0xea);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 3*/
addbyte(0xc7);
addlong(3);
addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
addbyte(0x14);
addbyte(0x95);
addlong((uint32_t) readlookup2);
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 3 + 1);
addbyte(0x83); /*CMP EDX, -1*/
addbyte(0xfa);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 1);
addbyte(0x8b); /*MOV EAX, [EDX+EDI]*/
addbyte(0x04);
addbyte(0x3a);
addbyte(0xc3); /*RET*/
addbyte(0x01); /*slowpath: ADD ESI,EAX*/
addbyte(0xc6);
addbyte(0x56); /*PUSH ESI*/
addbyte(0xe8); /*CALL readmemll*/
addlong((uint32_t) readmemll - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
addbyte(4);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t) (&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t
gen_MEM_LOAD_ADDR_EA_Q(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
addbyte(0xc2);
addbyte(0x89); /*MOV EDI, EDX*/
addbyte(0xd7);
addbyte(0xc1); /*SHR EDX, 12*/
addbyte(0xea);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 7*/
addbyte(0xc7);
addlong(7);
addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
addbyte(0x14);
addbyte(0x95);
addlong((uint32_t) readlookup2);
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 3 + 4 + 1);
addbyte(0x83); /*CMP EDX, -1*/
addbyte(0xfa);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 4 + 1);
addbyte(0x8b); /*MOV EAX, [EDX+EDI]*/
addbyte(0x04);
addbyte(0x3a);
addbyte(0x8b); /*MOV EDX, [EDX+EDI+4]*/
addbyte(0x54);
addbyte(0x3a);
addbyte(4);
addbyte(0xc3); /*RET*/
addbyte(0x01); /*slowpath: ADD ESI,EAX*/
addbyte(0xc6);
addbyte(0x56); /*PUSH ESI*/
addbyte(0xe8); /*CALL readmemql*/
addlong((uint32_t) readmemql - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
addbyte(4);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t) (&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t
gen_MEM_STORE_ADDR_EA_B(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
addbyte(0x01); /*ADDL ESI, EAX*/
addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xc0 | (REG_ESI << 3) | REG_EDI);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
addbyte(0x04 | (REG_ESI << 3));
addbyte(0x85 | (REG_ESI << 3));
addlong((uint32_t) writelookup2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 1);
addbyte(0x88); /*MOV [EDI+ESI],CL*/
addbyte(0x04 | (REG_ECX << 3));
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xc3); /*RET*/
addbyte(0x51); /*slowpath: PUSH ECX*/
addbyte(0x01); /*ADD EBX,EAX*/
addbyte(0xC3);
addbyte(0x53); /*PUSH EBX*/
addbyte(0xe8); /*CALL writemembl*/
addlong((uint32_t) writemembl - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t) (&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t
gen_MEM_STORE_ADDR_EA_W(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
addbyte(0x01); /*ADDL ESI, EAX*/
addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 1*/
addbyte(0xc7);
addlong(1);
addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
addbyte(0x04 | (REG_ESI << 3));
addbyte(0x85 | (REG_ESI << 3));
addlong((uint32_t) writelookup2);
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 4 + 1);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4 + 1);
addbyte(0x66); /*MOV [EDI+ESI],CX*/
addbyte(0x89);
addbyte(0x04 | (REG_CX << 3));
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xc3); /*RET*/
addbyte(0x51); /*slowpath: PUSH ECX*/
addbyte(0x01); /*ADD EBX,EAX*/
addbyte(0xC3);
addbyte(0x53); /*PUSH EBX*/
addbyte(0xe8); /*CALL writememwl*/
addlong((uint32_t) writememwl - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t) (&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t
gen_MEM_STORE_ADDR_EA_L(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
addbyte(0x01); /*ADDL ESI, EAX*/
addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 3*/
addbyte(0xc7);
addlong(3);
addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
addbyte(0x04 | (REG_ESI << 3));
addbyte(0x85 | (REG_ESI << 3));
addlong((uint32_t) writelookup2);
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 3 + 1);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 1);
addbyte(0x89); /*MOV [EDI+ESI],ECX*/
addbyte(0x04 | (REG_ECX << 3));
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xc3); /*RET*/
addbyte(0x51); /*slowpath: PUSH ECX*/
addbyte(0x01); /*ADD EBX,EAX*/
addbyte(0xC3);
addbyte(0x53); /*PUSH EBX*/
addbyte(0xe8); /*CALL writememll*/
addlong((uint32_t) writememll - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t) (&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t
gen_MEM_STORE_ADDR_EA_Q(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
/*dat = EBX/ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EDX, ESI*/
addbyte(0xf2);
addbyte(0x01); /*ADDL ESI, EAX*/
addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 7*/
addbyte(0xc7);
addlong(7);
addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
addbyte(0x04 | (REG_ESI << 3));
addbyte(0x85 | (REG_ESI << 3));
addlong((uint32_t) writelookup2);
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 3 + 4 + 1);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 4 + 1);
addbyte(0x89); /*MOV [EDI+ESI],EBX*/
addbyte(0x04 | (REG_EBX << 3));
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0x89); /*MOV 4[EDI+ESI],EBX*/
addbyte(0x44 | (REG_ECX << 3));
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(4);
addbyte(0xc3); /*RET*/
addbyte(0x51); /*slowpath: PUSH ECX*/
addbyte(0x53); /*PUSH EBX*/
addbyte(0x01); /*ADD EDX,EAX*/
addbyte(0xC2);
addbyte(0x52); /*PUSH EDX*/
addbyte(0xe8); /*CALL writememql*/
addlong((uint32_t) writememql - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 12*/
addbyte(0xc4);
addbyte(12);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t) (&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
# ifndef RELEASE_BUILD
static char gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_B_NO_ABRT aborted\n";
# endif
static uint32_t
gen_MEM_LOAD_ADDR_EA_B_NO_ABRT(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
addbyte(0xc2);
addbyte(0x89); /*MOV EDI, EDX*/
addbyte(0xd7);
addbyte(0xc1); /*SHR EDX, 12*/
addbyte(0xea);
addbyte(12);
addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
addbyte(0x14);
addbyte(0x95);
addlong((uint32_t) readlookup2);
addbyte(0x83); /*CMP EDX, -1*/
addbyte(0xfa);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4 + 1);
addbyte(0x0f); /*MOVZX ECX, B[EDX+EDI]*/
addbyte(0xb6);
addbyte(0x0c);
addbyte(0x3a);
addbyte(0xc3); /*RET*/
addbyte(0x01); /*slowpath: ADD ESI,EAX*/
addbyte(0xc6);
addbyte(0x56); /*PUSH ESI*/
addbyte(0xe8); /*CALL readmembl*/
addlong((uint32_t) readmembl - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
addbyte(4);
# ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
# endif
addbyte(0x0f); /*MOVZX ECX, AL*/
addbyte(0xb6);
addbyte(0xc8);
# ifndef RELEASE_BUILD
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
# endif
addbyte(0xc3); /*RET*/
# ifndef RELEASE_BUILD
addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong((uint32_t) gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t) fatal - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
# endif
return addr;
}
# ifndef RELEASE_BUILD
static char gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_W_NO_ABRT aborted\n";
# endif
static uint32_t
gen_MEM_LOAD_ADDR_EA_W_NO_ABRT(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
addbyte(0xc2);
addbyte(0x89); /*MOV EDI, EDX*/
addbyte(0xd7);
addbyte(0xc1); /*SHR EDX, 12*/
addbyte(0xea);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 1*/
addbyte(0xc7);
addlong(1);
addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
addbyte(0x14);
addbyte(0x95);
addlong((uint32_t) readlookup2);
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 4 + 1);
addbyte(0x83); /*CMP EDX, -1*/
addbyte(0xfa);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4 + 1);
addbyte(0x0f); /*MOVZX ECX, [EDX+EDI]W*/
addbyte(0xb7);
addbyte(0x0c);
addbyte(0x3a);
addbyte(0xc3); /*RET*/
addbyte(0x01); /*slowpath: ADD ESI,EAX*/
addbyte(0xc6);
addbyte(0x56); /*PUSH ESI*/
addbyte(0xe8); /*CALL readmemwl*/
addlong((uint32_t) readmemwl - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
addbyte(4);
# ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
# endif
addbyte(0x0f); /*MOVZX ECX, AX*/
addbyte(0xb7);
addbyte(0xc8);
# ifndef RELEASE_BUILD
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
# endif
addbyte(0xc3); /*RET*/
# ifndef RELEASE_BUILD
addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong((uint32_t) gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t) fatal - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
# endif
return addr;
}
# ifndef RELEASE_BUILD
static char gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_L_NO_ABRT aborted\n";
# endif
static uint32_t
gen_MEM_LOAD_ADDR_EA_L_NO_ABRT(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
addbyte(0xc2);
addbyte(0x89); /*MOV EDI, EDX*/
addbyte(0xd7);
addbyte(0xc1); /*SHR EDX, 12*/
addbyte(0xea);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 3*/
addbyte(0xc7);
addlong(3);
addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
addbyte(0x14);
addbyte(0x95);
addlong((uint32_t) readlookup2);
addbyte(0x75); /*JE slowpath*/
addbyte(3 + 2 + 3 + 1);
addbyte(0x83); /*CMP EDX, -1*/
addbyte(0xfa);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 1);
addbyte(0x8b); /*MOV ECX, [EDX+EDI]*/
addbyte(0x0c);
addbyte(0x3a);
addbyte(0xc3); /*RET*/
addbyte(0x01); /*slowpath: ADD ESI,EAX*/
addbyte(0xc6);
addbyte(0x56); /*PUSH ESI*/
addbyte(0xe8); /*CALL readmemll*/
addlong((uint32_t) readmemll - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
addbyte(4);
addbyte(0x89); /*MOV ECX, EAX*/
addbyte(0xc1);
# ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
# endif
addbyte(0xc3); /*RET*/
# ifndef RELEASE_BUILD
addbyte(0x83); /*SUBL 4,%esp*/
addbyte(0xEC);
addbyte(4);
addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong((uint32_t) gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t) fatal - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
# endif
return addr;
}
# ifndef RELEASE_BUILD
static char gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_B_NO_ABRT aborted\n";
# endif
static uint32_t
gen_MEM_STORE_ADDR_EA_B_NO_ABRT(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
addbyte(0x01); /*ADDL ESI, EAX*/
addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xc0 | (REG_ESI << 3) | REG_EDI);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
addbyte(0x04 | (REG_ESI << 3));
addbyte(0x85 | (REG_ESI << 3));
addlong((uint32_t) writelookup2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 1);
addbyte(0x88); /*MOV [EDI+ESI],CL*/
addbyte(0x04 | (REG_ECX << 3));
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xc3); /*RET*/
addbyte(0x51); /*slowpath: PUSH ECX*/
addbyte(0x01); /*ADD EBX,EAX*/
addbyte(0xc3);
addbyte(0x53); /*PUSH EBX*/
addbyte(0xe8); /*CALL writemembl*/
addlong((uint32_t) writemembl - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
# ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
# endif
addbyte(0xc3); /*RET*/
# ifndef RELEASE_BUILD
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong((uint32_t) gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t) fatal - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
# endif
return addr;
}
# ifndef RELEASE_BUILD
static char gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_W_NO_ABRT aborted\n";
# endif
static uint32_t
gen_MEM_STORE_ADDR_EA_W_NO_ABRT(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
addbyte(0x01); /*ADDL ESI, EAX*/
addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 1*/
addbyte(0xc7);
addlong(1);
addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
addbyte(0x04 | (REG_ESI << 3));
addbyte(0x85 | (REG_ESI << 3));
addlong((uint32_t) writelookup2);
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 4 + 1);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4 + 1);
addbyte(0x66); /*MOV [EDI+ESI],CX*/
addbyte(0x89);
addbyte(0x04 | (REG_CX << 3));
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xc3); /*RET*/
addbyte(0x51); /*slowpath: PUSH ECX*/
addbyte(0x01); /*ADD EBX,EAX*/
addbyte(0xC3);
addbyte(0x53); /*PUSH EBX*/
addbyte(0xe8); /*CALL writememwl*/
addlong((uint32_t) writememwl - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
# ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
# endif
addbyte(0xc3); /*RET*/
# ifndef RELEASE_BUILD
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong((uint32_t) gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t) fatal - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
# endif
return addr;
}
# ifndef RELEASE_BUILD
static char gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_L_NO_ABRT aborted\n";
# endif
static uint32_t
gen_MEM_STORE_ADDR_EA_L_NO_ABRT(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
addbyte(0x01); /*ADDL ESI, EAX*/
addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 3*/
addbyte(0xc7);
addlong(3);
addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
addbyte(0x04 | (REG_ESI << 3));
addbyte(0x85 | (REG_ESI << 3));
addlong((uint32_t) writelookup2);
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 3 + 1);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 1);
addbyte(0x89); /*MOV [EDI+ESI],ECX*/
addbyte(0x04 | (REG_ECX << 3));
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xc3); /*RET*/
addbyte(0x51); /*slowpath: PUSH ECX*/
addbyte(0x01); /*ADD EBX,EAX*/
addbyte(0xC3);
addbyte(0x53); /*PUSH EBX*/
addbyte(0xe8); /*CALL writememll*/
addlong((uint32_t) writememll - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
# ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
# endif
addbyte(0xc3); /*RET*/
# ifndef RELEASE_BUILD
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong((uint32_t) gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t) fatal - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
# endif
return addr;
}
static uint32_t
gen_MEM_CHECK_WRITE(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
addbyte(0x83); /*CMP cr0, 0*/
addbyte(0x3d);
addlong((uint32_t) &cr0);
addbyte(0);
addbyte(0x78); /*JS +*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0xc1); /*SHR EDI, 12*/
addbyte(0xef);
addbyte(12);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xfe);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(11);
addbyte(0x83); /*CMP writelookup2[EDI*4],-1*/
addbyte(0x3c);
addbyte(0xbd);
addlong((uint32_t) writelookup2);
addbyte(-1);
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
addbyte(0x6a); /*PUSH 1*/
addbyte(1);
addbyte(0x57); /*PUSH EDI*/
addbyte(0xe8); /*CALL mmutranslatereal32*/
addlong((uint32_t) mmutranslatereal32 - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t) (&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t
gen_MEM_CHECK_WRITE_W(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
addbyte(0x83); /*CMP cr0, 0*/
addbyte(0x3d);
addlong((uint32_t) &cr0);
addbyte(0);
addbyte(0x78); /*JS +*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xfe);
addbyte(-1);
addbyte(0x8d); /*LEA ESI, 1[EDI]*/
addbyte(0x77);
addbyte(0x01);
addbyte(0x74); /*JE slowpath*/
addbyte(11);
addbyte(0x89); /*MOV EAX, EDI*/
addbyte(0xf8);
addbyte(0xc1); /*SHR EDI, 12*/
addbyte(0xef);
addbyte(12);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xee);
addbyte(12);
addbyte(0x83); /*CMP writelookup2[EDI*4],-1*/
addbyte(0x3c);
addbyte(0xbd);
addlong((uint32_t) writelookup2);
addbyte(-1);
addbyte(0x74); /*JE +*/
addbyte(11);
addbyte(0x83); /*CMP writelookup2[ESI*4],-1*/
addbyte(0x3c);
addbyte(0xb5);
addlong((uint32_t) writelookup2);
addbyte(-1);
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x89); /*MOV EDI, EAX*/
addbyte(0xc7);
/*slowpath_lp:*/
addbyte(0x6a); /*PUSH 1*/
addbyte(1);
addbyte(0x57); /*PUSH EDI*/
addbyte(0xe8); /*CALL mmutranslatereal32*/
addlong((uint32_t) mmutranslatereal32 - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x5f); /*POP EDI*/
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
addbyte(4);
addbyte(0x83); /*ADD EDI, 1*/
addbyte(0xc7);
addbyte(1);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t) (&codeblock[block_current].data[block_pos]) + 4));
/*If bits 0-11 of the address are now 0 then this crosses a page, so loop back*/
addbyte(0xf7); /*TEST $fff, EDI*/
addbyte(0xc7);
addlong(0xfff);
addbyte(0x74); /*JE slowpath_lp*/
addbyte(-33);
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t
gen_MEM_CHECK_WRITE_L(void)
{
uint32_t addr = (uint32_t) &codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
addbyte(0x83); /*CMP cr0, 0*/
addbyte(0x3d);
addlong((uint32_t) &cr0);
addbyte(0);
addbyte(0x78); /*JS +*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xfe);
addbyte(-1);
addbyte(0x8d); /*LEA ESI, 3[EDI]*/
addbyte(0x77);
addbyte(0x03);
addbyte(0x74); /*JE slowpath*/
addbyte(11);
addbyte(0x89); /*MOV EAX, EDI*/
addbyte(0xf8);
addbyte(0xc1); /*SHR EDI, 12*/
addbyte(0xef);
addbyte(12);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xee);
addbyte(12);
addbyte(0x83); /*CMP writelookup2[EDI*4],-1*/
addbyte(0x3c);
addbyte(0xbd);
addlong((uint32_t) writelookup2);
addbyte(-1);
addbyte(0x74); /*JE +*/
addbyte(11);
addbyte(0x83); /*CMP writelookup2[ESI*4],-1*/
addbyte(0x3c);
addbyte(0xb5);
addlong((uint32_t) writelookup2);
addbyte(-1);
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x89); /*MOV EDI, EAX*/
addbyte(0xc7);
/*slowpath_lp:*/
addbyte(0x6a); /*PUSH 1*/
addbyte(1);
addbyte(0x57); /*PUSH EDI*/
addbyte(0xe8); /*CALL mmutranslatereal32*/
addlong((uint32_t) mmutranslatereal32 - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0x5f); /*POP EDI*/
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
addbyte(4);
addbyte(0x83); /*ADD EDI, 3*/
addbyte(0xc7);
addbyte(3);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t) (&codeblock[block_current].data[block_pos]) + 4));
/*If bits 2-11 of the address are now 0 then this crosses a page, so loop back*/
addbyte(0xf7); /*TEST EDI, FFC*/
addbyte(0xc7);
addlong(0xffc);
addbyte(0x74); /*JE slowpath_lp*/
addbyte(-33);
addbyte(0xc3); /*RET*/
return addr;
}
void
codegen_init(void)
{
# ifdef _WIN32
codeblock = VirtualAlloc(NULL, (BLOCK_SIZE + 1) * sizeof(codeblock_t), MEM_COMMIT, PAGE_EXECUTE_READWRITE);
# elif defined __unix__
codeblock = mmap(NULL, (BLOCK_SIZE + 1) * sizeof(codeblock_t), PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, 0, 0);
# else
codeblock = malloc((BLOCK_SIZE + 1) * sizeof(codeblock_t));
# endif
codeblock_hash = malloc(HASH_SIZE * sizeof(codeblock_t *));
memset(codeblock, 0, (BLOCK_SIZE + 1) * sizeof(codeblock_t));
memset(codeblock_hash, 0, HASH_SIZE * sizeof(codeblock_t *));
block_current = BLOCK_SIZE;
block_pos = 0;
mem_abrt_rout = (uint32_t) &codeblock[block_current].data[block_pos];
addbyte(0x83); /*ADDL $16+4,%esp*/
addbyte(0xC4);
addbyte(0x10 + 4);
addbyte(0x5f); /*POP EDI*/
addbyte(0x5e); /*POP ESI*/
addbyte(0x5d); /*POP EBP*/
addbyte(0x5b); /*POP EDX*/
addbyte(0xC3); /*RET*/
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_l = (uint32_t) gen_MEM_LOAD_ADDR_EA_L();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_w = (uint32_t) gen_MEM_LOAD_ADDR_EA_W();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_b = (uint32_t) gen_MEM_LOAD_ADDR_EA_B();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_q = (uint32_t) gen_MEM_LOAD_ADDR_EA_Q();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_l = (uint32_t) gen_MEM_STORE_ADDR_EA_L();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_w = (uint32_t) gen_MEM_STORE_ADDR_EA_W();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_b = (uint32_t) gen_MEM_STORE_ADDR_EA_B();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_q = (uint32_t) gen_MEM_STORE_ADDR_EA_Q();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_b_no_abrt = (uint32_t) gen_MEM_LOAD_ADDR_EA_B_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_b_no_abrt = (uint32_t) gen_MEM_STORE_ADDR_EA_B_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_w_no_abrt = (uint32_t) gen_MEM_LOAD_ADDR_EA_W_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_w_no_abrt = (uint32_t) gen_MEM_STORE_ADDR_EA_W_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_l_no_abrt = (uint32_t) gen_MEM_LOAD_ADDR_EA_L_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_l_no_abrt = (uint32_t) gen_MEM_STORE_ADDR_EA_L_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_check_write = (uint32_t) gen_MEM_CHECK_WRITE();
block_pos = (block_pos + 15) & ~15;
mem_check_write_w = (uint32_t) gen_MEM_CHECK_WRITE_W();
block_pos = (block_pos + 15) & ~15;
mem_check_write_l = (uint32_t) gen_MEM_CHECK_WRITE_L();
# ifndef _MSC_VER
asm(
"fstcw %0\n"
: "=m"(cpu_state.old_npxc));
# else
__asm
{
fstcw cpu_state.old_npxc
}
# endif
}
void
codegen_reset(void)
{
memset(codeblock, 0, BLOCK_SIZE * sizeof(codeblock_t));
memset(codeblock_hash, 0, HASH_SIZE * sizeof(codeblock_t *));
mem_reset_page_blocks();
}
void
dump_block(void)
{
}
static void
add_to_block_list(codeblock_t *block)
{
codeblock_t *block_prev = pages[block->phys >> 12].block[(block->phys >> 10) & 3];
if (!block->page_mask)
fatal("add_to_block_list - mask = 0\n");
if (block_prev) {
block->next = block_prev;
block_prev->prev = block;
pages[block->phys >> 12].block[(block->phys >> 10) & 3] = block;
} else {
block->next = NULL;
pages[block->phys >> 12].block[(block->phys >> 10) & 3] = block;
}
if (block->next) {
if (!block->next->valid)
fatal("block->next->valid=0 %p %p %x %x\n", (void *) block->next, (void *) codeblock, block_current, block_pos);
}
if (block->page_mask2) {
block_prev = pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3];
if (block_prev) {
block->next_2 = block_prev;
block_prev->prev_2 = block;
pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3] = block;
} else {
block->next_2 = NULL;
pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3] = block;
}
}
}
static void
remove_from_block_list(codeblock_t *block, uint32_t pc)
{
if (!block->page_mask)
return;
if (block->prev) {
block->prev->next = block->next;
if (block->next)
block->next->prev = block->prev;
} else {
pages[block->phys >> 12].block[(block->phys >> 10) & 3] = block->next;
if (block->next)
block->next->prev = NULL;
else
mem_flush_write_page(block->phys, 0);
}
if (!block->page_mask2) {
if (block->prev_2 || block->next_2)
fatal("Invalid block_2\n");
return;
}
if (block->prev_2) {
block->prev_2->next_2 = block->next_2;
if (block->next_2)
block->next_2->prev_2 = block->prev_2;
} else {
pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3] = block->next_2;
if (block->next_2)
block->next_2->prev_2 = NULL;
else
mem_flush_write_page(block->phys_2, 0);
}
}
static void
delete_block(codeblock_t *block)
{
uint32_t old_pc = block->pc;
if (block == codeblock_hash[HASH(block->phys)])
codeblock_hash[HASH(block->phys)] = NULL;
if (!block->valid)
fatal("Deleting deleted block\n");
block->valid = 0;
codeblock_tree_delete(block);
remove_from_block_list(block, old_pc);
}
void
codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
{
struct codeblock_t *block = page->block[(phys_addr >> 10) & 3];
while (block) {
if (mask & block->page_mask) {
delete_block(block);
}
if (block == block->next)
fatal("Broken 1\n");
block = block->next;
}
block = page->block_2[(phys_addr >> 10) & 3];
while (block) {
if (mask & block->page_mask2) {
delete_block(block);
}
if (block == block->next_2)
fatal("Broken 2\n");
block = block->next_2;
}
}
void
codegen_block_init(uint32_t phys_addr)
{
codeblock_t *block;
page_t *page = &pages[phys_addr >> 12];
if (!page->block[(phys_addr >> 10) & 3])
mem_flush_write_page(phys_addr, cs + cpu_state.pc);
block_current = (block_current + 1) & BLOCK_MASK;
block = &codeblock[block_current];
if (block->valid != 0) {
delete_block(block);
}
block_num = HASH(phys_addr);
codeblock_hash[block_num] = &codeblock[block_current];
block->valid = 1;
block->ins = 0;
block->pc = cs + cpu_state.pc;
block->_cs = cs;
block->pnt = block_current;
block->phys = phys_addr;
block->dirty_mask = &page->dirty_mask[(phys_addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK];
block->dirty_mask2 = NULL;
block->next = block->prev = NULL;
block->next_2 = block->prev_2 = NULL;
block->page_mask = 0;
block->flags = CODEBLOCK_STATIC_TOP;
block->status = cpu_cur_status;
block->was_recompiled = 0;
recomp_page = block->phys & ~0xfff;
codeblock_tree_add(block);
}
void
codegen_block_start_recompile(codeblock_t *block)
{
page_t *page = &pages[block->phys >> 12];
if (!page->block[(block->phys >> 10) & 3])
mem_flush_write_page(block->phys, cs + cpu_state.pc);
block_num = HASH(block->phys);
block_current = block->pnt;
if (block->pc != cs + cpu_state.pc || block->was_recompiled)
fatal("Recompile to used block!\n");
block->status = cpu_cur_status;
block_pos = BLOCK_GPF_OFFSET;
# ifdef OLD_GPF
addbyte(0xc7); /*MOV [ESP],0*/
addbyte(0x04);
addbyte(0x24);
addlong(0);
addbyte(0xc7); /*MOV [ESP+4],0*/
addbyte(0x44);
addbyte(0x24);
addbyte(0x04);
addlong(0);
addbyte(0xe8); /*CALL x86gpf*/
addlong((uint32_t) x86gpf - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
# else
addbyte(0xc6); /* mov byte ptr[&(cpu_state.abrt)],ABRT_GPF */
addbyte(0x05);
addlong((uint32_t) (uintptr_t) & (cpu_state.abrt));
addbyte(ABRT_GPF);
addbyte(0x31); /* xor eax,eax */
addbyte(0xc0);
addbyte(0xa3); /* mov [&(abrt_error)],eax */
addlong((uint32_t) (uintptr_t) & (abrt_error));
# endif
block_pos = BLOCK_EXIT_OFFSET; /*Exit code*/
addbyte(0x83); /*ADDL $16,%esp*/
addbyte(0xC4);
addbyte(0x10);
addbyte(0x5f); /*POP EDI*/
addbyte(0x5e); /*POP ESI*/
addbyte(0x5d); /*POP EBP*/
addbyte(0x5b); /*POP EDX*/
addbyte(0xC3); /*RET*/
cpu_block_end = 0;
block_pos = 0; /*Entry code*/
addbyte(0x53); /*PUSH EBX*/
addbyte(0x55); /*PUSH EBP*/
addbyte(0x56); /*PUSH ESI*/
addbyte(0x57); /*PUSH EDI*/
addbyte(0x83); /*SUBL $16,%esp*/
addbyte(0xEC);
addbyte(0x10);
addbyte(0xBD); /*MOVL EBP, &cpu_state*/
addlong(((uintptr_t) &cpu_state) + 128);
last_op32 = -1;
last_ea_seg = NULL;
last_ssegs = -1;
codegen_block_cycles = 0;
codegen_timing_block_start();
codegen_block_ins = 0;
codegen_block_full_ins = 0;
recomp_page = block->phys & ~0xfff;
codegen_flags_changed = 0;
codegen_fpu_entered = 0;
codegen_mmx_entered = 0;
codegen_fpu_loaded_iq[0] = codegen_fpu_loaded_iq[1] = codegen_fpu_loaded_iq[2] = codegen_fpu_loaded_iq[3] = codegen_fpu_loaded_iq[4] = codegen_fpu_loaded_iq[5] = codegen_fpu_loaded_iq[6] = codegen_fpu_loaded_iq[7] = 0;
cpu_state.seg_ds.checked = cpu_state.seg_es.checked = cpu_state.seg_fs.checked = cpu_state.seg_gs.checked = (cr0 & 1) ? 0 : 1;
block->TOP = cpu_state.TOP & 7;
block->was_recompiled = 1;
codegen_flat_ds = !(cpu_cur_status & CPU_STATUS_NOTFLATDS);
codegen_flat_ss = !(cpu_cur_status & CPU_STATUS_NOTFLATSS);
codegen_accumulate_reset();
}
void
codegen_block_remove(void)
{
codeblock_t *block = &codeblock[block_current];
delete_block(block);
recomp_page = -1;
}
void
codegen_block_generate_end_mask(void)
{
codeblock_t *block = &codeblock[block_current];
uint32_t start_pc;
uint32_t end_pc;
block->endpc = codegen_endpc;
block->page_mask = 0;
start_pc = (block->pc & 0x3ff) & ~15;
if ((block->pc ^ block->endpc) & ~0x3ff)
end_pc = 0x3ff & ~15;
else
end_pc = (block->endpc & 0x3ff) & ~15;
if (end_pc < start_pc)
end_pc = 0x3ff;
start_pc >>= PAGE_MASK_SHIFT;
end_pc >>= PAGE_MASK_SHIFT;
for (; start_pc <= end_pc; start_pc++) {
block->page_mask |= ((uint64_t) 1 << start_pc);
}
pages[block->phys >> 12].code_present_mask[(block->phys >> 10) & 3] |= block->page_mask;
block->phys_2 = -1;
block->page_mask2 = 0;
block->next_2 = block->prev_2 = NULL;
if ((block->pc ^ block->endpc) & ~0x3ff) {
block->phys_2 = get_phys_noabrt(block->endpc);
if (block->phys_2 != -1) {
page_t *page_2 = &pages[block->phys_2 >> 12];
start_pc = 0;
end_pc = (block->endpc & 0x3ff) >> PAGE_MASK_SHIFT;
for (; start_pc <= end_pc; start_pc++)
block->page_mask2 |= ((uint64_t) 1 << start_pc);
page_2->code_present_mask[(block->phys_2 >> 10) & 3] |= block->page_mask2;
if (!pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3])
mem_flush_write_page(block->phys_2, block->endpc);
if (!block->page_mask2)
fatal("!page_mask2\n");
if (block->next_2) {
if (!block->next_2->valid)
fatal("block->next_2->valid=0 %p\n", (void *) block->next_2);
}
block->dirty_mask2 = &page_2->dirty_mask[(block->phys_2 >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK];
}
}
recomp_page = -1;
}
void
codegen_block_end(void)
{
codeblock_t *block = &codeblock[block_current];
codegen_block_generate_end_mask();
add_to_block_list(block);
}
void
codegen_block_end_recompile(codeblock_t *block)
{
codegen_timing_block_end();
codegen_accumulate(ACCREG_cycles, -codegen_block_cycles);
codegen_accumulate_flush();
addbyte(0x83); /*ADDL $16,%esp*/
addbyte(0xC4);
addbyte(0x10);
addbyte(0x5f); /*POP EDI*/
addbyte(0x5e); /*POP ESI*/
addbyte(0x5d); /*POP EBP*/
addbyte(0x5b); /*POP EDX*/
addbyte(0xC3); /*RET*/
if (block_pos > BLOCK_GPF_OFFSET)
fatal("Over limit!\n");
remove_from_block_list(block, block->pc);
block->next = block->prev = NULL;
block->next_2 = block->prev_2 = NULL;
codegen_block_generate_end_mask();
add_to_block_list(block);
if (!(block->flags & CODEBLOCK_HAS_FPU))
block->flags &= ~CODEBLOCK_STATIC_TOP;
}
void
codegen_flush(void)
{
return;
}
// clang-format off
static int opcode_modrm[256] = {
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*00*/
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*10*/
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*20*/
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*30*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*40*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*50*/
0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, /*60*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*70*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*80*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*90*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*a0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*b0*/
1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, /*d0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*e0*/
0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, /*f0*/
};
int opcode_0f_modrm[256] = {
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, /*00*/
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, /*10*/
1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*20*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, /*30*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*40*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*50*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, /*60*/
0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, /*70*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*80*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*90*/
0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, /*a0*/
1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, /*b0*/
1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, /*d0*/
0, 1, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, /*e0*/
0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 0 /*f0*/
};
// clang-format on
void
codegen_debug(void)
{
//
}
static x86seg *
codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
{
if (!cpu_mod && cpu_rm == 6) {
addbyte(0xC7); /*MOVL $0,(ssegs)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(eaaddr));
addlong((fetchdat >> 8) & 0xffff);
(*op_pc) += 2;
} else {
switch (cpu_mod) {
case 0:
addbyte(0xa1); /*MOVL *mod1add[0][cpu_rm], %eax*/
addlong((uint32_t) mod1add[0][cpu_rm]);
addbyte(0x03); /*ADDL *mod1add[1][cpu_rm], %eax*/
addbyte(0x05);
addlong((uint32_t) mod1add[1][cpu_rm]);
break;
case 1:
addbyte(0xb8); /*MOVL ,%eax*/
addlong((uint32_t) (int8_t) (rmdat >> 8));
addbyte(0x03); /*ADDL *mod1add[0][cpu_rm], %eax*/
addbyte(0x05);
addlong((uint32_t) mod1add[0][cpu_rm]);
addbyte(0x03); /*ADDL *mod1add[1][cpu_rm], %eax*/
addbyte(0x05);
addlong((uint32_t) mod1add[1][cpu_rm]);
(*op_pc)++;
break;
case 2:
addbyte(0xb8); /*MOVL ,%eax*/
addlong((fetchdat >> 8) & 0xffff);
addbyte(0x03); /*ADDL *mod1add[0][cpu_rm], %eax*/
addbyte(0x05);
addlong((uint32_t) mod1add[0][cpu_rm]);
addbyte(0x03); /*ADDL *mod1add[1][cpu_rm], %eax*/
addbyte(0x05);
addlong((uint32_t) mod1add[1][cpu_rm]);
(*op_pc) += 2;
break;
}
addbyte(0x25); /*ANDL $0xffff, %eax*/
addlong(0xffff);
addbyte(0xa3);
addlong((uint32_t) &cpu_state.eaaddr);
if (mod1seg[cpu_rm] == &ss && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
}
return op_ea_seg;
}
static x86seg *
codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc, int stack_offset)
{
uint32_t new_eaaddr;
if (cpu_rm == 4) {
uint8_t sib = fetchdat >> 8;
(*op_pc)++;
switch (cpu_mod) {
case 0:
if ((sib & 7) == 5) {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOVL ,%eax*/
addlong(new_eaaddr);
(*op_pc) += 4;
} else {
addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[sib & 7].l));
}
break;
case 1:
new_eaaddr = (uint32_t) (int8_t) ((fetchdat >> 16) & 0xff);
addbyte(0xb8); /*MOVL new_eaaddr, %eax*/
addlong(new_eaaddr);
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[sib & 7].l));
(*op_pc)++;
break;
case 2:
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOVL new_eaaddr, %eax*/
addlong(new_eaaddr);
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[sib & 7].l));
(*op_pc) += 4;
break;
}
if (stack_offset && (sib & 7) == 4 && (cpu_mod || (sib & 7) != 5)) /*ESP*/
{
addbyte(0x05);
addlong(stack_offset);
}
if (((sib & 7) == 4 || (cpu_mod && (sib & 7) == 5)) && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (((sib >> 3) & 7) != 4) {
switch (sib >> 6) {
case 0:
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[(sib >> 3) & 7].l));
break;
case 1:
addbyte(0x8B);
addbyte(0x5D);
addbyte((uint8_t) cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0x01);
addbyte(0xD8); /*ADDL %ebx,%eax*/
addbyte(0x01);
addbyte(0xD8); /*ADDL %ebx,%eax*/
break;
case 2:
addbyte(0x8B);
addbyte(0x5D);
addbyte((uint8_t) cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0xC1);
addbyte(0xE3);
addbyte(2); /*SHL $2,%ebx*/
addbyte(0x01);
addbyte(0xD8); /*ADDL %ebx,%eax*/
break;
case 3:
addbyte(0x8B);
addbyte(0x5D);
addbyte((uint8_t) cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0xC1);
addbyte(0xE3);
addbyte(3); /*SHL $2,%ebx*/
addbyte(0x01);
addbyte(0xD8); /*ADDL %ebx,%eax*/
break;
}
}
addbyte(0xa3);
addlong((uint32_t) &cpu_state.eaaddr);
} else {
if (!cpu_mod && cpu_rm == 5) {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(eaaddr));
addlong(new_eaaddr);
(*op_pc) += 4;
return op_ea_seg;
}
addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[cpu_rm].l));
cpu_state.eaaddr = cpu_state.regs[cpu_rm].l;
if (cpu_mod) {
if (cpu_rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (cpu_mod == 1) {
addbyte(0x05);
addlong((uint32_t) (int8_t) (fetchdat >> 8));
(*op_pc)++;
} else {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x05);
addlong(new_eaaddr);
(*op_pc) += 4;
}
}
addbyte(0xa3);
addlong((uint32_t) &cpu_state.eaaddr);
}
return op_ea_seg;
}
void
codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_pc, uint32_t old_pc)
{
codeblock_t *block = &codeblock[block_current];
uint32_t op_32 = use32;
uint32_t op_pc = new_pc;
const OpFn *op_table = x86_dynarec_opcodes;
RecompOpFn *recomp_op_table = recomp_opcodes;
int opcode_shift = 0;
int opcode_mask = 0x3ff;
int over = 0;
int pc_off = 0;
int test_modrm = 1;
int c;
op_ea_seg = &cpu_state.seg_ds;
op_ssegs = 0;
op_old_pc = old_pc;
for (c = 0; c < NR_HOST_REGS; c++)
host_reg_mapping[c] = -1;
mmx_ebx_ecx_loaded = 0;
for (c = 0; c < NR_HOST_XMM_REGS; c++)
host_reg_xmm_mapping[c] = -1;
codegen_timing_start();
while (!over) {
switch (opcode) {
case 0x0f:
op_table = x86_dynarec_opcodes_0f;
recomp_op_table = fpu_softfloat ? recomp_opcodes_0f_no_mmx : recomp_opcodes_0f;
over = 1;
break;
case 0x26: /*ES:*/
op_ea_seg = &cpu_state.seg_es;
op_ssegs = 1;
break;
case 0x2e: /*CS:*/
op_ea_seg = &cpu_state.seg_cs;
op_ssegs = 1;
break;
case 0x36: /*SS:*/
op_ea_seg = &cpu_state.seg_ss;
op_ssegs = 1;
break;
case 0x3e: /*DS:*/
op_ea_seg = &cpu_state.seg_ds;
op_ssegs = 1;
break;
case 0x64: /*FS:*/
op_ea_seg = &cpu_state.seg_fs;
op_ssegs = 1;
break;
case 0x65: /*GS:*/
op_ea_seg = &cpu_state.seg_gs;
op_ssegs = 1;
break;
case 0x66: /*Data size select*/
op_32 = ((use32 & 0x100) ^ 0x100) | (op_32 & 0x200);
break;
case 0x67: /*Address size select*/
op_32 = ((use32 & 0x200) ^ 0x200) | (op_32 & 0x100);
break;
case 0xd8:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d8_a32 : x86_dynarec_opcodes_d8_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_d8;
opcode_shift = 3;
opcode_mask = 0x1f;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xd9:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d9_a32 : x86_dynarec_opcodes_d9_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_d9;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xda:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_da_a32 : x86_dynarec_opcodes_da_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_da;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xdb:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_db_a32 : x86_dynarec_opcodes_db_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_db;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xdc:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_dc_a32 : x86_dynarec_opcodes_dc_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_dc;
opcode_shift = 3;
opcode_mask = 0x1f;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xdd:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_dd_a32 : x86_dynarec_opcodes_dd_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_dd;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xde:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_de_a32 : x86_dynarec_opcodes_de_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_de;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xdf:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_df_a32 : x86_dynarec_opcodes_df_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_df;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xf0: /*LOCK*/
break;
case 0xf2: /*REPNE*/
op_table = x86_dynarec_opcodes_REPNE;
recomp_op_table = recomp_opcodes_REPNE;
break;
case 0xf3: /*REPE*/
op_table = x86_dynarec_opcodes_REPE;
recomp_op_table = recomp_opcodes_REPE;
break;
default:
goto generate_call;
}
fetchdat = fastreadl(cs + op_pc);
codegen_timing_prefix(opcode, fetchdat);
if (cpu_state.abrt)
return;
opcode = fetchdat & 0xff;
if (!pc_off)
fetchdat >>= 8;
op_pc++;
}
generate_call:
codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);
codegen_accumulate(ACCREG_cycles, -codegen_block_cycles);
codegen_block_cycles = 0;
if ((op_table == x86_dynarec_opcodes && ((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 || (opcode & 0xfe) == 0xca || (opcode & 0xfc) == 0xcc || (opcode & 0xfc) == 0xe8 || (opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30)))) || (op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80))) {
/*On some CPUs (eg K6), a jump/branch instruction may be able to pair with
subsequent instructions, so no cycles may have been deducted for it yet.
To prevent having zero cycle blocks (eg with a jump instruction pointing
to itself), apply the cycles that would be taken if this jump is taken,
then reverse it for subsequent instructions if the jump is not taken*/
int jump_cycles = 0;
if (codegen_timing_jump_cycles != NULL)
jump_cycles = codegen_timing_jump_cycles();
if (jump_cycles)
codegen_accumulate(ACCREG_cycles, -jump_cycles);
codegen_accumulate_flush();
if (jump_cycles)
codegen_accumulate(ACCREG_cycles, jump_cycles);
}
if ((op_table == x86_dynarec_opcodes_REPNE || op_table == x86_dynarec_opcodes_REPE) && !op_table[opcode | op_32]) {
op_table = x86_dynarec_opcodes;
recomp_op_table = recomp_opcodes;
}
if (recomp_op_table && recomp_op_table[(opcode | op_32) & 0x1ff]) {
uint32_t new_pc = recomp_op_table[(opcode | op_32) & 0x1ff](opcode, fetchdat, op_32, op_pc, block);
if (new_pc) {
if (new_pc != -1)
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.pc, new_pc);
codegen_block_ins++;
block->ins++;
codegen_block_full_ins++;
codegen_endpc = (cs + cpu_state.pc) + 8;
# ifdef CHECK_INT
/* Check for interrupts. */
addbyte(0xf6); /* test byte ptr[&pic_pending],1 */
addbyte(0x05);
addlong((uint32_t) (uintptr_t) &pic_pending);
addbyte(0x01);
addbyte(0x0F);
addbyte(0x85); /*JNZ 0*/
addlong((uint32_t) &block->data[BLOCK_EXIT_OFFSET] - (uint32_t) (&block->data[block_pos + 4]));
# endif
return;
}
}
op = op_table[((opcode >> opcode_shift) | op_32) & opcode_mask];
if (op_ssegs != last_ssegs) {
last_ssegs = op_ssegs;
addbyte(0xC6); /*MOVB [ssegs],op_ssegs*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ssegs));
addbyte(op_pc + pc_off);
}
if (!test_modrm || (op_table == x86_dynarec_opcodes && opcode_modrm[opcode]) || (op_table == x86_dynarec_opcodes_0f && opcode_0f_modrm[opcode])) {
int stack_offset = 0;
if (op_table == x86_dynarec_opcodes && opcode == 0x8f) /*POP*/
stack_offset = (op_32 & 0x100) ? 4 : 2;
cpu_mod = (fetchdat >> 6) & 3;
cpu_reg = (fetchdat >> 3) & 7;
cpu_rm = fetchdat & 7;
addbyte(0xC7); /*MOVL $rm | mod | reg,(rm_mod_reg_data)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(rm_data.rm_mod_reg_data));
addlong(cpu_rm | (cpu_mod << 8) | (cpu_reg << 16));
op_pc += pc_off;
if (cpu_mod != 3 && !(op_32 & 0x200))
op_ea_seg = codegen_generate_ea_16_long(op_ea_seg, fetchdat, op_ssegs, &op_pc);
if (cpu_mod != 3 && (op_32 & 0x200))
op_ea_seg = codegen_generate_ea_32_long(op_ea_seg, fetchdat, op_ssegs, &op_pc, stack_offset);
op_pc -= pc_off;
}
if (op_ea_seg != last_ea_seg) {
last_ea_seg = op_ea_seg;
addbyte(0xC7); /*MOVL $&cpu_state.seg_ds,(ea_seg)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ea_seg));
addlong((uint32_t) op_ea_seg);
}
codegen_accumulate_flush();
addbyte(0xC7); /*MOVL pc,new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(op_pc + pc_off);
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(oldpc));
addlong(old_pc);
if (op_32 != last_op32) {
last_op32 = op_32;
addbyte(0xC7); /*MOVL $use32,(op32)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(op32));
addlong(op_32);
}
addbyte(0xC7); /*MOVL $fetchdat,(%esp)*/
addbyte(0x04);
addbyte(0x24);
addlong(fetchdat);
addbyte(0xE8); /*CALL*/
addlong(((uint8_t *) op - (uint8_t *) (&block->data[block_pos + 4])));
codegen_block_ins++;
block->ins++;
# ifdef CHECK_INT
/* Check for interrupts. */
addbyte(0x0a); /* or al,byte ptr[&pic_pending] */
addbyte(0x05);
addlong((uint32_t) (uintptr_t) &pic_pending);
# endif
addbyte(0x09); /*OR %eax, %eax*/
addbyte(0xc0);
addbyte(0x0F);
addbyte(0x85); /*JNZ 0*/
addlong((uint32_t) &block->data[BLOCK_EXIT_OFFSET] - (uint32_t) (&block->data[block_pos + 4]));
codegen_endpc = (cs + cpu_state.pc) + 8;
}
#endif
``` | /content/code_sandbox/src/codegen/codegen_x86.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 24,350 |
```objective-c
#define OP_XCHG_AX_(reg) \
static uint32_t \
ropXCHG_AX_##reg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int ax_reg, host_reg, temp_reg; \
\
ax_reg = LOAD_REG_W(REG_AX); \
host_reg = LOAD_REG_W(REG_##reg); \
temp_reg = COPY_REG(host_reg); \
STORE_REG_TARGET_W_RELEASE(ax_reg, REG_##reg); \
STORE_REG_TARGET_W_RELEASE(temp_reg, REG_AX); \
\
return op_pc; \
}
OP_XCHG_AX_(BX)
OP_XCHG_AX_(CX)
OP_XCHG_AX_(DX)
OP_XCHG_AX_(SI)
OP_XCHG_AX_(DI)
OP_XCHG_AX_(SP)
OP_XCHG_AX_(BP)
#define OP_XCHG_EAX_(reg) \
static uint32_t \
ropXCHG_EAX_##reg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int eax_reg, host_reg, temp_reg; \
\
eax_reg = LOAD_REG_L(REG_EAX); \
host_reg = LOAD_REG_L(REG_##reg); \
temp_reg = COPY_REG(host_reg); \
STORE_REG_TARGET_L_RELEASE(eax_reg, REG_##reg); \
STORE_REG_TARGET_L_RELEASE(temp_reg, REG_EAX); \
\
return op_pc; \
}
OP_XCHG_EAX_(EBX)
OP_XCHG_EAX_(ECX)
OP_XCHG_EAX_(EDX)
OP_XCHG_EAX_(ESI)
OP_XCHG_EAX_(EDI)
OP_XCHG_EAX_(ESP)
OP_XCHG_EAX_(EBP)
static uint32_t
ropXCHG_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
int temp_reg;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
dst_reg = LOAD_REG_B(fetchdat & 7);
src_reg = LOAD_REG_B((fetchdat >> 3) & 7);
temp_reg = COPY_REG(src_reg);
STORE_REG_TARGET_B_RELEASE(dst_reg, (fetchdat >> 3) & 7);
STORE_REG_TARGET_B_RELEASE(temp_reg, fetchdat & 7);
return op_pc + 1;
}
static uint32_t
ropXCHG_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
int temp_reg;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
dst_reg = LOAD_REG_W(fetchdat & 7);
src_reg = LOAD_REG_W((fetchdat >> 3) & 7);
temp_reg = COPY_REG(src_reg);
STORE_REG_TARGET_W_RELEASE(dst_reg, (fetchdat >> 3) & 7);
STORE_REG_TARGET_W_RELEASE(temp_reg, fetchdat & 7);
return op_pc + 1;
}
static uint32_t
ropXCHG_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
int temp_reg;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
dst_reg = LOAD_REG_L(fetchdat & 7);
src_reg = LOAD_REG_L((fetchdat >> 3) & 7);
temp_reg = COPY_REG(src_reg);
STORE_REG_TARGET_L_RELEASE(dst_reg, (fetchdat >> 3) & 7);
STORE_REG_TARGET_L_RELEASE(temp_reg, fetchdat & 7);
return op_pc + 1;
}
``` | /content/code_sandbox/src/codegen/codegen_ops_xchg.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 937 |
```c
#if defined __amd64__ || defined _M_X64
# include <stdarg.h>
# include <stdio.h>
# include <string.h>
# include <stdint.h>
# include <stdlib.h>
# define HAVE_STDARG_H
# include <86box/86box.h>
# include "cpu.h"
# include "x86.h"
# include "x86_flags.h"
# include "x86_ops.h"
# include "x86seg_common.h"
# include "x86seg.h"
# include "x87_sf.h"
# include "x87.h"
# include <86box/mem.h>
# include <86box/plat_unused.h>
# include "386_common.h"
# include "codegen.h"
# include "codegen_accumulate.h"
# include "codegen_ops.h"
# include "codegen_ops_x86-64.h"
# if defined(__unix__) || defined(__APPLE__) || defined(__HAIKU__)
# include <sys/mman.h>
# include <unistd.h>
# endif
# if _WIN64
# include <windows.h>
# endif
int codegen_flat_ds;
int codegen_flat_ss;
int codegen_flags_changed = 0;
int codegen_fpu_entered = 0;
int codegen_fpu_loaded_iq[8];
int codegen_reg_loaded[8];
x86seg *op_ea_seg;
int op_ssegs;
uint32_t op_old_pc;
uint32_t recomp_page = -1;
int host_reg_mapping[NR_HOST_REGS];
int host_reg_xmm_mapping[NR_HOST_XMM_REGS];
codeblock_t *codeblock;
codeblock_t **codeblock_hash;
int codegen_mmx_entered = 0;
int block_current = 0;
static int block_num;
int block_pos;
uint32_t codegen_endpc;
int codegen_block_cycles;
static int codegen_block_ins;
static int codegen_block_full_ins;
static uint32_t last_op32;
static x86seg *last_ea_seg;
static int last_ssegs;
void
codegen_init(void)
{
# if _WIN64
codeblock = VirtualAlloc(NULL, BLOCK_SIZE * sizeof(codeblock_t), MEM_COMMIT, PAGE_EXECUTE_READWRITE);
# elif defined(__unix__) || defined(__APPLE__) || defined(__HAIKU__)
codeblock = mmap(NULL, BLOCK_SIZE * sizeof(codeblock_t), PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0);
# else
codeblock = malloc(BLOCK_SIZE * sizeof(codeblock_t));
# endif
codeblock_hash = malloc(HASH_SIZE * sizeof(codeblock_t *));
memset(codeblock, 0, BLOCK_SIZE * sizeof(codeblock_t));
memset(codeblock_hash, 0, HASH_SIZE * sizeof(codeblock_t *));
for (int c = 0; c < BLOCK_SIZE; c++)
codeblock[c].valid = 0;
}
void
codegen_reset(void)
{
memset(codeblock, 0, BLOCK_SIZE * sizeof(codeblock_t));
memset(codeblock_hash, 0, HASH_SIZE * sizeof(codeblock_t *));
mem_reset_page_blocks();
for (int c = 0; c < BLOCK_SIZE; c++)
codeblock[c].valid = 0;
}
void
dump_block(void)
{
//
}
static void
add_to_block_list(codeblock_t *block)
{
codeblock_t *block_prev = pages[block->phys >> 12].block[(block->phys >> 10) & 3];
if (!block->page_mask)
fatal("add_to_block_list - mask = 0\n");
if (block_prev) {
block->next = block_prev;
block_prev->prev = block;
pages[block->phys >> 12].block[(block->phys >> 10) & 3] = block;
} else {
block->next = NULL;
pages[block->phys >> 12].block[(block->phys >> 10) & 3] = block;
}
if (block->next) {
if (block->next->valid == 0)
fatal("block->next->valid=0 %p %p %x %x\n", (void *) block->next, (void *) codeblock, block_current, block_pos);
}
if (block->page_mask2) {
block_prev = pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3];
if (block_prev) {
block->next_2 = block_prev;
block_prev->prev_2 = block;
pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3] = block;
} else {
block->next_2 = NULL;
pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3] = block;
}
}
}
static void
remove_from_block_list(codeblock_t *block, uint32_t pc)
{
if (!block->page_mask)
return;
if (block->prev) {
block->prev->next = block->next;
if (block->next)
block->next->prev = block->prev;
} else {
pages[block->phys >> 12].block[(block->phys >> 10) & 3] = block->next;
if (block->next)
block->next->prev = NULL;
else
mem_flush_write_page(block->phys, 0);
}
if (!block->page_mask2) {
if (block->prev_2 || block->next_2)
fatal("Invalid block_2\n");
return;
}
if (block->prev_2) {
block->prev_2->next_2 = block->next_2;
if (block->next_2)
block->next_2->prev_2 = block->prev_2;
} else {
pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3] = block->next_2;
if (block->next_2)
block->next_2->prev_2 = NULL;
else
mem_flush_write_page(block->phys_2, 0);
}
}
static void
delete_block(codeblock_t *block)
{
uint32_t old_pc = block->pc;
if (block == codeblock_hash[HASH(block->phys)])
codeblock_hash[HASH(block->phys)] = NULL;
if (block->valid == 0)
fatal("Deleting deleted block\n");
block->valid = 0;
codeblock_tree_delete(block);
remove_from_block_list(block, old_pc);
}
void
codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
{
struct codeblock_t *block = page->block[(phys_addr >> 10) & 3];
while (block) {
if (mask & block->page_mask) {
delete_block(block);
}
if (block == block->next)
fatal("Broken 1\n");
block = block->next;
}
block = page->block_2[(phys_addr >> 10) & 3];
while (block) {
if (mask & block->page_mask2) {
delete_block(block);
}
if (block == block->next_2)
fatal("Broken 2\n");
block = block->next_2;
}
}
void
codegen_block_init(uint32_t phys_addr)
{
codeblock_t *block;
page_t *page = &pages[phys_addr >> 12];
if (!page->block[(phys_addr >> 10) & 3])
mem_flush_write_page(phys_addr, cs + cpu_state.pc);
block_current = (block_current + 1) & BLOCK_MASK;
block = &codeblock[block_current];
if (block->valid != 0) {
delete_block(block);
}
block_num = HASH(phys_addr);
codeblock_hash[block_num] = &codeblock[block_current];
block->valid = 1;
block->ins = 0;
block->pc = cs + cpu_state.pc;
block->_cs = cs;
block->pnt = block_current;
block->phys = phys_addr;
block->dirty_mask = &page->dirty_mask[(phys_addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK];
block->dirty_mask2 = NULL;
block->next = block->prev = NULL;
block->next_2 = block->prev_2 = NULL;
block->page_mask = 0;
block->flags = 0;
block->status = cpu_cur_status;
block->was_recompiled = 0;
recomp_page = block->phys & ~0xfff;
codeblock_tree_add(block);
}
void
codegen_block_start_recompile(codeblock_t *block)
{
page_t *page = &pages[block->phys >> 12];
uintptr_t rip_rel;
if (!page->block[(block->phys >> 10) & 3])
mem_flush_write_page(block->phys, cs + cpu_state.pc);
block_num = HASH(block->phys);
block_current = block->pnt;
if (block->pc != cs + cpu_state.pc || block->was_recompiled)
fatal("Recompile to used block!\n");
block->status = cpu_cur_status;
block_pos = BLOCK_GPF_OFFSET;
# ifdef OLD_GPF
# if _WIN64
addbyte(0x48); /*XOR RCX, RCX*/
addbyte(0x31);
addbyte(0xc9);
addbyte(0x31); /*XOR EDX, EDX*/
addbyte(0xd2);
# else
addbyte(0x48); /*XOR RDI, RDI*/
addbyte(0x31);
addbyte(0xff);
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
# endif
call(block, (uintptr_t) x86gpf);
while (block_pos < BLOCK_EXIT_OFFSET)
addbyte(0x90); /*NOP*/
# else
addbyte(0xC6); /*MOVB ABRT_GPF,(abrt)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(ABRT_GPF);
addbyte(0x31); /* xor eax,eax */
addbyte(0xc0);
addbyte(0x89); /*MOVB eax,(abrt_error)*/
addbyte(0x85);
rip_rel = ((uintptr_t) &cpu_state) + 128;
rip_rel = ((uintptr_t) & (abrt_error)) - rip_rel;
addlong((uint32_t) rip_rel);
# endif
block_pos = BLOCK_EXIT_OFFSET; /*Exit code*/
addbyte(0x48); /*ADDL $40,%rsp*/
addbyte(0x83);
addbyte(0xC4);
addbyte(0x28);
addbyte(0x41); /*POP R15*/
addbyte(0x5f);
addbyte(0x41); /*POP R14*/
addbyte(0x5e);
addbyte(0x41); /*POP R13*/
addbyte(0x5d);
addbyte(0x41); /*POP R12*/
addbyte(0x5c);
addbyte(0x5f); /*POP RDI*/
addbyte(0x5e); /*POP RSI*/
addbyte(0x5d); /*POP RBP*/
addbyte(0x5b); /*POP RDX*/
addbyte(0xC3); /*RET*/
cpu_block_end = 0;
block_pos = 0; /*Entry code*/
addbyte(0x53); /*PUSH RBX*/
addbyte(0x55); /*PUSH RBP*/
addbyte(0x56); /*PUSH RSI*/
addbyte(0x57); /*PUSH RDI*/
addbyte(0x41); /*PUSH R12*/
addbyte(0x54);
addbyte(0x41); /*PUSH R13*/
addbyte(0x55);
addbyte(0x41); /*PUSH R14*/
addbyte(0x56);
addbyte(0x41); /*PUSH R15*/
addbyte(0x57);
addbyte(0x48); /*SUBL $40,%rsp*/
addbyte(0x83);
addbyte(0xEC);
addbyte(0x28);
addbyte(0x48); /*MOVL RBP, &cpu_state*/
addbyte(0xBD);
addquad(((uintptr_t) &cpu_state) + 128);
last_op32 = -1;
last_ea_seg = NULL;
last_ssegs = -1;
codegen_block_cycles = 0;
codegen_timing_block_start();
codegen_block_ins = 0;
codegen_block_full_ins = 0;
recomp_page = block->phys & ~0xfff;
codegen_flags_changed = 0;
codegen_fpu_entered = 0;
codegen_mmx_entered = 0;
codegen_fpu_loaded_iq[0] = codegen_fpu_loaded_iq[1] = codegen_fpu_loaded_iq[2] = codegen_fpu_loaded_iq[3] = codegen_fpu_loaded_iq[4] = codegen_fpu_loaded_iq[5] = codegen_fpu_loaded_iq[6] = codegen_fpu_loaded_iq[7] = 0;
cpu_state.seg_ds.checked = cpu_state.seg_es.checked = cpu_state.seg_fs.checked = cpu_state.seg_gs.checked = (cr0 & 1) ? 0 : 1;
codegen_reg_loaded[0] = codegen_reg_loaded[1] = codegen_reg_loaded[2] = codegen_reg_loaded[3] = codegen_reg_loaded[4] = codegen_reg_loaded[5] = codegen_reg_loaded[6] = codegen_reg_loaded[7] = 0;
block->was_recompiled = 1;
codegen_flat_ds = !(cpu_cur_status & CPU_STATUS_NOTFLATDS);
codegen_flat_ss = !(cpu_cur_status & CPU_STATUS_NOTFLATSS);
}
void
codegen_block_remove(void)
{
codeblock_t *block = &codeblock[block_current];
delete_block(block);
recomp_page = -1;
}
void
codegen_block_generate_end_mask(void)
{
codeblock_t *block = &codeblock[block_current];
uint32_t start_pc;
uint32_t end_pc;
block->endpc = codegen_endpc;
block->page_mask = 0;
start_pc = (block->pc & 0x3ff) & ~15;
if ((block->pc ^ block->endpc) & ~0x3ff)
end_pc = 0x3ff & ~15;
else
end_pc = (block->endpc & 0x3ff) & ~15;
if (end_pc < start_pc)
end_pc = 0x3ff;
start_pc >>= PAGE_MASK_SHIFT;
end_pc >>= PAGE_MASK_SHIFT;
for (; start_pc <= end_pc; start_pc++)
block->page_mask |= ((uint64_t) 1 << start_pc);
pages[block->phys >> 12].code_present_mask[(block->phys >> 10) & 3] |= block->page_mask;
block->phys_2 = -1;
block->page_mask2 = 0;
block->next_2 = block->prev_2 = NULL;
if ((block->pc ^ block->endpc) & ~0x3ff) {
block->phys_2 = get_phys_noabrt(block->endpc);
if (block->phys_2 != -1) {
page_t *page_2 = &pages[block->phys_2 >> 12];
start_pc = 0;
end_pc = (block->endpc & 0x3ff) >> PAGE_MASK_SHIFT;
for (; start_pc <= end_pc; start_pc++)
block->page_mask2 |= ((uint64_t) 1 << start_pc);
page_2->code_present_mask[(block->phys_2 >> 10) & 3] |= block->page_mask2;
if (!pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3])
mem_flush_write_page(block->phys_2, block->endpc);
if (!block->page_mask2)
fatal("!page_mask2\n");
if (block->next_2) {
if (block->next_2->valid == 0)
fatal("block->next_2->valid=0 %p\n", (void *) block->next_2);
}
block->dirty_mask2 = &page_2->dirty_mask[(block->phys_2 >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK];
}
}
recomp_page = -1;
}
void
codegen_block_end(void)
{
codeblock_t *block = &codeblock[block_current];
codegen_block_generate_end_mask();
add_to_block_list(block);
}
void
codegen_block_end_recompile(codeblock_t *block)
{
codegen_timing_block_end();
codegen_accumulate(ACCREG_cycles, -codegen_block_cycles);
codegen_accumulate_flush();
addbyte(0x48); /*ADDL $40,%rsp*/
addbyte(0x83);
addbyte(0xC4);
addbyte(0x28);
addbyte(0x41); /*POP R15*/
addbyte(0x5f);
addbyte(0x41); /*POP R14*/
addbyte(0x5e);
addbyte(0x41); /*POP R13*/
addbyte(0x5d);
addbyte(0x41); /*POP R12*/
addbyte(0x5c);
addbyte(0x5f); /*POP RDI*/
addbyte(0x5e); /*POP RSI*/
addbyte(0x5d); /*POP RBP*/
addbyte(0x5b); /*POP RDX*/
addbyte(0xC3); /*RET*/
if (block_pos > BLOCK_GPF_OFFSET)
fatal("Over limit!\n");
remove_from_block_list(block, block->pc);
block->next = block->prev = NULL;
block->next_2 = block->prev_2 = NULL;
codegen_block_generate_end_mask();
add_to_block_list(block);
}
void
codegen_flush(void)
{
return;
}
// clang-format off
static int opcode_modrm[256] = {
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*00*/
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*10*/
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*20*/
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*30*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*40*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*50*/
0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, /*60*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*70*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*80*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*90*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*a0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*b0*/
1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, /*d0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*e0*/
0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, /*f0*/
};
int opcode_0f_modrm[256] = {
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, /*00*/
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, /*10*/
1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*20*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, /*30*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*40*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*50*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, /*60*/
0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, /*70*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*80*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*90*/
0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, /*a0*/
1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, /*b0*/
1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, /*d0*/
0, 1, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, /*e0*/
0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 0 /*f0*/
};
// clang-format off
void
codegen_debug(void)
{
//
}
static x86seg *
codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
{
if (!cpu_mod && cpu_rm == 6) {
addbyte(0xC7); /*MOVL $0,(ssegs)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(eaaddr));
addlong((fetchdat >> 8) & 0xffff);
(*op_pc) += 2;
} else {
int base_reg = 0, index_reg = 0;
switch (cpu_rm) {
case 0:
case 1:
case 7:
base_reg = LOAD_REG_W(REG_BX);
break;
case 2:
case 3:
case 6:
base_reg = LOAD_REG_W(REG_BP);
break;
case 4:
base_reg = LOAD_REG_W(REG_SI);
break;
case 5:
base_reg = LOAD_REG_W(REG_DI);
break;
}
if (!(cpu_rm & 4)) {
if (cpu_rm & 1)
index_reg = LOAD_REG_W(REG_DI);
else
index_reg = LOAD_REG_W(REG_SI);
}
base_reg &= 7;
index_reg &= 7;
switch (cpu_mod) {
case 0:
if (cpu_rm & 4) {
addbyte(0x41); /*MOVZX EAX, base_reg*/
addbyte(0x0f);
addbyte(0xb7);
addbyte(0xc0 | base_reg);
} else {
addbyte(0x67); /*LEA EAX, base_reg+index_reg*/
addbyte(0x43);
addbyte(0x8d);
if (base_reg == 5) {
addbyte(0x44);
addbyte(base_reg | (index_reg << 3));
addbyte(0);
} else {
addbyte(0x04);
addbyte(base_reg | (index_reg << 3));
}
}
break;
case 1:
if (cpu_rm & 4) {
addbyte(0x67); /*LEA EAX, base_reg+imm8*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x40 | base_reg);
addbyte((fetchdat >> 8) & 0xff);
} else {
addbyte(0x67); /*LEA EAX, base_reg+index_reg+imm8*/
addbyte(0x43);
addbyte(0x8d);
addbyte(0x44);
addbyte(base_reg | (index_reg << 3));
addbyte((fetchdat >> 8) & 0xff);
}
(*op_pc)++;
break;
case 2:
if (cpu_rm & 4) {
addbyte(0x67); /*LEA EAX, base_reg+imm8*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x80 | base_reg);
addlong((fetchdat >> 8) & 0xffff);
} else {
addbyte(0x67); /*LEA EAX, base_reg+index_reg+imm16*/
addbyte(0x43);
addbyte(0x8d);
addbyte(0x84);
addbyte(base_reg | (index_reg << 3));
addlong((fetchdat >> 8) & 0xffff);
}
(*op_pc) += 2;
break;
}
if (cpu_mod || !(cpu_rm & 4)) {
addbyte(0x25); /*ANDL $0xffff, %eax*/
addlong(0xffff);
}
addbyte(0x89); /*MOV eaaddr, EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(eaaddr));
if (mod1seg[cpu_rm] == &ss && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
}
return op_ea_seg;
}
// #if 0
static x86seg *
codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc, int stack_offset)
{
uint32_t new_eaaddr;
if (cpu_rm == 4) {
uint8_t sib = fetchdat >> 8;
int base_reg = -1, index_reg = -1;
(*op_pc)++;
if (cpu_mod || (sib & 7) != 5)
base_reg = LOAD_REG_L(sib & 7) & 7;
if (((sib >> 3) & 7) != 4)
index_reg = LOAD_REG_L((sib >> 3) & 7) & 7;
if (index_reg == -1) {
switch (cpu_mod) {
case 0:
if ((sib & 7) == 5) {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOV EAX, imm32*/
addlong(new_eaaddr);
(*op_pc) += 4;
} else {
addbyte(0x44); /*MOV EAX, base_reg*/
addbyte(0x89);
addbyte(0xc0 | (base_reg << 3));
}
break;
case 1:
addbyte(0x67); /*LEA EAX, imm8+base_reg*/
addbyte(0x41);
addbyte(0x8d);
if (base_reg == 4) {
addbyte(0x44);
addbyte(0x24);
} else {
addbyte(0x40 | base_reg);
}
addbyte((fetchdat >> 16) & 0xff);
(*op_pc)++;
break;
case 2:
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x67); /*LEA EAX, imm32+base_reg*/
addbyte(0x41);
addbyte(0x8d);
if (base_reg == 4) {
addbyte(0x84);
addbyte(0x24);
} else {
addbyte(0x80 | base_reg);
}
addlong(new_eaaddr);
(*op_pc) += 4;
break;
}
} else {
switch (cpu_mod) {
case 0:
if ((sib & 7) == 5) {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
if (sib >> 6) {
addbyte(0x67); /*LEA EAX, imm32+index_reg*scale*/
addbyte(0x42);
addbyte(0x8d);
addbyte(0x04);
addbyte(0x05 | (sib & 0xc0) | (index_reg << 3));
addlong(new_eaaddr);
} else {
addbyte(0x67); /*LEA EAX, imm32+index_reg*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x80 | index_reg);
addlong(new_eaaddr);
}
(*op_pc) += 4;
} else {
addbyte(0x67); /*LEA EAX, base_reg+index_reg*scale*/
addbyte(0x43);
addbyte(0x8d);
if (base_reg == 5) {
addbyte(0x44);
addbyte(base_reg | (index_reg << 3) | (sib & 0xc0));
addbyte(0);
} else {
addbyte(0x04);
addbyte(base_reg | (index_reg << 3) | (sib & 0xc0));
}
}
break;
case 1:
addbyte(0x67); /*LEA EAX, imm8+base_reg+index_reg*scale*/
addbyte(0x43);
addbyte(0x8d);
addbyte(0x44);
addbyte(base_reg | (index_reg << 3) | (sib & 0xc0));
addbyte((fetchdat >> 16) & 0xff);
(*op_pc)++;
break;
case 2:
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x67); /*LEA EAX, imm32+base_reg+index_reg*scale*/
addbyte(0x43);
addbyte(0x8d);
addbyte(0x84);
addbyte(base_reg | (index_reg << 3) | (sib & 0xc0));
addlong(new_eaaddr);
(*op_pc) += 4;
break;
}
}
if (stack_offset && (sib & 7) == 4 && (cpu_mod || (sib & 7) != 5)) /*ESP*/
{
addbyte(0x05);
addlong(stack_offset);
}
if (((sib & 7) == 4 || (cpu_mod && (sib & 7) == 5)) && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
addbyte(0x89); /*MOV eaaddr, EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(eaaddr));
} else {
int base_reg;
if (!cpu_mod && cpu_rm == 5) {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(eaaddr));
addlong(new_eaaddr);
(*op_pc) += 4;
return op_ea_seg;
}
base_reg = LOAD_REG_L(cpu_rm) & 7;
if (cpu_mod) {
if (cpu_rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (cpu_mod == 1) {
addbyte(0x67); /*LEA EAX, base_reg+imm8*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x40 | base_reg);
addbyte((fetchdat >> 8) & 0xff);
(*op_pc)++;
} else {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x67); /*LEA EAX, base_reg+imm32*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x80 | base_reg);
addlong(new_eaaddr);
(*op_pc) += 4;
}
addbyte(0x89); /*MOV eaaddr, EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(eaaddr));
} else {
addbyte(0x44); /*MOV eaaddr, base_reg*/
addbyte(0x89);
addbyte(0x45 | (base_reg << 3));
addbyte((uint8_t) cpu_state_offset(eaaddr));
}
}
return op_ea_seg;
}
// #endif
void
codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_pc, uint32_t old_pc)
{
codeblock_t *block = &codeblock[block_current];
uint32_t op_32 = use32;
uint32_t op_pc = new_pc;
const OpFn *op_table = (OpFn *) x86_dynarec_opcodes;
RecompOpFn *recomp_op_table = recomp_opcodes;
int opcode_shift = 0;
int opcode_mask = 0x3ff;
int over = 0;
int pc_off = 0;
int test_modrm = 1;
int c;
op_ea_seg = &cpu_state.seg_ds;
op_ssegs = 0;
op_old_pc = old_pc;
for (c = 0; c < NR_HOST_REGS; c++)
host_reg_mapping[c] = -1;
for (c = 0; c < NR_HOST_XMM_REGS; c++)
host_reg_xmm_mapping[c] = -1;
codegen_timing_start();
while (!over) {
switch (opcode) {
case 0x0f:
op_table = x86_dynarec_opcodes_0f;
recomp_op_table = fpu_softfloat ? recomp_opcodes_0f_no_mmx : recomp_opcodes_0f;
over = 1;
break;
case 0x26: /*ES:*/
op_ea_seg = &cpu_state.seg_es;
op_ssegs = 1;
break;
case 0x2e: /*CS:*/
op_ea_seg = &cpu_state.seg_cs;
op_ssegs = 1;
break;
case 0x36: /*SS:*/
op_ea_seg = &cpu_state.seg_ss;
op_ssegs = 1;
break;
case 0x3e: /*DS:*/
op_ea_seg = &cpu_state.seg_ds;
op_ssegs = 1;
break;
case 0x64: /*FS:*/
op_ea_seg = &cpu_state.seg_fs;
op_ssegs = 1;
break;
case 0x65: /*GS:*/
op_ea_seg = &cpu_state.seg_gs;
op_ssegs = 1;
break;
case 0x66: /*Data size select*/
op_32 = ((use32 & 0x100) ^ 0x100) | (op_32 & 0x200);
break;
case 0x67: /*Address size select*/
op_32 = ((use32 & 0x200) ^ 0x200) | (op_32 & 0x100);
break;
case 0xd8:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d8_a32 : x86_dynarec_opcodes_d8_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_d8;
opcode_shift = 3;
opcode_mask = 0x1f;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xd9:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d9_a32 : x86_dynarec_opcodes_d9_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_d9;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xda:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_da_a32 : x86_dynarec_opcodes_da_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_da;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xdb:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_db_a32 : x86_dynarec_opcodes_db_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_db;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xdc:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_dc_a32 : x86_dynarec_opcodes_dc_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_dc;
opcode_shift = 3;
opcode_mask = 0x1f;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xdd:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_dd_a32 : x86_dynarec_opcodes_dd_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_dd;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xde:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_de_a32 : x86_dynarec_opcodes_de_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_de;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xdf:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_df_a32 : x86_dynarec_opcodes_df_a16;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_df;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xf0: /*LOCK*/
break;
case 0xf2: /*REPNE*/
op_table = x86_dynarec_opcodes_REPNE;
recomp_op_table = recomp_opcodes_REPNE;
break;
case 0xf3: /*REPE*/
op_table = x86_dynarec_opcodes_REPE;
recomp_op_table = recomp_opcodes_REPE;
break;
default:
goto generate_call;
}
fetchdat = fastreadl(cs + op_pc);
codegen_timing_prefix(opcode, fetchdat);
if (cpu_state.abrt)
return;
opcode = fetchdat & 0xff;
if (!pc_off)
fetchdat >>= 8;
op_pc++;
}
generate_call:
codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);
codegen_accumulate(ACCREG_cycles, -codegen_block_cycles);
codegen_block_cycles = 0;
if ((op_table == x86_dynarec_opcodes && ((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 || (opcode & 0xfe) == 0xca || (opcode & 0xfc) == 0xcc || (opcode & 0xfc) == 0xe8 || (opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30)))) || (op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80))) {
/*On some CPUs (eg K6), a jump/branch instruction may be able to pair with
subsequent instructions, so no cycles may have been deducted for it yet.
To prevent having zero cycle blocks (eg with a jump instruction pointing
to itself), apply the cycles that would be taken if this jump is taken,
then reverse it for subsequent instructions if the jump is not taken*/
int jump_cycles = 0;
if (codegen_timing_jump_cycles != NULL)
jump_cycles = codegen_timing_jump_cycles();
if (jump_cycles)
codegen_accumulate(ACCREG_cycles, -jump_cycles);
codegen_accumulate_flush();
if (jump_cycles)
codegen_accumulate(ACCREG_cycles, jump_cycles);
}
if ((op_table == x86_dynarec_opcodes_REPNE || op_table == x86_dynarec_opcodes_REPE) && !op_table[opcode | op_32]) {
op_table = x86_dynarec_opcodes;
recomp_op_table = recomp_opcodes;
}
if (recomp_op_table && recomp_op_table[(opcode | op_32) & 0x1ff]) {
uint32_t new_pc = recomp_op_table[(opcode | op_32) & 0x1ff](opcode, fetchdat, op_32, op_pc, block);
if (new_pc) {
if (new_pc != -1)
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.pc, new_pc);
codegen_block_ins++;
block->ins++;
codegen_block_full_ins++;
codegen_endpc = (cs + cpu_state.pc) + 8;
# ifdef CHECK_INT
/* Check for interrupts. */
addbyte(0xf6); /* test byte ptr[&pic_pending],1 */
addbyte(0x04);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &pic_pending);
addbyte(0x01);
addbyte(0x0F);
addbyte(0x85); /*JNZ 0*/
addlong((uint32_t) (uintptr_t) &block->data[BLOCK_EXIT_OFFSET] - (uint32_t) (uintptr_t) (&block->data[block_pos + 4]));
# endif
return;
}
}
op = op_table[((opcode >> opcode_shift) | op_32) & opcode_mask];
if (op_ssegs != last_ssegs) {
last_ssegs = op_ssegs;
addbyte(0xC6); /*MOVB $0,(ssegs)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ssegs));
addbyte(op_ssegs);
}
if ((!test_modrm || (op_table == x86_dynarec_opcodes && opcode_modrm[opcode]) || (op_table == x86_dynarec_opcodes_0f && opcode_0f_modrm[opcode])) /* && !(op_32 & 0x200)*/) {
int stack_offset = 0;
if (op_table == x86_dynarec_opcodes && opcode == 0x8f) /*POP*/
stack_offset = (op_32 & 0x100) ? 4 : 2;
cpu_mod = (fetchdat >> 6) & 3;
cpu_reg = (fetchdat >> 3) & 7;
cpu_rm = fetchdat & 7;
addbyte(0xC7); /*MOVL $rm | mod | reg,(rm_mod_reg_data)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(rm_data.rm_mod_reg_data));
addlong(cpu_rm | (cpu_mod << 8) | (cpu_reg << 16));
op_pc += pc_off;
if (cpu_mod != 3 && !(op_32 & 0x200))
op_ea_seg = codegen_generate_ea_16_long(op_ea_seg, fetchdat, op_ssegs, &op_pc);
if (cpu_mod != 3 && (op_32 & 0x200))
op_ea_seg = codegen_generate_ea_32_long(op_ea_seg, fetchdat, op_ssegs, &op_pc, stack_offset);
op_pc -= pc_off;
}
if (op_ea_seg != last_ea_seg) {
addbyte(0xC7); /*MOVL $&_ds,(ea_seg)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ea_seg));
addlong((uint32_t) (uintptr_t) op_ea_seg);
}
codegen_accumulate_flush();
addbyte(0xC7); /*MOVL [pc],new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(op_pc + pc_off);
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(oldpc));
addlong(old_pc);
if (op_32 != last_op32) {
last_op32 = op_32;
addbyte(0xC7); /*MOVL $use32,(op32)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(op32));
addlong(op_32);
}
load_param_1_32(block, fetchdat);
call(block, (uintptr_t) op);
codegen_block_ins++;
block->ins++;
# ifdef CHECK_INT
/* Check for interrupts. */
addbyte(0x0a); /* or al,byte ptr[&pic_pending] */
addbyte(0x04);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &pic_pending);
# endif
addbyte(0x85); /*OR %eax, %eax*/
addbyte(0xc0);
addbyte(0x0F);
addbyte(0x85); /*JNZ 0*/
addlong((uint32_t) (uintptr_t) &block->data[BLOCK_EXIT_OFFSET] - (uint32_t) (uintptr_t) (&block->data[block_pos + 4]));
codegen_endpc = (cs + cpu_state.pc) + 8;
}
#endif
``` | /content/code_sandbox/src/codegen/codegen_x86-64.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 12,031 |
```objective-c
static uint32_t
ropNOP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
return op_pc;
}
static uint32_t
ropCLD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
CLEAR_BITS((uintptr_t) &cpu_state.flags, D_FLAG);
return op_pc;
}
static uint32_t
ropSTD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
SET_BITS((uintptr_t) &cpu_state.flags, D_FLAG);
return op_pc;
}
static uint32_t
ropCLI(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if (!IOPLp && (cr4 & (CR4_VME | CR4_PVI)))
return 0;
CLEAR_BITS((uintptr_t) &cpu_state.flags, I_FLAG);
#ifdef CHECK_INT
CLEAR_BITS((uintptr_t) &pic_pending, 0xffffffff);
#endif
return op_pc;
}
static uint32_t
ropSTI(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if (!IOPLp && (cr4 & (CR4_VME | CR4_PVI)))
return 0;
SET_BITS((uintptr_t) &cpu_state.flags, I_FLAG);
return op_pc;
}
static uint32_t
ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg = NULL;
int host_reg;
if ((fetchdat & 0x30) != 0x00)
return 0;
CALL_FUNC((uintptr_t) flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_B(fetchdat & 7);
else {
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
SAVE_EA();
MEM_CHECK_WRITE(target_seg);
host_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg);
}
switch (fetchdat & 0x38) {
case 0x00: /*INC*/
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_B(host_reg, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_INC8);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, host_reg);
break;
case 0x08: /*DEC*/
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_B(host_reg, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_DEC8);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, host_reg);
break;
}
if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_B_RELEASE(host_reg);
else {
LOAD_EA();
MEM_STORE_ADDR_EA_B_NO_ABRT(target_seg, host_reg);
}
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t codegen_temp;
static uint32_t
ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg = NULL;
int host_reg;
if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08))
return 0;
if ((fetchdat & 0x30) == 0x00)
CALL_FUNC((uintptr_t) flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_W(fetchdat & 7);
else {
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x30) != 0x00) {
MEM_LOAD_ADDR_EA_W(target_seg);
host_reg = 0;
} else {
SAVE_EA();
MEM_CHECK_WRITE_W(target_seg);
host_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg);
}
}
switch (fetchdat & 0x38) {
case 0x00: /*INC*/
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_W_RELEASE(host_reg);
else {
LOAD_EA();
MEM_STORE_ADDR_EA_W_NO_ABRT(target_seg, host_reg);
}
codegen_flags_changed = 1;
return op_pc + 1;
case 0x08: /*DEC*/
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_DEC16);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_W_RELEASE(host_reg);
else {
LOAD_EA();
MEM_STORE_ADDR_EA_W_NO_ABRT(target_seg, host_reg);
}
codegen_flags_changed = 1;
return op_pc + 1;
case 0x10: /*CALL*/
STORE_HOST_REG_ADDR_W((uintptr_t) &codegen_temp, host_reg);
RELEASE_REG(host_reg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-2);
host_reg = LOAD_REG_IMM(op_pc + 1);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
host_reg = LOAD_VAR_W((uintptr_t) &codegen_temp);
STORE_HOST_REG_ADDR_W((uintptr_t) &cpu_state.pc, host_reg);
return -1;
case 0x20: /*JMP*/
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.pc, host_reg);
return -1;
case 0x30: /*PUSH*/
if (!host_reg)
host_reg = LOAD_HOST_REG(host_reg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-2);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
return op_pc + 1;
}
return 0;
}
static uint32_t
ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg = NULL;
int host_reg;
if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08))
return 0;
if ((fetchdat & 0x30) == 0x00)
CALL_FUNC((uintptr_t) flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_L(fetchdat & 7);
else {
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x30) != 0x00) {
MEM_LOAD_ADDR_EA_L(target_seg);
host_reg = 0;
} else {
SAVE_EA();
MEM_CHECK_WRITE_L(target_seg);
host_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg);
}
}
switch (fetchdat & 0x38) {
case 0x00: /*INC*/
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_INC32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_L_RELEASE(host_reg);
else {
LOAD_EA();
MEM_STORE_ADDR_EA_L_NO_ABRT(target_seg, host_reg);
}
codegen_flags_changed = 1;
return op_pc + 1;
case 0x08: /*DEC*/
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_DEC32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_L_RELEASE(host_reg);
else {
LOAD_EA();
MEM_STORE_ADDR_EA_L_NO_ABRT(target_seg, host_reg);
}
codegen_flags_changed = 1;
return op_pc + 1;
case 0x10: /*CALL*/
STORE_HOST_REG_ADDR((uintptr_t) &codegen_temp, host_reg);
RELEASE_REG(host_reg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-4);
host_reg = LOAD_REG_IMM(op_pc + 1);
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
host_reg = LOAD_VAR_L((uintptr_t) &codegen_temp);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.pc, host_reg);
return -1;
case 0x20: /*JMP*/
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.pc, host_reg);
return -1;
case 0x30: /*PUSH*/
if (!host_reg)
host_reg = LOAD_HOST_REG(host_reg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-4);
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
return op_pc + 1;
}
return 0;
}
``` | /content/code_sandbox/src/codegen/codegen_ops_misc.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,603 |
```objective-c
#ifndef _CODEGEN_OPS_H_
#define _CODEGEN_OPS_H_
#include "codegen.h"
typedef uint32_t (*RecompOpFn)(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block);
extern RecompOpFn recomp_opcodes[512];
extern RecompOpFn recomp_opcodes_0f[512];
extern RecompOpFn recomp_opcodes_0f_no_mmx[512];
extern RecompOpFn recomp_opcodes_d8[512];
extern RecompOpFn recomp_opcodes_d9[512];
extern RecompOpFn recomp_opcodes_da[512];
extern RecompOpFn recomp_opcodes_db[512];
extern RecompOpFn recomp_opcodes_dc[512];
extern RecompOpFn recomp_opcodes_dd[512];
extern RecompOpFn recomp_opcodes_de[512];
extern RecompOpFn recomp_opcodes_df[512];
extern RecompOpFn recomp_opcodes_REPE[512];
extern RecompOpFn recomp_opcodes_REPNE[512];
#define REG_EAX 0
#define REG_ECX 1
#define REG_EDX 2
#define REG_EBX 3
#define REG_ESP 4
#define REG_EBP 5
#define REG_ESI 6
#define REG_EDI 7
#define REG_AX 0
#define REG_CX 1
#define REG_DX 2
#define REG_BX 3
#define REG_SP 4
#define REG_BP 5
#define REG_SI 6
#define REG_DI 7
#define REG_AL 0
#define REG_AH 4
#define REG_CL 1
#define REG_CH 5
#define REG_DL 2
#define REG_DH 6
#define REG_BL 3
#define REG_BH 7
#endif
``` | /content/code_sandbox/src/codegen/codegen_ops.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 416 |
```objective-c
static uint32_t
ropMOV_rb_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
STORE_IMM_REG_B(opcode & 7, fetchdat & 0xff);
return op_pc + 1;
}
static uint32_t
ropMOV_rw_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
STORE_IMM_REG_W(opcode & 7, fetchdat & 0xffff);
return op_pc + 2;
}
static uint32_t
ropMOV_rl_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
fetchdat = fastreadl(cs + op_pc);
STORE_IMM_REG_L(opcode & 7, fetchdat);
return op_pc + 4;
}
static uint32_t
ropMOV_b_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_B((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0) {
STORE_REG_TARGET_B_RELEASE(host_reg, fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 0);
MEM_STORE_ADDR_EA_B(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
}
static uint32_t
ropMOV_w_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0) {
STORE_REG_TARGET_W_RELEASE(host_reg, fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 1);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
}
static uint32_t
ropMOV_l_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
host_reg = LOAD_REG_L((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0) {
STORE_REG_TARGET_L_RELEASE(host_reg, fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 3);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
}
static uint32_t
ropMOV_r_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
int host_reg = LOAD_REG_B(fetchdat & 7);
STORE_REG_TARGET_B_RELEASE(host_reg, (fetchdat >> 3) & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
STORE_REG_TARGET_B_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t
ropMOV_r_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
int host_reg = LOAD_REG_W(fetchdat & 7);
STORE_REG_TARGET_W_RELEASE(host_reg, (fetchdat >> 3) & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
STORE_REG_TARGET_W_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t
ropMOV_r_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
int host_reg = LOAD_REG_L(fetchdat & 7);
STORE_REG_TARGET_L_RELEASE(host_reg, (fetchdat >> 3) & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t
ropMOV_b_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
STORE_IMM_REG_B(fetchdat & 7, (fetchdat >> 8) & 0xff);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
uint32_t imm = fastreadb(cs + op_pc + 1);
int host_reg = LOAD_REG_IMM(imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_B(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 2;
}
static uint32_t
ropMOV_w_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
STORE_IMM_REG_W(fetchdat & 7, (fetchdat >> 8) & 0xffff);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
uint32_t imm = fastreadw(cs + op_pc + 1);
int host_reg = LOAD_REG_IMM(imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 3;
}
static uint32_t
ropMOV_l_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
uint32_t imm = fastreadl(cs + op_pc + 1);
STORE_IMM_REG_L(fetchdat & 7, imm);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
uint32_t imm = fastreadl(cs + op_pc + 1);
int host_reg = LOAD_REG_IMM(imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 5;
}
static uint32_t
ropMOV_AL_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t addr;
if (op_32 & 0x200)
addr = fastreadl(cs + op_pc);
else
addr = fastreadw(cs + op_pc);
CHECK_SEG_READ(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_IMM_B(op_ea_seg, addr);
STORE_REG_TARGET_B_RELEASE(0, REG_AL);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t
ropMOV_AX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t addr;
if (op_32 & 0x200)
addr = fastreadl(cs + op_pc);
else
addr = fastreadw(cs + op_pc);
CHECK_SEG_READ(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_IMM_W(op_ea_seg, addr);
STORE_REG_TARGET_W_RELEASE(0, REG_AX);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t
ropMOV_EAX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t addr;
if (op_32 & 0x200)
addr = fastreadl(cs + op_pc);
else
addr = fastreadw(cs + op_pc);
CHECK_SEG_READ(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_IMM_L(op_ea_seg, addr);
STORE_REG_TARGET_L_RELEASE(0, REG_EAX);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t
ropMOV_a_AL(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t addr;
int host_reg;
if (op_32 & 0x200)
addr = fastreadl(cs + op_pc);
else
addr = fastreadw(cs + op_pc);
CHECK_SEG_WRITE(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
host_reg = LOAD_REG_B(REG_AL);
MEM_STORE_ADDR_IMM_B(op_ea_seg, addr, host_reg);
RELEASE_REG(host_reg);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t
ropMOV_a_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t addr;
int host_reg;
if (op_32 & 0x200)
addr = fastreadl(cs + op_pc);
else
addr = fastreadw(cs + op_pc);
CHECK_SEG_WRITE(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
host_reg = LOAD_REG_W(REG_AX);
MEM_STORE_ADDR_IMM_W(op_ea_seg, addr, host_reg);
RELEASE_REG(host_reg);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t
ropMOV_a_EAX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t addr;
int host_reg;
if (op_32 & 0x200)
addr = fastreadl(cs + op_pc);
else
addr = fastreadw(cs + op_pc);
CHECK_SEG_WRITE(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
host_reg = LOAD_REG_L(REG_EAX);
MEM_STORE_ADDR_IMM_L(op_ea_seg, addr, host_reg);
RELEASE_REG(host_reg);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t
ropLEA_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
return 0;
FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_REG_TARGET_W_RELEASE(0, dest_reg);
return op_pc + 1;
}
static uint32_t
ropLEA_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
return 0;
FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_REG_TARGET_L_RELEASE(0, dest_reg);
return op_pc + 1;
}
static uint32_t
ropMOVZX_w_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
int host_reg = LOAD_REG_B(fetchdat & 7);
host_reg = ZERO_EXTEND_W_B(host_reg);
STORE_REG_TARGET_W_RELEASE(host_reg, (fetchdat >> 3) & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
ZERO_EXTEND_W_B(0);
STORE_REG_TARGET_W_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t
ropMOVZX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
int host_reg = LOAD_REG_B(fetchdat & 7);
host_reg = ZERO_EXTEND_L_B(host_reg);
STORE_REG_TARGET_L_RELEASE(host_reg, (fetchdat >> 3) & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
ZERO_EXTEND_L_B(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t
ropMOVZX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
int host_reg = LOAD_REG_W(fetchdat & 7);
host_reg = ZERO_EXTEND_L_W(host_reg);
STORE_REG_TARGET_L_RELEASE(host_reg, (fetchdat >> 3) & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
ZERO_EXTEND_L_W(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t
ropMOVSX_w_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
int host_reg = LOAD_REG_B(fetchdat & 7);
host_reg = SIGN_EXTEND_W_B(host_reg);
STORE_REG_TARGET_W_RELEASE(host_reg, (fetchdat >> 3) & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
SIGN_EXTEND_W_B(0);
STORE_REG_TARGET_W_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t
ropMOVSX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
int host_reg = LOAD_REG_B(fetchdat & 7);
host_reg = SIGN_EXTEND_L_B(host_reg);
STORE_REG_TARGET_L_RELEASE(host_reg, (fetchdat >> 3) & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
SIGN_EXTEND_L_B(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t
ropMOVSX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if ((fetchdat & 0xc0) == 0xc0) {
int host_reg = LOAD_REG_W(fetchdat & 7);
host_reg = SIGN_EXTEND_L_W(host_reg);
STORE_REG_TARGET_L_RELEASE(host_reg, (fetchdat >> 3) & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
SIGN_EXTEND_L_W(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t
ropMOV_w_seg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
switch (fetchdat & 0x38) {
case 0x00: /*ES*/
host_reg = LOAD_VAR_WL((uintptr_t) &ES);
break;
case 0x08: /*CS*/
host_reg = LOAD_VAR_WL((uintptr_t) &CS);
break;
case 0x18: /*DS*/
host_reg = LOAD_VAR_WL((uintptr_t) &DS);
break;
case 0x10: /*SS*/
host_reg = LOAD_VAR_WL((uintptr_t) &SS);
break;
case 0x20: /*FS*/
host_reg = LOAD_VAR_WL((uintptr_t) &FS);
break;
case 0x28: /*GS*/
host_reg = LOAD_VAR_WL((uintptr_t) &GS);
break;
default:
return 0;
}
if ((fetchdat & 0xc0) == 0xc0) {
if (op_32 & 0x100)
STORE_REG_TARGET_L_RELEASE(host_reg, fetchdat & 7);
else
STORE_REG_TARGET_W_RELEASE(host_reg, fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 1);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
}
static uint32_t
ropMOV_seg_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
switch (fetchdat & 0x38) {
case 0x00: /*ES*/
case 0x18: /*DS*/
case 0x20: /*FS*/
case 0x28: /*GS*/
break;
case 0x10: /*SS*/
default:
return 0;
}
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_W(fetchdat & 7);
else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
host_reg = 0;
}
switch (fetchdat & 0x38) {
case 0x00: /*ES*/
LOAD_SEG(host_reg, &cpu_state.seg_es);
break;
case 0x18: /*DS*/
LOAD_SEG(host_reg, &cpu_state.seg_ds);
break;
case 0x20: /*FS*/
LOAD_SEG(host_reg, &cpu_state.seg_fs);
break;
case 0x28: /*GS*/
LOAD_SEG(host_reg, &cpu_state.seg_gs);
break;
}
return op_pc + 1;
}
#define ropLseg(seg, rseg) \
static uint32_t ropL##seg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) == 0xc0) \
return 0; \
\
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
SAVE_EA(); \
\
if (op_32 & 0x100) { \
MEM_LOAD_ADDR_EA_L(target_seg); \
STORE_HOST_REG_ADDR((uintptr_t) &codegen_temp, 0); \
LOAD_EA(); \
MEM_LOAD_ADDR_EA_W_OFFSET(target_seg, 4); \
} else { \
MEM_LOAD_ADDR_EA_W(target_seg); \
STORE_HOST_REG_ADDR_W((uintptr_t) &codegen_temp, 0); \
LOAD_EA(); \
MEM_LOAD_ADDR_EA_W_OFFSET(target_seg, 2); \
} \
LOAD_SEG(0, &rseg); \
if (op_32 & 0x100) { \
\
int host_reg = LOAD_VAR_L((uintptr_t) &codegen_temp); \
STORE_REG_TARGET_L_RELEASE(host_reg, dest_reg); \
} else { \
int host_reg = LOAD_VAR_W((uintptr_t) &codegen_temp); \
STORE_REG_TARGET_W_RELEASE(host_reg, dest_reg); \
} \
\
if (&rseg == &cpu_state.seg_ss) \
CPU_BLOCK_END(); /*Instruction might change stack size, so end block here*/ \
return op_pc + 1; \
}
// clang-format off
ropLseg(DS, cpu_state.seg_ds)
ropLseg(ES, cpu_state.seg_es)
ropLseg(FS, cpu_state.seg_fs)
ropLseg(GS, cpu_state.seg_gs)
ropLseg(SS, cpu_state.seg_ss)
// clang-format on
``` | /content/code_sandbox/src/codegen/codegen_ops_mov.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,861 |
```c
#include <stdint.h>
#include <stdio.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include "codegen.h"
#include "codegen_accumulate.h"
static struct
{
int count;
uintptr_t dest_reg;
} acc_regs[] = {
[ACCREG_cycles] = {0, (uintptr_t) & (cycles)},
};
void
codegen_accumulate(int acc_reg, int delta)
{
acc_regs[acc_reg].count += delta;
#ifdef USE_ACYCS
if ((acc_reg == ACCREG_cycles) && (delta != 0)) {
if (delta == -1) {
/* -delta = 1 */
addbyte(0xff); /*inc dword ptr[&acycs]*/
addbyte(0x04);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) & (acycs));
} else if (delta == 1) {
/* -delta = -1 */
addbyte(0xff); /*dec dword ptr[&acycs]*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) & (acycs));
} else {
addbyte(0x81); /*ADD $acc_regs[c].count,acc_regs[c].dest*/
addbyte(0x04);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) & (acycs));
addlong(-delta);
}
}
#endif
}
void
codegen_accumulate_flush(void)
{
if (acc_regs[0].count) {
/* To reduce the size of the generated code, we take advantage of
the fact that the target offset points to _cycles within cpu_state,
so we can just use our existing infrastracture for variables
relative to cpu_state. */
addbyte(0x81); /*ADDL $acc_regs[0].count,(_cycles)*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(_cycles));
addlong(acc_regs[0].count);
}
acc_regs[0].count = 0;
}
void
codegen_accumulate_reset(void)
{
acc_regs[0].count = 0;
}
``` | /content/code_sandbox/src/codegen/codegen_accumulate_x86-64.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 505 |
```objective-c
/*Register allocation :
R8-R15 - emulated registers
*/
#include <math.h>
#define HOST_REG_XMM_START 0
#define HOST_REG_XMM_END 7
#define IS_32_ADDR(x) !(((uintptr_t) x) & 0xffffffff00000000)
static __inline int
find_host_xmm_reg(void)
{
int c;
for (c = HOST_REG_XMM_START; c < HOST_REG_XMM_END; c++) {
if (host_reg_xmm_mapping[c] == -1)
break;
}
if (c == HOST_REG_XMM_END)
fatal("Out of host XMM regs!\n");
return c;
}
static __inline void
call(codeblock_t *block, uintptr_t func)
{
intptr_t diff = (intptr_t) (func - (uintptr_t) &block->data[block_pos + 5]);
codegen_reg_loaded[0] = codegen_reg_loaded[1] = codegen_reg_loaded[2] = codegen_reg_loaded[3] = 0;
codegen_reg_loaded[4] = codegen_reg_loaded[5] = codegen_reg_loaded[6] = codegen_reg_loaded[7] = 0;
if (diff >= -0x80000000LL && diff < 0x7fffffffLL) {
addbyte(0xE8); /*CALL*/
addlong((uint32_t) diff);
} else {
addbyte(0x48); /*MOV RAX, func*/
addbyte(0xb8);
addquad(func);
addbyte(0xff); /*CALL RAX*/
addbyte(0xd0);
}
}
static __inline void
call_long(uintptr_t func)
{
codegen_reg_loaded[0] = codegen_reg_loaded[1] = codegen_reg_loaded[2] = codegen_reg_loaded[3] = 0;
codegen_reg_loaded[4] = codegen_reg_loaded[5] = codegen_reg_loaded[6] = codegen_reg_loaded[7] = 0;
addbyte(0x48); /*MOV RAX, func*/
addbyte(0xb8);
addquad(func);
addbyte(0xff); /*CALL RAX*/
addbyte(0xd0);
}
static __inline void
load_param_1_32(codeblock_t *block, uint32_t param)
{
#if _WIN64
addbyte(0xb9); /*MOVL $fetchdat,%ecx*/
#else
addbyte(0xbf); /*MOVL $fetchdat,%edi*/
#endif
addlong(param);
}
static __inline void
load_param_1_reg_32(int reg)
{
#if _WIN64
if (reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOV ECX, EAX*/
addbyte(0xc0 | REG_ECX | (reg << 3));
#else
if (reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOV EDI, EAX*/
addbyte(0xc0 | REG_EDI | (reg << 3));
#endif
}
#if 0
static __inline void load_param_1_64(codeblock_t *block, uint64_t param)
{
addbyte(0x48);
# if _WIN64
addbyte(0xb9); /*MOVL $fetchdat,%ecx*/
# else
addbyte(0xbf); /*MOVL $fetchdat,%edi*/
# endif
addquad(param);
}
#endif
static __inline void
load_param_2_32(codeblock_t *block, uint32_t param)
{
#if _WIN64
addbyte(0xba); /*MOVL $fetchdat,%edx*/
#else
addbyte(0xbe); /*MOVL $fetchdat,%esi*/
#endif
addlong(param);
}
static __inline void
load_param_2_reg_32(int reg)
{
#if _WIN64
if (reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOV EDX, EAX*/
addbyte(0xc0 | REG_EDX | (reg << 3));
#else
if (reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOV ESI, EAX*/
addbyte(0xc0 | REG_ESI | (reg << 3));
#endif
}
static __inline void
load_param_2_64(codeblock_t *block, uint64_t param)
{
addbyte(0x48);
#if _WIN64
addbyte(0xba); /*MOVL $fetchdat,%edx*/
#else
addbyte(0xbe); /*MOVL $fetchdat,%esi*/
#endif
addquad(param);
}
static __inline void
load_param_2_reg_64(int reg)
{
if (reg & 8) {
#if _WIN64
addbyte(0x4c); /*MOVL EDX,reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EDX | ((reg & 7) << 3));
#else
addbyte(0x4c); /*MOVL ESI,reg*/
addbyte(0x89);
addbyte(0xc0 | REG_ESI | ((reg & 7) << 3));
#endif
} else {
#if _WIN64
addbyte(0x48); /*MOVL EDX,reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EDX | ((reg & 7) << 3));
#else
addbyte(0x48); /*MOVL ESI,reg*/
addbyte(0x89);
addbyte(0xc0 | REG_ESI | ((reg & 7) << 3));
#endif
}
}
static __inline void
load_param_3_reg_32(int reg)
{
if (reg & 8) {
#if _WIN64
addbyte(0x45); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));
#else
addbyte(0x44); /*MOV EDX, reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EDX | (reg << 3));
#endif
} else {
#if _WIN64
addbyte(0x41); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));
#else
addbyte(0x90);
addbyte(0x89); /*MOV EDX, reg*/
addbyte(0xc0 | REG_EDX | (reg << 3));
#endif
}
}
static __inline void
load_param_3_reg_64(int reg)
{
if (reg & 8) {
#if _WIN64
addbyte(0x4d); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));
#else
addbyte(0x4c); /*MOVL EDX,reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EDX | ((reg & 7) << 3));
#endif
} else {
#if _WIN64
addbyte(0x49); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));
#else
addbyte(0x48); /*MOVL EDX,reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EDX | ((reg & 7) << 3));
#endif
}
}
static __inline void
CALL_FUNC(uintptr_t func)
{
codegen_reg_loaded[0] = codegen_reg_loaded[1] = codegen_reg_loaded[2] = codegen_reg_loaded[3] = 0;
codegen_reg_loaded[4] = codegen_reg_loaded[5] = codegen_reg_loaded[6] = codegen_reg_loaded[7] = 0;
addbyte(0x48); /*MOV RAX, func*/
addbyte(0xb8);
addquad(func);
addbyte(0xff); /*CALL RAX*/
addbyte(0xd0);
}
static __inline void
RELEASE_REG(UNUSED(int host_reg))
{
//
}
static __inline int
LOAD_REG_B(int reg)
{
int host_reg = reg & 3;
if (!codegen_reg_loaded[reg & 3]) {
addbyte(0x44); /*MOVZX W[reg],host_reg*/
addbyte(0x8b);
addbyte(0x45 | (host_reg << 3));
addbyte(cpu_state_offset(regs[host_reg & 3].b));
}
codegen_reg_loaded[reg & 3] = 1;
if (reg & 4)
return host_reg | 0x18;
return host_reg | 8;
}
static __inline int
LOAD_REG_W(int reg)
{
int host_reg = reg;
if (!codegen_reg_loaded[reg & 7]) {
addbyte(0x44); /*MOVZX W[reg],host_reg*/
addbyte(0x8b);
addbyte(0x45 | (host_reg << 3));
addbyte(cpu_state_offset(regs[reg & 7].w));
}
codegen_reg_loaded[reg & 7] = 1;
return host_reg | 8;
}
static __inline int
LOAD_REG_L(int reg)
{
int host_reg = reg;
if (!codegen_reg_loaded[reg & 7]) {
addbyte(0x44); /*MOVZX W[reg],host_reg*/
addbyte(0x8b);
addbyte(0x45 | (host_reg << 3));
addbyte(cpu_state_offset(regs[reg & 7].l));
}
codegen_reg_loaded[reg & 7] = 1;
return host_reg | 8;
}
static __inline int
LOAD_REG_IMM(uint32_t imm)
{
int host_reg = REG_EBX;
addbyte(0xb8 | REG_EBX); /*MOVL EBX, imm*/
addlong(imm);
return host_reg;
}
static __inline void
STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
{
int dest_reg = LOAD_REG_L(guest_reg & 3) & 7;
if (guest_reg & 4) {
if (host_reg & 8) {
addbyte(0x66); /*MOV AX, host_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 3) << 3));
} else if (host_reg & 3) {
addbyte(0x66); /*MOV AX, host_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 3) << 3));
}
if (host_reg & 0x10) {
addbyte(0x66); /*AND AX, 0xff00*/
addbyte(0x25);
addword(0xff00);
} else {
addbyte(0x66); /*SHL AX, 8*/
addbyte(0xc1);
addbyte(0xe0);
addbyte(0x08);
}
addbyte(0x66); /*AND dest_reg, 0x00ff*/
addbyte(0x41);
addbyte(0x81);
addbyte(0xe0 | dest_reg);
addword(0x00ff);
addbyte(0x66); /*OR dest_reg, AX*/
addbyte(0x41);
addbyte(0x09);
addbyte(0xc0 | dest_reg);
addbyte(0x66); /*MOVW regs[guest_reg].w, dest_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | (dest_reg << 3));
addbyte(cpu_state_offset(regs[guest_reg & 3].w));
} else {
if (host_reg & 8) {
if (host_reg & 0x10) {
addbyte(0x66); /*MOV AX, host_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 3) << 3));
addbyte(0x88); /*MOV AL, AH*/
addbyte(0xe0);
addbyte(0x41); /*MOV dest_reg, AL*/
addbyte(0x88);
addbyte(0xc0 | (dest_reg & 7));
addbyte(0x88); /*MOVB regs[reg].b, AH*/
addbyte(0x65);
addbyte(cpu_state_offset(regs[guest_reg & 3].b));
} else {
addbyte(0x45); /*MOVB dest_reg, host_reg*/
addbyte(0x88);
addbyte(0xc0 | (dest_reg & 7) | ((host_reg & 7) << 3));
addbyte(0x44); /*MOVB regs[guest_reg].b, host_reg*/
addbyte(0x88);
addbyte(0x45 | ((host_reg & 3) << 3));
addbyte(cpu_state_offset(regs[guest_reg & 3].b));
}
} else {
if (host_reg & 0x10) {
addbyte(0xc1); /*SHR host_reg, 8*/
addbyte(0xe8 | (host_reg & 7));
addbyte(8);
}
addbyte(0x41); /*MOVB dest_reg, host_reg*/
addbyte(0x88);
addbyte(0xc0 | (dest_reg & 7) | ((host_reg & 7) << 3));
addbyte(0x88); /*MOVB regs[guest_reg].b, host_reg*/
addbyte(0x45 | ((host_reg & 3) << 3));
addbyte(cpu_state_offset(regs[guest_reg & 3].b));
}
}
}
static __inline void
STORE_REG_TARGET_W_RELEASE(int host_reg, int guest_reg)
{
int dest_reg = LOAD_REG_L(guest_reg & 7) & 7;
if (host_reg & 8) {
addbyte(0x66); /*MOVW guest_reg, host_reg*/
addbyte(0x45);
addbyte(0x89);
addbyte(0xc0 | dest_reg | ((host_reg & 7) << 3));
addbyte(0x66); /*MOVW regs[guest_reg].w, host_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte(cpu_state_offset(regs[guest_reg & 7].w));
} else {
addbyte(0x66); /*MOVW guest_reg, host_reg*/
addbyte(0x41);
addbyte(0x89);
addbyte(0xc0 | dest_reg | (host_reg << 3));
addbyte(0x66); /*MOVW regs[guest_reg].w, host_reg*/
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte(cpu_state_offset(regs[guest_reg & 7].w));
}
}
static __inline void
STORE_REG_TARGET_L_RELEASE(int host_reg, int guest_reg)
{
if (host_reg & 8) {
addbyte(0x45); /*MOVL guest_reg, host_reg*/
addbyte(0x89);
addbyte(0xc0 | guest_reg | (host_reg << 3));
addbyte(0x44); /*MOVL regs[guest_reg].l, host_reg*/
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte(cpu_state_offset(regs[guest_reg & 7].l));
} else {
addbyte(0x41); /*MOVL guest_reg, host_reg*/
addbyte(0x89);
addbyte(0xc0 | guest_reg | (host_reg << 3));
addbyte(0x89); /*MOVL regs[guest_reg].l, host_reg*/
addbyte(0x45 | (host_reg << 3));
addbyte(cpu_state_offset(regs[guest_reg & 7].l));
}
}
static __inline void
STORE_REG_B_RELEASE(int host_reg)
{
if (host_reg & 0x10) {
addbyte(0x66); /*MOVW [reg],host_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte(cpu_state_offset(regs[host_reg & 7].w));
} else {
addbyte(0x44); /*MOVB [reg],host_reg*/
addbyte(0x88);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte(cpu_state_offset(regs[host_reg & 7].b));
}
}
static __inline void
STORE_REG_W_RELEASE(int host_reg)
{
addbyte(0x66); /*MOVW [reg],host_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte(cpu_state_offset(regs[host_reg & 7].w));
}
static __inline void
STORE_REG_L_RELEASE(int host_reg)
{
addbyte(0x44); /*MOVL [reg],host_reg*/
addbyte(0x89);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte(cpu_state_offset(regs[host_reg & 7].l));
}
static __inline void
STORE_IMM_REG_B(int reg, uint8_t val)
{
if (reg & 4) {
int host_reg = LOAD_REG_W(reg & 3) & 7;
addbyte(0x66); /*AND host_reg, 0x00ff*/
addbyte(0x41);
addbyte(0x81);
addbyte(0xe0 | host_reg);
addword(0x00ff);
addbyte(0x66); /*OR host_reg, val << 8*/
addbyte(0x41);
addbyte(0x81);
addbyte(0xc8 | host_reg);
addword(val << 8);
addbyte(0x66); /*MOVW host_reg, regs[host_reg].w*/
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte(cpu_state_offset(regs[reg & 3].w));
} else {
addbyte(0x41); /*MOVB reg, imm*/
addbyte(0xb0 | reg);
addbyte(val);
addbyte(0x44); /*MOVB reg, regs[reg].b*/
addbyte(0x88);
addbyte(0x45 | (reg << 3));
addbyte(cpu_state_offset(regs[reg & 7].b));
}
}
static __inline void
STORE_IMM_REG_W(int reg, uint16_t val)
{
addbyte(0x66); /*MOVW reg, imm*/
addbyte(0x41);
addbyte(0xb8 | reg);
addword(val);
addbyte(0x66); /*MOVW reg, regs[reg].w*/
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | (reg << 3));
addbyte(cpu_state_offset(regs[reg & 7].w));
}
static __inline void
STORE_IMM_REG_L(int reg, uint32_t val)
{
addbyte(0x41); /*MOVL reg, imm*/
addbyte(0xb8 | reg);
addlong(val);
addbyte(0x44); /*MOVL reg, regs[reg].l*/
addbyte(0x89);
addbyte(0x45 | (reg << 3));
addbyte(cpu_state_offset(regs[reg & 7].l));
}
static __inline void
STORE_IMM_ADDR_L(uintptr_t addr, uint32_t val)
{
if (addr >= (uintptr_t) &cpu_state && addr < ((uintptr_t) &cpu_state) + 0x100) {
addbyte(0xC7); /*MOVL [addr],val*/
addbyte(0x45);
addbyte(addr - (uintptr_t) &cpu_state - 128);
addlong(val);
} else if (addr < 0x100000000) {
addbyte(0xC7); /*MOVL [addr],val*/
addbyte(0x04);
addbyte(0x25);
addlong(addr);
addlong(val);
} else {
addbyte(0x48); /*MOV ESI, &addr*/
addbyte(0xb8 | REG_ESI);
addquad(addr);
addbyte(0xc7); /*MOVL [ESI], val*/
addbyte(0x00 | REG_ESI);
addlong(val);
}
}
static x86seg *
FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
{
int mod = (fetchdat >> 6) & 3;
int rm = fetchdat & 7;
if (!mod && rm == 6) {
addbyte(0xb8); /*MOVL EAX, imm*/
addlong((fetchdat >> 8) & 0xffff);
(*op_pc) += 2;
} else {
int base_reg = 0;
int index_reg = 0;
switch (rm) {
case 0:
case 1:
case 7:
base_reg = LOAD_REG_W(REG_BX);
break;
case 2:
case 3:
case 6:
base_reg = LOAD_REG_W(REG_BP);
break;
case 4:
base_reg = LOAD_REG_W(REG_SI);
break;
case 5:
base_reg = LOAD_REG_W(REG_DI);
break;
}
if (!(rm & 4)) {
if (rm & 1)
index_reg = LOAD_REG_W(REG_DI);
else
index_reg = LOAD_REG_W(REG_SI);
}
base_reg &= 7;
index_reg &= 7;
switch (mod) {
case 0:
if (rm & 4) {
addbyte(0x41); /*MOVZX EAX, base_reg*/
addbyte(0x0f);
addbyte(0xb7);
addbyte(0xc0 | base_reg);
} else {
addbyte(0x67); /*LEA EAX, base_reg+index_reg*/
addbyte(0x43);
addbyte(0x8d);
if (base_reg == 5) {
addbyte(0x44);
addbyte(base_reg | (index_reg << 3));
addbyte(0);
} else {
addbyte(0x04);
addbyte(base_reg | (index_reg << 3));
}
}
break;
case 1:
if (rm & 4) {
addbyte(0x67); /*LEA EAX, base_reg+imm8*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x40 | base_reg);
addbyte((fetchdat >> 8) & 0xff);
} else {
addbyte(0x67); /*LEA EAX, base_reg+index_reg+imm8*/
addbyte(0x43);
addbyte(0x8d);
addbyte(0x44);
addbyte(base_reg | (index_reg << 3));
addbyte((fetchdat >> 8) & 0xff);
}
(*op_pc)++;
break;
case 2:
if (rm & 4) {
addbyte(0x67); /*LEA EAX, base_reg+imm8*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x80 | base_reg);
addlong((fetchdat >> 8) & 0xffff);
} else {
addbyte(0x67); /*LEA EAX, base_reg+index_reg+imm16*/
addbyte(0x43);
addbyte(0x8d);
addbyte(0x84);
addbyte(base_reg | (index_reg << 3));
addlong((fetchdat >> 8) & 0xffff);
}
(*op_pc) += 2;
break;
}
if (mod || !(rm & 4)) {
addbyte(0x25); /*ANDL $0xffff, %eax*/
addlong(0xffff);
}
if (mod1seg[rm] == &ss && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
}
return op_ea_seg;
}
static x86seg *
FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc, int stack_offset)
{
int mod = (fetchdat >> 6) & 3;
int rm = fetchdat & 7;
uint32_t new_eaaddr;
if (rm == 4) {
uint8_t sib = fetchdat >> 8;
int base_reg = -1;
int index_reg = -1;
(*op_pc)++;
if (mod || (sib & 7) != 5)
base_reg = LOAD_REG_L(sib & 7) & 7;
if (((sib >> 3) & 7) != 4)
index_reg = LOAD_REG_L((sib >> 3) & 7) & 7;
if (index_reg == -1) {
switch (mod) {
case 0:
if ((sib & 7) == 5) {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOV EAX, imm32*/
addlong(new_eaaddr);
(*op_pc) += 4;
} else {
addbyte(0x44); /*MOV EAX, base_reg*/
addbyte(0x89);
addbyte(0xc0 | (base_reg << 3));
}
break;
case 1:
addbyte(0x67); /*LEA EAX, imm8+base_reg*/
addbyte(0x41);
addbyte(0x8d);
if (base_reg == 4) {
addbyte(0x44);
addbyte(0x24);
} else {
addbyte(0x40 | base_reg);
}
addbyte((fetchdat >> 16) & 0xff);
(*op_pc)++;
break;
case 2:
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x67); /*LEA EAX, imm32+base_reg*/
addbyte(0x41);
addbyte(0x8d);
if (base_reg == 4) {
addbyte(0x84);
addbyte(0x24);
} else {
addbyte(0x80 | base_reg);
}
addlong(new_eaaddr);
(*op_pc) += 4;
break;
}
} else {
switch (mod) {
case 0:
if ((sib & 7) == 5) {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
if (sib >> 6) {
addbyte(0x67); /*LEA EAX, imm32+index_reg*scale*/
addbyte(0x42);
addbyte(0x8d);
addbyte(0x04);
addbyte(0x05 | (sib & 0xc0) | (index_reg << 3));
addlong(new_eaaddr);
} else {
addbyte(0x67); /*LEA EAX, imm32+index_reg*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x80 | index_reg);
addlong(new_eaaddr);
}
(*op_pc) += 4;
} else {
addbyte(0x67); /*LEA EAX, base_reg+index_reg*scale*/
addbyte(0x43);
addbyte(0x8d);
if (base_reg == 5) {
addbyte(0x44);
addbyte(base_reg | (index_reg << 3) | (sib & 0xc0));
addbyte(0);
} else {
addbyte(0x04);
addbyte(base_reg | (index_reg << 3) | (sib & 0xc0));
}
}
break;
case 1:
addbyte(0x67); /*LEA EAX, imm8+base_reg+index_reg*scale*/
addbyte(0x43);
addbyte(0x8d);
addbyte(0x44);
addbyte(base_reg | (index_reg << 3) | (sib & 0xc0));
addbyte((fetchdat >> 16) & 0xff);
(*op_pc)++;
break;
case 2:
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x67); /*LEA EAX, imm32+base_reg+index_reg*scale*/
addbyte(0x43);
addbyte(0x8d);
addbyte(0x84);
addbyte(base_reg | (index_reg << 3) | (sib & 0xc0));
addlong(new_eaaddr);
(*op_pc) += 4;
break;
}
}
if (stack_offset && (sib & 7) == 4 && (mod || (sib & 7) != 5)) /*ESP*/
{
addbyte(0x05);
addlong(stack_offset);
}
if (((sib & 7) == 4 || (mod && (sib & 7) == 5)) && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
} else {
int base_reg;
if (!mod && rm == 5) {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOVL EAX, new_eaaddr*/
addlong(new_eaaddr);
(*op_pc) += 4;
return op_ea_seg;
}
base_reg = LOAD_REG_L(rm) & 7;
if (mod) {
if (rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (mod == 1) {
addbyte(0x67); /*LEA EAX, base_reg+imm8*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x40 | base_reg);
addbyte((fetchdat >> 8) & 0xff);
(*op_pc)++;
} else {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x67); /*LEA EAX, base_reg+imm32*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x80 | base_reg);
addlong(new_eaaddr);
(*op_pc) += 4;
}
} else {
addbyte(0x44); /*MOV EAX, base_reg*/
addbyte(0x89);
addbyte(0xc0 | (base_reg << 3));
}
}
return op_ea_seg;
}
static __inline x86seg *
FETCH_EA(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc, uint32_t op_32)
{
if (op_32 & 0x200)
return FETCH_EA_32(op_ea_seg, fetchdat, op_ssegs, op_pc, 0);
return FETCH_EA_16(op_ea_seg, fetchdat, op_ssegs, op_pc);
}
static __inline void
CHECK_SEG_READ(x86seg *seg)
{
/*Segments always valid in real/V86 mode*/
if (!(cr0 & 1) || (cpu_state.eflags & VM_FLAG))
return;
/*CS and SS must always be valid*/
if (seg == &cpu_state.seg_cs || seg == &cpu_state.seg_ss)
return;
if (seg->checked)
return;
if (seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS))
return;
if (IS_32_ADDR(&seg->base)) {
addbyte(0x83); /*CMP seg->base, -1*/
addbyte(0x3c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
addbyte(-1);
} else {
addbyte(0x48); /*MOV RSI, &addr*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x83); /*CMP RSI, -1*/
addbyte(0xe8 | REG_ESI);
addbyte(0xff);
}
addbyte(0x0f); /*JE GPF_BLOCK_OFFSET*/
addbyte(0x84);
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
seg->checked = 1;
}
static __inline void
CHECK_SEG_WRITE(x86seg *seg)
{
/*Segments always valid in real/V86 mode*/
if (!(cr0 & 1) || (cpu_state.eflags & VM_FLAG))
return;
/*CS and SS must always be valid*/
if (seg == &cpu_state.seg_cs || seg == &cpu_state.seg_ss)
return;
if (seg->checked)
return;
if (seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS))
return;
if (IS_32_ADDR(&seg->base)) {
addbyte(0x83); /*CMP seg->base, -1*/
addbyte(0x3c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
addbyte(-1);
} else {
addbyte(0x48); /*MOV RSI, &addr*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x83); /*CMP RSI, -1*/
addbyte(0xe8 | REG_ESI);
addbyte(0xff);
}
addbyte(0x0f); /*JE GPF_BLOCK_OFFSET*/
addbyte(0x84);
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
seg->checked = 1;
}
static __inline void
CHECK_SEG_LIMITS(x86seg *seg, int end_offset)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
return;
if (IS_32_ADDR(&seg->base)) {
addbyte(0xb8 | REG_ESI); /*MOV ESI, &addr*/
addlong((uint32_t) (uintptr_t) seg);
} else {
addbyte(0x48); /*MOV RSI, &addr*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) seg);
}
addbyte(0x3b); /*CMP EAX, seg->limit_low*/
addbyte(0x46);
addbyte((uintptr_t) &seg->limit_low - (uintptr_t) seg);
addbyte(0x0f); /*JB BLOCK_GPF_OFFSET*/
addbyte(0x82);
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
if (end_offset) {
addbyte(0x83); /*ADD EAX, end_offset*/
addbyte(0xc0);
addbyte(end_offset);
addbyte(0x3b); /*CMP EAX, seg->limit_high*/
addbyte(0x46);
addbyte((uintptr_t) &seg->limit_high - (uintptr_t) seg);
addbyte(0x0f); /*JNBE BLOCK_GPF_OFFSET*/
addbyte(0x87);
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
addbyte(0x83); /*SUB EAX, end_offset*/
addbyte(0xe8);
addbyte(end_offset);
}
}
static __inline void
MEM_LOAD_ADDR_EA_B(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ECX, ECX*/
addbyte(0xc9);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL ECX, seg->base*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ECX, [RSI]*/
addbyte(0x0e);
}
addbyte(0x67); /*LEA ESI, (EAX,ECX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x08);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
if (IS_32_ADDR(readlookup2)) {
addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) readlookup2);
} else {
addbyte(0x48); /*MOV RDX, readlookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) readlookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 2);
addbyte(0x8b); /*MOV AL,[RDI+RSI]*/
addbyte(0x04);
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xeb); /*JMP done*/
addbyte(2 + 2 + 12 + 4 + 6);
/*slowpath:*/
addbyte(0x01); /*ADD ECX,EAX*/
addbyte(0xc1);
load_param_1_reg_32(REG_ECX);
call_long((uintptr_t) readmembl);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE end*/
addbyte(0x85);
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
/*done:*/
}
static __inline void
MEM_LOAD_ADDR_EA_W(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ECX, ECX*/
addbyte(0xc9);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL ECX, seg->base*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ECX, [RSI]*/
addbyte(0x0e);
}
addbyte(0x67); /*LEA ESI, (EAX,ECX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x08);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 1*/
addbyte(0xc7);
addlong(1);
if (IS_32_ADDR(readlookup2)) {
addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) readlookup2);
} else {
addbyte(0x48); /*MOV RDX, readlookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) readlookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 4 + 2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4 + 2);
addbyte(0x66); /*MOV AX,[RDI+RSI]*/
addbyte(0x8b);
addbyte(0x04);
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xeb); /*JMP done*/
addbyte(2 + 2 + 12 + 4 + 6);
/*slowpath:*/
addbyte(0x01); /*ADD ECX,EAX*/
addbyte(0xc1);
load_param_1_reg_32(REG_ECX);
call_long((uintptr_t) readmemwl);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE end*/
addbyte(0x85);
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
/*done:*/
}
static __inline void
MEM_LOAD_ADDR_EA_W_OFFSET(x86seg *seg, int offset)
{
addbyte(0x83); /*ADD EAX, offset*/
addbyte(0xc0);
addbyte(offset);
MEM_LOAD_ADDR_EA_W(seg);
}
static __inline void
MEM_LOAD_ADDR_EA_L(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ECX, ECX*/
addbyte(0xc9);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL ECX, seg->base*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ECX, [RSI]*/
addbyte(0x0e);
}
addbyte(0x67); /*LEA ESI, (EAX,ECX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x08);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 3*/
addbyte(0xc7);
addlong(3);
if (IS_32_ADDR(readlookup2)) {
addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) readlookup2);
} else {
addbyte(0x48); /*MOV RDX, readlookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) readlookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 3 + 2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 2);
addbyte(0x8b); /*MOV EAX,[RDI+RSI]*/
addbyte(0x04);
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xeb); /*JMP done*/
addbyte(2 + 2 + 12 + 4 + 6);
/*slowpath:*/
addbyte(0x01); /*ADD ECX,EAX*/
addbyte(0xc1);
load_param_1_reg_32(REG_ECX);
call_long((uintptr_t) readmemll);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE end*/
addbyte(0x85);
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
/*done:*/
}
static __inline void
MEM_LOAD_ADDR_EA_Q(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ECX, ECX*/
addbyte(0xc9);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL ECX, seg->base*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ECX, [RSI]*/
addbyte(0x0e);
}
addbyte(0x67); /*LEA ESI, (EAX,ECX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x08);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 7*/
addbyte(0xc7);
addlong(7);
if (IS_32_ADDR(readlookup2)) {
addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) readlookup2);
} else {
addbyte(0x48); /*MOV RDX, readlookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) readlookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 4 + 2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4 + 2);
addbyte(0x48); /*MOV RAX,[RDI+RSI]*/
addbyte(0x8b);
addbyte(0x04);
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xeb); /*JMP done*/
addbyte(2 + 2 + 12 + 4 + 6);
/*slowpath:*/
addbyte(0x01); /*ADD ECX,EAX*/
addbyte(0xc1);
load_param_1_reg_32(REG_ECX);
call_long((uintptr_t) readmemql);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE end*/
addbyte(0x85);
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
/*done:*/
}
static __inline void
MEM_LOAD_ADDR_IMM_B(x86seg *seg, uint32_t addr)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_LOAD_ADDR_EA_B(seg);
}
static __inline void
MEM_LOAD_ADDR_IMM_W(x86seg *seg, uint32_t addr)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_LOAD_ADDR_EA_W(seg);
}
static __inline void
MEM_LOAD_ADDR_IMM_L(x86seg *seg, uint32_t addr)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_LOAD_ADDR_EA_L(seg);
}
static __inline void
MEM_STORE_ADDR_EA_B(x86seg *seg, int host_reg)
{
if (host_reg & 0x10) {
/*Handle high byte of register*/
if (host_reg & 8) {
addbyte(0x45); /*MOVL R8, host_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3));
} else {
addbyte(0x41); /*MOVL R8, host_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3));
}
addbyte(0x66); /*SHR R8, 8*/
addbyte(0x41);
addbyte(0xc1);
addbyte(0xe8);
addbyte(8);
host_reg = 8;
}
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ECX, ECX*/
addbyte(0xc9);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL ECX, seg->base*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ECX, [RSI]*/
addbyte(0x0e);
}
addbyte(0x67); /*LEA ESI, (EAX,ECX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x08);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
if (IS_32_ADDR(writelookup2)) {
addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) writelookup2);
} else {
addbyte(0x48); /*MOV RDX, writelookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) writelookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(((host_reg & 8) ? 4 : 3) + 2);
if (host_reg & 8) {
addbyte(0x44); /*MOV [RDI+RSI],host_reg*/
addbyte(0x88);
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(REG_EDI | (REG_ESI << 3));
} else {
addbyte(0x88); /*MOV [RDI+RSI],host_reg*/
addbyte(0x04 | (host_reg << 3));
addbyte(REG_EDI | (REG_ESI << 3));
}
addbyte(0xeb); /*JMP done*/
if (host_reg & 8) {
addbyte(2 + 2 + 3 + 12 + 4 + 6);
} else {
addbyte(2 + 2 + 2 + 12 + 4 + 6);
}
/*slowpath:*/
addbyte(0x01); /*ADD ECX,EAX*/
addbyte(0xc1);
load_param_1_reg_32(REG_ECX);
load_param_2_reg_32(host_reg);
call_long((uintptr_t) writemembl);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE end*/
addbyte(0x85);
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
/*done:*/
}
static __inline void
MEM_STORE_ADDR_EA_W(x86seg *seg, int host_reg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ECX, ECX*/
addbyte(0xc9);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL ECX, seg->base*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ECX, [RSI]*/
addbyte(0x0e);
}
addbyte(0x67); /*LEA ESI, (EAX,ECX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x08);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 1*/
addbyte(0xc7);
addlong(1);
if (IS_32_ADDR(writelookup2)) {
addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) writelookup2);
} else {
addbyte(0x48); /*MOV RDX, writelookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) writelookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + ((host_reg & 8) ? 5 : 4) + 2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(((host_reg & 8) ? 5 : 4) + 2);
if (host_reg & 8) {
addbyte(0x66); /*MOV [RDI+RSI],host_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(REG_EDI | (REG_ESI << 3));
} else {
addbyte(0x66); /*MOV [RDI+RSI],host_reg*/
addbyte(0x89);
addbyte(0x04 | (host_reg << 3));
addbyte(REG_EDI | (REG_ESI << 3));
}
addbyte(0xeb); /*JMP done*/
if (host_reg & 8) {
addbyte(2 + 2 + 3 + 12 + 4 + 6);
} else {
addbyte(2 + 2 + 2 + 12 + 4 + 6);
}
/*slowpath:*/
addbyte(0x01); /*ADD ECX,EAX*/
addbyte(0xc1);
load_param_1_reg_32(REG_ECX);
load_param_2_reg_32(host_reg);
call_long((uintptr_t) writememwl);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE end*/
addbyte(0x85);
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
/*done:*/
}
static __inline void
MEM_STORE_ADDR_EA_L(x86seg *seg, int host_reg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ECX, ECX*/
addbyte(0xc9);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL ECX, seg->base*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ECX, [RSI]*/
addbyte(0x0e);
}
addbyte(0x67); /*LEA ESI, (EAX,ECX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x08);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 3*/
addbyte(0xc7);
addlong(3);
if (IS_32_ADDR(writelookup2)) {
addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) writelookup2);
} else {
addbyte(0x48); /*MOV RDX, writelookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) writelookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + ((host_reg & 8) ? 4 : 3) + 2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(((host_reg & 8) ? 4 : 3) + 2);
if (host_reg & 8) {
addbyte(0x44); /*MOV -3[RDI+RSI],host_reg*/
addbyte(0x89);
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(REG_EDI | (REG_ESI << 3));
} else {
addbyte(0x89); /*MOV -3[RDI+RSI],host_reg*/
addbyte(0x04 | (host_reg << 3));
addbyte(REG_EDI | (REG_ESI << 3));
}
addbyte(0xeb); /*JMP done*/
if (host_reg & 8) {
addbyte(2 + 2 + 3 + 12 + 4 + 6);
} else {
addbyte(2 + 2 + 2 + 12 + 4 + 6);
}
/*slowpath:*/
addbyte(0x01); /*ADD ECX,EAX*/
addbyte(0xc1);
load_param_1_reg_32(REG_ECX);
load_param_2_reg_32(host_reg);
call_long((uintptr_t) writememll);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE end*/
addbyte(0x85);
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
/*done:*/
}
static __inline void
MEM_STORE_ADDR_EA_Q(x86seg *seg, int host_reg, int host_reg2)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ECX, ECX*/
addbyte(0xc9);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL ECX, seg->base*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ECX, [RSI]*/
addbyte(0x0e);
}
addbyte(0x67); /*LEA ESI, (EAX,ECX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x08);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 7*/
addbyte(0xc7);
addlong(7);
if (IS_32_ADDR(writelookup2)) {
addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) writelookup2);
} else {
addbyte(0x48); /*MOV RDX, writelookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) writelookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 4 + 2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4 + 2);
if (host_reg & 8) {
addbyte(0x4c); /*MOV [RDI+RSI],host_reg*/
addbyte(0x89);
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(REG_EDI | (REG_ESI << 3));
} else {
addbyte(0x48); /*MOV [RDI+RSI],host_reg*/
addbyte(0x89);
addbyte(0x04 | (host_reg << 3));
addbyte(REG_EDI | (REG_ESI << 3));
}
addbyte(0xeb); /*JMP done*/
addbyte(2 + 2 + 3 + 12 + 4 + 6);
/*slowpath:*/
addbyte(0x01); /*ADD ECX,EAX*/
addbyte(0xc1);
load_param_1_reg_32(REG_ECX);
load_param_2_reg_64(host_reg);
call_long((uintptr_t) writememql);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE end*/
addbyte(0x85);
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
/*done:*/
}
static __inline void
MEM_STORE_ADDR_IMM_B(x86seg *seg, uint32_t addr, int host_reg)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_STORE_ADDR_EA_B(seg, host_reg);
}
static __inline void
MEM_STORE_ADDR_IMM_W(x86seg *seg, uint32_t addr, int host_reg)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_STORE_ADDR_EA_W(seg, host_reg);
}
static __inline void
MEM_STORE_ADDR_IMM_L(x86seg *seg, uint32_t addr, int host_reg)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_STORE_ADDR_EA_L(seg, host_reg);
}
static __inline void
STORE_HOST_REG_ADDR_BL(uintptr_t addr, int host_reg)
{
int temp_reg = REG_ECX;
if (host_reg_mapping[REG_ECX] != -1)
temp_reg = REG_EBX;
if (host_reg & 0x10) {
if (host_reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVZX temp_reg, host_reg*/
addbyte(0xb7);
addbyte(0xc0 | (temp_reg << 3) | (host_reg & 7));
addbyte(0xc1); /*SHR temp_reg, 8*/
addbyte(0xe8 | temp_reg);
addbyte(8);
} else {
if (host_reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVZX temp_reg, host_reg*/
addbyte(0xb6);
addbyte(0xc0 | (temp_reg << 3) | (host_reg & 7));
}
if (addr >= (uintptr_t) &cpu_state && addr < ((uintptr_t) &cpu_state) + 0x100) {
addbyte(0x89); /*MOV addr, temp_reg*/
addbyte(0x45 | (temp_reg << 3));
addbyte((uint32_t) addr - (uint32_t) (uintptr_t) &cpu_state - 128);
} else if (IS_32_ADDR(addr)) {
addbyte(0x89); /*MOV addr, temp_reg*/
addbyte(0x04 | (temp_reg << 3));
addbyte(0x25);
addlong(addr);
} else {
addbyte(0x48); /*MOV RSI, addr*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) addr);
addbyte(0x89); /*MOV [RSI], temp_reg*/
addbyte(0x06 | (temp_reg << 3));
}
}
static __inline void
STORE_HOST_REG_ADDR_WL(uintptr_t addr, int host_reg)
{
int temp_reg = REG_ECX;
if (host_reg_mapping[REG_ECX] != -1)
temp_reg = REG_EBX;
if (host_reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVZX temp_reg, host_reg*/
addbyte(0xb7);
addbyte(0xc0 | (temp_reg << 3) | (host_reg & 7));
if (addr >= (uintptr_t) &cpu_state && addr < ((uintptr_t) &cpu_state) + 0x100) {
addbyte(0x89); /*MOV addr, temp_reg*/
addbyte(0x45 | (temp_reg << 3));
addbyte((uint32_t) addr - (uint32_t) (uintptr_t) &cpu_state - 128);
} else if (IS_32_ADDR(addr)) {
addbyte(0x89); /*MOV addr, temp_reg*/
addbyte(0x04 | (temp_reg << 3));
addbyte(0x25);
addlong(addr);
} else {
addbyte(0x48); /*MOV RSI, addr*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) addr);
addbyte(0x89); /*MOV [RSI], temp_reg*/
addbyte(0x06 | (temp_reg << 3));
}
}
static __inline void
STORE_HOST_REG_ADDR_W(uintptr_t addr, int host_reg)
{
if (addr >= (uintptr_t) &cpu_state && addr < ((uintptr_t) &cpu_state) + 0x100) {
addbyte(0x66); /*MOVW [addr],host_reg*/
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte((uint32_t) addr - (uint32_t) (uintptr_t) &cpu_state - 128);
} else if (IS_32_ADDR(addr)) {
addbyte(0x66);
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOVW addr,host_reg*/
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(0x25);
addlong(addr);
} else {
addbyte(0x48); /*MOV RSI, addr*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) addr);
addbyte(0x66);
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOVW [RSI],host_reg*/
addbyte(0x06 | ((host_reg & 7) << 3));
}
}
static __inline void
STORE_HOST_REG_ADDR(uintptr_t addr, int host_reg)
{
if (addr >= (uintptr_t) &cpu_state && addr < ((uintptr_t) &cpu_state) + 0x100) {
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOVL [addr],host_reg*/
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte((uint32_t) addr - (uint32_t) (uintptr_t) &cpu_state - 128);
} else if (IS_32_ADDR(addr)) {
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOVL addr,host_reg*/
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(0x25);
addlong(addr);
} else {
addbyte(0x48); /*MOV RSI, addr*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) addr);
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOVL [RSI],host_reg*/
addbyte(0x06 | ((host_reg & 7) << 3));
}
}
static __inline void
AND_HOST_REG_B(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0x66); /*MOVW AX, src_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((src_reg & 7) << 3));
if (!(src_reg & 0x10)) {
addbyte(0x66); /*SHL AX, 8*/
addbyte(0xc1);
addbyte(0xe0);
addbyte(8);
}
addbyte(0x66); /*OR AX, 0x00ff*/
addbyte(0x0d);
addword(0xff);
addbyte(0x66); /*ANDW dst_reg, AX*/
addbyte(0x41);
addbyte(0x21);
addbyte(0xc0 | (dst_reg & 7));
} else if (src_reg & 0x10) {
addbyte(0x66); /*MOVW AX, src_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((src_reg & 7) << 3));
addbyte(0x66); /*SHR AX, 8*/
addbyte(0xc1);
addbyte(0xe8);
addbyte(8);
addbyte(0x41); /*ANDB dst_reg, AL*/
addbyte(0x20);
addbyte(0xc0 | (dst_reg & 7));
} else {
addbyte(0x45); /*ANDB dst_reg, src_reg*/
addbyte(0x20);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else if (dst_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0x66); /*SHL src_reg, 8*/
addbyte(0xc1);
addbyte(0xe0 | src_reg);
addbyte(0x08);
addbyte(0x66); /*OR src_reg, 0xff*/
addbyte(0x81);
addbyte(0xc8 | src_reg);
addword(0xff);
addbyte(0x66); /*ANDW dst_reg, src_reg*/
addbyte(0x41);
addbyte(0x21);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x41); /*ANDB dst_reg, src_reg*/
addbyte(0x20);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else if (src_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0xc1); /*SHR dst_reg, 8*/
addbyte(0xe8 | (dst_reg & 7));
addbyte(8);
}
if (src_reg & 0x10) {
addbyte(0x41); /*MOVZX EBX, src_reg*/
addbyte(0x0f);
addbyte(0xb7);
addbyte(0xd8 | (src_reg & 7));
addbyte(0xc1); /*SHR EBX, 8*/
addbyte(0xeb);
addbyte(8);
addbyte(0x20); /*ANDB dst_reg, EBX*/
addbyte(0xd8 | (dst_reg & 7));
} else {
addbyte(0x44); /*ANDB dst_reg, src_reg*/
addbyte(0x20);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else {
if (dst_reg & 0x10) {
addbyte(0xc1); /*SHR dst_reg, 8*/
addbyte(0xe8 | (dst_reg & 7));
addbyte(8);
}
if (src_reg & 0x10) {
addbyte(0x0f); /*MOVZX EBX, src_reg*/
addbyte(0xb7);
addbyte(0xd8 | (src_reg & 7));
addbyte(0xc1); /*SHR EBX, 8*/
addbyte(0xeb);
addbyte(8);
addbyte(0x20); /*ANDB dst_reg, EBX*/
addbyte(0xd8 | (dst_reg & 7));
} else {
addbyte(0x20); /*ANDB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
static __inline void
AND_HOST_REG_W(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
addbyte(0x66); /*ANDW dst_reg, src_reg*/
addbyte(0x45);
addbyte(0x21);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (dst_reg & 8) {
addbyte(0x66); /*ANDW dst_reg, src_reg*/
addbyte(0x41);
addbyte(0x21);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (src_reg & 8) {
addbyte(0x66); /*ANDW dst_reg, src_reg*/
addbyte(0x44);
addbyte(0x21);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x66); /*ANDW dst_reg, src_reg*/
addbyte(0x21);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
static __inline void
AND_HOST_REG_L(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
addbyte(0x45); /*ANDL dst_reg, src_reg*/
addbyte(0x21);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (dst_reg & 8) {
addbyte(0x41); /*ANDL dst_reg, src_reg*/
addbyte(0x21);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (src_reg & 8) {
addbyte(0x44); /*ANDL dst_reg, src_reg*/
addbyte(0x21);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x21); /*ANDL dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
static __inline void
AND_HOST_REG_IMM(int host_reg, uint32_t imm)
{
if (host_reg & 0x10) {
addbyte(0x66); /*ANDW host_reg, imm<<8*/
if (host_reg & 8)
addbyte(0x41);
addbyte(0x81);
addbyte(0xe0 | (host_reg & 7));
addword((imm << 8) | 0xff);
} else {
if (host_reg & 8)
addbyte(0x41);
addbyte(0x81); /*ANDL host_reg, imm*/
addbyte(0xe0 | (host_reg & 7));
addlong(imm);
}
}
static __inline int
TEST_HOST_REG_B(int dst_reg, int src_reg)
{
if (dst_reg & 8) {
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = (dst_reg & 0x10) | REG_EDX;
}
AND_HOST_REG_B(dst_reg, src_reg);
return dst_reg & ~0x10;
}
static __inline int
TEST_HOST_REG_W(int dst_reg, int src_reg)
{
if (dst_reg & 8) {
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
AND_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static __inline int
TEST_HOST_REG_L(int dst_reg, int src_reg)
{
if (dst_reg & 8) {
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
AND_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
static __inline int
TEST_HOST_REG_IMM(int host_reg, uint32_t imm)
{
if (host_reg & 8) {
addbyte(0x44); /*MOV EDX, host_reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EDX | ((host_reg & 7) << 3));
host_reg = REG_EDX | (host_reg & 0x10);
}
if (host_reg & 0x10) {
addbyte(0x66); /*ANDW host_reg, imm<<8*/
addbyte(0x81);
addbyte(0xe0 | (host_reg & 7));
addword((imm << 8) | 0xff);
} else {
addbyte(0x81); /*ANDL host_reg, imm*/
addbyte(0xe0 | (host_reg & 7));
addlong(imm);
}
return host_reg;
}
static __inline void
OR_HOST_REG_B(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0x66); /*MOVW AX, src_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((src_reg & 7) << 3));
if (!(src_reg & 0x10)) {
addbyte(0x66); /*SHL AX, 8*/
addbyte(0xc1);
addbyte(0xe0);
addbyte(8);
} else {
addbyte(0x66); /*AND AX, 0xff00*/
addbyte(0x25);
addword(0xff00);
}
addbyte(0x66); /*ORW dst_reg, AX*/
addbyte(0x41);
addbyte(0x09);
addbyte(0xc0 | (dst_reg & 7));
} else if (src_reg & 0x10) {
addbyte(0x66); /*MOVW AX, src_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((src_reg & 7) << 3));
addbyte(0x66); /*SHR AX, 8*/
addbyte(0xc1);
addbyte(0xe8);
addbyte(8);
addbyte(0x41); /*ORB dst_reg, AL*/
addbyte(0x08);
addbyte(0xc0 | (dst_reg & 7));
} else {
addbyte(0x45); /*ORB dst_reg, src_reg*/
addbyte(0x08);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else if (dst_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0x66); /*SHL src_reg, 8*/
addbyte(0xc1);
addbyte(0xe0 | src_reg);
addbyte(0x08);
addbyte(0x66); /*ORW dst_reg, src_reg*/
addbyte(0x41);
addbyte(0x09);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x41); /*ORB dst_reg, src_reg*/
addbyte(0x08);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else if (src_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0xc1); /*SHR dst_reg, 8*/
addbyte(0xe8 | (dst_reg & 7));
addbyte(8);
}
if (src_reg & 0x10) {
addbyte(0x41); /*MOVZX EBX, src_reg*/
addbyte(0x0f);
addbyte(0xb7);
addbyte(0xd8 | (src_reg & 7));
addbyte(0xc1); /*SHR EBX, 8*/
addbyte(0xeb);
addbyte(8);
addbyte(0x08); /*ORB dst_reg, EBX*/
addbyte(0xd8 | (dst_reg & 7));
} else {
addbyte(0x44); /*ORB dst_reg, src_reg*/
addbyte(0x08);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else {
if (dst_reg & 0x10) {
addbyte(0xc1); /*SHR dst_reg, 8*/
addbyte(0xe8 | (dst_reg & 7));
addbyte(8);
}
if (src_reg & 0x10) {
addbyte(0x0f); /*MOVZX EBX, src_reg*/
addbyte(0xb7);
addbyte(0xd8 | (src_reg & 7));
addbyte(0xc1); /*SHR EBX, 8*/
addbyte(0xeb);
addbyte(8);
addbyte(0x08); /*ORB dst_reg, EBX*/
addbyte(0xd8 | (dst_reg & 7));
} else {
addbyte(0x08); /*ORB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
static __inline void
OR_HOST_REG_W(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
addbyte(0x66); /*ORW dst_reg, src_reg*/
addbyte(0x45);
addbyte(0x09);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (dst_reg & 8) {
addbyte(0x66); /*ORW dst_reg, src_reg*/
addbyte(0x41);
addbyte(0x09);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (src_reg & 8) {
addbyte(0x66); /*ORW dst_reg, src_reg*/
addbyte(0x44);
addbyte(0x09);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x66); /*ORW dst_reg, src_reg*/
addbyte(0x09);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
static __inline void
OR_HOST_REG_L(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
addbyte(0x45); /*ORL dst_reg, src_reg*/
addbyte(0x09);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (dst_reg & 8) {
addbyte(0x41); /*ORL dst_reg, src_reg*/
addbyte(0x09);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (src_reg & 8) {
addbyte(0x44); /*ORL dst_reg, src_reg*/
addbyte(0x09);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x09); /*ORW dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
static __inline void
OR_HOST_REG_IMM(int host_reg, uint32_t imm)
{
if (host_reg & 0x10) {
addbyte(0x66); /*ORW host_reg, imm<<8*/
addbyte(0x41);
addbyte(0x81);
addbyte(0xc8 | (host_reg & 7));
addword(imm << 8);
} else if (host_reg & 8) {
addbyte(0x41); /*ORL host_reg, imm*/
addbyte(0x81);
addbyte(0xc8 | (host_reg & 7));
addlong(imm);
} else {
addbyte(0x81); /*ORL host_reg, imm*/
addbyte(0xc8 | (host_reg & 7));
addlong(imm);
}
}
static __inline void
XOR_HOST_REG_B(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0x66); /*MOVW AX, src_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((src_reg & 7) << 3));
if (!(src_reg & 0x10)) {
addbyte(0x66); /*SHL AX, 8*/
addbyte(0xc1);
addbyte(0xe0);
addbyte(8);
} else {
addbyte(0x66); /*AND AX, 0xff00*/
addbyte(0x25);
addword(0xff00);
}
addbyte(0x66); /*XORW dst_reg, AX*/
addbyte(0x41);
addbyte(0x31);
addbyte(0xc0 | (dst_reg & 7));
} else if (src_reg & 0x10) {
addbyte(0x66); /*MOVW AX, src_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((src_reg & 7) << 3));
addbyte(0x66); /*SHR AX, 8*/
addbyte(0xc1);
addbyte(0xe8);
addbyte(8);
addbyte(0x41); /*XORB dst_reg, AL*/
addbyte(0x30);
addbyte(0xc0 | (dst_reg & 7));
} else {
addbyte(0x45); /*XORB dst_reg, src_reg*/
addbyte(0x30);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else if (dst_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0x66); /*SHL src_reg, 8*/
addbyte(0xc1);
addbyte(0xe0 | src_reg);
addbyte(0x08);
addbyte(0x66); /*XORW dst_reg, src_reg*/
addbyte(0x41);
addbyte(0x31);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x41); /*XORB dst_reg, src_reg*/
addbyte(0x30);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else if (src_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0xc1); /*SHR dst_reg, 8*/
addbyte(0xe8 | (dst_reg & 7));
addbyte(8);
}
if (src_reg & 0x10) {
addbyte(0x41); /*MOVZX EBX, src_reg*/
addbyte(0x0f);
addbyte(0xb7);
addbyte(0xd8 | (src_reg & 7));
addbyte(0xc1); /*SHR EBX, 8*/
addbyte(0xeb);
addbyte(8);
addbyte(0x30); /*XORB dst_reg, EBX*/
addbyte(0xd8 | (dst_reg & 7));
} else {
addbyte(0x44); /*XORB dst_reg, src_reg*/
addbyte(0x30);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else {
if (dst_reg & 0x10) {
addbyte(0xc1); /*SHR dst_reg, 8*/
addbyte(0xe8 | (dst_reg & 7));
addbyte(8);
}
if (src_reg & 0x10) {
addbyte(0x0f); /*MOVZX EBX, src_reg*/
addbyte(0xb7);
addbyte(0xd8 | (src_reg & 7));
addbyte(0xc1); /*SHR EBX, 8*/
addbyte(0xeb);
addbyte(8);
addbyte(0x30); /*XORB dst_reg, EBX*/
addbyte(0xd8 | (dst_reg & 7));
} else {
addbyte(0x30); /*XORB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
static __inline void
XOR_HOST_REG_W(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
addbyte(0x66); /*XORW dst_reg, src_reg*/
addbyte(0x45);
addbyte(0x31);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (dst_reg & 8) {
addbyte(0x66); /*XORW dst_reg, src_reg*/
addbyte(0x41);
addbyte(0x31);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (src_reg & 8) {
addbyte(0x66); /*XORW dst_reg, src_reg*/
addbyte(0x44);
addbyte(0x31);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x66); /*XORW dst_reg, src_reg*/
addbyte(0x31);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
static __inline void
XOR_HOST_REG_L(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
addbyte(0x45); /*XORL dst_reg, src_reg*/
addbyte(0x31);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (dst_reg & 8) {
addbyte(0x41); /*XORL dst_reg, src_reg*/
addbyte(0x31);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (src_reg & 8) {
addbyte(0x44); /*XORW dst_reg, src_reg*/
addbyte(0x31);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x31); /*XORW dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
static __inline void
XOR_HOST_REG_IMM(int host_reg, uint32_t imm)
{
if (host_reg & 0x10) {
addbyte(0x66); /*ORW host_reg, imm<<8*/
addbyte(0x41);
addbyte(0x81);
addbyte(0xf0 | (host_reg & 7));
addword(imm << 8);
} else if (host_reg & 8) {
addbyte(0x41); /*ORL host_reg, imm*/
addbyte(0x81);
addbyte(0xf0 | (host_reg & 7));
addlong(imm);
} else {
addbyte(0x81); /*ORL host_reg, imm*/
addbyte(0xf0 | (host_reg & 7));
addlong(imm);
}
}
static __inline void
ADD_HOST_REG_B(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0x66); /*MOVW AX, src_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((src_reg & 7) << 3));
if (!(src_reg & 0x10)) {
addbyte(0x66); /*SHL AX, 8*/
addbyte(0xc1);
addbyte(0xe0);
addbyte(8);
} else {
addbyte(0x66); /*AND AX, 0xff00*/
addbyte(0x25);
addword(0xff00);
}
addbyte(0x66); /*ADDW dst_reg, AX*/
addbyte(0x41);
addbyte(0x01);
addbyte(0xc0 | (dst_reg & 7));
} else if (src_reg & 0x10) {
addbyte(0x66); /*MOVW AX, src_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((src_reg & 7) << 3));
addbyte(0x66); /*SHR AX, 8*/
addbyte(0xc1);
addbyte(0xe8);
addbyte(8);
addbyte(0x41); /*ADDB dst_reg, AL*/
addbyte(0x00);
addbyte(0xc0 | (dst_reg & 7));
} else {
addbyte(0x45); /*ADDB dst_reg, src_reg*/
addbyte(0x00);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else if (dst_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0x66); /*SHL src_reg, 8*/
addbyte(0xc1);
addbyte(0xe0 | src_reg);
addbyte(0x08);
addbyte(0x66); /*ADDW dst_reg, src_reg*/
addbyte(0x41);
addbyte(0x01);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x41); /*ADDB dst_reg, src_reg*/
addbyte(0x00);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else if (src_reg & 8) {
if (src_reg & 0x10) {
addbyte(0x66); /*MOVW AX, src_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((src_reg & 7) << 3));
addbyte(0x66); /*SHR AX, 8*/
addbyte(0xc1);
addbyte(0xe8);
addbyte(8);
addbyte(0x00); /*ADDB dst_reg, AL*/
addbyte(0xc0 | (dst_reg & 7));
} else {
addbyte(0x44); /*ADDB dst_reg, src_reg*/
addbyte(0x00);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else
fatal("!(dst_reg & src_reg & 8)\n");
}
static __inline void
ADD_HOST_REG_W(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
addbyte(0x66); /*ADDW dst_reg, src_reg*/
addbyte(0x45);
addbyte(0x01);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (dst_reg & 8) {
addbyte(0x66); /*ADDW dst_reg, src_reg*/
addbyte(0x41);
addbyte(0x01);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (src_reg & 8) {
addbyte(0x66); /*ADDW dst_reg, src_reg*/
addbyte(0x44);
addbyte(0x01);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else
fatal("!(dst_reg & src_reg & 8)\n");
}
static __inline void
ADD_HOST_REG_L(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
addbyte(0x45); /*ADDL dst_reg, src_reg*/
addbyte(0x01);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (dst_reg & 8) {
addbyte(0x41); /*ADDL dst_reg, src_reg*/
addbyte(0x01);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (src_reg & 8) {
addbyte(0x44); /*ADDL dst_reg, src_reg*/
addbyte(0x01);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else
fatal("!(dst_reg & src_reg & 8)\n");
}
static __inline void
SUB_HOST_REG_B(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0x66); /*MOVW AX, src_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((src_reg & 7) << 3));
if (!(src_reg & 0x10)) {
addbyte(0x66); /*SHL AX, 8*/
addbyte(0xc1);
addbyte(0xe0);
addbyte(8);
} else {
addbyte(0x66); /*AND AX, 0xff00*/
addbyte(0x25);
addword(0xff00);
}
addbyte(0x66); /*SUBW dst_reg, AX*/
addbyte(0x41);
addbyte(0x29);
addbyte(0xc0 | (dst_reg & 7));
} else if (src_reg & 0x10) {
addbyte(0x66); /*MOVW AX, src_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | ((src_reg & 7) << 3));
addbyte(0x66); /*SHR AX, 8*/
addbyte(0xc1);
addbyte(0xe8);
addbyte(8);
addbyte(0x41); /*SUBB dst_reg, AL*/
addbyte(0x28);
addbyte(0xc0 | (dst_reg & 7));
} else {
addbyte(0x45); /*SUBB dst_reg, src_reg*/
addbyte(0x28);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else if (dst_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0x66); /*SHL src_reg, 8*/
addbyte(0xc1);
addbyte(0xe0 | src_reg);
addbyte(0x08);
addbyte(0x66); /*SUBW dst_reg, src_reg*/
addbyte(0x41);
addbyte(0x29);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x41); /*SUBB dst_reg, src_reg*/
addbyte(0x28);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else if (src_reg & 8) {
if (dst_reg & 0x10) {
addbyte(0xc1); /*SHR dst_reg, 8*/
addbyte(0xe8 | (dst_reg & 7));
addbyte(8);
}
if (src_reg & 0x10) {
addbyte(0x41); /*MOVZX EBX, src_reg*/
addbyte(0x0f);
addbyte(0xb7);
addbyte(0xd8 | (src_reg & 7));
addbyte(0xc1); /*SHR EBX, 8*/
addbyte(0xeb);
addbyte(8);
addbyte(0x28); /*SUBB dst_reg, EBX*/
addbyte(0xd8 | (dst_reg & 7));
} else {
addbyte(0x44); /*SUBB dst_reg, src_reg*/
addbyte(0x28);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
} else {
if (dst_reg & 0x10) {
addbyte(0xc1); /*SHR dst_reg, 8*/
addbyte(0xe8 | (dst_reg & 7));
addbyte(8);
}
if (src_reg & 0x10) {
addbyte(0x0f); /*MOVZX EBX, src_reg*/
addbyte(0xb7);
addbyte(0xd8 | (src_reg & 7));
addbyte(0xc1); /*SHR EBX, 8*/
addbyte(0xeb);
addbyte(8);
addbyte(0x28); /*SUBB dst_reg, EBX*/
addbyte(0xd8 | (dst_reg & 7));
} else {
addbyte(0x28); /*SUBB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
static __inline void
SUB_HOST_REG_W(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
addbyte(0x66); /*SUBW dst_reg, src_reg*/
addbyte(0x45);
addbyte(0x29);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (dst_reg & 8) {
addbyte(0x66); /*SUBW dst_reg, src_reg*/
addbyte(0x41);
addbyte(0x29);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (src_reg & 8) {
addbyte(0x66); /*SUBW dst_reg, src_reg*/
addbyte(0x44);
addbyte(0x29);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x66); /*SUBW dst_reg, src_reg*/
addbyte(0x29);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
static __inline void
SUB_HOST_REG_L(int dst_reg, int src_reg)
{
if (dst_reg & src_reg & 8) {
addbyte(0x45); /*SUBL dst_reg, src_reg*/
addbyte(0x29);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (dst_reg & 8) {
addbyte(0x41); /*SUBL dst_reg, src_reg*/
addbyte(0x29);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else if (src_reg & 8) {
addbyte(0x44); /*SUBL dst_reg, src_reg*/
addbyte(0x29);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
} else {
addbyte(0x29); /*SUBL dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
static __inline int
CMP_HOST_REG_B(int dst_reg, int src_reg)
{
if (dst_reg & 8) {
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = (dst_reg & 0x10) | REG_EDX;
}
SUB_HOST_REG_B(dst_reg, src_reg);
return dst_reg & ~0x10;
}
static __inline int
CMP_HOST_REG_W(int dst_reg, int src_reg)
{
if (dst_reg & 8) {
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
SUB_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static __inline int
CMP_HOST_REG_L(int dst_reg, int src_reg)
{
if (dst_reg & 8) {
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
SUB_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
static __inline void
ADD_HOST_REG_IMM_B(int host_reg, uint8_t imm)
{
if (host_reg & 0x10) {
addbyte(0x66); /*ADDW host_reg, imm*/
if (host_reg & 8)
addbyte(0x41);
addbyte(0x81);
addbyte(0xC0 | (host_reg & 7));
addword(imm << 8);
} else {
if (host_reg & 8)
addbyte(0x41);
addbyte(0x80); /*ADDB host_reg, imm*/
addbyte(0xC0 | (host_reg & 7));
addbyte(imm);
}
}
static __inline void
ADD_HOST_REG_IMM_W(int host_reg, uint16_t imm)
{
addbyte(0x66); /*ADDW host_reg, imm*/
if (host_reg & 8)
addbyte(0x41);
addbyte(0x81);
addbyte(0xC0 | (host_reg & 7));
addword(imm);
}
static __inline void
ADD_HOST_REG_IMM(int host_reg, uint32_t imm)
{
if (host_reg & 8)
addbyte(0x41);
addbyte(0x81); /*ADDL host_reg, imm*/
addbyte(0xC0 | (host_reg & 7));
addlong(imm);
}
static __inline void
SUB_HOST_REG_IMM_B(int host_reg, uint8_t imm)
{
if (host_reg & 0x10) {
addbyte(0x66); /*SUBW host_reg, imm*/
if (host_reg & 8)
addbyte(0x41);
addbyte(0x81);
addbyte(0xE8 | (host_reg & 7));
addword(imm << 8);
} else {
if (host_reg & 8)
addbyte(0x41);
addbyte(0x80); /*SUBB host_reg, imm*/
addbyte(0xE8 | (host_reg & 7));
addbyte(imm);
}
}
static __inline void
SUB_HOST_REG_IMM_W(int host_reg, uint16_t imm)
{
addbyte(0x66); /*SUBW host_reg, imm*/
if (host_reg & 8)
addbyte(0x41);
addbyte(0x81);
addbyte(0xE8 | (host_reg & 7));
addword(imm);
}
static __inline void
SUB_HOST_REG_IMM(int host_reg, uint32_t imm)
{
if (host_reg & 8)
addbyte(0x41);
addbyte(0x81); /*SUBL host_reg, imm*/
addbyte(0xE8 | (host_reg & 7));
addlong(imm);
}
static __inline void
INC_HOST_REG_W(int host_reg)
{
addbyte(0x66); /*INCW host_reg*/
if (host_reg & 8)
addbyte(0x41);
addbyte(0xff);
addbyte(0xc0 | (host_reg & 7));
}
static __inline void
INC_HOST_REG(int host_reg)
{
if (host_reg & 8)
addbyte(0x41);
addbyte(0xff); /*INCL host_reg*/
addbyte(0xc0 | (host_reg & 7));
}
static __inline void
DEC_HOST_REG_W(int host_reg)
{
addbyte(0x66); /*DECW host_reg*/
if (host_reg & 8)
addbyte(0x41);
addbyte(0xff);
addbyte(0xc8 | (host_reg & 7));
}
static __inline void
DEC_HOST_REG(int host_reg)
{
if (host_reg & 8)
addbyte(0x41);
addbyte(0xff); /*DECL host_reg*/
addbyte(0xc8 | (host_reg & 7));
}
static __inline int
CMP_HOST_REG_IMM_B(int host_reg, uint8_t imm)
{
if (host_reg & 8) {
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3) | REG_EDX);
host_reg = (host_reg & 0x10) | REG_EDX;
}
SUB_HOST_REG_IMM_B(host_reg, imm);
return host_reg;
}
static __inline int
CMP_HOST_REG_IMM_W(int host_reg, uint16_t imm)
{
if (host_reg & 8) {
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3) | REG_EDX);
host_reg = REG_EDX;
}
SUB_HOST_REG_IMM_W(host_reg, imm);
return host_reg;
}
static __inline int
CMP_HOST_REG_IMM_L(int host_reg, uint32_t imm)
{
if (host_reg & 8) {
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3) | REG_EDX);
host_reg = REG_EDX;
}
SUB_HOST_REG_IMM(host_reg, imm);
return host_reg;
}
static __inline void
LOAD_STACK_TO_EA(int off)
{
if (stack32) {
addbyte(0x8b); /*MOVL EAX,[ESP]*/
addbyte(0x45 | (REG_EAX << 3));
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].l));
if (off) {
addbyte(0x83); /*ADD EAX, off*/
addbyte(0xc0 | (0 << 3) | REG_EAX);
addbyte(off);
}
} else {
addbyte(0x0f); /*MOVZX EAX,W[ESP]*/
addbyte(0xb7);
addbyte(0x45 | (REG_EAX << 3));
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].w));
if (off) {
addbyte(0x66); /*ADD AX, off*/
addbyte(0x05);
addword(off);
}
}
}
static __inline void
LOAD_EBP_TO_EA(int off)
{
if (stack32) {
addbyte(0x8b); /*MOVL EAX,[EBP]*/
addbyte(0x45 | (REG_EAX << 3));
addbyte((uint8_t) cpu_state_offset(regs[REG_EBP].l));
if (off) {
addbyte(0x83); /*ADD EAX, off*/
addbyte(0xc0 | (0 << 3) | REG_EAX);
addbyte(off);
}
} else {
addbyte(0x0f); /*MOVZX EAX,W[EBP]*/
addbyte(0xb7);
addbyte(0x45 | (REG_EAX << 3));
addbyte((uint8_t) cpu_state_offset(regs[REG_BP].l));
if (off) {
addbyte(0x66); /*ADD AX, off*/
addbyte(0x05);
addword(off);
}
}
}
static __inline void
SP_MODIFY(int off)
{
if (stack32) {
if (off < 0x80) {
addbyte(0x83); /*ADD [ESP], off*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].l));
addbyte(off);
} else {
addbyte(0x81); /*ADD [ESP], off*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].l));
addlong(off);
}
} else {
if (off < 0x80) {
addbyte(0x66); /*ADD [SP], off*/
addbyte(0x83);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].w));
addbyte(off);
} else {
addbyte(0x66); /*ADD [SP], off*/
addbyte(0x81);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].w));
addword(off);
}
}
}
static __inline void
TEST_ZERO_JUMP_W(int host_reg, uint32_t new_pc, int taken_cycles)
{
addbyte(0x66); /*CMPW host_reg, 0*/
if (host_reg & 8)
addbyte(0x41);
addbyte(0x83);
addbyte(0xc0 | 0x38 | (host_reg & 7));
addbyte(0);
addbyte(0x75); /*JNZ +*/
addbyte(7 + 5 + (taken_cycles ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(new_pc);
if (taken_cycles) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(taken_cycles);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
TEST_ZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
{
if (host_reg & 8)
addbyte(0x41);
addbyte(0x83); /*CMPW host_reg, 0*/
addbyte(0xc0 | 0x38 | (host_reg & 7));
addbyte(0);
addbyte(0x75); /*JNZ +*/
addbyte(7 + 5 + (taken_cycles ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(new_pc);
if (taken_cycles) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(taken_cycles);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
TEST_NONZERO_JUMP_W(int host_reg, uint32_t new_pc, int taken_cycles)
{
addbyte(0x66); /*CMPW host_reg, 0*/
if (host_reg & 8)
addbyte(0x41);
addbyte(0x83);
addbyte(0xc0 | 0x38 | (host_reg & 7));
addbyte(0);
addbyte(0x74); /*JZ +*/
addbyte(7 + 5 + (taken_cycles ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(new_pc);
if (taken_cycles) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(taken_cycles);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
TEST_NONZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
{
if (host_reg & 8)
addbyte(0x41);
addbyte(0x83); /*CMPW host_reg, 0*/
addbyte(0xc0 | 0x38 | (host_reg & 7));
addbyte(0);
addbyte(0x74); /*JZ +*/
addbyte(7 + 5 + (taken_cycles ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(new_pc);
if (taken_cycles) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(taken_cycles);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
{
uint8_t *jump1;
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN) {
addbyte(0x83); /*CMP flags_res, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(flags_res));
addbyte(0);
addbyte(0x74); /*JZ +*/
} else {
CALL_FUNC((uintptr_t) ZF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x75); /*JNZ +*/
}
jump1 = &codeblock[block_current].data[block_pos];
addbyte(0);
CALL_FUNC((uintptr_t) CF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
if (not )
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(7 + 5 + (timing_bt ? 4 : 0));
if (!not )
*jump1 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump1 - 1;
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(op_pc + pc_offset + offset);
if (timing_bt) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(timing_bt);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
if (not )
*jump1 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump1 - 1;
}
static __inline void
BRANCH_COND_L(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
{
CALL_FUNC((uintptr_t) NF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x0f); /*SETNE BL*/
addbyte(0x95);
addbyte(0xc3);
CALL_FUNC((uintptr_t) VF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x0f); /*SETNE AL*/
addbyte(0x95);
addbyte(0xc0);
addbyte(0x38); /*CMP AL, BL*/
addbyte(0xd8);
if (not )
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(7 + 5 + (timing_bt ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(op_pc + pc_offset + offset);
if (timing_bt) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(timing_bt);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
{
uint8_t *jump1;
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN) {
addbyte(0x83); /*CMP flags_res, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(flags_res));
addbyte(0);
addbyte(0x74); /*JZ +*/
} else {
CALL_FUNC((uintptr_t) ZF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x75); /*JNZ +*/
}
jump1 = &codeblock[block_current].data[block_pos];
addbyte(0);
CALL_FUNC((uintptr_t) NF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x0f); /*SETNE BL*/
addbyte(0x95);
addbyte(0xc3);
CALL_FUNC((uintptr_t) VF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x0f); /*SETNE AL*/
addbyte(0x95);
addbyte(0xc0);
addbyte(0x38); /*CMP AL, BL*/
addbyte(0xd8);
if (not )
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(7 + 5 + (timing_bt ? 4 : 0));
if (!not )
*jump1 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump1 - 1;
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(op_pc + pc_offset + offset);
if (timing_bt) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(timing_bt);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
if (not )
*jump1 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump1 - 1;
}
static __inline int
LOAD_VAR_W(uintptr_t addr)
{
int host_reg = REG_EBX;
if (addr >= (uintptr_t) &cpu_state && addr < ((uintptr_t) &cpu_state) + 0x100) {
addbyte(0x0f); /*MOVZX host_reg, offset[cpu_state]*/
addbyte(0xb7);
addbyte(0x45 | (host_reg << 3));
addbyte(addr - (uintptr_t) &cpu_state - 128);
} else if (IS_32_ADDR(addr)) {
addbyte(0x0f); /*MOVZX host_reg,[reg]*/
addbyte(0xb7);
addbyte(0x04 | (host_reg << 3));
addbyte(0x25);
addlong((uint32_t) addr);
} else {
addbyte(0x48); /*MOV host_reg, &addr*/
addbyte(0xb8 | host_reg);
addquad(addr);
addbyte(0x0f); /*MOVZX host_reg, [host_reg]*/
addbyte(0xb7);
addbyte(host_reg | (host_reg << 3));
}
return host_reg;
}
static __inline int
LOAD_VAR_WL(uintptr_t addr)
{
return LOAD_VAR_W(addr);
}
static __inline int
LOAD_VAR_L(uintptr_t addr)
{
int host_reg = REG_EBX;
if (addr >= (uintptr_t) &cpu_state && addr < ((uintptr_t) &cpu_state) + 0x100) {
addbyte(0x8b); /*MOVL host_reg, offset[cpu_state]*/
addbyte(0x45 | (host_reg << 3));
addbyte(addr - (uintptr_t) &cpu_state - 128);
} else if (IS_32_ADDR(addr)) {
addbyte(0x8b); /*MOVL host_reg,[reg]*/
addbyte(0x04 | (host_reg << 3));
addbyte(0x25);
addlong((uint32_t) addr);
} else {
addbyte(0x48); /*MOV host_reg, &addr*/
addbyte(0xb8 | host_reg);
addquad(addr);
addbyte(0x8b); /*MOVL host_reg, [host_reg]*/
addbyte(host_reg | (host_reg << 3));
}
return host_reg;
}
static __inline int
COPY_REG(int src_reg)
{
if (src_reg & 8)
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | REG_ECX | ((src_reg & 7) << 3));
return REG_ECX | (src_reg & 0x10);
}
static __inline int
LOAD_HOST_REG(int host_reg)
{
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | REG_EBX | ((host_reg & 7) << 3));
return REG_EBX | (host_reg & 0x10);
}
static __inline int
ZERO_EXTEND_W_B(int reg)
{
if (reg & 0x10) {
addbyte(0x44); /*MOV EAX, reg*/
addbyte(0x89);
addbyte(0xc0 | (reg << 3));
addbyte(0x0f); /*MOVZX EAX, AH*/
addbyte(0xb6);
addbyte(0xc4);
return REG_EAX;
}
if (reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVZX regl, regb*/
addbyte(0xb6);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static __inline int
ZERO_EXTEND_L_B(int reg)
{
if (reg & 0x10) {
addbyte(0x44); /*MOV EAX, reg*/
addbyte(0x89);
addbyte(0xc0 | (reg << 3));
addbyte(0x0f); /*MOVZX EAX, AH*/
addbyte(0xb6);
addbyte(0xc4);
return REG_EAX;
}
if (reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVZX regl, regb*/
addbyte(0xb6);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static __inline int
ZERO_EXTEND_L_W(int reg)
{
if (reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVZX regl, regw*/
addbyte(0xb7);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static __inline int
SIGN_EXTEND_W_B(int reg)
{
if (reg & 0x10) {
addbyte(0x44); /*MOV EAX, reg*/
addbyte(0x89);
addbyte(0xc0 | (reg << 3));
addbyte(0x0f); /*MOVSX EAX, AH*/
addbyte(0xbe);
addbyte(0xc4);
return REG_EAX;
}
if (reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVSX regl, regb*/
addbyte(0xbe);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static __inline int
SIGN_EXTEND_L_B(int reg)
{
if (reg & 0x10) {
addbyte(0x44); /*MOV EAX, reg*/
addbyte(0x89);
addbyte(0xc0 | (reg << 3));
addbyte(0x0f); /*MOVSX EAX, AH*/
addbyte(0xbe);
addbyte(0xc4);
return REG_EAX;
}
if (reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVSX regl, regb*/
addbyte(0xbe);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static __inline int
SIGN_EXTEND_L_W(int reg)
{
if (reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVSX regl, regw*/
addbyte(0xbf);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static __inline void
SHL_B_IMM(int reg, int count)
{
if (reg & 0x10) {
addbyte(0x44); /*MOV EAX, reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EAX | ((reg & 7) << 3));
addbyte(0xc0); /*SHL AH, count*/
addbyte(0xe0 | REG_AH);
addbyte(count);
addbyte(0x41); /*MOV reg, EAX*/
addbyte(0x89);
addbyte(0xc0 | (REG_EAX << 3) | (reg & 7));
} else {
if (reg & 8)
addbyte(0x41);
addbyte(0xc0); /*SHL reg, count*/
addbyte(0xc0 | (reg & 7) | 0x20);
addbyte(count);
}
}
static __inline void
SHL_W_IMM(int reg, int count)
{
addbyte(0x66); /*SHL reg, count*/
if (reg & 8)
addbyte(0x41);
addbyte(0xc1);
addbyte(0xc0 | (reg & 7) | 0x20);
addbyte(count);
}
static __inline void
SHL_L_IMM(int reg, int count)
{
if (reg & 8)
addbyte(0x41);
addbyte(0xc1); /*SHL reg, count*/
addbyte(0xc0 | (reg & 7) | 0x20);
addbyte(count);
}
static __inline void
SHR_B_IMM(int reg, int count)
{
if (reg & 0x10) {
addbyte(0x44); /*MOV EAX, reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EAX | ((reg & 7) << 3));
addbyte(0xc0); /*SHR AH, count*/
addbyte(0xe8 | REG_AH);
addbyte(count);
addbyte(0x41); /*MOV reg, EAX*/
addbyte(0x89);
addbyte(0xc0 | (REG_EAX << 3) | (reg & 7));
} else {
if (reg & 8)
addbyte(0x41);
addbyte(0xc0); /*SHR reg, count*/
addbyte(0xc0 | (reg & 7) | 0x28);
addbyte(count);
}
}
static __inline void
SHR_W_IMM(int reg, int count)
{
addbyte(0x66); /*SHR reg, count*/
if (reg & 8)
addbyte(0x41);
addbyte(0xc1);
addbyte(0xc0 | (reg & 7) | 0x28);
addbyte(count);
}
static __inline void
SHR_L_IMM(int reg, int count)
{
if (reg & 8)
addbyte(0x41);
addbyte(0xc1); /*SHR reg, count*/
addbyte(0xc0 | (reg & 7) | 0x28);
addbyte(count);
}
static __inline void
SAR_B_IMM(int reg, int count)
{
if (reg & 0x10) {
addbyte(0x44); /*MOV EAX, reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EAX | ((reg & 7) << 3));
addbyte(0xc0); /*SAR AH, count*/
addbyte(0xf8 | REG_AH);
addbyte(count);
addbyte(0x41); /*MOV reg, EAX*/
addbyte(0x89);
addbyte(0xc0 | (REG_EAX << 3) | (reg & 7));
} else {
if (reg & 8)
addbyte(0x41);
addbyte(0xc0); /*SAR reg, count*/
addbyte(0xc0 | (reg & 7) | 0x38);
addbyte(count);
}
}
static __inline void
SAR_W_IMM(int reg, int count)
{
addbyte(0x66); /*SAR reg, count*/
if (reg & 8)
addbyte(0x41);
addbyte(0xc1);
addbyte(0xc0 | (reg & 7) | 0x38);
addbyte(count);
}
static __inline void
SAR_L_IMM(int reg, int count)
{
if (reg & 8)
addbyte(0x41);
addbyte(0xc1); /*SAR reg, count*/
addbyte(0xc0 | (reg & 7) | 0x38);
addbyte(count);
}
static __inline void
NEG_HOST_REG_B(int reg)
{
if (reg & 0x10) {
if (reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOV BX, reg*/
addbyte(0xc3 | ((reg & 7) << 3));
addbyte(0xf6); /*NEG BH*/
addbyte(0xdf);
if (reg & 8)
addbyte(0x41);
addbyte(0x89); /*MOV reg, BX*/
addbyte(0xd8 | (reg & 7));
} else {
if (reg & 8)
addbyte(0x41);
addbyte(0xf6);
addbyte(0xd8 | (reg & 7));
}
}
static __inline void
NEG_HOST_REG_W(int reg)
{
addbyte(0x66);
if (reg & 8)
addbyte(0x41);
addbyte(0xf7);
addbyte(0xd8 | (reg & 7));
}
static __inline void
NEG_HOST_REG_L(int reg)
{
if (reg & 8)
addbyte(0x41);
addbyte(0xf7);
addbyte(0xd8 | (reg & 7));
}
static __inline void
FP_ENTER(void)
{
if (codegen_fpu_entered)
return;
if (IS_32_ADDR(&cr0)) {
addbyte(0xf6); /*TEST cr0, 0xc*/
addbyte(0x04);
addbyte(0x25);
addlong((uintptr_t) &cr0);
addbyte(0x0c);
} else {
addbyte(0x48); /*MOV RAX, &cr0*/
addbyte(0xb8 | REG_EAX);
addquad((uint64_t) &cr0);
addbyte(0xf6); /*TEST [RAX], 0xc*/
addbyte(0 | (REG_EAX << 3));
addbyte(0x0c);
}
addbyte(0x74); /*JZ +*/
addbyte(7 + 5 + 12 + 5);
addbyte(0xC7); /*MOVL [oldpc],op_old_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(oldpc));
addlong(op_old_pc);
load_param_1_32(&codeblock[block_current], 7);
CALL_FUNC((uintptr_t) x86_int);
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
codegen_fpu_entered = 1;
}
static __inline void
FP_FXCH(int reg)
{
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV EBX, EAX*/
addbyte(0xc3);
addbyte(0x83); /*ADD EAX, reg*/
addbyte(0xc0);
addbyte(reg);
addbyte(0x48); /*MOV RDX, ST[RBX*8]*/
addbyte(0x8b);
addbyte(0x54);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(0x07);
addbyte(0x48); /*MOV RCX, ST[RAX*8]*/
addbyte(0x8b);
addbyte(0x4c);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x48); /*MOV ST[RAX*8], RDX*/
addbyte(0x89);
addbyte(0x54);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x48); /*MOV ST[RBX*8], RCX*/
addbyte(0x89);
addbyte(0x4c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x8a); /*MOV CL, tag[EAX]*/
addbyte(0x4c);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(0x8a); /*MOV DL, tag[EBX]*/
addbyte(0x54);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(0x88); /*MOV tag[EBX], CL*/
addbyte(0x4c);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(0x88); /*MOV tag[EAX], DL*/
addbyte(0x54);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(0x48); /*MOV RDX, MM[RBX*8]*/
addbyte(0x8b);
addbyte(0x54);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0x48); /*MOV RCX, MM[RAX*8]*/
addbyte(0x8b);
addbyte(0x4c);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0x48); /*MOV MM[RAX*8], RDX*/
addbyte(0x89);
addbyte(0x54);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0x48); /*MOV MM[RBX*8], RCX*/
addbyte(0x89);
addbyte(0x4c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM));
}
static __inline void
FP_FLD(int reg)
{
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV EBX, EAX*/
addbyte(0xc3);
if (reg) {
addbyte(0x83); /*ADD EAX, reg*/
addbyte(0xc0);
addbyte(reg);
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(0x07);
} else {
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
}
addbyte(0x48); /*MOV RCX, ST[EAX*8]*/
addbyte(0x8b);
addbyte(0x4c);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(0x07);
addbyte(0x48); /*MOV RDX, ST_i64[EAX*8]*/
addbyte(0x8b);
addbyte(0x54);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0x8a); /*MOV AL, [tag+EAX]*/
addbyte(0x44);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(0x48); /*MOV ST[EBX*8], RCX*/
addbyte(0x89);
addbyte(0x4c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x48); /*MOV ST_i64[EBX*8], RDX*/
addbyte(0x89);
addbyte(0x54);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0x88); /*MOV [tag+EBX], AL*/
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(0x89); /*MOV [TOP], EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
}
static __inline void
FP_FST(int reg)
{
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x48); /*MOV RCX, ST[EAX*8]*/
addbyte(0x8b);
addbyte(0x4c);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x8a); /*MOV BL, [tag+EAX]*/
addbyte(0x5c);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag));
if (reg) {
addbyte(0x83); /*ADD EAX, reg*/
addbyte(0xc0);
addbyte(reg);
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(0x07);
}
addbyte(0x48); /*MOV ST[EAX*8], RCX*/
addbyte(0x89);
addbyte(0x4c);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x88); /*MOV [tag+EAX], BL*/
addbyte(0x5c);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag));
}
static __inline void
FP_POP(void)
{
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xc6); /*MOVB tag[EAX], 3*/
addbyte(0x44);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(3);
addbyte(0x83); /*ADD AL, 1*/
addbyte(0xc0);
addbyte(1);
addbyte(0x83); /*AND AL, 7*/
addbyte(0xe0);
addbyte(7);
addbyte(0x89); /*MOV [TOP], EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
}
static __inline void
FP_POP2(void)
{
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xc6); /*MOVB tag[EAX], 3*/
addbyte(0x44);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(3);
addbyte(0x83); /*ADD AL, 2*/
addbyte(0xc0);
addbyte(2);
addbyte(0x83); /*AND AL, 7*/
addbyte(0xe0);
addbyte(7);
addbyte(0x89); /*MOV [TOP], EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
}
static __inline void
FP_LOAD_S(void)
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x66); /*MOVD XMM0, EAX*/
addbyte(0x0f);
addbyte(0x6e);
addbyte(0xc0);
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
addbyte(0xf3); /*CVTSS2SD XMM0, XMM0*/
addbyte(0x0f);
addbyte(0x5a);
addbyte(0xc0);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0x85); /*TEST EAX, EAX*/
addbyte(0xc0);
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x66); /*MOVQ [ST+EBX*8], XMM0*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x0f); /*SETE [tag+EBX]*/
addbyte(0x94);
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag));
}
static __inline void
FP_LOAD_D(void)
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0x48); /*TEST RAX, RAX*/
addbyte(0x85);
addbyte(0xc0);
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x48); /*MOVQ [ST+EBX*8], RAX*/
addbyte(0x89);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x0f); /*SETE [tag+EBX]*/
addbyte(0x94);
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag));
}
static __inline void
FP_LOAD_IW(void)
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x0f); /*MOVSX EAX, AX*/
addbyte(0xbf);
addbyte(0xc0);
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
addbyte(0xf2); /*CVTSI2SD XMM0, EAX*/
addbyte(0x0f);
addbyte(0x2a);
addbyte(0xc0);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0x85); /*TEST EAX, EAX*/
addbyte(0xc0);
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x66); /*MOVQ [ST+EBX*8], XMM0*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x0f); /*SETE [tag+EBX]*/
addbyte(0x94);
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag));
}
static __inline void
FP_LOAD_IL(void)
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
addbyte(0xf2); /*CVTSI2SD XMM0, EAX*/
addbyte(0x0f);
addbyte(0x2a);
addbyte(0xc0);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0x85); /*TEST EAX, EAX*/
addbyte(0xc0);
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x66); /*MOVQ [ST+EBX*8], XMM0*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x0f); /*SETE [tag+EBX]*/
addbyte(0x94);
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag));
}
static __inline void
FP_LOAD_IQ(void)
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
addbyte(0xf2); /*CVTSI2SDQ XMM0, RAX*/
addbyte(0x48);
addbyte(0x0f);
addbyte(0x2a);
addbyte(0xc0);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0x48); /*TEST RAX, RAX*/
addbyte(0x85);
addbyte(0xc0);
addbyte(0x48); /*MOV [ST_i64+EBX*8], RAX*/
addbyte(0x89);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x0f); /*SETE AL*/
addbyte(0x94);
addbyte(0xc0);
addbyte(0x66); /*MOVQ [ST+EBX*8], XMM0*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x0c); /*OR AL, TAG_UINT64*/
addbyte(TAG_UINT64);
addbyte(0x88); /*MOV [tag+EBX], AL*/
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag));
}
static __inline void
FP_LOAD_IMM_Q(uint64_t v)
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0xc7); /*MOV ST[EBP+EBX*8], v*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addlong(v & 0xffffffff);
addbyte(0xc7); /*MOV ST[EBP+EBX*8]+4, v*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST) + 4);
addlong(v >> 32);
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xc6); /*MOV [tag+EBX], (v ? 0 : 1)*/
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(v ? 0 : 1);
}
static __inline void
FP_FCHS(void)
{
addbyte(0x8b); /*MOV EAX, TOP*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xf2); /*SUBSD XMM0, XMM0*/
addbyte(0x0f);
addbyte(0x5c);
addbyte(0xc0);
addbyte(0xf2); /*SUBSD XMM0, ST[EAX*8]*/
addbyte(0x0f);
addbyte(0x5c);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x80); /*AND tag[EAX], ~TAG_UINT64*/
addbyte(0x64);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(TAG_NOT_UINT64);
addbyte(0xf2); /*MOVSD ST[EAX*8], XMM0*/
addbyte(0x0f);
addbyte(0x11);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
}
static __inline int
FP_LOAD_REG(int reg)
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
if (reg) {
addbyte(0x83); /*ADD EBX, reg*/
addbyte(0xc0 | REG_EBX);
addbyte(reg);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe0 | REG_EBX);
addbyte(0x07);
}
addbyte(0xf3); /*MOVQ XMM0, ST[EBX*8]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0xf2); /*CVTSD2SS XMM0, XMM0*/
addbyte(0x0f);
addbyte(0x5a);
addbyte(0xc0);
addbyte(0x66); /*MOVD EBX, XMM0*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0xc0 | REG_EBX);
return REG_EBX;
}
static __inline void
FP_LOAD_REG_D(int reg, int *host_reg1, int *host_reg2)
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
if (reg) {
addbyte(0x83); /*ADD EBX, reg*/
addbyte(0xc0 | REG_EBX);
addbyte(reg);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe0 | REG_EBX);
addbyte(0x07);
}
addbyte(0x48); /*MOV RBX, ST[EBX*8]*/
addbyte(0x8b);
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
*host_reg1 = REG_EBX;
}
static __inline int64_t
x87_fround16_64(double b)
{
int16_t a;
int16_t c;
switch ((cpu_state.npxc >> 10) & 3) {
case 0: /*Nearest*/
a = (int16_t) floor(b);
c = (int16_t) floor(b + 1.0);
if ((b - a) < (c - b))
return (int64_t) a;
else if ((b - a) > (c - b))
return (int64_t) c;
else
return (a & 1) ? c : a;
case 1: /*Down*/
return (int64_t) ((int16_t) floor(b));
case 2: /*Up*/
return (int64_t) ((int16_t) ceil(b));
case 3: /*Chop*/
return (int64_t) ((int16_t) b);
}
return 0;
}
static __inline int64_t
x87_fround32_64(double b)
{
int32_t a;
int32_t c;
switch ((cpu_state.npxc >> 10) & 3) {
case 0: /*Nearest*/
a = (int32_t) floor(b);
c = (int32_t) floor(b + 1.0);
if ((b - a) < (c - b))
return (int64_t) a;
else if ((b - a) > (c - b))
return (int64_t) c;
else
return (a & 1) ? c : a;
case 1: /*Down*/
return (int64_t) ((int32_t) floor(b));
case 2: /*Up*/
return (int64_t) ((int32_t) ceil(b));
case 3: /*Chop*/
return (int64_t) ((int32_t) b);
}
return 0;
}
static __inline int64_t
x87_fround(double b)
{
int64_t a;
int64_t c;
switch ((cpu_state.npxc >> 10) & 3) {
case 0: /*Nearest*/
a = (int64_t) floor(b);
c = (int64_t) floor(b + 1.0);
if ((b - a) < (c - b))
return a;
else if ((b - a) > (c - b))
return c;
else
return (a & 1) ? c : a;
case 1: /*Down*/
return (int64_t) floor(b);
case 2: /*Up*/
return (int64_t) ceil(b);
case 3: /*Chop*/
return (int64_t) b;
}
return 0;
}
static __inline int
FP_LOAD_REG_INT_W(int reg)
{
addbyte(0x89); /*MOV EBX, EAX*/
addbyte(0xc3);
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
if (reg) {
addbyte(0x83); /*ADD EAX, reg*/
addbyte(0xc0);
addbyte(reg);
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(7);
}
addbyte(0xf3); /*MOVQ XMM0, ST[EAX*8]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
CALL_FUNC((uintptr_t) x87_fround16_64);
addbyte(0x93); /*XCHG EBX, EAX*/
return REG_EBX;
}
static __inline int
FP_LOAD_REG_INT(int reg)
{
addbyte(0x89); /*MOV EBX, EAX*/
addbyte(0xc3);
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
if (reg) {
addbyte(0x83); /*ADD EAX, reg*/
addbyte(0xc0);
addbyte(reg);
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(7);
}
addbyte(0xf3); /*MOVQ XMM0, ST[EAX*8]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
CALL_FUNC((uintptr_t) x87_fround32_64);
addbyte(0x93); /*XCHG EBX, EAX*/
return REG_EBX;
}
static __inline void
FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
{
addbyte(0x89); /*MOV EBX, EAX*/
addbyte(0xc3);
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
if (reg) {
addbyte(0x83); /*ADD EAX, reg*/
addbyte(0xc0);
addbyte(reg);
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(7);
}
if (codegen_fpu_loaded_iq[cpu_state.TOP] && (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)) {
/*If we know the register was loaded with FILDq in this block and
has not been modified, then we can skip most of the conversion
and just load the 64-bit integer representation directly */
addbyte(0x48); /*MOV RAX, [ST_i64+EAX*8]*/
addbyte(0x8b);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0x48); /*XCHG RBX, RAX*/
addbyte(0x93);
*host_reg1 = REG_EBX;
return;
}
addbyte(0xf6); /*TEST TAG[EAX], TAG_UINT64*/
addbyte(0x44);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(TAG_UINT64);
addbyte(0x74); /*JZ +*/
addbyte(5 + 2);
addbyte(0x48); /*MOV RAX, [ST_i64+EAX*8]*/
addbyte(0x8b);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0xeb); /*JMP done*/
addbyte(6 + 12);
addbyte(0xf3); /*MOVQ XMM0, ST[EAX*8]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
CALL_FUNC((uintptr_t) x87_fround);
addbyte(0x48); /*XCHG RBX, RAX*/
addbyte(0x93);
*host_reg1 = REG_EBX;
}
#define FPU_ADD 0
#define FPU_DIV 4
#define FPU_DIVR 5
#define FPU_MUL 1
#define FPU_SUB 2
#define FPU_SUBR 3
static __inline void
FP_OP_REG(int op, int dst, int src)
{
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV EBX, EAX*/
addbyte(0xc3);
if (dst) {
addbyte(0x83); /*ADD EAX, reg*/
addbyte(0xc0);
addbyte(dst);
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(0x07);
}
if (src) {
addbyte(0x83); /*ADD EBX, reg*/
addbyte(0xc0 | REG_EBX);
addbyte(src);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe0 | REG_EBX);
addbyte(0x07);
}
addbyte(0x80); /*AND tag[EAX], ~TAG_UINT64*/
addbyte(0x64);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(TAG_NOT_UINT64);
if (op == FPU_DIVR || op == FPU_SUBR) {
addbyte(0xf3); /*MOVQ XMM0, ST[RBX*8]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
} else {
addbyte(0xf3); /*MOVQ XMM0, ST[RAX*8]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
}
switch (op) {
case FPU_ADD:
addbyte(0xf2); /*ADDSD XMM0, ST[RBX*8]*/
addbyte(0x0f);
addbyte(0x58);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
break;
case FPU_DIV:
addbyte(0xf2); /*DIVSD XMM0, ST[RBX*8]*/
addbyte(0x0f);
addbyte(0x5e);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
break;
case FPU_DIVR:
addbyte(0xf2); /*DIVSD XMM0, ST[RAX*8]*/
addbyte(0x0f);
addbyte(0x5e);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
break;
case FPU_MUL:
addbyte(0xf2); /*MULSD XMM0, ST[RBX*8]*/
addbyte(0x0f);
addbyte(0x59);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
break;
case FPU_SUB:
addbyte(0xf2); /*SUBSD XMM0, ST[RBX*8]*/
addbyte(0x0f);
addbyte(0x5c);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
break;
case FPU_SUBR:
addbyte(0xf2); /*SUBSD XMM0, ST[RAX*8]*/
addbyte(0x0f);
addbyte(0x5c);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
break;
}
addbyte(0x66); /*MOVQ [RSI+RAX*8], XMM0*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
}
static __inline void
FP_OP_MEM(int op)
{
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xf3); /*MOVQ XMM0, ST[RAX*8]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x80); /*AND tag[EAX], ~TAG_UINT64*/
addbyte(0x64);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag));
addbyte(TAG_NOT_UINT64);
switch (op) {
case FPU_ADD:
addbyte(0xf2); /*ADDSD XMM0, XMM1*/
addbyte(0x0f);
addbyte(0x58);
addbyte(0xc1);
break;
case FPU_DIV:
addbyte(0xf2); /*DIVSD XMM0, XMM1*/
addbyte(0x0f);
addbyte(0x5e);
addbyte(0xc1);
break;
case FPU_DIVR:
addbyte(0xf2); /*DIVSD XMM1, XMM0*/
addbyte(0x0f);
addbyte(0x5e);
addbyte(0xc8);
break;
case FPU_MUL:
addbyte(0xf2); /*MULSD XMM0, XMM1*/
addbyte(0x0f);
addbyte(0x59);
addbyte(0xc1);
break;
case FPU_SUB:
addbyte(0xf2); /*SUBSD XMM0, XMM1*/
addbyte(0x0f);
addbyte(0x5c);
addbyte(0xc1);
break;
case FPU_SUBR:
addbyte(0xf2); /*SUBSD XMM1, XMM0*/
addbyte(0x0f);
addbyte(0x5c);
addbyte(0xc8);
break;
}
if (op == FPU_DIVR || op == FPU_SUBR) {
addbyte(0x66); /*MOVQ ST[RAX*8], XMM1*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x4c);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
} else {
addbyte(0x66); /*MOVQ ST[RAX*8], XMM0*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
}
}
static __inline void
FP_OP_S(int op)
{
addbyte(0x66); /*MOVD XMM1, EAX*/
addbyte(0x0f);
addbyte(0x6e);
addbyte(0xc8);
addbyte(0xf3); /*CVTSS2SD XMM1, XMM1*/
addbyte(0x0f);
addbyte(0x5a);
addbyte(0xc9);
FP_OP_MEM(op);
}
static __inline void
FP_OP_D(int op)
{
addbyte(0x66); /*MOVQ XMM1, RAX*/
addbyte(0x48);
addbyte(0x0f);
addbyte(0x6e);
addbyte(0xc8);
if (((cpu_state.npxc >> 10) & 3) && op == FPU_ADD) {
addbyte(0x0f); /*STMXCSR [ESP+8]*/
addbyte(0xae);
addbyte(0x5c);
addbyte(0x24);
addbyte(0x08);
addbyte(0x8b); /*MOV EAX, [ESP+8]*/
addbyte(0x44);
addbyte(0x24);
addbyte(0x08);
addbyte(0x25); /*AND EAX, ~(3 << 13)*/
addlong(~(3 << 10));
addbyte(0x0d); /*OR EAX, (npxc & (3 << 10)) << 3*/
addlong((cpu_state.npxc & (3 << 10)) << 3);
addbyte(0x89); /*MOV [RSP+12], EAX*/
addbyte(0x44);
addbyte(0x24);
addbyte(0x0c);
addbyte(0x0f); /*LDMXCSR [RSP+12]*/
addbyte(0xae);
addbyte(0x54);
addbyte(0x24);
addbyte(0x0c);
}
FP_OP_MEM(op);
if (((cpu_state.npxc >> 10) & 3) && op == FPU_ADD) {
addbyte(0x0f); /*LDMXCSR [RSP+8]*/
addbyte(0xae);
addbyte(0x54);
addbyte(0x24);
addbyte(0x08);
}
}
static __inline void
FP_OP_IW(int op)
{
addbyte(0x0f); /*MOVSX EAX, AX*/
addbyte(0xbf);
addbyte(0xc0);
addbyte(0xf2); /*CVTSI2SD XMM1, EAX*/
addbyte(0x0f);
addbyte(0x2a);
addbyte(0xc8);
FP_OP_MEM(op);
}
static __inline void
FP_OP_IL(int op)
{
addbyte(0xf2); /*CVTSI2SD XMM1, EAX*/
addbyte(0x0f);
addbyte(0x2a);
addbyte(0xc8);
FP_OP_MEM(op);
}
static __inline void
FP_COMPARE_REG(int dst, int src)
{
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV EBX, EAX*/
addbyte(0xc3);
if (src || dst) {
addbyte(0x83); /*ADD EAX, 1*/
addbyte(0xc0);
addbyte(src ? src : dst);
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(7);
}
addbyte(0x8a); /*MOV CL, [npxs+1]*/
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0x80); /*AND CL, ~(C0|C2|C3)*/
addbyte(0xe1);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
if (src) {
addbyte(0xf3); /*MOVQ XMM0, ST[RBX*8]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x66); /*COMISD XMM0, ST[RAX*8]*/
addbyte(0x0f);
addbyte(0x2f);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
} else {
addbyte(0xf3); /*MOVQ XMM0, ST[RAX*8]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x66); /*COMISD XMM0, ST[RBX*8]*/
addbyte(0x0f);
addbyte(0x2f);
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
}
addbyte(0x9f); /*LAHF*/
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR CL, AH*/
addbyte(0xe1);
addbyte(0x88); /*MOV [npxs+1], CL*/
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
}
static __inline void
FP_COMPARE_MEM(void)
{
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x8a); /*MOV CL, [npxs+1]*/
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0xf3); /*MOVQ XMM0, ST[RAX*8]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x80); /*AND CL, ~(C0|C2|C3)*/
addbyte(0xe1);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
addbyte(0x66); /*COMISD XMM0, XMM1*/
addbyte(0x0f);
addbyte(0x2f);
addbyte(0xc1);
addbyte(0x9f); /*LAHF*/
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR CL, AH*/
addbyte(0xe1);
addbyte(0x88); /*MOV [npxs+1], CL*/
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
}
static __inline void
FP_COMPARE_S(void)
{
addbyte(0x66); /*MOVD XMM1, EAX*/
addbyte(0x0f);
addbyte(0x6e);
addbyte(0xc8);
addbyte(0xf3); /*CVTSS2SD XMM1, XMM1*/
addbyte(0x0f);
addbyte(0x5a);
addbyte(0xc9);
FP_COMPARE_MEM();
}
static __inline void
FP_COMPARE_D(void)
{
addbyte(0x66); /*MOVQ XMM1, RAX*/
addbyte(0x48);
addbyte(0x0f);
addbyte(0x6e);
addbyte(0xc8);
FP_COMPARE_MEM();
}
static __inline void
FP_COMPARE_IW(void)
{
addbyte(0x0f); /*MOVSX EAX, AX*/
addbyte(0xbf);
addbyte(0xc0);
addbyte(0xf2); /*CVTSI2SD XMM1, EAX*/
addbyte(0x0f);
addbyte(0x2a);
addbyte(0xc8);
FP_COMPARE_MEM();
}
static __inline void
FP_COMPARE_IL(void)
{
addbyte(0xf2); /*CVTSI2SD XMM1, EAX*/
addbyte(0x0f);
addbyte(0x2a);
addbyte(0xc8);
FP_COMPARE_MEM();
}
static __inline void
UPDATE_NPXC(UNUSED(int reg))
{
//
}
static __inline void
SET_BITS(uintptr_t addr, uint32_t val)
{
if (IS_32_ADDR(addr)) {
if (val & ~0xff) {
addbyte(0x81); /*OR [addr], val*/
addbyte(0x0c);
addbyte(0x25);
addlong(addr);
addlong(val);
} else {
addbyte(0x80); /*OR [addr], val*/
addbyte(0x0c);
addbyte(0x25);
addlong(addr);
addbyte(val);
}
} else {
addbyte(0x48); /*MOV RAX, &addr*/
addbyte(0xb8 | REG_EAX);
addquad(addr);
if (val & ~0xff) {
addbyte(0x81); /*OR [RAX], val*/
addbyte(0x08);
addlong(val);
} else {
addbyte(0x80); /*OR [RAX], val*/
addbyte(0x08);
addbyte(val);
}
}
}
static __inline void
CLEAR_BITS(uintptr_t addr, uint32_t val)
{
if (IS_32_ADDR(addr)) {
if (val & ~0xff) {
addbyte(0x81); /*AND [addr], val*/
addbyte(0x24);
addbyte(0x25);
addlong(addr);
addlong(~val);
} else {
addbyte(0x80); /*AND [addr], val*/
addbyte(0x24);
addbyte(0x25);
addlong(addr);
addbyte(~val);
}
} else {
addbyte(0x48); /*MOV RAX, &addr*/
addbyte(0xb8 | REG_EAX);
addquad(addr);
if (val & ~0xff) {
addbyte(0x81); /*AND [RAX], val*/
addbyte(0x20);
addlong(~val);
} else {
addbyte(0x80); /*AND [RAX], val*/
addbyte(0x20);
addbyte(~val);
}
}
}
#define LOAD_Q_REG_1 REG_EAX
#define LOAD_Q_REG_2 REG_EDX
static __inline void
MMX_ENTER(void)
{
if (codegen_mmx_entered)
return;
if (IS_32_ADDR(&cr0)) {
addbyte(0xf6); /*TEST cr0, 0xc*/
addbyte(0x04);
addbyte(0x25);
addlong((uintptr_t) &cr0);
addbyte(0x0c);
} else {
addbyte(0x48); /*MOV RAX, &cr0*/
addbyte(0xb8 | REG_EAX);
addquad((uint64_t) &cr0);
addbyte(0xf6); /*TEST [RAX], 0xc*/
addbyte(0 | (REG_EAX << 3));
addbyte(0x0c);
}
addbyte(0x74); /*JZ +*/
addbyte(7 + 5 + 12 + 5);
addbyte(0xC7); /*MOVL [oldpc],op_old_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(oldpc));
addlong(op_old_pc);
load_param_1_32(&codeblock[block_current], 7);
CALL_FUNC((uintptr_t) x86_int);
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
addbyte(0x31); /*XOR EAX, EAX*/
addbyte(0xc0);
addbyte(0xc6); /*MOV ISMMX, 1*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ismmx));
addbyte(1);
addbyte(0x89); /*MOV TOP, EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV tag, EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(0x89); /*MOV tag+4, EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[4]));
codegen_mmx_entered = 1;
}
extern int mmx_ebx_ecx_loaded;
static __inline int
LOAD_MMX_D(int guest_reg)
{
int host_reg = REG_EBX;
addbyte(0x8b); /*MOV EBX, reg*/
addbyte(0x44 | (host_reg << 3));
addbyte(0x25);
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].l[0]));
return host_reg;
}
static __inline void
LOAD_MMX_Q(int guest_reg, int *host_reg1, int *host_reg2)
{
int host_reg = REG_EBX;
if (host_reg & 8)
addbyte(0x4c);
else
addbyte(0x48);
addbyte(0x8b); /*MOV RBX, reg*/
addbyte(0x44 | ((host_reg & 7) << 3));
addbyte(0x25);
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].q));
*host_reg1 = host_reg;
}
static __inline int
LOAD_MMX_Q_MMX(int guest_reg)
{
int dst_reg = find_host_xmm_reg();
host_reg_xmm_mapping[dst_reg] = 100;
addbyte(0xf3); /*MOV XMMx, reg*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x44 | ((dst_reg & 7) << 3));
addbyte(0x25);
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].q));
return dst_reg;
}
static __inline int
LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
{
int dst_reg = find_host_xmm_reg();
host_reg_xmm_mapping[dst_reg] = 100;
addbyte(0x66); /*MOVQ host_reg, src_reg1*/
if (src_reg1 & 8)
addbyte(0x49);
else
addbyte(0x48);
addbyte(0x0f);
addbyte(0x6e);
addbyte(0xc0 | (dst_reg << 3) | (src_reg1 & 7));
return dst_reg;
}
static __inline void
STORE_MMX_LQ(int guest_reg, int host_reg1)
{
addbyte(0xC7); /*MOVL [reg],0*/
addbyte(0x44);
addbyte(0x25);
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].l[1]));
addlong(0);
if (host_reg1 & 8)
addbyte(0x44);
addbyte(0x89); /*MOVL [reg],host_reg*/
addbyte(0x44 | ((host_reg1 & 7) << 3));
addbyte(0x25);
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].l[0]));
}
static __inline void
STORE_MMX_Q(int guest_reg, int host_reg1, int host_reg2)
{
if (host_reg1 & 8)
addbyte(0x4c);
else
addbyte(0x48);
addbyte(0x89); /*MOV [reg],host_reg*/
addbyte(0x44 | ((host_reg1 & 7) << 3));
addbyte(0x25);
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].l[0]));
}
static __inline void
STORE_MMX_Q_MMX(int guest_reg, int host_reg)
{
addbyte(0x66); /*MOVQ [guest_reg],host_reg*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x44 | (host_reg << 3));
addbyte(0x25);
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].q));
}
#define MMX_x86_OP(name, opcode) \
static __inline void \
MMX_##name(int dst_reg, int src_reg) \
{ \
addbyte(0x66); /*op dst_reg, src_reg*/ \
addbyte(0x0f); \
addbyte(opcode); \
addbyte(0xc0 | (dst_reg << 3) | src_reg); \
}
MMX_x86_OP(AND, 0xdb)
MMX_x86_OP(ANDN, 0xdf)
MMX_x86_OP(OR, 0xeb)
MMX_x86_OP(XOR, 0xef)
MMX_x86_OP(ADDB, 0xfc)
MMX_x86_OP(ADDW, 0xfd)
MMX_x86_OP(ADDD, 0xfe)
MMX_x86_OP(ADDSB, 0xec)
MMX_x86_OP(ADDSW, 0xed)
MMX_x86_OP(ADDUSB, 0xdc)
MMX_x86_OP(ADDUSW, 0xdd)
MMX_x86_OP(SUBB, 0xf8)
MMX_x86_OP(SUBW, 0xf9)
MMX_x86_OP(SUBD, 0xfa)
MMX_x86_OP(SUBSB, 0xe8)
MMX_x86_OP(SUBSW, 0xe9)
MMX_x86_OP(SUBUSB, 0xd8)
MMX_x86_OP(SUBUSW, 0xd9)
MMX_x86_OP(PUNPCKLBW, 0x60);
MMX_x86_OP(PUNPCKLWD, 0x61);
MMX_x86_OP(PUNPCKLDQ, 0x62);
MMX_x86_OP(PCMPGTB, 0x64);
MMX_x86_OP(PCMPGTW, 0x65);
MMX_x86_OP(PCMPGTD, 0x66);
MMX_x86_OP(PCMPEQB, 0x74);
MMX_x86_OP(PCMPEQW, 0x75);
MMX_x86_OP(PCMPEQD, 0x76);
MMX_x86_OP(PSRLW, 0xd1);
MMX_x86_OP(PSRLD, 0xd2);
MMX_x86_OP(PSRLQ, 0xd3);
MMX_x86_OP(PSRAW, 0xe1);
MMX_x86_OP(PSRAD, 0xe2);
MMX_x86_OP(PSLLW, 0xf1);
MMX_x86_OP(PSLLD, 0xf2);
MMX_x86_OP(PSLLQ, 0xf3);
MMX_x86_OP(PMULLW, 0xd5);
MMX_x86_OP(PMULHW, 0xe5);
MMX_x86_OP(PMADDWD, 0xf5);
static __inline void
MMX_PACKSSWB(int dst_reg, int src_reg)
{
addbyte(0x66); /*PACKSSWB dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x63);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x08);
}
static __inline void
MMX_PACKUSWB(int dst_reg, int src_reg)
{
addbyte(0x66); /*PACKUSWB dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x67);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x08);
}
static __inline void
MMX_PACKSSDW(int dst_reg, int src_reg)
{
addbyte(0x66); /*PACKSSDW dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x6b);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x08);
}
static __inline void
MMX_PUNPCKHBW(int dst_reg, int src_reg)
{
addbyte(0x66); /*PUNPCKLBW dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x60);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x0e);
}
static __inline void
MMX_PUNPCKHWD(int dst_reg, int src_reg)
{
addbyte(0x66); /*PUNPCKLWD dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x61);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x0e);
}
static __inline void
MMX_PUNPCKHDQ(int dst_reg, int src_reg)
{
addbyte(0x66); /*PUNPCKLDQ dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x62);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x0e);
}
static __inline void
MMX_PSRLW_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRLW dst_reg, amount*/
addbyte(0x0f);
addbyte(0x71);
addbyte(0xc0 | dst_reg | 0x10);
addbyte(amount);
}
static __inline void
MMX_PSRAW_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRAW dst_reg, amount*/
addbyte(0x0f);
addbyte(0x71);
addbyte(0xc0 | dst_reg | 0x20);
addbyte(amount);
}
static __inline void
MMX_PSLLW_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSLLW dst_reg, amount*/
addbyte(0x0f);
addbyte(0x71);
addbyte(0xc0 | dst_reg | 0x30);
addbyte(amount);
}
static __inline void
MMX_PSRLD_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRLD dst_reg, amount*/
addbyte(0x0f);
addbyte(0x72);
addbyte(0xc0 | dst_reg | 0x10);
addbyte(amount);
}
static __inline void
MMX_PSRAD_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRAD dst_reg, amount*/
addbyte(0x0f);
addbyte(0x72);
addbyte(0xc0 | dst_reg | 0x20);
addbyte(amount);
}
static __inline void
MMX_PSLLD_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSLLD dst_reg, amount*/
addbyte(0x0f);
addbyte(0x72);
addbyte(0xc0 | dst_reg | 0x30);
addbyte(amount);
}
static __inline void
MMX_PSRLQ_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRLQ dst_reg, amount*/
addbyte(0x0f);
addbyte(0x73);
addbyte(0xc0 | dst_reg | 0x10);
addbyte(amount);
}
static __inline void
MMX_PSRAQ_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRAQ dst_reg, amount*/
addbyte(0x0f);
addbyte(0x73);
addbyte(0xc0 | dst_reg | 0x20);
addbyte(amount);
}
static __inline void
MMX_PSLLQ_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSLLQ dst_reg, amount*/
addbyte(0x0f);
addbyte(0x73);
addbyte(0xc0 | dst_reg | 0x30);
addbyte(amount);
}
static __inline void
SAVE_EA(void)
{
addbyte(0x89); /*MOV [ESP+0x24], EAX*/
addbyte(0x44);
addbyte(0x24);
addbyte(0x24);
}
static __inline void
LOAD_EA(void)
{
addbyte(0x8b); /*MOV EAX, [ESP+0x24]*/
addbyte(0x44);
addbyte(0x24);
addbyte(0x24);
}
#define MEM_CHECK_WRITE_B MEM_CHECK_WRITE
static __inline void
MEM_CHECK_WRITE(x86seg *seg)
{
uint8_t *jump1 = NULL;
uint8_t *jump2 = NULL;
uint8_t *jump3 = NULL;
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOV ESI, seg->base*/
addbyte(0x34);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &addr*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ESI, [RSI]*/
addbyte(0x36);
}
/*seg = ESI, addr = EAX*/
if (IS_32_ADDR(&cr0)) {
addbyte(0x83); /*CMP cr0, 0*/
addbyte(0x3c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &cr0);
addbyte(0);
} else {
addbyte(0x48); /*MOV RDI, &cr0*/
addbyte(0xbf);
addquad((uint64_t) &cr0);
addbyte(0x83); /*CMPL [RDI], 0*/
addbyte(0x3f);
addbyte(0);
}
addbyte(0x67); /*LEA EDI, [EAX+ESI]*/
addbyte(0x8d);
addbyte(0x3c);
addbyte(0x30);
addbyte(0x79); /*JNS +*/
jump1 = &codeblock[block_current].data[block_pos];
addbyte(0);
addbyte(0xc1); /*SHR EDI, 12*/
addbyte(0xef);
addbyte(12);
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xfe);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
jump3 = &codeblock[block_current].data[block_pos];
addbyte(0);
}
if (IS_32_ADDR(writelookup2)) {
addbyte(0x83); /*CMP writelookup2[RDI*8],-1*/
addbyte(0x3c);
addbyte(0xfd);
addlong((uint32_t) (uintptr_t) writelookup2);
addbyte(-1);
} else {
addbyte(0x48); /*MOV RCX, writelookup2*/
addbyte(0xb9);
addquad((uint64_t) writelookup2);
addbyte(0x83); /*CMP [RCX+RDI*8], -1*/
addbyte(0x3c);
addbyte(0xf9);
addbyte(-1);
}
addbyte(0x75); /*JNE +*/
jump2 = &codeblock[block_current].data[block_pos];
addbyte(0);
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
*jump3 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump3 - 1;
/*slowpath:*/
addbyte(0x67); /*LEA EDI, [EAX+ESI]*/
addbyte(0x8d);
addbyte(0x3c);
addbyte(0x30);
load_param_1_reg_32(REG_EDI);
load_param_2_32(&codeblock[block_current], 1);
call(&codeblock[block_current], (uintptr_t) mmutranslatereal32);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong((uintptr_t) &codeblock[block_current].data[BLOCK_EXIT_OFFSET] - ((uintptr_t) (&codeblock[block_current].data[block_pos]) + 4));
*jump1 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump1 - 1;
*jump2 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump2 - 1;
LOAD_EA();
}
static __inline void
MEM_CHECK_WRITE_W(x86seg *seg)
{
uint8_t *jump1 = NULL;
uint8_t *jump2 = NULL;
uint8_t *jump3 = NULL;
uint8_t *jump4 = NULL;
int jump_pos;
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOV ESI, seg->base*/
addbyte(0x34);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &addr*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ESI, [RSI]*/
addbyte(0x36);
}
/*seg = ESI, addr = EAX*/
if (IS_32_ADDR(&cr0)) {
addbyte(0x83); /*CMP cr0, 0*/
addbyte(0x3c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &cr0);
addbyte(0);
} else {
addbyte(0x48); /*MOV RDI, &cr0*/
addbyte(0xbf);
addquad((uint64_t) &cr0);
addbyte(0x83); /*CMPL [RDI], 0*/
addbyte(0x3f);
addbyte(0);
}
addbyte(0x67); /*LEA EDI, [EAX+ESI]*/
addbyte(0x8d);
addbyte(0x3c);
addbyte(0x30);
addbyte(0x79); /*JNS +*/
jump1 = &codeblock[block_current].data[block_pos];
addbyte(0);
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xfe);
addbyte(-1);
}
addbyte(0x8d); /*LEA ESI, 1[EDI]*/
addbyte(0x77);
addbyte(0x01);
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x74); /*JE slowpath*/
jump4 = &codeblock[block_current].data[block_pos];
addbyte(0);
}
addbyte(0x89); /*MOV EBX, EDI*/
addbyte(0xfb);
addbyte(0xc1); /*SHR EDI, 12*/
addbyte(0xef);
addbyte(12);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xee);
addbyte(12);
if (IS_32_ADDR(writelookup2)) {
addbyte(0x83); /*CMP writelookup2[RDI*8],-1*/
addbyte(0x3c);
addbyte(0xfd);
addlong((uint32_t) (uintptr_t) writelookup2);
addbyte(-1);
} else {
addbyte(0x48); /*MOV RAX, writelookup2*/
addbyte(0xb8);
addquad((uint64_t) writelookup2);
addbyte(0x83); /*CMP [RAX+RDI*8], -1*/
addbyte(0x3c);
addbyte(0xf8);
addbyte(-1);
}
addbyte(0x74); /*JE +*/
jump2 = &codeblock[block_current].data[block_pos];
addbyte(0);
if (IS_32_ADDR(writelookup2)) {
addbyte(0x83); /*CMP writelookup2[RSI*8],-1*/
addbyte(0x3c);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) writelookup2);
addbyte(-1);
} else {
addbyte(0x83); /*CMP [RAX+RSI*8], -1*/
addbyte(0x3c);
addbyte(0xf0);
addbyte(-1);
}
addbyte(0x75); /*JNE +*/
jump3 = &codeblock[block_current].data[block_pos];
addbyte(0);
/*slowpath:*/
*jump2 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump2 - 1;
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
*jump4 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump4 - 1;
jump_pos = block_pos;
load_param_1_reg_32(REG_EBX);
load_param_2_32(&codeblock[block_current], 1);
call(&codeblock[block_current], (uintptr_t) mmutranslatereal32);
addbyte(0x83); /*ADD EBX, 1*/
addbyte(0xc3);
addbyte(1);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong((uintptr_t) &codeblock[block_current].data[BLOCK_EXIT_OFFSET] - ((uintptr_t) (&codeblock[block_current].data[block_pos]) + 4));
/*If bits 0-11 of the address are now 0 then this crosses a page, so loop back*/
addbyte(0xf7); /*TEST $fff, EBX*/
addbyte(0xc3);
addlong(0xfff);
addbyte(0x74); /*JNE slowpath*/
addbyte(jump_pos - block_pos - 1);
*jump1 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump1 - 1;
*jump3 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump3 - 1;
LOAD_EA();
}
static __inline void
MEM_CHECK_WRITE_L(x86seg *seg)
{
uint8_t *jump1 = NULL;
uint8_t *jump2 = NULL;
uint8_t *jump3 = NULL;
uint8_t *jump4 = NULL;
int jump_pos;
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOV ESI, seg->base*/
addbyte(0x34);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &addr*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ESI, [RSI]*/
addbyte(0x36);
}
/*seg = ESI, addr = EAX*/
if (IS_32_ADDR(&cr0)) {
addbyte(0x83); /*CMP cr0, 0*/
addbyte(0x3c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &cr0);
addbyte(0);
} else {
addbyte(0x48); /*MOV RDI, &cr0*/
addbyte(0xbf);
addquad((uint64_t) &cr0);
addbyte(0x83); /*CMPL [RDI], 0*/
addbyte(0x3f);
addbyte(0);
}
addbyte(0x67); /*LEA EDI, [EAX+ESI]*/
addbyte(0x8d);
addbyte(0x3c);
addbyte(0x30);
addbyte(0x79); /*JNS +*/
jump1 = &codeblock[block_current].data[block_pos];
addbyte(0);
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xfe);
addbyte(-1);
}
addbyte(0x8d); /*LEA ESI, 3[EDI]*/
addbyte(0x77);
addbyte(0x03);
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x74); /*JE slowpath*/
jump4 = &codeblock[block_current].data[block_pos];
addbyte(0);
}
addbyte(0x89); /*MOV EBX, EDI*/
addbyte(0xfb);
addbyte(0xc1); /*SHR EDI, 12*/
addbyte(0xef);
addbyte(12);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xee);
addbyte(12);
if (IS_32_ADDR(writelookup2)) {
addbyte(0x83); /*CMP writelookup2[RDI*8],-1*/
addbyte(0x3c);
addbyte(0xfd);
addlong((uint32_t) (uintptr_t) writelookup2);
addbyte(-1);
} else {
addbyte(0x48); /*MOV RAX, writelookup2*/
addbyte(0xb8);
addquad((uint64_t) writelookup2);
addbyte(0x83); /*CMP [RAX+RDI*8], -1*/
addbyte(0x3c);
addbyte(0xf8);
addbyte(-1);
}
addbyte(0x74); /*JE slowpath*/
jump2 = &codeblock[block_current].data[block_pos];
addbyte(0);
if (IS_32_ADDR(writelookup2)) {
addbyte(0x83); /*CMP writelookup2[RSI*8],-1*/
addbyte(0x3c);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) writelookup2);
addbyte(-1);
} else {
addbyte(0x83); /*CMP [RAX+RSI*8], -1*/
addbyte(0x3c);
addbyte(0xf0);
addbyte(-1);
}
addbyte(0x75); /*JNE +*/
jump3 = &codeblock[block_current].data[block_pos];
addbyte(0);
/*slowpath:*/
*jump2 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump2 - 1;
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
*jump4 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump4 - 1;
jump_pos = block_pos;
load_param_1_reg_32(REG_EBX);
load_param_2_32(&codeblock[block_current], 1);
call(&codeblock[block_current], (uintptr_t) mmutranslatereal32);
addbyte(0x83); /*ADD EBX, 3*/
addbyte(0xc3);
addbyte(3);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong((uintptr_t) &codeblock[block_current].data[BLOCK_EXIT_OFFSET] - ((uintptr_t) (&codeblock[block_current].data[block_pos]) + 4));
/*If bits 0-11 of the address are now 0 then this crosses a page, so loop back*/
addbyte(0xf7); /*TEST $ffc, EBX*/
addbyte(0xc3);
addlong(0xffc);
addbyte(0x74); /*JE slowpath*/
addbyte(jump_pos - block_pos - 1);
*jump1 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump1 - 1;
*jump3 = (uintptr_t) &codeblock[block_current].data[block_pos] - (uintptr_t) jump3 - 1;
LOAD_EA();
}
static __inline int
MEM_LOAD_ADDR_EA_B_NO_ABRT(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ECX, ECX*/
addbyte(0xc9);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL ECX, seg->base*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ECX, [RSI]*/
addbyte(0x0e);
}
addbyte(0x67); /*LEA ESI, (EAX,ECX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x08);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
if (IS_32_ADDR(readlookup2)) {
addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) readlookup2);
} else {
addbyte(0x48); /*MOV RDX, readlookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) readlookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 2);
addbyte(0x8b); /*MOV AL,[RDI+RSI]*/
addbyte(0x04);
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xeb); /*JMP done*/
addbyte(2 + 2 + 12);
/*slowpath:*/
addbyte(0x01); /*ADD ECX,EAX*/
addbyte(0xc1);
load_param_1_reg_32(REG_ECX);
call_long((uintptr_t) readmembl);
addbyte(0x89); /*MOV ECX, EAX*/
addbyte(0xc1);
/*done:*/
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static __inline int
MEM_LOAD_ADDR_EA_W_NO_ABRT(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ECX, ECX*/
addbyte(0xc9);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL ECX, seg->base*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ECX, [RSI]*/
addbyte(0x0e);
}
addbyte(0x67); /*LEA ESI, (EAX,ECX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x08);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 1*/
addbyte(0xc7);
addlong(1);
if (IS_32_ADDR(readlookup2)) {
addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) readlookup2);
} else {
addbyte(0x48); /*MOV RDX, readlookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) readlookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 4 + 2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4 + 2);
addbyte(0x66); /*MOV AX,[RDI+RSI]*/
addbyte(0x8b);
addbyte(0x04);
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xeb); /*JMP done*/
addbyte(2 + 2 + 12);
/*slowpath:*/
addbyte(0x01); /*ADD ECX,EAX*/
addbyte(0xc1);
load_param_1_reg_32(REG_ECX);
call_long((uintptr_t) readmemwl);
addbyte(0x89); /*MOV ECX, EAX*/
addbyte(0xc1);
/*done:*/
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static __inline int
MEM_LOAD_ADDR_EA_L_NO_ABRT(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ECX, ECX*/
addbyte(0xc9);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL ECX, seg->base*/
addbyte(0x0c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV ECX, [RSI]*/
addbyte(0x0e);
}
addbyte(0x67); /*LEA ESI, (EAX,ECX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x08);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 3*/
addbyte(0xc7);
addlong(3);
if (IS_32_ADDR(readlookup2)) {
addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) readlookup2);
} else {
addbyte(0x48); /*MOV RDX, readlookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) readlookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + 3 + 2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3 + 2);
addbyte(0x8b); /*MOV EAX,[RDI+RSI]*/
addbyte(0x04);
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xeb); /*JMP done*/
addbyte(2 + 2 + 12);
/*slowpath:*/
addbyte(0x01); /*ADD ECX,EAX*/
addbyte(0xc1);
load_param_1_reg_32(REG_ECX);
call_long((uintptr_t) readmemll);
addbyte(0x89); /*MOV ECX, EAX*/
addbyte(0xc1);
/*done:*/
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static __inline void
MEM_STORE_ADDR_EA_B_NO_ABRT(x86seg *seg, int host_reg)
{
if (host_reg & 0x10) {
/*Handle high byte of register*/
if (host_reg & 8) {
addbyte(0x45); /*MOVL R8, host_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3));
} else {
addbyte(0x41); /*MOVL R8, host_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3));
}
addbyte(0x66); /*SHR R8, 8*/
addbyte(0x41);
addbyte(0xc1);
addbyte(0xe8);
addbyte(8);
host_reg = 8;
}
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR EBX, EBX*/
addbyte(0xdb);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL EBX, seg->base*/
addbyte(0x1c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV EBX, [RSI]*/
addbyte(0x1e);
}
addbyte(0x67); /*LEA ESI, (EAX,EBX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x18);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
if (IS_32_ADDR(writelookup2)) {
addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) writelookup2);
} else {
addbyte(0x48); /*MOV RDX, writelookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) writelookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(((host_reg & 8) ? 4 : 3) + 2);
if (host_reg & 8) {
addbyte(0x44); /*MOV [RDI+RSI],host_reg*/
addbyte(0x88);
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(REG_EDI | (REG_ESI << 3));
} else {
addbyte(0x88); /*MOV [RDI+RSI],host_reg*/
addbyte(0x04 | (host_reg << 3));
addbyte(REG_EDI | (REG_ESI << 3));
}
addbyte(0xeb); /*JMP done*/
if (host_reg & 8) {
addbyte(2 + 2 + 3 + 12);
} else {
addbyte(2 + 2 + 2 + 12);
}
/*slowpath:*/
load_param_2_reg_32(host_reg);
addbyte(0x01); /*ADD EBX,EAX*/
addbyte(0xc3);
load_param_1_reg_32(REG_EBX);
call_long((uintptr_t) writemembl);
/*done:*/
}
static __inline void
MEM_STORE_ADDR_EA_W_NO_ABRT(x86seg *seg, int host_reg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR EBX, EBX*/
addbyte(0xdb);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL EBX, seg->base*/
addbyte(0x1c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV EBX, [RSI]*/
addbyte(0x1e);
}
addbyte(0x67); /*LEA ESI, (EAX,EBX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x18);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 1*/
addbyte(0xc7);
addlong(1);
if (IS_32_ADDR(writelookup2)) {
addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) writelookup2);
} else {
addbyte(0x48); /*MOV RDX, writelookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) writelookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + ((host_reg & 8) ? 5 : 4) + 2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(((host_reg & 8) ? 5 : 4) + 2);
if (host_reg & 8) {
addbyte(0x66); /*MOV [RDI+RSI],host_reg*/
addbyte(0x44);
addbyte(0x89);
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(REG_EDI | (REG_ESI << 3));
} else {
addbyte(0x66); /*MOV [RDI+RSI],host_reg*/
addbyte(0x89);
addbyte(0x04 | (host_reg << 3));
addbyte(REG_EDI | (REG_ESI << 3));
}
addbyte(0xeb); /*JMP done*/
if (host_reg & 8) {
addbyte(2 + 2 + 3 + 12);
} else {
addbyte(2 + 2 + 2 + 12);
}
/*slowpath:*/
load_param_2_reg_32(host_reg);
addbyte(0x01); /*ADD EBX,EAX*/
addbyte(0xc3);
load_param_1_reg_32(REG_EBX);
call_long((uintptr_t) writememwl);
/*done:*/
}
static __inline void
MEM_STORE_ADDR_EA_L_NO_ABRT(x86seg *seg, int host_reg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR EBX, EBX*/
addbyte(0xdb);
} else if (IS_32_ADDR(&seg->base)) {
addbyte(0x8b); /*MOVL EBX, seg->base*/
addbyte(0x1c);
addbyte(0x25);
addlong((uint32_t) (uintptr_t) &seg->base);
} else {
addbyte(0x48); /*MOV RSI, &seg->base*/
addbyte(0xb8 | REG_ESI);
addquad((uint64_t) &seg->base);
addbyte(0x8b); /*MOV EBX, [RSI]*/
addbyte(0x1e);
}
addbyte(0x67); /*LEA ESI, (EAX,EBX)*/
addbyte(0x8d);
addbyte(0x34);
addbyte(0x18);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xf7);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 3*/
addbyte(0xc7);
addlong(3);
if (IS_32_ADDR(writelookup2)) {
addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
addbyte(0x48);
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf5);
addlong((uint32_t) (uintptr_t) writelookup2);
} else {
addbyte(0x48); /*MOV RDX, writelookup2*/
addbyte(0xb8 | REG_EDX);
addquad((uint64_t) writelookup2);
addbyte(0x48); /*MOV RSI, [RDX+RSI*8]*/
addbyte(0x8b);
addbyte(0x34);
addbyte(0xf2);
}
addbyte(0x75); /*JNE slowpath*/
addbyte(3 + 2 + ((host_reg & 8) ? 4 : 3) + 2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(((host_reg & 8) ? 4 : 3) + 2);
if (host_reg & 8) {
addbyte(0x44); /*MOV [RDI+RSI],host_reg*/
addbyte(0x89);
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(REG_EDI | (REG_ESI << 3));
} else {
addbyte(0x89); /*MOV [RDI+RSI],host_reg*/
addbyte(0x04 | (host_reg << 3));
addbyte(REG_EDI | (REG_ESI << 3));
}
addbyte(0xeb); /*JMP done*/
if (host_reg & 8) {
addbyte(2 + 2 + 3 + 12);
} else {
addbyte(2 + 2 + 2 + 12);
}
/*slowpath:*/
load_param_2_reg_32(host_reg);
addbyte(0x01); /*ADD EBX,EAX*/
addbyte(0xc3);
load_param_1_reg_32(REG_EBX);
call_long((uintptr_t) writememll);
/*done:*/
}
static __inline void
LOAD_SEG(int host_reg, void *seg)
{
load_param_2_64(&codeblock[block_current], (uint64_t) seg);
load_param_1_reg_32(host_reg);
CALL_FUNC((uintptr_t) loadseg);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE end*/
addbyte(0x85);
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
``` | /content/code_sandbox/src/codegen/codegen_ops_x86-64.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 59,822 |
```objective-c
static uint32_t
ropMOVQ_q_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg1;
int host_reg2 = 0;
MMX_ENTER();
LOAD_MMX_Q((fetchdat >> 3) & 7, &host_reg1, &host_reg2);
if ((fetchdat & 0xc0) == 0xc0) {
STORE_MMX_Q(fetchdat & 7, host_reg1, host_reg2);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 7);
MEM_STORE_ADDR_EA_Q(target_seg, host_reg1, host_reg2);
}
return op_pc + 1;
}
static uint32_t
ropMOVQ_mm_q(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
MMX_ENTER();
if ((fetchdat & 0xc0) == 0xc0) {
int host_reg1;
int host_reg2;
LOAD_MMX_Q(fetchdat & 7, &host_reg1, &host_reg2);
STORE_MMX_Q((fetchdat >> 3) & 7, host_reg1, host_reg2);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_Q(target_seg);
STORE_MMX_Q((fetchdat >> 3) & 7, LOAD_Q_REG_1, LOAD_Q_REG_2);
}
return op_pc + 1;
}
static uint32_t
ropMOVD_l_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
MMX_ENTER();
host_reg = LOAD_MMX_D((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0) {
STORE_REG_TARGET_L_RELEASE(host_reg, fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 3);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
}
return op_pc + 1;
}
static uint32_t
ropMOVD_mm_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
MMX_ENTER();
if ((fetchdat & 0xc0) == 0xc0) {
int host_reg = LOAD_REG_L(fetchdat & 7);
STORE_MMX_LQ((fetchdat >> 3) & 7, host_reg);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
STORE_MMX_LQ((fetchdat >> 3) & 7, 0);
}
return op_pc + 1;
}
#define MMX_OP(name, func) \
static uint32_t \
name(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg1; \
int src_reg2; \
int xmm_src; \
int xmm_dst; \
\
MMX_ENTER(); \
\
if ((fetchdat & 0xc0) == 0xc0) { \
xmm_src = LOAD_MMX_Q_MMX(fetchdat & 7); \
} else { \
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
\
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
\
CHECK_SEG_READ(target_seg); \
\
MEM_LOAD_ADDR_EA_Q(target_seg); \
src_reg1 = LOAD_Q_REG_1; \
src_reg2 = LOAD_Q_REG_2; \
xmm_src = LOAD_INT_TO_MMX(src_reg1, src_reg2); \
} \
xmm_dst = LOAD_MMX_Q_MMX((fetchdat >> 3) & 7); \
func(xmm_dst, xmm_src); \
STORE_MMX_Q_MMX((fetchdat >> 3) & 7, xmm_dst); \
\
return op_pc + 1; \
}
MMX_OP(ropPAND, MMX_AND)
MMX_OP(ropPANDN, MMX_ANDN)
MMX_OP(ropPOR, MMX_OR)
MMX_OP(ropPXOR, MMX_XOR)
MMX_OP(ropPADDB, MMX_ADDB)
MMX_OP(ropPADDW, MMX_ADDW)
MMX_OP(ropPADDD, MMX_ADDD)
MMX_OP(ropPADDSB, MMX_ADDSB)
MMX_OP(ropPADDSW, MMX_ADDSW)
MMX_OP(ropPADDUSB, MMX_ADDUSB)
MMX_OP(ropPADDUSW, MMX_ADDUSW)
MMX_OP(ropPSUBB, MMX_SUBB)
MMX_OP(ropPSUBW, MMX_SUBW)
MMX_OP(ropPSUBD, MMX_SUBD)
MMX_OP(ropPSUBSB, MMX_SUBSB)
MMX_OP(ropPSUBSW, MMX_SUBSW)
MMX_OP(ropPSUBUSB, MMX_SUBUSB)
MMX_OP(ropPSUBUSW, MMX_SUBUSW)
MMX_OP(ropPUNPCKLBW, MMX_PUNPCKLBW);
MMX_OP(ropPUNPCKLWD, MMX_PUNPCKLWD);
MMX_OP(ropPUNPCKLDQ, MMX_PUNPCKLDQ);
MMX_OP(ropPACKSSWB, MMX_PACKSSWB);
MMX_OP(ropPCMPGTB, MMX_PCMPGTB);
MMX_OP(ropPCMPGTW, MMX_PCMPGTW);
MMX_OP(ropPCMPGTD, MMX_PCMPGTD);
MMX_OP(ropPACKUSWB, MMX_PACKUSWB);
MMX_OP(ropPUNPCKHBW, MMX_PUNPCKHBW);
MMX_OP(ropPUNPCKHWD, MMX_PUNPCKHWD);
MMX_OP(ropPUNPCKHDQ, MMX_PUNPCKHDQ);
MMX_OP(ropPACKSSDW, MMX_PACKSSDW);
MMX_OP(ropPCMPEQB, MMX_PCMPEQB);
MMX_OP(ropPCMPEQW, MMX_PCMPEQW);
MMX_OP(ropPCMPEQD, MMX_PCMPEQD);
MMX_OP(ropPSRLW, MMX_PSRLW)
MMX_OP(ropPSRLD, MMX_PSRLD)
MMX_OP(ropPSRLQ, MMX_PSRLQ)
MMX_OP(ropPSRAW, MMX_PSRAW)
MMX_OP(ropPSRAD, MMX_PSRAD)
MMX_OP(ropPSLLW, MMX_PSLLW)
MMX_OP(ropPSLLD, MMX_PSLLD)
MMX_OP(ropPSLLQ, MMX_PSLLQ)
MMX_OP(ropPMULLW, MMX_PMULLW);
MMX_OP(ropPMULHW, MMX_PMULHW);
MMX_OP(ropPMADDWD, MMX_PMADDWD);
static uint32_t
ropPSxxW_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int xmm_dst;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
if ((fetchdat & 0x08) || !(fetchdat & 0x30))
return 0;
MMX_ENTER();
xmm_dst = LOAD_MMX_Q_MMX(fetchdat & 7);
switch (fetchdat & 0x38) {
case 0x10: /*PSRLW*/
MMX_PSRLW_imm(xmm_dst, (fetchdat >> 8) & 0xff);
break;
case 0x20: /*PSRAW*/
MMX_PSRAW_imm(xmm_dst, (fetchdat >> 8) & 0xff);
break;
case 0x30: /*PSLLW*/
MMX_PSLLW_imm(xmm_dst, (fetchdat >> 8) & 0xff);
break;
}
STORE_MMX_Q_MMX(fetchdat & 7, xmm_dst);
return op_pc + 2;
}
static uint32_t
ropPSxxD_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int xmm_dst;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
if ((fetchdat & 0x08) || !(fetchdat & 0x30))
return 0;
MMX_ENTER();
xmm_dst = LOAD_MMX_Q_MMX(fetchdat & 7);
switch (fetchdat & 0x38) {
case 0x10: /*PSRLD*/
MMX_PSRLD_imm(xmm_dst, (fetchdat >> 8) & 0xff);
break;
case 0x20: /*PSRAD*/
MMX_PSRAD_imm(xmm_dst, (fetchdat >> 8) & 0xff);
break;
case 0x30: /*PSLLD*/
MMX_PSLLD_imm(xmm_dst, (fetchdat >> 8) & 0xff);
break;
}
STORE_MMX_Q_MMX(fetchdat & 7, xmm_dst);
return op_pc + 2;
}
static uint32_t
ropPSxxQ_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int xmm_dst;
if ((fetchdat & 0xc0) != 0xc0)
return 0;
if ((fetchdat & 0x08) || !(fetchdat & 0x30))
return 0;
MMX_ENTER();
xmm_dst = LOAD_MMX_Q_MMX(fetchdat & 7);
switch (fetchdat & 0x38) {
case 0x10: /*PSRLQ*/
MMX_PSRLQ_imm(xmm_dst, (fetchdat >> 8) & 0xff);
break;
case 0x20: /*PSRAQ*/
MMX_PSRAQ_imm(xmm_dst, (fetchdat >> 8) & 0xff);
break;
case 0x30: /*PSLLQ*/
MMX_PSLLQ_imm(xmm_dst, (fetchdat >> 8) & 0xff);
break;
}
STORE_MMX_Q_MMX(fetchdat & 7, xmm_dst);
return op_pc + 2;
}
static uint32_t
ropEMMS(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
codegen_mmx_entered = 0;
return 0;
}
``` | /content/code_sandbox/src/codegen/codegen_ops_mmx.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,742 |
```objective-c
#define BLOCK_SIZE 0x4000
#define BLOCK_MASK 0x3fff
#define BLOCK_START 0
#define HASH_SIZE 0x20000
#define HASH_MASK 0x1ffff
#define HASH(l) ((l) &0x1ffff)
#define BLOCK_EXIT_OFFSET 0x7f0
#ifdef OLD_GPF
# define BLOCK_GPF_OFFSET (BLOCK_EXIT_OFFSET - 20)
#else
# define BLOCK_GPF_OFFSET (BLOCK_EXIT_OFFSET - 14)
#endif
#define BLOCK_MAX 1720
enum {
OP_RET = 0xc3
};
#define NR_HOST_REGS 4
extern int host_reg_mapping[NR_HOST_REGS];
#define NR_HOST_XMM_REGS 8
extern int host_reg_xmm_mapping[NR_HOST_XMM_REGS];
extern uint32_t mem_load_addr_ea_b;
extern uint32_t mem_load_addr_ea_w;
extern uint32_t mem_load_addr_ea_l;
extern uint32_t mem_load_addr_ea_q;
extern uint32_t mem_store_addr_ea_b;
extern uint32_t mem_store_addr_ea_w;
extern uint32_t mem_store_addr_ea_l;
extern uint32_t mem_store_addr_ea_q;
extern uint32_t mem_load_addr_ea_b_no_abrt;
extern uint32_t mem_store_addr_ea_b_no_abrt;
extern uint32_t mem_load_addr_ea_w_no_abrt;
extern uint32_t mem_store_addr_ea_w_no_abrt;
extern uint32_t mem_load_addr_ea_l_no_abrt;
extern uint32_t mem_store_addr_ea_l_no_abrt;
extern uint32_t mem_check_write;
extern uint32_t mem_check_write_w;
extern uint32_t mem_check_write_l;
``` | /content/code_sandbox/src/codegen/codegen_x86.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 369 |
```objective-c
static uint32_t
ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
CALL_FUNC((uintptr_t) flags_rebuild_c);
host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
#if 0
ADD_HOST_REG_IMM_W(host_reg, 1);
#endif
INC_HOST_REG_W(host_reg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc;
}
static uint32_t
ropINC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
CALL_FUNC((uintptr_t) flags_rebuild_c);
host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
#if 0
ADD_HOST_REG_IMM(host_reg, 1);
#endif
INC_HOST_REG(host_reg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_INC32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc;
}
static uint32_t
ropDEC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
CALL_FUNC((uintptr_t) flags_rebuild_c);
host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
#if 0
SUB_HOST_REG_IMM_W(host_reg, 1);
#endif
DEC_HOST_REG_W(host_reg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_DEC16);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc;
}
static uint32_t
ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
CALL_FUNC((uintptr_t) flags_rebuild_c);
host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
#if 0
SUB_HOST_REG_IMM(host_reg, 1);
#endif
DEC_HOST_REG(host_reg);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_DEC32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc;
}
#define ROP_ARITH_RMW(name, op, writeback) \
static uint32_t \
rop##name##_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
dst_reg = LOAD_REG_B(fetchdat & 7); \
} else { \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_##op##8); \
src_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op2, src_reg); \
op##_HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) { \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_B_RELEASE(dst_reg); \
else { \
LOAD_EA(); \
MEM_STORE_ADDR_EA_B_NO_ABRT(target_seg, dst_reg); \
} \
} else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
codegen_flags_changed = 1; \
return op_pc + 1; \
} \
static uint32_t \
rop##name##_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
dst_reg = LOAD_REG_W(fetchdat & 7); \
} else { \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE_W(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_##op##16); \
src_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op2, src_reg); \
op##_HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) { \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_W_RELEASE(dst_reg); \
else { \
LOAD_EA(); \
MEM_STORE_ADDR_EA_W_NO_ABRT(target_seg, dst_reg); \
} \
} else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
codegen_flags_changed = 1; \
return op_pc + 1; \
} \
static uint32_t \
rop##name##_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
dst_reg = LOAD_REG_L(fetchdat & 7); \
} else { \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE_L(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_##op##32); \
src_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op2, src_reg); \
op##_HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) { \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_L_RELEASE(dst_reg); \
else { \
LOAD_EA(); \
MEM_STORE_ADDR_EA_L_NO_ABRT(target_seg, dst_reg); \
} \
} else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
codegen_flags_changed = 1; \
return op_pc + 1; \
}
#define ROP_ARITH_RM(name, op, writeback) \
static uint32_t \
rop##name##_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
src_reg = LOAD_REG_B(fetchdat & 7); \
} else { \
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
MEM_LOAD_ADDR_EA_B(target_seg); \
src_reg = 0; \
} \
\
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_##op##8); \
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op2, src_reg); \
op##_HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) \
STORE_REG_B_RELEASE(dst_reg); \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
codegen_flags_changed = 1; \
return op_pc + 1; \
} \
static uint32_t \
rop##name##_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
src_reg = LOAD_REG_W(fetchdat & 7); \
} else { \
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
MEM_LOAD_ADDR_EA_W(target_seg); \
src_reg = 0; \
} \
\
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_##op##16); \
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op2, src_reg); \
op##_HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) \
STORE_REG_W_RELEASE(dst_reg); \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
codegen_flags_changed = 1; \
return op_pc + 1; \
} \
static uint32_t \
rop##name##_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg; \
int dst_reg; \
\
if ((fetchdat & 0xc0) == 0xc0) { \
src_reg = LOAD_REG_L(fetchdat & 7); \
} else { \
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
MEM_LOAD_ADDR_EA_L(target_seg); \
src_reg = 0; \
} \
\
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_##op##32); \
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op2, src_reg); \
op##_HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, dst_reg); \
if (writeback) \
STORE_REG_L_RELEASE(dst_reg); \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
codegen_flags_changed = 1; \
return op_pc + 1; \
}
ROP_ARITH_RMW(ADD, ADD, 1)
ROP_ARITH_RMW(SUB, SUB, 1)
ROP_ARITH_RM(ADD, ADD, 1)
ROP_ARITH_RM(SUB, SUB, 1)
static uint32_t
ropCMP_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
if ((fetchdat & 0xc0) == 0xc0) {
src_reg = LOAD_REG_B(fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_B(target_seg);
src_reg = 0;
}
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_B(dst_reg, src_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
ropCMP_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
if ((fetchdat & 0xc0) == 0xc0) {
src_reg = LOAD_REG_W(fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_W(target_seg);
src_reg = 0;
}
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_W(dst_reg, src_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
ropCMP_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
if ((fetchdat & 0xc0) == 0xc0) {
src_reg = LOAD_REG_L(fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_L(target_seg);
src_reg = 0;
}
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_L(dst_reg, src_reg);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
ropCMP_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
if ((fetchdat & 0xc0) == 0xc0) {
dst_reg = LOAD_REG_B(fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_B(target_seg);
dst_reg = 0;
}
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB8);
src_reg = LOAD_REG_B((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_B(dst_reg, src_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
ropCMP_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
if ((fetchdat & 0xc0) == 0xc0) {
dst_reg = LOAD_REG_W(fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_W(target_seg);
dst_reg = 0;
}
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB16);
src_reg = LOAD_REG_W((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_W(dst_reg, src_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
ropCMP_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int src_reg;
int dst_reg;
if ((fetchdat & 0xc0) == 0xc0) {
dst_reg = LOAD_REG_L(fetchdat & 7);
} else {
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
MEM_LOAD_ADDR_EA_L(target_seg);
dst_reg = 0;
}
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB32);
src_reg = LOAD_REG_L((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_L(dst_reg, src_reg);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
ropADD_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ADD8);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
ropADD_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ADD16);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
static uint32_t
ropADD_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc);
ADD_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ADD32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 4;
}
static uint32_t
ropCMP_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
ropCMP_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
static uint32_t
ropCMP_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc);
host_reg = CMP_HOST_REG_IMM_L(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 4;
}
static uint32_t
ropSUB_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
ropSUB_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
static uint32_t
ropSUB_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc);
SUB_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 4;
}
static uint32_t
rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0) {
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x38) == 0x38) {
MEM_LOAD_ADDR_EA_B(target_seg);
host_reg = 0;
} else {
SAVE_EA();
MEM_CHECK_WRITE(target_seg);
host_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg);
}
imm = fastreadb(cs + op_pc + 1);
} else {
host_reg = LOAD_REG_B(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
}
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ADD8);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN8);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffffff00);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN8);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB8);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN8);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB8);
break;
}
STORE_HOST_REG_ADDR_BL((uintptr_t) &cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38) {
if ((fetchdat & 0xc0) != 0xc0) {
LOAD_EA();
MEM_STORE_ADDR_EA_B_NO_ABRT(target_seg, host_reg);
} else {
STORE_REG_B_RELEASE(host_reg);
}
} else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
static uint32_t
rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0) {
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x38) == 0x38) {
MEM_LOAD_ADDR_EA_W(target_seg);
host_reg = 0;
} else {
SAVE_EA();
MEM_CHECK_WRITE_W(target_seg);
host_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg);
}
imm = fastreadw(cs + op_pc + 1);
} else {
host_reg = LOAD_REG_W(fetchdat & 7);
imm = (fetchdat >> 8) & 0xffff;
}
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ADD16);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffff0000);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB16);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB16);
break;
}
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38) {
if ((fetchdat & 0xc0) != 0xc0) {
LOAD_EA();
MEM_STORE_ADDR_EA_W_NO_ABRT(target_seg, host_reg);
} else {
STORE_REG_W_RELEASE(host_reg);
}
} else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 3;
}
static uint32_t
rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0) {
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x38) == 0x38) {
MEM_LOAD_ADDR_EA_L(target_seg);
host_reg = 0;
} else {
SAVE_EA();
MEM_CHECK_WRITE_L(target_seg);
host_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg);
}
} else {
host_reg = LOAD_REG_L(fetchdat & 7);
}
imm = fastreadl(cs + op_pc + 1);
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ADD32);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB32);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_L(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB32);
break;
}
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38) {
if ((fetchdat & 0xc0) != 0xc0) {
LOAD_EA();
MEM_STORE_ADDR_EA_L_NO_ABRT(target_seg, host_reg);
} else {
STORE_REG_L_RELEASE(host_reg);
}
} else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 5;
}
static uint32_t
rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0) {
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x38) == 0x38) {
MEM_LOAD_ADDR_EA_W(target_seg);
host_reg = 0;
} else {
SAVE_EA();
MEM_CHECK_WRITE_W(target_seg);
host_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg);
}
imm = fastreadb(cs + op_pc + 1);
} else {
host_reg = LOAD_REG_W(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
}
if (imm & 0x80)
imm |= 0xff80;
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ADD16);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffff0000);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB16);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB16);
break;
}
STORE_HOST_REG_ADDR_WL((uintptr_t) &cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38) {
if ((fetchdat & 0xc0) != 0xc0) {
LOAD_EA();
MEM_STORE_ADDR_EA_W_NO_ABRT(target_seg, host_reg);
} else {
STORE_REG_W_RELEASE(host_reg);
}
} else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
static uint32_t
rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0) {
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x38) == 0x38) {
MEM_LOAD_ADDR_EA_L(target_seg);
host_reg = 0;
} else {
SAVE_EA();
MEM_CHECK_WRITE_L(target_seg);
host_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg);
}
imm = fastreadb(cs + op_pc + 1);
} else {
host_reg = LOAD_REG_L(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
}
if (imm & 0x80)
imm |= 0xffffff80;
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ADD32);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB32);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_L(host_reg, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.flags_op, FLAGS_SUB32);
break;
}
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38) {
if ((fetchdat & 0xc0) != 0xc0) {
LOAD_EA();
MEM_STORE_ADDR_EA_L_NO_ABRT(target_seg, host_reg);
} else {
STORE_REG_L_RELEASE(host_reg);
}
} else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
``` | /content/code_sandbox/src/codegen/codegen_ops_arith.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,663 |
```objective-c
/*Register allocation :
EBX, ECX, EDX - emulated registers
EAX - work register, EA storage
ESI, EDI - work registers
EBP - points at emulated register array
*/
#define HOST_REG_START 1
#define HOST_REG_END 4
#define HOST_REG_XMM_START 0
#define HOST_REG_XMM_END 7
static __inline int
find_host_reg(void)
{
int c;
for (c = HOST_REG_START; c < HOST_REG_END; c++) {
if (host_reg_mapping[c] == -1)
break;
}
if (c == NR_HOST_REGS)
fatal("Out of host regs!\n");
return c;
}
static __inline int
find_host_xmm_reg(void)
{
int c;
for (c = HOST_REG_XMM_START; c < HOST_REG_XMM_END; c++) {
if (host_reg_xmm_mapping[c] == -1)
break;
}
if (c == HOST_REG_XMM_END)
fatal("Out of host XMM regs!\n");
return c;
}
#if 0
static __inline void STORE_IMM_ADDR_B(uintptr_t addr, uint8_t val)
{
addbyte(0xC6); /*MOVB [addr],val*/
addbyte(0x05);
addlong(addr);
addbyte(val);
}
static __inline void STORE_IMM_ADDR_W(uintptr_t addr, uint16_t val)
{
addbyte(0x66); /*MOVW [addr],val*/
addbyte(0xC7);
addbyte(0x05);
addlong(addr);
addword(val);
}
#endif
static __inline void
STORE_IMM_ADDR_L(uintptr_t addr, uint32_t val)
{
if (addr >= (uintptr_t) &cpu_state && addr < ((uintptr_t) &cpu_state) + 0x100) {
addbyte(0xC7); /*MOVL [addr],val*/
addbyte(0x45);
addbyte(addr - (uint32_t) &cpu_state - 128);
addlong(val);
} else {
addbyte(0xC7); /*MOVL [addr],val*/
addbyte(0x05);
addlong(addr);
addlong(val);
}
}
static __inline void
STORE_IMM_REG_B(int reg, uint8_t val)
{
addbyte(0xC6); /*MOVB [addr],val*/
addbyte(0x45);
if (reg & 4)
addbyte((uint8_t) cpu_state_offset(regs[reg & 3].b.h));
else
addbyte((uint8_t) cpu_state_offset(regs[reg & 3].b.l));
addbyte(val);
}
static __inline void
STORE_IMM_REG_W(int reg, uint16_t val)
{
addbyte(0x66); /*MOVW [addr],val*/
addbyte(0xC7);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[reg & 7].w));
addword(val);
}
static __inline void
STORE_IMM_REG_L(int reg, uint32_t val)
{
addbyte(0xC7); /*MOVL [addr],val*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[reg & 7].l));
addlong(val);
}
static __inline int
LOAD_REG_B(int reg)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = reg;
addbyte(0x0f); /*MOVZX B[reg],host_reg*/
addbyte(0xb6);
addbyte(0x45 | (host_reg << 3));
if (reg & 4)
addbyte((uint8_t) cpu_state_offset(regs[reg & 3].b.h));
else
addbyte((uint8_t) cpu_state_offset(regs[reg & 3].b.l));
return host_reg;
}
static __inline int
LOAD_REG_W(int reg)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = reg;
addbyte(0x0f); /*MOVZX W[reg],host_reg*/
addbyte(0xb7);
addbyte(0x45 | (host_reg << 3));
addbyte((uint8_t) cpu_state_offset(regs[reg & 7].w));
return host_reg;
}
static __inline int
LOAD_REG_L(int reg)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = reg;
addbyte(0x8b); /*MOVL host_reg,[reg]*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint8_t) cpu_state_offset(regs[reg & 7].l));
return host_reg;
}
static __inline int
LOAD_VAR_W(uintptr_t addr)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = 0;
addbyte(0x66); /*MOVL host_reg,[reg]*/
addbyte(0x8b);
addbyte(0x05 | (host_reg << 3));
addlong((uint32_t) addr);
return host_reg;
}
static __inline int
LOAD_VAR_WL(uintptr_t addr)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = 0;
addbyte(0x0f); /*MOVZX host_reg, [addr]*/
addbyte(0xb7);
addbyte(0x05 | (host_reg << 3));
addlong((uint32_t) addr);
return host_reg;
}
static __inline int
LOAD_VAR_L(uintptr_t addr)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = 0;
addbyte(0x8b); /*MOVL host_reg,[reg]*/
addbyte(0x05 | (host_reg << 3));
addlong((uint32_t) addr);
return host_reg;
}
static __inline int
LOAD_REG_IMM(uint32_t imm)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = 0;
addbyte(0xc7); /*MOVL host_reg, imm*/
addbyte(0xc0 | host_reg);
addlong(imm);
return host_reg;
}
static __inline int
LOAD_HOST_REG(int host_reg)
{
int new_host_reg = find_host_reg();
host_reg_mapping[new_host_reg] = 0;
addbyte(0x89); /*MOV new_host_reg, host_reg*/
addbyte(0xc0 | (host_reg << 3) | new_host_reg);
return new_host_reg;
}
static __inline void
STORE_REG_B_RELEASE(int host_reg)
{
addbyte(0x88); /*MOVB [reg],host_reg*/
addbyte(0x45 | (host_reg << 3));
if (host_reg_mapping[host_reg] & 4)
addbyte((uint8_t) cpu_state_offset(regs[host_reg_mapping[host_reg] & 3].b.h));
else
addbyte((uint8_t) cpu_state_offset(regs[host_reg_mapping[host_reg] & 3].b.l));
host_reg_mapping[host_reg] = -1;
}
static __inline void
STORE_REG_W_RELEASE(int host_reg)
{
addbyte(0x66); /*MOVW [reg],host_reg*/
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte((uint8_t) cpu_state_offset(regs[host_reg_mapping[host_reg]].w));
host_reg_mapping[host_reg] = -1;
}
static __inline void
STORE_REG_L_RELEASE(int host_reg)
{
addbyte(0x89); /*MOVL [reg],host_reg*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint8_t) cpu_state_offset(regs[host_reg_mapping[host_reg]].l));
host_reg_mapping[host_reg] = -1;
}
static __inline void
STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
{
addbyte(0x88); /*MOVB [guest_reg],host_reg*/
addbyte(0x45 | (host_reg << 3));
if (guest_reg & 4)
addbyte((uint8_t) cpu_state_offset(regs[guest_reg & 3].b.h));
else
addbyte((uint8_t) cpu_state_offset(regs[guest_reg & 3].b.l));
host_reg_mapping[host_reg] = -1;
}
static __inline void
STORE_REG_TARGET_W_RELEASE(int host_reg, int guest_reg)
{
addbyte(0x66); /*MOVW [guest_reg],host_reg*/
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte((uint8_t) cpu_state_offset(regs[guest_reg & 7].w));
host_reg_mapping[host_reg] = -1;
}
static __inline void
STORE_REG_TARGET_L_RELEASE(int host_reg, int guest_reg)
{
addbyte(0x89); /*MOVL [guest_reg],host_reg*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint8_t) cpu_state_offset(regs[guest_reg & 7].l));
host_reg_mapping[host_reg] = -1;
}
static __inline void
RELEASE_REG(int host_reg)
{
host_reg_mapping[host_reg] = -1;
}
static __inline void
STORE_HOST_REG_ADDR_W(uintptr_t addr, int host_reg)
{
if (addr >= (uintptr_t) &cpu_state && addr < ((uintptr_t) &cpu_state) + 0x100) {
addbyte(0x66); /*MOVW [addr],host_reg*/
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t) addr - (uint32_t) &cpu_state - 128);
} else {
addbyte(0x66); /*MOVL [reg],host_reg*/
addbyte(0x89);
addbyte(0x05 | (host_reg << 3));
addlong(addr);
}
}
static __inline void
STORE_HOST_REG_ADDR(uintptr_t addr, int host_reg)
{
if (addr >= (uintptr_t) &cpu_state && addr < ((uintptr_t) &cpu_state) + 0x100) {
addbyte(0x89); /*MOVL [addr],host_reg*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t) addr - (uint32_t) &cpu_state - 128);
} else {
addbyte(0x89); /*MOVL [reg],host_reg*/
addbyte(0x05 | (host_reg << 3));
addlong(addr);
}
}
#define STORE_HOST_REG_ADDR_BL STORE_HOST_REG_ADDR
#define STORE_HOST_REG_ADDR_WL STORE_HOST_REG_ADDR
static __inline void
ADD_HOST_REG_B(int dst_reg, int src_reg)
{
addbyte(0x00); /*ADDB dst_reg, src_reg*/
addbyte(0xc0 | dst_reg | (src_reg << 3));
}
static __inline void
ADD_HOST_REG_W(int dst_reg, int src_reg)
{
addbyte(0x66); /*ADDW dst_reg, src_reg*/
addbyte(0x01);
addbyte(0xc0 | dst_reg | (src_reg << 3));
}
static __inline void
ADD_HOST_REG_L(int dst_reg, int src_reg)
{
addbyte(0x01); /*ADDL dst_reg, src_reg*/
addbyte(0xc0 | dst_reg | (src_reg << 3));
}
static __inline void
ADD_HOST_REG_IMM_B(int host_reg, uint8_t imm)
{
addbyte(0x80); /*ADDB host_reg, imm*/
addbyte(0xC0 | host_reg);
addbyte(imm);
}
static __inline void
ADD_HOST_REG_IMM_W(int host_reg, uint16_t imm)
{
if (imm < 0x80 || imm >= 0xff80) {
addbyte(0x66); /*ADDW host_reg, imm*/
addbyte(0x83);
addbyte(0xC0 | host_reg);
addbyte(imm & 0xff);
} else {
addbyte(0x66); /*ADDW host_reg, imm*/
addbyte(0x81);
addbyte(0xC0 | host_reg);
addword(imm);
}
}
static __inline void
ADD_HOST_REG_IMM(int host_reg, uint32_t imm)
{
if (imm < 0x80 || imm >= 0xffffff80) {
addbyte(0x83); /*ADDL host_reg, imm*/
addbyte(0xC0 | host_reg);
addbyte(imm & 0xff);
} else {
addbyte(0x81); /*ADDL host_reg, imm*/
addbyte(0xC0 | host_reg);
addlong(imm);
}
}
#define AND_HOST_REG_B AND_HOST_REG_L
#define AND_HOST_REG_W AND_HOST_REG_L
static __inline void
AND_HOST_REG_L(int dst_reg, int src_reg)
{
addbyte(0x21); /*ANDL dst_reg, src_reg*/
addbyte(0xc0 | dst_reg | (src_reg << 3));
}
static __inline void
AND_HOST_REG_IMM(int host_reg, uint32_t imm)
{
if (imm < 0x80 || imm >= 0xffffff80) {
addbyte(0x83); /*ANDL host_reg, imm*/
addbyte(0xE0 | host_reg);
addbyte(imm & 0xff);
} else {
addbyte(0x81); /*ANDL host_reg, imm*/
addbyte(0xE0 | host_reg);
addlong(imm);
}
}
static __inline int
TEST_HOST_REG_B(int dst_reg, int src_reg)
{
AND_HOST_REG_B(dst_reg, src_reg);
return dst_reg;
}
static __inline int
TEST_HOST_REG_W(int dst_reg, int src_reg)
{
AND_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static __inline int
TEST_HOST_REG_L(int dst_reg, int src_reg)
{
AND_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
static __inline int
TEST_HOST_REG_IMM(int host_reg, uint32_t imm)
{
AND_HOST_REG_IMM(host_reg, imm);
return host_reg;
}
#define OR_HOST_REG_B OR_HOST_REG_L
#define OR_HOST_REG_W OR_HOST_REG_L
static __inline void
OR_HOST_REG_L(int dst_reg, int src_reg)
{
addbyte(0x09); /*ORL dst_reg, src_reg*/
addbyte(0xc0 | dst_reg | (src_reg << 3));
}
static __inline void
OR_HOST_REG_IMM(int host_reg, uint32_t imm)
{
if (imm < 0x80 || imm >= 0xffffff80) {
addbyte(0x83); /*ORL host_reg, imm*/
addbyte(0xC8 | host_reg);
addbyte(imm & 0xff);
} else {
addbyte(0x81); /*ORL host_reg, imm*/
addbyte(0xC8 | host_reg);
addlong(imm);
}
}
static __inline void
NEG_HOST_REG_B(int reg)
{
addbyte(0xf6);
addbyte(0xd8 | reg);
}
static __inline void
NEG_HOST_REG_W(int reg)
{
addbyte(0x66);
addbyte(0xf7);
addbyte(0xd8 | reg);
}
static __inline void
NEG_HOST_REG_L(int reg)
{
addbyte(0xf7);
addbyte(0xd8 | reg);
}
static __inline void
SUB_HOST_REG_B(int dst_reg, int src_reg)
{
addbyte(0x28); /*SUBB dst_reg, src_reg*/
addbyte(0xc0 | dst_reg | (src_reg << 3));
}
static __inline void
SUB_HOST_REG_W(int dst_reg, int src_reg)
{
addbyte(0x66); /*SUBW dst_reg, src_reg*/
addbyte(0x29);
addbyte(0xc0 | dst_reg | (src_reg << 3));
}
static __inline void
SUB_HOST_REG_L(int dst_reg, int src_reg)
{
addbyte(0x29); /*SUBL dst_reg, src_reg*/
addbyte(0xc0 | dst_reg | (src_reg << 3));
}
static __inline void
SUB_HOST_REG_IMM_B(int host_reg, uint8_t imm)
{
addbyte(0x80); /*SUBB host_reg, imm*/
addbyte(0xE8 | host_reg);
addbyte(imm);
}
static __inline void
SUB_HOST_REG_IMM_W(int host_reg, uint16_t imm)
{
if (imm < 0x80 || imm >= 0xff80) {
addbyte(0x66); /*SUBW host_reg, imm*/
addbyte(0x83);
addbyte(0xE8 | host_reg);
addbyte(imm & 0xff);
} else {
addbyte(0x66); /*SUBW host_reg, imm*/
addbyte(0x81);
addbyte(0xE8 | host_reg);
addword(imm);
}
}
static __inline void
SUB_HOST_REG_IMM(int host_reg, uint32_t imm)
{
if (imm < 0x80 || imm >= 0xffffff80) {
addbyte(0x83); /*SUBL host_reg, imm*/
addbyte(0xE8 | host_reg);
addbyte(imm);
} else {
addbyte(0x81); /*SUBL host_reg, imm*/
addbyte(0xE8 | host_reg);
addlong(imm);
}
}
static __inline void
INC_HOST_REG_W(int host_reg)
{
addbyte(0x66); /*INCW host_reg*/
addbyte(0x40 | host_reg);
}
static __inline void
INC_HOST_REG(int host_reg)
{
addbyte(0x40 | host_reg); /*DECL host_reg*/
}
static __inline void
DEC_HOST_REG_W(int host_reg)
{
addbyte(0x66); /*DECW host_reg*/
addbyte(0x48 | host_reg);
}
static __inline void
DEC_HOST_REG(int host_reg)
{
addbyte(0x48 | host_reg); /*DECL host_reg*/
}
static __inline int
CMP_HOST_REG_B(int dst_reg, int src_reg)
{
SUB_HOST_REG_B(dst_reg, src_reg);
return dst_reg;
}
static __inline int
CMP_HOST_REG_W(int dst_reg, int src_reg)
{
SUB_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static __inline int
CMP_HOST_REG_L(int dst_reg, int src_reg)
{
SUB_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
static __inline int
CMP_HOST_REG_IMM_B(int host_reg, uint8_t imm)
{
SUB_HOST_REG_IMM_B(host_reg, imm);
return host_reg;
}
static __inline int
CMP_HOST_REG_IMM_W(int host_reg, uint16_t imm)
{
SUB_HOST_REG_IMM_W(host_reg, imm);
return host_reg;
}
static __inline int
CMP_HOST_REG_IMM_L(int host_reg, uint32_t imm)
{
SUB_HOST_REG_IMM(host_reg, imm);
return host_reg;
}
#define XOR_HOST_REG_B XOR_HOST_REG_L
#define XOR_HOST_REG_W XOR_HOST_REG_L
static __inline void
XOR_HOST_REG_L(int dst_reg, int src_reg)
{
addbyte(0x31); /*XORL dst_reg, src_reg*/
addbyte(0xc0 | dst_reg | (src_reg << 3));
}
static __inline void
XOR_HOST_REG_IMM(int host_reg, uint32_t imm)
{
if (imm < 0x80 || imm >= 0xffffff80) {
addbyte(0x83); /*XORL host_reg, imm*/
addbyte(0xF0 | host_reg);
addbyte(imm & 0xff);
} else {
addbyte(0x81); /*XORL host_reg, imm*/
addbyte(0xF0 | host_reg);
addlong(imm);
}
}
static __inline void
CALL_FUNC(uintptr_t dest)
{
addbyte(0xE8); /*CALL*/
addlong(((uintptr_t) dest - (uintptr_t) (&codeblock[block_current].data[block_pos + 4])));
}
static __inline void
SHL_B_IMM(int reg, int count)
{
addbyte(0xc0); /*SHL reg, count*/
addbyte(0xc0 | reg | 0x20);
addbyte(count);
}
static __inline void
SHL_W_IMM(int reg, int count)
{
addbyte(0x66); /*SHL reg, count*/
addbyte(0xc1);
addbyte(0xc0 | reg | 0x20);
addbyte(count);
}
static __inline void
SHL_L_IMM(int reg, int count)
{
addbyte(0xc1); /*SHL reg, count*/
addbyte(0xc0 | reg | 0x20);
addbyte(count);
}
static __inline void
SHR_B_IMM(int reg, int count)
{
addbyte(0xc0); /*SHR reg, count*/
addbyte(0xc0 | reg | 0x28);
addbyte(count);
}
static __inline void
SHR_W_IMM(int reg, int count)
{
addbyte(0x66); /*SHR reg, count*/
addbyte(0xc1);
addbyte(0xc0 | reg | 0x28);
addbyte(count);
}
static __inline void
SHR_L_IMM(int reg, int count)
{
addbyte(0xc1); /*SHR reg, count*/
addbyte(0xc0 | reg | 0x28);
addbyte(count);
}
static __inline void
SAR_B_IMM(int reg, int count)
{
addbyte(0xc0); /*SAR reg, count*/
addbyte(0xc0 | reg | 0x38);
addbyte(count);
}
static __inline void
SAR_W_IMM(int reg, int count)
{
addbyte(0x66); /*SAR reg, count*/
addbyte(0xc1);
addbyte(0xc0 | reg | 0x38);
addbyte(count);
}
static __inline void
SAR_L_IMM(int reg, int count)
{
addbyte(0xc1); /*SAR reg, count*/
addbyte(0xc0 | reg | 0x38);
addbyte(count);
}
static __inline void
CHECK_SEG_READ(x86seg *seg)
{
/*Segments always valid in real/V86 mode*/
if (!(cr0 & 1) || (cpu_state.eflags & VM_FLAG))
return;
/*CS and SS must always be valid*/
if (seg == &cpu_state.seg_cs || seg == &cpu_state.seg_ss)
return;
if (seg->checked)
return;
if (seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS))
return;
addbyte(0x83); /*CMP seg->base, -1*/
addbyte(0x05 | 0x38);
addlong((uint32_t) &seg->base);
addbyte(-1);
addbyte(0x0f);
addbyte(0x84); /*JE BLOCK_GPF_OFFSET*/
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
seg->checked = 1;
}
static __inline void
CHECK_SEG_WRITE(x86seg *seg)
{
/*Segments always valid in real/V86 mode*/
if (!(cr0 & 1) || (cpu_state.eflags & VM_FLAG))
return;
/*CS and SS must always be valid*/
if (seg == &cpu_state.seg_cs || seg == &cpu_state.seg_ss)
return;
if (seg->checked)
return;
if (seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS))
return;
addbyte(0x83); /*CMP seg->base, -1*/
addbyte(0x05 | 0x38);
addlong((uint32_t) &seg->base);
addbyte(-1);
addbyte(0x0f);
addbyte(0x84); /*JE BLOCK_GPF_OFFSET*/
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
seg->checked = 1;
}
static __inline void
CHECK_SEG_LIMITS(x86seg *seg, int end_offset)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
return;
addbyte(0x3b); /*CMP EAX, seg->limit_low*/
addbyte(0x05);
addlong((uint32_t) &seg->limit_low);
addbyte(0x0f); /*JB BLOCK_GPF_OFFSET*/
addbyte(0x82);
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
if (end_offset) {
addbyte(0x83); /*ADD EAX, end_offset*/
addbyte(0xc0);
addbyte(end_offset);
addbyte(0x3b); /*CMP EAX, seg->limit_high*/
addbyte(0x05);
addlong((uint32_t) &seg->limit_high);
addbyte(0x0f); /*JNBE BLOCK_GPF_OFFSET*/
addbyte(0x87);
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
addbyte(0x83); /*SUB EAX, end_offset*/
addbyte(0xe8);
addbyte(end_offset);
}
}
static __inline void
MEM_LOAD_ADDR_EA_B(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR EDX, EDX*/
addbyte(0xd2);
} else {
addbyte(0x8b); /*MOVL EDX, seg->base*/
addbyte(0x05 | (REG_EDX << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0xe8); /*CALL mem_load_addr_ea_b*/
addlong(mem_load_addr_ea_b - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[0] = 8;
}
static __inline int
MEM_LOAD_ADDR_EA_B_NO_ABRT(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR EDX, EDX*/
addbyte(0xd2);
} else {
addbyte(0x8b); /*MOVL EDX, seg->base*/
addbyte(0x05 | (REG_EDX << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0xe8); /*CALL mem_load_addr_ea_b_no_abrt*/
addlong(mem_load_addr_ea_b_no_abrt - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static __inline void
MEM_LOAD_ADDR_EA_W(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR EDX, EDX*/
addbyte(0xd2);
} else {
addbyte(0x8b); /*MOVL EDX, seg->base*/
addbyte(0x05 | (REG_EDX << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0xe8); /*CALL mem_load_addr_ea_w*/
addlong(mem_load_addr_ea_w - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[0] = 8;
}
static __inline void
MEM_LOAD_ADDR_EA_W_OFFSET(x86seg *seg, int offset)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR EDX, EDX*/
addbyte(0xd2);
} else {
addbyte(0x8b); /*MOVL EDX, seg->base*/
addbyte(0x05 | (REG_EDX << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0x83); /*ADD EAX, offset*/
addbyte(0xc0);
addbyte(offset);
addbyte(0xe8); /*CALL mem_load_addr_ea_w*/
addlong(mem_load_addr_ea_w - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[0] = 8;
}
static __inline int
MEM_LOAD_ADDR_EA_W_NO_ABRT(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR EDX, EDX*/
addbyte(0xd2);
} else {
addbyte(0x8b); /*MOVL EDX, seg->base*/
addbyte(0x05 | (REG_EDX << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0xe8); /*CALL mem_load_addr_ea_w_no_abrt*/
addlong(mem_load_addr_ea_w_no_abrt - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static __inline void
MEM_LOAD_ADDR_EA_L(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR EDX, EDX*/
addbyte(0xd2);
} else {
addbyte(0x8b); /*MOVL EDX, seg->base*/
addbyte(0x05 | (REG_EDX << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0xe8); /*CALL mem_load_addr_ea_l*/
addlong(mem_load_addr_ea_l - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[0] = 8;
}
static __inline int
MEM_LOAD_ADDR_EA_L_NO_ABRT(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR EDX, EDX*/
addbyte(0xd2);
} else {
addbyte(0x8b); /*MOVL EDX, seg->base*/
addbyte(0x05 | (REG_EDX << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0xe8); /*CALL mem_load_addr_ea_l_no_abrt*/
addlong(mem_load_addr_ea_l_no_abrt - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static __inline void
MEM_LOAD_ADDR_EA_Q(x86seg *seg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR EDX, EDX*/
addbyte(0xd2);
} else {
addbyte(0x8b); /*MOVL EDX, seg->base*/
addbyte(0x05 | (REG_EDX << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0xe8); /*CALL mem_load_addr_ea_q*/
addlong(mem_load_addr_ea_q - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[0] = 8;
}
static __inline void
MEM_LOAD_ADDR_IMM_B(x86seg *seg, uint32_t addr)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_LOAD_ADDR_EA_B(seg);
}
static __inline void
MEM_LOAD_ADDR_IMM_W(x86seg *seg, uint32_t addr)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_LOAD_ADDR_EA_W(seg);
}
static __inline void
MEM_LOAD_ADDR_IMM_L(x86seg *seg, uint32_t addr)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_LOAD_ADDR_EA_L(seg);
}
static __inline void
MEM_STORE_ADDR_EA_B(x86seg *seg, int host_reg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else {
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t) &seg->base);
}
if (host_reg != REG_ECX) {
addbyte(0x89); /*MOV ECX, host_reg*/
addbyte(0xc0 | REG_ECX | (host_reg << 3));
}
addbyte(0xe8); /*CALL mem_store_addr_ea_b*/
addlong(mem_store_addr_ea_b - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
}
static __inline void
MEM_STORE_ADDR_EA_B_NO_ABRT(x86seg *seg, int host_reg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else {
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t) &seg->base);
}
if (host_reg != REG_ECX) {
addbyte(0x89); /*MOV ECX, host_reg*/
addbyte(0xc0 | REG_ECX | (host_reg << 3));
}
addbyte(0xe8); /*CALL mem_store_addr_ea_b_no_abrt*/
addlong(mem_store_addr_ea_b_no_abrt - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
}
static __inline void
MEM_STORE_ADDR_EA_W(x86seg *seg, int host_reg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else {
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t) &seg->base);
}
if (host_reg != REG_ECX) {
addbyte(0x89); /*MOV ECX, host_reg*/
addbyte(0xc0 | REG_ECX | (host_reg << 3));
}
addbyte(0xe8); /*CALL mem_store_addr_ea_w*/
addlong(mem_store_addr_ea_w - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
}
static __inline void
MEM_STORE_ADDR_EA_W_NO_ABRT(x86seg *seg, int host_reg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else {
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t) &seg->base);
}
if (host_reg != REG_ECX) {
addbyte(0x89); /*MOV ECX, host_reg*/
addbyte(0xc0 | REG_ECX | (host_reg << 3));
}
addbyte(0xe8); /*CALL mem_store_addr_ea_w_no_abrt*/
addlong(mem_store_addr_ea_w_no_abrt - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
}
static __inline void
MEM_STORE_ADDR_EA_L(x86seg *seg, int host_reg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else {
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t) &seg->base);
}
if (host_reg != REG_ECX) {
addbyte(0x89); /*MOV ECX, host_reg*/
addbyte(0xc0 | REG_ECX | (host_reg << 3));
}
addbyte(0xe8); /*CALL mem_store_addr_ea_l*/
addlong(mem_store_addr_ea_l - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
}
static __inline void
MEM_STORE_ADDR_EA_L_NO_ABRT(x86seg *seg, int host_reg)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else {
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t) &seg->base);
}
if (host_reg != REG_ECX) {
addbyte(0x89); /*MOV ECX, host_reg*/
addbyte(0xc0 | REG_ECX | (host_reg << 3));
}
addbyte(0xe8); /*CALL mem_store_addr_ea_l_no_abrt*/
addlong(mem_store_addr_ea_l_no_abrt - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
}
static __inline void
MEM_STORE_ADDR_EA_Q(x86seg *seg, int host_reg, int host_reg2)
{
if (host_reg != REG_EBX) {
addbyte(0x89); /*MOV EBX, host_reg*/
addbyte(0xc0 | REG_EBX | (host_reg << 3));
}
if (host_reg2 != REG_ECX) {
addbyte(0x89); /*MOV ECX, host_reg2*/
addbyte(0xc0 | REG_ECX | (host_reg2 << 3));
}
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else {
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0xe8); /*CALL mem_store_addr_ea_q*/
addlong(mem_store_addr_ea_q - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
}
static __inline void
MEM_STORE_ADDR_IMM_B(x86seg *seg, uint32_t addr, int host_reg)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_STORE_ADDR_EA_B(seg, host_reg);
}
static __inline void
MEM_STORE_ADDR_IMM_L(x86seg *seg, uint32_t addr, int host_reg)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_STORE_ADDR_EA_L(seg, host_reg);
}
static __inline void
MEM_STORE_ADDR_IMM_W(x86seg *seg, uint32_t addr, int host_reg)
{
addbyte(0xb8); /*MOV EAX, addr*/
addlong(addr);
MEM_STORE_ADDR_EA_W(seg, host_reg);
}
static __inline x86seg *
FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
{
int mod = (fetchdat >> 6) & 3;
int rm = fetchdat & 7;
if (!mod && rm == 6) {
addbyte(0xb8); /*MOVL EAX, imm16*/
addlong((fetchdat >> 8) & 0xffff);
(*op_pc) += 2;
} else {
switch (mod) {
case 0:
addbyte(0xa1); /*MOVL EAX, *mod1add[0][rm]*/
addlong((uint32_t) mod1add[0][rm]);
if (mod1add[1][rm] != &zero) {
addbyte(0x03); /*ADDL EAX, *mod1add[1][rm]*/
addbyte(0x05);
addlong((uint32_t) mod1add[1][rm]);
}
break;
case 1:
addbyte(0xa1); /*MOVL EAX, *mod1add[0][rm]*/
addlong((uint32_t) mod1add[0][rm]);
addbyte(0x83); /*ADDL EAX, imm8*/
addbyte(0xc0 | REG_EAX);
addbyte((int8_t) (rmdat >> 8));
if (mod1add[1][rm] != &zero) {
addbyte(0x03); /*ADDL EAX, *mod1add[1][rm]*/
addbyte(0x05);
addlong((uint32_t) mod1add[1][rm]);
}
(*op_pc)++;
break;
case 2:
addbyte(0xb8); /*MOVL EAX, imm16*/
addlong((fetchdat >> 8) & 0xffff);
addbyte(0x03); /*ADDL EAX, *mod1add[0][rm]*/
addbyte(0x05);
addlong((uint32_t) mod1add[0][rm]);
if (mod1add[1][rm] != &zero) {
addbyte(0x03); /*ADDL EAX, *mod1add[1][rm]*/
addbyte(0x05);
addlong((uint32_t) mod1add[1][rm]);
}
(*op_pc) += 2;
break;
}
addbyte(0x25); /*ANDL EAX, 0xffff*/
addlong(0xffff);
if (mod1seg[rm] == &ss && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
}
return op_ea_seg;
}
static __inline x86seg *
FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc, int stack_offset)
{
uint32_t new_eaaddr;
int mod = (fetchdat >> 6) & 3;
int rm = fetchdat & 7;
if (rm == 4) {
uint8_t sib = fetchdat >> 8;
(*op_pc)++;
switch (mod) {
case 0:
if ((sib & 7) == 5) {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOVL EAX, imm32*/
addlong(new_eaaddr);
(*op_pc) += 4;
} else {
addbyte(0x8b); /*MOVL EAX, regs[sib&7].l*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[sib & 7].l));
}
break;
case 1:
addbyte(0x8b); /*MOVL EAX, regs[sib&7].l*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[sib & 7].l));
addbyte(0x83); /*ADDL EAX, imm8*/
addbyte(0xc0 | REG_EAX);
addbyte((int8_t) (rmdat >> 16));
(*op_pc)++;
break;
case 2:
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOVL EAX, new_eaaddr*/
addlong(new_eaaddr);
addbyte(0x03); /*ADDL EAX, regs[sib&7].l*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[sib & 7].l));
(*op_pc) += 4;
break;
}
if (stack_offset && (sib & 7) == 4 && (mod || (sib & 7) != 5)) /*ESP*/
{
if (stack_offset < 0x80 || stack_offset >= 0xffffff80) {
addbyte(0x83);
addbyte(0xc0 | REG_EAX);
addbyte(stack_offset);
} else {
addbyte(0x05); /*ADDL EAX, stack_offset*/
addlong(stack_offset);
}
}
if (((sib & 7) == 4 || (mod && (sib & 7) == 5)) && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (((sib >> 3) & 7) != 4) {
switch (sib >> 6) {
case 0:
addbyte(0x03); /*ADDL EAX, regs[sib&7].l*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[(sib >> 3) & 7].l));
break;
case 1:
addbyte(0x8B);
addbyte(0x45 | (REG_EDI << 3));
addbyte((uint8_t) cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL EDI, reg*/
addbyte(0x01);
addbyte(0xc0 | REG_EAX | (REG_EDI << 3)); /*ADDL EAX, EDI*/
addbyte(0x01);
addbyte(0xc0 | REG_EAX | (REG_EDI << 3)); /*ADDL EAX, EDI*/
break;
case 2:
addbyte(0x8B);
addbyte(0x45 | (REG_EDI << 3));
addbyte((uint8_t) cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL EDI, reg*/
addbyte(0xC1);
addbyte(0xE0 | REG_EDI);
addbyte(2); /*SHL EDI, 2*/
addbyte(0x01);
addbyte(0xc0 | REG_EAX | (REG_EDI << 3)); /*ADDL EAX, EDI*/
break;
case 3:
addbyte(0x8B);
addbyte(0x45 | (REG_EDI << 3));
addbyte((uint8_t) cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL EDI reg*/
addbyte(0xC1);
addbyte(0xE0 | REG_EDI);
addbyte(3); /*SHL EDI, 3*/
addbyte(0x01);
addbyte(0xc0 | REG_EAX | (REG_EDI << 3)); /*ADDL EAX, EDI*/
break;
}
}
} else {
if (!mod && rm == 5) {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOVL EAX, imm32*/
addlong(new_eaaddr);
(*op_pc) += 4;
return op_ea_seg;
}
addbyte(0x8b); /*MOVL EAX, regs[rm].l*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[rm].l));
cpu_state.eaaddr = cpu_state.regs[rm].l;
if (mod) {
if (rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (mod == 1) {
addbyte(0x83); /*ADD EAX, imm8*/
addbyte(0xc0 | REG_EAX);
addbyte((int8_t) (fetchdat >> 8));
(*op_pc)++;
} else {
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x05); /*ADD EAX, imm32*/
addlong(new_eaaddr);
(*op_pc) += 4;
}
}
}
return op_ea_seg;
}
static __inline x86seg *
FETCH_EA(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc, uint32_t op_32)
{
if (op_32 & 0x200)
return FETCH_EA_32(op_ea_seg, fetchdat, op_ssegs, op_pc, 0);
return FETCH_EA_16(op_ea_seg, fetchdat, op_ssegs, op_pc);
}
static __inline void
LOAD_STACK_TO_EA(int off)
{
if (stack32) {
addbyte(0x8b); /*MOVL EAX,[ESP]*/
addbyte(0x45 | (REG_EAX << 3));
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].l));
if (off) {
addbyte(0x83); /*ADD EAX, off*/
addbyte(0xc0 | (0 << 3) | REG_EAX);
addbyte(off);
}
} else {
addbyte(0x0f); /*MOVZX EAX,W[ESP]*/
addbyte(0xb7);
addbyte(0x45 | (REG_EAX << 3));
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].w));
if (off) {
addbyte(0x66); /*ADD AX, off*/
addbyte(0x05);
addword(off);
}
}
}
static __inline void
LOAD_EBP_TO_EA(int off)
{
if (stack32) {
addbyte(0x8b); /*MOVL EAX,[EBP]*/
addbyte(0x45 | (REG_EAX << 3));
addbyte((uint8_t) cpu_state_offset(regs[REG_EBP].l));
if (off) {
addbyte(0x83); /*ADD EAX, off*/
addbyte(0xc0 | (0 << 3) | REG_EAX);
addbyte(off);
}
} else {
addbyte(0x0f); /*MOVZX EAX,W[EBP]*/
addbyte(0xb7);
addbyte(0x45 | (REG_EAX << 3));
addbyte((uint8_t) cpu_state_offset(regs[REG_EBP].w));
if (off) {
addbyte(0x66); /*ADD AX, off*/
addbyte(0x05);
addword(off);
}
}
}
static __inline void
SP_MODIFY(int off)
{
if (stack32) {
if (off < 0x80) {
addbyte(0x83); /*ADD [ESP], off*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].l));
addbyte(off);
} else {
addbyte(0x81); /*ADD [ESP], off*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].l));
addlong(off);
}
} else {
if (off < 0x80) {
addbyte(0x66); /*ADD [SP], off*/
addbyte(0x83);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].w));
addbyte(off);
} else {
addbyte(0x66); /*ADD [SP], off*/
addbyte(0x81);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(regs[REG_ESP].w));
addword(off);
}
}
}
static __inline void
TEST_ZERO_JUMP_W(int host_reg, uint32_t new_pc, int taken_cycles)
{
addbyte(0x66); /*CMPW host_reg, 0*/
addbyte(0x83);
addbyte(0xc0 | 0x38 | host_reg);
addbyte(0);
addbyte(0x75); /*JNZ +*/
addbyte(7 + 5 + (taken_cycles ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(new_pc);
if (taken_cycles) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(taken_cycles);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
TEST_ZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
{
addbyte(0x83); /*CMPW host_reg, 0*/
addbyte(0xc0 | 0x38 | host_reg);
addbyte(0);
addbyte(0x75); /*JNZ +*/
addbyte(7 + 5 + (taken_cycles ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(new_pc);
if (taken_cycles) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(taken_cycles);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
TEST_NONZERO_JUMP_W(int host_reg, uint32_t new_pc, int taken_cycles)
{
addbyte(0x66); /*CMPW host_reg, 0*/
addbyte(0x83);
addbyte(0xc0 | 0x38 | host_reg);
addbyte(0);
addbyte(0x74); /*JZ +*/
addbyte(7 + 5 + (taken_cycles ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(new_pc);
if (taken_cycles) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(taken_cycles);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
TEST_NONZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
{
addbyte(0x83); /*CMPW host_reg, 0*/
addbyte(0xc0 | 0x38 | host_reg);
addbyte(0);
addbyte(0x74); /*JZ +*/
addbyte(7 + 5 + (taken_cycles ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(new_pc);
if (taken_cycles) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(taken_cycles);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
{
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_SUB8:
addbyte(0x8a); /*MOV AL, flags_op1*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op1));
addbyte(0x3a); /*CMP AL, flags_op2*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op2));
if (not )
addbyte(0x76); /*JBE*/
else
addbyte(0x77); /*JNBE*/
break;
case FLAGS_SUB16:
addbyte(0x66); /*MOV AX, flags_op1*/
addbyte(0x8b);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op1));
addbyte(0x66); /*CMP AX, flags_op2*/
addbyte(0x3b);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op2));
if (not )
addbyte(0x76); /*JBE*/
else
addbyte(0x77); /*JNBE*/
break;
case FLAGS_SUB32:
addbyte(0x8b); /*MOV EAX, flags_op1*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op1));
addbyte(0x3b); /*CMP EAX, flags_op2*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op2));
if (not )
addbyte(0x76); /*JBE*/
else
addbyte(0x77); /*JNBE*/
break;
default:
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN) {
addbyte(0x83); /*CMP flags_res, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(flags_res));
addbyte(0);
addbyte(0x74); /*JZ +*/
} else {
CALL_FUNC((uintptr_t) ZF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x75); /*JNZ +*/
}
if (not )
addbyte(5 + 2 + 2 + 7 + 5 + (timing_bt ? 4 : 0));
else
addbyte(5 + 2 + 2);
CALL_FUNC((uintptr_t) CF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
if (not )
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
break;
}
addbyte(7 + 5 + (timing_bt ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(op_pc + pc_offset + offset);
if (timing_bt) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(timing_bt);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
BRANCH_COND_L(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
{
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_SUB8:
addbyte(0x8a); /*MOV AL, flags_op1*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op1));
addbyte(0x3a); /*CMP AL, flags_op2*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op2));
if (not )
addbyte(0x7c); /*JL*/
else
addbyte(0x7d); /*JNL*/
break;
case FLAGS_SUB16:
addbyte(0x66); /*MOV AX, flags_op1*/
addbyte(0x8b);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op1));
addbyte(0x66); /*CMP AX, flags_op2*/
addbyte(0x3b);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op2));
if (not )
addbyte(0x7c); /*JL*/
else
addbyte(0x7d); /*JNL*/
break;
case FLAGS_SUB32:
addbyte(0x8b); /*MOV EAX, flags_op1*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op1));
addbyte(0x3b); /*CMP EAX, flags_op2*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op2));
if (not )
addbyte(0x7c); /*JL*/
else
addbyte(0x7d); /*JNL*/
break;
default:
CALL_FUNC((uintptr_t) NF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x0f); /*SETNE BL*/
addbyte(0x95);
addbyte(0xc3);
CALL_FUNC((uintptr_t) VF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x0f); /*SETNE AL*/
addbyte(0x95);
addbyte(0xc0);
addbyte(0x38); /*CMP AL, BL*/
addbyte(0xd8);
if (not )
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
break;
}
addbyte(7 + 5 + (timing_bt ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(op_pc + pc_offset + offset);
if (timing_bt) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(timing_bt);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
{
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_SUB8:
addbyte(0x8a); /*MOV AL, flags_op1*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op1));
addbyte(0x3a); /*CMP AL, flags_op2*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op2));
if (not )
addbyte(0x7e); /*JLE*/
else
addbyte(0x7f); /*JNLE*/
break;
case FLAGS_SUB16:
addbyte(0x66); /*MOV AX, flags_op1*/
addbyte(0x8b);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op1));
addbyte(0x66); /*CMP AX, flags_op2*/
addbyte(0x3b);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op2));
if (not )
addbyte(0x7e); /*JLE*/
else
addbyte(0x7f); /*JNLE*/
break;
case FLAGS_SUB32:
addbyte(0x8b); /*MOV EAX, flags_op1*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op1));
addbyte(0x3b); /*CMP EAX, flags_op2*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(flags_op2));
if (not )
addbyte(0x7e); /*JLE*/
else
addbyte(0x7f); /*JNLE*/
break;
default:
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN) {
addbyte(0x83); /*CMP flags_res, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(flags_res));
addbyte(0);
addbyte(0x74); /*JZ +*/
} else {
CALL_FUNC((uintptr_t) ZF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x75); /*JNZ +*/
}
if (not )
addbyte(5 + 2 + 3 + 5 + 2 + 3 + 2 + 2 + 7 + 5 + (timing_bt ? 4 : 0));
else
addbyte(5 + 2 + 3 + 5 + 2 + 3 + 2 + 2);
CALL_FUNC((uintptr_t) NF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x0f); /*SETNE BL*/
addbyte(0x95);
addbyte(0xc3);
CALL_FUNC((uintptr_t) VF_SET);
addbyte(0x85); /*TEST EAX,EAX*/
addbyte(0xc0);
addbyte(0x0f); /*SETNE AL*/
addbyte(0x95);
addbyte(0xc0);
addbyte(0x38); /*CMP AL, BL*/
addbyte(0xd8);
if (not )
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
break;
}
addbyte(7 + 5 + (timing_bt ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(pc));
addlong(op_pc + pc_offset + offset);
if (timing_bt) {
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(_cycles));
addbyte(timing_bt);
}
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
static __inline void
FP_ENTER(void)
{
if (codegen_fpu_entered)
return;
addbyte(0xf6); /*TEST cr0, 0xc*/
addbyte(0x05);
addlong((uintptr_t) &cr0);
addbyte(0xc);
addbyte(0x74); /*JZ +*/
addbyte(7 + 7 + 5 + 5);
addbyte(0xC7); /*MOVL [oldpc],op_old_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(oldpc));
addlong(op_old_pc);
addbyte(0xc7); /*MOV [ESP], 7*/
addbyte(0x04);
addbyte(0x24);
addlong(7);
addbyte(0xe8); /*CALL x86_int*/
addlong((uint32_t) x86_int - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
codegen_fpu_entered = 1;
}
static __inline void
FP_FLD(int reg)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0xf3); /*MOVQ XMM0, ST[reg][EBP]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP + reg) & 7]));
addbyte(0xc6); /*MOVB TOP[EBP], (TOP-1) & 7*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte((cpu_state.TOP - 1) & 7);
addbyte(0xf3); /*MOVQ XMM1, MM[reg][EBP]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(MM[(cpu_state.TOP + reg) & 7].q));
addbyte(0x66); /*MOVQ ST[-1][EBP], XMM0*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP - 1) & 7]));
addbyte(0x8a); /*MOV AL, tag[reg][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP + reg) & 7]));
addbyte(0x66); /*MOVQ MM[-1][EBP], XMM1*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(MM[(cpu_state.TOP - 1) & 7].q));
addbyte(0x88); /*MOV tag[-1][EBP], AL*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP - 1) & 7]));
} else {
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV EBX, EAX*/
addbyte(0xc3);
if (reg) {
addbyte(0x83); /*ADD EAX, reg*/
addbyte(0xc0);
addbyte(reg);
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(0x07);
} else {
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
}
addbyte(0xdd); /*FLD [ST+EAX*8]*/
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(0x07);
addbyte(0x8b); /*MOV EDX, [ST_i64+EAX]*/
addbyte(0x54);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0x8b); /*MOV ECX, [ST_i64+4+EAX]*/
addbyte(0x4c);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(MM) + 4);
addbyte(0x8a); /*MOV AL, [tag+EAX]*/
addbyte(0x44);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x88); /*MOV [tag+EBX], AL*/
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(0x89); /*MOV [ST_i64+EBX], EDX*/
addbyte(0x54);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0x89); /*MOV [ST_i64+EBX+4], ECX*/
addbyte(0x4c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM) + 4);
addbyte(0x89); /*MOV [TOP], EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
}
}
static __inline void
FP_FST(int reg)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0xf3); /*MOVQ XMM0, ST[0][EBP]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0x8a); /*MOV AL, tag[0][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[cpu_state.TOP]));
addbyte(0x66); /*MOVQ ST[reg][EBP], XMM0*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP + reg) & 7]));
addbyte(0x88); /*MOV tag[reg][EBP], AL*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP + reg) & 7]));
} else {
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xdd); /*FLD [ST+EAX*8]*/
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x8a); /*MOV BL, [tag+EAX]*/
addbyte(0x5c);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag[0]));
if (reg) {
addbyte(0x83); /*ADD EAX, reg*/
addbyte(0xc0);
addbyte(reg);
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(0x07);
}
addbyte(0xdd); /*FSTP [ST+EAX*8]*/
addbyte(0x5c);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x88); /*MOV [tag+EAX], BL*/
addbyte(0x5c);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag[0]));
}
}
static __inline void
FP_FXCH(int reg)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0xf3); /*MOVQ XMM0, ST[0][EBP]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0xf3); /*MOVQ XMM1, ST[reg][EBP]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP + reg) & 7]));
addbyte(0x66); /*MOVQ ST[reg][EBP], XMM0*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP + reg) & 7]));
addbyte(0xf3); /*MOVQ XMM2, MM[0][EBP]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x55);
addbyte((uint8_t) cpu_state_offset(MM[cpu_state.TOP].q));
addbyte(0x66); /*MOVQ ST[0][EBP], XMM1*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0xf3); /*MOVQ XMM3, MM[reg][EBP]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(MM[(cpu_state.TOP + reg) & 7].q));
addbyte(0x66); /*MOVQ MM[reg][EBP], XMM2*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x55);
addbyte((uint8_t) cpu_state_offset(MM[(cpu_state.TOP + reg) & 7].q));
addbyte(0x8a); /*MOV AL, tag[0][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[cpu_state.TOP]));
addbyte(0x66); /*MOVQ MM[0][EBP], XMM3*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(MM[cpu_state.TOP].q));
addbyte(0x8a); /*MOV AH, tag[reg][EBP]*/
addbyte(0x65);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP + reg) & 7]));
addbyte(0x88); /*MOV tag[reg][EBP], AL*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP + reg) & 7]));
addbyte(0x88); /*MOV tag[0][EBP], AH*/
addbyte(0x65);
addbyte((uint8_t) cpu_state_offset(tag[cpu_state.TOP]));
} else {
addbyte(0x8b); /*MOV EAX, [TOP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV EBX, EAX*/
addbyte(0xc3);
addbyte(0x83); /*ADD EAX, reg*/
addbyte(0xc0);
addbyte(reg);
addbyte(0xdd); /*FLD [ST+EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(0x07);
addbyte(0xdd); /*FLD [ST+EAX*8]*/
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0xdd); /*FSTP [ST+EAX*8]*/
addbyte(0x5c);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x8a); /*MOV CL, tag[EAX]*/
addbyte(0x4c);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(0x8a); /*MOV DL, tag[EBX]*/
addbyte(0x54);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(0x88); /*MOV tag[EBX], CL*/
addbyte(0x4c);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(0x88); /*MOV tag[EAX], DL*/
addbyte(0x54);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(0xbe); /*MOVL ESI, ST_int64*/
addlong((uintptr_t) cpu_state.MM);
addbyte(0x8b); /*MOV ECX, ST_int64[EAX*8]*/
addbyte(0x0c);
addbyte(0xc6);
addbyte(0x8b); /*MOV EDX, ST_int64[EBX*8]*/
addbyte(0x14);
addbyte(0xde);
addbyte(0x89); /*MOV ST_int64[EBX*8], ECX*/
addbyte(0x0c);
addbyte(0xde);
addbyte(0x89); /*MOV ST_int64[EAX*8], EDX*/
addbyte(0x14);
addbyte(0xc6);
addbyte(0x8b); /*MOV ECX, ST_int64[EAX*8]+4*/
addbyte(0x4c);
addbyte(0xc6);
addbyte(0x04);
addbyte(0x8b); /*MOV EDX, ST_int64[EBX*8]+4*/
addbyte(0x54);
addbyte(0xde);
addbyte(0x04);
addbyte(0x89); /*MOV ST_int64[EBX*8]+4, ECX*/
addbyte(0x4c);
addbyte(0xde);
addbyte(0x04);
addbyte(0x89); /*MOV ST_int64[EAX*8]+4, EDX*/
addbyte(0x54);
addbyte(0xc6);
addbyte(0x04);
}
}
static __inline void
FP_LOAD_S(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x85); /*TEST EAX, EAX*/
addbyte(0xc0);
addbyte(0xd9); /*FLD [ESP]*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xc6); /*MOVB TOP[EBP], (TOP-1) & 7*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte((cpu_state.TOP - 1) & 7);
addbyte(0x0f); /*SETE tag[reg][EBP]*/
addbyte(0x94);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP - 1) & 7]));
addbyte(0xdd); /*FSTP ST[reg][EBP]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP - 1) & 7]));
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(1);
addbyte(0xd9); /*FLD [ESP]*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0x85); /*TEST EAX, EAX*/
addbyte(0xc0);
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x0f); /*SETE [tag+EBX]*/
addbyte(0x94);
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
}
}
static __inline void
FP_LOAD_D(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x89); /*MOV ST[reg][EBP], EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP - 1) & 7]));
addbyte(0x09); /*OR EAX, EDX*/
addbyte(0xd0);
addbyte(0x89); /*MOV ST[reg][EBP]+4, EDX*/
addbyte(0x55);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP - 1) & 7]) + 4);
addbyte(0xc6); /*MOVB TOP[EBP], (TOP-1) & 7*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte((cpu_state.TOP - 1) & 7);
addbyte(0x0f); /*SETE tag[reg][EBP]*/
addbyte(0x94);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP - 1) & 7]));
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x89); /*MOV [ESP+4], EDX*/
addbyte(0x54);
addbyte(0x24);
addbyte(0x04);
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(1);
addbyte(0x09); /*OR EAX, EDX*/
addbyte(0xd0);
addbyte(0xdd); /*FLD [ESP]*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0x83); /*CMP EAX, 0*/
addbyte(0xf8);
addbyte(0);
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x0f); /*SETE [tag+EBX]*/
addbyte(0x94);
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
}
}
static __inline void
FP_LOAD_IW(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x66); /*MOV [ESP], AX*/
addbyte(0x89);
addbyte(0x04);
addbyte(0x24);
addbyte(0x66); /*TEST AX, AX*/
addbyte(0x85);
addbyte(0xc0);
addbyte(0xdf); /*FILDw [ESP]*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xc6); /*MOVB TOP[EBP], (TOP-1) & 7*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte((cpu_state.TOP - 1) & 7);
addbyte(0x0f); /*SETE tag[reg][EBP]*/
addbyte(0x94);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP - 1) & 7]));
addbyte(0xdd); /*FSTP ST[reg][EBP]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP - 1) & 7]));
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(1);
addbyte(0xdf); /*FILDw [ESP]*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0x83); /*CMP EAX, 0*/
addbyte(0xf8);
addbyte(0);
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x0f); /*SETE [tag+EBX]*/
addbyte(0x94);
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
}
}
static __inline void
FP_LOAD_IL(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x85); /*TEST EAX, EAX*/
addbyte(0xc0);
addbyte(0xdb); /*FILDl [ESP]*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xc6); /*MOVB TOP[EBP], (TOP-1) & 7*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte((cpu_state.TOP - 1) & 7);
addbyte(0x0f); /*SETE tag[reg][EBP]*/
addbyte(0x94);
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP - 1) & 7]));
addbyte(0xdd); /*FSTP ST[reg][EBP]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP - 1) & 7]));
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(1);
addbyte(0xdb); /*FILDl [ESP]*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0x83); /*CMP EAX, 0*/
addbyte(0xf8);
addbyte(0);
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x0f); /*SETE [tag+EBX]*/
addbyte(0x94);
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
}
}
static __inline void
FP_LOAD_IQ(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x89); /*MOV MM[reg][EBP], EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(MM[(cpu_state.TOP - 1) & 7].q));
addbyte(0x09); /*OR EAX, EDX*/
addbyte(0xd0);
addbyte(0x89); /*MOV MM[reg][EBP]+4, EDX*/
addbyte(0x55);
addbyte((uint8_t) cpu_state_offset(MM[(cpu_state.TOP - 1) & 7].q) + 4);
addbyte(0x0f); /*SETE AL*/
addbyte(0x94);
addbyte(0xc0);
addbyte(0xdf); /*FILDq MM[reg][EBP]*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(MM[(cpu_state.TOP - 1) & 7].q));
addbyte(0x0c); /*OR AL, TAG_UINT64*/
addbyte(TAG_UINT64);
addbyte(0xc6); /*MOVB TOP[EBP], (TOP-1) & 7*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte((cpu_state.TOP - 1) & 7);
addbyte(0x88); /*MOV tag[reg][EBP], AL*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP - 1) & 7]));
addbyte(0xdd); /*FSTP ST[reg][EBP]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP - 1) & 7]));
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(1);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0x89); /*MOV [ST_i64+EBX*8], EAX*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0x09); /*OR EAX, EDX*/
addbyte(0xd0);
addbyte(0x89); /*MOV [ST_i64+4+EBX*8], EDX*/
addbyte(0x54);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM) + 4);
addbyte(0x83); /*CMP EAX, 0*/
addbyte(0xf8);
addbyte(0);
addbyte(0xdf); /*FILDl [ST_i64+EBX*8]*/
addbyte(0x6c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0x0f); /*SETE AL*/
addbyte(0x94);
addbyte(0xc0);
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x0c); /*OR AL, TAG_UINT64*/
addbyte(TAG_UINT64);
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x88); /*MOV [tag+EBX], AL*/
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
}
}
static __inline void
FP_LOAD_IMM_Q(uint64_t v)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0xc7); /*MOV ST[reg][EBP], v*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP - 1) & 7]));
addlong(v & 0xffffffff);
addbyte(0xc7); /*MOV ST[reg][EBP]+4, v*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP - 1) & 7]) + 4);
addlong(v >> 32);
addbyte(0xc6); /*MOVB TOP[EBP], (TOP-1) & 7*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte((cpu_state.TOP - 1) & 7);
addbyte(0xc6); /*MOVB tag[reg][EBP], 1:0*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP - 1) & 7]));
addbyte(v ? 0 : 1);
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(1);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
addbyte(0xc7); /*MOV ST[EBP+EBX*8], v*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addlong(v & 0xffffffff);
addbyte(0xc7); /*MOV ST[EBP+EBX*8]+4, v*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST) + 4);
addlong(v >> 32);
addbyte(0xc6); /*MOVB tag[reg][EBP], 1:0*/
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(v ? 0 : 1);
addbyte(0x89); /*MOV TOP, EBX*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
}
}
static __inline int
FP_LOAD_REG(int reg)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0xdd); /*FLD ST[reg][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP + reg) & 7]));
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
if (reg) {
addbyte(0x83); /*ADD EBX, reg*/
addbyte(0xc3);
addbyte(reg);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
}
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
}
addbyte(0xd9); /*FSTP [ESP]*/
addbyte(0x1c);
addbyte(0x24);
addbyte(0x8b); /*MOV EAX, [ESP]*/
addbyte(0x04 | (REG_EBX << 3));
addbyte(0x24);
return REG_EBX;
}
static __inline void
FP_LOAD_REG_D(int reg, int *host_reg1, int *host_reg2)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0xdd); /*FLD ST[reg][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP + reg) & 7]));
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
if (reg) {
addbyte(0x83); /*ADD EBX, reg*/
addbyte(0xc3);
addbyte(reg);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
}
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
}
addbyte(0xdd); /*FSTP [ESP]*/
addbyte(0x1c);
addbyte(0x24);
addbyte(0x8b); /*MOV EBX, [ESP]*/
addbyte(0x04 | (REG_EBX << 3));
addbyte(0x24);
addbyte(0x8b); /*MOV ECX, [ESP+4]*/
addbyte(0x44 | (REG_ECX << 3));
addbyte(0x24);
addbyte(0x04);
*host_reg1 = REG_EBX;
*host_reg2 = REG_ECX;
}
static __inline int
FP_LOAD_REG_INT_W(int reg)
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
if (reg) {
addbyte(0x83); /*ADD EBX, reg*/
addbyte(0xc3);
addbyte(reg);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
}
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0xd9); /*FLDCW cpu_state.new_npxc*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(new_npxc));
addbyte(0xdb); /*FISTP [ESP]*/
addbyte(0x1c);
addbyte(0x24);
addbyte(0xd9); /*FLDCW cpu_state.old_npxc*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(old_npxc));
addbyte(0x8b); /*MOV EBX, [ESP]*/
addbyte(0x1c);
addbyte(0x24);
return REG_EBX;
}
static __inline int
FP_LOAD_REG_INT(int reg)
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
if (reg) {
addbyte(0x83); /*ADD EBX, reg*/
addbyte(0xc3);
addbyte(reg);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
}
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0xd9); /*FLDCW cpu_state.new_npxc*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(new_npxc));
addbyte(0xdb); /*FISTP [ESP]*/
addbyte(0x1c);
addbyte(0x24);
addbyte(0xd9); /*FLDCW cpu_state.old_npxc*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(old_npxc));
addbyte(0x8b); /*MOV EBX, [ESP]*/
addbyte(0x1c);
addbyte(0x24);
return REG_EBX;
}
static __inline void
FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
if (reg) {
addbyte(0x83); /*ADD EBX, reg*/
addbyte(0xc3);
addbyte(reg);
addbyte(0x83); /*AND EBX, 7*/
addbyte(0xe3);
addbyte(7);
}
if (codegen_fpu_loaded_iq[cpu_state.TOP] && (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)) {
/*If we know the register was loaded with FILDq in this block and
has not been modified, then we can skip most of the conversion
and just load the 64-bit integer representation directly */
addbyte(0x8b); /*MOV ECX, [ST_i64+EBX*8]*/
addbyte(0x4c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM) + 4);
addbyte(0x8b); /*MOV EBX, [ST_i64+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM));
return;
}
addbyte(0xf6); /*TEST TAG[EBX], TAG_UINT64*/
addbyte(0x44);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(TAG_UINT64);
addbyte(0x74); /*JZ +*/
addbyte(4 + 4 + 2);
addbyte(0x8b); /*MOV ECX, [ST_i64+EBX*8]*/
addbyte(0x4c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM) + 4);
addbyte(0x8b); /*MOV EBX, [ST_i64+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(MM));
addbyte(0xeb); /*JMP done*/
addbyte(4 + 3 + 3 + 3 + 3 + 4);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0xd9); /*FLDCW cpu_state.new_npxc*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(new_npxc));
addbyte(0xdf); /*FISTPQ [ESP]*/
addbyte(0x3c);
addbyte(0x24);
addbyte(0xd9); /*FLDCW cpu_state.old_npxc*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(old_npxc));
addbyte(0x8b); /*MOV EBX, [ESP]*/
addbyte(0x1c);
addbyte(0x24);
addbyte(0x8b); /*MOV ECX, 4[ESP]*/
addbyte(0x4c);
addbyte(0x24);
addbyte(4);
*host_reg1 = REG_EBX;
*host_reg2 = REG_ECX;
}
static __inline void
FP_POP(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0xc6); /*MOVB tag[0][EBP], 3*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[cpu_state.TOP]));
addbyte(3);
addbyte(0xc6); /*MOVB TOP[EBP], (TOP-1) & 7*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte((cpu_state.TOP + 1) & 7);
} else {
addbyte(0x8b); /*MOV EAX, TOP*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xc6); /*MOVB tag[EAX], 3*/
addbyte(0x44);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(3);
addbyte(0x04); /*ADD AL, 1*/
addbyte(1);
addbyte(0x24); /*AND AL, 7*/
addbyte(7);
addbyte(0x88); /*MOV TOP, AL*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
}
}
static __inline void
FP_POP2(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0xc6); /*MOVB tag[0][EBP], 3*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[cpu_state.TOP]));
addbyte(3);
addbyte(0xc6); /*MOVB tag[1][EBP], 3*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP + 1) & 7]));
addbyte(3);
addbyte(0xc6); /*MOVB TOP[EBP], (TOP+2) & 7*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte((cpu_state.TOP + 2) & 7);
} else {
addbyte(0x8b); /*MOV EAX, TOP*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xc6); /*MOVB tag[EAX], 3*/
addbyte(0x44);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(3);
addbyte(0x04); /*ADD AL, 2*/
addbyte(2);
addbyte(0x24); /*AND AL, 7*/
addbyte(7);
addbyte(0x88); /*MOV TOP, AL*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
}
}
#define FPU_ADD 0x00
#define FPU_DIV 0x30
#define FPU_DIVR 0x38
#define FPU_MUL 0x08
#define FPU_SUB 0x20
#define FPU_SUBR 0x28
static __inline void
FP_OP_S(int op)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[dst][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0x80); /*AND tag[dst][EBP], ~TAG_UINT64*/
addbyte(0x65);
addbyte((uint8_t) cpu_state_offset(tag[cpu_state.TOP]));
addbyte(TAG_NOT_UINT64);
addbyte(0xd8); /*FADD [ESP]*/
addbyte(0x04 | op);
addbyte(0x24);
addbyte(0xdd); /*FSTP ST[dst][EBP]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
addbyte(0x64);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(TAG_NOT_UINT64);
addbyte(0xd8); /*FADD [ESP]*/
addbyte(0x04 | op);
addbyte(0x24);
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
}
}
static __inline void
FP_OP_D(int op)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x89); /*MOV [ESP+4], EDX*/
addbyte(0x54);
addbyte(0x24);
addbyte(0x04);
if (((cpu_state.npxc >> 10) & 3) && op == FPU_ADD) {
addbyte(0xd9); /*FLDCW cpu_state.new_npxc*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(new_npxc));
}
addbyte(0xdd); /*FLD ST[dst][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0x80); /*AND tag[dst][EBP], ~TAG_UINT64*/
addbyte(0x65);
addbyte((uint8_t) cpu_state_offset(tag[cpu_state.TOP]));
addbyte(TAG_NOT_UINT64);
addbyte(0xdc); /*FADD [ESP]*/
addbyte(0x04 | op);
addbyte(0x24);
addbyte(0xdd); /*FSTP ST[dst][EBP]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
if (((cpu_state.npxc >> 10) & 3) && op == FPU_ADD) {
addbyte(0xd9); /*FLDCW cpu_state.old_npxc*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(old_npxc));
}
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
if (((cpu_state.npxc >> 10) & 3) && op == FPU_ADD) {
addbyte(0xd9); /*FLDCW cpu_state.new_npxc*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(new_npxc));
}
addbyte(0x89); /*MOV [ESP+4], EDX*/
addbyte(0x54);
addbyte(0x24);
addbyte(0x04);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
addbyte(0x64);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(TAG_NOT_UINT64);
addbyte(0xdc); /*FADD [ESP]*/
addbyte(0x04 | op);
addbyte(0x24);
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
if (((cpu_state.npxc >> 10) & 3) && op == FPU_ADD) {
addbyte(0xd9); /*FLDCW cpu_state.old_npxc*/
addbyte(0x6d);
addbyte((uint8_t) cpu_state_offset(old_npxc));
}
}
}
static __inline void
FP_OP_IW(int op)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x66); /*MOV [ESP], AX*/
addbyte(0x89);
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[0][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0x80); /*AND tag[0][EBP], ~TAG_UINT64*/
addbyte(0x65);
addbyte((uint8_t) cpu_state_offset(tag[cpu_state.TOP]));
addbyte(TAG_NOT_UINT64);
addbyte(0xde); /*FADD [ESP]*/
addbyte(0x04 | op);
addbyte(0x24);
addbyte(0xdd); /*FSTP ST[0][EBP]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
addbyte(0x64);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(TAG_NOT_UINT64);
addbyte(0xde); /*FADD [ESP]*/
addbyte(0x04 | op);
addbyte(0x24);
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
}
}
static __inline void
FP_OP_IL(int op)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[0][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0x80); /*AND tag[0][EBP], ~TAG_UINT64*/
addbyte(0x65);
addbyte((uint8_t) cpu_state_offset(tag[cpu_state.TOP]));
addbyte(TAG_NOT_UINT64);
addbyte(0xda); /*FADD [ESP]*/
addbyte(0x04 | op);
addbyte(0x24);
addbyte(0xdd); /*FSTP ST[0][EBP]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
addbyte(0x64);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(TAG_NOT_UINT64);
addbyte(0xda); /*FADD [ESP]*/
addbyte(0x04 | op);
addbyte(0x24);
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
}
}
#if 0
static __inline void FP_OP_IQ(int op)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP)
{
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x89); /*MOV [ESP+4], EDX*/
addbyte(0x54);
addbyte(0x24);
addbyte(0x04);
addbyte(0xdd); /*FLD ST[0][EBP]*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0x80); /*AND tag[0][EBP], ~TAG_UINT64*/
addbyte(0x65);
addbyte((uint8_t)cpu_state_offset(tag[cpu_state.TOP]));
addbyte(TAG_NOT_UINT64);
addbyte(0xdc); /*FADD [ESP]*/
addbyte(0x04 | op);
addbyte(0x24);
addbyte(0xdd); /*FSTP ST[0][EBP]*/
addbyte(0x5d);
addbyte((uint8_t)cpu_state_offset(ST[cpu_state.TOP]));
}
else
{
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t)cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x89); /*MOV [ESP+4], EDX*/
addbyte(0x54);
addbyte(0x24);
addbyte(0x04);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(ST));
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
addbyte(0x64);
addbyte(0x1d);
addbyte((uint8_t)cpu_state_offset(tag[0]));
addbyte(TAG_NOT_UINT64);
addbyte(0xdc); /*FADD [ESP]*/
addbyte(0x04 | op);
addbyte(0x24);
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(ST));
}
}
#endif
static __inline void
FP_COMPARE_S(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[0][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0x8a); /*MOV BL, [npxs+1]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0xdb); /*FCLEX*/
addbyte(0xe2);
addbyte(0x80); /*AND BL, ~(C0|C2|C3)*/
addbyte(0xe3);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
addbyte(0xd8); /*FCOMP [ESP]*/
addbyte(0x04 | 0x18);
addbyte(0x24);
addbyte(0xdf); /*FSTSW AX*/
addbyte(0xe0);
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR BL, AH*/
addbyte(0xe3);
addbyte(0x88); /*MOV [npxs+1], BL*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x8a); /*MOV BL, [npxs+1]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0xdb); /*FCLEX*/
addbyte(0xe2);
addbyte(0x80); /*AND BL, ~(C0|C2|C3)*/
addbyte(0xe3);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
addbyte(0xd8); /*FCOMP [ESP]*/
addbyte(0x04 | 0x18);
addbyte(0x24);
addbyte(0xdf); /*FSTSW AX*/
addbyte(0xe0);
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR BL, AH*/
addbyte(0xe3);
addbyte(0x88); /*MOV [npxs+1], BL*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
}
}
static __inline void
FP_COMPARE_D(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x89); /*MOV [ESP+4], EDX*/
addbyte(0x54);
addbyte(0x24);
addbyte(0x04);
addbyte(0xdd); /*FLD ST[0][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0x8a); /*MOV BL, [npxs+1]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0xdb); /*FCLEX*/
addbyte(0xe2);
addbyte(0x80); /*AND BL, ~(C0|C2|C3)*/
addbyte(0xe3);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
addbyte(0xdc); /*FCOMP [ESP]*/
addbyte(0x04 | 0x18);
addbyte(0x24);
addbyte(0xdf); /*FSTSW AX*/
addbyte(0xe0);
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR BL, AH*/
addbyte(0xe3);
addbyte(0x88); /*MOV [npxs+1], BL*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0x89); /*MOV [ESP+4], EDX*/
addbyte(0x54);
addbyte(0x24);
addbyte(0x04);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x8a); /*MOV BL, [npxs+1]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0xdb); /*FCLEX*/
addbyte(0xe2);
addbyte(0x80); /*AND BL, ~(C0|C2|C3)*/
addbyte(0xe3);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
addbyte(0xdc); /*FCOMP [ESP]*/
addbyte(0x04 | 0x18);
addbyte(0x24);
addbyte(0xdf); /*FSTSW AX*/
addbyte(0xe0);
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR BL, AH*/
addbyte(0xe3);
addbyte(0x88); /*MOV [npxs+1], BL*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
}
}
static __inline void
FP_COMPARE_IW(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x66); /*MOV [ESP], AX*/
addbyte(0x89);
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[0][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0x8a); /*MOV BL, [npxs+1]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0xdb); /*FCLEX*/
addbyte(0xe2);
addbyte(0x80); /*AND BL, ~(C0|C2|C3)*/
addbyte(0xe3);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
addbyte(0xde); /*FCOMP [ESP]*/
addbyte(0x04 | 0x18);
addbyte(0x24);
addbyte(0xdf); /*FSTSW AX*/
addbyte(0xe0);
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR BL, AH*/
addbyte(0xe3);
addbyte(0x88); /*MOV [npxs+1], BL*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x8a); /*MOV BL, [npxs+1]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0xdb); /*FCLEX*/
addbyte(0xe2);
addbyte(0x80); /*AND BL, ~(C0|C2|C3)*/
addbyte(0xe3);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
addbyte(0xde); /*FCOMP [ESP]*/
addbyte(0x04 | 0x18);
addbyte(0x24);
addbyte(0xdf); /*FSTSW AX*/
addbyte(0xe0);
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR BL, AH*/
addbyte(0xe3);
addbyte(0x88); /*MOV [npxs+1], BL*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
}
}
static __inline void
FP_COMPARE_IL(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[0][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0x8a); /*MOV BL, [npxs+1]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0xdb); /*FCLEX*/
addbyte(0xe2);
addbyte(0x80); /*AND BL, ~(C0|C2|C3)*/
addbyte(0xe3);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
addbyte(0xda); /*FCOMP [ESP]*/
addbyte(0x04 | 0x18);
addbyte(0x24);
addbyte(0xdf); /*FSTSW AX*/
addbyte(0xe0);
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR BL, AH*/
addbyte(0xe3);
addbyte(0x88); /*MOV [npxs+1], BL*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
} else {
addbyte(0x8b); /*MOV EBX, TOP*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV [ESP], EAX*/
addbyte(0x04);
addbyte(0x24);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x8a); /*MOV BL, [npxs+1]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0xdb); /*FCLEX*/
addbyte(0xe2);
addbyte(0x80); /*AND BL, ~(C0|C2|C3)*/
addbyte(0xe3);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
addbyte(0xda); /*FCOMP [ESP]*/
addbyte(0x04 | 0x18);
addbyte(0x24);
addbyte(0xdf); /*FSTSW AX*/
addbyte(0xe0);
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR BL, AH*/
addbyte(0xe3);
addbyte(0x88); /*MOV [npxs+1], BL*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
}
}
static __inline void
FP_OP_REG(int op, int dst, int src)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0xdd); /*FLD ST[dst][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP + dst) & 7]));
addbyte(0xdc); /*FADD ST[src][EBP]*/
addbyte(0x45 | op);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP + src) & 7]));
addbyte(0x80); /*AND tag[dst][EBP], ~TAG_UINT64*/
addbyte(0x65);
addbyte((uint8_t) cpu_state_offset(tag[(cpu_state.TOP + dst) & 7]));
addbyte(TAG_NOT_UINT64);
addbyte(0xdd); /*FSTP ST[dst][EBP]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP + dst) & 7]));
} else {
addbyte(0x8b); /*MOV EAX, TOP*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV EBX, EAX*/
addbyte(0xc3);
if (src || dst) {
addbyte(0x83); /*ADD EAX, 1*/
addbyte(0xc0);
addbyte(src ? src : dst);
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(7);
}
if (src) {
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
addbyte(0x64);
addbyte(0x1d);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(TAG_NOT_UINT64);
addbyte(0xdc); /*FADD ST[EAX*8]*/
addbyte(0x44 | op);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0xdd); /*FSTP ST[EBX*8]*/
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
} else {
addbyte(0xdd); /*FLD [ESI+EAX*8]*/
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x80); /*AND tag[EAX], ~TAG_UINT64*/
addbyte(0x64);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(TAG_NOT_UINT64);
addbyte(0xdc); /*FADD ST[EBX*8]*/
addbyte(0x44 | op);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0xdd); /*FSTP ST[EAX*8]*/
addbyte(0x5c);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
}
}
}
static __inline void
FP_COMPARE_REG(int dst, int src)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0x8a); /*MOV CL, [npxs+1]*/
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0xdb); /*FCLEX*/
addbyte(0xe2);
addbyte(0xdd); /*FLD ST[dst][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP + dst) & 7]));
addbyte(0x80); /*AND CL, ~(C0|C2|C3)*/
addbyte(0xe1);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
addbyte(0xdc); /*FCOMP ST[src][EBP]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(ST[(cpu_state.TOP + src) & 7]));
addbyte(0xdf); /*FSTSW AX*/
addbyte(0xe0);
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR CL, AH*/
addbyte(0xe1);
addbyte(0x88); /*MOV [npxs+1], CL*/
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
} else {
addbyte(0x8b); /*MOV EAX, TOP*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV EBX, EAX*/
addbyte(0xc3);
if (src || dst) {
addbyte(0x83); /*ADD EAX, 1*/
addbyte(0xc0);
addbyte(src ? src : dst);
addbyte(0x83); /*AND EAX, 7*/
addbyte(0xe0);
addbyte(7);
}
addbyte(0x8a); /*MOV CL, [npxs+1]*/
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
addbyte(0xdb); /*FCLEX*/
addbyte(0xe2);
addbyte(0x80); /*AND CL, ~(C0|C2|C3)*/
addbyte(0xe1);
addbyte((~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)) >> 8);
if (src) {
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0xdc); /*FCOMP ST[EAX*8]*/
addbyte(0x44 | 0x18);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
} else {
addbyte(0xdd); /*FLD [ESI+EAX*8]*/
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0xdc); /*FCOMP ST[EBX*8]*/
addbyte(0x44 | 0x18);
addbyte(0xdd);
addbyte((uint8_t) cpu_state_offset(ST));
}
addbyte(0xdf); /*FSTSW AX*/
addbyte(0xe0);
addbyte(0x80); /*AND AH, (C0|C2|C3)*/
addbyte(0xe4);
addbyte((FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3) >> 8);
addbyte(0x08); /*OR CL, AH*/
addbyte(0xe1);
addbyte(0x88); /*MOV [npxs+1], CL*/
addbyte(0x4d);
addbyte((uint8_t) cpu_state_offset(npxs) + 1);
}
}
static __inline void
FP_FCHS(void)
{
if (codeblock[block_current].flags & CODEBLOCK_STATIC_TOP) {
addbyte(0xdd); /*FLD ST[0][EBP]*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
addbyte(0xd9); /*FCHS*/
addbyte(0xe0);
addbyte(0x80); /*AND tag[dst][EBP], ~TAG_UINT64*/
addbyte(0x65);
addbyte((uint8_t) cpu_state_offset(tag[cpu_state.TOP]));
addbyte(TAG_NOT_UINT64);
addbyte(0xdd); /*FSTP ST[dst][EBP]*/
addbyte(0x5d);
addbyte((uint8_t) cpu_state_offset(ST[cpu_state.TOP]));
} else {
addbyte(0x8b); /*MOV EAX, TOP*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0xdd); /*FLD [ESI+EAX*8]*/
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
addbyte(0x80); /*AND tag[EAX], ~TAG_UINT64*/
addbyte(0x64);
addbyte(0x05);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(TAG_NOT_UINT64);
addbyte(0xd9); /*FCHS*/
addbyte(0xe0);
addbyte(0xdd); /*FSTP ST[EAX*8]*/
addbyte(0x5c);
addbyte(0xc5);
addbyte((uint8_t) cpu_state_offset(ST));
}
}
static __inline void
UPDATE_NPXC(int reg)
{
addbyte(0x66); /*AND cpu_state.new_npxc, ~0xc00*/
addbyte(0x81);
addbyte(0x65);
addbyte((uint8_t) cpu_state_offset(new_npxc));
addword(~0xc00);
if (reg) {
addbyte(0x66); /*AND reg, 0xc00*/
addbyte(0x81);
addbyte(0xe0 | reg);
addword(0xc00);
} else {
addbyte(0x66); /*AND AX, 0xc00*/
addbyte(0x25);
addword(0xc00);
}
addbyte(0x66); /*OR cpu_state.new_npxc, reg*/
addbyte(0x09);
addbyte(0x45 | (reg << 3));
addbyte((uint8_t) cpu_state_offset(new_npxc));
}
static __inline int
ZERO_EXTEND_W_B(int reg)
{
addbyte(0x0f); /*MOVZX regl, regb*/
addbyte(0xb6);
addbyte(0xc0 | reg | (reg << 3));
return reg;
}
static __inline int
ZERO_EXTEND_L_B(int reg)
{
addbyte(0x0f); /*MOVZX regl, regb*/
addbyte(0xb6);
addbyte(0xc0 | reg | (reg << 3));
return reg;
}
static __inline int
ZERO_EXTEND_L_W(int reg)
{
addbyte(0x0f); /*MOVZX regl, regw*/
addbyte(0xb7);
addbyte(0xc0 | reg | (reg << 3));
return reg;
}
static __inline int
SIGN_EXTEND_W_B(int reg)
{
addbyte(0x0f); /*MOVSX regl, regb*/
addbyte(0xbe);
addbyte(0xc0 | reg | (reg << 3));
return reg;
}
static __inline int
SIGN_EXTEND_L_B(int reg)
{
addbyte(0x0f); /*MOVSX regl, regb*/
addbyte(0xbe);
addbyte(0xc0 | reg | (reg << 3));
return reg;
}
static __inline int
SIGN_EXTEND_L_W(int reg)
{
addbyte(0x0f); /*MOVSX regl, regw*/
addbyte(0xbf);
addbyte(0xc0 | reg | (reg << 3));
return reg;
}
static __inline int
COPY_REG(int src_reg)
{
return src_reg;
}
static __inline void
SET_BITS(uintptr_t addr, uint32_t val)
{
if (val & ~0xff) {
addbyte(0x81);
addbyte(0x0d);
addlong(addr);
addlong(val);
} else {
addbyte(0x80);
addbyte(0x0d);
addlong(addr);
addbyte(val);
}
}
static __inline void
CLEAR_BITS(uintptr_t addr, uint32_t val)
{
if (val & ~0xff) {
addbyte(0x81);
addbyte(0x25);
addlong(addr);
addlong(~val);
} else {
addbyte(0x80);
addbyte(0x25);
addlong(addr);
addbyte(~val);
}
}
#define LOAD_Q_REG_1 REG_EAX
#define LOAD_Q_REG_2 REG_EDX
static __inline void
MMX_ENTER(void)
{
if (codegen_mmx_entered)
return;
addbyte(0xf6); /*TEST cr0, 0xc*/
addbyte(0x05);
addlong((uintptr_t) &cr0);
addbyte(0xc);
addbyte(0x74); /*JZ +*/
addbyte(7 + 7 + 5 + 5);
addbyte(0xC7); /*MOVL [oldpc],op_old_pc*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(oldpc));
addlong(op_old_pc);
addbyte(0xc7); /*MOV [ESP], 7*/
addbyte(0x04);
addbyte(0x24);
addlong(7);
addbyte(0xe8); /*CALL x86_int*/
addlong((uint32_t) x86_int - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
addbyte(0x31); /*XOR EAX, EAX*/
addbyte(0xc0);
addbyte(0xc6); /*MOV ISMMX, 1*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(ismmx));
addbyte(1);
addbyte(0x89); /*MOV TOP, EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(TOP));
addbyte(0x89); /*MOV tag, EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[0]));
addbyte(0x89); /*MOV tag+4, EAX*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(tag[4]));
codegen_mmx_entered = 1;
}
extern int mmx_ebx_ecx_loaded;
static __inline int
LOAD_MMX_D(int guest_reg)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = 100;
addbyte(0x8b); /*MOV EBX, reg*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].l[0]));
return host_reg;
}
static __inline void
LOAD_MMX_Q(int guest_reg, int *host_reg1, int *host_reg2)
{
if (!mmx_ebx_ecx_loaded) {
*host_reg1 = REG_EBX;
*host_reg2 = REG_ECX;
mmx_ebx_ecx_loaded = 1;
} else {
*host_reg1 = REG_EAX;
*host_reg2 = REG_EDX;
}
addbyte(0x8b); /*MOV EBX, reg*/
addbyte(0x45 | ((*host_reg1) << 3));
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].l[0]));
addbyte(0x8b); /*MOV ECX, reg+4*/
addbyte(0x45 | ((*host_reg2) << 3));
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].l[1]));
}
static __inline int
LOAD_MMX_Q_MMX(int guest_reg)
{
int dst_reg = find_host_xmm_reg();
host_reg_xmm_mapping[dst_reg] = guest_reg;
addbyte(0xf3); /*MOVQ dst_reg,[reg]*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0x45 | (dst_reg << 3));
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].q));
return dst_reg;
}
static __inline int
LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
{
int dst_reg = find_host_xmm_reg();
host_reg_xmm_mapping[dst_reg] = 100;
addbyte(0x66); /*MOVD dst_reg, src_reg1*/
addbyte(0x0f);
addbyte(0x6e);
addbyte(0xc0 | (dst_reg << 3) | src_reg1);
addbyte(0x66); /*MOVD XMM7, src_reg2*/
addbyte(0x0f);
addbyte(0x6e);
addbyte(0xc0 | (7 << 3) | src_reg2);
addbyte(0x66); /*PUNPCKLDQ dst_reg, XMM7*/
addbyte(0x0f);
addbyte(0x62);
addbyte(0xc0 | 7 | (dst_reg << 3));
return dst_reg;
}
static __inline void
STORE_MMX_LQ(int guest_reg, int host_reg1)
{
addbyte(0xC7); /*MOVL [reg],0*/
addbyte(0x45);
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].l[1]));
addlong(0);
addbyte(0x89); /*MOVL [reg],host_reg*/
addbyte(0x45 | (host_reg1 << 3));
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].l[0]));
}
static __inline void
STORE_MMX_Q(int guest_reg, int host_reg1, int host_reg2)
{
addbyte(0x89); /*MOVL [reg],host_reg*/
addbyte(0x45 | (host_reg1 << 3));
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].l[0]));
addbyte(0x89); /*MOVL [reg],host_reg*/
addbyte(0x45 | (host_reg2 << 3));
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].l[1]));
}
static __inline void
STORE_MMX_Q_MMX(int guest_reg, int host_reg)
{
addbyte(0x66); /*MOVQ [guest_reg],host_reg*/
addbyte(0x0f);
addbyte(0xd6);
addbyte(0x45 | (host_reg << 3));
addbyte((uint8_t) cpu_state_offset(MM[guest_reg].q));
}
#define MMX_x86_OP(name, opcode) \
static \
__inline void MMX_##name(int dst_reg, int src_reg) \
{ \
addbyte(0x66); /*op dst_reg, src_reg*/ \
addbyte(0x0f); \
addbyte(opcode); \
addbyte(0xc0 | (dst_reg << 3) | src_reg); \
}
// clang-format off
MMX_x86_OP(AND, 0xdb)
MMX_x86_OP(ANDN, 0xdf)
MMX_x86_OP(OR, 0xeb)
MMX_x86_OP(XOR, 0xef)
MMX_x86_OP(ADDB, 0xfc)
MMX_x86_OP(ADDW, 0xfd)
MMX_x86_OP(ADDD, 0xfe)
MMX_x86_OP(ADDSB, 0xec)
MMX_x86_OP(ADDSW, 0xed)
MMX_x86_OP(ADDUSB, 0xdc)
MMX_x86_OP(ADDUSW, 0xdd)
MMX_x86_OP(SUBB, 0xf8)
MMX_x86_OP(SUBW, 0xf9)
MMX_x86_OP(SUBD, 0xfa)
MMX_x86_OP(SUBSB, 0xe8)
MMX_x86_OP(SUBSW, 0xe9)
MMX_x86_OP(SUBUSB, 0xd8)
MMX_x86_OP(SUBUSW, 0xd9)
MMX_x86_OP(PUNPCKLBW, 0x60);
MMX_x86_OP(PUNPCKLWD, 0x61);
MMX_x86_OP(PUNPCKLDQ, 0x62);
MMX_x86_OP(PCMPGTB, 0x64);
MMX_x86_OP(PCMPGTW, 0x65);
MMX_x86_OP(PCMPGTD, 0x66);
MMX_x86_OP(PCMPEQB, 0x74);
MMX_x86_OP(PCMPEQW, 0x75);
MMX_x86_OP(PCMPEQD, 0x76);
MMX_x86_OP(PSRLW, 0xd1);
MMX_x86_OP(PSRLD, 0xd2);
MMX_x86_OP(PSRLQ, 0xd3);
MMX_x86_OP(PSRAW, 0xe1);
MMX_x86_OP(PSRAD, 0xe2);
MMX_x86_OP(PSLLW, 0xf1);
MMX_x86_OP(PSLLD, 0xf2);
MMX_x86_OP(PSLLQ, 0xf3);
MMX_x86_OP(PMULLW, 0xd5);
MMX_x86_OP(PMULHW, 0xe5);
MMX_x86_OP(PMADDWD, 0xf5);
// clang-format on
static __inline void
MMX_PACKSSWB(int dst_reg, int src_reg)
{
addbyte(0x66); /*PACKSSWB dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x63);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x08);
}
static __inline void
MMX_PACKUSWB(int dst_reg, int src_reg)
{
addbyte(0x66); /*PACKUSWB dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x67);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x08);
}
static __inline void
MMX_PACKSSDW(int dst_reg, int src_reg)
{
addbyte(0x66); /*PACKSSDW dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x6b);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x08);
}
static __inline void
MMX_PUNPCKHBW(int dst_reg, int src_reg)
{
addbyte(0x66); /*PUNPCKLBW dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x60);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x0e);
}
static __inline void
MMX_PUNPCKHWD(int dst_reg, int src_reg)
{
addbyte(0x66); /*PUNPCKLWD dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x61);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x0e);
}
static __inline void
MMX_PUNPCKHDQ(int dst_reg, int src_reg)
{
addbyte(0x66); /*PUNPCKLDQ dst_reg, src_reg*/
addbyte(0x0f);
addbyte(0x62);
addbyte(0xc0 | (dst_reg << 3) | src_reg);
addbyte(0x66); /*PSHUFD dst_reg, dst_reg*/
addbyte(0x0f);
addbyte(0x70);
addbyte(0xc0 | (dst_reg << 3) | dst_reg);
addbyte(0x0e);
}
static __inline void
MMX_PSRLW_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRLW dst_reg, amount*/
addbyte(0x0f);
addbyte(0x71);
addbyte(0xc0 | dst_reg | 0x10);
addbyte(amount);
}
static __inline void
MMX_PSRAW_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRAW dst_reg, amount*/
addbyte(0x0f);
addbyte(0x71);
addbyte(0xc0 | dst_reg | 0x20);
addbyte(amount);
}
static __inline void
MMX_PSLLW_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSLLW dst_reg, amount*/
addbyte(0x0f);
addbyte(0x71);
addbyte(0xc0 | dst_reg | 0x30);
addbyte(amount);
}
static __inline void
MMX_PSRLD_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRLD dst_reg, amount*/
addbyte(0x0f);
addbyte(0x72);
addbyte(0xc0 | dst_reg | 0x10);
addbyte(amount);
}
static __inline void
MMX_PSRAD_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRAD dst_reg, amount*/
addbyte(0x0f);
addbyte(0x72);
addbyte(0xc0 | dst_reg | 0x20);
addbyte(amount);
}
static __inline void
MMX_PSLLD_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSLLD dst_reg, amount*/
addbyte(0x0f);
addbyte(0x72);
addbyte(0xc0 | dst_reg | 0x30);
addbyte(amount);
}
static __inline void
MMX_PSRLQ_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRLQ dst_reg, amount*/
addbyte(0x0f);
addbyte(0x73);
addbyte(0xc0 | dst_reg | 0x10);
addbyte(amount);
}
static __inline void
MMX_PSRAQ_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSRAQ dst_reg, amount*/
addbyte(0x0f);
addbyte(0x73);
addbyte(0xc0 | dst_reg | 0x20);
addbyte(amount);
}
static __inline void
MMX_PSLLQ_imm(int dst_reg, int amount)
{
addbyte(0x66); /*PSLLQ dst_reg, amount*/
addbyte(0x0f);
addbyte(0x73);
addbyte(0xc0 | dst_reg | 0x30);
addbyte(amount);
}
static __inline void
SAVE_EA(void)
{
addbyte(0x89); /*MOV [ESP+12], EAX*/
addbyte(0x44);
addbyte(0x24);
addbyte(12);
}
static __inline void
LOAD_EA(void)
{
addbyte(0x8b); /*MOV EAX, [ESP+12]*/
addbyte(0x44);
addbyte(0x24);
addbyte(12);
}
#define MEM_CHECK_WRITE_B MEM_CHECK_WRITE
static __inline void
MEM_CHECK_WRITE(x86seg *seg)
{
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else {
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0xe8); /*CALL mem_check_write*/
addlong(mem_check_write - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
LOAD_EA();
}
static __inline void
MEM_CHECK_WRITE_W(x86seg *seg)
{
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else {
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0xe8); /*CALL mem_check_write_w*/
addlong(mem_check_write_w - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
LOAD_EA();
}
static __inline void
MEM_CHECK_WRITE_L(x86seg *seg)
{
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS))) {
addbyte(0x31); /*XOR ESI, ESI*/
addbyte(0xf6);
} else {
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t) &seg->base);
}
addbyte(0xe8); /*CALL mem_check_write_l*/
addlong(mem_check_write_l - (uint32_t) (&codeblock[block_current].data[block_pos + 4]));
LOAD_EA();
}
static __inline void
LOAD_SEG(int host_reg, void *seg)
{
addbyte(0xc7); /*MOV [ESP+4], seg*/
addbyte(0x44);
addbyte(0x24);
addbyte(4);
addlong((uint32_t) seg);
addbyte(0x89); /*MOV [ESP], host_reg*/
addbyte(0x04 | (host_reg << 3));
addbyte(0x24);
CALL_FUNC((uintptr_t) loadseg);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t) cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE end*/
addbyte(0x85);
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
}
``` | /content/code_sandbox/src/codegen/codegen_ops_x86.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 41,071 |
```c
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "cpu.h"
#include "x86.h"
#include "x86_ops.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "x87_sf.h"
#include "x87.h"
#include "386_common.h"
#include "cpu.h"
#include "codegen.h"
#include "codegen_ops.h"
#if defined __amd64__ || defined _M_X64
# include "codegen_ops_x86-64.h"
#elif defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
# include "codegen_ops_x86.h"
#endif
#include "codegen_ops_arith.h"
#include "codegen_ops_fpu.h"
#include "codegen_ops_jump.h"
#include "codegen_ops_logic.h"
#include "codegen_ops_misc.h"
#include "codegen_ops_mmx.h"
#include "codegen_ops_mov.h"
#include "codegen_ops_shift.h"
#include "codegen_ops_stack.h"
#include "codegen_ops_xchg.h"
RecompOpFn recomp_opcodes[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropADD_b_rmw, ropADD_w_rmw, ropADD_b_rm, ropADD_w_rm, ropADD_AL_imm, ropADD_AX_imm, ropPUSH_ES_16, ropPOP_ES_16, ropOR_b_rmw, ropOR_w_rmw, ropOR_b_rm, ropOR_w_rm, ropOR_AL_imm, ropOR_AX_imm, ropPUSH_CS_16, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_SS_16, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_DS_16, ropPOP_DS_16,
/*20*/ ropAND_b_rmw, ropAND_w_rmw, ropAND_b_rm, ropAND_w_rm, ropAND_AL_imm, ropAND_AX_imm, NULL, NULL, ropSUB_b_rmw, ropSUB_w_rmw, ropSUB_b_rm, ropSUB_w_rm, ropSUB_AL_imm, ropSUB_AX_imm, NULL, NULL,
/*30*/ ropXOR_b_rmw, ropXOR_w_rmw, ropXOR_b_rm, ropXOR_w_rm, ropXOR_AL_imm, ropXOR_AX_imm, NULL, NULL, ropCMP_b_rmw, ropCMP_w_rmw, ropCMP_b_rm, ropCMP_w_rm, ropCMP_AL_imm, ropCMP_AX_imm, NULL, NULL,
/*40*/ ropINC_rw, ropINC_rw, ropINC_rw, ropINC_rw, ropINC_rw, ropINC_rw, ropINC_rw, ropINC_rw, ropDEC_rw, ropDEC_rw, ropDEC_rw, ropDEC_rw, ropDEC_rw, ropDEC_rw, ropDEC_rw, ropDEC_rw,
/*50*/ ropPUSH_16, ropPUSH_16, ropPUSH_16, ropPUSH_16, ropPUSH_16, ropPUSH_16, ropPUSH_16, ropPUSH_16, ropPOP_16, ropPOP_16, ropPOP_16, ropPOP_16, ropPOP_16, ropPOP_16, ropPOP_16, ropPOP_16,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_imm_16, NULL, ropPUSH_imm_b16,NULL, NULL, NULL, NULL, NULL,
/*70*/ ropJO, ropJNO, ropJB, ropJNB, ropJE, ropJNE, ropJBE, ropJNBE, ropJS, ropJNS, ropJP, ropJNP, ropJL, ropJNL, ropJLE, ropJNLE,
/*80*/ rop80, rop81_w, rop80, rop83_w, ropTEST_b_rm, ropTEST_w_rm, ropXCHG_b, ropXCHG_w, ropMOV_b_r, ropMOV_w_r, ropMOV_r_b, ropMOV_r_w, ropMOV_w_seg, ropLEA_w, ropMOV_seg_w, NULL,
/*90*/ ropNOP, ropXCHG_AX_CX, ropXCHG_AX_DX, ropXCHG_AX_BX, ropXCHG_AX_SP, ropXCHG_AX_BP, ropXCHG_AX_SI, ropXCHG_AX_DI, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropMOV_AL_a, ropMOV_AX_a, ropMOV_a_AL, ropMOV_a_AX, NULL, NULL, NULL, NULL, ropTEST_AL_imm, ropTEST_AX_imm, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm,
/*c0*/ ropC0, ropC1_w, ropRET_imm_16, ropRET_16, ropLES, ropLDS, ropMOV_b_imm, ropMOV_w_imm, NULL, ropLEAVE_16, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ ropD0, ropD1_w, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, ropLOOP, ropJCXZ, NULL, NULL, NULL, NULL, ropCALL_r16, ropJMP_r16, NULL, ropJMP_r8, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, ropF6, ropF7_w, NULL, NULL, ropCLI, ropSTI, ropCLD, ropSTD, ropFE, ropFF_16,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropADD_b_rmw, ropADD_l_rmw, ropADD_b_rm, ropADD_l_rm, ropADD_AL_imm, ropADD_EAX_imm, ropPUSH_ES_32, ropPOP_ES_32, ropOR_b_rmw, ropOR_l_rmw, ropOR_b_rm, ropOR_l_rm, ropOR_AL_imm, ropOR_EAX_imm, ropPUSH_CS_32, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_SS_32, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_DS_32, ropPOP_DS_32,
/*20*/ ropAND_b_rmw, ropAND_l_rmw, ropAND_b_rm, ropAND_l_rm, ropAND_AL_imm, ropAND_EAX_imm, NULL, NULL, ropSUB_b_rmw, ropSUB_l_rmw, ropSUB_b_rm, ropSUB_l_rm, ropSUB_AL_imm, ropSUB_EAX_imm, NULL, NULL,
/*30*/ ropXOR_b_rmw, ropXOR_l_rmw, ropXOR_b_rm, ropXOR_l_rm, ropXOR_AL_imm, ropXOR_EAX_imm, NULL, NULL, ropCMP_b_rmw, ropCMP_l_rmw, ropCMP_b_rm, ropCMP_l_rm, ropCMP_AL_imm, ropCMP_EAX_imm, NULL, NULL,
/*40*/ ropINC_rl, ropINC_rl, ropINC_rl, ropINC_rl, ropINC_rl, ropINC_rl, ropINC_rl, ropINC_rl, ropDEC_rl, ropDEC_rl, ropDEC_rl, ropDEC_rl, ropDEC_rl, ropDEC_rl, ropDEC_rl, ropDEC_rl,
/*50*/ ropPUSH_32, ropPUSH_32, ropPUSH_32, ropPUSH_32, ropPUSH_32, ropPUSH_32, ropPUSH_32, ropPUSH_32, ropPOP_32, ropPOP_32, ropPOP_32, ropPOP_32, ropPOP_32, ropPOP_32, ropPOP_32, ropPOP_32,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_imm_32, NULL, ropPUSH_imm_b32,NULL, NULL, NULL, NULL, NULL,
/*70*/ ropJO, ropJNO, ropJB, ropJNB, ropJE, ropJNE, ropJBE, ropJNBE, ropJS, ropJNS, ropJP, ropJNP, ropJL, ropJNL, ropJLE, ropJNLE,
/*80*/ rop80, rop81_l, rop80, rop83_l, ropTEST_b_rm, ropTEST_l_rm, ropXCHG_b, ropXCHG_l, ropMOV_b_r, ropMOV_l_r, ropMOV_r_b, ropMOV_r_l, ropMOV_w_seg, ropLEA_l, ropMOV_seg_w, NULL,
/*90*/ ropNOP, ropXCHG_EAX_ECX,ropXCHG_EAX_EDX,ropXCHG_EAX_EBX,ropXCHG_EAX_ESP,ropXCHG_EAX_EBP,ropXCHG_EAX_ESI,ropXCHG_EAX_EDI,NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropMOV_AL_a, ropMOV_EAX_a, ropMOV_a_AL, ropMOV_a_EAX, NULL, NULL, NULL, NULL, ropTEST_AL_imm, ropTEST_EAX_imm,NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm,
/*c0*/ ropC0, ropC1_l, ropRET_imm_32, ropRET_32, ropLES, ropLDS, ropMOV_b_imm, ropMOV_l_imm, NULL, ropLEAVE_32, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ ropD0, ropD1_l, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, ropLOOP, ropJCXZ, NULL, NULL, NULL, NULL, ropCALL_r32, ropJMP_r32, NULL, ropJMP_r8, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, ropF6, ropF7_l, NULL, NULL, ropCLI, ropSTI, ropCLD, ropSTD, ropFE, ropFF_32
// clang-format on
};
RecompOpFn recomp_opcodes_0f[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ ropPUNPCKLBW, ropPUNPCKLWD, ropPUNPCKLDQ, ropPACKSSWB, ropPCMPGTB, ropPCMPGTW, ropPCMPGTD, ropPACKUSWB, ropPUNPCKHBW, ropPUNPCKHWD, ropPUNPCKHDQ, ropPACKSSDW, NULL, NULL, ropMOVD_mm_l, ropMOVQ_mm_q,
/*70*/ NULL, ropPSxxW_imm, ropPSxxD_imm, ropPSxxQ_imm, ropPCMPEQB, ropPCMPEQW, ropPCMPEQD, ropEMMS, NULL, NULL, NULL, NULL, NULL, NULL, ropMOVD_l_mm, ropMOVQ_q_mm,
/*80*/ ropJO_w, ropJNO_w, ropJB_w, ropJNB_w, ropJE_w, ropJNE_w, ropJBE_w, ropJNBE_w, ropJS_w, ropJNS_w, ropJP_w, ropJNP_w, ropJL_w, ropJNL_w, ropJLE_w, ropJNLE_w,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropPUSH_FS_16, ropPOP_FS_16, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_GS_16, ropPOP_GS_16, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, ropLSS, NULL, ropLFS, ropLGS, ropMOVZX_w_b, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropMOVSX_w_b, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, ropPSRLW, ropPSRLD, ropPSRLQ, NULL, ropPMULLW, NULL, NULL, ropPSUBUSB, ropPSUBUSW, NULL, ropPAND, ropPADDUSB, ropPADDUSW, NULL, ropPANDN,
/*e0*/ NULL, ropPSRAW, ropPSRAD, NULL, NULL, ropPMULHW, NULL, NULL, ropPSUBSB, ropPSUBSW, NULL, ropPOR, ropPADDSB, ropPADDSW, NULL, ropPXOR,
/*f0*/ NULL, ropPSLLW, ropPSLLD, ropPSLLQ, NULL, ropPMADDWD, NULL, NULL, ropPSUBB, ropPSUBW, ropPSUBD, NULL, ropPADDB, ropPADDW, ropPADDD, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ ropPUNPCKLBW, ropPUNPCKLWD, ropPUNPCKLDQ, ropPACKSSWB, ropPCMPGTB, ropPCMPGTW, ropPCMPGTD, ropPACKUSWB, ropPUNPCKHBW, ropPUNPCKHWD, ropPUNPCKHDQ, ropPACKSSDW, NULL, NULL, ropMOVD_mm_l, ropMOVQ_mm_q,
/*70*/ NULL, ropPSxxW_imm, ropPSxxD_imm, ropPSxxQ_imm, ropPCMPEQB, ropPCMPEQW, ropPCMPEQD, ropEMMS, NULL, NULL, NULL, NULL, NULL, NULL, ropMOVD_l_mm, ropMOVQ_q_mm,
/*80*/ ropJO_l, ropJNO_l, ropJB_l, ropJNB_l, ropJE_l, ropJNE_l, ropJBE_l, ropJNBE_l, ropJS_l, ropJNS_l, ropJP_l, ropJNP_l, ropJL_l, ropJNL_l, ropJLE_l, ropJNLE_l,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropPUSH_FS_32, ropPOP_FS_32, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_GS_32, ropPOP_GS_32, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, ropLSS, NULL, ropLFS, ropLGS, ropMOVZX_l_b, ropMOVZX_l_w, NULL, NULL, NULL, NULL, NULL, NULL, ropMOVSX_l_b, ropMOVSX_l_w,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, ropPSRLW, ropPSRLD, ropPSRLQ, NULL, ropPMULLW, NULL, NULL, ropPSUBUSB, ropPSUBUSW, NULL, ropPAND, ropPADDUSB, ropPADDUSW, NULL, ropPANDN,
/*e0*/ NULL, ropPSRAW, ropPSRAD, NULL, NULL, ropPMULHW, NULL, NULL, ropPSUBSB, ropPSUBSW, NULL, ropPOR, ropPADDSB, ropPADDSW, NULL, ropPXOR,
/*f0*/ NULL, ropPSLLW, ropPSLLD, ropPSLLQ, NULL, ropPMADDWD, NULL, NULL, ropPSUBB, ropPSUBW, ropPSUBD, NULL, ropPADDB, ropPADDW, ropPADDD, NULL,
// clang-format on
};
RecompOpFn recomp_opcodes_0f_no_mmx[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ ropJO_w, ropJNO_w, ropJB_w, ropJNB_w, ropJE_w, ropJNE_w, ropJBE_w, ropJNBE_w, ropJS_w, ropJNS_w, ropJP_w, ropJNP_w, ropJL_w, ropJNL_w, ropJLE_w, ropJNLE_w,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropPUSH_FS_16, ropPOP_FS_16, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_GS_16, ropPOP_GS_16, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, ropLSS, NULL, ropLFS, ropLGS, ropMOVZX_w_b, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropMOVSX_w_b, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ ropJO_l, ropJNO_l, ropJB_l, ropJNB_l, ropJE_l, ropJNE_l, ropJBE_l, ropJNBE_l, ropJS_l, ropJNS_l, ropJP_l, ropJNP_l, ropJL_l, ropJNL_l, ropJLE_l, ropJNLE_l,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropPUSH_FS_32, ropPOP_FS_32, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_GS_32, ropPOP_GS_32, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, ropLSS, NULL, ropLFS, ropLGS, ropMOVZX_l_b, ropMOVZX_l_w, NULL, NULL, NULL, NULL, NULL, NULL, ropMOVSX_l_b, ropMOVSX_l_w,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
// clang-format on
};
RecompOpFn recomp_opcodes_d8[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs,
/*10*/ ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs,
/*20*/ ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs,
/*30*/ ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs,
/*40*/ ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs,
/*50*/ ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs,
/*60*/ ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs,
/*70*/ ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs,
/*80*/ ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs,
/*90*/ ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs,
/*a0*/ ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs,
/*b0*/ ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs,
/*c0*/ ropFADD, ropFADD, ropFADD, ropFADD, ropFADD, ropFADD, ropFADD, ropFADD, ropFMUL, ropFMUL, ropFMUL, ropFMUL, ropFMUL, ropFMUL, ropFMUL, ropFMUL,
/*d0*/ ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP,
/*e0*/ ropFSUB, ropFSUB, ropFSUB, ropFSUB, ropFSUB, ropFSUB, ropFSUB, ropFSUB, ropFSUBR, ropFSUBR, ropFSUBR, ropFSUBR, ropFSUBR, ropFSUBR, ropFSUBR, ropFSUBR,
/*f0*/ ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs,
/*10*/ ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs,
/*20*/ ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs,
/*30*/ ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs,
/*40*/ ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs,
/*50*/ ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs,
/*60*/ ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs,
/*70*/ ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs,
/*80*/ ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs,
/*90*/ ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs,
/*a0*/ ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs,
/*b0*/ ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs, ropFDIVRs,
/*c0*/ ropFADD, ropFADD, ropFADD, ropFADD, ropFADD, ropFADD, ropFADD, ropFADD, ropFMUL, ropFMUL, ropFMUL, ropFMUL, ropFMUL, ropFMUL, ropFMUL, ropFMUL,
/*d0*/ ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP,
/*e0*/ ropFSUB, ropFSUB, ropFSUB, ropFSUB, ropFSUB, ropFSUB, ropFSUB, ropFSUB, ropFSUBR, ropFSUBR, ropFSUBR, ropFSUBR, ropFSUBR, ropFSUBR, ropFSUBR, ropFSUBR,
/*f0*/ ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR,
// clang-format on
};
RecompOpFn recomp_opcodes_d9[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW,
/*40*/ ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW,
/*80*/ ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW,
/*c0*/ ropFLD, ropFLD, ropFLD, ropFLD, ropFLD, ropFLD, ropFLD, ropFLD, ropFXCH, ropFXCH, ropFXCH, ropFXCH, ropFXCH, ropFXCH, ropFXCH, ropFXCH,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ ropFCHS, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLD1, ropFLDL2T, ropFLDL2E, ropFLDPI, ropFLDEG2, ropFLDLN2, ropFLDZ, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW,
/*40*/ ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW,
/*80*/ ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW, ropFSTCW,
/*c0*/ ropFLD, ropFLD, ropFLD, ropFLD, ropFLD, ropFLD, ropFLD, ropFLD, ropFXCH, ropFXCH, ropFXCH, ropFXCH, ropFXCH, ropFXCH, ropFXCH, ropFXCH,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ ropFCHS, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLD1, ropFLDL2T, ropFLDL2E, ropFLDPI, ropFLDEG2, ropFLDLN2, ropFLDZ, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
// clang-format on
};
RecompOpFn recomp_opcodes_da[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil,
/*10*/ ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil,
/*20*/ ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil,
/*30*/ ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil,
/*40*/ ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil,
/*50*/ ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil,
/*60*/ ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil,
/*70*/ ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil,
/*80*/ ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil,
/*90*/ ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil,
/*a0*/ ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil,
/*b0*/ ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil,
/*10*/ ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil,
/*20*/ ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil,
/*30*/ ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil,
/*40*/ ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil,
/*50*/ ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil,
/*60*/ ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil,
/*70*/ ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil,
/*80*/ ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil,
/*90*/ ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil,
/*a0*/ ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil,
/*b0*/ ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil, ropFDIVRil,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
// clang-format on
};
RecompOpFn recomp_opcodes_db[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*80*/ ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
// clang-format on
};
RecompOpFn recomp_opcodes_dc[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd,
/*10*/ ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd,
/*20*/ ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd,
/*30*/ ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd,
/*40*/ ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd,
/*50*/ ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd,
/*60*/ ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd,
/*70*/ ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd,
/*80*/ ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd,
/*90*/ ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd,
/*a0*/ ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd,
/*b0*/ ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd,
/*c0*/ ropFADDr, ropFADDr, ropFADDr, ropFADDr, ropFADDr, ropFADDr, ropFADDr, ropFADDr, ropFMULr, ropFMULr, ropFMULr, ropFMULr, ropFMULr, ropFMULr, ropFMULr, ropFMULr,
/*d0*/ ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP,
/*e0*/ ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBr, ropFSUBr, ropFSUBr, ropFSUBr, ropFSUBr, ropFSUBr, ropFSUBr, ropFSUBr,
/*f0*/ ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd,
/*10*/ ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd,
/*20*/ ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd,
/*30*/ ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd,
/*40*/ ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd,
/*50*/ ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd,
/*60*/ ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd,
/*70*/ ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd,
/*80*/ ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd,
/*90*/ ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd,
/*a0*/ ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd,
/*b0*/ ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd, ropFDIVRd,
/*c0*/ ropFADDr, ropFADDr, ropFADDr, ropFADDr, ropFADDr, ropFADDr, ropFADDr, ropFADDr, ropFMULr, ropFMULr, ropFMULr, ropFMULr, ropFMULr, ropFMULr, ropFMULr, ropFMULr,
/*d0*/ ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOM, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP, ropFCOMP,
/*e0*/ ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBRr, ropFSUBr, ropFSUBr, ropFSUBr, ropFSUBr, ropFSUBr, ropFSUBr, ropFSUBr, ropFSUBr,
/*f0*/ ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr,
// clang-format on
};
RecompOpFn recomp_opcodes_dd[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ ropFST, ropFST, ropFST, ropFST, ropFST, ropFST, ropFST, ropFST, ropFSTP, ropFSTP, ropFSTP, ropFSTP, ropFSTP, ropFSTP, ropFSTP, ropFSTP,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ ropFST, ropFST, ropFST, ropFST, ropFST, ropFST, ropFST, ropFST, ropFSTP, ropFSTP, ropFSTP, ropFSTP, ropFSTP, ropFSTP, ropFSTP, ropFSTP,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
// clang-format on
};
RecompOpFn recomp_opcodes_de[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw,
/*10*/ ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw,
/*20*/ ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw,
/*30*/ ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw,
/*40*/ ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw,
/*50*/ ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw,
/*60*/ ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw,
/*70*/ ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw,
/*80*/ ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw,
/*90*/ ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw,
/*a0*/ ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw,
/*b0*/ ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw,
/*c0*/ ropFADDP, ropFADDP, ropFADDP, ropFADDP, ropFADDP, ropFADDP, ropFADDP, ropFADDP, ropFMULP, ropFMULP, ropFMULP, ropFMULP, ropFMULP, ropFMULP, ropFMULP, ropFMULP,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFCOMPP, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBP, ropFSUBP, ropFSUBP, ropFSUBP, ropFSUBP, ropFSUBP, ropFSUBP, ropFSUBP,
/*f0*/ ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw,
/*10*/ ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw,
/*20*/ ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw,
/*30*/ ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw,
/*40*/ ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw,
/*50*/ ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw,
/*60*/ ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw,
/*70*/ ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw,
/*80*/ ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw,
/*90*/ ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw,
/*a0*/ ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw,
/*b0*/ ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIViw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw, ropFDIVRiw,
/*c0*/ ropFADDP, ropFADDP, ropFADDP, ropFADDP, ropFADDP, ropFADDP, ropFADDP, ropFADDP, ropFMULP, ropFMULP, ropFMULP, ropFMULP, ropFMULP, ropFMULP, ropFMULP, ropFMULP,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFCOMPP, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBRP, ropFSUBP, ropFSUBP, ropFSUBP, ropFSUBP, ropFSUBP, ropFSUBP, ropFSUBP, ropFSUBP,
/*f0*/ ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP,
// clang-format on
};
RecompOpFn recomp_opcodes_df[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq,
/*40*/ ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq,
/*80*/ ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ ropFSTSW_AX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq,
/*40*/ ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq,
/*80*/ ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq, ropFISTPq,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ ropFSTSW_AX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
// clang-format on
};
RecompOpFn recomp_opcodes_REPE[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
// clang-format on
};
RecompOpFn recomp_opcodes_REPNE[512] = {
// clang-format off
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
// clang-format on
};
``` | /content/code_sandbox/src/codegen/codegen_ops.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 33,791 |
```objective-c
static uint32_t
ropJMP_r8(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t offset = fetchdat & 0xff;
if (offset & 0x80)
offset |= 0xffffff00;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.pc, op_pc + 1 + offset);
return -1;
}
static uint32_t
ropJMP_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint16_t offset = fetchdat & 0xffff;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.pc, (op_pc + 2 + offset) & 0xffff);
return -1;
}
static uint32_t
ropJMP_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t offset = fastreadl(cs + op_pc);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.pc, op_pc + 4 + offset);
return -1;
}
static uint32_t
ropJCXZ(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t offset = fetchdat & 0xff;
if (offset & 0x80)
offset |= 0xffffff00;
if (op_32 & 0x200) {
int host_reg = LOAD_REG_L(REG_ECX);
TEST_ZERO_JUMP_L(host_reg, op_pc + 1 + offset, 0);
} else {
int host_reg = LOAD_REG_W(REG_CX);
TEST_ZERO_JUMP_W(host_reg, op_pc + 1 + offset, 0);
}
return op_pc + 1;
}
static uint32_t
ropLOOP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t offset = fetchdat & 0xff;
if (offset & 0x80)
offset |= 0xffffff00;
if (op_32 & 0x200) {
int host_reg = LOAD_REG_L(REG_ECX);
SUB_HOST_REG_IMM(host_reg, 1);
STORE_REG_L_RELEASE(host_reg);
TEST_NONZERO_JUMP_L(host_reg, op_pc + 1 + offset, 0);
} else {
int host_reg = LOAD_REG_W(REG_CX);
SUB_HOST_REG_IMM(host_reg, 1);
STORE_REG_W_RELEASE(host_reg);
TEST_NONZERO_JUMP_W(host_reg, op_pc + 1 + offset, 0);
}
return op_pc + 1;
}
static void
BRANCH_COND_B(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
{
CALL_FUNC((uintptr_t) CF_SET);
if (not )
TEST_ZERO_JUMP_L(0, op_pc + pc_offset + offset, timing_bt);
else
TEST_NONZERO_JUMP_L(0, op_pc + pc_offset + offset, timing_bt);
}
static void
BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
{
int host_reg;
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
case FLAGS_ZN16:
case FLAGS_ZN32:
case FLAGS_ADD8:
case FLAGS_ADD16:
case FLAGS_ADD32:
case FLAGS_SUB8:
case FLAGS_SUB16:
case FLAGS_SUB32:
case FLAGS_SHL8:
case FLAGS_SHL16:
case FLAGS_SHL32:
case FLAGS_SHR8:
case FLAGS_SHR16:
case FLAGS_SHR32:
case FLAGS_SAR8:
case FLAGS_SAR16:
case FLAGS_SAR32:
case FLAGS_INC8:
case FLAGS_INC16:
case FLAGS_INC32:
case FLAGS_DEC8:
case FLAGS_DEC16:
case FLAGS_DEC32:
host_reg = LOAD_VAR_L((uintptr_t) &cpu_state.flags_res);
if (not )
TEST_NONZERO_JUMP_L(host_reg, op_pc + pc_offset + offset, timing_bt);
else
TEST_ZERO_JUMP_L(host_reg, op_pc + pc_offset + offset, timing_bt);
break;
case FLAGS_UNKNOWN:
CALL_FUNC((uintptr_t) ZF_SET);
if (not )
TEST_ZERO_JUMP_L(0, op_pc + pc_offset + offset, timing_bt);
else
TEST_NONZERO_JUMP_L(0, op_pc + pc_offset + offset, timing_bt);
break;
}
}
static void
BRANCH_COND_O(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
{
CALL_FUNC((uintptr_t) VF_SET);
if (not )
TEST_ZERO_JUMP_L(0, op_pc + pc_offset + offset, timing_bt);
else
TEST_NONZERO_JUMP_L(0, op_pc + pc_offset + offset, timing_bt);
}
static void
BRANCH_COND_P(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
{
CALL_FUNC((uintptr_t) PF_SET);
if (not )
TEST_ZERO_JUMP_L(0, op_pc + pc_offset + offset, timing_bt);
else
TEST_NONZERO_JUMP_L(0, op_pc + pc_offset + offset, timing_bt);
}
static void
BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
{
int host_reg;
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
case FLAGS_ADD8:
case FLAGS_SUB8:
case FLAGS_SHL8:
case FLAGS_SHR8:
case FLAGS_SAR8:
case FLAGS_INC8:
case FLAGS_DEC8:
host_reg = LOAD_VAR_L((uintptr_t) &cpu_state.flags_res);
AND_HOST_REG_IMM(host_reg, 0x80);
if (not )
TEST_ZERO_JUMP_L(host_reg, op_pc + pc_offset + offset, timing_bt);
else
TEST_NONZERO_JUMP_L(host_reg, op_pc + pc_offset + offset, timing_bt);
break;
case FLAGS_ZN16:
case FLAGS_ADD16:
case FLAGS_SUB16:
case FLAGS_SHL16:
case FLAGS_SHR16:
case FLAGS_SAR16:
case FLAGS_INC16:
case FLAGS_DEC16:
host_reg = LOAD_VAR_L((uintptr_t) &cpu_state.flags_res);
AND_HOST_REG_IMM(host_reg, 0x8000);
if (not )
TEST_ZERO_JUMP_L(host_reg, op_pc + pc_offset + offset, timing_bt);
else
TEST_NONZERO_JUMP_L(host_reg, op_pc + pc_offset + offset, timing_bt);
break;
case FLAGS_ZN32:
case FLAGS_ADD32:
case FLAGS_SUB32:
case FLAGS_SHL32:
case FLAGS_SHR32:
case FLAGS_SAR32:
case FLAGS_INC32:
case FLAGS_DEC32:
host_reg = LOAD_VAR_L((uintptr_t) &cpu_state.flags_res);
AND_HOST_REG_IMM(host_reg, 0x80000000);
if (not )
TEST_ZERO_JUMP_L(host_reg, op_pc + pc_offset + offset, timing_bt);
else
TEST_NONZERO_JUMP_L(host_reg, op_pc + pc_offset + offset, timing_bt);
break;
case FLAGS_UNKNOWN:
CALL_FUNC((uintptr_t) NF_SET);
if (not )
TEST_ZERO_JUMP_L(0, op_pc + pc_offset + offset, timing_bt);
else
TEST_NONZERO_JUMP_L(0, op_pc + pc_offset + offset, timing_bt);
break;
}
}
#define ropBRANCH(name, func, not ) \
static uint32_t \
rop##name(uint8_t opcode, uint32_t fetchdat, \
uint32_t op_32, uint32_t op_pc, \
codeblock_t *block) \
{ \
uint32_t offset = fetchdat & 0xff; \
\
if (offset & 0x80) \
offset |= 0xffffff00; \
\
func(1, op_pc, offset, not ); \
\
return op_pc + 1; \
} \
static uint32_t \
rop##name##_w(uint8_t opcode, \
uint32_t fetchdat, uint32_t op_32, \
uint32_t op_pc, codeblock_t *block) \
{ \
uint32_t offset = fetchdat & 0xffff; \
\
if (offset & 0x8000) \
offset |= 0xffff0000; \
\
func(2, op_pc, offset, not ); \
\
return op_pc + 2; \
} \
static uint32_t \
rop##name##_l(uint8_t opcode, \
uint32_t fetchdat, uint32_t op_32, \
uint32_t op_pc, codeblock_t *block) \
{ \
uint32_t offset = fastreadl(cs + op_pc); \
\
func(4, op_pc, offset, not ); \
\
return op_pc + 4; \
}
// clang-format off
ropBRANCH(JB, BRANCH_COND_B, 0)
ropBRANCH(JNB, BRANCH_COND_B, 1)
ropBRANCH(JE, BRANCH_COND_E, 0)
ropBRANCH(JNE, BRANCH_COND_E, 1)
ropBRANCH(JO, BRANCH_COND_O, 0)
ropBRANCH(JNO, BRANCH_COND_O, 1)
ropBRANCH(JP, BRANCH_COND_P, 0)
ropBRANCH(JNP, BRANCH_COND_P, 1)
ropBRANCH(JS, BRANCH_COND_S, 0)
ropBRANCH(JNS, BRANCH_COND_S, 1)
ropBRANCH(JL, BRANCH_COND_L, 0)
ropBRANCH(JNL, BRANCH_COND_L, 1)
ropBRANCH(JLE, BRANCH_COND_LE, 0)
ropBRANCH(JNLE, BRANCH_COND_LE, 1)
ropBRANCH(JBE, BRANCH_COND_BE, 0)
ropBRANCH(JNBE, BRANCH_COND_BE, 1)
// clang-format on
``` | /content/code_sandbox/src/codegen/codegen_ops_jump.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,351 |
```c
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include "cpu.h"
#include "x86_ops.h"
#include "codegen.h"
void (*codegen_timing_start)(void);
void (*codegen_timing_prefix)(uint8_t prefix, uint32_t fetchdat);
void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
void (*codegen_timing_block_start)(void);
void (*codegen_timing_block_end)(void);
int (*codegen_timing_jump_cycles)(void);
void
codegen_timing_set(codegen_timing_t *timing)
{
codegen_timing_start = timing->start;
codegen_timing_prefix = timing->prefix;
codegen_timing_opcode = timing->opcode;
codegen_timing_block_start = timing->block_start;
codegen_timing_block_end = timing->block_end;
codegen_timing_jump_cycles = timing->jump_cycles;
}
int codegen_in_recompile;
/* This is for compatibility with new x87 code. */
void
codegen_set_rounding_mode(int mode)
{
#if 0
cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00) | (cpu_state.npxc & 0xc00);
#endif
cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00) | (mode << 10);
}
``` | /content/code_sandbox/src/codegen/codegen.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 318 |
```objective-c
static uint32_t
ropFXCH(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_FXCH(opcode & 7);
return op_pc;
}
static uint32_t
ropFLD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_FLD(opcode & 7);
return op_pc;
}
static uint32_t
ropFST(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_FST(opcode & 7);
return op_pc;
}
static uint32_t
ropFSTP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_FST(opcode & 7);
FP_POP();
return op_pc;
}
static uint32_t
ropFLDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
FP_LOAD_S();
return op_pc + 1;
}
static uint32_t
ropFLDd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_Q(target_seg);
FP_LOAD_D();
return op_pc + 1;
}
static uint32_t
ropFILDw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
FP_LOAD_IW();
return op_pc + 1;
}
static uint32_t
ropFILDl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
FP_LOAD_IL();
return op_pc + 1;
}
static uint32_t
ropFILDq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_Q(target_seg);
FP_LOAD_IQ();
codegen_fpu_loaded_iq[(cpu_state.TOP - 1) & 7] = 1;
return op_pc + 1;
}
static uint32_t
ropFSTs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
int host_reg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
host_reg = FP_LOAD_REG(0);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
return op_pc + 1;
}
static uint32_t
ropFSTd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
int host_reg1;
int host_reg2 = 0;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
FP_LOAD_REG_D(0, &host_reg1, &host_reg2);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 7);
MEM_STORE_ADDR_EA_Q(target_seg, host_reg1, host_reg2);
return op_pc + 1;
}
static uint32_t
ropFSTPs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFSTs(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
static uint32_t
ropFSTPd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFSTd(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
#define ropFarith(name, size, load, op) \
static uint32_t \
ropF##name##size(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
x86seg *target_seg; \
\
FP_ENTER(); \
op_pc--; \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
\
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
\
CHECK_SEG_READ(target_seg); \
load(target_seg); \
\
op(FPU_##name); \
\
return op_pc + 1; \
}
ropFarith(ADD, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(DIV, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(DIVR, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(MUL, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(SUB, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(SUBR, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(ADD, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(DIV, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(DIVR, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(MUL, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(SUB, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(SUBR, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(ADD, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(DIV, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(DIVR, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(MUL, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(SUB, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(SUBR, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(ADD, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(DIV, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(DIVR, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(MUL, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(SUB, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(SUBR, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
#define ropFcompare(name, size, load, op) \
static uint32_t \
ropF##name##size(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
x86seg *target_seg; \
\
FP_ENTER(); \
op_pc--; \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
\
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
\
CHECK_SEG_READ(target_seg); \
load(target_seg); \
\
op(); \
\
return op_pc + 1; \
} \
static uint32_t ropF##name##P##size(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
uint32_t new_pc = ropF##name##size(opcode, fetchdat, op_32, op_pc, block); \
\
FP_POP(); \
\
return new_pc; \
}
ropFcompare(COM, s, MEM_LOAD_ADDR_EA_L, FP_COMPARE_S);
ropFcompare(COM, d, MEM_LOAD_ADDR_EA_Q, FP_COMPARE_D);
ropFcompare(COM, iw, MEM_LOAD_ADDR_EA_W, FP_COMPARE_IW);
ropFcompare(COM, il, MEM_LOAD_ADDR_EA_L, FP_COMPARE_IL);
#if 0
static uint32_t
ropFADDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
FP_OP_S(FPU_ADD);
return op_pc + 1;
}
static uint32_t
ropFDIVs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
FP_OP_S(FPU_DIV);
return op_pc + 1;
}
static uint32_t
ropFMULs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
FP_OP_S(FPU_MUL);
return op_pc + 1;
}
static uint32_t
ropFSUBs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
FP_OP_S(FPU_SUB);
return op_pc + 1;
}
#endif
static uint32_t
ropFADD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_ADD, 0, opcode & 7);
return op_pc;
}
static uint32_t
ropFCOM(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_COMPARE_REG(0, opcode & 7);
return op_pc;
}
static uint32_t
ropFDIV(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIV, 0, opcode & 7);
return op_pc;
}
static uint32_t
ropFDIVR(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIVR, 0, opcode & 7);
return op_pc;
}
static uint32_t
ropFMUL(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_MUL, 0, opcode & 7);
return op_pc;
}
static uint32_t
ropFSUB(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUB, 0, opcode & 7);
return op_pc;
}
static uint32_t
ropFSUBR(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUBR, 0, opcode & 7);
return op_pc;
}
static uint32_t
ropFADDr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_ADD, opcode & 7, 0);
return op_pc;
}
static uint32_t
ropFDIVr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIV, opcode & 7, 0);
return op_pc;
}
static uint32_t
ropFDIVRr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIVR, opcode & 7, 0);
return op_pc;
}
static uint32_t
ropFMULr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_MUL, opcode & 7, 0);
return op_pc;
}
static uint32_t
ropFSUBr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUB, opcode & 7, 0);
return op_pc;
}
static uint32_t
ropFSUBRr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUBR, opcode & 7, 0);
return op_pc;
}
static uint32_t
ropFADDP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_ADD, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t
ropFCOMP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_COMPARE_REG(0, opcode & 7);
FP_POP();
return op_pc;
}
static uint32_t
ropFDIVP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIV, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t
ropFDIVRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIVR, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t
ropFMULP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_MUL, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t
ropFSUBP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUB, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t
ropFSUBRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUBR, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t
ropFCOMPP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_COMPARE_REG(0, 1);
FP_POP2();
return op_pc;
}
static uint32_t
ropFSTSW_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
FP_ENTER();
host_reg = LOAD_VAR_W((uintptr_t) &cpu_state.npxs);
STORE_REG_TARGET_W_RELEASE(host_reg, REG_AX);
return op_pc;
}
static uint32_t
ropFISTw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
int host_reg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
host_reg = FP_LOAD_REG_INT_W(0);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
return op_pc + 1;
}
static uint32_t
ropFISTl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
int host_reg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
host_reg = FP_LOAD_REG_INT(0);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
return op_pc + 1;
}
static uint32_t
ropFISTPw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFISTw(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
static uint32_t
ropFISTPl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFISTl(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
static uint32_t
ropFISTPq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
int host_reg1;
int host_reg2;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
FP_LOAD_REG_INT_Q(0, &host_reg1, &host_reg2);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_Q(target_seg, host_reg1, host_reg2);
FP_POP();
return op_pc + 1;
}
static uint32_t
ropFLDCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
STORE_HOST_REG_ADDR_W((uintptr_t) &cpu_state.npxc, 0);
UPDATE_NPXC(0);
return op_pc + 1;
}
static uint32_t
ropFSTCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
CHECK_SEG_WRITE(target_seg);
host_reg = LOAD_VAR_W((uintptr_t) &cpu_state.npxc);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
return op_pc + 1;
}
static uint32_t
ropFCHS(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_FCHS();
return op_pc;
}
#define opFLDimm(name, v) \
static uint32_t \
ropFLD##name(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
static double fp_imm = v; \
static uint64_t *fptr = (uint64_t *) &fp_imm; \
\
FP_ENTER(); \
FP_LOAD_IMM_Q(*fptr); \
\
return op_pc; \
}
// clang-format off
opFLDimm(1, 1.0)
opFLDimm(L2T, 3.3219280948873623)
opFLDimm(L2E, 1.4426950408889634);
opFLDimm(PI, 3.141592653589793);
opFLDimm(EG2, 0.3010299956639812);
opFLDimm(Z, 0.0)
// clang-format on
static uint32_t
ropFLDLN2(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_LOAD_IMM_Q(0x3fe62e42fefa39f0ULL);
return op_pc;
}
``` | /content/code_sandbox/src/codegen/codegen_ops_fpu.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,745 |
```objective-c
static uint32_t
ropPUSH_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-2);
host_reg = LOAD_REG_W(opcode & 7);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
return op_pc;
}
static uint32_t
ropPUSH_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-4);
host_reg = LOAD_REG_L(opcode & 7);
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
return op_pc;
}
static uint32_t
ropPUSH_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint16_t imm = fetchdat & 0xffff;
int host_reg;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-2);
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
return op_pc + 2;
}
static uint32_t
ropPUSH_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t imm = fastreadl(cs + op_pc);
int host_reg;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-4);
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
return op_pc + 4;
}
static uint32_t
ropPUSH_imm_b16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint16_t imm = fetchdat & 0xff;
int host_reg;
if (imm & 0x80)
imm |= 0xff00;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-2);
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
return op_pc + 1;
}
static uint32_t
ropPUSH_imm_b32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t imm = fetchdat & 0xff;
int host_reg;
if (imm & 0x80)
imm |= 0xffffff00;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-4);
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
return op_pc + 1;
}
static uint32_t
ropPOP_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss);
SP_MODIFY(2);
STORE_REG_TARGET_W_RELEASE(0, opcode & 7);
return op_pc;
}
static uint32_t
ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_L(&cpu_state.seg_ss);
SP_MODIFY(4);
STORE_REG_TARGET_L_RELEASE(0, opcode & 7);
return op_pc;
}
static uint32_t
ropRET_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.pc, 0);
SP_MODIFY(2);
return -1;
}
static uint32_t
ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_L(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.pc, 0);
SP_MODIFY(4);
return -1;
}
static uint32_t
ropRET_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint16_t offset = fetchdat & 0xffff;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.pc, 0);
SP_MODIFY(2 + offset);
return -1;
}
static uint32_t
ropRET_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint16_t offset = fetchdat & 0xffff;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_L(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t) &cpu_state.pc, 0);
SP_MODIFY(4 + offset);
return -1;
}
static uint32_t
ropCALL_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint16_t offset = fetchdat & 0xffff;
int host_reg;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-2);
host_reg = LOAD_REG_IMM(op_pc + 2);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.pc, (op_pc + 2 + offset) & 0xffff);
return -1;
}
static uint32_t
ropCALL_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t offset = fastreadl(cs + op_pc);
int host_reg;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(-4);
host_reg = LOAD_REG_IMM(op_pc + 4);
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.pc, op_pc + 4 + offset);
return -1;
}
static uint32_t
ropLEAVE_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_EBP_TO_EA(0);
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss);
host_reg = LOAD_REG_W(REG_BP); /*SP = BP + 2*/
ADD_HOST_REG_IMM_W(host_reg, 2);
STORE_REG_TARGET_W_RELEASE(host_reg, REG_SP);
STORE_REG_TARGET_W_RELEASE(0, REG_BP); /*BP = POP_W()*/
return op_pc;
}
static uint32_t
ropLEAVE_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc);
LOAD_EBP_TO_EA(0);
MEM_LOAD_ADDR_EA_L(&cpu_state.seg_ss);
host_reg = LOAD_REG_L(REG_EBP); /*ESP = EBP + 4*/
ADD_HOST_REG_IMM(host_reg, 4);
STORE_REG_TARGET_L_RELEASE(host_reg, REG_ESP);
STORE_REG_TARGET_L_RELEASE(0, REG_EBP); /*EBP = POP_L()*/
return op_pc;
}
#define ROP_PUSH_SEG(seg) \
static uint32_t \
ropPUSH_##seg##_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int host_reg; \
\
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
LOAD_STACK_TO_EA(-2); \
host_reg = LOAD_VAR_W((uintptr_t) &seg); \
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg); \
SP_MODIFY(-2); \
\
return op_pc; \
} \
static uint32_t \
ropPUSH_##seg##_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int host_reg; \
\
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
LOAD_STACK_TO_EA(-4); \
host_reg = LOAD_VAR_W((uintptr_t) &seg); \
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg); \
SP_MODIFY(-4); \
\
return op_pc; \
}
ROP_PUSH_SEG(CS)
ROP_PUSH_SEG(DS)
ROP_PUSH_SEG(ES)
ROP_PUSH_SEG(FS)
ROP_PUSH_SEG(GS)
ROP_PUSH_SEG(SS)
#define ROP_POP_SEG(seg, rseg) \
static uint32_t \
ropPOP_##seg##_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
LOAD_STACK_TO_EA(0); \
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss); \
LOAD_SEG(0, &rseg); \
SP_MODIFY(2); \
\
return op_pc; \
} \
static uint32_t \
ropPOP_##seg##_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
LOAD_STACK_TO_EA(0); \
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss); \
LOAD_SEG(0, &rseg); \
SP_MODIFY(4); \
\
return op_pc; \
}
ROP_POP_SEG(DS, cpu_state.seg_ds)
ROP_POP_SEG(ES, cpu_state.seg_es)
ROP_POP_SEG(FS, cpu_state.seg_fs)
ROP_POP_SEG(GS, cpu_state.seg_gs)
``` | /content/code_sandbox/src/codegen/codegen_ops_stack.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,802 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of a standard joystick.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <path_to_url
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/gameport.h>
#include <86box/plat_unused.h>
static void *
joystick_standard_init(void)
{
return NULL;
}
static void
joystick_standard_close(UNUSED(void *priv))
{
//
}
static uint8_t
joystick_standard_read(UNUSED(void *priv))
{
uint8_t ret = 0xf0;
if (JOYSTICK_PRESENT(0)) {
if (joystick_state[0].button[0])
ret &= ~0x10;
if (joystick_state[0].button[1])
ret &= ~0x20;
}
if (JOYSTICK_PRESENT(1)) {
if (joystick_state[1].button[0])
ret &= ~0x40;
if (joystick_state[1].button[1])
ret &= ~0x80;
}
return ret;
}
static uint8_t
joystick_standard_read_4button(UNUSED(void *priv))
{
uint8_t ret = 0xf0;
if (JOYSTICK_PRESENT(0)) {
if (joystick_state[0].button[0])
ret &= ~0x10;
if (joystick_state[0].button[1])
ret &= ~0x20;
if (joystick_state[0].button[2])
ret &= ~0x40;
if (joystick_state[0].button[3])
ret &= ~0x80;
}
return ret;
}
static void
joystick_standard_write(UNUSED(void *priv))
{
//
}
static int
joystick_standard_read_axis(UNUSED(void *priv), int axis)
{
switch (axis) {
case 0:
if (!JOYSTICK_PRESENT(0))
return AXIS_NOT_PRESENT;
return joystick_state[0].axis[0];
case 1:
if (!JOYSTICK_PRESENT(0))
return AXIS_NOT_PRESENT;
return joystick_state[0].axis[1];
case 2:
if (!JOYSTICK_PRESENT(1))
return AXIS_NOT_PRESENT;
return joystick_state[1].axis[0];
case 3:
if (!JOYSTICK_PRESENT(1))
return AXIS_NOT_PRESENT;
return joystick_state[1].axis[1];
default:
return 0;
}
}
static int
joystick_standard_read_axis_4button(UNUSED(void *priv), int axis)
{
if (!JOYSTICK_PRESENT(0))
return AXIS_NOT_PRESENT;
switch (axis) {
case 0:
return joystick_state[0].axis[0];
case 1:
return joystick_state[0].axis[1];
case 2:
return 0;
case 3:
return 0;
default:
return 0;
}
}
static int
joystick_standard_read_axis_3axis(UNUSED(void *priv), int axis)
{
if (!JOYSTICK_PRESENT(0))
return AXIS_NOT_PRESENT;
switch (axis) {
case 0:
return joystick_state[0].axis[0];
case 1:
return joystick_state[0].axis[1];
case 2:
return joystick_state[0].axis[2];
case 3:
return 0;
default:
return 0;
}
}
static int
joystick_standard_read_axis_4axis(UNUSED(void *priv), int axis)
{
if (!JOYSTICK_PRESENT(0))
return AXIS_NOT_PRESENT;
switch (axis) {
case 0:
return joystick_state[0].axis[0];
case 1:
return joystick_state[0].axis[1];
case 2:
return joystick_state[0].axis[2];
case 3:
return joystick_state[0].axis[3];
default:
return 0;
}
}
static int
joystick_standard_read_axis_6button(UNUSED(void *priv), int axis)
{
if (!JOYSTICK_PRESENT(0))
return AXIS_NOT_PRESENT;
switch (axis) {
case 0:
return joystick_state[0].axis[0];
case 1:
return joystick_state[0].axis[1];
case 2:
return joystick_state[0].button[4] ? -32767 : 32768;
case 3:
return joystick_state[0].button[5] ? -32767 : 32768;
default:
return 0;
}
}
static int
joystick_standard_read_axis_8button(UNUSED(void *priv), int axis)
{
if (!JOYSTICK_PRESENT(0))
return AXIS_NOT_PRESENT;
switch (axis) {
case 0:
return joystick_state[0].axis[0];
case 1:
return joystick_state[0].axis[1];
case 2:
if (joystick_state[0].button[4])
return -32767;
if (joystick_state[0].button[6])
return 32768;
return 0;
case 3:
if (joystick_state[0].button[5])
return -32767;
if (joystick_state[0].button[7])
return 32768;
return 0;
default:
return 0;
}
}
static void
joystick_standard_a0_over(UNUSED(void *priv))
{
//
}
const joystick_if_t joystick_2axis_2button = {
.name = "2-axis, 2-button joystick(s)",
.internal_name = "2axis_2button",
.init = joystick_standard_init,
.close = joystick_standard_close,
.read = joystick_standard_read,
.write = joystick_standard_write,
.read_axis = joystick_standard_read_axis,
.a0_over = joystick_standard_a0_over,
.axis_count = 2,
.button_count = 2,
.pov_count = 0,
.max_joysticks = 2,
.axis_names = { "X axis", "Y axis" },
.button_names = { "Button 1", "Button 2" },
.pov_names = { NULL }
};
const joystick_if_t joystick_2axis_4button = {
.name = "2-axis, 4-button joystick",
.internal_name = "2axis_4button",
.init = joystick_standard_init,
.close = joystick_standard_close,
.read = joystick_standard_read_4button,
.write = joystick_standard_write,
.read_axis = joystick_standard_read_axis_4button,
.a0_over = joystick_standard_a0_over,
.axis_count = 2,
.button_count = 4,
.pov_count = 0,
.max_joysticks = 1,
.axis_names = { "X axis", "Y axis" },
.button_names = { "Button 1", "Button 2", "Button 3", "Button 4" },
.pov_names = { NULL }
};
const joystick_if_t joystick_3axis_2button = {
.name = "3-axis, 2-button joystick",
.internal_name = "3axis_2button",
.init = joystick_standard_init,
.close = joystick_standard_close,
.read = joystick_standard_read,
.write = joystick_standard_write,
.read_axis = joystick_standard_read_axis_3axis,
.a0_over = joystick_standard_a0_over,
.axis_count = 3,
.button_count = 2,
.pov_count = 0,
.max_joysticks = 1,
.axis_names = { "X axis", "Y axis", "Z axis" },
.button_names = { "Button 1", "Button 2" },
.pov_names = { NULL }
};
const joystick_if_t joystick_3axis_4button = {
.name = "3-axis, 4-button joystick",
.internal_name = "3axis_4button",
.init = joystick_standard_init,
.close = joystick_standard_close,
.read = joystick_standard_read_4button,
.write = joystick_standard_write,
.read_axis = joystick_standard_read_axis_3axis,
.a0_over = joystick_standard_a0_over,
.axis_count = 3,
.button_count = 4,
.pov_count = 0,
.max_joysticks = 1,
.axis_names = { "X axis", "Y axis", "Z axis" },
.button_names = { "Button 1", "Button 2", "Button 3", "Button 4" },
.pov_names = { NULL }
};
const joystick_if_t joystick_4axis_4button = {
.name = "4-axis, 4-button joystick",
.internal_name = "4axis_4button",
.init = joystick_standard_init,
.close = joystick_standard_close,
.read = joystick_standard_read_4button,
.write = joystick_standard_write,
.read_axis = joystick_standard_read_axis_4axis,
.a0_over = joystick_standard_a0_over,
.axis_count = 4,
.button_count = 4,
.pov_count = 0,
.max_joysticks = 1,
.axis_names = { "X axis", "Y axis", "Z axis", "zX axis" },
.button_names = { "Button 1", "Button 2", "Button 3", "Button 4" },
.pov_names = { NULL }
};
const joystick_if_t joystick_2axis_6button = {
.name = "2-axis, 6-button joystick",
.internal_name = "2axis_6button",
.init = joystick_standard_init,
.close = joystick_standard_close,
.read = joystick_standard_read_4button,
.write = joystick_standard_write,
.read_axis = joystick_standard_read_axis_6button,
.a0_over = joystick_standard_a0_over,
.axis_count = 2,
.button_count = 6,
.pov_count = 0,
.max_joysticks = 1,
.axis_names = { "X axis", "Y axis" },
.button_names = { "Button 1", "Button 2", "Button 3", "Button 4", "Button 5", "Button 6" },
.pov_names = { NULL }
};
const joystick_if_t joystick_2axis_8button = {
.name = "2-axis, 8-button joystick",
.internal_name = "2axis_8button",
.init = joystick_standard_init,
.close = joystick_standard_close,
.read = joystick_standard_read_4button,
.write = joystick_standard_write,
.read_axis = joystick_standard_read_axis_8button,
.a0_over = joystick_standard_a0_over,
.axis_count = 2,
.button_count = 8,
.pov_count = 0,
.max_joysticks = 1,
.axis_names = { "X axis", "Y axis" },
.button_names = { "Button 1", "Button 2", "Button 3", "Button 4", "Button 5", "Button 6", "Button 7", "Button 8" },
.pov_names = { NULL }
};
``` | /content/code_sandbox/src/game/joystick_standard.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,865 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of a Side Winder GamePad.
*
* Notes: - Write to 0x201 starts packet transfer (5*N or 15*N bits)
* - Currently alternates between Mode A and Mode B (is there
* any way of actually controlling which is used?)
* - Windows 9x drivers require Mode B when more than 1 pad
* connected
* - Packet preceeded by high data (currently 50us), and
* followed by low data (currently 160us) - timings are
* probably wrong, but good enough for everything I've tried
* - Analog inputs are only used to time ID packet request.
* If A0 timing out is followed after ~64us by another 0x201
* write then an ID packet is triggered
* - Sidewinder game pad ID is 'H0003'
* - ID is sent in Mode A (1 bit per clock), but data bit 2
* must change during ID packet transfer, or Windows 9x
* drivers won't use Mode B. I don't know if it oscillates,
* mirrors the data transfer, or something else - the drivers
* only check that it changes at least 10 times during the
* transfer
* - Some DOS stuff will write to 0x201 while a packet is
* being transferred. This seems to be ignored.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <path_to_url
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/gameport.h>
#include <86box/plat_unused.h>
typedef struct sw_data {
pc_timer_t poll_timer;
int poll_left;
int poll_clock;
uint64_t poll_data;
int poll_mode;
pc_timer_t trigger_timer;
int data_mode;
} sw_data;
static void
sw_timer_over(void *priv)
{
sw_data *sw = (sw_data *) priv;
sw->poll_clock = !sw->poll_clock;
if (sw->poll_clock) {
sw->poll_data >>= (sw->poll_mode ? 3 : 1);
sw->poll_left--;
}
if (sw->poll_left == 1 && !sw->poll_clock)
timer_advance_u64(&sw->poll_timer, TIMER_USEC * 160);
else if (sw->poll_left)
timer_set_delay_u64(&sw->poll_timer, TIMER_USEC * 5);
}
static void
sw_trigger_timer_over(void *priv)
{
sw_data *sw = (sw_data *) priv;
timer_disable(&sw->trigger_timer);
}
static int
sw_parity(uint16_t data)
{
int bits_set = 0;
while (data) {
bits_set++;
data &= (data - 1);
}
return bits_set & 1;
}
static void *
sw_init(void)
{
sw_data *sw = (sw_data *) malloc(sizeof(sw_data));
memset(sw, 0, sizeof(sw_data));
timer_add(&sw->poll_timer, sw_timer_over, sw, 0);
timer_add(&sw->trigger_timer, sw_trigger_timer_over, sw, 0);
return sw;
}
static void
sw_close(void *priv)
{
sw_data *sw = (sw_data *) priv;
free(sw);
}
static uint8_t
sw_read(void *priv)
{
sw_data *sw = (sw_data *) priv;
uint8_t temp = 0;
if (!JOYSTICK_PRESENT(0))
return 0xff;
if (timer_is_enabled(&sw->poll_timer)) {
if (sw->poll_clock)
temp |= 0x10;
if (sw->poll_mode)
temp |= (sw->poll_data & 7) << 5;
else {
temp |= ((sw->poll_data & 1) << 5) | 0xc0;
if (sw->poll_left > 31 && !(sw->poll_left & 1))
temp &= ~0x80;
}
} else
temp |= 0xf0;
return temp;
}
static void
sw_write(void *priv)
{
sw_data *sw = (sw_data *) priv;
int64_t time_since_last = timer_get_remaining_us(&sw->trigger_timer);
if (!JOYSTICK_PRESENT(0))
return;
if (!sw->poll_left) {
sw->poll_clock = 1;
timer_set_delay_u64(&sw->poll_timer, TIMER_USEC * 40);
if (time_since_last > 9900 && time_since_last < 9940) {
sw->poll_mode = 0;
sw->poll_left = 49;
sw->poll_data = 0x2400ULL | (0x1830ULL << 15) | (0x19b0ULL << 30);
} else {
sw->poll_mode = sw->data_mode;
sw->data_mode = !sw->data_mode;
if (sw->poll_mode) {
sw->poll_left = 1;
sw->poll_data = 7;
} else {
sw->poll_left = 1;
sw->poll_data = 1;
}
for (uint8_t c = 0; c < 4; c++) {
uint16_t data = 0x3fff;
if (!JOYSTICK_PRESENT(c))
break;
if (joystick_state[c].axis[1] < -16383)
data &= ~1;
if (joystick_state[c].axis[1] > 16383)
data &= ~2;
if (joystick_state[c].axis[0] > 16383)
data &= ~4;
if (joystick_state[c].axis[0] < -16383)
data &= ~8;
for (uint8_t b = 0; b < 10; b++) {
if (joystick_state[c].button[b])
data &= ~(1 << (b + 4));
}
if (sw_parity(data))
data |= 0x4000;
if (sw->poll_mode) {
sw->poll_left += 5;
sw->poll_data |= (data << (c * 15 + 3));
} else {
sw->poll_left += 15;
sw->poll_data |= (data << (c * 15 + 1));
}
}
}
}
timer_disable(&sw->trigger_timer);
}
static int
sw_read_axis(UNUSED(void *priv), UNUSED(int axis))
{
if (!JOYSTICK_PRESENT(0))
return AXIS_NOT_PRESENT;
return 0; /*No analogue support on Sidewinder game pad*/
}
static void
sw_a0_over(void *priv)
{
sw_data *sw = (sw_data *) priv;
timer_set_delay_u64(&sw->trigger_timer, TIMER_USEC * 10000);
}
const joystick_if_t joystick_sw_pad = {
.name = "Microsoft SideWinder Pad",
.internal_name = "sidewinder_pad",
.init = sw_init,
.close = sw_close,
.read = sw_read,
.write = sw_write,
.read_axis = sw_read_axis,
.a0_over = sw_a0_over,
.axis_count = 2,
.button_count = 10,
.pov_count = 0,
.max_joysticks = 4,
.axis_names = { "X axis", "Y axis" },
.button_names = { "A", "B", "C", "X", "Y", "Z", "L", "R", "Start", "M" },
.pov_names = { NULL }
};
``` | /content/code_sandbox/src/game/joystick_sw_pad.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,961 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Flight Stick Pro.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <path_to_url
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/gameport.h>
#include <86box/plat_unused.h>
static void *
ch_flightstick_pro_init(void)
{
return NULL;
}
static void
ch_flightstick_pro_close(UNUSED(void *priv))
{
//
}
static uint8_t
ch_flightstick_pro_read(UNUSED(void *priv))
{
uint8_t ret = 0xf0;
if (JOYSTICK_PRESENT(0)) {
if (joystick_state[0].button[0])
ret &= ~0x10;
if (joystick_state[0].button[1])
ret &= ~0x20;
if (joystick_state[0].button[2])
ret &= ~0x40;
if (joystick_state[0].button[3])
ret &= ~0x80;
if (joystick_state[0].pov[0] != -1) {
if (joystick_state[0].pov[0] > 315 || joystick_state[0].pov[0] < 45)
ret &= ~0xf0;
else if (joystick_state[0].pov[0] >= 45 && joystick_state[0].pov[0] < 135)
ret &= ~0xb0;
else if (joystick_state[0].pov[0] >= 135 && joystick_state[0].pov[0] < 225)
ret &= ~0x70;
else if (joystick_state[0].pov[0] >= 225 && joystick_state[0].pov[0] < 315)
ret &= ~0x30;
}
}
return ret;
}
static void
ch_flightstick_pro_write(UNUSED(void *priv))
{
//
}
static int
ch_flightstick_pro_read_axis(UNUSED(void *priv), int axis)
{
if (!JOYSTICK_PRESENT(0))
return AXIS_NOT_PRESENT;
switch (axis) {
case 0:
return joystick_state[0].axis[0];
case 1:
return joystick_state[0].axis[1];
case 2:
return 0;
case 3:
return joystick_state[0].axis[2];
default:
return 0;
}
}
static void
ch_flightstick_pro_a0_over(UNUSED(void *priv))
{
//
}
const joystick_if_t joystick_ch_flightstick_pro = {
.name = "CH Flightstick Pro",
.internal_name = "ch_flightstick_pro",
.init = ch_flightstick_pro_init,
.close = ch_flightstick_pro_close,
.read = ch_flightstick_pro_read,
.write = ch_flightstick_pro_write,
.read_axis = ch_flightstick_pro_read_axis,
.a0_over = ch_flightstick_pro_a0_over,
.axis_count = 3,
.button_count = 4,
.pov_count = 1,
.max_joysticks = 1,
.axis_names = { "X axis", "Y axis", "Throttle" },
.button_names = { "Button 1", "Button 2", "Button 3", "Button 4" },
.pov_names = { "POV" }
};
``` | /content/code_sandbox/src/game/joystick_ch_flightstick_pro.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,007 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Thrust Master Flight Control System.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <path_to_url
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/gameport.h>
#include <86box/plat_unused.h>
static void *
tm_fcs_init(void)
{
return NULL;
}
static void
tm_fcs_close(UNUSED(void *priv))
{
//
}
static uint8_t
tm_fcs_read(UNUSED(void *priv))
{
uint8_t ret = 0xf0;
if (JOYSTICK_PRESENT(0)) {
if (joystick_state[0].button[0])
ret &= ~0x10;
if (joystick_state[0].button[1])
ret &= ~0x20;
if (joystick_state[0].button[2])
ret &= ~0x40;
if (joystick_state[0].button[3])
ret &= ~0x80;
}
return ret;
}
static void
tm_fcs_write(UNUSED(void *priv))
{
//
}
static int
tm_fcs_read_axis(UNUSED(void *priv), int axis)
{
if (!JOYSTICK_PRESENT(0))
return AXIS_NOT_PRESENT;
switch (axis) {
case 0:
return joystick_state[0].axis[0];
case 1:
return joystick_state[0].axis[1];
case 2:
return 0;
case 3:
if (joystick_state[0].pov[0] == -1)
return 32767;
if (joystick_state[0].pov[0] > 315 || joystick_state[0].pov[0] < 45)
return -32768;
if (joystick_state[0].pov[0] >= 45 && joystick_state[0].pov[0] < 135)
return -16384;
if (joystick_state[0].pov[0] >= 135 && joystick_state[0].pov[0] < 225)
return 0;
if (joystick_state[0].pov[0] >= 225 && joystick_state[0].pov[0] < 315)
return 16384;
return 0;
default:
return 0;
}
}
static void
tm_fcs_a0_over(UNUSED(void *priv))
{
//
}
const joystick_if_t joystick_tm_fcs = {
.name = "Thrustmaster Flight Control System",
.internal_name = "thrustmaster_fcs",
.init = tm_fcs_init,
.close = tm_fcs_close,
.read = tm_fcs_read,
.write = tm_fcs_write,
.read_axis = tm_fcs_read_axis,
.a0_over = tm_fcs_a0_over,
.axis_count = 2,
.button_count = 4,
.pov_count = 1,
.max_joysticks = 1,
.axis_names = { "X axis", "Y axis" },
.button_names = { "Button 1", "Button 2", "Button 3", "Button 4" },
.pov_names = { "POV" }
};
``` | /content/code_sandbox/src/game/joystick_tm_fcs.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 980 |
```c++
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Serial/Parallel ports configuration UI module.
*
*
*
* Authors: Joakim L. Gilje <jgilje@jgilje.net>
* Cacodemon345
*
*/
#include "qt_settingsports.hpp"
#include "ui_qt_settingsports.h"
extern "C" {
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/machine.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/serial_passthrough.h>
}
#include "qt_deviceconfig.hpp"
#include "qt_models_common.hpp"
SettingsPorts::SettingsPorts(QWidget *parent)
: QWidget(parent)
, ui(new Ui::SettingsPorts)
{
ui->setupUi(this);
for (int i = 0; i < PARALLEL_MAX; i++) {
auto *cbox = findChild<QComboBox *>(QString("comboBoxLpt%1").arg(i + 1));
auto *model = cbox->model();
int c = 0;
int selectedRow = 0;
while (true) {
const char *lptName = lpt_device_get_name(c);
if (lptName == nullptr) {
break;
}
Models::AddEntry(model, tr(lptName), c);
if (c == lpt_ports[i].device) {
selectedRow = c;
}
c++;
}
cbox->setCurrentIndex(selectedRow);
auto *checkBox = findChild<QCheckBox *>(QString("checkBoxParallel%1").arg(i + 1));
if (checkBox != NULL)
checkBox->setChecked(lpt_ports[i].enabled > 0);
if (cbox != NULL)
cbox->setEnabled(lpt_ports[i].enabled > 0);
}
for (int i = 0; i < SERIAL_MAX; i++) {
auto *checkBox = findChild<QCheckBox *>(QString("checkBoxSerial%1").arg(i + 1));
auto *checkBoxPass = findChild<QCheckBox *>(QString("checkBoxSerialPassThru%1").arg(i + 1));
if (checkBox != NULL)
checkBox->setChecked(com_ports[i].enabled > 0);
if (checkBoxPass != NULL)
checkBoxPass->setChecked(serial_passthrough_enabled[i]);
}
ui->pushButtonSerialPassThru1->setEnabled(serial_passthrough_enabled[0]);
ui->pushButtonSerialPassThru2->setEnabled(serial_passthrough_enabled[1]);
ui->pushButtonSerialPassThru3->setEnabled(serial_passthrough_enabled[2]);
ui->pushButtonSerialPassThru4->setEnabled(serial_passthrough_enabled[3]);
#if 0
ui->pushButtonSerialPassThru5->setEnabled(serial_passthrough_enabled[4]);
ui->pushButtonSerialPassThru6->setEnabled(serial_passthrough_enabled[5]);
ui->pushButtonSerialPassThru7->setEnabled(serial_passthrough_enabled[6]);
#endif
}
SettingsPorts::~SettingsPorts()
{
delete ui;
}
void
SettingsPorts::save()
{
for (int i = 0; i < PARALLEL_MAX; i++) {
auto *cbox = findChild<QComboBox *>(QString("comboBoxLpt%1").arg(i + 1));
auto *checkBox = findChild<QCheckBox *>(QString("checkBoxParallel%1").arg(i + 1));
if (cbox != NULL)
lpt_ports[i].device = cbox->currentData().toInt();
if (checkBox != NULL)
lpt_ports[i].enabled = checkBox->isChecked() ? 1 : 0;
}
for (int i = 0; i < SERIAL_MAX; i++) {
auto *checkBox = findChild<QCheckBox *>(QString("checkBoxSerial%1").arg(i + 1));
auto *checkBoxPass = findChild<QCheckBox *>(QString("checkBoxSerialPassThru%1").arg(i + 1));
if (checkBox != NULL)
com_ports[i].enabled = checkBox->isChecked() ? 1 : 0;
if (checkBoxPass != NULL)
serial_passthrough_enabled[i] = checkBoxPass->isChecked();
}
}
void
SettingsPorts::on_checkBoxParallel1_stateChanged(int state)
{
ui->comboBoxLpt1->setEnabled(state == Qt::Checked);
}
void
SettingsPorts::on_checkBoxParallel2_stateChanged(int state)
{
ui->comboBoxLpt2->setEnabled(state == Qt::Checked);
}
void
SettingsPorts::on_checkBoxParallel3_stateChanged(int state)
{
ui->comboBoxLpt3->setEnabled(state == Qt::Checked);
}
void
SettingsPorts::on_checkBoxParallel4_stateChanged(int state)
{
ui->comboBoxLpt4->setEnabled(state == Qt::Checked);
}
void
SettingsPorts::on_pushButtonSerialPassThru1_clicked()
{
DeviceConfig::ConfigureDevice(&serial_passthrough_device, 1, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsPorts::on_pushButtonSerialPassThru2_clicked()
{
DeviceConfig::ConfigureDevice(&serial_passthrough_device, 2, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsPorts::on_pushButtonSerialPassThru3_clicked()
{
DeviceConfig::ConfigureDevice(&serial_passthrough_device, 3, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsPorts::on_pushButtonSerialPassThru4_clicked()
{
DeviceConfig::ConfigureDevice(&serial_passthrough_device, 4, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsPorts::on_pushButtonSerialPassThru5_clicked()
{
DeviceConfig::ConfigureDevice(&serial_passthrough_device, 5, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsPorts::on_pushButtonSerialPassThru6_clicked()
{
DeviceConfig::ConfigureDevice(&serial_passthrough_device, 6, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsPorts::on_pushButtonSerialPassThru7_clicked()
{
DeviceConfig::ConfigureDevice(&serial_passthrough_device, 7, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsPorts::on_checkBoxSerialPassThru1_clicked(bool checked)
{
ui->pushButtonSerialPassThru1->setEnabled(checked);
}
void
SettingsPorts::on_checkBoxSerialPassThru2_clicked(bool checked)
{
ui->pushButtonSerialPassThru2->setEnabled(checked);
}
void
SettingsPorts::on_checkBoxSerialPassThru3_clicked(bool checked)
{
ui->pushButtonSerialPassThru3->setEnabled(checked);
}
void
SettingsPorts::on_checkBoxSerialPassThru4_clicked(bool checked)
{
ui->pushButtonSerialPassThru4->setEnabled(checked);
}
#if 0
void
SettingsPorts::on_checkBoxSerialPassThru5_clicked(bool checked)
{
ui->pushButtonSerialPassThru5->setEnabled(checked);
}
void
SettingsPorts::on_checkBoxSerialPassThru6_clicked(bool checked)
{
ui->pushButtonSerialPassThru6->setEnabled(checked);
}
void
SettingsPorts::on_checkBoxSerialPassThru7_clicked(bool checked)
{
ui->pushButtonSerialPassThru7->setEnabled(checked);
}
#endif
``` | /content/code_sandbox/src/qt/qt_settingsports.cpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,631 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of a generic Game Port.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <path_to_url
* RichardG, <richardg867@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/machine.h>
#include "cpu.h"
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/isapnp.h>
#include <86box/gameport.h>
#include <86box/plat_unused.h>
typedef struct g_axis_t {
pc_timer_t timer;
int axis_nr;
struct _joystick_instance_ *joystick;
} g_axis_t;
typedef struct _gameport_ {
uint16_t addr;
uint8_t len;
struct _joystick_instance_ *joystick;
struct _gameport_ *next;
} gameport_t;
typedef struct _joystick_instance_ {
uint8_t state;
g_axis_t axis[4];
const joystick_if_t *intf;
void *dat;
} joystick_instance_t;
int joystick_type = JS_TYPE_NONE;
static const joystick_if_t joystick_none = {
.name = "None",
.internal_name = "none",
.init = NULL,
.close = NULL,
.read = NULL,
.write = NULL,
.read_axis = NULL,
.a0_over = NULL,
.axis_count = 0,
.button_count = 0,
.pov_count = 0,
.max_joysticks = 0,
.axis_names = { NULL },
.button_names = { NULL },
.pov_names = { NULL }
};
static const struct {
const joystick_if_t *joystick;
} joysticks[] = {
{ &joystick_none },
{ &joystick_2axis_2button },
{ &joystick_2axis_4button },
{ &joystick_2axis_6button },
{ &joystick_2axis_8button },
{ &joystick_3axis_2button },
{ &joystick_3axis_4button },
{ &joystick_4axis_4button },
{ &joystick_ch_flightstick_pro },
{ &joystick_sw_pad },
{ &joystick_tm_fcs },
{ NULL }
};
static joystick_instance_t *joystick_instance = NULL;
static uint8_t gameport_pnp_rom[] = {
0x09, 0xf8, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, /* BOX0002, dummy checksum (filled in by isapnp_add_card) */
0x0a, 0x10, 0x10, /* PnP version 1.0, vendor version 1.0 */
0x82, 0x09, 0x00, 'G', 'a', 'm', 'e', ' ', 'P', 'o', 'r', 't', /* ANSI identifier */
0x15, 0x09, 0xf8, 0x00, 0x02, 0x01, /* logical device BOX0002, can participate in boot */
0x1c, 0x41, 0xd0, 0xb0, 0x2f, /* compatible device PNPB02F */
0x31, 0x00, /* start dependent functions, preferred */
0x47, 0x01, 0x00, 0x02, 0x00, 0x02, 0x08, 0x08, /* I/O 0x200, decodes 16-bit, 8-byte alignment, 8 addresses */
0x30, /* start dependent functions, acceptable */
0x47, 0x01, 0x08, 0x02, 0x08, 0x02, 0x08, 0x08, /* I/O 0x208, decodes 16-bit, 8-byte alignment, 8 addresses */
0x31, 0x02, /* start dependent functions, sub-optimal */
0x47, 0x01, 0x00, 0x01, 0xf8, 0xff, 0x08, 0x08, /* I/O 0x100-0xFFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x38, /* end dependent functions */
0x79, 0x00 /* end tag, dummy checksum (filled in by isapnp_add_card) */
};
static const isapnp_device_config_t gameport_pnp_defaults[] = {
{.activate = 1,
.io = {
{ .base = 0x200 },
}
}
};
const device_t *standalone_gameport_type;
int gameport_instance_id = 0;
/* Linked list of active game ports. Only the top port responds to reads
or writes, and ports at the standard 200h location are prioritized. */
static gameport_t *active_gameports = NULL;
const char *
joystick_get_name(int js)
{
if (!joysticks[js].joystick)
return NULL;
return joysticks[js].joystick->name;
}
const char *
joystick_get_internal_name(int js)
{
if (joysticks[js].joystick == NULL)
return "";
return joysticks[js].joystick->internal_name;
}
int
joystick_get_from_internal_name(char *s)
{
int c = 0;
while (joysticks[c].joystick != NULL) {
if (!strcmp(joysticks[c].joystick->internal_name, s))
return c;
c++;
}
return 0;
}
int
joystick_get_max_joysticks(int js)
{
return joysticks[js].joystick->max_joysticks;
}
int
joystick_get_axis_count(int js)
{
return joysticks[js].joystick->axis_count;
}
int
joystick_get_button_count(int js)
{
return joysticks[js].joystick->button_count;
}
int
joystick_get_pov_count(int js)
{
return joysticks[js].joystick->pov_count;
}
const char *
joystick_get_axis_name(int js, int id)
{
return joysticks[js].joystick->axis_names[id];
}
const char *
joystick_get_button_name(int js, int id)
{
return joysticks[js].joystick->button_names[id];
}
const char *
joystick_get_pov_name(int js, int id)
{
return joysticks[js].joystick->pov_names[id];
}
static void
gameport_time(joystick_instance_t *joystick, int nr, int axis)
{
if (axis == AXIS_NOT_PRESENT)
timer_disable(&joystick->axis[nr].timer);
else {
/* Convert axis value to 555 timing. */
axis += 32768;
axis = (axis * 100) / 65; /* axis now in ohms */
axis = (axis * 11) / 1000;
timer_set_delay_u64(&joystick->axis[nr].timer, TIMER_USEC * (axis + 24)); /* max = 11.115 ms */
}
}
static void
gameport_write(UNUSED(uint16_t addr), UNUSED(uint8_t val), void *priv)
{
gameport_t *dev = (gameport_t *) priv;
joystick_instance_t *joystick = dev->joystick;
/* Respond only if a joystick is present and this port is at the top of the active ports list. */
if (!joystick || (active_gameports != dev))
return;
/* Read all axes. */
joystick->state |= 0x0f;
gameport_time(joystick, 0, joystick->intf->read_axis(joystick->dat, 0));
gameport_time(joystick, 1, joystick->intf->read_axis(joystick->dat, 1));
gameport_time(joystick, 2, joystick->intf->read_axis(joystick->dat, 2));
gameport_time(joystick, 3, joystick->intf->read_axis(joystick->dat, 3));
/* Notify the interface. */
joystick->intf->write(joystick->dat);
cycles -= ISA_CYCLES(8);
}
static uint8_t
gameport_read(UNUSED(uint16_t addr), void *priv)
{
gameport_t *dev = (gameport_t *) priv;
joystick_instance_t *joystick = dev->joystick;
/* Respond only if a joystick is present and this port is at the top of the active ports list. */
if (!joystick || (active_gameports != dev))
return 0xff;
/* Merge axis state with button state. */
uint8_t ret = joystick->state | joystick->intf->read(joystick->dat);
cycles -= ISA_CYCLES(8);
return ret;
}
static void
timer_over(void *priv)
{
g_axis_t *axis = (g_axis_t *) priv;
axis->joystick->state &= ~(1 << axis->axis_nr);
/* Notify the joystick when the first axis' period is finished. */
if (axis == &axis->joystick->axis[0])
axis->joystick->intf->a0_over(axis->joystick->dat);
}
void
gameport_update_joystick_type(void)
{
/* Add a standalone game port if a joystick is enabled but no other game ports exist. */
if (standalone_gameport_type)
gameport_add(standalone_gameport_type);
/* Reset the joystick interface. */
if (joystick_instance) {
joystick_instance->intf->close(joystick_instance->dat);
joystick_instance->intf = joysticks[joystick_type].joystick;
joystick_instance->dat = joystick_instance->intf->init();
}
}
void
gameport_remap(void *priv, uint16_t address)
{
gameport_t *dev = (gameport_t *) priv;
gameport_t *other_dev;
if (dev->addr) {
/* Remove this port from the active ports list. */
if (active_gameports == dev) {
active_gameports = dev->next;
dev->next = NULL;
} else {
other_dev = active_gameports;
while (other_dev) {
if (other_dev->next == dev) {
other_dev->next = dev->next;
dev->next = NULL;
break;
}
other_dev = other_dev->next;
}
}
io_removehandler(dev->addr, dev->len,
gameport_read, NULL, NULL, gameport_write, NULL, NULL, dev);
}
dev->addr = address;
if (dev->addr) {
/* Add this port to the active ports list. */
if (!active_gameports || ((dev->addr & 0xfff8) == 0x200)) {
/* No ports have been added yet, or port within 200-207h: add to top. */
dev->next = active_gameports;
active_gameports = dev;
} else {
/* Port at other addresses: add to bottom. */
other_dev = active_gameports;
while (other_dev->next)
other_dev = other_dev->next;
other_dev->next = dev;
}
io_sethandler(dev->addr, dev->len,
gameport_read, NULL, NULL, gameport_write, NULL, NULL, dev);
}
}
static void
gameport_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
{
if (ld > 0)
return;
gameport_t *dev = (gameport_t *) priv;
/* Remap the game port to the specified address, or disable it. */
gameport_remap(dev, (config->activate && (config->io[0].base != ISAPNP_IO_DISABLED)) ? config->io[0].base : 0);
}
void *
gameport_add(const device_t *gameport_type)
{
/* Prevent a standalone game port from being added later on, unless this
is an unused Super I/O game port (no MACHINE_GAMEPORT machine flag). */
if (!(gameport_type->local & GAMEPORT_SIO) || machine_has_flags(machine, MACHINE_GAMEPORT))
standalone_gameport_type = NULL;
/* Add game port device. */
return device_add_inst(gameport_type, gameport_instance_id++);
}
static void *
gameport_init(const device_t *info)
{
gameport_t *dev = NULL;
dev = malloc(sizeof(gameport_t));
memset(dev, 0x00, sizeof(gameport_t));
/* Allocate global instance. */
if (!joystick_instance && joystick_type) {
joystick_instance = malloc(sizeof(joystick_instance_t));
memset(joystick_instance, 0x00, sizeof(joystick_instance_t));
joystick_instance->axis[0].joystick = joystick_instance;
joystick_instance->axis[1].joystick = joystick_instance;
joystick_instance->axis[2].joystick = joystick_instance;
joystick_instance->axis[3].joystick = joystick_instance;
joystick_instance->axis[0].axis_nr = 0;
joystick_instance->axis[1].axis_nr = 1;
joystick_instance->axis[2].axis_nr = 2;
joystick_instance->axis[3].axis_nr = 3;
timer_add(&joystick_instance->axis[0].timer, timer_over, &joystick_instance->axis[0], 0);
timer_add(&joystick_instance->axis[1].timer, timer_over, &joystick_instance->axis[1], 0);
timer_add(&joystick_instance->axis[2].timer, timer_over, &joystick_instance->axis[2], 0);
timer_add(&joystick_instance->axis[3].timer, timer_over, &joystick_instance->axis[3], 0);
joystick_instance->intf = joysticks[joystick_type].joystick;
joystick_instance->dat = joystick_instance->intf->init();
}
dev->joystick = joystick_instance;
/* Map game port to the default address. Not applicable on PnP-only ports. */
dev->len = (info->local >> 16) & 0xff;
gameport_remap(dev, info->local & 0xffff);
/* Register ISAPnP if this is a standard game port card. */
if ((info->local & 0xffff) == 0x200)
isapnp_set_device_defaults(isapnp_add_card(gameport_pnp_rom, sizeof(gameport_pnp_rom), gameport_pnp_config_changed, NULL, NULL, NULL, dev), 0, gameport_pnp_defaults);
return dev;
}
static void *
tmacm_init(UNUSED(const device_t *info))
{
uint16_t port = 0x0000;
gameport_t *dev = NULL;
dev = malloc(sizeof(gameport_t));
memset(dev, 0x00, sizeof(gameport_t));
port = (uint16_t) device_get_config_hex16("port1_addr");
switch (port) {
case 0x201:
dev = gameport_add(&gameport_201_device);
break;
case 0x203:
dev = gameport_add(&gameport_203_device);
break;
case 0x205:
dev = gameport_add(&gameport_205_device);
break;
case 0x207:
dev = gameport_add(&gameport_207_device);
break;
default:
break;
}
port = (uint16_t) device_get_config_hex16("port2_addr");
switch (port) {
case 0x209:
dev = gameport_add(&gameport_209_device);
break;
case 0x20b:
dev = gameport_add(&gameport_20b_device);
break;
case 0x20d:
dev = gameport_add(&gameport_20d_device);
break;
case 0x20f:
dev = gameport_add(&gameport_20f_device);
break;
default:
break;
}
return dev;
}
static void
gameport_close(void *priv)
{
gameport_t *dev = (gameport_t *) priv;
/* If this port was active, remove it from the active ports list. */
gameport_remap(dev, 0);
/* Free the global instance here, if it wasn't already freed. */
if (joystick_instance) {
joystick_instance->intf->close(joystick_instance->dat);
free(joystick_instance);
joystick_instance = NULL;
}
free(dev);
}
const device_t gameport_device = {
.name = "Game port",
.internal_name = "gameport",
.flags = 0,
.local = 0x080200,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_201_device = {
.name = "Game port (Port 201h only)",
.internal_name = "gameport_201",
.flags = 0,
.local = 0x010201,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_203_device = {
.name = "Game port (Port 203h only)",
.internal_name = "gameport_203",
.flags = 0,
.local = 0x010203,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_205_device = {
.name = "Game port (Port 205h only)",
.internal_name = "gameport_205",
.flags = 0,
.local = 0x010205,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_207_device = {
.name = "Game port (Port 207h only)",
.internal_name = "gameport_207",
.flags = 0,
.local = 0x010207,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_208_device = {
.name = "Game port (Port 208h-20fh)",
.internal_name = "gameport_208",
.flags = 0,
.local = 0x080208,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_209_device = {
.name = "Game port (Port 209h only)",
.internal_name = "gameport_209",
.flags = 0,
.local = 0x010209,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_20b_device = {
.name = "Game port (Port 20Bh only)",
.internal_name = "gameport_20b",
.flags = 0,
.local = 0x01020B,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_20d_device = {
.name = "Game port (Port 20Dh only)",
.internal_name = "gameport_20d",
.flags = 0,
.local = 0x01020D,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_20f_device = {
.name = "Game port (Port 20Fh only)",
.internal_name = "gameport_20f",
.flags = 0,
.local = 0x01020F,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
static const device_config_t tmacm_config[] = {
// clang-format off
{
.name = "port1_addr",
.description = "Port 1 Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0201,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "201h", .value = 0x0201 },
{ .description = "203h", .value = 0x0203 },
{ .description = "205h", .value = 0x0205 },
{ .description = "207h", .value = 0x0207 },
{ .description = "Disabled", .value = 0x0000 },
{ "" }
}
},
{
.name = "port2_addr",
.description = "Port 2 Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0209,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "209h", .value = 0x0209 },
{ .description = "20Bh", .value = 0x020B },
{ .description = "20Dh", .value = 0x020D },
{ .description = "20Fh", .value = 0x020F },
{ .description = "Disabled", .value = 0x0000 },
{ "" }
}
},
{ "", "", -1 }
// clang-format on
};
const device_t gameport_tm_acm_device = {
.name = "Game port (ThrustMaster ACM)",
.internal_name = "gameport_tmacm",
.flags = DEVICE_ISA,
.local = 0,
.init = tmacm_init,
.close = NULL,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = tmacm_config
};
const device_t gameport_pnp_device = {
.name = "Game port (Plug and Play only)",
.internal_name = "gameport_pnp",
.flags = 0,
.local = 0x080000,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_pnp_6io_device = {
.name = "Game port (Plug and Play only, 6 I/O ports)",
.internal_name = "gameport_pnp_6io",
.flags = 0,
.local = 0x060000,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_sio_device = {
.name = "Game port (Super I/O)",
.internal_name = "gameport_sio",
.flags = 0,
.local = 0x1080000,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gameport_sio_1io_device = {
.name = "Game port (Super I/O, 1 I/O port)",
.internal_name = "gameport_sio",
.flags = 0,
.local = 0x1010000,
.init = gameport_init,
.close = gameport_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/game/gameport.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,906 |
```c++
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Other removable devices configuration UI module.
*
*
*
* Authors: Joakim L. Gilje <jgilje@jgilje.net>
* Cacodemon345
*
*/
#include "qt_settingsotherremovable.hpp"
#include "ui_qt_settingsotherremovable.h"
extern "C" {
#include <86box/timer.h>
#include <86box/scsi_device.h>
#include <86box/mo.h>
#include <86box/zip.h>
}
#include <QStandardItemModel>
#include "qt_models_common.hpp"
#include "qt_harddrive_common.hpp"
#include "qt_settings_bus_tracking.hpp"
#include "qt_progsettings.hpp"
static QString
moDriveTypeName(int i)
{
return QString("%1 %2 %3").arg(mo_drive_types[i].vendor, mo_drive_types[i].model,
mo_drive_types[i].revision);
}
static void
setMOBus(QAbstractItemModel *model, const QModelIndex &idx, uint8_t bus, uint8_t channel)
{
QIcon icon;
switch (bus) {
case MO_BUS_DISABLED:
icon = ProgSettings::loadIcon("/mo_disabled.ico");
break;
case MO_BUS_ATAPI:
case MO_BUS_SCSI:
icon = ProgSettings::loadIcon("/mo.ico");
break;
default:
break;
}
auto i = idx.siblingAtColumn(0);
model->setData(i, Harddrives::BusChannelName(bus, channel));
model->setData(i, bus, Qt::UserRole);
model->setData(i, channel, Qt::UserRole + 1);
model->setData(i, icon, Qt::DecorationRole);
}
static void
setMOType(QAbstractItemModel *model, const QModelIndex &idx, uint32_t type)
{
auto i = idx.siblingAtColumn(1);
if (idx.siblingAtColumn(0).data(Qt::UserRole).toUInt() == MO_BUS_DISABLED)
model->setData(i, QCoreApplication::translate("", "None"));
else
model->setData(i, moDriveTypeName(type));
model->setData(i, type, Qt::UserRole);
}
static void
setZIPBus(QAbstractItemModel *model, const QModelIndex &idx, uint8_t bus, uint8_t channel)
{
QIcon icon;
switch (bus) {
case ZIP_BUS_DISABLED:
icon = ProgSettings::loadIcon("/zip_disabled.ico");
break;
case ZIP_BUS_ATAPI:
case ZIP_BUS_SCSI:
icon = ProgSettings::loadIcon("/zip.ico");
break;
default:
break;
}
auto i = idx.siblingAtColumn(0);
model->setData(i, Harddrives::BusChannelName(bus, channel));
model->setData(i, bus, Qt::UserRole);
model->setData(i, channel, Qt::UserRole + 1);
model->setData(i, icon, Qt::DecorationRole);
}
static void
setZIPType(QAbstractItemModel *model, const QModelIndex &idx, bool is250)
{
auto i = idx.siblingAtColumn(1);
model->setData(i, is250 ? "ZIP 250" : "ZIP 100");
model->setData(i, is250, Qt::UserRole);
}
SettingsOtherRemovable::SettingsOtherRemovable(QWidget *parent)
: QWidget(parent)
, ui(new Ui::SettingsOtherRemovable)
{
ui->setupUi(this);
Harddrives::populateRemovableBuses(ui->comboBoxMOBus->model());
auto *model = ui->comboBoxMOType->model();
for (uint32_t i = 0; i < KNOWN_MO_DRIVE_TYPES; i++) {
Models::AddEntry(model, moDriveTypeName(i), i);
}
model = new QStandardItemModel(0, 2, this);
ui->tableViewMO->setModel(model);
model->setHeaderData(0, Qt::Horizontal, tr("Bus"));
model->setHeaderData(1, Qt::Horizontal, tr("Type"));
model->insertRows(0, MO_NUM);
for (int i = 0; i < MO_NUM; i++) {
auto idx = model->index(i, 0);
setMOBus(model, idx, mo_drives[i].bus_type, mo_drives[i].res);
setMOType(model, idx.siblingAtColumn(1), mo_drives[i].type);
Harddrives::busTrackClass->device_track(1, DEV_MO, mo_drives[i].bus_type, mo_drives[i].bus_type == MO_BUS_ATAPI ? mo_drives[i].ide_channel : mo_drives[i].scsi_device_id);
}
ui->tableViewMO->resizeColumnsToContents();
ui->tableViewMO->horizontalHeader()->setSectionResizeMode(0, QHeaderView::Stretch);
connect(ui->tableViewMO->selectionModel(), &QItemSelectionModel::currentRowChanged, this, &SettingsOtherRemovable::onMORowChanged);
ui->tableViewMO->setCurrentIndex(model->index(0, 0));
Harddrives::populateRemovableBuses(ui->comboBoxZIPBus->model());
model = new QStandardItemModel(0, 2, this);
ui->tableViewZIP->setModel(model);
model->setHeaderData(0, Qt::Horizontal, tr("Bus"));
model->setHeaderData(1, Qt::Horizontal, tr("Type"));
model->insertRows(0, ZIP_NUM);
for (int i = 0; i < ZIP_NUM; i++) {
auto idx = model->index(i, 0);
setZIPBus(model, idx, zip_drives[i].bus_type, zip_drives[i].res);
setZIPType(model, idx, zip_drives[i].is_250 > 0);
Harddrives::busTrackClass->device_track(1, DEV_ZIP, zip_drives[i].bus_type, zip_drives[i].bus_type == ZIP_BUS_ATAPI ? zip_drives[i].ide_channel : zip_drives[i].scsi_device_id);
}
ui->tableViewZIP->resizeColumnsToContents();
ui->tableViewZIP->horizontalHeader()->setSectionResizeMode(0, QHeaderView::Stretch);
connect(ui->tableViewZIP->selectionModel(), &QItemSelectionModel::currentRowChanged, this, &SettingsOtherRemovable::onZIPRowChanged);
ui->tableViewZIP->setCurrentIndex(model->index(0, 0));
}
SettingsOtherRemovable::~SettingsOtherRemovable()
{
delete ui;
}
void
SettingsOtherRemovable::save()
{
const auto *model = ui->tableViewMO->model();
for (uint8_t i = 0; i < MO_NUM; i++) {
mo_drives[i].fp = NULL;
mo_drives[i].priv = NULL;
mo_drives[i].bus_type = model->index(i, 0).data(Qt::UserRole).toUInt();
mo_drives[i].res = model->index(i, 0).data(Qt::UserRole + 1).toUInt();
mo_drives[i].type = model->index(i, 1).data(Qt::UserRole).toUInt();
}
model = ui->tableViewZIP->model();
for (uint8_t i = 0; i < ZIP_NUM; i++) {
zip_drives[i].fp = NULL;
zip_drives[i].priv = NULL;
zip_drives[i].bus_type = model->index(i, 0).data(Qt::UserRole).toUInt();
zip_drives[i].res = model->index(i, 0).data(Qt::UserRole + 1).toUInt();
zip_drives[i].is_250 = model->index(i, 1).data(Qt::UserRole).toBool() ? 1 : 0;
}
}
void
SettingsOtherRemovable::onMORowChanged(const QModelIndex ¤t)
{
uint8_t bus = current.siblingAtColumn(0).data(Qt::UserRole).toUInt();
uint8_t channel = current.siblingAtColumn(0).data(Qt::UserRole + 1).toUInt();
uint8_t type = current.siblingAtColumn(1).data(Qt::UserRole).toUInt();
ui->comboBoxMOBus->setCurrentIndex(-1);
const auto *model = ui->comboBoxMOBus->model();
auto match = model->match(model->index(0, 0), Qt::UserRole, bus);
if (!match.isEmpty())
ui->comboBoxMOBus->setCurrentIndex(match.first().row());
model = ui->comboBoxMOChannel->model();
match = model->match(model->index(0, 0), Qt::UserRole, channel);
if (!match.isEmpty())
ui->comboBoxMOChannel->setCurrentIndex(match.first().row());
ui->comboBoxMOType->setCurrentIndex(type);
enableCurrentlySelectedChannel_MO();
}
void
SettingsOtherRemovable::onZIPRowChanged(const QModelIndex ¤t)
{
uint8_t bus = current.siblingAtColumn(0).data(Qt::UserRole).toUInt();
uint8_t channel = current.siblingAtColumn(0).data(Qt::UserRole + 1).toUInt();
bool is250 = current.siblingAtColumn(1).data(Qt::UserRole).toBool();
ui->comboBoxZIPBus->setCurrentIndex(-1);
const auto *model = ui->comboBoxZIPBus->model();
auto match = model->match(model->index(0, 0), Qt::UserRole, bus);
if (!match.isEmpty())
ui->comboBoxZIPBus->setCurrentIndex(match.first().row());
model = ui->comboBoxZIPChannel->model();
match = model->match(model->index(0, 0), Qt::UserRole, channel);
if (!match.isEmpty())
ui->comboBoxZIPChannel->setCurrentIndex(match.first().row());
ui->checkBoxZIP250->setChecked(is250);
enableCurrentlySelectedChannel_ZIP();
}
void
SettingsOtherRemovable::reloadBusChannels_MO() {
auto selected = ui->comboBoxMOChannel->currentIndex();
Harddrives::populateBusChannels(ui->comboBoxMOChannel->model(),
ui->comboBoxMOBus->currentData().toInt(), Harddrives::busTrackClass);
ui->comboBoxMOChannel->setCurrentIndex(selected);
enableCurrentlySelectedChannel_MO();
}
void
SettingsOtherRemovable::on_comboBoxMOBus_currentIndexChanged(int index)
{
if (index >= 0) {
int bus = ui->comboBoxMOBus->currentData().toInt();
bool enabled = (bus != MO_BUS_DISABLED);
ui->comboBoxMOChannel->setEnabled(enabled);
ui->comboBoxMOType->setEnabled(enabled);
Harddrives::populateBusChannels(ui->comboBoxMOChannel->model(), bus, Harddrives::busTrackClass);
}
}
void
SettingsOtherRemovable::on_comboBoxMOBus_activated(int)
{
auto i = ui->tableViewMO->selectionModel()->currentIndex().siblingAtColumn(0);
Harddrives::busTrackClass->device_track(0, DEV_MO, ui->tableViewMO->model()->data(i,
Qt::UserRole).toInt(), ui->tableViewMO->model()->data(i,
Qt::UserRole + 1).toInt());
ui->comboBoxMOChannel->setCurrentIndex(ui->comboBoxMOBus->currentData().toUInt() ==
MO_BUS_ATAPI ? Harddrives::busTrackClass->next_free_ide_channel() :
Harddrives::busTrackClass->next_free_scsi_id());
ui->tableViewMO->model()->data(i, Qt::UserRole + 1);
setMOBus(ui->tableViewMO->model(),
ui->tableViewMO->selectionModel()->currentIndex(),
ui->comboBoxMOBus->currentData().toUInt(),
ui->comboBoxMOChannel->currentData().toUInt());
setMOType(ui->tableViewMO->model(),
ui->tableViewMO->selectionModel()->currentIndex(),
ui->comboBoxMOType->currentData().toUInt());
ui->tableViewMO->resizeColumnsToContents();
ui->tableViewMO->horizontalHeader()->setSectionResizeMode(0, QHeaderView::Stretch);
Harddrives::busTrackClass->device_track(1, DEV_MO, ui->tableViewMO->model()->data(i,
Qt::UserRole).toInt(), ui->tableViewMO->model()->data(i,
Qt::UserRole + 1).toInt());
emit moChannelChanged();
}
void
SettingsOtherRemovable::enableCurrentlySelectedChannel_MO()
{
const auto *item_model = qobject_cast<QStandardItemModel*>(ui->comboBoxMOChannel->model());
const auto index = ui->comboBoxMOChannel->currentIndex();
auto *item = item_model->item(index);
if (item)
item->setEnabled(true);
}
void
SettingsOtherRemovable::on_comboBoxMOChannel_activated(int)
{
auto i = ui->tableViewMO->selectionModel()->currentIndex().siblingAtColumn(0);
Harddrives::busTrackClass->device_track(0, DEV_MO, ui->tableViewMO->model()->data(i,
Qt::UserRole).toInt(), ui->tableViewMO->model()->data(i,
Qt::UserRole + 1).toInt());
setMOBus(ui->tableViewMO->model(),
ui->tableViewMO->selectionModel()->currentIndex(),
ui->comboBoxMOBus->currentData().toUInt(),
ui->comboBoxMOChannel->currentData().toUInt());
Harddrives::busTrackClass->device_track(1, DEV_MO, ui->tableViewMO->model()->data(i,
Qt::UserRole).toInt(), ui->tableViewMO->model()->data(i,
Qt::UserRole + 1).toInt());
emit moChannelChanged();
}
void
SettingsOtherRemovable::on_comboBoxMOType_activated(int)
{
setMOType(ui->tableViewMO->model(),
ui->tableViewMO->selectionModel()->currentIndex(),
ui->comboBoxMOType->currentData().toUInt());
ui->tableViewMO->resizeColumnsToContents();
ui->tableViewMO->horizontalHeader()->setSectionResizeMode(0, QHeaderView::Stretch);
}
void
SettingsOtherRemovable::reloadBusChannels_ZIP() {
auto selected = ui->comboBoxZIPChannel->currentIndex();
Harddrives::populateBusChannels(ui->comboBoxZIPChannel->model(),
ui->comboBoxZIPBus->currentData().toInt(), Harddrives::busTrackClass);
ui->comboBoxZIPChannel->setCurrentIndex(selected);
enableCurrentlySelectedChannel_ZIP();
}
void
SettingsOtherRemovable::on_comboBoxZIPBus_currentIndexChanged(int index)
{
if (index >= 0) {
int bus = ui->comboBoxZIPBus->currentData().toInt();
bool enabled = (bus != ZIP_BUS_DISABLED);
ui->comboBoxZIPChannel->setEnabled(enabled);
ui->checkBoxZIP250->setEnabled(enabled);
Harddrives::populateBusChannels(ui->comboBoxZIPChannel->model(), bus, Harddrives::busTrackClass);
}
}
void
SettingsOtherRemovable::on_comboBoxZIPBus_activated(int)
{
auto i = ui->tableViewZIP->selectionModel()->currentIndex().siblingAtColumn(0);
Harddrives::busTrackClass->device_track(0, DEV_ZIP, ui->tableViewZIP->model()->data(i,
Qt::UserRole).toInt(), ui->tableViewZIP->model()->data(i,
Qt::UserRole + 1).toInt());
ui->comboBoxZIPChannel->setCurrentIndex(ui->comboBoxZIPBus->currentData().toUInt() == ZIP_BUS_ATAPI ?
Harddrives::busTrackClass->next_free_ide_channel() :
Harddrives::busTrackClass->next_free_scsi_id());
setZIPBus(ui->tableViewZIP->model(),
ui->tableViewZIP->selectionModel()->currentIndex(),
ui->comboBoxZIPBus->currentData().toUInt(),
ui->comboBoxZIPChannel->currentData().toUInt());
Harddrives::busTrackClass->device_track(1, DEV_ZIP, ui->tableViewZIP->model()->data(i,
Qt::UserRole).toInt(), ui->tableViewZIP->model()->data(i,
Qt::UserRole + 1).toInt());
emit zipChannelChanged();
}
void
SettingsOtherRemovable::enableCurrentlySelectedChannel_ZIP()
{
const auto *item_model = qobject_cast<QStandardItemModel*>(ui->comboBoxZIPChannel->model());
const auto index = ui->comboBoxZIPChannel->currentIndex();
auto *item = item_model->item(index);
if (item)
item->setEnabled(true);
}
void
SettingsOtherRemovable::on_comboBoxZIPChannel_activated(int)
{
auto i = ui->tableViewZIP->selectionModel()->currentIndex().siblingAtColumn(0);
Harddrives::busTrackClass->device_track(0, DEV_ZIP, ui->tableViewZIP->model()->data(i,
Qt::UserRole).toInt(), ui->tableViewZIP->model()->data(i,
Qt::UserRole + 1).toInt());
setZIPBus(ui->tableViewZIP->model(),
ui->tableViewZIP->selectionModel()->currentIndex(),
ui->comboBoxZIPBus->currentData().toUInt(),
ui->comboBoxZIPChannel->currentData().toUInt());
Harddrives::busTrackClass->device_track(1, DEV_ZIP, ui->tableViewZIP->model()->data(i,
Qt::UserRole).toInt(),
ui->tableViewZIP->model()->data(i, Qt::UserRole + 1).toInt());
emit zipChannelChanged();
}
void
SettingsOtherRemovable::on_checkBoxZIP250_stateChanged(int state)
{
setZIPType(ui->tableViewZIP->model(),
ui->tableViewZIP->selectionModel()->currentIndex(),
state == Qt::Checked);
}
``` | /content/code_sandbox/src/qt/qt_settingsotherremovable.cpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,879 |
```c++
#pragma once
class QString;
class QAbstractItemModel;
namespace Models {
int AddEntry(QAbstractItemModel *model, const QString &displayRole, int userRole);
};
``` | /content/code_sandbox/src/qt/qt_models_common.hpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 37 |
```c++
#ifndef QT_SETTINGSSTORAGECONTROLLERS_HPP
#define QT_SETTINGSSTORAGECONTROLLERS_HPP
#include <QWidget>
namespace Ui {
class SettingsStorageControllers;
}
class SettingsStorageControllers : public QWidget {
Q_OBJECT
public:
explicit SettingsStorageControllers(QWidget *parent = nullptr);
~SettingsStorageControllers();
void save();
public slots:
void onCurrentMachineChanged(int machineId);
private slots:
void on_pushButtonSCSI4_clicked();
void on_pushButtonSCSI3_clicked();
void on_pushButtonSCSI2_clicked();
void on_pushButtonSCSI1_clicked();
void on_comboBoxSCSI4_currentIndexChanged(int index);
void on_comboBoxSCSI3_currentIndexChanged(int index);
void on_comboBoxSCSI2_currentIndexChanged(int index);
void on_comboBoxSCSI1_currentIndexChanged(int index);
void on_pushButtonQuaternaryIDE_clicked();
void on_pushButtonTertiaryIDE_clicked();
void on_pushButtonFD_clicked();
void on_pushButtonHD_clicked();
void on_pushButtonCDInterface_clicked();
void on_checkBoxQuaternaryIDE_stateChanged(int arg1);
void on_checkBoxTertiaryIDE_stateChanged(int arg1);
void on_comboBoxFD_currentIndexChanged(int index);
void on_comboBoxHD_currentIndexChanged(int index);
void on_comboBoxCDInterface_currentIndexChanged(int index);
void on_checkBoxLbaEnhancer_stateChanged(int arg1);
void on_pushButtonConfigureLbaEnhancer_clicked();
private:
Ui::SettingsStorageControllers *ui;
int machineId = 0;
};
#endif // QT_SETTINGSSTORAGECONTROLLERS_HPP
``` | /content/code_sandbox/src/qt/qt_settingsstoragecontrollers.hpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 335 |
```c++
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Other peripherals configuration UI module.
*
*
*
* Authors: Joakim L. Gilje <jgilje@jgilje.net>
*
*/
#include "qt_settingsotherperipherals.hpp"
#include "ui_qt_settingsotherperipherals.h"
extern "C" {
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/machine.h>
#include <86box/isamem.h>
#include <86box/isartc.h>
#include <86box/unittester.h>
#include <86box/novell_cardkey.h>
}
#include "qt_deviceconfig.hpp"
#include "qt_models_common.hpp"
SettingsOtherPeripherals::SettingsOtherPeripherals(QWidget *parent)
: QWidget(parent)
, ui(new Ui::SettingsOtherPeripherals)
{
ui->setupUi(this);
onCurrentMachineChanged(machine);
}
void
SettingsOtherPeripherals::onCurrentMachineChanged(int machineId)
{
this->machineId = machineId;
bool machineHasIsa = (machine_has_bus(machineId, MACHINE_BUS_ISA) > 0);
ui->checkBoxISABugger->setChecked((machineHasIsa && (bugger_enabled > 0)) ? true : false);
ui->checkBoxPOSTCard->setChecked(postcard_enabled > 0 ? true : false);
ui->checkBoxUnitTester->setChecked(unittester_enabled > 0 ? true : false);
ui->checkBoxKeyCard->setChecked((machineHasIsa && (novell_keycard_enabled > 0)) ? true : false);
ui->checkBoxISABugger->setEnabled(machineHasIsa);
ui->checkBoxKeyCard->setEnabled(machineHasIsa);
ui->pushButtonConfigureKeyCard->setEnabled(novell_keycard_enabled > 0);
ui->pushButtonConfigureUT->setEnabled(unittester_enabled > 0);
ui->comboBoxRTC->setEnabled(machineHasIsa);
ui->pushButtonConfigureRTC->setEnabled(machineHasIsa);
ui->comboBoxCard1->clear();
ui->comboBoxCard2->clear();
ui->comboBoxCard3->clear();
ui->comboBoxCard4->clear();
ui->comboBoxRTC->clear();
auto *model = ui->comboBoxRTC->model();
int d = 0;
int selectedRow = 0;
while (true) {
QString name = DeviceConfig::DeviceName(isartc_get_device(d), isartc_get_internal_name(d), 0);
if (name.isEmpty()) {
break;
}
if (!device_is_valid(isartc_get_device(d), machineId)) {
break;
}
int row = Models::AddEntry(model, name, d);
if (d == isartc_type) {
selectedRow = row;
}
++d;
}
ui->comboBoxRTC->setCurrentIndex(selectedRow);
ui->pushButtonConfigureRTC->setEnabled((isartc_type != 0) && isartc_has_config(isartc_type) && machineHasIsa);
for (int c = 0; c < ISAMEM_MAX; c++) {
auto *cbox = findChild<QComboBox *>(QString("comboBoxCard%1").arg(c + 1));
model = cbox->model();
d = 0;
selectedRow = 0;
while (true) {
QString name = DeviceConfig::DeviceName(isamem_get_device(d), isamem_get_internal_name(d), 0);
if (name.isEmpty()) {
break;
}
if (!device_is_valid(isamem_get_device(d), machineId)) {
break;
}
int row = Models::AddEntry(model, name, d);
if (d == isamem_type[c]) {
selectedRow = row;
}
++d;
}
cbox->setCurrentIndex(-1);
cbox->setCurrentIndex(selectedRow);
cbox->setEnabled(machineHasIsa);
findChild<QPushButton *>(QString("pushButtonConfigureCard%1").arg(c + 1))->setEnabled((isamem_type[c] != 0) && isamem_has_config(isamem_type[c]) && machineHasIsa);
}
}
SettingsOtherPeripherals::~SettingsOtherPeripherals()
{
delete ui;
}
void
SettingsOtherPeripherals::save()
{
/* Other peripherals category */
bugger_enabled = ui->checkBoxISABugger->isChecked() ? 1 : 0;
postcard_enabled = ui->checkBoxPOSTCard->isChecked() ? 1 : 0;
unittester_enabled = ui->checkBoxUnitTester->isChecked() ? 1 : 0;
novell_keycard_enabled = ui->checkBoxKeyCard->isChecked() ? 1 : 0;
isartc_type = ui->comboBoxRTC->currentData().toInt();
/* ISA memory boards. */
for (int i = 0; i < ISAMEM_MAX; i++) {
auto *cbox = findChild<QComboBox *>(QString("comboBoxCard%1").arg(i + 1));
isamem_type[i] = cbox->currentData().toInt();
}
}
void
SettingsOtherPeripherals::on_comboBoxRTC_currentIndexChanged(int index)
{
if (index < 0) {
return;
}
ui->pushButtonConfigureRTC->setEnabled((index != 0) && isartc_has_config(index) && machine_has_bus(machineId, MACHINE_BUS_ISA));
}
void
SettingsOtherPeripherals::on_pushButtonConfigureRTC_clicked()
{
DeviceConfig::ConfigureDevice(isartc_get_device(ui->comboBoxRTC->currentData().toInt()), 0, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsOtherPeripherals::on_comboBoxCard1_currentIndexChanged(int index)
{
if (index < 0) {
return;
}
ui->pushButtonConfigureCard1->setEnabled((index != 0) && isamem_has_config(index) && machine_has_bus(machineId, MACHINE_BUS_ISA));
}
void
SettingsOtherPeripherals::on_pushButtonConfigureCard1_clicked()
{
DeviceConfig::ConfigureDevice(isamem_get_device(ui->comboBoxCard1->currentData().toInt()), 1, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsOtherPeripherals::on_comboBoxCard2_currentIndexChanged(int index)
{
if (index < 0) {
return;
}
ui->pushButtonConfigureCard2->setEnabled((index != 0) && isamem_has_config(index) && machine_has_bus(machineId, MACHINE_BUS_ISA));
}
void
SettingsOtherPeripherals::on_pushButtonConfigureCard2_clicked()
{
DeviceConfig::ConfigureDevice(isamem_get_device(ui->comboBoxCard2->currentData().toInt()), 2, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsOtherPeripherals::on_comboBoxCard3_currentIndexChanged(int index)
{
if (index < 0) {
return;
}
ui->pushButtonConfigureCard3->setEnabled((index != 0) && isamem_has_config(index) && machine_has_bus(machineId, MACHINE_BUS_ISA));
}
void
SettingsOtherPeripherals::on_pushButtonConfigureCard3_clicked()
{
DeviceConfig::ConfigureDevice(isamem_get_device(ui->comboBoxCard3->currentData().toInt()), 3, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsOtherPeripherals::on_comboBoxCard4_currentIndexChanged(int index)
{
if (index < 0) {
return;
}
ui->pushButtonConfigureCard4->setEnabled((index != 0) && isamem_has_config(index) && machine_has_bus(machineId, MACHINE_BUS_ISA));
}
void
SettingsOtherPeripherals::on_pushButtonConfigureCard4_clicked()
{
DeviceConfig::ConfigureDevice(isamem_get_device(ui->comboBoxCard4->currentData().toInt()), 4, qobject_cast<Settings *>(Settings::settings));
}
void
SettingsOtherPeripherals::on_checkBoxUnitTester_stateChanged(int arg1)
{
ui->pushButtonConfigureUT->setEnabled(arg1 != 0);
}
void
SettingsOtherPeripherals::on_pushButtonConfigureUT_clicked()
{
DeviceConfig::ConfigureDevice(&unittester_device);
}
void SettingsOtherPeripherals::on_pushButtonConfigureKeyCard_clicked()
{
DeviceConfig::ConfigureDevice(&novell_keycard_device);
}
void SettingsOtherPeripherals::on_checkBoxKeyCard_stateChanged(int arg1)
{
ui->pushButtonConfigureKeyCard->setEnabled(arg1 != 0);
}
``` | /content/code_sandbox/src/qt/qt_settingsotherperipherals.cpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,900 |
```c++
#ifndef QT_PROGSETTINGS_HPP
#define QT_PROGSETTINGS_HPP
#include <QDialog>
#include <QTranslator>
namespace Ui {
class ProgSettings;
}
class ProgSettings : public QDialog {
Q_OBJECT
public:
explicit ProgSettings(QWidget *parent = nullptr);
~ProgSettings();
static QString getIconSetPath();
static QIcon loadIcon(QString file);
#ifdef Q_OS_WINDOWS
static QString getFontName(uint32_t lcid);
#endif
static void loadTranslators(QObject *parent = nullptr);
static void reloadStrings();
class CustomTranslator : public QTranslator {
public:
CustomTranslator(QObject *parent = nullptr)
: QTranslator(parent) {};
protected:
QString translate(const char *context, const char *sourceText,
const char *disambiguation = nullptr, int n = -1) const override
{
if (strcmp(sourceText, "&Fullscreen") == 0)
sourceText = "&Fullscreen\tCtrl+Alt+PgUp";
if (strcmp(sourceText, "&Ctrl+Alt+Del") == 0)
sourceText = "&Ctrl+Alt+Del\tCtrl+F12";
if (strcmp(sourceText, "Take s&creenshot") == 0)
sourceText = "Take s&creenshot\tCtrl+F11";
if (strcmp(sourceText, "Begin trace") == 0)
sourceText = "Begin trace\tCtrl+T";
if (strcmp(sourceText, "End trace") == 0)
sourceText = "End trace\tCtrl+T";
QString finalstr = QTranslator::translate("", sourceText, disambiguation, n);
#ifdef Q_OS_MACOS
if (finalstr.contains('\t'))
finalstr.truncate(finalstr.indexOf('\t'));
#endif
return finalstr;
}
};
static CustomTranslator *translator;
static QTranslator *qtTranslator;
static QMap<uint32_t, QPair<QString, QString>> lcid_langcode;
static QMap<int, std::wstring> translatedstrings;
protected slots:
void accept() override;
private slots:
void on_pushButton_released();
void on_pushButtonLanguage_released();
void on_horizontalSlider_valueChanged(int value);
void on_pushButton_2_clicked();
private:
Ui::ProgSettings *ui;
friend class MainWindow;
double mouseSensitivity;
};
#endif // QT_PROGSETTINGS_HPP
``` | /content/code_sandbox/src/qt/qt_progsettings.hpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 514 |
```c++
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Style override class.
*
*
*
* Authors: Teemu Korhonen
*
*/
#include "qt_styleoverride.hpp"
#include <QComboBox>
#include <QAbstractItemView>
int
StyleOverride::styleHint(
StyleHint hint,
const QStyleOption *option,
const QWidget *widget,
QStyleHintReturn *returnData) const
{
/* Disable using menu with alt key */
if (hint == QStyle::SH_MenuBar_AltKeyNavigation)
return 0;
return QProxyStyle::styleHint(hint, option, widget, returnData);
}
void
StyleOverride::polish(QWidget *widget)
{
QProxyStyle::polish(widget);
/* Disable title bar context help buttons globally as they are unused. */
if (widget->isWindow()) {
if (widget->layout() && widget->minimumSize() == widget->maximumSize()) {
if (widget->minimumSize().width() < widget->minimumSizeHint().width()
|| widget->minimumSize().height() < widget->minimumSizeHint().height()) {
widget->setFixedSize(QSize(QWIDGETSIZE_MAX, QWIDGETSIZE_MAX));
widget->layout()->setSizeConstraint(QLayout::SetFixedSize);
}
widget->setWindowFlag(Qt::MSWindowsFixedSizeDialogHint, true);
}
widget->setWindowFlag(Qt::WindowContextHelpButtonHint, false);
}
if (qobject_cast<QComboBox *>(widget)) {
qobject_cast<QComboBox *>(widget)->view()->setMinimumWidth(widget->minimumSizeHint().width());
}
}
``` | /content/code_sandbox/src/qt/qt_styleoverride.cpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 411 |
```c++
#ifndef QT_NEWFLOPPYDIALOG_HPP
#define QT_NEWFLOPPYDIALOG_HPP
#include <QDialog>
namespace Ui {
class NewFloppyDialog;
}
struct disk_size_t;
class QProgressDialog;
class NewFloppyDialog : public QDialog {
Q_OBJECT
public:
enum class MediaType {
Floppy,
Zip,
Mo,
};
enum class FileType {
Img,
Fdi,
Zdi,
Mdi,
};
explicit NewFloppyDialog(MediaType type, QWidget *parent = nullptr);
~NewFloppyDialog();
QString fileName() const;
signals:
void fileProgress(int i);
private slots:
void onCreate();
private:
Ui::NewFloppyDialog *ui;
MediaType mediaType_;
bool create86f(const QString &filename, const disk_size_t &disk_size, uint8_t rpm_mode);
bool createSectorImage(const QString &filename, const disk_size_t &disk_size, FileType type);
bool createZipSectorImage(const QString &filename, const disk_size_t &disk_size, FileType type, QProgressDialog &pbar);
bool createMoSectorImage(const QString &filename, int8_t disk_size, FileType type, QProgressDialog &pbar);
};
#endif // QT_NEWFLOPPYDIALOG_HPP
``` | /content/code_sandbox/src/qt/qt_newfloppydialog.hpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 272 |
```objective-c
#ifndef QT_SPECIFYDIMENSIONS_H
#define QT_SPECIFYDIMENSIONS_H
#include <QDialog>
namespace Ui {
class SpecifyDimensions;
}
class SpecifyDimensions : public QDialog {
Q_OBJECT
public:
explicit SpecifyDimensions(QWidget *parent = nullptr);
~SpecifyDimensions();
private slots:
void on_SpecifyDimensions_accepted();
private:
Ui::SpecifyDimensions *ui;
};
#endif // QT_SPECIFYDIMENSIONS_H
``` | /content/code_sandbox/src/qt/qt_specifydimensions.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 90 |
```c++
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Main entry point module
*
*
* Authors: Joakim L. Gilje <jgilje@jgilje.net>
* Cacodemon345
* Teemu Korhonen
*
*/
#include <QApplication>
#include <QSurfaceFormat>
#include <QDebug>
#include <QElapsedTimer>
#include <QThread>
#include <QTimer>
#include <QTranslator>
#include <QDirIterator>
#include <QLibraryInfo>
#include <QString>
#include <QFont>
#include <QDialog>
#include <QMessageBox>
#include <QPushButton>
#ifdef QT_STATIC
/* Static builds need plugin imports */
# include <QtPlugin>
Q_IMPORT_PLUGIN(QICOPlugin)
# ifdef Q_OS_WINDOWS
Q_IMPORT_PLUGIN(QWindowsIntegrationPlugin)
Q_IMPORT_PLUGIN(QWindowsVistaStylePlugin)
# endif
#endif
#ifdef Q_OS_WINDOWS
# include "qt_winrawinputfilter.hpp"
# include "qt_winmanagerfilter.hpp"
# include <86box/win.h>
# include <shobjidl.h>
#endif
extern "C" {
#include <86box/86box.h>
#include <86box/config.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/video.h>
#ifdef DISCORD
# include <86box/discord.h>
#endif
#include <86box/gdbstub.h>
#include <86box/version.h>
}
#include <thread>
#include <iostream>
#include <memory>
#include "qt_mainwindow.hpp"
#include "qt_progsettings.hpp"
#include "qt_settings.hpp"
#include "cocoa_mouse.hpp"
#include "qt_styleoverride.hpp"
#include "qt_unixmanagerfilter.hpp"
#include "qt_util.hpp"
// Void Cast
#define VC(x) const_cast<wchar_t *>(x)
extern QElapsedTimer elapsed_timer;
extern MainWindow *main_window;
extern "C" {
#include <86box/timer.h>
#include <86box/nvr.h>
extern int qt_nvr_save(void);
}
void qt_set_sequence_auto_mnemonic(bool b);
void
main_thread_fn()
{
int frames;
QThread::currentThread()->setPriority(QThread::HighestPriority);
plat_set_thread_name(nullptr, "main_thread_fn");
framecountx = 0;
// title_update = 1;
uint64_t old_time = elapsed_timer.elapsed();
int drawits = frames = 0;
while (!is_quit && cpu_thread_run) {
/* See if it is time to run a frame of code. */
const uint64_t new_time = elapsed_timer.elapsed();
#ifdef USE_GDBSTUB
if (gdbstub_next_asap && (drawits <= 0))
drawits = 10;
else
#endif
drawits += static_cast<int>(new_time - old_time);
old_time = new_time;
if (drawits > 0 && !dopause) {
/* Yes, so do one frame now. */
drawits -= 10;
if (drawits > 50)
drawits = 0;
#ifdef USE_INSTRUMENT
uint64_t start_time = elapsed_timer.nsecsElapsed();
#endif
/* Run a block of code. */
pc_run();
#ifdef USE_INSTRUMENT
if (instru_enabled) {
uint64_t elapsed_us = (elapsed_timer.nsecsElapsed() - start_time) / 1000;
uint64_t total_elapsed_ms = (uint64_t) ((double) tsc / cpu_s->rspeed * 1000);
printf("[instrument] %llu, %llu\n", total_elapsed_ms, elapsed_us);
if (instru_run_ms && total_elapsed_ms >= instru_run_ms)
break;
}
#endif
/* Every 200 frames we save the machine status. */
if (++frames >= 200 && nvr_dosave) {
qt_nvr_save();
nvr_dosave = 0;
frames = 0;
}
} else {
/* Just so we dont overload the host OS. */
if (dopause)
ack_pause();
std::this_thread::sleep_for(std::chrono::milliseconds(1));
}
}
is_quit = 1;
for (uint8_t i = 1; i < GFXCARD_MAX; i ++) {
if (gfxcard[i]) {
ui_deinit_monitor(i);
std::this_thread::sleep_for(std::chrono::milliseconds(500));
}
}
QTimer::singleShot(0, QApplication::instance(), []() { QApplication::processEvents(); QApplication::instance()->quit(); });
}
static std::thread *main_thread;
int
main(int argc, char *argv[])
{
#if QT_VERSION < QT_VERSION_CHECK(6, 0, 0)
QApplication::setAttribute(Qt::AA_DisableHighDpiScaling, false);
QApplication::setAttribute(Qt::AA_UseHighDpiPixmaps);
QApplication::setAttribute(Qt::AA_EnableHighDpiScaling);
#endif
#if QT_VERSION >= QT_VERSION_CHECK(5, 14, 0)
QApplication::setHighDpiScaleFactorRoundingPolicy(Qt::HighDpiScaleFactorRoundingPolicy::PassThrough);
#endif
QApplication app(argc, argv);
QLocale::setDefault(QLocale::C);
qt_set_sequence_auto_mnemonic(false);
Q_INIT_RESOURCE(qt_resources);
Q_INIT_RESOURCE(qt_translations);
QSurfaceFormat fmt = QSurfaceFormat::defaultFormat();
fmt.setSwapInterval(0);
QSurfaceFormat::setDefaultFormat(fmt);
app.setStyle(new StyleOverride());
#ifdef __APPLE__
CocoaEventFilter cocoafilter;
app.installNativeEventFilter(&cocoafilter);
#endif
elapsed_timer.start();
if (!pc_init(argc, argv)) {
return 0;
}
bool startMaximized = window_remember && monitor_settings[0].mon_window_maximized;
fprintf(stderr, "Qt: version %s, platform \"%s\"\n", qVersion(), QApplication::platformName().toUtf8().data());
ProgSettings::loadTranslators(&app);
#ifdef Q_OS_WINDOWS
QApplication::setFont(QFont(ProgSettings::getFontName(lang_id), 9));
SetCurrentProcessExplicitAppUserModelID(L"86Box.86Box");
#endif
#ifndef Q_OS_MACOS
# ifdef RELEASE_BUILD
app.setWindowIcon(QIcon(":/settings/qt/icons/86Box-green.ico"));
# elif defined ALPHA_BUILD
app.setWindowIcon(QIcon(":/settings/qt/icons/86Box-red.ico"));
# elif defined BETA_BUILD
app.setWindowIcon(QIcon(":/settings/qt/icons/86Box-yellow.ico"));
# else
app.setWindowIcon(QIcon(":/settings/qt/icons/86Box-gray.ico"));
# endif
# ifdef Q_OS_UNIX
app.setDesktopFileName("net.86box.86Box");
# endif
#endif
if (!pc_init_modules()) {
QMessageBox fatalbox(QMessageBox::Icon::Critical, QObject::tr("No ROMs found"),
QObject::tr("86Box could not find any usable ROM images.\n\nPlease <a href=\"path_to_url">download</a> a ROM set and extract it into the \"roms\" directory."),
QMessageBox::Ok);
fatalbox.setTextFormat(Qt::TextFormat::RichText);
fatalbox.exec();
return 6;
}
// UUID / copy / move detection
if(!util::compareUuid()) {
QMessageBox movewarnbox;
movewarnbox.setIcon(QMessageBox::Icon::Warning);
movewarnbox.setText(QObject::tr("This machine might have been moved or copied."));
movewarnbox.setInformativeText(QObject::tr("In order to ensure proper networking functionality, 86Box needs to know if this machine was moved or copied.\n\nSelect \"I Copied It\" if you are not sure."));
const QPushButton *movedButton = movewarnbox.addButton(QObject::tr("I Moved It"), QMessageBox::AcceptRole);
const QPushButton *copiedButton = movewarnbox.addButton(QObject::tr("I Copied It"), QMessageBox::DestructiveRole);
QPushButton *cancelButton = movewarnbox.addButton(QObject::tr("Cancel"), QMessageBox::RejectRole);
movewarnbox.setDefaultButton(cancelButton);
movewarnbox.exec();
if (movewarnbox.clickedButton() == copiedButton) {
util::storeCurrentUuid();
util::generateNewMacAdresses();
} else if (movewarnbox.clickedButton() == movedButton) {
util::storeCurrentUuid();
}
}
#ifdef Q_OS_WINDOWS
# if !defined(EMU_BUILD_NUM) || (EMU_BUILD_NUM != 5624)
HWND winbox = FindWindowW(L"TWinBoxMain", NULL);
if (winbox &&
FindWindowExW(winbox, NULL, L"TToolBar", NULL) &&
FindWindowExW(winbox, NULL, L"TListBox", NULL) &&
FindWindowExW(winbox, NULL, L"TStatusBar", NULL) &&
(winbox = FindWindowExW(winbox, NULL, L"TPageControl", NULL)) && /* holds a TTabSheet even on VM pages */
FindWindowExW(winbox, NULL, L"TTabSheet", NULL))
# endif
{
QMessageBox warningbox(QMessageBox::Icon::Warning, QObject::tr("WinBox is no longer supported"),
QObject::tr("Development of the WinBox manager stopped in 2022 due to a lack of maintainers. As we direct our efforts towards making 86Box even better, we have made the decision to no longer support WinBox as a manager.\n\nNo further updates will be provided through WinBox, and you may encounter incorrect behavior should you continue using it with newer versions of 86Box. Any bug reports related to WinBox behavior will be closed as invalid.\n\nGo to 86box.net for a list of other managers you can use."),
QMessageBox::NoButton);
warningbox.addButton(QObject::tr("Continue"), QMessageBox::AcceptRole);
warningbox.addButton(QObject::tr("Exit"), QMessageBox::RejectRole);
warningbox.exec();
if (warningbox.result() == QDialog::Accepted)
return 0;
}
#endif
if (settings_only) {
Settings settings;
if (settings.exec() == QDialog::Accepted) {
settings.save();
config_save();
}
return 0;
}
/* Warn the user about unsupported configs */
if (cpu_override) {
QMessageBox warningbox(QMessageBox::Icon::Warning, QObject::tr("You are loading an unsupported configuration"),
QObject::tr("CPU type filtering based on selected machine is disabled for this emulated machine.\n\nThis makes it possible to choose a CPU that is otherwise incompatible with the selected machine. However, you may run into incompatibilities with the machine BIOS or other software.\n\nEnabling this setting is not officially supported and any bug reports filed may be closed as invalid."),
QMessageBox::NoButton);
warningbox.addButton(QObject::tr("Continue"), QMessageBox::AcceptRole);
warningbox.addButton(QObject::tr("Exit"), QMessageBox::RejectRole);
warningbox.exec();
if (warningbox.result() == QDialog::Accepted)
return 0;
}
#ifdef DISCORD
discord_load();
#endif
main_window = new MainWindow();
if (startMaximized) {
main_window->showMaximized();
} else {
main_window->show();
}
app.installEventFilter(main_window);
#ifdef Q_OS_WINDOWS
/* Setup VM-manager messages */
std::unique_ptr<WindowsManagerFilter> wmfilter;
if (source_hwnd) {
HWND main_hwnd = (HWND) main_window->winId();
wmfilter.reset(new WindowsManagerFilter());
QObject::connect(wmfilter.get(), &WindowsManagerFilter::showsettings, main_window, &MainWindow::showSettings);
QObject::connect(wmfilter.get(), &WindowsManagerFilter::pause, main_window, &MainWindow::togglePause);
QObject::connect(wmfilter.get(), &WindowsManagerFilter::reset, main_window, &MainWindow::hardReset);
QObject::connect(wmfilter.get(), &WindowsManagerFilter::request_shutdown, main_window, &MainWindow::close);
QObject::connect(wmfilter.get(), &WindowsManagerFilter::force_shutdown, []() {
do_stop();
emit main_window->close();
});
QObject::connect(wmfilter.get(), &WindowsManagerFilter::ctrlaltdel, []() { pc_send_cad(); });
QObject::connect(wmfilter.get(), &WindowsManagerFilter::dialogstatus, [main_hwnd](bool open) {
PostMessage((HWND) (uintptr_t) source_hwnd, WM_SENDDLGSTATUS, (WPARAM) (open ? 1 : 0), (LPARAM) main_hwnd);
});
/* Native filter to catch VM-managers commands */
app.installNativeEventFilter(wmfilter.get());
/* Filter to catch main window being blocked (by modal dialog) */
main_window->installEventFilter(wmfilter.get());
/* Send main window HWND to manager */
PostMessage((HWND) (uintptr_t) source_hwnd, WM_SENDHWND, (WPARAM) unique_id, (LPARAM) main_hwnd);
/* Send shutdown message to manager */
QObject::connect(&app, &QApplication::destroyed, [main_hwnd](QObject *) {
PostMessage((HWND) (uintptr_t) source_hwnd, WM_HAS_SHUTDOWN, (WPARAM) 0, (LPARAM) main_hwnd);
});
}
/* Setup raw input */
auto rawInputFilter = WindowsRawInputFilter::Register(main_window);
if (rawInputFilter) {
app.installNativeEventFilter(rawInputFilter.get());
main_window->setSendKeyboardInput(false);
}
#endif
UnixManagerSocket socket;
if (qgetenv("86BOX_MANAGER_SOCKET").size()) {
QObject::connect(&socket, &UnixManagerSocket::showsettings, main_window, &MainWindow::showSettings);
QObject::connect(&socket, &UnixManagerSocket::pause, main_window, &MainWindow::togglePause);
QObject::connect(&socket, &UnixManagerSocket::resetVM, main_window, &MainWindow::hardReset);
QObject::connect(&socket, &UnixManagerSocket::request_shutdown, main_window, &MainWindow::close);
QObject::connect(&socket, &UnixManagerSocket::force_shutdown, []() {
do_stop();
emit main_window->close();
});
QObject::connect(&socket, &UnixManagerSocket::ctrlaltdel, []() { pc_send_cad(); });
main_window->installEventFilter(&socket);
socket.connectToServer(qgetenv("86BOX_MANAGER_SOCKET"));
}
// pc_reset_hard_init();
QTimer onesec;
QObject::connect(&onesec, &QTimer::timeout, &app, [] {
pc_onesec();
});
onesec.setTimerType(Qt::PreciseTimer);
onesec.start(1000);
#ifdef DISCORD
QTimer discordupdate;
if (discord_loaded) {
QTimer::singleShot(1000, &app, [] {
if (enable_discord) {
discord_init();
discord_update_activity(dopause);
} else
discord_close();
});
QObject::connect(&discordupdate, &QTimer::timeout, &app, [] {
discord_run_callbacks();
});
discordupdate.start(1000);
}
#endif
/* Initialize the rendering window, or fullscreen. */
QTimer::singleShot(0, &app, [] {
pc_reset_hard_init();
main_thread = new std::thread(main_thread_fn);
/* Set the PAUSE mode depending on the renderer. */
#ifdef USE_VNC
if (vnc_enabled && vid_api != 5)
plat_pause(1);
else
#endif
plat_pause(0);
});
const auto ret = app.exec();
cpu_thread_run = 0;
main_thread->join();
pc_close(nullptr);
endblit();
socket.close();
return ret;
}
``` | /content/code_sandbox/src/qt/qt_main.cpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,504 |
```c++
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Definitions for xkbcommon Wayland keyboard input module.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
void xkbcommon_wl_init();
``` | /content/code_sandbox/src/qt/xkbcommon_wl_keyboard.hpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 111 |
```c++
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Machine selection and configuration UI module.
*
*
*
* Authors: Joakim L. Gilje <jgilje@jgilje.net>
*
*/
#include "qt_settingsmachine.hpp"
#include "ui_qt_settingsmachine.h"
#include <QDebug>
#include <QDialog>
#include <QFrame>
#include <QVBoxLayout>
#include <QDialogButtonBox>
#include <algorithm>
extern "C" {
#include "../cpu/cpu.h"
#include <86box/86box.h>
#include <86box/config.h>
#include <86box/device.h>
#include <86box/machine.h>
}
// from nvr.h, which we can't import into CPP code
#define TIME_SYNC_DISABLED 0
#define TIME_SYNC_ENABLED 1
#define TIME_SYNC_UTC 2
#include "qt_deviceconfig.hpp"
#include "qt_models_common.hpp"
SettingsMachine::SettingsMachine(QWidget *parent)
: QWidget(parent)
, ui(new Ui::SettingsMachine)
{
ui->setupUi(this);
switch (time_sync) {
case TIME_SYNC_ENABLED:
ui->radioButtonLocalTime->setChecked(true);
break;
case TIME_SYNC_ENABLED | TIME_SYNC_UTC:
ui->radioButtonUTC->setChecked(true);
break;
case TIME_SYNC_DISABLED:
default:
ui->radioButtonDisabled->setChecked(true);
break;
}
auto warning_icon = QIcon(":/misc/qt/icons/warning.ico");
ui->softFloatWarningIcon->setPixmap(warning_icon.pixmap(warning_icon.actualSize(QSize(16, 16))));
ui->softFloatWarningIcon->setVisible(false);
ui->softFloatWarningText->setVisible(false);
auto *waitStatesModel = ui->comboBoxWaitStates->model();
waitStatesModel->insertRows(0, 9);
auto idx = waitStatesModel->index(0, 0);
waitStatesModel->setData(idx, tr("Default"), Qt::DisplayRole);
waitStatesModel->setData(idx, 0, Qt::UserRole);
for (int i = 0; i < 8; ++i) {
idx = waitStatesModel->index(i + 1, 0);
waitStatesModel->setData(idx, QString::asprintf(tr("%i Wait state(s)").toUtf8().constData(), i), Qt::DisplayRole);
waitStatesModel->setData(idx, i + 1, Qt::UserRole);
}
auto *pitModeModel = ui->comboBoxPitMode->model();
pitModeModel->insertRows(0, 3);
idx = pitModeModel->index(0, 0);
pitModeModel->setData(idx, tr("Auto"), Qt::DisplayRole);
pitModeModel->setData(idx, -1, Qt::UserRole);
idx = pitModeModel->index(1, 0);
pitModeModel->setData(idx, tr("Slow"), Qt::DisplayRole);
pitModeModel->setData(idx, 0, Qt::UserRole);
idx = pitModeModel->index(2, 0);
pitModeModel->setData(idx, tr("Fast"), Qt::DisplayRole);
pitModeModel->setData(idx, 1, Qt::UserRole);
ui->comboBoxPitMode->setCurrentIndex(-1);
ui->comboBoxPitMode->setCurrentIndex(pit_mode + 1);
int selectedMachineType = 0;
auto *machineTypesModel = ui->comboBoxMachineType->model();
for (int i = 1; i < MACHINE_TYPE_MAX; ++i) {
int j = 0;
while (machine_get_internal_name_ex(j) != nullptr) {
if (machine_available(j) && (machine_get_type(j) == i)) {
int row = Models::AddEntry(machineTypesModel, machine_types[i].name, machine_types[i].id);
if (machine_types[i].id == machine_get_type(machine))
selectedMachineType = row;
break;
}
j++;
}
}
ui->comboBoxMachineType->setCurrentIndex(-1);
ui->comboBoxMachineType->setCurrentIndex(selectedMachineType);
#ifndef USE_DYNAREC
ui->checkBoxDynamicRecompiler->setEnabled(false);
ui->checkBoxDynamicRecompiler->setVisible(false);
#endif
}
SettingsMachine::~SettingsMachine()
{
delete ui;
}
void
SettingsMachine::save()
{
machine = ui->comboBoxMachine->currentData().toInt();
cpu_f = const_cast<cpu_family_t *>(&cpu_families[ui->comboBoxCPU->currentData().toInt()]);
cpu = ui->comboBoxSpeed->currentData().toInt();
fpu_type = ui->comboBoxFPU->currentData().toInt();
cpu_use_dynarec = ui->checkBoxDynamicRecompiler->isChecked() ? 1 : 0;
fpu_softfloat = ui->checkBoxFPUSoftfloat->isChecked() ? 1 : 0;
int64_t temp_mem_size;
if (machine_get_ram_granularity(machine) < 1024)
temp_mem_size = ui->spinBoxRAM->value();
else
temp_mem_size = ui->spinBoxRAM->value() * 1024;
temp_mem_size &= ~(machine_get_ram_granularity(machine) - 1);
if (temp_mem_size < machine_get_min_ram(machine))
temp_mem_size = machine_get_min_ram(machine);
else if (temp_mem_size > machine_get_max_ram(machine))
temp_mem_size = machine_get_max_ram(machine);
mem_size = static_cast<uint32_t>(temp_mem_size);
if (ui->comboBoxWaitStates->isEnabled())
cpu_waitstates = ui->comboBoxWaitStates->currentData().toInt();
else
cpu_waitstates = 0;
pit_mode = ui->comboBoxPitMode->currentData().toInt();
time_sync = 0;
if (ui->radioButtonLocalTime->isChecked())
time_sync = TIME_SYNC_ENABLED;
if (ui->radioButtonUTC->isChecked())
time_sync = TIME_SYNC_ENABLED | TIME_SYNC_UTC;
}
void
SettingsMachine::on_comboBoxMachineType_currentIndexChanged(int index)
{
if (index >= 0) {
auto *model = ui->comboBoxMachine->model();
int removeRows = model->rowCount();
int selectedMachineRow = 0;
for (int i = 0; i < machine_count(); ++i) {
if ((machine_get_type(i) == ui->comboBoxMachineType->currentData().toInt()) &&
machine_available(i)) {
int row = Models::AddEntry(model, machines[i].name, i);
if (i == machine)
selectedMachineRow = row - removeRows;
}
}
model->removeRows(0, removeRows);
ui->comboBoxMachine->setCurrentIndex(-1);
ui->comboBoxMachine->setCurrentIndex(selectedMachineRow);
}
}
void
SettingsMachine::on_comboBoxMachine_currentIndexChanged(int index)
{
// win_settings_machine_recalc_machine
if (index >= 0) {
int machineId = ui->comboBoxMachine->currentData().toInt();
const auto *device = machine_get_device(machineId);
ui->pushButtonConfigure->setEnabled((device != nullptr) && (device->config != nullptr));
auto *modelCpu = ui->comboBoxCPU->model();
int removeRows = modelCpu->rowCount();
int i = 0;
int eligibleRows = 0;
int selectedCpuFamilyRow = 0;
while (cpu_families[i].package != 0) {
if (cpu_family_is_eligible(&cpu_families[i], machineId)) {
Models::AddEntry(modelCpu, QString("%1 %2").arg(cpu_families[i].manufacturer,
cpu_families[i].name), i);
if (&cpu_families[i] == cpu_f)
selectedCpuFamilyRow = eligibleRows;
++eligibleRows;
}
++i;
}
modelCpu->removeRows(0, removeRows);
ui->comboBoxCPU->setEnabled(eligibleRows > 1);
ui->comboBoxCPU->setCurrentIndex(-1);
ui->comboBoxCPU->setCurrentIndex(selectedCpuFamilyRow);
int divisor;
if (machine_get_ram_granularity(machineId) < 1024) {
divisor = 1;
ui->spinBoxRAM->setSuffix(QCoreApplication::translate("", "KB").prepend(' '));
} else {
divisor = 1024;
ui->spinBoxRAM->setSuffix(QCoreApplication::translate("", "MB").prepend(' '));
}
ui->spinBoxRAM->setMinimum(machine_get_min_ram(machineId) / divisor);
ui->spinBoxRAM->setMaximum(machine_get_max_ram(machineId) / divisor);
ui->spinBoxRAM->setSingleStep(machine_get_ram_granularity(machineId) / divisor);
ui->spinBoxRAM->setValue(mem_size / divisor);
ui->spinBoxRAM->setEnabled(machine_get_min_ram(machineId) != machine_get_max_ram(machineId));
emit currentMachineChanged(machineId);
}
}
void
SettingsMachine::on_comboBoxCPU_currentIndexChanged(int index)
{
if (index >= 0) {
int machineId = ui->comboBoxMachine->currentData().toInt();
int cpuFamilyId = ui->comboBoxCPU->currentData().toInt();
const auto *cpuFamily = &cpu_families[cpuFamilyId];
auto *modelSpeed = ui->comboBoxSpeed->model();
int removeRows = modelSpeed->rowCount();
// win_settings_machine_recalc_cpu_m
int i = 0;
int eligibleRows = 0;
int selectedSpeedRow = 0;
while (cpuFamily->cpus[i].cpu_type != 0) {
if (cpu_is_eligible(cpuFamily, i, machineId)) {
Models::AddEntry(modelSpeed, QString("%1").arg(cpuFamily->cpus[i].name), i);
if (cpu == i)
selectedSpeedRow = eligibleRows;
++eligibleRows;
}
++i;
}
modelSpeed->removeRows(0, removeRows);
ui->comboBoxSpeed->setEnabled(eligibleRows > 1);
ui->comboBoxSpeed->setCurrentIndex(-1);
ui->comboBoxSpeed->setCurrentIndex(selectedSpeedRow);
}
}
void
SettingsMachine::on_comboBoxSpeed_currentIndexChanged(int index)
{
if (index >= 0) {
// win_settings_machine_recalc_cpu
int cpuFamilyId = ui->comboBoxCPU->currentData().toInt();
const auto *cpuFamily = &cpu_families[cpuFamilyId];
int cpuId = ui->comboBoxSpeed->currentData().toInt();
uint cpuType = cpuFamily->cpus[cpuId].cpu_type;
if ((cpuType >= CPU_286) && (cpuType <= CPU_386DX)) {
ui->comboBoxWaitStates->setEnabled(true);
ui->comboBoxWaitStates->setCurrentIndex(cpu_waitstates);
} else {
ui->comboBoxWaitStates->setCurrentIndex(0);
ui->comboBoxWaitStates->setEnabled(false);
}
#ifdef USE_DYNAREC
uint8_t flags = cpuFamily->cpus[cpuId].cpu_flags;
if (!(flags & CPU_SUPPORTS_DYNAREC)) {
ui->checkBoxDynamicRecompiler->setChecked(false);
ui->checkBoxDynamicRecompiler->setEnabled(false);
} else if ((flags & CPU_REQUIRES_DYNAREC) && !cpu_override) {
ui->checkBoxDynamicRecompiler->setChecked(true);
ui->checkBoxDynamicRecompiler->setEnabled(false);
} else {
ui->checkBoxDynamicRecompiler->setChecked(cpu_use_dynarec);
ui->checkBoxDynamicRecompiler->setEnabled(true);
}
#endif
// win_settings_machine_recalc_fpu
auto *modelFpu = ui->comboBoxFPU->model();
int removeRows = modelFpu->rowCount();
int i = 0;
int selectedFpuRow = 0;
for (const char *fpuName = fpu_get_name_from_index(cpuFamily, cpuId, i);
fpuName != nullptr; fpuName = fpu_get_name_from_index(cpuFamily, cpuId, ++i)) {
auto fpuType = fpu_get_type_from_index(cpuFamily, cpuId, i);
Models::AddEntry(modelFpu, tr(QString("%1").arg(fpuName).toUtf8().data()), fpuType);
if (fpu_type == fpuType)
selectedFpuRow = i;
}
modelFpu->removeRows(0, removeRows);
ui->comboBoxFPU->setEnabled(modelFpu->rowCount() > 1);
ui->comboBoxFPU->setCurrentIndex(-1);
ui->comboBoxFPU->setCurrentIndex(selectedFpuRow);
}
}
void
SettingsMachine::on_comboBoxFPU_currentIndexChanged(int index)
{
if (index >= 0) {
int cpuFamilyId = ui->comboBoxCPU->currentData().toInt();
const auto *cpuFamily = &cpu_families[cpuFamilyId];
int cpuId = ui->comboBoxSpeed->currentData().toInt();
int machineId = ui->comboBoxMachine->currentData().toInt();
if (fpu_get_type_from_index(cpuFamily, cpuId, index) == FPU_NONE) {
ui->checkBoxFPUSoftfloat->setChecked(false);
ui->checkBoxFPUSoftfloat->setEnabled(false);
} else {
ui->checkBoxFPUSoftfloat->setChecked(machine_has_flags(machineId, MACHINE_SOFTFLOAT_ONLY) ?
true : fpu_softfloat);
ui->checkBoxFPUSoftfloat->setEnabled(machine_has_flags(machineId, MACHINE_SOFTFLOAT_ONLY) ?
false : true);
}
}
}
void
SettingsMachine::on_pushButtonConfigure_clicked()
{
// deviceconfig_inst_open
int machineId = ui->comboBoxMachine->currentData().toInt();
const auto *device = machine_get_device(machineId);
DeviceConfig::ConfigureDevice(device, 0, qobject_cast<Settings *>(Settings::settings));
}
void SettingsMachine::on_checkBoxFPUSoftfloat_stateChanged(int state) {
if(state == Qt::Checked) {
ui->softFloatWarningIcon->setVisible(true);
ui->softFloatWarningText->setVisible(true);
} else {
ui->softFloatWarningIcon->setVisible(false);
ui->softFloatWarningText->setVisible(false);
}
}
``` | /content/code_sandbox/src/qt/qt_settingsmachine.cpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,192 |
```c
#define _XOPEN_SOURCE 500
#include <stdio.h>
#include <fcntl.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/log.h>
#include <86box/timer.h>
#include <86box/plat.h>
#include <86box/device.h>
#include <86box/plat_netsocket.h>
#include <86box/ui.h>
#include <winsock2.h>
#include <windows.h>
#include <ws2tcpip.h>
#include <winerror.h>
SOCKET
plat_netsocket_create(int type)
{
SOCKET socket = -1;
u_long yes = 1;
if (type != NET_SOCKET_TCP)
return -1;
socket = WSASocketA(AF_INET, SOCK_STREAM, IPPROTO_TCP, NULL, 0, WSA_FLAG_OVERLAPPED);
if (socket == INVALID_SOCKET)
return -1;
ioctlsocket(socket, FIONBIO, &yes);
return socket;
}
SOCKET
plat_netsocket_create_server(int type, unsigned short port)
{
struct sockaddr_in sock_addr;
SOCKET socket = -1;
u_long yes = 1;
if (type != NET_SOCKET_TCP)
return -1;
socket = WSASocketA(AF_INET, SOCK_STREAM, IPPROTO_TCP, NULL, 0, WSA_FLAG_OVERLAPPED);
if (socket == INVALID_SOCKET)
return -1;
memset(&sock_addr, 0, sizeof(struct sockaddr_in));
sock_addr.sin_family = AF_INET;
sock_addr.sin_addr.s_addr = INADDR_ANY;
sock_addr.sin_port = htons(port);
if (bind(socket, (struct sockaddr *) &sock_addr, sizeof(struct sockaddr_in)) == SOCKET_ERROR) {
plat_netsocket_close(socket);
return (SOCKET) -1;
}
if (listen(socket, 5) == SOCKET_ERROR) {
plat_netsocket_close(socket);
return (SOCKET) -1;
}
ioctlsocket(socket, FIONBIO, &yes);
return socket;
}
void
plat_netsocket_close(SOCKET socket)
{
closesocket((SOCKET) socket);
}
SOCKET
plat_netsocket_accept(SOCKET socket)
{
SOCKET clientsocket = accept(socket, NULL, NULL);
if (clientsocket == INVALID_SOCKET)
return -1;
return clientsocket;
}
int
plat_netsocket_connected(SOCKET socket)
{
struct sockaddr addr;
socklen_t len = sizeof(struct sockaddr);
fd_set wrfds, exfds;
struct timeval tv;
int res = SOCKET_ERROR;
int status = 0;
int optlen = 4;
FD_ZERO(&wrfds);
FD_ZERO(&exfds);
FD_SET(socket, &wrfds);
FD_SET(socket, &exfds);
tv.tv_sec = 0;
tv.tv_usec = 0;
res = select(socket + 1, NULL, &wrfds, &exfds, &tv);
if (res == SOCKET_ERROR)
return -1;
if (res >= 1 && FD_ISSET(socket, &exfds)) {
res = getsockopt(socket, SOL_SOCKET, SO_ERROR, (char *) &status, &optlen);
pclog("Socket error %d\n", status);
return -1;
}
if (res == 0 || !(res >= 1 && FD_ISSET(socket, &wrfds)))
return 0;
res = getsockopt(socket, SOL_SOCKET, SO_ERROR, (char *) &status, &optlen);
if (res == SOCKET_ERROR)
return -1;
if (status != 0)
return -1;
if (getpeername(socket, &addr, &len) == SOCKET_ERROR)
return -1;
return 1;
}
int
plat_netsocket_connect(SOCKET socket, const char *hostname, unsigned short port)
{
struct sockaddr_in sock_addr;
int res = -1;
sock_addr.sin_family = AF_INET;
sock_addr.sin_addr.s_addr = inet_addr(hostname);
sock_addr.sin_port = htons(port);
if (sock_addr.sin_addr.s_addr == INADDR_ANY || sock_addr.sin_addr.s_addr == INADDR_NONE) {
struct hostent *hp;
hp = gethostbyname(hostname);
if (hp)
memcpy(&sock_addr.sin_addr.s_addr, hp->h_addr_list[0], hp->h_length);
else
return -1;
}
res = connect(socket, (struct sockaddr *) &sock_addr, sizeof(struct sockaddr_in));
if (res == SOCKET_ERROR) {
int error = WSAGetLastError();
if (error == WSAEISCONN || error == WSAEWOULDBLOCK)
return 0;
res = -1;
}
return res;
}
int
plat_netsocket_send(SOCKET socket, const unsigned char *data, unsigned int size, int *wouldblock)
{
int res = send(socket, (const char *) data, size, 0);
if (res == SOCKET_ERROR) {
int error = WSAGetLastError();
if (wouldblock)
*wouldblock = !!(error == WSAEWOULDBLOCK);
return -1;
}
return res;
}
int
plat_netsocket_receive(SOCKET socket, unsigned char *data, unsigned int size, int *wouldblock)
{
int res = recv(socket, (char *) data, size, 0);
if (res == SOCKET_ERROR) {
int error = WSAGetLastError();
if (wouldblock)
*wouldblock = !!(error == WSAEWOULDBLOCK);
return -1;
}
return res;
}
``` | /content/code_sandbox/src/qt/win_netsocket.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,257 |
```c++
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Windows VM-managers native messages filter
*
*
*
* Authors: Teemu Korhonen
*
*/
#include "qt_winmanagerfilter.hpp"
#include <windows.h>
#include <86box/win.h>
bool
WindowsManagerFilter::nativeEventFilter(const QByteArray &eventType, void *message, result_t *result)
{
if (eventType == "windows_generic_MSG") {
MSG *msg = static_cast<MSG *>(message);
switch (msg->message) {
case WM_SHOWSETTINGS:
emit showsettings();
return true;
case WM_PAUSE:
emit pause();
return true;
case WM_HARDRESET:
emit reset();
return true;
case WM_SHUTDOWN:
if (msg->wParam == 1)
emit force_shutdown();
else
emit request_shutdown();
return true;
case WM_CTRLALTDEL:
emit ctrlaltdel();
return true;
}
}
return false;
}
bool
WindowsManagerFilter::eventFilter(QObject *obj, QEvent *event)
{
if (event->type() == QEvent::WindowBlocked) {
emit dialogstatus(1);
} else if (event->type() == QEvent::WindowUnblocked) {
emit dialogstatus(0);
}
return QObject::eventFilter(obj, event);
}
``` | /content/code_sandbox/src/qt/qt_winmanagerfilter.cpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 351 |
```c++
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Joystick configuration UI module.
*
*
*
* Authors: Joakim L. Gilje <jgilje@jgilje.net>
*
*/
#include "qt_joystickconfiguration.hpp"
#include "ui_qt_joystickconfiguration.h"
extern "C" {
#include <86box/device.h>
#include <86box/gameport.h>
}
#include <QLabel>
#include <QComboBox>
#include <QDialogButtonBox>
#include "qt_models_common.hpp"
JoystickConfiguration::JoystickConfiguration(int type, int joystick_nr, QWidget *parent)
: QDialog(parent)
, ui(new Ui::JoystickConfiguration)
, type(type)
, joystick_nr(joystick_nr)
{
ui->setupUi(this);
auto model = ui->comboBoxDevice->model();
Models::AddEntry(model, tr("None"), 0);
for (int c = 0; c < joysticks_present; c++) {
Models::AddEntry(model, plat_joystick_state[c].name, c + 1);
}
ui->comboBoxDevice->setCurrentIndex(joystick_state[joystick_nr].plat_joystick_nr);
layout()->setSizeConstraint(QLayout::SetFixedSize);
}
JoystickConfiguration::~JoystickConfiguration()
{
delete ui;
}
int
JoystickConfiguration::selectedDevice()
{
return ui->comboBoxDevice->currentIndex();
}
int
JoystickConfiguration::selectedAxis(int axis)
{
auto *cbox = findChild<QComboBox *>(QString("cboxAxis%1").arg(QString::number(axis)));
if (cbox == nullptr) {
return 0;
}
return cbox->currentIndex();
}
int
JoystickConfiguration::selectedButton(int button)
{
auto *cbox = findChild<QComboBox *>(QString("cboxButton%1").arg(QString::number(button)));
if (cbox == nullptr) {
return 0;
}
return cbox->currentIndex();
}
int
JoystickConfiguration::selectedPov(int pov)
{
auto *cbox = findChild<QComboBox *>(QString("cboxPov%1").arg(QString::number(pov)));
if (cbox == nullptr) {
return 0;
}
return cbox->currentIndex();
}
void
JoystickConfiguration::on_comboBoxDevice_currentIndexChanged(int index)
{
for (auto w : widgets) {
ui->ct->removeWidget(w);
w->deleteLater();
}
widgets.clear();
if (index == 0) {
return;
}
int joystick = index - 1;
int row = 0;
for (int c = 0; c < joystick_get_axis_count(type); c++) {
/*Combo box*/
auto label = new QLabel(joystick_get_axis_name(type, c), this);
auto cbox = new QComboBox(this);
cbox->setObjectName(QString("cboxAxis%1").arg(QString::number(c)));
cbox->setMaxVisibleItems(30);
auto model = cbox->model();
for (int d = 0; d < plat_joystick_state[joystick].nr_axes; d++) {
Models::AddEntry(model, plat_joystick_state[joystick].axis[d].name, 0);
}
for (int d = 0; d < plat_joystick_state[joystick].nr_povs; d++) {
Models::AddEntry(model, tr("%1 (X axis)").arg(plat_joystick_state[joystick].pov[d].name), 0);
Models::AddEntry(model, tr("%1 (Y axis)").arg(plat_joystick_state[joystick].pov[d].name), 0);
}
int nr_axes = plat_joystick_state[joystick].nr_axes;
int mapping = joystick_state[joystick_nr].axis_mapping[c];
if (mapping & POV_X)
cbox->setCurrentIndex(nr_axes + (mapping & 3) * 2);
else if (mapping & POV_Y)
cbox->setCurrentIndex(nr_axes + (mapping & 3) * 2 + 1);
else
cbox->setCurrentIndex(mapping);
ui->ct->addWidget(label, row, 0);
ui->ct->addWidget(cbox, row, 1);
widgets.append(label);
widgets.append(cbox);
++row;
}
for (int c = 0; c < joystick_get_button_count(type); c++) {
auto label = new QLabel(joystick_get_button_name(type, c), this);
auto cbox = new QComboBox(this);
cbox->setObjectName(QString("cboxButton%1").arg(QString::number(c)));
cbox->setMaxVisibleItems(30);
auto model = cbox->model();
for (int d = 0; d < plat_joystick_state[joystick].nr_buttons; d++) {
Models::AddEntry(model, plat_joystick_state[joystick].button[d].name, 0);
}
cbox->setCurrentIndex(joystick_state[joystick_nr].button_mapping[c]);
ui->ct->addWidget(label, row, 0);
ui->ct->addWidget(cbox, row, 1);
widgets.append(label);
widgets.append(cbox);
++row;
}
for (int c = 0; c < joystick_get_pov_count(type) * 2; c++) {
QLabel *label;
if (c & 1) {
label = new QLabel(tr("%1 (Y axis)").arg(joystick_get_pov_name(type, c / 2)), this);
} else {
label = new QLabel(tr("%1 (X axis)").arg(joystick_get_pov_name(type, c / 2)), this);
}
auto cbox = new QComboBox(this);
cbox->setObjectName(QString("cboxPov%1").arg(QString::number(c)));
cbox->setMaxVisibleItems(30);
auto model = cbox->model();
for (int d = 0; d < plat_joystick_state[joystick].nr_povs; d++) {
Models::AddEntry(model, tr("%1 (X axis)").arg(plat_joystick_state[joystick].pov[d].name), 0);
Models::AddEntry(model, tr("%1 (Y axis)").arg(plat_joystick_state[joystick].pov[d].name), 0);
}
for (int d = 0; d < plat_joystick_state[joystick].nr_axes; d++) {
Models::AddEntry(model, plat_joystick_state[joystick].axis[d].name, 0);
}
int mapping = joystick_state[joystick_nr].pov_mapping[c / 2][c & 1];
int nr_povs = plat_joystick_state[joystick].nr_povs;
if (mapping & POV_X)
cbox->setCurrentIndex((mapping & 3) * 2);
else if (mapping & POV_Y)
cbox->setCurrentIndex((mapping & 3) * 2 + 1);
else
cbox->setCurrentIndex(mapping + nr_povs * 2);
ui->ct->addWidget(label, row, 0);
ui->ct->addWidget(cbox, row, 1);
widgets.append(label);
widgets.append(cbox);
++row;
}
}
``` | /content/code_sandbox/src/qt/qt_joystickconfiguration.cpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,635 |
```c++
#ifndef QT_SETTINGSFLOPPYCDROM_HPP
#define QT_SETTINGSFLOPPYCDROM_HPP
#include <QWidget>
namespace Ui {
class SettingsFloppyCDROM;
}
class SettingsFloppyCDROM : public QWidget {
Q_OBJECT
public:
explicit SettingsFloppyCDROM(QWidget *parent = nullptr);
~SettingsFloppyCDROM();
void reloadBusChannels();
void save();
signals:
void cdromChannelChanged();
private slots:
void on_comboBoxCDROMType_activated(int index);
void on_comboBoxChannel_activated(int index);
void on_comboBoxBus_activated(int index);
void on_comboBoxSpeed_activated(int index);
void on_comboBoxBus_currentIndexChanged(int index);
void on_comboBoxFloppyType_activated(int index);
void on_checkBoxCheckBPB_stateChanged(int arg1);
void on_checkBoxTurboTimings_stateChanged(int arg1);
void onFloppyRowChanged(const QModelIndex ¤t);
void onCDROMRowChanged(const QModelIndex ¤t);
private:
Ui::SettingsFloppyCDROM *ui;
void enableCurrentlySelectedChannel();
};
#endif // QT_SETTINGSFLOPPYCDROM_HPP
``` | /content/code_sandbox/src/qt/qt_settingsfloppycdrom.hpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 253 |
```c++
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Program settings UI module.
*
*
*
* Authors: Cacodemon345
*
*/
#include <QDebug>
#include "qt_progsettings.hpp"
#include "ui_qt_progsettings.h"
#include "qt_mainwindow.hpp"
#include "ui_qt_mainwindow.h"
#include "qt_machinestatus.hpp"
#include <QMap>
#include <QDir>
#include <QFile>
#include <QLibraryInfo>
extern "C" {
#include <86box/86box.h>
#include <86box/version.h>
#include <86box/config.h>
#include <86box/plat.h>
#include <86box/mem.h>
#include <86box/rom.h>
}
static QMap<QString, QString> iconset_to_qt;
extern MainWindow *main_window;
ProgSettings::CustomTranslator *ProgSettings::translator = nullptr;
QTranslator *ProgSettings::qtTranslator = nullptr;
QString
ProgSettings::getIconSetPath()
{
if (iconset_to_qt.isEmpty()) {
// Always include default bundled icons
iconset_to_qt.insert("", ":/settings/qt/icons");
// Walk rom_paths to get the candidates
for (rom_path_t *emu_rom_path = &rom_paths; emu_rom_path != nullptr; emu_rom_path = emu_rom_path->next) {
// Check for icons subdir in each candidate
QDir roms_icons_dir(QString(emu_rom_path->path) + "/icons");
if (roms_icons_dir.isReadable()) {
auto dirList = roms_icons_dir.entryList(QDir::AllDirs | QDir::Executable | QDir::Readable);
for (auto &curIconSet : dirList) {
if (curIconSet == "." || curIconSet == "..") {
continue;
}
iconset_to_qt.insert(curIconSet, (roms_icons_dir.canonicalPath() + '/') + curIconSet);
}
}
}
}
return iconset_to_qt[icon_set];
}
QIcon
ProgSettings::loadIcon(QString file)
{
(void) getIconSetPath();
if (!QFile::exists(iconset_to_qt[icon_set] + file))
return QIcon(iconset_to_qt[""] + file);
return QIcon(iconset_to_qt[icon_set] + file);
}
ProgSettings::ProgSettings(QWidget *parent)
: QDialog(parent)
, ui(new Ui::ProgSettings)
{
ui->setupUi(this);
(void) getIconSetPath();
ui->comboBox->setItemData(0, "");
ui->comboBox->setCurrentIndex(0);
for (auto i = iconset_to_qt.begin(); i != iconset_to_qt.end(); i++) {
if (i.key() == "")
continue;
QFile iconfile(i.value() + "/iconinfo.txt");
iconfile.open(QFile::ReadOnly);
QString friendlyName;
QString iconsetinfo(iconfile.readAll());
iconfile.close();
if (iconsetinfo.isEmpty())
friendlyName = i.key();
else
friendlyName = iconsetinfo.split('\n')[0];
ui->comboBox->addItem(friendlyName, i.key());
if (strcmp(icon_set, i.key().toUtf8().data()) == 0) {
ui->comboBox->setCurrentIndex(ui->comboBox->findData(i.key()));
}
}
ui->comboBox->setItemData(0, '(' + tr("Default") + ')', Qt::DisplayRole);
ui->comboBoxLanguage->setItemData(0, 0xFFFF);
for (auto i = lcid_langcode.begin(); i != lcid_langcode.end(); i++) {
if (i.key() == 0xFFFF)
continue;
ui->comboBoxLanguage->addItem(lcid_langcode[i.key()].second, i.key());
if (i.key() == lang_id) {
ui->comboBoxLanguage->setCurrentIndex(ui->comboBoxLanguage->findData(i.key()));
}
}
ui->comboBoxLanguage->model()->sort(Qt::AscendingOrder);
mouseSensitivity = mouse_sensitivity;
ui->horizontalSlider->setValue(mouseSensitivity * 100.);
ui->openDirUsrPath->setChecked(open_dir_usr_path > 0);
}
void
ProgSettings::accept()
{
strcpy(icon_set, ui->comboBox->currentData().toString().toUtf8().data());
lang_id = ui->comboBoxLanguage->currentData().toUInt();
open_dir_usr_path = ui->openDirUsrPath->isChecked() ? 1 : 0;
loadTranslators(QCoreApplication::instance());
reloadStrings();
update_mouse_msg();
main_window->ui->retranslateUi(main_window);
QString vmname(vm_name);
if (vmname.at(vmname.size() - 1) == '"' || vmname.at(vmname.size() - 1) == '\'')
vmname.truncate(vmname.size() - 1);
main_window->setWindowTitle(QString("%1 - %2 %3").arg(vmname, EMU_NAME, EMU_VERSION_FULL));
QString msg = main_window->status->getMessage();
main_window->status.reset(new MachineStatus(main_window));
main_window->refreshMediaMenu();
main_window->status->message(msg);
connect(main_window, &MainWindow::updateStatusBarTip, main_window->status.get(), &MachineStatus::updateTip);
connect(main_window, &MainWindow::statusBarMessage, main_window->status.get(), &MachineStatus::message, Qt::QueuedConnection);
mouse_sensitivity = mouseSensitivity;
QDialog::accept();
}
ProgSettings::~ProgSettings()
{
delete ui;
}
void
ProgSettings::on_pushButton_released()
{
ui->comboBox->setCurrentIndex(0);
}
#ifdef Q_OS_WINDOWS
/* Return the standard font name on Windows, which is overridden per-language
to prevent CJK fonts with embedded bitmaps being chosen as a fallback. */
QString
ProgSettings::getFontName(uint32_t lcid)
{
switch (lcid) {
case 0x0404: /* zh-TW */
return "Microsoft JhengHei";
case 0x0411: /* ja-JP */
return "Meiryo UI";
case 0x0412: /* ko-KR */
return "Malgun Gothic";
case 0x0804: /* zh-CN */
return "Microsoft YaHei";
default:
return "Segoe UI";
}
}
#endif
void
ProgSettings::loadTranslators(QObject *parent)
{
if (qtTranslator) {
QApplication::removeTranslator(qtTranslator);
qtTranslator = nullptr;
}
if (translator) {
QApplication::removeTranslator(translator);
translator = nullptr;
}
qtTranslator = new QTranslator(parent);
translator = new CustomTranslator(parent);
QString localetofilename = "";
if (lang_id == 0xFFFF || lcid_langcode.contains(lang_id) == false) {
for (int i = 0; i < QLocale::system().uiLanguages().size(); i++) {
localetofilename = QLocale::system().uiLanguages()[i];
if (translator->load(QLatin1String("86box_") + localetofilename, QLatin1String(":/"))) {
qDebug() << "Translations loaded.\n";
QCoreApplication::installTranslator(translator);
if (!qtTranslator->load(QLatin1String("qtbase_") + localetofilename.replace('-', '_'), QLibraryInfo::location(QLibraryInfo::TranslationsPath)))
qtTranslator->load(QLatin1String("qt_") + localetofilename.replace('-', '_'), QApplication::applicationDirPath() + "/./translations/");
if (QApplication::installTranslator(qtTranslator)) {
qDebug() << "Qt translations loaded."
<< "\n";
}
break;
}
}
} else {
translator->load(QLatin1String("86box_") + lcid_langcode[lang_id].first, QLatin1String(":/"));
QCoreApplication::installTranslator(translator);
if (!qtTranslator->load(QLatin1String("qtbase_") + QString(lcid_langcode[lang_id].first).replace('-', '_'), QLibraryInfo::location(QLibraryInfo::TranslationsPath)))
qtTranslator->load(QLatin1String("qt_") + QString(lcid_langcode[lang_id].first).replace('-', '_'), QApplication::applicationDirPath() + "/./translations/");
QCoreApplication::installTranslator(qtTranslator);
}
}
void
ProgSettings::on_pushButtonLanguage_released()
{
ui->comboBoxLanguage->setCurrentIndex(0);
}
void
ProgSettings::on_horizontalSlider_valueChanged(int value)
{
mouseSensitivity = (double) value / 100.;
}
void
ProgSettings::on_pushButton_2_clicked()
{
mouseSensitivity = 1.0;
ui->horizontalSlider->setValue(100);
}
``` | /content/code_sandbox/src/qt/qt_progsettings.cpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,964 |
```c++
#pragma once
#include <QOpenGLFunctions>
#include <QOpenGLBuffer>
#include <QOpenGLWindow>
#include <QOpenGLVertexArrayObject>
#include <QOpenGLTexture>
#include <QOpenGLShader>
#include <QOpenGLShaderProgram>
#include <QOpenGLTextureBlitter>
#include <QOpenGLPixelTransferOptions>
#include <QPainter>
#include <QEvent>
#include <QKeyEvent>
#include <QWidget>
#include <atomic>
#include <mutex>
#include <array>
#include <vector>
#include <memory>
#include <QApplication>
#include "qt_renderercommon.hpp"
#ifdef WAYLAND
# include "wl_mouse.hpp"
#endif
class HardwareRenderer : public QOpenGLWindow, protected QOpenGLFunctions, public RendererCommon {
Q_OBJECT
private:
bool wayland = false;
QOpenGLContext *m_context;
QOpenGLTexture *m_texture { nullptr };
QOpenGLShaderProgram *m_prog { nullptr };
QOpenGLTextureBlitter *m_blt { nullptr };
QOpenGLBuffer m_vbo[2];
QOpenGLVertexArrayObject m_vao;
QOpenGLPixelTransferOptions m_transferOptions;
public:
enum class RenderType {
OpenGL,
OpenGLES,
OpenGL3,
};
void resizeGL(int w, int h) override;
void initializeGL() override;
void paintGL() override;
void exposeEvent(QExposeEvent *event) override
{
onResize(size().width(), size().height());
}
std::vector<std::tuple<uint8_t *, std::atomic_flag *>> getBuffers() override;
HardwareRenderer(QWidget *parent = nullptr, RenderType rtype = RenderType::OpenGL)
: QOpenGLWindow(QOpenGLWindow::NoPartialUpdate, parent->windowHandle())
, QOpenGLFunctions()
{
imagebufs[0] = std::unique_ptr<uint8_t>(new uint8_t[2048 * 2048 * 4]);
imagebufs[1] = std::unique_ptr<uint8_t>(new uint8_t[2048 * 2048 * 4]);
buf_usage = std::vector<std::atomic_flag>(2);
buf_usage[0].clear();
buf_usage[1].clear();
setMinimumSize(QSize(16, 16));
setFlags(Qt::FramelessWindowHint);
parentWidget = parent;
setRenderType(rtype);
m_transferOptions.setRowLength(2048);
m_context = new QOpenGLContext();
m_context->setFormat(format());
m_context->create();
update();
}
~HardwareRenderer()
{
m_context->makeCurrent(this);
if (m_blt)
m_blt->destroy();
m_prog->release();
delete m_prog;
m_prog = nullptr;
m_context->doneCurrent();
delete m_context;
}
void setRenderType(RenderType type);
public slots:
void onBlit(int buf_idx, int x, int y, int w, int h);
protected:
std::array<std::unique_ptr<uint8_t>, 2> imagebufs;
void resizeEvent(QResizeEvent *event) override;
bool event(QEvent *event) override;
};
``` | /content/code_sandbox/src/qt/qt_hardwarerenderer.hpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 683 |
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