repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
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| content
stringlengths 15
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| license
stringclasses 14
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|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o_4.v | 2,469 | module MODULE2 (
VAR6 ,
VAR2 ,
VAR11 ,
VAR9 ,
VAR8 ,
VAR4 ,
VAR5,
VAR12,
VAR3 ,
VAR7
);
output VAR6 ;
input VAR2 ;
input VAR11 ;
input VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR5;
input VAR12;
input VAR3 ;
input VAR7 ;
VAR10 VAR1 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR6 ,
VAR2,
VAR11,
VAR9,
VAR8,
VAR4
);
output VAR6 ;
input VAR2;
input VAR11;
input VAR9;
input VAR8;
input VAR4;
supply1 VAR5;
supply0 VAR12;
supply1 VAR3 ;
supply0 VAR7 ;
VAR10 VAR1 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/maj3/sky130_fd_sc_ls__maj3.behavioral.v | 1,581 | module MODULE1 (
VAR1,
VAR6,
VAR5,
VAR13
);
output VAR1;
input VAR6;
input VAR5;
input VAR13;
supply1 VAR8;
supply0 VAR11;
supply1 VAR17 ;
supply0 VAR12 ;
wire VAR3 ;
wire VAR7 ;
wire VAR4 ;
wire VAR9;
or VAR10 (VAR3 , VAR5, VAR6 );
and VAR15 (VAR7 , VAR3, VAR13 );
and VAR16 (VAR4 , VAR6, VAR5 );
or VAR2 (VAR9, VAR4, VAR7);
buf VAR14 (VAR1 , VAR9 );
endmodule | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/image_filter_AXIvideo2Mat.v | 29,950 | module MODULE1 (
VAR11,
VAR53,
VAR75,
VAR116,
VAR24,
VAR27,
VAR26,
VAR90,
VAR74,
VAR54,
VAR88,
VAR48,
VAR34,
VAR92,
VAR12,
VAR117,
VAR98,
VAR68,
VAR10,
VAR47,
VAR112,
VAR83,
VAR100,
VAR113,
VAR85,
VAR84,
VAR66
);
parameter VAR25 = 1'b1;
parameter VAR43 = 1'b0;
parameter VAR96 = 7'b1;
parameter VAR108 = 7'b10;
parameter VAR17 = 7'b100;
parameter VAR35 = 7'b1000;
parameter VAR23 = 7'b10000;
parameter VAR40 = 7'b100000;
parameter VAR3 = 7'b1000000;
parameter VAR19 = 32'b00000000000000000000000000000000;
parameter VAR55 = 1'b1;
parameter VAR82 = 32'b1;
parameter VAR30 = 32'b11;
parameter VAR18 = 32'b100;
parameter VAR87 = 1'b0;
parameter VAR50 = 32'b101;
parameter VAR58 = 32'b110;
parameter VAR42 = 32'b10;
parameter VAR64 = 12'b000000000000;
parameter VAR5 = 12'b1;
parameter VAR37 = 32'b1000;
parameter VAR16 = 32'b1111;
parameter VAR56 = 32'b10000;
parameter VAR106 = 32'b10111;
parameter VAR80 = 1'b1;
input VAR11;
input VAR53;
input VAR75;
output VAR116;
input VAR24;
output VAR27;
output VAR26;
input [31:0] VAR90;
input VAR74;
output VAR54;
input [3:0] VAR88;
input [3:0] VAR48;
input [0:0] VAR34;
input [0:0] VAR92;
input [0:0] VAR12;
input [0:0] VAR117;
input [11:0] VAR98;
input [11:0] VAR68;
output [7:0] VAR10;
input VAR47;
output VAR112;
output [7:0] VAR83;
input VAR100;
output VAR113;
output [7:0] VAR85;
input VAR84;
output VAR66;
reg VAR116;
reg VAR27;
reg VAR26;
reg VAR54;
reg VAR112;
reg VAR113;
reg VAR66;
reg VAR60 = 1'b0;
reg [6:0] VAR70 = 7'b1;
reg VAR119;
reg VAR51;
reg [0:0] VAR14;
reg [31:0] VAR39;
reg [11:0] VAR105;
reg [0:0] VAR78;
reg [0:0] VAR109;
reg [31:0] VAR52;
reg [0:0] VAR69;
reg VAR107;
reg [31:0] VAR41;
reg VAR65;
reg VAR73;
reg [0:0] VAR57;
wire [0:0] VAR97;
reg VAR110;
reg VAR115;
wire [11:0] VAR59;
reg [11:0] VAR28;
wire [0:0] VAR9;
reg [0:0] VAR86;
reg VAR2;
reg VAR99;
wire [0:0] VAR71;
reg VAR13;
reg VAR111 = 1'b0;
reg VAR81;
reg VAR120 = 1'b0;
wire [11:0] VAR102;
wire [7:0] VAR118;
reg [7:0] VAR94;
reg [7:0] VAR104;
reg [7:0] VAR8;
reg VAR49;
reg VAR20;
reg VAR62;
reg [0:0] VAR67;
reg [0:0] VAR77;
reg VAR93;
reg VAR72;
reg VAR114;
reg VAR61;
reg [31:0] VAR21;
reg [31:0] VAR44;
reg [11:0] VAR33;
reg [0:0] VAR32;
reg [31:0] VAR38;
reg [0:0] VAR101;
wire [0:0] VAR6;
wire [31:0] VAR79;
reg [31:0] VAR46;
wire [0:0] VAR1;
wire [0:0] VAR45;
reg [0:0] VAR63;
reg [0:0] VAR76;
wire [0:0] VAR91;
wire [0:0] VAR36;
reg [6:0] VAR4;
reg VAR7;
reg VAR31;
reg VAR103;
reg VAR29;
always @ (posedge VAR11)
begin : VAR95
if (VAR53 == 1'b1) begin
VAR70 <= VAR96;
end else begin
VAR70 <= VAR4;
end
end
always @ (posedge VAR11)
begin : VAR15
if (VAR53 == 1'b1) begin
VAR60 <= VAR43;
end else begin
if ((VAR25 == VAR24)) begin
VAR60 <= VAR43;
end else if (((VAR25 == VAR110) & ~(VAR97 == VAR87))) begin
VAR60 <= VAR25;
end
end
end
always @ (posedge VAR11)
begin : VAR121
if (VAR53 == 1'b1) begin
VAR111 <= VAR43;
end else begin
if (((VAR25 == VAR2) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))) & ~(VAR9 == VAR87))) begin
VAR111 <= VAR43;
end else if (((VAR25 == VAR110) & (VAR97 == VAR87))) begin
VAR111 <= VAR25;
end
end
end
always @ (posedge VAR11)
begin : VAR89
if (VAR53 == 1'b1) begin
VAR120 <= VAR43;
end else begin
if (((VAR25 == VAR2) & (VAR9 == VAR87) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))))) begin
VAR120 <= VAR25;
end else if ((((VAR25 == VAR110) & (VAR97 == VAR87)) | ((VAR25 == VAR2) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))) & ~(VAR9 == VAR87)))) begin
VAR120 <= VAR43;
end
end
end
always @(posedge VAR11)
begin
if ((VAR25 == VAR114)) begin
VAR44 <= VAR41;
end else if ((VAR25 == VAR93)) begin
VAR44 <= VAR21;
end
end
always @(posedge VAR11)
begin
if (((VAR25 == VAR2) & (VAR86 == VAR87) & (VAR25 == VAR120) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))))) begin
VAR39 <= VAR52;
end else if (((VAR25 == VAR110) & (VAR97 == VAR87))) begin
VAR39 <= VAR44;
end
end
always @(posedge VAR11)
begin
if (((VAR25 == VAR2) & (VAR25 == VAR111) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))) & ~(VAR9 == VAR87))) begin
VAR21 <= VAR38;
end else if (((VAR25 == VAR49) & (VAR87 == VAR63) & ~VAR62)) begin
VAR21 <= VAR90;
end
end
always @(posedge VAR11)
begin
if ((VAR25 == VAR114)) begin
VAR77 <= VAR57;
end else if ((VAR25 == VAR93)) begin
VAR77 <= VAR67;
end
end
always @(posedge VAR11)
begin
if (VAR103) begin
if (VAR31) begin
VAR109 <= VAR32;
end else if (VAR7) begin
VAR109 <= VAR92;
end else if ((VAR80 == VAR80)) begin
VAR109 <= VAR6;
end
end
end
always @(posedge VAR11)
begin
if (((VAR25 == VAR2) & (VAR25 == VAR111) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))) & ~(VAR9 == VAR87))) begin
VAR67 <= VAR32;
end else if (((VAR25 == VAR49) & (VAR87 == VAR63) & ~VAR62)) begin
VAR67 <= VAR92;
end
end
always @(posedge VAR11)
begin
if (((VAR25 == VAR2) & (VAR86 == VAR87) & (VAR25 == VAR120) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))))) begin
VAR14 <= VAR109;
end else if (((VAR25 == VAR110) & (VAR97 == VAR87))) begin
VAR14 <= VAR77;
end
end
always @(posedge VAR11)
begin
if (VAR103) begin
if (VAR31) begin
VAR69 <= VAR45;
end else if (VAR7) begin
VAR69 <= VAR92;
end else if ((VAR80 == VAR80)) begin
VAR69 <= VAR1;
end
end
end
always @(posedge VAR11)
begin
if (((VAR25 == VAR2) & (VAR25 == VAR111) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))) & ~(VAR9 == VAR87))) begin
VAR63 <= VAR101;
end else if (((VAR25 == VAR49) & (VAR87 == VAR63) & ~VAR62)) begin
VAR63 <= VAR92;
end
end
always @(posedge VAR11)
begin
if (((VAR25 == VAR2) & (VAR86 == VAR87) & (VAR25 == VAR120) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))))) begin
VAR78 <= VAR69;
end else if (((VAR25 == VAR110) & (VAR97 == VAR87))) begin
VAR78 <= VAR87;
end
end
always @(posedge VAR11)
begin
if (((VAR25 == VAR2) & (VAR9 == VAR87) & (VAR25 == VAR111) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))))) begin
VAR105 <= VAR102;
end else if (((VAR25 == VAR110) & (VAR97 == VAR87))) begin
VAR105 <= VAR64;
end
end
always @(posedge VAR11)
begin
if (VAR103) begin
if (VAR31) begin
VAR52 <= VAR38;
end else if (VAR7) begin
VAR52 <= VAR90;
end else if ((VAR80 == VAR80)) begin
VAR52 <= VAR79;
end
end
end
always @(posedge VAR11)
begin
if ((VAR25 == VAR114)) begin
VAR33 <= VAR64;
end else if ((VAR25 == VAR93)) begin
VAR33 <= VAR28;
end
end
always @(posedge VAR11)
begin
if (((VAR25 == VAR2) & (VAR9 == VAR87) & (VAR25 == VAR111) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))))) begin
VAR76 <= VAR87;
end else if ((VAR25 == VAR114)) begin
VAR76 <= VAR55;
end
end
always @(posedge VAR11)
begin
if (((VAR25 == VAR2) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))))) begin
VAR86 <= VAR9;
end
end
always @(posedge VAR11)
begin
if ((VAR25 == VAR110)) begin
VAR28 <= VAR59;
end
end
always @(posedge VAR11)
begin
if (((VAR25 == VAR2) & (VAR9 == VAR87) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))))) begin
VAR94 <= VAR118;
VAR104 <= {{VAR46[VAR16 : VAR37]}};
VAR8 <= {{VAR46[VAR106 : VAR56]}};
end
end
always @(posedge VAR11)
begin
if (((VAR25 == VAR65) & ~(VAR74 == VAR43))) begin
VAR41 <= VAR90;
VAR57 <= VAR92;
end
end
always @ (VAR74 or VAR65 or VAR9 or VAR2 or VAR71 or VAR13 or VAR111 or VAR81 or VAR120 or VAR49 or VAR62 or VAR63)
begin
if ((((VAR25 == VAR65) & ~(VAR74 == VAR43)) | ((VAR25 == VAR49) & (VAR87 == VAR63) & ~VAR62) | ((VAR25 == VAR2) & (VAR9 == VAR87) & (VAR87 == VAR71) & (VAR25 == VAR111) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120)))))) begin
VAR54 = VAR25;
end else begin
VAR54 = VAR43;
end
end
always @ (VAR60 or VAR97 or VAR110)
begin
if (((VAR25 == VAR60) | ((VAR25 == VAR110) & ~(VAR97 == VAR87)))) begin
VAR116 = VAR25;
end else begin
VAR116 = VAR43;
end
end
always @ (VAR75 or VAR119)
begin
if ((~(VAR25 == VAR75) & (VAR25 == VAR119))) begin
VAR27 = VAR25;
end else begin
VAR27 = VAR43;
end
end
always @ (VAR97 or VAR110)
begin
if (((VAR25 == VAR110) & ~(VAR97 == VAR87))) begin
VAR26 = VAR25;
end else begin
VAR26 = VAR43;
end
end
always @ (VAR99)
begin
if (VAR99) begin
VAR2 = VAR25;
end else begin
VAR2 = VAR43;
end
end
always @ (VAR51)
begin
if (VAR51) begin
VAR119 = VAR25;
end else begin
VAR119 = VAR43;
end
end
always @ (VAR73)
begin
if (VAR73) begin
VAR65 = VAR25;
end else begin
VAR65 = VAR43;
end
end
always @ (VAR61)
begin
if (VAR61) begin
VAR114 = VAR25;
end else begin
VAR114 = VAR43;
end
end
always @ (VAR115)
begin
if (VAR115) begin
VAR110 = VAR25;
end else begin
VAR110 = VAR43;
end
end
always @ (VAR20)
begin
if (VAR20) begin
VAR49 = VAR25;
end else begin
VAR49 = VAR43;
end
end
always @ (VAR72)
begin
if (VAR72) begin
VAR93 = VAR25;
end else begin
VAR93 = VAR43;
end
end
always @ (VAR39 or VAR52 or VAR86 or VAR2 or VAR120)
begin
if (((VAR25 == VAR2) & (VAR86 == VAR87) & (VAR25 == VAR120))) begin
VAR38 = VAR52;
end else begin
VAR38 = VAR39;
end
end
always @ (VAR14 or VAR109 or VAR86 or VAR2 or VAR120)
begin
if (((VAR25 == VAR2) & (VAR86 == VAR87) & (VAR25 == VAR120))) begin
VAR32 = VAR109;
end else begin
VAR32 = VAR14;
end
end
always @ (VAR78 or VAR69 or VAR86 or VAR2 or VAR120)
begin
if (((VAR25 == VAR2) & (VAR86 == VAR87) & (VAR25 == VAR120))) begin
VAR101 = VAR69;
end else begin
VAR101 = VAR78;
end
end
always @ (VAR86 or VAR2 or VAR13 or VAR111 or VAR81 or VAR120)
begin
if (((VAR25 == VAR2) & (VAR86 == VAR87) & (VAR25 == VAR120) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))))) begin
VAR112 = VAR25;
end else begin
VAR112 = VAR43;
end
end
always @ (VAR86 or VAR2 or VAR13 or VAR111 or VAR81 or VAR120)
begin
if (((VAR25 == VAR2) & (VAR86 == VAR87) & (VAR25 == VAR120) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))))) begin
VAR113 = VAR25;
end else begin
VAR113 = VAR43;
end
end
always @ (VAR86 or VAR2 or VAR13 or VAR111 or VAR81 or VAR120)
begin
if (((VAR25 == VAR2) & (VAR86 == VAR87) & (VAR25 == VAR120) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))))) begin
VAR66 = VAR25;
end else begin
VAR66 = VAR43;
end
end
always @ (VAR90 or VAR71 or VAR38 or VAR79 or VAR29)
begin
if (VAR29) begin
if (~(VAR87 == VAR71)) begin
VAR46 = VAR38;
end else if ((VAR87 == VAR71)) begin
VAR46 = VAR90;
end else begin
VAR46 = VAR79;
end
end else begin
VAR46 = VAR79;
end
end
always @ (VAR70 or VAR74 or VAR107 or VAR97 or VAR9 or VAR13 or VAR111 or VAR81 or VAR120 or VAR62 or VAR63 or VAR36)
begin
case (VAR70)
VAR96 :
begin
if (~VAR107) begin
VAR4 = VAR108;
end else begin
VAR4 = VAR96;
end
end
VAR108 :
begin
if ((~(VAR74 == VAR43) & (VAR87 == VAR36))) begin
VAR4 = VAR108;
end else if ((~(VAR74 == VAR43) & ~(VAR87 == VAR36))) begin
VAR4 = VAR17;
end else begin
VAR4 = VAR108;
end
end
VAR17 :
begin
VAR4 = VAR35;
end
VAR35 :
begin
if (~(VAR97 == VAR87)) begin
VAR4 = VAR96;
end else begin
VAR4 = VAR23;
end
end
VAR23 :
begin
if (~((VAR25 == VAR111) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))) & ~(VAR9 == VAR87))) begin
VAR4 = VAR23;
end else if (((VAR25 == VAR111) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))) & ~(VAR9 == VAR87))) begin
VAR4 = VAR40;
end else begin
VAR4 = VAR23;
end
end
VAR40 :
begin
if (((VAR87 == VAR63) & ~VAR62)) begin
VAR4 = VAR40;
end else if ((~VAR62 & ~(VAR87 == VAR63))) begin
VAR4 = VAR3;
end else begin
VAR4 = VAR40;
end
end
VAR3 :
begin
VAR4 = VAR35;
end
default :
begin
VAR4 = 'VAR22;
end
endcase
end
assign VAR6 = 'VAR22;
assign VAR1 = 'VAR22;
assign VAR79 = 'VAR22;
always @ (VAR70)
begin
VAR115 = (VAR55 == VAR70[VAR30]);
end
always @ (VAR70)
begin
VAR99 = (VAR55 == VAR70[VAR18]);
end
always @ (VAR9 or VAR71)
begin
VAR7 = ((VAR9 == VAR87) & (VAR87 == VAR71));
end
always @ (VAR74 or VAR9 or VAR71)
begin
VAR13 = ((VAR74 == VAR43) & (VAR9 == VAR87) & (VAR87 == VAR71));
end
always @ (VAR47 or VAR100 or VAR84 or VAR86)
begin
VAR81 = (((VAR47 == VAR43) & (VAR86 == VAR87)) | ((VAR86 == VAR87) & (VAR100 == VAR43)) | ((VAR86 == VAR87) & (VAR84 == VAR43)));
end
always @ (VAR2 or VAR13 or VAR111 or VAR81 or VAR120)
begin
VAR103 = ((VAR25 == VAR2) & (VAR25 == VAR111) & ~((VAR13 & (VAR25 == VAR111)) | (VAR81 & (VAR25 == VAR120))));
end
always @ (VAR70)
begin
VAR20 = (VAR55 == VAR70[VAR50]);
end
always @ (VAR74 or VAR63)
begin
VAR62 = ((VAR74 == VAR43) & (VAR87 == VAR63));
end
always @ (VAR70)
begin
VAR72 = (VAR55 == VAR70[VAR58]);
end
always @ (VAR70)
begin
VAR61 = (VAR55 == VAR70[VAR42]);
end
always @ (VAR9 or VAR71)
begin
VAR31 = ((VAR9 == VAR87) & ~(VAR87 == VAR71));
end
always @ (VAR9 or VAR2 or VAR111)
begin
VAR29 = ((VAR25 == VAR2) & (VAR9 == VAR87) & (VAR25 == VAR111));
end
always @ (VAR70)
begin
VAR51 = (VAR70[VAR19] == VAR55);
end
always @ (VAR75 or VAR60)
begin
VAR107 = ((VAR75 == VAR43) | (VAR60 == VAR25));
end
always @ (VAR70)
begin
VAR73 = (VAR55 == VAR70[VAR82]);
end
assign VAR45 = (VAR32 | VAR91);
assign VAR71 = (VAR76 | VAR101);
assign VAR97 = (VAR33 == VAR98? 1'b1: 1'b0);
assign VAR9 = (VAR105 == VAR68? 1'b1: 1'b0);
assign VAR59 = (VAR33 + VAR5);
assign VAR10 = VAR94;
assign VAR83 = VAR104;
assign VAR85 = VAR8;
assign VAR102 = (VAR105 + VAR5);
assign VAR91 = (VAR76 ^ VAR55);
assign VAR118 = VAR46[7:0];
assign VAR36 = VAR34;
endmodule | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/axi_crossbar_v2_1/da4c95fc/hdl/verilog/axi_crossbar_v2_1_addr_arbiter_sasd.v | 13,345 | module MODULE1 #
(
parameter VAR45 = "none",
parameter integer VAR9 = 1,
parameter integer VAR16 = 1,
parameter integer VAR37 = 1,
parameter VAR77 = 0,
parameter [VAR9*32-1:0] VAR41 = {VAR9{32'h00000000}}
)
(
input wire VAR2,
input wire VAR3,
input wire [VAR9*VAR37-1:0] VAR78,
input wire [VAR9*VAR37-1:0] VAR79,
input wire [VAR9-1:0] VAR36,
output wire [VAR9-1:0] VAR74,
input wire [VAR9-1:0] VAR28,
output wire [VAR9-1:0] VAR14,
output wire [VAR37-1:0] VAR75,
output wire [VAR16-1:0] VAR58,
output wire [VAR9-1:0] VAR59,
output wire VAR69,
output wire VAR57,
output wire VAR48,
input wire VAR76,
output wire VAR15,
input wire VAR73
);
function [VAR9-1:0] VAR6
(
input integer VAR43
);
reg [VAR9-1:0] VAR49;
integer VAR33;
begin
VAR49 = 0;
for (VAR33=0; VAR33 < VAR9; VAR33=VAR33+1) begin
VAR49[VAR33] = (VAR41[VAR33*32+:32] != 0);
end
VAR6 = VAR49;
end
endfunction
function [3:0] VAR30
(
input [15:0] VAR68
);
begin
VAR30[0] = |(VAR68 & 16'b1010101010101010);
VAR30[1] = |(VAR68 & 16'b1100110011001100);
VAR30[2] = |(VAR68 & 16'b1111000011110000);
VAR30[3] = |(VAR68 & 16'b1111111100000000);
end
endfunction
localparam [VAR9-1:0] VAR62 = VAR6(0);
reg VAR52;
reg [VAR9-1:0] VAR44;
reg [VAR9-1:0] VAR21;
reg [VAR9-1:0] VAR22;
wire [15:0] VAR11;
wire VAR54;
wire [VAR9-1:0] VAR72;
reg VAR1;
reg [VAR16-1:0] VAR64;
reg [VAR9-1:0] VAR20;
reg [VAR9-1:0] VAR50;
reg VAR24;
reg VAR40;
reg [VAR9-1:0] VAR19;
reg [VAR16-1:0] VAR38;
reg [4:0] VAR8;
reg [15:0] VAR70;
reg [VAR16-1:0] VAR53;
reg VAR42;
wire [VAR9-1:0] VAR46;
reg [15:0] VAR63;
reg [VAR16-1:0] VAR5;
reg [VAR9*VAR9-1:0] VAR17;
reg [VAR9*VAR9-1:0] VAR71;
reg VAR26;
wire [VAR9-1:0] VAR55;
wire [VAR16-1:0] VAR13;
integer VAR33;
wire [VAR37-1:0] VAR67;
reg [VAR37-1:0] VAR51;
wire [VAR9*VAR37-1:0] VAR32;
genvar VAR29;
always @(posedge VAR2) begin
if (VAR3) begin
VAR21 <= 0;
VAR22 <= 0;
end else if (|VAR44) begin
VAR21 <= 0;
VAR22 <= 0;
end else begin
VAR22 <= VAR28 & ~VAR21;
VAR21 <= VAR36 & ~VAR22 & (~VAR28 | VAR21);
end
end
assign VAR11 = VAR36 | VAR28;
assign VAR48 = VAR52 & ~VAR1;
assign VAR15 = VAR52 & VAR1;
assign VAR74 = VAR44 & {VAR9{~VAR1}};
assign VAR14 = VAR44 & {VAR9{VAR1}};
assign VAR58 = VAR77 ? VAR64 : 0;
assign VAR59 = VAR20;
assign VAR69 = VAR1;
assign VAR72 = VAR28 & ~VAR21;
assign VAR75 = VAR51;
assign VAR54 = VAR1 ? VAR73 : VAR76;
generate
for (VAR29=0; VAR29<VAR9; VAR29=VAR29+1) begin : VAR80
assign VAR32[VAR37*VAR29 +: VAR37] = VAR72[VAR29] ? VAR79[VAR37*VAR29 +: VAR37] : VAR78[VAR37*VAR29 +: VAR37];
end
if (VAR9>1) begin : VAR56
assign VAR57 = VAR24;
assign VAR55 = VAR42 ? VAR70 : VAR63;
assign VAR13 = VAR42 ? VAR53 : VAR5;
always @(posedge VAR2) begin
if (VAR3) begin
VAR52 <= 0;
VAR44 <= 0;
VAR20 <= 0;
VAR64 <= 0;
VAR24 <= 1'b0;
VAR50 <= {1'b1, {VAR9-1{1'b0}}};
VAR1 <= 1'b0;
end else begin
VAR44 <= 0;
if (VAR52) begin
if (VAR54) begin VAR52 <= 1'b0;
VAR20 <= 0;
VAR24 <= 1'b0;
end
end else if (VAR24) begin
VAR52 <= 1'b1;
VAR44 <= VAR20; end else begin
if (VAR42 | VAR26) begin
VAR20 <= VAR55;
VAR64 <= VAR13;
VAR24 <= 1'b1;
VAR1 <= |(VAR72 & VAR55);
if (~VAR42) begin
VAR50 <= VAR63;
end
end
end
end
end
always @ * begin : VAR47
integer VAR35;
VAR40 = 1'b0;
VAR19 = 0;
VAR38 = 0;
VAR8 = 0;
for (VAR35=0; VAR35 < VAR9; VAR35=VAR35+1) begin
if (VAR62[VAR35] & ({1'b0, VAR41[VAR35*32+:4]} > VAR8)) begin
if (VAR11[VAR35]) begin
VAR8[0+:4] = VAR41[VAR35*32+:4];
VAR40 = 1'b1;
VAR19 = 1'b1 << VAR35;
VAR38 = VAR35;
end
end
end
VAR42 = VAR40;
VAR70 = VAR19;
VAR53 = VAR38;
end
assign VAR46 = ~VAR62 & VAR11;
always @ * begin : VAR60
integer VAR12, VAR7, VAR4;
VAR63 = 0;
for (VAR12=0;VAR12<VAR9;VAR12=VAR12+1) begin
VAR4 = (VAR12>0) ? (VAR12-1) : (VAR9-1);
VAR17[VAR12*VAR9] = VAR50[VAR4];
VAR71[VAR12*VAR9] = ~VAR46[VAR4];
for (VAR7=1;VAR7<VAR9;VAR7=VAR7+1) begin
VAR4 = (VAR12-VAR7 > 0) ? (VAR12-VAR7-1) : (VAR9+VAR12-VAR7-1);
VAR17[VAR12*VAR9+VAR7] = VAR17[VAR12*VAR9+VAR7-1] | (VAR50[VAR4] & VAR71[VAR12*VAR9+VAR7-1]);
if (VAR7 < VAR9-1) begin
VAR71[VAR12*VAR9+VAR7] = VAR71[VAR12*VAR9+VAR7-1] & ~VAR46[VAR4];
end
end
VAR63[VAR12] = VAR46[VAR12] & VAR17[(VAR12+1)*VAR9-1];
end
VAR5 = VAR30(VAR63);
VAR26 = |(VAR63);
end
VAR23 #
(
.VAR45 ("VAR31"),
.VAR61 (VAR9),
.VAR34 (VAR16),
.VAR18 (VAR37)
) VAR39
(
.VAR27 (VAR13),
.VAR25 (VAR32),
.VAR66 (VAR67),
.VAR65 (1'b1)
);
always @(posedge VAR2) begin
if (VAR3) begin
VAR51 <= 0;
end else if (~VAR24) begin
VAR51 <= VAR67;
end
end
end else begin : VAR10
assign VAR57 = VAR20;
always @ (posedge VAR2) begin
if (VAR3) begin
VAR52 <= 1'b0;
VAR44 <= 1'b0;
VAR64 <= 0;
VAR20 <= 1'b0;
VAR1 <= 1'b0;
end else begin
VAR44 <= 1'b0;
if (VAR52) begin
if (VAR54) begin
VAR52 <= 1'b0;
VAR20 <= 1'b0;
end
end else if (VAR20) begin
VAR52 <= 1'b1;
VAR44[0] <= 1'b1; end else if (VAR11[0]) begin
VAR20 <= 1'b1;
VAR1 <= VAR72[0];
end
end
end
always @ (posedge VAR2) begin
if (VAR3) begin
VAR51 <= 0;
end else if (~VAR20) begin
VAR51 <= VAR32;
end
end
end endgenerate
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxtp/sky130_fd_sc_hs__sdfxtp.pp.symbol.v | 1,376 | module MODULE1 (
input VAR5 ,
output VAR3 ,
input VAR4 ,
input VAR6 ,
input VAR7 ,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/chip_top.v | 6,160 | module MODULE1 (
input wire VAR12,
input wire VAR9
,input wire VAR11
,output wire VAR7
,input wire [VAR2-1:0] VAR8
,output wire [VAR1-1:0] VAR6
,inout wire [VAR10-1:0] VAR4
);
wire clk ;
wire VAR14 ;
wire VAR13 ;
VAR5 VAR5 (
.VAR12 (VAR12 ),
.VAR9 (VAR9 ),
.clk (clk ),
.VAR14 (VAR14 ),
.VAR13 (VAR13 )
);
VAR3 VAR3 (
.clk (clk ),
.VAR14 (VAR14 ),
.reset (VAR13 )
, .VAR11 (VAR11 )
, .VAR7 (VAR7 )
, .VAR8 (VAR8 )
, .VAR6 (VAR6 )
, .VAR4 (VAR4 )
);
endmodule | apache-2.0 |
anderson1008/PAB-NOC | RTL/loadTrack.v | 1,486 | module MODULE1 (reset, clk, valid, VAR7, VAR10, VAR15, VAR4, VAR6);
input clk, reset,VAR10;
input [3:0] valid;
input [3:0] VAR7;
input [4*VAR12-1:0] VAR15; output reg [VAR3-1:0] VAR4;
output reg [4*VAR11-1:0] VAR6;
wire [VAR12-1:0] VAR14 [3:0];
genvar VAR5;
generate
for (VAR5=0; VAR5<4; VAR5= VAR5+1) begin : VAR9
assign VAR14[VAR5] = VAR15[VAR5*VAR12+:VAR12];
end
endgenerate
reg [VAR11-1:0] VAR8 [3:0];
reg [2:0] VAR1;
always @ (posedge clk or negedge reset) begin
if (~reset) begin
VAR6 <= 0;
VAR4 <= 0;
for (VAR1=0;VAR1<4;VAR1=VAR1+1)
VAR8[VAR1] <= 0;
end
else begin
if (~VAR10) begin
VAR6 <= 0;
VAR4 <= 0;
for (VAR1=0;VAR1<4;VAR1=VAR1+1) begin
if ((valid[VAR1] && (VAR14[VAR1] == VAR13))| (VAR7[VAR1] && (VAR14[VAR1] == VAR2)))
VAR8[VAR1] <= VAR8[VAR1] + 1;
end
end
else begin
VAR4 <= VAR8[3]+VAR8[2]+VAR8[1]+VAR8[0];
VAR6 <= {VAR8[3],VAR8[2],VAR8[1],VAR8[0]};
for (VAR1=0;VAR1<4;VAR1=VAR1+1)
VAR8[VAR1] <= 0;
end
end
end
endmodule | gpl-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/dbg_interface/dbg_sync_clk1_clk2.v | 4,979 | module MODULE1 (VAR4, VAR1, VAR2, VAR6, VAR14, VAR11);
parameter VAR10 = 1;
input VAR4;
input VAR1;
input VAR2;
input VAR6;
input VAR14;
output VAR11;
reg VAR13;
reg VAR7;
reg VAR5;
reg VAR8;
reg VAR3;
reg VAR9;
reg VAR11;
wire VAR12;
assign VAR12 = VAR14 | VAR13 & ~VAR9;
always @ (posedge VAR1 or posedge VAR6)
begin
if(VAR6)
VAR13 <=#VAR10 1'b0;
end
else
VAR13 <=#VAR10 VAR12;
end
always @ (posedge VAR1 or posedge VAR6)
begin
if(VAR6)
VAR7 <=#VAR10 1'b0;
end
else
VAR7 <=#VAR10 VAR13;
end
always @ (posedge VAR4 or posedge VAR2)
begin
if(VAR2)
VAR5 <=#VAR10 1'b0;
end
else
VAR5 <=#VAR10 VAR7;
end
always @ (posedge VAR4 or posedge VAR2)
begin
if(VAR2)
VAR8 <=#VAR10 1'b0;
end
else
VAR8 <=#VAR10 VAR5;
end
always @ (posedge VAR1 or posedge VAR6)
begin
if(VAR6)
VAR3 <=#VAR10 1'b0;
end
else
VAR3 <=#VAR10 VAR8;
end
always @ (posedge VAR1 or posedge VAR6)
begin
if(VAR6)
VAR9 <=#VAR10 1'b0;
end
else
VAR9 <=#VAR10 VAR3;
end
always @ (posedge VAR4 or posedge VAR2)
begin
if(VAR2)
VAR11 <=#VAR10 1'b0;
end
else
VAR11 <=#VAR10 VAR8;
end
endmodule | apache-2.0 |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/cpu/k580wm80a.v | 11,211 | module MODULE1(
input clk,
input VAR26,
input reset,
input VAR37,
input [7:0] VAR5,
output reg [15:0] addr,
output reg sync,
output rd,
output reg wr,
output VAR17,
output reg [7:0] VAR83);
reg VAR13,VAR70,VAR21,VAR74,VAR43,VAR6,VAR31,VAR56,VAR78,VAR2,VAR64,VAR58,VAR76,VAR3,VAR45,VAR29,VAR55,VAR12;
reg[2:0] state;
wire VAR68 = VAR70|VAR21|VAR74|VAR43|VAR6|VAR31|VAR56|VAR78|VAR2|VAR64|VAR58|VAR76|VAR3|VAR45|VAR29|VAR55;
reg[15:0] VAR36;
reg[15:0] VAR27;
reg[7:0] VAR52,VAR22,VAR46,VAR50,VAR49,VAR75,VAR57;
reg[7:0] VAR24,VAR73,VAR25;
reg[9:0] VAR72;
reg VAR41,VAR54,VAR34,VAR18,VAR79;
reg rd,VAR69;
assign rd = rd&~VAR69;
assign VAR17 = (rd&VAR69);
reg[1:0] VAR11;
reg VAR4,VAR62,VAR71;
reg VAR23,VAR81,VAR7,VAR15,VAR84,VAR28;
reg VAR66,VAR40,VAR60,VAR47,VAR20,VAR44;
reg VAR77;
always @ begin
casex (VAR25[5:3])
3'VAR65: VAR44 = VAR57[4]+VAR73[4];
3'VAR53: VAR44 = VAR57[4]-VAR73[4];
3'VAR61: VAR44 = VAR57[4]^VAR73[4];
3'b110: VAR44 = VAR57[4]|VAR73[4];
3'b111: VAR44 = VAR57[4]-VAR73[4];
endcase
end
always @(*) begin
case(VAR5[5:3])
3'h0: VAR77 = ~VAR54;
3'h1: VAR77 = VAR54;
3'h2: VAR77 = ~VAR79;
3'h3: VAR77 = VAR79;
3'h4: VAR77 = ~VAR18;
3'h5: VAR77 = VAR18;
3'h6: VAR77 = ~VAR41;
3'h7: VAR77 = VAR41;
endcase
end
wire[7:0] VAR32 = {VAR41,VAR54,1'b0,VAR34,1'b0,VAR18,1'b1,VAR79};
wire[7:0] VAR10 = VAR66 ? VAR73+{{7{VAR25[0]}},1'b1} : VAR73;
wire[15:0] VAR42 = VAR66 ? {VAR24,VAR73}+{{15{VAR25[3]}},1'b1} : {VAR24,VAR73};
wire[3:0] VAR19 = VAR34!=0 || VAR57[3:0] > 4'h9 ? 4'h6 : 4'h0;
wire[3:0] VAR59 = VAR79!=0 || VAR57[7:4] > {3'b100, VAR57[3:0]>4'h9 ? 1'b0 : 1'b1} ? 4'h6 : 4'h0;
always @(posedge clk or posedge reset)
begin
if (reset) begin
{VAR13,VAR70,VAR21,VAR74,VAR43,VAR6,VAR31,VAR56,VAR78,VAR2,VAR64,VAR58,VAR76,VAR3,VAR45,VAR29,VAR55} <= 0;
state <= 0; VAR36 <= 0; {VAR41,VAR54,VAR34,VAR18,VAR79} <= 0; {addr,VAR83} <= 0;
{sync,rd,VAR4,VAR71,VAR11,VAR23,VAR81,VAR7,VAR15,VAR66,VAR69} <= 0;
wr <= 1'b0;
end else if (VAR26) begin
sync <= 0; rd <= 0; wr <= 1'b0;
if (VAR71&~(VAR13|(VAR37&VAR11[1]))) begin
sync <= 1'b1; VAR83 <= 8'b10001010; end else
if (VAR13|~VAR68) begin
case (state)
3'b000: begin
VAR71 <= 0; VAR69 <= VAR37&VAR11[1]; VAR11[1] <= VAR11[0];
VAR13 <= 1'b1;
sync <= 1'b1;
VAR83 <= {7'b1010001,VAR37&VAR11[1]}; addr <= VAR4 ? {VAR24,VAR73} : VAR36;
state <= 3'b001;
if (VAR37&VAR11[1]) VAR11 <= 2'b0;
if (VAR23) begin
VAR41 <= VAR72[8];
VAR54 <= ~|VAR72[8:1];
VAR34 <= VAR72[5]^VAR44;
VAR18 <= ~^VAR72[8:1];
VAR79 <= VAR72[9]|(VAR79&VAR20);
if (VAR25[5:3]!=3'b111) VAR57 <= VAR72[8:1];
end else
if (VAR81) begin
VAR57 <= VAR10;
end else
if (VAR7) begin
case (VAR25[5:3])
3'b000: VAR52 <= VAR10;
3'b001: VAR22 <= VAR10;
3'b010: VAR46 <= VAR10;
3'b011: VAR50 <= VAR10;
3'b100: VAR49 <= VAR10;
3'b101: VAR75 <= VAR10;
3'b111: VAR57 <= VAR10;
endcase
if (VAR66) begin
VAR41 <= VAR10[7];
VAR54 <= ~|VAR10;
VAR34 <= VAR25[0] ? VAR10[3:0]!=4'b1111 : VAR10[3:0]==0;
VAR18 <= ~^VAR10;
end
end else
if (VAR15) begin
case (VAR25[5:4])
2'b00: {VAR52,VAR22} <= VAR42;
2'b01: {VAR46,VAR50} <= VAR42;
2'b10: {VAR49,VAR75} <= VAR42;
2'b11:
if (VAR47 || !VAR25[7]) begin
VAR27 <= VAR42;
end else begin
{VAR57,VAR41,VAR54,VAR34,VAR18,VAR79} <= {VAR42[15:8],VAR42[7],VAR42[6],VAR42[4],VAR42[2],VAR42[0]};
end
endcase
end
end
3'b001: begin
rd <= 1'b1;
VAR36 <= addr+{15'b0,~VAR69};
state <= 3'b010;
end
3'b010: begin
VAR25 <= VAR5;
{VAR4,VAR62,VAR23,VAR81,VAR7,VAR15,VAR84,VAR28,VAR66,VAR40,VAR60,VAR47,VAR12,VAR20} <= 0;
casex (VAR5)
8'VAR63: {VAR15,VAR70,VAR21} <= 3'b111;
8'VAR35: {VAR28,VAR29,VAR55} <= 3'b111;
8'VAR30: {VAR28,VAR3} <= 2'b11;
8'b00100010: {VAR70,VAR21,VAR3,VAR45} <= 4'b1111;
8'b00110010: {VAR70,VAR21,VAR3} <= 3'b111;
8'VAR87: {VAR28,VAR81,VAR58} <= 3'b111;
8'b00101010: {VAR15,VAR70,VAR21,VAR58,VAR76} <= 5'b11111;
8'b00111010: {VAR81,VAR70,VAR21,VAR58} <= 4'b1111;
8'VAR14: {VAR28,VAR15,VAR66,VAR12} <= 4'b1111;
8'VAR8: {VAR84,VAR7,VAR66,VAR12} <= {3'b111,VAR5[5:3]!=3'b110};
8'VAR86: {VAR7,VAR70} <= 2'b11;
8'b00000111: {VAR79,VAR57} <= {VAR57,VAR57[7]};
8'b00001111: {VAR57,VAR79} <= {VAR57[0],VAR57};
8'b00010111: {VAR79,VAR57} <= {VAR57,VAR79};
8'b00011111: {VAR57,VAR79} <= {VAR79,VAR57};
8'b00100111: {VAR20,VAR23,VAR25[5:3],VAR73} <= {5'b11000,VAR59,VAR19};
8'b00101111: VAR57 <= ~VAR57;
8'b00110111: VAR79 <= 1'b1;
8'b00111111: VAR79 <= ~VAR79;
end
8'VAR9: if (VAR5[5:0]==6'b110110) VAR71 <= 1'b1; else {VAR84,VAR7,VAR12} <= {2'b11,~(VAR5[5:3]==3'b110||VAR5[2:0]==3'b110)};
8'VAR38: {VAR84,VAR23} <= 2'b11;
8'VAR67: {VAR4,VAR56,VAR78} <= {3{VAR77}};
8'VAR33: {VAR15,VAR56,VAR78} <= 3'b111;
8'VAR51: {VAR4,VAR56,VAR78} <= 3'b111;
8'b11101001: {VAR28,VAR4,VAR12} <= 3'b111;
8'b11111001: {VAR28,VAR15,VAR12,VAR47} <= 4'b1111;
8'VAR85: {VAR4,VAR70,VAR21} <= {VAR77,2'b11};
8'VAR16: {VAR4,VAR70,VAR21} <= 3'b111;
8'b11010011: {VAR70,VAR31} <= 2'b11;
8'b11011011: {VAR70,VAR6} <= 2'b11;
8'b11100011: {VAR15,VAR56,VAR78,VAR2,VAR64,VAR40} <= 6'b111111;
8'b11101011: {VAR28,VAR15,VAR60} <= 3'b111;
8'VAR1: VAR11 <= VAR5[3] ? 2'b1 : 2'b0;
8'VAR80: {VAR4,VAR70,VAR21,VAR12,VAR2,VAR64,VAR62} <= {VAR77,3'b111,{3{VAR77}}};
8'VAR82: {VAR28,VAR12,VAR2,VAR64} <= 4'b1111;
8'VAR48: {VAR4,VAR70,VAR21,VAR12,VAR2,VAR64,VAR62} <= 7'b1111111;
8'VAR39: {VAR23,VAR70} <= 2'b11;
8'VAR88: {VAR4,VAR12,VAR2,VAR64,VAR62,VAR24,VAR73} <= {5'b11111,10'b0,VAR5[5:3],3'b0};
endcase
state <= 3'b011;
end
3'b011: begin
if (VAR28) begin
case (VAR25[5:4])
2'b00: {VAR24,VAR73} <= {VAR52,VAR22};
2'b01: {VAR24,VAR73} <= {VAR46,VAR50};
2'b10: {VAR24,VAR73} <= VAR60 ? {VAR46,VAR50} : {VAR49,VAR75};
2'b11: {VAR24,VAR73} <= VAR47 ? {VAR49,VAR75} : VAR25[7] ? {VAR57,VAR32} : VAR27;
endcase
if (VAR60) {VAR46,VAR50} <= {VAR49,VAR75};
end else
if (~(VAR4|VAR20)) begin
case (VAR66?VAR25[5:3]:VAR25[2:0])
3'b000: VAR73 <= VAR52;
3'b001: VAR73 <= VAR22;
3'b010: VAR73 <= VAR46;
3'b011: VAR73 <= VAR50;
3'b100: VAR73 <= VAR49;
3'b101: VAR73 <= VAR75;
3'b110: VAR74 <= VAR84;
3'b111: VAR73 <= VAR57;
endcase
VAR43 <= VAR7 && VAR25[5:3]==3'b110;
end
state <= VAR12 ? 3'b100 : 0;
VAR13 <= VAR12;
end
3'b100: begin
if (VAR2) VAR27 <= VAR27-16'b1;
state <= 0;
VAR13 <= 0;
end
endcase
end else
if (VAR70 || VAR21) begin
case (state)
3'b000: begin
sync <= 1'b1;
VAR83 <= {7'b1000001,VAR69}; addr <= VAR36;
state <= 3'b001;
end
3'b001: begin
rd <= 1'b1;
VAR36 <= addr+{15'b0,~VAR69};
state <= 3'b010;
end
3'b010: begin
if (VAR70) begin
VAR73 <= VAR5;
VAR70 <= 0;
end else begin
VAR24 <= VAR5;
VAR21 <= 0;
end
state <= 3'b000;
end
endcase
end else
if (VAR74) begin
case (state)
3'b000: begin
sync <= 1'b1;
VAR83 <= {7'b1000001,VAR69}; addr <= {VAR49,VAR75};
state <= 3'b001;
end
3'b001: begin
rd <= 1'b1;
state <= 3'b010;
end
3'b010: begin
VAR73 <= VAR5;
VAR74 <= 0;
state <= 3'b000;
end
endcase
end else
if (VAR43) begin
case (state)
3'b000: begin
sync <= 1'b1;
VAR83 <= {7'b0000000,VAR69}; addr <= {VAR49,VAR75};
state <= 3'b001;
end
3'b001: begin
VAR83 <= VAR10;
wr <= 1'b1;
state <= 3'b010;
end
3'b010: begin
VAR43 <= 0;
state <= 3'b000;
end
endcase
end else
if (VAR6) begin
case (state)
3'b000: begin
sync <= 1'b1;
VAR83 <= {7'b0100001,VAR69}; addr <= {VAR73,VAR73};
state <= 3'b001;
end
3'b001: begin
rd <= 1'b1;
state <= 3'b010;
end
3'b010: begin
VAR57 <= VAR5;
VAR6 <= 0;
state <= 3'b000;
end
endcase
end else
if (VAR31) begin
case (state)
3'b000: begin
sync <= 1'b1;
VAR83 <= {7'b0001000,VAR69}; addr <= {VAR73,VAR73};
state <= 3'b001;
end
3'b001: begin
VAR83 <= VAR57;
wr <= 1'b1;
state <= 3'b010;
end
3'b010: begin
VAR31 <= 0;
state <= 3'b000;
end
endcase
end else
if (VAR56 || VAR78) begin
case (state)
3'b000: begin
sync <= 1'b1;
VAR83 <= {7'b1000011,VAR69}; addr <= VAR27;
state <= 3'b001;
end
3'b001: begin
rd <= 1'b1;
if (VAR56 || !VAR40) VAR27 <= VAR27+16'b1;
state <= 3'b010;
end
3'b010: begin
if (VAR56) begin
VAR73 <= VAR5;
VAR56 <= 0;
end else begin
VAR24 <= VAR5;
VAR78 <= 0;
end
state <= 3'b000;
end
endcase
end else
if (VAR2 || VAR64) begin
case (state)
3'b000: begin
sync <= 1'b1;
VAR83 <= {7'b0000010,VAR69}; addr <= VAR27;
state <= 3'b001;
end
3'b001: begin
if (VAR2) begin
VAR27 <= VAR27-16'b1;
VAR83 <= VAR40 ? VAR49 : VAR62 ? VAR36[15:8] : VAR24;
end else begin
VAR83 <= VAR40 ? VAR75 : VAR62 ? VAR36[7:0] : VAR73;
end
wr <= 1'b1;
state <= 3'b010;
end
3'b010: begin
if (VAR2) begin
VAR2 <= 0;
end else begin
VAR64 <= 0;
end
state <= 3'b000;
end
endcase
end else
if (VAR58 || VAR76) begin
case (state)
3'b000: begin
sync <= 1'b1;
VAR83 <= {7'b1000001,VAR69}; addr <= VAR58 ? {VAR24,VAR73} : addr+16'b1;
state <= 3'b001;
end
3'b001: begin
rd <= 1'b1;
state <= 3'b010;
end
3'b010: begin
if (VAR58) begin
VAR73 <= VAR5;
VAR58 <= 0;
end else begin
VAR24 <= VAR5;
VAR76 <= 0;
end
state <= 3'b000;
end
endcase
end else
if (VAR3 || VAR45) begin
case (state)
3'b000: begin
sync <= 1'b1;
VAR83 <= {7'b0000000,VAR69}; addr <= VAR3 ? {VAR24,VAR73} : addr+16'b1;
state <= 3'b001;
end
3'b001: begin
if (VAR3) begin
VAR83 <= VAR45 ? VAR75 : VAR57;
end else begin
VAR83 <= VAR49;
end
wr <= 1'b1;
state <= 3'b010;
end
3'b010: begin
if (VAR3) begin
VAR3 <= 0;
end else begin
VAR45 <= 0;
end
state <= 3'b000;
end
endcase
end else
if (VAR29 || VAR55) begin
case (state)
3'b000: begin
sync <= 1'b1;
VAR83 <= {7'b0000001,VAR69}; state <= 3'b001;
end
3'b001: begin
state <= 3'b010;
end
3'b010: begin
if (VAR29) begin
VAR29 <= 0;
end else begin
{VAR79,VAR49,VAR75} <= {1'b0,VAR49,VAR75}+{1'b0,VAR24,VAR73};
VAR55 <= 0;
end
state <= 3'b000;
end
endcase
end
end
end
endmodule | gpl-3.0 |
alexforencich/verilog-ethernet | example/HXT100G/fpga/rtl/i2c_master.v | 29,804 | module MODULE1 (
input wire clk,
input wire rst,
input wire [6:0] VAR97,
input wire VAR51,
input wire VAR20,
input wire VAR38,
input wire VAR88,
input wire VAR98,
input wire VAR81,
output wire VAR113,
input wire [7:0] VAR28,
input wire VAR62,
output wire VAR33,
input wire VAR45,
output wire [7:0] VAR8,
output wire VAR12,
input wire VAR49,
output wire VAR64,
input wire VAR44,
output wire VAR91,
output wire VAR59,
input wire VAR83,
output wire VAR75,
output wire VAR76,
output wire VAR99,
output wire VAR11,
output wire VAR115,
output wire VAR6,
input wire [15:0] VAR39,
input wire VAR5
);
localparam [4:0]
VAR96 = 4'd0,
VAR74 = 4'd1,
VAR114 = 4'd2,
VAR118 = 4'd3,
VAR60 = 4'd4,
VAR4 = 4'd5,
VAR13 = 4'd6,
VAR1 = 4'd7,
VAR40 = 4'd8,
VAR43 = 4'd9,
VAR47 = 4'd10,
VAR24 = 4'd11;
reg [4:0] VAR111 = VAR96, VAR9;
localparam [4:0]
VAR19 = 5'd0,
VAR108 = 5'd1,
VAR34 = 5'd2,
VAR116 = 5'd3,
VAR100 = 5'd4,
VAR10 = 5'd5,
VAR110 = 5'd6,
VAR112 = 5'd7,
VAR52 = 5'd8,
VAR103 = 5'd9,
VAR21 = 5'd10,
VAR95 = 5'd11,
VAR2 = 5'd12,
VAR22 = 5'd13,
VAR7 = 5'd14,
VAR15 = 5'd15;
reg [4:0] VAR27 = VAR96, VAR55;
reg VAR16;
reg VAR117;
reg VAR48;
reg VAR61;
reg VAR46;
reg VAR66;
reg VAR93 = 1'b0, VAR104;
reg [6:0] VAR53 = 7'd0, VAR35;
reg [7:0] VAR77 = 8'd0, VAR30;
reg VAR72 = 1'b0, VAR36;
reg VAR25 = 1'b0, VAR50;
reg VAR70 = 1'b0, VAR54;
reg VAR68 = 1'b0, VAR31;
reg [16:0] VAR78 = 16'd0, VAR3;
reg VAR86 = 1'b0, VAR56;
reg VAR67 = 1'b0, VAR57;
reg [3:0] VAR101 = 4'd0, VAR90;
reg VAR69 = 1'b0, VAR26;
reg VAR41 = 1'b0, VAR84;
reg [7:0] VAR17 = 8'd0, VAR23;
reg VAR29 = 1'b0, VAR79;
reg VAR109 = 1'b0, VAR94;
reg VAR92 = 1'b1;
reg VAR63 = 1'b1;
reg VAR71 = 1'b1, VAR37;
reg VAR107 = 1'b1, VAR80;
reg VAR32 = 1'b1;
reg VAR18 = 1'b1;
reg VAR82 = 1'b0;
reg VAR106 = 1'b0;
reg VAR14 = 1'b0, VAR58;
reg VAR42 = 1'b0, VAR85;
assign VAR113 = VAR69;
assign VAR33 = VAR41;
assign VAR8 = VAR17;
assign VAR12 = VAR29;
assign VAR64 = VAR109;
assign VAR91 = VAR71;
assign VAR59 = VAR71;
assign VAR75 = VAR107;
assign VAR76 = VAR107;
assign VAR99 = VAR82;
assign VAR115 = VAR106;
assign VAR11 = VAR14;
assign VAR6 = VAR42;
wire VAR105 = VAR92 & ~VAR32;
wire VAR65 = ~VAR92 & VAR32;
wire VAR89 = VAR63 & ~VAR18;
wire VAR102 = ~VAR63 & VAR18;
wire VAR87 = VAR102 & VAR92;
wire VAR73 = VAR89 & VAR92;
always @* begin
VAR9 = VAR96;
VAR16 = 1'b0;
VAR117 = 1'b0;
VAR48 = 1'b0;
VAR61 = 1'b0;
VAR66 = 1'b0;
VAR46 = 1'b0;
VAR35 = VAR53;
VAR30 = VAR77;
VAR36 = VAR72;
VAR50 = VAR25;
VAR54 = VAR70;
VAR31 = VAR68;
VAR90 = VAR101;
VAR26 = 1'b0;
VAR84 = 1'b0;
VAR23 = VAR17;
VAR79 = VAR29 & ~VAR49;
VAR94 = VAR109;
VAR85 = 1'b0;
if (VAR27 != VAR19 && VAR27 != VAR108) begin
VAR9 = VAR111;
end else begin
case (VAR111)
VAR96: begin
VAR26 = 1'b1;
if (VAR113 & VAR81) begin
if (VAR20 ^ (VAR38 | VAR88)) begin
VAR35 = VAR97;
VAR50 = VAR20;
VAR54 = VAR88;
VAR31 = VAR98;
VAR26 = 1'b0;
if (VAR115) begin
VAR9 = VAR118;
end else begin
VAR16 = 1'b1;
VAR90 = 4'd8;
VAR9 = VAR4;
end
end else begin
VAR9 = VAR96;
end
end else begin
VAR9 = VAR96;
end
end
VAR74: begin
VAR26 = 1'b1;
if (VAR113 & VAR81) begin
if (VAR20 ^ (VAR38 | VAR88)) begin
VAR35 = VAR97;
VAR50 = VAR20;
VAR54 = VAR88;
VAR31 = VAR98;
VAR26 = 1'b0;
if (VAR51 || VAR97 != VAR53 || VAR20) begin
VAR16 = 1'b1;
VAR90 = 4'd8;
VAR9 = VAR4;
end else begin
VAR84 = 1'b1;
VAR9 = VAR1;
end
end else if (VAR98 && !(VAR20 || VAR38 || VAR88)) begin
VAR117 = 1'b1;
VAR9 = VAR96;
end else begin
VAR9 = VAR74;
end
end else begin
if (VAR5 & VAR113 & ~VAR81) begin
VAR117 = 1'b1;
VAR9 = VAR96;
end else begin
VAR9 = VAR74;
end
end
end
VAR114: begin
VAR26 = ~VAR12;
if (VAR113 & VAR81) begin
if (VAR20 ^ (VAR38 | VAR88)) begin
VAR35 = VAR97;
VAR50 = VAR20;
VAR54 = VAR88;
VAR31 = VAR98;
VAR26 = 1'b0;
if (VAR51 || VAR97 != VAR53 || VAR38) begin
VAR48 = 1'b1;
VAR66 = 1'b1;
VAR9 = VAR60;
end else begin
VAR48 = 1'b1;
VAR66 = 1'b0;
VAR90 = 4'd8;
VAR30 = 8'd0;
VAR9 = VAR47;
end
end else if (VAR98 && !(VAR20 || VAR38 || VAR88)) begin
VAR48 = 1'b1;
VAR66 = 1'b1;
VAR9 = VAR24;
end else begin
VAR9 = VAR114;
end
end else begin
if (VAR5 & VAR113 & ~VAR81) begin
VAR48 = 1'b1;
VAR66 = 1'b1;
VAR9 = VAR24;
end else begin
VAR9 = VAR114;
end
end
end
VAR118: begin
if (VAR115) begin
VAR9 = VAR118;
end else begin
VAR16 = 1'b1;
VAR90 = 4'd8;
VAR9 = VAR4;
end
end
VAR60: begin
VAR16 = 1'b1;
VAR90 = 4'd8;
VAR9 = VAR4;
end
VAR4: begin
VAR90 = VAR101 - 1;
if (VAR101 > 1) begin
VAR48 = 1'b1;
VAR66 = VAR53[VAR101-2];
VAR9 = VAR4;
end else if (VAR101 > 0) begin
VAR48 = 1'b1;
VAR66 = VAR25;
VAR9 = VAR4;
end else begin
VAR61 = 1'b1;
VAR9 = VAR13;
end
end
VAR13: begin
VAR85 = VAR93;
if (VAR25) begin
VAR90 = 4'd8;
VAR30 = 1'b0;
VAR9 = VAR47;
end else begin
VAR84 = 1'b1;
VAR9 = VAR1;
end
end
VAR1: begin
VAR84 = 1'b1;
if (VAR33 & VAR62) begin
VAR30 = VAR28;
VAR36 = VAR45;
VAR90 = 4'd8;
VAR84 = 1'b0;
VAR9 = VAR40;
end else begin
VAR9 = VAR1;
end
end
VAR40: begin
VAR90 = VAR101 - 1;
if (VAR101 > 0) begin
VAR48 = 1'b1;
VAR66 = VAR77[VAR101-1];
VAR9 = VAR40;
end else begin
VAR61 = 1'b1;
VAR9 = VAR43;
end
end
VAR43: begin
VAR85 = VAR93;
if (VAR70 && !VAR72) begin
VAR9 = VAR1;
end else if (VAR68) begin
VAR117 = 1'b1;
VAR9 = VAR96;
end else begin
VAR9 = VAR74;
end
end
VAR47: begin
VAR90 = VAR101 - 1;
VAR30 = {VAR77[6:0], VAR93};
if (VAR101 > 0) begin
VAR61 = 1'b1;
VAR9 = VAR47;
end else begin
VAR23 = VAR30;
VAR79 = 1'b1;
VAR94 = 1'b0;
if (VAR68) begin
VAR94 = 1'b1;
VAR48 = 1'b1;
VAR66 = 1'b1;
VAR9 = VAR24;
end else begin
VAR9 = VAR114;
end
end
end
VAR24: begin
VAR117 = 1'b1;
VAR9 = VAR96;
end
endcase
end
end
always @* begin
VAR55 = VAR19;
VAR104 = VAR93;
VAR3 = VAR78;
VAR56 = VAR86;
VAR57 = VAR67;
VAR37 = VAR71;
VAR80 = VAR107;
VAR58 = VAR14;
if (VAR46) begin
VAR80 = 1'b1;
VAR37 = 1'b1;
VAR56 = 1'b0;
VAR57 = 1'b0;
VAR3 = 1'b0;
VAR55 = VAR19;
end else if (VAR86) begin
VAR56 = VAR71 & ~VAR92;
VAR55 = VAR27;
end else if (VAR67) begin
VAR57 = VAR107 & ~VAR63;
VAR55 = VAR27;
end else if (VAR78 > 0) begin
VAR3 = VAR78 - 1;
VAR55 = VAR27;
end else begin
case (VAR27)
VAR19: begin
VAR80 = 1'b1;
VAR37 = 1'b1;
if (VAR16) begin
VAR80 = 1'b0;
VAR3 = VAR39;
VAR55 = VAR100;
end else begin
VAR55 = VAR19;
end
end
VAR108: begin
if (VAR16) begin
VAR80 = 1'b1;
VAR3 = VAR39;
VAR55 = VAR34;
end else if (VAR48) begin
VAR80 = VAR66;
VAR3 = VAR39;
VAR55 = VAR110;
end else if (VAR61) begin
VAR80 = 1'b1;
VAR3 = VAR39;
VAR55 = VAR103;
end else if (VAR117) begin
VAR80 = 1'b0;
VAR3 = VAR39;
VAR55 = VAR22;
end else begin
VAR55 = VAR108;
end
end
VAR34: begin
VAR37 = 1'b1;
VAR56 = 1'b1;
VAR3 = VAR39;
VAR55 = VAR116;
end
VAR116: begin
VAR80 = 1'b0;
VAR3 = VAR39;
VAR55 = VAR100;
end
VAR100: begin
VAR37 = 1'b0;
VAR3 = VAR39;
VAR55 = VAR10;
end
VAR10: begin
VAR58 = 1'b1;
VAR55 = VAR108;
end
VAR110: begin
VAR37 = 1'b1;
VAR56 = 1'b1;
VAR3 = VAR39 << 1;
VAR55 = VAR112;
end
VAR112: begin
VAR37 = 1'b0;
VAR3 = VAR39;
VAR55 = VAR52;
end
VAR52: begin
VAR55 = VAR108;
end
VAR103: begin
VAR37 = 1'b1;
VAR56 = 1'b1;
VAR3 = VAR39;
VAR55 = VAR21;
end
VAR21: begin
VAR104 = VAR63;
VAR3 = VAR39;
VAR55 = VAR95;
end
VAR95: begin
VAR37 = 1'b0;
VAR3 = VAR39;
VAR55 = VAR2;
end
VAR2: begin
VAR55 = VAR108;
end
VAR22: begin
VAR37 = 1'b1;
VAR56 = 1'b1;
VAR3 = VAR39;
VAR55 = VAR7;
end
VAR7: begin
VAR80 = 1'b1;
VAR3 = VAR39;
VAR55 = VAR15;
end
VAR15: begin
VAR58 = 1'b0;
VAR55 = VAR19;
end
endcase
end
end
always @(posedge clk) begin
if (rst) begin
VAR111 <= VAR96;
VAR27 <= VAR19;
VAR78 <= 16'd0;
VAR86 <= 1'b0;
VAR67 <= 1'b0;
VAR69 <= 1'b0;
VAR41 <= 1'b0;
VAR29 <= 1'b0;
VAR71 <= 1'b1;
VAR107 <= 1'b1;
VAR82 <= 1'b0;
VAR106 <= 1'b0;
VAR14 <= 1'b0;
VAR42 <= 1'b0;
end else begin
VAR111 <= VAR9;
VAR27 <= VAR55;
VAR78 <= VAR3;
VAR86 <= VAR56;
VAR67 <= VAR57;
VAR69 <= VAR26;
VAR41 <= VAR84;
VAR29 <= VAR79;
VAR71 <= VAR37;
VAR107 <= VAR80;
VAR82 <= !(VAR111 == VAR96 || VAR111 == VAR74 || VAR111 == VAR114);
if (VAR87) begin
VAR106 <= 1'b1;
end else if (VAR73) begin
VAR106 <= 1'b0;
end else begin
VAR106 <= VAR106;
end
VAR14 <= VAR58;
VAR42 <= VAR85;
end
VAR93 <= VAR104;
VAR53 <= VAR35;
VAR77 <= VAR30;
VAR72 <= VAR36;
VAR25 <= VAR50;
VAR70 <= VAR54;
VAR68 <= VAR31;
VAR101 <= VAR90;
VAR17 <= VAR23;
VAR109 <= VAR94;
VAR92 <= VAR44;
VAR63 <= VAR83;
VAR32 <= VAR92;
VAR18 <= VAR63;
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtn/sky130_fd_sc_hd__dlxtn_4.v | 2,204 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR3,
VAR7 ,
VAR8 ,
VAR1 ,
VAR2
);
output VAR6 ;
input VAR9 ;
input VAR3;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR2 ;
VAR5 VAR4 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6 ,
VAR9 ,
VAR3
);
output VAR6 ;
input VAR9 ;
input VAR3;
supply1 VAR7;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR2 ;
VAR5 VAR4 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_nrs/sky130_fd_sc_ls__udp_dff_nrs.blackbox.v | 1,347 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR5,
VAR2,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR5;
input VAR2;
input VAR3 ;
endmodule | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/FSM_Barra.v | 2,019 | module MODULE1(VAR4, reset, VAR3, VAR7,VAR6, VAR9);
input VAR4, reset, VAR3;
output VAR7;
output reg VAR6, VAR9;
reg [2:0] state;
parameter VAR8 = 0;
parameter VAR2 = 1;
parameter VAR1 = 2;
parameter VAR5 = 3;
begin
begin
begin
end
begin
begin
begin
begin | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_axi.v | 8,479 | module MODULE1 (
VAR21,
VAR7,
VAR18,
VAR35,
VAR34,
VAR23,
VAR27,
VAR6,
VAR36,
VAR5,
VAR8,
VAR3,
VAR12,
VAR14,
VAR22,
VAR32,
VAR25,
VAR24,
VAR17,
VAR19,
VAR30,
VAR13,
VAR26,
VAR20,
VAR31);
parameter VAR2 = 32'hffffffff;
parameter VAR10 = 32'h00000000;
input VAR21;
input VAR7;
input VAR18;
input [31:0] VAR35;
output VAR34;
input VAR23;
input [31:0] VAR27;
input [ 3:0] VAR6;
output VAR36;
output VAR5;
output [ 1:0] VAR8;
input VAR3;
input VAR12;
input [31:0] VAR14;
output VAR22;
output VAR32;
output [ 1:0] VAR25;
output [31:0] VAR24;
input VAR17;
output VAR19;
output VAR30;
output [13:0] VAR13;
output [31:0] VAR26;
input [31:0] VAR20;
input VAR31;
reg VAR34 = 'd0;
reg VAR36 = 'd0;
reg VAR22 = 'd0;
reg VAR5 = 'd0;
reg VAR32 = 'd0;
reg [31:0] VAR24 = 'd0;
reg VAR29 = 'd0;
reg VAR19 = 'd0;
reg VAR30 = 'd0;
reg [13:0] VAR13 = 'd0;
reg [31:0] VAR26 = 'd0;
reg VAR33 = 'd0;
reg [ 2:0] VAR4 = 'd0;
reg VAR16 = 'd0;
reg [31:0] VAR28 = 'd0;
wire VAR9;
wire VAR15;
wire [31:0] VAR11;
wire VAR1;
assign VAR8 = 2'd0;
assign VAR25 = 2'd0;
assign VAR9 = ((VAR35 >= VAR2) && (VAR35 <= VAR10)) ?
(VAR18 & VAR23 & ~VAR29) : 1'b0;
assign VAR15 = ((VAR14 >= VAR2) && (VAR14 <= VAR10)) ?
(VAR12 & ~VAR29) : 1'b0;
always @(negedge VAR21 or posedge VAR7) begin
if (VAR21 == 1'b0) begin
VAR34 <= 'd0;
VAR36 <= 'd0;
VAR22 <= 'd0;
VAR5 <= 'd0;
VAR32 <= 'd0;
VAR24 <= 'd0;
end else begin
if ((VAR34 == 1'b1) && (VAR18 == 1'b1)) begin
VAR34 <= 1'b0;
end else if (VAR9 == 1'b1) begin
VAR34 <= 1'b1;
end
if ((VAR36 == 1'b1) && (VAR23 == 1'b1)) begin
VAR36 <= 1'b0;
end else if (VAR9 == 1'b1) begin
VAR36 <= 1'b1;
end
if ((VAR22 == 1'b1) && (VAR12 == 1'b1)) begin
VAR22 <= 1'b0;
end else if (VAR15 == 1'b1) begin
VAR22 <= 1'b1;
end
if ((VAR3 == 1'b1) && (VAR5 == 1'b1)) begin
VAR5 <= 1'b0;
end else if ((VAR29 == 1'b1) && (VAR1 == 1'b1) && (VAR30 == 1'b1)) begin
VAR5 <= 1'b1;
end
if ((VAR17 == 1'b1) && (VAR32 == 1'b1)) begin
VAR32 <= 1'b0;
VAR24 <= 32'd0;
end else if ((VAR29 == 1'b1) && (VAR1 == 1'b1) && (VAR30 == 1'b0)) begin
VAR32 <= 1'b1;
VAR24 <= VAR11;
end
end
end
always @(negedge VAR21 or posedge VAR7) begin
if (VAR21 == 1'b0) begin
VAR29 <= 'd0;
VAR19 <= 'd0;
VAR30 <= 'd0;
VAR13 <= 'd0;
VAR26 <= 'd0;
end else begin
if (VAR29 == 1'b1) begin
if (VAR1 == 1'b1) begin
VAR29 <= 1'b0;
end
VAR19 <= 1'b0;
end else begin
VAR29 <= VAR9 | VAR15;
VAR19 <= VAR9 | VAR15;
end
if (VAR29 == 1'b0) begin
VAR30 <= VAR9;
if (VAR9 == 1'b1) begin
VAR13 <= VAR35[15:2];
VAR26 <= VAR27;
end else begin
VAR13 <= VAR14[15:2];
VAR26 <= 32'd0;
end
end
end
end
assign VAR11 = VAR20 | VAR28;
assign VAR1 = VAR31 | VAR16;
always @(negedge VAR21 or posedge VAR7) begin
if (VAR21 == 0) begin
VAR33 <= 'd0;
VAR4 <= 'd0;
VAR16 <= 'd0;
VAR28 <= 'd0;
end else begin
if (VAR19 == 1'b1) begin
VAR33 <= 1'b1;
end else if (VAR1 == 1'b1) begin
VAR33 <= 1'b0;
end
if (VAR33 == 1'b1) begin
VAR4 <= VAR4 + 1'b1;
end else begin
VAR4 <= 3'd0;
end
if ((VAR4 == 3'h7) && (VAR1 == 1'b0)) begin
VAR16 <= 1'b1;
VAR28 <= {2{16'hdead}};
end else begin
VAR16 <= 1'b0;
VAR28 <= 32'd0;
end
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_2.v | 2,262 | module MODULE2 (
VAR2,
VAR3 ,
VAR1,
VAR8 ,
VAR10,
VAR7,
VAR9 ,
VAR4
);
output VAR2;
input VAR3 ;
input VAR1;
input VAR8 ;
input VAR10;
input VAR7;
input VAR9 ;
input VAR4 ;
VAR6 VAR5 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR2,
VAR3 ,
VAR1,
VAR8
);
output VAR2;
input VAR3 ;
input VAR1;
input VAR8 ;
supply1 VAR10;
supply0 VAR7;
supply1 VAR9 ;
supply0 VAR4 ;
VAR6 VAR5 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor3/sky130_fd_sc_ls__xnor3.blackbox.v | 1,269 | module MODULE1 (
VAR8,
VAR4,
VAR5,
VAR3
);
output VAR8;
input VAR4;
input VAR5;
input VAR3;
supply1 VAR7;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab02/lab02/Code/SSeg_map.v | 1,701 | module MODULE1(input[63:0]VAR2,
output[63:0]VAR1
);
assign VAR1 = {VAR2[0], VAR2[4], VAR2[16], VAR2[25], VAR2[17], VAR2[5], VAR2[12], VAR2[24],
VAR2[1], VAR2[6], VAR2[18], VAR2[27], VAR2[19], VAR2[7], VAR2[13], VAR2[26],
VAR2[2], VAR2[8], VAR2[20], VAR2[29], VAR2[21], VAR2[9], VAR2[14], VAR2[28],
VAR2[3], VAR2[10], VAR2[22], VAR2[31], VAR2[23], VAR2[11], VAR2[15], VAR2[30],
VAR2[0], VAR2[4], VAR2[16], VAR2[25], VAR2[17], VAR2[5], VAR2[12], VAR2[24],
VAR2[1], VAR2[6], VAR2[18], VAR2[27], VAR2[19], VAR2[7], VAR2[13], VAR2[26],
VAR2[2], VAR2[8], VAR2[20], VAR2[29], VAR2[21], VAR2[9], VAR2[14], VAR2[28],
VAR2[3], VAR2[10], VAR2[22], VAR2[31], VAR2[23], VAR2[11], VAR2[15], VAR2[30]};
endmodule | gpl-3.0 |
VectorBlox/PYNQ | Pynq-Z1/vivado/ip/pmod_io_switch_1.0/src/switch_bit.v | 3,787 | module MODULE1(
input wire [3:0] VAR18,
output wire [7:0] VAR8,
input wire [7:0] VAR15,
input wire [7:0] VAR31,
input wire VAR32,
output reg VAR13,
output reg VAR4,
output wire VAR27,
input wire VAR17,
input wire VAR1,
output wire VAR9,
input wire VAR28,
input wire VAR12,
output wire VAR19,
input wire VAR22,
input wire VAR3,
output wire VAR16,
input wire VAR20,
input wire VAR10,
output wire VAR30,
input wire VAR21,
input wire VAR5,
output wire VAR11,
input wire VAR14,
input wire VAR2,
output wire VAR6,
input wire VAR26,
input wire VAR29,
output wire VAR25,
input wire VAR24,
input wire VAR7
);
reg [15:0] VAR23;
assign {VAR9,VAR27,VAR11,VAR30,VAR16,VAR19,VAR6,VAR25,VAR8} = VAR23;
always @(VAR18, VAR15, VAR24, VAR26, VAR22, VAR20, VAR21, VAR14, VAR17, VAR28)
case (VAR18)
4'h0: VAR13 = VAR15[0];
4'h1: VAR13 = VAR15[1];
4'h2: VAR13 = VAR15[2];
4'h3: VAR13 = VAR15[3];
4'h4: VAR13 = VAR15[4];
4'h5: VAR13 = VAR15[5];
4'h6: VAR13 = VAR15[6];
4'h7: VAR13 = VAR15[7];
4'h8: VAR13 = VAR24;
4'h9: VAR13 = VAR26;
4'hA: VAR13 = VAR22;
4'hB: VAR13 = VAR20;
4'hC: VAR13 = VAR21;
4'hD: VAR13 = VAR14;
4'hE: VAR13 = VAR17;
4'hF: VAR13 = VAR28;
default: VAR13 = 1'b0;
endcase
always @(VAR18, VAR32)
begin
VAR23 = {16{1'b0}};
case (VAR18)
4'h0: VAR23[0] = VAR32;
4'h1: VAR23[1] = VAR32;
4'h2: VAR23[2] = VAR32;
4'h3: VAR23[3] = VAR32;
4'h4: VAR23[4] = VAR32;
4'h5: VAR23[5] = VAR32;
4'h6: VAR23[6] = VAR32;
4'h7: VAR23[7] = VAR32;
4'h8: VAR23[8] = VAR32;
4'h9: VAR23[9] = VAR32;
4'hA: VAR23[10] = VAR32;
4'hB: VAR23[11] = VAR32;
4'hC: VAR23[12] = VAR32;
4'hD: VAR23[13] = VAR32;
4'hE: VAR23[14] = VAR32;
4'hF: VAR23[15] = VAR32;
endcase
end
always @(VAR18, VAR31, VAR7, VAR29, VAR3, VAR10, VAR5, VAR2, VAR1, VAR12)
case (VAR18)
4'h0: VAR4 = VAR31[0];
4'h1: VAR4 = VAR31[1];
4'h2: VAR4 = VAR31[2];
4'h3: VAR4 = VAR31[3];
4'h4: VAR4 = VAR31[4];
4'h5: VAR4 = VAR31[5];
4'h6: VAR4 = VAR31[6];
4'h7: VAR4 = VAR31[7];
4'h8: VAR4 = VAR7;
4'h9: VAR4 = VAR29;
4'hA: VAR4 = VAR3;
4'hB: VAR4 = VAR10;
4'hC: VAR4 = VAR5;
4'hD: VAR4 = VAR2;
4'hE: VAR4 = VAR1;
4'hF: VAR4 = VAR12;
default: VAR4 = 1'b0;
endcase
endmodule | bsd-3-clause |
sam-falvo/remex | rtl/tx_DS_sel.v | 2,893 | module MODULE1(
input VAR3,
input VAR23,
input VAR26,
input VAR22,
input VAR11,
input VAR15,
input VAR4,
input [8:0] VAR10,
output VAR1,
output VAR19,
output VAR8,
output VAR6,
output VAR12,
output [8:0] VAR14
);
reg VAR24,
VAR17,
VAR9,
VAR13,
VAR18;
reg [5:0] VAR16;
reg VAR1, VAR19, VAR8, VAR6, VAR12;
wire VAR20 = |VAR16;
wire VAR2 = |{VAR24, VAR17, VAR9, VAR13, VAR18};
wire VAR25 = VAR10[8] == 0;
wire VAR7 = (VAR10[8] == 1) && ((VAR10[1:0] == 2'b01) || (VAR10[1:0] == 2'b10));
wire VAR5 = VAR25 | VAR7;
always @(posedge VAR3) begin
VAR24 <= VAR24;
VAR17 <= VAR17;
VAR9 <= VAR9;
VAR13 <= VAR13;
VAR18 <= VAR18;
VAR16 <= VAR16;
VAR12 <= 0;
VAR1 <= 0;
VAR19 <= 0;
VAR8 <= 0;
VAR6 <= 0;
if(VAR23) begin
VAR24 <= 0;
VAR17 <= 0;
VAR9 <= 0;
VAR13 <= 0;
VAR18 <= 0;
VAR16 <= 0;
end
else begin
if(~VAR2 && VAR26) begin
if(VAR22) begin
VAR1 <= 1;
VAR24 <= 1;
VAR18 <= 1;
VAR14 <= 9'b100000011;
VAR12 <= 1;
end
else if(VAR11) begin
VAR19 <= 1;
VAR17 <= 1;
VAR14 <= 9'b100000000;
VAR12 <= 1;
end
else if(VAR15 && VAR5 && VAR20) begin
VAR8 <= 1;
VAR9 <= 1;
VAR14 <= VAR10;
VAR12 <= 1;
VAR16 <= VAR16 - 1;
end
else if(VAR15 && ~VAR5) begin
VAR8 <= 1;
end
else if(VAR4) begin
VAR6 <= 1;
VAR13 <= 1;
VAR18 <= 1;
VAR14 <= 8'b100000011;
VAR12 <= 1;
end
end
else if(VAR2 && VAR26) begin
if(VAR24 && VAR18 && ~VAR17 && ~VAR9 && ~VAR13) begin
VAR18 <= 0;
VAR9 <= 1;
VAR14 <= {1'b0, VAR21};
VAR12 <= 1;
end
if(VAR24 && VAR9 && ~VAR17 && ~VAR13 && ~VAR18) begin
VAR24 <= 0;
VAR9 <= 0;
end
if(~VAR24 && ~VAR9 && ~VAR13 && ~VAR18 && VAR17) begin
VAR17 <= 0;
end
if(~VAR24 && ~VAR17 && ~VAR9 && VAR13 && VAR18) begin
VAR18 <= 0;
VAR17 <= 1;
VAR14 <= 9'b100000000;
VAR12 <= 1;
end
if(~VAR24 && ~VAR9 && ~VAR18 && VAR17 && VAR13) begin
VAR17 <= 0;
VAR13 <= 0;
end
end
end
end
endmodule | mpl-2.0 |
cpulabs/mist1032isa | src/dps/utim64/dps_utim64.v | 6,696 | module MODULE1(
input wire VAR10, input wire VAR19,
input wire VAR36,
input wire VAR6,
output wire VAR16,
input wire VAR35,
input wire [4:0] VAR38,
input wire [31:0] VAR17,
output wire VAR24,
output wire [31:0] VAR39,
output wire VAR7,
input wire VAR31
);
wire [3:0] VAR30;
wire [3:0] VAR29;
reg [1:0] VAR23;
reg [7:0] VAR21;
reg VAR12;
reg [7:0] VAR1;
wire VAR3;
wire VAR15;
wire VAR33;
wire VAR25;
wire VAR8;
assign VAR33 = !VAR3 && !VAR15 && VAR6 && (VAR38 >= 5'h0 && VAR38 <= 5'he);
assign VAR25 = !VAR3 && !VAR15 && VAR6 && (VAR38 >= 5'h10 && VAR38 <= 5'h1e);
assign VAR8 = !VAR3 && !VAR15 && VAR6 && !VAR35 && (VAR38 == 5'h1f);
wire VAR34;
wire VAR11;
wire [31:0] VAR20;
wire [31:0] VAR37;
parameter VAR5 = 1'h0;
parameter VAR2 = 1'h1;
reg [1:0] VAR22; reg VAR26;
always@(posedge VAR10 or negedge VAR19)begin
if(!VAR19)begin
VAR26 <= VAR5;
VAR22 <= 2'b00;
end
else begin
case(VAR26)
VAR5:
begin
if(!VAR35)begin
if(VAR33)begin
VAR26 <= VAR2;
VAR22 <= 2'b00;
end
else if(VAR25)begin
VAR26 <= VAR2;
VAR22 <= 2'b01;
end
else if(VAR8)begin
VAR26 <= VAR2;
VAR22 <= 2'b10;
end
end
end
VAR2:
begin
if(VAR34 || VAR11 || VAR12)begin
VAR26 <= VAR5;
end
end
endcase
end
end
VAR32 VAR27(
.VAR14(VAR10),
.VAR36(VAR36),
.VAR19(VAR19),
.VAR6(VAR33),
.VAR16(VAR3),
.VAR35(VAR35),
.VAR38(VAR38[3:0]),
.VAR17(VAR17),
.VAR24(VAR34),
.VAR39(VAR20),
.VAR13(VAR30)
);
VAR32 VAR28(
.VAR14(VAR10),
.VAR36(VAR36),
.VAR19(VAR19),
.VAR6(VAR25),
.VAR16(VAR15),
.VAR35(VAR35),
.VAR38({1'b0, VAR38[2:0]}),
.VAR17(VAR17),
.VAR24(VAR11),
.VAR39(VAR37),
.VAR13(VAR29)
);
parameter VAR18 = 2'h0;
parameter VAR4 = 2'h1;
parameter VAR9 = 2'h2;
always@(posedge VAR10 or negedge VAR19)begin
if(!VAR19)begin
VAR23 <= VAR18;
VAR21 <= 8'h0;
end
else begin
case(VAR23)
VAR18:
begin
if(|{VAR30, VAR29})begin
VAR23 <= VAR4;
VAR21 <= VAR21 | {VAR29, VAR30};
end
begin
VAR21 <= VAR21 | {VAR29, VAR30};
end
end
VAR4:
begin
if(VAR31)begin
VAR23 <= VAR9;
end
VAR21 <= VAR21 | {VAR29, VAR30};
end
VAR9:
begin
if(VAR8)begin
VAR23 <= VAR18;
VAR21 <= {VAR29, VAR30};
end
else begin
VAR21 <= VAR21 | {VAR29, VAR30};
end
end
default:
begin
VAR23 <= VAR18;
end
endcase
end
end
always@(posedge VAR10 or negedge VAR19)begin
if(!VAR19)begin
VAR12 <= 1'b0;
VAR1 <= 8'h0;
end
else begin
VAR12 <= VAR8; VAR1 <= VAR21;
end
end
assign VAR7 = (VAR23 == VAR4)? 1'b1 : 1'b0;
assign VAR16 = (VAR26 != VAR5) || VAR3 || VAR15;
assign VAR24 = VAR34 || VAR11 || VAR12;
assign VAR39 = (VAR22 == 2'h0)? VAR20 : (
(VAR22 == 2'h1)? VAR37 : VAR1
);
endmodule | bsd-2-clause |
takeshineshiro/fpga_linear_128 | BC_bb.v | 5,012 | module MODULE1 (
address,
VAR1,
VAR2);
input [0:0] address;
input VAR1;
output [15:0] VAR2;
endmodule | mit |
kielfriedt/ece472 | lab2/lookahead.v | 1,409 | module MODULE1(VAR5, VAR4, VAR6, VAR2, VAR1, VAR7, VAR3);
input [3:0] VAR2, VAR1;
input VAR5;
output [2:0] VAR6;
output VAR4;
output VAR7, VAR3;
assign VAR6[0] = VAR1[0] | (VAR2[0] & VAR5);
assign VAR6[1] = VAR1[1] | (VAR1[0] & VAR2[1]) | (VAR2[1] & VAR2[0] & VAR5);
assign VAR6[2] = VAR1[2] | (VAR1[1] & VAR2[2]) | (VAR1[0] & VAR2[1] & VAR2[2]) | (VAR2[2] & VAR2[1] & VAR2[0] & VAR5);
assign VAR4 = VAR1[3] | (VAR1[2] & VAR2[3]) | (VAR1[1] & VAR2[2] & VAR2[3]) | (VAR1[0] & VAR2[1] & VAR2[2] & VAR2[3]) | (VAR2[3] & VAR2[2] & VAR2[1] & VAR2[0] & VAR5);
assign VAR3 = VAR1[3] | (VAR1[2] & VAR2[3]) | (VAR1[1] & VAR2[2] & VAR2[3]) | (VAR2[3] & VAR2[2] & VAR2[1] & VAR1[0]);
assign VAR7 = VAR2[3] & VAR2[2] & VAR2[1] & VAR2[0];
endmodule | gpl-3.0 |
Kipsora/MIPS-CPU | source/machine/cpu/stages/ex.v | 19,996 | module MODULE1(
input wire reset,
input wire[VAR41] VAR23,
input wire[VAR41] VAR5,
input wire VAR18,
input wire[VAR41] VAR8,
input wire[VAR41] VAR72,
input wire VAR17,
input wire[VAR41] VAR20,
input wire[VAR41] VAR67,
input wire[VAR9] VAR29,
input wire VAR27,
input wire[VAR60] VAR25,
input wire[VAR13] VAR12,
input wire[VAR41] VAR32,
input wire[VAR41] VAR53,
input wire[VAR57] VAR36,
input wire VAR69,
input wire[VAR9] VAR24,
input wire[VAR56] VAR78,
input wire[VAR41] VAR47,
input wire VAR71,
input wire[VAR41] VAR77,
output reg[VAR41] VAR43,
output reg[VAR41] VAR66,
output reg VAR7,
output reg VAR34,
output reg VAR74,
output reg[VAR41] VAR63,
output reg[VAR41] VAR70,
output reg[VAR57] VAR55,
output reg VAR46,
output reg[VAR41] VAR11,
output reg[VAR9] VAR40,
output reg[VAR56] VAR22,
output reg VAR30,
output wire[VAR60] VAR6,
output wire[VAR41] VAR1,
output wire[VAR41] VAR38
);
assign VAR6 = VAR25;
assign VAR1 = VAR53;
assign VAR38 = VAR32 + {{16{VAR77[15]}}, VAR77[15 : 0]};
reg[VAR41] VAR51;
reg[VAR41] VAR44;
reg[VAR41] VAR42;
reg[VAR41] VAR64;
reg[VAR9] VAR16;
reg[VAR41] VAR61;
reg[VAR41] VAR31;
reg[VAR41] VAR33;
reg[VAR41] VAR45;
wire VAR14;
wire[VAR41] VAR75;
wire[VAR41] VAR3;
wire[VAR41] VAR19;
wire[VAR41] VAR4;
wire[VAR41] VAR62;
reg VAR15;
reg VAR2;
assign VAR75 = (VAR25 == VAR68
|| VAR25 == VAR59
|| VAR25 == VAR58) ?
(~VAR53) + 1 : VAR53;
assign VAR19 = ~VAR32;
assign VAR3 = VAR32 + VAR75;
assign VAR14 = ((!VAR32[31] && !VAR75[31]) && VAR3[31])
|| (VAR32[31] && VAR75[31]) && (!VAR3[31]);
assign VAR4 = ((VAR25 == VAR48 || VAR25 == VAR28 || VAR25 == VAR49 || VAR25 == VAR26) && VAR32[31]) ? (~VAR32 + 1) : VAR32;
assign VAR62 = ((VAR25 == VAR48 || VAR25 == VAR28 || VAR25 == VAR49 || VAR25 == VAR26) && VAR53[31]) ? (~VAR53 + 1) : VAR53;
always @ begin
VAR30 <= VAR15 || VAR2;
end
always @ begin
if (reset == VAR21) begin
VAR40 <= 0; VAR22 <= 0; VAR2 <= VAR54;
end else begin
case (VAR25)
if (VAR78 == 0) begin VAR40 <= VAR16;
VAR22 <= 1; {VAR33, VAR45} <= 0; VAR2 <= VAR21;
end else if (VAR78 == 1) begin VAR40 <= 0; VAR22 <= 2; {VAR33, VAR45} <= VAR24 + {VAR61, VAR31};
VAR2 <= VAR54;
end
end
if (VAR78 == 0) begin VAR40 <= ~VAR16 + 1;
VAR22 <= 1; {VAR33, VAR45} <= 0; VAR2 <= VAR21;
end else if (VAR78 == 1) begin
VAR40 <= 0; VAR22 <= 2; {VAR33, VAR45} <= VAR24 + {VAR61, VAR31};
VAR2 <= VAR54;
end
end
default: begin
VAR40 <= 0; VAR22 <= 0; VAR2 <= VAR54;
end
endcase
end
end
always @ begin
if (reset == VAR21) begin
{VAR61, VAR31} <= 0; end else if (VAR17 == VAR21) begin
{VAR61, VAR31} <= {VAR20, VAR67};
end else if (VAR18 == VAR21) begin
{VAR61, VAR31} <= {VAR8, VAR72};
end else begin
{VAR61, VAR31} <= {VAR23, VAR5};
end
end
always @ begin
if (reset == VAR21) begin
VAR51 <= 0; end else begin
case (VAR25)
VAR51 <= VAR32 | VAR53;
end
VAR51 <= VAR32 & VAR53;
end
VAR51 <= ~(VAR32 | VAR53);
end
VAR51 <= VAR32 ^ VAR53;
end
default: begin
VAR51 <= 0; end
endcase
end
end
always @ begin
VAR55 <= VAR36;
if ((VAR25 == VAR65 || VAR25 == VAR73
|| VAR25 ==VAR68) && VAR14 == 1'b1) begin
VAR46 <= VAR54;
end else begin
VAR46 <= VAR69;
end
case (VAR12)
VAR11 <= VAR51;
end
VAR11 <= VAR44;
end
VAR11 <= VAR42;
end
VAR11 <= VAR64;
end
VAR11 <= VAR16;
end
VAR11 <= VAR47;
end
default: begin
VAR11 <= 0; end
endcase
end
always @ (*) begin
if (reset == VAR21) begin
VAR74 <= VAR54;
VAR63 <= 0; VAR70 <= 0; end else if (VAR25 == VAR37 || VAR25 == VAR35) begin
VAR74 <= VAR21;
VAR63 <= VAR29[63 : 32];
VAR70 <= VAR29[31 : 0];
end else if (VAR25 == VAR26 || VAR25 == VAR50
|| VAR25 == VAR49 || VAR25 == VAR10) begin
VAR74 <= VAR21;
VAR63 <= VAR33;
VAR70 <= VAR45;
end else if (VAR25 == VAR28 || VAR25 == VAR39) begin
VAR74 <= VAR21;
VAR63 <= VAR16[63 : 32];
VAR70 <= VAR16[31 : 0];
end else if (VAR25 == VAR52) begin
VAR74 <= VAR21;
VAR63 <= VAR32;
VAR70 <= VAR31;
end else if (VAR25 == VAR76) begin
VAR74 <= VAR21;
VAR63 <= VAR61;
VAR70 <= VAR32;
end else begin
VAR74 <= VAR54;
VAR63 <= 0; VAR70 <= 0; end
end
endmodule | mit |
Elphel/x353 | sensor/lens_flat.v | 16,679 | module MODULE1 (VAR21, VAR51, VAR78, VAR31, VAR13, VAR54, VAR18, VAR2,
VAR11, VAR53 );
input VAR21;
input VAR51;
input [15:0] VAR78;
input VAR31;
input VAR13;
input VAR54;
input VAR18;
input [1:0] VAR2;
input [15:0] VAR11;
output[15:0] VAR53;
reg [ 1:0] VAR48;
reg [23:0] VAR17;
reg [23:0] VAR23;
reg VAR7,VAR16,VAR33,VAR44,VAR72;
reg VAR27; reg VAR46,VAR14; reg VAR67;
reg [18:0] VAR47; reg [18:0] VAR34; reg [20:0] VAR88; reg [20:0] VAR1; reg [18:0] VAR77; reg [16:0] VAR71[0:3]; reg [15:0] VAR85; reg [15:0] VAR50; reg [ 3:0] VAR35;
wire [18:0] VAR87; wire [23:0] VAR83; wire [18:0] VAR58; reg [ 4:0] VAR69; reg VAR55;
reg VAR74;
reg [1:0] VAR5;
wire [35:0] VAR10;
reg [17:0] VAR24; wire [35:0] VAR40;
reg [15:0] VAR53;
wire [20:0] VAR38= VAR40[35:15] + {{5{VAR50[15]}},VAR50[15:0]};
wire VAR84=VAR18 && ~VAR69[0];
wire [17:0] VAR59 = {2'b0,VAR11[15:0]}-{{2{VAR85 [15]}},VAR85 [15:0]};
always @ (negedge VAR21) begin
VAR48[1:0] <= {VAR48[0],VAR51};
if (VAR51) VAR17[15: 0] <= VAR78[15:0];
if (VAR48[0]) VAR17[23:16] <= VAR78[ 7:0];
VAR23[23:0] <= VAR17[23:0];
VAR7 <= VAR48[1] && (VAR17[23:19]==5'h00); VAR33 <= VAR48[1] && (VAR17[23:19]==5'h01); VAR72 <= VAR48[1] && (VAR17[23:19]==5'h02); VAR16 <= VAR48[1] && (VAR17[23:21]==3'h1 ); VAR44 <= VAR48[1] && (VAR17[23:21]==3'h2 ); VAR27 <= VAR48[1] && (VAR17[23:19]==5'h0c); VAR46 <= VAR48[1] && (VAR17[23:16]==8'h68); VAR14 <= VAR48[1] && (VAR17[23:16]==8'h69); VAR67 <= VAR48[1] && (VAR17[23:16]==8'h6a);
if (VAR7) VAR47[18:0] <= VAR23[18:0];
if (VAR33) VAR34[18:0] <= VAR23[18:0];
if (VAR16) VAR88[20:0] <= VAR23[20:0];
if (VAR44) VAR1[20:0] <= VAR23[20:0];
if (VAR72) VAR77[18:0] <= VAR23[18:0];
if (VAR27) VAR71[VAR23[18:17]] <= VAR23[16:0];
if (VAR46) VAR85 [15:0] <= VAR23[15:0];
if (VAR14) VAR50[15:0] <= VAR23[15:0];
if (VAR67) VAR35 [ 3:0] <= VAR23[ 3:0];
end
always @ (posedge VAR31) begin
VAR69[4:0]<={VAR69[3:0],VAR18};
VAR55 <= !VAR13 && (VAR55 || VAR18);
VAR74<= VAR55? VAR74:VAR2[0];
VAR5[1:0] <= { VAR55? (VAR84 ^ VAR5[1]):VAR2[1] ,
(VAR55 &&(~VAR84))?~VAR5[0]:VAR74 };
case (VAR35 [2:0])
3'h0:VAR24[17:0]<= (~VAR10[35] & |VAR10[34:33]) ? 18'h1ffff:VAR10[33:16]; 3'h1:VAR24[17:0]<= (~VAR10[35] & |VAR10[34:32]) ? 18'h1ffff:VAR10[32:15];
3'h2:VAR24[17:0]<= (~VAR10[35] & |VAR10[34:31]) ? 18'h1ffff:VAR10[31:14];
3'h3:VAR24[17:0]<= (~VAR10[35] & |VAR10[34:30]) ? 18'h1ffff:VAR10[30:13];
3'h4:VAR24[17:0]<= (~VAR10[35] & |VAR10[34:29]) ? 18'h1ffff:VAR10[29:12];
3'h5:VAR24[17:0]<= (~VAR10[35] & |VAR10[34:28]) ? 18'h1ffff:VAR10[28:11];
3'h6:VAR24[17:0]<= (~VAR10[35] & |VAR10[34:27]) ? 18'h1ffff:VAR10[27:10];
3'h7:VAR24[17:0]<= (~VAR10[35] & |VAR10[34:26]) ? 18'h1ffff:VAR10[26: 9];
endcase
if (VAR69[4]) VAR53[15:0] <= VAR38[20]? 16'h0: ((|VAR38[19:16])?16'hffff: VAR38[15:0]);
end
VAR76 #(
.VAR8(1), .VAR15(1), .VAR3("VAR86"), .VAR29(1) ) VAR79 (
.VAR32(), .VAR73(VAR10[35:0]), .VAR70((VAR58[18]==VAR58[17])?VAR58[17:0]:(VAR58[18]?18'h20000:18'h1ffff)), .VAR12({1'b0,VAR71[~VAR5[1:0]]}), .VAR62(18'b0), .VAR28(VAR69[0]), .VAR20(VAR69[0]), .VAR36(VAR69[1]), .VAR19(VAR31), .VAR75(1'b0), .VAR63(1'b0), .VAR9(1'b0) );
VAR76 #(
.VAR8(1), .VAR15(0), .VAR3("VAR86"), .VAR29(1) ) VAR64 (
.VAR32(), .VAR73(VAR40[35:0]), .VAR70(VAR59[17:0]), .VAR12(VAR24[17:0]), .VAR62(18'b0), .VAR28(VAR69[2]), .VAR20(VAR69[0]), .VAR36(VAR69[3]), .VAR19(VAR31), .VAR75(1'b0), .VAR63(1'b0), .VAR9(1'b0) );
MODULE2 #(.VAR25(19), .VAR45(22), .VAR39(12), .VAR30(19), .VAR6(21)) VAR22( .VAR31(VAR31), .VAR57(VAR13), .VAR4(VAR54), .VAR42(VAR77[18:0]), .VAR49(24'b0), .VAR26(VAR34[18:0]), .VAR56(VAR1[20:0]), .VAR43(VAR87[18:0]),
.VAR52(VAR83[23:0]));
MODULE2 #(.VAR25(19), .VAR45(22), .VAR39(12), .VAR30(19), .VAR6(21)) VAR66( .VAR31(VAR31), .VAR57(VAR54), .VAR4(VAR18), .VAR42(VAR87[18:0]), .VAR49(VAR83[23:0]), .VAR26(VAR47[18:0]), .VAR56(VAR88[20:0]), .VAR43(VAR58[18:0]),
.VAR52());
endmodule
module MODULE2(
VAR31, VAR57, VAR4, VAR42, VAR49, VAR26, VAR56,
VAR43,
VAR52); parameter VAR25= 18; parameter VAR45=22; parameter VAR39=12; parameter VAR30=18; parameter VAR6=21; parameter VAR65=VAR6-VAR45+VAR39;
input VAR31;
input VAR57;
input VAR4;
input [VAR25-1:0] VAR42;
input [VAR45+1:0] VAR49;
input [VAR30-1:0] VAR26;
input [VAR6-1:0] VAR56;
output [VAR25-1:0] VAR43;
output [VAR45+1:0] VAR52;
reg [VAR45+1:0] VAR52; reg [VAR45+1:0] VAR60; reg [VAR45+1:1] VAR81; reg [(VAR65)-1:0] VAR80; reg [VAR25-1:0] VAR43; reg VAR37, VAR82; reg [VAR25-1:0] VAR68;
reg [VAR30-1:0] VAR70;
wire [VAR45+1:0] VAR61={VAR81[VAR45+1:1],1'b0}+VAR60[VAR45+1:0]-{VAR80[1:0],{VAR45{1'b0}}};
wire [1:0] VAR41= {VAR61[VAR45+1] & (~VAR61[VAR45] | ~VAR61[VAR45-1]),
(VAR61[VAR45+1:VAR45-1] != 3'h0) &
(VAR61[VAR45+1:VAR45-1] != 3'h7)};
always @(posedge VAR31) begin
VAR82 <=VAR57;
VAR37 <=VAR4;
if (VAR57) begin
VAR68 [VAR25-1:0] <= VAR42[ VAR25-1:0];
VAR80[(VAR65)-1:0] <= VAR56[VAR6-1: (VAR45-VAR39)];
VAR52[VAR45+1:0] <= VAR49[VAR45+1:0];
VAR60[VAR45+1:0] <= {{VAR45+2-VAR30{VAR26[VAR30-1]}},VAR26[VAR30-1:0]}+{VAR56[VAR6-1:0],{VAR45-VAR39{1'b0}}}; VAR70 [VAR30-1:0] <= VAR26[VAR30-1:0];
end else if (VAR4) begin
VAR80[(VAR65)-1:0] <= VAR80[(VAR65)-1:0]+{{((VAR65)-1){VAR41[1]}},VAR41[1:0]};
VAR52[VAR45-1:0]<= VAR61[VAR45-1:0];
VAR52[VAR45+1:VAR45]<= VAR61[VAR45+1:VAR45]-VAR41[1:0];
end
if (VAR82) VAR43[VAR25-1:0] <= VAR68[ VAR25-1:0];
end
else if (VAR37) VAR43[VAR25-1:0] <= VAR43[VAR25-1:0]+{{(VAR25-(VAR65)){VAR80[(VAR65)-1]}},VAR80[(VAR65)-1:0]};
if (VAR82) VAR81[VAR45+1:1] <= {{VAR45+2-VAR30{VAR70[VAR30-1]}},VAR70[VAR30-1:0]};
end
else if (VAR4) VAR81[VAR45+1:1] <= VAR81[VAR45+1:1] + {{VAR45+2-VAR30{VAR70[VAR30-1]}},VAR70[VAR30-1:0]};
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfsbp/sky130_fd_sc_hs__sdfsbp.blackbox.v | 1,419 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR1 ,
VAR3 ,
VAR7 ,
VAR4 ,
VAR2
);
input VAR9 ;
input VAR8 ;
output VAR1 ;
output VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR2;
supply1 VAR6;
supply0 VAR5;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_rdlvl.v | 84,965 | module MODULE1 #
(
parameter VAR32 = 100, parameter VAR217 = 2, parameter VAR150 = 3333, parameter VAR209 = 300, parameter VAR164 = 64, parameter VAR197 = 3, parameter VAR187 = 8, parameter VAR69 = 8, parameter VAR225 = 10, parameter VAR188 = 5, parameter VAR137 = "VAR138", parameter VAR121 = "VAR94" )
(
input clk,
input rst,
input [1:0] VAR95,
input VAR190,
output reg [1:0] VAR142,
output reg [1:0] VAR75,
output reg VAR222,
input VAR6,
input [VAR164-1:0] VAR171,
input [VAR164-1:0] VAR215,
input [VAR164-1:0] VAR86,
input [VAR164-1:0] VAR127,
output reg [VAR187-1:0] VAR126,
output reg VAR128,
output reg [3:0] VAR125,
output reg VAR200,
output reg [5*VAR187-1:0] VAR144,
output reg [5*VAR187-1:0] VAR67,
output reg [2*VAR187-1:0] VAR99,
output reg [2*VAR187-1:0] VAR184,
output reg [4:0] VAR210,
input VAR70, output reg VAR8, output [VAR197-1:0] VAR111, output [5*VAR187-1:0] VAR122,
output [5*VAR187-1:0] VAR140,
output reg [3*VAR187-1:0] VAR166,
output reg [2*VAR187-1:0] VAR193,
output reg [4:0] VAR195,
input VAR7,
input VAR123,
input VAR236,
input VAR134,
input VAR204,
input VAR148,
input [VAR197-1:0] VAR45,
input VAR40,
input [VAR197-1:0] VAR232,
input VAR42,
output [255:0] VAR13
);
localparam VAR85 = 3;
localparam VAR203 = 16;
localparam VAR161 = 8;
localparam VAR53 = VAR161/(2*VAR217);
localparam integer VAR36 = 1000000/(VAR209 * 64);
localparam VAR20
= (((VAR150/VAR217/4)/VAR36) > 31) ? 31 :
((VAR150/VAR217/4)/VAR36);
localparam VAR90 = 32;
localparam VAR208 = 8;
localparam VAR158 = 5;
localparam [11:0] VAR108 = 12'hFFF;
localparam [11:0] VAR57 = 12'h001;
localparam VAR74 = 32 - (VAR225/2);
localparam VAR55 = (VAR225/2);
localparam [4:0] VAR143 = 5'h00;
localparam [4:0] VAR135 = 5'h01;
localparam [4:0] VAR16 = 5'h02;
localparam [4:0] VAR77 = 5'h03;
localparam [4:0] VAR207 = 5'h04;
localparam [4:0] VAR72 = 5'h05;
localparam [4:0] VAR76 = 5'h06;
localparam [4:0] VAR147 = 5'h07;
localparam [4:0] VAR170 = 5'h08;
localparam [4:0] VAR1 = 5'h09;
localparam [4:0] VAR15 = 5'h0A;
localparam [4:0] VAR198 = 5'h0B;
localparam [4:0] VAR224 = 5'h0C;
localparam [4:0] VAR79 = 5'h0D;
localparam [4:0] VAR116 = 5'h0E;
localparam [4:0] VAR26 = 5'h0F;
localparam [4:0] VAR23 = 5'h10;
localparam [4:0] VAR172 = 5'h11;
localparam [4:0] VAR156 = 5'h12;
localparam [4:0] VAR97 = 5'h1F;
localparam VAR28 = 3'h0;
localparam VAR17 = 3'h1;
localparam VAR185 = 3'h2;
localparam VAR181 = 3'h3;
localparam VAR14 = 3'h4;
localparam VAR231 = 3'h5;
localparam VAR196 = 3'h6;
integer VAR61;
integer VAR167;
integer VAR50;
genvar VAR93;
reg [VAR197-1:0] VAR64;
reg VAR104;
reg VAR92;
reg [4:0] VAR133;
reg VAR165;
wire VAR39;
reg VAR51;
reg [4:0] VAR41;
reg [2*VAR187-1:0] VAR221;
reg [1:0] VAR43;
reg [4:0] VAR4;
reg [VAR197-1:0] VAR124;
reg [VAR187-1:0] VAR174;
reg [4:0] VAR228[VAR187-1:0];
reg VAR130;
reg VAR131;
reg VAR206;
reg VAR10;
reg [5*VAR187-1:0] VAR162;
reg VAR62;
reg [4:0] VAR56;
reg VAR212;
reg [4:0] VAR192;
reg [2*VAR187-1:0] VAR109;
reg [2:0] VAR230;
reg [2:0] VAR33;
reg [5:0] VAR98;
reg [4:0] VAR60;
reg [4:0] VAR189;
reg [3:0] VAR238;
reg [2:0] VAR58;
reg [3:0] VAR191;
reg [11:0] VAR105;
reg VAR155;
reg [11:0] VAR25;
reg VAR73;
reg VAR194;
wire VAR3;
reg [5*VAR187-1:0] VAR89;
reg [4:0] VAR2;
reg VAR132;
reg VAR78;
reg VAR237;
reg VAR31;
reg VAR163;
reg VAR223;
reg VAR216;
reg VAR22;
reg VAR119;
reg [4:0] VAR178;
reg VAR47;
reg VAR202;
reg VAR154;
reg [VAR69-1:0] VAR220;
reg [VAR69-1:0] VAR173;
reg [VAR69-1:0] VAR183;
reg [VAR69-1:0] VAR82;
reg VAR106;
reg [VAR53-1:0] VAR160 [VAR69-1:0];
reg [VAR53-1:0] VAR38 [VAR69-1:0];
reg [VAR53-1:0] VAR102 [VAR69-1:0];
reg [VAR53-1:0] VAR101 [VAR69-1:0];
reg VAR19;
reg VAR201;
wire [VAR53-1:0] VAR226 [3:0];
wire [VAR53-1:0] VAR65 [3:0];
reg [VAR69-1:0] VAR110;
reg VAR151;
reg [VAR69-1:0] VAR227;
reg VAR179;
reg [VAR69-1:0] VAR80;
reg VAR153;
reg [VAR69-1:0] VAR107;
reg VAR141;
wire [VAR53-1:0] VAR87 [3:0];
wire [VAR53-1:0] VAR21 [3:0];
wire VAR24;
reg VAR5;
reg VAR168;
reg VAR63;
reg [VAR69-1:0] VAR233;
reg VAR114;
reg [VAR69-1:0] VAR149;
reg VAR214;
reg [VAR69-1:0] VAR118;
reg VAR54;
reg [VAR69-1:0] VAR83;
reg VAR177;
reg VAR115;
reg [VAR53-1:0] VAR34 [VAR69-1:0];
reg [VAR53-1:0] VAR9 [VAR69-1:0];
reg [VAR53-1:0] VAR219 [VAR69-1:0];
reg [VAR53-1:0] VAR186 [VAR69-1:0];
reg [VAR197-1:0] VAR35;
reg VAR218;
reg VAR205;
reg VAR136;
reg [4:0] VAR27;
reg [4:0] VAR44;
reg [4:0] VAR199;
reg [VAR53-1:0] VAR117 [VAR69-1:0];
reg [VAR53-1:0] VAR91 [VAR69-1:0];
reg [VAR53-1:0] VAR49 [VAR69-1:0];
reg [VAR53-1:0] VAR129 [VAR69-1:0];
reg VAR180;
reg [VAR69-1:0] VAR159;
reg VAR81;
reg [VAR69-1:0] VAR88;
reg VAR152;
reg VAR103;
reg VAR48;
reg [VAR69-1:0] VAR175;
reg VAR68;
reg [VAR69-1:0] VAR52;
reg VAR182;
reg VAR84;
reg VAR229;
reg VAR139;
reg [5:0] VAR112;
reg [4:0] VAR113 [0:VAR187-1];
reg [4:0] VAR71 [0:VAR187-1];
assign VAR13[1:0] = VAR95[1:0];
assign VAR13[2] = VAR132;
assign VAR13[3] = VAR201;
assign VAR13[6:4] = VAR230[2:0];
assign VAR13[8:7] = VAR43[1:0];
assign VAR13[13:9] = VAR41[4:0];
assign VAR13[20:14] = VAR98;
assign VAR13[21] = VAR163;
assign VAR13[22] = VAR216;
assign VAR13[23] = VAR19;
assign VAR13[24] = VAR84;
assign VAR13[32:25] = {VAR91[0][1:0], VAR129[0][1:0],
VAR117[0][1:0], VAR49[0][1:0]};
assign VAR13[40:33] = {VAR38[0][1:0],
VAR101[0][1:0],
VAR160[0][1:0],
VAR102[0][1:0]};
assign VAR13[41] = VAR139;
assign VAR13[42] = VAR22;
assign VAR13[47:43] = VAR178;
assign VAR13[48] = VAR47;
assign VAR13[53:49] = VAR2;
assign VAR13[58:54] = VAR44;
assign VAR13[64:59] = VAR112;
assign VAR13[67:65] = VAR33;
assign VAR13[72:68] = VAR133;
assign VAR13[73] = VAR31;
assign VAR13[74] = VAR237;
assign VAR13[78:75] = VAR64;
assign VAR13[82:79] = VAR124;
assign VAR13[83] = VAR104;
assign VAR13[84] = VAR92;
assign VAR13[85] = VAR132;
assign VAR13[86] = VAR163;
assign VAR13[91:87] = VAR27;
assign VAR13[96:92] = VAR199;
assign VAR13[102:97] = VAR112;
assign VAR13[255:103] = 'b0;
generate
genvar VAR66;
for (VAR66 = 0; VAR66 < VAR187; VAR66 = VAR66 + 1) begin: VAR11
assign VAR122[(5*VAR66)+4:(5*VAR66)]
= VAR113[VAR66];
assign VAR140[(5*VAR66)+4:(5*VAR66)]
= VAR71[VAR66];
always @(posedge clk)
if (rst) begin
end else begin
if ((VAR41 == VAR147) ||
(VAR41 == VAR198)) begin
if (VAR163 && (VAR64 == VAR66))
VAR113[VAR66]
if (VAR216 && (VAR64 == VAR66))
VAR71[VAR66]
end
end
end
endgenerate
always @(posedge clk) begin
end
generate
genvar VAR234;
for (VAR234 = 0; VAR234 < VAR187; VAR234 = VAR234 + 1) begin: VAR37
always @(posedge clk) begin
end
end
endgenerate
always @(posedge clk) begin
case (VAR142[0])
endcase
end
generate
genvar VAR29;
for (VAR29 = 0; VAR29 < VAR69; VAR29 = VAR29 + 1) begin: VAR46
always @(posedge clk) begin
VAR29];
VAR29];
VAR29];
VAR29];
end
end
endgenerate
always @(posedge clk) begin
if (VAR104) begin
if ((VAR137 == "VAR138") ||
(VAR137 == "VAR235")) begin
end else if ((VAR137 == "VAR59") ||
(VAR137 == "VAR145")) begin
end
end else if (VAR121 == "VAR96") begin
if (VAR7 || VAR123 || VAR40) begin
VAR236 | VAR134}};
end else begin
VAR134;
end
end
end
always @(posedge clk) begin
if (VAR121 == "VAR96") begin
if (VAR7 || VAR123 || VAR42) begin
VAR123 |
VAR204 |
VAR148}};
end else begin
VAR148;
end
end
end
always @(posedge clk) begin
if ((VAR137 == "VAR138") ||
(VAR137 == "VAR235")) begin
end else if (VAR137 == "VAR59") begin
end else if (VAR137 == "VAR145") begin
end
end
always @(posedge clk) begin
end
assign VAR3 = VAR104 |
VAR106 |
(VAR41 == VAR79);
assign VAR24 = VAR3 || (VAR238 != VAR203-1);
always @(posedge clk)
if (rst)
end
else if (VAR3)
end
else if (VAR238 != VAR203-1)
always @(posedge clk)
if (rst)
end
else
generate
genvar VAR100;
for (VAR100 = 0; VAR100 < VAR69; VAR100 = VAR100 + 1) begin: VAR213
always @(posedge clk) begin
VAR183[VAR100]};
VAR220[VAR100]};
VAR82[VAR100]};
VAR173[VAR100]};
end
end
endgenerate
always @(posedge clk)
if (rst) begin
end else begin
if (VAR191 == VAR53-1) begin
end else begin
end
end
always @(posedge clk)
if (rst) begin
end else begin
VAR182 <= VAR139 & VAR84;
if (VAR229)
end
else if (VAR139 && VAR84)
end
always @(posedge clk)
if (rst) begin
end else begin
if (VAR229)
end
else if (VAR182)
if (VAR229) begin
end else begin
end
end
always @(posedge clk)
if (rst) begin
end else begin
end
generate
for (VAR93 = 0; VAR93 < VAR69; VAR93 = VAR93 + 1) begin: VAR12
always @(posedge clk) begin
if (VAR139) begin
end
if (VAR139 && VAR84) begin
end
end
end
endgenerate
generate
genvar VAR30;
for (VAR30 = 0; VAR30 < VAR69; VAR30 = VAR30 + 1) begin: VAR146
always @(posedge clk) begin
if (VAR139) begin
if (VAR49[VAR30] == VAR102[VAR30])
end
else
if (VAR117[VAR30] == VAR160[VAR30])
end
else
if (VAR129[VAR30] == VAR101[VAR30])
end
else
if (VAR91[VAR30] == VAR38[VAR30])
end
else
if (VAR49[VAR30] == VAR219[VAR30])
end
else
if (VAR117[VAR30] == VAR34[VAR30])
end
else
if (VAR129[VAR30] == VAR186[VAR30])
end
else
if (VAR91[VAR30] == VAR9[VAR30])
end
else
end
end
end
endgenerate
always @(posedge clk) begin
end
always @(posedge clk) begin
VAR132
!VAR68 || !VAR81) &&
VAR103);
VAR5
!VAR54 || !VAR114) &&
VAR115);
end
always @(posedge clk)
if (rst)
else begin
if (VAR194)
end
else if (VAR237)
end
always @(posedge clk)
if (rst)
else begin
if (((VAR137 == "VAR59") ||
(VAR137 == "VAR235")) &&
(VAR105 == 12'h001))
end
else if (VAR105 == VAR108)
else
end
always @(posedge clk)
if (rst)
else begin
if (VAR194)
end
else if (VAR155)
end
always @(posedge clk)
if (rst)
else begin
if (VAR194)
end
else if (((VAR137 == "VAR59") ||
(VAR137 == "VAR235")) &&
(VAR25 == 12'h001))
else if (VAR25 == VAR57)
end
assign VAR39 = VAR78 | VAR154;
always @(posedge clk)
if ((VAR41 == VAR143) || (VAR41 == VAR1)) begin
end else if (VAR41 != VAR77) begin
end else if (VAR41 == VAR77) begin
if (!VAR73) begin
if (VAR132)
if (VAR5)
end else begin
if (VAR39) begin
end else begin
if (VAR33 == VAR85-1)
end
else begin
end
end
end
end
always @(posedge clk)
if (rst) begin
end else begin
if (VAR106) begin
end else if (VAR104) begin
if (VAR92)
end
else
if ((VAR178 == VAR74-2) && VAR92)
end
else
end
end
always @(posedge clk)
if (rst)
end
else begin
if (VAR106)
end
else if (VAR133 == VAR74-1)
end
always @(posedge clk)
if (rst) begin
end else begin
case (VAR41)
VAR143:
if (VAR95[0]) begin
if (VAR137 == "VAR145") begin
end else begin
end
end
VAR135:
if (!VAR24)
VAR16: begin
if (VAR182)begin
end
else
end
end
VAR77: begin
if (VAR73) begin
if (VAR39) begin
if (!VAR163) begin
if (VAR178 == 5'b00000)
end
else
end
if (VAR163 && VAR22) begin
end else begin
if (!VAR47)
end
else begin
end
end
end else begin
if (!VAR47)
end
else begin
end
end
end
end
VAR207: begin
if (VAR182)begin
end
else
end
end
VAR72: begin
end
VAR76: begin
if (!VAR24)
end
VAR147: begin
if (VAR216)
VAR98
{1'b0, VAR2})>>1) + 1;
end
else if (VAR163)
if (VAR2 >= VAR74/2 &&
((VAR2+VAR20) < (VAR74 - 1)))
VAR98
end
else
VAR98
else
end
VAR170: begin
if (VAR98 == 7'b0000001)
end
VAR1: begin
if (VAR6) begin
if ((VAR64 >= VAR187-1) ||
(VAR137 == "VAR59"))
end
else begin
end
end
end
VAR198: begin
if (!VAR163) begin
end
if (VAR98 == 7'b0000000) begin
end else begin
end
end
VAR224: begin
if (VAR73) begin
if ((VAR132) && (~VAR163 ||
(VAR112 > 6'd5))) begin
if (VAR133 != 5'd0)
end
else
end else begin
if (VAR202) begin
end else
end
end
end
VAR79: begin
end
VAR116: begin
if (!VAR24)
end
VAR26: begin
if (VAR199 <= VAR112)
end
else if ((VAR2 + VAR112) <= VAR74-1)
end
else
end
VAR23: begin
if (VAR60 == 7'b0000000)
end
else begin
end
end
VAR156: begin
if(VAR178 < (VAR55))begin
end else
end
VAR15:
VAR97: begin
if (VAR189 == 5'b00001)
end
endcase
end
always @(posedge clk) begin
if (VAR133 > 5'd0)
end
else
end
always @(posedge clk) begin
end
assign VAR87[3] = 2'b10;
assign VAR226[3] = 2'b01;
assign VAR21[3] = 2'b11;
assign VAR65[3] = 2'b00;
assign VAR87[2] = 2'b11;
assign VAR226[2] = 2'b00;
assign VAR21[2] = 2'b00;
assign VAR65[2] = 2'b11;
assign VAR87[1] = 2'b10;
assign VAR226[1] = 2'b01;
assign VAR21[1] = 2'b10;
assign VAR65[1] = 2'b01;
assign VAR87[0] = 2'b11;
assign VAR226[0] = 2'b00;
assign VAR21[0] = 2'b01;
assign VAR65[0] = 2'b10;
generate
genvar VAR18;
for (VAR18 = 0; VAR18 < VAR69; VAR18 = VAR18 + 1) begin: VAR169
always @(posedge clk) begin
if (VAR49[VAR18] == VAR87[VAR18%4])
end
else
if (VAR117[VAR18] == VAR226[VAR18%4])
end
else
if (VAR129[VAR18] == VAR21[VAR18%4])
else
if (VAR91[VAR18] == VAR65[VAR18%4])
else
end
end
endgenerate
always @(posedge clk) begin
VAR151 &&
VAR141 &&
VAR179);
end
always @(posedge clk)
if (rst) begin
end else begin
if (VAR230 != VAR17) begin
end else begin
if (VAR58 == VAR208-1)
end
end
always @(posedge clk) begin
end
always @(posedge clk) begin
if (rst) begin
end else begin
case (VAR230)
VAR28:
if (VAR95[1]) begin
if (VAR137 == "VAR145") begin
case (VAR188)
endcase
end else
end
VAR17: begin
if ((VAR218 == 1'b1) && !VAR136)
end
VAR185: begin
if (VAR201)
end
else if (VAR4 == VAR90-1) begin
if (VAR43 != 2'b11) begin
if (VAR137 == "VAR59") begin
for (VAR61 = 0; VAR61 < VAR187; VAR61 = VAR61 + 1) begin: VAR120
VAR109[2*VAR61+:2]
end
end else
VAR109[2*(VAR124)+:2]
end else
end
end
VAR14: begin
if (VAR4 > VAR56)
if (VAR137 == "VAR59") begin
for (VAR167 = 0; VAR167 < VAR187; VAR167 = VAR167 + 1) begin: VAR176
end
end else
if (VAR6)
if (((VAR187 == 1) || (VAR137 == "VAR59")) ||
(VAR124 == VAR187-1)) begin
end else begin
end
end
VAR231:
VAR196: begin
if (VAR70) begin
end
end
endcase
end
end
assign VAR111 = VAR124;
always @(posedge clk)
if (VAR137 == "VAR145")
case (VAR188)
endcase
end
else if (!VAR142[1])
end
else
generate
genvar VAR211;
for (VAR211 = 0; VAR211 < VAR187; VAR211 = VAR211 + 1) begin: VAR157
always @(posedge clk)
VAR228[VAR211]
always @(posedge clk) begin
if (rst) begin
end else if (!VAR62) begin
end else begin
case (VAR228[VAR211])
5'b00000: begin
end
5'b00001: begin
end
5'b00010: begin
end
5'b00011: begin
end
default: begin
end
endcase
end
end
end
endgenerate
always @(posedge clk)
always @(posedge clk)
if (rst)
end
else
always @(posedge clk)
if (rst) begin
end else begin
end
endmodule | lgpl-3.0 |
alankarkotwal/lc-3b-processor | design/controller.v | 6,268 | module MODULE1(clk, VAR9, VAR11, VAR14, VAR15, VAR3, VAR23, VAR4, VAR21, VAR6, VAR18, VAR17, VAR8, VAR1, VAR12, VAR7, VAR2, VAR19, VAR16, VAR10, VAR5, VAR22);
input [15:0] VAR9;
input clk, VAR11, VAR14, VAR15;
output reg [3:0] VAR3;
output reg VAR23;
output reg [1:0] VAR4;
output reg [2:0] VAR21;
output reg [1:0] VAR6;
output reg [1:0] VAR18;
output reg [1:0] VAR17;
output reg [1:0] VAR8;
output reg VAR1;
output reg VAR12;
output reg VAR7;
output reg VAR2;
output reg VAR19;
output reg VAR16;
output reg [1:0] VAR10;
output reg [1:0] VAR5;
output reg VAR22;
assign VAR13 = VAR9[5];
assign VAR20 = (VAR9[11] && VAR11) || (VAR9[10] && VAR14) || (VAR9[9] && VAR15);
assign VAR24 = VAR9[11];
always@(posedge clk) begin
case(VAR3)
1: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b111;
VAR6 = 2'b01;
VAR18 = 2'b01;
VAR17 = 2'b10;
VAR8 = 2'b10;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b0;
VAR19 = 1'b0;
VAR16 = 1'b1;
VAR10 = 2'b00;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
2: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b000;
VAR6 = 2'b11;
VAR18 = 2'b11;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b11;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
3: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b111;
VAR6 = 2'b00;
VAR18 = 2'b00;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b0;
VAR10 = {VAR9[15], VAR9[14]};
VAR5 = {VAR9[5], VAR9[4]};
VAR22 = 1'b1;
end
4: begin
VAR23 = 1'b1;
VAR4 = 2'b01;
VAR21 = 3'b111;
VAR6 = 2'b11;
VAR18 = 2'b11;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b0;
VAR12 = 1'b0;
VAR7 = 1'b0;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b11;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
5: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b011;
VAR6 = 2'b01;
VAR18 = 2'b00;
VAR17 = 2'b00;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b0;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b00;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
6: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b111;
VAR6 = 2'b11;
VAR18 = 2'b11;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b0;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b11;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
7: begin
VAR23 = 1'b1;
VAR4 = 2'b10;
VAR21 = 3'b111;
VAR6 = 2'b11;
VAR18 = 2'b11;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b0;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b11;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
8: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b001;
VAR6 = 2'b01;
VAR18 = 2'b00;
VAR17 = 2'b01;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b0;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b00;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
9: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b101;
VAR6 = 2'b00;
VAR18 = 2'b00;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b00;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
10: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b111;
VAR6 = 2'b11;
VAR18 = 2'b11;
VAR17 = 2'b11;
VAR8 = 2'b01;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b11;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
11: begin
VAR23 = 1'b1;
VAR4 = 2'b00;
VAR21 = 3'b111;
VAR6 = 2'b10;
VAR18 = 2'b10;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b0;
VAR12 = 1'b0;
VAR7 = 1'b0;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b0;
VAR10 = 2'b00;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
12: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b010;
VAR6 = 2'b00;
VAR18 = 2'b00;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b00;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
13: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b011;
VAR6 = 2'b01;
VAR18 = 2'b00;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b0;
VAR10 = 2'b00;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
14: begin
VAR23 = 1'b1;
VAR4 = 2'b01;
VAR21 = 3'b111;
VAR6 = 2'b11;
VAR18 = 2'b11;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b0;
VAR12 = 1'b0;
VAR7 = 1'b0;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b11;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
15: begin
VAR23 = 1'b0;
VAR4 = 2'b11;
VAR21 = 3'b111;
VAR6 = 2'b11;
VAR18 = 2'b11;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b11;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
16: begin
VAR23 = 1'b0;
VAR4 = 2'b11;
VAR21 = 3'b101;
VAR6 = 2'b00;
VAR18 = 2'b00;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b00;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
17: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b111;
VAR6 = 2'b11;
VAR18 = 2'b11;
VAR17 = 2'b11;
VAR8 = 2'b01;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b11;
VAR5 = 2'b11;
VAR22 = 1'b0;
end
18: begin
VAR23 = 1'b1;
VAR4 = 2'b11;
VAR21 = 3'b010;
VAR6 = 2'b00;
VAR18 = 2'b00;
VAR17 = 2'b11;
VAR8 = 2'b11;
VAR1 = 1'b1;
VAR12 = 1'b0;
VAR7 = 1'b1;
VAR2 = 1'b1;
VAR19 = 1'b1;
VAR16 = 1'b1;
VAR10 = 2'b00;
VAR5 = 2'b11;
VAR22 = 1'b1;
end
endcase
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311ai/sky130_fd_sc_hd__o311ai.pp.symbol.v | 1,387 | module MODULE1 (
input VAR9 ,
input VAR1 ,
input VAR3 ,
input VAR10 ,
input VAR6 ,
output VAR2 ,
input VAR7 ,
input VAR5,
input VAR4,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41o/sky130_fd_sc_hs__a41o.behavioral.pp.v | 1,959 | module MODULE1 (
VAR7,
VAR8,
VAR16 ,
VAR11 ,
VAR15 ,
VAR13 ,
VAR5 ,
VAR14
);
input VAR7;
input VAR8;
output VAR16 ;
input VAR11 ;
input VAR15 ;
input VAR13 ;
input VAR5 ;
input VAR14 ;
wire VAR5 VAR9 ;
wire VAR2 ;
wire VAR3;
and VAR4 (VAR9 , VAR11, VAR15, VAR13, VAR5 );
or VAR10 (VAR2 , VAR9, VAR14 );
VAR12 VAR1 (VAR3, VAR2, VAR7, VAR8);
buf VAR6 (VAR16 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21bo/sky130_fd_sc_hs__a21bo.blackbox.v | 1,347 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR5 ,
VAR4
);
output VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR4;
supply1 VAR6;
supply0 VAR3;
endmodule | apache-2.0 |
mshaklunov/usb_devtrsac | rtl/usb_devtrsac.v | 9,996 | module MODULE1 (
input VAR40,
input VAR45,
input VAR24,
input VAR20,
input VAR74,
input VAR14,
output VAR61,
output VAR16,
output VAR36,
output[1:0] VAR33,
output[3:0] VAR79,
output[1:0] VAR27,
input[1:0] VAR55,
input VAR46,
output VAR30,
output[7:0] VAR31,
input VAR6,
output VAR15,
input[7:0] VAR21,
input[15:1] VAR77,
input[15:1] VAR26,
input[15:1] VAR64,
output VAR54,
output[10:0] VAR42,
input VAR2,
input VAR85,
input VAR80,
input[6:0] VAR58,
input VAR53,
input[7:0] VAR59,
output reg[2:0] VAR66
);
wire VAR57;
wire VAR71;
wire VAR78;
wire[3:0] VAR72;
wire VAR44;
wire VAR43;
wire VAR83;
wire VAR84;
wire VAR17;
wire VAR88;
wire VAR51;
wire VAR29;
wire VAR86;
wire VAR50;
wire VAR52;
wire VAR63;
wire VAR22;
wire VAR41;
wire VAR28;
wire VAR23;
wire VAR4;
wire VAR75;
wire VAR12;
wire VAR70;
wire[15:0] VAR35;
reg[6:0] VAR9;
reg[7:0] VAR1;
localparam VAR73=3'd0,
VAR32=3'd1,
VAR11=3'd2,
VAR81=3'd3,
VAR7=3'd4,
VAR68=3'd5,
VAR19=3'd6,
VAR38=3'd7;
VAR39
VAR18 (
.clk(VAR40),
.VAR45(VAR45),
.VAR24(VAR24 & !VAR57),
.VAR20(VAR36 ? VAR2 : VAR20),
.VAR74(VAR36 ? ~VAR2 : VAR74),
.VAR14(VAR36 ? VAR2 : VAR14),
.VAR36(VAR36),
.VAR57(VAR57),
.VAR71(VAR71),
.VAR78(VAR78),
.VAR62(VAR9),
.VAR77({VAR77,1'b1}),
.VAR72(VAR72),
.VAR44(VAR44),
.VAR43(VAR43),
.VAR83(VAR83),
.VAR84(VAR84),
.VAR17(VAR17),
.VAR88(VAR88),
.VAR51(VAR51),
.VAR29(VAR29),
.VAR54(VAR54),
.VAR42(VAR42),
.VAR86(VAR86),
.VAR50(VAR50),
.VAR52(VAR52),
.VAR63(VAR63),
.VAR34(VAR2)
);
VAR3
VAR60 (
.clk(VAR40),
.VAR45(VAR45),
.VAR24(VAR24 & !VAR57),
.VAR61(VAR61),
.VAR16(VAR16),
.VAR36(VAR36),
.VAR78(VAR78),
.VAR28(VAR75),
.VAR23(VAR23),
.VAR4(VAR4),
.VAR56(VAR85 & VAR66[2]),
.VAR34(VAR2)
);
VAR82
VAR37 (
.clk(VAR40),
.VAR45(VAR45),
.VAR24(VAR24 & !VAR57),
.VAR72(VAR72),
.VAR44(VAR44),
.VAR43(VAR43),
.VAR83(VAR83),
.VAR84(VAR84),
.VAR17(VAR17),
.VAR88(VAR88),
.VAR51(VAR51),
.VAR29(VAR29),
.VAR4(VAR4),
.VAR36(VAR36),
.VAR75(VAR75),
.VAR12(VAR12),
.VAR70(VAR70),
.VAR22(VAR22),
.VAR41(VAR41),
.VAR55(VAR55),
.VAR27(VAR27),
.VAR33(VAR33),
.VAR79(VAR79),
.VAR26({VAR26,1'b0}),
.VAR64({VAR64,1'b0}),
.VAR35(~VAR77[15:1]),
.VAR66(VAR66)
);
VAR25 #(.VAR47(3'd5),.VAR69(1'd0),.VAR76(2'd3))
VAR87
(
.clk(VAR40),
.VAR45(VAR45),
.VAR24(VAR63 & !VAR57),
.VAR5(VAR50),
.VAR65(VAR52),
.VAR48(VAR46),
.VAR13(VAR31),
.VAR67(VAR86),
.VAR8(VAR30)
);
VAR49 #(.VAR47(3'd4),.VAR69(2'd3),.VAR76(1'd0))
VAR10
(
.clk(VAR40),
.VAR45(VAR45),
.VAR24(!VAR57),
.VAR5(VAR6),
.VAR65(VAR21),
.VAR48( VAR75 & !VAR4 &
VAR70),
.VAR13(VAR41),
.VAR67(VAR15),
.VAR8(VAR22)
);
assign VAR23= VAR70 ? VAR41 :
VAR12;
always @(posedge VAR40, negedge VAR45)
begin
if(!VAR45)
begin
VAR9<=7'd0;
VAR1<=8'd0;
VAR66<=VAR73;
end
else if(!VAR24)
begin
VAR9<=7'd0;
VAR1<=8'd0;
VAR66<=VAR73;
end
else
begin
VAR9<= VAR57 ? 7'd0 :
VAR80 ? VAR58 :
VAR9;
VAR1<= VAR57 ? 8'd0 :
VAR53 ? VAR59 :
VAR1;
case(VAR66)
VAR73:
begin
VAR66<= VAR57 ? VAR32 :
VAR71 ? VAR7 :
VAR66;
end
VAR32:
begin
VAR66<= VAR9!=0 ? VAR11 :
VAR71 ? VAR68 :
VAR66;
end
VAR11:
begin
VAR66<= VAR57 | VAR9==7'd0 ? VAR32 :
VAR1!=0 ? VAR81 :
VAR71 ? VAR19 :
VAR66;
end
VAR81:
begin
VAR66<= VAR57 ? VAR32 :
VAR71 ? VAR38 :
VAR1==8'd0 ? VAR11 :
VAR66;
end
VAR7:
begin
VAR66<= !VAR71 ? VAR73 : VAR66;
end
VAR68:
begin
VAR66<= !VAR71 ? VAR32 : VAR66;
end
VAR19:
begin
VAR66<= !VAR71 ? VAR11 : VAR66;
end
VAR38:
begin
VAR66<= !VAR71 ? VAR81 : VAR66;
end
endcase
end
end
endmodule | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_jid_to_yid_pool.v | 18,290 | module MODULE1 (
VAR32, VAR53, VAR24, VAR28,
VAR41, VAR16, VAR30, VAR45, VAR22, VAR49, VAR21, clk,
VAR14
);
output VAR32; output [3:0] VAR53; input VAR41; input VAR16; input [3:0] VAR30; input VAR45; input [3:0] VAR22; input [3:0] VAR49; output VAR24; input [3:0] VAR21; output VAR28; input clk; input VAR14;
wire VAR20;
wire [3:0] VAR29, VAR36;
wire [15:0] VAR17, VAR44;
wire [15:0] VAR27;
wire [15:0] VAR18;
wire [15:0] VAR4;
wire [15:0] VAR26;
wire [15:0] VAR37;
wire [15:0] VAR3;
wire [15:0] VAR33;
reg VAR24, VAR28;
reg [3:0] VAR53;
VAR5 VAR15 (.din(VAR44[ 0]), .en(VAR27[ 0]), .VAR52(VAR17[ 0]), .VAR14(VAR14), .clk(clk));
VAR5 VAR35 (.din(VAR44[ 1]), .en(VAR27[ 1]), .VAR52(VAR17[ 1]), .VAR14(VAR14), .clk(clk));
VAR5 VAR9 (.din(VAR44[ 2]), .en(VAR27[ 2]), .VAR52(VAR17[ 2]), .VAR14(VAR14), .clk(clk));
VAR5 VAR50 (.din(VAR44[ 3]), .en(VAR27[ 3]), .VAR52(VAR17[ 3]), .VAR14(VAR14), .clk(clk));
VAR5 VAR46 (.din(VAR44[ 4]), .en(VAR27[ 4]), .VAR52(VAR17[ 4]), .VAR14(VAR14), .clk(clk));
VAR5 VAR25 (.din(VAR44[ 5]), .en(VAR27[ 5]), .VAR52(VAR17[ 5]), .VAR14(VAR14), .clk(clk));
VAR5 VAR19 (.din(VAR44[ 6]), .en(VAR27[ 6]), .VAR52(VAR17[ 6]), .VAR14(VAR14), .clk(clk));
VAR5 VAR13 (.din(VAR44[ 7]), .en(VAR27[ 7]), .VAR52(VAR17[ 7]), .VAR14(VAR14), .clk(clk));
VAR5 VAR12 (.din(VAR44[ 8]), .en(VAR27[ 8]), .VAR52(VAR17[ 8]), .VAR14(VAR14), .clk(clk));
VAR5 VAR7 (.din(VAR44[ 9]), .en(VAR27[ 9]), .VAR52(VAR17[ 9]), .VAR14(VAR14), .clk(clk));
VAR5 VAR1 (.din(VAR44[10]), .en(VAR27[10]), .VAR52(VAR17[10]), .VAR14(VAR14), .clk(clk));
VAR5 VAR10 (.din(VAR44[11]), .en(VAR27[11]), .VAR52(VAR17[11]), .VAR14(VAR14), .clk(clk));
VAR5 VAR6 (.din(VAR44[12]), .en(VAR27[12]), .VAR52(VAR17[12]), .VAR14(VAR14), .clk(clk));
VAR5 VAR23 (.din(VAR44[13]), .en(VAR27[13]), .VAR52(VAR17[13]), .VAR14(VAR14), .clk(clk));
VAR5 VAR8 (.din(VAR44[14]), .en(VAR27[14]), .VAR52(VAR17[14]), .VAR14(VAR14), .clk(clk));
VAR5 VAR51 (.din(VAR44[15]), .en(VAR27[15]), .VAR52(VAR17[15]), .VAR14(VAR14), .clk(clk));
assign VAR27[15:0] = (VAR4[15:0] | VAR18[15:0]);
assign VAR44[15:0] = VAR4[15:0];
assign VAR18[ 0] = (VAR16 && (VAR30 == 4'b0000)) || (VAR45 && (VAR22 == 4'b0000));
assign VAR4[ 0] = (VAR41 && (VAR53 == 4'b0000));
assign VAR18[ 1] = (VAR16 && (VAR30 == 4'b0001)) || (VAR45 && (VAR22 == 4'b0001));
assign VAR4[ 1] = (VAR41 && (VAR53 == 4'b0001));
assign VAR18[ 2] = (VAR16 && (VAR30 == 4'b0010)) || (VAR45 && (VAR22 == 4'b0010));
assign VAR4[ 2] = (VAR41 && (VAR53 == 4'b0010));
assign VAR18[ 3] = (VAR16 && (VAR30 == 4'b0011)) || (VAR45 && (VAR22 == 4'b0011));
assign VAR4[ 3] = (VAR41 && (VAR53 == 4'b0011));
assign VAR18[ 4] = (VAR16 && (VAR30 == 4'b0100)) || (VAR45 && (VAR22 == 4'b0100));
assign VAR4[ 4] = (VAR41 && (VAR53 == 4'b0100));
assign VAR18[ 5] = (VAR16 && (VAR30 == 4'b0101)) || (VAR45 && (VAR22 == 4'b0101));
assign VAR4[ 5] = (VAR41 && (VAR53 == 4'b0101));
assign VAR18[ 6] = (VAR16 && (VAR30 == 4'b0110)) || (VAR45 && (VAR22 == 4'b0110));
assign VAR4[ 6] = (VAR41 && (VAR53 == 4'b0110));
assign VAR18[ 7] = (VAR16 && (VAR30 == 4'b0111)) || (VAR45 && (VAR22 == 4'b0111));
assign VAR4[ 7] = (VAR41 && (VAR53 == 4'b0111));
assign VAR18[ 8] = (VAR16 && (VAR30 == 4'b1000)) || (VAR45 && (VAR22 == 4'b1000));
assign VAR4[ 8] = (VAR41 && (VAR53 == 4'b1000));
assign VAR18[ 9] = (VAR16 && (VAR30 == 4'b1001)) || (VAR45 && (VAR22 == 4'b1001));
assign VAR4[ 9] = (VAR41 && (VAR53 == 4'b1001));
assign VAR18[10] = (VAR16 && (VAR30 == 4'b1010)) || (VAR45 && (VAR22 == 4'b1010));
assign VAR4[10] = (VAR41 && (VAR53 == 4'b1010));
assign VAR18[11] = (VAR16 && (VAR30 == 4'b1011)) || (VAR45 && (VAR22 == 4'b1011));
assign VAR4[11] = (VAR41 && (VAR53 == 4'b1011));
assign VAR18[12] = (VAR16 && (VAR30 == 4'b1100)) || (VAR45 && (VAR22 == 4'b1100));
assign VAR4[12] = (VAR41 && (VAR53 == 4'b1100));
assign VAR18[13] = (VAR16 && (VAR30 == 4'b1101)) || (VAR45 && (VAR22 == 4'b1101));
assign VAR4[13] = (VAR41 && (VAR53 == 4'b1101));
assign VAR18[14] = (VAR16 && (VAR30 == 4'b1110)) || (VAR45 && (VAR22 == 4'b1110));
assign VAR4[14] = (VAR41 && (VAR53 == 4'b1110));
assign VAR18[15] = (VAR16 && (VAR30 == 4'b1111)) || (VAR45 && (VAR22 == 4'b1111));
assign VAR4[15] = (VAR41 && (VAR53 == 4'b1111));
always @(VAR49 or VAR17) begin
case (VAR49) 4'd00: VAR24 = VAR17[ 0];
4'd01: VAR24 = VAR17[ 1];
4'd02: VAR24 = VAR17[ 2];
4'd03: VAR24 = VAR17[ 3];
4'd04: VAR24 = VAR17[ 4];
4'd05: VAR24 = VAR17[ 5];
4'd06: VAR24 = VAR17[ 6];
4'd07: VAR24 = VAR17[ 7];
4'd08: VAR24 = VAR17[ 8];
4'd09: VAR24 = VAR17[ 9];
4'd10: VAR24 = VAR17[10];
4'd11: VAR24 = VAR17[11];
4'd12: VAR24 = VAR17[12];
4'd13: VAR24 = VAR17[13];
4'd14: VAR24 = VAR17[14];
4'd15: VAR24 = VAR17[15];
endcase
end
always @(VAR21 or VAR17) begin
case (VAR21) 4'd00: VAR28 = VAR17[ 0];
4'd01: VAR28 = VAR17[ 1];
4'd02: VAR28 = VAR17[ 2];
4'd03: VAR28 = VAR17[ 3];
4'd04: VAR28 = VAR17[ 4];
4'd05: VAR28 = VAR17[ 5];
4'd06: VAR28 = VAR17[ 6];
4'd07: VAR28 = VAR17[ 7];
4'd08: VAR28 = VAR17[ 8];
4'd09: VAR28 = VAR17[ 9];
4'd10: VAR28 = VAR17[10];
4'd11: VAR28 = VAR17[11];
4'd12: VAR28 = VAR17[12];
4'd13: VAR28 = VAR17[13];
4'd14: VAR28 = VAR17[14];
4'd15: VAR28 = VAR17[15];
endcase
end
assign VAR32 = (VAR17 != 16'b1111111111111111);
assign VAR29 = VAR53;
assign VAR20 = VAR41;
VAR5 #(4) VAR42 (.din(VAR29), .en(VAR20), .VAR52(VAR36), .VAR14(VAR14), .clk(clk));
assign VAR26[15:0] = ~VAR17[15:0];
assign VAR37[15:0] =
((VAR36 == 4'd00)? {VAR26[15:0] }: 16'b0) |
((VAR36 == 4'd15)? {VAR26[14:0], VAR26[15] }: 16'b0) |
((VAR36 == 4'd14)? {VAR26[13:0], VAR26[15:14]}: 16'b0) |
((VAR36 == 4'd13)? {VAR26[12:0], VAR26[15:13]}: 16'b0) |
((VAR36 == 4'd12)? {VAR26[11:0], VAR26[15:12]}: 16'b0) |
((VAR36 == 4'd11)? {VAR26[10:0], VAR26[15:11]}: 16'b0) |
((VAR36 == 4'd10)? {VAR26[ 9:0], VAR26[15:10]}: 16'b0) |
((VAR36 == 4'd09)? {VAR26[ 8:0], VAR26[15: 9]}: 16'b0) |
((VAR36 == 4'd08)? {VAR26[ 7:0], VAR26[15: 8]}: 16'b0) |
((VAR36 == 4'd07)? {VAR26[ 6:0], VAR26[15: 7]}: 16'b0) |
((VAR36 == 4'd06)? {VAR26[ 5:0], VAR26[15: 6]}: 16'b0) |
((VAR36 == 4'd05)? {VAR26[ 4:0], VAR26[15: 5]}: 16'b0) |
((VAR36 == 4'd04)? {VAR26[ 3:0], VAR26[15: 4]}: 16'b0) |
((VAR36 == 4'd03)? {VAR26[ 2:0], VAR26[15: 3]}: 16'b0) |
((VAR36 == 4'd02)? {VAR26[ 1:0], VAR26[15: 2]}: 16'b0) |
((VAR36 == 4'd01)? {VAR26[ 0], VAR26[15: 1]}: 16'b0) ;
assign VAR3[15:0] = {
(VAR37[15] ),
(VAR37[14] && !(| VAR37[15] )),
(VAR37[13] && !(| VAR37[15:14])),
(VAR37[12] && !(| VAR37[15:13])),
(VAR37[11] && !(| VAR37[15:12])),
(VAR37[10] && !(| VAR37[15:11])),
(VAR37[ 9] && !(| VAR37[15:10])),
(VAR37[ 8] && !(| VAR37[15: 9])),
(VAR37[ 7] && !(| VAR37[15: 8])),
(VAR37[ 6] && !(| VAR37[15: 7])),
(VAR37[ 5] && !(| VAR37[15: 6])),
(VAR37[ 4] && !(| VAR37[15: 5])),
(VAR37[ 3] && !(| VAR37[15: 4])),
(VAR37[ 2] && !(| VAR37[15: 3])),
(VAR37[ 1] && !(| VAR37[15: 2])),
(VAR37[ 0] && !(| VAR37[15: 1]))
};
assign VAR33[15:0] =
((VAR36 == 4'd00)? { VAR3[15: 0]}: 16'b0) |
((VAR36 == 4'd15)? {VAR3[ 0] , VAR3[15: 1]}: 16'b0) |
((VAR36 == 4'd14)? {VAR3[ 1:0], VAR3[15: 2]}: 16'b0) |
((VAR36 == 4'd13)? {VAR3[ 2:0], VAR3[15: 3]}: 16'b0) |
((VAR36 == 4'd12)? {VAR3[ 3:0], VAR3[15: 4]}: 16'b0) |
((VAR36 == 4'd11)? {VAR3[ 4:0], VAR3[15: 5]}: 16'b0) |
((VAR36 == 4'd10)? {VAR3[ 5:0], VAR3[15: 6]}: 16'b0) |
((VAR36 == 4'd09)? {VAR3[ 6:0], VAR3[15: 7]}: 16'b0) |
((VAR36 == 4'd08)? {VAR3[ 7:0], VAR3[15: 8]}: 16'b0) |
((VAR36 == 4'd07)? {VAR3[ 8:0], VAR3[15: 9]}: 16'b0) |
((VAR36 == 4'd06)? {VAR3[ 9:0], VAR3[15:10]}: 16'b0) |
((VAR36 == 4'd05)? {VAR3[10:0], VAR3[15:11]}: 16'b0) |
((VAR36 == 4'd04)? {VAR3[11:0], VAR3[15:12]}: 16'b0) |
((VAR36 == 4'd03)? {VAR3[12:0], VAR3[15:13]}: 16'b0) |
((VAR36 == 4'd02)? {VAR3[13:0], VAR3[15:14]}: 16'b0) |
((VAR36 == 4'd01)? {VAR3[14:0], VAR3[15 ]}: 16'b0);
always @(VAR33) begin
case (1'b1)
VAR33[15]: VAR53 = 4'd15;
VAR33[14]: VAR53 = 4'd14;
VAR33[13]: VAR53 = 4'd13;
VAR33[12]: VAR53 = 4'd12;
VAR33[11]: VAR53 = 4'd11;
VAR33[10]: VAR53 = 4'd10;
VAR33[ 9]: VAR53 = 4'd09;
VAR33[ 8]: VAR53 = 4'd08;
VAR33[ 7]: VAR53 = 4'd07;
VAR33[ 6]: VAR53 = 4'd06;
VAR33[ 5]: VAR53 = 4'd05;
VAR33[ 4]: VAR53 = 4'd04;
VAR33[ 3]: VAR53 = 4'd03;
VAR33[ 2]: VAR53 = 4'd02;
VAR33[ 1]: VAR53 = 4'd01;
VAR33[ 0]: VAR53 = 4'd00;
default: VAR53 = 4'VAR48;
endcase
end
always @(posedge clk) begin
if (VAR41 && !VAR32) begin
VAR43 ("VAR38", 49, "%VAR40 %VAR11: VAR34 - VAR47 VAR31 VAR2 VAR39!", );
end
end
endmodule | gpl-2.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v | 21,574 | module MODULE1 #
(parameter VAR126 = 3,
parameter VAR31 = 8,
parameter VAR19 = 4,
parameter VAR29 = 128,
parameter VAR41 = 100)
(
VAR86, VAR28, VAR123,
VAR103, VAR99, VAR46,
VAR83, VAR17, VAR81, VAR77, VAR34,
VAR23, VAR24, VAR53,
VAR52, VAR111, VAR72, VAR61,
VAR75, VAR62, VAR109,
clk, rst, VAR125, VAR133, VAR110,
VAR66, VAR9,
VAR134, VAR114, VAR113,
VAR116, VAR32, VAR63, VAR1,
VAR121, VAR89, VAR79, VAR27, VAR119, VAR124, VAR37,
VAR10, VAR117, VAR44, VAR131
);
function integer VAR12 (input integer VAR129); begin
VAR129 = VAR129 - 1;
for (VAR12=1; VAR129>1; VAR12=VAR12+1)
VAR129 = VAR129 >> 1;
end
endfunction
input clk;
input rst;
input VAR125;
reg VAR3;
output VAR86;
assign VAR86 = VAR3;
output [5:0] VAR24;
reg VAR105, VAR36;
output VAR28;
assign VAR28 = VAR36;
input [5:0] VAR133;
input [5:0] VAR110;
input [5:0] VAR66;
input VAR9;
reg VAR22, VAR18;
output VAR123;
assign VAR123 = VAR18;
reg VAR85, VAR112;
output VAR103;
assign VAR103 = VAR112;
reg VAR91, VAR118;
output VAR99;
assign VAR99 = VAR118;
reg VAR73, VAR76, VAR122, VAR100;
output VAR46, VAR83, VAR17, VAR81;
assign VAR46 = VAR73;
assign VAR83 = VAR76;
assign VAR17 = VAR122;
assign VAR81 = VAR100;
reg [8:0] VAR107, VAR82;
reg [5:0] VAR6, VAR43;
output [5:0] VAR77;
assign VAR77 = VAR43;
input [5:0] VAR44;
input [8:0] VAR134;
reg [5:0] VAR40;
reg [VAR31*6-1:0] VAR104, VAR16, VAR57, VAR80;
output [VAR31*6-1:0] VAR34, VAR23;
assign VAR34 = VAR16;
assign VAR23 = VAR80;
input [VAR126:0] VAR114;
wire [VAR31*6-1:0] VAR84 = VAR16 >> VAR114 * 6;
assign VAR24 = VAR84[5:0];
wire [5:0] VAR21 = VAR9 ? VAR24 : VAR133;
wire signed [8:0] VAR39 = VAR43 > VAR21
? -9'VAR101 * ({3'b0, (VAR43 - VAR21)})
: 9'VAR101 * ({3'b0, (VAR21 - VAR43)});
wire signed [8:0] VAR74 = ({3'b0, VAR44}) + VAR39;
reg signed [8:0] VAR67;
reg [5:0] VAR14, VAR13;
always @ begin
VAR95 = VAR66;
VAR55 = VAR110;
VAR7 = 2'd0;
VAR120 = 1'b0;
if (VAR70) begin
VAR95 = VAR121;
VAR55 = VAR1;
end
else if (VAR106) begin
VAR95 = VAR1;
VAR55 = VAR79;
VAR7 = 2'd1;
end
else if (VAR94) begin
VAR95 = VAR79;
VAR55 = VAR89;
VAR7 = 2'd2;
end
else if (VAR27) begin
VAR55 = VAR1;
end
else if (VAR37) begin
VAR95 = VAR79;
VAR7 = 2'd2;
end
else if (VAR119) begin
VAR95 = VAR121;
end
else VAR120 = 1'b1;
VAR30 = VAR59 ? VAR95 : VAR55;
end
output VAR62;
assign VAR62 = VAR53 == 2'd1;
reg VAR51, VAR20;
output VAR109;
assign VAR109 = VAR20;
wire VAR54 = VAR30 > VAR43;
wire VAR78 = VAR30 < VAR43;
reg VAR92, VAR93;
input VAR10;
wire VAR4 = VAR56 || VAR10;
wire VAR65 = VAR108 || VAR124;
localparam VAR88 = VAR29 * 2 > 15 ? VAR29 * 2 : 15;
localparam VAR130 = VAR88 > 31 ? VAR88 : 31;
localparam VAR49 = VAR12(VAR130 + 1);
reg [VAR49-1:0] VAR115, VAR42;
wire VAR87 = |VAR42;
reg VAR96, VAR68;
input VAR117;
input VAR131;
reg VAR102, VAR97;
reg [1:0] VAR45, VAR47;
reg [3:0] VAR8, VAR48;
reg VAR98, VAR58;
always @ begin
VAR105 = VAR36;
VAR57 = VAR80;
VAR15 = VAR33;
VAR135 = VAR64;
VAR51 = VAR20;
VAR69 = VAR11;
VAR132 = VAR59;
VAR90 = VAR50;
VAR73 = 1'b0;
VAR76 = 1'b0;
VAR122 = 1'b0;
VAR100 = 1'b0;
VAR22 = VAR18;
VAR85 = 1'b0;
VAR91 = VAR118;
VAR127 = 1'b0;
VAR96 = VAR68;
VAR26 = 1'b0;
VAR2 = 1'b0;
VAR60 = VAR38;
VAR3 = 1'b0;
VAR104 = VAR16;
VAR8 = VAR48;
VAR35 = 1'b0;
VAR102 = VAR97;
VAR107 = VAR82;
VAR6 = VAR43;
VAR45 = VAR47;
VAR115 = VAR42;
if (rst == 1'b1) begin
VAR105 = 1'b0;
VAR51 = 1'b0;
VAR132 = 1'b0;
VAR90 = 1'b0;
VAR69 = 1'b0;
VAR91 = 1'b0;
VAR22 = 1'b0;
VAR96 = 1'b1;
VAR115 = 5'd0;
VAR8 = 4'd0;
end else
case (VAR48)
4'd0:begin
VAR60 = 1'b0;
VAR107 = {3'b0, VAR44};
VAR6 = VAR21;
VAR15 = 1'b0;
if (VAR9) VAR105 = 1'b1;
if (!VAR125 && ~VAR87) begin
VAR105 = 1'b0;
VAR51 = 1'b0;
VAR35 = 1'b1;
VAR8 = 4'd1;
end
end
4'd1:begin
if (VAR117 && VAR71) begin
if (VAR9) VAR105 = 1'b1;
VAR15 = VAR33 || VAR4;
if (VAR65 && VAR33) begin
VAR22 = 1'b1;
VAR132 = 1'b1;
VAR51 = VAR120;
VAR8 = 4'd3;
end else begin
if (VAR15) VAR122 = 1'b1;
end
else VAR100 = 1'b1;
VAR8 = 4'd2;
end
end
end
4'd2:begin
if (VAR68 && ~VAR87) begin
VAR35 = 1'b1;
VAR8 = 4'd1;
VAR105 = 1'b0;
end
end
4'd3:begin
VAR2 = 1'b1;
VAR135 = |VAR128 ? 2'b01 : 2'b00;
if (~VAR87) begin
if (VAR68) begin
if (VAR92) VAR122 = 1'b1;
end
else if (VAR93) VAR100 = 1'b1;
end
else if (~VAR87) begin
VAR105 = 1'b0;
VAR8 = 4'd4;
VAR91 = 1'b1;
end
end end
end
4'd4:
if (~VAR87) begin
if (VAR113) begin
VAR69 = 1'b0;
if (VAR59) begin
VAR132 = 1'b0;
VAR90 = 1'b1;
VAR91 = 1'b0;
VAR8 = 4'd3;
end else if (VAR50) begin
VAR90 = 1'b0;
VAR8 = 4'd5;
end else if (~VAR116) begin
VAR8 = 4'd6;
VAR91 = 1'b0;
end else begin
if (VAR64 != VAR128 && VAR11) begin
VAR135 = VAR64 + 2'b01;
VAR8 = 4'd5;
end else begin
VAR91 = 1'b0;
VAR60 = VAR32;
VAR8 = 4'd8;
end
end end else VAR69 = 1'b1;
end
4'd5:
VAR8 = 4'd4;
4'd6:
if (~VAR87) begin
VAR100 = 1'b1;
VAR8 = 4'd7;
end
4'd7: begin
VAR127 = 1'b1; if (VAR68) begin
VAR8 = 4'd4;
VAR91 = 1'b1;
end
end
4'd8: begin
VAR26 = 1'b1;
if (VAR42 == 5'd1) begin
if (~VAR38) begin
VAR85 = 1'b1;
VAR22 = 1'b0;
end
end
if (~VAR87) begin
if (VAR131)
if (VAR38) begin
VAR122 = 1'b1;
VAR60 = 1'b0;
end
else if (~VAR25 && ~VAR5) begin
if (VAR9) VAR57[VAR114*6+:6] = VAR43;
end
else VAR104[VAR114*6+:6] = VAR43;
VAR8 = 4'd0;
VAR3 = 1'b1;
end else begin
VAR73 = VAR25;
VAR76 = VAR5;
end
end end
endcase
if (VAR122) begin
VAR6 = VAR43 + 6'h1;
VAR102 = 1'b0;
end
if (VAR100) begin
VAR6 = VAR43 - 6'h1;
VAR102 = 1'b1;
end
if (VAR122 || VAR100) begin
VAR96 = 1'b0;
VAR45 = 2'b00;
end
if (~VAR68)
if (VAR131)
if (VAR47 == 2'b10 || VAR127 || VAR2 || VAR26) VAR96 = 1'b1;
end
else begin
VAR45 = VAR47 + 2'b1;
if (VAR97) begin
VAR107 = VAR82 + 9'b1;
if (VAR82 >= 9'd0 && VAR82 < 9'd63) VAR73 = 1'b1;
end else begin
VAR107 = VAR82 - 9'b1;
if (VAR82 > 9'd0 && VAR82 <= 9'd63) VAR76 = 1'b1;
end
end
if (VAR132 && ~VAR59) VAR115 = 'b1;
end
else if (VAR91 && ~VAR118)
VAR115 = VAR88[VAR49-1:0];
end
else if (~VAR91 && VAR118) VAR115 = 'd15;
end
else if (VAR105 & ~VAR36 ||
VAR9 & VAR125 ||
VAR38 & VAR122) VAR115 = 'd31;
end
else if (|VAR42) VAR115 = VAR42 - 'd1;
end
endmodule | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/FIFO_image_filter_mask_data_stream_0_V.v | 3,013 | module MODULE1 (
clk,
VAR18,
VAR7,
VAR1,
VAR4);
parameter VAR6 = 32'd8;
parameter VAR16 = 32'd1;
parameter VAR25 = 32'd2;
input clk;
input [VAR6-1:0] VAR18;
input VAR7;
input [VAR16-1:0] VAR1;
output [VAR6-1:0] VAR4;
reg[VAR6-1:0] VAR17 [0:VAR25-1];
integer VAR13;
always @ (posedge clk)
begin
if (VAR7)
begin
for (VAR13=0;VAR13<VAR25-1;VAR13=VAR13+1)
VAR17[VAR13+1] <= VAR17[VAR13];
VAR17[0] <= VAR18;
end
end
assign VAR4 = VAR17[VAR1];
endmodule
module MODULE2 (
clk,
reset,
VAR19,
VAR23,
VAR2,
VAR12,
VAR21,
VAR22,
VAR3,
VAR27);
parameter VAR10 = "VAR14";
parameter VAR6 = 32'd8;
parameter VAR16 = 32'd1;
parameter VAR25 = 32'd2;
input clk;
input reset;
output VAR19;
input VAR23;
input VAR2;
output[VAR6 - 1:0] VAR12;
output VAR21;
input VAR22;
input VAR3;
input[VAR6 - 1:0] VAR27;
wire[VAR16 - 1:0] VAR15 ;
wire[VAR6 - 1:0] VAR5, VAR24;
reg[VAR16:0] VAR8 = {(VAR16+1){1'b1}};
reg VAR20 = 0, VAR26 = 1;
assign VAR19 = VAR20;
assign VAR21 = VAR26;
assign VAR5 = VAR27;
assign VAR12 = VAR24;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR8 <= ~{VAR16+1{1'b0}};
VAR20 <= 1'b0;
VAR26 <= 1'b1;
end
else begin
if (((VAR2 & VAR23) == 1 & VAR20 == 1) &&
((VAR3 & VAR22) == 0 | VAR26 == 0))
begin
VAR8 <= VAR8 -1;
if (VAR8 == 0)
VAR20 <= 1'b0;
VAR26 <= 1'b1;
end
else if (((VAR2 & VAR23) == 0 | VAR20 == 0) &&
((VAR3 & VAR22) == 1 & VAR26 == 1))
begin
VAR8 <= VAR8 +1;
VAR20 <= 1'b1;
if (VAR8 == VAR25-2)
VAR26 <= 1'b0;
end
end
end
assign VAR15 = VAR8[VAR16] == 1'b0 ? VAR8[VAR16-1:0]:{VAR16{1'b0}};
assign VAR9 = (VAR3 & VAR22) & VAR26;
MODULE1
.VAR6(VAR6),
.VAR16(VAR16),
.VAR25(VAR25))
VAR11 (
.clk(clk),
.VAR18(VAR5),
.VAR7(VAR9),
.VAR1(VAR15),
.VAR4(VAR24));
endmodule | gpl-3.0 |