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SymbiFlow/fpga-tool-perf | src/ibex/top_artya7.v | 3,573 | module MODULE1 (
VAR12,
VAR74,
VAR26
);
input VAR12;
input VAR74;
output [3:0] VAR26;
parameter signed [31:0] VAR33 = 65536;
parameter [31:0] VAR1 = 32'h00000000;
parameter [31:0] VAR42 = (VAR33 - 1);
wire VAR43;
wire VAR17;
wire VAR25;
reg VAR9;
wire VAR32;
wire [31:0] VAR55;
wire [31:0] VAR34;
wire VAR75;
reg VAR4;
reg VAR52;
wire VAR20;
wire [3:0] VAR38;
wire [31:0] VAR65;
wire [31:0] VAR19;
wire [31:0] VAR18;
reg [31:0] VAR41;
reg VAR58;
reg VAR67;
reg [3:0] VAR50;
reg [31:0] VAR2;
wire VAR22;
wire [31:0] VAR5;
VAR61 #(
.VAR49(32'h00000000),
.VAR53(32'h00000000)
) VAR64(
.VAR66(VAR43),
.VAR7(VAR17),
.VAR30('b0),
.VAR13(32'b0),
.VAR62(32'h00000000),
.VAR51(VAR25),
.VAR16(VAR9),
.VAR35(VAR32),
.VAR11(VAR55),
.VAR73(VAR34),
.VAR3('b0),
.VAR23(VAR75),
.VAR27(VAR4),
.VAR8(VAR52),
.VAR57(VAR20),
.VAR63(VAR38),
.VAR56(VAR65),
.VAR10(VAR19),
.VAR15(VAR18),
.VAR28('b0),
.VAR54(1'b0),
.VAR69(1'b0),
.VAR72(1'b0),
.VAR47(15'b0),
.VAR59(1'b0),
.VAR21('b0),
.VAR6('b1),
.VAR31()
);
always @(*) begin
VAR58 = 1'b0;
VAR41 = 32'b0;
VAR67 = 1'b0;
VAR50 = 4'b0;
VAR2 = 32'b0;
if (VAR25) begin
VAR58 = ((VAR55 & ~VAR42) == VAR1);
VAR41 = VAR55;
end
else if (VAR75) begin
VAR58 = ((VAR65 & ~VAR42) == VAR1);
VAR67 = VAR20;
VAR50 = VAR38;
VAR41 = VAR65;
VAR2 = VAR19;
end
end
VAR44 #(.VAR68((VAR33 / 4))) VAR60(
.VAR66(VAR43),
.VAR7(VAR17),
.VAR37(VAR58),
.VAR70(VAR67),
.VAR36(VAR50),
.VAR24(VAR41),
.VAR39(VAR2),
.VAR45(VAR22),
.VAR71(VAR5)
);
assign VAR34 = VAR5;
assign VAR18 = VAR5;
assign VAR32 = VAR22;
always @(posedge VAR43 or negedge VAR17)
if (!VAR17) begin
VAR9 <= 'b0;
VAR4 <= 'b0;
VAR52 <= 'b0;
end
else begin
VAR9 <= (VAR25 && VAR58);
VAR4 <= ((~VAR25 && VAR75) && VAR58);
VAR52 <= ((~VAR25 && VAR75) && VAR58);
end
reg [3:0] VAR46;
always @(posedge VAR43 or negedge VAR17)
if (!VAR17)
VAR46 <= 4'b0;
else if (((VAR58 && VAR75) && VAR20)) begin : VAR14
reg signed [31:0] VAR40;
for (VAR40 = 0; (VAR40 < 4); VAR40 = (VAR40 + 1))
if ((VAR38[VAR40] == 1'b1))
VAR46 <= VAR19[(VAR40 * 8)+:4];
end
assign VAR26 = VAR46;
VAR48 VAR29(
.VAR12(VAR12),
.VAR74(VAR74),
.VAR43(VAR43),
.VAR17(VAR17)
);
endmodule | isc |
hhuang25/uwaterloo_ece224 | Lab1/seven_seg_right_pio.v | 2,194 | module MODULE1 (
address,
VAR6,
clk,
VAR2,
VAR3,
VAR7,
VAR9,
VAR1
)
;
output [ 31: 0] VAR9;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR6;
input clk;
input VAR2;
input VAR3;
input [ 31: 0] VAR7;
wire VAR8;
reg [ 31: 0] VAR4;
wire [ 31: 0] VAR9;
wire [ 31: 0] VAR5;
wire [ 31: 0] VAR1;
assign VAR8 = 1;
assign VAR5 = {32 {(address == 0)}} & VAR4;
always @(posedge clk or negedge VAR2)
begin
if (VAR2 == 0)
VAR4 <= 0;
end
else if (VAR6 && ~VAR3 && (address == 0))
VAR4 <= VAR7[31 : 0];
end
assign VAR1 = VAR5;
assign VAR9 = VAR4;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd/sky130_fd_sc_ls__tapvgnd_1.v | 1,938 | module MODULE1 (
VAR4,
VAR1,
VAR3 ,
VAR2
);
input VAR4;
input VAR1;
input VAR3 ;
input VAR2 ;
VAR6 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
VAR6 VAR5 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/conb/sky130_fd_sc_ms__conb.functional.v | 1,183 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
output VAR2;
pullup VAR4 (VAR1 );
pulldown VAR3 (VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221oi/sky130_fd_sc_ms__a221oi.symbol.v | 1,402 | module MODULE1 (
input VAR2,
input VAR9,
input VAR3,
input VAR5,
input VAR6,
output VAR4
);
supply1 VAR7;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.functional.pp.v | 1,702 | module MODULE1( VAR5, VAR3, VAR22, VAR1, VAR11, VAR15, VAR7, VAR13 );
input VAR11, VAR15, VAR1, VAR22, VAR3;
inout VAR7, VAR13;
output VAR5;
wire VAR14;
not VAR10( VAR14, VAR11 );
wire VAR16;
not VAR4( VAR16, VAR15 );
wire VAR20;
and VAR19( VAR20, VAR14, VAR16 );
wire VAR8;
not VAR2( VAR8, VAR1 );
wire VAR21;
not VAR23( VAR21, VAR22 );
wire VAR6;
and VAR18( VAR6, VAR8, VAR21 );
wire VAR9;
not VAR12( VAR9, VAR3 );
or VAR17( VAR5, VAR20, VAR6, VAR9 );
endmodule | apache-2.0 |
YosysHQ/yosys | techlibs/anlogic/brams_map.v | 12,152 | module MODULE3 (...);
parameter VAR129 = 0;
parameter VAR166 = "VAR72";
parameter VAR80 = 9;
parameter VAR81 = 1;
parameter VAR2 = "VAR216";
input VAR61;
input VAR219;
input VAR43;
input VAR14;
input VAR188;
input [12:0] VAR20;
input [VAR80-1:0] VAR132;
output [VAR80-1:0] VAR214;
parameter VAR124 = 9;
parameter VAR156 = 1;
parameter VAR170 = "VAR216";
input VAR171;
input VAR206;
input VAR162;
input VAR224;
input VAR126;
input [12:0] VAR180;
input [VAR124-1:0] VAR5;
output [VAR124-1:0] VAR203;
function [255:0] VAR60;
input integer VAR181;
integer VAR27;
for (VAR27 = 0; VAR27 < 32; VAR27 = VAR27 + 1) begin
VAR60[VAR27*8+:8] = VAR129[(VAR181 * 32 + VAR27) * 9 +: 8];
end
endfunction
function [255:0] VAR30;
input integer VAR181;
integer VAR27;
for (VAR27 = 0; VAR27 < 256; VAR27 = VAR27 + 1) begin
VAR30[VAR27] = VAR129[(VAR181 * 256 + VAR27) * 9 + 8];
end
endfunction
wire [8:0] VAR176;
wire [8:0] VAR35;
wire [8:0] VAR167 = {9{VAR132}};
wire [8:0] VAR82 = {9{VAR5}};
assign VAR214 = VAR176;
assign VAR203 = VAR35;
VAR11 #(
.VAR155(VAR60('h00)),
.VAR233(VAR60('h01)),
.VAR9(VAR60('h02)),
.VAR212(VAR60('h03)),
.VAR28(VAR60('h04)),
.VAR55(VAR60('h05)),
.VAR90(VAR60('h06)),
.VAR63(VAR60('h07)),
.VAR102(VAR60('h08)),
.VAR127(VAR60('h09)),
.VAR144(VAR60('h0a)),
.VAR92(VAR60('h0b)),
.VAR69(VAR60('h0c)),
.VAR37(VAR60('h0d)),
.VAR190(VAR60('h0e)),
.VAR15(VAR60('h0f)),
.VAR217(VAR60('h10)),
.VAR29(VAR60('h11)),
.VAR6(VAR60('h12)),
.VAR66(VAR60('h13)),
.VAR23(VAR60('h14)),
.VAR160(VAR60('h15)),
.VAR77(VAR60('h16)),
.VAR70(VAR60('h17)),
.VAR152(VAR60('h18)),
.VAR230(VAR60('h19)),
.VAR209(VAR60('h1a)),
.VAR232(VAR60('h1b)),
.VAR31(VAR60('h1c)),
.VAR96(VAR60('h1d)),
.VAR34(VAR60('h1e)),
.VAR165(VAR60('h1f)),
.VAR83(VAR30('h00)),
.VAR119(VAR30('h01)),
.VAR18(VAR30('h02)),
.VAR13(VAR30('h03)),
.VAR25("VAR17"),
.VAR107(VAR174("%VAR117", VAR80)),
.VAR3(VAR174("%VAR117", VAR124)),
.VAR101("VAR62"),
.VAR133("VAR62"),
.VAR213(VAR166),
.VAR49(VAR166),
.VAR67(VAR81 ? "VAR22" : "VAR151"),
.VAR184(VAR156 ? "VAR22" : "VAR151"),
.VAR139(VAR2),
.VAR191(VAR170),
) VAR163 (
.VAR78(VAR61),
.VAR137(VAR43),
.VAR41(VAR219),
.VAR64(1'b1),
.VAR88(VAR166 == "VAR72" ? VAR14 : VAR188),
.VAR106(3'b111),
.VAR228(VAR80 == 9 ? {VAR20[12:1], 1'b1} : VAR20),
.VAR44(VAR167),
.VAR215(VAR176),
.VAR24(VAR171),
.VAR73(VAR162),
.VAR122(VAR206),
.VAR157(1'b1),
.VAR51(VAR166 == "VAR72" ? VAR224 : VAR126),
.VAR79(3'b111),
.VAR58(VAR124 == 9 ? {VAR180[12:1], 1'b1} : VAR180),
.VAR221(VAR82),
.VAR8(VAR35),
);
endmodule
module MODULE1 (...);
parameter VAR129 = 0;
parameter VAR166 = "VAR72";
parameter VAR189 = 18;
parameter VAR56 = 1;
input VAR199;
input VAR211;
input VAR94;
input VAR120;
input [12:0] VAR45;
output [VAR189-1:0] VAR175;
parameter VAR145 = 18;
parameter VAR131 = 2;
parameter VAR40 = 1;
input VAR110;
input VAR197;
input [12:0] VAR98;
input [VAR131-1:0] VAR16;
input [VAR145-1:0] VAR223;
function [255:0] VAR60;
input integer VAR181;
integer VAR27;
for (VAR27 = 0; VAR27 < 32; VAR27 = VAR27 + 1) begin
VAR60[VAR27*8+:8] = VAR129[(VAR181 * 32 + VAR27) * 9 +: 8];
end
endfunction
function [255:0] VAR30;
input integer VAR181;
integer VAR27;
for (VAR27 = 0; VAR27 < 256; VAR27 = VAR27 + 1) begin
VAR30[VAR27] = VAR129[(VAR181 * 256 + VAR27) * 9 + 8];
end
endfunction
wire [17:0] VAR202 = {18{VAR223}};
wire [17:0] VAR91;
assign VAR175 = VAR189 == 18 ? VAR91 : VAR91[17:9];
VAR11 #(
.VAR155(VAR60('h00)),
.VAR233(VAR60('h01)),
.VAR9(VAR60('h02)),
.VAR212(VAR60('h03)),
.VAR28(VAR60('h04)),
.VAR55(VAR60('h05)),
.VAR90(VAR60('h06)),
.VAR63(VAR60('h07)),
.VAR102(VAR60('h08)),
.VAR127(VAR60('h09)),
.VAR144(VAR60('h0a)),
.VAR92(VAR60('h0b)),
.VAR69(VAR60('h0c)),
.VAR37(VAR60('h0d)),
.VAR190(VAR60('h0e)),
.VAR15(VAR60('h0f)),
.VAR217(VAR60('h10)),
.VAR29(VAR60('h11)),
.VAR6(VAR60('h12)),
.VAR66(VAR60('h13)),
.VAR23(VAR60('h14)),
.VAR160(VAR60('h15)),
.VAR77(VAR60('h16)),
.VAR70(VAR60('h17)),
.VAR152(VAR60('h18)),
.VAR230(VAR60('h19)),
.VAR209(VAR60('h1a)),
.VAR232(VAR60('h1b)),
.VAR31(VAR60('h1c)),
.VAR96(VAR60('h1d)),
.VAR34(VAR60('h1e)),
.VAR165(VAR60('h1f)),
.VAR83(VAR30('h00)),
.VAR119(VAR30('h01)),
.VAR18(VAR30('h02)),
.VAR13(VAR30('h03)),
.VAR25("VAR89"),
.VAR107(VAR174("%VAR117", VAR145)),
.VAR3(VAR174("%VAR117", VAR189)),
.VAR101("VAR62"),
.VAR133("VAR62"),
.VAR213(VAR166),
.VAR49(VAR166),
.VAR67(VAR40 ? "VAR22" : "VAR151"),
.VAR184(VAR56 ? "VAR22" : "VAR151"),
) VAR163 (
.VAR78(VAR110),
.VAR137(VAR145 >= 9 ? 1'b1 : VAR16[0]),
.VAR41(VAR197),
.VAR64(1'b1),
.VAR88(1'b0),
.VAR106(3'b111),
.VAR228(VAR145 == 18 ? {VAR98[12:2], VAR16[1:0]} : (VAR145 == 9 ? {VAR98[12:1], VAR16[0]} : VAR98)),
.VAR44(VAR202[8:0]),
.VAR215(VAR91[8:0]),
.VAR24(VAR199),
.VAR73(1'b0),
.VAR122(VAR211),
.VAR157(1'b1),
.VAR51(VAR166 == "VAR72" ? VAR94 : VAR120),
.VAR79(3'b111),
.VAR58(VAR45),
.VAR221(VAR202[17:9]),
.VAR8(VAR91[17:9]),
);
endmodule
module MODULE2 (...);
parameter VAR129 = 0;
parameter VAR80 = 16;
parameter VAR86 = 2;
parameter VAR81 = 1;
parameter VAR2 = "VAR216";
input VAR61;
input VAR219;
input [VAR86-1:0] VAR43;
input [11:0] VAR20;
input [VAR80-1:0] VAR132;
output [VAR80-1:0] VAR214;
parameter VAR124 = 16;
parameter VAR227 = 2;
parameter VAR156 = 1;
parameter VAR170 = "VAR216";
input VAR171;
input VAR206;
input [VAR227-1:0] VAR162;
input [11:0] VAR180;
input [VAR124-1:0] VAR5;
output [VAR124-1:0] VAR203;
function [255:0] VAR60;
input integer VAR181;
VAR60 = VAR129[256 * VAR181 +: 256];
endfunction
wire [15:0] VAR176;
wire [15:0] VAR35;
wire [15:0] VAR167 = VAR132;
wire [15:0] VAR82 = VAR5;
assign VAR214 = VAR176;
assign VAR203 = VAR35;
wire VAR187, VAR153;
wire VAR4, VAR195;
generate
if (VAR80 == 8) begin
assign VAR187 = VAR20[0];
assign VAR153 = 1;
end else begin
assign VAR187 = VAR43 == 2;
assign VAR153 = ^VAR43;
end
if (VAR124 == 8) begin
assign VAR4 = VAR180[0];
assign VAR195 = 1;
end else begin
assign VAR4 = VAR162 == 2;
assign VAR195 = ^VAR162;
end
endgenerate
VAR76 #(
.VAR155(VAR60('h00)),
.VAR233(VAR60('h01)),
.VAR9(VAR60('h02)),
.VAR212(VAR60('h03)),
.VAR28(VAR60('h04)),
.VAR55(VAR60('h05)),
.VAR90(VAR60('h06)),
.VAR63(VAR60('h07)),
.VAR102(VAR60('h08)),
.VAR127(VAR60('h09)),
.VAR144(VAR60('h0a)),
.VAR92(VAR60('h0b)),
.VAR69(VAR60('h0c)),
.VAR37(VAR60('h0d)),
.VAR190(VAR60('h0e)),
.VAR15(VAR60('h0f)),
.VAR217(VAR60('h10)),
.VAR29(VAR60('h11)),
.VAR6(VAR60('h12)),
.VAR66(VAR60('h13)),
.VAR23(VAR60('h14)),
.VAR160(VAR60('h15)),
.VAR77(VAR60('h16)),
.VAR70(VAR60('h17)),
.VAR152(VAR60('h18)),
.VAR230(VAR60('h19)),
.VAR209(VAR60('h1a)),
.VAR232(VAR60('h1b)),
.VAR31(VAR60('h1c)),
.VAR96(VAR60('h1d)),
.VAR34(VAR60('h1e)),
.VAR165(VAR60('h1f)),
.VAR148(VAR60('h20)),
.VAR103(VAR60('h21)),
.VAR32(VAR60('h22)),
.VAR146(VAR60('h23)),
.VAR138(VAR60('h24)),
.VAR200(VAR60('h25)),
.VAR105(VAR60('h26)),
.VAR198(VAR60('h27)),
.VAR218(VAR60('h28)),
.VAR21(VAR60('h29)),
.VAR39(VAR60('h2a)),
.VAR10(VAR60('h2b)),
.VAR177(VAR60('h2c)),
.VAR36(VAR60('h2d)),
.VAR12(VAR60('h2e)),
.VAR75(VAR60('h2f)),
.VAR38(VAR60('h30)),
.VAR140(VAR60('h31)),
.VAR204(VAR60('h32)),
.VAR104(VAR60('h33)),
.VAR53(VAR60('h34)),
.VAR33(VAR60('h35)),
.VAR108(VAR60('h36)),
.VAR136(VAR60('h37)),
.VAR226(VAR60('h38)),
.VAR47(VAR60('h39)),
.VAR179(VAR60('h3a)),
.VAR54(VAR60('h3b)),
.VAR125(VAR60('h3c)),
.VAR186(VAR60('h3d)),
.VAR97(VAR60('h3e)),
.VAR229(VAR60('h3f)),
.VAR172(VAR60('h40)),
.VAR68(VAR60('h41)),
.VAR84(VAR60('h42)),
.VAR48(VAR60('h43)),
.VAR168(VAR60('h44)),
.VAR52(VAR60('h45)),
.VAR182(VAR60('h46)),
.VAR161(VAR60('h47)),
.VAR149(VAR60('h48)),
.VAR158(VAR60('h49)),
.VAR123(VAR60('h4a)),
.VAR222(VAR60('h4b)),
.VAR150(VAR60('h4c)),
.VAR183(VAR60('h4d)),
.VAR99(VAR60('h4e)),
.VAR74(VAR60('h4f)),
.VAR225(VAR60('h50)),
.VAR50(VAR60('h51)),
.VAR185(VAR60('h52)),
.VAR118(VAR60('h53)),
.VAR109(VAR60('h54)),
.VAR201(VAR60('h55)),
.VAR205(VAR60('h56)),
.VAR135(VAR60('h57)),
.VAR234(VAR60('h58)),
.VAR208(VAR60('h59)),
.VAR142(VAR60('h5a)),
.VAR114(VAR60('h5b)),
.VAR87(VAR60('h5c)),
.VAR7(VAR60('h5d)),
.VAR113(VAR60('h5e)),
.VAR115(VAR60('h5f)),
.VAR116(VAR60('h60)),
.VAR178(VAR60('h61)),
.VAR57(VAR60('h62)),
.VAR65(VAR60('h63)),
.VAR194(VAR60('h64)),
.VAR71(VAR60('h65)),
.VAR111(VAR60('h66)),
.VAR210(VAR60('h67)),
.VAR93(VAR60('h68)),
.VAR1(VAR60('h69)),
.VAR134(VAR60('h6a)),
.VAR46(VAR60('h6b)),
.VAR192(VAR60('h6c)),
.VAR19(VAR60('h6d)),
.VAR85(VAR60('h6e)),
.VAR143(VAR60('h6f)),
.VAR26(VAR60('h70)),
.VAR164(VAR60('h71)),
.VAR159(VAR60('h72)),
.VAR147(VAR60('h73)),
.VAR130(VAR60('h74)),
.VAR193(VAR60('h75)),
.VAR59(VAR60('h76)),
.VAR141(VAR60('h77)),
.VAR154(VAR60('h78)),
.VAR42(VAR60('h79)),
.VAR196(VAR60('h7a)),
.VAR207(VAR60('h7b)),
.VAR220(VAR60('h7c)),
.VAR100(VAR60('h7d)),
.VAR95(VAR60('h7e)),
.VAR121(VAR60('h7f)),
.VAR25("VAR169"),
.VAR107(VAR174("%VAR117", VAR80)),
.VAR3(VAR174("%VAR117", VAR124)),
.VAR101("VAR62"),
.VAR133("VAR62"),
.VAR139(VAR2),
.VAR191(VAR170),
.VAR67(VAR81 ? "VAR22" : "VAR151"),
.VAR184(VAR156 ? "VAR22" : "VAR151"),
) VAR163 (
.VAR78(VAR61),
.VAR106(VAR219),
.VAR137(|VAR43),
.VAR64(1'b1),
.VAR88(1'b0),
.VAR228(VAR20[11:1]),
.VAR112(VAR187),
.VAR173(VAR153),
.VAR44(VAR167),
.VAR215(VAR176),
.VAR24(VAR171),
.VAR79(VAR206),
.VAR73(|VAR162),
.VAR64(1'b1),
.VAR88(1'b0),
.VAR58(VAR180[11:1]),
.VAR231(VAR4),
.VAR128(VAR195),
.VAR221(VAR82),
.VAR8(VAR35),
);
endmodule | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3/sky130_fd_sc_hd__and3.pp.symbol.v | 1,280 | module MODULE1 (
input VAR6 ,
input VAR8 ,
input VAR3 ,
output VAR5 ,
input VAR1 ,
input VAR2,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
ViniciusLambardozzi/quanta | Hardware/quanta/db/pll128_altpll.v | 4,091 | module MODULE1
(
clk,
VAR35,
VAR13) ;
output [4:0] clk;
input [1:0] VAR35;
output VAR13;
tri0 [1:0] VAR35;
wire [4:0] VAR12;
wire VAR16;
wire VAR41;
VAR3 VAR18
(
.VAR38(),
.clk(VAR12),
.VAR8(),
.VAR24(VAR16),
.VAR5(VAR16),
.VAR35(VAR35),
.VAR13(VAR41),
.VAR9(),
.VAR37(),
.VAR6(),
.VAR25(),
.VAR30()
,
.VAR33(1'b0),
.VAR14(1'b0),
.VAR11(1'b0),
.VAR27(1'b1),
.VAR17({3{1'b0}}),
.VAR40(1'b0),
.VAR7(1'b0),
.VAR20(1'b0),
.VAR21(1'b1),
.VAR28(1'b0)
);
VAR18.VAR26 = "VAR10",
VAR18.VAR36 = 5,
VAR18.VAR1 = 50,
VAR18.VAR29 = 12,
VAR18.VAR22 = "0",
VAR18.VAR39 = "VAR32",
VAR18.VAR15 = 20000,
VAR18.VAR31 = "VAR34",
VAR18.VAR2 = "VAR10",
VAR18.VAR19 = "VAR4",
VAR18.VAR23 = "VAR3";
assign
clk = {VAR12[4:0]},
VAR13 = VAR41;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn.symbol.v | 1,333 | module MODULE1 (
input VAR5 ,
output VAR4 ,
input VAR1
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
titorgalaxy/Titor | rtl/verilog/ps2/PS2Wrapper.v | 3,450 | module MODULE1(
dout,
din,
address,
VAR4,
VAR17,
enable,
interrupt,
VAR6,
VAR1,
reset,
clk
);
output reg [VAR7-1:0] dout;
input wire [VAR7-1:0] din;
input wire [VAR7-1:0] address;
input wire [VAR24-1:0] VAR4;
input wire VAR17;
input wire enable;
output reg interrupt;
inout VAR6;
inout VAR1;
wire [VAR10-1:0] VAR22;
input reset;
input clk;
reg [VAR7-1:0] VAR3;
wire VAR9;
always @(posedge clk) begin
if(reset) begin
dout <= 0;
end
else if((address==0) && (enable==VAR2) && (VAR17==VAR11)) begin
dout <= VAR3;
end
end
localparam VAR8 = 0;
localparam VAR13 = 224;
localparam VAR15 = 255;
localparam VAR20 = 240;
reg VAR12;
reg [VAR7-1:0] VAR5;
reg VAR18;
reg [VAR7-1:0] VAR23;
reg VAR16;
reg VAR14;
always @(posedge clk) begin
if(reset) begin
VAR12 <= 0;
VAR5 <= VAR8;
VAR18 <= 0;
end
else begin
if(!VAR9) begin
VAR12 <= VAR12;
VAR5 <= VAR5;
VAR18 <= VAR18;
end
else begin
case(VAR22)
VAR13: begin
VAR12 <= VAR12;
VAR5 <= VAR13;
VAR18 <= 0;
end
VAR15: begin
VAR12 <= VAR12;
VAR5 <= VAR15;
VAR18 <= 0;
end
VAR20: begin
VAR12 <= VAR12;
VAR5 <= VAR5;
VAR18 <= 1;
end
default: begin
VAR12 <= VAR14;
VAR5 <= VAR8;
VAR18 <= 0;
end
endcase
end
end
end
always @(*) begin
if(!VAR9) begin
VAR23 <= 0;
VAR16 <= 0;
VAR14 <= 0;
end
else begin
end
end
always @(posedge clk) begin
if(reset) begin
interrupt <= 0;
VAR3 <= 0;
end
else if(VAR16) begin
interrupt <= !VAR12;
VAR3 <= (VAR18<<(VAR7-1)) | VAR23;
end
else begin
interrupt <= 0;
VAR3 <= VAR3;
end
end
VAR21 VAR19(
.VAR6(VAR6),
.VAR1(VAR1),
.VAR22(VAR22),
.VAR9(VAR9),
.reset(reset),
.clk(clk)
);
endmodule | gpl-3.0 |
jakubfi/mera400f | src/pp.v | 5,784 | module MODULE1(
input VAR4,
input VAR72,
input VAR11,
input VAR8,
input VAR69,
input VAR37,
input VAR91,
input VAR43,
input VAR35,
input VAR24,
input VAR46,
input VAR74,
input VAR28,
input VAR62,
output VAR52,
output irq,
input VAR21,
input VAR75,
input VAR59,
input VAR1,
input VAR88,
input VAR92,
input VAR27,
input VAR23,
input VAR42,
input VAR54,
input VAR79,
input VAR53,
input VAR45,
input VAR2,
input VAR34,
input VAR36,
input VAR78,
input [0:15] VAR47,
output [0:15] VAR87,
output [0:9] VAR51,
input [0:15] VAR14,
output VAR76,
output [0:15] VAR41
);
wire VAR21 = VAR21 | (VAR75 & VAR27);
wire VAR29 = VAR59 & VAR72;
VAR13 VAR58(
.VAR4(VAR4),
.VAR21(VAR21),
.VAR29(VAR29),
.VAR6(VAR6),
.VAR47(VAR47),
.VAR51(VAR51)
);
wire VAR15 = VAR24 & VAR46 & VAR75;
wire VAR71 = VAR43 & VAR15;
wire VAR44 = VAR35 & VAR15;
wire [0:31] VAR38 = {
VAR23, VAR54, VAR79, VAR67, VAR91, VAR53, VAR45, VAR2, VAR34, VAR36, VAR78, 1'b0, VAR90[0:15], VAR42, VAR64, VAR71, VAR44 };
wire [0:31] VAR9 = {
VAR47[0:11], 16'b0, VAR47[12:15] };
wire VAR86 = VAR75 & VAR8;
wire VAR63 = VAR75 & VAR92;
wire [0:31] VAR49 = {
{12{VAR86}},
{16{VAR63}},
{4{VAR86}}
};
wire 0rzw = VAR21 | VAR69;
wire 0rzz = VAR21 | VAR1;
wire VAR97 = 0rzw | (VAR15 & ~VAR43 & ~VAR35);
wire [0:31] VAR31 = {
{12{0rzw}},
{16{0rzz}},
{2{0rzw}},
{2{VAR97}}
};
wire [0:31] VAR93 = {
1'b1, VAR51[0:3], {7{VAR51[4]}}, {2{VAR51[5]}}, {2{VAR51[6]}}, {6{VAR51[7]}}, {6{VAR51[8]}}, {4{VAR51[9]}} };
wire VAR60 = VAR88 & VAR37;
wire [0:9] VAR6 = {
VAR66[1],
VAR66[2],
VAR66[3],
VAR66[4],
VAR66[11],
VAR66[13],
VAR66[15],
VAR66[21],
VAR66[27],
1'b1
};
wire [0:31] VAR66;
wire [0:31] VAR5 = {
VAR11,
VAR66[0:30]
};
wire [0:31] VAR98;
assign VAR87 = {
VAR98[0:11],
VAR98[28:31]
};
wire [0:31] VAR17;
wire [0:31] VAR82;
genvar VAR80;
generate
for (VAR80=0 ; VAR80<32 ; VAR80=VAR80+1) begin : VAR48
VAR99 VAR73(
.VAR4(VAR4),
.VAR56(VAR93[VAR80]), .irq(VAR38[VAR80]), .VAR47(VAR9[VAR80]), .VAR89(VAR49[VAR80]), .VAR65(VAR31[VAR80]), .VAR96(VAR60), .VAR10(VAR5[VAR80]), .VAR98(VAR98[VAR80]), .VAR17(VAR17[VAR80]), .VAR82(VAR82[VAR80]), .VAR26(VAR66[VAR80]) );
end
endgenerate
assign irq = |VAR17; assign VAR52 = VAR6[8] & ~VAR6[4];
wire VAR19 = ~VAR14[15] & VAR62; wire VAR16 = VAR14[15]; wire VAR68 = VAR19 | VAR16;
wire VAR33;
VAR76 VAR84(
.VAR4(VAR4),
.VAR74(VAR74),
.VAR28(VAR28),
.VAR68(VAR68),
.VAR33(VAR33),
.VAR76(VAR76)
);
wire VAR64 = VAR33 & VAR14[15] & VAR14[0];
wire VAR67 = VAR33 & VAR14[15] & ~VAR14[0];
wire [0:15] VAR90;
VAR32 VAR50(
.VAR25(VAR19),
.VAR81(VAR33),
.VAR7(VAR14[11:14]),
.VAR57(VAR90)
);
wire VAR70 = VAR82[24] | VAR82[25] | VAR82[26] | VAR82[27] | VAR82[28] | VAR82[29] | VAR82[30] | VAR82[31];
wire VAR55 = VAR82[20] | VAR82[21] | VAR82[22] | VAR82[23] | VAR82[28] | VAR82[29] | VAR82[30] | VAR82[31];
wire VAR39 = VAR82[18] | VAR82[19] | VAR82[22] | VAR82[23] | VAR82[26] | VAR82[27] | VAR82[30] | VAR82[31];
wire VAR85 = VAR82[17] | VAR82[19] | VAR82[21] | VAR82[23] | VAR82[25] | VAR82[27] | VAR82[29] | VAR82[31];
wire VAR95 = VAR82[ 8] | VAR82[ 9] | VAR82[10] | VAR82[11] | VAR82[12] | VAR82[13] | VAR82[14] | VAR82[15];
wire VAR83 = VAR82[ 4] | VAR82[ 5] | VAR82[ 6] | VAR82[ 7] | VAR82[12] | VAR82[13] | VAR82[14] | VAR82[15];
wire VAR18 = VAR82[ 2] | VAR82[ 3] | VAR82[ 6] | VAR82[ 7] | VAR82[10] | VAR82[11] | VAR82[14] | VAR82[15];
wire VAR94 = VAR82[ 1] | VAR82[ 3] | VAR82[ 5] | VAR82[ 7] | VAR82[ 9] | VAR82[11] | VAR82[13] | VAR82[15];
wire VAR12 = ~VAR6[6];
wire VAR30 = VAR70 ^ VAR95; wire VAR20 = VAR55 ^ VAR83; wire VAR22 = VAR39 ^ VAR18; wire VAR3 = VAR85 ^ VAR94; wire VAR77 = VAR30 ^ VAR20;
wire VAR40 = VAR92 & VAR28;
wire VAR61 = VAR37 & VAR28 & VAR27;
assign VAR41[0:3] = 'd0;
assign VAR41[4] = VAR40;
assign VAR41[5:10] = 'd0;
assign VAR41[11] = (VAR61 & VAR12) | (VAR40 & VAR77);
assign VAR41[12] = (VAR61 & VAR30) | (VAR40 & ~VAR20);
assign VAR41[13] = (VAR61 & VAR20) | (VAR40 & VAR22);
assign VAR41[14] = (VAR61 & VAR22) | (VAR40 & VAR3);
assign VAR41[15] = (VAR61 & VAR3);
endmodule | gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_pa.v | 13,194 | module MODULE1( clk, rst,
VAR42, VAR31, VAR3, VAR51,
VAR35,
VAR43, VAR26,
VAR36, VAR33,
VAR53,
VAR17, VAR19
);
input clk, rst;
output [7:0] VAR42;
output VAR31;
output VAR3;
input VAR51;
output VAR35;
input VAR43;
input [1:0] VAR26;
input VAR36;
input [1:0] VAR33;
input VAR53;
input [7:0] VAR17;
output VAR19;
parameter [4:0]
VAR12 = 5'b00001,
VAR7 = 5'b00010,
VAR39 = 5'b00100,
VAR2 = 5'b01000,
VAR44 = 5'b10000;
reg [4:0] state, VAR15;
reg VAR8;
reg VAR19;
reg [7:0] VAR6, VAR23; reg [7:0] VAR9;
reg [7:0] VAR25;
reg VAR11;
reg VAR1;
reg VAR22;
reg [7:0] VAR46;
reg VAR29, VAR50;
reg VAR37;
reg VAR16;
wire VAR4;
reg [15:0] VAR47;
wire [15:0] VAR5;
wire [15:0] VAR45;
wire VAR14;
reg VAR28;
reg VAR48;
reg VAR18;
reg VAR24;
reg VAR34;
always @(posedge clk)
VAR34 <= VAR53;
always @(posedge clk or negedge rst)
always @(posedge clk)
if(rst) VAR24 <= 1'b0;
else
if(VAR8) VAR24 <= 1'b0;
else
if(VAR4) VAR24 <= VAR34;
always @(posedge clk)
VAR18 <= VAR31;
always @(posedge clk)
VAR48 <= VAR18;
always @(posedge clk or negedge rst)
always @(posedge clk)
if(rst) VAR22 <= 1'b0;
else
if(VAR43) VAR22 <= 1'b1;
else
if(VAR51) VAR22 <= 1'b0;
always @(VAR26)
case(VAR26) 2'd0: VAR6 = { ~VAR20, VAR20};
2'd1: VAR6 = { ~VAR13, VAR13};
2'd2: VAR6 = {~VAR27, VAR27};
2'd3: VAR6 = { ~VAR21, VAR21};
endcase
always @(VAR33)
case(VAR33) 2'd0: VAR23 = { ~VAR40, VAR40};
2'd1: VAR23 = { ~VAR49, VAR49};
2'd2: VAR23 = { ~VAR41, VAR41};
2'd3: VAR23 = { ~VAR30, VAR30};
endcase
always @(VAR43 or VAR22 or VAR6 or VAR25)
if(VAR43 || VAR22) VAR9 = VAR6;
else VAR9 = VAR25;
always @(VAR11 or VAR17 or VAR46)
if(VAR11) VAR25 = VAR46;
else VAR25 = VAR17;
always @(VAR29 or VAR50 or VAR23 or VAR45)
if(!VAR29 && !VAR50) VAR46 = VAR23;
else
if(VAR29) VAR46 = VAR45[15:8]; else VAR46 = VAR45[7:0];
assign VAR42 = VAR9;
assign VAR3 = VAR43 | VAR8;
assign VAR31 = VAR1;
always @(posedge clk)
VAR37 <= VAR43 | VAR36;
assign VAR35 = (VAR43 | VAR36) & ! VAR37;
always @(posedge clk)
VAR16 <= VAR36;
always @(posedge clk)
VAR28 <= VAR16;
assign VAR4 = VAR36 & !VAR16;
assign VAR14 = !VAR24 & (VAR16 & !VAR28) | (VAR19 & !VAR29);
always @(posedge clk)
if(VAR4) VAR47 <= 16'hffff;
else
if(VAR14) VAR47 <= VAR5;
VAR52 VAR32(
.VAR10( VAR47 ),
.din( {VAR17[0], VAR17[1],
VAR17[2], VAR17[3],
VAR17[4], VAR17[5],
VAR17[6], VAR17[7]} ),
.VAR38( VAR5 ) );
assign VAR45[15] = ~VAR47[8];
assign VAR45[14] = ~VAR47[9];
assign VAR45[13] = ~VAR47[10];
assign VAR45[12] = ~VAR47[11];
assign VAR45[11] = ~VAR47[12];
assign VAR45[10] = ~VAR47[13];
assign VAR45[9] = ~VAR47[14];
assign VAR45[8] = ~VAR47[15];
assign VAR45[7] = ~VAR47[0];
assign VAR45[6] = ~VAR47[1];
assign VAR45[5] = ~VAR47[2];
assign VAR45[4] = ~VAR47[3];
assign VAR45[3] = ~VAR47[4];
assign VAR45[2] = ~VAR47[5];
assign VAR45[1] = ~VAR47[6];
assign VAR45[0] = ~VAR47[7];
always @(posedge clk or negedge rst)
always @(posedge clk)
if(rst) state <= VAR12;
else state <= VAR15;
always @(state or VAR36 or VAR51 or VAR48 or VAR34)
begin
VAR15 = state; VAR1 = 1'b0;
VAR11 = 1'b0;
VAR19 = 1'b0;
VAR8 = 1'b0;
VAR29 = 1'b0;
VAR50 = 1'b0;
case(state) VAR12:
begin
if(VAR34 && VAR36)
begin
VAR1 = 1'b1;
VAR15 = VAR44;
VAR11 = 1'b1;
end
else
if(VAR36) begin
VAR1 = 1'b1;
VAR15 = VAR7;
VAR11 = 1'b1;
end
end
VAR7:
begin
if(VAR51 && VAR48)
VAR19 = 1'b1;
VAR1 = 1'b1;
if(!VAR36 && VAR51 && VAR48)
begin
VAR11 = 1'b1;
VAR29 = 1'b1;
VAR15 = VAR39;
end
end
VAR44: begin
VAR29 = 1'b1;
VAR11 = 1'b1;
VAR1 = 1'b1;
VAR15 = VAR39;
end
VAR39:
begin
VAR11 = 1'b1;
VAR1 = 1'b1;
if(VAR51)
begin
VAR8 = 1'b1;
VAR50 = 1'b1;
VAR15 = VAR2;
end
else
begin
VAR1 = 1'b1;
VAR29 = 1'b1;
end
end
VAR2:
begin
VAR11 = 1'b1;
VAR50 = 1'b1;
if(VAR51)
begin
VAR15 = VAR12;
end
else
begin
VAR8 = 1'b1;
end
end
endcase
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2.blackbox.v | 1,323 | module MODULE1 (
VAR6,
VAR3
);
output VAR6;
input VAR3;
supply1 VAR5;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
forrestv/myhdl | example/manual/FramerCtrl.v | 1,588 | module MODULE1 (
VAR3,
state,
VAR6,
clk,
VAR1
);
output VAR3;
reg VAR3;
output [2:0] state;
reg [2:0] state;
input VAR6;
input clk;
input VAR1;
reg [7:0] VAR5;
always @(posedge clk, negedge VAR1) begin: VAR2
if ((VAR1 == 0)) begin
VAR3 <= 0;
VAR5 <= 0;
state <= 3'b001;
end
else begin
VAR5 <= ((VAR5 + 1) % 8);
VAR3 <= 0;
casez (state)
3'VAR4??1: begin
VAR5 <= 1;
if (VAR6) begin
state <= 3'b010;
end
end
3'VAR4?1?: begin
if ((VAR5 == 0)) begin
if (VAR6) begin
state <= 3'b100;
end
else begin
state <= 3'b001;
end
end
end
3'b1??: begin
if ((VAR5 == 0)) begin
if ((!VAR6)) begin
state <= 3'b001;
end
end
VAR3 <= (VAR5 == (8 - 1));
end
default: begin
end
endcase
end
end
endmodule | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbn/sky130_fd_sc_hs__dfbbn.behavioral.v | 2,882 | module MODULE1 (
VAR20 ,
VAR21 ,
VAR24 ,
VAR4 ,
VAR16 ,
VAR3,
VAR1 ,
VAR27
);
output VAR20 ;
output VAR21 ;
input VAR24 ;
input VAR4 ;
input VAR16 ;
input VAR3;
input VAR1 ;
input VAR27 ;
wire VAR7 ;
wire VAR28 ;
wire VAR14 ;
wire VAR15 ;
wire VAR13 ;
wire VAR26;
wire VAR12 ;
reg VAR19 ;
wire VAR6 ;
wire VAR22 ;
wire VAR5 ;
wire VAR17 ;
wire VAR2 ;
not VAR8 (VAR7 , VAR26 );
not VAR23 (VAR28 , VAR12 );
not VAR10 (VAR14 , VAR13 );
VAR25 VAR9 (VAR15 , VAR28, VAR7, VAR14, VAR6, VAR19, VAR1, VAR27);
assign VAR22 = ( VAR1 === 1'b1 );
assign VAR5 = ( VAR22 && ( VAR26 === 1'b1 ) );
assign VAR17 = ( VAR22 && ( VAR12 === 1'b1 ) );
assign VAR2 = ( VAR5 & VAR17 );
buf VAR11 (VAR20 , VAR15 );
not VAR18 (VAR21 , VAR15 );
endmodule | apache-2.0 |
Aetas/nbit-comparator | Quartus 2 proj/nbitcomparator.v | 5,355 | module MODULE1(VAR7, VAR8, VAR2, VAR9, VAR6, VAR1, VAR10, VAR4, VAR5, VAR3);
input VAR7, VAR8, VAR2, VAR9; input VAR6, VAR1, VAR10; output VAR4, VAR5, VAR3;
assign VAR4 = VAR6 & (VAR7 ~^ VAR2) & (VAR8 ~^ VAR9);
assign VAR5 = (VAR1 | (VAR7 & ~VAR2) | (VAR8 & ~VAR2 & ~VAR9) | (VAR7 & VAR8 & VAR2 & ~VAR9)) & ~VAR10;
assign VAR3 = VAR10 | ~(VAR4 | VAR5);
endmodule | mit |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.v | 3,951 | module MODULE1(
addr,
clk,
din,
dout,
en,
VAR18);
input [8 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input VAR18;
VAR37 #(
.VAR15(9),
.VAR46("0"),
.VAR35(512),
.VAR42(0),
.VAR7(1),
.VAR13(1),
.VAR40(1),
.VAR22(0),
.VAR21(0),
.VAR19(0),
.VAR45(0),
.VAR33(0),
.VAR6(1),
.VAR39(18),
.VAR5("VAR29"),
.VAR23(0),
.VAR2(0),
.VAR1("0"),
.VAR20(8),
.VAR16(0),
.VAR10("0"),
.VAR43(1),
.VAR38(0),
.VAR24("VAR25"),
.VAR36(0),
.VAR17("16kx1"),
.VAR11(1),
.VAR3("1024"),
.VAR30(0),
.VAR12(0),
.VAR44(1))
VAR26 (
.VAR34(addr),
.VAR32(clk),
.VAR9(din),
.VAR31(dout),
.VAR8(en),
.VAR14(VAR18),
.VAR28(),
.VAR4(),
.VAR27(),
.VAR41());
endmodule | bsd-3-clause |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/sdr_lib/dpram.v | 1,328 | module MODULE1(VAR3,VAR1,VAR4,VAR10,VAR8,VAR9,VAR7);
parameter VAR2 = 4;
parameter VAR11 = 16;
parameter VAR5 = 16;
input VAR3;
input [VAR11-1:0] VAR1;
input [VAR2-1:0] VAR4;
input VAR10;
input VAR8;
output reg [VAR11-1:0] VAR9;
input [VAR2-1:0] VAR7;
reg [VAR11-1:0] VAR6 [0:VAR5-1];
always @(posedge VAR3)
if(VAR10)
VAR6[VAR4] <= VAR1;
always @(posedge VAR8)
VAR9 <= VAR6[VAR7];
endmodule | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_multiplexer_64.v | 16,288 | module MODULE1
parameter VAR78 = 128,
parameter VAR43 = 12,
parameter VAR97 = 5, parameter VAR29 = "VAR66"
)
(
input VAR68,
input VAR96,
input [VAR43-1:0] VAR91, input [(VAR43*VAR74)-1:0] VAR46, input [(VAR43*VAR26)-1:0] VAR12, input [(VAR43*VAR78)-1:0] VAR106, output [VAR43-1:0] VAR105, output [VAR43-1:0] VAR60,
input [VAR43-1:0] VAR107, input [(VAR43*2)-1:0] VAR53, input [(VAR43*VAR74)-1:0] VAR92, input [(VAR43*VAR26)-1:0] VAR47, output [VAR43-1:0] VAR24,
output [5:0] VAR83, output VAR33, input [VAR97-1:0] VAR84, input VAR23,
output VAR117, input VAR109,
output VAR110,
output [VAR78-1:0] VAR55,
output VAR41,
output [VAR79(VAR78/32)-1:0] VAR100,
output VAR95,
output [VAR79(VAR78/32)-1:0] VAR44,
input VAR6,
output VAR49,
output [VAR98-1:0] VAR104,
output [VAR35-1:0] VAR36,
output [VAR74-1:0] VAR3,
output [VAR26-1:0] VAR18,
output [VAR28-1:0] VAR99,
output [VAR1-1:0] VAR64,
output [VAR48-1:0] VAR88,
output [VAR40-1:0] VAR5,
output VAR54,
input VAR56);
localparam VAR90 = 6'd6;
reg [3:0] VAR58=VAR118, VAR58=VAR118;
reg VAR114=0, VAR114=0;
reg [3:0] VAR77=0, VAR77=0;
reg [VAR97-1:0] VAR21=0, VAR21=0;
reg [9:0] VAR30=0, VAR30=0;
reg VAR63=0, VAR63=0;
reg VAR75=0,VAR75=0;
reg VAR17=0, VAR17=0;
reg VAR76=0, VAR76=0;
reg [9:0] VAR85=0, VAR85=0;
reg [VAR43-1:0] VAR71=0, VAR71=0;
reg VAR45, VAR45;
wire VAR2;
wire [3:0] VAR111;
wire VAR27;
wire [3:0] VAR102;
wire VAR86;
wire [3:0] VAR72;
wire [11:0] VAR37 = (VAR72*VAR78); wire [63:0] VAR11;
wire [9:0] VAR69;
wire [1:0] VAR15;
wire [63:0] VAR82;
wire [9:0] VAR8;
wire [VAR78-1:0] VAR34;
reg [3:0] VAR51=0, VAR51=0;
reg [61:0] VAR108=62'd0, VAR108=62'd0;
reg [9:0] VAR38=0, VAR38=0;
reg [1:0] VAR25=0, VAR25=0;
reg [3:0] VAR32=0, VAR32=0;
reg [61:0] VAR101=62'd0, VAR101=62'd0;
reg [9:0] VAR52=0, VAR52=0;
reg [VAR78-1:0] VAR14={VAR78{1'd0}}, VAR14={VAR78{1'd0}};
assign VAR11 = VAR92[VAR111 * VAR74 +: VAR74];
assign VAR69 = VAR47[VAR111 * VAR26 +: VAR26];
assign VAR15 = VAR53[VAR111 * 2 +: 2];
assign VAR82 = VAR46[VAR102 * VAR74 +: VAR74];
assign VAR8 = VAR12[VAR102 * VAR26 +: VAR26];
assign VAR34 = VAR106[VAR72 * VAR78 +: VAR78];
reg [3:0] VAR31=VAR80, VAR31=VAR80;
reg [VAR43-1:0] VAR89=0, VAR89=0;
reg [VAR43-1:0] VAR62=0, VAR62=0;
reg VAR9=0, VAR9=0;
reg [5:0] VAR61=0, VAR61=0;
reg [61:0] VAR65=62'd0, VAR65=62'd0;
reg VAR81=0, VAR81=0;
reg [9:0] VAR10=0, VAR10=0;
reg VAR59=0, VAR59=0;
reg VAR57=0, VAR57=0;
reg [VAR97-1:0] VAR70=0, VAR70=0;
reg [VAR90-1:0] VAR116=0, VAR116=0;
reg [(VAR90*4)-1:0] VAR13=0, VAR13=0;
reg [(VAR90*8)-1:0] VAR4=0, VAR4=0;
reg [(VAR90*62)-1:0] VAR22=0, VAR22=0;
reg [((VAR90+1)*10)-1:0] VAR93=0, VAR93=0;
reg [VAR90-1:0] VAR113=0, VAR113=0;
reg [VAR90-1:0] VAR94=0, VAR94=0;
reg [VAR90-1:0] VAR67=0, VAR67=0;
assign VAR105 = VAR71;
assign VAR60 = VAR62;
assign VAR24 = VAR89;
assign VAR83 = {VAR25, VAR51};
assign VAR33 = VAR57;
assign VAR117 = VAR45;
assign VAR86 = (VAR2 & VAR23 & VAR109);
VAR7 #(.VAR43(VAR43)) VAR20 (.VAR16(VAR96), .VAR68(VAR68), .VAR73(VAR107), .VAR50(VAR2), .VAR39(VAR111));
VAR7 #(.VAR43(VAR43)) VAR115 (.VAR16(VAR96), .VAR68(VAR68), .VAR73(VAR91), .VAR50(VAR27), .VAR39(VAR102));
always @ (posedge VAR68) begin
VAR51 <= VAR51;
VAR108 <= VAR108;
VAR38 <= VAR38;
VAR25 <= VAR25;
VAR32 <= VAR32;
VAR101 <= VAR101;
VAR52 <= VAR52;
VAR14 <= VAR14;
end
always @ begin
VAR31 = VAR31;
VAR89 = VAR89;
VAR62 = VAR62;
VAR9 = VAR9;
VAR61 = VAR61;
VAR65 = VAR65;
VAR81 = (VAR65[61:30] != 0);
VAR10 = VAR10;
VAR59 = VAR59;
VAR57 = VAR57;
VAR70 = VAR70;
VAR45 = VAR45;
case (VAR31)
VAR9 = !VAR2;
VAR89 = (VAR86<<VAR111);
VAR45 = VAR86;
VAR57 = VAR86;
VAR31 = (VAR86 ? VAR42 : VAR119);
end
VAR9 = VAR27;
VAR62 = (VAR27<<VAR102);
VAR31 = (VAR27 ? VAR42 : VAR80);
end
VAR45 = 0;
VAR89 = 0;
VAR62 = 0;
VAR59 = VAR9;
VAR57 = 0;
VAR70 = VAR84;
if (VAR9) begin
VAR61 = {2'd0, VAR32};
VAR65 = VAR101;
VAR10 = VAR52;
end
else begin
VAR61 = {VAR25, VAR51};
VAR65 = VAR108;
VAR10 = VAR38;
end
VAR31 = VAR87;
end
if (VAR56 & VAR58[0]) VAR31 = (VAR119>>(VAR59)); end
default : begin
VAR31 = VAR80;
end
endcase
end
always @ (posedge VAR68) begin
VAR58 <= (VAR96 ? VAR118 : VAR58);
VAR114 <= VAR114;
VAR85 <= VAR85;
VAR30 <= VAR30;
VAR63 <= VAR63;
VAR17 <= VAR17;
VAR77 <= VAR77;
VAR21 <= VAR21;
VAR76 <= VAR76;
VAR71 <= VAR71;
VAR75 <= VAR96 ? 0 : VAR75;
end
always @ begin
VAR116 = {VAR116[((VAR90-1)*1)-1:0], VAR59};
VAR22 = {VAR22[((VAR90-1)*62)-1:0], VAR65};
VAR93 = {VAR93[((VAR90-1)*10)-1:0], VAR85};
VAR13 = {VAR13[((VAR90-1)*4)-1:0], VAR77};
VAR4 = {VAR4[((VAR90-1)*8)-1:0], (8'd0 | VAR21)};
VAR113 = {VAR113[((VAR90-1)*1)-1:0], VAR75 & VAR114}; VAR94 = {VAR94[((VAR90-1)*1)-1:0], VAR63};
VAR67 = {VAR67[((VAR90-1)*1)-1:0], VAR17};
end
assign VAR55 = VAR14;
assign VAR110 = VAR113[(VAR90-1)*1 +:1];
assign VAR41 = VAR67[(VAR90-1)*1 +:1];
assign VAR100 = 0;
assign VAR95 = VAR94[(VAR90-1)*1 +:1];
assign VAR44 = VAR93[(VAR90-1)*10 +:VAR103] - 1;
assign VAR49 = VAR17;
assign VAR5 = VAR59 ? VAR19 : VAR112;
assign VAR3 = {VAR65,2'b00};
assign VAR18 = VAR10;
assign VAR36 = 4'b1111;
assign VAR104 = 4'b1111;
assign VAR99 = VAR21;
assign VAR54 = 1'b0;
assign VAR88 = 3'b110;
assign VAR64 = 0;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o.symbol.v | 1,327 | module MODULE1 (
input VAR7,
input VAR2,
input VAR3,
input VAR6,
output VAR5
);
supply1 VAR4;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/inv/sky130_fd_sc_hs__inv.pp.blackbox.v | 1,172 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR2;
input VAR1;
endmodule | apache-2.0 |
dries007/Basys3 | FPGA-Z/FPGA-Z.srcs/sources_1/ip/ClockDivider/ClockDivider.v | 4,164 | module MODULE1
(
input VAR5,
output VAR3,
output VAR6,
output VAR7,
output VAR1
);
VAR2 VAR4
(
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or3/sky130_fd_sc_hvl__or3.behavioral.v | 1,365 | module MODULE1 (
VAR2,
VAR1,
VAR10,
VAR6
);
output VAR2;
input VAR1;
input VAR10;
input VAR6;
supply1 VAR4;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR9 ;
wire VAR8;
or VAR7 (VAR8, VAR10, VAR1, VAR6 );
buf VAR11 (VAR2 , VAR8 );
endmodule | apache-2.0 |
cybero/Verilog | src/Parameterized Frequency Divider/Freq_Divider.v | 1,093 | module MODULE1#(
parameter VAR6 = 50000000, VAR1 = 1 )
(VAR5, VAR9);
input wire VAR5;
output reg VAR9;
parameter VAR7 = VAR6 / (2*VAR1);
localparam VAR2=VAR3(VAR7);
reg [VAR2-1:0]counter = 0;
always@(posedge VAR5) begin
if (counter == VAR7-1)
begin
counter <= 0;
VAR9 <= ~VAR9;
end
else
begin
counter <= counter + 1'd1;
end
end
function integer VAR3(input integer VAR4);
integer VAR8;
begin
VAR3=1;
for (VAR8=0; 2**VAR8 < VAR4; VAR8=VAR8+1)
VAR3=VAR8+1;
end
endfunction
endmodule | mit |
kielfriedt/ece472 | lab4/mem32.v | 2,292 | module MODULE1(clk, VAR1, VAR7, address, VAR5, VAR9);
input clk, VAR1, VAR7;
input [31:0] address, VAR5;
output [31:0] VAR9;
reg [31:0] VAR9;
parameter VAR8 = 25'd0;
reg [31:0] VAR3 [0:31];
wire [4:0] VAR2;
wire VAR6;
assign VAR2 = address[6:2];
assign VAR6 = (address[31:7] == VAR8);
always @(VAR1 or VAR6 or VAR2 or VAR3[VAR2])
begin
if (VAR1 == 1'b1 && VAR6 == 1'b1)
begin
if ((address % 4) != 0)
VAR9 = VAR3[VAR2];
end
else VAR9 = 32'VAR4;
end
always @(posedge clk)
begin
if (VAR7 == 1'b1 && VAR6 == 1'b1)
begin
VAR3[VAR2] <= VAR5;
end
end
integer VAR10; | gpl-3.0 |
sh-chris110/chris | FPGA/chris.convolution.ok/Qsys/soc_design/synthesis/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR2,
VAR3,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR2;
input VAR3;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1500859667 : 255;
endmodule | gpl-2.0 |
stevenokm/mor1kx | rtl/verilog/mor1kx_lsu_cappuccino.v | 26,804 | module MODULE1
parameter VAR30 = "VAR61",
parameter VAR37 = 32,
parameter VAR128 = 5,
parameter VAR12 = 9,
parameter VAR72 = 2,
parameter VAR125 = 32,
parameter VAR5 = "VAR61",
parameter VAR71 = "VAR61",
parameter VAR116 = "VAR61",
parameter VAR4 = 6,
parameter VAR127 = 1,
parameter VAR34 = "VAR126",
parameter VAR10 = 8,
parameter VAR95 = "VAR126"
)
(
input clk,
input rst,
input VAR15,
input VAR63, input VAR137,
input [VAR37-1:0] VAR18,
input [VAR37-1:0] VAR130,
input [VAR37-1:0] VAR155,
input VAR13,
input VAR153,
input VAR31,
input VAR139,
input VAR160,
input VAR142,
input VAR17,
input [1:0] VAR19,
input VAR115,
input [VAR37-1:0] VAR70,
output [VAR37-1:0] VAR159,
output [VAR37-1:0] VAR38,
output VAR158,
output VAR1,
output VAR103,
output VAR123,
output VAR108,
output reg VAR88,
output VAR51,
output VAR111,
output VAR99,
input [15:0] VAR73,
input VAR104,
input VAR68,
input [VAR37-1:0] VAR146,
output [VAR37-1:0] VAR50,
output VAR20,
output [VAR37-1:0] VAR131,
output VAR161,
input VAR164,
input VAR7,
input VAR16,
output [VAR37-1:0] VAR27,
output reg VAR42,
output [VAR37-1:0] VAR101,
output reg [3:0] VAR62,
output VAR121,
output VAR24,
input VAR147,
input VAR6,
input [VAR37-1:0] VAR143,
input VAR150,
input [31:0] VAR122,
input VAR151
);
reg [VAR37-1:0] VAR8; reg [VAR37-1:0] VAR40;
reg VAR97;
wire VAR145;
wire VAR48;
wire VAR149;
wire VAR152;
reg VAR167;
reg VAR41;
reg VAR44;
reg [VAR37-1:0] VAR98;
reg [VAR37-1:0] VAR124;
wire [VAR37-1:0] VAR105;
reg VAR163;
reg [3:0] VAR28;
wire VAR67;
wire VAR120;
wire [VAR37-1:0] VAR132;
wire [VAR37-1:0] VAR119;
wire VAR49;
wire VAR53;
wire VAR91;
wire [31:0] VAR59;
wire [31:0] VAR135;
wire [31:0] VAR55;
wire [31:0] VAR79;
wire VAR65;
wire VAR89;
wire [3:0] VAR45;
wire VAR66;
wire VAR141;
wire VAR56;
wire VAR107;
wire VAR154;
reg VAR76;
wire VAR69;
wire VAR157;
wire VAR29;
wire VAR148;
wire [VAR37-1:0] VAR60;
wire VAR2;
reg VAR33;
wire VAR58;
reg VAR165;
wire VAR112;
wire VAR64;
wire VAR109;
wire [VAR37-1:0] VAR114;
wire VAR43;
reg VAR162;
reg [VAR37-1:0] VAR85;
wire VAR84;
reg VAR22;
wire VAR54;
wire VAR26;
wire VAR138;
wire VAR81;
wire [VAR37-1:0] VAR25;
wire [VAR37-1:0] VAR134;
wire [VAR37-1:0] VAR96;
wire [VAR37/8-1:0] VAR83;
wire VAR140;
reg VAR35;
reg VAR87;
reg VAR129;
reg VAR52;
reg [VAR37-1:0] VAR80;
reg VAR9;
wire VAR118;
wire VAR32;
wire VAR39;
assign VAR32 = (VAR5 != "VAR61") ?
VAR151 & !((VAR122 == VAR27) & VAR6) :
0;
assign VAR157 = VAR139 | VAR160;
assign VAR119 = (VAR19 == 2'b00) ? {VAR155[7:0],VAR155[7:0],
VAR155[7:0],VAR155[7:0]} :
(VAR19 == 2'b01) ? {VAR155[15:0],VAR155[15:0]} :
VAR155;
assign VAR145 = |VAR130[1:0];
assign VAR48 = VAR130[0];
assign VAR158 = (VAR49 | VAR97) & !VAR109 & !VAR39;
assign VAR1 = VAR167 | VAR88;
assign VAR149 = (VAR19 == 2'b10) & VAR145 |
(VAR19 == 2'b01) & VAR48;
assign VAR152 = VAR157 & VAR149;
assign VAR103 = VAR152 & !VAR150;
assign VAR2 = VAR157 & VAR29 & VAR7 &
!VAR109;
assign VAR123 = VAR2 & !VAR150;
assign VAR58 = VAR157 & VAR148 & VAR7 &
!VAR109 | VAR43;
assign VAR108 = VAR58 & !VAR150;
assign VAR99 = VAR17 & (state == VAR21);
always @(posedge clk VAR36)
if (rst)
VAR97 <= 0;
else if (VAR15)
VAR97 <= 0;
else if (VAR49)
VAR97 <= 1;
always @(posedge clk VAR36)
if (rst)
VAR167 <= 0;
else if (VAR15 | VAR150)
VAR167 <= 0;
else if (VAR147)
VAR167 <= 1;
always @(posedge clk VAR36)
if (rst)
VAR33 <= 0;
else if (VAR15)
VAR33 <= 0;
else if (VAR2)
VAR33 <= 1;
always @(posedge clk VAR36)
if (rst)
VAR165 <= 0;
else if (VAR15)
VAR165 <= 0;
else if (VAR58)
VAR165 <= 1;
always @(posedge clk VAR36)
if (rst)
VAR88 <= 0;
else if (VAR150)
VAR88 <= 0;
else if (VAR147 & VAR121)
VAR88 <= 1;
always @
case({VAR115, VAR19})
3'b100: VAR40 = {24'd0,VAR8[31:24]};
3'b101: VAR40 = {16'd0,VAR8[31:16]};
3'b000: VAR40 = {{24{VAR8[31]}},
VAR8[31:24]};
3'b001: VAR40 = {{16{VAR8[31]}},
VAR8[31:16]};
default:
VAR40 = VAR8;
endcase
assign VAR38 = VAR40;
localparam [2:0]
VAR110 = 3'd0,
VAR74 = 3'd1,
VAR21 = 3'd2,
VAR3 = 3'd3,
VAR156 = 3'd4;
reg [2:0] state;
assign VAR67 = (!VAR66 | VAR109 | VAR160) &
(state != VAR156) | (state == VAR21);
reg VAR86;
always @(posedge clk)
VAR86 <= VAR56;
wire VAR166;
assign VAR166 = (VAR34!="VAR61") ?
VAR54 :
VAR52;
assign VAR49 = (VAR160 | state == VAR21) ?
(VAR166 & !VAR142 |
VAR52 & VAR142) :
(VAR67 ? VAR41 : VAR91);
assign VAR132 = VAR67 ? VAR98 : VAR59;
assign VAR27 = VAR124;
assign VAR101 = VAR98;
assign VAR24 = (state == VAR156) & !VAR154;
assign VAR121 = VAR163 & (!VAR87 | VAR9);
assign VAR105 = (VAR128 == 5) ?
{VAR124[31:5], VAR124[4:0] + 5'd4} : {VAR124[31:4], VAR124[3:0] + 4'd4};
always @(posedge clk VAR36)
if (rst)
VAR44 <= 0;
else
VAR44 <= VAR147;
always @(posedge clk) begin
VAR41 <= 0;
VAR52 <= 0;
VAR162 <= 0;
VAR22 <= 0;
case (state)
VAR110: begin
VAR42 <= 0;
VAR163 <= 0;
VAR124 <= 0;
VAR62 <= 4'hf;
VAR87 <= 0;
VAR129 <= 0;
if (VAR54 | !VAR81) begin
state <= VAR21;
end else if (VAR157 & VAR67 & !VAR56 & !VAR41 &
!VAR44 & !VAR167 & !VAR97 &
!VAR150) begin
if (VAR64) begin
VAR124 <= VAR114;
VAR42 <= 1;
state <= VAR3;
end else if (VAR7) begin
VAR124 <= VAR60;
if (!VAR29 & !VAR148 & !VAR152) begin
if (VAR139) begin
VAR42 <= 1;
VAR62 <= VAR28;
state <= VAR74;
end
end
end else if (!VAR152) begin
VAR124 <= VAR130;
if (VAR139) begin
VAR42 <= 1;
VAR62 <= VAR28;
state <= VAR74;
end
end
end else if (VAR107) begin
VAR42 <= 1;
VAR124 <= VAR79;
state <= VAR156;
end
end
VAR156: begin
VAR42 <= 1;
if (VAR6) begin
VAR124 <= VAR105;
if (VAR154) begin
VAR42 <= 0;
state <= VAR110;
end
end
if (VAR147 | VAR39) begin
VAR42 <= 0;
state <= VAR110;
end
end
VAR74: begin
VAR41 <= VAR6;
VAR98 <= VAR143;
if (VAR6 | VAR147) begin
VAR42 <= 0;
state <= VAR110;
end
end
VAR21: begin
VAR42 <= 1;
VAR163 <= 1;
if (!VAR42 | VAR6 & !VAR129) begin
VAR62 <= VAR83;
VAR124 <= VAR25;
VAR98 <= VAR96;
VAR87 <= VAR140;
VAR129 <= VAR81;
end
if (VAR54)
VAR129 <= 0;
if (VAR129 & VAR6 | VAR147) begin
VAR42 <= 0;
VAR163 <= 0;
if (!VAR54) begin
state <= VAR110;
VAR52 <= 1;
end
end
end
VAR3: begin
VAR124 <= VAR114;
VAR85 <= VAR143;
VAR162 <= VAR6 & VAR64;
if (!VAR64 | VAR147) begin
state <= VAR110;
VAR22 <= 1;
end
VAR42 <= VAR64;
if (VAR6 | VAR162)
VAR42 <= 0;
end
default:
state <= VAR110;
endcase
if (rst)
state <= VAR110;
end
assign VAR120 = VAR109 | VAR152 | VAR167 |
VAR2 | VAR58 |
VAR150;
generate
if (VAR95!="VAR61") begin : VAR82
reg VAR46;
reg VAR94;
always @(posedge clk VAR36)
if (rst)
VAR9 <= 0;
end
else if (VAR150)
VAR9 <= 0;
end
else if (VAR160 & VAR142 & VAR52 ||
!VAR142 & VAR54 &
(VAR134 == VAR80) ||
(VAR32 & (VAR122 == VAR80)))
VAR9 <= 0;
end
else if (VAR139 & VAR142 & VAR63)
VAR9 <= !(VAR32 & (VAR122 == VAR79));
always @(posedge clk)
if (VAR139 & VAR142 & VAR63)
VAR80 <= VAR79;
assign VAR118 = VAR160 & VAR142 &
VAR9 & (VAR124 == VAR80);
always @(posedge clk)
if (VAR63)
VAR46 <= 0;
end
else if (VAR52)
VAR46 <= VAR118 & VAR158;
always @(posedge clk)
if (VAR63)
VAR94 <= 0;
end
else if (VAR52)
VAR94 <= !VAR118 & VAR158 &
VAR142 & VAR160;
assign VAR51 = VAR46;
assign VAR111 = VAR94;
end else begin
assign VAR51 = 0;
assign VAR111 = 0;
assign VAR118 = 0;
always @(posedge clk) begin
VAR80 <= 0;
VAR9 <= 0;
end
end
endgenerate
always @(posedge clk)
if (rst)
VAR35 <= 0;
else if (VAR54 | VAR150)
VAR35 <= 0;
else if (VAR160 & VAR63 & !VAR120 &
(VAR138 | VAR56 | VAR86 | VAR39))
VAR35 <= 1;
assign VAR54 = (VAR160 &
(VAR63 | VAR22) |
VAR35) &
!VAR138 & !VAR56 & !VAR86 &
!VAR120 & !VAR39;
generate
if (VAR34!="VAR61") begin : VAR144
assign VAR26 = (state == VAR110) & VAR54 |
(state == VAR110) & !VAR81 |
(state == VAR21) & (VAR6 | !VAR42) &
(!VAR81 | VAR54) &
!VAR129 |
(state == VAR21) & VAR129 &
VAR54;
VAR113
.VAR100(VAR10),
.VAR37(VAR37)
)
VAR113
(
.clk (clk),
.rst (rst),
.VAR90 (VAR70),
.VAR133 (VAR134),
.VAR102 (VAR119),
.VAR23 (VAR28),
.VAR14 (VAR142),
.VAR92 (VAR54),
.VAR47 (VAR159),
.VAR136 (VAR25),
.VAR93 (VAR96),
.VAR78 (VAR83),
.VAR77 (VAR140),
.VAR57 (VAR26),
.VAR75 (VAR138),
.VAR106 (VAR81)
);
end else begin
assign VAR159 = VAR70;
assign VAR25 = VAR134;
assign VAR96 = VAR119;
assign VAR83 = VAR28;
assign VAR81 = 1'b1;
reg VAR11;
always @(posedge clk)
if (VAR54)
VAR11 <= 1;
end
else if (VAR52)
VAR11 <= 0;
assign VAR138 = VAR11 & !VAR52;
end
endgenerate
assign VAR134 = VAR79;
always @(posedge clk VAR36)
if (rst)
VAR76 <= 0;
else if (VAR164 & !VAR42)
VAR76 <= 1;
else if (!VAR164 & !VAR56)
VAR76 <= 0;
assign VAR69 = VAR164 & VAR76;
assign VAR55 = VAR15 &
(VAR13 | VAR153) ?
VAR18 : VAR130;
assign VAR79 = VAR7 ?
{VAR60[VAR37-1:2],2'b0} :
{VAR130[VAR37-1:2],2'b0};
assign VAR65 = VAR157 & VAR66 & !VAR97 & !VAR120 &
!(VAR87 & VAR163 & !VAR9);
assign VAR141 = !(VAR160 | state == VAR21) &
!VAR39 & !VAR32;
generate
if (VAR30!="VAR61") begin : VAR117
if (VAR125 == VAR37) begin
assign VAR66 = VAR160 | VAR69 &
!(VAR112 & VAR7);
end else if (VAR125 < VAR37) begin
assign VAR66 = VAR160 | VAR69 &
VAR79[VAR37-1:
VAR125] == 0 &
!(VAR112 & VAR7);
end else begin | mpl-2.0 |
fpgasystems/caribou | hw/src/regex/kvs_vs_RegexTop_fc.v | 6,837 | module MODULE1
(
input clk,
input VAR12,
input rst,
input VAR58,
input [511:0] VAR46,
input VAR28,
input VAR19,
output VAR38,
input [511:0] VAR20,
input VAR23,
output VAR45,
output VAR18,
output VAR11,
input VAR41
);
parameter VAR47 = 4;
parameter VAR40 = 16;
wire [511:0] VAR14 [VAR40-1:0];
reg [511:0] VAR29 [VAR40-1:0];
wire [VAR40-1:0] VAR9;
wire [VAR40-1:0] VAR30;
wire [VAR40-1:0] VAR48;
wire [VAR40-1:0] VAR56;
reg [VAR40-1:0] VAR25;
reg [VAR40-1:0] VAR43;
reg VAR27;
reg VAR5;
wire [VAR40*16-1:0] VAR24 ;
wire [VAR40-1:0] VAR34;
wire [VAR40-1:0] VAR15;
wire [VAR40-1:0] VAR55;
wire [VAR40-1:0] VAR63;
wire [VAR40-1:0] VAR62;
reg [VAR47-1:0] VAR13;
reg [VAR47-1:0] VAR60;
reg [VAR47-1:0] VAR61;
reg [VAR47-1:0] VAR42;
reg VAR7;
reg VAR6;
reg VAR52;
reg [7:0] VAR59;
reg VAR57;
assign VAR38 = (VAR6);
assign VAR45 = VAR57==0 ? (~VAR25[VAR61] && (VAR6) && (VAR59<VAR40-1)) : 0;
reg VAR37;
integer VAR3;
always @(posedge clk) begin
VAR37 <= rst;
if (rst) begin
VAR60 <= 0;
VAR61 <= 0;
VAR25 <= 0;
VAR42 <= 0;
VAR7 <= 0;
VAR6 <= 0;
VAR52 <= 0;
VAR59 <= 0;
VAR57 <= 0;
end
else begin
VAR25 <= 0;
VAR52 <= (VAR48 == {VAR40{1'b1}} ? 1 : 0) && (VAR30 == 0 ? 1 : 0);
VAR6 <= VAR52;
if (VAR45==1 && VAR23==1) begin
VAR29[VAR61] <= VAR20;
VAR25[VAR61] <= 1;
VAR43[VAR61] <= 1;
VAR59 <= VAR59+1;
if (VAR20[511]==1) begin
VAR57 <= 1;
end
if (VAR61==VAR40-1) begin
VAR61 <= 0;
end else begin
VAR61 <= VAR61 +1;
end
if (VAR20[511]==1) begin
for (VAR3=0; VAR3<VAR40; VAR3=VAR3+1) begin
VAR29[VAR3] <= VAR20;
end
VAR25 <= {VAR40{1'b1}};
VAR43 <= {VAR40{1'b1}};
end
end
if (VAR38==1 && VAR28==1) begin
if (VAR45==1 && VAR23==1 && VAR19==1) begin
VAR59 <= VAR59;
end else if (VAR19==1) begin
VAR59 <= VAR59-1;
end
VAR29[VAR60] <= VAR46;
VAR25[VAR60] <= 1;
VAR43[VAR60] <= 0;
if (VAR19==1) begin
if (VAR60==VAR40-1) begin
VAR60 <= 0;
end else begin
VAR60 <= VAR60 +1;
end
end
end
if (VAR11==1 && VAR41==1) begin
if (VAR42==VAR40-1) begin
VAR42 <= 0;
end else begin
VAR42 <= VAR42+1;
end
end
end
end
assign VAR11 = VAR55[VAR42];
assign VAR18 = VAR62[VAR42];
reg VAR33;
always @(posedge VAR12) begin
VAR33 <= VAR37;
VAR5 <= VAR33;
VAR27 <= VAR5;
end
genvar VAR54;
generate
for (VAR54=0; VAR54 < VAR40; VAR54=VAR54+1)
begin: VAR8
VAR1
VAR2 (
.VAR10(clk),
.VAR53(VAR12),
.VAR4(~rst),
.VAR44(VAR29[VAR54]),
.VAR51(VAR25[VAR54]),
.VAR31(VAR48[VAR54]),
.VAR21(VAR30[VAR54]),
.VAR50(VAR14[VAR54][511:0]),
.VAR17(VAR9[VAR54]),
.VAR16(VAR56[VAR54])
);
VAR26 VAR35 (
.clk(VAR12),
.rst(VAR58),
.VAR39(VAR27),
.VAR28(VAR9[VAR54]),
.VAR46(VAR14[VAR54][511:0]),
.VAR38(VAR56[VAR54]),
.VAR36(VAR15[VAR54]),
.VAR49(VAR34[VAR54]),
.VAR32(VAR24[(VAR54+1)*16-1:VAR54*16])
);
VAR64
VAR22 (
.VAR10(VAR12),
.VAR53(clk),
.VAR4(~VAR58),
.VAR44(VAR34[VAR54]),
.VAR51(VAR15[VAR54]),
.VAR31(),
.VAR50(VAR62[VAR54]),
.VAR17(VAR55[VAR54]),
.VAR16(VAR63[VAR54])
);
assign VAR63[VAR54] = VAR42==VAR54 ? VAR41 : 0;
end
endgenerate
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41ai/sky130_fd_sc_hd__o41ai.behavioral.pp.v | 2,059 | module MODULE1 (
VAR12 ,
VAR16 ,
VAR4 ,
VAR9 ,
VAR17 ,
VAR2 ,
VAR15,
VAR18,
VAR3 ,
VAR1
);
output VAR12 ;
input VAR16 ;
input VAR4 ;
input VAR9 ;
input VAR17 ;
input VAR2 ;
input VAR15;
input VAR18;
input VAR3 ;
input VAR1 ;
wire VAR8 ;
wire VAR5 ;
wire VAR13;
or VAR7 (VAR8 , VAR17, VAR9, VAR4, VAR16 );
nand VAR6 (VAR5 , VAR2, VAR8 );
VAR14 VAR10 (VAR13, VAR5, VAR15, VAR18);
buf VAR11 (VAR12 , VAR13 );
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/ctrl.v | 7,960 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR18] VAR50, output reg [VAR32] VAR45, output reg [VAR39] VAR29,
input wire [VAR25-1:0] irq, output reg VAR11,
input wire [VAR27] VAR22,
input wire [VAR27] VAR30, input wire VAR55, input wire VAR23, input wire [VAR35] VAR40, input wire [VAR18] VAR9, input wire [VAR44] VAR36, input wire [VAR32] VAR2,
input wire VAR41, input wire VAR37, input wire VAR8, output wire VAR14, output wire VAR12, output wire VAR10, output wire VAR52, output wire VAR17, output wire VAR21, output wire VAR51, output wire VAR49, output reg [VAR27] VAR28 );
reg VAR7; reg [VAR39] VAR13; reg VAR54; reg [VAR27] VAR33; reg [VAR27] VAR19; reg [VAR44] VAR31; reg VAR16; reg [VAR25-1:0] VAR53;
reg [VAR27] VAR48; reg VAR1;
wire VAR46 = VAR41 | VAR8;
assign VAR14 = VAR46 | VAR37;
assign VAR12 = VAR46;
assign VAR10 = VAR46;
assign VAR52 = VAR46;
reg VAR47;
assign VAR17 = VAR47;
assign VAR21 = VAR47 | VAR37;
assign VAR51 = VAR47;
assign VAR49 = VAR47;
always @ begin
if ((VAR7 == VAR38) && ((|((~VAR53) & irq)) == VAR38)) begin
VAR11 = VAR38;
end else begin
VAR11 = VAR4;
end
end
always @(*) begin
case (VAR50)
end
VAR54, VAR13};
end
end
end
end
VAR16, VAR31};
end
end
end
end
end
end
default : begin VAR45 = VAR34'h0;
end
endcase
end
always @(posedge clk or VAR43 reset) begin
if (reset == VAR3) begin
VAR29 <= VAR15;
VAR7 <= VAR4;
VAR13 <= VAR15;
VAR54 <= VAR4;
VAR31 <= VAR6;
VAR53 <= {VAR25{VAR38}};
VAR16 <= VAR4;
VAR33 <= VAR24'h0;
VAR19 <= VAR24'h0;
VAR48 <= VAR24'h0;
VAR1 <= VAR4;
end else begin
if ((VAR55 == VAR38) && (VAR46 == VAR4)) begin
VAR48 <= VAR30;
VAR1 <= VAR23;
if (VAR36 != VAR6) begin VAR29 <= VAR15;
VAR7 <= VAR4;
VAR13 <= VAR29;
VAR54 <= VAR7;
VAR31 <= VAR36;
VAR16 <= VAR1;
VAR33 <= VAR48;
end else if (VAR40 == VAR20) begin VAR29 <= VAR13;
VAR7 <= VAR54;
end else if (VAR40 == VAR5) begin
case (VAR9)
VAR7 <= VAR2[VAR26];
end
VAR54 <= VAR2[VAR26];
end
end
end
VAR31 <= VAR2[VAR42];
end
end
endcase
end
end
end
end
endmodule | apache-2.0 |
Iuliiapl/schoolMIPS | board/nexys4/nexys4.v | 1,956 | module MODULE1
(
input clk,
input VAR6,
input VAR35,
input VAR14,
input VAR31,
input VAR25,
input VAR2,
input [15:0] VAR27,
output [15:0] VAR17,
output VAR19,
output VAR29,
output VAR26,
output VAR12,
output VAR16,
output VAR10,
output [ 6:0] VAR39,
output VAR8,
output [ 7:0] VAR28,
inout [ 7:0] VAR22,
inout [ 7:0] VAR1,
input VAR24
);
wire VAR36;
wire VAR23 = clk;
wire VAR20 = VAR6;
wire VAR13 = VAR27 [9] | VAR14;
wire [ 3:0 ] VAR41 = VAR27 [8:5];
wire [ 4:0 ] VAR3 = VAR27 [4:0];
wire [ 31:0 ] VAR30;
VAR32 VAR32
(
.VAR23 ( VAR23 ),
.VAR20 ( VAR20 ),
.VAR41 ( VAR41 ),
.VAR13 ( VAR13 ),
.clk ( VAR36 ),
.VAR3 ( VAR3 ),
.VAR30 ( VAR30 )
);
assign VAR17[0] = VAR36;
assign VAR17[15:1] = VAR30[14:0];
wire [ 31:0 ] VAR11 = VAR30;
wire VAR4;
VAR9 VAR40
(
.VAR23 ( VAR23 ),
.VAR20 ( VAR20 ),
.VAR21 ( 4'b1 ),
.enable ( 1'b1 ),
.VAR5 ( VAR4 )
);
VAR38 VAR38
(
.VAR33 ( VAR4 ),
.VAR15 ( VAR20 ),
.VAR7 ( VAR11 ),
.VAR18 ( VAR39 ),
.VAR34 ( VAR8 ),
.VAR37 ( VAR28 )
);
assign VAR19 = 1'b0;
assign VAR29 = 1'b0;
assign VAR26 = 1'b0;
assign VAR12 = 1'b0;
assign VAR16 = 1'b0;
assign VAR10 = 1'b0;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufinv/sky130_fd_sc_ls__bufinv.behavioral.pp.v | 1,782 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR12,
VAR2,
VAR8 ,
VAR5
);
output VAR1 ;
input VAR4 ;
input VAR12;
input VAR2;
input VAR8 ;
input VAR5 ;
wire VAR6 ;
wire VAR11;
not VAR10 (VAR6 , VAR4 );
VAR3 VAR9 (VAR11, VAR6, VAR12, VAR2);
buf VAR7 (VAR1 , VAR11 );
endmodule | apache-2.0 |
r2apu/Labo_Digitales | L3/LCD.v | 19,840 | module MODULE1
(
input wire VAR19,
input wire VAR29,
output wire VAR40,
output reg VAR43, output wire VAR45,
output wire VAR9,
input wire VAR39;
input wire[7:0] VAR34;
output reg VAR11;
output reg VAR3;
output reg[3:0] VAR33
);
reg VAR48 ;
assign VAR40 = VAR48 ;
assign VAR9 = 0; assign VAR45 = 1; reg [7:0] VAR37,VAR23;
reg [31:0] VAR32;
reg VAR7;
reg[4:0]VAR30;
reg VAR5;
always @ ( posedge VAR19 )
if (VAR29)
begin
VAR37 <= VAR38;
VAR32 <= 32'b0;
end
else
begin
begin
if(~VAR5)
VAR30<= 4'b0;
end
else
VAR30 <= VAR30 + 4'b1;
end
begin
if (VAR7)
VAR32 <= 32'b0;
end
else
VAR32 <= VAR32 + 32'b1;
VAR37 <= VAR23;
end
end
always @ ( * )
begin
case (VAR37)
begin
VAR48 = 1'b0;
VAR33 = 4'h0;
VAR43 = 1'b0;
VAR7 = 1'b0;
VAR23 = VAR35;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h0;
VAR43 = 1'b0; if (VAR32 > 32'd750000 )
begin
VAR7 = 1'b1;
VAR23 = VAR53;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR35;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'h3;
VAR5=1'b1;
VAR43 = 1'b0; VAR7 = 1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR47;
end
else
VAR23 = VAR53;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd205000 )
begin
VAR7 = 1'b1;
VAR23 = VAR50;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR47;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'h3;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR31;
end
else
VAR23 = VAR50;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd5000 )
begin
VAR7 = 1'b1;
VAR23 = VAR16;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR31;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'h3;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR46;
end
else
VAR23 = VAR16;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd2000 )
begin
VAR7 = 1'b1;
VAR23 = VAR4;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR46;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'h2;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR14;
end
else
VAR23 = VAR4;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd2000 )
begin
VAR7 = 1'b1;
VAR23 = VAR27;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR14;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'd2;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR25;
end
else
VAR23 = VAR27;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd50 )
begin
VAR7 = 1'b1;
VAR23 = VAR15;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR25;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'd8;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR6;
end
else
VAR23 = VAR15;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd2000 )
begin
VAR7 = 1'b1;
VAR23 = VAR2;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR6;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'b0;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR52;
end
else
VAR23 = VAR2;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd50)
begin
VAR7 = 1'b1;
VAR23 = VAR8;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR52;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'd6;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR21;
end
else
VAR23 = VAR8;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd2000 )
begin
VAR7 = 1'b1;
VAR23 = VAR28;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR21;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'b0;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR42;
end
else
VAR23 = VAR28;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd50 )
begin
VAR7 = 1'b1;
VAR23 = VAR10;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR42;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'hC;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR22;
end
else
VAR23 = VAR10;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd2000 )
begin
VAR7 = 1'b1;
VAR23 = VAR26;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR22;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'b0;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR1;
end
else
VAR23 = VAR26;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd50 )
begin
VAR7 = 1'b1;
VAR23 = VAR20;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR1;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'b1;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR18;
end
else
VAR23 = VAR20;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd82000 )
begin
VAR7 = 1'b1;
VAR23 = VAR13;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR18;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'd8;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR17;
end
else
VAR23 = VAR13;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd50 )
begin
VAR7 = 1'b1;
VAR23 = VAR41;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR17;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'b0;
VAR43 = 1'b0; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR44;
end
else
VAR23 = VAR41;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd2000 )
begin
VAR7 = 1'b1;
VAR23 = VAR36;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR44;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'd4;
VAR43 = 1'b1; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR51;
end
else
VAR23 = VAR36;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd50 )
begin
VAR7 = 1'b1;
VAR23 = VAR49;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR51;
VAR5=1'b1;
end
end
begin
VAR48 = 1'b1;
VAR33 = 4'd8;
VAR43 = 1'b1; VAR7 = 1'b1;
VAR5=1'b1;
if ( VAR30 >4'd12 )
VAR23 = VAR12;
end
else
VAR23 = VAR49;
end
begin
VAR48 = 1'b0;
VAR33 = 4'h3;
VAR43 = 1'b0; if (VAR32 > 32'd2000 )
begin
VAR7 = 1'b1;
VAR23 = VAR24;
VAR5=1'b0;
end
else
begin
VAR7 = 1'b0;
VAR23 = VAR12;
VAR5=1'b1;
end
end
default:
begin
VAR48 = 1'b0;
VAR33 = 4'h2;
VAR43 = 1'b0;
VAR7 = 1'b0;
VAR23 = VAR38;
end
endcase
end
endmodule | gpl-3.0 |
shangdawei/proxmark3-lcd | fpga/hi_iso14443a.v | 8,618 | module MODULE1(
VAR5, VAR46, VAR26,
VAR22, VAR27, VAR47, VAR4, VAR55, VAR40,
VAR7, VAR30,
VAR21, VAR6, VAR49, VAR52,
VAR44, VAR45,
VAR8,
VAR53
);
input VAR5, VAR46, VAR26;
output VAR22, VAR27, VAR47, VAR4, VAR55, VAR40;
input [7:0] VAR7;
output VAR30;
input VAR49;
output VAR21, VAR6, VAR52;
input VAR44, VAR45;
output VAR8;
input [2:0] VAR53;
reg VAR52;
reg VAR21;
reg VAR35;
always @(posedge VAR46)
VAR35 = ~VAR35;
wire VAR30;
assign VAR30 = VAR46;
reg VAR41, VAR18, VAR3, VAR20;
reg [11:0] VAR54;
reg [8:0] VAR16;
reg [2:0] VAR9;
reg VAR12;
always @(negedge VAR30)
begin
if(& VAR7[7:6]) VAR41 <= 1'b1;
end
else if(~(| VAR7[7:4])) VAR41 <= 1'b0;
if(~(| VAR7[7:0]))
begin
if(VAR9 == 3'd7)
begin
VAR12 <= 1'b1;
VAR16 <= 8'd0;
end
else
VAR9 <= VAR9 + 1;
end
else
begin
VAR9 <= 3'd0;
if(VAR16 == 8'd255)
VAR12 <= 1'b0;
end
else
VAR16 <= VAR16 + 1;
end
if(VAR41)
begin
VAR54 <= 7'b0;
end
else
begin
if(VAR54 == 12'd4095)
begin
VAR54 <= 12'd0;
VAR41 <= 1'b1;
end
else
VAR54 <= VAR54 + 1;
end
end
reg [5:0] VAR32;
reg VAR42, VAR14, VAR19;
reg [3:0] VAR13;
reg [3:0] VAR15;
wire [7:0] VAR11;
reg [7:0] VAR50;
reg signed [12:0] VAR38;
reg signed [12:0] VAR25;
reg [7:0] VAR2;
reg VAR28;
reg [12:0] VAR1;
wire signed [9:0] VAR24;
reg signed [7:0] VAR56;
assign VAR11[7:0] = VAR1[11:4];
assign VAR24 = VAR50 - VAR11;
reg VAR29;
reg VAR23, VAR33;
reg [10:0] VAR57;
reg [47:0] VAR48;
wire VAR43;
reg [5:0] VAR10;
reg [3:0] VAR39;
reg VAR36, VAR31;
reg VAR17;
reg VAR51;
assign VAR43 = ~(|VAR48[47:0]);
reg [2:0] VAR37;
always @(negedge VAR30)
begin
if(VAR57 == 11'd740) VAR23 = 1'b1;
if(VAR57 == 11'd1148)
begin
if(VAR33)
begin
if(VAR32[3:0] == VAR39[3:0]) VAR31 <= VAR36;
end
else
begin
VAR39[3:0] <= VAR32[3:0];
VAR31 <= VAR36;
VAR33 = 1'b1;
VAR23 = 1'b0;
if(~(| VAR10[5:0])) VAR10 <= 6'b001001;
end
else VAR17 = 1'b1; end
end
else
begin
VAR57 <= VAR57 + 1;
end
if(& VAR32[3:0])
begin
if(~VAR41 && VAR43 && ~((VAR53 == 3'b100) || (VAR53 == 3'b011) || (VAR53 == 3'b010))) begin
VAR57 <= 11'd0;
VAR33 = 1'b0;
VAR23 = 1'b0;
VAR17 = 1'b0;
VAR10 <= 6'b000000;
end
VAR50 <= VAR11;
if(VAR2<16) VAR2 = 8'd16;
if(VAR24>0)
begin
VAR38 = VAR24*3;
VAR25 = VAR2*2; if(VAR38>VAR25)
begin
VAR28 = 1'b0;
VAR2 = VAR24;
end
end
else
begin
VAR38 = VAR24*3;
VAR38 = -VAR38;
VAR25 = VAR2*2;
if(VAR38>VAR25)
begin
VAR28 = 1'b1;
VAR2 = -VAR24;
end
end
if(VAR28)
begin
VAR15 <= 4'd0;
if(& VAR13[3:2])
begin
VAR28 = 1'b0; VAR2 = 8'd24; end
else
begin
VAR13 <= VAR13 + 1;
end
end
else
begin
VAR13 <= 4'd0;
if(& VAR15[3:0])
begin
VAR2 = 8'd24;
end
else
begin
VAR15 <= VAR15 + 1;
end
end
if(VAR53 == 3'b001) VAR51 = VAR41;
end
else if(VAR53 == 3'b010)
begin
if(VAR57 > 11'd772) VAR51 = VAR31;
end
else VAR51 = VAR23;
end
else if(VAR53 == 3'b011) VAR51 = VAR28;
else VAR51 = 1'b0;
end
if(~(| VAR32[3:0])) VAR1 <= VAR7;
else VAR1 <= VAR1 + VAR7;
if(VAR32 == 7'd63)
begin
if(VAR12)
begin
VAR56 <= {VAR18,VAR3,VAR20,VAR41,1'b0,1'b0,1'b0,1'b0};
end
else
begin
VAR56 <= {VAR18,VAR3,VAR20,VAR41,VAR42,VAR14,VAR19,VAR28};
end
VAR32 <= 0;
end
else
begin
VAR32 <= VAR32 + 1;
end
if(VAR32 == 6'd15)
begin
VAR18 <= VAR41;
VAR42 <= VAR28;
end
if(VAR32 == 6'd31)
begin
VAR3 <= VAR41;
VAR14 <= VAR28;
end
if(VAR32 == 6'd47)
begin
VAR20 <= VAR41;
VAR19 <= VAR28;
end
if(VAR53 != 3'b000)
begin
if(VAR32[3:0] == 4'b1000)
begin
VAR48[47:0] <= {VAR48[46:1], VAR49, 1'b0};
if((VAR49 || (| VAR10[5:0])) && ~VAR33)
if(VAR10 == 6'b101110)
begin
VAR10 <= 6'b000000;
end
else VAR10 <= VAR10 + 1;
end
else if(VAR33 && ~VAR17)
begin
if(VAR49) VAR17 = 1'b1;
if(VAR10 == 6'b000010) VAR10 <= 6'b001001;
end
else VAR10 <= VAR10 - 1;
end
else
begin
if(~VAR48[VAR10-1] && ~VAR48[VAR10+1]) VAR36 = 1'b0;
end
else VAR36 = VAR48[VAR10] & VAR33; end
end
end
if(VAR53 == 3'b000)
begin
if(VAR32[2:0] == 3'b100)
VAR52 <= 1'b0;
if(VAR32[2:0] == 3'b000)
begin
VAR52 <= 1'b1;
if(VAR32 != 7'd0)
begin
VAR56[7:1] <= VAR56[6:0];
end
end
if(VAR32[5:4] == 2'b00)
VAR21 = 1'b1;
end
else
VAR21 = 1'b0;
VAR29 = VAR56[7];
end
else
begin
if(VAR32[3:0] == 4'b1000) VAR52 <= 1'b0;
if(VAR32[3:0] == 4'b0111)
begin
if(VAR37 == 3'd7) VAR37 <= 3'd0;
end
else VAR37 <= VAR37 + 1;
end
if(VAR32[3:0] == 4'b0000)
begin
VAR52 <= 1'b1;
end
VAR21 = (VAR37 == 3'd7);
VAR29 = VAR51;
end
end
assign VAR6 = VAR29;
wire VAR34;
assign VAR34 = (VAR31 & VAR32[3] & (VAR53 == 3'b010));
assign VAR27 = (VAR26 & (((VAR53 == 3'b100) & ~VAR31) || (VAR53 == 3'b011)));
assign VAR4 = 1'b0;
assign VAR47 = 1'b0;
assign VAR40 = VAR34;
assign VAR55 = 1'b0;
assign VAR8 = VAR32[3];
assign VAR22 = 1'b0;
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_2.behavioral.v | 1,093 | module MODULE1( VAR1, VAR5 );
input VAR1;
output VAR5;
VAR4 VAR2(.VAR1(VAR1),.VAR5(VAR5));
VAR4 VAR3(.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_approximate/integracion_fisica/front_end/source/GDA_dyn_N16_M4.v | 3,795 | module MODULE1(
input [15:0] VAR57,
input [15:0] VAR105,
input [ 2:0] VAR47,
input VAR113,
input [ 1:0] VAR29,
input [ 2:0] VAR64,
output [16:0] VAR108
);
wire [4:0] VAR31, VAR102, VAR55, VAR17;
wire VAR98,VAR92,VAR87;
wire VAR70,VAR100,VAR49,VAR94,VAR19,VAR95,VAR74,VAR82;
wire VAR30,VAR91,VAR35,VAR41,VAR20;
wire VAR45, VAR50;
wire VAR67;
and VAR69(VAR94,VAR57[3],VAR105[3]);
and VAR3(VAR49,VAR57[2],VAR105[2]);
and VAR26(VAR100,VAR57[1],VAR105[1]);
and VAR60(VAR70,VAR57[0],VAR105[0]);
xor VAR89(VAR82,VAR57[3],VAR105[3]);
xor VAR115(VAR74,VAR57[2],VAR105[2]);
xor VAR114(VAR95,VAR57[1],VAR105[1]);
xor VAR125(VAR19,VAR57[0],VAR105[0]);
and VAR83(VAR30,VAR82,VAR49);
and VAR56(VAR91,VAR82,VAR74);
and VAR1(VAR35,VAR91,VAR100);
and VAR65(VAR41,VAR91,VAR95);
and VAR51(VAR20,VAR41,VAR70);
or VAR36(VAR45,VAR94,VAR30);
or VAR111(VAR50,VAR35,VAR20);
or VAR9(VAR67,VAR45,VAR50);
wire VAR24,VAR39,VAR126,VAR124,VAR61,VAR22,VAR12,VAR16;
wire VAR5,VAR8,VAR90,VAR106,VAR96,VAR77,VAR59;
wire VAR116, VAR13;
wire VAR7,VAR42,VAR118;
and VAR121 (VAR124,VAR57[7],VAR105[7]);
and VAR85(VAR126,VAR57[6],VAR105[6]);
and VAR25(VAR39,VAR57[5],VAR105[5]);
and VAR21(VAR24,VAR57[4],VAR105[4]);
xor VAR34(VAR16,VAR57[7],VAR105[7]);
xor VAR48(VAR12,VAR57[6],VAR105[6]);
xor VAR23(VAR22,VAR57[5],VAR105[5]);
xor VAR119(VAR61,VAR57[4],VAR105[4]);
and VAR18(VAR5,VAR16,VAR126);
and VAR88(VAR8,VAR16,VAR12);
and VAR37(VAR90,VAR8,VAR39);
and VAR103(VAR106,VAR8,VAR22);
and VAR73(VAR96,VAR106,VAR24);
or VAR110(VAR116,VAR124,VAR5);
or VAR72(VAR13,VAR90,VAR96);
or VAR15(VAR7,VAR116,VAR13);
and VAR75(VAR77,VAR106,VAR61);
and VAR81(VAR59,VAR77,VAR67);
assign VAR42 = VAR29[0]?VAR7:1'b0;
assign VAR118 = VAR29[1]?VAR59:1'b0;
wire VAR53,VAR78,VAR104,VAR71,VAR97,VAR76,VAR86,VAR40;
wire VAR80,VAR120,VAR107,VAR62,VAR28,VAR122,VAR52;
wire VAR2, VAR63;
wire VAR127,VAR4,VAR6,VAR38,VAR46;
and VAR33(VAR71,VAR57[11],VAR105[11]);
and VAR101(VAR104,VAR57[10],VAR105[10]);
and VAR44(VAR78,VAR57[9],VAR105[9]);
and VAR11(VAR53,VAR57[8],VAR105[8]);
xor VAR129(VAR40,VAR57[11],VAR105[11]);
xor VAR112(VAR86,VAR57[10],VAR105[10]);
xor VAR84(VAR76,VAR57[9],VAR105[9]);
xor VAR117(VAR97,VAR57[8],VAR105[8]);
and VAR14(VAR80,VAR40,VAR104);
and VAR79(VAR120,VAR40,VAR86);
and VAR123(VAR107,VAR120,VAR78);
and VAR99(VAR62,VAR120,VAR76);
and VAR68(VAR28,VAR62,VAR53);
or VAR66(VAR2,VAR71,VAR80);
or VAR43(VAR63,VAR107,VAR28);
or VAR27(VAR127,VAR2,VAR63);
and VAR32(VAR109,VAR62,VAR97);
and VAR93(VAR122,VAR109,VAR7);
and VAR128(VAR52,VAR109,VAR59);
assign VAR4 = VAR64[0]?VAR127:1'b0;
assign VAR6 = VAR64[1]?VAR122:1'b0;
assign VAR46 = VAR64[2]?VAR52:1'b0;
assign VAR98 = VAR113?VAR67:1'b0;
or VAR54(VAR92,VAR42,VAR118);
or VAR58(VAR38,VAR4,VAR6);
or VAR10(VAR87,VAR38,VAR46);
assign VAR31[4:0] = VAR57[ 3: 0] + VAR105[ 3: 0];
assign VAR102[4:0] = VAR57[ 7: 4] + VAR105[ 7: 4] + {VAR47[0]?VAR31[4]:VAR98};
assign VAR55[4:0] = VAR57[11: 8] + VAR105[11: 8] + {VAR47[1]?VAR102[4]:VAR92};
assign VAR17[4:0] = VAR57[15:12] + VAR105[15:12] + {VAR47[2]?VAR55[4]:VAR87};
assign VAR108[16:0] = {VAR17[4:0],VAR55[3:0],VAR102[3:0],VAR31[3:0]};
endmodule | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/src/stubs/hdl/fifo_async_103x16.v | 1,617 | module MODULE1(rst, VAR3, VAR1, din, VAR7, VAR4, dout, VAR5, VAR2, VAR6)
;
input rst;
input VAR3;
input VAR1;
input [102:0]din;
input VAR7;
input VAR4;
output [102:0]dout;
output VAR5;
output VAR2;
output VAR6;
assign VAR2 =1'b0;
assign VAR6 =1'b0;
assign dout[102:0] =103'b0;
assign VAR5 =1'b0;
endmodule | gpl-3.0 |
Digilent/vivado-library | ip/Pmods/PmodCOLOR_v1_0/src/PmodCOLOR.v | 13,693 | module MODULE1
(VAR16,
VAR210,
VAR47,
VAR175,
VAR108,
VAR7,
VAR67,
VAR54,
VAR115,
VAR198,
VAR202,
VAR134,
VAR129,
VAR152,
VAR144,
VAR43,
VAR133,
VAR156,
VAR45,
VAR85,
VAR80,
VAR71,
VAR170,
VAR189,
VAR94,
VAR121,
VAR27,
VAR102,
VAR35,
VAR125,
VAR169,
VAR68,
VAR3,
VAR128,
VAR10,
VAR95,
VAR163,
VAR58,
VAR52,
VAR4,
VAR188,
VAR92,
VAR40,
VAR73,
VAR151,
VAR28,
VAR180,
VAR24,
VAR1,
VAR42,
VAR136,
VAR2,
VAR101,
VAR110,
VAR46,
VAR185,
VAR143,
VAR78,
VAR147,
VAR150,
VAR211,
VAR72);
input [8:0]VAR16;
output VAR210;
input VAR47;
input [8:0]VAR175;
output VAR108;
input VAR7;
input VAR67;
output [1:0]VAR54;
output VAR115;
output [31:0]VAR198;
input VAR202;
output [1:0]VAR134;
output VAR129;
input [31:0]VAR152;
output VAR144;
input [3:0]VAR43;
input VAR133;
input [8:0]VAR156;
output VAR45;
input VAR85;
input [8:0]VAR80;
output VAR71;
input VAR170;
input VAR189;
output [1:0]VAR94;
output VAR121;
output [31:0]VAR27;
input VAR102;
output [1:0]VAR35;
output VAR125;
input [31:0]VAR169;
output VAR68;
input [3:0]VAR3;
input VAR128;
input VAR10;
output VAR95;
output VAR163;
input VAR58;
output VAR52;
output VAR4;
input VAR188;
output VAR92;
output VAR40;
input VAR73;
output VAR151;
output VAR28;
input VAR180;
output VAR24;
output VAR1;
input VAR42;
output VAR136;
output VAR2;
input VAR101;
output VAR110;
output VAR46;
input VAR185;
output VAR143;
output VAR78;
output VAR147;
output VAR150;
input VAR211;
input VAR72;
wire [8:0]VAR157;
wire VAR22;
wire VAR61;
wire [8:0]VAR88;
wire VAR209;
wire VAR190;
wire VAR60;
wire [1:0]VAR31;
wire VAR126;
wire [31:0]VAR76;
wire VAR167;
wire [1:0]VAR12;
wire VAR21;
wire [31:0]VAR97;
wire VAR17;
wire [3:0]VAR37;
wire VAR79;
wire [8:0]VAR168;
wire VAR203;
wire VAR14;
wire [8:0]VAR183;
wire VAR148;
wire VAR56;
wire VAR63;
wire [1:0]VAR30;
wire VAR191;
wire [31:0]VAR196;
wire VAR154;
wire [1:0]VAR119;
wire VAR83;
wire [31:0]VAR182;
wire VAR159;
wire [3:0]VAR13;
wire VAR66;
wire [1:0]VAR181;
wire [1:0]VAR172;
wire VAR90;
wire VAR114;
wire VAR38;
wire VAR117;
wire VAR127;
wire VAR5;
wire VAR19;
wire VAR161;
wire VAR145;
wire VAR15;
wire VAR89;
wire VAR77;
wire VAR29;
wire VAR26;
wire VAR33;
wire VAR192;
wire VAR199;
wire VAR195;
wire VAR50;
wire VAR146;
wire VAR112;
wire VAR131;
wire VAR184;
wire VAR41;
wire VAR123;
wire VAR149;
wire VAR135;
wire VAR158;
wire VAR107;
wire VAR178;
wire [3:0]VAR64;
wire [1:0]VAR84;
wire [3:0]VAR166;
wire [3:0]VAR70;
wire VAR109;
wire VAR6;
wire [0:0]VAR48;
wire [0:0]VAR87;
assign VAR210 = VAR203;
assign VAR108 = VAR148;
assign VAR54[1:0] = VAR30;
assign VAR115 = VAR191;
assign VAR198[31:0] = VAR196;
assign VAR134[1:0] = VAR119;
assign VAR129 = VAR83;
assign VAR144 = VAR159;
assign VAR45 = VAR22;
assign VAR71 = VAR209;
assign VAR94[1:0] = VAR31;
assign VAR121 = VAR126;
assign VAR27[31:0] = VAR76;
assign VAR35[1:0] = VAR12;
assign VAR125 = VAR21;
assign VAR68 = VAR17;
assign VAR95 = VAR161;
assign VAR163 = VAR145;
assign VAR52 = VAR89;
assign VAR4 = VAR77;
assign VAR92 = VAR26;
assign VAR40 = VAR33;
assign VAR151 = VAR199;
assign VAR28 = VAR195;
assign VAR24 = VAR146;
assign VAR1 = VAR112;
assign VAR136 = VAR184;
assign VAR2 = VAR41;
assign VAR110 = VAR149;
assign VAR46 = VAR135;
assign VAR143 = VAR107;
assign VAR78 = VAR178;
assign VAR157 = VAR156[8:0];
assign VAR61 = VAR85;
assign VAR88 = VAR80[8:0];
assign VAR190 = VAR170;
assign VAR60 = VAR189;
assign VAR167 = VAR102;
assign VAR97 = VAR169[31:0];
assign VAR37 = VAR3[3:0];
assign VAR79 = VAR128;
assign VAR168 = VAR16[8:0];
assign VAR14 = VAR47;
assign VAR183 = VAR175[8:0];
assign VAR56 = VAR7;
assign VAR63 = VAR67;
assign VAR154 = VAR202;
assign VAR182 = VAR152[31:0];
assign VAR13 = VAR43[3:0];
assign VAR66 = VAR133;
assign VAR147 = VAR90;
assign VAR150 = VAR114;
assign VAR19 = VAR10;
assign VAR15 = VAR58;
assign VAR29 = VAR188;
assign VAR192 = VAR73;
assign VAR50 = VAR180;
assign VAR131 = VAR42;
assign VAR123 = VAR101;
assign VAR158 = VAR185;
assign VAR109 = VAR211;
assign VAR6 = VAR72;
VAR18 VAR124
(.VAR74(VAR84),
.VAR44(VAR181),
.VAR171(VAR172),
.VAR206(VAR90),
.VAR211(VAR109),
.VAR160(VAR168),
.VAR72(VAR6),
.VAR32(VAR203),
.VAR193(VAR14),
.VAR20(VAR183),
.VAR139(VAR148),
.VAR93(VAR56),
.VAR116(VAR63),
.VAR179(VAR30),
.VAR120(VAR191),
.VAR118(VAR196),
.VAR23(VAR154),
.VAR106(VAR119),
.VAR98(VAR83),
.VAR99(VAR182),
.VAR86(VAR159),
.VAR65(VAR13),
.VAR104(VAR66));
VAR204 VAR113
(.VAR75(VAR114),
.VAR211(VAR109),
.VAR160(VAR157),
.VAR72(VAR6),
.VAR32(VAR22),
.VAR193(VAR61),
.VAR20(VAR88),
.VAR139(VAR209),
.VAR93(VAR190),
.VAR116(VAR60),
.VAR179(VAR31),
.VAR120(VAR126),
.VAR118(VAR76),
.VAR23(VAR167),
.VAR106(VAR12),
.VAR98(VAR21),
.VAR99(VAR97),
.VAR86(VAR17),
.VAR65(VAR37),
.VAR104(VAR79),
.VAR34(VAR48),
.VAR177(VAR38),
.VAR197(VAR117),
.VAR103(VAR87),
.VAR187(VAR127),
.VAR212(VAR5));
VAR62 VAR141
(.VAR36(VAR64),
.VAR57(VAR166),
.VAR200(VAR70),
.VAR153(VAR15),
.VAR176(VAR89),
.VAR51(VAR77),
.VAR59(VAR29),
.VAR91(VAR26),
.VAR55(VAR33),
.VAR49(VAR192),
.VAR8(VAR199),
.VAR111(VAR195),
.VAR201(VAR50),
.VAR173(VAR146),
.VAR194(VAR112),
.VAR155(VAR131),
.VAR81(VAR184),
.VAR186(VAR41),
.VAR11(VAR123),
.VAR162(VAR149),
.VAR165(VAR135),
.VAR208(VAR158),
.VAR82(VAR107),
.VAR9(VAR178),
.VAR96(VAR19),
.VAR69(VAR161),
.VAR105(VAR145));
VAR207 VAR205
(.VAR140(VAR64),
.VAR164(VAR84));
VAR130 VAR100
(.VAR132(VAR181),
.VAR25(VAR38),
.VAR138(VAR127),
.dout(VAR166));
VAR142 VAR174
(.VAR132(VAR172),
.VAR25(VAR117),
.VAR138(VAR5),
.dout(VAR70));
VAR122 VAR53
(.VAR140(VAR64),
.VAR164(VAR48));
VAR39 VAR137
(.VAR140(VAR64),
.VAR164(VAR87));
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21bai/sky130_fd_sc_ls__o21bai.blackbox.v | 1,389 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR7 ,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR5;
supply1 VAR8;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111oi/sky130_fd_sc_ls__a2111oi.pp.symbol.v | 1,408 | module MODULE1 (
input VAR1 ,
input VAR7 ,
input VAR3 ,
input VAR6 ,
input VAR10 ,
output VAR5 ,
input VAR2 ,
input VAR8,
input VAR4,
input VAR9
);
endmodule | apache-2.0 |
andykarpov/radio-86rk-wxeda | src/dma/k580wt57.v | 3,779 | module MODULE1(
input clk,
input VAR23,
input reset,
input[3:0] VAR7,
input[7:0] VAR5,
input[3:0] VAR17,
input VAR19,
input VAR6,
input VAR18,
output VAR20,
output reg[3:0] VAR3,
output[7:0] VAR26,
output[15:0] VAR12,
output VAR14,
output VAR25,
output VAR32,
output VAR16 );
parameter VAR13 = 3'b000;
parameter VAR21 = 3'b001;
parameter VAR31 = 3'b010;
parameter VAR28 = 3'b011;
parameter VAR10 = 3'b100;
parameter VAR8 = 3'b101;
parameter VAR9 = 3'b110;
parameter VAR1 = 3'b111;
reg[2:0] state;
reg[1:0] VAR27;
reg[7:0] VAR15;
reg[4:0] VAR30;
reg[15:0] VAR2[3:0];
reg[15:0] VAR33[3:0];
reg VAR4,VAR24;
assign VAR20 = state!=VAR13;
assign VAR26 = {3'b0,VAR30};
assign VAR12 = VAR2[VAR27];
assign VAR14 = VAR33[VAR27][14]==0 || state!=VAR28;
assign VAR25 = VAR33[VAR27][15]==0 || (state!=VAR31 && state!=VAR28);
assign VAR32 = VAR33[VAR27][15]==0 || state!=VAR28;
assign VAR16 = VAR33[VAR27][14]==0 || (state!=VAR31 && state!=VAR28);
wire[3:0] VAR22 = VAR17 & VAR15[3:0];
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 0; VAR4 <= 0; VAR15 <= 0; VAR24 <= 1'b1;
VAR30 <= 0; VAR3 <= 0;
end else begin
VAR24 <= VAR19;
if (VAR19 && ~VAR24) begin
VAR4 <= ~(VAR4|VAR7[3]);
if (VAR4) begin
if(VAR7==4'b0000) VAR2[0][15:8] <= VAR5;
if(VAR7==4'b0001) VAR33[0][15:8] <= VAR5;
if(VAR7==4'b0010) VAR2[1][15:8] <= VAR5;
if(VAR7==4'b0011) VAR33[1][15:8] <= VAR5;
if(VAR7==4'b0100) VAR2[2][15:8] <= VAR5;
if(VAR7==4'b0101) VAR33[2][15:8] <= VAR5;
if(VAR7==4'b0110 || (VAR7==4'b0100 && VAR15[7]==1'b1)) VAR2[3][15:8] <= VAR5;
if(VAR7==4'b0111 || (VAR7==4'b0101 && VAR15[7]==1'b1)) VAR33[3][15:8] <= VAR5;
end else begin
if(VAR7==4'b0000) VAR2[0][7:0] <= VAR5;
if(VAR7==4'b0001) VAR33[0][7:0] <= VAR5;
if(VAR7==4'b0010) VAR2[1][7:0] <= VAR5;
if(VAR7==4'b0011) VAR33[1][7:0] <= VAR5;
if(VAR7==4'b0100) VAR2[2][7:0] <= VAR5;
if(VAR7==4'b0101) VAR33[2][7:0] <= VAR5;
if(VAR7==4'b0110 || (VAR7==4'b0100 && VAR15[7]==1'b1)) VAR2[3][7:0] <= VAR5;
if(VAR7==4'b0111 || (VAR7==4'b0101 && VAR15[7]==1'b1)) VAR33[3][7:0] <= VAR5;
end
if (VAR7[3]) VAR15 <= VAR5;
end
if (VAR23) begin
case (state)
VAR13: begin
if (|VAR22) state <= VAR21;
end
VAR21: begin
if (VAR18) state <= VAR31;
casex (VAR22[3:1])
3'VAR29: VAR27 <= 2'b11;
3'VAR11: VAR27 <= 2'b10;
3'b001: VAR27 <= 2'b01;
3'b000: VAR27 <= 2'b00;
endcase
end
VAR31: begin
state <= VAR28;
VAR3[VAR27] <= 1'b1;
end
VAR28: begin
if (VAR22[VAR27]==0) begin
VAR3[VAR27] <= 0;
if (VAR33[VAR27][13:0]==0) begin
VAR30[VAR27] <= 1'b1;
if (VAR15[7]==1'b1 && VAR27==2'b10) begin
VAR2[VAR27] <= VAR2[2'b11];
VAR33[VAR27][13:0] <= VAR33[2'b11][13:0];
end
end else begin
VAR2[VAR27] <= VAR2[VAR27]+1'b1;
VAR33[VAR27][13:0] <= VAR33[VAR27][13:0]+14'h3FFF;
end
state <= VAR10;
end
end
VAR10: begin
state <= |VAR22 ? VAR21 : VAR13;
end
endcase
end
end
end
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21bo/sky130_fd_sc_ms__a21bo.symbol.v | 1,388 | module MODULE1 (
input VAR8 ,
input VAR5 ,
input VAR4,
output VAR6
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
Elphel/x353 | control/control_regs.v | 6,670 | module MODULE1 (VAR22, VAR8, VAR33, VAR11, VAR21, VAR29,
VAR50,
VAR2, VAR54,
VAR16,
VAR13,
VAR32,
VAR5,
VAR37,
VAR44,
VAR53,
VAR15, VAR36, VAR28,
VAR56,
VAR19, VAR6, VAR49, VAR24, VAR23 ); input VAR22;
input VAR8;
input [ 1:0] VAR33;
input [15:0] VAR11;
output [ 1:0] VAR21; output VAR29;
output VAR50;
output VAR2; output VAR54;
output VAR16;
output VAR13;
output VAR32;
output VAR5;
output VAR37;
output VAR44;
output VAR53;
output VAR15;
output VAR36;
output [7:0] VAR23;
output VAR28;
output VAR56;
output [1:0] VAR19; output [1:0] VAR6; output [2:0] VAR49; output VAR24; reg [1:0] VAR57; reg [1:0] VAR40; reg [2:0] VAR41; reg [15:0] VAR45;
reg [31:0] VAR31;
reg [7:0] VAR23=8'hff;
always @ (negedge VAR22) begin
VAR57[1:0] <= {VAR57[0], VAR8};
if (VAR8) VAR40[1:0] <= VAR33[1:0];
VAR41[2:0] <= {VAR57[1] & (VAR40[1:0]==2'h1), VAR57[1] & (VAR40[1:0]==2'h3), VAR57[1] & (VAR40[1:0]==2'h2)};
if (VAR8 || VAR57[0]) VAR45[15:0] <= VAR11[15:0];
if (VAR57[0]) VAR31[15: 0] <= VAR45[15:0];
if (VAR57[1]) VAR31[31:16] <= VAR45[15:0];
end
VAR43 VAR48 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[ 2]),.VAR25(VAR31[ 0]), .VAR55(VAR21[0]));
VAR43 VAR38 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[ 2]),.VAR25(VAR31[ 1]), .VAR55(VAR21[1]));
VAR43 VAR42 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[ 4]),.VAR25(VAR31[ 3]), .VAR55(VAR29));
VAR43 VAR27 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[ 6]),.VAR25(VAR31[ 5]), .VAR55(VAR50));
VAR43 VAR60 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[ 8]),.VAR25(VAR31[ 7]), .VAR55(VAR54));
VAR43 VAR47 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[10]),.VAR25(VAR31[ 9]), .VAR55(VAR16));
VAR43 VAR17 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[12]),.VAR25(VAR31[11]), .VAR55(VAR13));
VAR43 VAR26 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[14]),.VAR25(VAR31[13]), .VAR55(VAR32));
VAR43 VAR58 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[16]),.VAR25(VAR31[15]), .VAR55(VAR5));
VAR43 VAR46 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[18]),.VAR25(VAR31[17]), .VAR55(VAR37));
VAR43 VAR3 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[20]),.VAR25(VAR31[19]), .VAR55(VAR44));
VAR43 VAR59 (.VAR1(VAR22),.VAR51(VAR41[0] & VAR31[22]),.VAR25(VAR31[21]), .VAR55(VAR2));
VAR43 VAR39 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[ 1]),.VAR25(VAR31[ 0]), .VAR55(VAR53));
VAR43 VAR35(.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[ 3]),.VAR25(VAR31[ 2]), .VAR55(VAR15));
VAR43 VAR20 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[ 5]),.VAR25(VAR31[ 4]), .VAR55(VAR28));
VAR43 VAR18 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[ 7]),.VAR25(VAR31[ 6]), .VAR55(VAR56));
VAR43 VAR7 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[10]),.VAR25(VAR31[ 8]), .VAR55(VAR19[0]));
VAR43 VAR12 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[10]),.VAR25(VAR31[ 9]), .VAR55(VAR19[1]));
VAR43 VAR34 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[13]),.VAR25(VAR31[11]), .VAR55(VAR6[0]));
VAR43 VAR52 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[13]),.VAR25(VAR31[12]), .VAR55(VAR6[1]));
VAR43 VAR9 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[17]),.VAR25(VAR31[14]), .VAR55(VAR49[0]));
VAR43 VAR30 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[17]),.VAR25(VAR31[15]), .VAR55(VAR49[1]));
VAR43 VAR10 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[17]),.VAR25(VAR31[16]), .VAR55(VAR49[2]));
VAR43 VAR14 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[19]),.VAR25(VAR31[18]), .VAR55(VAR24));
VAR43 VAR4 (.VAR1(VAR22),.VAR51(VAR41[1] & VAR31[21]),.VAR25(VAR31[20]), .VAR55(VAR36));
always @ (negedge VAR22) begin
if (VAR41[2] & VAR31[8]) VAR23[7:0] <= VAR31[7:0];
end
endmodule | gpl-3.0 |
mbus/mbus | mbus/verilog/mbus_int_ctrl.v | 3,135 | module MODULE1
(
input VAR3,
input VAR17,
input VAR11, input VAR16,
input VAR19,
input VAR10,
input VAR8, input VAR4, output reg VAR13,
output reg VAR12,
input VAR9
);
reg VAR6;
reg VAR2;
always @ * begin
if (VAR11 ==VAR1)
VAR6 = 0;
end
else
VAR6 = VAR19;
end
wire VAR5 = ((~VAR6) & (~VAR16));
always @ (negedge VAR3 or negedge VAR17 or negedge VAR5) begin
if (~VAR17)
VAR2 <= 1;
end
else if (~VAR5)
VAR2 <= 1;
else
VAR2 <= 0;
end
wire VAR18 = (VAR17 & VAR3);
wire VAR14 = (VAR17 & (~VAR9));
wire VAR7 = (VAR10 & VAR2);
always @ (posedge VAR7 or negedge VAR18) begin
if (~VAR18)
VAR13 <= 0;
end
else begin
case ({VAR8, VAR4})
{VAR1, VAR1}: begin VAR13 <= 1; end
{VAR15, VAR1}: begin if (VAR2) VAR13 <= 1; end
default: begin end
endcase
end
end
always @ (posedge VAR7 or negedge VAR14) begin
if (~VAR14)
VAR12 <= 0;
end
else begin
case ({VAR8, VAR4})
{VAR1, VAR1}: begin VAR12 <= 1; end
{VAR15, VAR1}: begin if (VAR2) VAR12 <= 1; end
default: begin end
endcase
end
end
endmodule | apache-2.0 |
ptracton/pmodacl2 | soc/picoblaze/cpu.v | 2,818 | module MODULE1 (
VAR14, VAR2, VAR21, VAR3, VAR1,
VAR13, VAR6, interrupt, VAR4, VAR11
) ;
input VAR13;
input [7:0] VAR6;
output [7:0] VAR14;
output [7:0] VAR2;
output VAR21;
output VAR3;
input interrupt; output VAR1;
input VAR4;
input VAR11;
wire [11:0] address;
wire [17:0] VAR10;
wire [7:0] VAR2;
wire [7:0] VAR14;
wire VAR18;
wire VAR8;
wire VAR9;
wire VAR1;
wire VAR3;
wire VAR21;
wire VAR20;
VAR7 #(
.VAR16 (12'h3FF),
.VAR15(64),
.VAR17 (8'h00))
VAR12 (
.address (address),
.VAR10 (VAR10),
.VAR18 (VAR18),
.VAR14 (VAR14),
.VAR21 (VAR21),
.VAR8 (VAR8),
.VAR2 (VAR2),
.VAR3 (VAR3),
.VAR6 (VAR6),
.interrupt (interrupt),
.VAR1 (VAR1),
.reset (VAR9),
.VAR22 (VAR4),
.clk (VAR13));
VAR5 VAR19 ( .enable (VAR18),
.address (address),
.VAR10 (VAR10),
.clk (VAR13));
assign VAR9 = VAR11;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i_2.v | 2,214 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR8 ,
VAR2 ,
VAR3,
VAR10,
VAR9 ,
VAR1
);
output VAR7 ;
input VAR4 ;
input VAR8 ;
input VAR2 ;
input VAR3;
input VAR10;
input VAR9 ;
input VAR1 ;
VAR5 VAR6 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7 ,
VAR4,
VAR8,
VAR2
);
output VAR7 ;
input VAR4;
input VAR8;
input VAR2 ;
supply1 VAR3;
supply0 VAR10;
supply1 VAR9 ;
supply0 VAR1 ;
VAR5 VAR6 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/cfg.v | 4,781 | module MODULE1 ( VAR6 );
output [255:0] VAR6;
assign VAR6[151:120] = 32'h0001FEED ;
assign VAR6[183:152] = 32'h02000000 ;
assign VAR6[215:184] = 32'h0000FEED ;
assign VAR6[114] = VAR1 ;
assign VAR6[0] = VAR5 ;
assign VAR6[32:1] = VAR4 ;
assign VAR6[33] = VAR8 ;
assign VAR6[35:34] = VAR7 ;
assign VAR6[36] = VAR2 ;
assign VAR6[37] = VAR1 ;
assign VAR6[69:38] = VAR3 ;
assign VAR6[70] = VAR8 ;
assign VAR6[72:71] = VAR7 ;
assign VAR6[73] = VAR2 ;
assign VAR6[74] = VAR1 ;
assign VAR6[106:75] = VAR3 ;
assign VAR6[107] = VAR8 ;
assign VAR6[109:108] = VAR7 ;
assign VAR6[110] = VAR2 ;
assign VAR6[231:224] = 8'h00 ;
assign VAR6[223:216] = 8'h00 ;
assign VAR6[112] = VAR5 ;
assign VAR6[113] = VAR5 ;
assign VAR6[116] = VAR1 ;
assign VAR6[239:232] = 8'h00 ;
assign VAR6[118] = VAR1 ;
assign VAR6[240] = VAR1 ;
assign VAR6[111] = VAR1 ;
assign VAR6[117] = VAR1 ;
assign VAR6[119] = VAR1 ;
assign VAR6[244] = VAR1 ;
assign VAR6[254:245] = 10'b0010000000;
assign VAR6[115] = VAR1 ;
assign VAR6[241] = VAR1 ;
assign VAR6[242] = VAR1 ;
assign VAR6[243] = VAR1 ;
assign VAR6[255] = VAR1 ;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2i/sky130_fd_sc_hdll__mux2i.functional.pp.v | 1,954 | module MODULE1 (
VAR13 ,
VAR12 ,
VAR3 ,
VAR4 ,
VAR8,
VAR9,
VAR1 ,
VAR11
);
output VAR13 ;
input VAR12 ;
input VAR3 ;
input VAR4 ;
input VAR8;
input VAR9;
input VAR1 ;
input VAR11 ;
wire VAR2;
wire VAR10;
VAR5 VAR14 (VAR2, VAR12, VAR3, VAR4 );
VAR6 VAR7 (VAR10, VAR2, VAR8, VAR9);
buf VAR15 (VAR13 , VAR10 );
endmodule | apache-2.0 |
AngelTerrones/MUSB | Hardware/uart/uart_rx.v | 5,810 | module MODULE1(
input clk,
input rst,
input VAR17, input VAR4, output reg [7:0] VAR22 = 0, output ready );
localparam [3:0] VAR19=0; localparam [3:0] VAR15=1; localparam [3:0] VAR2=2; localparam [3:0] VAR10=3; localparam [3:0] VAR20=4; localparam [3:0] VAR12=5; localparam [3:0] VAR18=6; localparam [3:0] VAR14=7; localparam [3:0] VAR7=8; localparam [3:0] VAR9=9; localparam [3:0] VAR11=10;
reg [3:0] state = VAR19;
reg VAR3 = 0;
reg [3:0] VAR8 = 4'b1110;
wire VAR13;
wire VAR16;
assign VAR13 = (VAR4 & VAR16 & (state!=VAR19) & (state!=VAR11));
assign VAR16 = (VAR8 == 4'b1111);
reg [1:0] VAR1 = 2'b11; always @(posedge clk) begin
VAR1 <= (VAR4) ? {VAR1[0], VAR17} : VAR1;
end
reg [1:0] VAR6 = 0;
reg VAR21 = 1; always @(posedge clk) begin
if (VAR4) begin
case (VAR1[1])
0: VAR6 <= (VAR6 == 2'b11) ? VAR6 : VAR6 + 2'b1;
1: VAR6 <= (VAR6 == 2'b00) ? VAR6 : VAR6 - 2'b1;
endcase
VAR21 <= (VAR6 == 2'b11) ? 1'b0 : ((VAR6 == 2'b00) ? 1'b1 : VAR21);
end
else begin
VAR6 <= VAR6;
VAR21 <= VAR21;
end
end
always @(posedge clk) begin
if (VAR4) begin
if (~VAR3)
end
VAR3 <= ~VAR21; else
VAR3 <= ((state == VAR19) && (VAR21 == 1'b1)) ? 1'b0 : VAR3;
VAR8 <= (VAR3) ? VAR8 + 4'b1 : 4'b1110;
end
else begin
VAR3 <= VAR3;
VAR8 <= VAR8;
end
end
always @(posedge clk) begin
if (rst)
state <= VAR19;
end
else if (VAR4) begin
case (state)
VAR19: state <= (VAR16 & (VAR21 == 1'b0)) ? VAR2 : VAR19; VAR2: state <= (VAR16) ? VAR10 : VAR2;
VAR10: state <= (VAR16) ? VAR20 : VAR10;
VAR20: state <= (VAR16) ? VAR12 : VAR20;
VAR12: state <= (VAR16) ? VAR18 : VAR12;
VAR18: state <= (VAR16) ? VAR14 : VAR18;
VAR14: state <= (VAR16) ? VAR7 : VAR14;
VAR7: state <= (VAR16) ? VAR9 : VAR7;
VAR9: state <= (VAR16) ? VAR11 : VAR9;
VAR11: state <= (VAR16) ? VAR19 : VAR11;
default: state <= 4'VAR5;
endcase
end
else state <= state;
end
always @(posedge clk) begin
VAR22 <= (VAR13) ? {VAR21, VAR22[7:1]} : VAR22[7:0];
end
assign ready = (VAR4 & VAR16 & (state==VAR11));
endmodule | mit |
fabianmcg/usbc_tcpc | src/cmos_cells.v | 2,555 | module MODULE1(VAR3, VAR9);
input VAR3;
output VAR9;
assign VAR9 = VAR3;
parameter VAR5=VAR6;
wire [31:0] VAR2;
reg VAR7;
VAR1 VAR8(VAR2,VAR7,VAR3);
integer VAR4;
begin
begin
begin
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221o/sky130_fd_sc_hd__a221o.functional.pp.v | 2,199 | module MODULE1 (
VAR14 ,
VAR11 ,
VAR15 ,
VAR12 ,
VAR3 ,
VAR7 ,
VAR2,
VAR17,
VAR4 ,
VAR16
);
output VAR14 ;
input VAR11 ;
input VAR15 ;
input VAR12 ;
input VAR3 ;
input VAR7 ;
input VAR2;
input VAR17;
input VAR4 ;
input VAR16 ;
wire VAR5 ;
wire VAR9 ;
wire VAR6 ;
wire VAR13;
and VAR20 (VAR5 , VAR12, VAR3 );
and VAR1 (VAR9 , VAR11, VAR15 );
or VAR18 (VAR6 , VAR9, VAR5, VAR7);
VAR8 VAR10 (VAR13, VAR6, VAR2, VAR17 );
buf VAR19 (VAR14 , VAR13 );
endmodule | apache-2.0 |
fbalakirev/red-pitaya-notes | projects/red_pitaya_0_92/red_pitaya_asg_ch.v | 6,637 | module MODULE1
parameter VAR16 = 14
)
(
output reg [ 14-1: 0] VAR2 , input VAR12 , input VAR26 ,
input VAR22 , input VAR7 , input [ 3-1: 0] VAR9 , output VAR6 ,
input VAR32 , input [ 14-1: 0] VAR31 , input [ 14-1: 0] VAR3 , output reg [ 14-1: 0] VAR14 ,
input [VAR16+15: 0] VAR15 , input [VAR16+15: 0] VAR38 , input [VAR16+15: 0] VAR13 , input VAR5 , input VAR29 , input VAR18 , input [ 14-1: 0] VAR21 , input [ 14-1: 0] VAR10 , input VAR23
);
reg [ 14-1: 0] VAR28 [0:(1<<VAR16)-1] ;
reg [ 14-1: 0] VAR36 ;
reg [ 14-1: 0] VAR34 ;
reg [ VAR16-1: 0] VAR33 ;
reg [VAR16+15: 0] VAR35 ;
reg VAR17 ;
reg VAR4 ;
wire [VAR16+16: 0] VAR25 ; reg [ 28-1: 0] VAR37 ;
reg [ 15-1: 0] VAR20 ;
always @(posedge VAR12) begin
VAR33 <= VAR35[VAR16+15:16];
VAR36 <= VAR28[VAR33] ;
VAR34 <= VAR36 ; end
always @(posedge VAR12) begin
if (VAR32)
VAR28[VAR31] <= VAR3[14-1:0] ;
end
always @(posedge VAR12) begin
VAR14 <= VAR28[VAR31] ;
end
always @(posedge VAR12) begin
VAR37 <= (VAR34) * ({1'b0,VAR21}) ;
VAR20 <= (VAR37[28-1:13]) + (VAR10) ;
if (VAR23)
VAR2 <= 14'h0 ;
end
else if ((VAR20[15-1:0]) > (14'h1FFF)) VAR2 <= 14'h1FFF ;
else if ((VAR20[15-1:0]) < (14'h2000)) VAR2 <= 14'h2000 ;
else
VAR2 <= VAR20[13:0] ;
end
wire VAR27 ;
wire VAR24 ;
always @(posedge VAR12) begin
if (VAR26 == 1'b0) begin
VAR17 <= 1'b0 ;
VAR35 <= {VAR16+16{1'b0}} ;
VAR4 <= 1'h0 ;
end
else begin
case (VAR9)
3'd1 : VAR4 <= VAR22 ; 3'd2 : VAR4 <= VAR27 ; 3'd3 : VAR4 <= VAR24 ; default : VAR4 <= 1'b0 ;
endcase
if (VAR4 && !VAR5)
VAR17 <= 1'b1 ;
end
else if (VAR5 || (VAR29 && (VAR25 >= {1'b0,VAR15})) )
VAR17 <= 1'b0 ;
if (VAR5 || (VAR4 && !VAR17)) VAR35 <= VAR13 ;
end
else if (VAR17 && !VAR29 && !VAR18 && (VAR25 > {1'b0,VAR15}) ) VAR35 <= VAR13 ;
else if (VAR17 && !VAR29 && VAR18 && (VAR25 > {1'b0,VAR15}) ) VAR35 <= VAR25 - {1'b0,VAR15} - 'h10000 ; else if (VAR17) VAR35 <= VAR25[VAR16+15:0] ;
end
end
assign VAR25 = VAR35 + VAR38;
assign VAR6 = VAR4 ;
reg [ 3-1: 0] VAR1 ;
reg [ 2-1: 0] VAR19 ;
reg [ 2-1: 0] VAR8 ;
reg [ 20-1: 0] VAR30 ;
reg [ 20-1: 0] VAR11 ;
always @(posedge VAR12) begin
if (VAR26 == 1'b0) begin
VAR1 <= 3'h0 ;
VAR19 <= 2'h0 ;
VAR8 <= 2'h0 ;
VAR30 <= 20'h0 ;
VAR11 <= 20'h0 ;
end
else begin
VAR1 <= {VAR1[1:0],VAR7} ;
if ((VAR30 == 20'h0) && (VAR1[1] && !VAR1[2]))
end
VAR30 <= 20'd62500 ; else if (VAR30 != 20'h0)
VAR30 <= VAR30 - 20'd1 ;
if ((VAR11 == 20'h0) && (!VAR1[1] && VAR1[2]))
end
VAR11 <= 20'd62500 ; else if (VAR11 != 20'h0)
VAR11 <= VAR11 - 20'd1 ;
VAR19[1] <= VAR19[0] ;
if (VAR30 == 20'h0)
VAR19[0] <= VAR1[1] ;
VAR8[1] <= VAR8[0] ;
if (VAR11 == 20'h0)
VAR8[0] <= VAR1[1] ;
end
end
assign VAR27 = (VAR19 == 2'b01) ;
assign VAR24 = (VAR8 == 2'b10) ;
endmodule | mit |
alan4186/Hardware-CNN | Hardware/v/window_selector.v | 4,832 | module MODULE1(
input VAR22,
input reset,
input [VAR20:0] VAR14,
input [VAR13:0] VAR8,
input [VAR6:0] VAR4,
output reg[VAR17:0] VAR15
);
wire [VAR17:0] VAR21 [VAR9:0][VAR5:0];
reg[VAR17:0] VAR7 [VAR5:0];
genvar VAR12;
genvar VAR11;
generate
for (VAR12=0; VAR12<VAR19; VAR12=VAR12+1) begin : VAR1
for(VAR11=0; VAR11<VAR16; VAR11=VAR11+1) begin : VAR10
assign VAR21[VAR11][VAR12] = VAR14[
(VAR2*VAR11)+(VAR16*VAR2*VAR12) +VAR17:
(VAR2*VAR11)+(VAR16*VAR2*VAR12)
];
end end endgenerate
genvar VAR18;
generate
for (VAR18=0; VAR18<VAR19; VAR18=VAR18+1) begin : VAR3
always@ begin
case(VAR4)
default: VAR15 = VAR2'd0;
endcase
end
endmodule | mit |
olgirard/openmsp430 | fpga/actel_m1a3pl_dev_kit/bench/verilog/msp_debug.v | 14,534 | module MODULE1 (
VAR12, VAR59, VAR107, VAR69, VAR82, VAR54, VAR99,
VAR83, VAR44 );
output [8*32-1:0] VAR12; output [8*32-1:0] VAR59; output [31:0] VAR107; output [8*32-1:0] VAR69; output [31:0] VAR82; output [15:0] VAR54; output [8*32-1:0] VAR99;
input VAR83; input VAR44;
function [64*8-1:0] VAR79;
input [32*8-1:0] VAR64;
input [32*8-1:0] VAR7;
input [3:0] VAR65;
integer VAR88,VAR20;
begin
VAR79 = 0;
VAR20 = 0;
for ( VAR88=0; VAR88 < 32; VAR88=VAR88+1) begin
VAR79[8*VAR88 +: 8] = VAR7[8*VAR88 +: 8];
if ((VAR7[8*VAR88 +: 8] == 0) && (VAR20 == 0)) VAR20=VAR88;
end
for ( VAR88=0; VAR88 < VAR65; VAR88=VAR88+1) VAR79[8*(VAR20+VAR88) +: 8] = " ";
VAR20=VAR20+VAR65;
for ( VAR88=0; VAR88 < 32; VAR88=VAR88+1) VAR79[8*(VAR20+VAR88) +: 8] = VAR64[8*VAR88 +: 8];
end
endfunction
wire [2:0] VAR95 = VAR25.VAR94.VAR16.VAR28.VAR59;
wire [3:0] VAR68 = VAR25.VAR94.VAR16.VAR28.VAR12;
wire VAR91 = VAR25.VAR94.VAR16.VAR28.VAR91;
wire [15:0] VAR90 = VAR25.VAR94.VAR16.VAR28.VAR90;
wire VAR66 = VAR25.VAR94.VAR16.VAR28.VAR66;
wire [3:0] VAR14 = VAR25.VAR94.VAR16.VAR28.VAR14;
wire [15:0] VAR86 = VAR25.VAR94.VAR16.VAR28.VAR86;
reg [8*32-1:0] VAR59;
always @(VAR95)
case(VAR95)
3'h0 : VAR59 = "VAR72";
3'h1 : VAR59 = "VAR46";
3'h2 : VAR59 = "VAR5";
3'h3 : VAR59 = "VAR53";
3'h4 : VAR59 = "VAR58";
3'h5 : VAR59 = "VAR61";
default : VAR59 = "VAR97";
endcase
reg [8*32-1:0] VAR12;
always @(VAR68)
case(VAR68)
4'h2 : VAR12 = "VAR26";
4'h1 : VAR12 = "VAR81";
4'h0 : VAR12 = "VAR85";
4'h3 : VAR12 = "VAR96";
4'h4 : VAR12 = "VAR23";
4'h5 : VAR12 = "VAR80";
4'h6 : VAR12 = "VAR57";
4'h7 : VAR12 = "VAR89";
4'h8 : VAR12 = "VAR52";
4'h9 : VAR12 = "VAR55";
4'hA : VAR12 = "VAR22";
4'hB : VAR12 = "VAR70";
4'hC : VAR12 = "VAR32";
4'hD : VAR12 = "VAR61";
default : VAR12 = "VAR40";
endcase
reg [31:0] VAR82;
always @(posedge VAR83 or posedge VAR44)
if (VAR44) VAR82 <= 0;
else if (VAR91) VAR82 <= VAR82+1;
reg [31:0] VAR107;
always @(posedge VAR83 or posedge VAR44)
if (VAR44) VAR107 <= 0;
else if (VAR91) VAR107 <= 0;
else VAR107 <= VAR107+1;
reg [15:0] VAR21;
always @(posedge VAR83 or posedge VAR44)
if (VAR44) VAR21 <= 0;
else if (VAR91) VAR21 <= VAR90;
reg irq;
always @(posedge VAR83 or posedge VAR44)
if (VAR44) irq <= 1'b1;
else if (VAR91) irq <= VAR66;
reg [8*32-1:0] VAR1;
always @(VAR21 or irq)
if (irq)
VAR1 = "VAR29";
else
case(VAR21[15:13])
3'b000 : VAR1 = "VAR34-VAR74";
3'b001 : VAR1 = "VAR32";
default : VAR1 = "VAR102-VAR74";
endcase
reg [8*32-1:0] VAR3;
always @(VAR21 or VAR1 or VAR14)
if (VAR1=="VAR29")
case(VAR14[3:0])
4'b0000 : VAR3 = "VAR29 0";
4'b0001 : VAR3 = "VAR29 1";
4'b0010 : VAR3 = "VAR29 2";
4'b0011 : VAR3 = "VAR29 3";
4'b0100 : VAR3 = "VAR29 4";
4'b0101 : VAR3 = "VAR29 5";
4'b0110 : VAR3 = "VAR29 6";
4'b0111 : VAR3 = "VAR29 7";
4'b1000 : VAR3 = "VAR29 8";
4'b1001 : VAR3 = "VAR29 9";
4'b1010 : VAR3 = "VAR29 10";
4'b1011 : VAR3 = "VAR29 11";
4'b1100 : VAR3 = "VAR29 12";
4'b1101 : VAR3 = "VAR29 13";
4'b1110 : VAR3 = "VAR98";
default : VAR3 = "VAR48";
endcase
else if (VAR1=="VAR34-VAR74")
case(VAR21[15:7])
9'b000100000 : VAR3 = "VAR67";
9'b000100001 : VAR3 = "VAR62";
9'b000100010 : VAR3 = "VAR35";
9'b000100011 : VAR3 = "VAR109";
9'b000100100 : VAR3 = "VAR108";
9'b000100101 : VAR3 = "VAR36";
9'b000100110 : VAR3 = "VAR42";
default : VAR3 = "VAR40";
endcase
else if (VAR1=="VAR32")
case(VAR21[15:10])
6'b001000 : VAR3 = "VAR38";
6'b001001 : VAR3 = "VAR8";
6'b001010 : VAR3 = "VAR13";
6'b001011 : VAR3 = "VAR103";
6'b001100 : VAR3 = "VAR104";
6'b001101 : VAR3 = "VAR110";
6'b001110 : VAR3 = "VAR45";
6'b001111 : VAR3 = "VAR93";
default : VAR3 = "VAR40";
endcase
else if (VAR1=="VAR102-VAR74")
case(VAR21[15:12])
4'b0100 : VAR3 = "VAR24";
4'b0101 : VAR3 = "VAR37";
4'b0110 : VAR3 = "VAR39";
4'b0111 : VAR3 = "VAR17";
4'b1000 : VAR3 = "VAR63";
4'b1001 : VAR3 = "VAR78";
4'b1010 : VAR3 = "VAR101";
4'b1011 : VAR3 = "VAR73";
4'b1100 : VAR3 = "VAR111";
4'b1101 : VAR3 = "VAR76";
4'b1110 : VAR3 = "VAR27";
4'b1111 : VAR3 = "VAR4";
default : VAR3 = "VAR40";
endcase
reg [8*32-1:0] VAR43;
always @(VAR21 or VAR1)
if (VAR1=="VAR29")
VAR43 = "";
else if (VAR1=="VAR34-VAR74")
VAR43 = VAR21[6] ? ".VAR11" : "";
else if (VAR1=="VAR32")
VAR43 = "";
else if (VAR1=="VAR102-VAR74")
VAR43 = VAR21[6] ? ".VAR11" : "";
reg [8*32-1:0] VAR50;
wire [3:0] VAR84 = (VAR1=="VAR34-VAR74") ? VAR21[3:0] : VAR21[11:8];
always @(VAR84 or VAR1)
if (VAR1=="VAR29")
VAR50 = "";
else if (VAR1=="VAR32")
VAR50 = "";
else if ((VAR1=="VAR34-VAR74") || (VAR1=="VAR102-VAR74"))
case(VAR84)
4'b0000 : VAR50 = "VAR19";
4'b0001 : VAR50 = "VAR105";
4'b0010 : VAR50 = "VAR106";
4'b0011 : VAR50 = "VAR56";
4'b0100 : VAR50 = "VAR60";
4'b0101 : VAR50 = "VAR75";
4'b0110 : VAR50 = "VAR9";
4'b0111 : VAR50 = "VAR2";
4'b1000 : VAR50 = "VAR41";
4'b1001 : VAR50 = "VAR49";
4'b1010 : VAR50 = "VAR18";
4'b1011 : VAR50 = "VAR71";
4'b1100 : VAR50 = "VAR51";
4'b1101 : VAR50 = "VAR92";
4'b1110 : VAR50 = "VAR10";
default : VAR50 = "VAR33";
endcase
reg [8*32-1:0] VAR30;
always @(VAR21 or VAR1)
if (VAR1=="VAR29")
VAR30 = "";
else if (VAR1=="VAR34-VAR74")
VAR30 = "";
else if (VAR1=="VAR32")
VAR30 = "";
else if (VAR1=="VAR102-VAR74")
case(VAR21[3:0])
4'b0000 : VAR30 = "VAR19";
4'b0001 : VAR30 = "VAR105";
4'b0010 : VAR30 = "VAR106";
4'b0011 : VAR30 = "VAR56";
4'b0100 : VAR30 = "VAR60";
4'b0101 : VAR30 = "VAR75";
4'b0110 : VAR30 = "VAR9";
4'b0111 : VAR30 = "VAR2";
4'b1000 : VAR30 = "VAR41";
4'b1001 : VAR30 = "VAR49";
4'b1010 : VAR30 = "VAR18";
4'b1011 : VAR30 = "VAR71";
4'b1100 : VAR30 = "VAR51";
4'b1101 : VAR30 = "VAR92";
4'b1110 : VAR30 = "VAR10";
default : VAR30 = "VAR33";
endcase
reg [8*32-1:0] VAR87;
always @(VAR1 or VAR84 or VAR21 or VAR50)
begin
if (VAR1=="VAR29")
VAR87 = "";
end
else if (VAR1=="VAR32")
VAR87 = "";
else if (VAR84==4'h3) case (VAR21[5:4])
2'b11 : VAR87 = "#-1";
2'b10 : VAR87 = "";
2'b01 : VAR87 = "";
default: VAR87 = "";
endcase
else if (VAR84==4'h2) case (VAR21[5:4])
2'b11 : VAR87 = "";
2'b10 : VAR87 = "";
2'b01 : VAR87 = "&VAR47";
default: VAR87 = VAR50;
endcase
else if (VAR84==4'h0) case (VAR21[5:4])
2'b11 : VAR87 = "#VAR100";
2'b10 : VAR87 = VAR79("@", VAR50, 0);
2'b01 : VAR87 = "VAR47";
default: VAR87 = VAR50;
endcase
else case (VAR21[5:4])
2'b11 : begin
VAR87 = VAR79("@", VAR50, 0);
VAR87 = VAR79(VAR87, "+", 0);
end
2'b10 : VAR87 = VAR79("@", VAR50, 0);
2'b01 : begin
VAR87 = VAR79("VAR77(", VAR50, 0);
VAR87 = VAR79(VAR87, ")", 0);
end
default: VAR87 = VAR50;
endcase
end
reg [8*32-1:0] VAR31;
always @(VAR21 or VAR1 or VAR30)
begin
if (VAR1!="VAR102-VAR74")
VAR31 = "";
end
else if (VAR21[3:0]==4'h2) case (VAR21[7])
1'b1 : VAR31 = "&VAR47";
default: VAR31 = VAR30;
endcase
else if (VAR21[3:0]==4'h0) case (VAR21[7])
2'b1 : VAR31 = "VAR47";
default: VAR31 = VAR30;
endcase
else case (VAR21[7])
2'b1 : begin
VAR31 = VAR79("VAR77(", VAR30, 0);
VAR31 = VAR79(VAR31, ")", 0);
end
default: VAR31 = VAR30;
endcase
end
wire [8*32-1:0] VAR99 = VAR3;
reg [8*32-1:0] VAR69;
always @(VAR1 or VAR3 or VAR43 or VAR87 or VAR31)
begin
VAR69 = VAR79(VAR3, VAR43, 0);
VAR69 = VAR79(VAR69, VAR87, 1);
if (VAR1=="VAR102-VAR74")
VAR69 = VAR79(VAR69, ",", 0);
VAR69 = VAR79(VAR69, VAR31, 1);
if (VAR21==16'h4303)
VAR69 = "VAR112";
if (VAR21==VAR6)
VAR69 = "VAR15";
end
reg [15:0] VAR54;
always @(posedge VAR83 or posedge VAR44)
if (VAR44) VAR54 <= 16'h0000;
else if (VAR91) VAR54 <= VAR86;
endmodule | bsd-3-clause |
vipinkmenon/scas | hw/fpga/ipcore_dir/tx_fifo_blank.v | 3,009 | module MODULE1(
rst,
VAR7,
VAR4,
din,
VAR3,
VAR5,
dout,
VAR8,
VAR1,
VAR6,
VAR2
);
input rst;
input VAR7;
input VAR4;
input [63 : 0] din;
input VAR3;
input VAR5;
output [7 : 0] dout;
output VAR8;
output VAR1;
output [13 : 0] VAR6;
output [10 : 0] VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2b/sky130_fd_sc_hs__nor2b.blackbox.v | 1,271 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR4
);
output VAR1 ;
input VAR3 ;
input VAR4;
supply1 VAR5;
supply0 VAR2;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/ucore/syscop.v | 15,187 | module MODULE1
(
VAR31,VAR3,
VAR41,VAR12,VAR30,VAR55,VAR38,VAR45,
VAR48,VAR10,
VAR68,VAR35,VAR34,
VAR1,VAR66,VAR11,
VAR39,VAR15,VAR24,
VAR17,VAR40,VAR54
);
parameter VAR19 = VAR59;
parameter VAR18 = 26'b10000000000000000000011000;
parameter VAR57 = 26'b10000000000000000000011111;
parameter VAR9 = 26'VAR13;
parameter VAR8 = 6'b011000;
parameter VAR22 = 6'b011111;
parameter VAR50 = 6'b100000;
parameter VAR47 = 0;
parameter VAR27 = 12;
parameter VAR67 = 13;
parameter VAR29 = 14;
parameter VAR6 = 15;
parameter VAR52 = 16;
parameter VAR71 = 17;
parameter VAR58 = 18;
parameter VAR62 = 7'b0000001;
parameter VAR25 = 7'b0000010;
parameter VAR64 = 7'b0000100;
parameter VAR69 = 7'b0001000;
parameter VAR63 = 7'b0010000;
parameter VAR65 = 7'b0100000;
parameter VAR44 = 7'b1000000;
input VAR31;
input VAR3;
input [31:0] VAR41;
input [31:0] VAR12;
input [VAR16-1:0] VAR30;
input VAR55;
input VAR38;
input VAR45;
input VAR48;
input [VAR21-1:0] VAR10;
output VAR68; output VAR35; output [31:0] VAR34; reg VAR35;
reg [31:0] VAR34;
output [31:0] VAR1; output [VAR70-1-1:0] VAR66; output VAR11; reg [31:0] VAR1;
reg [VAR70-1-1:0] VAR66;
reg VAR11;
output [VAR70-1-1:0] VAR39; reg [VAR70-1-1:0] VAR39;
output VAR15;
reg VAR15;
input [31:0] VAR24;
input [VAR70-1:0] VAR17;
input VAR40;
input [31:0] VAR54;
wire [31:0] VAR4;
assign VAR4 = 32'hffffffff;
wire VAR5;
assign VAR5 = VAR40 & VAR17[VAR70-1:0] == VAR71 +32;
reg [31:0] VAR23;
reg [6:0] VAR14;
reg VAR37;
reg VAR56;
reg VAR7,VAR2;
reg [31:0] VAR53,VAR20;
reg VAR43;
reg [VAR21-1:0] VAR28;
reg VAR60;
reg VAR51;
reg VAR42;
assign VAR68 = VAR51 | VAR37 | VAR56;
always @(VAR30,VAR12,VAR55,VAR28,VAR43,VAR45)
begin
VAR37 = 0;
VAR56 = 0;
VAR7 = 0;
VAR53 = 32'b0;
case(VAR30) VAR33,
begin
VAR37 = 1;
VAR53[31] = VAR45;
VAR53[30:VAR16] = 0;
VAR53[VAR16-1:0] = VAR30;
if(VAR30 == VAR26)
begin
case(VAR12[5:0]) VAR8 : VAR7 = 1;
VAR22: VAR7 = 1;
VAR50 : VAR7 = 0;
default : VAR7 = 0;
endcase
end
end
if((VAR43 ||(|VAR28)) &VAR55)
begin
VAR53[31] = VAR45;
VAR53[30:VAR21+VAR16+1] = 0;
VAR53[VAR16-1:0] = 0;
VAR56 = 1;
VAR53[VAR21+VAR16:VAR16] =
VAR43 ? 5'b10000:
VAR28[3] ? 5'b01000:
VAR28[2] ? 5'b00100:
VAR28[1] ? 5'b00010:
VAR28[0] ? 5'b00001:5'VAR36;
end
endcase
end
always @(posedge VAR31 or posedge VAR3)
begin
if(VAR3)
begin
VAR42 <= #VAR19 1'VAR32;
VAR11 <= #VAR19 0;
VAR1 <= #VAR19 32'VAR32;
VAR66 <= #VAR19 5'VAR32;
VAR39 <= #VAR19 5'VAR32;
VAR15 <= #VAR19 0;
VAR35 <= #VAR19 0;
VAR51 <= #VAR19 0;
VAR34 <= #VAR19 32'VAR32;
VAR23 <= #VAR19 0;
VAR28 <= #VAR19 0;
VAR43 <= #VAR19 0;
VAR2 <= #VAR19 0;
VAR20 <= #VAR19 32'VAR32;
VAR60 <= #VAR19 0;
VAR14 <= #VAR19 VAR62;
end
else begin : VAR49
reg [VAR21-1:0] VAR61;
if(VAR5 & ~VAR56)
begin
VAR23[VAR21-1:0] <= #VAR19 VAR54[VAR21-1:0];
VAR61 = VAR54[VAR21-1:0];
end
else
VAR61 = VAR23[VAR21-1:0];
if(~VAR43) VAR43 <= VAR48;
if(~VAR28[0]) VAR28[0] <= VAR10[0]& ~VAR61[0] ;
if(~VAR28[1]) VAR28[1] <= VAR10[1]& ~VAR61[1] ;
if(~VAR28[2]) VAR28[2] <= VAR10[2]& ~VAR61[2] ;
if(~VAR28[3]) VAR28[3] <= VAR10[3]& ~VAR61[3] ;
case(VAR14) VAR62:
begin
VAR42 <= #VAR19 1'b0;
VAR51 <= #VAR19 0;
VAR35 <= #VAR19 0;
VAR34 <= #VAR19 32'VAR32;
VAR11 <= #VAR19 0;
VAR1 <= #VAR19 32'VAR32;
VAR66 <= #VAR19 5'VAR32;
VAR39 <= #VAR19 5'VAR32;
VAR15 <= #VAR19 0;
VAR60 <= #VAR19 VAR56;
if(VAR37 || VAR56)
begin
VAR51 <= #VAR19 1;
VAR20 <= #VAR19 VAR53;
if(~VAR7)
begin
VAR2 <= #VAR19 0;
VAR1 <= #VAR19 VAR23;
VAR66 <= #VAR19 VAR58;
VAR11 <= #VAR19 1;
VAR23[VAR21-1:0] <= #VAR19 VAR4[VAR21-1:0];
VAR14 <= #VAR19 VAR25;
end
else begin
VAR2 <= #VAR19 1;
VAR42 <= #VAR19 1'b1;
VAR15 <= #VAR19 1;
VAR39 <= #VAR19 VAR58;
VAR14 <= #VAR19 VAR64;
end
end
else VAR14 <= #VAR19 VAR62;
end
VAR25:
begin
VAR1 <= #VAR19 VAR20;
VAR66 <= #VAR19 VAR67;
VAR11 <= #VAR19 1;
if(VAR60)
VAR14 <= #VAR19 VAR63;
end
else VAR14 <= #VAR19 VAR69;
end
VAR69:
begin
VAR1 <= #VAR19 VAR12;
VAR66 <= #VAR19 VAR52;
VAR11 <= #VAR19 1;
VAR14 <= #VAR19 VAR63;
end
VAR63:
begin
if(VAR45)
end
VAR1 <= #VAR19 VAR41 + (~4+1); else if(~VAR60 | VAR38)
VAR1 <= #VAR19 VAR41+4;
end
else
VAR1 <= #VAR19 VAR41;
VAR66 <= #VAR19 VAR29;
VAR11 <= #VAR19 1;
VAR14 <= #VAR19 VAR64;
end
VAR64:
begin
if(~VAR2)
begin
VAR66 <= #VAR19 VAR71;
VAR11 <= #VAR19 1;
VAR1 <= #VAR19 VAR23; VAR14 <= #VAR19 VAR65;
end
else begin
if(VAR42)
begin
VAR15 <= 1;
VAR39 <= #VAR19 VAR29;
VAR14 <= VAR64;
VAR42 <= 1'b0;
end
else begin
VAR66 <= #VAR19 VAR71;
VAR11 <= #VAR19 1;
VAR1 <= #VAR19 VAR24;
VAR23 <= #VAR19 VAR24;
VAR15 <= 1;
VAR39 <= #VAR19 VAR29;
VAR14 <= #VAR19 VAR44;
end
end
end
VAR65:
begin
VAR11 <= #VAR19 0;
VAR35 <= #VAR19 1;
VAR34 <= #VAR19 VAR46;
if(VAR60)
{VAR43,VAR28} <= #VAR19 {VAR43,VAR28} & ~VAR20[VAR21+VAR16:VAR16];
VAR14 <= #VAR19 VAR62;
end
VAR44:
begin
VAR11 <= #VAR19 0;
VAR15 <= #VAR19 0;
VAR35 <= #VAR19 1;
VAR34 <= #VAR19 VAR24;
VAR14 <= #VAR19 VAR62;
end
default:
begin
VAR14 <= #VAR19 VAR62;
VAR42 <= #VAR19 1'VAR32;
VAR11 <= #VAR19 0;
VAR1 <= #VAR19 32'VAR32;
VAR66 <= #VAR19 5'VAR32;
VAR39 <= #VAR19 5'VAR32;
VAR15 <= #VAR19 0;
VAR35 <= #VAR19 0;
VAR51 <= #VAR19 0;
VAR34 <= #VAR19 32'VAR32;
VAR60 <= #VAR19 0;
VAR23 <= #VAR19 0;
VAR28 <= #VAR19 0;
VAR2 <= #VAR19 0;
VAR43 <= #VAR19 0;
VAR20 <= #VAR19 32'VAR32;
end
endcase
end
end
endmodule | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_mem/bsg_mem_2r1w.v | 2,831 | if (VAR10 == VAR31 && VAR39 == VAR14) \
begin: VAR43 \
wire [VAR10-1:0] VAR32 = (VAR34 << VAR11); \
wire [VAR10-1:0] VAR25 = (VAR36 << VAR37); \
wire [VAR10-1:0] VAR15 = (VAR21 << VAR35); \
\
VAR40 VAR42 \
( .VAR26(VAR3) \
,.VAR18(VAR27) \
,.VAR19(VAR32) \
,.VAR6 ({VAR15,VAR25}) \
,.VAR9({VAR4,VAR30}) \
); \
end
module MODULE1 #(parameter VAR7(VAR39)
, parameter VAR7(VAR10)
, parameter VAR5=0
, parameter VAR12=VAR8(VAR10)
)
(input VAR3
, input VAR1
, input VAR34
, input [VAR12-1:0] VAR11
, input [VAR39-1:0] VAR27
, input VAR36
, input [VAR12-1:0] VAR37
, output logic [VAR39-1:0] VAR30
, input VAR21
, input [VAR12-1:0] VAR35
, output logic [VAR39-1:0] VAR4
);
else
begin: VAR22
VAR28
,.VAR10(VAR10)
,.VAR5(VAR5)
) VAR17
(.*);
end
VAR2 @(posedge VAR3)
if (VAR34)
begin
assert (VAR11 < VAR10)
end
else ("VAR24 address %VAR20 VAR29 %VAR13 VAR41 VAR16 %VAR20\VAR23", VAR11, VAR10);
assert (~(VAR37 == VAR11 && VAR34 && VAR36 && !VAR5))
else ("%VAR13: VAR33 VAR29 read and write VAR38 address");
assert (~(VAR35 == VAR11 && VAR34 && VAR21 && !VAR5))
else ("%VAR13: VAR33 VAR29 read and write VAR38 address");
end
begin | bsd-3-clause |
Jawanga/ece385lab8 | lab8_usb/usb_system/synthesis/submodules/usb_system_sdram_clk.v | 10,949 | module MODULE1
(
VAR10,
VAR9,
VAR8,
VAR1) ;
input VAR10;
input VAR9;
input [0:0] VAR8;
output [0:0] VAR1;
tri0 VAR10;
tri1 VAR9;
reg [0:0] VAR5;
reg [0:0] VAR4;
reg [0:0] VAR3;
wire VAR2;
wire VAR7;
wire VAR6; | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32o/sky130_fd_sc_hs__a32o.functional.pp.v | 2,125 | module MODULE1 (
VAR15,
VAR12,
VAR16 ,
VAR17 ,
VAR3 ,
VAR14 ,
VAR18 ,
VAR5
);
input VAR15;
input VAR12;
output VAR16 ;
input VAR17 ;
input VAR3 ;
input VAR14 ;
input VAR18 ;
input VAR5 ;
wire VAR18 VAR7 ;
wire VAR18 VAR13 ;
wire VAR2 ;
wire VAR8;
and VAR11 (VAR7 , VAR14, VAR17, VAR3 );
and VAR4 (VAR13 , VAR18, VAR5 );
or VAR9 (VAR2 , VAR13, VAR7 );
VAR6 VAR1 (VAR8, VAR2, VAR15, VAR12);
buf VAR10 (VAR16 , VAR8 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/vga/vga_top.v | 5,912 | module MODULE1
(
input VAR64, input VAR13, input VAR21, input VAR62, input VAR23, input VAR6, input VAR36, input VAR54, input [3:0] VAR10, input [22:0] VAR59, input [31:0] VAR66, input [31:0] VAR47, input VAR43, input VAR55, input VAR38, input VAR11,
output [31:0] VAR71, output [2:0] VAR40,
output VAR58, output VAR7, output VAR63, output [7:0] VAR30, output VAR2, output VAR50, output VAR17, output VAR60, output VAR20, output [17:0] VAR72, output [3:0] VAR53, output [31:0] VAR28 );
wire [3:0] VAR32; wire [31:0] VAR65; wire [31:0] VAR26; wire [22:0] VAR14; wire [3:0] VAR25; wire VAR48; wire VAR49; wire VAR52;
wire VAR42;
wire [5:0] VAR5;
assign VAR40 = { VAR5[5], VAR5[1:0]};
VAR33 VAR70
(
.VAR62 (VAR62),
.VAR21 (VAR21),
.VAR73 (VAR6),
.VAR36 (VAR36),
.VAR54 (VAR54),
.VAR10 (VAR10),
.VAR66 (VAR66),
.VAR59 (VAR59),
.VAR13 (VAR13),
.VAR26 (VAR26),
.VAR42 (VAR42),
.VAR71 (VAR71),
.VAR65 (VAR65),
.VAR14 (VAR14),
.VAR52 (VAR52),
.VAR49 (VAR49),
.VAR25 (VAR25),
.VAR48 (VAR48),
.VAR19 (VAR7),
.VAR57 (VAR58)
);
VAR1 VAR8
(
.VAR56 (VAR14),
.VAR37 (VAR25),
.VAR18 (VAR48),
.VAR45 (VAR49),
.VAR35 (VAR21),
.VAR22 (VAR13),
.VAR29 (VAR52),
.VAR67 (VAR23),
.VAR4 (VAR64),
.VAR15 (VAR43),
.VAR68 (VAR55),
.VAR9 (VAR47),
.VAR31 (VAR65),
.VAR38 (VAR38),
.VAR11 (VAR11),
.VAR27 (VAR28),
.VAR24 (VAR26),
.VAR41 (VAR63),
.VAR69 (VAR2),
.VAR39 (VAR50),
.VAR46 (VAR17),
.VAR3 (VAR42),
.VAR51 (VAR30),
.VAR61 (VAR72),
.VAR16 ({VAR32, VAR53}),
.VAR44 (VAR60),
.VAR12 (VAR5),
.VAR34 (VAR20)
);
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.behavioral.pp.v | 2,375 | module MODULE1( VAR10, VAR6, VAR8, VAR1, VAR5, VAR2, VAR7 );
input VAR1, VAR5, VAR6, VAR10;
inout VAR2, VAR7;
output VAR8;
VAR3 VAR9(.VAR10(VAR10),.VAR6(VAR6),.VAR8(VAR8),.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7));
VAR3 VAR4(.VAR10(VAR10),.VAR6(VAR6),.VAR8(VAR8),.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7)); | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/dat_i_arbiter.v | 2,209 | module MODULE1(
input wire VAR5,
output wire [7:0] VAR2,
input [7:0] VAR12,
input VAR7,
input [7:0] VAR11,
input VAR3,
input [7:0] VAR6,
input VAR10,
input [7:0] VAR8,
input VAR16,
input [7:0] VAR9,
input VAR4,
input [7:0] VAR14,
input VAR15,
input [7:0] VAR13,
input VAR1
);
assign VAR2 = (VAR7) ? VAR12 :
(VAR3) ? VAR11 :
(VAR16) ? VAR8 :
(VAR10) ? VAR6 :
(VAR4) ? VAR9 :
(VAR15) ? VAR14 :
(VAR1) ? VAR13 :
8'd255;
endmodule | gpl-3.0 |
jmacneal/Design-Project | Display/VGA_Audio_PLL.v | 17,782 | module MODULE1 (
VAR95,
VAR6,
VAR87,
VAR81,
VAR14);
input VAR95;
input VAR6;
output VAR87;
output VAR81;
output VAR14;
tri0 VAR95;
wire [5:0] VAR52;
wire [0:0] VAR73 = 1'h0;
wire [2:2] VAR77 = VAR52[2:2];
wire [0:0] VAR43 = VAR52[0:0];
wire [1:1] VAR11 = VAR52[1:1];
wire VAR81 = VAR11;
wire VAR87 = VAR43;
wire VAR14 = VAR77;
wire VAR39 = VAR6;
wire [1:0] VAR103 = {VAR73, VAR39};
VAR89 VAR88 (
.VAR95 (VAR95),
.VAR79 (VAR103),
.clk (VAR52),
.VAR58 (),
.VAR74 (),
.VAR64 ({6{1'b1}}),
.VAR50 (),
.VAR105 (1'b0),
.VAR2 (1'b0),
.VAR46 (),
.VAR42 (),
.VAR13 (),
.VAR86 ({4{1'b1}}),
.VAR83 (1'b1),
.VAR25 (),
.VAR37 (),
.VAR24 (),
.VAR51 (),
.VAR31 (),
.VAR38 (1'b1),
.VAR69 ({4{1'b1}}),
.VAR36 (),
.VAR110 (1'b1),
.VAR84 (1'b1),
.VAR44 (1'b1),
.VAR78 (1'b0),
.VAR62 (1'b0),
.VAR4 (1'b1),
.VAR19 (1'b0),
.VAR12 (),
.VAR54 (),
.VAR75 (1'b0),
.VAR59 (1'b0),
.VAR7 (),
.VAR72 (),
.VAR9 (),
.VAR30 ());
VAR88.VAR96 = 15,
VAR88.VAR90 = 50,
VAR88.VAR47 = 14,
VAR88.VAR80 = "0",
VAR88.VAR76 = 3,
VAR88.VAR15 = 50,
VAR88.VAR1 = 2,
VAR88.VAR70 = "0",
VAR88.VAR56 = 15,
VAR88.VAR67 = 50,
VAR88.VAR85 = 14,
VAR88.VAR91 = "-9921",
VAR88.VAR93 = "VAR57",
VAR88.VAR23 = 37037,
VAR88.VAR45 = "VAR33 VAR22",
VAR88.VAR35 = "VAR89",
VAR88.VAR68 = "VAR106",
VAR88.VAR10 = "VAR41",
VAR88.VAR5 = "VAR29",
VAR88.VAR61 = "VAR41",
VAR88.VAR112 = "VAR41",
VAR88.VAR26 = "VAR41",
VAR88.VAR98 = "VAR41",
VAR88.VAR53 = "VAR41",
VAR88.VAR66 = "VAR41",
VAR88.VAR97 = "VAR29",
VAR88.VAR113 = "VAR41",
VAR88.VAR65 = "VAR41",
VAR88.VAR27 = "VAR41",
VAR88.VAR3 = "VAR41",
VAR88.VAR21 = "VAR41",
VAR88.VAR107 = "VAR41",
VAR88.VAR102 = "VAR41",
VAR88.VAR28 = "VAR41",
VAR88.VAR32 = "VAR41",
VAR88.VAR49 = "VAR41",
VAR88.VAR63 = "VAR41",
VAR88.VAR94 = "VAR41",
VAR88.VAR8 = "VAR41",
VAR88.VAR48 = "VAR41",
VAR88.VAR99 = "VAR41",
VAR88.VAR17 = "VAR41",
VAR88.VAR18 = "VAR29",
VAR88.VAR111 = "VAR29",
VAR88.VAR16 = "VAR29",
VAR88.VAR82 = "VAR41",
VAR88.VAR109 = "VAR41",
VAR88.VAR55 = "VAR41",
VAR88.VAR71 = "VAR41",
VAR88.VAR40 = "VAR41",
VAR88.VAR100 = "VAR41",
VAR88.VAR101 = "VAR41",
VAR88.VAR60 = "VAR41",
VAR88.VAR92 = "VAR41",
VAR88.VAR104 = "VAR41",
VAR88.VAR108 = "VAR41",
VAR88.VAR34 = "VAR41",
VAR88.VAR20 = "VAR41";
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux4/sky130_fd_sc_hd__mux4.blackbox.v | 1,339 | module MODULE1 (
VAR6 ,
VAR4,
VAR3,
VAR7,
VAR10,
VAR2,
VAR5
);
output VAR6 ;
input VAR4;
input VAR3;
input VAR7;
input VAR10;
input VAR2;
input VAR5;
supply1 VAR9;
supply0 VAR1;
supply1 VAR11 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/01BLUETOOTH/Version_02/02 verilog/periferico_BT/transmision.v | 1,666 | module MODULE1 (input enable,
input VAR5,
input reset,
input wire [7:0] din,
output VAR2,
output reg VAR3,
output reg VAR4);
parameter VAR1 = 8; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22oi/sky130_fd_sc_hd__a22oi.behavioral.pp.v | 2,164 | module MODULE1 (
VAR13 ,
VAR8 ,
VAR11 ,
VAR17 ,
VAR18 ,
VAR9,
VAR1,
VAR15 ,
VAR14
);
output VAR13 ;
input VAR8 ;
input VAR11 ;
input VAR17 ;
input VAR18 ;
input VAR9;
input VAR1;
input VAR15 ;
input VAR14 ;
wire VAR12 ;
wire VAR7 ;
wire VAR5 ;
wire VAR19;
nand VAR2 (VAR12 , VAR11, VAR8 );
nand VAR10 (VAR7 , VAR18, VAR17 );
and VAR16 (VAR5 , VAR12, VAR7 );
VAR4 VAR6 (VAR19, VAR5, VAR9, VAR1);
buf VAR3 (VAR13 , VAR19 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s.behavioral.pp.v | 1,766 | module MODULE1 (
VAR4,
VAR10,
VAR6 ,
VAR8
);
input VAR4;
input VAR10;
output VAR6 ;
input VAR8 ;
wire VAR5 ;
wire VAR1;
buf VAR7 (VAR5 , VAR8 );
VAR9 VAR2 (VAR1, VAR5, VAR4, VAR10);
buf VAR3 (VAR6 , VAR1 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_2.behavioral.v | 1,180 | module MODULE1( VAR2, VAR1, VAR3 );
input VAR2, VAR3;
output VAR1;
VAR5 VAR4(.VAR2(VAR2),.VAR1(VAR1),.VAR3(VAR3));
VAR5 VAR6(.VAR2(VAR2),.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
jotego/jt12 | hdl/adpcm/jt10_adpcmb.v | 3,929 | module MODULE1(
input VAR12,
input clk, input VAR5, input [3:0] VAR7,
input VAR6, input VAR24,
input VAR2,
output signed [15:0] VAR23
);
localparam VAR11 = 15, VAR20=16;
reg signed [VAR20-1:0] VAR19, VAR18;
reg [VAR11-1:0] VAR17;
reg [VAR11+1:0] VAR9;
assign VAR23 = VAR19[VAR20-1:VAR20-16];
wire [VAR20-1:0] VAR4 = {1'b0, {VAR20-1{1'b1}}};
wire [VAR20-1:0] VAR30 = {1'b1, {VAR20-1{1'b0}}};
reg [18:0] VAR26;
reg [VAR20-1:0] VAR14,VAR27;
reg [3:0] VAR21;
reg [7:0] VAR8;
reg [22:0] VAR28;
always @(*) begin
casez( VAR21[3:1] )
3'b0??: VAR8 = 8'd57;
3'b100: VAR8 = 8'd77;
3'b101: VAR8 = 8'd102;
3'b110: VAR8 = 8'd128;
3'b111: VAR8 = 8'd153;
endcase
VAR26 = VAR21 * VAR17; VAR28 = VAR8 * VAR17; end
reg [3:0] VAR22;
reg VAR25, VAR13, VAR15, VAR16;
reg [3:0] VAR3;
reg VAR29;
wire [3:0] VAR1 = VAR2 || ~VAR6 ? 4'd0 : VAR7;
always @( posedge clk or negedge VAR12 )
if( ! VAR12 ) begin
VAR19 <= 'd0; VAR17 <= 'd127;
VAR21 <= 'd0; VAR14 <= 'd0; VAR27 <= 'd0;
VAR29 <= 0;
end else begin
if( VAR2 )
VAR29 <= 1'd1;
if(VAR5) begin
VAR3 <= {1'b0,VAR3[3:1]};
if( VAR24 ) begin
VAR21 <= {VAR1[2:0],1'b1};
VAR25 <= VAR1[3];
VAR3[3] <= 1'b1;
end
VAR14 <= { {VAR20-16{1'b0}}, VAR26[18:3] }; VAR9<= VAR28[22:6];
VAR13<=VAR25;
VAR27 <= VAR13 ? ~VAR14+1'd1 : VAR14;
VAR15<=VAR13;
VAR18 <= VAR19+VAR27;
VAR16<=VAR15;
if( VAR6 ) begin if( VAR3[0] ) begin
if( VAR16 == VAR19[VAR20-1] && (VAR19[VAR20-1]!=VAR18[VAR20-1]) )
VAR19 <= VAR19[VAR20-1] ? VAR30 : VAR4;
end
else
VAR19 <= VAR18;
if( VAR9 < 127 )
VAR17 <= 15'd127;
end
else if( VAR9 > 24576 )
VAR17 <= 15'd24576;
end
else
VAR17 <= VAR9[14:0];
end
end else begin
VAR19 <= 'd0;
VAR17 <= 'd127;
end
if( VAR29 ) begin
VAR19 <= 'd0;
VAR17 <= 'd127;
VAR9 <= 'd127;
VAR21 <= 'd0; VAR14 <= 'd0; VAR27 <= 'd0;
VAR18 <= 'd0;
VAR29 <= 1'd0;
end
end
end
endmodule VAR10 | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2.blackbox.v | 1,227 | module MODULE1 (
VAR7,
VAR1,
VAR5
);
output VAR7;
input VAR1;
input VAR5;
supply1 VAR6;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.functional.pp.v | 1,027 | module MODULE1( VAR18, VAR11, VAR16, VAR8, VAR14, VAR13, VAR10, VAR6 );
input VAR18, VAR11, VAR8, VAR16, VAR13, VAR10, VAR6;
output VAR14;
not VAR12( VAR4, VAR18 );
not VAR17( VAR5, VAR8 );
not VAR19( VAR9, VAR16 );
not VAR15( VAR3, VAR11 );
VAR1( VAR2, VAR9, VAR5, VAR4, VAR3, VAR6 );
not VAR7( VAR14, VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4bb/sky130_fd_sc_lp__nand4bb.pp.blackbox.v | 1,357 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR6 ,
VAR4 ,
VAR7 ,
VAR2,
VAR3,
VAR5 ,
VAR8
);
output VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR7 ;
input VAR2;
input VAR3;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v | 5,482 | module MODULE1(
clk, rst,
VAR9, VAR3, VAR1,
addr, en, VAR2, VAR17, VAR6
);
parameter VAR4 = VAR5;
parameter VAR19 = VAR7;
input clk;
input rst;
input [VAR19-1:0] addr;
input en;
input [3:0] VAR2;
input [VAR4-1:0] VAR17;
output [VAR4-1:0] VAR6;
input VAR9;
input [VAR8 - 1:0] VAR1;
output VAR3;
assign VAR6 = {VAR4{1'b0}};
assign VAR3 = VAR9;
VAR11 VAR18(
VAR10 VAR18(
VAR13 VAR18(
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.clk(clk),
.rst(rst),
.VAR14(en),
.VAR2(VAR2[0]),
.VAR15(1'b1),
.addr(addr),
.VAR12(VAR17),
.VAR16(VAR6)
);
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2b/sky130_fd_sc_ms__or2b.symbol.v | 1,285 | module MODULE1 (
input VAR1 ,
input VAR4,
output VAR7
);
supply1 VAR6;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/slaveController/sctxportarbiter.v | 7,275 | module MODULE1 (VAR14, VAR22, VAR13, VAR32, VAR1, clk, VAR29, VAR9, VAR5, VAR12, VAR31, rst, VAR30, VAR23, VAR3, VAR25, VAR4);
input VAR13;
input clk;
input [7:0] VAR29;
input [7:0] VAR9;
input VAR12;
input VAR31;
input rst;
input [7:0] VAR30;
input [7:0] VAR23;
input VAR25;
input VAR4;
output [7:0] VAR14;
output [7:0] VAR22;
output VAR32;
output VAR1;
output VAR5;
output VAR3;
reg [7:0] VAR14, VAR7;
reg [7:0] VAR22, VAR2;
wire VAR13;
reg VAR32, VAR10;
reg VAR1, VAR6;
wire clk;
wire [7:0] VAR29;
wire [7:0] VAR9;
reg VAR5, VAR27;
wire VAR12;
wire VAR31;
wire rst;
wire [7:0] VAR30;
wire [7:0] VAR23;
reg VAR3, VAR18;
wire VAR25;
wire VAR4;
reg VAR17, VAR28;
reg [1:0] VAR26;
reg [1:0] VAR19;
always @(VAR13)
begin
VAR32 <= VAR13;
end
always @(VAR17 or
VAR31 or VAR9 or VAR29 or
VAR31 or VAR9 or VAR29 or
VAR4 or VAR23 or VAR30)
begin
if (VAR17 == 1'b1)
begin
VAR1 <= VAR31;
VAR22 <= VAR9;
VAR14 <= VAR29;
end
else
begin
VAR1 <= VAR4;
VAR22 <= VAR23;
VAR14 <= VAR30;
end
end
always @ (VAR25 or VAR12 or VAR3 or VAR17 or VAR5 or VAR26)
begin : VAR8
VAR19 <= VAR26;
VAR18 <= VAR3;
VAR28 <= VAR17;
VAR27 <= VAR5;
case (VAR26)
if (VAR25 == 1'b1)
begin
VAR19 <= VAR21;
VAR18 <= 1'b1;
VAR28 <= 1'b0;
end
else if (VAR12 == 1'b1)
begin
VAR19 <= VAR20;
VAR27 <= 1'b1;
VAR28 <= 1'b1;
end
if (VAR25 == 1'b0)
begin
VAR19 <= VAR11;
VAR18 <= 1'b0;
end
if (VAR12 == 1'b0)
begin
VAR19 <= VAR11;
VAR27 <= 1'b0;
end
VAR19 <= VAR11;
endcase
end
always @ (posedge clk)
begin : VAR15
if (rst)
VAR26 <= VAR16;
end
else
VAR26 <= VAR19;
end
always @ (posedge clk)
begin : VAR24
if (rst)
begin
VAR17 <= 1'b0;
VAR3 <= 1'b0;
VAR5 <= 1'b0;
end
else
begin
VAR17 <= VAR28;
VAR3 <= VAR18;
VAR5 <= VAR27;
end
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221o/sky130_fd_sc_hd__a221o.functional.v | 1,566 | module MODULE1 (
VAR9 ,
VAR10,
VAR12,
VAR5,
VAR4,
VAR6
);
output VAR9 ;
input VAR10;
input VAR12;
input VAR5;
input VAR4;
input VAR6;
wire VAR3 ;
wire VAR7 ;
wire VAR1;
and VAR2 (VAR3 , VAR5, VAR4 );
and VAR13 (VAR7 , VAR10, VAR12 );
or VAR8 (VAR1, VAR7, VAR3, VAR6);
buf VAR11 (VAR9 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22oi/sky130_fd_sc_hs__a22oi.pp.blackbox.v | 1,340 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR3 ,
VAR2 ,
VAR7 ,
VAR1,
VAR5
);
output VAR4 ;
input VAR6 ;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR1;
input VAR5;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf_2.v | 1,993 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR6,
VAR3,
VAR7 ,
VAR8
);
output VAR1 ;
input VAR5 ;
input VAR6;
input VAR3;
input VAR7 ;
input VAR8 ;
VAR4 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
supply1 VAR6;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR8 ;
VAR4 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32o/sky130_fd_sc_hd__a32o.functional.pp.v | 2,224 | module MODULE1 (
VAR19 ,
VAR12 ,
VAR20 ,
VAR5 ,
VAR18 ,
VAR13 ,
VAR11,
VAR8,
VAR10 ,
VAR15
);
output VAR19 ;
input VAR12 ;
input VAR20 ;
input VAR5 ;
input VAR18 ;
input VAR13 ;
input VAR11;
input VAR8;
input VAR10 ;
input VAR15 ;
wire VAR9 ;
wire VAR14 ;
wire VAR6 ;
wire VAR3;
and VAR2 (VAR9 , VAR5, VAR12, VAR20 );
and VAR7 (VAR14 , VAR18, VAR13 );
or VAR4 (VAR6 , VAR14, VAR9 );
VAR1 VAR16 (VAR3, VAR6, VAR11, VAR8);
buf VAR17 (VAR19 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_p_pp_pkg_sn.symbol.v | 1,467 | module MODULE1 (
input VAR7 ,
output VAR6 ,
input VAR1 ,
input VAR3 ,
input VAR8 ,
input VAR5,
input VAR4 ,
input VAR2
);
endmodule | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ip/cdn_axi_bfm_1/hdl/src/verilog/cdn_axi_bfm_1.v | 7,427 | module MODULE1 (VAR9, VAR15,
VAR19, VAR6, VAR1,
VAR41,VAR12,VAR39,VAR27, VAR38);
parameter VAR31 = "MODULE1";
parameter VAR2 = 24;
parameter VAR30 = 8;
parameter VAR20 = 4;
parameter VAR22 = 8;
parameter VAR13 = 10;
parameter VAR37 = 8;
parameter VAR3 = 8;
parameter VAR8 = 1;
parameter VAR21 = 0;
input wire VAR9;
input wire VAR15;
input wire VAR19; output wire VAR6; input wire [VAR2-1:0] VAR1; input wire [(VAR2/8)-1:0] VAR41; input wire VAR38; input wire [VAR30-1:0] VAR12; input wire [VAR20-1:0] VAR39; input wire [VAR22-1:0] VAR27;
VAR4 #(.VAR23(VAR31),
.VAR7(VAR2),
.VAR32(VAR30),
.VAR18(VAR20),
.VAR10(VAR22),
.VAR5(VAR13),
.VAR42(VAR37),
.VAR35(VAR8),
.VAR16(VAR21)
)
VAR28(.VAR17(VAR9),
.VAR26(VAR15),
.VAR29(VAR19),
.VAR36(VAR6),
.VAR24(VAR1),
.VAR33(VAR41),
.VAR34(VAR41),
.VAR25(VAR12),
.VAR14(VAR39),
.VAR40(VAR27),
.VAR11(VAR38)
);
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31a/sky130_fd_sc_hd__o31a.pp.blackbox.v | 1,368 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR8 ,
VAR2 ,
VAR5 ,
VAR1,
VAR6,
VAR7 ,
VAR4
);
output VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR1;
input VAR6;
input VAR7 ;
input VAR4 ;
endmodule | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/amber23/a23_multiply.v | 7,545 | module MODULE1 (
input VAR11,
input VAR21,
input [31:0] VAR23, input [31:0] VAR26, input [1:0] VAR17,
input VAR3,
output [31:0] VAR18,
output [1:0] VAR7, output reg VAR12 = 'd0 );
wire enable;
wire VAR20;
wire [33:0] VAR8;
wire [33:0] VAR4;
wire [33:0] sum;
wire [33:0] VAR5;
reg [5:0] VAR16 = 'd0;
reg [5:0] VAR24;
reg [67:0] VAR15 = 'd0;
reg [67:0] VAR13;
reg [1:0] VAR9;
wire [32:0] VAR6;
assign enable = VAR17[0];
assign VAR20 = VAR17[1];
assign VAR8 = { 2'd0, VAR23} ;
assign VAR4 = ~{ 2'd0, VAR23} + 34'd1 ;
assign VAR5 = VAR15[1:0] == 2'b01 ? VAR8 :
VAR15[1:0] == 2'b10 ? VAR4 :
34'd0 ;
VAR25 #(.VAR10(34))
VAR1 #(.VAR10(34))
VAR28 (
.VAR30 ( VAR15[67:34] ),
.VAR14 ( VAR5 ),
.VAR27 ( 1'd0 ),
.VAR22 ( 1'd0 ),
.VAR19 ( sum ),
.VAR29 ( )
);
VAR25 #(.VAR10(33))
VAR1 #(.VAR10(33))
VAR2 (
.VAR30 ( {1'd0, VAR15[32:1]} ),
.VAR14 ( {1'd0, VAR23} ),
.VAR27 ( 1'd0 ),
.VAR22 ( 1'd0 ),
.VAR19 ( VAR6 ),
.VAR29 ( )
);
assign sum = VAR15[67:34] + VAR5;
assign VAR6 = {1'd0, VAR15[32:1]} + {1'd0, VAR23};
always @*
begin
VAR24 = VAR16;
VAR13 = VAR15;
VAR9 = { VAR15[32], VAR15[32:1] == 32'd0 };
if ( VAR16 == 6'd0 )
VAR13 = {33'd0, 1'd0, VAR26, 1'd0 } ;
end
else if ( VAR16 <= 6'd33 )
VAR13 = { sum[33], sum, VAR15[33:1]} ;
else if ( VAR16 == 6'd34 && VAR20 )
begin
VAR13 = { VAR15[64:33], VAR6[31:0], 1'd0}; end
if (VAR16 == 6'd0) VAR24 = enable ? 6'd1 : 6'd0;
else if ((VAR16 == 6'd34 && !VAR20) || (VAR16 == 6'd35 && VAR20) ) VAR24 = 6'd0;
else
VAR24 = VAR16 + 1'd1;
end
always @ ( posedge VAR11 )
if ( !VAR21 )
begin
VAR16 <= VAR3 ? VAR24 : VAR16;
VAR15 <= VAR3 ? VAR13 : VAR15;
VAR12 <= VAR3 ? VAR16 == 6'd31 : VAR12;
end
assign VAR18 = VAR15[32:1];
assign VAR7 = VAR9;
endmodule | lgpl-3.0 |
UviDTE-UviSpace/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/camera_capture.v | 4,922 | module MODULE1 #(
parameter VAR20 = 12
) (
input VAR17,
input VAR16,
input [11:0] VAR25,
input [11:0] VAR9,
input VAR15,
input VAR22,
input VAR24,
input [VAR20-1:0] VAR4,
output [31:0] VAR8,
output VAR21,
output [VAR20-1:0] VAR2,
output [11:0] VAR18,
output [11:0] VAR13,
output VAR14
);
reg [11:0] VAR19;
reg [11:0] VAR3;
always @(posedge VAR17)
begin
if (!VAR16) begin
VAR19[11:0] <= {VAR25[10:0], 1'b0}; VAR3[11:0] <= {VAR9[10:0], 1'b0}; end
end
reg VAR7;
reg VAR7;
reg VAR1;
always @(posedge VAR17)
begin
if (VAR16) begin
VAR7 <= VAR7;
if (VAR7 && !VAR7) begin VAR1 <= 1'b0;
end
else if (VAR15) begin
VAR1 <= 1'b1;
end
end
else begin
VAR1 <= 1'b0;
end
end
reg VAR24;
reg VAR5;
reg VAR23;
reg [VAR20-1:0] VAR6;
reg [31:0] VAR26;
assign VAR8 = VAR26;
always @(posedge VAR17)
begin
VAR24 <= VAR24;
if (VAR1 & !VAR7) begin
VAR23 <= VAR24 & VAR22;
VAR6[VAR20-1:0] <= VAR4[VAR20-1:0];
if (VAR24 && !VAR24) begin VAR5 <= 1'b1;
end
else if(!VAR24 && VAR24) begin VAR5 <= 1'b0;
VAR26 <= VAR26+1;
end
end
else begin
VAR23 <= 1'b0;
VAR5 <= 1'b0;
VAR6[VAR20-1:0] <= 0;
end
end
reg valid;
reg [VAR20-1:0] VAR10;
reg [11:0] VAR12;
reg [11:0] VAR11;
always @(posedge VAR17)
begin
if (VAR1 & !VAR7) begin
valid <= VAR5 & VAR23;
VAR10[VAR20-1:0] <= VAR6[VAR20-1:0];
if (valid) begin
if (VAR12 < (VAR19 - 1)) begin
VAR12[11:0] <= VAR12[11:0] + 16'd1;
end
else begin
if (VAR11 < (VAR3 - 1)) begin
VAR12[11:0] <= 12'd0;
VAR11[11:0] <= VAR11[11:0] + 16'd1;
end
end
end
if ((VAR12 == (VAR19 - 1)) &&
(VAR11 == (VAR3 - 1))) begin
VAR7 <= 1'b1;
end
end
else begin
valid <= 1'b0;
VAR10[VAR20-1:0] <= 0;
VAR12[11:0] <= 12'd0;
VAR11[11:0] <= 12'd0;
VAR7 <= 1'b0;
end
end
assign VAR21 = valid;
assign VAR2[VAR20-1:0] = VAR10[VAR20-1:0];
assign VAR18[11:0] = VAR12[11:0];
assign VAR13[11:0] = VAR11[11:0];
assign VAR14 = (VAR1) ? VAR7 : 1'b1;
endmodule | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_impctl_sclk.v | 4,228 | module MODULE1(VAR28 ,VAR19 ,VAR29 ,VAR33 ,VAR36 ,VAR30 ,
VAR41 );
output VAR19 ;
output VAR29 ;
output VAR33 ;
input VAR28 ;
input VAR36 ;
input VAR30 ;
input VAR41 ;
wire [2:0] VAR49 ;
wire [3:0] VAR38 ;
wire [3:0] VAR32 ;
wire VAR46 ;
wire VAR52 ;
wire VAR14 ;
wire VAR22 ;
wire VAR7 ;
wire VAR27 ;
wire VAR4 ;
wire VAR16 ;
wire VAR6 ;
VAR2 VAR24 (
.VAR51 (VAR38[2] ),
.VAR26 (VAR7 ),
.VAR3 (VAR28 ),
.VAR34 (VAR32[2] ),
.VAR36 (VAR36 ),
.VAR1 (VAR22 ),
.VAR50 (VAR41 ) );
VAR47 VAR40 (
.VAR10 (VAR4 ),
.VAR44 (VAR30 ) );
VAR15 VAR31 (
.VAR10 (VAR32[1] ),
.VAR44 (VAR38[1] ),
.VAR37 (VAR49[0] ) );
VAR15 VAR45 (
.VAR10 (VAR32[2] ),
.VAR44 (VAR38[2] ),
.VAR37 (VAR49[1] ) );
VAR13 VAR21 (
.VAR10 (VAR32[0] ),
.VAR44 (VAR38[0] ) );
VAR15 VAR11 (
.VAR10 (VAR32[3] ),
.VAR44 (VAR38[3] ),
.VAR37 (VAR49[2] ) );
VAR47 VAR35 (
.VAR10 (VAR49[0] ),
.VAR44 (VAR32[0] ) );
VAR23 VAR17 (
.VAR10 (VAR46 ),
.VAR44 (VAR38[0] ),
.VAR37 (VAR38[1] ) );
VAR54 VAR48 (
.VAR10 (VAR19 ),
.VAR44 (VAR46 ) );
VAR47 VAR39 (
.VAR10 (VAR6 ),
.VAR44 (VAR38[2] ) );
VAR12 VAR25 (
.VAR10 (VAR49[2] ),
.VAR44 (VAR6 ),
.VAR37 (VAR46 ) );
VAR2 VAR9 (
.VAR51 (VAR29 ),
.VAR26 (VAR16 ),
.VAR3 (VAR28 ),
.VAR34 (VAR49[1] ),
.VAR36 (VAR36 ),
.VAR1 (VAR27 ),
.VAR50 (VAR41 ) );
VAR2 VAR42 (
.VAR51 (VAR38[0] ),
.VAR26 (VAR14 ),
.VAR3 (VAR28 ),
.VAR34 (VAR32[0] ),
.VAR36 (VAR36 ),
.VAR1 (VAR4 ),
.VAR50 (VAR41 ) );
VAR5 VAR8 (
.VAR10 (VAR33 ),
.VAR44 (VAR16 ) );
VAR13 VAR53 (
.VAR10 (VAR52 ),
.VAR44 (VAR19 ) );
VAR5 VAR20 (
.VAR10 (VAR49[1] ),
.VAR44 (VAR52 ) );
VAR2 VAR43 (
.VAR51 (VAR38[1] ),
.VAR26 (VAR22 ),
.VAR3 (VAR28 ),
.VAR34 (VAR32[1] ),
.VAR36 (VAR36 ),
.VAR1 (VAR14 ),
.VAR50 (VAR41 ) );
VAR2 VAR18 (
.VAR51 (VAR38[3] ),
.VAR26 (VAR27 ),
.VAR3 (VAR28 ),
.VAR34 (VAR32[3] ),
.VAR36 (VAR36 ),
.VAR1 (VAR7 ),
.VAR50 (VAR41 ) );
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe_3.v | 1,910 | module MODULE1 (
VAR3,
VAR2,
VAR6 ,
VAR4
);
input VAR3;
input VAR2;
input VAR6 ;
input VAR4 ;
VAR1 VAR5 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR4 ;
VAR1 VAR5 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb.functional.v | 1,068 | module MODULE1 ();
endmodule | apache-2.0 |
DreamSourceLab/DSLogic-hdl | src/loopback.v | 9,675 | module MODULE1(
input VAR42,
input VAR82,
input VAR46,
input VAR37,
input VAR60,
input VAR16,
input VAR36,
input mux,
input VAR68,
input VAR26,
output reg VAR81,
output reg VAR55,
output reg VAR10,
output [31:0] VAR53,
output VAR52,
output reg VAR72,
output reg [15:0] VAR54,
input VAR14,
input VAR59,
output reg VAR17,
output reg VAR18,
output VAR8,
output [31:0] VAR86,
output VAR90,
output reg VAR33,
input VAR85,
input [15:0] VAR43,
input VAR24,
output reg VAR58
);
parameter VAR7 = 32'hffffff;
parameter VAR80 = 3'b000;
parameter VAR50 = 3'b001;
parameter VAR35 = 3'b010;
parameter VAR20 = 3'b100;
parameter VAR28 = 3'b101;
wire VAR49;
wire VAR21;
wire VAR3;
reg [3:0] VAR47;
wire [3:0] VAR74;
reg [2:0] VAR64;
reg [2:0] VAR73;
reg VAR44;
wire VAR66;
reg VAR34;
wire VAR9;
reg VAR62;
reg VAR48;
reg VAR5;
reg VAR57;
reg VAR32;
reg VAR39;
assign VAR53 = VAR7;
assign VAR21 = ((VAR64 != VAR50) & (VAR73 == VAR50)) ? 1'b1 :
((VAR64 != VAR20) & (VAR73 == VAR20)) ? 1'b0 : VAR55;
assign VAR3 = ((VAR73 != VAR50) & (VAR73 != VAR20)) ? 1'b1 : 1'b0;
assign VAR49 = ((VAR64 != VAR50) & (VAR73 == VAR50)) ? 1'b1 :
((VAR64 != VAR20) & (VAR73 == VAR20)) ? 1'b1 :
~|VAR47 ? 1'b0 : VAR81;
assign VAR74 = ((VAR64 != VAR50) & (VAR73 == VAR50)) ? 4'b1111 :
((VAR64 != VAR20) & (VAR73 == VAR20)) ? 4'b1111 :
|VAR47 ? VAR47 - 1'b1 : VAR47;
always @(posedge VAR60 or posedge VAR16)
begin
if (VAR16) begin
VAR55 <= VAR22 1'b0;
VAR10 <= VAR22 1'b0;
VAR81 <= VAR22 1'b0;
VAR47 <= VAR22 4'b0;
end else begin
VAR55 <= VAR22 VAR21;
VAR10 <= VAR22 VAR3;
VAR81 <= VAR22 VAR49;
VAR47 <= VAR22 VAR74;
end
end
reg VAR79;
reg VAR84;
reg VAR70;
reg VAR13;
reg VAR4;
reg VAR89;
reg VAR83;
reg VAR1;
always @(posedge VAR60)
begin
VAR79 <= VAR22 VAR68;
VAR84 <= VAR22 VAR79;
VAR70 <= VAR22 VAR84;
VAR13 <= VAR22 VAR26;
VAR4 <= VAR22 VAR13;
VAR89 <= VAR22 VAR4;
VAR83 <= VAR22 VAR84 & VAR4;
VAR1 <= VAR22 VAR83;
end
assign VAR66 = ((VAR64 == VAR50) & VAR83) ? 1'b1 : 1'b0;
assign VAR9 = ((VAR64 == VAR20) & VAR83) ? 1'b1 : 1'b0;
always @(posedge VAR60 or posedge VAR16)
begin
if (VAR16) begin
VAR44 <= VAR22 1'b0;
VAR34 <= VAR22 1'b0;
end else begin
VAR44 <= VAR22 VAR66;
VAR34 <= VAR22 VAR9;
end
end
always @(posedge VAR60 or posedge VAR16)
begin
if (VAR16)
VAR64 <= VAR22 VAR80;
end
else
VAR64 <= VAR22 VAR73;
end
always @(*)
begin
case(VAR64)
VAR80:
if (VAR36 & VAR48 & VAR39)
VAR73 = VAR50;
end
else
VAR73 = VAR80;
VAR50:
if (VAR44)
VAR73 = VAR35;
end
else
VAR73 = VAR50;
VAR35:
if (VAR57)
VAR73 = VAR20;
else
VAR73 = VAR35;
VAR20:
if (VAR24)
VAR73 = VAR28;
else
VAR73 = VAR20;
VAR28:
if (VAR17)
VAR73 = VAR50;
else
VAR73 = VAR28;
default:
VAR73 = VAR80;
endcase
end
reg [7:0] VAR15;
reg VAR67;
wire VAR30;
assign VAR30 = |VAR15;
always @(posedge VAR46)
begin
VAR15 <= VAR22 {VAR15[6:0], VAR14};
VAR67 <= VAR22 VAR30;
end
always @(posedge VAR60)
begin
VAR62 <= VAR22 VAR59;
VAR48 <= VAR22 VAR62;
VAR32 <= VAR22 mux;
VAR39 <= VAR22 VAR32;
VAR5 <= VAR22 VAR67;
VAR57 <= VAR22 VAR5;
end
reg VAR87;
reg VAR29;
wire VAR2;
wire VAR31;
wire VAR19;
assign VAR2 = (VAR73 == VAR35);
assign VAR31 = (VAR73 == VAR28);
assign VAR19 = (VAR73 == VAR20) | (VAR73 == VAR28);
always @(posedge VAR60)
begin
VAR87 <= VAR22 VAR2;
VAR29 <= VAR22 VAR31;
VAR18 <= VAR22 VAR19;
end
reg VAR45;
reg VAR56;
reg VAR12;
always @(posedge VAR42)
begin
VAR45 <= VAR22 VAR87;
VAR56 <= VAR22 VAR45;
VAR12 <= VAR22 VAR56;
end
reg [31:0] VAR25;
wire [31:0] VAR63;
reg VAR88;
wire VAR6;
assign VAR6 = (VAR56 & ~VAR12) ? ~VAR88 : VAR88;
assign VAR63 = (VAR56 & ~VAR12) ? VAR7 :
VAR72 ? VAR25 - 1'b1 : VAR25;
always @(posedge VAR42 or posedge VAR82)
begin
if (VAR82) begin
VAR88 <= VAR22 1'b0;
VAR25 <= VAR22 VAR7;
end else begin
VAR88 <= VAR22 VAR6;
VAR25 <= VAR22 VAR63;
end
end
wire VAR76;
wire [31:0] VAR11;
assign VAR52 = VAR72 & ~|VAR25;
assign VAR76 = (VAR56 & ~VAR12) ? 1'b1 :
~|VAR25 ? 1'b0 : VAR72;
assign VAR11 = (~VAR88 & VAR72) ? VAR54 + 1'b1 :
(VAR88 & VAR72) ? VAR54 - 1'b1 : VAR54;
always @(posedge VAR42 or posedge VAR82)
begin
if (VAR82) begin
VAR54 <= VAR22 16'b0;
VAR72 <= VAR22 1'b0;
end else begin
VAR54 <= VAR22 VAR11;
VAR72 <= VAR22 VAR76;
end
end
reg [31:0] VAR75;
wire [31:0] VAR65;
reg VAR91;
wire VAR61;
reg VAR27;
reg VAR71;
reg VAR78;
always @(posedge VAR46)
begin
VAR27 <= VAR22 VAR29;
VAR71 <= VAR22 VAR27;
VAR78 <= VAR22 VAR71;
end
assign VAR8 = VAR71 & ~VAR78;
reg VAR40;
always @(posedge VAR60)
begin
VAR40 <= VAR22 VAR29;
end
assign VAR77 = VAR29 & ~VAR40;
assign VAR86 = 32'b0;
assign VAR90 = 1'b0;
wire VAR69;
assign VAR69 = VAR77 ? 1'b1 :
((VAR75 == 32'b0) & VAR33 & VAR85) ? 1'b0 : VAR33;
always @(posedge VAR60 or posedge VAR16)
begin
if (VAR16) begin
VAR33 <= VAR22 1'b0;
end else begin
VAR33 <= VAR22 VAR69;
end
end
assign VAR23 = VAR17 ? 1'b0 :
(VAR75 == 32'b0 & VAR33 & VAR85) ? 1'b1 : VAR17;
assign VAR61 = VAR77 ? ~VAR91 : VAR91;
assign VAR65 = VAR77 ? VAR7 :
(VAR33 & VAR85) ? VAR75 - 1'b1 : VAR75;
always @(posedge VAR60 or posedge VAR16)
begin
if (VAR16) begin
VAR75 <= VAR22 32'b0;
VAR17 <= VAR22 1'b0;
VAR91 <= VAR22 1'b0;
end else begin
VAR75 <= VAR22 VAR65;
VAR17 <= VAR22 VAR23;
VAR91 <= VAR22 VAR61;
end
end
reg [15:0] VAR41;
wire [15:0] VAR51;
wire VAR38;
assign VAR51 = (~VAR91 & VAR33 & VAR85) ? VAR41 + 1'b1 :
(VAR91 & VAR33 & VAR85) ? VAR41 - 1'b1 : VAR41;
assign VAR38 = (VAR33 & VAR85 & (VAR41 != VAR43) | VAR58) ? 1'b1 : 1'b0;
always @(posedge VAR60 or posedge VAR16)
begin
if (VAR16) begin
VAR41 <= VAR22 16'b0;
VAR58 <= VAR22 1'b0;
end else begin
VAR41 <= VAR22 VAR51;
VAR58 <= VAR22 VAR38;
end
end
endmodule | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_fpext.v | 11,328 | module MODULE1
(
VAR37,
VAR25,
VAR44,
VAR29) ;
input VAR37;
input VAR25;
input [31:0] VAR44;
output [63:0] VAR29;
tri1 VAR37;
reg [10:0] VAR34;
reg [34:0] VAR8;
reg VAR26;
reg VAR30;
reg VAR43;
reg [22:0] VAR23;
reg VAR12;
wire [10:0] VAR18;
wire VAR20;
wire [10:0] VAR16;
wire [10:0] VAR38;
wire VAR15;
wire [33:0] VAR7;
wire [34:0] VAR1;
wire [7:0] VAR27;
wire VAR35;
wire [7:0] VAR6;
wire [10:0] VAR46;
wire [10:0] VAR21;
wire [7:0] VAR24;
wire VAR36;
wire [2:0] VAR45;
wire [10:0] VAR28;
wire [7:0] VAR33;
wire VAR32;
wire [33:0] VAR2;
wire VAR4;
wire [33:0] VAR5;
wire [22:0] VAR10;
wire [21:0] VAR48;
wire [22:0] VAR40;
wire [22:0] VAR11;
wire VAR42;
wire [22:0] VAR22;
wire [22:0] VAR13;
wire VAR19;
wire [33:0] VAR14;
wire VAR47;
wire [33:0] VAR41;
wire VAR3;
wire VAR9;
wire [33:0] VAR17;
wire VAR39;
wire [33:0] VAR31; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2.symbol.v | 1,321 | module MODULE1 (
input VAR2,
output VAR3
);
supply1 VAR1;
supply0 VAR4;
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/dbg_interface/dbg_trace.v | 21,600 | module MODULE1 (VAR56, VAR100, VAR2, VAR68, VAR18, VAR95, VAR73,
VAR86, VAR9, VAR33, VAR97, VAR1,
VAR25, VAR77, VAR16, VAR96, VAR82, VAR34,
VAR49, VAR24, VAR50, VAR79, VAR21, VAR40,
VAR45, VAR63, VAR93, VAR58,
VAR91,
VAR7, VAR65, VAR87, VAR71,
VAR64, VAR10, VAR83, VAR35, VAR75,
VAR47, VAR29, VAR15, VAR37, VAR3, VAR13, VAR88,
VAR67, VAR11
);
parameter VAR5 = 1;
input [10:0] VAR56; input VAR100; input [31:0] VAR2; input [3:0] VAR18; input [1:0] VAR95;
input VAR86; input VAR9; input VAR75;
input VAR97; input VAR1;
input [10:0] VAR25; input VAR77; input [3:0] VAR16; input [1:0] VAR96; input [1:0] VAR82;
input [10:0] VAR34; input VAR49; input [3:0] VAR24; input [1:0] VAR50; input [1:0] VAR79;
input [10:0] VAR47; input VAR29; input [3:0] VAR15; input [1:0] VAR37; input [1:0] VAR3;
input VAR21; input VAR40; input VAR45; input VAR63; input VAR93; input VAR58; input VAR91;
input VAR7; input VAR65; input VAR87; input VAR71;
input VAR64; input VAR10; input VAR83; input VAR35;
input VAR13; input VAR88; input VAR67; input VAR11;
output [VAR31-1:0] VAR68; output VAR73; output [39:0] VAR33;
reg VAR43;
reg VAR22;
reg [VAR53:0] VAR94;
reg [VAR53-1:0] VAR20;
reg [VAR53-1:0] VAR36;
reg VAR32;
reg VAR39;
reg [VAR31-1:0] VAR28;
reg [VAR30-1:0] VAR12[0:VAR84-1];
reg VAR57;
wire VAR62 = |(VAR56[10:0] & VAR25[10:0]);
wire VAR42 = VAR100 & VAR77;
wire VAR99 = VAR18[3:0] == VAR16[3:0];
wire VAR90 = VAR95[1:0] == VAR96[1:0];
wire VAR55 = ( (VAR62 | ~VAR7)
& (VAR42 | ~VAR65)
& (VAR99 | ~VAR87)
& (VAR90 | ~VAR71)
)
& (VAR7 | VAR65 | VAR87 | VAR71);
wire VAR51 = ( (VAR62 & VAR7)
| (VAR42 & VAR65)
| (VAR99 & VAR87)
| (VAR90 & VAR71)
);
wire VAR98 = VAR22 & (~VAR82[1]? 1 : VAR82[0]? VAR55 : VAR51 );
wire VAR48 = |(VAR56[10:0] & VAR34[10:0]);
wire VAR52 = VAR100 & VAR49;
wire VAR8 = VAR18[3:0] == VAR24[3:0];
wire VAR17 = VAR95[1:0] == VAR50[1:0];
wire VAR60 = ( (VAR48 | ~VAR64)
& (VAR52 | ~VAR10)
& (VAR8 | ~VAR83)
& (VAR17 | ~VAR35)
)
& (VAR64 | VAR10 | VAR83 | VAR35);
wire VAR76 = ( (VAR48 & VAR64)
| (VAR52 & VAR10)
| (VAR8 & VAR83)
| (VAR17 & VAR35)
);
wire VAR38;
wire VAR6 = VAR22 & ~VAR38 & (~VAR79[1]? 1 : VAR79[0]? VAR60 : VAR76 );
wire VAR54 = |(VAR56[10:0] & VAR47[10:0]);
wire VAR19 = VAR100 & VAR29;
wire VAR72 = VAR18[3:0] == VAR15[3:0];
wire VAR26 = VAR95[1:0] == VAR37[1:0];
wire VAR59 = ( (VAR54 | ~VAR13)
& (VAR19 | ~VAR88)
& (VAR72 | ~VAR67)
& (VAR26 | ~VAR11)
)
& (VAR13 | VAR88 | VAR67 | VAR11);
wire VAR69 = ( (VAR54 & VAR13)
| (VAR19 & VAR88)
| (VAR72 & VAR67)
| (VAR26 & VAR11)
);
assign VAR38 = VAR22 & (~VAR3[1]? 0 : VAR3[0]? VAR59 : VAR69 );
always @(posedge VAR86 or posedge VAR9)
begin
if(VAR9)
VAR57<=#VAR5 0;
end
else
if(VAR57 & ~VAR22)
VAR57<=#VAR5 0;
else
if(VAR98)
VAR57<=#VAR5 1;
end
always @(posedge VAR86 or posedge VAR9)
begin
if(VAR9)
begin
VAR43<=#VAR5 0;
VAR22<=#VAR5 0;
end
else
begin
VAR43<=#VAR5 VAR1;
VAR22<=#VAR5 VAR43;
end
end
reg VAR81;
wire [VAR92-1:0] VAR14;
wire VAR80 = VAR94[VAR53:0]==VAR84;
wire VAR66 = VAR94[VAR53:0]==0;
wire VAR74 = VAR39 & ~(VAR80 | VAR81) & VAR6 & VAR14[VAR28];
wire VAR23 = VAR39 & (~VAR80 | VAR97) & VAR6 & VAR14[VAR28];
wire VAR4 = VAR23;
wire VAR41 = VAR75 & ~VAR66 & (~VAR97 | VAR97 & ~VAR22);
wire VAR70 = VAR74 ^ VAR41;
wire VAR46;
wire VAR44;
reg VAR85;
reg VAR101;
reg VAR27;
always @(posedge VAR86)
begin
VAR27<=#VAR5 VAR6;
VAR85<=#VAR5 VAR80;
VAR101<=#VAR5 VAR85;
VAR39 <=#VAR5 VAR73;
end
wire VAR89 = VAR6 & ~VAR27 & VAR57 |
VAR27 & VAR98 & ~VAR57 |
VAR6 & VAR98 & ~VAR27 & ~VAR57 ;
wire VAR61 = VAR73 & ~VAR39 |
VAR27 & VAR57 &
(
(~VAR97 & ~VAR80 & ~VAR85 & VAR28==VAR92-1) |
(~VAR97 & ~VAR85 & VAR101 & VAR28==0) |
( VAR97 & VAR28==VAR92-1)
);
assign VAR46 = (
(~VAR97 & ~VAR80 & ~VAR85 & VAR28==VAR92-2) |
(~VAR97 & ~VAR80 & VAR85 & VAR28==VAR92-1) |
( VAR97 & VAR28==VAR92-2)
);
assign VAR73 = VAR89 | VAR32;
always @(posedge VAR86 or posedge VAR9)
begin
if(VAR9)
VAR94<=#VAR5 0;
end
else
if(VAR70)
if(VAR74)
VAR94[VAR53:0]<=#VAR5 VAR94[VAR53:0] + 1;
else
VAR94[VAR53:0]<=#VAR5 VAR94[VAR53:0] - 1;
end
always @(posedge VAR86 or posedge VAR9)
begin
if(VAR9)
VAR20<=#VAR5 0;
end
else
if(VAR23)
VAR20[VAR53-1:0]<=#VAR5 VAR20[VAR53-1:0] + 1;
end
always @(posedge VAR86 or posedge VAR9)
begin
if(VAR9)
VAR36<=#VAR5 0;
end
else
if(VAR41 & ~VAR97 | VAR41 & VAR97 & ~VAR22)
VAR36[VAR53-1:0]<=#VAR5 VAR36[VAR53-1:0] + 1;
else
if(VAR97 & VAR23 & (VAR80 | VAR81))
VAR36[VAR53-1:0]<=#VAR5 VAR20[VAR53-1:0] + 1;
end
always @(posedge VAR86)
begin
if(~VAR22)
VAR81<=#VAR5 0;
end
else
if(VAR97 & VAR80)
VAR81<=#VAR5 1;
end
always @(posedge VAR86 or posedge VAR9)
begin
if(VAR9)
VAR32<=#VAR5 0;
end
else
if(VAR46)
VAR32<=#VAR5 0;
else
if(VAR61)
VAR32<=#VAR5 1;
end
always @(posedge VAR86)
begin
if(VAR44)
VAR28<=#VAR5 0;
end
else
if(VAR39 & (~VAR80 | VAR97))
VAR28<=#VAR5 VAR28+1;
end
assign VAR44 = VAR28==(VAR92-1) & ~VAR80 | VAR9;
wire VAR78 = ~VAR66;
always @ (posedge VAR86)
begin
if(VAR4)
VAR12[VAR20[VAR53-1:0]]<={VAR2, 1'b0, VAR68[VAR31-1:0]};
end
assign VAR33 = {VAR12[VAR36], 3'h0, VAR78};
assign VAR68[VAR31-1:0] = VAR28[VAR31-1:0];
assign VAR14 = {1'b0, VAR91, VAR58, VAR93, VAR63, VAR45, VAR40, VAR21};
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtp/sky130_fd_sc_lp__dlxtp.pp.symbol.v | 1,333 | module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR4,
input VAR7 ,
input VAR5,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
davidkoltak/tawas-core | ip/enet/rtl/sgmii_autoneg.v | 9,273 | module MODULE1
(
input rst,
input VAR3,
input [7:0] VAR5,
input VAR13,
input VAR6,
output VAR10,
output VAR11,
output VAR21,
output VAR19,
output [15:0] VAR20
);
parameter VAR8 = 16'd40000;
reg [5:0] VAR2;
wire [5:0] VAR9 = (VAR2 + 6'd1);
reg VAR1;
reg VAR7;
reg VAR12;
reg VAR18;
reg [15:0] VAR15;
reg [15:0] VAR17;
reg [15:0] VAR14;
reg [15:0] VAR4;
wire VAR16 = VAR6 || (VAR13 && (VAR5 == 8'd0));
assign VAR10 = VAR1;
assign VAR11 = VAR7;
assign VAR21 = VAR12;
assign VAR19 = VAR18;
assign VAR20 = VAR4;
always @ (posedge VAR3 or posedge rst)
if (rst)
begin
VAR2 <= 6'd0;
VAR1 <= 1'b0;
VAR7 <= 1'b0;
VAR12 <= 1'b0;
VAR18 <= 1'b0;
VAR15 <= 16'd0;
VAR17 <= 16'd0;
VAR14 <= 16'd0;
VAR4 <= 16'd0;
end
else
case (VAR2)
6'd0:
begin
VAR2 <= 6'd1;
VAR1 <= 1'b0;
VAR7 <= 1'b0;
VAR12 <= 1'b0;
VAR18 <= 1'b0;
VAR15 <= 16'd0;
VAR17 <= 16'd0;
VAR14 <= 16'd0;
VAR4 <= 16'd0;
end
6'd1: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd1;
6'd2: VAR2 <= (!VAR13 && (VAR5 == 8'hB5)) ? VAR9 : 6'd1;
6'd3: VAR2 <= (VAR13) ? 6'd0 : VAR9;
6'd4: VAR2 <= (VAR13) ? 6'd0 : VAR9;
6'd5: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd0;
6'd6: VAR2 <= (!VAR13 && (VAR5 == 8'h42)) ? VAR9 : 6'd0;
6'd7: VAR2 <= (VAR13) ? 6'd0 : VAR9;
6'd8: VAR2 <= (VAR13) ? 6'd0 : 6'd11;
6'd11: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd0;
6'd12: VAR2 <= (!VAR13 && (VAR5 == 8'hB5)) ? VAR9 : 6'd0;
6'd13:
begin
VAR1 <= 1'b1;
VAR15 <= VAR15 + 16'd1;
VAR17[7:0] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 : VAR9;
end
6'd14:
begin
VAR17[15:8] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 : VAR9;
end
6'd15: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd0;
6'd16: VAR2 <= (!VAR13 && (VAR5 == 8'h42)) ? VAR9 : 6'd0;
6'd17:
begin
VAR14[7:0] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 : VAR9;
end
6'd18:
begin
VAR14[15:8] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 :
(VAR15 == VAR8) ? 6'd21 : 6'd11;
end
6'd21: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd0;
6'd22: VAR2 <= (!VAR13 && (VAR5 == 8'hB5)) ? VAR9 : 6'd0;
6'd23:
begin
VAR15 <= 16'd0;
VAR17[7:0] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 : VAR9;
end
6'd24:
begin
VAR17[15:8] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 : VAR9;
end
6'd25: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd0;
6'd26: VAR2 <= (!VAR13 && (VAR5 == 8'h42)) ? VAR9 : 6'd0;
6'd27:
begin
VAR14[7:0] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 : VAR9;
end
6'd28:
begin
VAR14[15:8] <= VAR5;
VAR4 <= VAR14;
VAR2 <= (VAR13) ? 6'd0 : (VAR17[0] && VAR14[0] && VAR4[0]) ? 6'd31 : 6'd21;
end
6'd31: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd0;
6'd32: VAR2 <= (!VAR13 && (VAR5 == 8'hB5)) ? VAR9 : 6'd0;
6'd33:
begin
VAR7 <= 1'b1;
VAR17[7:0] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 : VAR9;
end
6'd34:
begin
VAR17[15:8] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 : VAR9;
end
6'd35: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd0;
6'd36: VAR2 <= (!VAR13 && (VAR5 == 8'h42)) ? VAR9 : 6'd0;
6'd37:
begin
VAR14[7:0] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 : VAR9;
end
6'd38:
begin
VAR14[15:8] <= VAR5;
VAR4 <= VAR14;
VAR2 <= (VAR13) ? 6'd0 :
(VAR17[14] && VAR17[0] && VAR14[14] && VAR14[0] && VAR4[14] && VAR4[0]) ? 6'd41 : 6'd31;
end
6'd41: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd0;
6'd42: VAR2 <= (VAR13) ? 6'd0 : (VAR5 == 8'hB5) ? VAR9 :
((VAR5 == 8'hC5) || (VAR5 == 8'h50)) ? 6'd51 : 6'd0;
6'd43:
begin
VAR15 <= VAR15 + 16'd1;
VAR17[7:0] <= VAR5;
VAR2 <= (VAR13 || (VAR17 != VAR14) || (VAR17 != VAR4)) ? 6'd0 : VAR9;
end
6'd44:
begin
VAR17[15:8] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 : VAR9;
end
6'd45: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd0;
6'd46: VAR2 <= (!VAR13 && (VAR5 == 8'h42)) ? VAR9 : 6'd0;
6'd47:
begin
VAR14[7:0] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 : VAR9;
end
6'd48:
begin
VAR14[15:8] <= VAR5;
VAR2 <= (VAR13) ? 6'd0 :
(VAR15 == VAR8) ? 6'd51 : 6'd41;
end
6'd51:
begin
VAR12 <= 1'b1;
VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd51;
end
6'd52: VAR2 <= (!VAR13 && (VAR5 == 8'hB5)) ? 6'd59 :
(!VAR13 && ((VAR5 == 8'h50) || (VAR5 == 8'hC5))) ? VAR9 : 6'd51;
6'd53: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd51;
6'd54: VAR2 <= (!VAR13 && ((VAR5 == 8'h50) || (VAR5 == 8'hC5))) ? VAR9 : 6'd51;
6'd55: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd51;
6'd56: VAR2 <= (!VAR13 && ((VAR5 == 8'h50) || (VAR5 == 8'hC5))) ? VAR9 : 6'd51;
6'd57: VAR2 <= (VAR13 && (VAR5 == 8'hBC)) ? VAR9 : 6'd51;
6'd58: VAR2 <= (!VAR13 && ((VAR5 == 8'h50) || (VAR5 == 8'hC5))) ? 6'd61 : 6'd51;
6'd59: VAR2 <= (!VAR13 && (VAR5 != VAR4[7:0])) ? 6'd0 : 6'd60;
6'd60: VAR2 <= (!VAR13 && (VAR5 != VAR4[15:8])) ? 6'd0 : 6'd51;
6'd61:
begin
VAR18 <= 1'b1;
VAR2 <= VAR9;
end
6'd62:
VAR2 <= (VAR16) ? 6'd0 :
(VAR13 && (VAR5 == 8'hBC)) ? VAR9 : VAR2;
6'd63:
VAR2 <= (VAR16) ? 6'd0 :
(!VAR13 && ((VAR5 == 8'hB5) || (VAR5 == 8'h42))) ? 6'd0 : 6'd62;
default: VAR2 <= 6'd0;
endcase
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.behavioral.v | 2,510 | module MODULE1( VAR2, VAR7, VAR4, VAR3 );
input VAR7, VAR2, VAR4;
output VAR3;
VAR6 VAR5(.VAR2(VAR2),.VAR7(VAR7),.VAR4(VAR4),.VAR3(VAR3));
VAR6 VAR1(.VAR2(VAR2),.VAR7(VAR7),.VAR4(VAR4),.VAR3(VAR3)); | apache-2.0 |
swallat/yosys | techlibs/achronix/speedster22i/cells_map.v | 3,682 | module \VAR24 (input VAR26, VAR15, output VAR17);
parameter VAR23="VAR20";
VAR45 #(.VAR39(VAR23)) VAR19 (.VAR16(VAR26), .VAR35(VAR17), .clk(VAR15), .VAR28(1'b1), .VAR42(1'b1), .VAR18(1'b1), .VAR37(1'b0), .VAR12(1'b0), .VAR27(1'b0), .VAR6(1'b0));
endmodule
module \VAR41 (input VAR26, VAR15, output VAR17);
parameter VAR23="VAR20";
VAR45 #(.VAR39(VAR23)) VAR19 (.VAR16(VAR26), .VAR35(VAR17), .clk(VAR15), .VAR28(1'b1), .VAR42(1'b1), .VAR18(1'b1), .VAR37(1'b0), .VAR12(1'b0), .VAR27(1'b0), .VAR6(1'b0));
endmodule
module \VAR25 (input VAR26, VAR15, VAR8, output VAR17);
parameter VAR23="VAR20";
VAR45 #(.VAR39(VAR23)) VAR19 (.VAR16(VAR26), .VAR35(VAR17), .clk(VAR15), .VAR28(VAR8), .VAR42(1'b1), .VAR18(1'b1), .VAR37(1'b0), .VAR12(1'b0), .VAR27(1'b0), .VAR6(1'b0));
endmodule
module \VAR5 (input VAR26, VAR15, VAR8, output VAR17);
parameter VAR23="VAR20";
wire VAR36 = ~ VAR8;
VAR45 #(.VAR39(VAR23)) VAR19 (.VAR16(VAR26), .VAR35(VAR17), .clk(VAR15), .VAR28(VAR36), .VAR42(1'b1), .VAR18(1'b1), .VAR37(1'b0), .VAR12(1'b0), .VAR27(1'b0), .VAR6(1'b0));
endmodule
module \VAR25 (input VAR26, VAR15, VAR8, output VAR17);
parameter VAR23="VAR20";
VAR45 #(.VAR39(VAR23)) VAR19 (.VAR16(VAR26), .VAR35(VAR17), .clk(VAR15), .VAR28(VAR8), .VAR42(1'b1), .VAR18(1'b1), .VAR37(1'b0), .VAR12(1'b0), .VAR27(1'b0), .VAR6(1'b0));
endmodule
module \VAR34 (input VAR26, VAR15, VAR32, VAR8, output VAR17);
parameter VAR23="VAR20";
wire VAR31 = ~ VAR32;
VAR45 #(.VAR39(VAR23)) VAR19 (.VAR16(VAR26), .VAR35(VAR17), .clk(VAR15), .VAR28(VAR8), .VAR42(1'b1), .VAR18(1'b1), .VAR37(1'b0), .VAR12(1'b0), .VAR27(VAR31), .VAR6(1'b0));
endmodule
module \VAR29 (input VAR11, output VAR40);
VAR33 VAR19 (.VAR46(VAR40), .VAR10(VAR11));
endmodule
module \VAR38 (input VAR11, output VAR40);
VAR2 VAR19 (.VAR46(VAR40), .VAR10(VAR11), .VAR14(1'b1));
endmodule
module MODULE9 (VAR21, VAR1);
parameter VAR22 = 0;
parameter VAR3 = 0;
input [VAR22-1:0] VAR21;
output VAR1;
generate
if (VAR22 == 1) begin
assign VAR1 = ~VAR21[0]; end else
if (VAR22 == 2) begin
VAR43 #(.VAR30({4{VAR3}})) VAR19 (.dout(VAR1), .VAR13(VAR21[0]), .VAR44(VAR21[1]), .VAR4(1'b0),.VAR9(1'b0));
end else
if(VAR22 == 3) begin
VAR43 #(.VAR30({2{VAR3}})) VAR19 (.dout(VAR1), .VAR13(VAR21[0]), .VAR44(VAR21[1]), .VAR4(VAR21[2]),.VAR9(1'b0));
end else
if(VAR22 == 4) begin
VAR43 #(.VAR30(VAR3)) VAR19 (.dout(VAR1), .VAR13(VAR21[0]), .VAR44(VAR21[1]), .VAR4(VAR21[2]), .VAR9(VAR21[3]));
end else
wire VAR7 = 1;
endgenerate
endmodule | isc |
8l/beri | cherilibs/trunk/peripherals/TERASIC_ISP1761/ISP1761_IF.v | 2,682 | module MODULE1(
VAR6,
VAR16,
VAR3,
VAR1,
VAR17,
VAR18,
VAR21,
VAR23,
VAR20,
VAR15,
VAR7,
VAR9,
VAR10,
VAR11,
VAR4,
VAR5,
VAR2,
VAR13,
VAR14,
VAR19,
VAR8,
VAR12
);
input VAR6;
input VAR16;
input VAR3;
input [15:0] VAR1;
input VAR17;
input [31:0] VAR18;
input VAR21;
output [31:0] VAR23;
output VAR20;
output VAR15;
output [31:0] VAR7;
output VAR9;
output VAR10;
output VAR11;
inout [31:0] VAR4;
output [17:1] VAR5;
input VAR2;
input VAR13;
input VAR14;
input VAR19;
output VAR8;
output VAR12;
assign VAR9 = VAR3;
assign VAR10 = VAR17;
assign VAR11 = VAR21;
assign VAR5 = {VAR1[15:0],1'b0};
assign VAR20 = VAR13;
assign VAR15 = VAR2;
assign VAR4 = (!VAR3 & VAR21) ? VAR18 : 32'VAR22;
assign VAR23 = VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32o/sky130_fd_sc_hd__a32o.behavioral.v | 1,676 | module MODULE1 (
VAR12 ,
VAR6,
VAR2,
VAR8,
VAR10,
VAR9
);
output VAR12 ;
input VAR6;
input VAR2;
input VAR8;
input VAR10;
input VAR9;
supply1 VAR4;
supply0 VAR17;
supply1 VAR16 ;
supply0 VAR5 ;
wire VAR15 ;
wire VAR13 ;
wire VAR7;
and VAR1 (VAR15 , VAR8, VAR6, VAR2 );
and VAR14 (VAR13 , VAR10, VAR9 );
or VAR11 (VAR7, VAR13, VAR15);
buf VAR3 (VAR12 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv_lp.v | 2,003 | module MODULE2 (
VAR2 ,
VAR1 ,
VAR6,
VAR8,
VAR7 ,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR6;
input VAR8;
input VAR7 ;
input VAR4 ;
VAR3 VAR5 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
supply1 VAR6;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR4 ;
VAR3 VAR5 (
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule | apache-2.0 |