system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} | code for sm_80
Function : _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IMAD R7, R9.reuse, c[0x0][0x170], RZ ; /* 0x00005c0009077a24 */
/* 0x041fe400078e02ff */
/*0070*/ IMAD R9, R9, c[0x0][0x174], RZ ; /* 0x00005d0009097a24 */
/* 0x000fe400078e02ff */
/*0080*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x001fe40000011400 */
/*0090*/ IADD3 R2, P0, P1, R0, c[0x0][0x160], R7 ; /* 0x0000580000027a10 */
/* 0x000fc8000791e007 */
/*00a0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590005037a10 */
/* 0x000fcc00007e24ff */
/*00b0*/ LDG.E.U8 R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1100 */
/*00c0*/ IADD3 R4, P0, P1, R0.reuse, c[0x0][0x168], R9 ; /* 0x00005a0000047a10 */
/* 0x040fe4000791e009 */
/*00d0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, P1 ; /* 0x00005b0005057a10 */
/* 0x000fe400007e24ff */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc60003f06270 */
/*0100*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041f4000c101104 */
/*0110*/ @!P0 BRA 0x80 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} | .file "tmpxft_00097a77_00000000-6_PadMatrixInLeadingDimensionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
.type _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii, @function
_Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z33PadMatrixInLeadingDimensionKernelPKaPaii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii, .-_Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii, @function
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, .-_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z33PadMatrixInLeadingDimensionKernelPKaPaii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z33PadMatrixInLeadingDimensionKernelPKaPaii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 8
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii,@function
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x14
s_load_b32 s0, s[0:1], 0x24
s_mul_i32 s3, s15, s2
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s4, s3
s_mul_i32 s15, s15, s8
s_addc_u32 s4, s5, 0
s_add_u32 s5, s6, s15
s_addc_u32 s6, s7, 0
s_and_b32 s7, s0, 0xffff
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v0
v_add_co_u32 v1, vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s4, v3, vcc_lo
global_load_u8 v4, v[1:2], off
v_add_co_u32 v1, vcc_lo, s5, v0
v_add_nc_u32_e32 v0, s7, v0
v_add_co_ci_u32_e32 v2, vcc_lo, s6, v3, vcc_lo
v_cmp_le_i32_e64 s0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
global_store_b8 v[1:2], v4, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, .Lfunc_end0-_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z33PadMatrixInLeadingDimensionKernelPKaPaii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PadMatrixInLeadingDimensionKernel(const int8_t* src, int8_t* dst, int col_src, int col_dst) {
for (int32_t i = threadIdx.x; i < col_src; i += blockDim.x) {
*(dst + blockIdx.x * col_dst + i) = *(src + blockIdx.x * col_src + i);
}
} | .text
.file "PadMatrixInLeadingDimensionKernel.hip"
.globl _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii # -- Begin function _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 4, 0x90
.type _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii,@function
_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii: # @_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z33PadMatrixInLeadingDimensionKernelPKaPaii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii, .Lfunc_end0-_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33PadMatrixInLeadingDimensionKernelPKaPaii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii,@object # @_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .rodata,"a",@progbits
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 3, 0x0
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
.quad _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33PadMatrixInLeadingDimensionKernelPKaPaii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IMAD R7, R9.reuse, c[0x0][0x170], RZ ; /* 0x00005c0009077a24 */
/* 0x041fe400078e02ff */
/*0070*/ IMAD R9, R9, c[0x0][0x174], RZ ; /* 0x00005d0009097a24 */
/* 0x000fe400078e02ff */
/*0080*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x001fe40000011400 */
/*0090*/ IADD3 R2, P0, P1, R0, c[0x0][0x160], R7 ; /* 0x0000580000027a10 */
/* 0x000fc8000791e007 */
/*00a0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590005037a10 */
/* 0x000fcc00007e24ff */
/*00b0*/ LDG.E.U8 R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1100 */
/*00c0*/ IADD3 R4, P0, P1, R0.reuse, c[0x0][0x168], R9 ; /* 0x00005a0000047a10 */
/* 0x040fe4000791e009 */
/*00d0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, P1 ; /* 0x00005b0005057a10 */
/* 0x000fe400007e24ff */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc60003f06270 */
/*0100*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041f4000c101104 */
/*0110*/ @!P0 BRA 0x80 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 8
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii,@function
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x14
s_load_b32 s0, s[0:1], 0x24
s_mul_i32 s3, s15, s2
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s4, s3
s_mul_i32 s15, s15, s8
s_addc_u32 s4, s5, 0
s_add_u32 s5, s6, s15
s_addc_u32 s6, s7, 0
s_and_b32 s7, s0, 0xffff
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v0
v_add_co_u32 v1, vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s4, v3, vcc_lo
global_load_u8 v4, v[1:2], off
v_add_co_u32 v1, vcc_lo, s5, v0
v_add_nc_u32_e32 v0, s7, v0
v_add_co_ci_u32_e32 v2, vcc_lo, s6, v3, vcc_lo
v_cmp_le_i32_e64 s0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
global_store_b8 v[1:2], v4, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, .Lfunc_end0-_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z33PadMatrixInLeadingDimensionKernelPKaPaii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00097a77_00000000-6_PadMatrixInLeadingDimensionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
.type _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii, @function
_Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z33PadMatrixInLeadingDimensionKernelPKaPaii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii, .-_Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii, @function
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z33PadMatrixInLeadingDimensionKernelPKaPaiiPKaPaii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, .-_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z33PadMatrixInLeadingDimensionKernelPKaPaii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z33PadMatrixInLeadingDimensionKernelPKaPaii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "PadMatrixInLeadingDimensionKernel.hip"
.globl _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii # -- Begin function _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 4, 0x90
.type _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii,@function
_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii: # @_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z33PadMatrixInLeadingDimensionKernelPKaPaii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii, .Lfunc_end0-_Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33PadMatrixInLeadingDimensionKernelPKaPaii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33PadMatrixInLeadingDimensionKernelPKaPaii,@object # @_Z33PadMatrixInLeadingDimensionKernelPKaPaii
.section .rodata,"a",@progbits
.globl _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.p2align 3, 0x0
_Z33PadMatrixInLeadingDimensionKernelPKaPaii:
.quad _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.size _Z33PadMatrixInLeadingDimensionKernelPKaPaii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33PadMatrixInLeadingDimensionKernelPKaPaii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__PadMatrixInLeadingDimensionKernelPKaPaii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33PadMatrixInLeadingDimensionKernelPKaPaii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
cudaMalloc((void**)&pA, (N*N)*sizeof(float));
cudaMalloc((void**)&pB, (N*N)*sizeof(float));
cudaMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
cudaMemcpy(pA, A, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pB, B, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pC, C, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
cudaMemcpy(C, pC, (N*N)*sizeof(float), cudaMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} | code for sm_80
Function : _Z7MatMultPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R5, c[0x0][0x17c] ; /* 0x00005f0000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fe2000f8e3c3f */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e2a0000209400 */
/*0050*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf23270 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc40000000a00 */
/*0070*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00b0*/ IADD3 R4, RZ, -R3, RZ ; /* 0x80000003ff047210 */
/* 0x002fca0007ffe0ff */
/*00c0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*00d0*/ IABS R4, c[0x0][0x178] ; /* 0x00005e0000047a13 */
/* 0x000fc60000000000 */
/*00e0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*00f0*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0100*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fe200078e00ff */
/*0110*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e260000002200 */
/*0120*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0130*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe20003f44070 */
/*0150*/ IMAD R4, R7, c[0x0][0x17c], R2 ; /* 0x00005f0007047a24 */
/* 0x001fd800078e0202 */
/*0160*/ @!P2 IADD3 R0, R0, -R5.reuse, RZ ; /* 0x800000050000a210 */
/* 0x080fe40007ffe0ff */
/*0170*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0190*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f45270 */
/*01a0*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*01b0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e2c0000002100 */
/*01c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ MOV R11, R3 ; /* 0x00000003000b7202 */
/* 0x000fe20000000f00 */
/*01e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fc800000001ff */
/*01f0*/ @!P1 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b9224 */
/* 0x000fe200078e0a0b */
/*0200*/ @!P2 LOP3.LUT R11, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff0baa12 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe20003f06270 */
/*0220*/ IMAD R5, R5, c[0x0][0x17c], R0 ; /* 0x00005f0005057a24 */
/* 0x001fd800078e0200 */
/*0230*/ @!P0 BRA 0xaf0 ; /* 0x000008b000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R3, R11.reuse, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x040fe20007ffe0ff */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT R6, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b067812 */
/* 0x000fe400078ec0ff */
/*0270*/ ISETP.GE.U32.AND P2, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f46070 */
/*0280*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f06270 */
/*0290*/ SHF.L.U32 R9, R2, 0x3, RZ ; /* 0x0000000302097819 */
/* 0x000fe400000006ff */
/*02a0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc40003f25270 */
/*02b0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*02c0*/ ISETP.LT.AND P0, PT, R5, c[0x0][0x178], !P0 ; /* 0x00005e0005007a0c */
/* 0x000fe40004701270 */
/*02d0*/ LEA R8, R0, R9, 0x2 ; /* 0x0000000900087211 */
/* 0x000fe200078e10ff */
/*02e0*/ @!P2 BRA 0x910 ; /* 0x000006200000a947 */
/* 0x000fea0003800000 */
/*02f0*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe20000000f00 */
/*0300*/ IMAD R18, R4, c[0x0][0x178], R0 ; /* 0x00005e0004127a24 */
/* 0x000fe200078e0200 */
/*0310*/ IADD3 R20, R2, c[0x0][0x17c], RZ ; /* 0x00005f0002147a10 */
/* 0x000fe20007ffe0ff */
/*0320*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0330*/ LEA R16, R13.reuse, R2, 0x1 ; /* 0x000000020d107211 */
/* 0x040fe200078e08ff */
/*0340*/ IMAD R14, R13, 0x3, R2 ; /* 0x000000030d0e7824 */
/* 0x000fe200078e0202 */
/*0350*/ BSSY B0, 0x910 ; /* 0x000005b000007945 */
/* 0x000fe20003800000 */
/*0360*/ IADD3 R10, -R11, R6, RZ ; /* 0x000000060b0a7210 */
/* 0x000fe20007ffe1ff */
/*0370*/ IMAD R12, R13, c[0x0][0x178], RZ ; /* 0x00005e000d0c7a24 */
/* 0x000fc400078e02ff */
/*0380*/ IMAD R9, R13.reuse, 0x3, R18 ; /* 0x000000030d097824 */
/* 0x040fe200078e0212 */
/*0390*/ LEA R13, R13, R18, 0x1 ; /* 0x000000120d0d7211 */
/* 0x000fe200078e08ff */
/*03a0*/ IMAD R19, R2, c[0x0][0x178], R5.reuse ; /* 0x00005e0002137a24 */
/* 0x100fe400078e0205 */
/*03b0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*03c0*/ IMAD R23, R20, c[0x0][0x178], R5.reuse ; /* 0x00005e0014177a24 */
/* 0x100fe400078e0205 */
/*03d0*/ IMAD R21, R14, c[0x0][0x178], R5.reuse ; /* 0x00005e000e157a24 */
/* 0x100fe400078e0205 */
/*03e0*/ IMAD R11, R16, c[0x0][0x178], R5 ; /* 0x00005e00100b7a24 */
/* 0x000fc400078e0205 */
/*03f0*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff100424 */
/* 0x000fc800078e00ff */
/*0400*/ @P0 IMAD.WIDE.U32 R14, R18, R16, c[0x0][0x160] ; /* 0x00005800120e0625 */
/* 0x000fc800078e0010 */
/*0410*/ @P0 IMAD.WIDE.U32 R16, R19, R16, c[0x0][0x168] ; /* 0x00005a0013100625 */
/* 0x000fe200078e0010 */
/*0420*/ @P0 LDG.E R25, [R14.64] ; /* 0x000000040e190981 */
/* 0x0000a8000c1e1900 */
/*0430*/ @P0 LDG.E R27, [R16.64] ; /* 0x00000004101b0981 */
/* 0x0002e2000c1e1900 */
/*0440*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0450*/ @P0 IADD3 R20, R18, c[0x0][0x17c], RZ ; /* 0x00005f0012140a10 */
/* 0x000fe40007ffe0ff */
/*0460*/ @P0 MOV R22, 0x4 ; /* 0x0000000400160802 */
/* 0x000fca0000000f00 */
/*0470*/ @P0 IMAD.WIDE.U32 R14, R20, R22, c[0x0][0x160] ; /* 0x00005800140e0625 */
/* 0x001fc800078e0016 */
/*0480*/ @P0 IMAD.WIDE.U32 R16, R23, R22, c[0x0][0x168] ; /* 0x00005a0017100625 */
/* 0x002fe200078e0016 */
/*0490*/ @P0 STS [R8], R25 ; /* 0x0000001908000388 */
/* 0x004fe80000000800 */
/*04a0*/ @P0 STS [R8+0x10], R27 ; /* 0x0000101b08000388 */
/* 0x0081e80000000800 */
/*04b0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*04c0*/ @P0 LDS R26, [R0.X4+0x10] ; /* 0x00001000001a0984 */
/* 0x000fe80000004800 */
/*04d0*/ @P0 LDS R24, [R2.X8] ; /* 0x0000000002180984 */
/* 0x000e680000008800 */
/*04e0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*04f0*/ @P0 LDS R28, [R0.X4+0x18] ; /* 0x00001800001c0984 */
/* 0x000fe80000004800 */
/*0500*/ @P0 LDS R25, [R2.X8+0x4] ; /* 0x0000040002190984 */
/* 0x000ea80000008800 */
/*0510*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0520*/ @P0 LDG.E R27, [R14.64] ; /* 0x000000040e1b0981 */
/* 0x0010e8000c1e1900 */
/*0530*/ @P0 LDG.E R29, [R16.64] ; /* 0x00000004101d0981 */
/* 0x000962000c1e1900 */
/*0540*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0550*/ @P0 FFMA R24, R26, R24, R3 ; /* 0x000000181a180223 */
/* 0x002fc80000000003 */
/*0560*/ @P0 FFMA R3, R28, R25, R24 ; /* 0x000000191c030223 */
/* 0x004fe20000000018 */
/*0570*/ @P0 MOV R16, 0x4 ; /* 0x0000000400100802 */
/* 0x010fca0000000f00 */
/*0580*/ @P0 IMAD.WIDE.U32 R14, R13, R16, c[0x0][0x160] ; /* 0x000058000d0e0625 */
/* 0x001fc800078e0010 */
/*0590*/ @P0 IMAD.WIDE.U32 R16, R11, R16, c[0x0][0x168] ; /* 0x00005a000b100625 */
/* 0x000fe200078e0010 */
/*05a0*/ @P0 STS [R8], R27 ; /* 0x0000001b08000388 */
/* 0x008fe80000000800 */
/*05b0*/ @P0 STS [R8+0x10], R29 ; /* 0x0000101d08000388 */
/* 0x0201e80000000800 */
/*05c0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*05d0*/ @P0 LDS R20, [R0.X4+0x10] ; /* 0x0000100000140984 */
/* 0x000fe80000004800 */
/*05e0*/ @P0 LDS R22, [R2.X8] ; /* 0x0000000002160984 */
/* 0x000e680000008800 */
/*05f0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0600*/ @P0 LDS R27, [R0.X4+0x18] ; /* 0x00001800001b0984 */
/* 0x000fe80000004800 */
/*0610*/ @P0 LDS R26, [R2.X8+0x4] ; /* 0x00000400021a0984 */
/* 0x000ea80000008800 */
/*0620*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0630*/ @P0 LDG.E R29, [R14.64] ; /* 0x000000040e1d0981 */
/* 0x0010e8000c1e1900 */
/*0640*/ @P0 LDG.E R28, [R16.64] ; /* 0x00000004101c0981 */
/* 0x000962000c1e1900 */
/*0650*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0660*/ @P0 FFMA R20, R20, R22, R3 ; /* 0x0000001614140223 */
/* 0x002fc80000000003 */
/*0670*/ @P0 FFMA R3, R27, R26, R20 ; /* 0x0000001a1b030223 */
/* 0x004fe20000000014 */
/*0680*/ @P0 MOV R16, 0x4 ; /* 0x0000000400100802 */
/* 0x010fca0000000f00 */
/*0690*/ @P0 IMAD.WIDE.U32 R14, R9, R16, c[0x0][0x160] ; /* 0x00005800090e0625 */
/* 0x001fc800078e0010 */
/*06a0*/ @P0 IMAD.WIDE.U32 R16, R21, R16, c[0x0][0x168] ; /* 0x00005a0015100625 */
/* 0x000fe200078e0010 */
/*06b0*/ @P0 STS [R8], R29 ; /* 0x0000001d08000388 */
/* 0x008fe80000000800 */
/*06c0*/ @P0 STS [R8+0x10], R28 ; /* 0x0000101c08000388 */
/* 0x020fe80000000800 */
/*06d0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*06e0*/ @P0 LDS R24, [R0.X4+0x10] ; /* 0x0000100000180984 */
/* 0x000fe80000004800 */
/*06f0*/ @P0 LDS R25, [R2.X8] ; /* 0x0000000002190984 */
/* 0x000e280000008800 */
/*0700*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0710*/ @P0 LDS R20, [R0.X4+0x18] ; /* 0x0000180000140984 */
/* 0x000fe80000004800 */
/*0720*/ @P0 LDS R27, [R2.X8+0x4] ; /* 0x00000400021b0984 */
/* 0x000e680000008800 */
/*0730*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0740*/ @P0 LDG.E R15, [R14.64] ; /* 0x000000040e0f0981 */
/* 0x0004e8000c1e1900 */
/*0750*/ @P0 LDG.E R17, [R16.64] ; /* 0x0000000410110981 */
/* 0x000962000c1e1900 */
/*0760*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0770*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007ffe0ff */
/*0780*/ @P0 FFMA R24, R24, R25, R3 ; /* 0x0000001918180223 */
/* 0x001fe20000000003 */
/*0790*/ LEA R23, R12.reuse, R23, 0x2 ; /* 0x000000170c177211 */
/* 0x040fe200078e10ff */
/*07a0*/ IMAD R21, R12.reuse, 0x4, R21 ; /* 0x000000040c157824 */
/* 0x040fe200078e0215 */
/*07b0*/ LEA R19, R12, R19, 0x2 ; /* 0x000000130c137211 */
/* 0x000fe200078e10ff */
/*07c0*/ IMAD.IADD R14, R10, 0x1, R7 ; /* 0x000000010a0e7824 */
/* 0x004fe200078e0207 */
/*07d0*/ LEA R11, R12, R11, 0x2 ; /* 0x0000000b0c0b7211 */
/* 0x000fe200078e10ff */
/*07e0*/ @P0 FFMA R3, R20, R27, R24 ; /* 0x0000001b14030223 */
/* 0x002fe20000000018 */
/*07f0*/ MOV R16, c[0x0][0x17c] ; /* 0x00005f0000107a02 */
/* 0x010fc40000000f00 */
/*0800*/ ISETP.NE.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f45270 */
/*0810*/ LEA R9, R16.reuse, R9, 0x2 ; /* 0x0000000910097211 */
/* 0x040fe200078e10ff */
/*0820*/ IMAD R18, R16.reuse, 0x4, R18 ; /* 0x0000000410127824 */
/* 0x040fe200078e0212 */
/*0830*/ LEA R13, R16, R13, 0x2 ; /* 0x0000000d100d7211 */
/* 0x000fe200078e10ff */
/*0840*/ @P0 STS [R8], R15 ; /* 0x0000000f08000388 */
/* 0x008fe80000000800 */
/*0850*/ @P0 STS [R8+0x10], R17 ; /* 0x0000101108000388 */
/* 0x020fe80000000800 */
/*0860*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0870*/ @P0 LDS R22, [R0.X4+0x10] ; /* 0x0000100000160984 */
/* 0x000fe80000004800 */
/*0880*/ @P0 LDS R26, [R2.X8] ; /* 0x00000000021a0984 */
/* 0x000e280000008800 */
/*0890*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*08a0*/ @P0 LDS R29, [R0.X4+0x18] ; /* 0x00001800001d0984 */
/* 0x000fe80000004800 */
/*08b0*/ @P0 LDS R28, [R2.X8+0x4] ; /* 0x00000400021c0984 */
/* 0x000e620000008800 */
/*08c0*/ @P0 FFMA R22, R22, R26, R3 ; /* 0x0000001a16160223 */
/* 0x001fc80000000003 */
/*08d0*/ @P0 FFMA R3, R29, R28, R22 ; /* 0x0000001c1d030223 */
/* 0x002fe20000000016 */
/*08e0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*08f0*/ @P2 BRA 0x3f0 ; /* 0xfffffaf000002947 */
/* 0x000fea000383ffff */
/*0900*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0910*/ BSSY B0, 0xaf0 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0920*/ @!P1 BRA 0xae0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0930*/ IMAD R10, R7.reuse, c[0x0][0x17c], R2 ; /* 0x00005f00070a7a24 */
/* 0x040fe400078e0202 */
/*0940*/ IMAD R7, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007077a24 */
/* 0x000fc400078e0200 */
/*0950*/ IMAD R9, R10, c[0x0][0x178], R5 ; /* 0x00005e000a097a24 */
/* 0x000fe400078e0205 */
/*0960*/ IMAD R7, R4, c[0x0][0x178], R7 ; /* 0x00005e0004077a24 */
/* 0x000fe400078e0207 */
/*0970*/ @P0 MOV R12, 0x4 ; /* 0x00000004000c0802 */
/* 0x000fca0000000f00 */
/*0980*/ @P0 IMAD.WIDE.U32 R10, R7, R12, c[0x0][0x160] ; /* 0x00005800070a0625 */
/* 0x000fc800078e000c */
/*0990*/ @P0 IMAD.WIDE.U32 R12, R9, R12, c[0x0][0x168] ; /* 0x00005a00090c0625 */
/* 0x000fe400078e000c */
/*09a0*/ @P0 LDG.E R11, [R10.64] ; /* 0x000000040a0b0981 */
/* 0x0000a8000c1e1900 */
/*09b0*/ @P0 LDG.E R13, [R12.64] ; /* 0x000000040c0d0981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*09d0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ IADD3 R7, R7, c[0x0][0x17c], RZ ; /* 0x00005f0007077a10 */
/* 0x000fc40007ffe0ff */
/*09f0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*0a00*/ MOV R10, c[0x0][0x17c] ; /* 0x00005f00000a7a02 */
/* 0x001fca0000000f00 */
/*0a10*/ IMAD R9, R10, c[0x0][0x178], R9 ; /* 0x00005e000a097a24 */
/* 0x000fe200078e0209 */
/*0a20*/ @P0 STS [R8], R11 ; /* 0x0000000b08000388 */
/* 0x004fe80000000800 */
/*0a30*/ @P0 STS [R8+0x10], R13 ; /* 0x0000100d08000388 */
/* 0x008fe80000000800 */
/*0a40*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0a50*/ @P0 LDS R14, [R0.X4+0x10] ; /* 0x00001000000e0984 */
/* 0x000fe80000004800 */
/*0a60*/ @P0 LDS R15, [R2.X8] ; /* 0x00000000020f0984 */
/* 0x000e280000008800 */
/*0a70*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0a80*/ @P0 LDS R17, [R0.X4+0x18] ; /* 0x0000180000110984 */
/* 0x000fe80000004800 */
/*0a90*/ @P0 LDS R16, [R2.X8+0x4] ; /* 0x0000040002100984 */
/* 0x000e620000008800 */
/*0aa0*/ @P0 FFMA R14, R14, R15, R3 ; /* 0x0000000f0e0e0223 */
/* 0x001fc80000000003 */
/*0ab0*/ @P0 FFMA R3, R17, R16, R14 ; /* 0x0000001011030223 */
/* 0x002fe2000000000e */
/*0ac0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0ad0*/ @P1 BRA 0x970 ; /* 0xfffffe9000001947 */
/* 0x000fea000383ffff */
/*0ae0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0af0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fe20000000f00 */
/*0b00*/ IMAD R4, R4, c[0x0][0x178], R5 ; /* 0x00005e0004047a24 */
/* 0x000fc800078e0205 */
/*0b10*/ IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0207 */
/*0b20*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
cudaMalloc((void**)&pA, (N*N)*sizeof(float));
cudaMalloc((void**)&pB, (N*N)*sizeof(float));
cudaMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
cudaMemcpy(pA, A, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pB, B, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pC, C, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
cudaMemcpy(C, pC, (N*N)*sizeof(float), cudaMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} | .file "tmpxft_00139677_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4absff
.type _Z4absff, @function
_Z4absff:
.LFB2059:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L7
.L4:
ret
.L7:
xorps .LC1(%rip), %xmm0
ret
.cfi_endproc
.LFE2059:
.size _Z4absff, .-_Z4absff
.globl _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
.type _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii, @function
_Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7MatMultPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
.globl _Z7MatMultPfS_S_ii
.type _Z7MatMultPfS_S_ii, @function
_Z7MatMultPfS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7MatMultPfS_S_ii, .-_Z7MatMultPfS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Kernel matrix multiplication time: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "TEST PASSED\n"
.text
.globl _Z12HostFunctionPA_fS0_S0_ii
.type _Z12HostFunctionPA_fS0_S0_ii, @function
_Z12HostFunctionPA_fS0_S0_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 48(%rsp)
movl %ecx, %r15d
movl %r8d, 60(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
testl %ecx, %ecx
jle .L17
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movslq %ecx, %r14
salq $2, %r14
movl $0, 56(%rsp)
.L18:
movq 24(%rsp), %r13
movq 16(%rsp), %r12
movq 8(%rsp), %rbp
movl $0, %ebx
.L19:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, (%r12)
movl $0x00000000, 0(%r13)
movl %ebx, %eax
addl $1, %ebx
addq %r14, %rbp
addq %r14, %r12
addq %r14, %r13
cmpl %ebx, %r15d
jne .L19
movl 56(%rsp), %ebx
leal 1(%rbx), %edx
addq $4, 8(%rsp)
addq $4, 16(%rsp)
addq $4, 24(%rsp)
cmpl %eax, %ebx
je .L17
movl %edx, 56(%rsp)
jmp .L18
.L17:
movl %r15d, %ebx
imull %r15d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 68(%rsp)
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl 60(%rsp), %eax
movl %eax, 112(%rsp)
movl %eax, 116(%rsp)
movl $1, 120(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC9(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC4(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L20:
cvttss2sil %xmm3, %eax
movl %eax, 124(%rsp)
movl %eax, 128(%rsp)
movl $1, 132(%rsp)
movl 120(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movq 124(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L21:
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movq 104(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %rdi
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 96(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq dsize(%rip), %rdi
call malloc@PLT
movq %rax, %rbx
testl %r15d, %r15d
jle .L22
movq 32(%rsp), %r10
movslq %r15d, %rax
leaq 0(,%rax,4), %rsi
movq 40(%rsp), %r13
addq %rsi, %r13
negq %rax
leaq 0(,%rax,4), %r11
movl $0, %ebp
movl $0, %r12d
jmp .L23
.L35:
movl 60(%rsp), %r8d
movl %r15d, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
jmp .L21
.L29:
movl %eax, %edi
.L25:
movq %r8, %r9
leaq (%rcx,%r11), %rax
movq %r10, %rdx
pxor %xmm1, %xmm1
.L24:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq %rsi, %rdx
addq $4, %rax
cmpq %rcx, %rax
jne .L24
movss %xmm1, (%r9)
leal 1(%rdi), %eax
addq %rsi, %r8
addq %rsi, %rcx
cmpl %eax, %r15d
jne .L29
leal 1(%rbp), %eax
addq $4, %r10
addq $4, %rbx
cmpl %edi, %ebp
je .L30
movl %eax, %ebp
.L23:
movq %r13, %rcx
movq %rbx, %r8
movl %r12d, %edi
jmp .L25
.L30:
movl $0, %ecx
.L26:
movl $0, %eax
.L27:
movl %eax, %edx
addl $1, %eax
cmpl %edx, %edi
jne .L27
leal 1(%rcx), %eax
cmpl %ecx, %edi
je .L22
movl %eax, %ecx
jmp .L26
.L22:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12HostFunctionPA_fS0_S0_ii, .-_Z12HostFunctionPA_fS0_S0_ii
.section .rodata.str1.1
.LC10:
.string "Tile Width = %d:\n"
.LC11:
.string "N = %d\n"
.LC12:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $2, 16(%rsp)
movl $4, 20(%rsp)
movl $10, 24(%rsp)
movl $20, 28(%rsp)
movl $25, 32(%rsp)
movl $100, 48(%rsp)
movl $200, 52(%rsp)
movl $500, 56(%rsp)
movl $1500, 60(%rsp)
movl $5000, 64(%rsp)
movl $2, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %r14
leaq 64(%rsp), %r15
.L38:
movl (%r14), %r13d
movl %r13d, %ebx
imull %r13d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, dsize(%rip)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %r8d
movl %r13d, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z12HostFunctionPA_fS0_S0_ii
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
addq $4, %r14
cmpq %r14, %r15
jne .L38
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %r13
leaq 36(%rsp), %rax
movq %rax, 8(%rsp)
leaq .LC12(%rip), %r15
.L39:
movl 0(%r13), %r14d
movl %r14d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $100000000, dsize(%rip)
movl $100000000, %edi
call malloc@PLT
movq %rax, %r12
movl $100000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $100000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $5000, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %r8d
movl $5000, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z12HostFunctionPA_fS0_S0_ii
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r13
cmpq %r13, 8(%rsp)
jne .L39
movq stdin(%rip), %rdi
call getc@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z7MatMultPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7MatMultPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dsize
.bss
.align 8
.type dsize, @object
.size dsize, 8
dsize:
.zero 8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1092616192
.align 4
.LC3:
.long 805306368
.align 4
.LC4:
.long 1258291200
.align 4
.LC6:
.long 1065353216
.align 4
.LC9:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
cudaMalloc((void**)&pA, (N*N)*sizeof(float));
cudaMalloc((void**)&pB, (N*N)*sizeof(float));
cudaMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
cudaMemcpy(pA, A, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pB, B, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(pC, C, (N*N)*sizeof(float), cudaMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
cudaMemcpy(C, pC, (N*N)*sizeof(float), cudaMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
hipMalloc((void**)&pA, (N*N)*sizeof(float));
hipMalloc((void**)&pB, (N*N)*sizeof(float));
hipMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
hipMemcpy(pA, A, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pB, B, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pC, C, (N*N)*sizeof(float), hipMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
hipMemcpy(C, pC, (N*N)*sizeof(float), hipMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
hipFree(pA);
hipFree(pB);
hipFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
hipMalloc((void**)&pA, (N*N)*sizeof(float));
hipMalloc((void**)&pB, (N*N)*sizeof(float));
hipMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
hipMemcpy(pA, A, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pB, B, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pC, C, (N*N)*sizeof(float), hipMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
hipMemcpy(C, pC, (N*N)*sizeof(float), hipMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
hipFree(pA);
hipFree(pB);
hipFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7MatMultPfS_S_ii
.globl _Z7MatMultPfS_S_ii
.p2align 8
.type _Z7MatMultPfS_S_ii,@function
_Z7MatMultPfS_S_ii:
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s9, 31
s_ashr_i32 s6, s8, 31
s_add_i32 s3, s9, s2
s_add_i32 s7, s8, s6
s_xor_b32 s3, s3, s2
s_xor_b32 s7, s7, s6
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s5, 0, s3
v_mad_u64_u32 v[4:5], null, s15, s9, v[2:3]
s_xor_b32 s2, s6, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s4, v1
v_mad_u64_u32 v[0:1], null, s14, s9, v[3:4]
v_mul_lo_u32 v1, v4, s8
s_mul_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s7, s4
s_mul_i32 s5, s4, s3
s_add_i32 s6, s4, 1
s_sub_i32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s7, s5, s3
s_cmp_ge_u32 s5, s3
s_cselect_b32 s4, s6, s4
s_cselect_b32 s5, s7, s5
s_add_i32 s6, s4, 1
s_cmp_ge_u32 s5, s3
s_cselect_b32 s3, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
s_sub_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v7, 2, v3
v_max_i32_e32 v6, v0, v4
v_lshlrev_b32_e32 v4, 3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 16, v7
v_cmp_gt_i32_e32 vcc_lo, s8, v6
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v6, v1, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v4, v7
v_add_nc_u32_e32 v8, v5, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, s3
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz .LBB0_2
s_mul_i32 s2, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v13, s2, v2
v_add_nc_u32_e32 v9, s2, v6
v_mad_u64_u32 v[11:12], null, v13, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v12, v10
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, s2, s4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s2, s5, v10, s2
v_add_co_u32 v11, s2, s6, v11
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s2, s7, v12, s2
s_mov_b32 s2, 0
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v5
s_waitcnt vmcnt(1)
ds_store_b32 v7, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_5:
v_add_nc_u32_e32 v10, s2, v4
s_add_i32 s2, s2, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 8, v9
s_cmp_eq_u32 s2, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fmac_f32_e32 v3, v10, v11
s_cbranch_scc1 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
v_mov_b32_e32 v3, 0
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7MatMultPfS_S_ii
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7MatMultPfS_S_ii, .Lfunc_end0-_Z7MatMultPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7MatMultPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7MatMultPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// thread block size
#define BLOCKDIM 16
#define TILE_WIDTH 2
// threshold
#define TOLERANCE 0.01
float absf(float n);
__global__ void MatMult(float *a, float *b, float *c, int N, int tileWidth) {
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int i = blockIdx.x * tileWidth + threadIdx.x;
int j = blockIdx.y * tileWidth + threadIdx.y;
int index = i + j * N;
float PValue = 0;
for (int k = 0; k < N/tileWidth; ++k) {
if (i < N && j < N) {
Mds[threadIdx.y][threadIdx.x] = a[j*N + (k*tileWidth + threadIdx.x)];
Nds[threadIdx.y][threadIdx.x] = b[i + (k*tileWidth + threadIdx.y)*N];
__syncthreads();
for (int m = 0; m < TILE_WIDTH; m++) {
PValue += Mds[threadIdx.y][m] * Nds[m][threadIdx.x];
__syncthreads();
}
}
}
c[index] = PValue;
//printf("%d %d %f\n", i, j, total);
}
typedef float myMat[];
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth);
size_t dsize;
int main() {
myMat *A, *B, *C;
int tileWidths[5] = { 2, 4, 10, 20, 25 };
int Nsizes[5] = { 100, 200, 500, 1500, 5000 };
int tileWidth = TILE_WIDTH;
printf("Tile Width = %d:\n", tileWidth);
for (int i = 0; i < 4; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
//5000 matricies, they take foreverrrr
for (int j = 0; j < 5; j++) {
int tileWidth = tileWidths[j];
printf("Tile Width = %d:\n", tileWidth);
for (int i = 4; i < 5; i++) {
int N = Nsizes[i];
dsize = N*N*sizeof(float);
A = (myMat*)malloc(dsize);
B = (myMat*)malloc(dsize);
C = (myMat*)malloc(dsize);
printf("N = %d\n", N);
HostFunction(A, B, C, N, tileWidth);
printf("\n");
free(A);
free(B);
free(C);
}
printf("\n");
}
getc(stdin);
return 0;
}
void HostFunction(myMat* A, myMat* B, myMat* C, int N, int tileWidth) {
//Initialize matricies
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*A)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*B)[index] = 10 * (float)rand() / (float)RAND_MAX;
(*C)[index] = 0.0f;
}
}
//Pointers to matricies
float *pA, *pB, *pC;
//Allocate matrices in device memory
hipMalloc((void**)&pA, (N*N)*sizeof(float));
hipMalloc((void**)&pB, (N*N)*sizeof(float));
hipMalloc((void**)&pC, (N*N)*sizeof(float));
/*
float time = 0;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
addHandler(pA, pB, pC, N);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Kernal function time: %f\n", time);*/
//Copy matrices from host memory to device memory
hipMemcpy(pA, A, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pB, B, (N*N)*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(pC, C, (N*N)*sizeof(float), hipMemcpyHostToDevice);
//KERNEL CALL
//Each thread produces 1 output matrix element
float time = 0;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
dim3 threadsPerBlock(tileWidth, tileWidth);
dim3 numBlocks((int)ceil(N / (float)tileWidth), (int)ceil(N / (float)tileWidth));
MatMult <<<numBlocks, threadsPerBlock>>>(pA, pB, pC, N, tileWidth);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
printf("Kernel matrix multiplication time: %f\n", time);
//Copy result from device memory to host memory
hipMemcpy(C, pC, (N*N)*sizeof(float), hipMemcpyDeviceToHost);
//Compute matrix multiplication using the CPU
myMat *CTemp;
CTemp = (myMat*)malloc(dsize);
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int index = i + j * N;
(*CTemp)[index] = 0.0;
for (int k = 0; k < N; k++) {
int a_index = i + k * N;
int b_index = k + j * N;
(*CTemp)[index] += (*A)[a_index] * (*B)[b_index];
}
}
}
//Compare GPU computed multiplication to CPU
int good = 1;
int i, j;
//printf("Array C = \n");
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
int index = i + j * N;
float val = (*C)[index];
//printf("%f ", val);
float diff = (*CTemp)[index] - val;
/*if (absf(diff) > TOLERANCE) {
printf("%d %d %f %f %f\n", i, j, val, (*CTemp)[index], diff);
good = 0;
}*/
}
//printf("\n");
}
if (good == 1) {
printf("TEST PASSED\n");
}
else {
printf("TEST FAILED\n");
}
// free device memory
hipFree(pA);
hipFree(pB);
hipFree(pC);
}
float absf(float n) {
if (n < 0)
return -n;
return n;
} | .text
.file "kernel.hip"
.globl _Z22__device_stub__MatMultPfS_S_ii # -- Begin function _Z22__device_stub__MatMultPfS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__MatMultPfS_S_ii,@function
_Z22__device_stub__MatMultPfS_S_ii: # @_Z22__device_stub__MatMultPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7MatMultPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__MatMultPfS_S_ii, .Lfunc_end0-_Z22__device_stub__MatMultPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 2 # 0x2
.long 4 # 0x4
.long 10 # 0xa
.long 20 # 0x14
.LCPI1_1:
.long 100 # 0x64
.long 200 # 0xc8
.long 500 # 0x1f4
.long 1500 # 0x5dc
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [2,4,10,20]
movaps %xmm0, 32(%rsp)
movl $25, 48(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [100,200,500,1500]
movaps %xmm0, (%rsp)
movl $5000, 16(%rsp) # imm = 0x1388
movl $.L.str, %edi
movl $2, %esi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl (%rsp,%r13,4), %ebx
movl %ebx, %r14d
imull %r14d, %r14d
shlq $2, %r14
movq %r14, dsize(%rip)
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r14
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq %r15, %rdi
movq %r12, %rsi
movq %r14, %rdx
movl %ebx, %ecx
movl $2, %r8d
callq _Z12HostFunctionPA_fS0_S0_ii
movl $10, %edi
callq putchar@PLT
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r14, %rdi
callq free
incq %r13
cmpq $4, %r13
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.critedge
# =>This Inner Loop Header: Depth=1
movl 32(%rsp,%r13,4), %ebx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq $100000000, dsize(%rip) # imm = 0x5F5E100
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r14
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r15
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r12
movl $.L.str.1, %edi
movl $5000, %esi # imm = 0x1388
xorl %eax, %eax
callq printf
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $5000, %ecx # imm = 0x1388
movl %ebx, %r8d
callq _Z12HostFunctionPA_fS0_S0_ii
movl $10, %edi
callq putchar@PLT
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movl $10, %edi
callq putchar@PLT
incq %r13
cmpq $5, %r13
jne .LBB1_3
# %bb.4:
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12HostFunctionPA_fS0_S0_ii
.LCPI2_0:
.long 0x41200000 # float 10
.LCPI2_1:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z12HostFunctionPA_fS0_S0_ii
.p2align 4, 0x90
.type _Z12HostFunctionPA_fS0_S0_ii,@function
_Z12HostFunctionPA_fS0_S0_ii: # @_Z12HostFunctionPA_fS0_S0_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 52(%rsp) # 4-byte Spill
movq %rdx, 80(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, 64(%rsp) # 8-byte Spill
movl %ecx, (%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB2_5
# %bb.1: # %.preheader98.lr.ph
movl (%rsp), %r14d # 4-byte Reload
leaq (,%r14,4), %rbx
xorl %eax, %eax
movq 64(%rsp), %r13 # 8-byte Reload
movq 72(%rsp), %r12 # 8-byte Reload
movq 80(%rsp), %r15 # 8-byte Reload
movq %r14, 88(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_2: # %.preheader98
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movq %rax, 96(%rsp) # 8-byte Spill
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
mulss .LCPI2_1(%rip), %xmm0
movss %xmm0, (%r13,%rbp)
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r12,%rbp)
movl $0, (%r15,%rbp)
addq %rbx, %rbp
decq %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
incq %rax
addq $4, %r15
addq $4, %r12
addq $4, %r13
movq 88(%rsp), %r14 # 8-byte Reload
cmpq %r14, %rax
jne .LBB2_2
.LBB2_5: # %._crit_edge101
movl (%rsp), %r15d # 4-byte Reload
movl %r15d, %r14d
imull %r14d, %r14d
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 52(%rsp), %ebp # 4-byte Reload
movl %ebp, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r15d, 60(%rsp)
movl %ebp, 56(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z7MatMultPfS_S_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7: # %._crit_edge111
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12HostFunctionPA_fS0_S0_ii, .Lfunc_end2-_Z12HostFunctionPA_fS0_S0_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z4absff
.LCPI3_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z4absff
.p2align 4, 0x90
.type _Z4absff,@function
_Z4absff: # @_Z4absff
.cfi_startproc
# %bb.0:
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm1
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end3:
.size _Z4absff, .Lfunc_end3-_Z4absff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7MatMultPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7MatMultPfS_S_ii,@object # @_Z7MatMultPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z7MatMultPfS_S_ii
.p2align 3, 0x0
_Z7MatMultPfS_S_ii:
.quad _Z22__device_stub__MatMultPfS_S_ii
.size _Z7MatMultPfS_S_ii, 8
.type dsize,@object # @dsize
.bss
.globl dsize
.p2align 3, 0x0
dsize:
.quad 0 # 0x0
.size dsize, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tile Width = %d:\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "N = %d\n"
.size .L.str.1, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Kernel matrix multiplication time: %f\n"
.size .L.str.3, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7MatMultPfS_S_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "TEST PASSED"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__MatMultPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7MatMultPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7MatMultPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R5, c[0x0][0x17c] ; /* 0x00005f0000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fe2000f8e3c3f */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e2a0000209400 */
/*0050*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf23270 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc40000000a00 */
/*0070*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00b0*/ IADD3 R4, RZ, -R3, RZ ; /* 0x80000003ff047210 */
/* 0x002fca0007ffe0ff */
/*00c0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*00d0*/ IABS R4, c[0x0][0x178] ; /* 0x00005e0000047a13 */
/* 0x000fc60000000000 */
/*00e0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*00f0*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0100*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fe200078e00ff */
/*0110*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e260000002200 */
/*0120*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0130*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe20003f44070 */
/*0150*/ IMAD R4, R7, c[0x0][0x17c], R2 ; /* 0x00005f0007047a24 */
/* 0x001fd800078e0202 */
/*0160*/ @!P2 IADD3 R0, R0, -R5.reuse, RZ ; /* 0x800000050000a210 */
/* 0x080fe40007ffe0ff */
/*0170*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0190*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f45270 */
/*01a0*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*01b0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e2c0000002100 */
/*01c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ MOV R11, R3 ; /* 0x00000003000b7202 */
/* 0x000fe20000000f00 */
/*01e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fc800000001ff */
/*01f0*/ @!P1 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b9224 */
/* 0x000fe200078e0a0b */
/*0200*/ @!P2 LOP3.LUT R11, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff0baa12 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe20003f06270 */
/*0220*/ IMAD R5, R5, c[0x0][0x17c], R0 ; /* 0x00005f0005057a24 */
/* 0x001fd800078e0200 */
/*0230*/ @!P0 BRA 0xaf0 ; /* 0x000008b000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R3, R11.reuse, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x040fe20007ffe0ff */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT R6, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b067812 */
/* 0x000fe400078ec0ff */
/*0270*/ ISETP.GE.U32.AND P2, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f46070 */
/*0280*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f06270 */
/*0290*/ SHF.L.U32 R9, R2, 0x3, RZ ; /* 0x0000000302097819 */
/* 0x000fe400000006ff */
/*02a0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc40003f25270 */
/*02b0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*02c0*/ ISETP.LT.AND P0, PT, R5, c[0x0][0x178], !P0 ; /* 0x00005e0005007a0c */
/* 0x000fe40004701270 */
/*02d0*/ LEA R8, R0, R9, 0x2 ; /* 0x0000000900087211 */
/* 0x000fe200078e10ff */
/*02e0*/ @!P2 BRA 0x910 ; /* 0x000006200000a947 */
/* 0x000fea0003800000 */
/*02f0*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe20000000f00 */
/*0300*/ IMAD R18, R4, c[0x0][0x178], R0 ; /* 0x00005e0004127a24 */
/* 0x000fe200078e0200 */
/*0310*/ IADD3 R20, R2, c[0x0][0x17c], RZ ; /* 0x00005f0002147a10 */
/* 0x000fe20007ffe0ff */
/*0320*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0330*/ LEA R16, R13.reuse, R2, 0x1 ; /* 0x000000020d107211 */
/* 0x040fe200078e08ff */
/*0340*/ IMAD R14, R13, 0x3, R2 ; /* 0x000000030d0e7824 */
/* 0x000fe200078e0202 */
/*0350*/ BSSY B0, 0x910 ; /* 0x000005b000007945 */
/* 0x000fe20003800000 */
/*0360*/ IADD3 R10, -R11, R6, RZ ; /* 0x000000060b0a7210 */
/* 0x000fe20007ffe1ff */
/*0370*/ IMAD R12, R13, c[0x0][0x178], RZ ; /* 0x00005e000d0c7a24 */
/* 0x000fc400078e02ff */
/*0380*/ IMAD R9, R13.reuse, 0x3, R18 ; /* 0x000000030d097824 */
/* 0x040fe200078e0212 */
/*0390*/ LEA R13, R13, R18, 0x1 ; /* 0x000000120d0d7211 */
/* 0x000fe200078e08ff */
/*03a0*/ IMAD R19, R2, c[0x0][0x178], R5.reuse ; /* 0x00005e0002137a24 */
/* 0x100fe400078e0205 */
/*03b0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*03c0*/ IMAD R23, R20, c[0x0][0x178], R5.reuse ; /* 0x00005e0014177a24 */
/* 0x100fe400078e0205 */
/*03d0*/ IMAD R21, R14, c[0x0][0x178], R5.reuse ; /* 0x00005e000e157a24 */
/* 0x100fe400078e0205 */
/*03e0*/ IMAD R11, R16, c[0x0][0x178], R5 ; /* 0x00005e00100b7a24 */
/* 0x000fc400078e0205 */
/*03f0*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff100424 */
/* 0x000fc800078e00ff */
/*0400*/ @P0 IMAD.WIDE.U32 R14, R18, R16, c[0x0][0x160] ; /* 0x00005800120e0625 */
/* 0x000fc800078e0010 */
/*0410*/ @P0 IMAD.WIDE.U32 R16, R19, R16, c[0x0][0x168] ; /* 0x00005a0013100625 */
/* 0x000fe200078e0010 */
/*0420*/ @P0 LDG.E R25, [R14.64] ; /* 0x000000040e190981 */
/* 0x0000a8000c1e1900 */
/*0430*/ @P0 LDG.E R27, [R16.64] ; /* 0x00000004101b0981 */
/* 0x0002e2000c1e1900 */
/*0440*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0450*/ @P0 IADD3 R20, R18, c[0x0][0x17c], RZ ; /* 0x00005f0012140a10 */
/* 0x000fe40007ffe0ff */
/*0460*/ @P0 MOV R22, 0x4 ; /* 0x0000000400160802 */
/* 0x000fca0000000f00 */
/*0470*/ @P0 IMAD.WIDE.U32 R14, R20, R22, c[0x0][0x160] ; /* 0x00005800140e0625 */
/* 0x001fc800078e0016 */
/*0480*/ @P0 IMAD.WIDE.U32 R16, R23, R22, c[0x0][0x168] ; /* 0x00005a0017100625 */
/* 0x002fe200078e0016 */
/*0490*/ @P0 STS [R8], R25 ; /* 0x0000001908000388 */
/* 0x004fe80000000800 */
/*04a0*/ @P0 STS [R8+0x10], R27 ; /* 0x0000101b08000388 */
/* 0x0081e80000000800 */
/*04b0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*04c0*/ @P0 LDS R26, [R0.X4+0x10] ; /* 0x00001000001a0984 */
/* 0x000fe80000004800 */
/*04d0*/ @P0 LDS R24, [R2.X8] ; /* 0x0000000002180984 */
/* 0x000e680000008800 */
/*04e0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*04f0*/ @P0 LDS R28, [R0.X4+0x18] ; /* 0x00001800001c0984 */
/* 0x000fe80000004800 */
/*0500*/ @P0 LDS R25, [R2.X8+0x4] ; /* 0x0000040002190984 */
/* 0x000ea80000008800 */
/*0510*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0520*/ @P0 LDG.E R27, [R14.64] ; /* 0x000000040e1b0981 */
/* 0x0010e8000c1e1900 */
/*0530*/ @P0 LDG.E R29, [R16.64] ; /* 0x00000004101d0981 */
/* 0x000962000c1e1900 */
/*0540*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0550*/ @P0 FFMA R24, R26, R24, R3 ; /* 0x000000181a180223 */
/* 0x002fc80000000003 */
/*0560*/ @P0 FFMA R3, R28, R25, R24 ; /* 0x000000191c030223 */
/* 0x004fe20000000018 */
/*0570*/ @P0 MOV R16, 0x4 ; /* 0x0000000400100802 */
/* 0x010fca0000000f00 */
/*0580*/ @P0 IMAD.WIDE.U32 R14, R13, R16, c[0x0][0x160] ; /* 0x000058000d0e0625 */
/* 0x001fc800078e0010 */
/*0590*/ @P0 IMAD.WIDE.U32 R16, R11, R16, c[0x0][0x168] ; /* 0x00005a000b100625 */
/* 0x000fe200078e0010 */
/*05a0*/ @P0 STS [R8], R27 ; /* 0x0000001b08000388 */
/* 0x008fe80000000800 */
/*05b0*/ @P0 STS [R8+0x10], R29 ; /* 0x0000101d08000388 */
/* 0x0201e80000000800 */
/*05c0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*05d0*/ @P0 LDS R20, [R0.X4+0x10] ; /* 0x0000100000140984 */
/* 0x000fe80000004800 */
/*05e0*/ @P0 LDS R22, [R2.X8] ; /* 0x0000000002160984 */
/* 0x000e680000008800 */
/*05f0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0600*/ @P0 LDS R27, [R0.X4+0x18] ; /* 0x00001800001b0984 */
/* 0x000fe80000004800 */
/*0610*/ @P0 LDS R26, [R2.X8+0x4] ; /* 0x00000400021a0984 */
/* 0x000ea80000008800 */
/*0620*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0630*/ @P0 LDG.E R29, [R14.64] ; /* 0x000000040e1d0981 */
/* 0x0010e8000c1e1900 */
/*0640*/ @P0 LDG.E R28, [R16.64] ; /* 0x00000004101c0981 */
/* 0x000962000c1e1900 */
/*0650*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0660*/ @P0 FFMA R20, R20, R22, R3 ; /* 0x0000001614140223 */
/* 0x002fc80000000003 */
/*0670*/ @P0 FFMA R3, R27, R26, R20 ; /* 0x0000001a1b030223 */
/* 0x004fe20000000014 */
/*0680*/ @P0 MOV R16, 0x4 ; /* 0x0000000400100802 */
/* 0x010fca0000000f00 */
/*0690*/ @P0 IMAD.WIDE.U32 R14, R9, R16, c[0x0][0x160] ; /* 0x00005800090e0625 */
/* 0x001fc800078e0010 */
/*06a0*/ @P0 IMAD.WIDE.U32 R16, R21, R16, c[0x0][0x168] ; /* 0x00005a0015100625 */
/* 0x000fe200078e0010 */
/*06b0*/ @P0 STS [R8], R29 ; /* 0x0000001d08000388 */
/* 0x008fe80000000800 */
/*06c0*/ @P0 STS [R8+0x10], R28 ; /* 0x0000101c08000388 */
/* 0x020fe80000000800 */
/*06d0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*06e0*/ @P0 LDS R24, [R0.X4+0x10] ; /* 0x0000100000180984 */
/* 0x000fe80000004800 */
/*06f0*/ @P0 LDS R25, [R2.X8] ; /* 0x0000000002190984 */
/* 0x000e280000008800 */
/*0700*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0710*/ @P0 LDS R20, [R0.X4+0x18] ; /* 0x0000180000140984 */
/* 0x000fe80000004800 */
/*0720*/ @P0 LDS R27, [R2.X8+0x4] ; /* 0x00000400021b0984 */
/* 0x000e680000008800 */
/*0730*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0740*/ @P0 LDG.E R15, [R14.64] ; /* 0x000000040e0f0981 */
/* 0x0004e8000c1e1900 */
/*0750*/ @P0 LDG.E R17, [R16.64] ; /* 0x0000000410110981 */
/* 0x000962000c1e1900 */
/*0760*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*0770*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007ffe0ff */
/*0780*/ @P0 FFMA R24, R24, R25, R3 ; /* 0x0000001918180223 */
/* 0x001fe20000000003 */
/*0790*/ LEA R23, R12.reuse, R23, 0x2 ; /* 0x000000170c177211 */
/* 0x040fe200078e10ff */
/*07a0*/ IMAD R21, R12.reuse, 0x4, R21 ; /* 0x000000040c157824 */
/* 0x040fe200078e0215 */
/*07b0*/ LEA R19, R12, R19, 0x2 ; /* 0x000000130c137211 */
/* 0x000fe200078e10ff */
/*07c0*/ IMAD.IADD R14, R10, 0x1, R7 ; /* 0x000000010a0e7824 */
/* 0x004fe200078e0207 */
/*07d0*/ LEA R11, R12, R11, 0x2 ; /* 0x0000000b0c0b7211 */
/* 0x000fe200078e10ff */
/*07e0*/ @P0 FFMA R3, R20, R27, R24 ; /* 0x0000001b14030223 */
/* 0x002fe20000000018 */
/*07f0*/ MOV R16, c[0x0][0x17c] ; /* 0x00005f0000107a02 */
/* 0x010fc40000000f00 */
/*0800*/ ISETP.NE.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f45270 */
/*0810*/ LEA R9, R16.reuse, R9, 0x2 ; /* 0x0000000910097211 */
/* 0x040fe200078e10ff */
/*0820*/ IMAD R18, R16.reuse, 0x4, R18 ; /* 0x0000000410127824 */
/* 0x040fe200078e0212 */
/*0830*/ LEA R13, R16, R13, 0x2 ; /* 0x0000000d100d7211 */
/* 0x000fe200078e10ff */
/*0840*/ @P0 STS [R8], R15 ; /* 0x0000000f08000388 */
/* 0x008fe80000000800 */
/*0850*/ @P0 STS [R8+0x10], R17 ; /* 0x0000101108000388 */
/* 0x020fe80000000800 */
/*0860*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0870*/ @P0 LDS R22, [R0.X4+0x10] ; /* 0x0000100000160984 */
/* 0x000fe80000004800 */
/*0880*/ @P0 LDS R26, [R2.X8] ; /* 0x00000000021a0984 */
/* 0x000e280000008800 */
/*0890*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*08a0*/ @P0 LDS R29, [R0.X4+0x18] ; /* 0x00001800001d0984 */
/* 0x000fe80000004800 */
/*08b0*/ @P0 LDS R28, [R2.X8+0x4] ; /* 0x00000400021c0984 */
/* 0x000e620000008800 */
/*08c0*/ @P0 FFMA R22, R22, R26, R3 ; /* 0x0000001a16160223 */
/* 0x001fc80000000003 */
/*08d0*/ @P0 FFMA R3, R29, R28, R22 ; /* 0x0000001c1d030223 */
/* 0x002fe20000000016 */
/*08e0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*08f0*/ @P2 BRA 0x3f0 ; /* 0xfffffaf000002947 */
/* 0x000fea000383ffff */
/*0900*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0910*/ BSSY B0, 0xaf0 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0920*/ @!P1 BRA 0xae0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0930*/ IMAD R10, R7.reuse, c[0x0][0x17c], R2 ; /* 0x00005f00070a7a24 */
/* 0x040fe400078e0202 */
/*0940*/ IMAD R7, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007077a24 */
/* 0x000fc400078e0200 */
/*0950*/ IMAD R9, R10, c[0x0][0x178], R5 ; /* 0x00005e000a097a24 */
/* 0x000fe400078e0205 */
/*0960*/ IMAD R7, R4, c[0x0][0x178], R7 ; /* 0x00005e0004077a24 */
/* 0x000fe400078e0207 */
/*0970*/ @P0 MOV R12, 0x4 ; /* 0x00000004000c0802 */
/* 0x000fca0000000f00 */
/*0980*/ @P0 IMAD.WIDE.U32 R10, R7, R12, c[0x0][0x160] ; /* 0x00005800070a0625 */
/* 0x000fc800078e000c */
/*0990*/ @P0 IMAD.WIDE.U32 R12, R9, R12, c[0x0][0x168] ; /* 0x00005a00090c0625 */
/* 0x000fe400078e000c */
/*09a0*/ @P0 LDG.E R11, [R10.64] ; /* 0x000000040a0b0981 */
/* 0x0000a8000c1e1900 */
/*09b0*/ @P0 LDG.E R13, [R12.64] ; /* 0x000000040c0d0981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ @P0 WARPSYNC 0xffffffff ; /* 0xffffffff00000948 */
/* 0x000fe20003800000 */
/*09d0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ IADD3 R7, R7, c[0x0][0x17c], RZ ; /* 0x00005f0007077a10 */
/* 0x000fc40007ffe0ff */
/*09f0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*0a00*/ MOV R10, c[0x0][0x17c] ; /* 0x00005f00000a7a02 */
/* 0x001fca0000000f00 */
/*0a10*/ IMAD R9, R10, c[0x0][0x178], R9 ; /* 0x00005e000a097a24 */
/* 0x000fe200078e0209 */
/*0a20*/ @P0 STS [R8], R11 ; /* 0x0000000b08000388 */
/* 0x004fe80000000800 */
/*0a30*/ @P0 STS [R8+0x10], R13 ; /* 0x0000100d08000388 */
/* 0x008fe80000000800 */
/*0a40*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0a50*/ @P0 LDS R14, [R0.X4+0x10] ; /* 0x00001000000e0984 */
/* 0x000fe80000004800 */
/*0a60*/ @P0 LDS R15, [R2.X8] ; /* 0x00000000020f0984 */
/* 0x000e280000008800 */
/*0a70*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0a80*/ @P0 LDS R17, [R0.X4+0x18] ; /* 0x0000180000110984 */
/* 0x000fe80000004800 */
/*0a90*/ @P0 LDS R16, [R2.X8+0x4] ; /* 0x0000040002100984 */
/* 0x000e620000008800 */
/*0aa0*/ @P0 FFMA R14, R14, R15, R3 ; /* 0x0000000f0e0e0223 */
/* 0x001fc80000000003 */
/*0ab0*/ @P0 FFMA R3, R17, R16, R14 ; /* 0x0000001011030223 */
/* 0x002fe2000000000e */
/*0ac0*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fec0000010000 */
/*0ad0*/ @P1 BRA 0x970 ; /* 0xfffffe9000001947 */
/* 0x000fea000383ffff */
/*0ae0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0af0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fe20000000f00 */
/*0b00*/ IMAD R4, R4, c[0x0][0x178], R5 ; /* 0x00005e0004047a24 */
/* 0x000fc800078e0205 */
/*0b10*/ IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0207 */
/*0b20*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7MatMultPfS_S_ii
.globl _Z7MatMultPfS_S_ii
.p2align 8
.type _Z7MatMultPfS_S_ii,@function
_Z7MatMultPfS_S_ii:
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s9, 31
s_ashr_i32 s6, s8, 31
s_add_i32 s3, s9, s2
s_add_i32 s7, s8, s6
s_xor_b32 s3, s3, s2
s_xor_b32 s7, s7, s6
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s5, 0, s3
v_mad_u64_u32 v[4:5], null, s15, s9, v[2:3]
s_xor_b32 s2, s6, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s4, v1
v_mad_u64_u32 v[0:1], null, s14, s9, v[3:4]
v_mul_lo_u32 v1, v4, s8
s_mul_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s7, s4
s_mul_i32 s5, s4, s3
s_add_i32 s6, s4, 1
s_sub_i32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s7, s5, s3
s_cmp_ge_u32 s5, s3
s_cselect_b32 s4, s6, s4
s_cselect_b32 s5, s7, s5
s_add_i32 s6, s4, 1
s_cmp_ge_u32 s5, s3
s_cselect_b32 s3, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
s_sub_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v7, 2, v3
v_max_i32_e32 v6, v0, v4
v_lshlrev_b32_e32 v4, 3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 16, v7
v_cmp_gt_i32_e32 vcc_lo, s8, v6
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v6, v1, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v4, v7
v_add_nc_u32_e32 v8, v5, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, s3
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz .LBB0_2
s_mul_i32 s2, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v13, s2, v2
v_add_nc_u32_e32 v9, s2, v6
v_mad_u64_u32 v[11:12], null, v13, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v12, v10
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, s2, s4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s2, s5, v10, s2
v_add_co_u32 v11, s2, s6, v11
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s2, s7, v12, s2
s_mov_b32 s2, 0
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v5
s_waitcnt vmcnt(1)
ds_store_b32 v7, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_5:
v_add_nc_u32_e32 v10, s2, v4
s_add_i32 s2, s2, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 8, v9
s_cmp_eq_u32 s2, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fmac_f32_e32 v3, v10, v11
s_cbranch_scc1 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
v_mov_b32_e32 v3, 0
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7MatMultPfS_S_ii
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7MatMultPfS_S_ii, .Lfunc_end0-_Z7MatMultPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7MatMultPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7MatMultPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00139677_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4absff
.type _Z4absff, @function
_Z4absff:
.LFB2059:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L7
.L4:
ret
.L7:
xorps .LC1(%rip), %xmm0
ret
.cfi_endproc
.LFE2059:
.size _Z4absff, .-_Z4absff
.globl _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
.type _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii, @function
_Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7MatMultPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
.globl _Z7MatMultPfS_S_ii
.type _Z7MatMultPfS_S_ii, @function
_Z7MatMultPfS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7MatMultPfS_S_ii, .-_Z7MatMultPfS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Kernel matrix multiplication time: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "TEST PASSED\n"
.text
.globl _Z12HostFunctionPA_fS0_S0_ii
.type _Z12HostFunctionPA_fS0_S0_ii, @function
_Z12HostFunctionPA_fS0_S0_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 48(%rsp)
movl %ecx, %r15d
movl %r8d, 60(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
testl %ecx, %ecx
jle .L17
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movslq %ecx, %r14
salq $2, %r14
movl $0, 56(%rsp)
.L18:
movq 24(%rsp), %r13
movq 16(%rsp), %r12
movq 8(%rsp), %rbp
movl $0, %ebx
.L19:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, (%r12)
movl $0x00000000, 0(%r13)
movl %ebx, %eax
addl $1, %ebx
addq %r14, %rbp
addq %r14, %r12
addq %r14, %r13
cmpl %ebx, %r15d
jne .L19
movl 56(%rsp), %ebx
leal 1(%rbx), %edx
addq $4, 8(%rsp)
addq $4, 16(%rsp)
addq $4, 24(%rsp)
cmpl %eax, %ebx
je .L17
movl %edx, 56(%rsp)
jmp .L18
.L17:
movl %r15d, %ebx
imull %r15d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 68(%rsp)
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl 60(%rsp), %eax
movl %eax, 112(%rsp)
movl %eax, 116(%rsp)
movl $1, 120(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC9(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC4(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L20:
cvttss2sil %xmm3, %eax
movl %eax, 124(%rsp)
movl %eax, 128(%rsp)
movl $1, 132(%rsp)
movl 120(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movq 124(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L21:
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movq 104(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %rdi
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 96(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq dsize(%rip), %rdi
call malloc@PLT
movq %rax, %rbx
testl %r15d, %r15d
jle .L22
movq 32(%rsp), %r10
movslq %r15d, %rax
leaq 0(,%rax,4), %rsi
movq 40(%rsp), %r13
addq %rsi, %r13
negq %rax
leaq 0(,%rax,4), %r11
movl $0, %ebp
movl $0, %r12d
jmp .L23
.L35:
movl 60(%rsp), %r8d
movl %r15d, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z32__device_stub__Z7MatMultPfS_S_iiPfS_S_ii
jmp .L21
.L29:
movl %eax, %edi
.L25:
movq %r8, %r9
leaq (%rcx,%r11), %rax
movq %r10, %rdx
pxor %xmm1, %xmm1
.L24:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq %rsi, %rdx
addq $4, %rax
cmpq %rcx, %rax
jne .L24
movss %xmm1, (%r9)
leal 1(%rdi), %eax
addq %rsi, %r8
addq %rsi, %rcx
cmpl %eax, %r15d
jne .L29
leal 1(%rbp), %eax
addq $4, %r10
addq $4, %rbx
cmpl %edi, %ebp
je .L30
movl %eax, %ebp
.L23:
movq %r13, %rcx
movq %rbx, %r8
movl %r12d, %edi
jmp .L25
.L30:
movl $0, %ecx
.L26:
movl $0, %eax
.L27:
movl %eax, %edx
addl $1, %eax
cmpl %edx, %edi
jne .L27
leal 1(%rcx), %eax
cmpl %ecx, %edi
je .L22
movl %eax, %ecx
jmp .L26
.L22:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12HostFunctionPA_fS0_S0_ii, .-_Z12HostFunctionPA_fS0_S0_ii
.section .rodata.str1.1
.LC10:
.string "Tile Width = %d:\n"
.LC11:
.string "N = %d\n"
.LC12:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $2, 16(%rsp)
movl $4, 20(%rsp)
movl $10, 24(%rsp)
movl $20, 28(%rsp)
movl $25, 32(%rsp)
movl $100, 48(%rsp)
movl $200, 52(%rsp)
movl $500, 56(%rsp)
movl $1500, 60(%rsp)
movl $5000, 64(%rsp)
movl $2, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %r14
leaq 64(%rsp), %r15
.L38:
movl (%r14), %r13d
movl %r13d, %ebx
imull %r13d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, dsize(%rip)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %r8d
movl %r13d, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z12HostFunctionPA_fS0_S0_ii
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
addq $4, %r14
cmpq %r14, %r15
jne .L38
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %r13
leaq 36(%rsp), %rax
movq %rax, 8(%rsp)
leaq .LC12(%rip), %r15
.L39:
movl 0(%r13), %r14d
movl %r14d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $100000000, dsize(%rip)
movl $100000000, %edi
call malloc@PLT
movq %rax, %r12
movl $100000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $100000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $5000, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %r8d
movl $5000, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z12HostFunctionPA_fS0_S0_ii
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r13
cmpq %r13, 8(%rsp)
jne .L39
movq stdin(%rip), %rdi
call getc@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z7MatMultPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7MatMultPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dsize
.bss
.align 8
.type dsize, @object
.size dsize, 8
dsize:
.zero 8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1092616192
.align 4
.LC3:
.long 805306368
.align 4
.LC4:
.long 1258291200
.align 4
.LC6:
.long 1065353216
.align 4
.LC9:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z22__device_stub__MatMultPfS_S_ii # -- Begin function _Z22__device_stub__MatMultPfS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__MatMultPfS_S_ii,@function
_Z22__device_stub__MatMultPfS_S_ii: # @_Z22__device_stub__MatMultPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7MatMultPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__MatMultPfS_S_ii, .Lfunc_end0-_Z22__device_stub__MatMultPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 2 # 0x2
.long 4 # 0x4
.long 10 # 0xa
.long 20 # 0x14
.LCPI1_1:
.long 100 # 0x64
.long 200 # 0xc8
.long 500 # 0x1f4
.long 1500 # 0x5dc
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [2,4,10,20]
movaps %xmm0, 32(%rsp)
movl $25, 48(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [100,200,500,1500]
movaps %xmm0, (%rsp)
movl $5000, 16(%rsp) # imm = 0x1388
movl $.L.str, %edi
movl $2, %esi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl (%rsp,%r13,4), %ebx
movl %ebx, %r14d
imull %r14d, %r14d
shlq $2, %r14
movq %r14, dsize(%rip)
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r14
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq %r15, %rdi
movq %r12, %rsi
movq %r14, %rdx
movl %ebx, %ecx
movl $2, %r8d
callq _Z12HostFunctionPA_fS0_S0_ii
movl $10, %edi
callq putchar@PLT
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r14, %rdi
callq free
incq %r13
cmpq $4, %r13
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.critedge
# =>This Inner Loop Header: Depth=1
movl 32(%rsp,%r13,4), %ebx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq $100000000, dsize(%rip) # imm = 0x5F5E100
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r14
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r15
movl $100000000, %edi # imm = 0x5F5E100
callq malloc
movq %rax, %r12
movl $.L.str.1, %edi
movl $5000, %esi # imm = 0x1388
xorl %eax, %eax
callq printf
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $5000, %ecx # imm = 0x1388
movl %ebx, %r8d
callq _Z12HostFunctionPA_fS0_S0_ii
movl $10, %edi
callq putchar@PLT
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movl $10, %edi
callq putchar@PLT
incq %r13
cmpq $5, %r13
jne .LBB1_3
# %bb.4:
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12HostFunctionPA_fS0_S0_ii
.LCPI2_0:
.long 0x41200000 # float 10
.LCPI2_1:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z12HostFunctionPA_fS0_S0_ii
.p2align 4, 0x90
.type _Z12HostFunctionPA_fS0_S0_ii,@function
_Z12HostFunctionPA_fS0_S0_ii: # @_Z12HostFunctionPA_fS0_S0_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 52(%rsp) # 4-byte Spill
movq %rdx, 80(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, 64(%rsp) # 8-byte Spill
movl %ecx, (%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB2_5
# %bb.1: # %.preheader98.lr.ph
movl (%rsp), %r14d # 4-byte Reload
leaq (,%r14,4), %rbx
xorl %eax, %eax
movq 64(%rsp), %r13 # 8-byte Reload
movq 72(%rsp), %r12 # 8-byte Reload
movq 80(%rsp), %r15 # 8-byte Reload
movq %r14, 88(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_2: # %.preheader98
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movq %rax, 96(%rsp) # 8-byte Spill
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
mulss .LCPI2_1(%rip), %xmm0
movss %xmm0, (%r13,%rbp)
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r12,%rbp)
movl $0, (%r15,%rbp)
addq %rbx, %rbp
decq %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq 96(%rsp), %rax # 8-byte Reload
incq %rax
addq $4, %r15
addq $4, %r12
addq $4, %r13
movq 88(%rsp), %r14 # 8-byte Reload
cmpq %r14, %rax
jne .LBB2_2
.LBB2_5: # %._crit_edge101
movl (%rsp), %r15d # 4-byte Reload
movl %r15d, %r14d
imull %r14d, %r14d
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 52(%rsp), %ebp # 4-byte Reload
movl %ebp, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r15d, 60(%rsp)
movl %ebp, 56(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z7MatMultPfS_S_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7: # %._crit_edge111
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12HostFunctionPA_fS0_S0_ii, .Lfunc_end2-_Z12HostFunctionPA_fS0_S0_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z4absff
.LCPI3_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z4absff
.p2align 4, 0x90
.type _Z4absff,@function
_Z4absff: # @_Z4absff
.cfi_startproc
# %bb.0:
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm1
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end3:
.size _Z4absff, .Lfunc_end3-_Z4absff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7MatMultPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7MatMultPfS_S_ii,@object # @_Z7MatMultPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z7MatMultPfS_S_ii
.p2align 3, 0x0
_Z7MatMultPfS_S_ii:
.quad _Z22__device_stub__MatMultPfS_S_ii
.size _Z7MatMultPfS_S_ii, 8
.type dsize,@object # @dsize
.bss
.globl dsize
.p2align 3, 0x0
dsize:
.quad 0 # 0x0
.size dsize, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tile Width = %d:\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "N = %d\n"
.size .L.str.1, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Kernel matrix multiplication time: %f\n"
.size .L.str.3, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7MatMultPfS_S_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "TEST PASSED"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__MatMultPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7MatMultPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ int sign(DECNUM x)
{
return((x > 0.0f) - (x < 0.0f));
}
__device__ int mminus2(int ix, int nx)
{
int xminus;
if (ix <= 1)
{
xminus = 0;
}
else
{
xminus = ix - 2;
}
return(xminus);
}
__device__ int pplus(int ix, int nx)
{
int xplus;
if (ix == nx - 1)
{
xplus = nx - 1;
}
else
{
xplus = ix + 1;
}
return(xplus);
}
__device__ int mminus(int ix, int nx)
{
int xminus;
if (ix == 0)
{
xminus = 0;
}
else
{
xminus = ix - 1;
}
return(xminus);
}
__global__ void vvlatbnd(int nx, int ny, DECNUM * uu)
{
// Neumann_v boundary
unsigned int ix = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = ix + iy*nx;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ DECNUM uut[16][16];
__shared__ DECNUM uub[16][16];
if (ix < nx && iy < ny)
{
unsigned int yminus = mminus(iy, ny);
unsigned int yminus2 = mminus2(iy, ny);
unsigned int yplus = pplus(iy, ny);
uut[tx][ty] = uu[ix + yplus*nx];
uub[tx][ty] = uu[ix + yminus*nx];
if (iy == 0)
{
uu[i] = uut[tx][ty];
}
if (iy == ny - 2)
{
uu[i] = uub[tx][ty];
}
}
//
} | code for sm_80
Function : _Z8vvlatbndiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R10, SR_TID.Y ; /* 0x00000000000a7919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x4], R10 ; /* 0x0000010007077a24 */
/* 0x001fca00078e020a */
/*0060*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x164], PT ; /* 0x0000590007007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0209 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff087624 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.NE.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720c */
/* 0x040fe20003f05270 */
/*00c0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00d0*/ IADD3 R2, R7, -0x1, RZ ; /* 0xffffffff07027810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fe40007ffe0ff */
/*0100*/ SEL R3, R2, RZ, P0 ; /* 0x000000ff02037207 */
/* 0x000fe40000000000 */
/*0110*/ ISETP.NE.AND P1, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fc60003f25270 */
/*0120*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fd400078e0200 */
/*0130*/ @P1 IADD3 R4, R7, 0x1, RZ ; /* 0x0000000107041810 */
/* 0x000fca0007ffe0ff */
/*0140*/ IMAD R2, R4, c[0x0][0x160], R0 ; /* 0x0000580004027a24 */
/* 0x000fe400078e0200 */
/*0150*/ IMAD.WIDE.U32 R4, R3, R11, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e000b */
/*0160*/ IMAD.WIDE.U32 R2, R2, R11.reuse, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x080fe400078e000b */
/*0170*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*0190*/ IADD3 R8, R8, -0x2, RZ ; /* 0xfffffffe08087810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD R6, R7.reuse, c[0x0][0x160], R0 ; /* 0x0000580007067a24 */
/* 0x040fe200078e0200 */
/*01b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*01c0*/ IMAD R10, R9, 0x10, R10 ; /* 0x00000010090a7824 */
/* 0x000fe200078e020a */
/*01d0*/ ISETP.NE.AND P1, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fe20003f25270 */
/*01e0*/ IMAD.WIDE.U32 R6, R6, R11, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e000b */
/*01f0*/ STS [R10.X4+0x400], R5 ; /* 0x000400050a007388 */
/* 0x0041e80000004800 */
/*0200*/ STS [R10.X4], R3 ; /* 0x000000030a007388 */
/* 0x0081e80000004800 */
/*0210*/ @!P0 STG.E [R6.64], R3 ; /* 0x0000000306008986 */
/* 0x0001e2000c101904 */
/*0220*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0230*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int sign(DECNUM x)
{
return((x > 0.0f) - (x < 0.0f));
}
__device__ int mminus2(int ix, int nx)
{
int xminus;
if (ix <= 1)
{
xminus = 0;
}
else
{
xminus = ix - 2;
}
return(xminus);
}
__device__ int pplus(int ix, int nx)
{
int xplus;
if (ix == nx - 1)
{
xplus = nx - 1;
}
else
{
xplus = ix + 1;
}
return(xplus);
}
__device__ int mminus(int ix, int nx)
{
int xminus;
if (ix == 0)
{
xminus = 0;
}
else
{
xminus = ix - 1;
}
return(xminus);
}
__global__ void vvlatbnd(int nx, int ny, DECNUM * uu)
{
// Neumann_v boundary
unsigned int ix = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = ix + iy*nx;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ DECNUM uut[16][16];
__shared__ DECNUM uub[16][16];
if (ix < nx && iy < ny)
{
unsigned int yminus = mminus(iy, ny);
unsigned int yminus2 = mminus2(iy, ny);
unsigned int yplus = pplus(iy, ny);
uut[tx][ty] = uu[ix + yplus*nx];
uub[tx][ty] = uu[ix + yminus*nx];
if (iy == 0)
{
uu[i] = uut[tx][ty];
}
if (iy == ny - 2)
{
uu[i] = uub[tx][ty];
}
}
//
} | .file "tmpxft_0014341b_00000000-6_vvlatbnd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4signf
.type _Z4signf, @function
_Z4signf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4signf, .-_Z4signf
.globl _Z7mminus2ii
.type _Z7mminus2ii, @function
_Z7mminus2ii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z7mminus2ii, .-_Z7mminus2ii
.globl _Z5pplusii
.type _Z5pplusii, @function
_Z5pplusii:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z5pplusii, .-_Z5pplusii
.globl _Z6mminusii
.type _Z6mminusii, @function
_Z6mminusii:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z6mminusii, .-_Z6mminusii
.globl _Z29__device_stub__Z8vvlatbndiiPfiiPf
.type _Z29__device_stub__Z8vvlatbndiiPfiiPf, @function
_Z29__device_stub__Z8vvlatbndiiPfiiPf:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8vvlatbndiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z29__device_stub__Z8vvlatbndiiPfiiPf, .-_Z29__device_stub__Z8vvlatbndiiPfiiPf
.globl _Z8vvlatbndiiPf
.type _Z8vvlatbndiiPf, @function
_Z8vvlatbndiiPf:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8vvlatbndiiPfiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z8vvlatbndiiPf, .-_Z8vvlatbndiiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8vvlatbndiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8vvlatbndiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl uuavg
.bss
.align 4
.type uuavg, @object
.size uuavg, 4
uuavg:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int sign(DECNUM x)
{
return((x > 0.0f) - (x < 0.0f));
}
__device__ int mminus2(int ix, int nx)
{
int xminus;
if (ix <= 1)
{
xminus = 0;
}
else
{
xminus = ix - 2;
}
return(xminus);
}
__device__ int pplus(int ix, int nx)
{
int xplus;
if (ix == nx - 1)
{
xplus = nx - 1;
}
else
{
xplus = ix + 1;
}
return(xplus);
}
__device__ int mminus(int ix, int nx)
{
int xminus;
if (ix == 0)
{
xminus = 0;
}
else
{
xminus = ix - 1;
}
return(xminus);
}
__global__ void vvlatbnd(int nx, int ny, DECNUM * uu)
{
// Neumann_v boundary
unsigned int ix = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = ix + iy*nx;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ DECNUM uut[16][16];
__shared__ DECNUM uub[16][16];
if (ix < nx && iy < ny)
{
unsigned int yminus = mminus(iy, ny);
unsigned int yminus2 = mminus2(iy, ny);
unsigned int yplus = pplus(iy, ny);
uut[tx][ty] = uu[ix + yplus*nx];
uub[tx][ty] = uu[ix + yminus*nx];
if (iy == 0)
{
uu[i] = uut[tx][ty];
}
if (iy == ny - 2)
{
uu[i] = uub[tx][ty];
}
}
//
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int sign(DECNUM x)
{
return((x > 0.0f) - (x < 0.0f));
}
__device__ int mminus2(int ix, int nx)
{
int xminus;
if (ix <= 1)
{
xminus = 0;
}
else
{
xminus = ix - 2;
}
return(xminus);
}
__device__ int pplus(int ix, int nx)
{
int xplus;
if (ix == nx - 1)
{
xplus = nx - 1;
}
else
{
xplus = ix + 1;
}
return(xplus);
}
__device__ int mminus(int ix, int nx)
{
int xminus;
if (ix == 0)
{
xminus = 0;
}
else
{
xminus = ix - 1;
}
return(xminus);
}
__global__ void vvlatbnd(int nx, int ny, DECNUM * uu)
{
// Neumann_v boundary
unsigned int ix = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = ix + iy*nx;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ DECNUM uut[16][16];
__shared__ DECNUM uub[16][16];
if (ix < nx && iy < ny)
{
unsigned int yminus = mminus(iy, ny);
unsigned int yminus2 = mminus2(iy, ny);
unsigned int yplus = pplus(iy, ny);
uut[tx][ty] = uu[ix + yplus*nx];
uub[tx][ty] = uu[ix + yminus*nx];
if (iy == 0)
{
uu[i] = uut[tx][ty];
}
if (iy == ny - 2)
{
uu[i] = uub[tx][ty];
}
}
//
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int sign(DECNUM x)
{
return((x > 0.0f) - (x < 0.0f));
}
__device__ int mminus2(int ix, int nx)
{
int xminus;
if (ix <= 1)
{
xminus = 0;
}
else
{
xminus = ix - 2;
}
return(xminus);
}
__device__ int pplus(int ix, int nx)
{
int xplus;
if (ix == nx - 1)
{
xplus = nx - 1;
}
else
{
xplus = ix + 1;
}
return(xplus);
}
__device__ int mminus(int ix, int nx)
{
int xminus;
if (ix == 0)
{
xminus = 0;
}
else
{
xminus = ix - 1;
}
return(xminus);
}
__global__ void vvlatbnd(int nx, int ny, DECNUM * uu)
{
// Neumann_v boundary
unsigned int ix = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = ix + iy*nx;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ DECNUM uut[16][16];
__shared__ DECNUM uub[16][16];
if (ix < nx && iy < ny)
{
unsigned int yminus = mminus(iy, ny);
unsigned int yminus2 = mminus2(iy, ny);
unsigned int yplus = pplus(iy, ny);
uut[tx][ty] = uu[ix + yplus*nx];
uub[tx][ty] = uu[ix + yminus*nx];
if (iy == 0)
{
uu[i] = uut[tx][ty];
}
if (iy == ny - 2)
{
uu[i] = uub[tx][ty];
}
}
//
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8vvlatbndiiPf
.globl _Z8vvlatbndiiPf
.p2align 8
.type _Z8vvlatbndiiPf,@function
_Z8vvlatbndiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_cmp_gt_u32_e32 vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x8
v_sub_nc_u32_e64 v4, v0, 1 clamp
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s4, v[3:4]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s4, v[3:4]
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
s_add_i32 s3, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, s3, v0
v_cndmask_b32_e64 v2, 1, s3, vcc_lo
v_mad_u64_u32 v[5:6], null, v2, s4, v[3:4]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[5:6]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v5, v[2:3], off
v_mov_b32_e32 v2, v6
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s2, s5, -2
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8vvlatbndiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8vvlatbndiiPf, .Lfunc_end0-_Z8vvlatbndiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8vvlatbndiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8vvlatbndiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int sign(DECNUM x)
{
return((x > 0.0f) - (x < 0.0f));
}
__device__ int mminus2(int ix, int nx)
{
int xminus;
if (ix <= 1)
{
xminus = 0;
}
else
{
xminus = ix - 2;
}
return(xminus);
}
__device__ int pplus(int ix, int nx)
{
int xplus;
if (ix == nx - 1)
{
xplus = nx - 1;
}
else
{
xplus = ix + 1;
}
return(xplus);
}
__device__ int mminus(int ix, int nx)
{
int xminus;
if (ix == 0)
{
xminus = 0;
}
else
{
xminus = ix - 1;
}
return(xminus);
}
__global__ void vvlatbnd(int nx, int ny, DECNUM * uu)
{
// Neumann_v boundary
unsigned int ix = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = ix + iy*nx;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ DECNUM uut[16][16];
__shared__ DECNUM uub[16][16];
if (ix < nx && iy < ny)
{
unsigned int yminus = mminus(iy, ny);
unsigned int yminus2 = mminus2(iy, ny);
unsigned int yplus = pplus(iy, ny);
uut[tx][ty] = uu[ix + yplus*nx];
uub[tx][ty] = uu[ix + yminus*nx];
if (iy == 0)
{
uu[i] = uut[tx][ty];
}
if (iy == ny - 2)
{
uu[i] = uub[tx][ty];
}
}
//
} | .text
.file "vvlatbnd.hip"
.globl _Z23__device_stub__vvlatbndiiPf # -- Begin function _Z23__device_stub__vvlatbndiiPf
.p2align 4, 0x90
.type _Z23__device_stub__vvlatbndiiPf,@function
_Z23__device_stub__vvlatbndiiPf: # @_Z23__device_stub__vvlatbndiiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8vvlatbndiiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__vvlatbndiiPf, .Lfunc_end0-_Z23__device_stub__vvlatbndiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8vvlatbndiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type uuavg,@object # @uuavg
.bss
.globl uuavg
.p2align 2, 0x0
uuavg:
.long 0x00000000 # float 0
.size uuavg, 4
.type _Z8vvlatbndiiPf,@object # @_Z8vvlatbndiiPf
.section .rodata,"a",@progbits
.globl _Z8vvlatbndiiPf
.p2align 3, 0x0
_Z8vvlatbndiiPf:
.quad _Z23__device_stub__vvlatbndiiPf
.size _Z8vvlatbndiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8vvlatbndiiPf"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__vvlatbndiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8vvlatbndiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8vvlatbndiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R10, SR_TID.Y ; /* 0x00000000000a7919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x4], R10 ; /* 0x0000010007077a24 */
/* 0x001fca00078e020a */
/*0060*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x164], PT ; /* 0x0000590007007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0209 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff087624 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.NE.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720c */
/* 0x040fe20003f05270 */
/*00c0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00d0*/ IADD3 R2, R7, -0x1, RZ ; /* 0xffffffff07027810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fe40007ffe0ff */
/*0100*/ SEL R3, R2, RZ, P0 ; /* 0x000000ff02037207 */
/* 0x000fe40000000000 */
/*0110*/ ISETP.NE.AND P1, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fc60003f25270 */
/*0120*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fd400078e0200 */
/*0130*/ @P1 IADD3 R4, R7, 0x1, RZ ; /* 0x0000000107041810 */
/* 0x000fca0007ffe0ff */
/*0140*/ IMAD R2, R4, c[0x0][0x160], R0 ; /* 0x0000580004027a24 */
/* 0x000fe400078e0200 */
/*0150*/ IMAD.WIDE.U32 R4, R3, R11, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e000b */
/*0160*/ IMAD.WIDE.U32 R2, R2, R11.reuse, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x080fe400078e000b */
/*0170*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*0190*/ IADD3 R8, R8, -0x2, RZ ; /* 0xfffffffe08087810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD R6, R7.reuse, c[0x0][0x160], R0 ; /* 0x0000580007067a24 */
/* 0x040fe200078e0200 */
/*01b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*01c0*/ IMAD R10, R9, 0x10, R10 ; /* 0x00000010090a7824 */
/* 0x000fe200078e020a */
/*01d0*/ ISETP.NE.AND P1, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fe20003f25270 */
/*01e0*/ IMAD.WIDE.U32 R6, R6, R11, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e000b */
/*01f0*/ STS [R10.X4+0x400], R5 ; /* 0x000400050a007388 */
/* 0x0041e80000004800 */
/*0200*/ STS [R10.X4], R3 ; /* 0x000000030a007388 */
/* 0x0081e80000004800 */
/*0210*/ @!P0 STG.E [R6.64], R3 ; /* 0x0000000306008986 */
/* 0x0001e2000c101904 */
/*0220*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0230*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8vvlatbndiiPf
.globl _Z8vvlatbndiiPf
.p2align 8
.type _Z8vvlatbndiiPf,@function
_Z8vvlatbndiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_cmp_gt_u32_e32 vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x8
v_sub_nc_u32_e64 v4, v0, 1 clamp
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s4, v[3:4]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s4, v[3:4]
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
s_add_i32 s3, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, s3, v0
v_cndmask_b32_e64 v2, 1, s3, vcc_lo
v_mad_u64_u32 v[5:6], null, v2, s4, v[3:4]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[5:6]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v5, v[2:3], off
v_mov_b32_e32 v2, v6
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s2, s5, -2
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8vvlatbndiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8vvlatbndiiPf, .Lfunc_end0-_Z8vvlatbndiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8vvlatbndiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8vvlatbndiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014341b_00000000-6_vvlatbnd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4signf
.type _Z4signf, @function
_Z4signf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4signf, .-_Z4signf
.globl _Z7mminus2ii
.type _Z7mminus2ii, @function
_Z7mminus2ii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z7mminus2ii, .-_Z7mminus2ii
.globl _Z5pplusii
.type _Z5pplusii, @function
_Z5pplusii:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z5pplusii, .-_Z5pplusii
.globl _Z6mminusii
.type _Z6mminusii, @function
_Z6mminusii:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z6mminusii, .-_Z6mminusii
.globl _Z29__device_stub__Z8vvlatbndiiPfiiPf
.type _Z29__device_stub__Z8vvlatbndiiPfiiPf, @function
_Z29__device_stub__Z8vvlatbndiiPfiiPf:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8vvlatbndiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z29__device_stub__Z8vvlatbndiiPfiiPf, .-_Z29__device_stub__Z8vvlatbndiiPfiiPf
.globl _Z8vvlatbndiiPf
.type _Z8vvlatbndiiPf, @function
_Z8vvlatbndiiPf:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8vvlatbndiiPfiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z8vvlatbndiiPf, .-_Z8vvlatbndiiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8vvlatbndiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8vvlatbndiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl uuavg
.bss
.align 4
.type uuavg, @object
.size uuavg, 4
uuavg:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vvlatbnd.hip"
.globl _Z23__device_stub__vvlatbndiiPf # -- Begin function _Z23__device_stub__vvlatbndiiPf
.p2align 4, 0x90
.type _Z23__device_stub__vvlatbndiiPf,@function
_Z23__device_stub__vvlatbndiiPf: # @_Z23__device_stub__vvlatbndiiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8vvlatbndiiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__vvlatbndiiPf, .Lfunc_end0-_Z23__device_stub__vvlatbndiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8vvlatbndiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type uuavg,@object # @uuavg
.bss
.globl uuavg
.p2align 2, 0x0
uuavg:
.long 0x00000000 # float 0
.size uuavg, 4
.type _Z8vvlatbndiiPf,@object # @_Z8vvlatbndiiPf
.section .rodata,"a",@progbits
.globl _Z8vvlatbndiiPf
.p2align 3, 0x0
_Z8vvlatbndiiPf:
.quad _Z23__device_stub__vvlatbndiiPf
.size _Z8vvlatbndiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8vvlatbndiiPf"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__vvlatbndiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8vvlatbndiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001677fb_00000000-6_reordered-f.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s, %s\n"
.text
.globl _Z11check_errorPKc
.type _Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_errorPKc, .-_Z11check_errorPKc
.globl _Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.type _Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, @function
_Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
movq %rcx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
movq %r8, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
movq %r9, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
movq 288(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
movq 296(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
movq %rsp, %rax
movq %rax, 240(%rsp)
leaq 328(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, .-_Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.globl _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.type _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, @function
_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, .-_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.globl _Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.type _Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, @function
_Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
movq %rcx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
movq %r8, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
movq %r9, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
movq 288(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
movq 296(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
movq %rsp, %rax
movq %rax, 240(%rsp)
leaq 328(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, .-_Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.globl _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.type _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, @function
_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, .-_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.globl _Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.type _Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, @function
_Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
movq %rcx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
movq %r8, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
movq %r9, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
movq 288(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
movq 296(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
movq %rsp, %rax
movq %rax, 240(%rsp)
leaq 328(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i, .-_Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
.globl _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.type _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, @function
_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, .-_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate device memory for uacc_0\n"
.align 8
.LC2:
.string "Failed to allocate device memory for uacc_1\n"
.align 8
.LC3:
.string "Failed to allocate device memory for uacc_2\n"
.align 8
.LC4:
.string "Failed to allocate device memory for u_0\n"
.align 8
.LC5:
.string "Failed to allocate device memory for u_1\n"
.align 8
.LC6:
.string "Failed to allocate device memory for u_2\n"
.align 8
.LC7:
.string "Failed to allocate device memory for mu\n"
.align 8
.LC8:
.string "Failed to allocate device memory for la\n"
.align 8
.LC9:
.string "Failed to allocate device memory for strx\n"
.align 8
.LC10:
.string "Failed to allocate device memory for stry\n"
.align 8
.LC11:
.string "Failed to allocate device memory for strz\n"
.text
.globl host_code
.type host_code, @function
host_code:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movq 256(%rsp), %r15
movq 264(%rsp), %r14
movq 272(%rsp), %r13
movq 280(%rsp), %rax
movq %rax, 48(%rsp)
movq 288(%rsp), %rbx
movq %rbx, 56(%rsp)
movl 296(%rsp), %r12d
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movslq %r12d, %rbp
movq %rbp, %rbx
imulq %rbp, %rbx
imulq %rbp, %rbx
salq $3, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC3(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC4(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC5(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC6(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC7(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
leaq 128(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC8(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
salq $3, %rbp
leaq 136(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC9(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
leaq 144(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC10(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
leaq 152(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC11(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 152(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 168(%rsp)
movl %r12d, %edx
shrl $3, %edx
movl %edx, %eax
addl $1, %eax
testb $7, %r12b
cmove %edx, %eax
movl %r12d, %ecx
shrl $4, %ecx
movl %ecx, %edx
addl $1, %edx
testb $15, %r12b
cmove %ecx, %edx
movl %edx, 172(%rsp)
movl %eax, 176(%rsp)
movl $1, 180(%rsp)
movl $16, 160(%rsp)
movl $8, 164(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movl $1, %ecx
movq 172(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L36:
movl 168(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movq 172(%rsp), %rdi
movl 180(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L37:
movl 168(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movq 172(%rsp), %rdi
movl 180(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L38:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq %r12
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 160(%rsp)
.cfi_def_cfa_offset 288
pushq 160(%rsp)
.cfi_def_cfa_offset 296
pushq 160(%rsp)
.cfi_def_cfa_offset 304
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z45__device_stub__Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $48, %rsp
.cfi_def_cfa_offset 256
jmp .L36
.L42:
pushq %r12
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 160(%rsp)
.cfi_def_cfa_offset 288
pushq 160(%rsp)
.cfi_def_cfa_offset 296
pushq 160(%rsp)
.cfi_def_cfa_offset 304
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z45__device_stub__Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $48, %rsp
.cfi_def_cfa_offset 256
jmp .L37
.L43:
pushq %r12
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 160(%rsp)
.cfi_def_cfa_offset 288
pushq 160(%rsp)
.cfi_def_cfa_offset 296
pushq 160(%rsp)
.cfi_def_cfa_offset 304
movq 160(%rsp), %r9
movq 152(%rsp), %r8
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z45__device_stub__Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_S_i
addq $48, %rsp
.cfi_def_cfa_offset 256
jmp .L38
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size host_code, .-host_code
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i"
.align 8
.LC13:
.string "_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i"
.align 8
.LC14:
.string "_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reordered-f.hip"
.globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc
.p2align 4, 0x90
.type _Z11check_errorPKc,@function
_Z11check_errorPKc: # @_Z11check_errorPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
.cfi_endproc
# -- End function
.globl _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i,@function
_Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i: # @_Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end1:
.size _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end1-_Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i,@function
_Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i: # @_Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end2:
.size _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end2-_Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i,@function
_Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i: # @_Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end3:
.size _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end3-_Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.globl host_code # -- Begin function host_code
.p2align 4, 0x90
.type host_code,@function
host_code: # @host_code
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 352(%rsp) # 8-byte Spill
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, 336(%rsp) # 8-byte Spill
movq %rsi, 344(%rsp) # 8-byte Spill
movq %rdi, %rbp
movslq 456(%rsp), %r12
leaq (,%r12,8), %r13
movq %r12, %r14
imulq %r12, %r14
imulq %r13, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_1
# %bb.3: # %_Z11check_errorPKc.exit
movq 24(%rsp), %rdi
movq %rbp, 232(%rsp) # 8-byte Spill
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_4
# %bb.5: # %_Z11check_errorPKc.exit110
movq 16(%rsp), %rdi
movq 344(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_6
# %bb.7: # %_Z11check_errorPKc.exit112
movq 8(%rsp), %rdi
movq 336(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 88(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_8
# %bb.9: # %_Z11check_errorPKc.exit114
movq 88(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_10
# %bb.11: # %_Z11check_errorPKc.exit116
movq 80(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 72(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_12
# %bb.13: # %_Z11check_errorPKc.exit118
movq 72(%rsp), %rdi
movq 352(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
movq 232(%rsp), %rbx # 8-byte Reload
jne .LBB4_14
# %bb.15: # %_Z11check_errorPKc.exit120
movq 416(%rsp), %rsi
movq 64(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_16
# %bb.17: # %_Z11check_errorPKc.exit122
movq 424(%rsp), %rsi
movq 56(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_18
# %bb.19: # %_Z11check_errorPKc.exit124
movq 432(%rsp), %rsi
movq 48(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_20
# %bb.21: # %_Z11check_errorPKc.exit126
movq 440(%rsp), %rsi
movq 40(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB4_22
# %bb.23: # %_Z11check_errorPKc.exit128
movq 448(%rsp), %rsi
movabsq $34359738384, %rbp # imm = 0x800000010
movq 32(%rsp), %rdi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r12d, %eax
shrl $4, %eax
leal 1(%rax), %ecx
testb $15, %r12b
cmovel %eax, %ecx
movl %r12d, %eax
shrl $3, %eax
leal 1(%rax), %r13d
testb $7, %r12b
cmovel %eax, %r13d
shlq $32, %r13
orq %rcx, %r13
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_25
# %bb.24:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
movq 72(%rsp), %r8
movq 64(%rsp), %r9
movq 56(%rsp), %r10
movq 48(%rsp), %r11
movq 40(%rsp), %rbx
movq 32(%rsp), %r15
movq %rax, 224(%rsp)
movq %rcx, 216(%rsp)
movq %rdx, 208(%rsp)
movq %rsi, 200(%rsp)
movq %rdi, 192(%rsp)
movq %r8, 184(%rsp)
movq %r9, 176(%rsp)
movq %r10, 168(%rsp)
movq %r11, 160(%rsp)
movq %rbx, 152(%rsp)
movq 232(%rsp), %rbx # 8-byte Reload
movq %r15, 144(%rsp)
movl %r12d, 4(%rsp)
leaq 224(%rsp), %rax
movq %rax, 240(%rsp)
leaq 216(%rsp), %rax
movq %rax, 248(%rsp)
leaq 208(%rsp), %rax
movq %rax, 256(%rsp)
leaq 200(%rsp), %rax
movq %rax, 264(%rsp)
leaq 192(%rsp), %rax
movq %rax, 272(%rsp)
leaq 184(%rsp), %rax
movq %rax, 280(%rsp)
leaq 176(%rsp), %rax
movq %rax, 288(%rsp)
leaq 168(%rsp), %rax
movq %rax, 296(%rsp)
leaq 160(%rsp), %rax
movq %rax, 304(%rsp)
leaq 152(%rsp), %rax
movq %rax, 312(%rsp)
leaq 144(%rsp), %rax
movq %rax, 320(%rsp)
leaq 4(%rsp), %rax
movq %rax, 328(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_25:
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_27
# %bb.26:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
movq 72(%rsp), %r8
movq 64(%rsp), %r9
movq 56(%rsp), %r10
movq 48(%rsp), %r11
movq 40(%rsp), %rbx
movq 32(%rsp), %r15
movq %rax, 224(%rsp)
movq %rcx, 216(%rsp)
movq %rdx, 208(%rsp)
movq %rsi, 200(%rsp)
movq %rdi, 192(%rsp)
movq %r8, 184(%rsp)
movq %r9, 176(%rsp)
movq %r10, 168(%rsp)
movq %r11, 160(%rsp)
movq %rbx, 152(%rsp)
movq 232(%rsp), %rbx # 8-byte Reload
movq %r15, 144(%rsp)
movl %r12d, 4(%rsp)
leaq 224(%rsp), %rax
movq %rax, 240(%rsp)
leaq 216(%rsp), %rax
movq %rax, 248(%rsp)
leaq 208(%rsp), %rax
movq %rax, 256(%rsp)
leaq 200(%rsp), %rax
movq %rax, 264(%rsp)
leaq 192(%rsp), %rax
movq %rax, 272(%rsp)
leaq 184(%rsp), %rax
movq %rax, 280(%rsp)
leaq 176(%rsp), %rax
movq %rax, 288(%rsp)
leaq 168(%rsp), %rax
movq %rax, 296(%rsp)
leaq 160(%rsp), %rax
movq %rax, 304(%rsp)
leaq 152(%rsp), %rax
movq %rax, 312(%rsp)
leaq 144(%rsp), %rax
movq %rax, 320(%rsp)
leaq 4(%rsp), %rax
movq %rax, 328(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_27:
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_29
# %bb.28:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
movq 72(%rsp), %r8
movq 64(%rsp), %r9
movq 56(%rsp), %r10
movq 48(%rsp), %r11
movq 40(%rsp), %rbx
movq 32(%rsp), %r15
movq %rax, 224(%rsp)
movq %rcx, 216(%rsp)
movq %rdx, 208(%rsp)
movq %rsi, 200(%rsp)
movq %rdi, 192(%rsp)
movq %r8, 184(%rsp)
movq %r9, 176(%rsp)
movq %r10, 168(%rsp)
movq %r11, 160(%rsp)
movq %rbx, 152(%rsp)
movq 232(%rsp), %rbx # 8-byte Reload
movq %r15, 144(%rsp)
movl %r12d, 4(%rsp)
leaq 224(%rsp), %rax
movq %rax, 240(%rsp)
leaq 216(%rsp), %rax
movq %rax, 248(%rsp)
leaq 208(%rsp), %rax
movq %rax, 256(%rsp)
leaq 200(%rsp), %rax
movq %rax, 264(%rsp)
leaq 192(%rsp), %rax
movq %rax, 272(%rsp)
leaq 184(%rsp), %rax
movq %rax, 280(%rsp)
leaq 176(%rsp), %rax
movq %rax, 288(%rsp)
leaq 168(%rsp), %rax
movq %rax, 296(%rsp)
leaq 160(%rsp), %rax
movq %rax, 304(%rsp)
leaq 152(%rsp), %rax
movq %rax, 312(%rsp)
leaq 144(%rsp), %rax
movq %rax, 320(%rsp)
leaq 4(%rsp), %rax
movq %rax, 328(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_29:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq 344(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movq 336(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 416
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB4_2
.LBB4_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
jmp .LBB4_2
.LBB4_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.3, %esi
jmp .LBB4_2
.LBB4_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.4, %esi
jmp .LBB4_2
.LBB4_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.5, %esi
jmp .LBB4_2
.LBB4_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.6, %esi
jmp .LBB4_2
.LBB4_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.7, %esi
jmp .LBB4_2
.LBB4_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.8, %esi
jmp .LBB4_2
.LBB4_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.9, %esi
jmp .LBB4_2
.LBB4_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.10, %esi
jmp .LBB4_2
.LBB4_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.11, %esi
.LBB4_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end4:
.size host_code, .Lfunc_end4-host_code
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s, %s\n"
.size .L.str, 21
.type _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i,@object # @_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i:
.quad _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.size _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i, 8
.type _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i,@object # @_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.globl _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i:
.quad _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.size _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i, 8
.type _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i,@object # @_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.globl _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i:
.quad _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.size _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate device memory for uacc_0\n"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for uacc_1\n"
.size .L.str.2, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate device memory for uacc_2\n"
.size .L.str.3, 45
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate device memory for u_0\n"
.size .L.str.4, 42
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device memory for u_1\n"
.size .L.str.5, 42
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to allocate device memory for u_2\n"
.size .L.str.6, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device memory for mu\n"
.size .L.str.7, 41
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate device memory for la\n"
.size .L.str.8, 41
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to allocate device memory for strx\n"
.size .L.str.9, 43
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to allocate device memory for stry\n"
.size .L.str.10, 43
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to allocate device memory for strz\n"
.size .L.str.11, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym _Z20__device_stub__sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym _Z20__device_stub__sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sw4_1PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym _Z5sw4_2PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym _Z5sw4_3PdS_S_S_S_S_S_S_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <float.h>
#include <limits.h>
#define XSIZE 1201
#define YSIZE 801
#define RADIUS 100
#define RADSTEP 1
#define ANGLESIZE 36
#define PI 3.141592653589793
int main()
{
FILE *datTxt,*outputAnisotropy00,*outputAnisotropy09,*outputAnisotropy49,*outputAnisotropy99;
FILE *outputAzimuth00,*outputAzimuth09,*outputAzimuth49,*outputAzimuth99;
int data[YSIZE][XSIZE];
FILE * inpCheck;
inpCheck = fopen("inpCheck.txt","w");
if(inpCheck == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
//1200 ints in a row which are max of 5 digits
//with a space in the front and the back and space
//between each number
char line[1200 * 5 +2+1200];
memset(line, '\0', sizeof(line));
char *startPtr,*endPtr;
datTxt = fopen("dat.txt","r");
if(datTxt == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
outputAnisotropy00 = fopen("outputDataAni00.txt","w");
outputAnisotropy09 = fopen("outputDataAni09.txt","w");
outputAnisotropy49 = fopen("outputDataAni49.txt","w");
outputAnisotropy99 = fopen("outputDataAni99.txt","w");
if((outputAnisotropy00 == NULL)||(outputAnisotropy09 == NULL)||(outputAnisotropy49 == NULL)||(outputAnisotropy99 == NULL)) {
perror("Cannot open Anisotropy file");
return (-1);
}
outputAzimuth00 = fopen("outputDataAzi00.txt","w");
outputAzimuth09 = fopen("outputDataAzi09.txt","w");
outputAzimuth49 = fopen("outputDataAzi49.txt","w");
outputAzimuth99 = fopen("outputDataAzi99.txt","w");
if((outputAzimuth00 == NULL)||(outputAzimuth09 == NULL)||(outputAzimuth49 == NULL)||(outputAzimuth99 == NULL)) {
perror("Cannot open Azimuth file");
return (-1);
}
int i,j,Value;
j = 0;
char tempVal[5];
memset(tempVal,'\0',sizeof(tempVal));
while(fgets(line,1200 *5 + 2 + 1200,datTxt)!=NULL) {
startPtr = line;
for(i=0;i<XSIZE;i++) {
Value = 0;
memset(tempVal,'\0',sizeof(tempVal));
if(i != (XSIZE - 1)) {
endPtr = strchr(startPtr,' ');
strncpy(tempVal,startPtr,endPtr-startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d ",Value);
endPtr = endPtr + 1;
startPtr = endPtr;
}
else if(i == (XSIZE - 1)){
strcpy(tempVal,startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d\n",Value);
}
}
j++;
}
//Fine
float angle[ANGLESIZE];
for(int i=0;i<ANGLESIZE;i++) {
angle[i] = i * 5 * PI/180;
}
//Initializing 3D matrix anisotropy
float*** anisotropy;
anisotropy = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
anisotropy[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
anisotropy[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Initializing 3D matrix anzimuth
float*** azimuth;
azimuth = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
azimuth[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
azimuth[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Actual computation
int xrad,yrad,x,y,xradOrtho,yradOrtho,xradOneEighty,yradOneEighty,valueOneEighty;
float variance[100];
float orientation[100];
float ortho[100];
float value,sum_value,avg_value;
float valueOrtho,sum_valueOrtho,avg_valueOrtho;
sum_value = 0;
avg_value = 0;
sum_valueOrtho = 0;
avg_valueOrtho = 0;
//y = 0;
for(y=0;y<YSIZE;y++) {
for(x = 0;x<XSIZE;x++) {
/*for(x = 0;x<XSIZE+1;x++) {
if(x==XSIZE) {
y++;
if(y==YSIZE){
x = XSIZE;
continue;
}
x=0;
continue;
}
*/
if((y>(YSIZE - RADIUS - 1))||(y<(RADIUS + 1))) continue;
if((x>(XSIZE - RADIUS - 1))||(x<(RADIUS + 1))) continue;
for(i=0;i<100;i++){
variance[i] = FLT_MAX;
ortho[i] = FLT_MAX;
}
//Flipped
for(i=0;i<ANGLESIZE;i++) {
sum_value = 0;
sum_valueOrtho = 0;
for(j = 0;j<RADIUS;j+=RADSTEP) {
xrad = (int)round(cos(angle[i]) * (j+1) + x);
yrad = (int)round(sin(angle[i]) * (j+1) + y);
value = data[y][x] - data[yrad][xrad];
value = value * value * 0.5;
//sum_value = sum_value + value;
//avg_value = sum_value/(j+1);
//Ortho computation
xradOrtho = (int)round(cos(angle[i]+PI/2) * (j+1) + x);
yradOrtho = (int)round(sin(angle[i]+PI/2) * (j+1) + y);
valueOrtho = data[y][x] - data[yradOrtho][xradOrtho];
valueOrtho = valueOrtho * valueOrtho *0.5;
sum_valueOrtho = sum_valueOrtho + valueOrtho;
avg_valueOrtho = sum_valueOrtho/(j+1);
//One eighty angle computation
xradOneEighty = (int)round(cos(angle[i]+PI) * (j+1) + x);
yradOneEighty = (int)round(sin(angle[i]+PI) * (j+1) + y);
valueOneEighty = data[y][x] - data[yradOneEighty][xradOneEighty];
valueOneEighty = valueOneEighty * valueOneEighty * 0.5;
sum_value = sum_value + value + valueOneEighty;
avg_value = sum_value/(2*(j+1));
//Fail safe to ensure there is no nan or inf
if(avg_value == 0) {
if((avg_valueOrtho < 1) && (avg_valueOrtho > 0)) {
avg_value = avg_valueOrtho;
}
else {
avg_value = 1;
}
}
if(avg_valueOrtho == 0) {
avg_valueOrtho = 1;
}
//printf("1(%d,%d) %f %f\n",(j+1),(i+1),variance[j],avg_value);
if(avg_value < variance[j]) {
// printf("2(%d) %f %f\n",j,variance[j],avg_value);
variance[j] = avg_value;
orientation[j] = angle[i];
ortho[j] = avg_valueOrtho;
}
}
}
for(j=0;j<RADIUS;j+=RADSTEP){
anisotropy[y][x][j] = ortho[j]/variance[j];
azimuth[y][x][j] = orientation[j] * 180/PI ;
//printf("%f %f\n",variance[j],anisotropy[y][x][j]);
}
// Writing to files
if (x == (XSIZE - RADIUS - 1)) {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\n");
fprintf(outputAzimuth00,"\n");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\n");
fprintf(outputAzimuth09,"\n");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\n");
fprintf(outputAzimuth49,"\n");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\n");
fprintf(outputAzimuth99,"\n");
}
else {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\t");
fprintf(outputAzimuth00,"\t");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\t");
fprintf(outputAzimuth09,"\t");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\t");
fprintf(outputAzimuth49,"\t");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\t");
fprintf(outputAzimuth99,"\t");
}
}
}
fclose(datTxt);
fclose(inpCheck);
fclose(outputAnisotropy00);
fclose(outputAnisotropy09);
fclose(outputAnisotropy49);
fclose(outputAnisotropy99);
fclose(outputAzimuth00);
fclose(outputAzimuth09);
fclose(outputAzimuth49);
fclose(outputAzimuth99);
//Freeing 3D matrix anisotropy
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(anisotropy[i][j]);
}
free(anisotropy[i]);
}
free(anisotropy);
//Freeing 3D matrix azimuth
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(azimuth[i][j]);
}
free(azimuth[i]);
}
free(azimuth);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <float.h>
#include <limits.h>
#define XSIZE 1201
#define YSIZE 801
#define RADIUS 100
#define RADSTEP 1
#define ANGLESIZE 36
#define PI 3.141592653589793
int main()
{
FILE *datTxt,*outputAnisotropy00,*outputAnisotropy09,*outputAnisotropy49,*outputAnisotropy99;
FILE *outputAzimuth00,*outputAzimuth09,*outputAzimuth49,*outputAzimuth99;
int data[YSIZE][XSIZE];
FILE * inpCheck;
inpCheck = fopen("inpCheck.txt","w");
if(inpCheck == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
//1200 ints in a row which are max of 5 digits
//with a space in the front and the back and space
//between each number
char line[1200 * 5 +2+1200];
memset(line, '\0', sizeof(line));
char *startPtr,*endPtr;
datTxt = fopen("dat.txt","r");
if(datTxt == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
outputAnisotropy00 = fopen("outputDataAni00.txt","w");
outputAnisotropy09 = fopen("outputDataAni09.txt","w");
outputAnisotropy49 = fopen("outputDataAni49.txt","w");
outputAnisotropy99 = fopen("outputDataAni99.txt","w");
if((outputAnisotropy00 == NULL)||(outputAnisotropy09 == NULL)||(outputAnisotropy49 == NULL)||(outputAnisotropy99 == NULL)) {
perror("Cannot open Anisotropy file");
return (-1);
}
outputAzimuth00 = fopen("outputDataAzi00.txt","w");
outputAzimuth09 = fopen("outputDataAzi09.txt","w");
outputAzimuth49 = fopen("outputDataAzi49.txt","w");
outputAzimuth99 = fopen("outputDataAzi99.txt","w");
if((outputAzimuth00 == NULL)||(outputAzimuth09 == NULL)||(outputAzimuth49 == NULL)||(outputAzimuth99 == NULL)) {
perror("Cannot open Azimuth file");
return (-1);
}
int i,j,Value;
j = 0;
char tempVal[5];
memset(tempVal,'\0',sizeof(tempVal));
while(fgets(line,1200 *5 + 2 + 1200,datTxt)!=NULL) {
startPtr = line;
for(i=0;i<XSIZE;i++) {
Value = 0;
memset(tempVal,'\0',sizeof(tempVal));
if(i != (XSIZE - 1)) {
endPtr = strchr(startPtr,' ');
strncpy(tempVal,startPtr,endPtr-startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d ",Value);
endPtr = endPtr + 1;
startPtr = endPtr;
}
else if(i == (XSIZE - 1)){
strcpy(tempVal,startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d\n",Value);
}
}
j++;
}
//Fine
float angle[ANGLESIZE];
for(int i=0;i<ANGLESIZE;i++) {
angle[i] = i * 5 * PI/180;
}
//Initializing 3D matrix anisotropy
float*** anisotropy;
anisotropy = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
anisotropy[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
anisotropy[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Initializing 3D matrix anzimuth
float*** azimuth;
azimuth = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
azimuth[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
azimuth[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Actual computation
int xrad,yrad,x,y,xradOrtho,yradOrtho,xradOneEighty,yradOneEighty,valueOneEighty;
float variance[100];
float orientation[100];
float ortho[100];
float value,sum_value,avg_value;
float valueOrtho,sum_valueOrtho,avg_valueOrtho;
sum_value = 0;
avg_value = 0;
sum_valueOrtho = 0;
avg_valueOrtho = 0;
//y = 0;
for(y=0;y<YSIZE;y++) {
for(x = 0;x<XSIZE;x++) {
/*for(x = 0;x<XSIZE+1;x++) {
if(x==XSIZE) {
y++;
if(y==YSIZE){
x = XSIZE;
continue;
}
x=0;
continue;
}
*/
if((y>(YSIZE - RADIUS - 1))||(y<(RADIUS + 1))) continue;
if((x>(XSIZE - RADIUS - 1))||(x<(RADIUS + 1))) continue;
for(i=0;i<100;i++){
variance[i] = FLT_MAX;
ortho[i] = FLT_MAX;
}
//Flipped
for(i=0;i<ANGLESIZE;i++) {
sum_value = 0;
sum_valueOrtho = 0;
for(j = 0;j<RADIUS;j+=RADSTEP) {
xrad = (int)round(cos(angle[i]) * (j+1) + x);
yrad = (int)round(sin(angle[i]) * (j+1) + y);
value = data[y][x] - data[yrad][xrad];
value = value * value * 0.5;
//sum_value = sum_value + value;
//avg_value = sum_value/(j+1);
//Ortho computation
xradOrtho = (int)round(cos(angle[i]+PI/2) * (j+1) + x);
yradOrtho = (int)round(sin(angle[i]+PI/2) * (j+1) + y);
valueOrtho = data[y][x] - data[yradOrtho][xradOrtho];
valueOrtho = valueOrtho * valueOrtho *0.5;
sum_valueOrtho = sum_valueOrtho + valueOrtho;
avg_valueOrtho = sum_valueOrtho/(j+1);
//One eighty angle computation
xradOneEighty = (int)round(cos(angle[i]+PI) * (j+1) + x);
yradOneEighty = (int)round(sin(angle[i]+PI) * (j+1) + y);
valueOneEighty = data[y][x] - data[yradOneEighty][xradOneEighty];
valueOneEighty = valueOneEighty * valueOneEighty * 0.5;
sum_value = sum_value + value + valueOneEighty;
avg_value = sum_value/(2*(j+1));
//Fail safe to ensure there is no nan or inf
if(avg_value == 0) {
if((avg_valueOrtho < 1) && (avg_valueOrtho > 0)) {
avg_value = avg_valueOrtho;
}
else {
avg_value = 1;
}
}
if(avg_valueOrtho == 0) {
avg_valueOrtho = 1;
}
//printf("1(%d,%d) %f %f\n",(j+1),(i+1),variance[j],avg_value);
if(avg_value < variance[j]) {
// printf("2(%d) %f %f\n",j,variance[j],avg_value);
variance[j] = avg_value;
orientation[j] = angle[i];
ortho[j] = avg_valueOrtho;
}
}
}
for(j=0;j<RADIUS;j+=RADSTEP){
anisotropy[y][x][j] = ortho[j]/variance[j];
azimuth[y][x][j] = orientation[j] * 180/PI ;
//printf("%f %f\n",variance[j],anisotropy[y][x][j]);
}
// Writing to files
if (x == (XSIZE - RADIUS - 1)) {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\n");
fprintf(outputAzimuth00,"\n");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\n");
fprintf(outputAzimuth09,"\n");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\n");
fprintf(outputAzimuth49,"\n");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\n");
fprintf(outputAzimuth99,"\n");
}
else {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\t");
fprintf(outputAzimuth00,"\t");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\t");
fprintf(outputAzimuth09,"\t");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\t");
fprintf(outputAzimuth49,"\t");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\t");
fprintf(outputAzimuth99,"\t");
}
}
}
fclose(datTxt);
fclose(inpCheck);
fclose(outputAnisotropy00);
fclose(outputAnisotropy09);
fclose(outputAnisotropy49);
fclose(outputAnisotropy99);
fclose(outputAzimuth00);
fclose(outputAzimuth09);
fclose(outputAzimuth49);
fclose(outputAzimuth99);
//Freeing 3D matrix anisotropy
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(anisotropy[i][j]);
}
free(anisotropy[i]);
}
free(anisotropy);
//Freeing 3D matrix azimuth
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(azimuth[i][j]);
}
free(azimuth[i]);
}
free(azimuth);
return 0;
} | .file "tmpxft_0005c739_00000000-6_topographic_anisotropy_NewMethod.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "w"
.LC3:
.string "inpCheck.txt"
.LC4:
.string "Cannot open dat.txt file"
.LC5:
.string "r"
.LC6:
.string "dat.txt"
.LC7:
.string "outputDataAni00.txt"
.LC8:
.string "outputDataAni09.txt"
.LC9:
.string "outputDataAni49.txt"
.LC10:
.string "outputDataAni99.txt"
.LC11:
.string "Cannot open Anisotropy file"
.LC12:
.string "outputDataAzi00.txt"
.LC13:
.string "outputDataAzi09.txt"
.LC14:
.string "outputDataAzi49.txt"
.LC15:
.string "outputDataAzi99.txt"
.LC16:
.string "Cannot open Azimuth file"
.LC17:
.string "%d "
.LC18:
.string "%d\n"
.LC26:
.string "%f"
.LC27:
.string "\n"
.LC28:
.string "\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -3854336(%rsp), %r11
.cfi_def_cfa 11, 3854392
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2552, %rsp
.cfi_def_cfa_offset 3856944
movq %fs:40, %rax
movq %rax, 3856872(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L68
movq %rax, %r15
leaq 3849664(%rsp), %rdx
movl $900, %ecx
movl $0, %eax
movq %rdx, %rdi
rep stosq
movw $0, (%rdi)
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, 176(%rsp)
testq %rax, %rax
je .L69
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, %r14
movq %rax, 112(%rsp)
movq %rbx, %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %rax, 120(%rsp)
movq %rbx, %rsi
leaq .LC9(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movq %rax, 128(%rsp)
movq %rbx, %rsi
leaq .LC10(%rip), %rdi
call fopen@PLT
movq %rax, 160(%rsp)
testq %r14, %r14
je .L7
testq %rbp, %rbp
je .L7
testq %r13, %r13
je .L7
testq %rax, %rax
je .L7
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
leaq .LC12(%rip), %rdi
call fopen@PLT
movq %rax, %r14
movq %rax, 136(%rsp)
movq %rbx, %rsi
leaq .LC13(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %rax, 144(%rsp)
movq %rbx, %rsi
leaq .LC14(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movq %rax, 152(%rsp)
movq %rbx, %rsi
leaq .LC15(%rip), %rdi
call fopen@PLT
movq %rax, 168(%rsp)
testq %r14, %r14
je .L10
testq %rbp, %rbp
je .L10
testq %r13, %r13
je .L10
testq %rax, %rax
je .L10
movl $0, 3849659(%rsp)
movb $0, 3849663(%rsp)
leaq 6448(%rsp), %rbx
leaq 3849664(%rsp), %r14
jmp .L13
.L68:
leaq .LC4(%rip), %rdi
call perror@PLT
movl $-1, %eax
jmp .L3
.L69:
leaq .LC4(%rip), %rdi
call perror@PLT
movl $-1, %eax
jmp .L3
.L7:
leaq .LC11(%rip), %rdi
call perror@PLT
movl $-1, %eax
jmp .L3
.L10:
leaq .LC16(%rip), %rdi
call perror@PLT
movl $-1, %eax
jmp .L3
.L70:
movl $32, %esi
movq %r12, %rdi
call strchr@PLT
movq %rax, %rdx
movq %rax, (%rsp)
subq %r12, %rdx
leaq 3849659(%rsp), %r13
movl $5, %ecx
movq %r12, %rsi
movq %r13, %rdi
call __strncpy_chk@PLT
movl $10, %edx
movl $0, %esi
movq %r13, %rdi
call __isoc23_strtol@PLT
movl %eax, %ecx
movl %eax, 0(%rbp)
leaq .LC17(%rip), %rdx
movl $2, %esi
movq %r15, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq (%rsp), %rdx
addq $1, %rdx
movq %rdx, %r12
leaq 4(%rbp), %rax
cmpq %rbx, %rbp
je .L16
movq %rax, %rbp
.L15:
movl $0, 3849659(%rsp)
movb $0, 3849663(%rsp)
cmpq %rbx, %rbp
jne .L70
leaq 3849659(%rsp), %rbp
movl $5, %edx
movq %r12, %rsi
movq %rbp, %rdi
call __strcpy_chk@PLT
movl $10, %edx
movl $0, %esi
movq %rbp, %rdi
call __isoc23_strtol@PLT
movl %eax, %ecx
movl %eax, (%rbx)
leaq .LC18(%rip), %rdx
movl $2, %esi
movq %r15, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L16:
addq $4804, %rbx
.L13:
movq 176(%rsp), %rcx
movl $7202, %edx
movl $7202, %esi
movq %r14, %rdi
call __fgets_chk@PLT
testq %rax, %rax
je .L71
leaq -4800(%rbx), %rbp
movq %r14, %r12
jmp .L15
.L71:
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
movq %rax, %rdx
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC19(%rip), %xmm0
divsd .LC20(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rdx)
addl $5, %eax
addq $4, %rdx
cmpl $180, %eax
jne .L18
movl $6408, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, 184(%rsp)
movq %rax, %r13
leaq 6408(%rax), %r14
.L20:
movl $9608, %edi
call malloc@PLT
movq %rax, (%r12)
movq %rax, %rbx
leaq 9608(%rax), %rbp
.L19:
movl $400, %edi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbx, %rbp
jne .L19
addq $8, %r12
cmpq %r14, %r12
jne .L20
movl $6408, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, 192(%rsp)
movq %rax, %rbp
leaq 6408(%rax), %rax
movq %rax, 200(%rsp)
.L22:
movl $9608, %edi
call malloc@PLT
movq %rax, (%r12)
movq %rax, %rbx
addq $9608, %rax
movq %rax, (%rsp)
.L21:
movl $400, %edi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbx, (%rsp)
jne .L21
addq $8, %r12
cmpq %r12, 200(%rsp)
jne .L22
leaq 1648(%rsp), %rcx
movl $0, %edx
jmp .L23
.L27:
movd %ebp, %xmm4
pxor %xmm5, %xmm5
ucomiss %xmm5, %xmm4
jp .L29
cmove %r13d, %ebp
.L29:
movss 444(%rsp,%rbx,4), %xmm1
comiss %xmm0, %xmm1
jbe .L32
movss %xmm0, 444(%rsp,%rbx,4)
movl %r14d, 844(%rsp,%rbx,4)
movl %ebp, 1244(%rsp,%rbx,4)
.L32:
addq $1, %rbx
cmpq $101, %rbx
je .L72
.L34:
pxor %xmm5, %xmm5
cvtsi2ssl %ebx, %xmm5
movss %xmm5, 8(%rsp)
movaps %xmm5, %xmm0
mulss 84(%rsp), %xmm0
addss 92(%rsp), %xmm0
call roundf@PLT
movss %xmm0, (%rsp)
movss 8(%rsp), %xmm6
mulss 88(%rsp), %xmm6
movaps %xmm6, %xmm0
addss 104(%rsp), %xmm0
call roundf@PLT
cvttss2sil (%rsp), %edx
movslq %edx, %rdx
cvttss2sil %xmm0, %eax
cltq
imulq $1201, %rax, %rax
addq %rdx, %rax
movl %r12d, %ecx
subl 1648(%rsp,%rax,4), %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss %xmm0, %xmm0
movss %xmm0, 80(%rsp)
pxor %xmm3, %xmm3
cvtsi2sdl %ebx, %xmm3
movsd 48(%rsp), %xmm5
movsd %xmm3, (%rsp)
mulsd %xmm3, %xmm5
movapd %xmm5, %xmm0
addsd 16(%rsp), %xmm0
call round@PLT
movsd %xmm0, 40(%rsp)
movsd (%rsp), %xmm4
mulsd 56(%rsp), %xmm4
movapd %xmm4, %xmm0
addsd 24(%rsp), %xmm0
call round@PLT
cvttsd2sil 40(%rsp), %edx
movslq %edx, %rdx
cvttsd2sil %xmm0, %eax
cltq
imulq $1201, %rax, %rax
addq %rdx, %rax
movl %r12d, %esi
subl 1648(%rsp,%rax,4), %esi
pxor %xmm0, %xmm0
cvtsi2ssl %esi, %xmm0
mulss %xmm0, %xmm0
mulss .LC22(%rip), %xmm0
addss 32(%rsp), %xmm0
movaps %xmm0, %xmm7
movss %xmm0, 32(%rsp)
divss 8(%rsp), %xmm7
movd %xmm7, %ebp
movsd (%rsp), %xmm0
mulsd 64(%rsp), %xmm0
addsd 16(%rsp), %xmm0
call round@PLT
movsd %xmm0, 8(%rsp)
movsd (%rsp), %xmm0
mulsd 72(%rsp), %xmm0
addsd 24(%rsp), %xmm0
call round@PLT
cvttsd2sil 8(%rsp), %edx
movslq %edx, %rdx
cvttsd2sil %xmm0, %eax
cltq
imulq $1201, %rax, %rax
addq %rdx, %rax
movl %r12d, %edi
subl 1648(%rsp,%rax,4), %edi
movl %edi, %eax
imull %edi, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd .LC23(%rip), %xmm1
movss .LC22(%rip), %xmm6
mulss 80(%rsp), %xmm6
movaps %xmm6, %xmm0
addss 36(%rsp), %xmm0
cvttsd2sil %xmm1, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movaps %xmm1, %xmm2
addss %xmm0, %xmm2
movss %xmm2, 36(%rsp)
leal (%rbx,%rbx), %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm2
movaps %xmm2, %xmm0
pxor %xmm6, %xmm6
ucomiss %xmm6, %xmm2
jp .L27
movaps %xmm6, %xmm7
jne .L27
movss .LC1(%rip), %xmm3
movd %ebp, %xmm6
movss .LC1(%rip), %xmm0
comiss %xmm6, %xmm3
jbe .L29
movd %ebp, %xmm0
comiss %xmm7, %xmm6
ja .L29
movaps %xmm3, %xmm0
jmp .L27
.L72:
addq $4, %r15
movq 96(%rsp), %rax
cmpq %rax, %r15
je .L35
.L26:
movl (%r15), %r14d
leaq 300(%rsp), %rdi
leaq 296(%rsp), %rsi
movd %r14d, %xmm0
call sincosf@PLT
movss 296(%rsp), %xmm2
movss %xmm2, 84(%rsp)
movss 300(%rsp), %xmm5
movss %xmm5, 88(%rsp)
movd %r14d, %xmm2
pxor %xmm5, %xmm5
cvtss2sd %xmm2, %xmm5
leaq 288(%rsp), %rbx
leaq 280(%rsp), %rbp
movsd .LC24(%rip), %xmm2
movsd %xmm5, (%rsp)
addsd %xmm5, %xmm2
movapd %xmm2, %xmm0
movq %rbp, %rsi
movq %rbx, %rdi
call sincos@PLT
movsd 280(%rsp), %xmm2
movsd %xmm2, 48(%rsp)
movsd 288(%rsp), %xmm2
movsd %xmm2, 56(%rsp)
movsd (%rsp), %xmm0
addsd .LC19(%rip), %xmm0
movq %rbp, %rsi
movq %rbx, %rdi
call sincos@PLT
movsd 280(%rsp), %xmm5
movsd %xmm5, 64(%rsp)
movsd 288(%rsp), %xmm5
movsd %xmm5, 72(%rsp)
movl $1, %ebx
movl $0x00000000, 32(%rsp)
movl $0x00000000, 36(%rsp)
movl 108(%rsp), %ecx
pxor %xmm5, %xmm5
cvtsi2ssl %ecx, %xmm5
movss %xmm5, 92(%rsp)
movl 216(%rsp), %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
movss %xmm2, 104(%rsp)
pxor %xmm5, %xmm5
cvtsi2sdl %ecx, %xmm5
movsd %xmm5, 16(%rsp)
pxor %xmm2, %xmm2
cvtsi2sdl %eax, %xmm2
movsd %xmm2, 24(%rsp)
movl .LC1(%rip), %r13d
jmp .L34
.L35:
movq 264(%rsp), %rbx
movq 272(%rsp), %rbp
movq 184(%rsp), %rax
movq (%rax,%rbp,8), %rcx
movq (%rcx,%rbx,8), %r13
movq 192(%rsp), %rax
movq (%rax,%rbp,8), %r14
movq (%r14,%rbx,8), %r12
movl $0, %eax
leaq 448(%rsp), %rdx
movss .LC25(%rip), %xmm2
movsd .LC19(%rip), %xmm1
.L36:
movss 1248(%rsp,%rax), %xmm0
divss (%rax,%rdx), %xmm0
movss %xmm0, 0(%r13,%rax)
movaps %xmm2, %xmm0
mulss 848(%rsp,%rax), %xmm0
cvtss2sd %xmm0, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L36
cmpl $1100, %ebx
je .L73
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
leaq .LC26(%rip), %r15
movq %r15, %rdx
movl $2, %esi
movq 112(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 136(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq .LC28(%rip), %r14
movq %r14, %rdx
movl $2, %esi
movq 112(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq 136(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%r13), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 120(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%r12), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 144(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq 120(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq 144(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 196(%r13), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 128(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 196(%r12), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 152(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq 128(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq 152(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 396(%r13), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 160(%rsp), %r13
movq %r13, %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 396(%r12), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 168(%rsp), %r15
movq %r15, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq %r15, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L38:
addq $1, %rbx
jmp .L41
.L73:
movq 8800(%rcx), %r15
pxor %xmm0, %xmm0
cvtss2sd (%r15), %xmm0
leaq .LC26(%rip), %r13
movq %r13, %rdx
movl $2, %esi
movq 112(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 8800(%r14), %r14
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 136(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq .LC27(%rip), %r12
movq %r12, %rdx
movl $2, %esi
movq 112(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 136(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%r15), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 120(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%r14), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 144(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 120(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 144(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 196(%r15), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 128(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 196(%r14), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 152(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 128(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 152(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 396(%r15), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 160(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 396(%r14), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 168(%rsp), %r15
movq %r15, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 160(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq %r15, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L38
.L24:
addq $1, %rbx
cmpq $1201, %rbx
je .L74
.L41:
movl 220(%rsp), %eax
subl $101, %eax
cmpl $599, %eax
ja .L24
leal -101(%rbx), %eax
cmpl $999, %eax
ja .L24
movl $0, %eax
.L25:
movss .LC21(%rip), %xmm5
movss %xmm5, 448(%rsp,%rax)
movss %xmm5, 1248(%rsp,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L25
movl %ebx, 108(%rsp)
movq 208(%rsp), %rax
movl (%rax,%rbx,4), %r12d
movq 224(%rsp), %r15
leaq 144(%r15), %rax
movq %rax, 96(%rsp)
movq %rbx, 264(%rsp)
movq %rbp, 272(%rsp)
jmp .L26
.L74:
movq 232(%rsp), %r13
movq 208(%rsp), %rcx
movq 240(%rsp), %r15
movq %rbp, %rdx
movq 248(%rsp), %rbp
movq 256(%rsp), %r14
addq $1, %rdx
addq $4804, %rcx
cmpq $801, %rdx
je .L40
.L23:
movl %edx, 220(%rsp)
movl %edx, 216(%rsp)
movl $0, %ebx
movq %r13, 232(%rsp)
movq %rcx, 208(%rsp)
movq %r15, 240(%rsp)
movq %rbp, 248(%rsp)
movq %rdx, %rbp
movq %r14, 256(%rsp)
jmp .L41
.L40:
movq 176(%rsp), %rdi
call fclose@PLT
movq %r15, %rdi
call fclose@PLT
movq 112(%rsp), %rdi
call fclose@PLT
movq 120(%rsp), %rdi
call fclose@PLT
movq 128(%rsp), %rdi
call fclose@PLT
movq 160(%rsp), %rdi
call fclose@PLT
movq 136(%rsp), %rdi
call fclose@PLT
movq 144(%rsp), %rdi
call fclose@PLT
movq 152(%rsp), %rdi
call fclose@PLT
movq 168(%rsp), %rdi
call fclose@PLT
.L42:
movl $0, %ebx
.L43:
movq 0(%r13), %r12
movq (%r12,%rbx), %rdi
call free@PLT
addq $8, %rbx
cmpq $9608, %rbx
jne .L43
movq %r12, %rdi
call free@PLT
addq $8, %r13
cmpq %r14, %r13
jne .L42
movq 184(%rsp), %rdi
call free@PLT
.L45:
movl $0, %ebx
.L46:
movq 0(%rbp), %r12
movq (%r12,%rbx), %rdi
call free@PLT
addq $8, %rbx
cmpq $9608, %rbx
jne .L46
movq %r12, %rdi
call free@PLT
addq $8, %rbp
cmpq %rbp, 200(%rsp)
jne .L45
movq 192(%rsp), %rdi
call free@PLT
movl $0, %eax
.L3:
movq 3856872(%rsp), %rdx
subq %fs:40, %rdx
jne .L75
addq $3856888, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC19:
.long 1413754136
.long 1074340347
.align 8
.LC20:
.long 0
.long 1080459264
.section .rodata.cst4
.align 4
.LC21:
.long 2139095039
.align 4
.LC22:
.long 1056964608
.section .rodata.cst8
.align 8
.LC23:
.long 0
.long 1071644672
.align 8
.LC24:
.long 1413754136
.long 1073291771
.section .rodata.cst4
.align 4
.LC25:
.long 1127481344
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <float.h>
#include <limits.h>
#define XSIZE 1201
#define YSIZE 801
#define RADIUS 100
#define RADSTEP 1
#define ANGLESIZE 36
#define PI 3.141592653589793
int main()
{
FILE *datTxt,*outputAnisotropy00,*outputAnisotropy09,*outputAnisotropy49,*outputAnisotropy99;
FILE *outputAzimuth00,*outputAzimuth09,*outputAzimuth49,*outputAzimuth99;
int data[YSIZE][XSIZE];
FILE * inpCheck;
inpCheck = fopen("inpCheck.txt","w");
if(inpCheck == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
//1200 ints in a row which are max of 5 digits
//with a space in the front and the back and space
//between each number
char line[1200 * 5 +2+1200];
memset(line, '\0', sizeof(line));
char *startPtr,*endPtr;
datTxt = fopen("dat.txt","r");
if(datTxt == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
outputAnisotropy00 = fopen("outputDataAni00.txt","w");
outputAnisotropy09 = fopen("outputDataAni09.txt","w");
outputAnisotropy49 = fopen("outputDataAni49.txt","w");
outputAnisotropy99 = fopen("outputDataAni99.txt","w");
if((outputAnisotropy00 == NULL)||(outputAnisotropy09 == NULL)||(outputAnisotropy49 == NULL)||(outputAnisotropy99 == NULL)) {
perror("Cannot open Anisotropy file");
return (-1);
}
outputAzimuth00 = fopen("outputDataAzi00.txt","w");
outputAzimuth09 = fopen("outputDataAzi09.txt","w");
outputAzimuth49 = fopen("outputDataAzi49.txt","w");
outputAzimuth99 = fopen("outputDataAzi99.txt","w");
if((outputAzimuth00 == NULL)||(outputAzimuth09 == NULL)||(outputAzimuth49 == NULL)||(outputAzimuth99 == NULL)) {
perror("Cannot open Azimuth file");
return (-1);
}
int i,j,Value;
j = 0;
char tempVal[5];
memset(tempVal,'\0',sizeof(tempVal));
while(fgets(line,1200 *5 + 2 + 1200,datTxt)!=NULL) {
startPtr = line;
for(i=0;i<XSIZE;i++) {
Value = 0;
memset(tempVal,'\0',sizeof(tempVal));
if(i != (XSIZE - 1)) {
endPtr = strchr(startPtr,' ');
strncpy(tempVal,startPtr,endPtr-startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d ",Value);
endPtr = endPtr + 1;
startPtr = endPtr;
}
else if(i == (XSIZE - 1)){
strcpy(tempVal,startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d\n",Value);
}
}
j++;
}
//Fine
float angle[ANGLESIZE];
for(int i=0;i<ANGLESIZE;i++) {
angle[i] = i * 5 * PI/180;
}
//Initializing 3D matrix anisotropy
float*** anisotropy;
anisotropy = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
anisotropy[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
anisotropy[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Initializing 3D matrix anzimuth
float*** azimuth;
azimuth = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
azimuth[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
azimuth[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Actual computation
int xrad,yrad,x,y,xradOrtho,yradOrtho,xradOneEighty,yradOneEighty,valueOneEighty;
float variance[100];
float orientation[100];
float ortho[100];
float value,sum_value,avg_value;
float valueOrtho,sum_valueOrtho,avg_valueOrtho;
sum_value = 0;
avg_value = 0;
sum_valueOrtho = 0;
avg_valueOrtho = 0;
//y = 0;
for(y=0;y<YSIZE;y++) {
for(x = 0;x<XSIZE;x++) {
/*for(x = 0;x<XSIZE+1;x++) {
if(x==XSIZE) {
y++;
if(y==YSIZE){
x = XSIZE;
continue;
}
x=0;
continue;
}
*/
if((y>(YSIZE - RADIUS - 1))||(y<(RADIUS + 1))) continue;
if((x>(XSIZE - RADIUS - 1))||(x<(RADIUS + 1))) continue;
for(i=0;i<100;i++){
variance[i] = FLT_MAX;
ortho[i] = FLT_MAX;
}
//Flipped
for(i=0;i<ANGLESIZE;i++) {
sum_value = 0;
sum_valueOrtho = 0;
for(j = 0;j<RADIUS;j+=RADSTEP) {
xrad = (int)round(cos(angle[i]) * (j+1) + x);
yrad = (int)round(sin(angle[i]) * (j+1) + y);
value = data[y][x] - data[yrad][xrad];
value = value * value * 0.5;
//sum_value = sum_value + value;
//avg_value = sum_value/(j+1);
//Ortho computation
xradOrtho = (int)round(cos(angle[i]+PI/2) * (j+1) + x);
yradOrtho = (int)round(sin(angle[i]+PI/2) * (j+1) + y);
valueOrtho = data[y][x] - data[yradOrtho][xradOrtho];
valueOrtho = valueOrtho * valueOrtho *0.5;
sum_valueOrtho = sum_valueOrtho + valueOrtho;
avg_valueOrtho = sum_valueOrtho/(j+1);
//One eighty angle computation
xradOneEighty = (int)round(cos(angle[i]+PI) * (j+1) + x);
yradOneEighty = (int)round(sin(angle[i]+PI) * (j+1) + y);
valueOneEighty = data[y][x] - data[yradOneEighty][xradOneEighty];
valueOneEighty = valueOneEighty * valueOneEighty * 0.5;
sum_value = sum_value + value + valueOneEighty;
avg_value = sum_value/(2*(j+1));
//Fail safe to ensure there is no nan or inf
if(avg_value == 0) {
if((avg_valueOrtho < 1) && (avg_valueOrtho > 0)) {
avg_value = avg_valueOrtho;
}
else {
avg_value = 1;
}
}
if(avg_valueOrtho == 0) {
avg_valueOrtho = 1;
}
//printf("1(%d,%d) %f %f\n",(j+1),(i+1),variance[j],avg_value);
if(avg_value < variance[j]) {
// printf("2(%d) %f %f\n",j,variance[j],avg_value);
variance[j] = avg_value;
orientation[j] = angle[i];
ortho[j] = avg_valueOrtho;
}
}
}
for(j=0;j<RADIUS;j+=RADSTEP){
anisotropy[y][x][j] = ortho[j]/variance[j];
azimuth[y][x][j] = orientation[j] * 180/PI ;
//printf("%f %f\n",variance[j],anisotropy[y][x][j]);
}
// Writing to files
if (x == (XSIZE - RADIUS - 1)) {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\n");
fprintf(outputAzimuth00,"\n");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\n");
fprintf(outputAzimuth09,"\n");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\n");
fprintf(outputAzimuth49,"\n");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\n");
fprintf(outputAzimuth99,"\n");
}
else {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\t");
fprintf(outputAzimuth00,"\t");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\t");
fprintf(outputAzimuth09,"\t");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\t");
fprintf(outputAzimuth49,"\t");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\t");
fprintf(outputAzimuth99,"\t");
}
}
}
fclose(datTxt);
fclose(inpCheck);
fclose(outputAnisotropy00);
fclose(outputAnisotropy09);
fclose(outputAnisotropy49);
fclose(outputAnisotropy99);
fclose(outputAzimuth00);
fclose(outputAzimuth09);
fclose(outputAzimuth49);
fclose(outputAzimuth99);
//Freeing 3D matrix anisotropy
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(anisotropy[i][j]);
}
free(anisotropy[i]);
}
free(anisotropy);
//Freeing 3D matrix azimuth
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(azimuth[i][j]);
}
free(azimuth[i]);
}
free(azimuth);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <float.h>
#include <limits.h>
#define XSIZE 1201
#define YSIZE 801
#define RADIUS 100
#define RADSTEP 1
#define ANGLESIZE 36
#define PI 3.141592653589793
int main()
{
FILE *datTxt,*outputAnisotropy00,*outputAnisotropy09,*outputAnisotropy49,*outputAnisotropy99;
FILE *outputAzimuth00,*outputAzimuth09,*outputAzimuth49,*outputAzimuth99;
int data[YSIZE][XSIZE];
FILE * inpCheck;
inpCheck = fopen("inpCheck.txt","w");
if(inpCheck == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
//1200 ints in a row which are max of 5 digits
//with a space in the front and the back and space
//between each number
char line[1200 * 5 +2+1200];
memset(line, '\0', sizeof(line));
char *startPtr,*endPtr;
datTxt = fopen("dat.txt","r");
if(datTxt == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
outputAnisotropy00 = fopen("outputDataAni00.txt","w");
outputAnisotropy09 = fopen("outputDataAni09.txt","w");
outputAnisotropy49 = fopen("outputDataAni49.txt","w");
outputAnisotropy99 = fopen("outputDataAni99.txt","w");
if((outputAnisotropy00 == NULL)||(outputAnisotropy09 == NULL)||(outputAnisotropy49 == NULL)||(outputAnisotropy99 == NULL)) {
perror("Cannot open Anisotropy file");
return (-1);
}
outputAzimuth00 = fopen("outputDataAzi00.txt","w");
outputAzimuth09 = fopen("outputDataAzi09.txt","w");
outputAzimuth49 = fopen("outputDataAzi49.txt","w");
outputAzimuth99 = fopen("outputDataAzi99.txt","w");
if((outputAzimuth00 == NULL)||(outputAzimuth09 == NULL)||(outputAzimuth49 == NULL)||(outputAzimuth99 == NULL)) {
perror("Cannot open Azimuth file");
return (-1);
}
int i,j,Value;
j = 0;
char tempVal[5];
memset(tempVal,'\0',sizeof(tempVal));
while(fgets(line,1200 *5 + 2 + 1200,datTxt)!=NULL) {
startPtr = line;
for(i=0;i<XSIZE;i++) {
Value = 0;
memset(tempVal,'\0',sizeof(tempVal));
if(i != (XSIZE - 1)) {
endPtr = strchr(startPtr,' ');
strncpy(tempVal,startPtr,endPtr-startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d ",Value);
endPtr = endPtr + 1;
startPtr = endPtr;
}
else if(i == (XSIZE - 1)){
strcpy(tempVal,startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d\n",Value);
}
}
j++;
}
//Fine
float angle[ANGLESIZE];
for(int i=0;i<ANGLESIZE;i++) {
angle[i] = i * 5 * PI/180;
}
//Initializing 3D matrix anisotropy
float*** anisotropy;
anisotropy = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
anisotropy[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
anisotropy[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Initializing 3D matrix anzimuth
float*** azimuth;
azimuth = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
azimuth[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
azimuth[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Actual computation
int xrad,yrad,x,y,xradOrtho,yradOrtho,xradOneEighty,yradOneEighty,valueOneEighty;
float variance[100];
float orientation[100];
float ortho[100];
float value,sum_value,avg_value;
float valueOrtho,sum_valueOrtho,avg_valueOrtho;
sum_value = 0;
avg_value = 0;
sum_valueOrtho = 0;
avg_valueOrtho = 0;
//y = 0;
for(y=0;y<YSIZE;y++) {
for(x = 0;x<XSIZE;x++) {
/*for(x = 0;x<XSIZE+1;x++) {
if(x==XSIZE) {
y++;
if(y==YSIZE){
x = XSIZE;
continue;
}
x=0;
continue;
}
*/
if((y>(YSIZE - RADIUS - 1))||(y<(RADIUS + 1))) continue;
if((x>(XSIZE - RADIUS - 1))||(x<(RADIUS + 1))) continue;
for(i=0;i<100;i++){
variance[i] = FLT_MAX;
ortho[i] = FLT_MAX;
}
//Flipped
for(i=0;i<ANGLESIZE;i++) {
sum_value = 0;
sum_valueOrtho = 0;
for(j = 0;j<RADIUS;j+=RADSTEP) {
xrad = (int)round(cos(angle[i]) * (j+1) + x);
yrad = (int)round(sin(angle[i]) * (j+1) + y);
value = data[y][x] - data[yrad][xrad];
value = value * value * 0.5;
//sum_value = sum_value + value;
//avg_value = sum_value/(j+1);
//Ortho computation
xradOrtho = (int)round(cos(angle[i]+PI/2) * (j+1) + x);
yradOrtho = (int)round(sin(angle[i]+PI/2) * (j+1) + y);
valueOrtho = data[y][x] - data[yradOrtho][xradOrtho];
valueOrtho = valueOrtho * valueOrtho *0.5;
sum_valueOrtho = sum_valueOrtho + valueOrtho;
avg_valueOrtho = sum_valueOrtho/(j+1);
//One eighty angle computation
xradOneEighty = (int)round(cos(angle[i]+PI) * (j+1) + x);
yradOneEighty = (int)round(sin(angle[i]+PI) * (j+1) + y);
valueOneEighty = data[y][x] - data[yradOneEighty][xradOneEighty];
valueOneEighty = valueOneEighty * valueOneEighty * 0.5;
sum_value = sum_value + value + valueOneEighty;
avg_value = sum_value/(2*(j+1));
//Fail safe to ensure there is no nan or inf
if(avg_value == 0) {
if((avg_valueOrtho < 1) && (avg_valueOrtho > 0)) {
avg_value = avg_valueOrtho;
}
else {
avg_value = 1;
}
}
if(avg_valueOrtho == 0) {
avg_valueOrtho = 1;
}
//printf("1(%d,%d) %f %f\n",(j+1),(i+1),variance[j],avg_value);
if(avg_value < variance[j]) {
// printf("2(%d) %f %f\n",j,variance[j],avg_value);
variance[j] = avg_value;
orientation[j] = angle[i];
ortho[j] = avg_valueOrtho;
}
}
}
for(j=0;j<RADIUS;j+=RADSTEP){
anisotropy[y][x][j] = ortho[j]/variance[j];
azimuth[y][x][j] = orientation[j] * 180/PI ;
//printf("%f %f\n",variance[j],anisotropy[y][x][j]);
}
// Writing to files
if (x == (XSIZE - RADIUS - 1)) {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\n");
fprintf(outputAzimuth00,"\n");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\n");
fprintf(outputAzimuth09,"\n");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\n");
fprintf(outputAzimuth49,"\n");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\n");
fprintf(outputAzimuth99,"\n");
}
else {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\t");
fprintf(outputAzimuth00,"\t");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\t");
fprintf(outputAzimuth09,"\t");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\t");
fprintf(outputAzimuth49,"\t");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\t");
fprintf(outputAzimuth99,"\t");
}
}
}
fclose(datTxt);
fclose(inpCheck);
fclose(outputAnisotropy00);
fclose(outputAnisotropy09);
fclose(outputAnisotropy49);
fclose(outputAnisotropy99);
fclose(outputAzimuth00);
fclose(outputAzimuth09);
fclose(outputAzimuth49);
fclose(outputAzimuth99);
//Freeing 3D matrix anisotropy
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(anisotropy[i][j]);
}
free(anisotropy[i]);
}
free(anisotropy);
//Freeing 3D matrix azimuth
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(azimuth[i][j]);
}
free(azimuth[i]);
}
free(azimuth);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <float.h>
#include <limits.h>
#define XSIZE 1201
#define YSIZE 801
#define RADIUS 100
#define RADSTEP 1
#define ANGLESIZE 36
#define PI 3.141592653589793
int main()
{
FILE *datTxt,*outputAnisotropy00,*outputAnisotropy09,*outputAnisotropy49,*outputAnisotropy99;
FILE *outputAzimuth00,*outputAzimuth09,*outputAzimuth49,*outputAzimuth99;
int data[YSIZE][XSIZE];
FILE * inpCheck;
inpCheck = fopen("inpCheck.txt","w");
if(inpCheck == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
//1200 ints in a row which are max of 5 digits
//with a space in the front and the back and space
//between each number
char line[1200 * 5 +2+1200];
memset(line, '\0', sizeof(line));
char *startPtr,*endPtr;
datTxt = fopen("dat.txt","r");
if(datTxt == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
outputAnisotropy00 = fopen("outputDataAni00.txt","w");
outputAnisotropy09 = fopen("outputDataAni09.txt","w");
outputAnisotropy49 = fopen("outputDataAni49.txt","w");
outputAnisotropy99 = fopen("outputDataAni99.txt","w");
if((outputAnisotropy00 == NULL)||(outputAnisotropy09 == NULL)||(outputAnisotropy49 == NULL)||(outputAnisotropy99 == NULL)) {
perror("Cannot open Anisotropy file");
return (-1);
}
outputAzimuth00 = fopen("outputDataAzi00.txt","w");
outputAzimuth09 = fopen("outputDataAzi09.txt","w");
outputAzimuth49 = fopen("outputDataAzi49.txt","w");
outputAzimuth99 = fopen("outputDataAzi99.txt","w");
if((outputAzimuth00 == NULL)||(outputAzimuth09 == NULL)||(outputAzimuth49 == NULL)||(outputAzimuth99 == NULL)) {
perror("Cannot open Azimuth file");
return (-1);
}
int i,j,Value;
j = 0;
char tempVal[5];
memset(tempVal,'\0',sizeof(tempVal));
while(fgets(line,1200 *5 + 2 + 1200,datTxt)!=NULL) {
startPtr = line;
for(i=0;i<XSIZE;i++) {
Value = 0;
memset(tempVal,'\0',sizeof(tempVal));
if(i != (XSIZE - 1)) {
endPtr = strchr(startPtr,' ');
strncpy(tempVal,startPtr,endPtr-startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d ",Value);
endPtr = endPtr + 1;
startPtr = endPtr;
}
else if(i == (XSIZE - 1)){
strcpy(tempVal,startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d\n",Value);
}
}
j++;
}
//Fine
float angle[ANGLESIZE];
for(int i=0;i<ANGLESIZE;i++) {
angle[i] = i * 5 * PI/180;
}
//Initializing 3D matrix anisotropy
float*** anisotropy;
anisotropy = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
anisotropy[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
anisotropy[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Initializing 3D matrix anzimuth
float*** azimuth;
azimuth = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
azimuth[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
azimuth[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Actual computation
int xrad,yrad,x,y,xradOrtho,yradOrtho,xradOneEighty,yradOneEighty,valueOneEighty;
float variance[100];
float orientation[100];
float ortho[100];
float value,sum_value,avg_value;
float valueOrtho,sum_valueOrtho,avg_valueOrtho;
sum_value = 0;
avg_value = 0;
sum_valueOrtho = 0;
avg_valueOrtho = 0;
//y = 0;
for(y=0;y<YSIZE;y++) {
for(x = 0;x<XSIZE;x++) {
/*for(x = 0;x<XSIZE+1;x++) {
if(x==XSIZE) {
y++;
if(y==YSIZE){
x = XSIZE;
continue;
}
x=0;
continue;
}
*/
if((y>(YSIZE - RADIUS - 1))||(y<(RADIUS + 1))) continue;
if((x>(XSIZE - RADIUS - 1))||(x<(RADIUS + 1))) continue;
for(i=0;i<100;i++){
variance[i] = FLT_MAX;
ortho[i] = FLT_MAX;
}
//Flipped
for(i=0;i<ANGLESIZE;i++) {
sum_value = 0;
sum_valueOrtho = 0;
for(j = 0;j<RADIUS;j+=RADSTEP) {
xrad = (int)round(cos(angle[i]) * (j+1) + x);
yrad = (int)round(sin(angle[i]) * (j+1) + y);
value = data[y][x] - data[yrad][xrad];
value = value * value * 0.5;
//sum_value = sum_value + value;
//avg_value = sum_value/(j+1);
//Ortho computation
xradOrtho = (int)round(cos(angle[i]+PI/2) * (j+1) + x);
yradOrtho = (int)round(sin(angle[i]+PI/2) * (j+1) + y);
valueOrtho = data[y][x] - data[yradOrtho][xradOrtho];
valueOrtho = valueOrtho * valueOrtho *0.5;
sum_valueOrtho = sum_valueOrtho + valueOrtho;
avg_valueOrtho = sum_valueOrtho/(j+1);
//One eighty angle computation
xradOneEighty = (int)round(cos(angle[i]+PI) * (j+1) + x);
yradOneEighty = (int)round(sin(angle[i]+PI) * (j+1) + y);
valueOneEighty = data[y][x] - data[yradOneEighty][xradOneEighty];
valueOneEighty = valueOneEighty * valueOneEighty * 0.5;
sum_value = sum_value + value + valueOneEighty;
avg_value = sum_value/(2*(j+1));
//Fail safe to ensure there is no nan or inf
if(avg_value == 0) {
if((avg_valueOrtho < 1) && (avg_valueOrtho > 0)) {
avg_value = avg_valueOrtho;
}
else {
avg_value = 1;
}
}
if(avg_valueOrtho == 0) {
avg_valueOrtho = 1;
}
//printf("1(%d,%d) %f %f\n",(j+1),(i+1),variance[j],avg_value);
if(avg_value < variance[j]) {
// printf("2(%d) %f %f\n",j,variance[j],avg_value);
variance[j] = avg_value;
orientation[j] = angle[i];
ortho[j] = avg_valueOrtho;
}
}
}
for(j=0;j<RADIUS;j+=RADSTEP){
anisotropy[y][x][j] = ortho[j]/variance[j];
azimuth[y][x][j] = orientation[j] * 180/PI ;
//printf("%f %f\n",variance[j],anisotropy[y][x][j]);
}
// Writing to files
if (x == (XSIZE - RADIUS - 1)) {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\n");
fprintf(outputAzimuth00,"\n");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\n");
fprintf(outputAzimuth09,"\n");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\n");
fprintf(outputAzimuth49,"\n");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\n");
fprintf(outputAzimuth99,"\n");
}
else {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\t");
fprintf(outputAzimuth00,"\t");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\t");
fprintf(outputAzimuth09,"\t");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\t");
fprintf(outputAzimuth49,"\t");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\t");
fprintf(outputAzimuth99,"\t");
}
}
}
fclose(datTxt);
fclose(inpCheck);
fclose(outputAnisotropy00);
fclose(outputAnisotropy09);
fclose(outputAnisotropy49);
fclose(outputAnisotropy99);
fclose(outputAzimuth00);
fclose(outputAzimuth09);
fclose(outputAzimuth49);
fclose(outputAzimuth99);
//Freeing 3D matrix anisotropy
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(anisotropy[i][j]);
}
free(anisotropy[i]);
}
free(anisotropy);
//Freeing 3D matrix azimuth
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(azimuth[i][j]);
}
free(azimuth[i]);
}
free(azimuth);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <float.h>
#include <limits.h>
#define XSIZE 1201
#define YSIZE 801
#define RADIUS 100
#define RADSTEP 1
#define ANGLESIZE 36
#define PI 3.141592653589793
int main()
{
FILE *datTxt,*outputAnisotropy00,*outputAnisotropy09,*outputAnisotropy49,*outputAnisotropy99;
FILE *outputAzimuth00,*outputAzimuth09,*outputAzimuth49,*outputAzimuth99;
int data[YSIZE][XSIZE];
FILE * inpCheck;
inpCheck = fopen("inpCheck.txt","w");
if(inpCheck == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
//1200 ints in a row which are max of 5 digits
//with a space in the front and the back and space
//between each number
char line[1200 * 5 +2+1200];
memset(line, '\0', sizeof(line));
char *startPtr,*endPtr;
datTxt = fopen("dat.txt","r");
if(datTxt == NULL) {
perror("Cannot open dat.txt file");
return (-1);
}
outputAnisotropy00 = fopen("outputDataAni00.txt","w");
outputAnisotropy09 = fopen("outputDataAni09.txt","w");
outputAnisotropy49 = fopen("outputDataAni49.txt","w");
outputAnisotropy99 = fopen("outputDataAni99.txt","w");
if((outputAnisotropy00 == NULL)||(outputAnisotropy09 == NULL)||(outputAnisotropy49 == NULL)||(outputAnisotropy99 == NULL)) {
perror("Cannot open Anisotropy file");
return (-1);
}
outputAzimuth00 = fopen("outputDataAzi00.txt","w");
outputAzimuth09 = fopen("outputDataAzi09.txt","w");
outputAzimuth49 = fopen("outputDataAzi49.txt","w");
outputAzimuth99 = fopen("outputDataAzi99.txt","w");
if((outputAzimuth00 == NULL)||(outputAzimuth09 == NULL)||(outputAzimuth49 == NULL)||(outputAzimuth99 == NULL)) {
perror("Cannot open Azimuth file");
return (-1);
}
int i,j,Value;
j = 0;
char tempVal[5];
memset(tempVal,'\0',sizeof(tempVal));
while(fgets(line,1200 *5 + 2 + 1200,datTxt)!=NULL) {
startPtr = line;
for(i=0;i<XSIZE;i++) {
Value = 0;
memset(tempVal,'\0',sizeof(tempVal));
if(i != (XSIZE - 1)) {
endPtr = strchr(startPtr,' ');
strncpy(tempVal,startPtr,endPtr-startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d ",Value);
endPtr = endPtr + 1;
startPtr = endPtr;
}
else if(i == (XSIZE - 1)){
strcpy(tempVal,startPtr);
Value = atoi(tempVal);
data[j][i] = Value;
fprintf(inpCheck,"%d\n",Value);
}
}
j++;
}
//Fine
float angle[ANGLESIZE];
for(int i=0;i<ANGLESIZE;i++) {
angle[i] = i * 5 * PI/180;
}
//Initializing 3D matrix anisotropy
float*** anisotropy;
anisotropy = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
anisotropy[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
anisotropy[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Initializing 3D matrix anzimuth
float*** azimuth;
azimuth = (float***)malloc(YSIZE * sizeof(float**));
for(i = 0;i<YSIZE;i++) {
azimuth[i] = (float**)malloc(XSIZE * sizeof(float *));
for(j = 0; j<XSIZE;j++) {
azimuth[i][j] = (float*)malloc(RADIUS * sizeof(float));
}
}
//Actual computation
int xrad,yrad,x,y,xradOrtho,yradOrtho,xradOneEighty,yradOneEighty,valueOneEighty;
float variance[100];
float orientation[100];
float ortho[100];
float value,sum_value,avg_value;
float valueOrtho,sum_valueOrtho,avg_valueOrtho;
sum_value = 0;
avg_value = 0;
sum_valueOrtho = 0;
avg_valueOrtho = 0;
//y = 0;
for(y=0;y<YSIZE;y++) {
for(x = 0;x<XSIZE;x++) {
/*for(x = 0;x<XSIZE+1;x++) {
if(x==XSIZE) {
y++;
if(y==YSIZE){
x = XSIZE;
continue;
}
x=0;
continue;
}
*/
if((y>(YSIZE - RADIUS - 1))||(y<(RADIUS + 1))) continue;
if((x>(XSIZE - RADIUS - 1))||(x<(RADIUS + 1))) continue;
for(i=0;i<100;i++){
variance[i] = FLT_MAX;
ortho[i] = FLT_MAX;
}
//Flipped
for(i=0;i<ANGLESIZE;i++) {
sum_value = 0;
sum_valueOrtho = 0;
for(j = 0;j<RADIUS;j+=RADSTEP) {
xrad = (int)round(cos(angle[i]) * (j+1) + x);
yrad = (int)round(sin(angle[i]) * (j+1) + y);
value = data[y][x] - data[yrad][xrad];
value = value * value * 0.5;
//sum_value = sum_value + value;
//avg_value = sum_value/(j+1);
//Ortho computation
xradOrtho = (int)round(cos(angle[i]+PI/2) * (j+1) + x);
yradOrtho = (int)round(sin(angle[i]+PI/2) * (j+1) + y);
valueOrtho = data[y][x] - data[yradOrtho][xradOrtho];
valueOrtho = valueOrtho * valueOrtho *0.5;
sum_valueOrtho = sum_valueOrtho + valueOrtho;
avg_valueOrtho = sum_valueOrtho/(j+1);
//One eighty angle computation
xradOneEighty = (int)round(cos(angle[i]+PI) * (j+1) + x);
yradOneEighty = (int)round(sin(angle[i]+PI) * (j+1) + y);
valueOneEighty = data[y][x] - data[yradOneEighty][xradOneEighty];
valueOneEighty = valueOneEighty * valueOneEighty * 0.5;
sum_value = sum_value + value + valueOneEighty;
avg_value = sum_value/(2*(j+1));
//Fail safe to ensure there is no nan or inf
if(avg_value == 0) {
if((avg_valueOrtho < 1) && (avg_valueOrtho > 0)) {
avg_value = avg_valueOrtho;
}
else {
avg_value = 1;
}
}
if(avg_valueOrtho == 0) {
avg_valueOrtho = 1;
}
//printf("1(%d,%d) %f %f\n",(j+1),(i+1),variance[j],avg_value);
if(avg_value < variance[j]) {
// printf("2(%d) %f %f\n",j,variance[j],avg_value);
variance[j] = avg_value;
orientation[j] = angle[i];
ortho[j] = avg_valueOrtho;
}
}
}
for(j=0;j<RADIUS;j+=RADSTEP){
anisotropy[y][x][j] = ortho[j]/variance[j];
azimuth[y][x][j] = orientation[j] * 180/PI ;
//printf("%f %f\n",variance[j],anisotropy[y][x][j]);
}
// Writing to files
if (x == (XSIZE - RADIUS - 1)) {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\n");
fprintf(outputAzimuth00,"\n");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\n");
fprintf(outputAzimuth09,"\n");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\n");
fprintf(outputAzimuth49,"\n");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\n");
fprintf(outputAzimuth99,"\n");
}
else {
fprintf(outputAnisotropy00,"%f",anisotropy[y][x][0]);
fprintf(outputAzimuth00,"%f",azimuth[y][x][0]);
fprintf(outputAnisotropy00,"\t");
fprintf(outputAzimuth00,"\t");
fprintf(outputAnisotropy09,"%f",anisotropy[y][x][9]);
fprintf(outputAzimuth09,"%f",azimuth[y][x][9]);
fprintf(outputAnisotropy09,"\t");
fprintf(outputAzimuth09,"\t");
fprintf(outputAnisotropy49,"%f",anisotropy[y][x][49]);
fprintf(outputAzimuth49,"%f",azimuth[y][x][49]);
fprintf(outputAnisotropy49,"\t");
fprintf(outputAzimuth49,"\t");
fprintf(outputAnisotropy99,"%f",anisotropy[y][x][99]);
fprintf(outputAzimuth99,"%f",azimuth[y][x][99]);
fprintf(outputAnisotropy99,"\t");
fprintf(outputAzimuth99,"\t");
}
}
}
fclose(datTxt);
fclose(inpCheck);
fclose(outputAnisotropy00);
fclose(outputAnisotropy09);
fclose(outputAnisotropy49);
fclose(outputAnisotropy99);
fclose(outputAzimuth00);
fclose(outputAzimuth09);
fclose(outputAzimuth49);
fclose(outputAzimuth99);
//Freeing 3D matrix anisotropy
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(anisotropy[i][j]);
}
free(anisotropy[i]);
}
free(anisotropy);
//Freeing 3D matrix azimuth
for(i = 0;i<YSIZE;i++) {
for(j=0;j<XSIZE;j++) {
free(azimuth[i][j]);
}
free(azimuth[i]);
}
free(azimuth);
return 0;
} | .text
.file "topographic_anisotropy_NewMethod.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI0_1:
.quad 0x4066800000000000 # double 180
.LCPI0_2:
.quad 0x3ff921fb54442d18 # double 1.5707963267948966
.LCPI0_4:
.quad 0x3fe0000000000000 # double 0.5
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI0_3:
.long 0x3f000000 # float 0.5
.LCPI0_5:
.long 0x3f800000 # float 1
.LCPI0_6:
.long 0x43340000 # float 180
.LCPI0_7:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $3856808, %rsp # imm = 0x3AD9A8
.cfi_def_cfa_offset 3856864
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 112(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB0_2
# %bb.1:
leaq 1584(%rsp), %rdi
movl $7202, %edx # imm = 0x1C22
xorl %esi, %esi
callq memset@PLT
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, 56(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB0_2
# %bb.4:
movl $.L.str.5, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.6, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 104(%rsp) # 8-byte Spill
movl $.L.str.7, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 96(%rsp) # 8-byte Spill
movl $.L.str.8, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 88(%rsp) # 8-byte Spill
movq %rbx, 160(%rsp) # 8-byte Spill
testq %rbx, %rbx
je .LBB0_8
# %bb.5:
cmpq $0, 104(%rsp) # 8-byte Folded Reload
je .LBB0_8
# %bb.6:
cmpq $0, 96(%rsp) # 8-byte Folded Reload
je .LBB0_8
# %bb.7:
cmpq $0, 88(%rsp) # 8-byte Folded Reload
je .LBB0_8
# %bb.9:
movl $.L.str.10, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.11, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 80(%rsp) # 8-byte Spill
movl $.L.str.12, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 72(%rsp) # 8-byte Spill
movl $.L.str.13, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 64(%rsp) # 8-byte Spill
movq %rbx, 152(%rsp) # 8-byte Spill
testq %rbx, %rbx
je .LBB0_13
# %bb.10:
cmpq $0, 80(%rsp) # 8-byte Folded Reload
je .LBB0_13
# %bb.11:
cmpq $0, 72(%rsp) # 8-byte Folded Reload
je .LBB0_13
# %bb.12:
cmpq $0, 64(%rsp) # 8-byte Folded Reload
je .LBB0_13
# %bb.14:
movb $0, 20(%rsp)
movl $0, 16(%rsp)
leaq 1584(%rsp), %r14
movq %r14, %rdi
movl $7202, %esi # imm = 0x1C22
movq 56(%rsp), %rdx # 8-byte Reload
callq fgets
testq %rax, %rax
je .LBB0_22
# %bb.15: # %.preheader324.preheader
leaq 8800(%rsp), %rbx
leaq 16(%rsp), %r13
xorl %r15d, %r15d
jmp .LBB0_16
.p2align 4, 0x90
.LBB0_21: # in Loop: Header=BB0_16 Depth=1
movq 32(%rsp), %r15 # 8-byte Reload
incq %r15
leaq 1584(%rsp), %r14
movq %r14, %rdi
movl $7202, %esi # imm = 0x1C22
movq 56(%rsp), %rdx # 8-byte Reload
callq fgets
addq $4804, %rbx # imm = 0x12C4
testq %rax, %rax
je .LBB0_22
.LBB0_16: # %.preheader324
# =>This Loop Header: Depth=1
# Child Loop BB0_17 Depth 2
movq %r15, 32(%rsp) # 8-byte Spill
imulq $4804, %r15, %rax # imm = 0x12C4
leaq (%rsp,%rax), %r12
addq $13600, %r12 # imm = 0x3520
movq $-1201, %r15 # imm = 0xFB4F
jmp .LBB0_17
.p2align 4, 0x90
.LBB0_19: # in Loop: Header=BB0_17 Depth=2
movq %r13, %rdi
movq %r14, %rsi
callq strcpy
movq %r13, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, (%r12)
movl $.L.str.16, %esi
movq 112(%rsp), %rdi # 8-byte Reload
movl %eax, %edx
xorl %eax, %eax
callq fprintf
incq %r15
je .LBB0_21
.LBB0_17: # Parent Loop BB0_16 Depth=1
# => This Inner Loop Header: Depth=2
movb $0, 20(%rsp)
movl $0, 16(%rsp)
cmpq $-1, %r15
je .LBB0_19
# %bb.18: # in Loop: Header=BB0_17 Depth=2
movq %r14, %rdi
movl $32, %esi
callq strchr
movq %rax, %rbp
movq %rax, %rdx
subq %r14, %rdx
movq %r13, %rdi
movq %r14, %rsi
callq strncpy
movq %r13, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 4804(%rbx,%r15,4)
movl $.L.str.15, %esi
movq 112(%rsp), %rdi # 8-byte Reload
movl %eax, %edx
xorl %eax, %eax
callq fprintf
incq %rbp
movq %rbp, %r14
incq %r15
jne .LBB0_17
jmp .LBB0_21
.LBB0_22: # %._crit_edge
leaq 240(%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB0_23: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
mulsd .LCPI0_0(%rip), %xmm1
divsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rax)
addq $5, %rcx
addq $4, %rax
cmpq $180, %rcx
jne .LBB0_23
# %bb.24:
movl $6408, %edi # imm = 0x1908
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_25: # =>This Loop Header: Depth=1
# Child Loop BB0_26 Depth 2
movl $9608, %edi # imm = 0x2588
callq malloc
movq %rax, %r14
movq 24(%rsp), %rax # 8-byte Reload
movq %r14, (%rax,%rbx,8)
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_26: # Parent Loop BB0_25 Depth=1
# => This Inner Loop Header: Depth=2
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, (%r14,%r15,8)
incq %r15
cmpq $1201, %r15 # imm = 0x4B1
jne .LBB0_26
# %bb.27: # in Loop: Header=BB0_25 Depth=1
incq %rbx
cmpq $801, %rbx # imm = 0x321
jne .LBB0_25
# %bb.28:
movl $6408, %edi # imm = 0x1908
callq malloc
movq %rax, %r12
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_29: # =>This Loop Header: Depth=1
# Child Loop BB0_30 Depth 2
movl $9608, %edi # imm = 0x2588
callq malloc
movq %rax, %r14
movq %rax, (%r12,%rbx,8)
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_30: # Parent Loop BB0_29 Depth=1
# => This Inner Loop Header: Depth=2
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, (%r14,%r15,8)
incq %r15
cmpq $1201, %r15 # imm = 0x4B1
jne .LBB0_30
# %bb.31: # in Loop: Header=BB0_29 Depth=1
incq %rbx
cmpq $801, %rbx # imm = 0x321
jne .LBB0_29
# %bb.32:
xorl %r13d, %r13d
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
movq %r12, 120(%rsp) # 8-byte Spill
jmp .LBB0_33
.p2align 4, 0x90
.LBB0_53: # in Loop: Header=BB0_33 Depth=1
incq %r13
cmpq $801, %r13 # imm = 0x321
je .LBB0_54
.LBB0_33: # %.preheader323
# =>This Loop Header: Depth=1
# Child Loop BB0_34 Depth 2
# Child Loop BB0_37 Depth 3
# Child Loop BB0_39 Depth 3
# Child Loop BB0_40 Depth 4
# Child Loop BB0_47 Depth 3
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
movss %xmm0, 140(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
movsd %xmm0, 176(%rsp) # 8-byte Spill
leal -701(%r13), %ecx
imulq $4804, %r13, %rax # imm = 0x12C4
addq %rsp, %rax
addq $8800, %rax # imm = 0x2260
movq %rax, 232(%rsp) # 8-byte Spill
xorl %edx, %edx
movq %r13, 128(%rsp) # 8-byte Spill
movl %ecx, 136(%rsp) # 4-byte Spill
jmp .LBB0_34
.p2align 4, 0x90
.LBB0_50: # in Loop: Header=BB0_34 Depth=2
leaq (,%rbx,8), %r15
addq (%rsi,%rdi,8), %r15
movl $9, %r14d
.LBB0_51: # %.sink.split
# in Loop: Header=BB0_34 Depth=2
movq (%r15), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 160(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movb $1, %al
callq fprintf
movq 120(%rsp), %rax # 8-byte Reload
movq 128(%rsp), %rcx # 8-byte Reload
movq (%rax,%rcx,8), %r13
movq (%r13,%rbx,8), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 152(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movb $1, %al
callq fprintf
movl %r14d, %edi
movq %r12, %rsi
callq fputc@PLT
movl %r14d, %edi
movq %rbp, %rsi
callq fputc@PLT
movq (%r15), %rax
movss 36(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 104(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movb $1, %al
callq fprintf
movq (%r13,%rbx,8), %rax
movss 36(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 80(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movb $1, %al
callq fprintf
movl %r14d, %edi
movq %r12, %rsi
callq fputc@PLT
movl %r14d, %edi
movq %rbp, %rsi
callq fputc@PLT
movq (%r15), %rax
movss 196(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 96(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movb $1, %al
callq fprintf
movq (%r13,%rbx,8), %rax
movss 196(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 72(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movb $1, %al
callq fprintf
movl %r14d, %edi
movq %r12, %rsi
callq fputc@PLT
movl %r14d, %edi
movq %rbp, %rsi
callq fputc@PLT
movq (%r15), %rax
movss 396(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 88(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movb $1, %al
callq fprintf
movq (%r13,%rbx,8), %rax
movq 128(%rsp), %r13 # 8-byte Reload
movq 120(%rsp), %r12 # 8-byte Reload
movss 396(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 64(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movb $1, %al
callq fprintf
movl %r14d, %edi
movq %r15, %rsi
callq fputc@PLT
movl %r14d, %edi
movq %rbx, %rsi
callq fputc@PLT
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
movl 136(%rsp), %ecx # 4-byte Reload
movq 168(%rsp), %rdx # 8-byte Reload
.LBB0_52: # in Loop: Header=BB0_34 Depth=2
incq %rdx
cmpq $1201, %rdx # imm = 0x4B1
je .LBB0_53
.LBB0_34: # Parent Loop BB0_33 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_37 Depth 3
# Child Loop BB0_39 Depth 3
# Child Loop BB0_40 Depth 4
# Child Loop BB0_47 Depth 3
cmpl $-600, %ecx # imm = 0xFDA8
jb .LBB0_52
# %bb.35: # in Loop: Header=BB0_34 Depth=2
leal -1101(%rdx), %eax
cmpl $-1000, %eax # imm = 0xFC18
jb .LBB0_52
# %bb.36: # %.preheader322.preheader
# in Loop: Header=BB0_34 Depth=2
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_37: # %.preheader322
# Parent Loop BB0_33 Depth=1
# Parent Loop BB0_34 Depth=2
# => This Inner Loop Header: Depth=3
movl $2139095039, 384(%rsp,%rax,4) # imm = 0x7F7FFFFF
movl $2139095039, 784(%rsp,%rax,4) # imm = 0x7F7FFFFF
incq %rax
cmpq $100, %rax
jne .LBB0_37
# %bb.38: # %.preheader321
# in Loop: Header=BB0_34 Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, 144(%rsp) # 4-byte Spill
movq 232(%rsp), %rax # 8-byte Reload
movl (%rax,%rdx,4), %r14d
movq %rdx, 168(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
movsd %xmm0, 184(%rsp) # 8-byte Spill
xorl %r13d, %r13d
jmp .LBB0_39
.p2align 4, 0x90
.LBB0_45: # in Loop: Header=BB0_39 Depth=3
incq %r13
cmpq $36, %r13
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
je .LBB0_46
.LBB0_39: # %.preheader319
# Parent Loop BB0_33 Depth=1
# Parent Loop BB0_34 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB0_40 Depth 4
movss 240(%rsp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movaps %xmm0, %xmm2
addsd .LCPI0_2(%rip), %xmm2
movsd %xmm2, 192(%rsp) # 8-byte Spill
addsd %xmm1, %xmm0
movsd %xmm0, 200(%rsp) # 8-byte Spill
xorpd %xmm0, %xmm0
movl $2, %ebp
xorl %r15d, %r15d
xorps %xmm4, %xmm4
jmp .LBB0_40
.p2align 4, 0x90
.LBB0_44: # in Loop: Header=BB0_40 Depth=4
addl $2, %ebp
movq %rbx, %r15
cmpq $100, %rbx
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
je .LBB0_45
.LBB0_40: # Parent Loop BB0_33 Depth=1
# Parent Loop BB0_34 Depth=2
# Parent Loop BB0_39 Depth=3
# => This Inner Loop Header: Depth=4
movaps %xmm4, 32(%rsp) # 16-byte Spill
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq cosf
leaq 1(%r15), %rbx
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
movss %xmm1, 208(%rsp) # 4-byte Spill
mulss %xmm1, %xmm0
addss 144(%rsp), %xmm0 # 4-byte Folded Reload
callq roundf@PLT
cvttss2si %xmm0, %r12d
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sinf
mulss 208(%rsp), %xmm0 # 4-byte Folded Reload
addss 140(%rsp), %xmm0 # 4-byte Folded Reload
callq roundf@PLT
cvttss2si %xmm0, %eax
cltq
movslq %r12d, %rcx
imulq $4804, %rax, %rax # imm = 0x12C4
addq %rsp, %rax
addq $8800, %rax # imm = 0x2260
movl %r14d, %edx
subl (%rax,%rcx,4), %edx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
mulss %xmm1, %xmm1
movss .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss 32(%rsp), %xmm1 # 16-byte Folded Reload
movss %xmm1, 148(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
xorps %xmm1, %xmm1
cvtsi2sd %ebx, %xmm1
movsd %xmm1, 32(%rsp) # 8-byte Spill
mulsd %xmm1, %xmm0
addsd 184(%rsp), %xmm0 # 8-byte Folded Reload
callq round@PLT
cvttsd2si %xmm0, %r12d
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 32(%rsp), %xmm0 # 8-byte Folded Reload
addsd 176(%rsp), %xmm0 # 8-byte Folded Reload
callq round@PLT
cvttsd2si %xmm0, %eax
cltq
movslq %r12d, %rcx
imulq $4804, %rax, %rax # imm = 0x12C4
addq %rsp, %rax
addq $8800, %rax # imm = 0x2260
movl %r14d, %edx
subl (%rax,%rcx,4), %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
mulss %xmm0, %xmm0
mulss .LCPI0_3(%rip), %xmm0
addss 8(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 8(%rsp) # 4-byte Spill
divss 208(%rsp), %xmm0 # 4-byte Folded Reload
movaps %xmm0, 208(%rsp) # 16-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 32(%rsp), %xmm0 # 8-byte Folded Reload
addsd 184(%rsp), %xmm0 # 8-byte Folded Reload
callq round@PLT
cvttsd2si %xmm0, %r12d
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 32(%rsp), %xmm0 # 8-byte Folded Reload
addsd 176(%rsp), %xmm0 # 8-byte Folded Reload
callq round@PLT
movaps 208(%rsp), %xmm5 # 16-byte Reload
cvttsd2si %xmm0, %eax
cltq
movslq %r12d, %rcx
imulq $4804, %rax, %rax # imm = 0x12C4
addq %rsp, %rax
addq $8800, %rax # imm = 0x2260
movl %r14d, %edx
subl (%rax,%rcx,4), %edx
imull %edx, %edx
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
mulsd .LCPI0_4(%rip), %xmm0
cvttpd2dq %xmm0, %xmm0
cvtdq2ps %xmm0, %xmm4
addss 148(%rsp), %xmm4 # 4-byte Folded Reload
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
movaps %xmm4, %xmm0
divss %xmm1, %xmm0
ucomiss .LCPI0_7(%rip), %xmm0
jne .LBB0_42
jp .LBB0_42
# %bb.41: # in Loop: Header=BB0_40 Depth=4
xorps %xmm1, %xmm1
cmpltss %xmm5, %xmm1
movaps %xmm1, %xmm0
andps %xmm5, %xmm0
movss .LCPI0_5(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
andnps %xmm2, %xmm1
orps %xmm0, %xmm1
movaps %xmm5, %xmm0
cmpltss %xmm2, %xmm0
andps %xmm0, %xmm1
andnps %xmm2, %xmm0
orps %xmm1, %xmm0
.LBB0_42: # in Loop: Header=BB0_40 Depth=4
movss 384(%rsp,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB0_44
# %bb.43: # in Loop: Header=BB0_40 Depth=4
movaps %xmm5, %xmm1
cmpeqss .LCPI0_7(%rip), %xmm1
movaps %xmm1, %xmm2
movss .LCPI0_5(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
andps %xmm3, %xmm2
andnps %xmm5, %xmm1
orps %xmm2, %xmm1
movss %xmm0, 384(%rsp,%r15,4)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 1184(%rsp,%r15,4)
movss %xmm1, 784(%rsp,%r15,4)
jmp .LBB0_44
.p2align 4, 0x90
.LBB0_46: # %.preheader320
# in Loop: Header=BB0_34 Depth=2
movq 24(%rsp), %rsi # 8-byte Reload
movq 128(%rsp), %rdi # 8-byte Reload
movq (%rsi,%rdi,8), %rax
movq 168(%rsp), %rbx # 8-byte Reload
movq (%rax,%rbx,8), %rax
movq 120(%rsp), %rcx # 8-byte Reload
movq (%rcx,%rdi,8), %rcx
movq (%rcx,%rbx,8), %rcx
xorl %edx, %edx
movss .LCPI0_6(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_47: # Parent Loop BB0_33 Depth=1
# Parent Loop BB0_34 Depth=2
# => This Inner Loop Header: Depth=3
movss 784(%rsp,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 384(%rsp,%rdx,4), %xmm0
movss %xmm0, (%rax,%rdx,4)
movss 1184(%rsp,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rcx,%rdx,4)
incq %rdx
cmpq $100, %rdx
jne .LBB0_47
# %bb.48: # in Loop: Header=BB0_34 Depth=2
cmpq $1100, %rbx # imm = 0x44C
jne .LBB0_50
# %bb.49: # in Loop: Header=BB0_34 Depth=2
movq (%rsi,%rdi,8), %r15
movl $8800, %eax # imm = 0x2260
addq %rax, %r15
movl $10, %r14d
movl $1100, %ebx # imm = 0x44C
jmp .LBB0_51
.LBB0_54:
movq 56(%rsp), %rdi # 8-byte Reload
callq fclose
movq 112(%rsp), %rdi # 8-byte Reload
callq fclose
movq 160(%rsp), %rdi # 8-byte Reload
callq fclose
movq 104(%rsp), %rdi # 8-byte Reload
callq fclose
movq 96(%rsp), %rdi # 8-byte Reload
callq fclose
movq 88(%rsp), %rdi # 8-byte Reload
callq fclose
movq 152(%rsp), %rdi # 8-byte Reload
callq fclose
movq 80(%rsp), %rdi # 8-byte Reload
callq fclose
movq 72(%rsp), %rdi # 8-byte Reload
callq fclose
movq 64(%rsp), %rdi # 8-byte Reload
callq fclose
xorl %ebx, %ebx
movq 24(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB0_55: # %.preheader318
# =>This Loop Header: Depth=1
# Child Loop BB0_56 Depth 2
movq (%r14,%rbx,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_56: # Parent Loop BB0_55 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%r15,8), %rdi
callq free
incq %r15
cmpq $1201, %r15 # imm = 0x4B1
jne .LBB0_56
# %bb.57: # in Loop: Header=BB0_55 Depth=1
movq 24(%rsp), %r14 # 8-byte Reload
movq (%r14,%rbx,8), %rdi
callq free
incq %rbx
cmpq $801, %rbx # imm = 0x321
jne .LBB0_55
# %bb.58:
movq %r14, %rdi
callq free
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_59: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_60 Depth 2
movq (%r12,%rbx,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_60: # Parent Loop BB0_59 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%r15,8), %rdi
callq free
incq %r15
cmpq $1201, %r15 # imm = 0x4B1
jne .LBB0_60
# %bb.61: # in Loop: Header=BB0_59 Depth=1
movq (%r12,%rbx,8), %rdi
callq free
incq %rbx
cmpq $801, %rbx # imm = 0x321
jne .LBB0_59
# %bb.62:
movq %r12, %rdi
callq free
xorl %eax, %eax
jmp .LBB0_63
.LBB0_2:
movl $.L.str.2, %edi
jmp .LBB0_3
.LBB0_8:
movl $.L.str.9, %edi
jmp .LBB0_3
.LBB0_13:
movl $.L.str.14, %edi
.LBB0_3:
callq perror
movl $-1, %eax
.LBB0_63:
addq $3856808, %rsp # imm = 0x3AD9A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "inpCheck.txt"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cannot open dat.txt file"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "dat.txt"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "outputDataAni00.txt"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "outputDataAni09.txt"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "outputDataAni49.txt"
.size .L.str.7, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "outputDataAni99.txt"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Cannot open Anisotropy file"
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "outputDataAzi00.txt"
.size .L.str.10, 20
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "outputDataAzi09.txt"
.size .L.str.11, 20
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "outputDataAzi49.txt"
.size .L.str.12, 20
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "outputDataAzi99.txt"
.size .L.str.13, 20
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Cannot open Azimuth file"
.size .L.str.14, 25
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "%d "
.size .L.str.15, 4
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "%d\n"
.size .L.str.16, 4
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "%f"
.size .L.str.17, 3
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005c739_00000000-6_topographic_anisotropy_NewMethod.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "w"
.LC3:
.string "inpCheck.txt"
.LC4:
.string "Cannot open dat.txt file"
.LC5:
.string "r"
.LC6:
.string "dat.txt"
.LC7:
.string "outputDataAni00.txt"
.LC8:
.string "outputDataAni09.txt"
.LC9:
.string "outputDataAni49.txt"
.LC10:
.string "outputDataAni99.txt"
.LC11:
.string "Cannot open Anisotropy file"
.LC12:
.string "outputDataAzi00.txt"
.LC13:
.string "outputDataAzi09.txt"
.LC14:
.string "outputDataAzi49.txt"
.LC15:
.string "outputDataAzi99.txt"
.LC16:
.string "Cannot open Azimuth file"
.LC17:
.string "%d "
.LC18:
.string "%d\n"
.LC26:
.string "%f"
.LC27:
.string "\n"
.LC28:
.string "\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -3854336(%rsp), %r11
.cfi_def_cfa 11, 3854392
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2552, %rsp
.cfi_def_cfa_offset 3856944
movq %fs:40, %rax
movq %rax, 3856872(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L68
movq %rax, %r15
leaq 3849664(%rsp), %rdx
movl $900, %ecx
movl $0, %eax
movq %rdx, %rdi
rep stosq
movw $0, (%rdi)
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, 176(%rsp)
testq %rax, %rax
je .L69
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, %r14
movq %rax, 112(%rsp)
movq %rbx, %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %rax, 120(%rsp)
movq %rbx, %rsi
leaq .LC9(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movq %rax, 128(%rsp)
movq %rbx, %rsi
leaq .LC10(%rip), %rdi
call fopen@PLT
movq %rax, 160(%rsp)
testq %r14, %r14
je .L7
testq %rbp, %rbp
je .L7
testq %r13, %r13
je .L7
testq %rax, %rax
je .L7
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
leaq .LC12(%rip), %rdi
call fopen@PLT
movq %rax, %r14
movq %rax, 136(%rsp)
movq %rbx, %rsi
leaq .LC13(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %rax, 144(%rsp)
movq %rbx, %rsi
leaq .LC14(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movq %rax, 152(%rsp)
movq %rbx, %rsi
leaq .LC15(%rip), %rdi
call fopen@PLT
movq %rax, 168(%rsp)
testq %r14, %r14
je .L10
testq %rbp, %rbp
je .L10
testq %r13, %r13
je .L10
testq %rax, %rax
je .L10
movl $0, 3849659(%rsp)
movb $0, 3849663(%rsp)
leaq 6448(%rsp), %rbx
leaq 3849664(%rsp), %r14
jmp .L13
.L68:
leaq .LC4(%rip), %rdi
call perror@PLT
movl $-1, %eax
jmp .L3
.L69:
leaq .LC4(%rip), %rdi
call perror@PLT
movl $-1, %eax
jmp .L3
.L7:
leaq .LC11(%rip), %rdi
call perror@PLT
movl $-1, %eax
jmp .L3
.L10:
leaq .LC16(%rip), %rdi
call perror@PLT
movl $-1, %eax
jmp .L3
.L70:
movl $32, %esi
movq %r12, %rdi
call strchr@PLT
movq %rax, %rdx
movq %rax, (%rsp)
subq %r12, %rdx
leaq 3849659(%rsp), %r13
movl $5, %ecx
movq %r12, %rsi
movq %r13, %rdi
call __strncpy_chk@PLT
movl $10, %edx
movl $0, %esi
movq %r13, %rdi
call __isoc23_strtol@PLT
movl %eax, %ecx
movl %eax, 0(%rbp)
leaq .LC17(%rip), %rdx
movl $2, %esi
movq %r15, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq (%rsp), %rdx
addq $1, %rdx
movq %rdx, %r12
leaq 4(%rbp), %rax
cmpq %rbx, %rbp
je .L16
movq %rax, %rbp
.L15:
movl $0, 3849659(%rsp)
movb $0, 3849663(%rsp)
cmpq %rbx, %rbp
jne .L70
leaq 3849659(%rsp), %rbp
movl $5, %edx
movq %r12, %rsi
movq %rbp, %rdi
call __strcpy_chk@PLT
movl $10, %edx
movl $0, %esi
movq %rbp, %rdi
call __isoc23_strtol@PLT
movl %eax, %ecx
movl %eax, (%rbx)
leaq .LC18(%rip), %rdx
movl $2, %esi
movq %r15, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L16:
addq $4804, %rbx
.L13:
movq 176(%rsp), %rcx
movl $7202, %edx
movl $7202, %esi
movq %r14, %rdi
call __fgets_chk@PLT
testq %rax, %rax
je .L71
leaq -4800(%rbx), %rbp
movq %r14, %r12
jmp .L15
.L71:
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
movq %rax, %rdx
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC19(%rip), %xmm0
divsd .LC20(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rdx)
addl $5, %eax
addq $4, %rdx
cmpl $180, %eax
jne .L18
movl $6408, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, 184(%rsp)
movq %rax, %r13
leaq 6408(%rax), %r14
.L20:
movl $9608, %edi
call malloc@PLT
movq %rax, (%r12)
movq %rax, %rbx
leaq 9608(%rax), %rbp
.L19:
movl $400, %edi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbx, %rbp
jne .L19
addq $8, %r12
cmpq %r14, %r12
jne .L20
movl $6408, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, 192(%rsp)
movq %rax, %rbp
leaq 6408(%rax), %rax
movq %rax, 200(%rsp)
.L22:
movl $9608, %edi
call malloc@PLT
movq %rax, (%r12)
movq %rax, %rbx
addq $9608, %rax
movq %rax, (%rsp)
.L21:
movl $400, %edi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbx, (%rsp)
jne .L21
addq $8, %r12
cmpq %r12, 200(%rsp)
jne .L22
leaq 1648(%rsp), %rcx
movl $0, %edx
jmp .L23
.L27:
movd %ebp, %xmm4
pxor %xmm5, %xmm5
ucomiss %xmm5, %xmm4
jp .L29
cmove %r13d, %ebp
.L29:
movss 444(%rsp,%rbx,4), %xmm1
comiss %xmm0, %xmm1
jbe .L32
movss %xmm0, 444(%rsp,%rbx,4)
movl %r14d, 844(%rsp,%rbx,4)
movl %ebp, 1244(%rsp,%rbx,4)
.L32:
addq $1, %rbx
cmpq $101, %rbx
je .L72
.L34:
pxor %xmm5, %xmm5
cvtsi2ssl %ebx, %xmm5
movss %xmm5, 8(%rsp)
movaps %xmm5, %xmm0
mulss 84(%rsp), %xmm0
addss 92(%rsp), %xmm0
call roundf@PLT
movss %xmm0, (%rsp)
movss 8(%rsp), %xmm6
mulss 88(%rsp), %xmm6
movaps %xmm6, %xmm0
addss 104(%rsp), %xmm0
call roundf@PLT
cvttss2sil (%rsp), %edx
movslq %edx, %rdx
cvttss2sil %xmm0, %eax
cltq
imulq $1201, %rax, %rax
addq %rdx, %rax
movl %r12d, %ecx
subl 1648(%rsp,%rax,4), %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss %xmm0, %xmm0
movss %xmm0, 80(%rsp)
pxor %xmm3, %xmm3
cvtsi2sdl %ebx, %xmm3
movsd 48(%rsp), %xmm5
movsd %xmm3, (%rsp)
mulsd %xmm3, %xmm5
movapd %xmm5, %xmm0
addsd 16(%rsp), %xmm0
call round@PLT
movsd %xmm0, 40(%rsp)
movsd (%rsp), %xmm4
mulsd 56(%rsp), %xmm4
movapd %xmm4, %xmm0
addsd 24(%rsp), %xmm0
call round@PLT
cvttsd2sil 40(%rsp), %edx
movslq %edx, %rdx
cvttsd2sil %xmm0, %eax
cltq
imulq $1201, %rax, %rax
addq %rdx, %rax
movl %r12d, %esi
subl 1648(%rsp,%rax,4), %esi
pxor %xmm0, %xmm0
cvtsi2ssl %esi, %xmm0
mulss %xmm0, %xmm0
mulss .LC22(%rip), %xmm0
addss 32(%rsp), %xmm0
movaps %xmm0, %xmm7
movss %xmm0, 32(%rsp)
divss 8(%rsp), %xmm7
movd %xmm7, %ebp
movsd (%rsp), %xmm0
mulsd 64(%rsp), %xmm0
addsd 16(%rsp), %xmm0
call round@PLT
movsd %xmm0, 8(%rsp)
movsd (%rsp), %xmm0
mulsd 72(%rsp), %xmm0
addsd 24(%rsp), %xmm0
call round@PLT
cvttsd2sil 8(%rsp), %edx
movslq %edx, %rdx
cvttsd2sil %xmm0, %eax
cltq
imulq $1201, %rax, %rax
addq %rdx, %rax
movl %r12d, %edi
subl 1648(%rsp,%rax,4), %edi
movl %edi, %eax
imull %edi, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd .LC23(%rip), %xmm1
movss .LC22(%rip), %xmm6
mulss 80(%rsp), %xmm6
movaps %xmm6, %xmm0
addss 36(%rsp), %xmm0
cvttsd2sil %xmm1, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movaps %xmm1, %xmm2
addss %xmm0, %xmm2
movss %xmm2, 36(%rsp)
leal (%rbx,%rbx), %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm2
movaps %xmm2, %xmm0
pxor %xmm6, %xmm6
ucomiss %xmm6, %xmm2
jp .L27
movaps %xmm6, %xmm7
jne .L27
movss .LC1(%rip), %xmm3
movd %ebp, %xmm6
movss .LC1(%rip), %xmm0
comiss %xmm6, %xmm3
jbe .L29
movd %ebp, %xmm0
comiss %xmm7, %xmm6
ja .L29
movaps %xmm3, %xmm0
jmp .L27
.L72:
addq $4, %r15
movq 96(%rsp), %rax
cmpq %rax, %r15
je .L35
.L26:
movl (%r15), %r14d
leaq 300(%rsp), %rdi
leaq 296(%rsp), %rsi
movd %r14d, %xmm0
call sincosf@PLT
movss 296(%rsp), %xmm2
movss %xmm2, 84(%rsp)
movss 300(%rsp), %xmm5
movss %xmm5, 88(%rsp)
movd %r14d, %xmm2
pxor %xmm5, %xmm5
cvtss2sd %xmm2, %xmm5
leaq 288(%rsp), %rbx
leaq 280(%rsp), %rbp
movsd .LC24(%rip), %xmm2
movsd %xmm5, (%rsp)
addsd %xmm5, %xmm2
movapd %xmm2, %xmm0
movq %rbp, %rsi
movq %rbx, %rdi
call sincos@PLT
movsd 280(%rsp), %xmm2
movsd %xmm2, 48(%rsp)
movsd 288(%rsp), %xmm2
movsd %xmm2, 56(%rsp)
movsd (%rsp), %xmm0
addsd .LC19(%rip), %xmm0
movq %rbp, %rsi
movq %rbx, %rdi
call sincos@PLT
movsd 280(%rsp), %xmm5
movsd %xmm5, 64(%rsp)
movsd 288(%rsp), %xmm5
movsd %xmm5, 72(%rsp)
movl $1, %ebx
movl $0x00000000, 32(%rsp)
movl $0x00000000, 36(%rsp)
movl 108(%rsp), %ecx
pxor %xmm5, %xmm5
cvtsi2ssl %ecx, %xmm5
movss %xmm5, 92(%rsp)
movl 216(%rsp), %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
movss %xmm2, 104(%rsp)
pxor %xmm5, %xmm5
cvtsi2sdl %ecx, %xmm5
movsd %xmm5, 16(%rsp)
pxor %xmm2, %xmm2
cvtsi2sdl %eax, %xmm2
movsd %xmm2, 24(%rsp)
movl .LC1(%rip), %r13d
jmp .L34
.L35:
movq 264(%rsp), %rbx
movq 272(%rsp), %rbp
movq 184(%rsp), %rax
movq (%rax,%rbp,8), %rcx
movq (%rcx,%rbx,8), %r13
movq 192(%rsp), %rax
movq (%rax,%rbp,8), %r14
movq (%r14,%rbx,8), %r12
movl $0, %eax
leaq 448(%rsp), %rdx
movss .LC25(%rip), %xmm2
movsd .LC19(%rip), %xmm1
.L36:
movss 1248(%rsp,%rax), %xmm0
divss (%rax,%rdx), %xmm0
movss %xmm0, 0(%r13,%rax)
movaps %xmm2, %xmm0
mulss 848(%rsp,%rax), %xmm0
cvtss2sd %xmm0, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L36
cmpl $1100, %ebx
je .L73
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
leaq .LC26(%rip), %r15
movq %r15, %rdx
movl $2, %esi
movq 112(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 136(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq .LC28(%rip), %r14
movq %r14, %rdx
movl $2, %esi
movq 112(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq 136(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%r13), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 120(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%r12), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 144(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq 120(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq 144(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 196(%r13), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 128(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 196(%r12), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 152(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq 128(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq 152(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 396(%r13), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 160(%rsp), %r13
movq %r13, %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 396(%r12), %xmm0
movq %r15, %rdx
movl $2, %esi
movq 168(%rsp), %r15
movq %r15, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r14, %rdx
movl $2, %esi
movq %r15, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L38:
addq $1, %rbx
jmp .L41
.L73:
movq 8800(%rcx), %r15
pxor %xmm0, %xmm0
cvtss2sd (%r15), %xmm0
leaq .LC26(%rip), %r13
movq %r13, %rdx
movl $2, %esi
movq 112(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 8800(%r14), %r14
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 136(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq .LC27(%rip), %r12
movq %r12, %rdx
movl $2, %esi
movq 112(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 136(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%r15), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 120(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%r14), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 144(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 120(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 144(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 196(%r15), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 128(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 196(%r14), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 152(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 128(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 152(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 396(%r15), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 160(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 396(%r14), %xmm0
movq %r13, %rdx
movl $2, %esi
movq 168(%rsp), %r15
movq %r15, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq 160(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r12, %rdx
movl $2, %esi
movq %r15, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L38
.L24:
addq $1, %rbx
cmpq $1201, %rbx
je .L74
.L41:
movl 220(%rsp), %eax
subl $101, %eax
cmpl $599, %eax
ja .L24
leal -101(%rbx), %eax
cmpl $999, %eax
ja .L24
movl $0, %eax
.L25:
movss .LC21(%rip), %xmm5
movss %xmm5, 448(%rsp,%rax)
movss %xmm5, 1248(%rsp,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L25
movl %ebx, 108(%rsp)
movq 208(%rsp), %rax
movl (%rax,%rbx,4), %r12d
movq 224(%rsp), %r15
leaq 144(%r15), %rax
movq %rax, 96(%rsp)
movq %rbx, 264(%rsp)
movq %rbp, 272(%rsp)
jmp .L26
.L74:
movq 232(%rsp), %r13
movq 208(%rsp), %rcx
movq 240(%rsp), %r15
movq %rbp, %rdx
movq 248(%rsp), %rbp
movq 256(%rsp), %r14
addq $1, %rdx
addq $4804, %rcx
cmpq $801, %rdx
je .L40
.L23:
movl %edx, 220(%rsp)
movl %edx, 216(%rsp)
movl $0, %ebx
movq %r13, 232(%rsp)
movq %rcx, 208(%rsp)
movq %r15, 240(%rsp)
movq %rbp, 248(%rsp)
movq %rdx, %rbp
movq %r14, 256(%rsp)
jmp .L41
.L40:
movq 176(%rsp), %rdi
call fclose@PLT
movq %r15, %rdi
call fclose@PLT
movq 112(%rsp), %rdi
call fclose@PLT
movq 120(%rsp), %rdi
call fclose@PLT
movq 128(%rsp), %rdi
call fclose@PLT
movq 160(%rsp), %rdi
call fclose@PLT
movq 136(%rsp), %rdi
call fclose@PLT
movq 144(%rsp), %rdi
call fclose@PLT
movq 152(%rsp), %rdi
call fclose@PLT
movq 168(%rsp), %rdi
call fclose@PLT
.L42:
movl $0, %ebx
.L43:
movq 0(%r13), %r12
movq (%r12,%rbx), %rdi
call free@PLT
addq $8, %rbx
cmpq $9608, %rbx
jne .L43
movq %r12, %rdi
call free@PLT
addq $8, %r13
cmpq %r14, %r13
jne .L42
movq 184(%rsp), %rdi
call free@PLT
.L45:
movl $0, %ebx
.L46:
movq 0(%rbp), %r12
movq (%r12,%rbx), %rdi
call free@PLT
addq $8, %rbx
cmpq $9608, %rbx
jne .L46
movq %r12, %rdi
call free@PLT
addq $8, %rbp
cmpq %rbp, 200(%rsp)
jne .L45
movq 192(%rsp), %rdi
call free@PLT
movl $0, %eax
.L3:
movq 3856872(%rsp), %rdx
subq %fs:40, %rdx
jne .L75
addq $3856888, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC19:
.long 1413754136
.long 1074340347
.align 8
.LC20:
.long 0
.long 1080459264
.section .rodata.cst4
.align 4
.LC21:
.long 2139095039
.align 4
.LC22:
.long 1056964608
.section .rodata.cst8
.align 8
.LC23:
.long 0
.long 1071644672
.align 8
.LC24:
.long 1413754136
.long 1073291771
.section .rodata.cst4
.align 4
.LC25:
.long 1127481344
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "topographic_anisotropy_NewMethod.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI0_1:
.quad 0x4066800000000000 # double 180
.LCPI0_2:
.quad 0x3ff921fb54442d18 # double 1.5707963267948966
.LCPI0_4:
.quad 0x3fe0000000000000 # double 0.5
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI0_3:
.long 0x3f000000 # float 0.5
.LCPI0_5:
.long 0x3f800000 # float 1
.LCPI0_6:
.long 0x43340000 # float 180
.LCPI0_7:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $3856808, %rsp # imm = 0x3AD9A8
.cfi_def_cfa_offset 3856864
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 112(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB0_2
# %bb.1:
leaq 1584(%rsp), %rdi
movl $7202, %edx # imm = 0x1C22
xorl %esi, %esi
callq memset@PLT
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, 56(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB0_2
# %bb.4:
movl $.L.str.5, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.6, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 104(%rsp) # 8-byte Spill
movl $.L.str.7, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 96(%rsp) # 8-byte Spill
movl $.L.str.8, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 88(%rsp) # 8-byte Spill
movq %rbx, 160(%rsp) # 8-byte Spill
testq %rbx, %rbx
je .LBB0_8
# %bb.5:
cmpq $0, 104(%rsp) # 8-byte Folded Reload
je .LBB0_8
# %bb.6:
cmpq $0, 96(%rsp) # 8-byte Folded Reload
je .LBB0_8
# %bb.7:
cmpq $0, 88(%rsp) # 8-byte Folded Reload
je .LBB0_8
# %bb.9:
movl $.L.str.10, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.11, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 80(%rsp) # 8-byte Spill
movl $.L.str.12, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 72(%rsp) # 8-byte Spill
movl $.L.str.13, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 64(%rsp) # 8-byte Spill
movq %rbx, 152(%rsp) # 8-byte Spill
testq %rbx, %rbx
je .LBB0_13
# %bb.10:
cmpq $0, 80(%rsp) # 8-byte Folded Reload
je .LBB0_13
# %bb.11:
cmpq $0, 72(%rsp) # 8-byte Folded Reload
je .LBB0_13
# %bb.12:
cmpq $0, 64(%rsp) # 8-byte Folded Reload
je .LBB0_13
# %bb.14:
movb $0, 20(%rsp)
movl $0, 16(%rsp)
leaq 1584(%rsp), %r14
movq %r14, %rdi
movl $7202, %esi # imm = 0x1C22
movq 56(%rsp), %rdx # 8-byte Reload
callq fgets
testq %rax, %rax
je .LBB0_22
# %bb.15: # %.preheader324.preheader
leaq 8800(%rsp), %rbx
leaq 16(%rsp), %r13
xorl %r15d, %r15d
jmp .LBB0_16
.p2align 4, 0x90
.LBB0_21: # in Loop: Header=BB0_16 Depth=1
movq 32(%rsp), %r15 # 8-byte Reload
incq %r15
leaq 1584(%rsp), %r14
movq %r14, %rdi
movl $7202, %esi # imm = 0x1C22
movq 56(%rsp), %rdx # 8-byte Reload
callq fgets
addq $4804, %rbx # imm = 0x12C4
testq %rax, %rax
je .LBB0_22
.LBB0_16: # %.preheader324
# =>This Loop Header: Depth=1
# Child Loop BB0_17 Depth 2
movq %r15, 32(%rsp) # 8-byte Spill
imulq $4804, %r15, %rax # imm = 0x12C4
leaq (%rsp,%rax), %r12
addq $13600, %r12 # imm = 0x3520
movq $-1201, %r15 # imm = 0xFB4F
jmp .LBB0_17
.p2align 4, 0x90
.LBB0_19: # in Loop: Header=BB0_17 Depth=2
movq %r13, %rdi
movq %r14, %rsi
callq strcpy
movq %r13, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, (%r12)
movl $.L.str.16, %esi
movq 112(%rsp), %rdi # 8-byte Reload
movl %eax, %edx
xorl %eax, %eax
callq fprintf
incq %r15
je .LBB0_21
.LBB0_17: # Parent Loop BB0_16 Depth=1
# => This Inner Loop Header: Depth=2
movb $0, 20(%rsp)
movl $0, 16(%rsp)
cmpq $-1, %r15
je .LBB0_19
# %bb.18: # in Loop: Header=BB0_17 Depth=2
movq %r14, %rdi
movl $32, %esi
callq strchr
movq %rax, %rbp
movq %rax, %rdx
subq %r14, %rdx
movq %r13, %rdi
movq %r14, %rsi
callq strncpy
movq %r13, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 4804(%rbx,%r15,4)
movl $.L.str.15, %esi
movq 112(%rsp), %rdi # 8-byte Reload
movl %eax, %edx
xorl %eax, %eax
callq fprintf
incq %rbp
movq %rbp, %r14
incq %r15
jne .LBB0_17
jmp .LBB0_21
.LBB0_22: # %._crit_edge
leaq 240(%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB0_23: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
mulsd .LCPI0_0(%rip), %xmm1
divsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rax)
addq $5, %rcx
addq $4, %rax
cmpq $180, %rcx
jne .LBB0_23
# %bb.24:
movl $6408, %edi # imm = 0x1908
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_25: # =>This Loop Header: Depth=1
# Child Loop BB0_26 Depth 2
movl $9608, %edi # imm = 0x2588
callq malloc
movq %rax, %r14
movq 24(%rsp), %rax # 8-byte Reload
movq %r14, (%rax,%rbx,8)
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_26: # Parent Loop BB0_25 Depth=1
# => This Inner Loop Header: Depth=2
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, (%r14,%r15,8)
incq %r15
cmpq $1201, %r15 # imm = 0x4B1
jne .LBB0_26
# %bb.27: # in Loop: Header=BB0_25 Depth=1
incq %rbx
cmpq $801, %rbx # imm = 0x321
jne .LBB0_25
# %bb.28:
movl $6408, %edi # imm = 0x1908
callq malloc
movq %rax, %r12
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_29: # =>This Loop Header: Depth=1
# Child Loop BB0_30 Depth 2
movl $9608, %edi # imm = 0x2588
callq malloc
movq %rax, %r14
movq %rax, (%r12,%rbx,8)
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_30: # Parent Loop BB0_29 Depth=1
# => This Inner Loop Header: Depth=2
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, (%r14,%r15,8)
incq %r15
cmpq $1201, %r15 # imm = 0x4B1
jne .LBB0_30
# %bb.31: # in Loop: Header=BB0_29 Depth=1
incq %rbx
cmpq $801, %rbx # imm = 0x321
jne .LBB0_29
# %bb.32:
xorl %r13d, %r13d
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
movq %r12, 120(%rsp) # 8-byte Spill
jmp .LBB0_33
.p2align 4, 0x90
.LBB0_53: # in Loop: Header=BB0_33 Depth=1
incq %r13
cmpq $801, %r13 # imm = 0x321
je .LBB0_54
.LBB0_33: # %.preheader323
# =>This Loop Header: Depth=1
# Child Loop BB0_34 Depth 2
# Child Loop BB0_37 Depth 3
# Child Loop BB0_39 Depth 3
# Child Loop BB0_40 Depth 4
# Child Loop BB0_47 Depth 3
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
movss %xmm0, 140(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
movsd %xmm0, 176(%rsp) # 8-byte Spill
leal -701(%r13), %ecx
imulq $4804, %r13, %rax # imm = 0x12C4
addq %rsp, %rax
addq $8800, %rax # imm = 0x2260
movq %rax, 232(%rsp) # 8-byte Spill
xorl %edx, %edx
movq %r13, 128(%rsp) # 8-byte Spill
movl %ecx, 136(%rsp) # 4-byte Spill
jmp .LBB0_34
.p2align 4, 0x90
.LBB0_50: # in Loop: Header=BB0_34 Depth=2
leaq (,%rbx,8), %r15
addq (%rsi,%rdi,8), %r15
movl $9, %r14d
.LBB0_51: # %.sink.split
# in Loop: Header=BB0_34 Depth=2
movq (%r15), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 160(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movb $1, %al
callq fprintf
movq 120(%rsp), %rax # 8-byte Reload
movq 128(%rsp), %rcx # 8-byte Reload
movq (%rax,%rcx,8), %r13
movq (%r13,%rbx,8), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 152(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movb $1, %al
callq fprintf
movl %r14d, %edi
movq %r12, %rsi
callq fputc@PLT
movl %r14d, %edi
movq %rbp, %rsi
callq fputc@PLT
movq (%r15), %rax
movss 36(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 104(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movb $1, %al
callq fprintf
movq (%r13,%rbx,8), %rax
movss 36(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 80(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movb $1, %al
callq fprintf
movl %r14d, %edi
movq %r12, %rsi
callq fputc@PLT
movl %r14d, %edi
movq %rbp, %rsi
callq fputc@PLT
movq (%r15), %rax
movss 196(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 96(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movb $1, %al
callq fprintf
movq (%r13,%rbx,8), %rax
movss 196(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 72(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movb $1, %al
callq fprintf
movl %r14d, %edi
movq %r12, %rsi
callq fputc@PLT
movl %r14d, %edi
movq %rbp, %rsi
callq fputc@PLT
movq (%r15), %rax
movss 396(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 88(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movb $1, %al
callq fprintf
movq (%r13,%rbx,8), %rax
movq 128(%rsp), %r13 # 8-byte Reload
movq 120(%rsp), %r12 # 8-byte Reload
movss 396(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq 64(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movb $1, %al
callq fprintf
movl %r14d, %edi
movq %r15, %rsi
callq fputc@PLT
movl %r14d, %edi
movq %rbx, %rsi
callq fputc@PLT
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
movl 136(%rsp), %ecx # 4-byte Reload
movq 168(%rsp), %rdx # 8-byte Reload
.LBB0_52: # in Loop: Header=BB0_34 Depth=2
incq %rdx
cmpq $1201, %rdx # imm = 0x4B1
je .LBB0_53
.LBB0_34: # Parent Loop BB0_33 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_37 Depth 3
# Child Loop BB0_39 Depth 3
# Child Loop BB0_40 Depth 4
# Child Loop BB0_47 Depth 3
cmpl $-600, %ecx # imm = 0xFDA8
jb .LBB0_52
# %bb.35: # in Loop: Header=BB0_34 Depth=2
leal -1101(%rdx), %eax
cmpl $-1000, %eax # imm = 0xFC18
jb .LBB0_52
# %bb.36: # %.preheader322.preheader
# in Loop: Header=BB0_34 Depth=2
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_37: # %.preheader322
# Parent Loop BB0_33 Depth=1
# Parent Loop BB0_34 Depth=2
# => This Inner Loop Header: Depth=3
movl $2139095039, 384(%rsp,%rax,4) # imm = 0x7F7FFFFF
movl $2139095039, 784(%rsp,%rax,4) # imm = 0x7F7FFFFF
incq %rax
cmpq $100, %rax
jne .LBB0_37
# %bb.38: # %.preheader321
# in Loop: Header=BB0_34 Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, 144(%rsp) # 4-byte Spill
movq 232(%rsp), %rax # 8-byte Reload
movl (%rax,%rdx,4), %r14d
movq %rdx, 168(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
movsd %xmm0, 184(%rsp) # 8-byte Spill
xorl %r13d, %r13d
jmp .LBB0_39
.p2align 4, 0x90
.LBB0_45: # in Loop: Header=BB0_39 Depth=3
incq %r13
cmpq $36, %r13
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
je .LBB0_46
.LBB0_39: # %.preheader319
# Parent Loop BB0_33 Depth=1
# Parent Loop BB0_34 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB0_40 Depth 4
movss 240(%rsp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movaps %xmm0, %xmm2
addsd .LCPI0_2(%rip), %xmm2
movsd %xmm2, 192(%rsp) # 8-byte Spill
addsd %xmm1, %xmm0
movsd %xmm0, 200(%rsp) # 8-byte Spill
xorpd %xmm0, %xmm0
movl $2, %ebp
xorl %r15d, %r15d
xorps %xmm4, %xmm4
jmp .LBB0_40
.p2align 4, 0x90
.LBB0_44: # in Loop: Header=BB0_40 Depth=4
addl $2, %ebp
movq %rbx, %r15
cmpq $100, %rbx
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
je .LBB0_45
.LBB0_40: # Parent Loop BB0_33 Depth=1
# Parent Loop BB0_34 Depth=2
# Parent Loop BB0_39 Depth=3
# => This Inner Loop Header: Depth=4
movaps %xmm4, 32(%rsp) # 16-byte Spill
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq cosf
leaq 1(%r15), %rbx
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
movss %xmm1, 208(%rsp) # 4-byte Spill
mulss %xmm1, %xmm0
addss 144(%rsp), %xmm0 # 4-byte Folded Reload
callq roundf@PLT
cvttss2si %xmm0, %r12d
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sinf
mulss 208(%rsp), %xmm0 # 4-byte Folded Reload
addss 140(%rsp), %xmm0 # 4-byte Folded Reload
callq roundf@PLT
cvttss2si %xmm0, %eax
cltq
movslq %r12d, %rcx
imulq $4804, %rax, %rax # imm = 0x12C4
addq %rsp, %rax
addq $8800, %rax # imm = 0x2260
movl %r14d, %edx
subl (%rax,%rcx,4), %edx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
mulss %xmm1, %xmm1
movss .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss 32(%rsp), %xmm1 # 16-byte Folded Reload
movss %xmm1, 148(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
xorps %xmm1, %xmm1
cvtsi2sd %ebx, %xmm1
movsd %xmm1, 32(%rsp) # 8-byte Spill
mulsd %xmm1, %xmm0
addsd 184(%rsp), %xmm0 # 8-byte Folded Reload
callq round@PLT
cvttsd2si %xmm0, %r12d
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 32(%rsp), %xmm0 # 8-byte Folded Reload
addsd 176(%rsp), %xmm0 # 8-byte Folded Reload
callq round@PLT
cvttsd2si %xmm0, %eax
cltq
movslq %r12d, %rcx
imulq $4804, %rax, %rax # imm = 0x12C4
addq %rsp, %rax
addq $8800, %rax # imm = 0x2260
movl %r14d, %edx
subl (%rax,%rcx,4), %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
mulss %xmm0, %xmm0
mulss .LCPI0_3(%rip), %xmm0
addss 8(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 8(%rsp) # 4-byte Spill
divss 208(%rsp), %xmm0 # 4-byte Folded Reload
movaps %xmm0, 208(%rsp) # 16-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 32(%rsp), %xmm0 # 8-byte Folded Reload
addsd 184(%rsp), %xmm0 # 8-byte Folded Reload
callq round@PLT
cvttsd2si %xmm0, %r12d
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 32(%rsp), %xmm0 # 8-byte Folded Reload
addsd 176(%rsp), %xmm0 # 8-byte Folded Reload
callq round@PLT
movaps 208(%rsp), %xmm5 # 16-byte Reload
cvttsd2si %xmm0, %eax
cltq
movslq %r12d, %rcx
imulq $4804, %rax, %rax # imm = 0x12C4
addq %rsp, %rax
addq $8800, %rax # imm = 0x2260
movl %r14d, %edx
subl (%rax,%rcx,4), %edx
imull %edx, %edx
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
mulsd .LCPI0_4(%rip), %xmm0
cvttpd2dq %xmm0, %xmm0
cvtdq2ps %xmm0, %xmm4
addss 148(%rsp), %xmm4 # 4-byte Folded Reload
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
movaps %xmm4, %xmm0
divss %xmm1, %xmm0
ucomiss .LCPI0_7(%rip), %xmm0
jne .LBB0_42
jp .LBB0_42
# %bb.41: # in Loop: Header=BB0_40 Depth=4
xorps %xmm1, %xmm1
cmpltss %xmm5, %xmm1
movaps %xmm1, %xmm0
andps %xmm5, %xmm0
movss .LCPI0_5(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
andnps %xmm2, %xmm1
orps %xmm0, %xmm1
movaps %xmm5, %xmm0
cmpltss %xmm2, %xmm0
andps %xmm0, %xmm1
andnps %xmm2, %xmm0
orps %xmm1, %xmm0
.LBB0_42: # in Loop: Header=BB0_40 Depth=4
movss 384(%rsp,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jbe .LBB0_44
# %bb.43: # in Loop: Header=BB0_40 Depth=4
movaps %xmm5, %xmm1
cmpeqss .LCPI0_7(%rip), %xmm1
movaps %xmm1, %xmm2
movss .LCPI0_5(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
andps %xmm3, %xmm2
andnps %xmm5, %xmm1
orps %xmm2, %xmm1
movss %xmm0, 384(%rsp,%r15,4)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 1184(%rsp,%r15,4)
movss %xmm1, 784(%rsp,%r15,4)
jmp .LBB0_44
.p2align 4, 0x90
.LBB0_46: # %.preheader320
# in Loop: Header=BB0_34 Depth=2
movq 24(%rsp), %rsi # 8-byte Reload
movq 128(%rsp), %rdi # 8-byte Reload
movq (%rsi,%rdi,8), %rax
movq 168(%rsp), %rbx # 8-byte Reload
movq (%rax,%rbx,8), %rax
movq 120(%rsp), %rcx # 8-byte Reload
movq (%rcx,%rdi,8), %rcx
movq (%rcx,%rbx,8), %rcx
xorl %edx, %edx
movss .LCPI0_6(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_47: # Parent Loop BB0_33 Depth=1
# Parent Loop BB0_34 Depth=2
# => This Inner Loop Header: Depth=3
movss 784(%rsp,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 384(%rsp,%rdx,4), %xmm0
movss %xmm0, (%rax,%rdx,4)
movss 1184(%rsp,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rcx,%rdx,4)
incq %rdx
cmpq $100, %rdx
jne .LBB0_47
# %bb.48: # in Loop: Header=BB0_34 Depth=2
cmpq $1100, %rbx # imm = 0x44C
jne .LBB0_50
# %bb.49: # in Loop: Header=BB0_34 Depth=2
movq (%rsi,%rdi,8), %r15
movl $8800, %eax # imm = 0x2260
addq %rax, %r15
movl $10, %r14d
movl $1100, %ebx # imm = 0x44C
jmp .LBB0_51
.LBB0_54:
movq 56(%rsp), %rdi # 8-byte Reload
callq fclose
movq 112(%rsp), %rdi # 8-byte Reload
callq fclose
movq 160(%rsp), %rdi # 8-byte Reload
callq fclose
movq 104(%rsp), %rdi # 8-byte Reload
callq fclose
movq 96(%rsp), %rdi # 8-byte Reload
callq fclose
movq 88(%rsp), %rdi # 8-byte Reload
callq fclose
movq 152(%rsp), %rdi # 8-byte Reload
callq fclose
movq 80(%rsp), %rdi # 8-byte Reload
callq fclose
movq 72(%rsp), %rdi # 8-byte Reload
callq fclose
movq 64(%rsp), %rdi # 8-byte Reload
callq fclose
xorl %ebx, %ebx
movq 24(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB0_55: # %.preheader318
# =>This Loop Header: Depth=1
# Child Loop BB0_56 Depth 2
movq (%r14,%rbx,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_56: # Parent Loop BB0_55 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%r15,8), %rdi
callq free
incq %r15
cmpq $1201, %r15 # imm = 0x4B1
jne .LBB0_56
# %bb.57: # in Loop: Header=BB0_55 Depth=1
movq 24(%rsp), %r14 # 8-byte Reload
movq (%r14,%rbx,8), %rdi
callq free
incq %rbx
cmpq $801, %rbx # imm = 0x321
jne .LBB0_55
# %bb.58:
movq %r14, %rdi
callq free
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_59: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_60 Depth 2
movq (%r12,%rbx,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_60: # Parent Loop BB0_59 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%r15,8), %rdi
callq free
incq %r15
cmpq $1201, %r15 # imm = 0x4B1
jne .LBB0_60
# %bb.61: # in Loop: Header=BB0_59 Depth=1
movq (%r12,%rbx,8), %rdi
callq free
incq %rbx
cmpq $801, %rbx # imm = 0x321
jne .LBB0_59
# %bb.62:
movq %r12, %rdi
callq free
xorl %eax, %eax
jmp .LBB0_63
.LBB0_2:
movl $.L.str.2, %edi
jmp .LBB0_3
.LBB0_8:
movl $.L.str.9, %edi
jmp .LBB0_3
.LBB0_13:
movl $.L.str.14, %edi
.LBB0_3:
callq perror
movl $-1, %eax
.LBB0_63:
addq $3856808, %rsp # imm = 0x3AD9A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "inpCheck.txt"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cannot open dat.txt file"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "dat.txt"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "outputDataAni00.txt"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "outputDataAni09.txt"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "outputDataAni49.txt"
.size .L.str.7, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "outputDataAni99.txt"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Cannot open Anisotropy file"
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "outputDataAzi00.txt"
.size .L.str.10, 20
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "outputDataAzi09.txt"
.size .L.str.11, 20
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "outputDataAzi49.txt"
.size .L.str.12, 20
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "outputDataAzi99.txt"
.size .L.str.13, 20
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Cannot open Azimuth file"
.size .L.str.14, 25
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "%d "
.size .L.str.15, 4
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "%d\n"
.size .L.str.16, 4
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "%f"
.size .L.str.17, 3
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KparamAR(double* a, double* b, double* c, double ss, double dtAR, int width, int height)
{
#define eps 1E-12;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i >= width || j >= height) return;
int x= i;
int y= j;
if (i> width/2) x = width-i;
if (j> height/2) y = height-j;
double r = sqrt( (double)x*x + (double)y*y )+Eps;
a[i+j*width] = 2-dtAR*2*ss*r- pow(dtAR*ss*r,2);
b[i+j*width] = -1+dtAR*2*ss*r;
// c[i+j*width] = 50* pow(dtAR,2);
// Correction Jonathan 7-12-16
c[i+j*width] = 1;
} | code for sm_80
Function : _Z8KparamARPdS_S_ddii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x18c], PT ; /* 0x0000630002007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x188], P0 ; /* 0x0000620003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x188] ; /* 0x0000620000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IADD3 R5, -R2, c[0x0][0x18c], RZ ; /* 0x0000630002057a10 */
/* 0x000fe20007ffe1ff */
/*00c0*/ ULEA.HI UR4, UR7, UR7, URZ, 0x1 ; /* 0x0000000707047291 */
/* 0x000fe2000f8f083f */
/*00d0*/ IADD3 R0, -R3, c[0x0][0x188], RZ ; /* 0x0000620003007a10 */
/* 0x000fe20007ffe1ff */
/*00e0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe200078e00ff */
/*00f0*/ BSSY B0, 0x2d0 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0100*/ USHF.R.S32.HI UR5, URZ, 0x1, UR4 ; /* 0x000000013f057899 */
/* 0x000fe20008011404 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe200078e00ff */
/*0120*/ ULEA.HI UR4, UR6, UR6, URZ, 0x1 ; /* 0x0000000606047291 */
/* 0x000fc8000f8f083f */
/*0130*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011404 */
/*0140*/ ISETP.GT.AND P0, PT, R2, UR5, PT ; /* 0x0000000502007c0c */
/* 0x000fc8000bf04270 */
/*0150*/ SEL R12, R5, R2, P0 ; /* 0x00000002050c7207 */
/* 0x000fe40000000000 */
/*0160*/ ISETP.GT.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fe4000bf04270 */
/*0170*/ I2F.F64 R6, R12 ; /* 0x0000000c00067312 */
/* 0x000e240000201c00 */
/*0180*/ SEL R0, R0, R3, P0 ; /* 0x0000000300007207 */
/* 0x000fcc0000000000 */
/*0190*/ I2F.F64 R4, R0 ; /* 0x0000000000047312 */
/* 0x000e620000201c00 */
/*01a0*/ DMUL R6, R6, R6 ; /* 0x0000000606067228 */
/* 0x001e4c0000000000 */
/*01b0*/ DFMA R4, R4, R4, R6 ; /* 0x000000040404722b */
/* 0x002e0c0000000006 */
/*01c0*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e280000001c00 */
/*01d0*/ IADD3 R6, R5, -0x3500000, RZ ; /* 0xfcb0000005067810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ; /* 0x7ca000000600780c */
/* 0x000fe40003f06070 */
/*01f0*/ DMUL R8, R6, R6 ; /* 0x0000000606087228 */
/* 0x001e0c0000000000 */
/*0200*/ DFMA R8, R4, -R8, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000808 */
/*0210*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */
/* 0x001fc8000000000a */
/*0220*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */
/* 0x000e0c0000000000 */
/*0230*/ DFMA R8, R10, R8, R6 ; /* 0x000000080a08722b */
/* 0x001e0c0000000006 */
/*0240*/ DMUL R10, R4, R8 ; /* 0x00000008040a7228 */
/* 0x001e080000000000 */
/*0250*/ IADD3 R17, R9, -0x100000, RZ ; /* 0xfff0000009117810 */
/* 0x000fe20007ffe0ff */
/*0260*/ IMAD.MOV.U32 R16, RZ, RZ, R8 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0008 */
/*0270*/ DFMA R12, R10, -R10, R4 ; /* 0x8000000a0a0c722b */
/* 0x001e0c0000000004 */
/*0280*/ DFMA R14, R12, R16, R10 ; /* 0x000000100c0e722b */
/* 0x001062000000000a */
/*0290*/ @!P0 BRA 0x2c0 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*02a0*/ MOV R0, 0x2c0 ; /* 0x000002c000007802 */
/* 0x000fca0000000f00 */
/*02b0*/ CALL.REL.NOINC 0x600 ; /* 0x0000034000007944 */
/* 0x003fea0003c00000 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fe200078e00ff */
/*02e0*/ DADD R4, R14, c[0x2][0x0] ; /* 0x008000000e047629 */
/* 0x002fe20000000000 */
/*02f0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff077624 */
/* 0x000fe200078e00ff */
/*0300*/ BSSY B0, 0x360 ; /* 0x0000005000007945 */
/* 0x000fe20003800000 */
/*0310*/ MOV R0, 0x350 ; /* 0x0000035000007802 */
/* 0x000fc80000000f00 */
/*0320*/ DMUL R6, R6, c[0x0][0x180] ; /* 0x0000600006067a28 */
/* 0x000e4c0000000000 */
/*0330*/ DMUL R6, R4, R6 ; /* 0x0000000604067228 */
/* 0x00228c0000000000 */
/*0340*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000056000007944 */
/* 0x007fea0003c00000 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ DADD R8, R6.reuse, 2 ; /* 0x4000000006087429 */
/* 0x040e220000000000 */
/*0370*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0380*/ BSSY B0, 0x4b0 ; /* 0x0000012000007945 */
/* 0x000fe40003800000 */
/*0390*/ DSETP.NEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e4c0003f0d000 */
/*03a0*/ LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009087812 */
/* 0x001fe200078ec0ff */
/*03b0*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0011 */
/*03c0*/ ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ; /* 0x7ff000000800780c */
/* 0x000fe20003f25270 */
/*03d0*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0010 */
/*03e0*/ @!P0 CS2R R8, SRZ ; /* 0x0000000000088805 */
/* 0x002fd2000001ff00 */
/*03f0*/ @P1 BRA 0x4a0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0400*/ DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e1c0003f0c200 */
/*0410*/ @P0 BRA 0x490 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*0420*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0430*/ LOP3.LUT R0, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07007812 */
/* 0x000fc800078ec0ff */
/*0440*/ ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; /* 0x7ff000000000780c */
/* 0x000fda0000705670 */
/*0450*/ @P0 BRA 0x4a0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0460*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe400078e00ff */
/*0470*/ IMAD.MOV.U32 R9, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff097424 */
/* 0x000fe200078e00ff */
/*0480*/ BRA 0x4a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0490*/ DADD R8, R6, 2 ; /* 0x4000000006087429 */
/* 0x00004c0000000000 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0a7624 */
/* 0x000fe200078e00ff */
/*04c0*/ DSETP.NEU.AND P0, PT, R6, 1, PT ; /* 0x3ff000000600742a */
/* 0x000ea20003f0d000 */
/*04d0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff0b7624 */
/* 0x000fe400078e00ff */
/*04e0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fe400078e00ff */
/*04f0*/ IMAD R0, R2, c[0x0][0x188], R3 ; /* 0x0000620002007a24 */
/* 0x000fe200078e0203 */
/*0500*/ FSEL R8, R8, RZ, P0 ; /* 0x000000ff08087208 */
/* 0x006fe20000000000 */
/*0510*/ DADD R10, R10, c[0x0][0x180] ; /* 0x000060000a0a7629 */
/* 0x000e620000000000 */
/*0520*/ FSEL R9, R9, 1.875, P0 ; /* 0x3ff0000009097808 */
/* 0x000fe20000000000 */
/*0530*/ IMAD.WIDE R2, R0, R15, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020f */
/*0540*/ DMUL R10, R10, c[0x0][0x178] ; /* 0x00005e000a0a7a28 */
/* 0x002e620000000000 */
/*0550*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff0d7424 */
/* 0x000fc600078e00ff */
/*0570*/ DFMA R6, R4, -R10, 2 ; /* 0x400000000406742b */
/* 0x003e08000000080a */
/*0580*/ DFMA R10, R4, R10, -1 ; /* 0xbff00000040a742b */
/* 0x0003e4000000000a */
/*0590*/ IMAD.WIDE R4, R0.reuse, R15.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c2fe400078e020f */
/*05a0*/ DADD R6, R6, -R8 ; /* 0x0000000006067229 */
/* 0x0010640000000808 */
/*05b0*/ IMAD.WIDE R8, R0, R15, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x001fca00078e020f */
/*05c0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x002fe8000c101b04 */
/*05d0*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x000fe8000c101b04 */
/*05e0*/ STG.E.64 [R8.64], R12 ; /* 0x0000000c08007986 */
/* 0x000fe2000c101b04 */
/*05f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.U32.AND P0, PT, R6, -0x3400000, PT ; /* 0xfcc000000600780c */
/* 0x000fe20003f06070 */
/*0610*/ BSSY B1, 0x860 ; /* 0x0000024000017945 */
/* 0x000fe20003800000 */
/*0620*/ MOV R9, R17 ; /* 0x0000001100097202 */
/* 0x000fd60000000f00 */
/*0630*/ @!P0 BRA 0x6c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0640*/ DFMA.RM R8, R12, R8, R10 ; /* 0x000000080c08722b */
/* 0x000e14000000400a */
/*0650*/ IADD3 R6, P0, R8, 0x1, RZ ; /* 0x0000000108067810 */
/* 0x001fca0007f1e0ff */
/*0660*/ IMAD.X R7, RZ, RZ, R9, P0 ; /* 0x000000ffff077224 */
/* 0x000fcc00000e0609 */
/*0670*/ DFMA.RP R4, -R8, R6, R4 ; /* 0x000000060804722b */
/* 0x000e0c0000008104 */
/*0680*/ DSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x001e0c0003f04000 */
/*0690*/ FSEL R6, R6, R8, P0 ; /* 0x0000000806067208 */
/* 0x001fe40000000000 */
/*06a0*/ FSEL R7, R7, R9, P0 ; /* 0x0000000907077208 */
/* 0x000fe20000000000 */
/*06b0*/ BRA 0x850 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*06c0*/ DSETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e1c0003f05000 */
/*06d0*/ @!P0 BRA 0x840 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*06e0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f06270 */
/*06f0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff068424 */
/* 0x000fe400078e00ff */
/*0700*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x80000 ; /* 0xfff80000ff078424 */
/* 0x000fe200078e00ff */
/*0710*/ @!P0 BRA 0x850 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0720*/ ISETP.GT.AND P0, PT, R5, 0x7fefffff, PT ; /* 0x7fefffff0500780c */
/* 0x000fda0003f04270 */
/*0730*/ @P0 BRA 0x840 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0740*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x000e220000000000 */
/*0750*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0760*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0770*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe200078e00ff */
/*0780*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001c00 */
/*0790*/ DMUL R8, R6, R6 ; /* 0x0000000606087228 */
/* 0x001e0c0000000000 */
/*07a0*/ DFMA R8, R4, -R8, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000808 */
/*07b0*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */
/* 0x001fc8000000000a */
/*07c0*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */
/* 0x000e0c0000000000 */
/*07d0*/ DFMA R8, R10, R8, R6 ; /* 0x000000080a08722b */
/* 0x001e0c0000000006 */
/*07e0*/ DMUL R6, R4, R8 ; /* 0x0000000804067228 */
/* 0x0010480000000000 */
/*07f0*/ IADD3 R9, R9, -0x100000, RZ ; /* 0xfff0000009097810 */
/* 0x001fe40007ffe0ff */
/*0800*/ DFMA R10, R6, -R6, R4 ; /* 0x80000006060a722b */
/* 0x002e0c0000000004 */
/*0810*/ DFMA R6, R8, R10, R6 ; /* 0x0000000a0806722b */
/* 0x001e140000000006 */
/*0820*/ IADD3 R7, R7, -0x3500000, RZ ; /* 0xfcb0000007077810 */
/* 0x001fe20007ffe0ff */
/*0830*/ BRA 0x850 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0840*/ DADD R6, R4, R4 ; /* 0x0000000004067229 */
/* 0x00004c0000000004 */
/*0850*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0000 */
/*0870*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe400078e00ff */
/*0880*/ IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e7224 */
/* 0x002fe400078e0006 */
/*0890*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0007 */
/*08a0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff75004007950 */
/* 0x000fec0003c3ffff */
/*08b0*/ DADD R10, -RZ, |R6| ; /* 0x00000000ff0a7229 */
/* 0x000e220000000506 */
/*08c0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*08d0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff127424 */
/* 0x000fc400078e00ff */
/*08e0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff137424 */
/* 0x000fca00078e00ff */
/*08f0*/ SHF.R.U32.HI R26, RZ, 0x14, R11 ; /* 0x00000014ff1a7819 */
/* 0x001fc8000001160b */
/*0900*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fda0003f05270 */
/*0910*/ @!P0 DMUL R8, R10, 1.80143985094819840000e+16 ; /* 0x435000000a088828 */
/* 0x000e140000000000 */
/*0920*/ @!P0 MOV R11, R9 ; /* 0x00000009000b8202 */
/* 0x001fe20000000f00 */
/*0930*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e0008 */
/*0940*/ @!P0 LEA.HI R26, R9, 0xffffffca, RZ, 0xc ; /* 0xffffffca091a8811 */
/* 0x000fe200078f60ff */
/*0950*/ IMAD.MOV.U32 R9, RZ, RZ, 0x43300000 ; /* 0x43300000ff097424 */
/* 0x000fe200078e00ff */
/*0960*/ LOP3.LUT R11, R11, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fe200078ec0ff */
/*0970*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000a */
/*0980*/ IADD3 R8, R26, -0x3ff, RZ ; /* 0xfffffc011a087810 */
/* 0x000fe40007ffe0ff */
/*0990*/ LOP3.LUT R13, R11, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000b0d7812 */
/* 0x000fc800078efcff */
/*09a0*/ ISETP.GE.U32.AND P1, PT, R13, 0x3ff6a09f, PT ; /* 0x3ff6a09f0d00780c */
/* 0x000fda0003f26070 */
/*09b0*/ @P1 IADD3 R11, R13, -0x100000, RZ ; /* 0xfff000000d0b1810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ @P1 IADD3 R8, R26, -0x3fe, RZ ; /* 0xfffffc021a081810 */
/* 0x000fc60007ffe0ff */
/*09d0*/ @P1 IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d1224 */
/* 0x000fe200078e000b */
/*09e0*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000008087812 */
/* 0x000fca00078e3cff */
/*09f0*/ DADD R16, R12, 1 ; /* 0x3ff000000c107429 */
/* 0x000e080000000000 */
/*0a00*/ DADD R12, R12, -1 ; /* 0xbff000000c0c7429 */
/* 0x000fe40000000000 */
/*0a10*/ MUFU.RCP64H R15, R17 ; /* 0x00000011000f7308 */
/* 0x001e240000001800 */
/*0a20*/ DFMA R10, -R16, R14, 1 ; /* 0x3ff00000100a742b */
/* 0x001e0c000000010e */
/*0a30*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0a40*/ DFMA R14, R14, R10, R14 ; /* 0x0000000a0e0e722b */
/* 0x001e0c000000000e */
/*0a50*/ DMUL R10, R14, R12 ; /* 0x0000000c0e0a7228 */
/* 0x001e0c0000000000 */
/*0a60*/ DFMA R10, R14, R12, R10 ; /* 0x0000000c0e0a722b */
/* 0x001e0c000000000a */
/*0a70*/ DMUL R20, R10, R10 ; /* 0x0000000a0a147228 */
/* 0x001e080000000000 */
/*0a80*/ DADD R16, R12, -R10 ; /* 0x000000000c107229 */
/* 0x000e48000000080a */
/*0a90*/ DFMA R18, R20, R18, c[0x2][0x8] ; /* 0x008002001412762b */
/* 0x001e080000000012 */
/*0aa0*/ DADD R16, R16, R16 ; /* 0x0000000010107229 */
/* 0x002e480000000010 */
/*0ab0*/ DFMA R18, R20, R18, c[0x2][0x10] ; /* 0x008004001412762b */
/* 0x001e080000000012 */
/*0ac0*/ DFMA R16, R12, -R10, R16 ; /* 0x8000000a0c10722b */
/* 0x002e480000000010 */
/*0ad0*/ DFMA R18, R20, R18, c[0x2][0x18] ; /* 0x008006001412762b */
/* 0x001e080000000012 */
/*0ae0*/ DMUL R14, R14, R16 ; /* 0x000000100e0e7228 */
/* 0x002fc80000000000 */
/*0af0*/ DFMA R18, R20, R18, c[0x2][0x20] ; /* 0x008008001412762b */
/* 0x001e080000000012 */
/*0b00*/ DMUL R16, R10, R10 ; /* 0x0000000a0a107228 */
/* 0x000e480000000000 */
/*0b10*/ DFMA R18, R20, R18, c[0x2][0x28] ; /* 0x00800a001412762b */
/* 0x001e080000000012 */
/*0b20*/ DFMA R24, R10, R10, -R16 ; /* 0x0000000a0a18722b */
/* 0x002fc80000000810 */
/*0b30*/ DFMA R18, R20, R18, c[0x2][0x30] ; /* 0x00800c001412762b */
/* 0x001e0c0000000012 */
/*0b40*/ DFMA R12, R20, R18, c[0x2][0x38] ; /* 0x00800e00140c762b */
/* 0x001e0c0000000012 */
/*0b50*/ DADD R22, -R12, c[0x2][0x38] ; /* 0x00800e000c167629 */
/* 0x001e0c0000000100 */
/*0b60*/ DFMA R20, R20, R18, R22 ; /* 0x000000121414722b */
/* 0x0010640000000016 */
/*0b70*/ IADD3 R23, R15, 0x100000, RZ ; /* 0x001000000f177810 */
/* 0x001fe20007ffe0ff */
/*0b80*/ IMAD.MOV.U32 R22, RZ, RZ, R14 ; /* 0x000000ffff167224 */
/* 0x000fe200078e000e */
/*0b90*/ DMUL R18, R10, R16 ; /* 0x000000100a127228 */
/* 0x000e080000000000 */
/*0ba0*/ DADD R20, RZ, R20 ; /* 0x00000000ff147229 */
/* 0x002e480000000014 */
/*0bb0*/ DFMA R22, R10, R22, R24 ; /* 0x000000160a16722b */
/* 0x000fc80000000018 */
/*0bc0*/ DFMA R24, R10, R16, -R18 ; /* 0x000000100a18722b */
/* 0x001e080000000812 */
/*0bd0*/ DADD R20, R20, c[0x2][0x40] ; /* 0x0080100014147629 */
/* 0x002e480000000000 */
/*0be0*/ DFMA R24, R14, R16, R24 ; /* 0x000000100e18722b */
/* 0x001e080000000018 */
/*0bf0*/ DADD R16, R12, R20 ; /* 0x000000000c107229 */
/* 0x002e480000000014 */
/*0c00*/ DFMA R22, R10, R22, R24 ; /* 0x000000160a16722b */
/* 0x001fc80000000018 */
/*0c10*/ DADD R24, R12, -R16 ; /* 0x000000000c187229 */
/* 0x002e080000000810 */
/*0c20*/ DMUL R12, R16, R18 ; /* 0x00000012100c7228 */
/* 0x000e480000000000 */
/*0c30*/ DADD R24, R20, R24 ; /* 0x0000000014187229 */
/* 0x001fc80000000018 */
/*0c40*/ DFMA R20, R16, R18, -R12 ; /* 0x000000121014722b */
/* 0x002e0c000000080c */
/*0c50*/ DFMA R20, R16, R22, R20 ; /* 0x000000161014722b */
/* 0x001e0c0000000014 */
/*0c60*/ DFMA R24, R24, R18, R20 ; /* 0x000000121818722b */
/* 0x0010640000000014 */
/*0c70*/ MOV R20, 0x69ce2bdf ; /* 0x69ce2bdf00147802 */
/* 0x001fe20000000f00 */
/*0c80*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff157424 */
/* 0x000fc600078e00ff */
/*0c90*/ DADD R18, R12, R24 ; /* 0x000000000c127229 */
/* 0x002e0c0000000018 */
/*0ca0*/ DADD R16, R10, R18 ; /* 0x000000000a107229 */
/* 0x001e080000000012 */
/*0cb0*/ DADD R12, R12, -R18 ; /* 0x000000000c0c7229 */
/* 0x000e480000000812 */
/*0cc0*/ DADD R10, R10, -R16 ; /* 0x000000000a0a7229 */
/* 0x001e080000000810 */
/*0cd0*/ DADD R12, R24, R12 ; /* 0x00000000180c7229 */
/* 0x002fc8000000000c */
/*0ce0*/ DADD R10, R18, R10 ; /* 0x00000000120a7229 */
/* 0x001e0c000000000a */
/*0cf0*/ DADD R10, R12, R10 ; /* 0x000000000c0a7229 */
/* 0x001e0c000000000a */
/*0d00*/ DADD R14, R14, R10 ; /* 0x000000000e0e7229 */
/* 0x001e08000000000a */
/*0d10*/ DADD R10, R8, c[0x2][0x48] ; /* 0x00801200080a7629 */
/* 0x000fc80000000000 */
/*0d20*/ DADD R12, R16, R14 ; /* 0x00000000100c7229 */
/* 0x001e0c000000000e */
/*0d30*/ DFMA R8, R10, c[0x2][0x50], R12 ; /* 0x008014000a087a2b */
/* 0x001e08000000000c */
/*0d40*/ DADD R16, R16, -R12 ; /* 0x0000000010107229 */
/* 0x000e48000000080c */
/*0d50*/ DFMA R18, -R10, c[0x2][0x50], R8 ; /* 0x008014000a127a2b */
/* 0x001e080000000108 */
/*0d60*/ DADD R16, R14, R16 ; /* 0x000000000e107229 */
/* 0x0023e40000000010 */
/*0d70*/ IMAD.MOV.U32 R14, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0e7424 */
/* 0x002fe400078e00ff */
/*0d80*/ DADD R18, -R12, R18 ; /* 0x000000000c127229 */
/* 0x001e220000000112 */
/*0d90*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0f7424 */
/* 0x000fca00078e00ff */
/*0da0*/ DADD R16, R16, -R18 ; /* 0x0000000010107229 */
/* 0x001e0c0000000812 */
/*0db0*/ DFMA R16, R10, c[0x2][0x58], R16 ; /* 0x008016000a107a2b */
/* 0x001e0c0000000010 */
/*0dc0*/ DADD R10, R8, R16 ; /* 0x00000000080a7229 */
/* 0x001e0c0000000010 */
/*0dd0*/ DADD R12, R8, -R10 ; /* 0x00000000080c7229 */
/* 0x001e08000000080a */
/*0de0*/ DMUL R8, R10, 2 ; /* 0x400000000a087828 */
/* 0x000e480000000000 */
/*0df0*/ DADD R12, R16, R12 ; /* 0x00000000100c7229 */
/* 0x001fc8000000000c */
/*0e00*/ DFMA R10, R10, 2, -R8 ; /* 0x400000000a0a782b */
/* 0x002e0c0000000808 */
/*0e10*/ DFMA R10, R12, 2, R10 ; /* 0x400000000c0a782b */
/* 0x001e0c000000000a */
/*0e20*/ DADD R12, R8, R10 ; /* 0x00000000080c7229 */
/* 0x001e0c000000000a */
/*0e30*/ DFMA R14, R12, R14, 6.75539944105574400000e+15 ; /* 0x433800000c0e742b */
/* 0x001e08000000000e */
/*0e40*/ FSETP.GEU.AND P0, PT, |R13|, 4.1917929649353027344, PT ; /* 0x4086232b0d00780b */
/* 0x000fe40003f0e200 */
/*0e50*/ DADD R16, R14, -6.75539944105574400000e+15 ; /* 0xc33800000e107429 */
/* 0x001e0c0000000000 */
/*0e60*/ DFMA R18, R16, c[0x2][0x60], R12 ; /* 0x0080180010127a2b */
/* 0x001e0c000000000c */
/*0e70*/ DFMA R16, R16, c[0x2][0x68], R18 ; /* 0x00801a0010107a2b */
/* 0x001e0c0000000012 */
/*0e80*/ DFMA R18, R16, R20, c[0x2][0x70] ; /* 0x00801c001012762b */
/* 0x001e0c0000000014 */
/*0e90*/ DFMA R18, R16, R18, c[0x2][0x78] ; /* 0x00801e001012762b */
/* 0x001e0c0000000012 */
/*0ea0*/ DFMA R18, R16, R18, c[0x2][0x80] ; /* 0x008020001012762b */
/* 0x001e0c0000000012 */
/*0eb0*/ DFMA R18, R16, R18, c[0x2][0x88] ; /* 0x008022001012762b */
/* 0x001e0c0000000012 */
/*0ec0*/ DFMA R18, R16, R18, c[0x2][0x90] ; /* 0x008024001012762b */
/* 0x001e0c0000000012 */
/*0ed0*/ DFMA R18, R16, R18, c[0x2][0x98] ; /* 0x008026001012762b */
/* 0x001e0c0000000012 */
/*0ee0*/ DFMA R18, R16, R18, c[0x2][0xa0] ; /* 0x008028001012762b */
/* 0x001e0c0000000012 */
/*0ef0*/ DFMA R18, R16, R18, c[0x2][0xa8] ; /* 0x00802a001012762b */
/* 0x001e0c0000000012 */
/*0f00*/ DFMA R18, R16, R18, c[0x2][0xb0] ; /* 0x00802c001012762b */
/* 0x001e0c0000000012 */
/*0f10*/ DFMA R18, R16, R18, 1 ; /* 0x3ff000001012742b */
/* 0x001e0c0000000012 */
/*0f20*/ DFMA R18, R16, R18, 1 ; /* 0x3ff000001012742b */
/* 0x001e140000000012 */
/*0f30*/ IMAD R17, R14, 0x100000, R19 ; /* 0x001000000e117824 */
/* 0x001fe400078e0213 */
/*0f40*/ IMAD.MOV.U32 R16, RZ, RZ, R18 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0012 */
/*0f50*/ @!P0 BRA 0x1020 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0f60*/ FSETP.GEU.AND P1, PT, |R13|, 4.2275390625, PT ; /* 0x408748000d00780b */
/* 0x000fe20003f2e200 */
/*0f70*/ DADD R16, R12, +INF ; /* 0x7ff000000c107429 */
/* 0x000fc80000000000 */
/*0f80*/ DSETP.GEU.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00722a */
/* 0x000e0c0003f0e000 */
/*0f90*/ FSEL R16, R16, RZ, P0 ; /* 0x000000ff10107208 */
/* 0x001fe40000000000 */
/*0fa0*/ @!P1 LEA.HI R15, R14, R14, RZ, 0x1 ; /* 0x0000000e0e0f9211 */
/* 0x000fe400078f08ff */
/*0fb0*/ FSEL R17, R17, RZ, P0 ; /* 0x000000ff11117208 */
/* 0x000fe40000000000 */
/*0fc0*/ @!P1 SHF.R.S32.HI R15, RZ, 0x1, R15 ; /* 0x00000001ff0f9819 */
/* 0x000fca000001140f */
/*0fd0*/ @!P1 IMAD.IADD R14, R14, 0x1, -R15 ; /* 0x000000010e0e9824 */
/* 0x000fe400078e0a0f */
/*0fe0*/ @!P1 IMAD R19, R15, 0x100000, R19 ; /* 0x001000000f139824 */
/* 0x000fc600078e0213 */
/*0ff0*/ @!P1 LEA R15, R14, 0x3ff00000, 0x14 ; /* 0x3ff000000e0f9811 */
/* 0x000fe200078ea0ff */
/*1000*/ @!P1 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e9224 */
/* 0x000fcc00078e00ff */
/*1010*/ @!P1 DMUL R16, R18, R14 ; /* 0x0000000e12109228 */
/* 0x0000540000000000 */
/*1020*/ LOP3.LUT R14, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110e7812 */
/* 0x003fe200078ec0ff */
/*1030*/ DADD R8, R8, -R12 ; /* 0x0000000008087229 */
/* 0x000e06000000080c */
/*1040*/ ISETP.NE.AND P0, PT, R14, 0x7ff00000, PT ; /* 0x7ff000000e00780c */
/* 0x000fc60003f05270 */
/*1050*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x001e220000000008 */
/*1060*/ ISETP.EQ.AND P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702270 */
/*1070*/ @!P0 DFMA R16, R8, R16, R16 ; /* 0x000000100810822b */
/* 0x0010640000000010 */
/*1080*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0000 */
/*1090*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*10a0*/ RET.REL.NODEC R8 0x0 ; /* 0xffffef5008007950 */
/* 0x002fea0003c3ffff */
/*10b0*/ BRA 0x10b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KparamAR(double* a, double* b, double* c, double ss, double dtAR, int width, int height)
{
#define eps 1E-12;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i >= width || j >= height) return;
int x= i;
int y= j;
if (i> width/2) x = width-i;
if (j> height/2) y = height-j;
double r = sqrt( (double)x*x + (double)y*y )+Eps;
a[i+j*width] = 2-dtAR*2*ss*r- pow(dtAR*ss*r,2);
b[i+j*width] = -1+dtAR*2*ss*r;
// c[i+j*width] = 50* pow(dtAR,2);
// Correction Jonathan 7-12-16
c[i+j*width] = 1;
} | .file "tmpxft_00035ae3_00000000-6_KparamAR.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii
.type _Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii, @function
_Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8KparamARPdS_S_ddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii, .-_Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii
.globl _Z8KparamARPdS_S_ddii
.type _Z8KparamARPdS_S_ddii, @function
_Z8KparamARPdS_S_ddii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8KparamARPdS_S_ddii, .-_Z8KparamARPdS_S_ddii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8KparamARPdS_S_ddii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8KparamARPdS_S_ddii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl MaxThreadsY
.bss
.align 4
.type MaxThreadsY, @object
.size MaxThreadsY, 4
MaxThreadsY:
.zero 4
.globl MaxThreadsX
.align 4
.type MaxThreadsX, @object
.size MaxThreadsX, 4
MaxThreadsX:
.zero 4
.globl MaxThreadsPerBlock
.align 4
.type MaxThreadsPerBlock, @object
.size MaxThreadsPerBlock, 4
MaxThreadsPerBlock:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KparamAR(double* a, double* b, double* c, double ss, double dtAR, int width, int height)
{
#define eps 1E-12;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i >= width || j >= height) return;
int x= i;
int y= j;
if (i> width/2) x = width-i;
if (j> height/2) y = height-j;
double r = sqrt( (double)x*x + (double)y*y )+Eps;
a[i+j*width] = 2-dtAR*2*ss*r- pow(dtAR*ss*r,2);
b[i+j*width] = -1+dtAR*2*ss*r;
// c[i+j*width] = 50* pow(dtAR,2);
// Correction Jonathan 7-12-16
c[i+j*width] = 1;
} | #include <hip/hip_runtime.h>
#include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KparamAR(double* a, double* b, double* c, double ss, double dtAR, int width, int height)
{
#define eps 1E-12;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i >= width || j >= height) return;
int x= i;
int y= j;
if (i> width/2) x = width-i;
if (j> height/2) y = height-j;
double r = sqrt( (double)x*x + (double)y*y )+Eps;
a[i+j*width] = 2-dtAR*2*ss*r- pow(dtAR*ss*r,2);
b[i+j*width] = -1+dtAR*2*ss*r;
// c[i+j*width] = 50* pow(dtAR,2);
// Correction Jonathan 7-12-16
c[i+j*width] = 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KparamAR(double* a, double* b, double* c, double ss, double dtAR, int width, int height)
{
#define eps 1E-12;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i >= width || j >= height) return;
int x= i;
int y= j;
if (i> width/2) x = width-i;
if (j> height/2) y = height-j;
double r = sqrt( (double)x*x + (double)y*y )+Eps;
a[i+j*width] = 2-dtAR*2*ss*r- pow(dtAR*ss*r,2);
b[i+j*width] = -1+dtAR*2*ss*r;
// c[i+j*width] = 50* pow(dtAR,2);
// Correction Jonathan 7-12-16
c[i+j*width] = 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8KparamARPdS_S_ddii
.globl _Z8KparamARPdS_S_ddii
.p2align 8
.type _Z8KparamARPdS_S_ddii,@function
_Z8KparamARPdS_S_ddii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[12:13], s[0:1], 0x28
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s12, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s13, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_lshr_b32 s2, s13, 31
v_sub_nc_u32_e32 v2, s13, v1
s_add_i32 s2, s13, s2
v_sub_nc_u32_e32 v4, s12, v0
s_ashr_i32 s2, s2, 1
s_mov_b32 s15, 0x3fba6564
v_cmp_lt_i32_e32 vcc_lo, s2, v1
s_lshr_b32 s2, s12, 31
s_mov_b32 s14, 0x968915a9
s_add_i32 s2, s12, s2
s_mov_b32 s17, 0x3fbdee67
v_cndmask_b32_e32 v2, v1, v2, vcc_lo
s_ashr_i32 s2, s2, 1
s_mov_b32 s16, 0x4222de17
v_cmp_lt_i32_e32 vcc_lo, s2, v0
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x20
v_cvt_f64_i32_e32 v[2:3], v2
s_mov_b32 s1, 0x3eb0c6f7
s_mov_b32 s0, 0xa0b5ed8d
v_cndmask_b32_e32 v4, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[4:5], v4
v_mul_f64 v[2:3], v[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[4:5], v[4:5], v[2:3]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[2:3]
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 8, v4
v_ldexp_f64 v[2:3], v[2:3], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[4:5], v[2:3]
s_waitcnt_depctr 0xfff
v_mul_f64 v[6:7], v[2:3], v[4:5]
v_mul_f64 v[4:5], v[4:5], 0.5
v_fma_f64 v[8:9], -v[4:5], v[6:7], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[8:9], v[4:5], v[6:7]
v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
v_cndmask_b32_e64 v6, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x260
v_ldexp_f64 v[4:5], v[4:5], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
s_waitcnt lgkmcnt(0)
v_mul_f64 v[4:5], s[10:11], s[2:3]
v_add_f64 v[2:3], v[2:3], s[0:1]
s_mov_b32 s1, 0x3fe55555
s_mov_b32 s0, 0x55555555
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[4:5], v[2:3]
v_frexp_mant_f64_e64 v[6:7], |v[4:5]|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[6:7]
v_cndmask_b32_e64 v8, 0, 1, vcc_lo
v_ldexp_f64 v[6:7], v[6:7], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[6:7], 1.0
v_add_f64 v[14:15], v[6:7], -1.0
v_rcp_f64_e32 v[10:11], v[8:9]
v_add_f64 v[16:17], v[8:9], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[16:17]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[14:15], v[10:11]
v_mul_f64 v[18:19], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[12:13], v[8:9], -v[18:19]
v_fma_f64 v[6:7], v[12:13], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[18:19], v[6:7]
v_add_f64 v[16:17], v[14:15], -v[8:9]
v_add_f64 v[18:19], v[8:9], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[14:15], -v[16:17]
v_add_f64 v[6:7], v[18:19], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[14:15], -v[8:9]
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[16:17], v[6:7]
v_mul_f64 v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[12:13], v[6:7]
v_add_f64 v[10:11], v[8:9], -v[12:13]
v_mul_f64 v[12:13], v[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[10:11]
v_fma_f64 v[10:11], v[8:9], v[8:9], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[6:7], v[6:7]
v_fma_f64 v[10:11], v[8:9], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[12:13], v[10:11]
v_fma_f64 v[16:17], v[14:15], s[16:17], s[14:15]
s_mov_b32 s15, 0x3fbe25e4
s_mov_b32 s14, 0x3abe935a
v_add_f64 v[12:13], v[14:15], -v[12:13]
v_mul_f64 v[22:23], v[8:9], v[14:15]
s_mov_b32 s17, 0x3ff71547
s_mov_b32 s16, 0x652b82fe
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[14:15]
s_mov_b32 s15, 0x3fc110ef
s_mov_b32 s14, 0x47e6c9c2
v_add_f64 v[10:11], v[10:11], -v[12:13]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[14:15]
s_mov_b32 s15, 0x3fc3b13b
s_mov_b32 s14, 0xcfa74449
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[14:15]
s_mov_b32 s15, 0x3fc745d1
s_mov_b32 s14, 0x71bf3c30
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[14:15]
s_mov_b32 s15, 0x3fcc71c7
s_mov_b32 s14, 0x1c7792ce
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[14:15]
s_mov_b32 s15, 0x3fd24924
s_mov_b32 s14, 0x924920da
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[14:15]
s_mov_b32 s15, 0x3fd99999
s_mov_b32 s14, 0x9999999c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[14:15]
s_mov_b32 s15, 0x3c7abc9e
s_mov_b32 s14, 0x3b39803f
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[14:15], v[16:17]
v_fma_f64 v[12:13], v[14:15], v[16:17], -v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], v[16:17], v[12:13]
v_add_f64 v[16:17], v[18:19], v[12:13]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[20:21], v[16:17], s[0:1]
v_add_f64 v[18:19], v[16:17], -v[18:19]
s_mov_b32 s1, 0xbfe55555
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[24:25], v[20:21], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], -v[18:19]
v_fma_f64 v[18:19], v[14:15], v[8:9], -v[22:23]
s_mov_b32 s1, 0x3c8543b0
s_mov_b32 s0, 0xd5df274d
v_add_f64 v[16:17], v[16:17], -v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], s[0:1]
v_fma_f64 v[14:15], v[14:15], v[6:7], v[18:19]
s_mov_b32 s1, 0x3fe62e42
s_mov_b32 s0, 0xfefa39ef
v_ldexp_f64 v[6:7], v[6:7], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], v[16:17]
v_fma_f64 v[10:11], v[10:11], v[8:9], v[14:15]
v_ldexp_f64 v[8:9], v[8:9], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[20:21], v[12:13]
v_add_f64 v[16:17], v[22:23], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[20:21], -v[14:15]
v_mul_f64 v[20:21], v[16:17], v[14:15]
v_add_f64 v[22:23], v[16:17], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], v[18:19]
v_fma_f64 v[18:19], v[16:17], v[14:15], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[22:23]
v_fma_f64 v[12:13], v[16:17], v[12:13], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[10:11], v[14:15], v[12:13]
v_frexp_exp_i32_f64_e32 v14, v[4:5]
v_add_f64 v[12:13], v[20:21], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
v_cvt_f64_i32_e32 v[14:15], v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[8:9], v[12:13]
v_add_f64 v[18:19], v[12:13], -v[20:21]
v_mul_f64 v[20:21], v[14:15], s[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[16:17], -v[8:9]
v_add_f64 v[10:11], v[10:11], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], v[14:15], s[0:1], -v[20:21]
s_mov_b32 s1, 0xbfe62e42
v_add_f64 v[8:9], v[12:13], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[6:7], v[10:11]
v_fma_f64 v[10:11], v[14:15], s[14:15], v[18:19]
s_mov_b32 s15, 0xbc7abc9e
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[8:9]
v_add_f64 v[8:9], v[20:21], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[16:17], v[6:7]
v_add_f64 v[20:21], v[8:9], -v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[8:9], v[12:13]
v_add_f64 v[16:17], v[12:13], -v[16:17]
v_add_f64 v[10:11], v[10:11], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[14:15], -v[8:9]
v_add_f64 v[6:7], v[6:7], -v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], v[14:15], -v[18:19]
v_add_f64 v[12:13], v[12:13], -v[18:19]
v_add_f64 v[16:17], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[8:9], -v[22:23]
v_add_f64 v[8:9], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[16:17], -v[10:11]
v_add_f64 v[8:9], v[16:17], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[16:17], -v[12:13]
v_add_f64 v[6:7], v[6:7], -v[12:13]
v_add_f64 v[18:19], v[14:15], v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[16:17]
v_add_f64 v[12:13], v[18:19], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[10:11]
v_add_f64 v[8:9], v[8:9], -v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], v[8:9]
v_add_f64 v[8:9], v[18:19], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[8:9], -v[18:19]
v_add_f64 v[12:13], v[8:9], v[8:9]
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[8:9], 2.0, -v[12:13]
v_cmp_class_f64_e64 vcc_lo, v[12:13], 0x204
v_fma_f64 v[6:7], v[6:7], 2.0, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[12:13], v[6:7]
v_dual_cndmask_b32 v11, v9, v13 :: v_dual_cndmask_b32 v10, v8, v12
v_add_f64 v[8:9], v[8:9], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f64 v[14:15], v[10:11], s[16:17]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[10:11]|
v_add_f64 v[6:7], v[6:7], -v[8:9]
v_add_f64 v[8:9], s[2:3], s[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rndne_f64_e32 v[14:15], v[14:15]
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_f64 v[8:9], v[8:9], s[10:11]
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_fma_f64 v[16:17], v[14:15], s[0:1], v[10:11]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
v_cvt_i32_f64_e32 v20, v[14:15]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[16:17], v[14:15], s[14:15], v[16:17]
s_mov_b32 s15, 0x3e5ade15
s_mov_b32 s14, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], s[14:15], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
v_cmp_nlt_f64_e64 s0, 0x40900000, v[10:11]
v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], v[16:17], v[18:19], 1.0
s_and_b32 vcc_lo, s1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[16:17], v[18:19], 1.0
v_ldexp_f64 v[12:13], v[14:15], v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, 0x7ff00000, v13, s0
v_cndmask_b32_e32 v10, 0, v12, vcc_lo
v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[4:5]|
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v11, 0, v13, s1
v_cmp_neq_f64_e64 s1, 0, v[4:5]
v_fma_f64 v[4:5], -v[8:9], v[2:3], 2.0
v_fma_f64 v[2:3], v[8:9], v[2:3], -1.0
v_fma_f64 v[6:7], v[10:11], v[6:7], v[10:11]
v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
s_and_b32 vcc_lo, s1, s0
v_dual_cndmask_b32 v6, 0, v6 :: v_dual_and_b32 v7, 0x7fffffff, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 0x7ff00000, v7, s0
v_cndmask_b32_e64 v7, 0, v7, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[6:7]
v_mad_u64_u32 v[6:7], null, v1, s12, v[0:1]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[6:7]
v_dual_mov_b32 v7, 0x3ff00000 :: v_dual_mov_b32 v6, 0
v_add_co_u32 v8, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b64 v[8:9], v[4:5], off
global_store_b64 v[10:11], v[2:3], off
global_store_b64 v[0:1], v[6:7], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8KparamARPdS_S_ddii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8KparamARPdS_S_ddii, .Lfunc_end0-_Z8KparamARPdS_S_ddii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8KparamARPdS_S_ddii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z8KparamARPdS_S_ddii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KparamAR(double* a, double* b, double* c, double ss, double dtAR, int width, int height)
{
#define eps 1E-12;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i >= width || j >= height) return;
int x= i;
int y= j;
if (i> width/2) x = width-i;
if (j> height/2) y = height-j;
double r = sqrt( (double)x*x + (double)y*y )+Eps;
a[i+j*width] = 2-dtAR*2*ss*r- pow(dtAR*ss*r,2);
b[i+j*width] = -1+dtAR*2*ss*r;
// c[i+j*width] = 50* pow(dtAR,2);
// Correction Jonathan 7-12-16
c[i+j*width] = 1;
} | .text
.file "KparamAR.hip"
.globl _Z23__device_stub__KparamARPdS_S_ddii # -- Begin function _Z23__device_stub__KparamARPdS_S_ddii
.p2align 4, 0x90
.type _Z23__device_stub__KparamARPdS_S_ddii,@function
_Z23__device_stub__KparamARPdS_S_ddii: # @_Z23__device_stub__KparamARPdS_S_ddii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8KparamARPdS_S_ddii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__KparamARPdS_S_ddii, .Lfunc_end0-_Z23__device_stub__KparamARPdS_S_ddii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8KparamARPdS_S_ddii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type MaxThreadsPerBlock,@object # @MaxThreadsPerBlock
.bss
.globl MaxThreadsPerBlock
.p2align 2, 0x0
MaxThreadsPerBlock:
.long 0 # 0x0
.size MaxThreadsPerBlock, 4
.type MaxThreadsX,@object # @MaxThreadsX
.globl MaxThreadsX
.p2align 2, 0x0
MaxThreadsX:
.long 0 # 0x0
.size MaxThreadsX, 4
.type MaxThreadsY,@object # @MaxThreadsY
.globl MaxThreadsY
.p2align 2, 0x0
MaxThreadsY:
.long 0 # 0x0
.size MaxThreadsY, 4
.type _Z8KparamARPdS_S_ddii,@object # @_Z8KparamARPdS_S_ddii
.section .rodata,"a",@progbits
.globl _Z8KparamARPdS_S_ddii
.p2align 3, 0x0
_Z8KparamARPdS_S_ddii:
.quad _Z23__device_stub__KparamARPdS_S_ddii
.size _Z8KparamARPdS_S_ddii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8KparamARPdS_S_ddii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__KparamARPdS_S_ddii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8KparamARPdS_S_ddii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00035ae3_00000000-6_KparamAR.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii
.type _Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii, @function
_Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8KparamARPdS_S_ddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii, .-_Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii
.globl _Z8KparamARPdS_S_ddii
.type _Z8KparamARPdS_S_ddii, @function
_Z8KparamARPdS_S_ddii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8KparamARPdS_S_ddiiPdS_S_ddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8KparamARPdS_S_ddii, .-_Z8KparamARPdS_S_ddii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8KparamARPdS_S_ddii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8KparamARPdS_S_ddii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl MaxThreadsY
.bss
.align 4
.type MaxThreadsY, @object
.size MaxThreadsY, 4
MaxThreadsY:
.zero 4
.globl MaxThreadsX
.align 4
.type MaxThreadsX, @object
.size MaxThreadsX, 4
MaxThreadsX:
.zero 4
.globl MaxThreadsPerBlock
.align 4
.type MaxThreadsPerBlock, @object
.size MaxThreadsPerBlock, 4
MaxThreadsPerBlock:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "KparamAR.hip"
.globl _Z23__device_stub__KparamARPdS_S_ddii # -- Begin function _Z23__device_stub__KparamARPdS_S_ddii
.p2align 4, 0x90
.type _Z23__device_stub__KparamARPdS_S_ddii,@function
_Z23__device_stub__KparamARPdS_S_ddii: # @_Z23__device_stub__KparamARPdS_S_ddii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8KparamARPdS_S_ddii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__KparamARPdS_S_ddii, .Lfunc_end0-_Z23__device_stub__KparamARPdS_S_ddii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8KparamARPdS_S_ddii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type MaxThreadsPerBlock,@object # @MaxThreadsPerBlock
.bss
.globl MaxThreadsPerBlock
.p2align 2, 0x0
MaxThreadsPerBlock:
.long 0 # 0x0
.size MaxThreadsPerBlock, 4
.type MaxThreadsX,@object # @MaxThreadsX
.globl MaxThreadsX
.p2align 2, 0x0
MaxThreadsX:
.long 0 # 0x0
.size MaxThreadsX, 4
.type MaxThreadsY,@object # @MaxThreadsY
.globl MaxThreadsY
.p2align 2, 0x0
MaxThreadsY:
.long 0 # 0x0
.size MaxThreadsY, 4
.type _Z8KparamARPdS_S_ddii,@object # @_Z8KparamARPdS_S_ddii
.section .rodata,"a",@progbits
.globl _Z8KparamARPdS_S_ddii
.p2align 3, 0x0
_Z8KparamARPdS_S_ddii:
.quad _Z23__device_stub__KparamARPdS_S_ddii
.size _Z8KparamARPdS_S_ddii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8KparamARPdS_S_ddii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__KparamARPdS_S_ddii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8KparamARPdS_S_ddii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ void computearray_size(int* block_cntr_array,int *finalsize,int *orig_number_of_char)
{
*finalsize = 0;
for(int i=0;i<*orig_number_of_char;i++)
{
(*finalsize)=(*finalsize) + block_cntr_array[i];
}
}
__device__ int char_huffman_table_gpu[MAX_CHAR][MAX_CHAR-1]; //To write the output from compression in GPU //char *compressedfile_array=0; bool *compressedfile_array=0; bool *finalcompressed_array=0; // To keep track of how many characters each block wrote int *block_cntr_array=0; int *block_cntr_array_check=0; int *d_last_byte_padding=0; int *finalsize=0; int *orig_number_of_char=0; int *huffman_check = (int *)malloc((MAX_CHAR)*(MAX_CHAR-1) *sizeof(int));
bool *d_bool = 0;
bool *h_bool = 0;
__global__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array,int number_of_char)
//__device__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array)
{
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int final_index=0;
if(index_blocks < number_of_char)
{
for(int i=0;i<index_blocks;i++)
{
final_index = final_index+ block_cntr_array[i];
}
for(int i=0;i<block_cntr_array[index_blocks];i++)
{
finalcompressed_array[final_index+i]=compressedfile_array[index_file+i];
}
}
}
__global__ void compress_file_gpu(unsigned char *d_input,bool *compressedfile_array,int *char_huffman_table2,int *block_cntr_array,int* d_last_byte_padding,int *finalsize,int *orig_number_of_char,int number_of_char)
{
//int write_counter=0,
int block_counter=0; //how many bits have been written in specific byte
unsigned char input_char;
//unsigned char output_char = 0x0;
//unsigned char end_of_file = 255;
//unsigned char mask = 0x01; //00000001;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
if(index_blocks < number_of_char)
{
//for(int i=0;i<MAX_CHAR;i++)
//{
//int *row = (int*)((char*)char_huffman_table2 + i * pitch);
//for (int c = 0; c < MAX_CHAR-1; ++c) {
// char_huffman_table_gpu[i][c] = row[c];
//}
//}
input_char = d_input[index_blocks];
for(int i = 0 ; i < (MAX_CHAR - 1) ; i++)
{
if(char_huffman_table2[input_char*255+i] == 0) //detect if current character on particular position has 0 or 1
{
//output_char = output_char << 1; //if 0 then shift bits one position to left (last bit after shifting is 0)
compressedfile_array[index_file+i] = false;
//write_counter++;
block_counter++;
}
else if(char_huffman_table2[input_char*255+i] == 1)
{
//output_char = output_char << 1; //if 1 then shift bits one position to left...
//output_char = output_char | mask; //...and last bit change to: 1
//write_counter++;
compressedfile_array[index_file+i] = true;
block_counter++;
}
else //-1
{
/*if(input_char == end_of_file) //if EOF is detected then write current result to file
{
if(write_counter != 0)
{
output_char = output_char << (8-write_counter);
compressedfile_array[index_file]=output_char;
output_char = 0x0;
}
else //write_counter == 0
{
compressedfile_array[index_file]=output_char;
}
}*/
break;
}
/*if(write_counter == 8) //if result achieved 8 (size of char) then write it to compressed_file
{
compressedfile_array[index_file]=output_char;
output_char = 0x0;
write_counter = 0;
}*/
}
block_cntr_array[index_blocks]=block_counter;
//*d_last_byte_padding = write_counter; //to decompress file we have to know how many bits in last byte have been written
//update_config(write_counter); //TODO to zakomentowac przy ostatecznych pomiarach
computearray_size(block_cntr_array,finalsize,orig_number_of_char);
//final_compression(block_cntr_array,compressedfile_array,finalcompressed_array);
}
} | code for sm_80
Function : _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x198], PT ; /* 0x0000660006007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ SHF.R.S32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x000fe20000011406 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IADD3 R2, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006027a10 */
/* 0x000fc80007f1e0ff */
/*00a0*/ IADD3.X R3, R9, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590009037a10 */
/* 0x000fca00007fe4ff */
/*00b0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000162000c1e1100 */
/*00c0*/ BSSY B1, 0x500 ; /* 0x0000043000017945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD R4, R7, 0xff, R8 ; /* 0x000000ff07047824 */
/* 0x021fc800078e0208 */
/*0110*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*0120*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD R3, R6, 0xff, R8 ; /* 0x000000ff06037824 */
/* 0x001fe200078e0208 */
/*0140*/ BSSY B0, 0x210 ; /* 0x000000c000007945 */
/* 0x000fe80003800000 */
/*0150*/ IADD3 R2, P1, R3, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */
/* 0x000fc80007f3e0ff */
/*0160*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b0003037a11 */
/* 0x000fe400008f0eff */
/*0170*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*0180*/ @!P0 BRA 0x1f0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f05270 */
/*01a0*/ @P0 BREAK B0 ; /* 0x0000000000000942 */
/* 0x000fe20003800000 */
/*01b0*/ @P0 BRA 0x4f0 ; /* 0x0000033000000947 */
/* 0x000fea0003800000 */
/*01c0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fca00078e00ff */
/*01d0*/ STG.E.U8 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0001e2000c101106 */
/*01e0*/ BRA 0x200 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*01f0*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e4000c101106 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000406040a7981 */
/* 0x001ea2000c1e1900 */
/*0220*/ BSSY B2, 0x2e0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0230*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*0240*/ @!P0 BRA 0x2c0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0250*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f05270 */
/*0260*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fd800078e00ff */
/*0270*/ @!P0 STG.E.U8 [R2.64+0x1], R10 ; /* 0x0000010a02008986 */
/* 0x0001e2000c101106 */
/*0280*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0290*/ @!P0 BRA 0x2d0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*02a0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ BRA 0x4f0 ; /* 0x0000023000007947 */
/* 0x000fea0003800000 */
/*02c0*/ STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02007986 */
/* 0x0001e4000c101106 */
/*02d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*02e0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000806040a7981 */
/* 0x001ea2000c1e1900 */
/*02f0*/ BSSY B2, 0x3b0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0300*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*0310*/ @!P0 BRA 0x390 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0320*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f05270 */
/*0330*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fd800078e00ff */
/*0340*/ @!P0 STG.E.U8 [R2.64+0x2], R10 ; /* 0x0000020a02008986 */
/* 0x0001e2000c101106 */
/*0350*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0360*/ @!P0 BRA 0x3a0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fe20007ffe0ff */
/*0380*/ BRA 0x4f0 ; /* 0x0000016000007947 */
/* 0x000fea0003800000 */
/*0390*/ STG.E.U8 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x0001e4000c101106 */
/*03a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*03b0*/ IADD3 R10, R8, 0x3, RZ ; /* 0x00000003080a7810 */
/* 0x001fc80007ffe0ff */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R10, 0xff, PT ; /* 0x000000ff0a00780c */
/* 0x000fda0003f06070 */
/*03d0*/ @P0 BRA 0x4e0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R4, [R4.64+0xc] ; /* 0x00000c0604047981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ BSSY B2, 0x4b0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0400*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f05270 */
/*0410*/ @!P0 BRA 0x490 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f05270 */
/*0430*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fd800078e00ff */
/*0440*/ @!P0 STG.E.U8 [R2.64+0x3], R4 ; /* 0x0000030402008986 */
/* 0x0001e2000c101106 */
/*0450*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0460*/ @!P0 BRA 0x4a0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0470*/ IADD3 R0, R0, 0x3, RZ ; /* 0x0000000300007810 */
/* 0x000fe20007ffe0ff */
/*0480*/ BRA 0x4f0 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0490*/ STG.E.U8 [R2.64+0x3], RZ ; /* 0x000003ff02007986 */
/* 0x0001e4000c101106 */
/*04a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*04b0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ BRA 0xf0 ; /* 0xfffffc1000007947 */
/* 0x000fea000383ffff */
/*04e0*/ IADD3 R0, R0, 0x3, RZ ; /* 0x0000000300007810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0500*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0510*/ LEA R4, P0, R6.reuse, c[0x0][0x178], 0x2 ; /* 0x00005e0006047a11 */
/* 0x041fe200078010ff */
/*0520*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fe400078e00ff */
/*0530*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fe200078e00ff */
/*0540*/ LEA.HI.X R5, R6, c[0x0][0x17c], R9, 0x2, P0 ; /* 0x00005f0006057a11 */
/* 0x000fe200000f1409 */
/*0550*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff087624 */
/* 0x000fc400078e00ff */
/*0560*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff097624 */
/* 0x000fe400078e00ff */
/*0570*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x0001e8000c101906 */
/*0580*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101906 */
/*0590*/ LDG.E R6, [R8.64] ; /* 0x0000000608067981 */
/* 0x000ea4000c1e1900 */
/*05a0*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f06270 */
/*05b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x001fe200078e00ff */
/*05d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*05e0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*05f0*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fca000f8e00ff */
/*0600*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0610*/ IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104077824 */
/* 0x004fca00078e0207 */
/*0620*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101906 */
/*0630*/ LDG.E R0, [R8.64] ; /* 0x0000000608007981 */
/* 0x000ea2000c1e1900 */
/*0640*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*0650*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fc8000ff1e03f */
/*0660*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0670*/ ISETP.LE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x004fda000bf03270 */
/*0680*/ @!P0 BRA 0x5e0 ; /* 0xffffff5000008947 */
/* 0x001fea000383ffff */
/*0690*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17final_compressionPiPbS0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B2, 0x760 ; /* 0x000006d000027945 */
/* 0x000fe20003800000 */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd400078e00ff */
/*00a0*/ @!P0 BRA 0x750 ; /* 0x000006a000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ BSSY B1, 0x680 ; /* 0x000005b000017945 */
/* 0x000fe20003800000 */
/*00d0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd800078e00ff */
/*0110*/ @!P0 BRA 0x670 ; /* 0x0000055000008947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.IADD R7, R0, 0x1, -R5 ; /* 0x0000000100077824 */
/* 0x000fe200078e0a05 */
/*0130*/ BSSY B0, 0x590 ; /* 0x0000045000007945 */
/* 0x000fe20003800000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0160*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fd800078e00ff */
/*0180*/ @!P0 BRA 0x580 ; /* 0x000003f000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe20003f24270 */
/*01a0*/ BSSY B3, 0x3e0 ; /* 0x0000023000037945 */
/* 0x000fe20003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x3d0 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000404020c7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R15, [R2.64+0x8] ; /* 0x00000804020f7981 */
/* 0x0000e8000c1e1900 */
/*0210*/ LDG.E R14, [R2.64+0xc] ; /* 0x00000c04020e7981 */
/* 0x0000e8000c1e1900 */
/*0220*/ LDG.E R17, [R2.64+0x10] ; /* 0x0000100402117981 */
/* 0x000128000c1e1900 */
/*0230*/ LDG.E R16, [R2.64+0x14] ; /* 0x0000140402107981 */
/* 0x000128000c1e1900 */
/*0240*/ LDG.E R19, [R2.64+0x18] ; /* 0x0000180402137981 */
/* 0x000168000c1e1900 */
/*0250*/ LDG.E R18, [R2.64+0x1c] ; /* 0x00001c0402127981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R21, [R2.64+0x20] ; /* 0x0000200402157981 */
/* 0x000168000c1e1900 */
/*0270*/ LDG.E R20, [R2.64+0x24] ; /* 0x0000240402147981 */
/* 0x000168000c1e1900 */
/*0280*/ LDG.E R23, [R2.64+0x28] ; /* 0x0000280402177981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R22, [R2.64+0x2c] ; /* 0x00002c0402167981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R11, [R2.64+0x30] ; /* 0x00003004020b7981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R10, [R2.64+0x34] ; /* 0x00003404020a7981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R9, [R2.64+0x38] ; /* 0x0000380402097981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R8, [R2.64+0x3c] ; /* 0x00003c0402087981 */
/* 0x000162000c1e1900 */
/*02e0*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc40007ffe0ff */
/*02f0*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0300*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*0310*/ IADD3 R12, R12, R13, R4 ; /* 0x0000000d0c0c7210 */
/* 0x004fe40007ffe004 */
/*0320*/ IADD3 R13, P2, R2, 0x40, RZ ; /* 0x00000040020d7810 */
/* 0x000fca0007f5e0ff */
/*0330*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*0340*/ IADD3 R12, R14, R15, R12 ; /* 0x0000000f0e0c7210 */
/* 0x008fe20007ffe00c */
/*0350*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000d */
/*0360*/ IADD3 R12, R16, R17, R12 ; /* 0x00000011100c7210 */
/* 0x010fc80007ffe00c */
/*0370*/ IADD3 R12, R18, R19, R12 ; /* 0x00000013120c7210 */
/* 0x020fc80007ffe00c */
/*0380*/ IADD3 R12, R20, R21, R12 ; /* 0x00000015140c7210 */
/* 0x000fc80007ffe00c */
/*0390*/ IADD3 R12, R22, R23, R12 ; /* 0x00000017160c7210 */
/* 0x000fc80007ffe00c */
/*03a0*/ IADD3 R10, R10, R11, R12 ; /* 0x0000000b0a0a7210 */
/* 0x000fc80007ffe00c */
/*03b0*/ IADD3 R4, R8, R9, R10 ; /* 0x0000000908047210 */
/* 0x000fe20007ffe00a */
/*03c0*/ @P1 BRA 0x1e0 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*03d0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*03e0*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fe20003f24270 */
/*03f0*/ BSSY B3, 0x550 ; /* 0x0000015000037945 */
/* 0x000fd80003800000 */
/*0400*/ @!P1 BRA 0x540 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x0000e8000c1e1900 */
/*0440*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c04020a7981 */
/* 0x0000e8000c1e1900 */
/*0450*/ LDG.E R13, [R2.64+0x10] ; /* 0x00001004020d7981 */
/* 0x000128000c1e1900 */
/*0460*/ LDG.E R12, [R2.64+0x14] ; /* 0x00001404020c7981 */
/* 0x000128000c1e1900 */
/*0470*/ LDG.E R15, [R2.64+0x18] ; /* 0x00001804020f7981 */
/* 0x000168000c1e1900 */
/*0480*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000162000c1e1900 */
/*0490*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*04a0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ IADD3 R8, R8, R9, R4 ; /* 0x0000000908087210 */
/* 0x004fe40007ffe004 */
/*04d0*/ IADD3 R9, P1, R2, 0x20, RZ ; /* 0x0000002002097810 */
/* 0x000fca0007f3e0ff */
/*04e0*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0009 */
/*04f0*/ IADD3 R8, R10, R11, R8 ; /* 0x0000000b0a087210 */
/* 0x008fe20007ffe008 */
/*0500*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc800008e0603 */
/*0510*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0520*/ IADD3 R8, R12, R13, R8 ; /* 0x0000000d0c087210 */
/* 0x010fc80007ffe008 */
/*0530*/ IADD3 R4, R14, R15, R8 ; /* 0x0000000f0e047210 */
/* 0x020fe40007ffe008 */
/*0540*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*0560*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0570*/ @!P0 BRA 0x670 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0580*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x0000a8000c1e1900 */
/*05a0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x0000a8000c1e1900 */
/*05b0*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x0000e8000c1e1900 */
/*05c0*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c04020a7981 */
/* 0x0000e2000c1e1900 */
/*05d0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc40007ffe0ff */
/*05e0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f3e0ff */
/*05f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*0600*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007ffe0ff */
/*0610*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0603 */
/*0620*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000c */
/*0630*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0640*/ IADD3 R4, R8, R9, R4 ; /* 0x0000000908047210 */
/* 0x004fc80007ffe004 */
/*0650*/ IADD3 R4, R10, R11, R4 ; /* 0x0000000b0a047210 */
/* 0x008fe20007ffe004 */
/*0660*/ @P0 BRA 0x590 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0670*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0690*/ @!P0 BRA 0x750 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*06b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*06c0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*06d0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0006 */
/*06e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0710*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f05270 */
/*0720*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*0730*/ IMAD.IADD R4, R3, 0x1, R4 ; /* 0x0000000103047824 */
/* 0x004fd000078e0204 */
/*0740*/ @P0 BRA 0x6c0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0750*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0760*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0770*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0780*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0790*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*07a0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x004fda0003f06270 */
/*07b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07c0*/ IMAD R0, R0, 0xff, RZ ; /* 0x000000ff00007824 */
/* 0x000fe200078e02ff */
/*07d0*/ IADD3 R8, P1, R4, c[0x0][0x170], RZ ; /* 0x00005c0004087a10 */
/* 0x000fe20007f3e0ff */
/*07e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*07f0*/ IADD3 R10, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a00000a7a10 */
/* 0x000fe40007f1e0ff */
/*0800*/ LEA.HI.X.SX32 R11, R4, c[0x0][0x174], 0x1, P1 ; /* 0x00005d00040b7a11 */
/* 0x000fe400008f0eff */
/*0810*/ LEA.HI.X.SX32 R13, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b00000d7a11 */
/* 0x000fc600000f0eff */
/*0820*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000a */
/*0830*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000d */
/*0840*/ LDG.E.U8 R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x0000a4000c1e1100 */
/*0850*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0008 */
/*0860*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000b */
/*0870*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c101104 */
/*0880*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0890*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R10, P1, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe40007f3e0ff */
/*08b0*/ IADD3 R8, P2, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fc60007f5e0ff */
/*08c0*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e060d */
/*08d0*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e060b */
/*08e0*/ ISETP.GE.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x004fda0003f06270 */
/*08f0*/ @!P0 BRA 0x820 ; /* 0xffffff2000008947 */
/* 0x001fea000383ffff */
/*0900*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0910*/ BRA 0x910; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ void computearray_size(int* block_cntr_array,int *finalsize,int *orig_number_of_char)
{
*finalsize = 0;
for(int i=0;i<*orig_number_of_char;i++)
{
(*finalsize)=(*finalsize) + block_cntr_array[i];
}
}
__device__ int char_huffman_table_gpu[MAX_CHAR][MAX_CHAR-1]; //To write the output from compression in GPU //char *compressedfile_array=0; bool *compressedfile_array=0; bool *finalcompressed_array=0; // To keep track of how many characters each block wrote int *block_cntr_array=0; int *block_cntr_array_check=0; int *d_last_byte_padding=0; int *finalsize=0; int *orig_number_of_char=0; int *huffman_check = (int *)malloc((MAX_CHAR)*(MAX_CHAR-1) *sizeof(int));
bool *d_bool = 0;
bool *h_bool = 0;
__global__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array,int number_of_char)
//__device__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array)
{
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int final_index=0;
if(index_blocks < number_of_char)
{
for(int i=0;i<index_blocks;i++)
{
final_index = final_index+ block_cntr_array[i];
}
for(int i=0;i<block_cntr_array[index_blocks];i++)
{
finalcompressed_array[final_index+i]=compressedfile_array[index_file+i];
}
}
}
__global__ void compress_file_gpu(unsigned char *d_input,bool *compressedfile_array,int *char_huffman_table2,int *block_cntr_array,int* d_last_byte_padding,int *finalsize,int *orig_number_of_char,int number_of_char)
{
//int write_counter=0,
int block_counter=0; //how many bits have been written in specific byte
unsigned char input_char;
//unsigned char output_char = 0x0;
//unsigned char end_of_file = 255;
//unsigned char mask = 0x01; //00000001;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
if(index_blocks < number_of_char)
{
//for(int i=0;i<MAX_CHAR;i++)
//{
//int *row = (int*)((char*)char_huffman_table2 + i * pitch);
//for (int c = 0; c < MAX_CHAR-1; ++c) {
// char_huffman_table_gpu[i][c] = row[c];
//}
//}
input_char = d_input[index_blocks];
for(int i = 0 ; i < (MAX_CHAR - 1) ; i++)
{
if(char_huffman_table2[input_char*255+i] == 0) //detect if current character on particular position has 0 or 1
{
//output_char = output_char << 1; //if 0 then shift bits one position to left (last bit after shifting is 0)
compressedfile_array[index_file+i] = false;
//write_counter++;
block_counter++;
}
else if(char_huffman_table2[input_char*255+i] == 1)
{
//output_char = output_char << 1; //if 1 then shift bits one position to left...
//output_char = output_char | mask; //...and last bit change to: 1
//write_counter++;
compressedfile_array[index_file+i] = true;
block_counter++;
}
else //-1
{
/*if(input_char == end_of_file) //if EOF is detected then write current result to file
{
if(write_counter != 0)
{
output_char = output_char << (8-write_counter);
compressedfile_array[index_file]=output_char;
output_char = 0x0;
}
else //write_counter == 0
{
compressedfile_array[index_file]=output_char;
}
}*/
break;
}
/*if(write_counter == 8) //if result achieved 8 (size of char) then write it to compressed_file
{
compressedfile_array[index_file]=output_char;
output_char = 0x0;
write_counter = 0;
}*/
}
block_cntr_array[index_blocks]=block_counter;
//*d_last_byte_padding = write_counter; //to decompress file we have to know how many bits in last byte have been written
//update_config(write_counter); //TODO to zakomentowac przy ostatecznych pomiarach
computearray_size(block_cntr_array,finalsize,orig_number_of_char);
//final_compression(block_cntr_array,compressedfile_array,finalcompressed_array);
}
} | .file "tmpxft_000c926a_00000000-6_compress_file_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17computearray_sizePiS_S_
.type _Z17computearray_sizePiS_S_, @function
_Z17computearray_sizePiS_S_:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17computearray_sizePiS_S_, .-_Z17computearray_sizePiS_S_
.globl _Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i
.type _Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i, @function
_Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17final_compressionPiPbS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i, .-_Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i
.globl _Z17final_compressionPiPbS0_i
.type _Z17final_compressionPiPbS0_i, @function
_Z17final_compressionPiPbS0_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17final_compressionPiPbS0_i, .-_Z17final_compressionPiPbS0_i
.globl _Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i
.type _Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i, @function
_Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i:
.LFB2054:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i, .-_Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i
.globl _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.type _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i, @function
_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i, .-_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z17final_compressionPiPbS0_i"
.LC2:
.string "char_huffman_table_gpu"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17final_compressionPiPbS0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $261120, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL22char_huffman_table_gpu(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl h_bool
.bss
.align 8
.type h_bool, @object
.size h_bool, 8
h_bool:
.zero 8
.globl d_bool
.align 8
.type d_bool, @object
.size d_bool, 8
d_bool:
.zero 8
.local _ZL22char_huffman_table_gpu
.comm _ZL22char_huffman_table_gpu,261120,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ void computearray_size(int* block_cntr_array,int *finalsize,int *orig_number_of_char)
{
*finalsize = 0;
for(int i=0;i<*orig_number_of_char;i++)
{
(*finalsize)=(*finalsize) + block_cntr_array[i];
}
}
__device__ int char_huffman_table_gpu[MAX_CHAR][MAX_CHAR-1]; //To write the output from compression in GPU //char *compressedfile_array=0; bool *compressedfile_array=0; bool *finalcompressed_array=0; // To keep track of how many characters each block wrote int *block_cntr_array=0; int *block_cntr_array_check=0; int *d_last_byte_padding=0; int *finalsize=0; int *orig_number_of_char=0; int *huffman_check = (int *)malloc((MAX_CHAR)*(MAX_CHAR-1) *sizeof(int));
bool *d_bool = 0;
bool *h_bool = 0;
__global__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array,int number_of_char)
//__device__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array)
{
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int final_index=0;
if(index_blocks < number_of_char)
{
for(int i=0;i<index_blocks;i++)
{
final_index = final_index+ block_cntr_array[i];
}
for(int i=0;i<block_cntr_array[index_blocks];i++)
{
finalcompressed_array[final_index+i]=compressedfile_array[index_file+i];
}
}
}
__global__ void compress_file_gpu(unsigned char *d_input,bool *compressedfile_array,int *char_huffman_table2,int *block_cntr_array,int* d_last_byte_padding,int *finalsize,int *orig_number_of_char,int number_of_char)
{
//int write_counter=0,
int block_counter=0; //how many bits have been written in specific byte
unsigned char input_char;
//unsigned char output_char = 0x0;
//unsigned char end_of_file = 255;
//unsigned char mask = 0x01; //00000001;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
if(index_blocks < number_of_char)
{
//for(int i=0;i<MAX_CHAR;i++)
//{
//int *row = (int*)((char*)char_huffman_table2 + i * pitch);
//for (int c = 0; c < MAX_CHAR-1; ++c) {
// char_huffman_table_gpu[i][c] = row[c];
//}
//}
input_char = d_input[index_blocks];
for(int i = 0 ; i < (MAX_CHAR - 1) ; i++)
{
if(char_huffman_table2[input_char*255+i] == 0) //detect if current character on particular position has 0 or 1
{
//output_char = output_char << 1; //if 0 then shift bits one position to left (last bit after shifting is 0)
compressedfile_array[index_file+i] = false;
//write_counter++;
block_counter++;
}
else if(char_huffman_table2[input_char*255+i] == 1)
{
//output_char = output_char << 1; //if 1 then shift bits one position to left...
//output_char = output_char | mask; //...and last bit change to: 1
//write_counter++;
compressedfile_array[index_file+i] = true;
block_counter++;
}
else //-1
{
/*if(input_char == end_of_file) //if EOF is detected then write current result to file
{
if(write_counter != 0)
{
output_char = output_char << (8-write_counter);
compressedfile_array[index_file]=output_char;
output_char = 0x0;
}
else //write_counter == 0
{
compressedfile_array[index_file]=output_char;
}
}*/
break;
}
/*if(write_counter == 8) //if result achieved 8 (size of char) then write it to compressed_file
{
compressedfile_array[index_file]=output_char;
output_char = 0x0;
write_counter = 0;
}*/
}
block_cntr_array[index_blocks]=block_counter;
//*d_last_byte_padding = write_counter; //to decompress file we have to know how many bits in last byte have been written
//update_config(write_counter); //TODO to zakomentowac przy ostatecznych pomiarach
computearray_size(block_cntr_array,finalsize,orig_number_of_char);
//final_compression(block_cntr_array,compressedfile_array,finalcompressed_array);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void computearray_size(int* block_cntr_array,int *finalsize,int *orig_number_of_char)
{
*finalsize = 0;
for(int i=0;i<*orig_number_of_char;i++)
{
(*finalsize)=(*finalsize) + block_cntr_array[i];
}
}
__device__ int char_huffman_table_gpu[MAX_CHAR][MAX_CHAR-1]; //To write the output from compression in GPU //char *compressedfile_array=0; bool *compressedfile_array=0; bool *finalcompressed_array=0; // To keep track of how many characters each block wrote int *block_cntr_array=0; int *block_cntr_array_check=0; int *d_last_byte_padding=0; int *finalsize=0; int *orig_number_of_char=0; int *huffman_check = (int *)malloc((MAX_CHAR)*(MAX_CHAR-1) *sizeof(int));
bool *d_bool = 0;
bool *h_bool = 0;
__global__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array,int number_of_char)
//__device__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array)
{
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int final_index=0;
if(index_blocks < number_of_char)
{
for(int i=0;i<index_blocks;i++)
{
final_index = final_index+ block_cntr_array[i];
}
for(int i=0;i<block_cntr_array[index_blocks];i++)
{
finalcompressed_array[final_index+i]=compressedfile_array[index_file+i];
}
}
}
__global__ void compress_file_gpu(unsigned char *d_input,bool *compressedfile_array,int *char_huffman_table2,int *block_cntr_array,int* d_last_byte_padding,int *finalsize,int *orig_number_of_char,int number_of_char)
{
//int write_counter=0,
int block_counter=0; //how many bits have been written in specific byte
unsigned char input_char;
//unsigned char output_char = 0x0;
//unsigned char end_of_file = 255;
//unsigned char mask = 0x01; //00000001;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
if(index_blocks < number_of_char)
{
//for(int i=0;i<MAX_CHAR;i++)
//{
//int *row = (int*)((char*)char_huffman_table2 + i * pitch);
//for (int c = 0; c < MAX_CHAR-1; ++c) {
// char_huffman_table_gpu[i][c] = row[c];
//}
//}
input_char = d_input[index_blocks];
for(int i = 0 ; i < (MAX_CHAR - 1) ; i++)
{
if(char_huffman_table2[input_char*255+i] == 0) //detect if current character on particular position has 0 or 1
{
//output_char = output_char << 1; //if 0 then shift bits one position to left (last bit after shifting is 0)
compressedfile_array[index_file+i] = false;
//write_counter++;
block_counter++;
}
else if(char_huffman_table2[input_char*255+i] == 1)
{
//output_char = output_char << 1; //if 1 then shift bits one position to left...
//output_char = output_char | mask; //...and last bit change to: 1
//write_counter++;
compressedfile_array[index_file+i] = true;
block_counter++;
}
else //-1
{
/*if(input_char == end_of_file) //if EOF is detected then write current result to file
{
if(write_counter != 0)
{
output_char = output_char << (8-write_counter);
compressedfile_array[index_file]=output_char;
output_char = 0x0;
}
else //write_counter == 0
{
compressedfile_array[index_file]=output_char;
}
}*/
break;
}
/*if(write_counter == 8) //if result achieved 8 (size of char) then write it to compressed_file
{
compressedfile_array[index_file]=output_char;
output_char = 0x0;
write_counter = 0;
}*/
}
block_cntr_array[index_blocks]=block_counter;
//*d_last_byte_padding = write_counter; //to decompress file we have to know how many bits in last byte have been written
//update_config(write_counter); //TODO to zakomentowac przy ostatecznych pomiarach
computearray_size(block_cntr_array,finalsize,orig_number_of_char);
//final_compression(block_cntr_array,compressedfile_array,finalcompressed_array);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void computearray_size(int* block_cntr_array,int *finalsize,int *orig_number_of_char)
{
*finalsize = 0;
for(int i=0;i<*orig_number_of_char;i++)
{
(*finalsize)=(*finalsize) + block_cntr_array[i];
}
}
__device__ int char_huffman_table_gpu[MAX_CHAR][MAX_CHAR-1]; //To write the output from compression in GPU //char *compressedfile_array=0; bool *compressedfile_array=0; bool *finalcompressed_array=0; // To keep track of how many characters each block wrote int *block_cntr_array=0; int *block_cntr_array_check=0; int *d_last_byte_padding=0; int *finalsize=0; int *orig_number_of_char=0; int *huffman_check = (int *)malloc((MAX_CHAR)*(MAX_CHAR-1) *sizeof(int));
bool *d_bool = 0;
bool *h_bool = 0;
__global__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array,int number_of_char)
//__device__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array)
{
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int final_index=0;
if(index_blocks < number_of_char)
{
for(int i=0;i<index_blocks;i++)
{
final_index = final_index+ block_cntr_array[i];
}
for(int i=0;i<block_cntr_array[index_blocks];i++)
{
finalcompressed_array[final_index+i]=compressedfile_array[index_file+i];
}
}
}
__global__ void compress_file_gpu(unsigned char *d_input,bool *compressedfile_array,int *char_huffman_table2,int *block_cntr_array,int* d_last_byte_padding,int *finalsize,int *orig_number_of_char,int number_of_char)
{
//int write_counter=0,
int block_counter=0; //how many bits have been written in specific byte
unsigned char input_char;
//unsigned char output_char = 0x0;
//unsigned char end_of_file = 255;
//unsigned char mask = 0x01; //00000001;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
if(index_blocks < number_of_char)
{
//for(int i=0;i<MAX_CHAR;i++)
//{
//int *row = (int*)((char*)char_huffman_table2 + i * pitch);
//for (int c = 0; c < MAX_CHAR-1; ++c) {
// char_huffman_table_gpu[i][c] = row[c];
//}
//}
input_char = d_input[index_blocks];
for(int i = 0 ; i < (MAX_CHAR - 1) ; i++)
{
if(char_huffman_table2[input_char*255+i] == 0) //detect if current character on particular position has 0 or 1
{
//output_char = output_char << 1; //if 0 then shift bits one position to left (last bit after shifting is 0)
compressedfile_array[index_file+i] = false;
//write_counter++;
block_counter++;
}
else if(char_huffman_table2[input_char*255+i] == 1)
{
//output_char = output_char << 1; //if 1 then shift bits one position to left...
//output_char = output_char | mask; //...and last bit change to: 1
//write_counter++;
compressedfile_array[index_file+i] = true;
block_counter++;
}
else //-1
{
/*if(input_char == end_of_file) //if EOF is detected then write current result to file
{
if(write_counter != 0)
{
output_char = output_char << (8-write_counter);
compressedfile_array[index_file]=output_char;
output_char = 0x0;
}
else //write_counter == 0
{
compressedfile_array[index_file]=output_char;
}
}*/
break;
}
/*if(write_counter == 8) //if result achieved 8 (size of char) then write it to compressed_file
{
compressedfile_array[index_file]=output_char;
output_char = 0x0;
write_counter = 0;
}*/
}
block_cntr_array[index_blocks]=block_counter;
//*d_last_byte_padding = write_counter; //to decompress file we have to know how many bits in last byte have been written
//update_config(write_counter); //TODO to zakomentowac przy ostatecznych pomiarach
computearray_size(block_cntr_array,finalsize,orig_number_of_char);
//final_compression(block_cntr_array,compressedfile_array,finalcompressed_array);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17final_compressionPiPbS0_i
.globl _Z17final_compressionPiPbS0_i
.p2align 8
.type _Z17final_compressionPiPbS0_i,@function
_Z17final_compressionPiPbS0_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_8
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s7, 0
s_mov_b32 s6, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v2, v1
s_waitcnt lgkmcnt(0)
s_mov_b64 s[4:5], s[2:3]
s_mov_b32 s8, 0
.LBB0_3:
s_load_b32 s9, s[4:5], 0x0
v_add_nc_u32_e32 v2, -1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_waitcnt lgkmcnt(0)
s_add_i32 s8, s9, s8
s_add_u32 s4, s4, 4
v_mov_b32_e32 v0, s8
s_addc_u32 s5, s5, 0
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s7
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s6
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, 0
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v2, v1, 0xff
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_7:
global_load_u8 v5, v[2:3], off
v_add_nc_u32_e32 v4, -1, v4
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v5, off
v_add_co_u32 v0, s0, v0, 1
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17final_compressionPiPbS0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17final_compressionPiPbS0_i, .Lfunc_end0-_Z17final_compressionPiPbS0_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.globl _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.p2align 8
.type _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i,@function
_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s3, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_16
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mul_i32 s2, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mulk_i32 s2, 0xff
v_mad_u32_u24 v0, v0, 0xff, s2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
s_mov_b32 s5, 0
global_load_u8 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_u32_u24_e32 v3, 0xff, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
v_add_co_u32 v3, s2, s8, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s9, 0, s2
s_mov_b32 s2, 0
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s8, exec_lo, s11
v_mov_b32_e32 v6, s10
s_or_b32 s2, s8, s2
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s8, s4, exec_lo
s_or_b32 s3, s3, s8
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB1_11
.LBB1_3:
global_load_b32 v7, v[3:4], off
s_mov_b32 s8, 0
s_mov_b32 s11, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v7
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB1_7
s_mov_b32 s9, exec_lo
v_cmpx_eq_u32_e32 1, v7
s_mov_b32 s8, exec_lo
s_mov_b32 s10, 1
s_or_b32 exec_lo, exec_lo, s9
s_mov_b32 s9, -1
s_and_b32 s8, s8, exec_lo
.LBB1_7:
s_or_saveexec_b32 s11, s11
v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s10
s_xor_b32 exec_lo, exec_lo, s11
v_cmp_eq_u32_e32 vcc_lo, 0, v7
v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, 0
s_and_not1_b32 s8, s8, exec_lo
s_or_b32 s9, s9, exec_lo
s_and_b32 s10, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s10
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s4, s4, exec_lo
s_and_b32 s9, s9, exec_lo
s_mov_b32 s11, -1
s_or_b32 s4, s4, s9
s_and_saveexec_b32 s9, s8
s_cbranch_execz .LBB1_2
v_add_nc_u32_e32 v5, s5, v0
v_add_co_u32 v3, vcc_lo, v3, 4
s_add_i32 s8, s5, 1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v8, 31, v5
v_add_co_u32 v7, vcc_lo, s6, v5
s_cmpk_eq_i32 s8, 0xff
v_mov_b32_e32 v5, s5
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_cselect_b32 s11, -1, 0
s_movk_i32 s10, 0xff
s_and_not1_b32 s4, s4, exec_lo
s_or_not1_b32 s11, s11, exec_lo
s_mov_b32 s5, s8
global_store_b8 v[7:8], v6, off
s_branch .LBB1_2
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
v_mov_b32_e32 v6, v5
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_mov_b32_e32 v0, 0
global_store_b32 v[2:3], v6, off
global_store_b32 v0, v0, s[0:1]
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v1
s_cbranch_vccnz .LBB1_16
s_mov_b32 s6, 0
.LBB1_15:
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[4:5]
s_add_i32 s6, s6, 1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, s6, v1
s_cbranch_vccnz .LBB1_15
.LBB1_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i, .Lfunc_end1-_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected char_huffman_table_gpu
.type char_huffman_table_gpu,@object
.section .bss,"aw",@nobits
.globl char_huffman_table_gpu
.p2align 4, 0x0
char_huffman_table_gpu:
.zero 261120
.size char_huffman_table_gpu, 261120
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17final_compressionPiPbS0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17final_compressionPiPbS0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void computearray_size(int* block_cntr_array,int *finalsize,int *orig_number_of_char)
{
*finalsize = 0;
for(int i=0;i<*orig_number_of_char;i++)
{
(*finalsize)=(*finalsize) + block_cntr_array[i];
}
}
__device__ int char_huffman_table_gpu[MAX_CHAR][MAX_CHAR-1]; //To write the output from compression in GPU //char *compressedfile_array=0; bool *compressedfile_array=0; bool *finalcompressed_array=0; // To keep track of how many characters each block wrote int *block_cntr_array=0; int *block_cntr_array_check=0; int *d_last_byte_padding=0; int *finalsize=0; int *orig_number_of_char=0; int *huffman_check = (int *)malloc((MAX_CHAR)*(MAX_CHAR-1) *sizeof(int));
bool *d_bool = 0;
bool *h_bool = 0;
__global__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array,int number_of_char)
//__device__ void final_compression(int *block_cntr_array,bool *compressedfile_array,bool *finalcompressed_array)
{
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int final_index=0;
if(index_blocks < number_of_char)
{
for(int i=0;i<index_blocks;i++)
{
final_index = final_index+ block_cntr_array[i];
}
for(int i=0;i<block_cntr_array[index_blocks];i++)
{
finalcompressed_array[final_index+i]=compressedfile_array[index_file+i];
}
}
}
__global__ void compress_file_gpu(unsigned char *d_input,bool *compressedfile_array,int *char_huffman_table2,int *block_cntr_array,int* d_last_byte_padding,int *finalsize,int *orig_number_of_char,int number_of_char)
{
//int write_counter=0,
int block_counter=0; //how many bits have been written in specific byte
unsigned char input_char;
//unsigned char output_char = 0x0;
//unsigned char end_of_file = 255;
//unsigned char mask = 0x01; //00000001;
int index_file=(blockIdx.x*blockDim.x+threadIdx.x)*255;
int index_blocks=blockIdx.x*blockDim.x+threadIdx.x;
if(index_blocks < number_of_char)
{
//for(int i=0;i<MAX_CHAR;i++)
//{
//int *row = (int*)((char*)char_huffman_table2 + i * pitch);
//for (int c = 0; c < MAX_CHAR-1; ++c) {
// char_huffman_table_gpu[i][c] = row[c];
//}
//}
input_char = d_input[index_blocks];
for(int i = 0 ; i < (MAX_CHAR - 1) ; i++)
{
if(char_huffman_table2[input_char*255+i] == 0) //detect if current character on particular position has 0 or 1
{
//output_char = output_char << 1; //if 0 then shift bits one position to left (last bit after shifting is 0)
compressedfile_array[index_file+i] = false;
//write_counter++;
block_counter++;
}
else if(char_huffman_table2[input_char*255+i] == 1)
{
//output_char = output_char << 1; //if 1 then shift bits one position to left...
//output_char = output_char | mask; //...and last bit change to: 1
//write_counter++;
compressedfile_array[index_file+i] = true;
block_counter++;
}
else //-1
{
/*if(input_char == end_of_file) //if EOF is detected then write current result to file
{
if(write_counter != 0)
{
output_char = output_char << (8-write_counter);
compressedfile_array[index_file]=output_char;
output_char = 0x0;
}
else //write_counter == 0
{
compressedfile_array[index_file]=output_char;
}
}*/
break;
}
/*if(write_counter == 8) //if result achieved 8 (size of char) then write it to compressed_file
{
compressedfile_array[index_file]=output_char;
output_char = 0x0;
write_counter = 0;
}*/
}
block_cntr_array[index_blocks]=block_counter;
//*d_last_byte_padding = write_counter; //to decompress file we have to know how many bits in last byte have been written
//update_config(write_counter); //TODO to zakomentowac przy ostatecznych pomiarach
computearray_size(block_cntr_array,finalsize,orig_number_of_char);
//final_compression(block_cntr_array,compressedfile_array,finalcompressed_array);
}
} | .text
.file "compress_file_gpu.hip"
.globl _Z32__device_stub__final_compressionPiPbS0_i # -- Begin function _Z32__device_stub__final_compressionPiPbS0_i
.p2align 4, 0x90
.type _Z32__device_stub__final_compressionPiPbS0_i,@function
_Z32__device_stub__final_compressionPiPbS0_i: # @_Z32__device_stub__final_compressionPiPbS0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17final_compressionPiPbS0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__final_compressionPiPbS0_i, .Lfunc_end0-_Z32__device_stub__final_compressionPiPbS0_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i # -- Begin function _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i
.p2align 4, 0x90
.type _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i,@function
_Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i: # @_Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i, .Lfunc_end1-_Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17final_compressionPiPbS0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $char_huffman_table_gpu, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $261120, %r9d # imm = 0x3FC00
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type char_huffman_table_gpu,@object # @char_huffman_table_gpu
.local char_huffman_table_gpu
.comm char_huffman_table_gpu,261120,16
.type d_bool,@object # @d_bool
.bss
.globl d_bool
.p2align 3, 0x0
d_bool:
.quad 0
.size d_bool, 8
.type h_bool,@object # @h_bool
.globl h_bool
.p2align 3, 0x0
h_bool:
.quad 0
.size h_bool, 8
.type _Z17final_compressionPiPbS0_i,@object # @_Z17final_compressionPiPbS0_i
.section .rodata,"a",@progbits
.globl _Z17final_compressionPiPbS0_i
.p2align 3, 0x0
_Z17final_compressionPiPbS0_i:
.quad _Z32__device_stub__final_compressionPiPbS0_i
.size _Z17final_compressionPiPbS0_i, 8
.type _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i,@object # @_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.globl _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.p2align 3, 0x0
_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i:
.quad _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i
.size _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17final_compressionPiPbS0_i"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i"
.size .L__unnamed_2, 41
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "char_huffman_table_gpu"
.size .L__unnamed_3, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__final_compressionPiPbS0_i
.addrsig_sym _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym char_huffman_table_gpu
.addrsig_sym _Z17final_compressionPiPbS0_i
.addrsig_sym _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c926a_00000000-6_compress_file_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17computearray_sizePiS_S_
.type _Z17computearray_sizePiS_S_, @function
_Z17computearray_sizePiS_S_:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17computearray_sizePiS_S_, .-_Z17computearray_sizePiS_S_
.globl _Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i
.type _Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i, @function
_Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17final_compressionPiPbS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i, .-_Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i
.globl _Z17final_compressionPiPbS0_i
.type _Z17final_compressionPiPbS0_i, @function
_Z17final_compressionPiPbS0_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17final_compressionPiPbS0_iPiPbS0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17final_compressionPiPbS0_i, .-_Z17final_compressionPiPbS0_i
.globl _Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i
.type _Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i, @function
_Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i:
.LFB2054:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i, .-_Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i
.globl _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.type _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i, @function
_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z17compress_file_gpuPhPbPiS1_S1_S1_S1_iPhPbPiS1_S1_S1_S1_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i, .-_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z17final_compressionPiPbS0_i"
.LC2:
.string "char_huffman_table_gpu"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17final_compressionPiPbS0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $261120, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL22char_huffman_table_gpu(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl h_bool
.bss
.align 8
.type h_bool, @object
.size h_bool, 8
h_bool:
.zero 8
.globl d_bool
.align 8
.type d_bool, @object
.size d_bool, 8
d_bool:
.zero 8
.local _ZL22char_huffman_table_gpu
.comm _ZL22char_huffman_table_gpu,261120,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "compress_file_gpu.hip"
.globl _Z32__device_stub__final_compressionPiPbS0_i # -- Begin function _Z32__device_stub__final_compressionPiPbS0_i
.p2align 4, 0x90
.type _Z32__device_stub__final_compressionPiPbS0_i,@function
_Z32__device_stub__final_compressionPiPbS0_i: # @_Z32__device_stub__final_compressionPiPbS0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17final_compressionPiPbS0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__final_compressionPiPbS0_i, .Lfunc_end0-_Z32__device_stub__final_compressionPiPbS0_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i # -- Begin function _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i
.p2align 4, 0x90
.type _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i,@function
_Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i: # @_Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i, .Lfunc_end1-_Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17final_compressionPiPbS0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $char_huffman_table_gpu, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $261120, %r9d # imm = 0x3FC00
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type char_huffman_table_gpu,@object # @char_huffman_table_gpu
.local char_huffman_table_gpu
.comm char_huffman_table_gpu,261120,16
.type d_bool,@object # @d_bool
.bss
.globl d_bool
.p2align 3, 0x0
d_bool:
.quad 0
.size d_bool, 8
.type h_bool,@object # @h_bool
.globl h_bool
.p2align 3, 0x0
h_bool:
.quad 0
.size h_bool, 8
.type _Z17final_compressionPiPbS0_i,@object # @_Z17final_compressionPiPbS0_i
.section .rodata,"a",@progbits
.globl _Z17final_compressionPiPbS0_i
.p2align 3, 0x0
_Z17final_compressionPiPbS0_i:
.quad _Z32__device_stub__final_compressionPiPbS0_i
.size _Z17final_compressionPiPbS0_i, 8
.type _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i,@object # @_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.globl _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.p2align 3, 0x0
_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i:
.quad _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i
.size _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17final_compressionPiPbS0_i"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i"
.size .L__unnamed_2, 41
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "char_huffman_table_gpu"
.size .L__unnamed_3, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__final_compressionPiPbS0_i
.addrsig_sym _Z32__device_stub__compress_file_gpuPhPbPiS1_S1_S1_S1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym char_huffman_table_gpu
.addrsig_sym _Z17final_compressionPiPbS0_i
.addrsig_sym _Z17compress_file_gpuPhPbPiS1_S1_S1_S1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Parametric equalizer back-end GPU code.
*/
#include <cuda_runtime.h>
#include <cufft.h>
#include "parametric_eq_cuda.cuh"
const float PI = 3.14159265358979;
/**
* This kernel takes an array of Filters, and creates the appropriate
* output transfer function in the frequency domain. This just involves a
* superposition of the transfer functions described by each filter. The
* resulting transfer function will be floor(bufSamples/2) + 1 in length,
* since we only care about the positive frequencies in our FFT (since
* we're FFTing real signals).
*
*/
__global__
void cudaFilterSetupKernel(const Filter *filters,
const unsigned int numFilters,
cufftComplex *transferFunc,
const unsigned int samplingRate,
const unsigned int bufSamples)
{
// This is the index in "transferFunc" to which we're initially writing
// on this thread.
unsigned int transFuncInd = blockIdx.x * blockDim.x + threadIdx.x;
// The resolution of this transfer function will be
// samplingRate/bufSamples (in Hz), as is standard in FFTs.
const float transFuncRes = ((float) samplingRate) / bufSamples;
// The length of the resulting transfer function.
const unsigned int transFuncLength = (bufSamples / 2) + 1;
// Each thread might have to write to multiple indices of the transfer
// function array.
while (transFuncInd < transFuncLength)
{
// The frequency of this element is just the index times the
// resolution, but we multiply by "2 pi sqrt(-1)" to get an
// imaginary angular frequency (as desired for s-plane transfer
// functions).
float thisFreq = transFuncInd * transFuncRes;
float thisSReal = 2.0 * PI * thisFreq;
cufftComplex s;
s.x = 0.0;
s.y = thisSReal;
// The output to store in the appropriate index of the transfer
// function.
cufftComplex output;
output.x = 1.0;
output.y = 0.0;
// Iterate through all of the filters and superimpose their
// transfer functions. This "superposition" is actually a
// multiplication, since we're dealing with transfer functions.
for (int i = 0; i < numFilters; i++)
{
Filter thisFilter = filters[i];
FilterType thisFilterType = thisFilter.type;
switch (thisFilterType)
{
case FT_BAND_BOOST:
case FT_BAND_CUT:
{
// For boosts, use the transfer function:
//
// H(s) = (s^2 + K * omegaNought/Q * s + omegaNought^2)
// / (s^2 + omegaNought/Q * s + omegaNought^2)
//
// And use the reciprocal of this for cuts.
cufftComplex sSq;
float omegaNought, Q, K, omegaNoughtOvQ, omegaNoughtSq;
omegaNought = thisFilter.bandBCProp->omegaNought;
Q = thisFilter.bandBCProp->Q;
K = thisFilter.bandBCProp->K;
// Do some precomputation
sSq = cuCmulf(s, s);
omegaNoughtOvQ = omegaNought / Q;
omegaNoughtSq = omegaNought * omegaNought;
// The numerator and denominator of the above H(s) for
// boosts.
cufftComplex numerBoost;
cufftComplex denomBoost;
numerBoost.x = sSq.x + K * omegaNoughtOvQ * s.x +
omegaNoughtSq;
numerBoost.y = sSq.y + K * omegaNoughtOvQ * s.y;
denomBoost.x = sSq.x + omegaNoughtOvQ * s.x +
omegaNoughtSq;
denomBoost.y = sSq.y + omegaNoughtOvQ * s.y;
// If this is a boost, then just add numerBoost /
// denomBoost to the output element. Otherwise, if it's
// a cut, add the reciprocal of this.
cufftComplex quot;
if (thisFilterType == FT_BAND_BOOST)
{
quot = cuCdivf(numerBoost, denomBoost);
}
else
{
quot = cuCdivf(denomBoost, numerBoost);
}
// Multiply the previous transfer function by this one.
output.x *= quot.x;
output.y *= quot.y;
break;
}
case FT_HIGH_SHELF:
case FT_LOW_SHELF:
{
// The real-valued transfer function for low-shelf
// filters is:
//
// H(s) = 1 + (K - 1) *
// {1 - tanh( (|s| - Omega_0) / Omega_BW ) } / 2
//
// For high-shelf filters, we negate the argument to
// the tanh.
float tanhArg, tanhVal;
float omegaNought, omegaBW, KMinus1;
float positiveExp, negativeExp;
float filterVal;
omegaNought = thisFilter.shelvingProp->omegaNought;
omegaBW = thisFilter.shelvingProp->omegaBW;
KMinus1 = thisFilter.shelvingProp->K - 1.0;
// Calculate the argument to the tanh function.
tanhArg = (thisSReal - omegaNought) / omegaBW;
// Negate if this is a high-shelf filter.
if (thisFilterType == FT_HIGH_SHELF)
{
tanhArg *= -1.0;
}
// Sometimes there's blow-up to deal with when taking a
// tanh.
if (tanhArg >= 9.0)
{
// tanh(9.0) is pretty much 1.
tanhVal = 1.0;
}
else if (tanhArg <= -9.0)
{
// tanh(-9.0) is pretty much -1.
tanhVal = -1.0;
}
else
{
// Compute tanh efficiently via __expf. Each __expf
// call is supposed to take ~1 clock cycle
// according to the CUDA Programming Guide.
positiveExp = __expf(tanhArg);
negativeExp = __expf(-tanhArg);
// tanh(x) = (e^x - e^{-x}) / (e^x + e^{-x})
tanhVal = (positiveExp - negativeExp) /
(positiveExp + negativeExp);
}
filterVal = 1.0 + KMinus1 * (1.0 - tanhVal) / 2.0;
// Only multiply the real part of the previous transfer
// function by this one (this transfer function is
// purely real).
output.x *= filterVal;
break;
}
default:
printf("Unknown filter type; exiting");
asm("trap;");
}
}
// Write the "output" to global memory.
transferFunc[transFuncInd] = output;
// This thread might have to process multiple entries.
transFuncInd += blockDim.x * gridDim.x;
}
}
/**
* This kernel takes an input-output FFT'd audio buffer, which is
* floor(bufSamples/2) + 1 long (because we ignore the negative frequencies
* in the FFT). We multiply each element in this buffer by the
* corresponding element in the transfer function, which is assumed to be
* of the same length. This multiplication is carried out in place.
*
* After multiplying, we also divide by bufSamples (since IFFT(FFT(x)) will
* be bufSamples * x otherwise).
*
*/
__global__
void cudaProcessBufKernel(cufftComplex *inOutAudioFFTBuf,
const cufftComplex *transferFunc,
const unsigned int bufSamples)
{
// The index in the buffer that this thread is initially looking at.
unsigned int bufInd = blockIdx.x * blockDim.x + threadIdx.x;
// The FFT should be floor(bufSamples/2) + 1 elements long.
const unsigned int fftLength = (bufSamples / 2) + 1;
// Each thread might have to write to more than one entry in the FFT
// buffer.
while (bufInd < fftLength)
{
// Pointwise-multiply by the transfer function, and downscale.
cufftComplex transferFuncValue = transferFunc[bufInd];
cufftComplex newValue = inOutAudioFFTBuf[bufInd];
newValue = cuCmulf(newValue, transferFuncValue);
newValue.x /= bufSamples;
newValue.y /= bufSamples;
// Write to global memory.
inOutAudioFFTBuf[bufInd] = newValue;
// Process the next entry in the FFT buffer.
bufInd += blockDim.x * gridDim.x;
}
}
/**
* This kernel takes an audio buffer of floats, and clips all of its values
* so that they can be stored in an array of signed 16-bit shorts.
*
* It is assumed that both the input and output audio buffers are
* "bufSamples" long.
*
*/
__global__
void cudaClippingKernel(const float *inAudioBuf,
const unsigned int bufSamples,
int16_t *outAudioBuf)
{
// The index in the input buffer we're initially dealing with.
unsigned int bufInd = blockIdx.x * blockDim.x + threadIdx.x;
// Each thread might have to write to multiple entries.
while (bufInd < bufSamples)
{
float input = inAudioBuf[bufInd];
// Use fminf and fmaxf for clamping, since these are probably
// optimized (and allow for less divergence and better pipelining).
float output = fminf(input, 32767.0 - 0.001);
output = fmaxf(output, -32768.0 + 0.001);
outAudioBuf[bufInd] = (int16_t) output;
// Process the next entry in the input buffer.
bufInd += blockDim.x * gridDim.x;
}
}
void cudaCallFilterSetupKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const cudaStream_t stream,
const Filter *filters,
const unsigned int numFilters,
cufftComplex *transferFunc,
const unsigned int samplingRate,
const unsigned int bufSamples)
{
int shmemBytes = 0;
cudaFilterSetupKernel<<<blocks, threadsPerBlock, shmemBytes, stream>>>
(filters, numFilters, transferFunc, samplingRate, bufSamples);
}
void cudaCallProcessBufKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const cudaStream_t stream,
cufftComplex *inOutAudioFFTBuf,
const cufftComplex *transferFunc,
const unsigned int bufSamples)
{
int shmemBytes = 0;
cudaProcessBufKernel<<<blocks, threadsPerBlock, shmemBytes, stream>>>
(inOutAudioFFTBuf, transferFunc, bufSamples);
}
void cudaCallClippingKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const cudaStream_t stream,
const float *inAudioBuf,
const unsigned int bufSamples,
int16_t *outAudioBuf)
{
int shmemBytes = 0;
cudaClippingKernel<<<blocks, threadsPerBlock, shmemBytes, stream>>>
(inAudioBuf, bufSamples, outAudioBuf);
} | .file "tmpxft_000a187c_00000000-6_parametric_eq_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj
.type _Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj, @function
_Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj:
.LFB2107:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21cudaFilterSetupKernelPK6FilterjP6float2jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2107:
.size _Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj, .-_Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj
.globl _Z21cudaFilterSetupKernelPK6FilterjP6float2jj
.type _Z21cudaFilterSetupKernelPK6FilterjP6float2jj, @function
_Z21cudaFilterSetupKernelPK6FilterjP6float2jj:
.LFB2108:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size _Z21cudaFilterSetupKernelPK6FilterjP6float2jj, .-_Z21cudaFilterSetupKernelPK6FilterjP6float2jj
.globl _Z25cudaCallFilterSetupKerneljjP11CUstream_stPK6FilterjP6float2jj
.type _Z25cudaCallFilterSetupKerneljjP11CUstream_stPK6FilterjP6float2jj, @function
_Z25cudaCallFilterSetupKerneljjP11CUstream_stPK6FilterjP6float2jj:
.LFB2080:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rcx, %rbx
movl %r8d, %ebp
movq %r9, %r12
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movq %rdx, %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl 72(%rsp), %r8d
movl 64(%rsp), %ecx
movq %r12, %rdx
movl %ebp, %esi
movq %rbx, %rdi
call _Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj
jmp .L11
.cfi_endproc
.LFE2080:
.size _Z25cudaCallFilterSetupKerneljjP11CUstream_stPK6FilterjP6float2jj, .-_Z25cudaCallFilterSetupKerneljjP11CUstream_stPK6FilterjP6float2jj
.globl _Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j
.type _Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j, @function
_Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j:
.LFB2109:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20cudaProcessBufKernelP6float2PKS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2109:
.size _Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j, .-_Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j
.globl _Z20cudaProcessBufKernelP6float2PKS_j
.type _Z20cudaProcessBufKernelP6float2PKS_j, @function
_Z20cudaProcessBufKernelP6float2PKS_j:
.LFB2110:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _Z20cudaProcessBufKernelP6float2PKS_j, .-_Z20cudaProcessBufKernelP6float2PKS_j
.globl _Z24cudaCallProcessBufKerneljjP11CUstream_stP6float2PKS1_j
.type _Z24cudaCallProcessBufKerneljjP11CUstream_stP6float2PKS1_j, @function
_Z24cudaCallProcessBufKerneljjP11CUstream_stP6float2PKS1_j:
.LFB2081:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rcx, %rbx
movq %r8, %rbp
movl %r9d, %r12d
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movq %rdx, %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %r12d, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j
jmp .L23
.cfi_endproc
.LFE2081:
.size _Z24cudaCallProcessBufKerneljjP11CUstream_stP6float2PKS1_j, .-_Z24cudaCallProcessBufKerneljjP11CUstream_stP6float2PKS1_j
.globl _Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs
.type _Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs, @function
_Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs:
.LFB2111:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18cudaClippingKernelPKfjPs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2111:
.size _Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs, .-_Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs
.globl _Z18cudaClippingKernelPKfjPs
.type _Z18cudaClippingKernelPKfjPs, @function
_Z18cudaClippingKernelPKfjPs:
.LFB2112:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2112:
.size _Z18cudaClippingKernelPKfjPs, .-_Z18cudaClippingKernelPKfjPs
.globl _Z22cudaCallClippingKerneljjP11CUstream_stPKfjPs
.type _Z22cudaCallClippingKerneljjP11CUstream_stPKfjPs, @function
_Z22cudaCallClippingKerneljjP11CUstream_stPKfjPs:
.LFB2082:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rcx, %rbx
movl %r8d, %ebp
movq %r9, %r12
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movq %rdx, %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq %r12, %rdx
movl %ebp, %esi
movq %rbx, %rdi
call _Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs
jmp .L35
.cfi_endproc
.LFE2082:
.size _Z22cudaCallClippingKerneljjP11CUstream_stPKfjPs, .-_Z22cudaCallClippingKerneljjP11CUstream_stPKfjPs
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18cudaClippingKernelPKfjPs"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z20cudaProcessBufKernelP6float2PKS_j"
.align 8
.LC2:
.string "_Z21cudaFilterSetupKernelPK6FilterjP6float2jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2114:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18cudaClippingKernelPKfjPs(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20cudaProcessBufKernelP6float2PKS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21cudaFilterSetupKernelPK6FilterjP6float2jj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2114:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Parametric equalizer back-end GPU code.
*/
#include <cuda_runtime.h>
#include <cufft.h>
#include "parametric_eq_cuda.cuh"
const float PI = 3.14159265358979;
/**
* This kernel takes an array of Filters, and creates the appropriate
* output transfer function in the frequency domain. This just involves a
* superposition of the transfer functions described by each filter. The
* resulting transfer function will be floor(bufSamples/2) + 1 in length,
* since we only care about the positive frequencies in our FFT (since
* we're FFTing real signals).
*
*/
__global__
void cudaFilterSetupKernel(const Filter *filters,
const unsigned int numFilters,
cufftComplex *transferFunc,
const unsigned int samplingRate,
const unsigned int bufSamples)
{
// This is the index in "transferFunc" to which we're initially writing
// on this thread.
unsigned int transFuncInd = blockIdx.x * blockDim.x + threadIdx.x;
// The resolution of this transfer function will be
// samplingRate/bufSamples (in Hz), as is standard in FFTs.
const float transFuncRes = ((float) samplingRate) / bufSamples;
// The length of the resulting transfer function.
const unsigned int transFuncLength = (bufSamples / 2) + 1;
// Each thread might have to write to multiple indices of the transfer
// function array.
while (transFuncInd < transFuncLength)
{
// The frequency of this element is just the index times the
// resolution, but we multiply by "2 pi sqrt(-1)" to get an
// imaginary angular frequency (as desired for s-plane transfer
// functions).
float thisFreq = transFuncInd * transFuncRes;
float thisSReal = 2.0 * PI * thisFreq;
cufftComplex s;
s.x = 0.0;
s.y = thisSReal;
// The output to store in the appropriate index of the transfer
// function.
cufftComplex output;
output.x = 1.0;
output.y = 0.0;
// Iterate through all of the filters and superimpose their
// transfer functions. This "superposition" is actually a
// multiplication, since we're dealing with transfer functions.
for (int i = 0; i < numFilters; i++)
{
Filter thisFilter = filters[i];
FilterType thisFilterType = thisFilter.type;
switch (thisFilterType)
{
case FT_BAND_BOOST:
case FT_BAND_CUT:
{
// For boosts, use the transfer function:
//
// H(s) = (s^2 + K * omegaNought/Q * s + omegaNought^2)
// / (s^2 + omegaNought/Q * s + omegaNought^2)
//
// And use the reciprocal of this for cuts.
cufftComplex sSq;
float omegaNought, Q, K, omegaNoughtOvQ, omegaNoughtSq;
omegaNought = thisFilter.bandBCProp->omegaNought;
Q = thisFilter.bandBCProp->Q;
K = thisFilter.bandBCProp->K;
// Do some precomputation
sSq = cuCmulf(s, s);
omegaNoughtOvQ = omegaNought / Q;
omegaNoughtSq = omegaNought * omegaNought;
// The numerator and denominator of the above H(s) for
// boosts.
cufftComplex numerBoost;
cufftComplex denomBoost;
numerBoost.x = sSq.x + K * omegaNoughtOvQ * s.x +
omegaNoughtSq;
numerBoost.y = sSq.y + K * omegaNoughtOvQ * s.y;
denomBoost.x = sSq.x + omegaNoughtOvQ * s.x +
omegaNoughtSq;
denomBoost.y = sSq.y + omegaNoughtOvQ * s.y;
// If this is a boost, then just add numerBoost /
// denomBoost to the output element. Otherwise, if it's
// a cut, add the reciprocal of this.
cufftComplex quot;
if (thisFilterType == FT_BAND_BOOST)
{
quot = cuCdivf(numerBoost, denomBoost);
}
else
{
quot = cuCdivf(denomBoost, numerBoost);
}
// Multiply the previous transfer function by this one.
output.x *= quot.x;
output.y *= quot.y;
break;
}
case FT_HIGH_SHELF:
case FT_LOW_SHELF:
{
// The real-valued transfer function for low-shelf
// filters is:
//
// H(s) = 1 + (K - 1) *
// {1 - tanh( (|s| - Omega_0) / Omega_BW ) } / 2
//
// For high-shelf filters, we negate the argument to
// the tanh.
float tanhArg, tanhVal;
float omegaNought, omegaBW, KMinus1;
float positiveExp, negativeExp;
float filterVal;
omegaNought = thisFilter.shelvingProp->omegaNought;
omegaBW = thisFilter.shelvingProp->omegaBW;
KMinus1 = thisFilter.shelvingProp->K - 1.0;
// Calculate the argument to the tanh function.
tanhArg = (thisSReal - omegaNought) / omegaBW;
// Negate if this is a high-shelf filter.
if (thisFilterType == FT_HIGH_SHELF)
{
tanhArg *= -1.0;
}
// Sometimes there's blow-up to deal with when taking a
// tanh.
if (tanhArg >= 9.0)
{
// tanh(9.0) is pretty much 1.
tanhVal = 1.0;
}
else if (tanhArg <= -9.0)
{
// tanh(-9.0) is pretty much -1.
tanhVal = -1.0;
}
else
{
// Compute tanh efficiently via __expf. Each __expf
// call is supposed to take ~1 clock cycle
// according to the CUDA Programming Guide.
positiveExp = __expf(tanhArg);
negativeExp = __expf(-tanhArg);
// tanh(x) = (e^x - e^{-x}) / (e^x + e^{-x})
tanhVal = (positiveExp - negativeExp) /
(positiveExp + negativeExp);
}
filterVal = 1.0 + KMinus1 * (1.0 - tanhVal) / 2.0;
// Only multiply the real part of the previous transfer
// function by this one (this transfer function is
// purely real).
output.x *= filterVal;
break;
}
default:
printf("Unknown filter type; exiting");
asm("trap;");
}
}
// Write the "output" to global memory.
transferFunc[transFuncInd] = output;
// This thread might have to process multiple entries.
transFuncInd += blockDim.x * gridDim.x;
}
}
/**
* This kernel takes an input-output FFT'd audio buffer, which is
* floor(bufSamples/2) + 1 long (because we ignore the negative frequencies
* in the FFT). We multiply each element in this buffer by the
* corresponding element in the transfer function, which is assumed to be
* of the same length. This multiplication is carried out in place.
*
* After multiplying, we also divide by bufSamples (since IFFT(FFT(x)) will
* be bufSamples * x otherwise).
*
*/
__global__
void cudaProcessBufKernel(cufftComplex *inOutAudioFFTBuf,
const cufftComplex *transferFunc,
const unsigned int bufSamples)
{
// The index in the buffer that this thread is initially looking at.
unsigned int bufInd = blockIdx.x * blockDim.x + threadIdx.x;
// The FFT should be floor(bufSamples/2) + 1 elements long.
const unsigned int fftLength = (bufSamples / 2) + 1;
// Each thread might have to write to more than one entry in the FFT
// buffer.
while (bufInd < fftLength)
{
// Pointwise-multiply by the transfer function, and downscale.
cufftComplex transferFuncValue = transferFunc[bufInd];
cufftComplex newValue = inOutAudioFFTBuf[bufInd];
newValue = cuCmulf(newValue, transferFuncValue);
newValue.x /= bufSamples;
newValue.y /= bufSamples;
// Write to global memory.
inOutAudioFFTBuf[bufInd] = newValue;
// Process the next entry in the FFT buffer.
bufInd += blockDim.x * gridDim.x;
}
}
/**
* This kernel takes an audio buffer of floats, and clips all of its values
* so that they can be stored in an array of signed 16-bit shorts.
*
* It is assumed that both the input and output audio buffers are
* "bufSamples" long.
*
*/
__global__
void cudaClippingKernel(const float *inAudioBuf,
const unsigned int bufSamples,
int16_t *outAudioBuf)
{
// The index in the input buffer we're initially dealing with.
unsigned int bufInd = blockIdx.x * blockDim.x + threadIdx.x;
// Each thread might have to write to multiple entries.
while (bufInd < bufSamples)
{
float input = inAudioBuf[bufInd];
// Use fminf and fmaxf for clamping, since these are probably
// optimized (and allow for less divergence and better pipelining).
float output = fminf(input, 32767.0 - 0.001);
output = fmaxf(output, -32768.0 + 0.001);
outAudioBuf[bufInd] = (int16_t) output;
// Process the next entry in the input buffer.
bufInd += blockDim.x * gridDim.x;
}
}
void cudaCallFilterSetupKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const cudaStream_t stream,
const Filter *filters,
const unsigned int numFilters,
cufftComplex *transferFunc,
const unsigned int samplingRate,
const unsigned int bufSamples)
{
int shmemBytes = 0;
cudaFilterSetupKernel<<<blocks, threadsPerBlock, shmemBytes, stream>>>
(filters, numFilters, transferFunc, samplingRate, bufSamples);
}
void cudaCallProcessBufKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const cudaStream_t stream,
cufftComplex *inOutAudioFFTBuf,
const cufftComplex *transferFunc,
const unsigned int bufSamples)
{
int shmemBytes = 0;
cudaProcessBufKernel<<<blocks, threadsPerBlock, shmemBytes, stream>>>
(inOutAudioFFTBuf, transferFunc, bufSamples);
}
void cudaCallClippingKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const cudaStream_t stream,
const float *inAudioBuf,
const unsigned int bufSamples,
int16_t *outAudioBuf)
{
int shmemBytes = 0;
cudaClippingKernel<<<blocks, threadsPerBlock, shmemBytes, stream>>>
(inAudioBuf, bufSamples, outAudioBuf);
} | /**
* Parametric equalizer back-end.
*/
#ifndef PARAMETRIC_EQ_CUDA_CUH
#define PARAMETRIC_EQ_CUDA_CUH
#include <hipfft/hipfft.h>
#include <stdio.h>
#include <stdint.h>
/**
* This struct represents the properties of a band-pass boost or cut
* filter. See p. 278 of the following link for more information:
* http://www.thatcorp.com/datashts/AES13-041_Control_of_DSP_Parametric_EQs.pdf
*
* Note: both band-pass boost and cut filters have properties with the same
* names, but the transfer functions of cuts are the reciprocals of those
* of boosts. We distinguish between boost and cut filters by using their
* FilterTypes.
*/
typedef struct BandBoostCutProp
{
/*
* omegaNought = 2 pi * f_0, where f_0 is the central frequency of the
* filter in Hz.
*/
float omegaNought;
/* Q = f_0/BW, where BW is the bandwidth of the filter in Hz. */
float Q;
/*
* K = 10^(G/20), where G (positive) is the desired boost or cut in dB
* (depending on whether this is a boost or cut filter).
*/
float K;
} BandBoostProp;
/**
* This struct represents the properties of a high-shelving or low-shelving
* filter. The transfer function equation for this filter is completely
* real, and is given by the following function for low-shelf filters:
*
* H(s) = 1 + (K - 1) * {1 - tanh( (|s| - Omega_0) / Omega_BW ) } / 2
*
* Where K = 10^(G/20) (where G here can be negative), Omega_0 = 2 * pi *
* f_0, and Omega_BW = 2 * pi * BW. The transfer function for high-shelf
* filters is identical, but the argument to the tanh is negated.
*
* Note that this is mostly a heuristic filter that Laksh came up with.
* There's no guarantees that it has nice properties about roll-offs etc.
* However, there weren't very many nicely parametrizable filters to use
* for low-shelving and high-shelving filters.
*/
typedef struct ShelvingProp
{
/*
* omegaNought = 2 * pi * f_0, where f_0 is the central frequency of
* the filter in Hz.
*/
float omegaNought;
/*
* omegaBW = 2 * pi * BW, where BW is the bandwidth of the filter in
* Hz. (This is technically the "width" over which the filter's
* passband transitions to the stopband; it's not a "bandwidth" in the
* ordinary sense.
*/
float omegaBW;
/*
* K = 10^(G/20), where G (can be positive or negative) is the desired
* gain in dB.
*/
float K;
} ShelvingProp;
/**
* This enumeration specifies all the different kinds of filters allowed in
* this parametric equalizer. It is used to "tag" filters.
*/
typedef enum FilterType
{
FT_BAND_BOOST, /* Band-pass boost filter. */
FT_BAND_CUT, /* Band-pass cut filter. */
FT_HIGH_SHELF, /* High-shelving filter. */
FT_LOW_SHELF /* Low-shelving filter. */
} FilterType;
/**
* A struct that represents a generic filter, including its type and a
* pointer to a properties struct (representing that filter's specific
* properties).
*/
typedef struct Filter
{
/* The type of this filter. */
FilterType type;
/*
* A union of all the different possible properties that this filter
* could have. These are pointers to structs with more information. The
* specific property struct to use is indicated by the type tag.
*/
union
{
BandBoostCutProp *bandBCProp; /* FT_BAND_BOOST, FT_BAND_CUT */
ShelvingProp *shelvingProp; /* FT_HIGH_SHELF, FT_LOW_SHELF */
};
} Filter;
/**
* This function calls a kernel that will take an array of filters
* (representing the parametric equalizer) and construct a new transfer
* function at "transferFunc" of length floor(bufSamples/2) + 1 (the number
* of samples in each buffer divided by two, since we are only considering
* positive frequencies in the FFT since we have real signals). This
* kernel is used to update the filter data stored on the GPU, before
* the next buffer of data is passed into the equalizer.
*
*/
void cudaCallFilterSetupKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const hipStream_t stream,
const Filter *filters,
const unsigned int numFilters,
hipfftComplex *transferFunc,
const unsigned int samplingRate,
const unsigned int bufSamples);
/**
* This function calls a kernel that will process a given buffer of audio
* after it has been FFT'd. The input audio buffer will only contain a
* *single* channel's samples post-FFT.
*
* This processing involves multiplication by a transfer function, as well
* as downscaling by bufSamples (because of the properties of the FFT).
* This is all carried out in place, using the input-output parameter
* inOutAudioFFTBuf.
*
*/
void cudaCallProcessBufKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const hipStream_t stream,
hipfftComplex *inOutAudioFFTBuf,
const hipfftComplex *transferFunc,
const unsigned int bufSamples);
/**
* This function calls a kernel that clips all values in a given array of
* floats, so that they can be stored as an array of signed 16-bit shorts.
* Note that the input array contains bufSamples entries (i.e. it only
* contains the data needed for one channel).
*
*/
void cudaCallClippingKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const hipStream_t stream,
const float *inAudioBuf,
const unsigned int bufSamples,
int16_t *outAudioBuf);
#endif // PARAMETRIC_EQ_CUDA_CUH |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Parametric equalizer back-end.
*/
#ifndef PARAMETRIC_EQ_CUDA_CUH
#define PARAMETRIC_EQ_CUDA_CUH
#include <hipfft/hipfft.h>
#include <stdio.h>
#include <stdint.h>
/**
* This struct represents the properties of a band-pass boost or cut
* filter. See p. 278 of the following link for more information:
* http://www.thatcorp.com/datashts/AES13-041_Control_of_DSP_Parametric_EQs.pdf
*
* Note: both band-pass boost and cut filters have properties with the same
* names, but the transfer functions of cuts are the reciprocals of those
* of boosts. We distinguish between boost and cut filters by using their
* FilterTypes.
*/
typedef struct BandBoostCutProp
{
/*
* omegaNought = 2 pi * f_0, where f_0 is the central frequency of the
* filter in Hz.
*/
float omegaNought;
/* Q = f_0/BW, where BW is the bandwidth of the filter in Hz. */
float Q;
/*
* K = 10^(G/20), where G (positive) is the desired boost or cut in dB
* (depending on whether this is a boost or cut filter).
*/
float K;
} BandBoostProp;
/**
* This struct represents the properties of a high-shelving or low-shelving
* filter. The transfer function equation for this filter is completely
* real, and is given by the following function for low-shelf filters:
*
* H(s) = 1 + (K - 1) * {1 - tanh( (|s| - Omega_0) / Omega_BW ) } / 2
*
* Where K = 10^(G/20) (where G here can be negative), Omega_0 = 2 * pi *
* f_0, and Omega_BW = 2 * pi * BW. The transfer function for high-shelf
* filters is identical, but the argument to the tanh is negated.
*
* Note that this is mostly a heuristic filter that Laksh came up with.
* There's no guarantees that it has nice properties about roll-offs etc.
* However, there weren't very many nicely parametrizable filters to use
* for low-shelving and high-shelving filters.
*/
typedef struct ShelvingProp
{
/*
* omegaNought = 2 * pi * f_0, where f_0 is the central frequency of
* the filter in Hz.
*/
float omegaNought;
/*
* omegaBW = 2 * pi * BW, where BW is the bandwidth of the filter in
* Hz. (This is technically the "width" over which the filter's
* passband transitions to the stopband; it's not a "bandwidth" in the
* ordinary sense.
*/
float omegaBW;
/*
* K = 10^(G/20), where G (can be positive or negative) is the desired
* gain in dB.
*/
float K;
} ShelvingProp;
/**
* This enumeration specifies all the different kinds of filters allowed in
* this parametric equalizer. It is used to "tag" filters.
*/
typedef enum FilterType
{
FT_BAND_BOOST, /* Band-pass boost filter. */
FT_BAND_CUT, /* Band-pass cut filter. */
FT_HIGH_SHELF, /* High-shelving filter. */
FT_LOW_SHELF /* Low-shelving filter. */
} FilterType;
/**
* A struct that represents a generic filter, including its type and a
* pointer to a properties struct (representing that filter's specific
* properties).
*/
typedef struct Filter
{
/* The type of this filter. */
FilterType type;
/*
* A union of all the different possible properties that this filter
* could have. These are pointers to structs with more information. The
* specific property struct to use is indicated by the type tag.
*/
union
{
BandBoostCutProp *bandBCProp; /* FT_BAND_BOOST, FT_BAND_CUT */
ShelvingProp *shelvingProp; /* FT_HIGH_SHELF, FT_LOW_SHELF */
};
} Filter;
/**
* This function calls a kernel that will take an array of filters
* (representing the parametric equalizer) and construct a new transfer
* function at "transferFunc" of length floor(bufSamples/2) + 1 (the number
* of samples in each buffer divided by two, since we are only considering
* positive frequencies in the FFT since we have real signals). This
* kernel is used to update the filter data stored on the GPU, before
* the next buffer of data is passed into the equalizer.
*
*/
void cudaCallFilterSetupKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const hipStream_t stream,
const Filter *filters,
const unsigned int numFilters,
hipfftComplex *transferFunc,
const unsigned int samplingRate,
const unsigned int bufSamples);
/**
* This function calls a kernel that will process a given buffer of audio
* after it has been FFT'd. The input audio buffer will only contain a
* *single* channel's samples post-FFT.
*
* This processing involves multiplication by a transfer function, as well
* as downscaling by bufSamples (because of the properties of the FFT).
* This is all carried out in place, using the input-output parameter
* inOutAudioFFTBuf.
*
*/
void cudaCallProcessBufKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const hipStream_t stream,
hipfftComplex *inOutAudioFFTBuf,
const hipfftComplex *transferFunc,
const unsigned int bufSamples);
/**
* This function calls a kernel that clips all values in a given array of
* floats, so that they can be stored as an array of signed 16-bit shorts.
* Note that the input array contains bufSamples entries (i.e. it only
* contains the data needed for one channel).
*
*/
void cudaCallClippingKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const hipStream_t stream,
const float *inAudioBuf,
const unsigned int bufSamples,
int16_t *outAudioBuf);
#endif // PARAMETRIC_EQ_CUDA_CUH | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Parametric equalizer back-end.
*/
#ifndef PARAMETRIC_EQ_CUDA_CUH
#define PARAMETRIC_EQ_CUDA_CUH
#include <hipfft/hipfft.h>
#include <stdio.h>
#include <stdint.h>
/**
* This struct represents the properties of a band-pass boost or cut
* filter. See p. 278 of the following link for more information:
* http://www.thatcorp.com/datashts/AES13-041_Control_of_DSP_Parametric_EQs.pdf
*
* Note: both band-pass boost and cut filters have properties with the same
* names, but the transfer functions of cuts are the reciprocals of those
* of boosts. We distinguish between boost and cut filters by using their
* FilterTypes.
*/
typedef struct BandBoostCutProp
{
/*
* omegaNought = 2 pi * f_0, where f_0 is the central frequency of the
* filter in Hz.
*/
float omegaNought;
/* Q = f_0/BW, where BW is the bandwidth of the filter in Hz. */
float Q;
/*
* K = 10^(G/20), where G (positive) is the desired boost or cut in dB
* (depending on whether this is a boost or cut filter).
*/
float K;
} BandBoostProp;
/**
* This struct represents the properties of a high-shelving or low-shelving
* filter. The transfer function equation for this filter is completely
* real, and is given by the following function for low-shelf filters:
*
* H(s) = 1 + (K - 1) * {1 - tanh( (|s| - Omega_0) / Omega_BW ) } / 2
*
* Where K = 10^(G/20) (where G here can be negative), Omega_0 = 2 * pi *
* f_0, and Omega_BW = 2 * pi * BW. The transfer function for high-shelf
* filters is identical, but the argument to the tanh is negated.
*
* Note that this is mostly a heuristic filter that Laksh came up with.
* There's no guarantees that it has nice properties about roll-offs etc.
* However, there weren't very many nicely parametrizable filters to use
* for low-shelving and high-shelving filters.
*/
typedef struct ShelvingProp
{
/*
* omegaNought = 2 * pi * f_0, where f_0 is the central frequency of
* the filter in Hz.
*/
float omegaNought;
/*
* omegaBW = 2 * pi * BW, where BW is the bandwidth of the filter in
* Hz. (This is technically the "width" over which the filter's
* passband transitions to the stopband; it's not a "bandwidth" in the
* ordinary sense.
*/
float omegaBW;
/*
* K = 10^(G/20), where G (can be positive or negative) is the desired
* gain in dB.
*/
float K;
} ShelvingProp;
/**
* This enumeration specifies all the different kinds of filters allowed in
* this parametric equalizer. It is used to "tag" filters.
*/
typedef enum FilterType
{
FT_BAND_BOOST, /* Band-pass boost filter. */
FT_BAND_CUT, /* Band-pass cut filter. */
FT_HIGH_SHELF, /* High-shelving filter. */
FT_LOW_SHELF /* Low-shelving filter. */
} FilterType;
/**
* A struct that represents a generic filter, including its type and a
* pointer to a properties struct (representing that filter's specific
* properties).
*/
typedef struct Filter
{
/* The type of this filter. */
FilterType type;
/*
* A union of all the different possible properties that this filter
* could have. These are pointers to structs with more information. The
* specific property struct to use is indicated by the type tag.
*/
union
{
BandBoostCutProp *bandBCProp; /* FT_BAND_BOOST, FT_BAND_CUT */
ShelvingProp *shelvingProp; /* FT_HIGH_SHELF, FT_LOW_SHELF */
};
} Filter;
/**
* This function calls a kernel that will take an array of filters
* (representing the parametric equalizer) and construct a new transfer
* function at "transferFunc" of length floor(bufSamples/2) + 1 (the number
* of samples in each buffer divided by two, since we are only considering
* positive frequencies in the FFT since we have real signals). This
* kernel is used to update the filter data stored on the GPU, before
* the next buffer of data is passed into the equalizer.
*
*/
void cudaCallFilterSetupKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const hipStream_t stream,
const Filter *filters,
const unsigned int numFilters,
hipfftComplex *transferFunc,
const unsigned int samplingRate,
const unsigned int bufSamples);
/**
* This function calls a kernel that will process a given buffer of audio
* after it has been FFT'd. The input audio buffer will only contain a
* *single* channel's samples post-FFT.
*
* This processing involves multiplication by a transfer function, as well
* as downscaling by bufSamples (because of the properties of the FFT).
* This is all carried out in place, using the input-output parameter
* inOutAudioFFTBuf.
*
*/
void cudaCallProcessBufKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const hipStream_t stream,
hipfftComplex *inOutAudioFFTBuf,
const hipfftComplex *transferFunc,
const unsigned int bufSamples);
/**
* This function calls a kernel that clips all values in a given array of
* floats, so that they can be stored as an array of signed 16-bit shorts.
* Note that the input array contains bufSamples entries (i.e. it only
* contains the data needed for one channel).
*
*/
void cudaCallClippingKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
const hipStream_t stream,
const float *inAudioBuf,
const unsigned int bufSamples,
int16_t *outAudioBuf);
#endif // PARAMETRIC_EQ_CUDA_CUH | .text
.file "parametric_eq_cuda.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a187c_00000000-6_parametric_eq_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj
.type _Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj, @function
_Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj:
.LFB2107:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21cudaFilterSetupKernelPK6FilterjP6float2jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2107:
.size _Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj, .-_Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj
.globl _Z21cudaFilterSetupKernelPK6FilterjP6float2jj
.type _Z21cudaFilterSetupKernelPK6FilterjP6float2jj, @function
_Z21cudaFilterSetupKernelPK6FilterjP6float2jj:
.LFB2108:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size _Z21cudaFilterSetupKernelPK6FilterjP6float2jj, .-_Z21cudaFilterSetupKernelPK6FilterjP6float2jj
.globl _Z25cudaCallFilterSetupKerneljjP11CUstream_stPK6FilterjP6float2jj
.type _Z25cudaCallFilterSetupKerneljjP11CUstream_stPK6FilterjP6float2jj, @function
_Z25cudaCallFilterSetupKerneljjP11CUstream_stPK6FilterjP6float2jj:
.LFB2080:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rcx, %rbx
movl %r8d, %ebp
movq %r9, %r12
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movq %rdx, %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl 72(%rsp), %r8d
movl 64(%rsp), %ecx
movq %r12, %rdx
movl %ebp, %esi
movq %rbx, %rdi
call _Z59__device_stub__Z21cudaFilterSetupKernelPK6FilterjP6float2jjPK6FilterjP6float2jj
jmp .L11
.cfi_endproc
.LFE2080:
.size _Z25cudaCallFilterSetupKerneljjP11CUstream_stPK6FilterjP6float2jj, .-_Z25cudaCallFilterSetupKerneljjP11CUstream_stPK6FilterjP6float2jj
.globl _Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j
.type _Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j, @function
_Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j:
.LFB2109:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20cudaProcessBufKernelP6float2PKS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2109:
.size _Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j, .-_Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j
.globl _Z20cudaProcessBufKernelP6float2PKS_j
.type _Z20cudaProcessBufKernelP6float2PKS_j, @function
_Z20cudaProcessBufKernelP6float2PKS_j:
.LFB2110:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _Z20cudaProcessBufKernelP6float2PKS_j, .-_Z20cudaProcessBufKernelP6float2PKS_j
.globl _Z24cudaCallProcessBufKerneljjP11CUstream_stP6float2PKS1_j
.type _Z24cudaCallProcessBufKerneljjP11CUstream_stP6float2PKS1_j, @function
_Z24cudaCallProcessBufKerneljjP11CUstream_stP6float2PKS1_j:
.LFB2081:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rcx, %rbx
movq %r8, %rbp
movl %r9d, %r12d
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movq %rdx, %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %r12d, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z51__device_stub__Z20cudaProcessBufKernelP6float2PKS_jP6float2PKS_j
jmp .L23
.cfi_endproc
.LFE2081:
.size _Z24cudaCallProcessBufKerneljjP11CUstream_stP6float2PKS1_j, .-_Z24cudaCallProcessBufKerneljjP11CUstream_stP6float2PKS1_j
.globl _Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs
.type _Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs, @function
_Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs:
.LFB2111:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18cudaClippingKernelPKfjPs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2111:
.size _Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs, .-_Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs
.globl _Z18cudaClippingKernelPKfjPs
.type _Z18cudaClippingKernelPKfjPs, @function
_Z18cudaClippingKernelPKfjPs:
.LFB2112:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2112:
.size _Z18cudaClippingKernelPKfjPs, .-_Z18cudaClippingKernelPKfjPs
.globl _Z22cudaCallClippingKerneljjP11CUstream_stPKfjPs
.type _Z22cudaCallClippingKerneljjP11CUstream_stPKfjPs, @function
_Z22cudaCallClippingKerneljjP11CUstream_stPKfjPs:
.LFB2082:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rcx, %rbx
movl %r8d, %ebp
movq %r9, %r12
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movq %rdx, %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq %r12, %rdx
movl %ebp, %esi
movq %rbx, %rdi
call _Z42__device_stub__Z18cudaClippingKernelPKfjPsPKfjPs
jmp .L35
.cfi_endproc
.LFE2082:
.size _Z22cudaCallClippingKerneljjP11CUstream_stPKfjPs, .-_Z22cudaCallClippingKerneljjP11CUstream_stPKfjPs
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18cudaClippingKernelPKfjPs"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z20cudaProcessBufKernelP6float2PKS_j"
.align 8
.LC2:
.string "_Z21cudaFilterSetupKernelPK6FilterjP6float2jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2114:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18cudaClippingKernelPKfjPs(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20cudaProcessBufKernelP6float2PKS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21cudaFilterSetupKernelPK6FilterjP6float2jj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2114:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parametric_eq_cuda.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdint.h>
//#include <stdio.h>
template <typename T>
__device__ void fill_contiguous(T *data, size_t len, T val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < len; i += gridDim.x * blockDim.x) {
data[i] = val;
}
}
// Note that pitch must be expressed in elements, not bytes!
template <typename T>
__device__ void fill_pitched(T *data, size_t width, size_t height, size_t depth, size_t pitch, T val) {
int idxx = blockIdx.x * blockDim.x + threadIdx.x;
int idxy = blockIdx.y * blockDim.y + threadIdx.y;
int idxz = blockIdx.z * blockDim.z + threadIdx.z;
for (int iz = idxz; iz < depth; iz += gridDim.z * blockDim.z) {
int offsetz = iz;
for (int iy = idxy; iy < height; iy += gridDim.y * blockDim.y) {
int offsety = height*offsetz + iy;
for (int ix = idxx; ix < width; ix += gridDim.x * blockDim.x) {
data[pitch*offsety + ix] = val;
}
}
}
}
extern "C"
{
void __global__ fill_contiguous_double(double *data, size_t len, double val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_float(float *data, size_t len, float val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int64(int64_t *data, size_t len, int64_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint64(uint64_t *data, size_t len, uint64_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int32(int32_t *data, size_t len, int32_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint32(uint32_t *data, size_t len, uint32_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int16(int16_t *data, size_t len, int16_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint16(uint16_t *data, size_t len, uint16_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int8(int8_t *data, size_t len, int8_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint8(uint8_t *data, size_t len, uint8_t val) {fill_contiguous(data, len, val);}
void __global__ fill_pitched_double(double *data, size_t width, size_t height, size_t depth, size_t pitch, double val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_float(float *data, size_t width, size_t height, size_t depth, size_t pitch, float val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int64(int64_t *data, size_t width, size_t height, size_t depth, size_t pitch, int64_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint64(uint64_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint64_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int32(int32_t *data, size_t width, size_t height, size_t depth, size_t pitch, int32_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint32(uint32_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint32_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int16(int16_t *data, size_t width, size_t height, size_t depth, size_t pitch, int16_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint16(uint16_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint16_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int8(int8_t *data, size_t width, size_t height, size_t depth, size_t pitch, int8_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint8(uint8_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint8_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
}
// For implementing sleep, from http://stackoverflow.com/questions/11217117/equivalent-of-usleep-in-cuda-kernel
extern "C" {
// __global__ void clock_block(int64_t *d_o, int64_t clock_count)
__global__ void clock_block(int64_t clock_count)
{
int64_t start_clock = clock64();
int64_t clock_offset = 0;
while (clock_offset < clock_count)
{
clock_offset = clock64() - start_clock;
}
// d_o[0] = (int64_t) clock_offset;
}
}
/*// Debugging
int main()
{
size_t width = 5;
size_t height = 3;
size_t depth = 1;
size_t pitch = sizeof(double)*width;
cudaSetDevice(0);
cudaExtent extent = make_cudaExtent(pitch, height, depth);
cudaPitchedPtr devpp;
cudaMalloc3D(&devpp, extent);
pitch = devpp.pitch;
fill_pitched_double<<<32,16>>>((double *) devpp.ptr, width, height, depth, pitch/sizeof(double), (double) 8.4);
cudaDeviceSynchronize();
double *host = new double[width*height];
cudaPos dstpos = make_cudaPos(0, 0, 0);
cudaPos srcpos = make_cudaPos(0, 0, 0);
cudaPitchedPtr hostpp = make_cudaPitchedPtr(host, sizeof(double)*width, width, height);
cudaMemcpy3DParms mcpp = {0};
mcpp.srcPos = srcpos;
mcpp.dstPos = dstpos;
mcpp.srcPtr = devpp;
mcpp.dstPtr = hostpp;
mcpp.extent = extent;
mcpp.kind = cudaMemcpyDeviceToHost;
cudaMemcpy3D(&mcpp);
cudaDeviceSynchronize();
for (int i = 0; i < width*height; i++)
printf("%g\n", host[i]);
cudaDeviceReset();
}*/ | #include <hip/hip_runtime.h>
#include <stdint.h>
//#include <stdio.h>
template <typename T>
__device__ void fill_contiguous(T *data, size_t len, T val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < len; i += gridDim.x * blockDim.x) {
data[i] = val;
}
}
// Note that pitch must be expressed in elements, not bytes!
template <typename T>
__device__ void fill_pitched(T *data, size_t width, size_t height, size_t depth, size_t pitch, T val) {
int idxx = blockIdx.x * blockDim.x + threadIdx.x;
int idxy = blockIdx.y * blockDim.y + threadIdx.y;
int idxz = blockIdx.z * blockDim.z + threadIdx.z;
for (int iz = idxz; iz < depth; iz += gridDim.z * blockDim.z) {
int offsetz = iz;
for (int iy = idxy; iy < height; iy += gridDim.y * blockDim.y) {
int offsety = height*offsetz + iy;
for (int ix = idxx; ix < width; ix += gridDim.x * blockDim.x) {
data[pitch*offsety + ix] = val;
}
}
}
}
extern "C"
{
void __global__ fill_contiguous_double(double *data, size_t len, double val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_float(float *data, size_t len, float val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int64(int64_t *data, size_t len, int64_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint64(uint64_t *data, size_t len, uint64_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int32(int32_t *data, size_t len, int32_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint32(uint32_t *data, size_t len, uint32_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int16(int16_t *data, size_t len, int16_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint16(uint16_t *data, size_t len, uint16_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int8(int8_t *data, size_t len, int8_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint8(uint8_t *data, size_t len, uint8_t val) {fill_contiguous(data, len, val);}
void __global__ fill_pitched_double(double *data, size_t width, size_t height, size_t depth, size_t pitch, double val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_float(float *data, size_t width, size_t height, size_t depth, size_t pitch, float val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int64(int64_t *data, size_t width, size_t height, size_t depth, size_t pitch, int64_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint64(uint64_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint64_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int32(int32_t *data, size_t width, size_t height, size_t depth, size_t pitch, int32_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint32(uint32_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint32_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int16(int16_t *data, size_t width, size_t height, size_t depth, size_t pitch, int16_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint16(uint16_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint16_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int8(int8_t *data, size_t width, size_t height, size_t depth, size_t pitch, int8_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint8(uint8_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint8_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
}
// For implementing sleep, from http://stackoverflow.com/questions/11217117/equivalent-of-usleep-in-cuda-kernel
extern "C" {
// __global__ void clock_block(int64_t *d_o, int64_t clock_count)
__global__ void clock_block(int64_t clock_count)
{
int64_t start_clock = clock64();
int64_t clock_offset = 0;
while (clock_offset < clock_count)
{
clock_offset = clock64() - start_clock;
}
// d_o[0] = (int64_t) clock_offset;
}
}
/*// Debugging
int main()
{
size_t width = 5;
size_t height = 3;
size_t depth = 1;
size_t pitch = sizeof(double)*width;
cudaSetDevice(0);
cudaExtent extent = make_cudaExtent(pitch, height, depth);
cudaPitchedPtr devpp;
cudaMalloc3D(&devpp, extent);
pitch = devpp.pitch;
fill_pitched_double<<<32,16>>>((double *) devpp.ptr, width, height, depth, pitch/sizeof(double), (double) 8.4);
cudaDeviceSynchronize();
double *host = new double[width*height];
cudaPos dstpos = make_cudaPos(0, 0, 0);
cudaPos srcpos = make_cudaPos(0, 0, 0);
cudaPitchedPtr hostpp = make_cudaPitchedPtr(host, sizeof(double)*width, width, height);
cudaMemcpy3DParms mcpp = {0};
mcpp.srcPos = srcpos;
mcpp.dstPos = dstpos;
mcpp.srcPtr = devpp;
mcpp.dstPtr = hostpp;
mcpp.extent = extent;
mcpp.kind = cudaMemcpyDeviceToHost;
cudaMemcpy3D(&mcpp);
cudaDeviceSynchronize();
for (int i = 0; i < width*height; i++)
printf("%g\n", host[i]);
cudaDeviceReset();
}*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdint.h>
//#include <stdio.h>
template <typename T>
__device__ void fill_contiguous(T *data, size_t len, T val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < len; i += gridDim.x * blockDim.x) {
data[i] = val;
}
}
// Note that pitch must be expressed in elements, not bytes!
template <typename T>
__device__ void fill_pitched(T *data, size_t width, size_t height, size_t depth, size_t pitch, T val) {
int idxx = blockIdx.x * blockDim.x + threadIdx.x;
int idxy = blockIdx.y * blockDim.y + threadIdx.y;
int idxz = blockIdx.z * blockDim.z + threadIdx.z;
for (int iz = idxz; iz < depth; iz += gridDim.z * blockDim.z) {
int offsetz = iz;
for (int iy = idxy; iy < height; iy += gridDim.y * blockDim.y) {
int offsety = height*offsetz + iy;
for (int ix = idxx; ix < width; ix += gridDim.x * blockDim.x) {
data[pitch*offsety + ix] = val;
}
}
}
}
extern "C"
{
void __global__ fill_contiguous_double(double *data, size_t len, double val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_float(float *data, size_t len, float val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int64(int64_t *data, size_t len, int64_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint64(uint64_t *data, size_t len, uint64_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int32(int32_t *data, size_t len, int32_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint32(uint32_t *data, size_t len, uint32_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int16(int16_t *data, size_t len, int16_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint16(uint16_t *data, size_t len, uint16_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_int8(int8_t *data, size_t len, int8_t val) {fill_contiguous(data, len, val);}
void __global__ fill_contiguous_uint8(uint8_t *data, size_t len, uint8_t val) {fill_contiguous(data, len, val);}
void __global__ fill_pitched_double(double *data, size_t width, size_t height, size_t depth, size_t pitch, double val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_float(float *data, size_t width, size_t height, size_t depth, size_t pitch, float val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int64(int64_t *data, size_t width, size_t height, size_t depth, size_t pitch, int64_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint64(uint64_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint64_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int32(int32_t *data, size_t width, size_t height, size_t depth, size_t pitch, int32_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint32(uint32_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint32_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int16(int16_t *data, size_t width, size_t height, size_t depth, size_t pitch, int16_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint16(uint16_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint16_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_int8(int8_t *data, size_t width, size_t height, size_t depth, size_t pitch, int8_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
void __global__ fill_pitched_uint8(uint8_t *data, size_t width, size_t height, size_t depth, size_t pitch, uint8_t val) {
fill_pitched(data, width, height, depth, pitch, val);
}
}
// For implementing sleep, from http://stackoverflow.com/questions/11217117/equivalent-of-usleep-in-cuda-kernel
extern "C" {
// __global__ void clock_block(int64_t *d_o, int64_t clock_count)
__global__ void clock_block(int64_t clock_count)
{
int64_t start_clock = clock64();
int64_t clock_offset = 0;
while (clock_offset < clock_count)
{
clock_offset = clock64() - start_clock;
}
// d_o[0] = (int64_t) clock_offset;
}
}
/*// Debugging
int main()
{
size_t width = 5;
size_t height = 3;
size_t depth = 1;
size_t pitch = sizeof(double)*width;
cudaSetDevice(0);
cudaExtent extent = make_cudaExtent(pitch, height, depth);
cudaPitchedPtr devpp;
cudaMalloc3D(&devpp, extent);
pitch = devpp.pitch;
fill_pitched_double<<<32,16>>>((double *) devpp.ptr, width, height, depth, pitch/sizeof(double), (double) 8.4);
cudaDeviceSynchronize();
double *host = new double[width*height];
cudaPos dstpos = make_cudaPos(0, 0, 0);
cudaPos srcpos = make_cudaPos(0, 0, 0);
cudaPitchedPtr hostpp = make_cudaPitchedPtr(host, sizeof(double)*width, width, height);
cudaMemcpy3DParms mcpp = {0};
mcpp.srcPos = srcpos;
mcpp.dstPos = dstpos;
mcpp.srcPtr = devpp;
mcpp.dstPtr = hostpp;
mcpp.extent = extent;
mcpp.kind = cudaMemcpyDeviceToHost;
cudaMemcpy3D(&mcpp);
cudaDeviceSynchronize();
for (int i = 0; i < width*height; i++)
printf("%g\n", host[i]);
cudaDeviceReset();
}*/ | .text
.file "utils.hip"
.globl __device_stub__fill_contiguous_double # -- Begin function __device_stub__fill_contiguous_double
.p2align 4, 0x90
.type __device_stub__fill_contiguous_double,@function
__device_stub__fill_contiguous_double: # @__device_stub__fill_contiguous_double
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fill_contiguous_double, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__fill_contiguous_double, .Lfunc_end0-__device_stub__fill_contiguous_double
.cfi_endproc
# -- End function
.globl __device_stub__fill_contiguous_float # -- Begin function __device_stub__fill_contiguous_float
.p2align 4, 0x90
.type __device_stub__fill_contiguous_float,@function
__device_stub__fill_contiguous_float: # @__device_stub__fill_contiguous_float
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fill_contiguous_float, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size __device_stub__fill_contiguous_float, .Lfunc_end1-__device_stub__fill_contiguous_float
.cfi_endproc
# -- End function
.globl __device_stub__fill_contiguous_int64 # -- Begin function __device_stub__fill_contiguous_int64
.p2align 4, 0x90
.type __device_stub__fill_contiguous_int64,@function
__device_stub__fill_contiguous_int64: # @__device_stub__fill_contiguous_int64
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fill_contiguous_int64, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size __device_stub__fill_contiguous_int64, .Lfunc_end2-__device_stub__fill_contiguous_int64
.cfi_endproc
# -- End function
.globl __device_stub__fill_contiguous_uint64 # -- Begin function __device_stub__fill_contiguous_uint64
.p2align 4, 0x90
.type __device_stub__fill_contiguous_uint64,@function
__device_stub__fill_contiguous_uint64: # @__device_stub__fill_contiguous_uint64
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fill_contiguous_uint64, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size __device_stub__fill_contiguous_uint64, .Lfunc_end3-__device_stub__fill_contiguous_uint64
.cfi_endproc
# -- End function
.globl __device_stub__fill_contiguous_int32 # -- Begin function __device_stub__fill_contiguous_int32
.p2align 4, 0x90
.type __device_stub__fill_contiguous_int32,@function
__device_stub__fill_contiguous_int32: # @__device_stub__fill_contiguous_int32
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fill_contiguous_int32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size __device_stub__fill_contiguous_int32, .Lfunc_end4-__device_stub__fill_contiguous_int32
.cfi_endproc
# -- End function
.globl __device_stub__fill_contiguous_uint32 # -- Begin function __device_stub__fill_contiguous_uint32
.p2align 4, 0x90
.type __device_stub__fill_contiguous_uint32,@function
__device_stub__fill_contiguous_uint32: # @__device_stub__fill_contiguous_uint32
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fill_contiguous_uint32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size __device_stub__fill_contiguous_uint32, .Lfunc_end5-__device_stub__fill_contiguous_uint32
.cfi_endproc
# -- End function
.globl __device_stub__fill_contiguous_int16 # -- Begin function __device_stub__fill_contiguous_int16
.p2align 4, 0x90
.type __device_stub__fill_contiguous_int16,@function
__device_stub__fill_contiguous_int16: # @__device_stub__fill_contiguous_int16
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movw %dx, 14(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 14(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fill_contiguous_int16, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size __device_stub__fill_contiguous_int16, .Lfunc_end6-__device_stub__fill_contiguous_int16
.cfi_endproc
# -- End function
.globl __device_stub__fill_contiguous_uint16 # -- Begin function __device_stub__fill_contiguous_uint16
.p2align 4, 0x90
.type __device_stub__fill_contiguous_uint16,@function
__device_stub__fill_contiguous_uint16: # @__device_stub__fill_contiguous_uint16
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movw %dx, 14(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 14(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fill_contiguous_uint16, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end7:
.size __device_stub__fill_contiguous_uint16, .Lfunc_end7-__device_stub__fill_contiguous_uint16
.cfi_endproc
# -- End function
.globl __device_stub__fill_contiguous_int8 # -- Begin function __device_stub__fill_contiguous_int8
.p2align 4, 0x90
.type __device_stub__fill_contiguous_int8,@function
__device_stub__fill_contiguous_int8: # @__device_stub__fill_contiguous_int8
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movb %dl, 15(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 15(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fill_contiguous_int8, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end8:
.size __device_stub__fill_contiguous_int8, .Lfunc_end8-__device_stub__fill_contiguous_int8
.cfi_endproc
# -- End function
.globl __device_stub__fill_contiguous_uint8 # -- Begin function __device_stub__fill_contiguous_uint8
.p2align 4, 0x90
.type __device_stub__fill_contiguous_uint8,@function
__device_stub__fill_contiguous_uint8: # @__device_stub__fill_contiguous_uint8
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movb %dl, 15(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 15(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fill_contiguous_uint8, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end9:
.size __device_stub__fill_contiguous_uint8, .Lfunc_end9-__device_stub__fill_contiguous_uint8
.cfi_endproc
# -- End function
.globl __device_stub__fill_pitched_double # -- Begin function __device_stub__fill_pitched_double
.p2align 4, 0x90
.type __device_stub__fill_pitched_double,@function
__device_stub__fill_pitched_double: # @__device_stub__fill_pitched_double
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $fill_pitched_double, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end10:
.size __device_stub__fill_pitched_double, .Lfunc_end10-__device_stub__fill_pitched_double
.cfi_endproc
# -- End function
.globl __device_stub__fill_pitched_float # -- Begin function __device_stub__fill_pitched_float
.p2align 4, 0x90
.type __device_stub__fill_pitched_float,@function
__device_stub__fill_pitched_float: # @__device_stub__fill_pitched_float
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $fill_pitched_float, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end11:
.size __device_stub__fill_pitched_float, .Lfunc_end11-__device_stub__fill_pitched_float
.cfi_endproc
# -- End function
.globl __device_stub__fill_pitched_int64 # -- Begin function __device_stub__fill_pitched_int64
.p2align 4, 0x90
.type __device_stub__fill_pitched_int64,@function
__device_stub__fill_pitched_int64: # @__device_stub__fill_pitched_int64
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $fill_pitched_int64, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end12:
.size __device_stub__fill_pitched_int64, .Lfunc_end12-__device_stub__fill_pitched_int64
.cfi_endproc
# -- End function
.globl __device_stub__fill_pitched_uint64 # -- Begin function __device_stub__fill_pitched_uint64
.p2align 4, 0x90
.type __device_stub__fill_pitched_uint64,@function
__device_stub__fill_pitched_uint64: # @__device_stub__fill_pitched_uint64
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $fill_pitched_uint64, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end13:
.size __device_stub__fill_pitched_uint64, .Lfunc_end13-__device_stub__fill_pitched_uint64
.cfi_endproc
# -- End function
.globl __device_stub__fill_pitched_int32 # -- Begin function __device_stub__fill_pitched_int32
.p2align 4, 0x90
.type __device_stub__fill_pitched_int32,@function
__device_stub__fill_pitched_int32: # @__device_stub__fill_pitched_int32
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $fill_pitched_int32, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end14:
.size __device_stub__fill_pitched_int32, .Lfunc_end14-__device_stub__fill_pitched_int32
.cfi_endproc
# -- End function
.globl __device_stub__fill_pitched_uint32 # -- Begin function __device_stub__fill_pitched_uint32
.p2align 4, 0x90
.type __device_stub__fill_pitched_uint32,@function
__device_stub__fill_pitched_uint32: # @__device_stub__fill_pitched_uint32
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $fill_pitched_uint32, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end15:
.size __device_stub__fill_pitched_uint32, .Lfunc_end15-__device_stub__fill_pitched_uint32
.cfi_endproc
# -- End function
.globl __device_stub__fill_pitched_int16 # -- Begin function __device_stub__fill_pitched_int16
.p2align 4, 0x90
.type __device_stub__fill_pitched_int16,@function
__device_stub__fill_pitched_int16: # @__device_stub__fill_pitched_int16
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movw %r9w, 6(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 6(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $fill_pitched_int16, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end16:
.size __device_stub__fill_pitched_int16, .Lfunc_end16-__device_stub__fill_pitched_int16
.cfi_endproc
# -- End function
.globl __device_stub__fill_pitched_uint16 # -- Begin function __device_stub__fill_pitched_uint16
.p2align 4, 0x90
.type __device_stub__fill_pitched_uint16,@function
__device_stub__fill_pitched_uint16: # @__device_stub__fill_pitched_uint16
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movw %r9w, 6(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 6(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $fill_pitched_uint16, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end17:
.size __device_stub__fill_pitched_uint16, .Lfunc_end17-__device_stub__fill_pitched_uint16
.cfi_endproc
# -- End function
.globl __device_stub__fill_pitched_int8 # -- Begin function __device_stub__fill_pitched_int8
.p2align 4, 0x90
.type __device_stub__fill_pitched_int8,@function
__device_stub__fill_pitched_int8: # @__device_stub__fill_pitched_int8
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movb %r9b, 7(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 7(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $fill_pitched_int8, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end18:
.size __device_stub__fill_pitched_int8, .Lfunc_end18-__device_stub__fill_pitched_int8
.cfi_endproc
# -- End function
.globl __device_stub__fill_pitched_uint8 # -- Begin function __device_stub__fill_pitched_uint8
.p2align 4, 0x90
.type __device_stub__fill_pitched_uint8,@function
__device_stub__fill_pitched_uint8: # @__device_stub__fill_pitched_uint8
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movb %r9b, 7(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 7(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $fill_pitched_uint8, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end19:
.size __device_stub__fill_pitched_uint8, .Lfunc_end19-__device_stub__fill_pitched_uint8
.cfi_endproc
# -- End function
.globl __device_stub__clock_block # -- Begin function __device_stub__clock_block
.p2align 4, 0x90
.type __device_stub__clock_block,@function
__device_stub__clock_block: # @__device_stub__clock_block
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $clock_block, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end20:
.size __device_stub__clock_block, .Lfunc_end20-__device_stub__clock_block
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB21_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB21_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_contiguous_double, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_contiguous_float, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_contiguous_int64, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_contiguous_uint64, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_contiguous_int32, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_contiguous_uint32, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_contiguous_int16, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_contiguous_uint16, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_contiguous_int8, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_contiguous_uint8, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_pitched_double, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_pitched_float, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_pitched_int64, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_pitched_uint64, %esi
movl $.L__unnamed_14, %edx
movl $.L__unnamed_14, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_pitched_int32, %esi
movl $.L__unnamed_15, %edx
movl $.L__unnamed_15, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_pitched_uint32, %esi
movl $.L__unnamed_16, %edx
movl $.L__unnamed_16, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_pitched_int16, %esi
movl $.L__unnamed_17, %edx
movl $.L__unnamed_17, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_pitched_uint16, %esi
movl $.L__unnamed_18, %edx
movl $.L__unnamed_18, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_pitched_int8, %esi
movl $.L__unnamed_19, %edx
movl $.L__unnamed_19, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fill_pitched_uint8, %esi
movl $.L__unnamed_20, %edx
movl $.L__unnamed_20, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $clock_block, %esi
movl $.L__unnamed_21, %edx
movl $.L__unnamed_21, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end21:
.size __hip_module_ctor, .Lfunc_end21-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB22_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB22_2:
retq
.Lfunc_end22:
.size __hip_module_dtor, .Lfunc_end22-__hip_module_dtor
.cfi_endproc
# -- End function
.type fill_contiguous_double,@object # @fill_contiguous_double
.section .rodata,"a",@progbits
.globl fill_contiguous_double
.p2align 3, 0x0
fill_contiguous_double:
.quad __device_stub__fill_contiguous_double
.size fill_contiguous_double, 8
.type fill_contiguous_float,@object # @fill_contiguous_float
.globl fill_contiguous_float
.p2align 3, 0x0
fill_contiguous_float:
.quad __device_stub__fill_contiguous_float
.size fill_contiguous_float, 8
.type fill_contiguous_int64,@object # @fill_contiguous_int64
.globl fill_contiguous_int64
.p2align 3, 0x0
fill_contiguous_int64:
.quad __device_stub__fill_contiguous_int64
.size fill_contiguous_int64, 8
.type fill_contiguous_uint64,@object # @fill_contiguous_uint64
.globl fill_contiguous_uint64
.p2align 3, 0x0
fill_contiguous_uint64:
.quad __device_stub__fill_contiguous_uint64
.size fill_contiguous_uint64, 8
.type fill_contiguous_int32,@object # @fill_contiguous_int32
.globl fill_contiguous_int32
.p2align 3, 0x0
fill_contiguous_int32:
.quad __device_stub__fill_contiguous_int32
.size fill_contiguous_int32, 8
.type fill_contiguous_uint32,@object # @fill_contiguous_uint32
.globl fill_contiguous_uint32
.p2align 3, 0x0
fill_contiguous_uint32:
.quad __device_stub__fill_contiguous_uint32
.size fill_contiguous_uint32, 8
.type fill_contiguous_int16,@object # @fill_contiguous_int16
.globl fill_contiguous_int16
.p2align 3, 0x0
fill_contiguous_int16:
.quad __device_stub__fill_contiguous_int16
.size fill_contiguous_int16, 8
.type fill_contiguous_uint16,@object # @fill_contiguous_uint16
.globl fill_contiguous_uint16
.p2align 3, 0x0
fill_contiguous_uint16:
.quad __device_stub__fill_contiguous_uint16
.size fill_contiguous_uint16, 8
.type fill_contiguous_int8,@object # @fill_contiguous_int8
.globl fill_contiguous_int8
.p2align 3, 0x0
fill_contiguous_int8:
.quad __device_stub__fill_contiguous_int8
.size fill_contiguous_int8, 8
.type fill_contiguous_uint8,@object # @fill_contiguous_uint8
.globl fill_contiguous_uint8
.p2align 3, 0x0
fill_contiguous_uint8:
.quad __device_stub__fill_contiguous_uint8
.size fill_contiguous_uint8, 8
.type fill_pitched_double,@object # @fill_pitched_double
.globl fill_pitched_double
.p2align 3, 0x0
fill_pitched_double:
.quad __device_stub__fill_pitched_double
.size fill_pitched_double, 8
.type fill_pitched_float,@object # @fill_pitched_float
.globl fill_pitched_float
.p2align 3, 0x0
fill_pitched_float:
.quad __device_stub__fill_pitched_float
.size fill_pitched_float, 8
.type fill_pitched_int64,@object # @fill_pitched_int64
.globl fill_pitched_int64
.p2align 3, 0x0
fill_pitched_int64:
.quad __device_stub__fill_pitched_int64
.size fill_pitched_int64, 8
.type fill_pitched_uint64,@object # @fill_pitched_uint64
.globl fill_pitched_uint64
.p2align 3, 0x0
fill_pitched_uint64:
.quad __device_stub__fill_pitched_uint64
.size fill_pitched_uint64, 8
.type fill_pitched_int32,@object # @fill_pitched_int32
.globl fill_pitched_int32
.p2align 3, 0x0
fill_pitched_int32:
.quad __device_stub__fill_pitched_int32
.size fill_pitched_int32, 8
.type fill_pitched_uint32,@object # @fill_pitched_uint32
.globl fill_pitched_uint32
.p2align 3, 0x0
fill_pitched_uint32:
.quad __device_stub__fill_pitched_uint32
.size fill_pitched_uint32, 8
.type fill_pitched_int16,@object # @fill_pitched_int16
.globl fill_pitched_int16
.p2align 3, 0x0
fill_pitched_int16:
.quad __device_stub__fill_pitched_int16
.size fill_pitched_int16, 8
.type fill_pitched_uint16,@object # @fill_pitched_uint16
.globl fill_pitched_uint16
.p2align 3, 0x0
fill_pitched_uint16:
.quad __device_stub__fill_pitched_uint16
.size fill_pitched_uint16, 8
.type fill_pitched_int8,@object # @fill_pitched_int8
.globl fill_pitched_int8
.p2align 3, 0x0
fill_pitched_int8:
.quad __device_stub__fill_pitched_int8
.size fill_pitched_int8, 8
.type fill_pitched_uint8,@object # @fill_pitched_uint8
.globl fill_pitched_uint8
.p2align 3, 0x0
fill_pitched_uint8:
.quad __device_stub__fill_pitched_uint8
.size fill_pitched_uint8, 8
.type clock_block,@object # @clock_block
.globl clock_block
.p2align 3, 0x0
clock_block:
.quad __device_stub__clock_block
.size clock_block, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "fill_contiguous_double"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "fill_contiguous_float"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "fill_contiguous_int64"
.size .L__unnamed_3, 22
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "fill_contiguous_uint64"
.size .L__unnamed_4, 23
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "fill_contiguous_int32"
.size .L__unnamed_5, 22
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "fill_contiguous_uint32"
.size .L__unnamed_6, 23
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "fill_contiguous_int16"
.size .L__unnamed_7, 22
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "fill_contiguous_uint16"
.size .L__unnamed_8, 23
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "fill_contiguous_int8"
.size .L__unnamed_9, 21
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "fill_contiguous_uint8"
.size .L__unnamed_10, 22
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "fill_pitched_double"
.size .L__unnamed_11, 20
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "fill_pitched_float"
.size .L__unnamed_12, 19
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "fill_pitched_int64"
.size .L__unnamed_13, 19
.type .L__unnamed_14,@object # @13
.L__unnamed_14:
.asciz "fill_pitched_uint64"
.size .L__unnamed_14, 20
.type .L__unnamed_15,@object # @14
.L__unnamed_15:
.asciz "fill_pitched_int32"
.size .L__unnamed_15, 19
.type .L__unnamed_16,@object # @15
.L__unnamed_16:
.asciz "fill_pitched_uint32"
.size .L__unnamed_16, 20
.type .L__unnamed_17,@object # @16
.L__unnamed_17:
.asciz "fill_pitched_int16"
.size .L__unnamed_17, 19
.type .L__unnamed_18,@object # @17
.L__unnamed_18:
.asciz "fill_pitched_uint16"
.size .L__unnamed_18, 20
.type .L__unnamed_19,@object # @18
.L__unnamed_19:
.asciz "fill_pitched_int8"
.size .L__unnamed_19, 18
.type .L__unnamed_20,@object # @19
.L__unnamed_20:
.asciz "fill_pitched_uint8"
.size .L__unnamed_20, 19
.type .L__unnamed_21,@object # @20
.L__unnamed_21:
.asciz "clock_block"
.size .L__unnamed_21, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__fill_contiguous_double
.addrsig_sym __device_stub__fill_contiguous_float
.addrsig_sym __device_stub__fill_contiguous_int64
.addrsig_sym __device_stub__fill_contiguous_uint64
.addrsig_sym __device_stub__fill_contiguous_int32
.addrsig_sym __device_stub__fill_contiguous_uint32
.addrsig_sym __device_stub__fill_contiguous_int16
.addrsig_sym __device_stub__fill_contiguous_uint16
.addrsig_sym __device_stub__fill_contiguous_int8
.addrsig_sym __device_stub__fill_contiguous_uint8
.addrsig_sym __device_stub__fill_pitched_double
.addrsig_sym __device_stub__fill_pitched_float
.addrsig_sym __device_stub__fill_pitched_int64
.addrsig_sym __device_stub__fill_pitched_uint64
.addrsig_sym __device_stub__fill_pitched_int32
.addrsig_sym __device_stub__fill_pitched_uint32
.addrsig_sym __device_stub__fill_pitched_int16
.addrsig_sym __device_stub__fill_pitched_uint16
.addrsig_sym __device_stub__fill_pitched_int8
.addrsig_sym __device_stub__fill_pitched_uint8
.addrsig_sym __device_stub__clock_block
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym fill_contiguous_double
.addrsig_sym fill_contiguous_float
.addrsig_sym fill_contiguous_int64
.addrsig_sym fill_contiguous_uint64
.addrsig_sym fill_contiguous_int32
.addrsig_sym fill_contiguous_uint32
.addrsig_sym fill_contiguous_int16
.addrsig_sym fill_contiguous_uint16
.addrsig_sym fill_contiguous_int8
.addrsig_sym fill_contiguous_uint8
.addrsig_sym fill_pitched_double
.addrsig_sym fill_pitched_float
.addrsig_sym fill_pitched_int64
.addrsig_sym fill_pitched_uint64
.addrsig_sym fill_pitched_int32
.addrsig_sym fill_pitched_uint32
.addrsig_sym fill_pitched_int16
.addrsig_sym fill_pitched_uint16
.addrsig_sym fill_pitched_int8
.addrsig_sym fill_pitched_uint8
.addrsig_sym clock_block
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
// ref: https://cs.calvin.edu/courses/cs/374/CUDA/CUDA-Thread-Indexing-Cheatsheet.pdf
__device__ int getGlobalIdx_3D_3D() {
int blockId = blockIdx.x + blockIdx.y * gridDim.x +
gridDim.x * gridDim.y * blockIdx.z;
int threadId= blockId * (blockDim.x * blockDim.y * blockDim.z) +
(threadIdx.z * (blockDim.x * blockDim.y)) +
(threadIdx.y * blockDim.x) + threadIdx.x;
return threadId;
}
__global__ void mem_transfer(int * input, int size){
int gid = getGlobalIdx_3D_3D();
if (gid < size) {
printf("tid.xyz = %d %d %d, gid = %d, value = %d\n",
threadIdx.x, threadIdx.y, threadIdx.z, gid, input[gid]);
}
}
int main(int argc, char ** argv) {
int size = 64;
int byte_size = size * sizeof(int);
int *h_input;
h_input = (int *)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for (int i=0; i<size; i++) {
h_input[i] = (int) (rand() & 0xff);
}
int * d_input;
cudaMalloc((void**)&d_input, byte_size);
cudaMemcpy(d_input, h_input, byte_size, cudaMemcpyHostToDevice);
dim3 block(2,2,2);
dim3 grid(2,2,2);
mem_transfer <<<grid, block>>>(d_input, size);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z12mem_transferPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e220000002700 */
/*0020*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0040*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fc60007f3e0ff */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0060*/ S2R R10, SR_TID.Z ; /* 0x00000000000a7919 */
/* 0x000ea80000002300 */
/*0070*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000ee80000002200 */
/*0080*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000f220000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R3, R0, c[0x0][0xc], R5 ; /* 0x0000030000037a24 */
/* 0x002fc800078e0205 */
/*00b0*/ IMAD R0, R3, c[0x0][0x8], R10 ; /* 0x0000020003007a24 */
/* 0x004fc800078e020a */
/*00c0*/ IMAD R11, R0, c[0x0][0x4], R13 ; /* 0x00000100000b7a24 */
/* 0x008fc800078e020d */
/*00d0*/ IMAD R11, R11, c[0x0][0x0], R12 ; /* 0x000000000b0b7a24 */
/* 0x010fca00078e020c */
/*00e0*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x168], PT ; /* 0x00005a000b007a0c */
/* 0x000fda0003f06270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0120*/ IMAD.WIDE R2, R11, R2, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x000fcc00078e0202 */
/*0130*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0140*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3.X R7, RZ, c[0x0][0x24], RZ, P1, !PT ; /* 0x00000900ff077a10 */
/* 0x000fe20000ffe4ff */
/*0170*/ STL.64 [R1], R12 ; /* 0x0000000c01007387 */
/* 0x0001e20000100a00 */
/*0180*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*0190*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x000fe40000000f00 */
/*01a0*/ STL.64 [R1+0x8], R10 ; /* 0x0000080a01007387 */
/* 0x0001e80000100a00 */
/*01b0*/ STL [R1+0x10], R2 ; /* 0x0000100201007387 */
/* 0x0041e40000100800 */
/*01c0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe40000000000 */
/*01d0*/ MOV R11, 0x240 ; /* 0x00000240000b7802 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R20, 0x1c0 ; /* 0x000001c000147802 */
/* 0x000fc40000000f00 */
/*01f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0200*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0210*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0220*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0230*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
// ref: https://cs.calvin.edu/courses/cs/374/CUDA/CUDA-Thread-Indexing-Cheatsheet.pdf
__device__ int getGlobalIdx_3D_3D() {
int blockId = blockIdx.x + blockIdx.y * gridDim.x +
gridDim.x * gridDim.y * blockIdx.z;
int threadId= blockId * (blockDim.x * blockDim.y * blockDim.z) +
(threadIdx.z * (blockDim.x * blockDim.y)) +
(threadIdx.y * blockDim.x) + threadIdx.x;
return threadId;
}
__global__ void mem_transfer(int * input, int size){
int gid = getGlobalIdx_3D_3D();
if (gid < size) {
printf("tid.xyz = %d %d %d, gid = %d, value = %d\n",
threadIdx.x, threadIdx.y, threadIdx.z, gid, input[gid]);
}
}
int main(int argc, char ** argv) {
int size = 64;
int byte_size = size * sizeof(int);
int *h_input;
h_input = (int *)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for (int i=0; i<size; i++) {
h_input[i] = (int) (rand() & 0xff);
}
int * d_input;
cudaMalloc((void**)&d_input, byte_size);
cudaMemcpy(d_input, h_input, byte_size, cudaMemcpyHostToDevice);
dim3 block(2,2,2);
dim3 grid(2,2,2);
mem_transfer <<<grid, block>>>(d_input, size);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | .file "tmpxft_0005448c_00000000-6_mem_ex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18getGlobalIdx_3D_3Dv
.type _Z18getGlobalIdx_3D_3Dv, @function
_Z18getGlobalIdx_3D_3Dv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z18getGlobalIdx_3D_3Dv, .-_Z18getGlobalIdx_3D_3Dv
.globl _Z33__device_stub__Z12mem_transferPiiPii
.type _Z33__device_stub__Z12mem_transferPiiPii, @function
_Z33__device_stub__Z12mem_transferPiiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12mem_transferPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z12mem_transferPiiPii, .-_Z33__device_stub__Z12mem_transferPiiPii
.globl _Z12mem_transferPii
.type _Z12mem_transferPii, @function
_Z12mem_transferPii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12mem_transferPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12mem_transferPii, .-_Z12mem_transferPii
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $256, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 256(%r12), %rbp
.L14:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $256, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 16(%rsp)
movl $2, 20(%rsp)
movl $2, 28(%rsp)
movl $2, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $2, %ecx
movq 28(%rsp), %rdi
movl $2, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %esi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z12mem_transferPiiPii
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mem_transferPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mem_transferPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
// ref: https://cs.calvin.edu/courses/cs/374/CUDA/CUDA-Thread-Indexing-Cheatsheet.pdf
__device__ int getGlobalIdx_3D_3D() {
int blockId = blockIdx.x + blockIdx.y * gridDim.x +
gridDim.x * gridDim.y * blockIdx.z;
int threadId= blockId * (blockDim.x * blockDim.y * blockDim.z) +
(threadIdx.z * (blockDim.x * blockDim.y)) +
(threadIdx.y * blockDim.x) + threadIdx.x;
return threadId;
}
__global__ void mem_transfer(int * input, int size){
int gid = getGlobalIdx_3D_3D();
if (gid < size) {
printf("tid.xyz = %d %d %d, gid = %d, value = %d\n",
threadIdx.x, threadIdx.y, threadIdx.z, gid, input[gid]);
}
}
int main(int argc, char ** argv) {
int size = 64;
int byte_size = size * sizeof(int);
int *h_input;
h_input = (int *)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for (int i=0; i<size; i++) {
h_input[i] = (int) (rand() & 0xff);
}
int * d_input;
cudaMalloc((void**)&d_input, byte_size);
cudaMemcpy(d_input, h_input, byte_size, cudaMemcpyHostToDevice);
dim3 block(2,2,2);
dim3 grid(2,2,2);
mem_transfer <<<grid, block>>>(d_input, size);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "hip/hip_runtime.h"
// ref: https://cs.calvin.edu/courses/cs/374/CUDA/CUDA-Thread-Indexing-Cheatsheet.pdf
__device__ int getGlobalIdx_3D_3D() {
int blockId = blockIdx.x + blockIdx.y * gridDim.x +
gridDim.x * gridDim.y * blockIdx.z;
int threadId= blockId * (blockDim.x * blockDim.y * blockDim.z) +
(threadIdx.z * (blockDim.x * blockDim.y)) +
(threadIdx.y * blockDim.x) + threadIdx.x;
return threadId;
}
__global__ void mem_transfer(int * input, int size){
int gid = getGlobalIdx_3D_3D();
if (gid < size) {
printf("tid.xyz = %d %d %d, gid = %d, value = %d\n",
threadIdx.x, threadIdx.y, threadIdx.z, gid, input[gid]);
}
}
int main(int argc, char ** argv) {
int size = 64;
int byte_size = size * sizeof(int);
int *h_input;
h_input = (int *)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for (int i=0; i<size; i++) {
h_input[i] = (int) (rand() & 0xff);
}
int * d_input;
hipMalloc((void**)&d_input, byte_size);
hipMemcpy(d_input, h_input, byte_size, hipMemcpyHostToDevice);
dim3 block(2,2,2);
dim3 grid(2,2,2);
mem_transfer <<<grid, block>>>(d_input, size);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "hip/hip_runtime.h"
// ref: https://cs.calvin.edu/courses/cs/374/CUDA/CUDA-Thread-Indexing-Cheatsheet.pdf
__device__ int getGlobalIdx_3D_3D() {
int blockId = blockIdx.x + blockIdx.y * gridDim.x +
gridDim.x * gridDim.y * blockIdx.z;
int threadId= blockId * (blockDim.x * blockDim.y * blockDim.z) +
(threadIdx.z * (blockDim.x * blockDim.y)) +
(threadIdx.y * blockDim.x) + threadIdx.x;
return threadId;
}
__global__ void mem_transfer(int * input, int size){
int gid = getGlobalIdx_3D_3D();
if (gid < size) {
printf("tid.xyz = %d %d %d, gid = %d, value = %d\n",
threadIdx.x, threadIdx.y, threadIdx.z, gid, input[gid]);
}
}
int main(int argc, char ** argv) {
int size = 64;
int byte_size = size * sizeof(int);
int *h_input;
h_input = (int *)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for (int i=0; i<size; i++) {
h_input[i] = (int) (rand() & 0xff);
}
int * d_input;
hipMalloc((void**)&d_input, byte_size);
hipMemcpy(d_input, h_input, byte_size, hipMemcpyHostToDevice);
dim3 block(2,2,2);
dim3 grid(2,2,2);
mem_transfer <<<grid, block>>>(d_input, size);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} | .text
.file "mem_ex.hip"
.globl _Z27__device_stub__mem_transferPii # -- Begin function _Z27__device_stub__mem_transferPii
.p2align 4, 0x90
.type _Z27__device_stub__mem_transferPii,@function
_Z27__device_stub__mem_transferPii: # @_Z27__device_stub__mem_transferPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12mem_transferPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__mem_transferPii, .Lfunc_end0-_Z27__device_stub__mem_transferPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
leaq 96(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $64, %r14
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 16(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movl $2, %esi
movq %rdi, %rdx
movl $2, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $64, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12mem_transferPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mem_transferPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mem_transferPii,@object # @_Z12mem_transferPii
.section .rodata,"a",@progbits
.globl _Z12mem_transferPii
.p2align 3, 0x0
_Z12mem_transferPii:
.quad _Z27__device_stub__mem_transferPii
.size _Z12mem_transferPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mem_transferPii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mem_transferPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mem_transferPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005448c_00000000-6_mem_ex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18getGlobalIdx_3D_3Dv
.type _Z18getGlobalIdx_3D_3Dv, @function
_Z18getGlobalIdx_3D_3Dv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z18getGlobalIdx_3D_3Dv, .-_Z18getGlobalIdx_3D_3Dv
.globl _Z33__device_stub__Z12mem_transferPiiPii
.type _Z33__device_stub__Z12mem_transferPiiPii, @function
_Z33__device_stub__Z12mem_transferPiiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12mem_transferPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z12mem_transferPiiPii, .-_Z33__device_stub__Z12mem_transferPiiPii
.globl _Z12mem_transferPii
.type _Z12mem_transferPii, @function
_Z12mem_transferPii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12mem_transferPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12mem_transferPii, .-_Z12mem_transferPii
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $256, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 256(%r12), %rbp
.L14:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $256, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 16(%rsp)
movl $2, 20(%rsp)
movl $2, 28(%rsp)
movl $2, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $2, %ecx
movq 28(%rsp), %rdi
movl $2, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %esi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z12mem_transferPiiPii
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mem_transferPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mem_transferPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mem_ex.hip"
.globl _Z27__device_stub__mem_transferPii # -- Begin function _Z27__device_stub__mem_transferPii
.p2align 4, 0x90
.type _Z27__device_stub__mem_transferPii,@function
_Z27__device_stub__mem_transferPii: # @_Z27__device_stub__mem_transferPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12mem_transferPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__mem_transferPii, .Lfunc_end0-_Z27__device_stub__mem_transferPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
leaq 96(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $64, %r14
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 16(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movl $2, %esi
movq %rdi, %rdx
movl $2, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $64, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12mem_transferPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mem_transferPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mem_transferPii,@object # @_Z12mem_transferPii
.section .rodata,"a",@progbits
.globl _Z12mem_transferPii
.p2align 3, 0x0
_Z12mem_transferPii:
.quad _Z27__device_stub__mem_transferPii
.size _Z12mem_transferPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mem_transferPii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mem_transferPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mem_transferPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<cuda.h>
#define TILE_WIDTH 8
//const unsigned int WIDTH = 4096;
float *Md, *Nd, *Pd;
//generate matrix
#define IJK 0
#define IKJ 1
#define JIK 2
#define KIJ 3
#define JKI 4
#define KJI 5
#define LOOP_VER JIK
#define CHECK 0
float *GenMatrix(const unsigned int n)
{
float *matrix;
const unsigned int M_SIZE = n*n;
unsigned int i = 0, j = 0;
matrix = (float*) malloc(M_SIZE * sizeof(float));
for(i = 0 ;i < n; i++){
for(j = 0 ;j < n; j++){
matrix[i * n + j] = (rand()*1.0)/ RAND_MAX;
}
}
return matrix;
}
//display matrix
int PrintMatrix(float *P, const unsigned int n)
{
unsigned int i = 0, j = 0;
printf("\n");
for(i = 0 ;i < n; i++){
for(j = 0 ;j < n; j++){
printf("%.3f\t", P[i * n + j]);
}
printf("\n");
}
return 1;
}
//Init data
void Init_Cuda(float *M, float *N, unsigned int width)
{
const unsigned int size = width*width*sizeof(float);
//allocate matrix
cudaMalloc((void**)&Md, size);
cudaMemcpy(Md, M, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&Nd, size);
cudaMemcpy(Nd, N, size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&Pd, size);
cudaMemset(Pd, 0, size);
}
//Free memory
void Free_Cuda()
{
cudaFree(Md);
cudaFree(Nd);
cudaFree(Pd);
}
//kernel function
__global__ void MatrixMulKernel(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int i, r, c;
i = blockIdx.x*blockDim.x + threadIdx.x;
while(i<width*width)
{
r = i / width;
c = i % width;
float sum = 0.0;
for(int k=0; k<width; k++)
{ //sum+= M[r*width + k] * N[k * width + c];
float a = M[r*width +k];
float b = N[k*width +c];
//sum+= __ldg(&M[r*width + k]) * __ldg(&N[k * width + c]);
sum+= a * b;
}
P[r * width + c] = sum;
i+= gridDim.x * blockDim.x;
}
}
//ijk
__global__ void MatrixMulKernel_ijk(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
i = idx / width;
j = idx % width;
float sum = 0.0;
for(int k=0; k<width; k++)
{
float a = M[i*width + k];
float b = N[k*width + j];
sum+= a * b;
}
P[i * width + j] = sum;
idx+= gridDim.x * blockDim.x;
}
}
//ikj
__global__ void MatrixMulKernel_ikj(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
i = idx / width;
k = idx % width;
float a = M[i*width + k];
for(j=0; j<width; j++)
{
float b = N[k*width + j];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//jik
__global__ void MatrixMulKernel_jik(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
j = idx / width;
i = idx % width;
float sum = 0.0;
for(k=0; k<width; k++)
{
float a = M[i*width + k];
float b = N[k*width + j];
sum+= a * b;
}
P[i * width + j] = sum;
idx+= gridDim.x * blockDim.x;
}
}
//kij
__global__ void MatrixMulKernel_kij(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
k = idx / width;
i = idx % width;
float a = M[i*width + k];
for(j=0; j<width; j++)
{
float b = N[k*width + j];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//jki
__global__ void MatrixMulKernel_jki(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
j = idx / width;
k = idx % width;
float b = N[k*width + j];
for(i=0; i<width; i++)
{
float a = M[i*width + k];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//kji
__global__ void MatrixMulKernel_kji(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
k = idx / width;
j = idx % width;
float b = N[k*width + j];
for(i=0; i<width; i++)
{
float a = M[i*width + k];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
int MatrixMul(float *P, const float *M, const float *N, unsigned int n)
{
int i, j, k ;
float sum, a, b ;
for(i = 0 ;i < n; i++)
for(j = 0 ;j < n; j++)
{ sum = 0;
for(k = 0 ;k < n; k++)
{
a = M[i * n + k];
b = N[k * n + j];
sum += a*b;
}
P [ i* n + j] = (float)sum;
}
return 1;
}
int Check(float *KP, float *CP, unsigned int n)
{
int i, j;
float e = 0.001;
int correct = 1;
for(i = 0; i < n ; i++)
for(j = 0; j < n; j++)
{ if(abs(KP[i * n + j] - CP[i * n + j]) > e)
{ printf("%.10f %.10f\n", KP[i * n + j], CP[i * n + j]);
return 0;
}
}
return correct;
}
int main(int argc, char * argv[])
{
float *M, *N, *KP, *CP;
int width = 512;
cudaEvent_t start, stop;
float elapsedTime;
//initialize host memory
//create number of blocks and number of threads
int T = 128;
dim3 block(T, 1, 1);
dim3 grid(((width*width)+ T - 1) / T, 1, 1);
if (argc != 4) /* argc should be 2 for correct execution */
{
/* We print argv[0] assuming it is the program name */
printf("Usage: %s %s %s %s.\n", argv[0], "[matrix_size]", "[block_div]", "[num_threads]");
exit(0);
} else {
//printf("Arguments: %d %d", atoi(argv[1]), atoi(argv[2]));
width = atoi(argv[1]);
block.x = atoi(argv[3]);
block.y = 1;
grid.x = ((width*width)/atoi(argv[2]) + (block.x * block.y) - 1) / (block.x*block.y);
//grid.x = ((width*width)/atoi(argv[2]) + block.x - 1) / block.x;
}
M = GenMatrix(width);
//PrintMatrix(M, width);
N = GenMatrix(width);
//PrintMatrix(N, width);
KP = GenMatrix(width);
CP = GenMatrix(width);
//initialize device memory
Init_Cuda(M, N, width);
//create cudaEvent start and stop to record elapsed time
cudaEventCreate(&start);
cudaEventCreate(&stop);
//record start time to start event
for (int ver = 0; ver < 6; ver++) {
//record start time to start event
cudaEventRecord(start, 0);
switch (ver) {
case IJK:
MatrixMulKernel_ijk<<<grid, block>>>(Pd, Md, Nd, width);
break;
case IKJ:
MatrixMulKernel_ikj<<<grid, block>>>(Pd, Md, Nd, width);
break;
case JIK:
MatrixMulKernel_jik<<<grid, block>>>(Pd, Md, Nd, width);
break;
case KIJ:
MatrixMulKernel_kij<<<grid, block>>>(Pd, Md, Nd, width);
break;
case JKI:
MatrixMulKernel_jki<<<grid, block>>>(Pd, Md, Nd, width);
break;
case KJI:
MatrixMulKernel_kji<<<grid, block>>>(Pd, Md, Nd, width);
break;
default:
MatrixMulKernel_ijk<<<grid, block>>>(Pd, Md, Nd, width);
break;
}
//record start time to stop event
cudaEventRecord(stop, 0);
//synchronize the stop event
cudaEventSynchronize(stop);
//calculate the elapsed time
cudaEventElapsedTime(&elapsedTime, start, stop);
switch (ver) {
case IJK:
printf("ijk %.3f (ms)\n", elapsedTime);
break;
case IKJ:
printf("ikj %.3f (ms)\n", elapsedTime);
break;
case JIK:
printf("jik %.3f (ms)\n", elapsedTime);
break;
case KIJ:
printf("kij %.3f (ms)\n", elapsedTime);
break;
case JKI:
printf("jki %.3f (ms)\n", elapsedTime);
break;
case KJI:
printf("kji %.3f (ms)\n", elapsedTime);
break;
default:
printf("ijk %.3f (ms)\n", elapsedTime);
break;
}
//copy data from device memory to host memory
cudaMemcpy(KP, Pd, width*width*sizeof(float), cudaMemcpyDeviceToHost);
#if (CHECK)
MatrixMul(CP, M, N, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix(CP, width);
if(Check(KP, CP, width))
printf(" We do it.\n");
else
printf(" Something is wrong.\n");
#endif
cudaMemset(Pd, 0, width*width*sizeof(float));
}
//destroy the start and stop event
cudaEventDestroy(start);
cudaEventDestroy(stop);
//PrintMatrix(P, width);
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(M, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(N, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(KP, width);
*/
//free host memory
free(M);
free(N);
free(KP);
free(CP);
//free device memory
Free_Cuda();
return 0;
} | .file "tmpxft_000feebc_00000000-6_s_mm_1D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9GenMatrixj
.type _Z9GenMatrixj, @function
_Z9GenMatrixj:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %r13d
imull %edi, %edi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movl %r13d, %ebp
movl $0, %r14d
testl %r13d, %r13d
je .L3
.L4:
movl %ebp, %ebx
subl %r13d, %ebx
.L6:
call rand@PLT
movl %eax, %edx
movl %ebx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
divsd .LC0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rax,4)
addl $1, %ebx
cmpl %ebp, %ebx
jne .L6
addl $1, %r14d
addl %r13d, %ebp
cmpl %r14d, %r13d
jne .L4
.L3:
movq %r12, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9GenMatrixj, .-_Z9GenMatrixj
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n"
.LC2:
.string "%.3f\t"
.text
.globl _Z11PrintMatrixPfj
.type _Z11PrintMatrixPfj, @function
_Z11PrintMatrixPfj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl %esi, %r14d
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %ebp
movl $0, %r15d
leaq .LC2(%rip), %r13
testl %r14d, %r14d
je .L13
.L12:
movl %ebp, %ebx
subl %r14d, %ebx
.L14:
movl %ebx, %eax
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rax,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebp, %ebx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r15d
addl %r14d, %ebp
cmpl %r15d, %r14d
jne .L12
.L13:
movl $1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11PrintMatrixPfj, .-_Z11PrintMatrixPfj
.globl _Z9Init_CudaPfS_j
.type _Z9Init_CudaPfS_j, @function
_Z9Init_CudaPfS_j:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
imull %edx, %edx
leal 0(,%rdx,4), %ebx
movq %rbx, %rsi
leaq Md(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq Md(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq Nd(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq Nd(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq Pd(%rip), %rdi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $0, %esi
movq Pd(%rip), %rdi
call cudaMemset@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z9Init_CudaPfS_j, .-_Z9Init_CudaPfS_j
.globl _Z9Free_Cudav
.type _Z9Free_Cudav, @function
_Z9Free_Cudav:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq Md(%rip), %rdi
call cudaFree@PLT
movq Nd(%rip), %rdi
call cudaFree@PLT
movq Pd(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9Free_Cudav, .-_Z9Free_Cudav
.globl _Z9MatrixMulPfPKfS1_j
.type _Z9MatrixMulPfPKfS1_j, @function
_Z9MatrixMulPfPKfS1_j:
.LFB2061:
.cfi_startproc
endbr64
testl %ecx, %ecx
je .L31
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %rbx
movq %rsi, %r9
movq %rdx, %r10
movl %ecx, %edi
movl %ecx, %r8d
movl $0, %ebp
movl $0, %r13d
.L25:
movl $0, %r11d
.L28:
movl %r11d, %r12d
movl %r11d, %edx
movl %ebp, %eax
pxor %xmm1, %xmm1
.L26:
movl %eax, %esi
movl %edx, %ecx
movss (%r9,%rsi,4), %xmm0
mulss (%r10,%rcx,4), %xmm0
addss %xmm0, %xmm1
addl $1, %eax
addl %edi, %edx
cmpl %r8d, %eax
jne .L26
leal (%r12,%rbp), %eax
movss %xmm1, (%rbx,%rax,4)
addl $1, %r11d
cmpl %edi, %r11d
jne .L28
addl $1, %r13d
addl %edi, %ebp
addl %edi, %r8d
cmpl %edi, %r13d
jne .L25
movl $1, %eax
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
movl $1, %eax
ret
.cfi_endproc
.LFE2061:
.size _Z9MatrixMulPfPKfS1_j, .-_Z9MatrixMulPfPKfS1_j
.section .rodata.str1.1
.LC6:
.string "%.10f %.10f\n"
.text
.globl _Z5CheckPfS_j
.type _Z5CheckPfS_j, @function
_Z5CheckPfS_j:
.LFB2062:
.cfi_startproc
endbr64
testl %edx, %edx
je .L40
movl %edx, %r8d
movl $0, %r9d
movl $0, %r10d
movss .LC4(%rip), %xmm3
.L36:
movl %r9d, %eax
.L39:
movl %eax, %ecx
movss (%rdi,%rcx,4), %xmm0
movss (%rsi,%rcx,4), %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps %xmm3, %xmm2
comiss .LC5(%rip), %xmm2
ja .L49
addl $1, %eax
cmpl %r8d, %eax
jne .L39
addl $1, %r10d
addl %edx, %r8d
addl %edx, %r9d
cmpl %edx, %r10d
jne .L36
movl $1, %eax
ret
.L49:
subq $8, %rsp
.cfi_def_cfa_offset 16
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L40:
movl $1, %eax
ret
.cfi_endproc
.LFE2062:
.size _Z5CheckPfS_j, .-_Z5CheckPfS_j
.globl _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.type _Z15MatrixMulKernelPfS_S_i, @function
_Z15MatrixMulKernelPfS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i
.globl _Z44__device_stub__Z19MatrixMulKernel_ijkPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19MatrixMulKernel_ijkPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19MatrixMulKernel_ijkPfS_S_iPfS_S_i:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L62
.L58:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L63
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19MatrixMulKernel_ijkPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L58
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z44__device_stub__Z19MatrixMulKernel_ijkPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19MatrixMulKernel_ijkPfS_S_iPfS_S_i
.globl _Z19MatrixMulKernel_ijkPfS_S_i
.type _Z19MatrixMulKernel_ijkPfS_S_i, @function
_Z19MatrixMulKernel_ijkPfS_S_i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19MatrixMulKernel_ijkPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z19MatrixMulKernel_ijkPfS_S_i, .-_Z19MatrixMulKernel_ijkPfS_S_i
.globl _Z44__device_stub__Z19MatrixMulKernel_ikjPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19MatrixMulKernel_ikjPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19MatrixMulKernel_ikjPfS_S_iPfS_S_i:
.LFB2092:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L70
.L66:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L71
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19MatrixMulKernel_ikjPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L66
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z44__device_stub__Z19MatrixMulKernel_ikjPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19MatrixMulKernel_ikjPfS_S_iPfS_S_i
.globl _Z19MatrixMulKernel_ikjPfS_S_i
.type _Z19MatrixMulKernel_ikjPfS_S_i, @function
_Z19MatrixMulKernel_ikjPfS_S_i:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19MatrixMulKernel_ikjPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z19MatrixMulKernel_ikjPfS_S_i, .-_Z19MatrixMulKernel_ikjPfS_S_i
.globl _Z44__device_stub__Z19MatrixMulKernel_jikPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19MatrixMulKernel_jikPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19MatrixMulKernel_jikPfS_S_iPfS_S_i:
.LFB2094:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L78
.L74:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L79
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19MatrixMulKernel_jikPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L74
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z44__device_stub__Z19MatrixMulKernel_jikPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19MatrixMulKernel_jikPfS_S_iPfS_S_i
.globl _Z19MatrixMulKernel_jikPfS_S_i
.type _Z19MatrixMulKernel_jikPfS_S_i, @function
_Z19MatrixMulKernel_jikPfS_S_i:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19MatrixMulKernel_jikPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z19MatrixMulKernel_jikPfS_S_i, .-_Z19MatrixMulKernel_jikPfS_S_i
.globl _Z44__device_stub__Z19MatrixMulKernel_kijPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19MatrixMulKernel_kijPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19MatrixMulKernel_kijPfS_S_iPfS_S_i:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L86
.L82:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L87
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19MatrixMulKernel_kijPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L82
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z44__device_stub__Z19MatrixMulKernel_kijPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19MatrixMulKernel_kijPfS_S_iPfS_S_i
.globl _Z19MatrixMulKernel_kijPfS_S_i
.type _Z19MatrixMulKernel_kijPfS_S_i, @function
_Z19MatrixMulKernel_kijPfS_S_i:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19MatrixMulKernel_kijPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z19MatrixMulKernel_kijPfS_S_i, .-_Z19MatrixMulKernel_kijPfS_S_i
.globl _Z44__device_stub__Z19MatrixMulKernel_jkiPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19MatrixMulKernel_jkiPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19MatrixMulKernel_jkiPfS_S_iPfS_S_i:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L94
.L90:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L95
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19MatrixMulKernel_jkiPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L90
.L95:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z44__device_stub__Z19MatrixMulKernel_jkiPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19MatrixMulKernel_jkiPfS_S_iPfS_S_i
.globl _Z19MatrixMulKernel_jkiPfS_S_i
.type _Z19MatrixMulKernel_jkiPfS_S_i, @function
_Z19MatrixMulKernel_jkiPfS_S_i:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19MatrixMulKernel_jkiPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z19MatrixMulKernel_jkiPfS_S_i, .-_Z19MatrixMulKernel_jkiPfS_S_i
.globl _Z44__device_stub__Z19MatrixMulKernel_kjiPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19MatrixMulKernel_kjiPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19MatrixMulKernel_kjiPfS_S_iPfS_S_i:
.LFB2100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L102
.L98:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L103
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L102:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19MatrixMulKernel_kjiPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L98
.L103:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z44__device_stub__Z19MatrixMulKernel_kjiPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19MatrixMulKernel_kjiPfS_S_iPfS_S_i
.globl _Z19MatrixMulKernel_kjiPfS_S_i
.type _Z19MatrixMulKernel_kjiPfS_S_i, @function
_Z19MatrixMulKernel_kjiPfS_S_i:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19MatrixMulKernel_kjiPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z19MatrixMulKernel_kjiPfS_S_i, .-_Z19MatrixMulKernel_kjiPfS_S_i
.section .rodata.str1.1
.LC7:
.string "[num_threads]"
.LC8:
.string "[block_div]"
.LC9:
.string "[matrix_size]"
.LC10:
.string "Usage: %s %s %s %s.\n"
.LC11:
.string "kji %.3f (ms)\n"
.LC12:
.string "ijk %.3f (ms)\n"
.LC13:
.string "ikj %.3f (ms)\n"
.LC14:
.string "jik %.3f (ms)\n"
.LC15:
.string "kij %.3f (ms)\n"
.LC16:
.string "jki %.3f (ms)\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 72(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
cmpl $4, %edi
je .L107
leaq .LC7(%rip), %r9
leaq .LC8(%rip), %r8
leaq .LC9(%rip), %rcx
movq (%rsi), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L107:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r15d
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq %rax, 24(%rsp)
movl %eax, %r14d
imull %ebx, %ebx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rcx
movl %ebx, %eax
cltd
idivl %ecx
leal -1(%rax,%r13), %eax
movl $0, %edx
divl %r13d
movl %eax, 76(%rsp)
movl %r15d, %edi
call _Z9GenMatrixj
movq %rax, %r12
movq %rax, (%rsp)
movl %r15d, %edi
call _Z9GenMatrixj
movq %rax, %rbp
movq %rax, 8(%rsp)
movl %r15d, %edi
call _Z9GenMatrixj
movq %rax, %r13
movl %r15d, %edi
call _Z9GenMatrixj
movq %rax, 16(%rsp)
movl %r15d, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _Z9Init_CudaPfS_j
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movslq %ebx, %rbx
salq $2, %rbx
movl $0, %ebp
leaq .L110(%rip), %r12
jmp .L123
.L115:
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L128
.L116:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L124
.L128:
movl %r15d, %ecx
movq Nd(%rip), %rdx
movq Md(%rip), %rsi
movq Pd(%rip), %rdi
call _Z44__device_stub__Z19MatrixMulKernel_ijkPfS_S_iPfS_S_i
jmp .L116
.L114:
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L129
.L117:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L124
.L129:
movl %r15d, %ecx
movq Nd(%rip), %rdx
movq Md(%rip), %rsi
movq Pd(%rip), %rdi
call _Z44__device_stub__Z19MatrixMulKernel_ikjPfS_S_iPfS_S_i
jmp .L117
.L113:
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L130
.L118:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L124
.L130:
movl %r15d, %ecx
movq Nd(%rip), %rdx
movq Md(%rip), %rsi
movq Pd(%rip), %rdi
call _Z44__device_stub__Z19MatrixMulKernel_jikPfS_S_iPfS_S_i
jmp .L118
.L112:
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L131
.L119:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L124
.L131:
movl %r15d, %ecx
movq Nd(%rip), %rdx
movq Md(%rip), %rsi
movq Pd(%rip), %rdi
call _Z44__device_stub__Z19MatrixMulKernel_kijPfS_S_iPfS_S_i
jmp .L119
.L111:
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L132
.L120:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L124
.L132:
movl %r15d, %ecx
movq Nd(%rip), %rdx
movq Md(%rip), %rsi
movq Pd(%rip), %rdi
call _Z44__device_stub__Z19MatrixMulKernel_jkiPfS_S_iPfS_S_i
jmp .L120
.L109:
movl 24(%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L133
.L121:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq Pd(%rip), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movl $0, %esi
movq Pd(%rip), %rdi
call cudaMemset@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
call _Z9Free_Cudav
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L134
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L133:
.cfi_restore_state
movl %r15d, %ecx
movq Nd(%rip), %rdx
movq Md(%rip), %rsi
movq Pd(%rip), %rdi
call _Z44__device_stub__Z19MatrixMulKernel_kjiPfS_S_iPfS_S_i
jmp .L121
.L108:
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L135
.L122:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L124:
movl $2, %ecx
movq %rbx, %rdx
movq Pd(%rip), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movl $0, %esi
movq Pd(%rip), %rdi
call cudaMemset@PLT
addl $1, %ebp
.L123:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
cmpl $5, %ebp
ja .L108
movl %ebp, %eax
movslq (%r12,%rax,4), %rax
addq %r12, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L110:
.long .L115-.L110
.long .L114-.L110
.long .L113-.L110
.long .L112-.L110
.long .L111-.L110
.long .L109-.L110
.text
.L135:
movl %r15d, %ecx
movq Nd(%rip), %rdx
movq Md(%rip), %rsi
movq Pd(%rip), %rdi
call _Z44__device_stub__Z19MatrixMulKernel_ijkPfS_S_iPfS_S_i
jmp .L122
.L134:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC17:
.string "_Z19MatrixMulKernel_kjiPfS_S_i"
.align 8
.LC18:
.string "_Z19MatrixMulKernel_jkiPfS_S_i"
.align 8
.LC19:
.string "_Z19MatrixMulKernel_kijPfS_S_i"
.align 8
.LC20:
.string "_Z19MatrixMulKernel_jikPfS_S_i"
.align 8
.LC21:
.string "_Z19MatrixMulKernel_ikjPfS_S_i"
.align 8
.LC22:
.string "_Z19MatrixMulKernel_ijkPfS_S_i"
.section .rodata.str1.1
.LC23:
.string "_Z15MatrixMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z19MatrixMulKernel_kjiPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z19MatrixMulKernel_jkiPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z19MatrixMulKernel_kijPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z19MatrixMulKernel_jikPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z19MatrixMulKernel_ikjPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z19MatrixMulKernel_ijkPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl Pd
.bss
.align 8
.type Pd, @object
.size Pd, 8
Pd:
.zero 8
.globl Nd
.align 8
.type Nd, @object
.size Nd, 8
Nd:
.zero 8
.globl Md
.align 8
.type Md, @object
.size Md, 8
Md:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<cuda.h>
#define TILE_WIDTH 8
//const unsigned int WIDTH = 4096;
float *Md, *Nd, *Pd;
//generate matrix
#define IJK 0
#define IKJ 1
#define JIK 2
#define KIJ 3
#define JKI 4
#define KJI 5
#define LOOP_VER JIK
#define CHECK 0
float *GenMatrix(const unsigned int n)
{
float *matrix;
const unsigned int M_SIZE = n*n;
unsigned int i = 0, j = 0;
matrix = (float*) malloc(M_SIZE * sizeof(float));
for(i = 0 ;i < n; i++){
for(j = 0 ;j < n; j++){
matrix[i * n + j] = (rand()*1.0)/ RAND_MAX;
}
}
return matrix;
}
//display matrix
int PrintMatrix(float *P, const unsigned int n)
{
unsigned int i = 0, j = 0;
printf("\n");
for(i = 0 ;i < n; i++){
for(j = 0 ;j < n; j++){
printf("%.3f\t", P[i * n + j]);
}
printf("\n");
}
return 1;
}
//Init data
void Init_Cuda(float *M, float *N, unsigned int width)
{
const unsigned int size = width*width*sizeof(float);
//allocate matrix
cudaMalloc((void**)&Md, size);
cudaMemcpy(Md, M, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&Nd, size);
cudaMemcpy(Nd, N, size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&Pd, size);
cudaMemset(Pd, 0, size);
}
//Free memory
void Free_Cuda()
{
cudaFree(Md);
cudaFree(Nd);
cudaFree(Pd);
}
//kernel function
__global__ void MatrixMulKernel(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int i, r, c;
i = blockIdx.x*blockDim.x + threadIdx.x;
while(i<width*width)
{
r = i / width;
c = i % width;
float sum = 0.0;
for(int k=0; k<width; k++)
{ //sum+= M[r*width + k] * N[k * width + c];
float a = M[r*width +k];
float b = N[k*width +c];
//sum+= __ldg(&M[r*width + k]) * __ldg(&N[k * width + c]);
sum+= a * b;
}
P[r * width + c] = sum;
i+= gridDim.x * blockDim.x;
}
}
//ijk
__global__ void MatrixMulKernel_ijk(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
i = idx / width;
j = idx % width;
float sum = 0.0;
for(int k=0; k<width; k++)
{
float a = M[i*width + k];
float b = N[k*width + j];
sum+= a * b;
}
P[i * width + j] = sum;
idx+= gridDim.x * blockDim.x;
}
}
//ikj
__global__ void MatrixMulKernel_ikj(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
i = idx / width;
k = idx % width;
float a = M[i*width + k];
for(j=0; j<width; j++)
{
float b = N[k*width + j];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//jik
__global__ void MatrixMulKernel_jik(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
j = idx / width;
i = idx % width;
float sum = 0.0;
for(k=0; k<width; k++)
{
float a = M[i*width + k];
float b = N[k*width + j];
sum+= a * b;
}
P[i * width + j] = sum;
idx+= gridDim.x * blockDim.x;
}
}
//kij
__global__ void MatrixMulKernel_kij(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
k = idx / width;
i = idx % width;
float a = M[i*width + k];
for(j=0; j<width; j++)
{
float b = N[k*width + j];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//jki
__global__ void MatrixMulKernel_jki(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
j = idx / width;
k = idx % width;
float b = N[k*width + j];
for(i=0; i<width; i++)
{
float a = M[i*width + k];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//kji
__global__ void MatrixMulKernel_kji(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
k = idx / width;
j = idx % width;
float b = N[k*width + j];
for(i=0; i<width; i++)
{
float a = M[i*width + k];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
int MatrixMul(float *P, const float *M, const float *N, unsigned int n)
{
int i, j, k ;
float sum, a, b ;
for(i = 0 ;i < n; i++)
for(j = 0 ;j < n; j++)
{ sum = 0;
for(k = 0 ;k < n; k++)
{
a = M[i * n + k];
b = N[k * n + j];
sum += a*b;
}
P [ i* n + j] = (float)sum;
}
return 1;
}
int Check(float *KP, float *CP, unsigned int n)
{
int i, j;
float e = 0.001;
int correct = 1;
for(i = 0; i < n ; i++)
for(j = 0; j < n; j++)
{ if(abs(KP[i * n + j] - CP[i * n + j]) > e)
{ printf("%.10f %.10f\n", KP[i * n + j], CP[i * n + j]);
return 0;
}
}
return correct;
}
int main(int argc, char * argv[])
{
float *M, *N, *KP, *CP;
int width = 512;
cudaEvent_t start, stop;
float elapsedTime;
//initialize host memory
//create number of blocks and number of threads
int T = 128;
dim3 block(T, 1, 1);
dim3 grid(((width*width)+ T - 1) / T, 1, 1);
if (argc != 4) /* argc should be 2 for correct execution */
{
/* We print argv[0] assuming it is the program name */
printf("Usage: %s %s %s %s.\n", argv[0], "[matrix_size]", "[block_div]", "[num_threads]");
exit(0);
} else {
//printf("Arguments: %d %d", atoi(argv[1]), atoi(argv[2]));
width = atoi(argv[1]);
block.x = atoi(argv[3]);
block.y = 1;
grid.x = ((width*width)/atoi(argv[2]) + (block.x * block.y) - 1) / (block.x*block.y);
//grid.x = ((width*width)/atoi(argv[2]) + block.x - 1) / block.x;
}
M = GenMatrix(width);
//PrintMatrix(M, width);
N = GenMatrix(width);
//PrintMatrix(N, width);
KP = GenMatrix(width);
CP = GenMatrix(width);
//initialize device memory
Init_Cuda(M, N, width);
//create cudaEvent start and stop to record elapsed time
cudaEventCreate(&start);
cudaEventCreate(&stop);
//record start time to start event
for (int ver = 0; ver < 6; ver++) {
//record start time to start event
cudaEventRecord(start, 0);
switch (ver) {
case IJK:
MatrixMulKernel_ijk<<<grid, block>>>(Pd, Md, Nd, width);
break;
case IKJ:
MatrixMulKernel_ikj<<<grid, block>>>(Pd, Md, Nd, width);
break;
case JIK:
MatrixMulKernel_jik<<<grid, block>>>(Pd, Md, Nd, width);
break;
case KIJ:
MatrixMulKernel_kij<<<grid, block>>>(Pd, Md, Nd, width);
break;
case JKI:
MatrixMulKernel_jki<<<grid, block>>>(Pd, Md, Nd, width);
break;
case KJI:
MatrixMulKernel_kji<<<grid, block>>>(Pd, Md, Nd, width);
break;
default:
MatrixMulKernel_ijk<<<grid, block>>>(Pd, Md, Nd, width);
break;
}
//record start time to stop event
cudaEventRecord(stop, 0);
//synchronize the stop event
cudaEventSynchronize(stop);
//calculate the elapsed time
cudaEventElapsedTime(&elapsedTime, start, stop);
switch (ver) {
case IJK:
printf("ijk %.3f (ms)\n", elapsedTime);
break;
case IKJ:
printf("ikj %.3f (ms)\n", elapsedTime);
break;
case JIK:
printf("jik %.3f (ms)\n", elapsedTime);
break;
case KIJ:
printf("kij %.3f (ms)\n", elapsedTime);
break;
case JKI:
printf("jki %.3f (ms)\n", elapsedTime);
break;
case KJI:
printf("kji %.3f (ms)\n", elapsedTime);
break;
default:
printf("ijk %.3f (ms)\n", elapsedTime);
break;
}
//copy data from device memory to host memory
cudaMemcpy(KP, Pd, width*width*sizeof(float), cudaMemcpyDeviceToHost);
#if (CHECK)
MatrixMul(CP, M, N, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix(CP, width);
if(Check(KP, CP, width))
printf(" We do it.\n");
else
printf(" Something is wrong.\n");
#endif
cudaMemset(Pd, 0, width*width*sizeof(float));
}
//destroy the start and stop event
cudaEventDestroy(start);
cudaEventDestroy(stop);
//PrintMatrix(P, width);
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(M, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(N, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(KP, width);
*/
//free host memory
free(M);
free(N);
free(KP);
free(CP);
//free device memory
Free_Cuda();
return 0;
} | #include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#define TILE_WIDTH 8
//const unsigned int WIDTH = 4096;
float *Md, *Nd, *Pd;
//generate matrix
#define IJK 0
#define IKJ 1
#define JIK 2
#define KIJ 3
#define JKI 4
#define KJI 5
#define LOOP_VER JIK
#define CHECK 0
float *GenMatrix(const unsigned int n)
{
float *matrix;
const unsigned int M_SIZE = n*n;
unsigned int i = 0, j = 0;
matrix = (float*) malloc(M_SIZE * sizeof(float));
for(i = 0 ;i < n; i++){
for(j = 0 ;j < n; j++){
matrix[i * n + j] = (rand()*1.0)/ RAND_MAX;
}
}
return matrix;
}
//display matrix
int PrintMatrix(float *P, const unsigned int n)
{
unsigned int i = 0, j = 0;
printf("\n");
for(i = 0 ;i < n; i++){
for(j = 0 ;j < n; j++){
printf("%.3f\t", P[i * n + j]);
}
printf("\n");
}
return 1;
}
//Init data
void Init_Cuda(float *M, float *N, unsigned int width)
{
const unsigned int size = width*width*sizeof(float);
//allocate matrix
hipMalloc((void**)&Md, size);
hipMemcpy(Md, M, size, hipMemcpyHostToDevice);
hipMalloc((void**)&Nd, size);
hipMemcpy(Nd, N, size,hipMemcpyHostToDevice);
hipMalloc((void**)&Pd, size);
hipMemset(Pd, 0, size);
}
//Free memory
void Free_Cuda()
{
hipFree(Md);
hipFree(Nd);
hipFree(Pd);
}
//kernel function
__global__ void MatrixMulKernel(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int i, r, c;
i = blockIdx.x*blockDim.x + threadIdx.x;
while(i<width*width)
{
r = i / width;
c = i % width;
float sum = 0.0;
for(int k=0; k<width; k++)
{ //sum+= M[r*width + k] * N[k * width + c];
float a = M[r*width +k];
float b = N[k*width +c];
//sum+= __ldg(&M[r*width + k]) * __ldg(&N[k * width + c]);
sum+= a * b;
}
P[r * width + c] = sum;
i+= gridDim.x * blockDim.x;
}
}
//ijk
__global__ void MatrixMulKernel_ijk(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
i = idx / width;
j = idx % width;
float sum = 0.0;
for(int k=0; k<width; k++)
{
float a = M[i*width + k];
float b = N[k*width + j];
sum+= a * b;
}
P[i * width + j] = sum;
idx+= gridDim.x * blockDim.x;
}
}
//ikj
__global__ void MatrixMulKernel_ikj(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
i = idx / width;
k = idx % width;
float a = M[i*width + k];
for(j=0; j<width; j++)
{
float b = N[k*width + j];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//jik
__global__ void MatrixMulKernel_jik(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
j = idx / width;
i = idx % width;
float sum = 0.0;
for(k=0; k<width; k++)
{
float a = M[i*width + k];
float b = N[k*width + j];
sum+= a * b;
}
P[i * width + j] = sum;
idx+= gridDim.x * blockDim.x;
}
}
//kij
__global__ void MatrixMulKernel_kij(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
k = idx / width;
i = idx % width;
float a = M[i*width + k];
for(j=0; j<width; j++)
{
float b = N[k*width + j];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//jki
__global__ void MatrixMulKernel_jki(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
j = idx / width;
k = idx % width;
float b = N[k*width + j];
for(i=0; i<width; i++)
{
float a = M[i*width + k];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//kji
__global__ void MatrixMulKernel_kji(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
k = idx / width;
j = idx % width;
float b = N[k*width + j];
for(i=0; i<width; i++)
{
float a = M[i*width + k];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
int MatrixMul(float *P, const float *M, const float *N, unsigned int n)
{
int i, j, k ;
float sum, a, b ;
for(i = 0 ;i < n; i++)
for(j = 0 ;j < n; j++)
{ sum = 0;
for(k = 0 ;k < n; k++)
{
a = M[i * n + k];
b = N[k * n + j];
sum += a*b;
}
P [ i* n + j] = (float)sum;
}
return 1;
}
int Check(float *KP, float *CP, unsigned int n)
{
int i, j;
float e = 0.001;
int correct = 1;
for(i = 0; i < n ; i++)
for(j = 0; j < n; j++)
{ if(abs(KP[i * n + j] - CP[i * n + j]) > e)
{ printf("%.10f %.10f\n", KP[i * n + j], CP[i * n + j]);
return 0;
}
}
return correct;
}
int main(int argc, char * argv[])
{
float *M, *N, *KP, *CP;
int width = 512;
hipEvent_t start, stop;
float elapsedTime;
//initialize host memory
//create number of blocks and number of threads
int T = 128;
dim3 block(T, 1, 1);
dim3 grid(((width*width)+ T - 1) / T, 1, 1);
if (argc != 4) /* argc should be 2 for correct execution */
{
/* We print argv[0] assuming it is the program name */
printf("Usage: %s %s %s %s.\n", argv[0], "[matrix_size]", "[block_div]", "[num_threads]");
exit(0);
} else {
//printf("Arguments: %d %d", atoi(argv[1]), atoi(argv[2]));
width = atoi(argv[1]);
block.x = atoi(argv[3]);
block.y = 1;
grid.x = ((width*width)/atoi(argv[2]) + (block.x * block.y) - 1) / (block.x*block.y);
//grid.x = ((width*width)/atoi(argv[2]) + block.x - 1) / block.x;
}
M = GenMatrix(width);
//PrintMatrix(M, width);
N = GenMatrix(width);
//PrintMatrix(N, width);
KP = GenMatrix(width);
CP = GenMatrix(width);
//initialize device memory
Init_Cuda(M, N, width);
//create cudaEvent start and stop to record elapsed time
hipEventCreate(&start);
hipEventCreate(&stop);
//record start time to start event
for (int ver = 0; ver < 6; ver++) {
//record start time to start event
hipEventRecord(start, 0);
switch (ver) {
case IJK:
MatrixMulKernel_ijk<<<grid, block>>>(Pd, Md, Nd, width);
break;
case IKJ:
MatrixMulKernel_ikj<<<grid, block>>>(Pd, Md, Nd, width);
break;
case JIK:
MatrixMulKernel_jik<<<grid, block>>>(Pd, Md, Nd, width);
break;
case KIJ:
MatrixMulKernel_kij<<<grid, block>>>(Pd, Md, Nd, width);
break;
case JKI:
MatrixMulKernel_jki<<<grid, block>>>(Pd, Md, Nd, width);
break;
case KJI:
MatrixMulKernel_kji<<<grid, block>>>(Pd, Md, Nd, width);
break;
default:
MatrixMulKernel_ijk<<<grid, block>>>(Pd, Md, Nd, width);
break;
}
//record start time to stop event
hipEventRecord(stop, 0);
//synchronize the stop event
hipEventSynchronize(stop);
//calculate the elapsed time
hipEventElapsedTime(&elapsedTime, start, stop);
switch (ver) {
case IJK:
printf("ijk %.3f (ms)\n", elapsedTime);
break;
case IKJ:
printf("ikj %.3f (ms)\n", elapsedTime);
break;
case JIK:
printf("jik %.3f (ms)\n", elapsedTime);
break;
case KIJ:
printf("kij %.3f (ms)\n", elapsedTime);
break;
case JKI:
printf("jki %.3f (ms)\n", elapsedTime);
break;
case KJI:
printf("kji %.3f (ms)\n", elapsedTime);
break;
default:
printf("ijk %.3f (ms)\n", elapsedTime);
break;
}
//copy data from device memory to host memory
hipMemcpy(KP, Pd, width*width*sizeof(float), hipMemcpyDeviceToHost);
#if (CHECK)
MatrixMul(CP, M, N, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix(CP, width);
if(Check(KP, CP, width))
printf(" We do it.\n");
else
printf(" Something is wrong.\n");
#endif
hipMemset(Pd, 0, width*width*sizeof(float));
}
//destroy the start and stop event
hipEventDestroy(start);
hipEventDestroy(stop);
//PrintMatrix(P, width);
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(M, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(N, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(KP, width);
*/
//free host memory
free(M);
free(N);
free(KP);
free(CP);
//free device memory
Free_Cuda();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#define TILE_WIDTH 8
//const unsigned int WIDTH = 4096;
float *Md, *Nd, *Pd;
//generate matrix
#define IJK 0
#define IKJ 1
#define JIK 2
#define KIJ 3
#define JKI 4
#define KJI 5
#define LOOP_VER JIK
#define CHECK 0
float *GenMatrix(const unsigned int n)
{
float *matrix;
const unsigned int M_SIZE = n*n;
unsigned int i = 0, j = 0;
matrix = (float*) malloc(M_SIZE * sizeof(float));
for(i = 0 ;i < n; i++){
for(j = 0 ;j < n; j++){
matrix[i * n + j] = (rand()*1.0)/ RAND_MAX;
}
}
return matrix;
}
//display matrix
int PrintMatrix(float *P, const unsigned int n)
{
unsigned int i = 0, j = 0;
printf("\n");
for(i = 0 ;i < n; i++){
for(j = 0 ;j < n; j++){
printf("%.3f\t", P[i * n + j]);
}
printf("\n");
}
return 1;
}
//Init data
void Init_Cuda(float *M, float *N, unsigned int width)
{
const unsigned int size = width*width*sizeof(float);
//allocate matrix
hipMalloc((void**)&Md, size);
hipMemcpy(Md, M, size, hipMemcpyHostToDevice);
hipMalloc((void**)&Nd, size);
hipMemcpy(Nd, N, size,hipMemcpyHostToDevice);
hipMalloc((void**)&Pd, size);
hipMemset(Pd, 0, size);
}
//Free memory
void Free_Cuda()
{
hipFree(Md);
hipFree(Nd);
hipFree(Pd);
}
//kernel function
__global__ void MatrixMulKernel(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int i, r, c;
i = blockIdx.x*blockDim.x + threadIdx.x;
while(i<width*width)
{
r = i / width;
c = i % width;
float sum = 0.0;
for(int k=0; k<width; k++)
{ //sum+= M[r*width + k] * N[k * width + c];
float a = M[r*width +k];
float b = N[k*width +c];
//sum+= __ldg(&M[r*width + k]) * __ldg(&N[k * width + c]);
sum+= a * b;
}
P[r * width + c] = sum;
i+= gridDim.x * blockDim.x;
}
}
//ijk
__global__ void MatrixMulKernel_ijk(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
i = idx / width;
j = idx % width;
float sum = 0.0;
for(int k=0; k<width; k++)
{
float a = M[i*width + k];
float b = N[k*width + j];
sum+= a * b;
}
P[i * width + j] = sum;
idx+= gridDim.x * blockDim.x;
}
}
//ikj
__global__ void MatrixMulKernel_ikj(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
i = idx / width;
k = idx % width;
float a = M[i*width + k];
for(j=0; j<width; j++)
{
float b = N[k*width + j];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//jik
__global__ void MatrixMulKernel_jik(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
j = idx / width;
i = idx % width;
float sum = 0.0;
for(k=0; k<width; k++)
{
float a = M[i*width + k];
float b = N[k*width + j];
sum+= a * b;
}
P[i * width + j] = sum;
idx+= gridDim.x * blockDim.x;
}
}
//kij
__global__ void MatrixMulKernel_kij(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
k = idx / width;
i = idx % width;
float a = M[i*width + k];
for(j=0; j<width; j++)
{
float b = N[k*width + j];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//jki
__global__ void MatrixMulKernel_jki(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
j = idx / width;
k = idx % width;
float b = N[k*width + j];
for(i=0; i<width; i++)
{
float a = M[i*width + k];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
//kji
__global__ void MatrixMulKernel_kji(float *P, float* M, float* N, int width)
//__global__ void MatrixMulKernel(float *P, float* const __restrict__ M, float* const __restrict__ N, int width)
{
int idx, i, j, k;
idx = blockIdx.x*blockDim.x + threadIdx.x;
while(idx<width*width)
{
k = idx / width;
j = idx % width;
float b = N[k*width + j];
for(i=0; i<width; i++)
{
float a = M[i*width + k];
atomicAdd(&P[i*width + j], a * b);
}
idx+= gridDim.x * blockDim.x;
}
}
int MatrixMul(float *P, const float *M, const float *N, unsigned int n)
{
int i, j, k ;
float sum, a, b ;
for(i = 0 ;i < n; i++)
for(j = 0 ;j < n; j++)
{ sum = 0;
for(k = 0 ;k < n; k++)
{
a = M[i * n + k];
b = N[k * n + j];
sum += a*b;
}
P [ i* n + j] = (float)sum;
}
return 1;
}
int Check(float *KP, float *CP, unsigned int n)
{
int i, j;
float e = 0.001;
int correct = 1;
for(i = 0; i < n ; i++)
for(j = 0; j < n; j++)
{ if(abs(KP[i * n + j] - CP[i * n + j]) > e)
{ printf("%.10f %.10f\n", KP[i * n + j], CP[i * n + j]);
return 0;
}
}
return correct;
}
int main(int argc, char * argv[])
{
float *M, *N, *KP, *CP;
int width = 512;
hipEvent_t start, stop;
float elapsedTime;
//initialize host memory
//create number of blocks and number of threads
int T = 128;
dim3 block(T, 1, 1);
dim3 grid(((width*width)+ T - 1) / T, 1, 1);
if (argc != 4) /* argc should be 2 for correct execution */
{
/* We print argv[0] assuming it is the program name */
printf("Usage: %s %s %s %s.\n", argv[0], "[matrix_size]", "[block_div]", "[num_threads]");
exit(0);
} else {
//printf("Arguments: %d %d", atoi(argv[1]), atoi(argv[2]));
width = atoi(argv[1]);
block.x = atoi(argv[3]);
block.y = 1;
grid.x = ((width*width)/atoi(argv[2]) + (block.x * block.y) - 1) / (block.x*block.y);
//grid.x = ((width*width)/atoi(argv[2]) + block.x - 1) / block.x;
}
M = GenMatrix(width);
//PrintMatrix(M, width);
N = GenMatrix(width);
//PrintMatrix(N, width);
KP = GenMatrix(width);
CP = GenMatrix(width);
//initialize device memory
Init_Cuda(M, N, width);
//create cudaEvent start and stop to record elapsed time
hipEventCreate(&start);
hipEventCreate(&stop);
//record start time to start event
for (int ver = 0; ver < 6; ver++) {
//record start time to start event
hipEventRecord(start, 0);
switch (ver) {
case IJK:
MatrixMulKernel_ijk<<<grid, block>>>(Pd, Md, Nd, width);
break;
case IKJ:
MatrixMulKernel_ikj<<<grid, block>>>(Pd, Md, Nd, width);
break;
case JIK:
MatrixMulKernel_jik<<<grid, block>>>(Pd, Md, Nd, width);
break;
case KIJ:
MatrixMulKernel_kij<<<grid, block>>>(Pd, Md, Nd, width);
break;
case JKI:
MatrixMulKernel_jki<<<grid, block>>>(Pd, Md, Nd, width);
break;
case KJI:
MatrixMulKernel_kji<<<grid, block>>>(Pd, Md, Nd, width);
break;
default:
MatrixMulKernel_ijk<<<grid, block>>>(Pd, Md, Nd, width);
break;
}
//record start time to stop event
hipEventRecord(stop, 0);
//synchronize the stop event
hipEventSynchronize(stop);
//calculate the elapsed time
hipEventElapsedTime(&elapsedTime, start, stop);
switch (ver) {
case IJK:
printf("ijk %.3f (ms)\n", elapsedTime);
break;
case IKJ:
printf("ikj %.3f (ms)\n", elapsedTime);
break;
case JIK:
printf("jik %.3f (ms)\n", elapsedTime);
break;
case KIJ:
printf("kij %.3f (ms)\n", elapsedTime);
break;
case JKI:
printf("jki %.3f (ms)\n", elapsedTime);
break;
case KJI:
printf("kji %.3f (ms)\n", elapsedTime);
break;
default:
printf("ijk %.3f (ms)\n", elapsedTime);
break;
}
//copy data from device memory to host memory
hipMemcpy(KP, Pd, width*width*sizeof(float), hipMemcpyDeviceToHost);
#if (CHECK)
MatrixMul(CP, M, N, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix(CP, width);
if(Check(KP, CP, width))
printf(" We do it.\n");
else
printf(" Something is wrong.\n");
#endif
hipMemset(Pd, 0, width*width*sizeof(float));
}
//destroy the start and stop event
hipEventDestroy(start);
hipEventDestroy(stop);
//PrintMatrix(P, width);
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(M, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(N, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix(KP, width);
*/
//free host memory
free(M);
free(N);
free(KP);
free(CP);
//free device memory
Free_Cuda();
return 0;
} | .text
.file "s_mm_1D.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9GenMatrixj
.LCPI0_0:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl _Z9GenMatrixj
.p2align 4, 0x90
.type _Z9GenMatrixj,@function
_Z9GenMatrixj: # @_Z9GenMatrixj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
imull %edi, %edi
shlq $2, %rdi
callq malloc
movq %rax, %rbx
testl %ebp, %ebp
je .LBB0_5
# %bb.1: # %.preheader.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
leal (%r15,%r12), %eax
movss %xmm0, (%rbx,%rax,4)
incq %r12
cmpq %r12, %r14
jne .LBB0_3
# %bb.4: # in Loop: Header=BB0_2 Depth=1
incl %ebp
addq %r14, %r15
cmpl %r14d, %ebp
jne .LBB0_2
.LBB0_5: # %._crit_edge
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9GenMatrixj, .Lfunc_end0-_Z9GenMatrixj
.cfi_endproc
# -- End function
.globl _Z11PrintMatrixPfj # -- Begin function _Z11PrintMatrixPfj
.p2align 4, 0x90
.type _Z11PrintMatrixPfj,@function
_Z11PrintMatrixPfj: # @_Z11PrintMatrixPfj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $10, %edi
callq putchar@PLT
testl %ebp, %ebp
je .LBB1_5
# %bb.1: # %.preheader.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r15,%r12), %eax
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r14
jne .LBB1_3
# %bb.4: # in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
addq %r14, %r15
cmpl %r14d, %ebp
jne .LBB1_2
.LBB1_5: # %._crit_edge
movl $1, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11PrintMatrixPfj, .Lfunc_end1-_Z11PrintMatrixPfj
.cfi_endproc
# -- End function
.globl _Z9Init_CudaPfS_j # -- Begin function _Z9Init_CudaPfS_j
.p2align 4, 0x90
.type _Z9Init_CudaPfS_j,@function
_Z9Init_CudaPfS_j: # @_Z9Init_CudaPfS_j
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
imull %ebx, %ebx
shll $2, %ebx
movl $Md, %edi
movq %rbx, %rsi
callq hipMalloc
movq Md(%rip), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl $Nd, %edi
movq %rbx, %rsi
callq hipMalloc
movq Nd(%rip), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl $Pd, %edi
movq %rbx, %rsi
callq hipMalloc
movq Pd(%rip), %rdi
xorl %esi, %esi
movq %rbx, %rdx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipMemset # TAILCALL
.Lfunc_end2:
.size _Z9Init_CudaPfS_j, .Lfunc_end2-_Z9Init_CudaPfS_j
.cfi_endproc
# -- End function
.globl _Z9Free_Cudav # -- Begin function _Z9Free_Cudav
.p2align 4, 0x90
.type _Z9Free_Cudav,@function
_Z9Free_Cudav: # @_Z9Free_Cudav
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq Md(%rip), %rdi
callq hipFree
movq Nd(%rip), %rdi
callq hipFree
movq Pd(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end3:
.size _Z9Free_Cudav, .Lfunc_end3-_Z9Free_Cudav
.cfi_endproc
# -- End function
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end4-_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__MatrixMulKernel_ijkPfS_S_i # -- Begin function _Z34__device_stub__MatrixMulKernel_ijkPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__MatrixMulKernel_ijkPfS_S_i,@function
_Z34__device_stub__MatrixMulKernel_ijkPfS_S_i: # @_Z34__device_stub__MatrixMulKernel_ijkPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19MatrixMulKernel_ijkPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z34__device_stub__MatrixMulKernel_ijkPfS_S_i, .Lfunc_end5-_Z34__device_stub__MatrixMulKernel_ijkPfS_S_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__MatrixMulKernel_ikjPfS_S_i # -- Begin function _Z34__device_stub__MatrixMulKernel_ikjPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__MatrixMulKernel_ikjPfS_S_i,@function
_Z34__device_stub__MatrixMulKernel_ikjPfS_S_i: # @_Z34__device_stub__MatrixMulKernel_ikjPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19MatrixMulKernel_ikjPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z34__device_stub__MatrixMulKernel_ikjPfS_S_i, .Lfunc_end6-_Z34__device_stub__MatrixMulKernel_ikjPfS_S_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__MatrixMulKernel_jikPfS_S_i # -- Begin function _Z34__device_stub__MatrixMulKernel_jikPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__MatrixMulKernel_jikPfS_S_i,@function
_Z34__device_stub__MatrixMulKernel_jikPfS_S_i: # @_Z34__device_stub__MatrixMulKernel_jikPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19MatrixMulKernel_jikPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size _Z34__device_stub__MatrixMulKernel_jikPfS_S_i, .Lfunc_end7-_Z34__device_stub__MatrixMulKernel_jikPfS_S_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__MatrixMulKernel_kijPfS_S_i # -- Begin function _Z34__device_stub__MatrixMulKernel_kijPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__MatrixMulKernel_kijPfS_S_i,@function
_Z34__device_stub__MatrixMulKernel_kijPfS_S_i: # @_Z34__device_stub__MatrixMulKernel_kijPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19MatrixMulKernel_kijPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end8:
.size _Z34__device_stub__MatrixMulKernel_kijPfS_S_i, .Lfunc_end8-_Z34__device_stub__MatrixMulKernel_kijPfS_S_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__MatrixMulKernel_jkiPfS_S_i # -- Begin function _Z34__device_stub__MatrixMulKernel_jkiPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__MatrixMulKernel_jkiPfS_S_i,@function
_Z34__device_stub__MatrixMulKernel_jkiPfS_S_i: # @_Z34__device_stub__MatrixMulKernel_jkiPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19MatrixMulKernel_jkiPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end9:
.size _Z34__device_stub__MatrixMulKernel_jkiPfS_S_i, .Lfunc_end9-_Z34__device_stub__MatrixMulKernel_jkiPfS_S_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__MatrixMulKernel_kjiPfS_S_i # -- Begin function _Z34__device_stub__MatrixMulKernel_kjiPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__MatrixMulKernel_kjiPfS_S_i,@function
_Z34__device_stub__MatrixMulKernel_kjiPfS_S_i: # @_Z34__device_stub__MatrixMulKernel_kjiPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19MatrixMulKernel_kjiPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end10:
.size _Z34__device_stub__MatrixMulKernel_kjiPfS_S_i, .Lfunc_end10-_Z34__device_stub__MatrixMulKernel_kjiPfS_S_i
.cfi_endproc
# -- End function
.globl _Z9MatrixMulPfPKfS1_j # -- Begin function _Z9MatrixMulPfPKfS1_j
.p2align 4, 0x90
.type _Z9MatrixMulPfPKfS1_j,@function
_Z9MatrixMulPfPKfS1_j: # @_Z9MatrixMulPfPKfS1_j
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
je .LBB11_8
# %bb.1: # %.preheader28.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB11_2: # %.preheader28
# =>This Loop Header: Depth=1
# Child Loop BB11_3 Depth 2
# Child Loop BB11_4 Depth 3
movl %r9d, %r10d
imull %ecx, %r10d
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB11_3: # %.preheader
# Parent Loop BB11_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB11_4 Depth 3
xorps %xmm0, %xmm0
movl %r11d, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB11_4: # Parent Loop BB11_2 Depth=1
# Parent Loop BB11_3 Depth=2
# => This Inner Loop Header: Depth=3
leal (%r8,%r14), %r15d
movss (%rsi,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %ebx, %r15d
mulss (%rdx,%r15,4), %xmm1
addss %xmm1, %xmm0
incq %r14
addl %ecx, %ebx
cmpq %r14, %rax
jne .LBB11_4
# %bb.5: # in Loop: Header=BB11_3 Depth=2
leal (%r10,%r11), %ebx
movss %xmm0, (%rdi,%rbx,4)
incq %r11
cmpq %rax, %r11
jne .LBB11_3
# %bb.6: # in Loop: Header=BB11_2 Depth=1
incl %r9d
addq %rax, %r8
cmpl %eax, %r9d
jne .LBB11_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB11_8: # %._crit_edge
movl $1, %eax
retq
.Lfunc_end11:
.size _Z9MatrixMulPfPKfS1_j, .Lfunc_end11-_Z9MatrixMulPfPKfS1_j
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z5CheckPfS_j
.LCPI12_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI12_1:
.long 0x3a83126f # float 0.00100000005
.text
.globl _Z5CheckPfS_j
.p2align 4, 0x90
.type _Z5CheckPfS_j,@function
_Z5CheckPfS_j: # @_Z5CheckPfS_j
.cfi_startproc
# %bb.0:
movl $1, %eax
testl %edx, %edx
je .LBB12_7
# %bb.1: # %.preheader.preheader
movl %edx, %ecx
xorl %edx, %edx
movaps .LCPI12_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movss .LCPI12_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %r8d, %r8d
.LBB12_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB12_4 Depth 2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB12_4: # Parent Loop BB12_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%r9), %r10d
movss (%rdi,%r10,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rsi,%r10,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
ucomiss %xmm1, %xmm4
ja .LBB12_5
# %bb.3: # in Loop: Header=BB12_4 Depth=2
incq %r9
cmpq %r9, %rcx
jne .LBB12_4
# %bb.6: # in Loop: Header=BB12_2 Depth=1
incl %r8d
addq %rcx, %rdx
cmpl %ecx, %r8d
jne .LBB12_2
.LBB12_7: # %.loopexit
retq
.LBB12_5:
pushq %rax
.cfi_def_cfa_offset 16
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str.2, %edi
movb $2, %al
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end12:
.size _Z5CheckPfS_j, .Lfunc_end12-_Z5CheckPfS_j
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI13_0:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
cmpl $4, %edi
jne .LBB13_41
# %bb.1:
movq 8(%r14), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 128(%rsp) # 8-byte Spill
movl %eax, %ebx
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %ebx, %r15d
imull %r15d, %r15d
movq 16(%r14), %rdi
movl %ebx, %r14d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rcx
movl %r15d, %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
addl %r12d, %eax
decl %eax
xorl %edx, %edx
movq %r12, 136(%rsp) # 8-byte Spill
divl %r12d
# kill: def $eax killed $eax def $rax
movq %rax, 184(%rsp) # 8-byte Spill
shlq $2, %r15
movq %r15, 152(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, 176(%rsp) # 8-byte Spill
testl %ebx, %ebx
je .LBB13_6
# %bb.2: # %.preheader.i.preheader
movl 128(%rsp), %eax # 4-byte Reload
movq %rax, 88(%rsp) # 8-byte Spill
xorl %ebx, %ebx
movq 176(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB13_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB13_4 Depth 2
movl %r13d, %r15d
movq 88(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB13_4: # Parent Loop BB13_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI13_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movl %r15d, %eax
movss %xmm0, (%r12,%rax,4)
incl %r15d
decq %rbp
jne .LBB13_4
# %bb.5: # in Loop: Header=BB13_3 Depth=1
incl %ebx
addl %r14d, %r13d
cmpl %r14d, %ebx
jne .LBB13_3
.LBB13_6: # %_Z9GenMatrixj.exit
movl 136(%rsp), %eax # 4-byte Reload
movq %rax, 136(%rsp) # 8-byte Spill
movq 152(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r12
testl %r14d, %r14d
je .LBB13_11
# %bb.7: # %.preheader.i100.preheader
movl 128(%rsp), %eax # 4-byte Reload
movq %rax, 88(%rsp) # 8-byte Spill
xorl %ebp, %ebp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB13_8: # %.preheader.i100
# =>This Loop Header: Depth=1
# Child Loop BB13_9 Depth 2
movl %ebp, %r15d
movq 88(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB13_9: # Parent Loop BB13_8 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI13_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movl %r15d, %eax
movss %xmm0, (%r12,%rax,4)
incl %r15d
decq %r13
jne .LBB13_9
# %bb.10: # in Loop: Header=BB13_8 Depth=1
incl %ebx
addl %r14d, %ebp
cmpl %r14d, %ebx
jne .LBB13_8
.LBB13_11: # %_Z9GenMatrixj.exit107
movabsq $4294967296, %r13 # imm = 0x100000000
movq 152(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %rbp
movl %r14d, 88(%rsp) # 4-byte Spill
testl %r14d, %r14d
je .LBB13_21
# %bb.12: # %.preheader.i109.preheader
movl 128(%rsp), %eax # 4-byte Reload
movq %rax, 192(%rsp) # 8-byte Spill
xorl %r13d, %r13d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB13_13: # %.preheader.i109
# =>This Loop Header: Depth=1
# Child Loop BB13_14 Depth 2
movl %r13d, %ebx
movq 192(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB13_14: # Parent Loop BB13_13 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI13_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movl %ebx, %eax
movss %xmm0, (%rbp,%rax,4)
incl %ebx
decq %r14
jne .LBB13_14
# %bb.15: # in Loop: Header=BB13_13 Depth=1
incl %r15d
movl 88(%rsp), %eax # 4-byte Reload
addl %eax, %r13d
cmpl %eax, %r15d
jne .LBB13_13
# %bb.16: # %_Z9GenMatrixj.exit116
cmpl $0, 88(%rsp) # 4-byte Folded Reload
movabsq $4294967296, %r13 # imm = 0x100000000
je .LBB13_21
# %bb.17: # %.preheader.i118.preheader
movl 128(%rsp), %ebx # 4-byte Reload
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB13_18: # %.preheader.i118
# =>This Loop Header: Depth=1
# Child Loop BB13_19 Depth 2
movq %rbx, %r15
.p2align 4, 0x90
.LBB13_19: # Parent Loop BB13_18 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
decq %r15
jne .LBB13_19
# %bb.20: # in Loop: Header=BB13_18 Depth=1
incl %r14d
cmpl 88(%rsp), %r14d # 4-byte Folded Reload
jne .LBB13_18
.LBB13_21: # %_Z9GenMatrixj.exit125
addq %r13, 136(%rsp) # 8-byte Folded Spill
addq %r13, 184(%rsp) # 8-byte Folded Spill
movq 128(%rsp), %rbx # 8-byte Reload
imull %ebx, %ebx
shll $2, %ebx
movl $Md, %edi
movq %rbx, %rsi
callq hipMalloc
movq Md(%rip), %rdi
movq 176(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl $Nd, %edi
movq %rbx, %rsi
callq hipMalloc
movq Nd(%rip), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl $Pd, %edi
movq %rbx, %rsi
callq hipMalloc
movq Pd(%rip), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
leaq 160(%rsp), %rdi
callq hipEventCreate
leaq 144(%rsp), %rdi
callq hipEventCreate
movl 88(%rsp), %ebx # 4-byte Reload
movq 152(%rsp), %r14 # 8-byte Reload
jmp .LBB13_22
.p2align 4, 0x90
.LBB13_39: # in Loop: Header=BB13_22 Depth=1
cvtss2sd %xmm0, %xmm0
movb $1, %al
callq printf
movq Pd(%rip), %rsi
movq %rbp, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq Pd(%rip), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq hipMemset
incq %r13
cmpl $6, %r13d
je .LBB13_40
.LBB13_22: # =>This Inner Loop Header: Depth=1
movq 160(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 184(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 136(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
cmpl $5, %r13d
ja .LBB13_34
# %bb.23: # in Loop: Header=BB13_22 Depth=1
movl %r13d, %ecx
jmpq *.LJTI13_0(,%rcx,8)
.LBB13_34: # in Loop: Header=BB13_22 Depth=1
testl %eax, %eax
jne .LBB13_37
# %bb.35: # in Loop: Header=BB13_22 Depth=1
movq Pd(%rip), %rax
movq Md(%rip), %rcx
movq Nd(%rip), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z19MatrixMulKernel_ijkPfS_S_i, %edi
jmp .LBB13_36
.LBB13_30: # in Loop: Header=BB13_22 Depth=1
testl %eax, %eax
jne .LBB13_37
# %bb.31: # in Loop: Header=BB13_22 Depth=1
movq Pd(%rip), %rax
movq Md(%rip), %rcx
movq Nd(%rip), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z19MatrixMulKernel_jkiPfS_S_i, %edi
jmp .LBB13_36
.LBB13_26: # in Loop: Header=BB13_22 Depth=1
testl %eax, %eax
jne .LBB13_37
# %bb.27: # in Loop: Header=BB13_22 Depth=1
movq Pd(%rip), %rax
movq Md(%rip), %rcx
movq Nd(%rip), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z19MatrixMulKernel_jikPfS_S_i, %edi
jmp .LBB13_36
.LBB13_28: # in Loop: Header=BB13_22 Depth=1
testl %eax, %eax
jne .LBB13_37
# %bb.29: # in Loop: Header=BB13_22 Depth=1
movq Pd(%rip), %rax
movq Md(%rip), %rcx
movq Nd(%rip), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z19MatrixMulKernel_kijPfS_S_i, %edi
jmp .LBB13_36
.LBB13_24: # in Loop: Header=BB13_22 Depth=1
testl %eax, %eax
jne .LBB13_37
# %bb.25: # in Loop: Header=BB13_22 Depth=1
movq Pd(%rip), %rax
movq Md(%rip), %rcx
movq Nd(%rip), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z19MatrixMulKernel_ikjPfS_S_i, %edi
jmp .LBB13_36
.LBB13_32: # in Loop: Header=BB13_22 Depth=1
testl %eax, %eax
jne .LBB13_37
# %bb.33: # in Loop: Header=BB13_22 Depth=1
movq Pd(%rip), %rax
movq Md(%rip), %rcx
movq Nd(%rip), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z19MatrixMulKernel_kjiPfS_S_i, %edi
.p2align 4, 0x90
.LBB13_36: # in Loop: Header=BB13_22 Depth=1
leaq 96(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB13_37: # in Loop: Header=BB13_22 Depth=1
movq 144(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 144(%rsp), %rdi
callq hipEventSynchronize
movq 160(%rsp), %rsi
movq 144(%rsp), %rdx
leaq 172(%rsp), %rdi
callq hipEventElapsedTime
movss 172(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $.L.str.7, %edi
cmpl $5, %r13d
ja .LBB13_39
# %bb.38: # %switch.lookup
# in Loop: Header=BB13_22 Depth=1
movq .Lswitch.table.main(,%r13,8), %rdi
jmp .LBB13_39
.LBB13_40:
movq 160(%rsp), %rdi
callq hipEventDestroy
movq 144(%rsp), %rdi
callq hipEventDestroy
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %rbp, %rdi
callq free
movq Md(%rip), %rdi
callq hipFree
movq Nd(%rip), %rdi
callq hipFree
movq Pd(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB13_41:
.cfi_def_cfa_offset 256
movq (%r14), %rsi
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movl $.L.str.5, %ecx
movl $.L.str.6, %r8d
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end13:
.size main, .Lfunc_end13-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI13_0:
.quad .LBB13_34
.quad .LBB13_24
.quad .LBB13_26
.quad .LBB13_28
.quad .LBB13_30
.quad .LBB13_32
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB14_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB14_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MatrixMulKernel_ijkPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MatrixMulKernel_ikjPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MatrixMulKernel_jikPfS_S_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MatrixMulKernel_kijPfS_S_i, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MatrixMulKernel_jkiPfS_S_i, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MatrixMulKernel_kjiPfS_S_i, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end14:
.size __hip_module_ctor, .Lfunc_end14-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB15_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB15_2:
retq
.Lfunc_end15:
.size __hip_module_dtor, .Lfunc_end15-__hip_module_dtor
.cfi_endproc
# -- End function
.type Md,@object # @Md
.bss
.globl Md
.p2align 3, 0x0
Md:
.quad 0
.size Md, 8
.type Nd,@object # @Nd
.globl Nd
.p2align 3, 0x0
Nd:
.quad 0
.size Nd, 8
.type Pd,@object # @Pd
.globl Pd
.p2align 3, 0x0
Pd:
.quad 0
.size Pd, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.3f\t"
.size .L.str.1, 6
.type _Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_i
.size _Z15MatrixMulKernelPfS_S_i, 8
.type _Z19MatrixMulKernel_ijkPfS_S_i,@object # @_Z19MatrixMulKernel_ijkPfS_S_i
.globl _Z19MatrixMulKernel_ijkPfS_S_i
.p2align 3, 0x0
_Z19MatrixMulKernel_ijkPfS_S_i:
.quad _Z34__device_stub__MatrixMulKernel_ijkPfS_S_i
.size _Z19MatrixMulKernel_ijkPfS_S_i, 8
.type _Z19MatrixMulKernel_ikjPfS_S_i,@object # @_Z19MatrixMulKernel_ikjPfS_S_i
.globl _Z19MatrixMulKernel_ikjPfS_S_i
.p2align 3, 0x0
_Z19MatrixMulKernel_ikjPfS_S_i:
.quad _Z34__device_stub__MatrixMulKernel_ikjPfS_S_i
.size _Z19MatrixMulKernel_ikjPfS_S_i, 8
.type _Z19MatrixMulKernel_jikPfS_S_i,@object # @_Z19MatrixMulKernel_jikPfS_S_i
.globl _Z19MatrixMulKernel_jikPfS_S_i
.p2align 3, 0x0
_Z19MatrixMulKernel_jikPfS_S_i:
.quad _Z34__device_stub__MatrixMulKernel_jikPfS_S_i
.size _Z19MatrixMulKernel_jikPfS_S_i, 8
.type _Z19MatrixMulKernel_kijPfS_S_i,@object # @_Z19MatrixMulKernel_kijPfS_S_i
.globl _Z19MatrixMulKernel_kijPfS_S_i
.p2align 3, 0x0
_Z19MatrixMulKernel_kijPfS_S_i:
.quad _Z34__device_stub__MatrixMulKernel_kijPfS_S_i
.size _Z19MatrixMulKernel_kijPfS_S_i, 8
.type _Z19MatrixMulKernel_jkiPfS_S_i,@object # @_Z19MatrixMulKernel_jkiPfS_S_i
.globl _Z19MatrixMulKernel_jkiPfS_S_i
.p2align 3, 0x0
_Z19MatrixMulKernel_jkiPfS_S_i:
.quad _Z34__device_stub__MatrixMulKernel_jkiPfS_S_i
.size _Z19MatrixMulKernel_jkiPfS_S_i, 8
.type _Z19MatrixMulKernel_kjiPfS_S_i,@object # @_Z19MatrixMulKernel_kjiPfS_S_i
.globl _Z19MatrixMulKernel_kjiPfS_S_i
.p2align 3, 0x0
_Z19MatrixMulKernel_kjiPfS_S_i:
.quad _Z34__device_stub__MatrixMulKernel_kjiPfS_S_i
.size _Z19MatrixMulKernel_kjiPfS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%.10f %.10f\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Usage: %s %s %s %s.\n"
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[matrix_size]"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "[block_div]"
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "[num_threads]"
.size .L.str.6, 14
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "ijk %.3f (ms)\n"
.size .L.str.7, 15
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "ikj %.3f (ms)\n"
.size .L.str.8, 15
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "jik %.3f (ms)\n"
.size .L.str.9, 15
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "kij %.3f (ms)\n"
.size .L.str.10, 15
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "jki %.3f (ms)\n"
.size .L.str.11, 15
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "kji %.3f (ms)\n"
.size .L.str.12, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19MatrixMulKernel_ijkPfS_S_i"
.size .L__unnamed_2, 31
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z19MatrixMulKernel_ikjPfS_S_i"
.size .L__unnamed_3, 31
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z19MatrixMulKernel_jikPfS_S_i"
.size .L__unnamed_4, 31
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z19MatrixMulKernel_kijPfS_S_i"
.size .L__unnamed_5, 31
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z19MatrixMulKernel_jkiPfS_S_i"
.size .L__unnamed_6, 31
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z19MatrixMulKernel_kjiPfS_S_i"
.size .L__unnamed_7, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lswitch.table.main,@object # @switch.table.main
.section .rodata,"a",@progbits
.p2align 3, 0x0
.Lswitch.table.main:
.quad .L.str.7
.quad .L.str.8
.quad .L.str.9
.quad .L.str.10
.quad .L.str.11
.quad .L.str.12
.size .Lswitch.table.main, 48
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i
.addrsig_sym _Z34__device_stub__MatrixMulKernel_ijkPfS_S_i
.addrsig_sym _Z34__device_stub__MatrixMulKernel_ikjPfS_S_i
.addrsig_sym _Z34__device_stub__MatrixMulKernel_jikPfS_S_i
.addrsig_sym _Z34__device_stub__MatrixMulKernel_kijPfS_S_i
.addrsig_sym _Z34__device_stub__MatrixMulKernel_jkiPfS_S_i
.addrsig_sym _Z34__device_stub__MatrixMulKernel_kjiPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Md
.addrsig_sym Nd
.addrsig_sym Pd
.addrsig_sym _Z15MatrixMulKernelPfS_S_i
.addrsig_sym _Z19MatrixMulKernel_ijkPfS_S_i
.addrsig_sym _Z19MatrixMulKernel_ikjPfS_S_i
.addrsig_sym _Z19MatrixMulKernel_jikPfS_S_i
.addrsig_sym _Z19MatrixMulKernel_kijPfS_S_i
.addrsig_sym _Z19MatrixMulKernel_jkiPfS_S_i
.addrsig_sym _Z19MatrixMulKernel_kjiPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void makeEigenvalues( float *eigenvalues, float *blockHessian, int *blocknums, int *blocksizes, int *hessiannums, int N, int numblocks ) {
// elementnum is the degree of freedom (0 to 3n-1)
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
if( elementNum >= N ) {
return;
}
// b is the block number in which DOF elementnum resides
// blocknums contains atom numbers, so we must divide by 3
// We find the first index with an atom number larger than
// ours, and take one less (or numblocks-1 if we are at the end)
int b = 0;
while( b < numblocks ) {
if( blocknums[b] > elementNum / 3 ) {
break;
}
b++;
}
b--;
// 3*blocknums[b] is the starting degree of freedom for our block
// We must compute an offset from that, call it x.
int x = elementNum - 3 * blocknums[b];
// We initialize our spot to hessiannums[b], which is the starting
// Hessian location for our block.
// We then want to take the diagonal entry from that offset
// So element (x,x)
int spot = hessiannums[b] + x * ( 3 * blocksizes[b] ) + x;
eigenvalues[elementNum] = blockHessian[spot];
} | code for sm_80
Function : _Z15makeEigenvaluesPfS_PiS0_S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x188], PT ; /* 0x000062000a007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x18c] ; /* 0x0000630000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0090*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fd800000001ff */
/*00a0*/ @!P0 BRA 0x180 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.HI R2, R10, 0x55555556, RZ ; /* 0x555555560a027827 */
/* 0x000fe200078e02ff */
/*00c0*/ BSSY B0, 0x180 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*00d0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fc60000000f00 */
/*00e0*/ LEA.HI R4, R2, R2, RZ, 0x1 ; /* 0x0000000202047211 */
/* 0x000fe400078f08ff */
/*00f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0120*/ ISETP.GT.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x004fda0003f04270 */
/*0130*/ @P0 BRA 0x170 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x18c], PT ; /* 0x0000630000007a0c */
/* 0x000fda0003f06270 */
/*0160*/ @!P0 BRA 0xf0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0190*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fca0000000f00 */
/*01a0*/ IMAD.WIDE R2, R0, R11, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e020b */
/*01b0*/ IMAD.WIDE R4, R0.reuse, R11.reuse, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x0c0fe400078e020b */
/*01c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ IMAD.WIDE R6, R0, R11, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe400078e020b */
/*01e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee8000c1e1900 */
/*01f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0200*/ IMAD R0, R3, -0x3, R10 ; /* 0xfffffffd03007824 */
/* 0x004fca00078e020a */
/*0210*/ IADD3 R8, R0, R5, RZ ; /* 0x0000000500087210 */
/* 0x008fe20007ffe0ff */
/*0220*/ IMAD R9, R6, 0x3, RZ ; /* 0x0000000306097824 */
/* 0x010fc800078e02ff */
/*0230*/ IMAD R8, R0, R9, R8 ; /* 0x0000000900087224 */
/* 0x000fc800078e0208 */
/*0240*/ IMAD.WIDE R8, R8, R11, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fcc00078e020b */
/*0250*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e020b */
/*0270*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x004fe2000c101904 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void makeEigenvalues( float *eigenvalues, float *blockHessian, int *blocknums, int *blocksizes, int *hessiannums, int N, int numblocks ) {
// elementnum is the degree of freedom (0 to 3n-1)
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
if( elementNum >= N ) {
return;
}
// b is the block number in which DOF elementnum resides
// blocknums contains atom numbers, so we must divide by 3
// We find the first index with an atom number larger than
// ours, and take one less (or numblocks-1 if we are at the end)
int b = 0;
while( b < numblocks ) {
if( blocknums[b] > elementNum / 3 ) {
break;
}
b++;
}
b--;
// 3*blocknums[b] is the starting degree of freedom for our block
// We must compute an offset from that, call it x.
int x = elementNum - 3 * blocknums[b];
// We initialize our spot to hessiannums[b], which is the starting
// Hessian location for our block.
// We then want to take the diagonal entry from that offset
// So element (x,x)
int spot = hessiannums[b] + x * ( 3 * blocksizes[b] ) + x;
eigenvalues[elementNum] = blockHessian[spot];
} | .file "tmpxft_0003318e_00000000-6_makeEigenvalues.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii
.type _Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii, @function
_Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15makeEigenvaluesPfS_PiS0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii, .-_Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii
.globl _Z15makeEigenvaluesPfS_PiS0_S0_ii
.type _Z15makeEigenvaluesPfS_PiS0_S0_ii, @function
_Z15makeEigenvaluesPfS_PiS0_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15makeEigenvaluesPfS_PiS0_S0_ii, .-_Z15makeEigenvaluesPfS_PiS0_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15makeEigenvaluesPfS_PiS0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15makeEigenvaluesPfS_PiS0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void makeEigenvalues( float *eigenvalues, float *blockHessian, int *blocknums, int *blocksizes, int *hessiannums, int N, int numblocks ) {
// elementnum is the degree of freedom (0 to 3n-1)
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
if( elementNum >= N ) {
return;
}
// b is the block number in which DOF elementnum resides
// blocknums contains atom numbers, so we must divide by 3
// We find the first index with an atom number larger than
// ours, and take one less (or numblocks-1 if we are at the end)
int b = 0;
while( b < numblocks ) {
if( blocknums[b] > elementNum / 3 ) {
break;
}
b++;
}
b--;
// 3*blocknums[b] is the starting degree of freedom for our block
// We must compute an offset from that, call it x.
int x = elementNum - 3 * blocknums[b];
// We initialize our spot to hessiannums[b], which is the starting
// Hessian location for our block.
// We then want to take the diagonal entry from that offset
// So element (x,x)
int spot = hessiannums[b] + x * ( 3 * blocksizes[b] ) + x;
eigenvalues[elementNum] = blockHessian[spot];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void makeEigenvalues( float *eigenvalues, float *blockHessian, int *blocknums, int *blocksizes, int *hessiannums, int N, int numblocks ) {
// elementnum is the degree of freedom (0 to 3n-1)
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
if( elementNum >= N ) {
return;
}
// b is the block number in which DOF elementnum resides
// blocknums contains atom numbers, so we must divide by 3
// We find the first index with an atom number larger than
// ours, and take one less (or numblocks-1 if we are at the end)
int b = 0;
while( b < numblocks ) {
if( blocknums[b] > elementNum / 3 ) {
break;
}
b++;
}
b--;
// 3*blocknums[b] is the starting degree of freedom for our block
// We must compute an offset from that, call it x.
int x = elementNum - 3 * blocknums[b];
// We initialize our spot to hessiannums[b], which is the starting
// Hessian location for our block.
// We then want to take the diagonal entry from that offset
// So element (x,x)
int spot = hessiannums[b] + x * ( 3 * blocksizes[b] ) + x;
eigenvalues[elementNum] = blockHessian[spot];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void makeEigenvalues( float *eigenvalues, float *blockHessian, int *blocknums, int *blocksizes, int *hessiannums, int N, int numblocks ) {
// elementnum is the degree of freedom (0 to 3n-1)
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
if( elementNum >= N ) {
return;
}
// b is the block number in which DOF elementnum resides
// blocknums contains atom numbers, so we must divide by 3
// We find the first index with an atom number larger than
// ours, and take one less (or numblocks-1 if we are at the end)
int b = 0;
while( b < numblocks ) {
if( blocknums[b] > elementNum / 3 ) {
break;
}
b++;
}
b--;
// 3*blocknums[b] is the starting degree of freedom for our block
// We must compute an offset from that, call it x.
int x = elementNum - 3 * blocknums[b];
// We initialize our spot to hessiannums[b], which is the starting
// Hessian location for our block.
// We then want to take the diagonal entry from that offset
// So element (x,x)
int spot = hessiannums[b] + x * ( 3 * blocksizes[b] ) + x;
eigenvalues[elementNum] = blockHessian[spot];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15makeEigenvaluesPfS_PiS0_S0_ii
.globl _Z15makeEigenvaluesPfS_PiS0_S0_ii
.p2align 8
.type _Z15makeEigenvaluesPfS_PiS0_S0_ii,@function
_Z15makeEigenvaluesPfS_PiS0_S0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_9
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_7
v_mul_hi_i32 v0, v1, 0x55555556
s_mov_b32 s7, 0
s_mov_b64 s[4:5], s[2:3]
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s10, exec_lo, s9
s_or_b32 s7, s10, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_6
.LBB0_4:
s_load_b32 s10, s[4:5], 0x0
v_mov_b32_e32 v2, s8
s_or_b32 s9, s9, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s10, v0
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_3
s_add_i32 s8, s8, 1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s6, s8
v_mov_b32_e32 v2, s6
s_cselect_b32 s11, -1, 0
s_and_not1_b32 s9, s9, exec_lo
s_and_b32 s11, s11, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s9, s9, s11
s_branch .LBB0_3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v2, -1, v2
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_branch .LBB0_8
.LBB0_7:
v_mov_b32_e32 v2, -1
v_mov_b32_e32 v3, -1
.LBB0_8:
s_load_b128 s[4:7], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v0, v[4:5], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(2)
v_mad_u64_u32 v[2:3], null, v0, -3, v[1:2]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v4, v2
v_lshl_add_u32 v0, v0, 1, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v2, v5, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15makeEigenvaluesPfS_PiS0_S0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15makeEigenvaluesPfS_PiS0_S0_ii, .Lfunc_end0-_Z15makeEigenvaluesPfS_PiS0_S0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15makeEigenvaluesPfS_PiS0_S0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15makeEigenvaluesPfS_PiS0_S0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void makeEigenvalues( float *eigenvalues, float *blockHessian, int *blocknums, int *blocksizes, int *hessiannums, int N, int numblocks ) {
// elementnum is the degree of freedom (0 to 3n-1)
int elementNum = blockIdx.x * blockDim.x + threadIdx.x;
if( elementNum >= N ) {
return;
}
// b is the block number in which DOF elementnum resides
// blocknums contains atom numbers, so we must divide by 3
// We find the first index with an atom number larger than
// ours, and take one less (or numblocks-1 if we are at the end)
int b = 0;
while( b < numblocks ) {
if( blocknums[b] > elementNum / 3 ) {
break;
}
b++;
}
b--;
// 3*blocknums[b] is the starting degree of freedom for our block
// We must compute an offset from that, call it x.
int x = elementNum - 3 * blocknums[b];
// We initialize our spot to hessiannums[b], which is the starting
// Hessian location for our block.
// We then want to take the diagonal entry from that offset
// So element (x,x)
int spot = hessiannums[b] + x * ( 3 * blocksizes[b] ) + x;
eigenvalues[elementNum] = blockHessian[spot];
} | .text
.file "makeEigenvalues.hip"
.globl _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii # -- Begin function _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii
.p2align 4, 0x90
.type _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii,@function
_Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii: # @_Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15makeEigenvaluesPfS_PiS0_S0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii, .Lfunc_end0-_Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15makeEigenvaluesPfS_PiS0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15makeEigenvaluesPfS_PiS0_S0_ii,@object # @_Z15makeEigenvaluesPfS_PiS0_S0_ii
.section .rodata,"a",@progbits
.globl _Z15makeEigenvaluesPfS_PiS0_S0_ii
.p2align 3, 0x0
_Z15makeEigenvaluesPfS_PiS0_S0_ii:
.quad _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii
.size _Z15makeEigenvaluesPfS_PiS0_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15makeEigenvaluesPfS_PiS0_S0_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15makeEigenvaluesPfS_PiS0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15makeEigenvaluesPfS_PiS0_S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x188], PT ; /* 0x000062000a007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x18c] ; /* 0x0000630000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0090*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fd800000001ff */
/*00a0*/ @!P0 BRA 0x180 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.HI R2, R10, 0x55555556, RZ ; /* 0x555555560a027827 */
/* 0x000fe200078e02ff */
/*00c0*/ BSSY B0, 0x180 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*00d0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fc60000000f00 */
/*00e0*/ LEA.HI R4, R2, R2, RZ, 0x1 ; /* 0x0000000202047211 */
/* 0x000fe400078f08ff */
/*00f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0120*/ ISETP.GT.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x004fda0003f04270 */
/*0130*/ @P0 BRA 0x170 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x18c], PT ; /* 0x0000630000007a0c */
/* 0x000fda0003f06270 */
/*0160*/ @!P0 BRA 0xf0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0190*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fca0000000f00 */
/*01a0*/ IMAD.WIDE R2, R0, R11, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e020b */
/*01b0*/ IMAD.WIDE R4, R0.reuse, R11.reuse, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x0c0fe400078e020b */
/*01c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ IMAD.WIDE R6, R0, R11, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe400078e020b */
/*01e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee8000c1e1900 */
/*01f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0200*/ IMAD R0, R3, -0x3, R10 ; /* 0xfffffffd03007824 */
/* 0x004fca00078e020a */
/*0210*/ IADD3 R8, R0, R5, RZ ; /* 0x0000000500087210 */
/* 0x008fe20007ffe0ff */
/*0220*/ IMAD R9, R6, 0x3, RZ ; /* 0x0000000306097824 */
/* 0x010fc800078e02ff */
/*0230*/ IMAD R8, R0, R9, R8 ; /* 0x0000000900087224 */
/* 0x000fc800078e0208 */
/*0240*/ IMAD.WIDE R8, R8, R11, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fcc00078e020b */
/*0250*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e020b */
/*0270*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x004fe2000c101904 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15makeEigenvaluesPfS_PiS0_S0_ii
.globl _Z15makeEigenvaluesPfS_PiS0_S0_ii
.p2align 8
.type _Z15makeEigenvaluesPfS_PiS0_S0_ii,@function
_Z15makeEigenvaluesPfS_PiS0_S0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_9
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_7
v_mul_hi_i32 v0, v1, 0x55555556
s_mov_b32 s7, 0
s_mov_b64 s[4:5], s[2:3]
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s10, exec_lo, s9
s_or_b32 s7, s10, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_6
.LBB0_4:
s_load_b32 s10, s[4:5], 0x0
v_mov_b32_e32 v2, s8
s_or_b32 s9, s9, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s10, v0
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_3
s_add_i32 s8, s8, 1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s6, s8
v_mov_b32_e32 v2, s6
s_cselect_b32 s11, -1, 0
s_and_not1_b32 s9, s9, exec_lo
s_and_b32 s11, s11, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s9, s9, s11
s_branch .LBB0_3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v2, -1, v2
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_branch .LBB0_8
.LBB0_7:
v_mov_b32_e32 v2, -1
v_mov_b32_e32 v3, -1
.LBB0_8:
s_load_b128 s[4:7], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v0, v[4:5], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(2)
v_mad_u64_u32 v[2:3], null, v0, -3, v[1:2]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v4, v2
v_lshl_add_u32 v0, v0, 1, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v2, v5, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15makeEigenvaluesPfS_PiS0_S0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15makeEigenvaluesPfS_PiS0_S0_ii, .Lfunc_end0-_Z15makeEigenvaluesPfS_PiS0_S0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15makeEigenvaluesPfS_PiS0_S0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15makeEigenvaluesPfS_PiS0_S0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003318e_00000000-6_makeEigenvalues.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii
.type _Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii, @function
_Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15makeEigenvaluesPfS_PiS0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii, .-_Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii
.globl _Z15makeEigenvaluesPfS_PiS0_S0_ii
.type _Z15makeEigenvaluesPfS_PiS0_S0_ii, @function
_Z15makeEigenvaluesPfS_PiS0_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z15makeEigenvaluesPfS_PiS0_S0_iiPfS_PiS0_S0_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15makeEigenvaluesPfS_PiS0_S0_ii, .-_Z15makeEigenvaluesPfS_PiS0_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15makeEigenvaluesPfS_PiS0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15makeEigenvaluesPfS_PiS0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "makeEigenvalues.hip"
.globl _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii # -- Begin function _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii
.p2align 4, 0x90
.type _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii,@function
_Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii: # @_Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15makeEigenvaluesPfS_PiS0_S0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii, .Lfunc_end0-_Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15makeEigenvaluesPfS_PiS0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15makeEigenvaluesPfS_PiS0_S0_ii,@object # @_Z15makeEigenvaluesPfS_PiS0_S0_ii
.section .rodata,"a",@progbits
.globl _Z15makeEigenvaluesPfS_PiS0_S0_ii
.p2align 3, 0x0
_Z15makeEigenvaluesPfS_PiS0_S0_ii:
.quad _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii
.size _Z15makeEigenvaluesPfS_PiS0_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15makeEigenvaluesPfS_PiS0_S0_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__makeEigenvaluesPfS_PiS0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15makeEigenvaluesPfS_PiS0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
This works for all.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <float.h>
#include <math.h>
#include <iostream>
#include <climits>
#include <vector>
#include <stack>
using namespace std;
//#include <thrust/host_vector.h>
//#include <thrust/device_vector.h>
struct edge{ int flow,capacity,to; edge(int to,int capacity){ this->to=to; this->capacity=capacity; this->flow=0; } };
struct node{ int height,excess,color; vector<edge> edges; };
node* graph;
//functions
void push_relabel_GPU(int N, node * graph);
void addEdge(int from,int to,int capacity){
graph[from].edges.push_back(edge(to,capacity));
}
void findMinCut(int N)
{
int src=0,sink=N-1; // src should be background
// compute preflow
for(int i=0;i<N;i++){ graph[i].height=0; graph[i].excess=0; } graph[src].height=N;
for(vector<edge>::iterator e=graph[src].edges.begin();e!=graph[src].edges.end();e++){
graph[e->to].excess=e->capacity; e->flow=e->capacity;
addEdge(e->to,src,e->flow);
}
bool hasExcessNode=true;
while(hasExcessNode)
{
hasExcessNode=false;
for(int i=1;i<N-1;i++) if(graph[i].excess>0)
{
// push from i to neighbours
hasExcessNode=true; bool pushed=false;
for(vector<edge>::iterator e=graph[i].edges.begin();e!=graph[i].edges.end();e++) if(graph[e->to].height<graph[i].height and e->capacity>e->flow)
{
int del=min(graph[i].excess,e->capacity-e->flow);
e->flow+=del; graph[i].excess-=del; graph[e->to].excess+=del;
// update residual graph
bool edgeFound=false;
for(vector<edge>::iterator e2=graph[e->to].edges.begin();e2!=graph[e->to].edges.end();e2++)
if(e2->to==i){ e2->flow-=del; edgeFound=true; break; }
if(!edgeFound) addEdge(e->to,i,del);
pushed=true; break;
}
if(!pushed)
{
// relabel i to enable push afterwards
int minHeight = INT_MAX;
for(int j=0; j<graph[i].edges.size();j++)
{
edge e = graph[i].edges[j];
if(e.to!=sink and e.capacity>e.flow){
minHeight=min(minHeight,graph[e.to].height);
}
}
if(graph[i].height<=minHeight) graph[i].height=minHeight+1;
}
}
}
// do a dfs from src to mark background pixels
stack<int> stack; stack.push(src);
while(!stack.empty())
{
int curr=stack.top(); stack.pop();
graph[curr].color=0; // mark the pixel as background
for(vector<edge>::iterator e=graph[curr].edges.begin();e!=graph[curr].edges.end();e++)
if(e->capacity==e->flow and graph[e->to].color!=0) stack.push(e->to);
}
}
// 0 , 1 , 2 , N = 3
// (0,1,2),(3,4),(5,6,7) assume num_neighbours = 2
//[2][0] gives 3 + 1*2 + 0 = 5
//[1][1] gives 3 + 0*2 + 1 = 4
//[0][2] gives
__host__ __device__ int get_index(int i, int j, int num_neighbours, int N){
// cout<<"got i = "<<i<<" j = "<<j<<" N = "<<N<<'\n';
int ans = 0;
if(i>0)
{
ans+=N;
ans+=(i-1)*num_neighbours;
ans+=j;
}
else
{
ans+=j;
}
// cout<<"returning ans = "<<ans<<'\n';
return ans;
}
int main()
{
int N=6;
graph=new node[N];
for(int i=0;i<N;i++) graph[i].color=1;
/*addEdge(0,1,3);
addEdge(0,2,2);
addEdge(1,2,5);
addEdge(2,3,3);
addEdge(1,3,2);*/
addEdge(0, 2, 13);
addEdge(0, 1, 16);
addEdge(1, 2, 10);
// addEdge(2, 1, 4);
addEdge(1, 3, 12);
addEdge(2, 4, 14);
addEdge(3, 2, 9);
addEdge(2, 3, 9);
addEdge(3, 5, 20);
addEdge(4, 3, 7);
addEdge(4, 5, 4);
// findMinCut(N);
// for(int i=0;i<N;i++) if(graph[i].color==0) cout<<i<<" "; cout<<endl;
// cout<<graph[N-1].excess;
push_relabel_GPU(N,graph); //Make sure findMinCut is NOT called before this as it modifies graph.
}
__global__ void kernel(int * height_d, int * excess_d,int * adjacency_list_d,int * size_matrix_d, int * capacity_d, int * flow_d, int N, int num_neighbours, int sink){
int cycle = 1;
int u = blockIdx.x*blockDim.x+threadIdx.x;
while(cycle>0)
{
printf("Working on node/thread %d\n",u);
if(excess_d[u]>0 && u!=sink)
{
int e_dash = excess_d[u];
int h_dash = 100000;
int v_dash = -1;
int i_dash = -1;
for(int i=0;i<size_matrix_d[u];i++)
{
int ind = get_index(u,i,num_neighbours,N);
int v = adjacency_list_d[ind];
int h_da_da = height_d[v];
if(h_da_da<h_dash && ((capacity_d[ind] - flow_d[ind])>0))
{
v_dash = v;
i_dash = i;
h_dash = h_da_da;
}
}
if(height_d[u]>h_dash)
{
printf("nearest neighbour with lower height %d\n",v_dash);
int d = 0;
int x_tmp=capacity_d[get_index(u,i_dash,num_neighbours,N)]-flow_d[get_index(u,i_dash,num_neighbours,N)];
if(x_tmp<0)
{
//assert(false)
}
if(e_dash<x_tmp)
{
d = e_dash;
}
else{
d = x_tmp;
}
int ind_of_u_in_v_list = 0;
for(int i=0;i<size_matrix_d[v_dash];i++)
{
if(adjacency_list_d[get_index(v_dash,i,num_neighbours,N)]==u)
{
ind_of_u_in_v_list = i;
break;
}
}
atomicAdd(&flow_d[get_index(u,i_dash,num_neighbours,N)],d);
// atomicSub(&flow_d[get_index(v_dash,ind_of_u_in_v_list,num_neighbours,N)],d);
atomicSub(&excess_d[u],d);
atomicAdd(&excess_d[v_dash],d);
}
else{
height_d[u]= h_dash +1;
}
}
cycle-=1;
}
}
void global_relabel(int * height, int * excess,int * adjacency_list,int * size_matrix, int * capacity, int * flow, int N, int num_neighbours, int src, int sink)
{
for(int i=0;i<N;i++)
{
for(int j=0;j<size_matrix[i];j++)
{
int ind = get_index(i,j,num_neighbours,N);
int u = i, v = adjacency_list[ind];
int ind_of_v_in_u_list =-1;
if(height[u]>height[v]+1)
{
int cfuv = (capacity[get_index(u,j,num_neighbours,N)]-flow[get_index(u,j,num_neighbours,N)]);
excess[u] =excess[u] - cfuv;
excess[v] =excess[v] + cfuv;
for(int k=0;k<size_matrix[v];k++)
{
if(adjacency_list[get_index(v,k,num_neighbours,N)]==u)
{
ind_of_v_in_u_list = k;
break;
}
}
int ind1 = get_index(v,ind_of_v_in_u_list ,num_neighbours,N);
// int cfvu = capacity[ind1] - flow[ind1];
flow[ind1] = flow[ind1] - cfuv;
flow[ind] = capacity[ind];
}
}
}
}
void print_flow(int * flow,int N, int * size_matrix, int * adjlist, string s, int * excess)
{
if(s=="excess")
{
for(int i=0;i<N;i++)
{
cout<<"Excess for "<<i<<' '<<excess[i];
}cout<<'\n';
return;
}
for(int i=0;i<N;i++)
{
for(int j=0;j<size_matrix[i];j++)
{
int ind = get_index(i,j,16,N);
cout<<s+" for "<<i<<" and "<<adjlist[ind]<<" = ";
cout<<" "<<flow[ind]<<" ";
}
cout<<'\n';
}
}
void push_relabel_GPU(int N, node * graph)
{
int src=0,sink=N-1; // src should be background
// compute preflow
// int * height_arr = malloc(sizeof(int))
size_t nsize = sizeof(int)*N;
int NUM_NEIGHBOURS = 16;
size_t twonsize = sizeof(int)*((N-2)*NUM_NEIGHBOURS + 2*N);
//CPU variables
int * height = (int*)malloc(nsize);
int * excess = (int*)malloc(nsize);
int * adjacency_list = (int*)malloc(twonsize);
int * size_matrix = (int*)malloc(nsize);
int * capacity = (int*)malloc(twonsize);
int * flow = (int*)malloc(twonsize);
int * cf = (int*)malloc(twonsize);
//GPU variables
int * height_d; cudaMalloc(&height_d, nsize);
int * excess_d; cudaMalloc(&excess_d, nsize);
int * adjacency_list_d; cudaMalloc(&adjacency_list_d,twonsize);
int * size_matrix_d; cudaMalloc(&size_matrix_d, nsize);
int * capacity_d; cudaMalloc(&capacity_d,twonsize);
int * flow_d; cudaMalloc(&flow_d,twonsize);
int * cf_d = (int*)malloc(twonsize);
//Setting values for new AoS implementation
memset(height,0,nsize);
memset(excess,0,nsize);
for(int i=0;i<N;i++)
{
size_matrix[i]=0;
}
for(int i=0;i<N;i++)
{
int s = graph[i].edges.size();
// size_matrix[i] = s;
for(int j=0;j<s;j++)
{
cout<<" -------------- << s = << "<<s<<'\n';
// int u = get_index(i,j,NUM_NEIGHBOURS,N);
// cout<<"i = "<<i<<" j = "<<j<< "setting "<< u<<"adj_list[ ] as "<< (graph[i].edges)[j].to<<'\n';
int v = (graph[i].edges)[j].to;
int cap = (((graph[i].edges)[j]).capacity);
adjacency_list[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = v;
capacity[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = cap;
flow[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = 0;
cf[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = capacity[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)]-flow[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)];
size_matrix[i]++;
adjacency_list[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = i;
capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = cap;
// capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = 0;
flow[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = 0;
cf[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)]-flow[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)];
size_matrix[v]++;
// capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = i;
// capacity[get_index(i,j,NUM_NEIGHBOURS,N)] = (((graph[i].edges)[j]).capacity);
//cout<<"i = "<<i<<" j = "<<j<< "setting capacity "<< u<<"adj_list[ ] as "<< (graph[i].edges)[j].capacity<<'\n';
}
}
//excess is the excess flow of vertex, flow is the flow on edge
//Initializing pre-flow
for(int i=0;i<N;i++){ height[i]=0; excess[i]=0; } height[src]=N;
// for(int i = 0;i<size_matrix[src];i++){
// //v is the to vertex
// int v = adjacency_list[get_index(src,i,NUM_NEIGHBOURS,N)];
// excess[v]=capacity[get_index(src,i,NUM_NEIGHBOURS,N)];
// int cap = capacity[get_index(src,i,NUM_NEIGHBOURS,N)];
// flow[get_index(src,i,NUM_NEIGHBOURS,N)]= cap;
// cout<<"set excess of "<<v<<" to "<<excess[v];
// //add-edge implementation
// //!!!!! CHECK 7
// int last_elem = size_matrix[v];
// cout<<"last elem of "<<v<<" = "<<last_elem<<'\n';
//// adjacency_list[get_index(v,last_elem,NUM_NEIGHBOURS,N)] = src;
//// cout<<" setting edge in list "<<get_index(v,last_elem,NUM_NEIGHBOURS,N)<<'\n';
//// capacity[get_index(v,last_elem,NUM_NEIGHBOURS,N)] = 0;
//// flow[get_index(v,last_elem,NUM_NEIGHBOURS,N)] = -flow[get_index(src,i,NUM_NEIGHBOURS,N)];
//// cout<<"flow = "<<flow[get_index(v,last_elem,NUM_NEIGHBOURS,N)]<<'\n';
//// size_matrix[v]++;
//// addEdge(e->to,src,e->flow);
// //add edge fn ends or include next line too
// excess[src] -= flow[get_index(src,i,NUM_NEIGHBOURS,N)];
// cout<<"Loop end---------------------------------"<<'\n';
// }
for(int i=0;i<size_matrix[src];i++)
{
int index_v = get_index(src, i, NUM_NEIGHBOURS, N);
int cap = capacity[index_v];
int v = adjacency_list[index_v];
flow[index_v] = cap;
excess[src] -= cap;
excess[v] = cap;
//uncomment loop cfor correct termination
// for(int j=0;j<size_matrix[v];j++)
// {
// int ind = get_index(v,j,NUM_NEIGHBOURS,N);
// if(adjacency_list[ind]==src)
// {
// flow[ind] = -cap;
// break;
// }
// }
}
height[src] = N;
//pre-flow ends
//Copying
cudaMemcpy( excess_d, excess, nsize, cudaMemcpyHostToDevice);
cudaMemcpy(capacity_d, capacity,twonsize, cudaMemcpyHostToDevice);
cudaMemcpy(flow_d, flow,twonsize, cudaMemcpyHostToDevice);
cudaMemcpy(size_matrix_d, size_matrix,nsize, cudaMemcpyHostToDevice);
cudaMemcpy(adjacency_list_d, adjacency_list,twonsize, cudaMemcpyHostToDevice);
//Starting main loop
cout<<"graph[src].excess = "<<excess[src]<<" graph[sink].excess = "<<excess[sink]<<'\n';
int cnt =1000;
while(excess[src]+ excess[sink]< 0 && cnt>0)
{
cout<<"graph[src].excess = "<<excess[src]<<" graph[sink].excess = "<<excess[sink]<<'\n';
cudaMemcpy(height_d, height, nsize, cudaMemcpyHostToDevice);
//call kernel here
kernel<<<1,N>>>(height_d,excess_d,adjacency_list_d,size_matrix_d,capacity_d,flow_d,N,NUM_NEIGHBOURS,sink);
cudaMemcpy(height, height_d, nsize, cudaMemcpyDeviceToHost);
cudaMemcpy( excess, excess_d, nsize, cudaMemcpyDeviceToHost);
cudaMemcpy(capacity, capacity_d,twonsize, cudaMemcpyDeviceToHost);
cudaMemcpy(flow, flow_d,twonsize, cudaMemcpyDeviceToHost);
cudaMemcpy(size_matrix, size_matrix_d,nsize, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
cout<<"H array: --------------------------------------------\n";
for(int q=0;q<N;q++)
{
cout<<height[q]<<' ';
}
printf("FLOW:\n");
print_flow(flow,N,size_matrix, adjacency_list,"flow",excess);
printf("EXCESS:\n");
print_flow(flow,N,size_matrix, adjacency_list,"excess",excess);
printf("capacity:\n");
print_flow(capacity,N,size_matrix, adjacency_list,"capacity",excess);
cnt--;
//global_relabel(height,excess,adjacency_list,size_matrix,capacity,flow,N,NUM_NEIGHBOURS,src,sink);
//call global relabel here
}
} | code for sm_80
Function : _Z6kernelPiS_S_S_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R22, SR_CTAID.X ; /* 0x0000000000167919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff057624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R19, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001137a10 */
/* 0x000fe20007f3e0ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fc800078e00ff */
/*00a0*/ IMAD.X R18, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff127624 */
/* 0x000fe400008e06ff */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, R19 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0013 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0012 */
/*00d0*/ IMAD R22, R22, c[0x0][0x0], R3 ; /* 0x0000000016167a24 */
/* 0x001fe400078e0203 */
/*00e0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e240000000a00 */
/*00f0*/ IMAD.WIDE R16, R22.reuse, R17, c[0x0][0x168] ; /* 0x00005a0016107625 */
/* 0x040fe200078e0211 */
/*0100*/ STL [R1], R22 ; /* 0x0000001601007387 */
/* 0x0003e20000100800 */
/*0110*/ IADD3 R0, R22, -0x1, RZ ; /* 0xffffffff16007810 */
/* 0x000fc40007ffe0ff */
/*0120*/ ISETP.GT.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f04270 */
/*0130*/ SHF.R.S32.HI R23, RZ, 0x1f, R22 ; /* 0x0000001fff177819 */
/* 0x000fe20000011416 */
/*0140*/ IMAD R0, R0, R5, c[0x0][0x190] ; /* 0x0000640000007624 */
/* 0x000fe400078e0205 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*0160*/ SEL R24, R0, RZ, P0 ; /* 0x000000ff00187207 */
/* 0x000fe40000000000 */
/*0170*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fe20000000000 */
/*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*01f0*/ LDG.E R25, [R16.64] ; /* 0x0000002410197981 */
/* 0x000ea4000c1e1900 */
/*0200*/ ISETP.GE.AND P0, PT, R25, 0x1, PT ; /* 0x000000011900780c */
/* 0x004fc80003f06270 */
/*0210*/ ISETP.EQ.OR P0, PT, R22, c[0x0][0x198], !P0 ; /* 0x0000660016007a0c */
/* 0x000fda0004702670 */
/*0220*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0230*/ IMAD.SHL.U32 R0, R22.reuse, 0x4, RZ ; /* 0x0000000416007824 */
/* 0x040fe200078e00ff */
/*0240*/ SHF.L.U64.HI R12, R22, 0x2, R23 ; /* 0x00000002160c7819 */
/* 0x000fc80000010217 */
/*0250*/ IADD3 R2, P0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a10 */
/* 0x000fc80007f1e0ff */
/*0260*/ IADD3.X R3, R12, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000c037a10 */
/* 0x000fca00007fe4ff */
/*0270*/ LDG.E R5, [R2.64] ; /* 0x0000002402057981 */
/* 0x000ea2000c1e1900 */
/*0280*/ BSSY B0, 0xb40 ; /* 0x000008b000007945 */
/* 0x000fe20003800000 */
/*0290*/ IMAD.MOV.U32 R22, RZ, RZ, -0x1 ; /* 0xffffffffff167424 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R29, RZ, RZ, 0x186a0 ; /* 0x000186a0ff1d7424 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R23, RZ, RZ, -0x1 ; /* 0xffffffffff177424 */
/* 0x000fe200078e00ff */
/*02c0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x004fda0003f06270 */
/*02d0*/ @!P0 BRA 0xb30 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R2, R5.reuse, -0x1, RZ ; /* 0xffffffff05027810 */
/* 0x040fe20007ffe0ff */
/*02f0*/ BSSY B1, 0x7e0 ; /* 0x000004e000017945 */
/* 0x000fe20003800000 */
/*0300*/ LOP3.LUT R20, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305147812 */
/* 0x000fe200078ec0ff */
/*0310*/ IMAD.MOV.U32 R23, RZ, RZ, -0x1 ; /* 0xffffffffff177424 */
/* 0x000fe200078e00ff */
/*0320*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0330*/ IMAD.MOV.U32 R29, RZ, RZ, 0x186a0 ; /* 0x000186a0ff1d7424 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0350*/ IMAD.MOV.U32 R22, RZ, RZ, -0x1 ; /* 0xffffffffff167424 */
/* 0x000fd000078e00ff */
/*0360*/ @!P0 BRA 0x7d0 ; /* 0x0000046000008947 */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0380*/ BSSY B2, 0x7d0 ; /* 0x0000044000027945 */
/* 0x000fe20003800000 */
/*0390*/ IMAD.IADD R14, R5, 0x1, -R20 ; /* 0x00000001050e7824 */
/* 0x000fe400078e0a14 */
/*03a0*/ IMAD.WIDE R2, R24, R3, c[0x0][0x170] ; /* 0x00005c0018027625 */
/* 0x000fc800078e0203 */
/*03b0*/ IMAD.MOV.U32 R29, RZ, RZ, 0x186a0 ; /* 0x000186a0ff1d7424 */
/* 0x000fe400078e00ff */
/*03c0*/ IMAD.MOV.U32 R23, RZ, RZ, -0x1 ; /* 0xffffffffff177424 */
/* 0x000fe400078e00ff */
/*03d0*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe400078e00ff */
/*03e0*/ IMAD.MOV.U32 R30, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff1e7624 */
/* 0x000fe400078e00ff */
/*03f0*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff157624 */
/* 0x000fe400078e00ff */
/*0400*/ IMAD.MOV.U32 R26, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff1a7624 */
/* 0x000fc400078e00ff */
/*0410*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0d7624 */
/* 0x000fe400078e00ff */
/*0420*/ LDG.E R15, [R2.64] ; /* 0x00000024020f7981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.MOV.U32 R32, RZ, RZ, 0x4 ; /* 0x00000004ff207424 */
/* 0x000fc600078e00ff */
/*0440*/ LDG.E R27, [R2.64+0x4] ; /* 0x00000424021b7981 */
/* 0x000ee2000c1e1900 */
/*0450*/ IMAD.MOV.U32 R4, RZ, RZ, R30 ; /* 0x000000ffff047224 */
/* 0x000fe400078e001e */
/*0460*/ IMAD.MOV.U32 R5, RZ, RZ, R21 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0015 */
/*0470*/ LDG.E R31, [R2.64+0x8] ; /* 0x00000824021f7981 */
/* 0x000f22000c1e1900 */
/*0480*/ IMAD.WIDE R10, R15, R32, c[0x0][0x160] ; /* 0x000058000f0a7625 */
/* 0x004fcc00078e0220 */
/*0490*/ LDG.E R10, [R10.64] ; /* 0x000000240a0a7981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IMAD.MOV.U32 R6, RZ, RZ, R26 ; /* 0x000000ffff067224 */
/* 0x000fe400078e001a */
/*04b0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000d */
/*04c0*/ IMAD.WIDE R4, R24, 0x4, R4 ; /* 0x0000000418047825 */
/* 0x000fc800078e0204 */
/*04d0*/ IMAD.WIDE R6, R24, 0x4, R6 ; /* 0x0000000418067825 */
/* 0x000fc800078e0206 */
/*04e0*/ IMAD.WIDE R8, R27, R32, c[0x0][0x160] ; /* 0x000058001b087625 */
/* 0x008fcc00078e0220 */
/*04f0*/ LDG.E R8, [R8.64] ; /* 0x0000002408087981 */
/* 0x000ee2000c1e1900 */
/*0500*/ ISETP.GE.AND P3, PT, R10, R29, PT ; /* 0x0000001d0a00720c */
/* 0x004fda0003f66270 */
/*0510*/ @!P3 LDG.E R33, [R4.64] ; /* 0x000000240421b981 */
/* 0x000ea8000c1e1900 */
/*0520*/ @!P3 LDG.E R34, [R6.64] ; /* 0x000000240622b981 */
/* 0x000ea4000c1e1900 */
/*0530*/ ISETP.GT.AND P3, PT, R33, R34, !P3 ; /* 0x000000222100720c */
/* 0x004fe40005f64270 */
/*0540*/ LDG.E R33, [R2.64+0xc] ; /* 0x00000c2402217981 */
/* 0x000ea4000c1e1900 */
/*0550*/ SEL R35, R10, R29, P3 ; /* 0x0000001d0a237207 */
/* 0x000fc80001800000 */
/*0560*/ ISETP.GE.AND P0, PT, R8, R35, PT ; /* 0x000000230800720c */
/* 0x008fe20003f06270 */
/*0570*/ IMAD.WIDE R10, R31, R32, c[0x0][0x160] ; /* 0x000058001f0a7625 */
/* 0x010fcc00078e0220 */
/*0580*/ LDG.E R10, [R10.64] ; /* 0x000000240a0a7981 */
/* 0x000eec000c1e1900 */
/*0590*/ @!P0 LDG.E R29, [R6.64+0x4] ; /* 0x00000424061d8981 */
/* 0x000f28000c1e1900 */
/*05a0*/ @!P0 LDG.E R34, [R4.64+0x4] ; /* 0x0000042404228981 */
/* 0x000f24000c1e1900 */
/*05b0*/ ISETP.GT.AND P0, PT, R34, R29, !P0 ; /* 0x0000001d2200720c */
/* 0x010fc80004704270 */
/*05c0*/ SEL R35, R8, R35, P0 ; /* 0x0000002308237207 */
/* 0x000fc80000000000 */
/*05d0*/ ISETP.GE.AND P1, PT, R10, R35, PT ; /* 0x000000230a00720c */
/* 0x008fe20003f26270 */
/*05e0*/ IMAD.WIDE R8, R33, R32, c[0x0][0x160] ; /* 0x0000580021087625 */
/* 0x004fcc00078e0220 */
/*05f0*/ LDG.E R8, [R8.64] ; /* 0x0000002408087981 */
/* 0x000eac000c1e1900 */
/*0600*/ @!P1 LDG.E R29, [R6.64+0x8] ; /* 0x00000824061d9981 */
/* 0x000ee8000c1e1900 */
/*0610*/ @!P1 LDG.E R34, [R4.64+0x8] ; /* 0x0000082404229981 */
/* 0x000ee4000c1e1900 */
/*0620*/ ISETP.GT.AND P1, PT, R34, R29, !P1 ; /* 0x0000001d2200720c */
/* 0x008fc80004f24270 */
/*0630*/ SEL R29, R10, R35, P1 ; /* 0x000000230a1d7207 */
/* 0x000fc80000800000 */
/*0640*/ ISETP.GE.AND P2, PT, R8, R29, PT ; /* 0x0000001d0800720c */
/* 0x004fda0003f46270 */
/*0650*/ @!P2 LDG.E R10, [R6.64+0xc] ; /* 0x00000c24060aa981 */
/* 0x000ea8000c1e1900 */
/*0660*/ @!P2 LDG.E R11, [R4.64+0xc] ; /* 0x00000c24040ba981 */
/* 0x000ea2000c1e1900 */
/*0670*/ SEL R22, R15, R22, P3 ; /* 0x000000160f167207 */
/* 0x000fe40001800000 */
/*0680*/ IADD3 R14, R14, -0x4, RZ ; /* 0xfffffffc0e0e7810 */
/* 0x000fe40007ffe0ff */
/*0690*/ SEL R23, R28, R23, P3 ; /* 0x000000171c177207 */
/* 0x000fe40001800000 */
/*06a0*/ SEL R22, R27, R22, P0 ; /* 0x000000161b167207 */
/* 0x000fc40000000000 */
/*06b0*/ @P0 IADD3 R23, R28, 0x1, RZ ; /* 0x000000011c170810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f05270 */
/*06d0*/ IADD3 R2, P3, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007f7e0ff */
/*06e0*/ SEL R22, R31, R22, P1 ; /* 0x000000161f167207 */
/* 0x000fe40000800000 */
/*06f0*/ @P1 IADD3 R23, R28, 0x2, RZ ; /* 0x000000021c171810 */
/* 0x000fe20007ffe0ff */
/*0700*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe200018e0603 */
/*0710*/ IADD3 R26, P1, R26, 0x10, RZ ; /* 0x000000101a1a7810 */
/* 0x000fc40007f3e0ff */
/*0720*/ IADD3 R30, P3, R30, 0x10, RZ ; /* 0x000000101e1e7810 */
/* 0x000fc60007f7e0ff */
/*0730*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e060d */
/*0740*/ IMAD.X R21, RZ, RZ, R21, P3 ; /* 0x000000ffff157224 */
/* 0x000fe200018e0615 */
/*0750*/ ISETP.GT.AND P2, PT, R11, R10, !P2 ; /* 0x0000000a0b00720c */
/* 0x004fc80005744270 */
/*0760*/ SEL R29, R8, R29, P2 ; /* 0x0000001d081d7207 */
/* 0x000fe40001000000 */
/*0770*/ IADD3 R8, R28, 0x4, RZ ; /* 0x000000041c087810 */
/* 0x000fe40007ffe0ff */
/*0780*/ SEL R22, R33, R22, P2 ; /* 0x0000001621167207 */
/* 0x000fca0001000000 */
/*0790*/ @P2 IADD3 R23, R28, 0x3, RZ ; /* 0x000000031c172810 */
/* 0x000fe20007ffe0ff */
/*07a0*/ IMAD.MOV.U32 R28, RZ, RZ, R8 ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e0008 */
/*07b0*/ @P0 BRA 0x420 ; /* 0xfffffc6000000947 */
/* 0x000fea000383ffff */
/*07c0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fda0003f05270 */
/*07f0*/ @!P0 BRA 0xb30 ; /* 0x0000033000008947 */
/* 0x000fea0003800000 */
/*0800*/ IMAD.IADD R6, R24, 0x1, R8 ; /* 0x0000000118067824 */
/* 0x000fe400078e0208 */
/*0810*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc800078e00ff */
/*0820*/ IMAD.WIDE R2, R6, R15, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fca00078e020f */
/*0830*/ LDG.E R13, [R2.64] ; /* 0x00000024020d7981 */
/* 0x000ea4000c1e1900 */
/*0840*/ IMAD.WIDE R10, R13, R15, c[0x0][0x160] ; /* 0x000058000d0a7625 */
/* 0x004fca00078e020f */
/*0850*/ LDG.E R14, [R10.64] ; /* 0x000000240a0e7981 */
/* 0x000ea2000c1e1900 */
/*0860*/ BSSY B1, 0x910 ; /* 0x000000a000017945 */
/* 0x000fe20003800000 */
/*0870*/ IMAD.WIDE R4, R6, R15.reuse, c[0x0][0x180] ; /* 0x0000600006047625 */
/* 0x080fe200078e020f */
/*0880*/ ISETP.NE.AND P2, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fe40003f45270 */
/*0890*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*08a0*/ IMAD.WIDE R6, R6, R15, c[0x0][0x188] ; /* 0x0000620006067625 */
/* 0x000fe200078e020f */
/*08b0*/ ISETP.GE.AND P1, PT, R14, R29, PT ; /* 0x0000001d0e00720c */
/* 0x004fda0003f26270 */
/*08c0*/ @P1 BRA 0x900 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*08d0*/ LDG.E R9, [R4.64] ; /* 0x0000002404097981 */
/* 0x000ea8000c1e1900 */
/*08e0*/ LDG.E R10, [R6.64] ; /* 0x00000024060a7981 */
/* 0x000ea4000c1e1900 */
/*08f0*/ ISETP.GT.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x004fd00003f04270 */
/*0900*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0910*/ SEL R29, R14, R29, P0 ; /* 0x0000001d0e1d7207 */
/* 0x000fe40000000000 */
/*0920*/ SEL R22, R13, R22, P0 ; /* 0x000000160d167207 */
/* 0x000fe40000000000 */
/*0930*/ SEL R23, R8, R23, P0 ; /* 0x0000001708177207 */
/* 0x000fe20000000000 */
/*0940*/ @!P2 BRA 0xb30 ; /* 0x000001e00000a947 */
/* 0x000fea0003800000 */
/*0950*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000424020d7981 */
/* 0x000ea4000c1e1900 */
/*0960*/ IMAD.WIDE R10, R13, R15, c[0x0][0x160] ; /* 0x000058000d0a7625 */
/* 0x004fca00078e020f */
/*0970*/ LDG.E R14, [R10.64] ; /* 0x000000240a0e7981 */
/* 0x000ea2000c1e1900 */
/*0980*/ BSSY B1, 0xa10 ; /* 0x0000008000017945 */
/* 0x000fe20003800000 */
/*0990*/ ISETP.NE.AND P2, PT, R20, 0x2, PT ; /* 0x000000021400780c */
/* 0x000fe40003f45270 */
/*09a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*09b0*/ ISETP.GE.AND P1, PT, R14, R29, PT ; /* 0x0000001d0e00720c */
/* 0x004fda0003f26270 */
/*09c0*/ @P1 BRA 0xa00 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*09d0*/ LDG.E R9, [R6.64+0x4] ; /* 0x0000042406097981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000424040a7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ ISETP.GT.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720c */
/* 0x004fd00003f04270 */
/*0a00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a10*/ SEL R29, R14, R29, P0 ; /* 0x0000001d0e1d7207 */
/* 0x000fe40000000000 */
/*0a20*/ SEL R22, R13, R22, P0 ; /* 0x000000160d167207 */
/* 0x000fe40000000000 */
/*0a30*/ @P0 IADD3 R23, R8, 0x1, RZ ; /* 0x0000000108170810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ @!P2 BRA 0xb30 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*0a50*/ LDG.E R3, [R2.64+0x8] ; /* 0x0000082402037981 */
/* 0x000ea4000c1e1900 */
/*0a60*/ IMAD.WIDE R10, R3, R15, c[0x0][0x160] ; /* 0x00005800030a7625 */
/* 0x004fcc00078e020f */
/*0a70*/ LDG.E R10, [R10.64] ; /* 0x000000240a0a7981 */
/* 0x000ea2000c1e1900 */
/*0a80*/ BSSY B1, 0xb00 ; /* 0x0000007000017945 */
/* 0x000fe20003800000 */
/*0a90*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0aa0*/ ISETP.GE.AND P1, PT, R10, R29, PT ; /* 0x0000001d0a00720c */
/* 0x004fda0003f26270 */
/*0ab0*/ @P1 BRA 0xaf0 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*0ac0*/ LDG.E R6, [R6.64+0x8] ; /* 0x0000082406067981 */
/* 0x000ea8000c1e1900 */
/*0ad0*/ LDG.E R5, [R4.64+0x8] ; /* 0x0000082404057981 */
/* 0x000ea4000c1e1900 */
/*0ae0*/ ISETP.GT.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x004fd00003f04270 */
/*0af0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b00*/ SEL R29, R10, R29, P0 ; /* 0x0000001d0a1d7207 */
/* 0x000fe40000000000 */
/*0b10*/ SEL R22, R3, R22, P0 ; /* 0x0000001603167207 */
/* 0x000fe40000000000 */
/*0b20*/ @P0 IADD3 R23, R8, 0x2, RZ ; /* 0x0000000208170810 */
/* 0x000fc40007ffe0ff */
/*0b30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b40*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*0b50*/ IADD3.X R3, R12, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000c037a10 */
/* 0x000fca00007fe4ff */
/*0b60*/ LDG.E R0, [R2.64] ; /* 0x0000002402007981 */
/* 0x000ea4000c1e1900 */
/*0b70*/ ISETP.GT.AND P0, PT, R0, R29, PT ; /* 0x0000001d0000720c */
/* 0x004fda0003f04270 */
/*0b80*/ @!P0 IADD3 R29, R29, 0x1, RZ ; /* 0x000000011d1d8810 */
/* 0x000fca0007ffe0ff */
/*0b90*/ @!P0 STG.E [R2.64], R29 ; /* 0x0000001d02008986 */
/* 0x0001e2000c101924 */
/*0ba0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0bb0*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x001fe20000000f00 */
/*0bc0*/ STL [R1], R22 ; /* 0x0000001601007387 */
/* 0x0001e20000100800 */
/*0bd0*/ IMAD.MOV.U32 R6, RZ, RZ, R19 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0013 */
/*0be0*/ IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0012 */
/*0bf0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*0c00*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0c10*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fca00078e00ff */
/*0c20*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*0c30*/ MOV R11, 0xca0 ; /* 0x00000ca0000b7802 */
/* 0x000fc40000000f00 */
/*0c40*/ MOV R20, 0xc20 ; /* 0x00000c2000147802 */
/* 0x000fe40000000f00 */
/*0c50*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0c60*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0c70*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0c80*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0c90*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x003fea0003c00000 */
/*0ca0*/ IMAD.IADD R4, R24, 0x1, R23 ; /* 0x0000000118047824 */
/* 0x000fe400078e0217 */
/*0cb0*/ IMAD.MOV.U32 R23, RZ, RZ, 0x4 ; /* 0x00000004ff177424 */
/* 0x000fc800078e00ff */
/*0cc0*/ IMAD.WIDE R2, R4, R23, c[0x0][0x180] ; /* 0x0000600004027625 */
/* 0x000fc800078e0217 */
/*0cd0*/ IMAD.WIDE R4, R4, R23.reuse, c[0x0][0x188] ; /* 0x0000620004047625 */
/* 0x080fe400078e0217 */
/*0ce0*/ LDG.E R3, [R2.64] ; /* 0x0000002402037981 */
/* 0x000ea8000c1e1900 */
/*0cf0*/ LDG.E R0, [R4.64] ; /* 0x0000002404007981 */
/* 0x000ea2000c1e1900 */
/*0d00*/ IMAD.WIDE R22, R22, R23, c[0x0][0x168] ; /* 0x00005a0016167625 */
/* 0x000fc800078e0217 */
/*0d10*/ IMAD.IADD R0, R3, 0x1, -R0 ; /* 0x0000000103007824 */
/* 0x004fca00078e0a00 */
/*0d20*/ IMNMX R25, R25, R0, PT ; /* 0x0000000019197217 */
/* 0x000fca0003800200 */
/*0d30*/ IMAD.MOV R7, RZ, RZ, -R25 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a19 */
/*0d40*/ RED.E.ADD.STRONG.GPU [R4.64], R25 ; /* 0x000000190400798e */
/* 0x000fe8000c10e1a4 */
/*0d50*/ RED.E.ADD.STRONG.GPU [R16.64], R7 ; /* 0x000000071000798e */
/* 0x000fe8000c10e1a4 */
/*0d60*/ RED.E.ADD.STRONG.GPU [R22.64], R25 ; /* 0x000000191600798e */
/* 0x000fe2000c10e1a4 */
/*0d70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d80*/ BRA 0xd80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
This works for all.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <float.h>
#include <math.h>
#include <iostream>
#include <climits>
#include <vector>
#include <stack>
using namespace std;
//#include <thrust/host_vector.h>
//#include <thrust/device_vector.h>
struct edge{ int flow,capacity,to; edge(int to,int capacity){ this->to=to; this->capacity=capacity; this->flow=0; } };
struct node{ int height,excess,color; vector<edge> edges; };
node* graph;
//functions
void push_relabel_GPU(int N, node * graph);
void addEdge(int from,int to,int capacity){
graph[from].edges.push_back(edge(to,capacity));
}
void findMinCut(int N)
{
int src=0,sink=N-1; // src should be background
// compute preflow
for(int i=0;i<N;i++){ graph[i].height=0; graph[i].excess=0; } graph[src].height=N;
for(vector<edge>::iterator e=graph[src].edges.begin();e!=graph[src].edges.end();e++){
graph[e->to].excess=e->capacity; e->flow=e->capacity;
addEdge(e->to,src,e->flow);
}
bool hasExcessNode=true;
while(hasExcessNode)
{
hasExcessNode=false;
for(int i=1;i<N-1;i++) if(graph[i].excess>0)
{
// push from i to neighbours
hasExcessNode=true; bool pushed=false;
for(vector<edge>::iterator e=graph[i].edges.begin();e!=graph[i].edges.end();e++) if(graph[e->to].height<graph[i].height and e->capacity>e->flow)
{
int del=min(graph[i].excess,e->capacity-e->flow);
e->flow+=del; graph[i].excess-=del; graph[e->to].excess+=del;
// update residual graph
bool edgeFound=false;
for(vector<edge>::iterator e2=graph[e->to].edges.begin();e2!=graph[e->to].edges.end();e2++)
if(e2->to==i){ e2->flow-=del; edgeFound=true; break; }
if(!edgeFound) addEdge(e->to,i,del);
pushed=true; break;
}
if(!pushed)
{
// relabel i to enable push afterwards
int minHeight = INT_MAX;
for(int j=0; j<graph[i].edges.size();j++)
{
edge e = graph[i].edges[j];
if(e.to!=sink and e.capacity>e.flow){
minHeight=min(minHeight,graph[e.to].height);
}
}
if(graph[i].height<=minHeight) graph[i].height=minHeight+1;
}
}
}
// do a dfs from src to mark background pixels
stack<int> stack; stack.push(src);
while(!stack.empty())
{
int curr=stack.top(); stack.pop();
graph[curr].color=0; // mark the pixel as background
for(vector<edge>::iterator e=graph[curr].edges.begin();e!=graph[curr].edges.end();e++)
if(e->capacity==e->flow and graph[e->to].color!=0) stack.push(e->to);
}
}
// 0 , 1 , 2 , N = 3
// (0,1,2),(3,4),(5,6,7) assume num_neighbours = 2
//[2][0] gives 3 + 1*2 + 0 = 5
//[1][1] gives 3 + 0*2 + 1 = 4
//[0][2] gives
__host__ __device__ int get_index(int i, int j, int num_neighbours, int N){
// cout<<"got i = "<<i<<" j = "<<j<<" N = "<<N<<'\n';
int ans = 0;
if(i>0)
{
ans+=N;
ans+=(i-1)*num_neighbours;
ans+=j;
}
else
{
ans+=j;
}
// cout<<"returning ans = "<<ans<<'\n';
return ans;
}
int main()
{
int N=6;
graph=new node[N];
for(int i=0;i<N;i++) graph[i].color=1;
/*addEdge(0,1,3);
addEdge(0,2,2);
addEdge(1,2,5);
addEdge(2,3,3);
addEdge(1,3,2);*/
addEdge(0, 2, 13);
addEdge(0, 1, 16);
addEdge(1, 2, 10);
// addEdge(2, 1, 4);
addEdge(1, 3, 12);
addEdge(2, 4, 14);
addEdge(3, 2, 9);
addEdge(2, 3, 9);
addEdge(3, 5, 20);
addEdge(4, 3, 7);
addEdge(4, 5, 4);
// findMinCut(N);
// for(int i=0;i<N;i++) if(graph[i].color==0) cout<<i<<" "; cout<<endl;
// cout<<graph[N-1].excess;
push_relabel_GPU(N,graph); //Make sure findMinCut is NOT called before this as it modifies graph.
}
__global__ void kernel(int * height_d, int * excess_d,int * adjacency_list_d,int * size_matrix_d, int * capacity_d, int * flow_d, int N, int num_neighbours, int sink){
int cycle = 1;
int u = blockIdx.x*blockDim.x+threadIdx.x;
while(cycle>0)
{
printf("Working on node/thread %d\n",u);
if(excess_d[u]>0 && u!=sink)
{
int e_dash = excess_d[u];
int h_dash = 100000;
int v_dash = -1;
int i_dash = -1;
for(int i=0;i<size_matrix_d[u];i++)
{
int ind = get_index(u,i,num_neighbours,N);
int v = adjacency_list_d[ind];
int h_da_da = height_d[v];
if(h_da_da<h_dash && ((capacity_d[ind] - flow_d[ind])>0))
{
v_dash = v;
i_dash = i;
h_dash = h_da_da;
}
}
if(height_d[u]>h_dash)
{
printf("nearest neighbour with lower height %d\n",v_dash);
int d = 0;
int x_tmp=capacity_d[get_index(u,i_dash,num_neighbours,N)]-flow_d[get_index(u,i_dash,num_neighbours,N)];
if(x_tmp<0)
{
//assert(false)
}
if(e_dash<x_tmp)
{
d = e_dash;
}
else{
d = x_tmp;
}
int ind_of_u_in_v_list = 0;
for(int i=0;i<size_matrix_d[v_dash];i++)
{
if(adjacency_list_d[get_index(v_dash,i,num_neighbours,N)]==u)
{
ind_of_u_in_v_list = i;
break;
}
}
atomicAdd(&flow_d[get_index(u,i_dash,num_neighbours,N)],d);
// atomicSub(&flow_d[get_index(v_dash,ind_of_u_in_v_list,num_neighbours,N)],d);
atomicSub(&excess_d[u],d);
atomicAdd(&excess_d[v_dash],d);
}
else{
height_d[u]= h_dash +1;
}
}
cycle-=1;
}
}
void global_relabel(int * height, int * excess,int * adjacency_list,int * size_matrix, int * capacity, int * flow, int N, int num_neighbours, int src, int sink)
{
for(int i=0;i<N;i++)
{
for(int j=0;j<size_matrix[i];j++)
{
int ind = get_index(i,j,num_neighbours,N);
int u = i, v = adjacency_list[ind];
int ind_of_v_in_u_list =-1;
if(height[u]>height[v]+1)
{
int cfuv = (capacity[get_index(u,j,num_neighbours,N)]-flow[get_index(u,j,num_neighbours,N)]);
excess[u] =excess[u] - cfuv;
excess[v] =excess[v] + cfuv;
for(int k=0;k<size_matrix[v];k++)
{
if(adjacency_list[get_index(v,k,num_neighbours,N)]==u)
{
ind_of_v_in_u_list = k;
break;
}
}
int ind1 = get_index(v,ind_of_v_in_u_list ,num_neighbours,N);
// int cfvu = capacity[ind1] - flow[ind1];
flow[ind1] = flow[ind1] - cfuv;
flow[ind] = capacity[ind];
}
}
}
}
void print_flow(int * flow,int N, int * size_matrix, int * adjlist, string s, int * excess)
{
if(s=="excess")
{
for(int i=0;i<N;i++)
{
cout<<"Excess for "<<i<<' '<<excess[i];
}cout<<'\n';
return;
}
for(int i=0;i<N;i++)
{
for(int j=0;j<size_matrix[i];j++)
{
int ind = get_index(i,j,16,N);
cout<<s+" for "<<i<<" and "<<adjlist[ind]<<" = ";
cout<<" "<<flow[ind]<<" ";
}
cout<<'\n';
}
}
void push_relabel_GPU(int N, node * graph)
{
int src=0,sink=N-1; // src should be background
// compute preflow
// int * height_arr = malloc(sizeof(int))
size_t nsize = sizeof(int)*N;
int NUM_NEIGHBOURS = 16;
size_t twonsize = sizeof(int)*((N-2)*NUM_NEIGHBOURS + 2*N);
//CPU variables
int * height = (int*)malloc(nsize);
int * excess = (int*)malloc(nsize);
int * adjacency_list = (int*)malloc(twonsize);
int * size_matrix = (int*)malloc(nsize);
int * capacity = (int*)malloc(twonsize);
int * flow = (int*)malloc(twonsize);
int * cf = (int*)malloc(twonsize);
//GPU variables
int * height_d; cudaMalloc(&height_d, nsize);
int * excess_d; cudaMalloc(&excess_d, nsize);
int * adjacency_list_d; cudaMalloc(&adjacency_list_d,twonsize);
int * size_matrix_d; cudaMalloc(&size_matrix_d, nsize);
int * capacity_d; cudaMalloc(&capacity_d,twonsize);
int * flow_d; cudaMalloc(&flow_d,twonsize);
int * cf_d = (int*)malloc(twonsize);
//Setting values for new AoS implementation
memset(height,0,nsize);
memset(excess,0,nsize);
for(int i=0;i<N;i++)
{
size_matrix[i]=0;
}
for(int i=0;i<N;i++)
{
int s = graph[i].edges.size();
// size_matrix[i] = s;
for(int j=0;j<s;j++)
{
cout<<" -------------- << s = << "<<s<<'\n';
// int u = get_index(i,j,NUM_NEIGHBOURS,N);
// cout<<"i = "<<i<<" j = "<<j<< "setting "<< u<<"adj_list[ ] as "<< (graph[i].edges)[j].to<<'\n';
int v = (graph[i].edges)[j].to;
int cap = (((graph[i].edges)[j]).capacity);
adjacency_list[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = v;
capacity[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = cap;
flow[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = 0;
cf[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = capacity[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)]-flow[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)];
size_matrix[i]++;
adjacency_list[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = i;
capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = cap;
// capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = 0;
flow[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = 0;
cf[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)]-flow[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)];
size_matrix[v]++;
// capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = i;
// capacity[get_index(i,j,NUM_NEIGHBOURS,N)] = (((graph[i].edges)[j]).capacity);
//cout<<"i = "<<i<<" j = "<<j<< "setting capacity "<< u<<"adj_list[ ] as "<< (graph[i].edges)[j].capacity<<'\n';
}
}
//excess is the excess flow of vertex, flow is the flow on edge
//Initializing pre-flow
for(int i=0;i<N;i++){ height[i]=0; excess[i]=0; } height[src]=N;
// for(int i = 0;i<size_matrix[src];i++){
// //v is the to vertex
// int v = adjacency_list[get_index(src,i,NUM_NEIGHBOURS,N)];
// excess[v]=capacity[get_index(src,i,NUM_NEIGHBOURS,N)];
// int cap = capacity[get_index(src,i,NUM_NEIGHBOURS,N)];
// flow[get_index(src,i,NUM_NEIGHBOURS,N)]= cap;
// cout<<"set excess of "<<v<<" to "<<excess[v];
// //add-edge implementation
// //!!!!! CHECK 7
// int last_elem = size_matrix[v];
// cout<<"last elem of "<<v<<" = "<<last_elem<<'\n';
//// adjacency_list[get_index(v,last_elem,NUM_NEIGHBOURS,N)] = src;
//// cout<<" setting edge in list "<<get_index(v,last_elem,NUM_NEIGHBOURS,N)<<'\n';
//// capacity[get_index(v,last_elem,NUM_NEIGHBOURS,N)] = 0;
//// flow[get_index(v,last_elem,NUM_NEIGHBOURS,N)] = -flow[get_index(src,i,NUM_NEIGHBOURS,N)];
//// cout<<"flow = "<<flow[get_index(v,last_elem,NUM_NEIGHBOURS,N)]<<'\n';
//// size_matrix[v]++;
//// addEdge(e->to,src,e->flow);
// //add edge fn ends or include next line too
// excess[src] -= flow[get_index(src,i,NUM_NEIGHBOURS,N)];
// cout<<"Loop end---------------------------------"<<'\n';
// }
for(int i=0;i<size_matrix[src];i++)
{
int index_v = get_index(src, i, NUM_NEIGHBOURS, N);
int cap = capacity[index_v];
int v = adjacency_list[index_v];
flow[index_v] = cap;
excess[src] -= cap;
excess[v] = cap;
//uncomment loop cfor correct termination
// for(int j=0;j<size_matrix[v];j++)
// {
// int ind = get_index(v,j,NUM_NEIGHBOURS,N);
// if(adjacency_list[ind]==src)
// {
// flow[ind] = -cap;
// break;
// }
// }
}
height[src] = N;
//pre-flow ends
//Copying
cudaMemcpy( excess_d, excess, nsize, cudaMemcpyHostToDevice);
cudaMemcpy(capacity_d, capacity,twonsize, cudaMemcpyHostToDevice);
cudaMemcpy(flow_d, flow,twonsize, cudaMemcpyHostToDevice);
cudaMemcpy(size_matrix_d, size_matrix,nsize, cudaMemcpyHostToDevice);
cudaMemcpy(adjacency_list_d, adjacency_list,twonsize, cudaMemcpyHostToDevice);
//Starting main loop
cout<<"graph[src].excess = "<<excess[src]<<" graph[sink].excess = "<<excess[sink]<<'\n';
int cnt =1000;
while(excess[src]+ excess[sink]< 0 && cnt>0)
{
cout<<"graph[src].excess = "<<excess[src]<<" graph[sink].excess = "<<excess[sink]<<'\n';
cudaMemcpy(height_d, height, nsize, cudaMemcpyHostToDevice);
//call kernel here
kernel<<<1,N>>>(height_d,excess_d,adjacency_list_d,size_matrix_d,capacity_d,flow_d,N,NUM_NEIGHBOURS,sink);
cudaMemcpy(height, height_d, nsize, cudaMemcpyDeviceToHost);
cudaMemcpy( excess, excess_d, nsize, cudaMemcpyDeviceToHost);
cudaMemcpy(capacity, capacity_d,twonsize, cudaMemcpyDeviceToHost);
cudaMemcpy(flow, flow_d,twonsize, cudaMemcpyDeviceToHost);
cudaMemcpy(size_matrix, size_matrix_d,nsize, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
cout<<"H array: --------------------------------------------\n";
for(int q=0;q<N;q++)
{
cout<<height[q]<<' ';
}
printf("FLOW:\n");
print_flow(flow,N,size_matrix, adjacency_list,"flow",excess);
printf("EXCESS:\n");
print_flow(flow,N,size_matrix, adjacency_list,"excess",excess);
printf("capacity:\n");
print_flow(capacity,N,size_matrix, adjacency_list,"capacity",excess);
cnt--;
//global_relabel(height,excess,adjacency_list,size_matrix,capacity,flow,N,NUM_NEIGHBOURS,src,sink);
//call global relabel here
}
} | /*
This works for all.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <float.h>
#include <math.h>
#include <iostream>
#include <climits>
#include <vector>
#include <stack>
using namespace std;
//#include <thrust/host_vector.h>
//#include <thrust/device_vector.h>
struct edge{ int flow,capacity,to; edge(int to,int capacity){ this->to=to; this->capacity=capacity; this->flow=0; } };
struct node{ int height,excess,color; vector<edge> edges; };
node* graph;
//functions
void push_relabel_GPU(int N, node * graph);
void addEdge(int from,int to,int capacity){
graph[from].edges.push_back(edge(to,capacity));
}
void findMinCut(int N)
{
int src=0,sink=N-1; // src should be background
// compute preflow
for(int i=0;i<N;i++){ graph[i].height=0; graph[i].excess=0; } graph[src].height=N;
for(vector<edge>::iterator e=graph[src].edges.begin();e!=graph[src].edges.end();e++){
graph[e->to].excess=e->capacity; e->flow=e->capacity;
addEdge(e->to,src,e->flow);
}
bool hasExcessNode=true;
while(hasExcessNode)
{
hasExcessNode=false;
for(int i=1;i<N-1;i++) if(graph[i].excess>0)
{
// push from i to neighbours
hasExcessNode=true; bool pushed=false;
for(vector<edge>::iterator e=graph[i].edges.begin();e!=graph[i].edges.end();e++) if(graph[e->to].height<graph[i].height and e->capacity>e->flow)
{
int del=min(graph[i].excess,e->capacity-e->flow);
e->flow+=del; graph[i].excess-=del; graph[e->to].excess+=del;
// update residual graph
bool edgeFound=false;
for(vector<edge>::iterator e2=graph[e->to].edges.begin();e2!=graph[e->to].edges.end();e2++)
if(e2->to==i){ e2->flow-=del; edgeFound=true; break; }
if(!edgeFound) addEdge(e->to,i,del);
pushed=true; break;
}
if(!pushed)
{
// relabel i to enable push afterwards
int minHeight = INT_MAX;
for(int j=0; j<graph[i].edges.size();j++)
{
edge e = graph[i].edges[j];
if(e.to!=sink and e.capacity>e.flow){
minHeight=min(minHeight,graph[e.to].height);
}
}
if(graph[i].height<=minHeight) graph[i].height=minHeight+1;
}
}
}
// do a dfs from src to mark background pixels
stack<int> stack; stack.push(src);
while(!stack.empty())
{
int curr=stack.top(); stack.pop();
graph[curr].color=0; // mark the pixel as background
for(vector<edge>::iterator e=graph[curr].edges.begin();e!=graph[curr].edges.end();e++)
if(e->capacity==e->flow and graph[e->to].color!=0) stack.push(e->to);
}
}
// 0 , 1 , 2 , N = 3
// (0,1,2),(3,4),(5,6,7) assume num_neighbours = 2
//[2][0] gives 3 + 1*2 + 0 = 5
//[1][1] gives 3 + 0*2 + 1 = 4
//[0][2] gives
__host__ __device__ int get_index(int i, int j, int num_neighbours, int N){
// cout<<"got i = "<<i<<" j = "<<j<<" N = "<<N<<'\n';
int ans = 0;
if(i>0)
{
ans+=N;
ans+=(i-1)*num_neighbours;
ans+=j;
}
else
{
ans+=j;
}
// cout<<"returning ans = "<<ans<<'\n';
return ans;
}
int main()
{
int N=6;
graph=new node[N];
for(int i=0;i<N;i++) graph[i].color=1;
/*addEdge(0,1,3);
addEdge(0,2,2);
addEdge(1,2,5);
addEdge(2,3,3);
addEdge(1,3,2);*/
addEdge(0, 2, 13);
addEdge(0, 1, 16);
addEdge(1, 2, 10);
// addEdge(2, 1, 4);
addEdge(1, 3, 12);
addEdge(2, 4, 14);
addEdge(3, 2, 9);
addEdge(2, 3, 9);
addEdge(3, 5, 20);
addEdge(4, 3, 7);
addEdge(4, 5, 4);
// findMinCut(N);
// for(int i=0;i<N;i++) if(graph[i].color==0) cout<<i<<" "; cout<<endl;
// cout<<graph[N-1].excess;
push_relabel_GPU(N,graph); //Make sure findMinCut is NOT called before this as it modifies graph.
}
__global__ void kernel(int * height_d, int * excess_d,int * adjacency_list_d,int * size_matrix_d, int * capacity_d, int * flow_d, int N, int num_neighbours, int sink){
int cycle = 1;
int u = blockIdx.x*blockDim.x+threadIdx.x;
while(cycle>0)
{
printf("Working on node/thread %d\n",u);
if(excess_d[u]>0 && u!=sink)
{
int e_dash = excess_d[u];
int h_dash = 100000;
int v_dash = -1;
int i_dash = -1;
for(int i=0;i<size_matrix_d[u];i++)
{
int ind = get_index(u,i,num_neighbours,N);
int v = adjacency_list_d[ind];
int h_da_da = height_d[v];
if(h_da_da<h_dash && ((capacity_d[ind] - flow_d[ind])>0))
{
v_dash = v;
i_dash = i;
h_dash = h_da_da;
}
}
if(height_d[u]>h_dash)
{
printf("nearest neighbour with lower height %d\n",v_dash);
int d = 0;
int x_tmp=capacity_d[get_index(u,i_dash,num_neighbours,N)]-flow_d[get_index(u,i_dash,num_neighbours,N)];
if(x_tmp<0)
{
//assert(false)
}
if(e_dash<x_tmp)
{
d = e_dash;
}
else{
d = x_tmp;
}
int ind_of_u_in_v_list = 0;
for(int i=0;i<size_matrix_d[v_dash];i++)
{
if(adjacency_list_d[get_index(v_dash,i,num_neighbours,N)]==u)
{
ind_of_u_in_v_list = i;
break;
}
}
atomicAdd(&flow_d[get_index(u,i_dash,num_neighbours,N)],d);
// atomicSub(&flow_d[get_index(v_dash,ind_of_u_in_v_list,num_neighbours,N)],d);
atomicSub(&excess_d[u],d);
atomicAdd(&excess_d[v_dash],d);
}
else{
height_d[u]= h_dash +1;
}
}
cycle-=1;
}
}
void global_relabel(int * height, int * excess,int * adjacency_list,int * size_matrix, int * capacity, int * flow, int N, int num_neighbours, int src, int sink)
{
for(int i=0;i<N;i++)
{
for(int j=0;j<size_matrix[i];j++)
{
int ind = get_index(i,j,num_neighbours,N);
int u = i, v = adjacency_list[ind];
int ind_of_v_in_u_list =-1;
if(height[u]>height[v]+1)
{
int cfuv = (capacity[get_index(u,j,num_neighbours,N)]-flow[get_index(u,j,num_neighbours,N)]);
excess[u] =excess[u] - cfuv;
excess[v] =excess[v] + cfuv;
for(int k=0;k<size_matrix[v];k++)
{
if(adjacency_list[get_index(v,k,num_neighbours,N)]==u)
{
ind_of_v_in_u_list = k;
break;
}
}
int ind1 = get_index(v,ind_of_v_in_u_list ,num_neighbours,N);
// int cfvu = capacity[ind1] - flow[ind1];
flow[ind1] = flow[ind1] - cfuv;
flow[ind] = capacity[ind];
}
}
}
}
void print_flow(int * flow,int N, int * size_matrix, int * adjlist, string s, int * excess)
{
if(s=="excess")
{
for(int i=0;i<N;i++)
{
cout<<"Excess for "<<i<<' '<<excess[i];
}cout<<'\n';
return;
}
for(int i=0;i<N;i++)
{
for(int j=0;j<size_matrix[i];j++)
{
int ind = get_index(i,j,16,N);
cout<<s+" for "<<i<<" and "<<adjlist[ind]<<" = ";
cout<<" "<<flow[ind]<<" ";
}
cout<<'\n';
}
}
void push_relabel_GPU(int N, node * graph)
{
int src=0,sink=N-1; // src should be background
// compute preflow
// int * height_arr = malloc(sizeof(int))
size_t nsize = sizeof(int)*N;
int NUM_NEIGHBOURS = 16;
size_t twonsize = sizeof(int)*((N-2)*NUM_NEIGHBOURS + 2*N);
//CPU variables
int * height = (int*)malloc(nsize);
int * excess = (int*)malloc(nsize);
int * adjacency_list = (int*)malloc(twonsize);
int * size_matrix = (int*)malloc(nsize);
int * capacity = (int*)malloc(twonsize);
int * flow = (int*)malloc(twonsize);
int * cf = (int*)malloc(twonsize);
//GPU variables
int * height_d; hipMalloc(&height_d, nsize);
int * excess_d; hipMalloc(&excess_d, nsize);
int * adjacency_list_d; hipMalloc(&adjacency_list_d,twonsize);
int * size_matrix_d; hipMalloc(&size_matrix_d, nsize);
int * capacity_d; hipMalloc(&capacity_d,twonsize);
int * flow_d; hipMalloc(&flow_d,twonsize);
int * cf_d = (int*)malloc(twonsize);
//Setting values for new AoS implementation
memset(height,0,nsize);
memset(excess,0,nsize);
for(int i=0;i<N;i++)
{
size_matrix[i]=0;
}
for(int i=0;i<N;i++)
{
int s = graph[i].edges.size();
// size_matrix[i] = s;
for(int j=0;j<s;j++)
{
cout<<" -------------- << s = << "<<s<<'\n';
// int u = get_index(i,j,NUM_NEIGHBOURS,N);
// cout<<"i = "<<i<<" j = "<<j<< "setting "<< u<<"adj_list[ ] as "<< (graph[i].edges)[j].to<<'\n';
int v = (graph[i].edges)[j].to;
int cap = (((graph[i].edges)[j]).capacity);
adjacency_list[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = v;
capacity[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = cap;
flow[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = 0;
cf[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)] = capacity[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)]-flow[get_index(i,size_matrix[i],NUM_NEIGHBOURS,N)];
size_matrix[i]++;
adjacency_list[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = i;
capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = cap;
// capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = 0;
flow[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = 0;
cf[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)]-flow[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)];
size_matrix[v]++;
// capacity[get_index(v,size_matrix[v],NUM_NEIGHBOURS,N)] = i;
// capacity[get_index(i,j,NUM_NEIGHBOURS,N)] = (((graph[i].edges)[j]).capacity);
//cout<<"i = "<<i<<" j = "<<j<< "setting capacity "<< u<<"adj_list[ ] as "<< (graph[i].edges)[j].capacity<<'\n';
}
}
//excess is the excess flow of vertex, flow is the flow on edge
//Initializing pre-flow
for(int i=0;i<N;i++){ height[i]=0; excess[i]=0; } height[src]=N;
// for(int i = 0;i<size_matrix[src];i++){
// //v is the to vertex
// int v = adjacency_list[get_index(src,i,NUM_NEIGHBOURS,N)];
// excess[v]=capacity[get_index(src,i,NUM_NEIGHBOURS,N)];
// int cap = capacity[get_index(src,i,NUM_NEIGHBOURS,N)];
// flow[get_index(src,i,NUM_NEIGHBOURS,N)]= cap;
// cout<<"set excess of "<<v<<" to "<<excess[v];
// //add-edge implementation
// //!!!!! CHECK 7
// int last_elem = size_matrix[v];
// cout<<"last elem of "<<v<<" = "<<last_elem<<'\n';
//// adjacency_list[get_index(v,last_elem,NUM_NEIGHBOURS,N)] = src;
//// cout<<" setting edge in list "<<get_index(v,last_elem,NUM_NEIGHBOURS,N)<<'\n';
//// capacity[get_index(v,last_elem,NUM_NEIGHBOURS,N)] = 0;
//// flow[get_index(v,last_elem,NUM_NEIGHBOURS,N)] = -flow[get_index(src,i,NUM_NEIGHBOURS,N)];
//// cout<<"flow = "<<flow[get_index(v,last_elem,NUM_NEIGHBOURS,N)]<<'\n';
//// size_matrix[v]++;
//// addEdge(e->to,src,e->flow);
// //add edge fn ends or include next line too
// excess[src] -= flow[get_index(src,i,NUM_NEIGHBOURS,N)];
// cout<<"Loop end---------------------------------"<<'\n';
// }
for(int i=0;i<size_matrix[src];i++)
{
int index_v = get_index(src, i, NUM_NEIGHBOURS, N);
int cap = capacity[index_v];
int v = adjacency_list[index_v];
flow[index_v] = cap;
excess[src] -= cap;
excess[v] = cap;
//uncomment loop cfor correct termination
// for(int j=0;j<size_matrix[v];j++)
// {
// int ind = get_index(v,j,NUM_NEIGHBOURS,N);
// if(adjacency_list[ind]==src)
// {
// flow[ind] = -cap;
// break;
// }
// }
}
height[src] = N;
//pre-flow ends
//Copying
hipMemcpy( excess_d, excess, nsize, hipMemcpyHostToDevice);
hipMemcpy(capacity_d, capacity,twonsize, hipMemcpyHostToDevice);
hipMemcpy(flow_d, flow,twonsize, hipMemcpyHostToDevice);
hipMemcpy(size_matrix_d, size_matrix,nsize, hipMemcpyHostToDevice);
hipMemcpy(adjacency_list_d, adjacency_list,twonsize, hipMemcpyHostToDevice);
//Starting main loop
cout<<"graph[src].excess = "<<excess[src]<<" graph[sink].excess = "<<excess[sink]<<'\n';
int cnt =1000;
while(excess[src]+ excess[sink]< 0 && cnt>0)
{
cout<<"graph[src].excess = "<<excess[src]<<" graph[sink].excess = "<<excess[sink]<<'\n';
hipMemcpy(height_d, height, nsize, hipMemcpyHostToDevice);
//call kernel here
kernel<<<1,N>>>(height_d,excess_d,adjacency_list_d,size_matrix_d,capacity_d,flow_d,N,NUM_NEIGHBOURS,sink);
hipMemcpy(height, height_d, nsize, hipMemcpyDeviceToHost);
hipMemcpy( excess, excess_d, nsize, hipMemcpyDeviceToHost);
hipMemcpy(capacity, capacity_d,twonsize, hipMemcpyDeviceToHost);
hipMemcpy(flow, flow_d,twonsize, hipMemcpyDeviceToHost);
hipMemcpy(size_matrix, size_matrix_d,nsize, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
cout<<"H array: --------------------------------------------\n";
for(int q=0;q<N;q++)
{
cout<<height[q]<<' ';
}
printf("FLOW:\n");
print_flow(flow,N,size_matrix, adjacency_list,"flow",excess);
printf("EXCESS:\n");
print_flow(flow,N,size_matrix, adjacency_list,"excess",excess);
printf("capacity:\n");
print_flow(capacity,N,size_matrix, adjacency_list,"capacity",excess);
cnt--;
//global_relabel(height,excess,adjacency_list,size_matrix,capacity,flow,N,NUM_NEIGHBOURS,src,sink);
//call global relabel here
}
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_diagdiv_fl(int M, float eps, float *y, float *x){
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
/* make sure to use only M threads */
if (tid<M) {
if (x[tid]>eps) {
y[tid]=y[tid]/x[tid];
} else {
y[tid]=0.0f;
}
}
} | code for sm_80
Function : _Z17kernel_diagdiv_flifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R2, R3, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x000fcc00078e0003 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0003 */
/*00b0*/ FSETP.GT.AND P0, PT, R4, c[0x0][0x164], PT ; /* 0x0000590004007a0b */
/* 0x004fda0003f04000 */
/*00c0*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0001e2000c101904 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e620000001000 */
/*0100*/ BSSY B0, 0x1c0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0110*/ FFMA R0, -R4, R5, 1 ; /* 0x3f80000004007423 */
/* 0x002fc80000000105 */
/*0120*/ FFMA R0, R5, R0, R5 ; /* 0x0000000005007223 */
/* 0x000fe40000000005 */
/*0130*/ FCHK P0, R8, R4 ; /* 0x0000000408007302 */
/* 0x004e640000000000 */
/*0140*/ FFMA R5, R0, R8, RZ ; /* 0x0000000800057223 */
/* 0x000fc800000000ff */
/*0150*/ FFMA R6, -R4, R5, R8 ; /* 0x0000000504067223 */
/* 0x000fc80000000108 */
/*0160*/ FFMA R5, R0, R6, R5 ; /* 0x0000000600057223 */
/* 0x000fe20000000005 */
/*0170*/ @!P0 BRA 0x1b0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0180*/ MOV R0, 0x1a0 ; /* 0x000001a000007802 */
/* 0x000fe40000000f00 */
/*0190*/ CALL.REL.NOINC 0x1e0 ; /* 0x0000004000007944 */
/* 0x001fea0003c00000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0006 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ SHF.R.U32.HI R6, RZ, 0x17, R4 ; /* 0x00000017ff067819 */
/* 0x000fe20000011604 */
/*01f0*/ BSSY B1, 0x840 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0200*/ SHF.R.U32.HI R5, RZ, 0x17, R8 ; /* 0x00000017ff057819 */
/* 0x000fe20000011608 */
/*0210*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0220*/ LOP3.LUT R7, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06077812 */
/* 0x000fe400078ec0ff */
/*0230*/ LOP3.LUT R6, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05067812 */
/* 0x000fe400078ec0ff */
/*0240*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc40007ffe0ff */
/*0250*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0270*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0280*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0290*/ @!P0 BRA 0x420 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*02a0*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe20003f1c200 */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0008 */
/*02c0*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*02d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02e0*/ @P0 BRA 0x820 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0300*/ @!P0 BRA 0x800 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.NEU.FTZ.AND P2, PT, |R5|.reuse, +INF , PT ; /* 0x7f8000000500780b */
/* 0x040fe40003f5d200 */
/*0320*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0330*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*0340*/ @!P1 BRA !P2, 0x800 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0350*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0360*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0370*/ @P1 BRA 0x7e0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0380*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0390*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03a0*/ @P0 BRA 0x7b0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*03c0*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*03d0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*03e0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*03f0*/ @!P0 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005088823 */
/* 0x000fe400000000ff */
/*0400*/ @!P1 FFMA R9, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004099823 */
/* 0x000fe200000000ff */
/*0410*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0420*/ LEA R4, R7, 0xc0800000, 0x17 ; /* 0xc080000007047811 */
/* 0x000fe200078eb8ff */
/*0430*/ BSSY B2, 0x7a0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0440*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*0450*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a04 */
/*0460*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*0470*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*0480*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0490*/ FADD.FTZ R5, -R9, -RZ ; /* 0x800000ff09057221 */
/* 0x000fe40000010100 */
/*04a0*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*04b0*/ FFMA R11, R4, R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000005 */
/*04c0*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*04d0*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*04e0*/ FFMA R11, R5, R4, R8 ; /* 0x00000004050b7223 */
/* 0x000fc80000000008 */
/*04f0*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*0500*/ FFMA R8, R5, R12, R8 ; /* 0x0000000c05087223 */
/* 0x000fc80000000008 */
/*0510*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*0520*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0530*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0540*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0550*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0570*/ @!P0 BRA 0x780 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0590*/ @P0 BRA 0x750 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05b0*/ @P0 BRA 0x790 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*05d0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*05e0*/ @!P0 BRA 0x790 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05f0*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0600*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0610*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*0620*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0630*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0640*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0650*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0670*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0680*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0690*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*06a0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06b0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*06c0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*06d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06e0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*06f0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0700*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0710*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0720*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0730*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0740*/ BRA 0x790 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0760*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0770*/ BRA 0x790 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0790*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07a0*/ BRA 0x830 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*07c0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x830 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*07f0*/ BRA 0x830 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0800*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0810*/ BRA 0x830 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0820*/ FADD.FTZ R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x000fe40000010000 */
/*0830*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0840*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0004 */
/*0850*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0860*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0870*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff78004007950 */
/* 0x000fea0003c3ffff */
/*0880*/ BRA 0x880; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_diagdiv_fl(int M, float eps, float *y, float *x){
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
/* make sure to use only M threads */
if (tid<M) {
if (x[tid]>eps) {
y[tid]=y[tid]/x[tid];
} else {
y[tid]=0.0f;
}
}
} | .file "tmpxft_00051a7e_00000000-6_kernel_diagdiv_fl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_
.type _Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_, @function
_Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17kernel_diagdiv_flifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_, .-_Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_
.globl _Z17kernel_diagdiv_flifPfS_
.type _Z17kernel_diagdiv_flifPfS_, @function
_Z17kernel_diagdiv_flifPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17kernel_diagdiv_flifPfS_, .-_Z17kernel_diagdiv_flifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17kernel_diagdiv_flifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kernel_diagdiv_flifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_diagdiv_fl(int M, float eps, float *y, float *x){
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
/* make sure to use only M threads */
if (tid<M) {
if (x[tid]>eps) {
y[tid]=y[tid]/x[tid];
} else {
y[tid]=0.0f;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_diagdiv_fl(int M, float eps, float *y, float *x){
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
/* make sure to use only M threads */
if (tid<M) {
if (x[tid]>eps) {
y[tid]=y[tid]/x[tid];
} else {
y[tid]=0.0f;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_diagdiv_fl(int M, float eps, float *y, float *x){
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
/* make sure to use only M threads */
if (tid<M) {
if (x[tid]>eps) {
y[tid]=y[tid]/x[tid];
} else {
y[tid]=0.0f;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17kernel_diagdiv_flifPfS_
.globl _Z17kernel_diagdiv_flifPfS_
.p2align 8
.type _Z17kernel_diagdiv_flifPfS_,@function
_Z17kernel_diagdiv_flifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v1, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, s0, v3
v_add_co_u32 v0, s0, s4, v0
v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_3
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v2, v4, v3, v2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kernel_diagdiv_flifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17kernel_diagdiv_flifPfS_, .Lfunc_end0-_Z17kernel_diagdiv_flifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kernel_diagdiv_flifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17kernel_diagdiv_flifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_diagdiv_fl(int M, float eps, float *y, float *x){
unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x;
/* make sure to use only M threads */
if (tid<M) {
if (x[tid]>eps) {
y[tid]=y[tid]/x[tid];
} else {
y[tid]=0.0f;
}
}
} | .text
.file "kernel_diagdiv_fl.hip"
.globl _Z32__device_stub__kernel_diagdiv_flifPfS_ # -- Begin function _Z32__device_stub__kernel_diagdiv_flifPfS_
.p2align 4, 0x90
.type _Z32__device_stub__kernel_diagdiv_flifPfS_,@function
_Z32__device_stub__kernel_diagdiv_flifPfS_: # @_Z32__device_stub__kernel_diagdiv_flifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17kernel_diagdiv_flifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__kernel_diagdiv_flifPfS_, .Lfunc_end0-_Z32__device_stub__kernel_diagdiv_flifPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kernel_diagdiv_flifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17kernel_diagdiv_flifPfS_,@object # @_Z17kernel_diagdiv_flifPfS_
.section .rodata,"a",@progbits
.globl _Z17kernel_diagdiv_flifPfS_
.p2align 3, 0x0
_Z17kernel_diagdiv_flifPfS_:
.quad _Z32__device_stub__kernel_diagdiv_flifPfS_
.size _Z17kernel_diagdiv_flifPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17kernel_diagdiv_flifPfS_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__kernel_diagdiv_flifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17kernel_diagdiv_flifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17kernel_diagdiv_flifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R2, R3, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x000fcc00078e0003 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0003 */
/*00b0*/ FSETP.GT.AND P0, PT, R4, c[0x0][0x164], PT ; /* 0x0000590004007a0b */
/* 0x004fda0003f04000 */
/*00c0*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0001e2000c101904 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e620000001000 */
/*0100*/ BSSY B0, 0x1c0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0110*/ FFMA R0, -R4, R5, 1 ; /* 0x3f80000004007423 */
/* 0x002fc80000000105 */
/*0120*/ FFMA R0, R5, R0, R5 ; /* 0x0000000005007223 */
/* 0x000fe40000000005 */
/*0130*/ FCHK P0, R8, R4 ; /* 0x0000000408007302 */
/* 0x004e640000000000 */
/*0140*/ FFMA R5, R0, R8, RZ ; /* 0x0000000800057223 */
/* 0x000fc800000000ff */
/*0150*/ FFMA R6, -R4, R5, R8 ; /* 0x0000000504067223 */
/* 0x000fc80000000108 */
/*0160*/ FFMA R5, R0, R6, R5 ; /* 0x0000000600057223 */
/* 0x000fe20000000005 */
/*0170*/ @!P0 BRA 0x1b0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0180*/ MOV R0, 0x1a0 ; /* 0x000001a000007802 */
/* 0x000fe40000000f00 */
/*0190*/ CALL.REL.NOINC 0x1e0 ; /* 0x0000004000007944 */
/* 0x001fea0003c00000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0006 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ SHF.R.U32.HI R6, RZ, 0x17, R4 ; /* 0x00000017ff067819 */
/* 0x000fe20000011604 */
/*01f0*/ BSSY B1, 0x840 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0200*/ SHF.R.U32.HI R5, RZ, 0x17, R8 ; /* 0x00000017ff057819 */
/* 0x000fe20000011608 */
/*0210*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0220*/ LOP3.LUT R7, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06077812 */
/* 0x000fe400078ec0ff */
/*0230*/ LOP3.LUT R6, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05067812 */
/* 0x000fe400078ec0ff */
/*0240*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc40007ffe0ff */
/*0250*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0270*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0280*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0290*/ @!P0 BRA 0x420 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*02a0*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe20003f1c200 */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0008 */
/*02c0*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*02d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02e0*/ @P0 BRA 0x820 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0300*/ @!P0 BRA 0x800 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.NEU.FTZ.AND P2, PT, |R5|.reuse, +INF , PT ; /* 0x7f8000000500780b */
/* 0x040fe40003f5d200 */
/*0320*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0330*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*0340*/ @!P1 BRA !P2, 0x800 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0350*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0360*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0370*/ @P1 BRA 0x7e0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0380*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0390*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03a0*/ @P0 BRA 0x7b0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*03c0*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*03d0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*03e0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*03f0*/ @!P0 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005088823 */
/* 0x000fe400000000ff */
/*0400*/ @!P1 FFMA R9, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004099823 */
/* 0x000fe200000000ff */
/*0410*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0420*/ LEA R4, R7, 0xc0800000, 0x17 ; /* 0xc080000007047811 */
/* 0x000fe200078eb8ff */
/*0430*/ BSSY B2, 0x7a0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0440*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*0450*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a04 */
/*0460*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*0470*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*0480*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0490*/ FADD.FTZ R5, -R9, -RZ ; /* 0x800000ff09057221 */
/* 0x000fe40000010100 */
/*04a0*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*04b0*/ FFMA R11, R4, R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000005 */
/*04c0*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*04d0*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*04e0*/ FFMA R11, R5, R4, R8 ; /* 0x00000004050b7223 */
/* 0x000fc80000000008 */
/*04f0*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*0500*/ FFMA R8, R5, R12, R8 ; /* 0x0000000c05087223 */
/* 0x000fc80000000008 */
/*0510*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*0520*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0530*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0540*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0550*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0570*/ @!P0 BRA 0x780 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0590*/ @P0 BRA 0x750 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05b0*/ @P0 BRA 0x790 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*05d0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*05e0*/ @!P0 BRA 0x790 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05f0*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0600*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0610*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*0620*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0630*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0640*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0650*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0670*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0680*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0690*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*06a0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06b0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*06c0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*06d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06e0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*06f0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0700*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0710*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0720*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0730*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0740*/ BRA 0x790 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0760*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0770*/ BRA 0x790 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0790*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07a0*/ BRA 0x830 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*07c0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x830 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*07f0*/ BRA 0x830 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0800*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0810*/ BRA 0x830 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0820*/ FADD.FTZ R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x000fe40000010000 */
/*0830*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0840*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0004 */
/*0850*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0860*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0870*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff78004007950 */
/* 0x000fea0003c3ffff */
/*0880*/ BRA 0x880; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17kernel_diagdiv_flifPfS_
.globl _Z17kernel_diagdiv_flifPfS_
.p2align 8
.type _Z17kernel_diagdiv_flifPfS_,@function
_Z17kernel_diagdiv_flifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v1, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, s0, v3
v_add_co_u32 v0, s0, s4, v0
v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_3
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v2, v4, v3, v2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kernel_diagdiv_flifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17kernel_diagdiv_flifPfS_, .Lfunc_end0-_Z17kernel_diagdiv_flifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kernel_diagdiv_flifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17kernel_diagdiv_flifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00051a7e_00000000-6_kernel_diagdiv_fl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_
.type _Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_, @function
_Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17kernel_diagdiv_flifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_, .-_Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_
.globl _Z17kernel_diagdiv_flifPfS_
.type _Z17kernel_diagdiv_flifPfS_, @function
_Z17kernel_diagdiv_flifPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z17kernel_diagdiv_flifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17kernel_diagdiv_flifPfS_, .-_Z17kernel_diagdiv_flifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17kernel_diagdiv_flifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kernel_diagdiv_flifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_diagdiv_fl.hip"
.globl _Z32__device_stub__kernel_diagdiv_flifPfS_ # -- Begin function _Z32__device_stub__kernel_diagdiv_flifPfS_
.p2align 4, 0x90
.type _Z32__device_stub__kernel_diagdiv_flifPfS_,@function
_Z32__device_stub__kernel_diagdiv_flifPfS_: # @_Z32__device_stub__kernel_diagdiv_flifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17kernel_diagdiv_flifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__kernel_diagdiv_flifPfS_, .Lfunc_end0-_Z32__device_stub__kernel_diagdiv_flifPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kernel_diagdiv_flifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17kernel_diagdiv_flifPfS_,@object # @_Z17kernel_diagdiv_flifPfS_
.section .rodata,"a",@progbits
.globl _Z17kernel_diagdiv_flifPfS_
.p2align 3, 0x0
_Z17kernel_diagdiv_flifPfS_:
.quad _Z32__device_stub__kernel_diagdiv_flifPfS_
.size _Z17kernel_diagdiv_flifPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17kernel_diagdiv_flifPfS_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__kernel_diagdiv_flifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17kernel_diagdiv_flifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void mergeLocation(const short2* loc_, float* x, float* y, const int npoints, float scale)
{
const int ptidx = blockIdx.x * blockDim.x + threadIdx.x;
if (ptidx < npoints)
{
short2 loc = loc_[ptidx];
x[ptidx] = loc.x * scale;
y[ptidx] = loc.y * scale;
}
} | code for sm_80
Function : _Z13mergeLocationPK6short2PfS2_if
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00c0*/ I2F.S16 R0, R2 ; /* 0x0000000200007306 */
/* 0x004e300000101400 */
/*00d0*/ I2F.S16 R8, R2.H1 ; /* 0x1000000200087306 */
/* 0x000e620000101400 */
/*00e0*/ FMUL R9, R0, c[0x0][0x17c] ; /* 0x00005f0000097a20 */
/* 0x001fca0000400000 */
/*00f0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0100*/ FMUL R11, R8, c[0x0][0x17c] ; /* 0x00005f00080b7a20 */
/* 0x002fca0000400000 */
/*0110*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void mergeLocation(const short2* loc_, float* x, float* y, const int npoints, float scale)
{
const int ptidx = blockIdx.x * blockDim.x + threadIdx.x;
if (ptidx < npoints)
{
short2 loc = loc_[ptidx];
x[ptidx] = loc.x * scale;
y[ptidx] = loc.y * scale;
}
} | .file "tmpxft_000f8452_00000000-6_mergeLocation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if
.type _Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if, @function
_Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13mergeLocationPK6short2PfS2_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if, .-_Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if
.globl _Z13mergeLocationPK6short2PfS2_if
.type _Z13mergeLocationPK6short2PfS2_if, @function
_Z13mergeLocationPK6short2PfS2_if:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13mergeLocationPK6short2PfS2_if, .-_Z13mergeLocationPK6short2PfS2_if
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13mergeLocationPK6short2PfS2_if"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13mergeLocationPK6short2PfS2_if(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void mergeLocation(const short2* loc_, float* x, float* y, const int npoints, float scale)
{
const int ptidx = blockIdx.x * blockDim.x + threadIdx.x;
if (ptidx < npoints)
{
short2 loc = loc_[ptidx];
x[ptidx] = loc.x * scale;
y[ptidx] = loc.y * scale;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mergeLocation(const short2* loc_, float* x, float* y, const int npoints, float scale)
{
const int ptidx = blockIdx.x * blockDim.x + threadIdx.x;
if (ptidx < npoints)
{
short2 loc = loc_[ptidx];
x[ptidx] = loc.x * scale;
y[ptidx] = loc.y * scale;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mergeLocation(const short2* loc_, float* x, float* y, const int npoints, float scale)
{
const int ptidx = blockIdx.x * blockDim.x + threadIdx.x;
if (ptidx < npoints)
{
short2 loc = loc_[ptidx];
x[ptidx] = loc.x * scale;
y[ptidx] = loc.y * scale;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.globl _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.p2align 8
.type _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if,@function
_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x1c
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_i16 v4, v[2:3], off
global_load_i16 v5, v[2:3], off offset:2
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v4, v4
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_mul_f32 v4, s0, v4 :: v_dual_mul_f32 v5, s0, v5
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if, .Lfunc_end0-_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mergeLocation(const short2* loc_, float* x, float* y, const int npoints, float scale)
{
const int ptidx = blockIdx.x * blockDim.x + threadIdx.x;
if (ptidx < npoints)
{
short2 loc = loc_[ptidx];
x[ptidx] = loc.x * scale;
y[ptidx] = loc.y * scale;
}
} | .text
.file "mergeLocation.hip"
.globl _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if # -- Begin function _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.p2align 4, 0x90
.type _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if,@function
_Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if: # @_Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movss %xmm0, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if, .Lfunc_end0-_Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if,@object # @_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.section .rodata,"a",@progbits
.globl _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.p2align 3, 0x0
_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if:
.quad _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.size _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13mergeLocationPK6short2PfS2_if
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00c0*/ I2F.S16 R0, R2 ; /* 0x0000000200007306 */
/* 0x004e300000101400 */
/*00d0*/ I2F.S16 R8, R2.H1 ; /* 0x1000000200087306 */
/* 0x000e620000101400 */
/*00e0*/ FMUL R9, R0, c[0x0][0x17c] ; /* 0x00005f0000097a20 */
/* 0x001fca0000400000 */
/*00f0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0100*/ FMUL R11, R8, c[0x0][0x17c] ; /* 0x00005f00080b7a20 */
/* 0x002fca0000400000 */
/*0110*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.globl _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.p2align 8
.type _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if,@function
_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x1c
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_i16 v4, v[2:3], off
global_load_i16 v5, v[2:3], off offset:2
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v4, v4
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_mul_f32 v4, s0, v4 :: v_dual_mul_f32 v5, s0, v5
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if, .Lfunc_end0-_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f8452_00000000-6_mergeLocation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if
.type _Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if, @function
_Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13mergeLocationPK6short2PfS2_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if, .-_Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if
.globl _Z13mergeLocationPK6short2PfS2_if
.type _Z13mergeLocationPK6short2PfS2_if, @function
_Z13mergeLocationPK6short2PfS2_if:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z13mergeLocationPK6short2PfS2_ifPK6short2PfS2_if
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13mergeLocationPK6short2PfS2_if, .-_Z13mergeLocationPK6short2PfS2_if
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13mergeLocationPK6short2PfS2_if"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13mergeLocationPK6short2PfS2_if(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mergeLocation.hip"
.globl _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if # -- Begin function _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.p2align 4, 0x90
.type _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if,@function
_Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if: # @_Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movss %xmm0, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if, .Lfunc_end0-_Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if,@object # @_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.section .rodata,"a",@progbits
.globl _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.p2align 3, 0x0
_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if:
.quad _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.size _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13mergeLocationPK15HIP_vector_typeIsLj2EEPfS3_if
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void my_first_kernel(float *x) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
x[tid] = float(threadIdx.x);
}
int main() {
float *h_ptr, *d_ptr;
int blocks, threads, size, n;
blocks = 2;
threads = 8;
size = blocks * threads;
h_ptr = (float*)malloc(sizeof(float) * size);
cudaMalloc((void**)&d_ptr, size * sizeof(float));
my_first_kernel<<<blocks, threads>>>(d_ptr);
cudaDeviceSynchronize();
cudaMemcpy(h_ptr, d_ptr, size * sizeof(float), cudaMemcpyDeviceToHost);
for (n = 0; n < size; n++) {
printf("%d %f\n", n, h_ptr[n]);
}
free(h_ptr);
cudaFree(d_ptr);
return 0;
} | code for sm_80
Function : _Z15my_first_kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ I2F.U32 R5, R0 ; /* 0x0000000000057306 */
/* 0x001e220000201000 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x002fca00078e0200 */
/*0070*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void my_first_kernel(float *x) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
x[tid] = float(threadIdx.x);
}
int main() {
float *h_ptr, *d_ptr;
int blocks, threads, size, n;
blocks = 2;
threads = 8;
size = blocks * threads;
h_ptr = (float*)malloc(sizeof(float) * size);
cudaMalloc((void**)&d_ptr, size * sizeof(float));
my_first_kernel<<<blocks, threads>>>(d_ptr);
cudaDeviceSynchronize();
cudaMemcpy(h_ptr, d_ptr, size * sizeof(float), cudaMemcpyDeviceToHost);
for (n = 0; n < size; n++) {
printf("%d %f\n", n, h_ptr[n]);
}
free(h_ptr);
cudaFree(d_ptr);
return 0;
} | .file "tmpxft_000f8987_00000000-6_first.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z15my_first_kernelPfPf
.type _Z35__device_stub__Z15my_first_kernelPfPf, @function
_Z35__device_stub__Z15my_first_kernelPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15my_first_kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z15my_first_kernelPfPf, .-_Z35__device_stub__Z15my_first_kernelPfPf
.globl _Z15my_first_kernelPf
.type _Z15my_first_kernelPf, @function
_Z15my_first_kernelPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15my_first_kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15my_first_kernelPf, .-_Z15my_first_kernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r12
.L13:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L13
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z35__device_stub__Z15my_first_kernelPfPf
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z15my_first_kernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15my_first_kernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void my_first_kernel(float *x) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
x[tid] = float(threadIdx.x);
}
int main() {
float *h_ptr, *d_ptr;
int blocks, threads, size, n;
blocks = 2;
threads = 8;
size = blocks * threads;
h_ptr = (float*)malloc(sizeof(float) * size);
cudaMalloc((void**)&d_ptr, size * sizeof(float));
my_first_kernel<<<blocks, threads>>>(d_ptr);
cudaDeviceSynchronize();
cudaMemcpy(h_ptr, d_ptr, size * sizeof(float), cudaMemcpyDeviceToHost);
for (n = 0; n < size; n++) {
printf("%d %f\n", n, h_ptr[n]);
}
free(h_ptr);
cudaFree(d_ptr);
return 0;
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void my_first_kernel(float *x) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
x[tid] = float(threadIdx.x);
}
int main() {
float *h_ptr, *d_ptr;
int blocks, threads, size, n;
blocks = 2;
threads = 8;
size = blocks * threads;
h_ptr = (float*)malloc(sizeof(float) * size);
hipMalloc((void**)&d_ptr, size * sizeof(float));
my_first_kernel<<<blocks, threads>>>(d_ptr);
hipDeviceSynchronize();
hipMemcpy(h_ptr, d_ptr, size * sizeof(float), hipMemcpyDeviceToHost);
for (n = 0; n < size; n++) {
printf("%d %f\n", n, h_ptr[n]);
}
free(h_ptr);
hipFree(d_ptr);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void my_first_kernel(float *x) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
x[tid] = float(threadIdx.x);
}
int main() {
float *h_ptr, *d_ptr;
int blocks, threads, size, n;
blocks = 2;
threads = 8;
size = blocks * threads;
h_ptr = (float*)malloc(sizeof(float) * size);
hipMalloc((void**)&d_ptr, size * sizeof(float));
my_first_kernel<<<blocks, threads>>>(d_ptr);
hipDeviceSynchronize();
hipMemcpy(h_ptr, d_ptr, size * sizeof(float), hipMemcpyDeviceToHost);
for (n = 0; n < size; n++) {
printf("%d %f\n", n, h_ptr[n]);
}
free(h_ptr);
hipFree(d_ptr);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15my_first_kernelPf
.globl _Z15my_first_kernelPf
.p2align 8
.type _Z15my_first_kernelPf,@function
_Z15my_first_kernelPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
v_cvt_f32_u32_e32 v3, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15my_first_kernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15my_first_kernelPf, .Lfunc_end0-_Z15my_first_kernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15my_first_kernelPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15my_first_kernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void my_first_kernel(float *x) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
x[tid] = float(threadIdx.x);
}
int main() {
float *h_ptr, *d_ptr;
int blocks, threads, size, n;
blocks = 2;
threads = 8;
size = blocks * threads;
h_ptr = (float*)malloc(sizeof(float) * size);
hipMalloc((void**)&d_ptr, size * sizeof(float));
my_first_kernel<<<blocks, threads>>>(d_ptr);
hipDeviceSynchronize();
hipMemcpy(h_ptr, d_ptr, size * sizeof(float), hipMemcpyDeviceToHost);
for (n = 0; n < size; n++) {
printf("%d %f\n", n, h_ptr[n]);
}
free(h_ptr);
hipFree(d_ptr);
return 0;
} | .text
.file "first.hip"
.globl _Z30__device_stub__my_first_kernelPf # -- Begin function _Z30__device_stub__my_first_kernelPf
.p2align 4, 0x90
.type _Z30__device_stub__my_first_kernelPf,@function
_Z30__device_stub__my_first_kernelPf: # @_Z30__device_stub__my_first_kernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15my_first_kernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z30__device_stub__my_first_kernelPf, .Lfunc_end0-_Z30__device_stub__my_first_kernelPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 6(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15my_first_kernelPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq $16, %r14
jne .LBB1_3
# %bb.4:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15my_first_kernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15my_first_kernelPf,@object # @_Z15my_first_kernelPf
.section .rodata,"a",@progbits
.globl _Z15my_first_kernelPf
.p2align 3, 0x0
_Z15my_first_kernelPf:
.quad _Z30__device_stub__my_first_kernelPf
.size _Z15my_first_kernelPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %f\n"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15my_first_kernelPf"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__my_first_kernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15my_first_kernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15my_first_kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ I2F.U32 R5, R0 ; /* 0x0000000000057306 */
/* 0x001e220000201000 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x002fca00078e0200 */
/*0070*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15my_first_kernelPf
.globl _Z15my_first_kernelPf
.p2align 8
.type _Z15my_first_kernelPf,@function
_Z15my_first_kernelPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
v_cvt_f32_u32_e32 v3, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15my_first_kernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15my_first_kernelPf, .Lfunc_end0-_Z15my_first_kernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15my_first_kernelPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15my_first_kernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f8987_00000000-6_first.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z15my_first_kernelPfPf
.type _Z35__device_stub__Z15my_first_kernelPfPf, @function
_Z35__device_stub__Z15my_first_kernelPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15my_first_kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z15my_first_kernelPfPf, .-_Z35__device_stub__Z15my_first_kernelPfPf
.globl _Z15my_first_kernelPf
.type _Z15my_first_kernelPf, @function
_Z15my_first_kernelPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15my_first_kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15my_first_kernelPf, .-_Z15my_first_kernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r12
.L13:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L13
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z35__device_stub__Z15my_first_kernelPfPf
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z15my_first_kernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15my_first_kernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "first.hip"
.globl _Z30__device_stub__my_first_kernelPf # -- Begin function _Z30__device_stub__my_first_kernelPf
.p2align 4, 0x90
.type _Z30__device_stub__my_first_kernelPf,@function
_Z30__device_stub__my_first_kernelPf: # @_Z30__device_stub__my_first_kernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15my_first_kernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z30__device_stub__my_first_kernelPf, .Lfunc_end0-_Z30__device_stub__my_first_kernelPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 6(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15my_first_kernelPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq $16, %r14
jne .LBB1_3
# %bb.4:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15my_first_kernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15my_first_kernelPf,@object # @_Z15my_first_kernelPf
.section .rodata,"a",@progbits
.globl _Z15my_first_kernelPf
.p2align 3, 0x0
_Z15my_first_kernelPf:
.quad _Z30__device_stub__my_first_kernelPf
.size _Z15my_first_kernelPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %f\n"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15my_first_kernelPf"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__my_first_kernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15my_first_kernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define iceil(num, den) (num + den - 1) / den
#define ARRAY_SIZE 20 //must be an even number; this number/2 = number of points //sets random array and constant mem size
//#define BIN 100 //divides the grid into square bins to vote on. perfect square value
#define NUM_LINES 4 //top X voted lines. Picks first X Largest from top left to bottom right of grid space.
/*GRID evaluated for bin voting
* Must always be a square grid with origin at center
*/
#define dimension 5
#define LXBOUND (-1*dimension) //lowest X
#define RXBOUND (dimension) //highest X
#define LYBOUND (-1*dimension) //lowest Y
#define UYBOUND (dimension) //highest Y
////////////////////////////////
#define INCREMENT 1 //precision, length of 1 side of the square(bin)
//The (abs)difference between between two sides is the length of the grid. Length/Increment determines how many bins
#define column (((RXBOUND - LXBOUND) / INCREMENT) * ((RXBOUND - LXBOUND) / INCREMENT)) / ((RXBOUND + UYBOUND) / INCREMENT)
__constant__ int d_coordarray[ARRAY_SIZE];//Place coordinates in constant memory
//show grid with votes. Becomes unuseful when bins > 20x20
__global__ void kernelHough(int size, int* d_binarray) {
/*
take a piece of the array. discretize into y=mx+b format per point. check all points and increment all bins touched
at the end recombine all shared memory to a global bin tally. Take the most significant X numbers as lines.
discretized from point(1,1) ==(m,n)==> (-1,1)
check each bin for count and sum them to a global array in sync
NUM of coordinates will check all bins for their own equation and increment appropriately
*/
// Number from 0 through arraysize / 2
const int thread = 2 * (blockDim.x * blockIdx.x + threadIdx.x);
// Slope is discretized space = -x
const float slope = -1.0 * d_coordarray[thread];
// Intercept in discretized space = y
const float intercept = d_coordarray[thread + 1];
int counter = 0;//keeps current array index being checked
//loop through entire graph
for (float x = LXBOUND; x < RXBOUND; x += INCREMENT) {
const float xMin = x;
const float xMax = x + INCREMENT;
for (float y = UYBOUND; y > LYBOUND; y -= INCREMENT) {
const float yMin = y - INCREMENT;
const float yMax = y;
//calculates possible y range associated with the known x range
const float lower_range = slope * xMin + intercept;
const float upper_range = slope * xMax + intercept;
//if the possible y ranges corresponding to the x values exist within the actual y range increment bin
if ((lower_range <= yMax && lower_range >= yMin) || (upper_range <= yMax && upper_range >= yMin))
atomicAdd(&d_binarray[counter], 1);//increment bin, protected from race condition
counter++;
}
}
} | code for sm_80
Function : _Z11kernelHoughiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, -0x3f600000 ; /* 0xc0a00000ff087424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fc800078e00ff */
/*0070*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fc800078e00ff */
/*0080*/ LDC.64 R6, c[0x3][R4] ; /* 0x00c0000004067b82 */
/* 0x000e240000000a00 */
/*0090*/ I2F.F64 R2, R6 ; /* 0x0000000600027312 */
/* 0x001e300000201c00 */
/*00a0*/ I2F R0, R7 ; /* 0x0000000700007306 */
/* 0x0002b00000201400 */
/*00b0*/ F2F.F32.F64 R5, R2 ; /* 0x0000000200057310 */
/* 0x0010e40000301000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x001fc400078e00ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x006fc800078e00ff */
/*00e0*/ FADD R4, R8, 1 ; /* 0x3f80000008047421 */
/* 0x000fe20000000000 */
/*00f0*/ BSSY B0, 0x250 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0100*/ FFMA R9, -R5.reuse, R8, R0.reuse ; /* 0x0000000805097223 */
/* 0x148fe40000000100 */
/*0110*/ FFMA R10, -R5, R4, R0 ; /* 0x00000004050a7223 */
/* 0x000fc60000000100 */
/*0120*/ FSETP.GE.AND P0, PT, R9.reuse, 4, PT ; /* 0x408000000900780b */
/* 0x040fe40003f06000 */
/*0130*/ FSETP.GE.AND P4, PT, R10.reuse, 4, PT ; /* 0x408000000a00780b */
/* 0x040fe40003f86000 */
/*0140*/ FSETP.LE.AND P0, PT, R9.reuse, 5, P0 ; /* 0x40a000000900780b */
/* 0x040fe40000703000 */
/*0150*/ FSETP.GTU.OR P4, PT, R10, 5, !P4 ; /* 0x40a000000a00780b */
/* 0x000fe4000678c400 */
/*0160*/ FSETP.GE.AND P2, PT, R9.reuse, -1, PT ; /* 0xbf8000000900780b */
/* 0x040fe40003f46000 */
/*0170*/ FSETP.GE.AND P6, PT, R9, 3, PT ; /* 0x404000000900780b */
/* 0x000fc40003fc6000 */
/*0180*/ P2R R6, PR, RZ, 0x4 ; /* 0x00000004ff067803 */
/* 0x000fe40000000000 */
/*0190*/ FSETP.GE.AND P1, PT, R9.reuse, 2, PT ; /* 0x400000000900780b */
/* 0x040fe40003f26000 */
/*01a0*/ FSETP.GE.AND P3, PT, R9.reuse, 1, PT ; /* 0x3f8000000900780b */
/* 0x040fe40003f66000 */
/*01b0*/ FSETP.GE.AND P5, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fe40003fa6000 */
/*01c0*/ FSETP.GE.AND P2, PT, R10, 3, PT ; /* 0x404000000a00780b */
/* 0x000fe20003f46000 */
/*01d0*/ @P4 BRA !P0, 0x240 ; /* 0x0000006000004947 */
/* 0x000fee0004000000 */
/*01e0*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e220000000000 */
/*01f0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fc400038e0100 */
/*0200*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0210*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x000e6a0008000000 */
/*0220*/ ISETP.EQ.U32.AND P0, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x001fda000bf02070 */
/*0230*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R7 ; /* 0x000000070200098e */
/* 0x0021e4000c10e184 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ FSETP.LE.AND P6, PT, R9.reuse, 4, P6 ; /* 0x408000000900780b */
/* 0x040fe200037c3000 */
/*0260*/ BSSY B0, 0x320 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0270*/ FSETP.GTU.OR P2, PT, R10.reuse, 4, !P2 ; /* 0x408000000a00780b */
/* 0x040fe4000574c400 */
/*0280*/ FSETP.GE.AND P4, PT, R9, -2, PT ; /* 0xc00000000900780b */
/* 0x000fe40003f86000 */
/*0290*/ FSETP.GE.AND P0, PT, R10, 2, PT ; /* 0x400000000a00780b */
/* 0x000fd20003f06000 */
/*02a0*/ @P2 BRA !P6, 0x310 ; /* 0x0000006000002947 */
/* 0x000fea0007000000 */
/*02b0*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*02c0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*02d0*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*02e0*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*02f0*/ ISETP.EQ.U32.AND P2, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bf42070 */
/*0300*/ @P2 RED.E.ADD.STRONG.GPU [R2.64+0x4], R7 ; /* 0x000004070200298e */
/* 0x0011e4000c10e184 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ FSETP.LE.AND P1, PT, R9.reuse, 3, P1 ; /* 0x404000000900780b */
/* 0x040fe20000f23000 */
/*0330*/ BSSY B0, 0x3f0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0340*/ FSETP.GTU.OR P6, PT, R10.reuse, 3, !P0 ; /* 0x404000000a00780b */
/* 0x040fe400047cc400 */
/*0350*/ FSETP.GE.AND P2, PT, R9, -3, PT ; /* 0xc04000000900780b */
/* 0x000fe40003f46000 */
/*0360*/ FSETP.GE.AND P0, PT, R10, 1, PT ; /* 0x3f8000000a00780b */
/* 0x000fd20003f06000 */
/*0370*/ @P6 BRA !P1, 0x3e0 ; /* 0x0000006000006947 */
/* 0x000fea0004800000 */
/*0380*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*0390*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*03a0*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*03b0*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*03c0*/ ISETP.EQ.U32.AND P1, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bf22070 */
/*03d0*/ @P1 RED.E.ADD.STRONG.GPU [R2.64+0x8], R7 ; /* 0x000008070200198e */
/* 0x0011e4000c10e184 */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ FSETP.LE.AND P3, PT, R9.reuse, 2, P3 ; /* 0x400000000900780b */
/* 0x040fe20001f63000 */
/*0400*/ BSSY B0, 0x4c0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0410*/ FSETP.GTU.OR P6, PT, R10, 2, !P0 ; /* 0x400000000a00780b */
/* 0x000fe400047cc400 */
/*0420*/ FSETP.GE.AND P1, PT, R9.reuse, -4, PT ; /* 0xc08000000900780b */
/* 0x040fe40003f26000 */
/*0430*/ FSETP.GE.AND P0, PT, R9, -5, PT ; /* 0xc0a000000900780b */
/* 0x000fd20003f06000 */
/*0440*/ @P6 BRA !P3, 0x4b0 ; /* 0x0000006000006947 */
/* 0x000fea0005800000 */
/*0450*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*0460*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0470*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0480*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*0490*/ ISETP.EQ.U32.AND P3, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bf62070 */
/*04a0*/ @P3 RED.E.ADD.STRONG.GPU [R2.64+0xc], R7 ; /* 0x00000c070200398e */
/* 0x0011e4000c10e184 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ FSETP.GE.AND P6, PT, R10.reuse, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x040fe20003fc6000 */
/*04d0*/ BSSY B0, 0x5d0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*04e0*/ FSETP.LE.AND P5, PT, R9.reuse, 1, P5 ; /* 0x3f8000000900780b */
/* 0x040fe40002fa3000 */
/*04f0*/ FSETP.GTU.OR P6, PT, R10, 1, !P6 ; /* 0x3f8000000a00780b */
/* 0x000fe400077cc400 */
/*0500*/ FSETP.LE.AND P4, PT, R9, -1, P4 ; /* 0xbf8000000900780b */
/* 0x000fe40002783000 */
/*0510*/ ISETP.NE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f65270 */
/*0520*/ P2R R6, PR, RZ, 0x10 ; /* 0x00000010ff067803 */
/* 0x000fc40000000000 */
/*0530*/ FSETP.LE.AND P3, PT, R9, RZ, P3 ; /* 0x000000ff0900720b */
/* 0x000fe40001f63000 */
/*0540*/ FSETP.GE.AND P4, PT, R10, -1, PT ; /* 0xbf8000000a00780b */
/* 0x000fc60003f86000 */
/*0550*/ @P6 BRA !P5, 0x5c0 ; /* 0x0000006000006947 */
/* 0x000fea0006800000 */
/*0560*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*0570*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0580*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0590*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*05a0*/ ISETP.EQ.U32.AND P5, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bfa2070 */
/*05b0*/ @P5 RED.E.ADD.STRONG.GPU [R2.64+0x10], R7 ; /* 0x000010070200598e */
/* 0x0011e4000c10e184 */
/*05c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05d0*/ FSETP.GTU.OR P6, PT, R10.reuse, RZ, !P4 ; /* 0x000000ff0a00720b */
/* 0x040fe200067cc400 */
/*05e0*/ BSSY B0, 0x6b0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*05f0*/ FSETP.GE.AND P5, PT, R10.reuse, -2, PT ; /* 0xc00000000a00780b */
/* 0x040fe40003fa6000 */
/*0600*/ FSETP.LE.AND P2, PT, R9.reuse, -2, P2 ; /* 0xc00000000900780b */
/* 0x040fe40001743000 */
/*0610*/ FSETP.LE.AND P1, PT, R9, -3, P1 ; /* 0xc04000000900780b */
/* 0x000fe40000f23000 */
/*0620*/ FSETP.GE.AND P4, PT, R10, -3, PT ; /* 0xc04000000a00780b */
/* 0x000fca0003f86000 */
/*0630*/ @P6 BRA !P3, 0x6a0 ; /* 0x0000006000006947 */
/* 0x000fea0005800000 */
/*0640*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*0650*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0660*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0670*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*0680*/ ISETP.EQ.U32.AND P3, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bf62070 */
/*0690*/ @P3 RED.E.ADD.STRONG.GPU [R2.64+0x14], R7 ; /* 0x000014070200398e */
/* 0x0011e4000c10e184 */
/*06a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06b0*/ ISETP.NE.AND P6, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003fc5270 */
/*06c0*/ BSSY B0, 0x7d0 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*06d0*/ FSETP.GTU.OR P5, PT, R10.reuse, -1, !P5 ; /* 0xbf8000000a00780b */
/* 0x040fe40006fac400 */
/*06e0*/ FSETP.GTU.OR P4, PT, R10.reuse, -2, !P4 ; /* 0xc00000000a00780b */
/* 0x040fe4000678c400 */
/*06f0*/ FSETP.GE.AND P3, PT, R10.reuse, -4, PT ; /* 0xc08000000a00780b */
/* 0x040fe40003f66000 */
/*0700*/ P2R R6, PR, RZ, 0x10 ; /* 0x00000010ff067803 */
/* 0x000fe40000000000 */
/*0710*/ FSETP.GE.AND P4, PT, R10, -5, PT ; /* 0xc0a000000a00780b */
/* 0x000fc40003f86000 */
/*0720*/ FSETP.LE.AND P0, PT, R9, -4, P0 ; /* 0xc08000000900780b */
/* 0x000fe40000703000 */
/*0730*/ FSETP.GTU.OR P3, PT, R10.reuse, -3, !P3 ; /* 0xc04000000a00780b */
/* 0x040fe40005f6c400 */
/*0740*/ FSETP.GTU.OR P4, PT, R10, -4, !P4 ; /* 0xc08000000a00780b */
/* 0x000fe2000678c400 */
/*0750*/ @P5 BRA !P6, 0x7c0 ; /* 0x0000006000005947 */
/* 0x000fee0007000000 */
/*0760*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*0770*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0780*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0790*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*07a0*/ ISETP.EQ.U32.AND P5, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bfa2070 */
/*07b0*/ @P5 RED.E.ADD.STRONG.GPU [R2.64+0x18], R7 ; /* 0x000018070200598e */
/* 0x0011e4000c10e184 */
/*07c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07d0*/ ISETP.NE.AND P6, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003fc5270 */
/*07e0*/ BSSY B0, 0x880 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*07f0*/ FSETP.GEU.AND P5, PT, R4, 5, PT ; /* 0x40a000000400780b */
/* 0x000fd60003fae000 */
/*0800*/ @P6 BRA !P2, 0x870 ; /* 0x0000006000006947 */
/* 0x000fea0005000000 */
/*0810*/ S2R R6, SR_LANEID ; /* 0x0000000000067919 */
/* 0x000e620000000000 */
/*0820*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0830*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0840*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*0850*/ ISETP.EQ.U32.AND P2, PT, R6, UR7, PT ; /* 0x0000000706007c0c */
/* 0x002fda000bf42070 */
/*0860*/ @P2 RED.E.ADD.STRONG.GPU [R2.64+0x1c], R7 ; /* 0x00001c070200298e */
/* 0x0011e4000c10e184 */
/*0870*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0880*/ BSSY B0, 0x910 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0890*/ @P3 BRA !P1, 0x900 ; /* 0x0000006000003947 */
/* 0x000fea0004800000 */
/*08a0*/ S2R R6, SR_LANEID ; /* 0x0000000000067919 */
/* 0x000e620000000000 */
/*08b0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*08c0*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*08d0*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*08e0*/ ISETP.EQ.U32.AND P1, PT, R6, UR7, PT ; /* 0x0000000706007c0c */
/* 0x002fda000bf22070 */
/*08f0*/ @P1 RED.E.ADD.STRONG.GPU [R2.64+0x20], R7 ; /* 0x000020070200198e */
/* 0x0011e4000c10e184 */
/*0900*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0910*/ BSSY B0, 0x9b0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0920*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0930*/ @P4 BRA !P0, 0x9a0 ; /* 0x0000006000004947 */
/* 0x000fea0004000000 */
/*0940*/ S2R R4, SR_LANEID ; /* 0x0000000000047919 */
/* 0x000e620000000000 */
/*0950*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0960*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0970*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*0980*/ ISETP.EQ.U32.AND P0, PT, R4, UR7, PT ; /* 0x0000000704007c0c */
/* 0x002fda000bf02070 */
/*0990*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x24], R7 ; /* 0x000024070200098e */
/* 0x0011e4000c10e184 */
/*09a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09b0*/ IADD3 R2, P0, R2, 0x28, RZ ; /* 0x0000002802027810 */
/* 0x001fca0007f1e0ff */
/*09c0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*09d0*/ @!P5 BRA 0xe0 ; /* 0xfffff7000000d947 */
/* 0x000fea000383ffff */
/*09e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define iceil(num, den) (num + den - 1) / den
#define ARRAY_SIZE 20 //must be an even number; this number/2 = number of points //sets random array and constant mem size
//#define BIN 100 //divides the grid into square bins to vote on. perfect square value
#define NUM_LINES 4 //top X voted lines. Picks first X Largest from top left to bottom right of grid space.
/*GRID evaluated for bin voting
* Must always be a square grid with origin at center
*/
#define dimension 5
#define LXBOUND (-1*dimension) //lowest X
#define RXBOUND (dimension) //highest X
#define LYBOUND (-1*dimension) //lowest Y
#define UYBOUND (dimension) //highest Y
////////////////////////////////
#define INCREMENT 1 //precision, length of 1 side of the square(bin)
//The (abs)difference between between two sides is the length of the grid. Length/Increment determines how many bins
#define column (((RXBOUND - LXBOUND) / INCREMENT) * ((RXBOUND - LXBOUND) / INCREMENT)) / ((RXBOUND + UYBOUND) / INCREMENT)
__constant__ int d_coordarray[ARRAY_SIZE];//Place coordinates in constant memory
//show grid with votes. Becomes unuseful when bins > 20x20
__global__ void kernelHough(int size, int* d_binarray) {
/*
take a piece of the array. discretize into y=mx+b format per point. check all points and increment all bins touched
at the end recombine all shared memory to a global bin tally. Take the most significant X numbers as lines.
discretized from point(1,1) ==(m,n)==> (-1,1)
check each bin for count and sum them to a global array in sync
NUM of coordinates will check all bins for their own equation and increment appropriately
*/
// Number from 0 through arraysize / 2
const int thread = 2 * (blockDim.x * blockIdx.x + threadIdx.x);
// Slope is discretized space = -x
const float slope = -1.0 * d_coordarray[thread];
// Intercept in discretized space = y
const float intercept = d_coordarray[thread + 1];
int counter = 0;//keeps current array index being checked
//loop through entire graph
for (float x = LXBOUND; x < RXBOUND; x += INCREMENT) {
const float xMin = x;
const float xMax = x + INCREMENT;
for (float y = UYBOUND; y > LYBOUND; y -= INCREMENT) {
const float yMin = y - INCREMENT;
const float yMax = y;
//calculates possible y range associated with the known x range
const float lower_range = slope * xMin + intercept;
const float upper_range = slope * xMax + intercept;
//if the possible y ranges corresponding to the x values exist within the actual y range increment bin
if ((lower_range <= yMax && lower_range >= yMin) || (upper_range <= yMax && upper_range >= yMin))
atomicAdd(&d_binarray[counter], 1);//increment bin, protected from race condition
counter++;
}
}
} | .file "tmpxft_0005aa5b_00000000-6_kernelHough.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11kernelHoughiPiiPi
.type _Z32__device_stub__Z11kernelHoughiPiiPi, @function
_Z32__device_stub__Z11kernelHoughiPiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11kernelHoughiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11kernelHoughiPiiPi, .-_Z32__device_stub__Z11kernelHoughiPiiPi
.globl _Z11kernelHoughiPi
.type _Z11kernelHoughiPi, @function
_Z11kernelHoughiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11kernelHoughiPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kernelHoughiPi, .-_Z11kernelHoughiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kernelHoughiPi"
.LC1:
.string "d_coordarray"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kernelHoughiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $80, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12d_coordarray(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL12d_coordarray
.comm _ZL12d_coordarray,80,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define iceil(num, den) (num + den - 1) / den
#define ARRAY_SIZE 20 //must be an even number; this number/2 = number of points //sets random array and constant mem size
//#define BIN 100 //divides the grid into square bins to vote on. perfect square value
#define NUM_LINES 4 //top X voted lines. Picks first X Largest from top left to bottom right of grid space.
/*GRID evaluated for bin voting
* Must always be a square grid with origin at center
*/
#define dimension 5
#define LXBOUND (-1*dimension) //lowest X
#define RXBOUND (dimension) //highest X
#define LYBOUND (-1*dimension) //lowest Y
#define UYBOUND (dimension) //highest Y
////////////////////////////////
#define INCREMENT 1 //precision, length of 1 side of the square(bin)
//The (abs)difference between between two sides is the length of the grid. Length/Increment determines how many bins
#define column (((RXBOUND - LXBOUND) / INCREMENT) * ((RXBOUND - LXBOUND) / INCREMENT)) / ((RXBOUND + UYBOUND) / INCREMENT)
__constant__ int d_coordarray[ARRAY_SIZE];//Place coordinates in constant memory
//show grid with votes. Becomes unuseful when bins > 20x20
__global__ void kernelHough(int size, int* d_binarray) {
/*
take a piece of the array. discretize into y=mx+b format per point. check all points and increment all bins touched
at the end recombine all shared memory to a global bin tally. Take the most significant X numbers as lines.
discretized from point(1,1) ==(m,n)==> (-1,1)
check each bin for count and sum them to a global array in sync
NUM of coordinates will check all bins for their own equation and increment appropriately
*/
// Number from 0 through arraysize / 2
const int thread = 2 * (blockDim.x * blockIdx.x + threadIdx.x);
// Slope is discretized space = -x
const float slope = -1.0 * d_coordarray[thread];
// Intercept in discretized space = y
const float intercept = d_coordarray[thread + 1];
int counter = 0;//keeps current array index being checked
//loop through entire graph
for (float x = LXBOUND; x < RXBOUND; x += INCREMENT) {
const float xMin = x;
const float xMax = x + INCREMENT;
for (float y = UYBOUND; y > LYBOUND; y -= INCREMENT) {
const float yMin = y - INCREMENT;
const float yMax = y;
//calculates possible y range associated with the known x range
const float lower_range = slope * xMin + intercept;
const float upper_range = slope * xMax + intercept;
//if the possible y ranges corresponding to the x values exist within the actual y range increment bin
if ((lower_range <= yMax && lower_range >= yMin) || (upper_range <= yMax && upper_range >= yMin))
atomicAdd(&d_binarray[counter], 1);//increment bin, protected from race condition
counter++;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define iceil(num, den) (num + den - 1) / den
#define ARRAY_SIZE 20 //must be an even number; this number/2 = number of points //sets random array and constant mem size
//#define BIN 100 //divides the grid into square bins to vote on. perfect square value
#define NUM_LINES 4 //top X voted lines. Picks first X Largest from top left to bottom right of grid space.
/*GRID evaluated for bin voting
* Must always be a square grid with origin at center
*/
#define dimension 5
#define LXBOUND (-1*dimension) //lowest X
#define RXBOUND (dimension) //highest X
#define LYBOUND (-1*dimension) //lowest Y
#define UYBOUND (dimension) //highest Y
////////////////////////////////
#define INCREMENT 1 //precision, length of 1 side of the square(bin)
//The (abs)difference between between two sides is the length of the grid. Length/Increment determines how many bins
#define column (((RXBOUND - LXBOUND) / INCREMENT) * ((RXBOUND - LXBOUND) / INCREMENT)) / ((RXBOUND + UYBOUND) / INCREMENT)
__constant__ int d_coordarray[ARRAY_SIZE];//Place coordinates in constant memory
//show grid with votes. Becomes unuseful when bins > 20x20
__global__ void kernelHough(int size, int* d_binarray) {
/*
take a piece of the array. discretize into y=mx+b format per point. check all points and increment all bins touched
at the end recombine all shared memory to a global bin tally. Take the most significant X numbers as lines.
discretized from point(1,1) ==(m,n)==> (-1,1)
check each bin for count and sum them to a global array in sync
NUM of coordinates will check all bins for their own equation and increment appropriately
*/
// Number from 0 through arraysize / 2
const int thread = 2 * (blockDim.x * blockIdx.x + threadIdx.x);
// Slope is discretized space = -x
const float slope = -1.0 * d_coordarray[thread];
// Intercept in discretized space = y
const float intercept = d_coordarray[thread + 1];
int counter = 0;//keeps current array index being checked
//loop through entire graph
for (float x = LXBOUND; x < RXBOUND; x += INCREMENT) {
const float xMin = x;
const float xMax = x + INCREMENT;
for (float y = UYBOUND; y > LYBOUND; y -= INCREMENT) {
const float yMin = y - INCREMENT;
const float yMax = y;
//calculates possible y range associated with the known x range
const float lower_range = slope * xMin + intercept;
const float upper_range = slope * xMax + intercept;
//if the possible y ranges corresponding to the x values exist within the actual y range increment bin
if ((lower_range <= yMax && lower_range >= yMin) || (upper_range <= yMax && upper_range >= yMin))
atomicAdd(&d_binarray[counter], 1);//increment bin, protected from race condition
counter++;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define iceil(num, den) (num + den - 1) / den
#define ARRAY_SIZE 20 //must be an even number; this number/2 = number of points //sets random array and constant mem size
//#define BIN 100 //divides the grid into square bins to vote on. perfect square value
#define NUM_LINES 4 //top X voted lines. Picks first X Largest from top left to bottom right of grid space.
/*GRID evaluated for bin voting
* Must always be a square grid with origin at center
*/
#define dimension 5
#define LXBOUND (-1*dimension) //lowest X
#define RXBOUND (dimension) //highest X
#define LYBOUND (-1*dimension) //lowest Y
#define UYBOUND (dimension) //highest Y
////////////////////////////////
#define INCREMENT 1 //precision, length of 1 side of the square(bin)
//The (abs)difference between between two sides is the length of the grid. Length/Increment determines how many bins
#define column (((RXBOUND - LXBOUND) / INCREMENT) * ((RXBOUND - LXBOUND) / INCREMENT)) / ((RXBOUND + UYBOUND) / INCREMENT)
__constant__ int d_coordarray[ARRAY_SIZE];//Place coordinates in constant memory
//show grid with votes. Becomes unuseful when bins > 20x20
__global__ void kernelHough(int size, int* d_binarray) {
/*
take a piece of the array. discretize into y=mx+b format per point. check all points and increment all bins touched
at the end recombine all shared memory to a global bin tally. Take the most significant X numbers as lines.
discretized from point(1,1) ==(m,n)==> (-1,1)
check each bin for count and sum them to a global array in sync
NUM of coordinates will check all bins for their own equation and increment appropriately
*/
// Number from 0 through arraysize / 2
const int thread = 2 * (blockDim.x * blockIdx.x + threadIdx.x);
// Slope is discretized space = -x
const float slope = -1.0 * d_coordarray[thread];
// Intercept in discretized space = y
const float intercept = d_coordarray[thread + 1];
int counter = 0;//keeps current array index being checked
//loop through entire graph
for (float x = LXBOUND; x < RXBOUND; x += INCREMENT) {
const float xMin = x;
const float xMax = x + INCREMENT;
for (float y = UYBOUND; y > LYBOUND; y -= INCREMENT) {
const float yMin = y - INCREMENT;
const float yMax = y;
//calculates possible y range associated with the known x range
const float lower_range = slope * xMin + intercept;
const float upper_range = slope * xMax + intercept;
//if the possible y ranges corresponding to the x values exist within the actual y range increment bin
if ((lower_range <= yMax && lower_range >= yMin) || (upper_range <= yMax && upper_range >= yMin))
atomicAdd(&d_binarray[counter], 1);//increment bin, protected from race condition
counter++;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kernelHoughiPi
.globl _Z11kernelHoughiPi
.p2align 8
.type _Z11kernelHoughiPi,@function
_Z11kernelHoughiPi:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_coordarray@rel32@lo+4
s_addc_u32 s3, s3, d_coordarray@rel32@hi+12
v_add_lshl_u32 v0, s15, v0, 1
v_or_b32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, v0, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b64 s[2:3], s[0:1], 0x8
s_mov_b32 s1, 0
s_clause 0x1
global_load_b32 v0, v[0:1], off
global_load_b32 v2, v[2:3], off
v_mov_b32_e32 v1, 0xc0a00000
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v0, v0
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v2, v2
s_branch .LBB0_2
.LBB0_1:
s_set_inst_prefetch_distance 0x2
v_cmp_gt_f32_e32 vcc_lo, 0x40a00000, v1
s_add_i32 s1, s1, s4
s_cbranch_vccz .LBB0_10
.LBB0_2:
v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v7, 0x40a00000
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v1, 1.0, v4
v_fma_f32 v4, -v4, v0, v2
v_fma_f32 v5, -v1, v0, v2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v6, -1.0, v7
v_cmp_nle_f32_e32 vcc_lo, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_nge_f32_e64 s0, v4, v6
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, s0, -1
s_and_saveexec_b32 s6, s0
v_cmp_le_f32_e32 vcc_lo, v5, v7
v_cmp_ge_f32_e64 s0, v5, v6
s_and_not1_b32 s5, s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s0
s_or_b32 exec_lo, exec_lo, s6
s_and_saveexec_b32 s0, s5
s_cbranch_execz .LBB0_8
s_mov_b32 s5, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v7, s5, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v7
s_and_b32 s6, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s6
s_cbranch_execz .LBB0_8
s_add_i32 s6, s1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[6:7], s[6:7], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_bcnt1_i32_b32 s5, s5
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v7, s5
global_atomic_add_u32 v3, v7, s[6:7]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 10
s_cbranch_scc1 .LBB0_1
v_mov_b32_e32 v7, v6
s_branch .LBB0_3
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kernelHoughiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kernelHoughiPi, .Lfunc_end0-_Z11kernelHoughiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_coordarray
.type d_coordarray,@object
.section .bss,"aw",@nobits
.globl d_coordarray
.p2align 4, 0x0
d_coordarray:
.zero 80
.size d_coordarray, 80
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_coordarray
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kernelHoughiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kernelHoughiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define iceil(num, den) (num + den - 1) / den
#define ARRAY_SIZE 20 //must be an even number; this number/2 = number of points //sets random array and constant mem size
//#define BIN 100 //divides the grid into square bins to vote on. perfect square value
#define NUM_LINES 4 //top X voted lines. Picks first X Largest from top left to bottom right of grid space.
/*GRID evaluated for bin voting
* Must always be a square grid with origin at center
*/
#define dimension 5
#define LXBOUND (-1*dimension) //lowest X
#define RXBOUND (dimension) //highest X
#define LYBOUND (-1*dimension) //lowest Y
#define UYBOUND (dimension) //highest Y
////////////////////////////////
#define INCREMENT 1 //precision, length of 1 side of the square(bin)
//The (abs)difference between between two sides is the length of the grid. Length/Increment determines how many bins
#define column (((RXBOUND - LXBOUND) / INCREMENT) * ((RXBOUND - LXBOUND) / INCREMENT)) / ((RXBOUND + UYBOUND) / INCREMENT)
__constant__ int d_coordarray[ARRAY_SIZE];//Place coordinates in constant memory
//show grid with votes. Becomes unuseful when bins > 20x20
__global__ void kernelHough(int size, int* d_binarray) {
/*
take a piece of the array. discretize into y=mx+b format per point. check all points and increment all bins touched
at the end recombine all shared memory to a global bin tally. Take the most significant X numbers as lines.
discretized from point(1,1) ==(m,n)==> (-1,1)
check each bin for count and sum them to a global array in sync
NUM of coordinates will check all bins for their own equation and increment appropriately
*/
// Number from 0 through arraysize / 2
const int thread = 2 * (blockDim.x * blockIdx.x + threadIdx.x);
// Slope is discretized space = -x
const float slope = -1.0 * d_coordarray[thread];
// Intercept in discretized space = y
const float intercept = d_coordarray[thread + 1];
int counter = 0;//keeps current array index being checked
//loop through entire graph
for (float x = LXBOUND; x < RXBOUND; x += INCREMENT) {
const float xMin = x;
const float xMax = x + INCREMENT;
for (float y = UYBOUND; y > LYBOUND; y -= INCREMENT) {
const float yMin = y - INCREMENT;
const float yMax = y;
//calculates possible y range associated with the known x range
const float lower_range = slope * xMin + intercept;
const float upper_range = slope * xMax + intercept;
//if the possible y ranges corresponding to the x values exist within the actual y range increment bin
if ((lower_range <= yMax && lower_range >= yMin) || (upper_range <= yMax && upper_range >= yMin))
atomicAdd(&d_binarray[counter], 1);//increment bin, protected from race condition
counter++;
}
}
} | .text
.file "kernelHough.hip"
.globl _Z26__device_stub__kernelHoughiPi # -- Begin function _Z26__device_stub__kernelHoughiPi
.p2align 4, 0x90
.type _Z26__device_stub__kernelHoughiPi,@function
_Z26__device_stub__kernelHoughiPi: # @_Z26__device_stub__kernelHoughiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11kernelHoughiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__kernelHoughiPi, .Lfunc_end0-_Z26__device_stub__kernelHoughiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kernelHoughiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_coordarray, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $80, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_coordarray,@object # @d_coordarray
.local d_coordarray
.comm d_coordarray,80,16
.type _Z11kernelHoughiPi,@object # @_Z11kernelHoughiPi
.section .rodata,"a",@progbits
.globl _Z11kernelHoughiPi
.p2align 3, 0x0
_Z11kernelHoughiPi:
.quad _Z26__device_stub__kernelHoughiPi
.size _Z11kernelHoughiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kernelHoughiPi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_coordarray"
.size .L__unnamed_2, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kernelHoughiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_coordarray
.addrsig_sym _Z11kernelHoughiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11kernelHoughiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, -0x3f600000 ; /* 0xc0a00000ff087424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fc800078e00ff */
/*0070*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fc800078e00ff */
/*0080*/ LDC.64 R6, c[0x3][R4] ; /* 0x00c0000004067b82 */
/* 0x000e240000000a00 */
/*0090*/ I2F.F64 R2, R6 ; /* 0x0000000600027312 */
/* 0x001e300000201c00 */
/*00a0*/ I2F R0, R7 ; /* 0x0000000700007306 */
/* 0x0002b00000201400 */
/*00b0*/ F2F.F32.F64 R5, R2 ; /* 0x0000000200057310 */
/* 0x0010e40000301000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x001fc400078e00ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x006fc800078e00ff */
/*00e0*/ FADD R4, R8, 1 ; /* 0x3f80000008047421 */
/* 0x000fe20000000000 */
/*00f0*/ BSSY B0, 0x250 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0100*/ FFMA R9, -R5.reuse, R8, R0.reuse ; /* 0x0000000805097223 */
/* 0x148fe40000000100 */
/*0110*/ FFMA R10, -R5, R4, R0 ; /* 0x00000004050a7223 */
/* 0x000fc60000000100 */
/*0120*/ FSETP.GE.AND P0, PT, R9.reuse, 4, PT ; /* 0x408000000900780b */
/* 0x040fe40003f06000 */
/*0130*/ FSETP.GE.AND P4, PT, R10.reuse, 4, PT ; /* 0x408000000a00780b */
/* 0x040fe40003f86000 */
/*0140*/ FSETP.LE.AND P0, PT, R9.reuse, 5, P0 ; /* 0x40a000000900780b */
/* 0x040fe40000703000 */
/*0150*/ FSETP.GTU.OR P4, PT, R10, 5, !P4 ; /* 0x40a000000a00780b */
/* 0x000fe4000678c400 */
/*0160*/ FSETP.GE.AND P2, PT, R9.reuse, -1, PT ; /* 0xbf8000000900780b */
/* 0x040fe40003f46000 */
/*0170*/ FSETP.GE.AND P6, PT, R9, 3, PT ; /* 0x404000000900780b */
/* 0x000fc40003fc6000 */
/*0180*/ P2R R6, PR, RZ, 0x4 ; /* 0x00000004ff067803 */
/* 0x000fe40000000000 */
/*0190*/ FSETP.GE.AND P1, PT, R9.reuse, 2, PT ; /* 0x400000000900780b */
/* 0x040fe40003f26000 */
/*01a0*/ FSETP.GE.AND P3, PT, R9.reuse, 1, PT ; /* 0x3f8000000900780b */
/* 0x040fe40003f66000 */
/*01b0*/ FSETP.GE.AND P5, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fe40003fa6000 */
/*01c0*/ FSETP.GE.AND P2, PT, R10, 3, PT ; /* 0x404000000a00780b */
/* 0x000fe20003f46000 */
/*01d0*/ @P4 BRA !P0, 0x240 ; /* 0x0000006000004947 */
/* 0x000fee0004000000 */
/*01e0*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e220000000000 */
/*01f0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fc400038e0100 */
/*0200*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0210*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x000e6a0008000000 */
/*0220*/ ISETP.EQ.U32.AND P0, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x001fda000bf02070 */
/*0230*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R7 ; /* 0x000000070200098e */
/* 0x0021e4000c10e184 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ FSETP.LE.AND P6, PT, R9.reuse, 4, P6 ; /* 0x408000000900780b */
/* 0x040fe200037c3000 */
/*0260*/ BSSY B0, 0x320 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0270*/ FSETP.GTU.OR P2, PT, R10.reuse, 4, !P2 ; /* 0x408000000a00780b */
/* 0x040fe4000574c400 */
/*0280*/ FSETP.GE.AND P4, PT, R9, -2, PT ; /* 0xc00000000900780b */
/* 0x000fe40003f86000 */
/*0290*/ FSETP.GE.AND P0, PT, R10, 2, PT ; /* 0x400000000a00780b */
/* 0x000fd20003f06000 */
/*02a0*/ @P2 BRA !P6, 0x310 ; /* 0x0000006000002947 */
/* 0x000fea0007000000 */
/*02b0*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*02c0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*02d0*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*02e0*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*02f0*/ ISETP.EQ.U32.AND P2, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bf42070 */
/*0300*/ @P2 RED.E.ADD.STRONG.GPU [R2.64+0x4], R7 ; /* 0x000004070200298e */
/* 0x0011e4000c10e184 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ FSETP.LE.AND P1, PT, R9.reuse, 3, P1 ; /* 0x404000000900780b */
/* 0x040fe20000f23000 */
/*0330*/ BSSY B0, 0x3f0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0340*/ FSETP.GTU.OR P6, PT, R10.reuse, 3, !P0 ; /* 0x404000000a00780b */
/* 0x040fe400047cc400 */
/*0350*/ FSETP.GE.AND P2, PT, R9, -3, PT ; /* 0xc04000000900780b */
/* 0x000fe40003f46000 */
/*0360*/ FSETP.GE.AND P0, PT, R10, 1, PT ; /* 0x3f8000000a00780b */
/* 0x000fd20003f06000 */
/*0370*/ @P6 BRA !P1, 0x3e0 ; /* 0x0000006000006947 */
/* 0x000fea0004800000 */
/*0380*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*0390*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*03a0*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*03b0*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*03c0*/ ISETP.EQ.U32.AND P1, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bf22070 */
/*03d0*/ @P1 RED.E.ADD.STRONG.GPU [R2.64+0x8], R7 ; /* 0x000008070200198e */
/* 0x0011e4000c10e184 */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ FSETP.LE.AND P3, PT, R9.reuse, 2, P3 ; /* 0x400000000900780b */
/* 0x040fe20001f63000 */
/*0400*/ BSSY B0, 0x4c0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0410*/ FSETP.GTU.OR P6, PT, R10, 2, !P0 ; /* 0x400000000a00780b */
/* 0x000fe400047cc400 */
/*0420*/ FSETP.GE.AND P1, PT, R9.reuse, -4, PT ; /* 0xc08000000900780b */
/* 0x040fe40003f26000 */
/*0430*/ FSETP.GE.AND P0, PT, R9, -5, PT ; /* 0xc0a000000900780b */
/* 0x000fd20003f06000 */
/*0440*/ @P6 BRA !P3, 0x4b0 ; /* 0x0000006000006947 */
/* 0x000fea0005800000 */
/*0450*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*0460*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0470*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0480*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*0490*/ ISETP.EQ.U32.AND P3, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bf62070 */
/*04a0*/ @P3 RED.E.ADD.STRONG.GPU [R2.64+0xc], R7 ; /* 0x00000c070200398e */
/* 0x0011e4000c10e184 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ FSETP.GE.AND P6, PT, R10.reuse, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x040fe20003fc6000 */
/*04d0*/ BSSY B0, 0x5d0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*04e0*/ FSETP.LE.AND P5, PT, R9.reuse, 1, P5 ; /* 0x3f8000000900780b */
/* 0x040fe40002fa3000 */
/*04f0*/ FSETP.GTU.OR P6, PT, R10, 1, !P6 ; /* 0x3f8000000a00780b */
/* 0x000fe400077cc400 */
/*0500*/ FSETP.LE.AND P4, PT, R9, -1, P4 ; /* 0xbf8000000900780b */
/* 0x000fe40002783000 */
/*0510*/ ISETP.NE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f65270 */
/*0520*/ P2R R6, PR, RZ, 0x10 ; /* 0x00000010ff067803 */
/* 0x000fc40000000000 */
/*0530*/ FSETP.LE.AND P3, PT, R9, RZ, P3 ; /* 0x000000ff0900720b */
/* 0x000fe40001f63000 */
/*0540*/ FSETP.GE.AND P4, PT, R10, -1, PT ; /* 0xbf8000000a00780b */
/* 0x000fc60003f86000 */
/*0550*/ @P6 BRA !P5, 0x5c0 ; /* 0x0000006000006947 */
/* 0x000fea0006800000 */
/*0560*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*0570*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0580*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0590*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*05a0*/ ISETP.EQ.U32.AND P5, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bfa2070 */
/*05b0*/ @P5 RED.E.ADD.STRONG.GPU [R2.64+0x10], R7 ; /* 0x000010070200598e */
/* 0x0011e4000c10e184 */
/*05c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05d0*/ FSETP.GTU.OR P6, PT, R10.reuse, RZ, !P4 ; /* 0x000000ff0a00720b */
/* 0x040fe200067cc400 */
/*05e0*/ BSSY B0, 0x6b0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*05f0*/ FSETP.GE.AND P5, PT, R10.reuse, -2, PT ; /* 0xc00000000a00780b */
/* 0x040fe40003fa6000 */
/*0600*/ FSETP.LE.AND P2, PT, R9.reuse, -2, P2 ; /* 0xc00000000900780b */
/* 0x040fe40001743000 */
/*0610*/ FSETP.LE.AND P1, PT, R9, -3, P1 ; /* 0xc04000000900780b */
/* 0x000fe40000f23000 */
/*0620*/ FSETP.GE.AND P4, PT, R10, -3, PT ; /* 0xc04000000a00780b */
/* 0x000fca0003f86000 */
/*0630*/ @P6 BRA !P3, 0x6a0 ; /* 0x0000006000006947 */
/* 0x000fea0005800000 */
/*0640*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*0650*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0660*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0670*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*0680*/ ISETP.EQ.U32.AND P3, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bf62070 */
/*0690*/ @P3 RED.E.ADD.STRONG.GPU [R2.64+0x14], R7 ; /* 0x000014070200398e */
/* 0x0011e4000c10e184 */
/*06a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06b0*/ ISETP.NE.AND P6, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003fc5270 */
/*06c0*/ BSSY B0, 0x7d0 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*06d0*/ FSETP.GTU.OR P5, PT, R10.reuse, -1, !P5 ; /* 0xbf8000000a00780b */
/* 0x040fe40006fac400 */
/*06e0*/ FSETP.GTU.OR P4, PT, R10.reuse, -2, !P4 ; /* 0xc00000000a00780b */
/* 0x040fe4000678c400 */
/*06f0*/ FSETP.GE.AND P3, PT, R10.reuse, -4, PT ; /* 0xc08000000a00780b */
/* 0x040fe40003f66000 */
/*0700*/ P2R R6, PR, RZ, 0x10 ; /* 0x00000010ff067803 */
/* 0x000fe40000000000 */
/*0710*/ FSETP.GE.AND P4, PT, R10, -5, PT ; /* 0xc0a000000a00780b */
/* 0x000fc40003f86000 */
/*0720*/ FSETP.LE.AND P0, PT, R9, -4, P0 ; /* 0xc08000000900780b */
/* 0x000fe40000703000 */
/*0730*/ FSETP.GTU.OR P3, PT, R10.reuse, -3, !P3 ; /* 0xc04000000a00780b */
/* 0x040fe40005f6c400 */
/*0740*/ FSETP.GTU.OR P4, PT, R10, -4, !P4 ; /* 0xc08000000a00780b */
/* 0x000fe2000678c400 */
/*0750*/ @P5 BRA !P6, 0x7c0 ; /* 0x0000006000005947 */
/* 0x000fee0007000000 */
/*0760*/ S2R R8, SR_LANEID ; /* 0x0000000000087919 */
/* 0x000e620000000000 */
/*0770*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0780*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0790*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*07a0*/ ISETP.EQ.U32.AND P5, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x002fda000bfa2070 */
/*07b0*/ @P5 RED.E.ADD.STRONG.GPU [R2.64+0x18], R7 ; /* 0x000018070200598e */
/* 0x0011e4000c10e184 */
/*07c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07d0*/ ISETP.NE.AND P6, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003fc5270 */
/*07e0*/ BSSY B0, 0x880 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*07f0*/ FSETP.GEU.AND P5, PT, R4, 5, PT ; /* 0x40a000000400780b */
/* 0x000fd60003fae000 */
/*0800*/ @P6 BRA !P2, 0x870 ; /* 0x0000006000006947 */
/* 0x000fea0005000000 */
/*0810*/ S2R R6, SR_LANEID ; /* 0x0000000000067919 */
/* 0x000e620000000000 */
/*0820*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0830*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0840*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*0850*/ ISETP.EQ.U32.AND P2, PT, R6, UR7, PT ; /* 0x0000000706007c0c */
/* 0x002fda000bf42070 */
/*0860*/ @P2 RED.E.ADD.STRONG.GPU [R2.64+0x1c], R7 ; /* 0x00001c070200298e */
/* 0x0011e4000c10e184 */
/*0870*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0880*/ BSSY B0, 0x910 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0890*/ @P3 BRA !P1, 0x900 ; /* 0x0000006000003947 */
/* 0x000fea0004800000 */
/*08a0*/ S2R R6, SR_LANEID ; /* 0x0000000000067919 */
/* 0x000e620000000000 */
/*08b0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*08c0*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*08d0*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*08e0*/ ISETP.EQ.U32.AND P1, PT, R6, UR7, PT ; /* 0x0000000706007c0c */
/* 0x002fda000bf22070 */
/*08f0*/ @P1 RED.E.ADD.STRONG.GPU [R2.64+0x20], R7 ; /* 0x000020070200198e */
/* 0x0011e4000c10e184 */
/*0900*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0910*/ BSSY B0, 0x9b0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0920*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0930*/ @P4 BRA !P0, 0x9a0 ; /* 0x0000006000004947 */
/* 0x000fea0004000000 */
/*0940*/ S2R R4, SR_LANEID ; /* 0x0000000000047919 */
/* 0x000e620000000000 */
/*0950*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0960*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0970*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x001e2a0008000000 */
/*0980*/ ISETP.EQ.U32.AND P0, PT, R4, UR7, PT ; /* 0x0000000704007c0c */
/* 0x002fda000bf02070 */
/*0990*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x24], R7 ; /* 0x000024070200098e */
/* 0x0011e4000c10e184 */
/*09a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09b0*/ IADD3 R2, P0, R2, 0x28, RZ ; /* 0x0000002802027810 */
/* 0x001fca0007f1e0ff */
/*09c0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*09d0*/ @!P5 BRA 0xe0 ; /* 0xfffff7000000d947 */
/* 0x000fea000383ffff */
/*09e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kernelHoughiPi
.globl _Z11kernelHoughiPi
.p2align 8
.type _Z11kernelHoughiPi,@function
_Z11kernelHoughiPi:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_coordarray@rel32@lo+4
s_addc_u32 s3, s3, d_coordarray@rel32@hi+12
v_add_lshl_u32 v0, s15, v0, 1
v_or_b32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, v0, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b64 s[2:3], s[0:1], 0x8
s_mov_b32 s1, 0
s_clause 0x1
global_load_b32 v0, v[0:1], off
global_load_b32 v2, v[2:3], off
v_mov_b32_e32 v1, 0xc0a00000
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v0, v0
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v2, v2
s_branch .LBB0_2
.LBB0_1:
s_set_inst_prefetch_distance 0x2
v_cmp_gt_f32_e32 vcc_lo, 0x40a00000, v1
s_add_i32 s1, s1, s4
s_cbranch_vccz .LBB0_10
.LBB0_2:
v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v7, 0x40a00000
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v1, 1.0, v4
v_fma_f32 v4, -v4, v0, v2
v_fma_f32 v5, -v1, v0, v2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v6, -1.0, v7
v_cmp_nle_f32_e32 vcc_lo, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_nge_f32_e64 s0, v4, v6
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, s0, -1
s_and_saveexec_b32 s6, s0
v_cmp_le_f32_e32 vcc_lo, v5, v7
v_cmp_ge_f32_e64 s0, v5, v6
s_and_not1_b32 s5, s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s0
s_or_b32 exec_lo, exec_lo, s6
s_and_saveexec_b32 s0, s5
s_cbranch_execz .LBB0_8
s_mov_b32 s5, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v7, s5, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v7
s_and_b32 s6, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s6
s_cbranch_execz .LBB0_8
s_add_i32 s6, s1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[6:7], s[6:7], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_bcnt1_i32_b32 s5, s5
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v7, s5
global_atomic_add_u32 v3, v7, s[6:7]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 10
s_cbranch_scc1 .LBB0_1
v_mov_b32_e32 v7, v6
s_branch .LBB0_3
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kernelHoughiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kernelHoughiPi, .Lfunc_end0-_Z11kernelHoughiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_coordarray
.type d_coordarray,@object
.section .bss,"aw",@nobits
.globl d_coordarray
.p2align 4, 0x0
d_coordarray:
.zero 80
.size d_coordarray, 80
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_coordarray
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kernelHoughiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kernelHoughiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005aa5b_00000000-6_kernelHough.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11kernelHoughiPiiPi
.type _Z32__device_stub__Z11kernelHoughiPiiPi, @function
_Z32__device_stub__Z11kernelHoughiPiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11kernelHoughiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11kernelHoughiPiiPi, .-_Z32__device_stub__Z11kernelHoughiPiiPi
.globl _Z11kernelHoughiPi
.type _Z11kernelHoughiPi, @function
_Z11kernelHoughiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11kernelHoughiPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kernelHoughiPi, .-_Z11kernelHoughiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kernelHoughiPi"
.LC1:
.string "d_coordarray"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kernelHoughiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $80, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12d_coordarray(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL12d_coordarray
.comm _ZL12d_coordarray,80,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelHough.hip"
.globl _Z26__device_stub__kernelHoughiPi # -- Begin function _Z26__device_stub__kernelHoughiPi
.p2align 4, 0x90
.type _Z26__device_stub__kernelHoughiPi,@function
_Z26__device_stub__kernelHoughiPi: # @_Z26__device_stub__kernelHoughiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11kernelHoughiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__kernelHoughiPi, .Lfunc_end0-_Z26__device_stub__kernelHoughiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kernelHoughiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_coordarray, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $80, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_coordarray,@object # @d_coordarray
.local d_coordarray
.comm d_coordarray,80,16
.type _Z11kernelHoughiPi,@object # @_Z11kernelHoughiPi
.section .rodata,"a",@progbits
.globl _Z11kernelHoughiPi
.p2align 3, 0x0
_Z11kernelHoughiPi:
.quad _Z26__device_stub__kernelHoughiPi
.size _Z11kernelHoughiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kernelHoughiPi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_coordarray"
.size .L__unnamed_2, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kernelHoughiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_coordarray
.addrsig_sym _Z11kernelHoughiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void Sample1Kernel(float *d_A, float *d_B, float *d_C) {
// Step 1. 自身のCUDAスレッドIDを計算する
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
// Step 2. CUDAスレッドIDを用いてグローバルメモリからデータを読み込み，計算する
d_C[thread_id] = d_A[thread_id] + d_B[thread_id];
}
__host__ void Sample1Host(float *h_A, float *h_B, float *h_C, int length) {
for (int i = 0; i < length; ++i) {
h_C[i] = h_A[i] + h_B[i];
}
} | code for sm_80
Function : _Z13Sample1KernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void Sample1Kernel(float *d_A, float *d_B, float *d_C) {
// Step 1. 自身のCUDAスレッドIDを計算する
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
// Step 2. CUDAスレッドIDを用いてグローバルメモリからデータを読み込み，計算する
d_C[thread_id] = d_A[thread_id] + d_B[thread_id];
}
__host__ void Sample1Host(float *h_A, float *h_B, float *h_C, int length) {
for (int i = 0; i < length; ++i) {
h_C[i] = h_A[i] + h_B[i];
}
} | .file "tmpxft_000778e8_00000000-6_sample1_kernel_time.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11Sample1HostPfS_S_i
.type _Z11Sample1HostPfS_S_i, @function
_Z11Sample1HostPfS_S_i:
.LFB2027:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L5:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2027:
.size _Z11Sample1HostPfS_S_i, .-_Z11Sample1HostPfS_S_i
.globl _Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_
.type _Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_, @function
_Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13Sample1KernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_, .-_Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_
.globl _Z13Sample1KernelPfS_S_
.type _Z13Sample1KernelPfS_S_, @function
_Z13Sample1KernelPfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13Sample1KernelPfS_S_, .-_Z13Sample1KernelPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13Sample1KernelPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Sample1KernelPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void Sample1Kernel(float *d_A, float *d_B, float *d_C) {
// Step 1. 自身のCUDAスレッドIDを計算する
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
// Step 2. CUDAスレッドIDを用いてグローバルメモリからデータを読み込み，計算する
d_C[thread_id] = d_A[thread_id] + d_B[thread_id];
}
__host__ void Sample1Host(float *h_A, float *h_B, float *h_C, int length) {
for (int i = 0; i < length; ++i) {
h_C[i] = h_A[i] + h_B[i];
}
} | #include <hip/hip_runtime.h>
__global__ void Sample1Kernel(float *d_A, float *d_B, float *d_C) {
// Step 1. 自身のCUDAスレッドIDを計算する
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
// Step 2. CUDAスレッドIDを用いてグローバルメモリからデータを読み込み，計算する
d_C[thread_id] = d_A[thread_id] + d_B[thread_id];
}
__host__ void Sample1Host(float *h_A, float *h_B, float *h_C, int length) {
for (int i = 0; i < length; ++i) {
h_C[i] = h_A[i] + h_B[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void Sample1Kernel(float *d_A, float *d_B, float *d_C) {
// Step 1. 自身のCUDAスレッドIDを計算する
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
// Step 2. CUDAスレッドIDを用いてグローバルメモリからデータを読み込み，計算する
d_C[thread_id] = d_A[thread_id] + d_B[thread_id];
}
__host__ void Sample1Host(float *h_A, float *h_B, float *h_C, int length) {
for (int i = 0; i < length; ++i) {
h_C[i] = h_A[i] + h_B[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Sample1KernelPfS_S_
.globl _Z13Sample1KernelPfS_S_
.p2align 8
.type _Z13Sample1KernelPfS_S_,@function
_Z13Sample1KernelPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Sample1KernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Sample1KernelPfS_S_, .Lfunc_end0-_Z13Sample1KernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Sample1KernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13Sample1KernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void Sample1Kernel(float *d_A, float *d_B, float *d_C) {
// Step 1. 自身のCUDAスレッドIDを計算する
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
// Step 2. CUDAスレッドIDを用いてグローバルメモリからデータを読み込み，計算する
d_C[thread_id] = d_A[thread_id] + d_B[thread_id];
}
__host__ void Sample1Host(float *h_A, float *h_B, float *h_C, int length) {
for (int i = 0; i < length; ++i) {
h_C[i] = h_A[i] + h_B[i];
}
} | .text
.file "sample1_kernel_time.hip"
.globl _Z28__device_stub__Sample1KernelPfS_S_ # -- Begin function _Z28__device_stub__Sample1KernelPfS_S_
.p2align 4, 0x90
.type _Z28__device_stub__Sample1KernelPfS_S_,@function
_Z28__device_stub__Sample1KernelPfS_S_: # @_Z28__device_stub__Sample1KernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13Sample1KernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__Sample1KernelPfS_S_, .Lfunc_end0-_Z28__device_stub__Sample1KernelPfS_S_
.cfi_endproc
# -- End function
.globl _Z11Sample1HostPfS_S_i # -- Begin function _Z11Sample1HostPfS_S_i
.p2align 4, 0x90
.type _Z11Sample1HostPfS_S_i,@function
_Z11Sample1HostPfS_S_i: # @_Z11Sample1HostPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11Sample1HostPfS_S_i, .Lfunc_end1-_Z11Sample1HostPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Sample1KernelPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13Sample1KernelPfS_S_,@object # @_Z13Sample1KernelPfS_S_
.section .rodata,"a",@progbits
.globl _Z13Sample1KernelPfS_S_
.p2align 3, 0x0
_Z13Sample1KernelPfS_S_:
.quad _Z28__device_stub__Sample1KernelPfS_S_
.size _Z13Sample1KernelPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13Sample1KernelPfS_S_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Sample1KernelPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13Sample1KernelPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13Sample1KernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Sample1KernelPfS_S_
.globl _Z13Sample1KernelPfS_S_
.p2align 8
.type _Z13Sample1KernelPfS_S_,@function
_Z13Sample1KernelPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Sample1KernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Sample1KernelPfS_S_, .Lfunc_end0-_Z13Sample1KernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Sample1KernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13Sample1KernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000778e8_00000000-6_sample1_kernel_time.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11Sample1HostPfS_S_i
.type _Z11Sample1HostPfS_S_i, @function
_Z11Sample1HostPfS_S_i:
.LFB2027:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L5:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2027:
.size _Z11Sample1HostPfS_S_i, .-_Z11Sample1HostPfS_S_i
.globl _Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_
.type _Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_, @function
_Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13Sample1KernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_, .-_Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_
.globl _Z13Sample1KernelPfS_S_
.type _Z13Sample1KernelPfS_S_, @function
_Z13Sample1KernelPfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13Sample1KernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13Sample1KernelPfS_S_, .-_Z13Sample1KernelPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13Sample1KernelPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Sample1KernelPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sample1_kernel_time.hip"
.globl _Z28__device_stub__Sample1KernelPfS_S_ # -- Begin function _Z28__device_stub__Sample1KernelPfS_S_
.p2align 4, 0x90
.type _Z28__device_stub__Sample1KernelPfS_S_,@function
_Z28__device_stub__Sample1KernelPfS_S_: # @_Z28__device_stub__Sample1KernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13Sample1KernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__Sample1KernelPfS_S_, .Lfunc_end0-_Z28__device_stub__Sample1KernelPfS_S_
.cfi_endproc
# -- End function
.globl _Z11Sample1HostPfS_S_i # -- Begin function _Z11Sample1HostPfS_S_i
.p2align 4, 0x90
.type _Z11Sample1HostPfS_S_i,@function
_Z11Sample1HostPfS_S_i: # @_Z11Sample1HostPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11Sample1HostPfS_S_i, .Lfunc_end1-_Z11Sample1HostPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Sample1KernelPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13Sample1KernelPfS_S_,@object # @_Z13Sample1KernelPfS_S_
.section .rodata,"a",@progbits
.globl _Z13Sample1KernelPfS_S_
.p2align 3, 0x0
_Z13Sample1KernelPfS_S_:
.quad _Z28__device_stub__Sample1KernelPfS_S_
.size _Z13Sample1KernelPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13Sample1KernelPfS_S_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Sample1KernelPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13Sample1KernelPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
Subsets and Splits