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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
35,593 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 35,593 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2017 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "third_party/blink/renderer/core/editing/markers/active_suggestion_marker_list_impl.h"
#include "third_party/blink/renderer/core/editing/markers/active_suggestion_marker.h"
#include "third_party/blink/renderer/core/editing/testing/editing_test_base.h"
namespace blink {
class ActiveSuggestionMarkerListImplTest : public EditingTestBase {
protected:
ActiveSuggestionMarkerListImplTest()
: marker_list_(new ActiveSuggestionMarkerListImpl()) {}
DocumentMarker* CreateMarker(unsigned start_offset, unsigned end_offset) {
return new ActiveSuggestionMarker(
start_offset, end_offset, Color::kTransparent,
ui::mojom::ImeTextSpanThickness::kThin, Color::kBlack);
}
Persistent<ActiveSuggestionMarkerListImpl> marker_list_;
};
// ActiveSuggestionMarkerListImpl shouldn't merge markers with touching
// endpoints
TEST_F(ActiveSuggestionMarkerListImplTest, Add) {
EXPECT_EQ(0u, marker_list_->GetMarkers().size());
marker_list_->Add(CreateMarker(0, 1));
marker_list_->Add(CreateMarker(1, 2));
EXPECT_EQ(2u, marker_list_->GetMarkers().size());
EXPECT_EQ(0u, marker_list_->GetMarkers()[0]->StartOffset());
EXPECT_EQ(1u, marker_list_->GetMarkers()[0]->EndOffset());
EXPECT_EQ(1u, marker_list_->GetMarkers()[1]->StartOffset());
EXPECT_EQ(2u, marker_list_->GetMarkers()[1]->EndOffset());
}
} // namespace blink
| null | null | null | null | 32,456 |
36,363 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 201,358 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* RackMac vu-meter driver
*
* (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
* <benh@kernel.crashing.org>
*
* Released under the term of the GNU GPL v2.
*
* Support the CPU-meter LEDs of the Xserve G5
*
* TODO: Implement PWM to do variable intensity and provide userland
* interface for fun. Also, the CPU-meter could be made nicer by being
* a bit less "immediate" but giving instead a more average load over
* time. Patches welcome :-)
*
*/
#undef DEBUG
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/kernel_stat.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/pmac_feature.h>
#include <asm/dbdma.h>
#include <asm/macio.h>
#include <asm/keylargo.h>
/* Number of samples in a sample buffer */
#define SAMPLE_COUNT 256
/* CPU meter sampling rate in ms */
#define CPU_SAMPLING_RATE 250
struct rackmeter_dma {
struct dbdma_cmd cmd[4] ____cacheline_aligned;
u32 mark ____cacheline_aligned;
u32 buf1[SAMPLE_COUNT] ____cacheline_aligned;
u32 buf2[SAMPLE_COUNT] ____cacheline_aligned;
} ____cacheline_aligned;
struct rackmeter_cpu {
struct delayed_work sniffer;
struct rackmeter *rm;
u64 prev_wall;
u64 prev_idle;
int zero;
} ____cacheline_aligned;
struct rackmeter {
struct macio_dev *mdev;
unsigned int irq;
struct device_node *i2s;
u8 *ubuf;
struct dbdma_regs __iomem *dma_regs;
void __iomem *i2s_regs;
dma_addr_t dma_buf_p;
struct rackmeter_dma *dma_buf_v;
int stale_irq;
struct rackmeter_cpu cpu[2];
int paused;
struct mutex sem;
};
/* To be set as a tunable */
static int rackmeter_ignore_nice;
/* This GPIO is whacked by the OS X driver when initializing */
#define RACKMETER_MAGIC_GPIO 0x78
/* This is copied from cpufreq_ondemand, maybe we should put it in
* a common header somewhere
*/
static inline u64 get_cpu_idle_time(unsigned int cpu)
{
u64 retval;
retval = kcpustat_cpu(cpu).cpustat[CPUTIME_IDLE] +
kcpustat_cpu(cpu).cpustat[CPUTIME_IOWAIT];
if (rackmeter_ignore_nice)
retval += kcpustat_cpu(cpu).cpustat[CPUTIME_NICE];
return retval;
}
static void rackmeter_setup_i2s(struct rackmeter *rm)
{
struct macio_chip *macio = rm->mdev->bus->chip;
/* First whack magic GPIO */
pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, RACKMETER_MAGIC_GPIO, 5);
/* Call feature code to enable the sound channel and the proper
* clock sources
*/
pmac_call_feature(PMAC_FTR_SOUND_CHIP_ENABLE, rm->i2s, 0, 1);
/* Power i2s and stop i2s clock. We whack MacIO FCRs directly for now.
* This is a bit racy, thus we should add new platform functions to
* handle that. snd-aoa needs that too
*/
MACIO_BIS(KEYLARGO_FCR1, KL1_I2S0_ENABLE);
MACIO_BIC(KEYLARGO_FCR1, KL1_I2S0_CLK_ENABLE_BIT);
(void)MACIO_IN32(KEYLARGO_FCR1);
udelay(10);
/* Then setup i2s. For now, we use the same magic value that
* the OS X driver seems to use. We might want to play around
* with the clock divisors later
*/
out_le32(rm->i2s_regs + 0x10, 0x01fa0000);
(void)in_le32(rm->i2s_regs + 0x10);
udelay(10);
/* Fully restart i2s*/
MACIO_BIS(KEYLARGO_FCR1, KL1_I2S0_CELL_ENABLE |
KL1_I2S0_CLK_ENABLE_BIT);
(void)MACIO_IN32(KEYLARGO_FCR1);
udelay(10);
}
static void rackmeter_set_default_pattern(struct rackmeter *rm)
{
int i;
for (i = 0; i < 16; i++) {
if (i < 8)
rm->ubuf[i] = (i & 1) * 255;
else
rm->ubuf[i] = ((~i) & 1) * 255;
}
}
static void rackmeter_do_pause(struct rackmeter *rm, int pause)
{
struct rackmeter_dma *rdma = rm->dma_buf_v;
pr_debug("rackmeter: %s\n", pause ? "paused" : "started");
rm->paused = pause;
if (pause) {
DBDMA_DO_STOP(rm->dma_regs);
return;
}
memset(rdma->buf1, 0, ARRAY_SIZE(rdma->buf1));
memset(rdma->buf2, 0, ARRAY_SIZE(rdma->buf2));
rm->dma_buf_v->mark = 0;
mb();
out_le32(&rm->dma_regs->cmdptr_hi, 0);
out_le32(&rm->dma_regs->cmdptr, rm->dma_buf_p);
out_le32(&rm->dma_regs->control, (RUN << 16) | RUN);
}
static void rackmeter_setup_dbdma(struct rackmeter *rm)
{
struct rackmeter_dma *db = rm->dma_buf_v;
struct dbdma_cmd *cmd = db->cmd;
/* Make sure dbdma is reset */
DBDMA_DO_RESET(rm->dma_regs);
pr_debug("rackmeter: mark offset=0x%zx\n",
offsetof(struct rackmeter_dma, mark));
pr_debug("rackmeter: buf1 offset=0x%zx\n",
offsetof(struct rackmeter_dma, buf1));
pr_debug("rackmeter: buf2 offset=0x%zx\n",
offsetof(struct rackmeter_dma, buf2));
/* Prepare 4 dbdma commands for the 2 buffers */
memset(cmd, 0, 4 * sizeof(struct dbdma_cmd));
cmd->req_count = cpu_to_le16(4);
cmd->command = cpu_to_le16(STORE_WORD | INTR_ALWAYS | KEY_SYSTEM);
cmd->phy_addr = cpu_to_le32(rm->dma_buf_p +
offsetof(struct rackmeter_dma, mark));
cmd->cmd_dep = cpu_to_le32(0x02000000);
cmd++;
cmd->req_count = cpu_to_le16(SAMPLE_COUNT * 4);
cmd->command = cpu_to_le16(OUTPUT_MORE);
cmd->phy_addr = cpu_to_le32(rm->dma_buf_p +
offsetof(struct rackmeter_dma, buf1));
cmd++;
cmd->req_count = cpu_to_le16(4);
cmd->command = cpu_to_le16(STORE_WORD | INTR_ALWAYS | KEY_SYSTEM);
cmd->phy_addr = cpu_to_le32(rm->dma_buf_p +
offsetof(struct rackmeter_dma, mark));
cmd->cmd_dep = cpu_to_le32(0x01000000);
cmd++;
cmd->req_count = cpu_to_le16(SAMPLE_COUNT * 4);
cmd->command = cpu_to_le16(OUTPUT_MORE | BR_ALWAYS);
cmd->phy_addr = cpu_to_le32(rm->dma_buf_p +
offsetof(struct rackmeter_dma, buf2));
cmd->cmd_dep = cpu_to_le32(rm->dma_buf_p);
rackmeter_do_pause(rm, 0);
}
static void rackmeter_do_timer(struct work_struct *work)
{
struct rackmeter_cpu *rcpu =
container_of(work, struct rackmeter_cpu, sniffer.work);
struct rackmeter *rm = rcpu->rm;
unsigned int cpu = smp_processor_id();
u64 cur_nsecs, total_idle_nsecs;
u64 total_nsecs, idle_nsecs;
int i, offset, load, cumm, pause;
cur_nsecs = jiffies64_to_nsecs(get_jiffies_64());
total_nsecs = cur_nsecs - rcpu->prev_wall;
rcpu->prev_wall = cur_nsecs;
total_idle_nsecs = get_cpu_idle_time(cpu);
idle_nsecs = total_idle_nsecs - rcpu->prev_idle;
idle_nsecs = min(idle_nsecs, total_nsecs);
rcpu->prev_idle = total_idle_nsecs;
/* We do a very dumb calculation to update the LEDs for now,
* we'll do better once we have actual PWM implemented
*/
load = div64_u64(9 * (total_nsecs - idle_nsecs), total_nsecs);
offset = cpu << 3;
cumm = 0;
for (i = 0; i < 8; i++) {
u8 ub = (load > i) ? 0xff : 0;
rm->ubuf[i + offset] = ub;
cumm |= ub;
}
rcpu->zero = (cumm == 0);
/* Now check if LEDs are all 0, we can stop DMA */
pause = (rm->cpu[0].zero && rm->cpu[1].zero);
if (pause != rm->paused) {
mutex_lock(&rm->sem);
pause = (rm->cpu[0].zero && rm->cpu[1].zero);
rackmeter_do_pause(rm, pause);
mutex_unlock(&rm->sem);
}
schedule_delayed_work_on(cpu, &rcpu->sniffer,
msecs_to_jiffies(CPU_SAMPLING_RATE));
}
static void rackmeter_init_cpu_sniffer(struct rackmeter *rm)
{
unsigned int cpu;
/* This driver works only with 1 or 2 CPUs numbered 0 and 1,
* but that's really all we have on Apple Xserve. It doesn't
* play very nice with CPU hotplug neither but we don't do that
* on those machines yet
*/
rm->cpu[0].rm = rm;
INIT_DELAYED_WORK(&rm->cpu[0].sniffer, rackmeter_do_timer);
rm->cpu[1].rm = rm;
INIT_DELAYED_WORK(&rm->cpu[1].sniffer, rackmeter_do_timer);
for_each_online_cpu(cpu) {
struct rackmeter_cpu *rcpu;
if (cpu > 1)
continue;
rcpu = &rm->cpu[cpu];
rcpu->prev_idle = get_cpu_idle_time(cpu);
rcpu->prev_wall = jiffies64_to_nsecs(get_jiffies_64());
schedule_delayed_work_on(cpu, &rm->cpu[cpu].sniffer,
msecs_to_jiffies(CPU_SAMPLING_RATE));
}
}
static void rackmeter_stop_cpu_sniffer(struct rackmeter *rm)
{
cancel_delayed_work_sync(&rm->cpu[0].sniffer);
cancel_delayed_work_sync(&rm->cpu[1].sniffer);
}
static int rackmeter_setup(struct rackmeter *rm)
{
pr_debug("rackmeter: setting up i2s..\n");
rackmeter_setup_i2s(rm);
pr_debug("rackmeter: setting up default pattern..\n");
rackmeter_set_default_pattern(rm);
pr_debug("rackmeter: setting up dbdma..\n");
rackmeter_setup_dbdma(rm);
pr_debug("rackmeter: start CPU measurements..\n");
rackmeter_init_cpu_sniffer(rm);
printk(KERN_INFO "RackMeter initialized\n");
return 0;
}
/* XXX FIXME: No PWM yet, this is 0/1 */
static u32 rackmeter_calc_sample(struct rackmeter *rm, unsigned int index)
{
int led;
u32 sample = 0;
for (led = 0; led < 16; led++) {
sample >>= 1;
sample |= ((rm->ubuf[led] >= 0x80) << 15);
}
return (sample << 17) | (sample >> 15);
}
static irqreturn_t rackmeter_irq(int irq, void *arg)
{
struct rackmeter *rm = arg;
struct rackmeter_dma *db = rm->dma_buf_v;
unsigned int mark, i;
u32 *buf;
/* Flush PCI buffers with an MMIO read. Maybe we could actually
* check the status one day ... in case things go wrong, though
* this never happened to me
*/
(void)in_le32(&rm->dma_regs->status);
/* Make sure the CPU gets us in order */
rmb();
/* Read mark */
mark = db->mark;
if (mark != 1 && mark != 2) {
printk(KERN_WARNING "rackmeter: Incorrect DMA mark 0x%08x\n",
mark);
/* We allow for 3 errors like that (stale DBDMA irqs) */
if (++rm->stale_irq > 3) {
printk(KERN_ERR "rackmeter: Too many errors,"
" stopping DMA\n");
DBDMA_DO_RESET(rm->dma_regs);
}
return IRQ_HANDLED;
}
/* Next buffer we need to fill is mark value */
buf = mark == 1 ? db->buf1 : db->buf2;
/* Fill it now. This routine converts the 8 bits depth sample array
* into the PWM bitmap for each LED.
*/
for (i = 0; i < SAMPLE_COUNT; i++)
buf[i] = rackmeter_calc_sample(rm, i);
return IRQ_HANDLED;
}
static int rackmeter_probe(struct macio_dev* mdev,
const struct of_device_id *match)
{
struct device_node *i2s = NULL, *np = NULL;
struct rackmeter *rm = NULL;
struct resource ri2s, rdma;
int rc = -ENODEV;
pr_debug("rackmeter_probe()\n");
/* Get i2s-a node */
while ((i2s = of_get_next_child(mdev->ofdev.dev.of_node, i2s)) != NULL)
if (strcmp(i2s->name, "i2s-a") == 0)
break;
if (i2s == NULL) {
pr_debug(" i2s-a child not found\n");
goto bail;
}
/* Get lightshow or virtual sound */
while ((np = of_get_next_child(i2s, np)) != NULL) {
if (strcmp(np->name, "lightshow") == 0)
break;
if ((strcmp(np->name, "sound") == 0) &&
of_get_property(np, "virtual", NULL) != NULL)
break;
}
if (np == NULL) {
pr_debug(" lightshow or sound+virtual child not found\n");
goto bail;
}
/* Create and initialize our instance data */
rm = kzalloc(sizeof(struct rackmeter), GFP_KERNEL);
if (rm == NULL) {
printk(KERN_ERR "rackmeter: failed to allocate memory !\n");
rc = -ENOMEM;
goto bail_release;
}
rm->mdev = mdev;
rm->i2s = i2s;
mutex_init(&rm->sem);
dev_set_drvdata(&mdev->ofdev.dev, rm);
/* Check resources availability. We need at least resource 0 and 1 */
#if 0 /* Use that when i2s-a is finally an mdev per-se */
if (macio_resource_count(mdev) < 2 || macio_irq_count(mdev) < 2) {
printk(KERN_ERR
"rackmeter: found match but lacks resources: %s"
" (%d resources, %d interrupts)\n",
mdev->ofdev.node->full_name);
rc = -ENXIO;
goto bail_free;
}
if (macio_request_resources(mdev, "rackmeter")) {
printk(KERN_ERR
"rackmeter: failed to request resources: %s\n",
mdev->ofdev.node->full_name);
rc = -EBUSY;
goto bail_free;
}
rm->irq = macio_irq(mdev, 1);
#else
rm->irq = irq_of_parse_and_map(i2s, 1);
if (!rm->irq ||
of_address_to_resource(i2s, 0, &ri2s) ||
of_address_to_resource(i2s, 1, &rdma)) {
printk(KERN_ERR
"rackmeter: found match but lacks resources: %s",
mdev->ofdev.dev.of_node->full_name);
rc = -ENXIO;
goto bail_free;
}
#endif
pr_debug(" i2s @0x%08x\n", (unsigned int)ri2s.start);
pr_debug(" dma @0x%08x\n", (unsigned int)rdma.start);
pr_debug(" irq %d\n", rm->irq);
rm->ubuf = (u8 *)__get_free_page(GFP_KERNEL);
if (rm->ubuf == NULL) {
printk(KERN_ERR
"rackmeter: failed to allocate samples page !\n");
rc = -ENOMEM;
goto bail_release;
}
rm->dma_buf_v = dma_alloc_coherent(&macio_get_pci_dev(mdev)->dev,
sizeof(struct rackmeter_dma),
&rm->dma_buf_p, GFP_KERNEL);
if (rm->dma_buf_v == NULL) {
printk(KERN_ERR
"rackmeter: failed to allocate dma buffer !\n");
rc = -ENOMEM;
goto bail_free_samples;
}
#if 0
rm->i2s_regs = ioremap(macio_resource_start(mdev, 0), 0x1000);
#else
rm->i2s_regs = ioremap(ri2s.start, 0x1000);
#endif
if (rm->i2s_regs == NULL) {
printk(KERN_ERR
"rackmeter: failed to map i2s registers !\n");
rc = -ENXIO;
goto bail_free_dma;
}
#if 0
rm->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x100);
#else
rm->dma_regs = ioremap(rdma.start, 0x100);
#endif
if (rm->dma_regs == NULL) {
printk(KERN_ERR
"rackmeter: failed to map dma registers !\n");
rc = -ENXIO;
goto bail_unmap_i2s;
}
rc = rackmeter_setup(rm);
if (rc) {
printk(KERN_ERR
"rackmeter: failed to initialize !\n");
rc = -ENXIO;
goto bail_unmap_dma;
}
rc = request_irq(rm->irq, rackmeter_irq, 0, "rackmeter", rm);
if (rc != 0) {
printk(KERN_ERR
"rackmeter: failed to request interrupt !\n");
goto bail_stop_dma;
}
of_node_put(np);
return 0;
bail_stop_dma:
DBDMA_DO_RESET(rm->dma_regs);
bail_unmap_dma:
iounmap(rm->dma_regs);
bail_unmap_i2s:
iounmap(rm->i2s_regs);
bail_free_dma:
dma_free_coherent(&macio_get_pci_dev(mdev)->dev,
sizeof(struct rackmeter_dma),
rm->dma_buf_v, rm->dma_buf_p);
bail_free_samples:
free_page((unsigned long)rm->ubuf);
bail_release:
#if 0
macio_release_resources(mdev);
#endif
bail_free:
kfree(rm);
bail:
of_node_put(i2s);
of_node_put(np);
dev_set_drvdata(&mdev->ofdev.dev, NULL);
return rc;
}
static int rackmeter_remove(struct macio_dev* mdev)
{
struct rackmeter *rm = dev_get_drvdata(&mdev->ofdev.dev);
/* Stop CPU sniffer timer & work queues */
rackmeter_stop_cpu_sniffer(rm);
/* Clear reference to private data */
dev_set_drvdata(&mdev->ofdev.dev, NULL);
/* Stop/reset dbdma */
DBDMA_DO_RESET(rm->dma_regs);
/* Release the IRQ */
free_irq(rm->irq, rm);
/* Unmap registers */
iounmap(rm->dma_regs);
iounmap(rm->i2s_regs);
/* Free DMA */
dma_free_coherent(&macio_get_pci_dev(mdev)->dev,
sizeof(struct rackmeter_dma),
rm->dma_buf_v, rm->dma_buf_p);
/* Free samples */
free_page((unsigned long)rm->ubuf);
#if 0
/* Release resources */
macio_release_resources(mdev);
#endif
/* Get rid of me */
kfree(rm);
return 0;
}
static int rackmeter_shutdown(struct macio_dev* mdev)
{
struct rackmeter *rm = dev_get_drvdata(&mdev->ofdev.dev);
if (rm == NULL)
return -ENODEV;
/* Stop CPU sniffer timer & work queues */
rackmeter_stop_cpu_sniffer(rm);
/* Stop/reset dbdma */
DBDMA_DO_RESET(rm->dma_regs);
return 0;
}
static struct of_device_id rackmeter_match[] = {
{ .name = "i2s" },
{ }
};
MODULE_DEVICE_TABLE(of, rackmeter_match);
static struct macio_driver rackmeter_driver = {
.driver = {
.name = "rackmeter",
.owner = THIS_MODULE,
.of_match_table = rackmeter_match,
},
.probe = rackmeter_probe,
.remove = rackmeter_remove,
.shutdown = rackmeter_shutdown,
};
static int __init rackmeter_init(void)
{
pr_debug("rackmeter_init()\n");
return macio_register_driver(&rackmeter_driver);
}
static void __exit rackmeter_exit(void)
{
pr_debug("rackmeter_exit()\n");
macio_unregister_driver(&rackmeter_driver);
}
module_init(rackmeter_init);
module_exit(rackmeter_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
MODULE_DESCRIPTION("RackMeter: Support vu-meter on XServe front panel");
| null | null | null | null | 109,705 |
54,464 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 54,464 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2013 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef CHROME_TEST_BASE_TESTING_BROWSER_PROCESS_PLATFORM_PART_H_
#define CHROME_TEST_BASE_TESTING_BROWSER_PROCESS_PLATFORM_PART_H_
#include "base/macros.h"
#include "chrome/browser/browser_process_platform_part.h"
// A TestingBrowserProcessPlatformPart is essentially a
// BrowserProcessPlatformPart except it doesn't have an OomPriorityManager on
// Chrome OS.
class TestingBrowserProcessPlatformPart : public BrowserProcessPlatformPart {
public:
TestingBrowserProcessPlatformPart();
~TestingBrowserProcessPlatformPart() override;
private:
DISALLOW_COPY_AND_ASSIGN(TestingBrowserProcessPlatformPart);
};
#endif // CHROME_TEST_BASE_TESTING_BROWSER_PROCESS_PLATFORM_PART_H_
| null | null | null | null | 51,327 |
858 | 13,28,29,30,31,32,33,34,35,36,37,98,99,100 | train_val | ea3d7209ca01da209cda6f0dea8be9cc4b7a933b | 165,853 | linux | 1 | https://github.com/torvalds/linux | 2015-12-07 14:28:03-05:00 | static long ext4_zero_range(struct file *file, loff_t offset,
loff_t len, int mode)
{
struct inode *inode = file_inode(file);
handle_t *handle = NULL;
unsigned int max_blocks;
loff_t new_size = 0;
int ret = 0;
int flags;
int credits;
int partial_begin, partial_end;
loff_t start, end;
ext4_lblk_t lblk;
struct address_space *mapping = inode->i_mapping;
unsigned int blkbits = inode->i_blkbits;
trace_ext4_zero_range(inode, offset, len, mode);
if (!S_ISREG(inode->i_mode))
return -EINVAL;
/* Call ext4_force_commit to flush all data in case of data=journal. */
if (ext4_should_journal_data(inode)) {
ret = ext4_force_commit(inode->i_sb);
if (ret)
return ret;
}
/*
* Write out all dirty pages to avoid race conditions
* Then release them.
*
if (mapping->nrpages && mapping_tagged(mapping, PAGECACHE_TAG_DIRTY)) {
ret = filemap_write_and_wait_range(mapping, offset,
offset + len - 1);
if (ret)
return ret;
}
/*
* Round up offset. This is not fallocate, we neet to zero out
* blocks, so convert interior block aligned part of the range to
* unwritten and possibly manually zero out unaligned parts of the
* range.
*/
start = round_up(offset, 1 << blkbits);
end = round_down((offset + len), 1 << blkbits);
if (start < offset || end > offset + len)
return -EINVAL;
partial_begin = offset & ((1 << blkbits) - 1);
partial_end = (offset + len) & ((1 << blkbits) - 1);
lblk = start >> blkbits;
max_blocks = (end >> blkbits);
if (max_blocks < lblk)
max_blocks = 0;
else
max_blocks -= lblk;
mutex_lock(&inode->i_mutex);
/*
* Indirect files do not support unwritten extnets
*/
if (!(ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS))) {
ret = -EOPNOTSUPP;
goto out_mutex;
}
if (!(mode & FALLOC_FL_KEEP_SIZE) &&
offset + len > i_size_read(inode)) {
new_size = offset + len;
ret = inode_newsize_ok(inode, new_size);
if (ret)
goto out_mutex;
}
flags = EXT4_GET_BLOCKS_CREATE_UNWRIT_EXT;
if (mode & FALLOC_FL_KEEP_SIZE)
flags |= EXT4_GET_BLOCKS_KEEP_SIZE;
/* Preallocate the range including the unaligned edges */
if (partial_begin || partial_end) {
ret = ext4_alloc_file_blocks(file,
round_down(offset, 1 << blkbits) >> blkbits,
(round_up((offset + len), 1 << blkbits) -
round_down(offset, 1 << blkbits)) >> blkbits,
new_size, flags, mode);
if (ret)
goto out_mutex;
}
/* Zero range excluding the unaligned edges */
if (max_blocks > 0) {
flags |= (EXT4_GET_BLOCKS_CONVERT_UNWRITTEN |
EXT4_EX_NOCACHE);
/* Now release the pages and zero block aligned part of pages*
truncate_pagecache_range(inode, start, end - 1);
inode->i_mtime = inode->i_ctime = ext4_current_time(inode);
/* Wait all existing dio workers, newcomers will block on i_mutex */
ext4_inode_block_unlocked_dio(inode);
inode_dio_wait(inode);
ret = ext4_alloc_file_blocks(file, lblk, max_blocks, new_size,
flags, mode);
if (ret)
goto out_dio;
}
if (!partial_begin && !partial_end)
goto out_dio;
/*
* In worst case we have to writeout two nonadjacent unwritten
* blocks and update the inode
*/
credits = (2 * ext4_ext_index_trans_blocks(inode, 2)) + 1;
if (ext4_should_journal_data(inode))
credits += 2;
handle = ext4_journal_start(inode, EXT4_HT_MISC, credits);
if (IS_ERR(handle)) {
ret = PTR_ERR(handle);
ext4_std_error(inode->i_sb, ret);
goto out_dio;
}
inode->i_mtime = inode->i_ctime = ext4_current_time(inode);
if (new_size) {
ext4_update_inode_size(inode, new_size);
} else {
/*
* Mark that we allocate beyond EOF so the subsequent truncate
* can proceed even if the new size is the same as i_size.
*/
if ((offset + len) > i_size_read(inode))
ext4_set_inode_flag(inode, EXT4_INODE_EOFBLOCKS);
}
ext4_mark_inode_dirty(handle, inode);
/* Zero out partial block at the edges of the range */
ret = ext4_zero_partial_blocks(handle, inode, offset, len);
if (file->f_flags & O_SYNC)
ext4_handle_sync(handle);
ext4_journal_stop(handle);
out_dio:
ext4_inode_resume_unlocked_dio(inode);
out_mutex:
mutex_unlock(&inode->i_mutex);
return ret;
}
| CVE-2015-8839 | CWE-362 | https://github.com/torvalds/linux/commit/ea3d7209ca01da209cda6f0dea8be9cc4b7a933b | Medium | 3,747 |
13,365 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 13,365 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2013 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "components/ntp_tiles/most_visited_sites.h"
#include <algorithm>
#include <iterator>
#include <utility>
#include "base/bind.h"
#include "base/callback.h"
#include "base/feature_list.h"
#include "base/metrics/user_metrics.h"
#include "base/strings/string_util.h"
#include "base/strings/utf_string_conversions.h"
#include "components/history/core/browser/top_sites.h"
#include "components/ntp_tiles/constants.h"
#include "components/ntp_tiles/icon_cacher.h"
#include "components/ntp_tiles/pref_names.h"
#include "components/ntp_tiles/switches.h"
#include "components/pref_registry/pref_registry_syncable.h"
#include "components/prefs/pref_service.h"
using history::TopSites;
using suggestions::ChromeSuggestion;
using suggestions::SuggestionsProfile;
using suggestions::SuggestionsService;
namespace ntp_tiles {
namespace {
const base::Feature kDisplaySuggestionsServiceTiles{
"DisplaySuggestionsServiceTiles", base::FEATURE_ENABLED_BY_DEFAULT};
// URL host prefixes. Hosts with these prefixes often redirect to each other, or
// have the same content.
// Popular sites are excluded if the user has visited a page whose host only
// differs by one of these prefixes. Even if the URL does not point to the exact
// same page, the user will have a personalized suggestion that is more likely
// to be of use for them.
// A cleaner way could be checking the history for redirects but this requires
// the page to be visited on the device.
const char* kKnownGenericPagePrefixes[] = {
"m.", "mobile.", // Common prefixes among popular sites.
"edition.", // Used among news papers (CNN, Independent, ...)
"www.", // Usually no-www domains redirect to www or vice-versa.
// The following entry MUST REMAIN LAST as it is prefix of every string!
""}; // The no-www domain matches domains on same level .
// Determine whether we need any tiles from PopularSites to fill up a grid of
// |num_tiles| tiles. If exploration sections are used, we need popular sites
// regardless of how many tiles we already have.
bool NeedPopularSites(const PrefService* prefs, int num_tiles) {
return base::FeatureList::IsEnabled(kSiteExplorationUiFeature) ||
prefs->GetInteger(prefs::kNumPersonalTiles) < num_tiles;
}
bool AreURLsEquivalent(const GURL& url1, const GURL& url2) {
return url1.host_piece() == url2.host_piece() &&
url1.path_piece() == url2.path_piece();
}
bool HasHomeTile(const NTPTilesVector& tiles) {
for (const auto& tile : tiles) {
if (tile.source == TileSource::HOMEPAGE) {
return true;
}
}
return false;
}
std::string StripFirstGenericPrefix(const std::string& host) {
for (const char* prefix : kKnownGenericPagePrefixes) {
if (base::StartsWith(host, prefix, base::CompareCase::INSENSITIVE_ASCII)) {
return std::string(
base::TrimString(host, prefix, base::TrimPositions::TRIM_LEADING));
}
}
return host;
}
bool ShouldShowPopularSites() {
return base::FeatureList::IsEnabled(kUsePopularSitesSuggestions);
}
} // namespace
MostVisitedSites::MostVisitedSites(
PrefService* prefs,
scoped_refptr<history::TopSites> top_sites,
SuggestionsService* suggestions,
std::unique_ptr<PopularSites> popular_sites,
std::unique_ptr<IconCacher> icon_cacher,
std::unique_ptr<MostVisitedSitesSupervisor> supervisor)
: prefs_(prefs),
top_sites_(top_sites),
suggestions_service_(suggestions),
popular_sites_(std::move(popular_sites)),
icon_cacher_(std::move(icon_cacher)),
supervisor_(std::move(supervisor)),
observer_(nullptr),
num_sites_(0u),
top_sites_observer_(this),
mv_source_(TileSource::TOP_SITES),
top_sites_weak_ptr_factory_(this) {
DCHECK(prefs_);
// top_sites_ can be null in tests.
// TODO(sfiera): have iOS use a dummy TopSites in its tests.
DCHECK(suggestions_service_);
if (supervisor_)
supervisor_->SetObserver(this);
}
MostVisitedSites::~MostVisitedSites() {
if (supervisor_)
supervisor_->SetObserver(nullptr);
}
// static
bool MostVisitedSites::IsHostOrMobilePageKnown(
const std::set<std::string>& hosts_to_skip,
const std::string& host) {
std::string no_prefix_host = StripFirstGenericPrefix(host);
for (const char* prefix : kKnownGenericPagePrefixes) {
if (hosts_to_skip.count(prefix + no_prefix_host) ||
hosts_to_skip.count(prefix + host)) {
return true;
}
}
return false;
}
bool MostVisitedSites::DoesSourceExist(TileSource source) const {
switch (source) {
case TileSource::TOP_SITES:
return top_sites_ != nullptr;
case TileSource::SUGGESTIONS_SERVICE:
return suggestions_service_ != nullptr;
case TileSource::POPULAR_BAKED_IN:
case TileSource::POPULAR:
return popular_sites_ != nullptr;
case TileSource::WHITELIST:
return supervisor_ != nullptr;
case TileSource::HOMEPAGE:
return home_page_client_ != nullptr;
}
NOTREACHED();
return false;
}
void MostVisitedSites::SetHomePageClient(
std::unique_ptr<HomePageClient> client) {
DCHECK(client);
home_page_client_ = std::move(client);
}
void MostVisitedSites::SetMostVisitedURLsObserver(Observer* observer,
size_t num_sites) {
DCHECK(observer);
observer_ = observer;
num_sites_ = num_sites;
// The order for this condition is important, ShouldShowPopularSites() should
// always be called last to keep metrics as relevant as possible.
if (popular_sites_ && NeedPopularSites(prefs_, num_sites_) &&
ShouldShowPopularSites()) {
popular_sites_->MaybeStartFetch(
false, base::Bind(&MostVisitedSites::OnPopularSitesDownloaded,
base::Unretained(this)));
}
if (top_sites_) {
// Register as TopSitesObserver so that we can update ourselves when the
// TopSites changes.
top_sites_observer_.Add(top_sites_.get());
}
suggestions_subscription_ = suggestions_service_->AddCallback(base::Bind(
&MostVisitedSites::OnSuggestionsProfileChanged, base::Unretained(this)));
// Immediately build the current set of tiles, getting suggestions from the
// SuggestionsService's cache or, if that is empty, sites from TopSites.
BuildCurrentTiles();
// Also start a request for fresh suggestions.
Refresh();
}
void MostVisitedSites::Refresh() {
if (top_sites_) {
// TopSites updates itself after a delay. To ensure up-to-date results,
// force an update now.
// TODO(mastiz): Is seems unnecessary to refresh TopSites if we will end up
// using server-side suggestions.
top_sites_->SyncWithHistory();
}
suggestions_service_->FetchSuggestionsData();
}
void MostVisitedSites::OnHomePageStateChanged() {
BuildCurrentTiles();
}
void MostVisitedSites::AddOrRemoveBlacklistedUrl(const GURL& url,
bool add_url) {
if (add_url) {
base::RecordAction(base::UserMetricsAction("Suggestions.Site.Removed"));
} else {
base::RecordAction(
base::UserMetricsAction("Suggestions.Site.RemovalUndone"));
}
if (top_sites_) {
// Always blacklist in the local TopSites.
if (add_url)
top_sites_->AddBlacklistedURL(url);
else
top_sites_->RemoveBlacklistedURL(url);
}
// Only blacklist in the server-side suggestions service if it's active.
if (mv_source_ == TileSource::SUGGESTIONS_SERVICE) {
if (add_url)
suggestions_service_->BlacklistURL(url);
else
suggestions_service_->UndoBlacklistURL(url);
}
}
void MostVisitedSites::ClearBlacklistedUrls() {
if (top_sites_) {
// Always update the blacklist in the local TopSites.
top_sites_->ClearBlacklistedURLs();
}
// Only update the server-side blacklist if it's active.
if (mv_source_ == TileSource::SUGGESTIONS_SERVICE) {
suggestions_service_->ClearBlacklist();
}
}
void MostVisitedSites::OnBlockedSitesChanged() {
BuildCurrentTiles();
}
// static
void MostVisitedSites::RegisterProfilePrefs(
user_prefs::PrefRegistrySyncable* registry) {
registry->RegisterIntegerPref(prefs::kNumPersonalTiles, 0);
}
void MostVisitedSites::InitiateTopSitesQuery() {
if (!top_sites_)
return;
if (top_sites_weak_ptr_factory_.HasWeakPtrs())
return; // Ongoing query.
top_sites_->GetMostVisitedURLs(
base::Bind(&MostVisitedSites::OnMostVisitedURLsAvailable,
top_sites_weak_ptr_factory_.GetWeakPtr()),
false);
}
base::FilePath MostVisitedSites::GetWhitelistLargeIconPath(const GURL& url) {
if (supervisor_) {
for (const auto& whitelist : supervisor_->GetWhitelists()) {
if (AreURLsEquivalent(whitelist.entry_point, url))
return whitelist.large_icon_path;
}
}
return base::FilePath();
}
void MostVisitedSites::OnMostVisitedURLsAvailable(
const history::MostVisitedURLList& visited_list) {
// Ignore the event if tiles provided by the Suggestions Service, which take
// precedence.
if (mv_source_ == TileSource::SUGGESTIONS_SERVICE) {
return;
}
NTPTilesVector tiles;
size_t num_tiles = std::min(visited_list.size(), num_sites_);
for (size_t i = 0; i < num_tiles; ++i) {
const history::MostVisitedURL& visited = visited_list[i];
if (visited.url.is_empty())
break; // This is the signal that there are no more real visited sites.
if (supervisor_ && supervisor_->IsBlocked(visited.url))
continue;
NTPTile tile;
tile.title = visited.title;
tile.url = visited.url;
tile.source = TileSource::TOP_SITES;
tile.whitelist_icon_path = GetWhitelistLargeIconPath(visited.url);
// MostVisitedURL.title is either the title or the URL which is treated
// exactly as the title. Differentiating here is not worth the overhead.
tile.title_source = TileTitleSource::TITLE_TAG;
// TODO(crbug.com/773278): Populate |data_generation_time| here in order to
// log UMA metrics of age.
tiles.push_back(std::move(tile));
}
mv_source_ = TileSource::TOP_SITES;
InitiateNotificationForNewTiles(std::move(tiles));
}
void MostVisitedSites::OnSuggestionsProfileChanged(
const SuggestionsProfile& suggestions_profile) {
if (suggestions_profile.suggestions_size() == 0 &&
mv_source_ != TileSource::SUGGESTIONS_SERVICE) {
return;
}
BuildCurrentTilesGivenSuggestionsProfile(suggestions_profile);
}
void MostVisitedSites::BuildCurrentTiles() {
BuildCurrentTilesGivenSuggestionsProfile(
suggestions_service_->GetSuggestionsDataFromCache().value_or(
SuggestionsProfile()));
}
void MostVisitedSites::BuildCurrentTilesGivenSuggestionsProfile(
const suggestions::SuggestionsProfile& suggestions_profile) {
size_t num_tiles = suggestions_profile.suggestions_size();
// With no server suggestions, fall back to local TopSites.
if (num_tiles == 0 ||
!base::FeatureList::IsEnabled(kDisplaySuggestionsServiceTiles)) {
mv_source_ = TileSource::TOP_SITES;
InitiateTopSitesQuery();
return;
}
if (num_sites_ < num_tiles)
num_tiles = num_sites_;
const base::Time profile_timestamp =
base::Time::UnixEpoch() +
base::TimeDelta::FromMicroseconds(suggestions_profile.timestamp());
NTPTilesVector tiles;
for (size_t i = 0; i < num_tiles; ++i) {
const ChromeSuggestion& suggestion_pb = suggestions_profile.suggestions(i);
GURL url(suggestion_pb.url());
if (supervisor_ && supervisor_->IsBlocked(url))
continue;
NTPTile tile;
tile.title = base::UTF8ToUTF16(suggestion_pb.title());
tile.url = url;
tile.source = TileSource::SUGGESTIONS_SERVICE;
// The title is an aggregation of multiple history entries of one site.
tile.title_source = TileTitleSource::INFERRED;
tile.whitelist_icon_path = GetWhitelistLargeIconPath(url);
tile.thumbnail_url = GURL(suggestion_pb.thumbnail());
tile.favicon_url = GURL(suggestion_pb.favicon_url());
tile.data_generation_time = profile_timestamp;
icon_cacher_->StartFetchMostLikely(
url, base::Bind(&MostVisitedSites::OnIconMadeAvailable,
base::Unretained(this), url));
tiles.push_back(std::move(tile));
}
mv_source_ = TileSource::SUGGESTIONS_SERVICE;
InitiateNotificationForNewTiles(std::move(tiles));
}
NTPTilesVector MostVisitedSites::CreateWhitelistEntryPointTiles(
const std::set<std::string>& used_hosts,
size_t num_actual_tiles) {
if (!supervisor_) {
return NTPTilesVector();
}
NTPTilesVector whitelist_tiles;
for (const auto& whitelist : supervisor_->GetWhitelists()) {
if (whitelist_tiles.size() + num_actual_tiles >= num_sites_)
break;
// Skip blacklisted sites.
if (top_sites_ && top_sites_->IsBlacklisted(whitelist.entry_point))
continue;
// Skip tiles already present.
if (used_hosts.find(whitelist.entry_point.host()) != used_hosts.end())
continue;
// Skip whitelist entry points that are manually blocked.
if (supervisor_->IsBlocked(whitelist.entry_point))
continue;
NTPTile tile;
tile.title = whitelist.title;
tile.url = whitelist.entry_point;
tile.source = TileSource::WHITELIST;
// User-set. Might be the title but we cannot be sure.
tile.title_source = TileTitleSource::UNKNOWN;
tile.whitelist_icon_path = whitelist.large_icon_path;
whitelist_tiles.push_back(std::move(tile));
}
return whitelist_tiles;
}
std::map<SectionType, NTPTilesVector>
MostVisitedSites::CreatePopularSitesSections(
const std::set<std::string>& used_hosts,
size_t num_actual_tiles) {
std::map<SectionType, NTPTilesVector> sections = {
std::make_pair(SectionType::PERSONALIZED, NTPTilesVector())};
// For child accounts popular sites tiles will not be added.
if (supervisor_ && supervisor_->IsChildProfile()) {
return sections;
}
if (!popular_sites_ || !ShouldShowPopularSites()) {
return sections;
}
const std::set<std::string> no_hosts;
for (const auto& section_type_and_sites : popular_sites()->sections()) {
SectionType type = section_type_and_sites.first;
const PopularSites::SitesVector& sites = section_type_and_sites.second;
if (type == SectionType::PERSONALIZED) {
size_t num_required_tiles = num_sites_ - num_actual_tiles;
sections[type] =
CreatePopularSitesTiles(/*popular_sites=*/sites,
/*hosts_to_skip=*/used_hosts,
/*num_max_tiles=*/num_required_tiles);
} else {
sections[type] = CreatePopularSitesTiles(/*popular_sites=*/sites,
/*hosts_to_skip=*/no_hosts,
/*num_max_tiles=*/num_sites_);
}
}
return sections;
}
NTPTilesVector MostVisitedSites::CreatePopularSitesTiles(
const PopularSites::SitesVector& sites_vector,
const std::set<std::string>& hosts_to_skip,
size_t num_max_tiles) {
// Collect non-blacklisted popular suggestions, skipping those already present
// in the personal suggestions.
NTPTilesVector popular_sites_tiles;
for (const PopularSites::Site& popular_site : sites_vector) {
if (popular_sites_tiles.size() >= num_max_tiles) {
break;
}
// Skip blacklisted sites.
if (top_sites_ && top_sites_->IsBlacklisted(popular_site.url))
continue;
const std::string& host = popular_site.url.host();
if (IsHostOrMobilePageKnown(hosts_to_skip, host)) {
continue;
}
NTPTile tile;
tile.title = popular_site.title;
tile.url = GURL(popular_site.url);
tile.title_source = popular_site.title_source;
tile.source = popular_site.baked_in ? TileSource::POPULAR_BAKED_IN
: TileSource::POPULAR;
popular_sites_tiles.push_back(std::move(tile));
base::Closure icon_available =
base::Bind(&MostVisitedSites::OnIconMadeAvailable,
base::Unretained(this), popular_site.url);
icon_cacher_->StartFetchPopularSites(popular_site, icon_available,
icon_available);
}
return popular_sites_tiles;
}
void MostVisitedSites::OnHomePageTitleDetermined(
NTPTilesVector tiles,
const base::Optional<base::string16>& title) {
if (!title.has_value()) {
return; // If there is no title, the most recent tile was already sent out.
}
SaveTilesAndNotify(InsertHomeTile(std::move(tiles), title.value()));
}
NTPTilesVector MostVisitedSites::InsertHomeTile(
NTPTilesVector tiles,
const base::string16& title) const {
DCHECK(home_page_client_);
DCHECK_GT(num_sites_, 0u);
const GURL& home_page_url = home_page_client_->GetHomePageUrl();
NTPTilesVector new_tiles;
bool home_tile_added = false;
for (auto& tile : tiles) {
if (new_tiles.size() >= num_sites_) {
break;
}
// TODO(fhorschig): Introduce a more sophisticated deduplication.
if (tile.url.host() == home_page_url.host()) {
tile.source = TileSource::HOMEPAGE;
home_tile_added = true;
}
new_tiles.push_back(std::move(tile));
}
// Add the home page tile if there are less than 4 tiles
// and none of them is the home page (and there is space left).
if (!home_tile_added) {
// Make room for the home page tile.
if (new_tiles.size() >= num_sites_) {
new_tiles.pop_back();
}
NTPTile home_tile;
home_tile.url = home_page_url;
home_tile.title = title;
home_tile.source = TileSource::HOMEPAGE;
home_tile.title_source = TileTitleSource::TITLE_TAG; // From history.
new_tiles.push_back(std::move(home_tile));
}
return new_tiles;
}
void MostVisitedSites::InitiateNotificationForNewTiles(
NTPTilesVector new_tiles) {
if (ShouldAddHomeTile() && !HasHomeTile(new_tiles)) {
home_page_client_->QueryHomePageTitle(
base::BindOnce(&MostVisitedSites::OnHomePageTitleDetermined,
base::Unretained(this), new_tiles));
// Don't wait for the homepage title from history but immediately serve a
// copy of new tiles.
new_tiles = InsertHomeTile(std::move(new_tiles), base::string16());
}
SaveTilesAndNotify(std::move(new_tiles));
}
void MostVisitedSites::SaveTilesAndNotify(NTPTilesVector personal_tiles) {
std::set<std::string> used_hosts;
size_t num_actual_tiles = 0u;
AddToHostsAndTotalCount(personal_tiles, &used_hosts, &num_actual_tiles);
NTPTilesVector whitelist_tiles =
CreateWhitelistEntryPointTiles(used_hosts, num_actual_tiles);
AddToHostsAndTotalCount(whitelist_tiles, &used_hosts, &num_actual_tiles);
std::map<SectionType, NTPTilesVector> sections =
CreatePopularSitesSections(used_hosts, num_actual_tiles);
AddToHostsAndTotalCount(sections[SectionType::PERSONALIZED], &used_hosts,
&num_actual_tiles);
NTPTilesVector new_tiles =
MergeTiles(std::move(personal_tiles), std::move(whitelist_tiles),
std::move(sections[SectionType::PERSONALIZED]));
if (current_tiles_.has_value() && (*current_tiles_ == new_tiles)) {
return;
}
current_tiles_.emplace(std::move(new_tiles));
DCHECK_EQ(num_actual_tiles, current_tiles_->size());
int num_personal_tiles = 0;
for (const auto& tile : *current_tiles_) {
if (tile.source != TileSource::POPULAR &&
tile.source != TileSource::POPULAR_BAKED_IN) {
num_personal_tiles++;
}
}
prefs_->SetInteger(prefs::kNumPersonalTiles, num_personal_tiles);
if (!observer_)
return;
sections[SectionType::PERSONALIZED] = *current_tiles_;
observer_->OnURLsAvailable(sections);
}
// static
NTPTilesVector MostVisitedSites::MergeTiles(NTPTilesVector personal_tiles,
NTPTilesVector whitelist_tiles,
NTPTilesVector popular_tiles) {
NTPTilesVector merged_tiles;
std::move(personal_tiles.begin(), personal_tiles.end(),
std::back_inserter(merged_tiles));
std::move(whitelist_tiles.begin(), whitelist_tiles.end(),
std::back_inserter(merged_tiles));
std::move(popular_tiles.begin(), popular_tiles.end(),
std::back_inserter(merged_tiles));
return merged_tiles;
}
void MostVisitedSites::OnPopularSitesDownloaded(bool success) {
if (!success) {
LOG(WARNING) << "Download of popular sites failed";
return;
}
for (const auto& section : popular_sites_->sections()) {
for (const PopularSites::Site& site : section.second) {
// Ignore callback; these icons will be seen on the *next* NTP.
icon_cacher_->StartFetchPopularSites(site, base::Closure(),
base::Closure());
}
}
}
void MostVisitedSites::OnIconMadeAvailable(const GURL& site_url) {
observer_->OnIconMadeAvailable(site_url);
}
void MostVisitedSites::TopSitesLoaded(TopSites* top_sites) {}
void MostVisitedSites::TopSitesChanged(TopSites* top_sites,
ChangeReason change_reason) {
if (mv_source_ == TileSource::TOP_SITES) {
// The displayed tiles are invalidated.
InitiateTopSitesQuery();
}
}
bool MostVisitedSites::ShouldAddHomeTile() const {
return num_sites_ > 0u &&
home_page_client_ && // No platform-specific implementation - no tile.
home_page_client_->IsHomePageEnabled() &&
!home_page_client_->IsNewTabPageUsedAsHomePage() &&
!home_page_client_->GetHomePageUrl().is_empty() &&
!(top_sites_ &&
top_sites_->IsBlacklisted(home_page_client_->GetHomePageUrl()));
}
void MostVisitedSites::AddToHostsAndTotalCount(const NTPTilesVector& new_tiles,
std::set<std::string>* hosts,
size_t* total_tile_count) const {
for (const auto& tile : new_tiles) {
hosts->insert(tile.url.host());
}
*total_tile_count += new_tiles.size();
DCHECK_LE(*total_tile_count, num_sites_);
}
} // namespace ntp_tiles
| null | null | null | null | 10,228 |
15,791 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 180,786 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2014, Imagination Technologies Ltd.
*
* EVA functions for generic code
*/
#ifndef _ASM_EVA_H
#define _ASM_EVA_H
#include <kernel-entry-init.h>
#ifdef __ASSEMBLY__
#ifdef CONFIG_EVA
/*
* EVA early init code
*
* Platforms must define their own 'platform_eva_init' macro in
* their kernel-entry-init.h header. This macro usually does the
* platform specific configuration of the segmentation registers,
* and it is normally called from assembly code.
*
*/
.macro eva_init
platform_eva_init
.endm
#else
.macro eva_init
.endm
#endif /* CONFIG_EVA */
#endif /* __ASSEMBLY__ */
#endif
| null | null | null | null | 89,133 |
8,397 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 8,397 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2006-2008 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
// See net/disk_cache/disk_cache.h for the public interface of the cache.
#ifndef NET_DISK_CACHE_BLOCKFILE_FILE_BLOCK_H_
#define NET_DISK_CACHE_BLOCKFILE_FILE_BLOCK_H_
#include <stddef.h>
namespace disk_cache {
// This interface exposes common functionality for a single block of data
// stored on a file-block, regardless of the real type or size of the block.
// Used to simplify loading / storing the block from disk.
class FileBlock {
public:
virtual ~FileBlock() {}
// Returns a pointer to the actual data.
virtual void* buffer() const = 0;
// Returns the size of the block;
virtual size_t size() const = 0;
// Returns the file offset of this block.
virtual int offset() const = 0;
};
} // namespace disk_cache
#endif // NET_DISK_CACHE_BLOCKFILE_FILE_BLOCK_H_
| null | null | null | null | 5,260 |
46,330 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 46,330 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2017 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "ash/tray_action/tray_action.h"
#include <utility>
#include "ash/lock_screen_action/lock_screen_note_display_state_handler.h"
#include "ash/tray_action/tray_action_observer.h"
#include "base/bind.h"
#include "base/callback.h"
#include "base/logging.h"
#include "ui/events/devices/input_device_manager.h"
#include "ui/events/devices/stylus_state.h"
namespace ash {
TrayAction::TrayAction(BacklightsForcedOffSetter* backlights_forced_off_setter)
: backlights_forced_off_setter_(backlights_forced_off_setter),
stylus_observer_(this) {
stylus_observer_.Add(ui::InputDeviceManager::GetInstance());
}
TrayAction::~TrayAction() = default;
void TrayAction::AddObserver(TrayActionObserver* observer) {
observers_.AddObserver(observer);
}
void TrayAction::RemoveObserver(TrayActionObserver* observer) {
observers_.RemoveObserver(observer);
}
void TrayAction::BindRequest(mojom::TrayActionRequest request) {
bindings_.AddBinding(this, std::move(request));
}
mojom::TrayActionState TrayAction::GetLockScreenNoteState() const {
if (!tray_action_client_)
return mojom::TrayActionState::kNotAvailable;
return lock_screen_note_state_;
}
bool TrayAction::IsLockScreenNoteActive() const {
return GetLockScreenNoteState() == mojom::TrayActionState::kActive;
}
void TrayAction::SetClient(mojom::TrayActionClientPtr tray_action_client,
mojom::TrayActionState lock_screen_note_state) {
mojom::TrayActionState old_lock_screen_note_state = GetLockScreenNoteState();
tray_action_client_ = std::move(tray_action_client);
if (tray_action_client_) {
// Makes sure the state is updated in case the connection is lost.
tray_action_client_.set_connection_error_handler(
base::Bind(&TrayAction::SetClient, base::Unretained(this), nullptr,
mojom::TrayActionState::kNotAvailable));
lock_screen_note_state_ = lock_screen_note_state;
lock_screen_note_display_state_handler_ =
std::make_unique<LockScreenNoteDisplayStateHandler>(
backlights_forced_off_setter_);
} else {
lock_screen_note_display_state_handler_.reset();
}
// Setting action handler value can change effective state - notify observers
// if that was the case.
if (GetLockScreenNoteState() != old_lock_screen_note_state)
NotifyLockScreenNoteStateChanged();
}
void TrayAction::UpdateLockScreenNoteState(mojom::TrayActionState state) {
if (state == lock_screen_note_state_)
return;
lock_screen_note_state_ = state;
if (lock_screen_note_state_ == mojom::TrayActionState::kNotAvailable)
lock_screen_note_display_state_handler_->Reset();
// If the client is not set, the effective state has not changed, so no need
// to notify observers of a state change.
if (tray_action_client_)
NotifyLockScreenNoteStateChanged();
}
void TrayAction::RequestNewLockScreenNote(mojom::LockScreenNoteOrigin origin) {
if (GetLockScreenNoteState() != mojom::TrayActionState::kAvailable)
return;
// An action state can be kAvailable only if |tray_action_client_| is set.
DCHECK(tray_action_client_);
tray_action_client_->RequestNewLockScreenNote(origin);
}
void TrayAction::CloseLockScreenNote(mojom::CloseLockScreenNoteReason reason) {
if (tray_action_client_)
tray_action_client_->CloseLockScreenNote(reason);
}
void TrayAction::OnStylusStateChanged(ui::StylusState state) {
if (state == ui::StylusState::REMOVED)
lock_screen_note_display_state_handler_->AttemptNoteLaunchForStylusEject();
}
void TrayAction::FlushMojoForTesting() {
if (tray_action_client_)
tray_action_client_.FlushForTesting();
}
void TrayAction::NotifyLockScreenNoteStateChanged() {
for (auto& observer : observers_)
observer.OnLockScreenNoteStateChanged(GetLockScreenNoteState());
}
} // namespace ash
| null | null | null | null | 43,193 |
66,713 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 66,713 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chrome/browser/download/notification/download_notification_manager.h"
#include "base/callback.h"
#include "base/command_line.h"
#include "base/location.h"
#include "base/single_thread_task_runner.h"
#include "base/strings/string_number_conversions.h"
#include "base/threading/thread_task_runner_handle.h"
#include "chrome/browser/browser_process.h"
#include "chrome/browser/download/download_item_model.h"
#include "chrome/browser/download/notification/download_item_notification.h"
#include "chrome/common/chrome_switches.h"
#include "components/download/public/common/download_item.h"
#include "content/public/browser/download_item_utils.h"
#include "ui/base/resource/resource_bundle.h"
///////////////////////////////////////////////////////////////////////////////
// DownloadNotificationManager implementation:
///////////////////////////////////////////////////////////////////////////////
DownloadNotificationManager::DownloadNotificationManager(Profile* profile)
: main_profile_(profile) {}
DownloadNotificationManager::~DownloadNotificationManager() = default;
void DownloadNotificationManager::OnAllDownloadsRemoving(Profile* profile) {
manager_for_profile_.erase(profile);
}
void DownloadNotificationManager::OnNewDownloadReady(
download::DownloadItem* download) {
Profile* profile = Profile::FromBrowserContext(
content::DownloadItemUtils::GetBrowserContext(download));
if (manager_for_profile_.find(profile) == manager_for_profile_.end()) {
manager_for_profile_[profile] =
std::make_unique<DownloadNotificationManagerForProfile>(profile, this);
}
manager_for_profile_[profile]->OnNewDownloadReady(download);
}
DownloadNotificationManagerForProfile*
DownloadNotificationManager::GetForProfile(Profile* profile) const {
return manager_for_profile_.at(profile).get();
}
///////////////////////////////////////////////////////////////////////////////
// DownloadNotificationManagerForProfile implementation:
///////////////////////////////////////////////////////////////////////////////
DownloadNotificationManagerForProfile::DownloadNotificationManagerForProfile(
Profile* profile,
DownloadNotificationManager* parent_manager)
: profile_(profile), parent_manager_(parent_manager) {}
DownloadNotificationManagerForProfile::
~DownloadNotificationManagerForProfile() {
for (const auto& download : items_) {
download.first->RemoveObserver(this);
}
}
void DownloadNotificationManagerForProfile::OnDownloadUpdated(
download::DownloadItem* changed_download) {
DCHECK(items_.find(changed_download) != items_.end());
items_[changed_download]->OnDownloadUpdated(changed_download);
}
void DownloadNotificationManagerForProfile::OnDownloadOpened(
download::DownloadItem* changed_download) {
items_[changed_download]->OnDownloadUpdated(changed_download);
}
void DownloadNotificationManagerForProfile::OnDownloadRemoved(
download::DownloadItem* download) {
DCHECK(items_.find(download) != items_.end());
std::unique_ptr<DownloadItemNotification> item = std::move(items_[download]);
items_.erase(download);
download->RemoveObserver(this);
// notify
item->OnDownloadRemoved(download);
// This removing might be initiated from DownloadNotificationItem, so delaying
// deleting for item to do remaining cleanups.
base::ThreadTaskRunnerHandle::Get()->DeleteSoon(FROM_HERE, item.release());
if (items_.size() == 0 && parent_manager_)
parent_manager_->OnAllDownloadsRemoving(profile_);
// |this| is deleted.
}
void DownloadNotificationManagerForProfile::OnDownloadDestroyed(
download::DownloadItem* download) {
// Do nothing. Cleanup is done in OnDownloadRemoved().
std::unique_ptr<DownloadItemNotification> item = std::move(items_[download]);
items_.erase(download);
item->OnDownloadRemoved(download);
// This removing might be initiated from DownloadNotificationItem, so delaying
// deleting for item to do remaining cleanups.
base::ThreadTaskRunnerHandle::Get()->DeleteSoon(FROM_HERE, item.release());
if (items_.size() == 0 && parent_manager_)
parent_manager_->OnAllDownloadsRemoving(profile_);
// |this| is deleted.
}
void DownloadNotificationManagerForProfile::OnNewDownloadReady(
download::DownloadItem* download) {
DCHECK_EQ(profile_,
Profile::FromBrowserContext(
content::DownloadItemUtils::GetBrowserContext(download)));
download->AddObserver(this);
for (auto& item : items_) {
download::DownloadItem* download_item = item.first;
DownloadItemNotification* download_notification = item.second.get();
if (download_item->GetState() == download::DownloadItem::IN_PROGRESS)
download_notification->DisablePopup();
}
items_[download] = std::make_unique<DownloadItemNotification>(download);
}
DownloadItemNotification*
DownloadNotificationManagerForProfile::GetNotificationItemByGuid(
const std::string& guid) {
for (auto& item : items_) {
if (item.first->GetGuid() == guid)
return item.second.get();
}
NOTREACHED();
return nullptr;
}
| null | null | null | null | 63,576 |
41,779 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 41,779 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef TRACE_AFTER_DISPATCH_IMPL_H_
#define TRACE_AFTER_DISPATCH_IMPL_H_
#include "heap/stubs.h"
namespace blink {
class X : public GarbageCollected<X> {
public:
void Trace(Visitor*) {}
};
enum ClassTag {
BASE, DERIVED
};
class TraceAfterDispatchInlinedBase
: public GarbageCollected<TraceAfterDispatchInlinedBase> {
public:
explicit TraceAfterDispatchInlinedBase(ClassTag tag) : tag_(tag) {}
void Trace(Visitor*);
void TraceAfterDispatch(Visitor* visitor) { visitor->Trace(x_base_); }
private:
ClassTag tag_;
Member<X> x_base_;
};
class TraceAfterDispatchInlinedDerived : public TraceAfterDispatchInlinedBase {
public:
TraceAfterDispatchInlinedDerived() : TraceAfterDispatchInlinedBase(DERIVED) {}
void TraceAfterDispatch(Visitor* visitor) {
visitor->Trace(x_derived_);
TraceAfterDispatchInlinedBase::TraceAfterDispatch(visitor);
}
private:
Member<X> x_derived_;
};
class TraceAfterDispatchExternBase
: public GarbageCollected<TraceAfterDispatchExternBase> {
public:
explicit TraceAfterDispatchExternBase(ClassTag tag) : tag_(tag) {}
void Trace(Visitor* visitor);
void TraceAfterDispatch(Visitor* visitor);
private:
ClassTag tag_;
Member<X> x_base_;
};
class TraceAfterDispatchExternDerived : public TraceAfterDispatchExternBase {
public:
TraceAfterDispatchExternDerived() : TraceAfterDispatchExternBase(DERIVED) {}
void TraceAfterDispatch(Visitor* visitor);
private:
Member<X> x_derived_;
};
}
#endif // TRACE_AFTER_DISPATCH_IMPL_H_
| null | null | null | null | 38,642 |
813 | null | train_val | c536b6be1a72aefd632d5530106a67c516cb9f4b | 257,200 | openssl | 0 | https://github.com/openssl/openssl | 2016-09-22 23:12:38+01:00 | /*
* Copyright 1995-2016 The OpenSSL Project Authors. All Rights Reserved.
*
* Licensed under the OpenSSL license (the "License"). You may not use
* this file except in compliance with the License. You can obtain a copy
* in the file LICENSE in the source distribution or at
* https://www.openssl.org/source/license.html
*/
#include <stdio.h>
#include <limits.h>
#include "internal/cryptlib.h"
#include <openssl/asn1.h>
static int asn1_get_length(const unsigned char **pp, int *inf, long *rl,
long max);
static void asn1_put_length(unsigned char **pp, int length);
static int _asn1_check_infinite_end(const unsigned char **p, long len)
{
/*
* If there is 0 or 1 byte left, the length check should pick things up
*/
if (len <= 0)
return (1);
else if ((len >= 2) && ((*p)[0] == 0) && ((*p)[1] == 0)) {
(*p) += 2;
return (1);
}
return (0);
}
int ASN1_check_infinite_end(unsigned char **p, long len)
{
return _asn1_check_infinite_end((const unsigned char **)p, len);
}
int ASN1_const_check_infinite_end(const unsigned char **p, long len)
{
return _asn1_check_infinite_end(p, len);
}
int ASN1_get_object(const unsigned char **pp, long *plength, int *ptag,
int *pclass, long omax)
{
int i, ret;
long l;
const unsigned char *p = *pp;
int tag, xclass, inf;
long max = omax;
if (!max)
goto err;
ret = (*p & V_ASN1_CONSTRUCTED);
xclass = (*p & V_ASN1_PRIVATE);
i = *p & V_ASN1_PRIMITIVE_TAG;
if (i == V_ASN1_PRIMITIVE_TAG) { /* high-tag */
p++;
if (--max == 0)
goto err;
l = 0;
while (*p & 0x80) {
l <<= 7L;
l |= *(p++) & 0x7f;
if (--max == 0)
goto err;
if (l > (INT_MAX >> 7L))
goto err;
}
l <<= 7L;
l |= *(p++) & 0x7f;
tag = (int)l;
if (--max == 0)
goto err;
} else {
tag = i;
p++;
if (--max == 0)
goto err;
}
*ptag = tag;
*pclass = xclass;
if (!asn1_get_length(&p, &inf, plength, max))
goto err;
if (inf && !(ret & V_ASN1_CONSTRUCTED))
goto err;
if (*plength > (omax - (p - *pp))) {
ASN1err(ASN1_F_ASN1_GET_OBJECT, ASN1_R_TOO_LONG);
/*
* Set this so that even if things are not long enough the values are
* set correctly
*/
ret |= 0x80;
}
*pp = p;
return (ret | inf);
err:
ASN1err(ASN1_F_ASN1_GET_OBJECT, ASN1_R_HEADER_TOO_LONG);
return (0x80);
}
static int asn1_get_length(const unsigned char **pp, int *inf, long *rl,
long max)
{
const unsigned char *p = *pp;
unsigned long ret = 0;
unsigned long i;
if (max-- < 1)
return 0;
if (*p == 0x80) {
*inf = 1;
ret = 0;
p++;
} else {
*inf = 0;
i = *p & 0x7f;
if (*(p++) & 0x80) {
if (max < (long)i + 1)
return 0;
/* Skip leading zeroes */
while (i && *p == 0) {
p++;
i--;
}
if (i > sizeof(long))
return 0;
while (i-- > 0) {
ret <<= 8L;
ret |= *(p++);
}
} else
ret = i;
}
if (ret > LONG_MAX)
return 0;
*pp = p;
*rl = (long)ret;
return 1;
}
/*
* class 0 is constructed constructed == 2 for indefinite length constructed
*/
void ASN1_put_object(unsigned char **pp, int constructed, int length, int tag,
int xclass)
{
unsigned char *p = *pp;
int i, ttag;
i = (constructed) ? V_ASN1_CONSTRUCTED : 0;
i |= (xclass & V_ASN1_PRIVATE);
if (tag < 31)
*(p++) = i | (tag & V_ASN1_PRIMITIVE_TAG);
else {
*(p++) = i | V_ASN1_PRIMITIVE_TAG;
for (i = 0, ttag = tag; ttag > 0; i++)
ttag >>= 7;
ttag = i;
while (i-- > 0) {
p[i] = tag & 0x7f;
if (i != (ttag - 1))
p[i] |= 0x80;
tag >>= 7;
}
p += ttag;
}
if (constructed == 2)
*(p++) = 0x80;
else
asn1_put_length(&p, length);
*pp = p;
}
int ASN1_put_eoc(unsigned char **pp)
{
unsigned char *p = *pp;
*p++ = 0;
*p++ = 0;
*pp = p;
return 2;
}
static void asn1_put_length(unsigned char **pp, int length)
{
unsigned char *p = *pp;
int i, l;
if (length <= 127)
*(p++) = (unsigned char)length;
else {
l = length;
for (i = 0; l > 0; i++)
l >>= 8;
*(p++) = i | 0x80;
l = i;
while (i-- > 0) {
p[i] = length & 0xff;
length >>= 8;
}
p += l;
}
*pp = p;
}
int ASN1_object_size(int constructed, int length, int tag)
{
int ret = 1;
if (length < 0)
return -1;
if (tag >= 31) {
while (tag > 0) {
tag >>= 7;
ret++;
}
}
if (constructed == 2) {
ret += 3;
} else {
ret++;
if (length > 127) {
int tmplen = length;
while (tmplen > 0) {
tmplen >>= 8;
ret++;
}
}
}
if (ret >= INT_MAX - length)
return -1;
return ret + length;
}
int ASN1_STRING_copy(ASN1_STRING *dst, const ASN1_STRING *str)
{
if (str == NULL)
return 0;
dst->type = str->type;
if (!ASN1_STRING_set(dst, str->data, str->length))
return 0;
/* Copy flags but preserve embed value */
dst->flags &= ASN1_STRING_FLAG_EMBED;
dst->flags |= str->flags & ~ASN1_STRING_FLAG_EMBED;
return 1;
}
ASN1_STRING *ASN1_STRING_dup(const ASN1_STRING *str)
{
ASN1_STRING *ret;
if (!str)
return NULL;
ret = ASN1_STRING_new();
if (ret == NULL)
return NULL;
if (!ASN1_STRING_copy(ret, str)) {
ASN1_STRING_free(ret);
return NULL;
}
return ret;
}
int ASN1_STRING_set(ASN1_STRING *str, const void *_data, int len)
{
unsigned char *c;
const char *data = _data;
if (len < 0) {
if (data == NULL)
return (0);
else
len = strlen(data);
}
if ((str->length <= len) || (str->data == NULL)) {
c = str->data;
str->data = OPENSSL_realloc(c, len + 1);
if (str->data == NULL) {
ASN1err(ASN1_F_ASN1_STRING_SET, ERR_R_MALLOC_FAILURE);
str->data = c;
return (0);
}
}
str->length = len;
if (data != NULL) {
memcpy(str->data, data, len);
/* an allowance for strings :-) */
str->data[len] = '\0';
}
return (1);
}
void ASN1_STRING_set0(ASN1_STRING *str, void *data, int len)
{
OPENSSL_free(str->data);
str->data = data;
str->length = len;
}
ASN1_STRING *ASN1_STRING_new(void)
{
return (ASN1_STRING_type_new(V_ASN1_OCTET_STRING));
}
ASN1_STRING *ASN1_STRING_type_new(int type)
{
ASN1_STRING *ret;
ret = OPENSSL_zalloc(sizeof(*ret));
if (ret == NULL) {
ASN1err(ASN1_F_ASN1_STRING_TYPE_NEW, ERR_R_MALLOC_FAILURE);
return (NULL);
}
ret->type = type;
return (ret);
}
void ASN1_STRING_free(ASN1_STRING *a)
{
if (a == NULL)
return;
if (!(a->flags & ASN1_STRING_FLAG_NDEF))
OPENSSL_free(a->data);
if (!(a->flags & ASN1_STRING_FLAG_EMBED))
OPENSSL_free(a);
}
void ASN1_STRING_clear_free(ASN1_STRING *a)
{
if (a == NULL)
return;
if (a->data && !(a->flags & ASN1_STRING_FLAG_NDEF))
OPENSSL_cleanse(a->data, a->length);
ASN1_STRING_free(a);
}
int ASN1_STRING_cmp(const ASN1_STRING *a, const ASN1_STRING *b)
{
int i;
i = (a->length - b->length);
if (i == 0) {
i = memcmp(a->data, b->data, a->length);
if (i == 0)
return (a->type - b->type);
else
return (i);
} else
return (i);
}
int ASN1_STRING_length(const ASN1_STRING *x)
{
return x->length;
}
void ASN1_STRING_length_set(ASN1_STRING *x, int len)
{
x->length = len;
}
int ASN1_STRING_type(const ASN1_STRING *x)
{
return x->type;
}
const unsigned char *ASN1_STRING_get0_data(const ASN1_STRING *x)
{
return x->data;
}
# if OPENSSL_API_COMPAT < 0x10100000L
unsigned char *ASN1_STRING_data(ASN1_STRING *x)
{
return x->data;
}
#endif
| null | null | null | null | 118,645 |
30,079 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 30,079 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | /*
** 2016 September 10
**
** The author disclaims copyright to this source code. In place of
** a legal notice, here is a blessing:
**
** May you do good and not evil.
** May you find forgiveness for yourself and forgive others.
** May you share freely, never taking more than you give.
**
*************************************************************************
** This file contains test code to delete an SQLite database and all
** of its associated files. Associated files include:
**
** * The journal file.
** * The wal file.
** * The SQLITE_ENABLE_8_3_NAMES version of the db, journal or wal files.
** * Files created by the test_multiplex.c module to extend any of the
** above.
*/
#ifndef SQLITE_OS_WIN
# include <unistd.h>
# include <errno.h>
#endif
#include <string.h>
#include <assert.h>
#include "sqlite3.h"
/* The following #defines are copied from test_multiplex.c */
#ifndef MX_CHUNK_NUMBER
# define MX_CHUNK_NUMBER 299
#endif
#ifndef SQLITE_MULTIPLEX_JOURNAL_8_3_OFFSET
# define SQLITE_MULTIPLEX_JOURNAL_8_3_OFFSET 400
#endif
#ifndef SQLITE_MULTIPLEX_WAL_8_3_OFFSET
# define SQLITE_MULTIPLEX_WAL_8_3_OFFSET 700
#endif
/*
** This routine is a copy of (most of) the code from SQLite function
** sqlite3FileSuffix3(). It modifies the filename in buffer z in the
** same way as SQLite does when in 8.3 filenames mode.
*/
static void sqlite3Delete83Name(char *z){
int i, sz;
sz = (int)strlen(z);
for(i=sz-1; i>0 && z[i]!='/' && z[i]!='.'; i--){}
if( z[i]=='.' && (sz>i+4) ) memmove(&z[i+1], &z[sz-3], 4);
}
/*
** zFile is a filename. Assuming no error occurs, if this file exists,
** set *pbExists to true and unlink it. Or, if the file does not exist,
** set *pbExists to false before returning.
**
** If an error occurs, non-zero is returned. Or, if no error occurs, zero.
*/
static int sqlite3DeleteUnlinkIfExists(
sqlite3_vfs *pVfs,
const char *zFile,
int *pbExists
){
int rc = SQLITE_ERROR;
#if SQLITE_OS_WIN
if( pVfs ){
if( pbExists ) *pbExists = 1;
rc = pVfs->xDelete(pVfs, zFile, 0);
if( rc==SQLITE_IOERR_DELETE_NOENT ){
if( pbExists ) *pbExists = 0;
rc = SQLITE_OK;
}
}
#else
assert( pVfs==0 );
rc = access(zFile, F_OK);
if( rc ){
if( errno==ENOENT ){
if( pbExists ) *pbExists = 0;
rc = SQLITE_OK;
}
}else{
if( pbExists ) *pbExists = 1;
rc = unlink(zFile);
}
#endif
return rc;
}
/*
** Delete the database file identified by the string argument passed to this
** function. The string must contain a filename, not an SQLite URI.
*/
SQLITE_API int sqlite3_delete_database(
const char *zFile /* File to delete */
){
char *zBuf; /* Buffer to sprintf() filenames to */
int nBuf; /* Size of buffer in bytes */
int rc = 0; /* System error code */
int i; /* Iterate through azFmt[] and aMFile[] */
const char *azFmt[] = { "%s", "%s-journal", "%s-wal", "%s-shm" };
struct MFile {
const char *zFmt;
int iOffset;
int b83;
} aMFile[] = {
{ "%s%03d", 0, 0 },
{ "%s-journal%03d", 0, 0 },
{ "%s-wal%03d", 0, 0 },
{ "%s%03d", 0, 1 },
{ "%s-journal%03d", SQLITE_MULTIPLEX_JOURNAL_8_3_OFFSET, 1 },
{ "%s-wal%03d", SQLITE_MULTIPLEX_WAL_8_3_OFFSET, 1 },
};
#ifdef SQLITE_OS_WIN
sqlite3_vfs *pVfs = sqlite3_vfs_find("win32");
#else
sqlite3_vfs *pVfs = 0;
#endif
/* Allocate a buffer large enough for any of the files that need to be
** deleted. */
nBuf = (int)strlen(zFile) + 100;
zBuf = (char*)sqlite3_malloc(nBuf);
if( zBuf==0 ) return SQLITE_NOMEM;
/* Delete both the regular and 8.3 filenames versions of the database,
** journal, wal and shm files. */
for(i=0; rc==0 && i<sizeof(azFmt)/sizeof(azFmt[0]); i++){
sqlite3_snprintf(nBuf, zBuf, azFmt[i], zFile);
rc = sqlite3DeleteUnlinkIfExists(pVfs, zBuf, 0);
if( rc==0 && i!=0 ){
sqlite3Delete83Name(zBuf);
rc = sqlite3DeleteUnlinkIfExists(pVfs, zBuf, 0);
}
}
/* Delete any multiplexor files */
for(i=0; rc==0 && i<sizeof(aMFile)/sizeof(aMFile[0]); i++){
struct MFile *p = &aMFile[i];
int iChunk;
for(iChunk=1; iChunk<=MX_CHUNK_NUMBER; iChunk++){
int bExists;
sqlite3_snprintf(nBuf, zBuf, p->zFmt, zFile, iChunk+p->iOffset);
if( p->b83 ) sqlite3Delete83Name(zBuf);
rc = sqlite3DeleteUnlinkIfExists(pVfs, zBuf, &bExists);
if( bExists==0 || rc!=0 ) break;
}
}
sqlite3_free(zBuf);
return (rc ? SQLITE_ERROR : SQLITE_OK);
}
| null | null | null | null | 26,942 |
8,834 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 8,834 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "net/ssl/ssl_client_session_cache.h"
#include "base/memory/ptr_util.h"
#include "base/run_loop.h"
#include "base/strings/string_number_conversions.h"
#include "base/test/simple_test_clock.h"
#include "base/time/time.h"
#include "base/trace_event/memory_allocator_dump.h"
#include "base/trace_event/process_memory_dump.h"
#include "base/trace_event/trace_event_argument.h"
#include "testing/gmock/include/gmock/gmock.h"
#include "testing/gtest/include/gtest/gtest.h"
#include "third_party/boringssl/src/include/openssl/ssl.h"
using testing::Contains;
using testing::Eq;
using testing::Field;
using testing::ByRef;
namespace net {
namespace {
std::unique_ptr<base::SimpleTestClock> MakeTestClock() {
std::unique_ptr<base::SimpleTestClock> clock =
std::make_unique<base::SimpleTestClock>();
// SimpleTestClock starts at the null base::Time which converts to and from
// time_t confusingly.
clock->SetNow(base::Time::FromTimeT(1000000000));
return clock;
}
class SSLClientSessionCacheTest : public testing::Test {
public:
SSLClientSessionCacheTest() : ssl_ctx_(SSL_CTX_new(TLS_method())) {}
protected:
bssl::UniquePtr<SSL_SESSION> NewSSLSession(
uint16_t version = TLS1_2_VERSION) {
SSL_SESSION* session = SSL_SESSION_new(ssl_ctx_.get());
if (!SSL_SESSION_set_protocol_version(session, version))
return nullptr;
return bssl::UniquePtr<SSL_SESSION>(session);
}
bssl::UniquePtr<SSL_SESSION> MakeTestSession(base::Time now,
base::TimeDelta timeout) {
bssl::UniquePtr<SSL_SESSION> session = NewSSLSession();
SSL_SESSION_set_time(session.get(), now.ToTimeT());
SSL_SESSION_set_timeout(session.get(), timeout.InSeconds());
return session;
}
private:
bssl::UniquePtr<SSL_CTX> ssl_ctx_;
};
} // namespace
// Test basic insertion and lookup operations.
TEST_F(SSLClientSessionCacheTest, Basic) {
SSLClientSessionCache::Config config;
SSLClientSessionCache cache(config);
bssl::UniquePtr<SSL_SESSION> session1 = NewSSLSession();
bssl::UniquePtr<SSL_SESSION> session2 = NewSSLSession();
bssl::UniquePtr<SSL_SESSION> session3 = NewSSLSession();
EXPECT_EQ(1u, session1->references);
EXPECT_EQ(1u, session2->references);
EXPECT_EQ(1u, session3->references);
EXPECT_EQ(nullptr, cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(0u, cache.size());
cache.Insert("key1", session1.get());
EXPECT_EQ(session1.get(), cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(1u, cache.size());
cache.Insert("key2", session2.get());
EXPECT_EQ(session1.get(), cache.Lookup("key1").get());
EXPECT_EQ(session2.get(), cache.Lookup("key2").get());
EXPECT_EQ(2u, cache.size());
EXPECT_EQ(2u, session1->references);
EXPECT_EQ(2u, session2->references);
cache.Insert("key1", session3.get());
EXPECT_EQ(session3.get(), cache.Lookup("key1").get());
EXPECT_EQ(session2.get(), cache.Lookup("key2").get());
EXPECT_EQ(2u, cache.size());
EXPECT_EQ(1u, session1->references);
EXPECT_EQ(2u, session2->references);
EXPECT_EQ(2u, session3->references);
cache.Flush();
EXPECT_EQ(nullptr, cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(nullptr, cache.Lookup("key3").get());
EXPECT_EQ(0u, cache.size());
EXPECT_EQ(1u, session1->references);
EXPECT_EQ(1u, session2->references);
EXPECT_EQ(1u, session3->references);
}
// Test basic insertion and lookup operations with single-use sessions.
TEST_F(SSLClientSessionCacheTest, BasicSingleUse) {
SSLClientSessionCache::Config config;
SSLClientSessionCache cache(config);
bssl::UniquePtr<SSL_SESSION> session1 = NewSSLSession(TLS1_3_VERSION);
bssl::UniquePtr<SSL_SESSION> session2 = NewSSLSession(TLS1_3_VERSION);
bssl::UniquePtr<SSL_SESSION> session3 = NewSSLSession(TLS1_3_VERSION);
EXPECT_EQ(1u, session1->references);
EXPECT_EQ(1u, session2->references);
EXPECT_EQ(1u, session3->references);
EXPECT_EQ(nullptr, cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(0u, cache.size());
cache.Insert("key1", session1.get());
EXPECT_EQ(session1.get(), cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(0u, cache.size());
EXPECT_EQ(nullptr, cache.Lookup("key1").get());
cache.Insert("key1", session1.get());
cache.Insert("key1", session1.get());
cache.Insert("key2", session2.get());
EXPECT_EQ(3u, session1->references);
EXPECT_EQ(2u, session2->references);
EXPECT_EQ(session1.get(), cache.Lookup("key1").get());
EXPECT_EQ(session2.get(), cache.Lookup("key2").get());
EXPECT_EQ(1u, cache.size());
EXPECT_EQ(session1.get(), cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(1u, session1->references);
EXPECT_EQ(1u, session2->references);
cache.Insert("key1", session1.get());
cache.Insert("key1", session3.get());
cache.Insert("key2", session2.get());
EXPECT_EQ(session3.get(), cache.Lookup("key1").get());
EXPECT_EQ(session1.get(), cache.Lookup("key1").get());
EXPECT_EQ(session2.get(), cache.Lookup("key2").get());
EXPECT_EQ(0u, cache.size());
EXPECT_EQ(1u, session1->references);
EXPECT_EQ(1u, session2->references);
EXPECT_EQ(1u, session3->references);
cache.Flush();
EXPECT_EQ(nullptr, cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(nullptr, cache.Lookup("key3").get());
EXPECT_EQ(0u, cache.size());
cache.Insert("key1", session1.get());
cache.Insert("key1", session2.get());
cache.Insert("key1", session3.get());
EXPECT_EQ(1u, session1->references);
EXPECT_EQ(2u, session2->references);
EXPECT_EQ(2u, session3->references);
EXPECT_EQ(session3.get(), cache.Lookup("key1").get());
EXPECT_EQ(session2.get(), cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key1").get());
EXPECT_EQ(1u, session1->references);
EXPECT_EQ(1u, session2->references);
EXPECT_EQ(1u, session3->references);
}
// Test insertion and lookup operations with both single-use and reusable
// sessions.
TEST_F(SSLClientSessionCacheTest, MixedUse) {
SSLClientSessionCache::Config config;
SSLClientSessionCache cache(config);
bssl::UniquePtr<SSL_SESSION> session_single = NewSSLSession(TLS1_3_VERSION);
bssl::UniquePtr<SSL_SESSION> session_reuse = NewSSLSession(TLS1_2_VERSION);
EXPECT_EQ(1u, session_single->references);
EXPECT_EQ(1u, session_reuse->references);
EXPECT_EQ(nullptr, cache.Lookup("key1").get());
EXPECT_EQ(0u, cache.size());
cache.Insert("key1", session_reuse.get());
EXPECT_EQ(session_reuse.get(), cache.Lookup("key1").get());
EXPECT_EQ(1u, cache.size());
cache.Insert("key1", session_single.get());
EXPECT_EQ(session_single.get(), cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key1").get());
EXPECT_EQ(0u, cache.size());
EXPECT_EQ(1u, session_single->references);
EXPECT_EQ(1u, session_reuse->references);
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(0u, cache.size());
cache.Insert("key2", session_single.get());
cache.Insert("key2", session_single.get());
EXPECT_EQ(1u, cache.size());
EXPECT_EQ(session_single.get(), cache.Lookup("key2").get());
EXPECT_EQ(session_single.get(), cache.Lookup("key2").get());
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(0u, cache.size());
cache.Insert("key2", session_single.get());
cache.Insert("key2", session_reuse.get());
EXPECT_EQ(session_reuse.get(), cache.Lookup("key2").get());
EXPECT_EQ(session_reuse.get(), cache.Lookup("key2").get());
EXPECT_EQ(1u, cache.size());
EXPECT_EQ(2u, session_single->references);
EXPECT_EQ(2u, session_reuse->references);
}
// Test that a session may be inserted at two different keys. This should never
// be necessary, but the API doesn't prohibit it.
TEST_F(SSLClientSessionCacheTest, DoubleInsert) {
SSLClientSessionCache::Config config;
SSLClientSessionCache cache(config);
bssl::UniquePtr<SSL_SESSION> session = NewSSLSession();
EXPECT_EQ(1u, session->references);
EXPECT_EQ(nullptr, cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(0u, cache.size());
cache.Insert("key1", session.get());
EXPECT_EQ(session.get(), cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(1u, cache.size());
EXPECT_EQ(2u, session->references);
cache.Insert("key2", session.get());
EXPECT_EQ(session.get(), cache.Lookup("key1").get());
EXPECT_EQ(session.get(), cache.Lookup("key2").get());
EXPECT_EQ(2u, cache.size());
EXPECT_EQ(3u, session->references);
cache.Flush();
EXPECT_EQ(nullptr, cache.Lookup("key1").get());
EXPECT_EQ(nullptr, cache.Lookup("key2").get());
EXPECT_EQ(0u, cache.size());
EXPECT_EQ(1u, session->references);
}
// Tests that the session cache's size is correctly bounded.
TEST_F(SSLClientSessionCacheTest, MaxEntries) {
SSLClientSessionCache::Config config;
config.max_entries = 3;
SSLClientSessionCache cache(config);
bssl::UniquePtr<SSL_SESSION> session1 = NewSSLSession();
bssl::UniquePtr<SSL_SESSION> session2 = NewSSLSession();
bssl::UniquePtr<SSL_SESSION> session3 = NewSSLSession();
bssl::UniquePtr<SSL_SESSION> session4 = NewSSLSession();
// Insert three entries.
cache.Insert("key1", session1.get());
cache.Insert("key2", session2.get());
cache.Insert("key3", session3.get());
EXPECT_EQ(session1.get(), cache.Lookup("key1").get());
EXPECT_EQ(session2.get(), cache.Lookup("key2").get());
EXPECT_EQ(session3.get(), cache.Lookup("key3").get());
EXPECT_EQ(3u, cache.size());
// On insertion of a fourth, the first is removed.
cache.Insert("key4", session4.get());
EXPECT_EQ(nullptr, cache.Lookup("key1").get());
EXPECT_EQ(session4.get(), cache.Lookup("key4").get());
EXPECT_EQ(session3.get(), cache.Lookup("key3").get());
EXPECT_EQ(session2.get(), cache.Lookup("key2").get());
EXPECT_EQ(3u, cache.size());
// Despite being newest, the next to be removed is session4 as it was accessed
// least. recently.
cache.Insert("key1", session1.get());
EXPECT_EQ(session1.get(), cache.Lookup("key1").get());
EXPECT_EQ(session2.get(), cache.Lookup("key2").get());
EXPECT_EQ(session3.get(), cache.Lookup("key3").get());
EXPECT_EQ(nullptr, cache.Lookup("key4").get());
EXPECT_EQ(3u, cache.size());
}
// Tests that session expiration works properly.
TEST_F(SSLClientSessionCacheTest, Expiration) {
const size_t kNumEntries = 20;
const size_t kExpirationCheckCount = 10;
const base::TimeDelta kTimeout = base::TimeDelta::FromSeconds(1000);
SSLClientSessionCache::Config config;
config.expiration_check_count = kExpirationCheckCount;
SSLClientSessionCache cache(config);
std::unique_ptr<base::SimpleTestClock> clock = MakeTestClock();
cache.SetClockForTesting(clock.get());
// Add |kNumEntries - 1| entries.
for (size_t i = 0; i < kNumEntries - 1; i++) {
bssl::UniquePtr<SSL_SESSION> session =
MakeTestSession(clock->Now(), kTimeout);
cache.Insert(base::NumberToString(i), session.get());
}
EXPECT_EQ(kNumEntries - 1, cache.size());
// Expire all the previous entries and insert one more entry.
clock->Advance(kTimeout * 2);
bssl::UniquePtr<SSL_SESSION> session =
MakeTestSession(clock->Now(), kTimeout);
cache.Insert("key", session.get());
// All entries are still in the cache.
EXPECT_EQ(kNumEntries, cache.size());
// Perform one fewer lookup than needed to trigger the expiration check. This
// shall not expire any session.
for (size_t i = 0; i < kExpirationCheckCount - 1; i++)
cache.Lookup("key");
// All entries are still in the cache.
EXPECT_EQ(kNumEntries, cache.size());
// Perform one more lookup. This will expire all sessions but the last one.
cache.Lookup("key");
EXPECT_EQ(1u, cache.size());
EXPECT_EQ(session.get(), cache.Lookup("key").get());
for (size_t i = 0; i < kNumEntries - 1; i++) {
SCOPED_TRACE(i);
EXPECT_EQ(nullptr, cache.Lookup(base::NumberToString(i)));
}
}
// Tests that Lookup performs an expiration check before returning a cached
// session.
TEST_F(SSLClientSessionCacheTest, LookupExpirationCheck) {
// kExpirationCheckCount is set to a suitably large number so the automated
// pruning never triggers.
const size_t kExpirationCheckCount = 1000;
const base::TimeDelta kTimeout = base::TimeDelta::FromSeconds(1000);
SSLClientSessionCache::Config config;
config.expiration_check_count = kExpirationCheckCount;
SSLClientSessionCache cache(config);
std::unique_ptr<base::SimpleTestClock> clock = MakeTestClock();
cache.SetClockForTesting(clock.get());
// Insert an entry into the session cache.
bssl::UniquePtr<SSL_SESSION> session =
MakeTestSession(clock->Now(), kTimeout);
cache.Insert("key", session.get());
EXPECT_EQ(session.get(), cache.Lookup("key").get());
EXPECT_EQ(1u, cache.size());
// Expire the session.
clock->Advance(kTimeout * 2);
// The entry has not been removed yet.
EXPECT_EQ(1u, cache.size());
// But it will not be returned on lookup and gets pruned at that point.
EXPECT_EQ(nullptr, cache.Lookup("key").get());
EXPECT_EQ(0u, cache.size());
// Re-inserting a session does not refresh the lifetime. The expiration
// information in the session is used.
cache.Insert("key", session.get());
EXPECT_EQ(nullptr, cache.Lookup("key").get());
EXPECT_EQ(0u, cache.size());
// Re-insert a fresh copy of the session.
session = MakeTestSession(clock->Now(), kTimeout);
cache.Insert("key", session.get());
EXPECT_EQ(session.get(), cache.Lookup("key").get());
EXPECT_EQ(1u, cache.size());
// Sessions also are treated as expired if the clock rewinds.
clock->Advance(base::TimeDelta::FromSeconds(-1));
EXPECT_EQ(nullptr, cache.Lookup("key").get());
EXPECT_EQ(0u, cache.size());
}
// Test that SSL cache is flushed on low memory notifications
TEST_F(SSLClientSessionCacheTest, TestFlushOnMemoryNotifications) {
// kExpirationCheckCount is set to a suitably large number so the automated
// pruning never triggers.
const size_t kExpirationCheckCount = 1000;
const base::TimeDelta kTimeout = base::TimeDelta::FromSeconds(1000);
SSLClientSessionCache::Config config;
config.expiration_check_count = kExpirationCheckCount;
SSLClientSessionCache cache(config);
std::unique_ptr<base::SimpleTestClock> clock = MakeTestClock();
cache.SetClockForTesting(clock.get());
// Insert an entry into the session cache.
bssl::UniquePtr<SSL_SESSION> session1 =
MakeTestSession(clock->Now(), kTimeout);
cache.Insert("key1", session1.get());
EXPECT_EQ(session1.get(), cache.Lookup("key1").get());
EXPECT_EQ(1u, cache.size());
// Expire the session.
clock->Advance(kTimeout * 2);
// Add one more session.
bssl::UniquePtr<SSL_SESSION> session2 =
MakeTestSession(clock->Now(), kTimeout);
cache.Insert("key2", session2.get());
EXPECT_EQ(2u, cache.size());
// Fire a notification that will flush expired sessions.
base::MemoryPressureListener::NotifyMemoryPressure(
base::MemoryPressureListener::MEMORY_PRESSURE_LEVEL_MODERATE);
base::RunLoop().RunUntilIdle();
// Expired session's cache should be flushed.
// Lookup returns nullptr, when cache entry not found.
EXPECT_FALSE(cache.Lookup("key1"));
EXPECT_TRUE(cache.Lookup("key2"));
EXPECT_EQ(1u, cache.size());
// Fire notification that will flush everything.
base::MemoryPressureListener::NotifyMemoryPressure(
base::MemoryPressureListener::MEMORY_PRESSURE_LEVEL_CRITICAL);
base::RunLoop().RunUntilIdle();
EXPECT_EQ(0u, cache.size());
}
class SSLClientSessionCacheMemoryDumpTest
: public SSLClientSessionCacheTest,
public testing::WithParamInterface<
base::trace_event::MemoryDumpLevelOfDetail> {};
INSTANTIATE_TEST_CASE_P(
/* no prefix */,
SSLClientSessionCacheMemoryDumpTest,
::testing::Values(base::trace_event::MemoryDumpLevelOfDetail::DETAILED,
base::trace_event::MemoryDumpLevelOfDetail::BACKGROUND));
// Basic test for dumping memory stats.
TEST_P(SSLClientSessionCacheMemoryDumpTest, TestDumpMemoryStats) {
SSLClientSessionCache::Config config;
SSLClientSessionCache cache(config);
bssl::UniquePtr<SSL_SESSION> session1 = NewSSLSession();
bssl::UniquePtr<SSL_SESSION> session2 = NewSSLSession();
bssl::UniquePtr<SSL_SESSION> session3 = NewSSLSession();
// Insert three entries.
cache.Insert("key1", session1.get());
cache.Insert("key2", session2.get());
cache.Insert("key3", session3.get());
EXPECT_EQ(session1.get(), cache.Lookup("key1").get());
EXPECT_EQ(session2.get(), cache.Lookup("key2").get());
EXPECT_EQ(session3.get(), cache.Lookup("key3").get());
EXPECT_EQ(3u, cache.size());
base::trace_event::MemoryDumpArgs dump_args = {GetParam()};
std::unique_ptr<base::trace_event::ProcessMemoryDump> process_memory_dump(
new base::trace_event::ProcessMemoryDump(nullptr, dump_args));
cache.DumpMemoryStats(process_memory_dump.get());
using Entry = base::trace_event::MemoryAllocatorDump::Entry;
const base::trace_event::MemoryAllocatorDump* dump =
process_memory_dump->GetAllocatorDump("net/ssl_session_cache");
ASSERT_NE(nullptr, dump);
const std::vector<Entry>& entries = dump->entries();
EXPECT_THAT(entries, Contains(Field(&Entry::name, Eq("cert_count"))));
EXPECT_THAT(entries, Contains(Field(&Entry::name, Eq("cert_size"))));
EXPECT_THAT(entries,
Contains(Field(&Entry::name, Eq("undeduped_cert_size"))));
EXPECT_THAT(entries,
Contains(Field(&Entry::name, Eq("undeduped_cert_count"))));
EXPECT_THAT(
entries,
Contains(Field(&Entry::name,
Eq(base::trace_event::MemoryAllocatorDump::kNameSize))));
}
} // namespace net
| null | null | null | null | 5,697 |
64,653 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 64,653 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2011 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef CHROME_BROWSER_UI_COCOA_INFOBARS_BEFORE_TRANSLATE_INFOBAR_CONTROLLER_H_
#define CHROME_BROWSER_UI_COCOA_INFOBARS_BEFORE_TRANSLATE_INFOBAR_CONTROLLER_H_
#import "chrome/browser/ui/cocoa/infobars/translate_infobar_base.h"
@interface BeforeTranslateInfobarController : TranslateInfoBarControllerBase {
base::scoped_nsobject<NSButton> alwaysTranslateButton_;
base::scoped_nsobject<NSButton> neverTranslateButton_;
}
// Creates and initializes the alwaysTranslate and neverTranslate buttons.
- (void)initializeExtraControls;
@end
@interface BeforeTranslateInfobarController (TestingAPI)
- (NSButton*)alwaysTranslateButton;
- (NSButton*)neverTranslateButton;
@end
#endif // CHROME_BROWSER_UI_COCOA_INFOBARS_BEFORE_TRANSLATE_INFOBAR_CONTROLLER_H_
| null | null | null | null | 61,516 |
29,676 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 194,671 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* drivers/usb/core/usb.c
*
* (C) Copyright Linus Torvalds 1999
* (C) Copyright Johannes Erdfelt 1999-2001
* (C) Copyright Andreas Gal 1999
* (C) Copyright Gregory P. Smith 1999
* (C) Copyright Deti Fliegl 1999 (new USB architecture)
* (C) Copyright Randy Dunlap 2000
* (C) Copyright David Brownell 2000-2004
* (C) Copyright Yggdrasil Computing, Inc. 2000
* (usb_device_id matching changes by Adam J. Richter)
* (C) Copyright Greg Kroah-Hartman 2002-2003
*
* Released under the GPLv2 only.
* SPDX-License-Identifier: GPL-2.0
*
* NOTE! This is not actually a driver at all, rather this is
* just a collection of helper routines that implement the
* generic USB things that the real drivers can use..
*
* Think of this as a "USB library" rather than anything else.
* It should be considered a slave, with no callbacks. Callbacks
* are evil.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/slab.h>
#include <linux/interrupt.h> /* for in_interrupt() */
#include <linux/kmod.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include <linux/debugfs.h>
#include <linux/usb/of.h>
#include <asm/io.h>
#include <linux/scatterlist.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include "usb.h"
const char *usbcore_name = "usbcore";
static bool nousb; /* Disable USB when built into kernel image */
module_param(nousb, bool, 0444);
/*
* for external read access to <nousb>
*/
int usb_disabled(void)
{
return nousb;
}
EXPORT_SYMBOL_GPL(usb_disabled);
#ifdef CONFIG_PM
static int usb_autosuspend_delay = 2; /* Default delay value,
* in seconds */
module_param_named(autosuspend, usb_autosuspend_delay, int, 0644);
MODULE_PARM_DESC(autosuspend, "default autosuspend delay");
#else
#define usb_autosuspend_delay 0
#endif
/**
* usb_find_alt_setting() - Given a configuration, find the alternate setting
* for the given interface.
* @config: the configuration to search (not necessarily the current config).
* @iface_num: interface number to search in
* @alt_num: alternate interface setting number to search for.
*
* Search the configuration's interface cache for the given alt setting.
*
* Return: The alternate setting, if found. %NULL otherwise.
*/
struct usb_host_interface *usb_find_alt_setting(
struct usb_host_config *config,
unsigned int iface_num,
unsigned int alt_num)
{
struct usb_interface_cache *intf_cache = NULL;
int i;
for (i = 0; i < config->desc.bNumInterfaces; i++) {
if (config->intf_cache[i]->altsetting[0].desc.bInterfaceNumber
== iface_num) {
intf_cache = config->intf_cache[i];
break;
}
}
if (!intf_cache)
return NULL;
for (i = 0; i < intf_cache->num_altsetting; i++)
if (intf_cache->altsetting[i].desc.bAlternateSetting == alt_num)
return &intf_cache->altsetting[i];
printk(KERN_DEBUG "Did not find alt setting %u for intf %u, "
"config %u\n", alt_num, iface_num,
config->desc.bConfigurationValue);
return NULL;
}
EXPORT_SYMBOL_GPL(usb_find_alt_setting);
/**
* usb_ifnum_to_if - get the interface object with a given interface number
* @dev: the device whose current configuration is considered
* @ifnum: the desired interface
*
* This walks the device descriptor for the currently active configuration
* to find the interface object with the particular interface number.
*
* Note that configuration descriptors are not required to assign interface
* numbers sequentially, so that it would be incorrect to assume that
* the first interface in that descriptor corresponds to interface zero.
* This routine helps device drivers avoid such mistakes.
* However, you should make sure that you do the right thing with any
* alternate settings available for this interfaces.
*
* Don't call this function unless you are bound to one of the interfaces
* on this device or you have locked the device!
*
* Return: A pointer to the interface that has @ifnum as interface number,
* if found. %NULL otherwise.
*/
struct usb_interface *usb_ifnum_to_if(const struct usb_device *dev,
unsigned ifnum)
{
struct usb_host_config *config = dev->actconfig;
int i;
if (!config)
return NULL;
for (i = 0; i < config->desc.bNumInterfaces; i++)
if (config->interface[i]->altsetting[0]
.desc.bInterfaceNumber == ifnum)
return config->interface[i];
return NULL;
}
EXPORT_SYMBOL_GPL(usb_ifnum_to_if);
/**
* usb_altnum_to_altsetting - get the altsetting structure with a given alternate setting number.
* @intf: the interface containing the altsetting in question
* @altnum: the desired alternate setting number
*
* This searches the altsetting array of the specified interface for
* an entry with the correct bAlternateSetting value.
*
* Note that altsettings need not be stored sequentially by number, so
* it would be incorrect to assume that the first altsetting entry in
* the array corresponds to altsetting zero. This routine helps device
* drivers avoid such mistakes.
*
* Don't call this function unless you are bound to the intf interface
* or you have locked the device!
*
* Return: A pointer to the entry of the altsetting array of @intf that
* has @altnum as the alternate setting number. %NULL if not found.
*/
struct usb_host_interface *usb_altnum_to_altsetting(
const struct usb_interface *intf,
unsigned int altnum)
{
int i;
for (i = 0; i < intf->num_altsetting; i++) {
if (intf->altsetting[i].desc.bAlternateSetting == altnum)
return &intf->altsetting[i];
}
return NULL;
}
EXPORT_SYMBOL_GPL(usb_altnum_to_altsetting);
struct find_interface_arg {
int minor;
struct device_driver *drv;
};
static int __find_interface(struct device *dev, void *data)
{
struct find_interface_arg *arg = data;
struct usb_interface *intf;
if (!is_usb_interface(dev))
return 0;
if (dev->driver != arg->drv)
return 0;
intf = to_usb_interface(dev);
return intf->minor == arg->minor;
}
/**
* usb_find_interface - find usb_interface pointer for driver and device
* @drv: the driver whose current configuration is considered
* @minor: the minor number of the desired device
*
* This walks the bus device list and returns a pointer to the interface
* with the matching minor and driver. Note, this only works for devices
* that share the USB major number.
*
* Return: A pointer to the interface with the matching major and @minor.
*/
struct usb_interface *usb_find_interface(struct usb_driver *drv, int minor)
{
struct find_interface_arg argb;
struct device *dev;
argb.minor = minor;
argb.drv = &drv->drvwrap.driver;
dev = bus_find_device(&usb_bus_type, NULL, &argb, __find_interface);
/* Drop reference count from bus_find_device */
put_device(dev);
return dev ? to_usb_interface(dev) : NULL;
}
EXPORT_SYMBOL_GPL(usb_find_interface);
struct each_dev_arg {
void *data;
int (*fn)(struct usb_device *, void *);
};
static int __each_dev(struct device *dev, void *data)
{
struct each_dev_arg *arg = (struct each_dev_arg *)data;
/* There are struct usb_interface on the same bus, filter them out */
if (!is_usb_device(dev))
return 0;
return arg->fn(to_usb_device(dev), arg->data);
}
/**
* usb_for_each_dev - iterate over all USB devices in the system
* @data: data pointer that will be handed to the callback function
* @fn: callback function to be called for each USB device
*
* Iterate over all USB devices and call @fn for each, passing it @data. If it
* returns anything other than 0, we break the iteration prematurely and return
* that value.
*/
int usb_for_each_dev(void *data, int (*fn)(struct usb_device *, void *))
{
struct each_dev_arg arg = {data, fn};
return bus_for_each_dev(&usb_bus_type, NULL, &arg, __each_dev);
}
EXPORT_SYMBOL_GPL(usb_for_each_dev);
/**
* usb_release_dev - free a usb device structure when all users of it are finished.
* @dev: device that's been disconnected
*
* Will be called only by the device core when all users of this usb device are
* done.
*/
static void usb_release_dev(struct device *dev)
{
struct usb_device *udev;
struct usb_hcd *hcd;
udev = to_usb_device(dev);
hcd = bus_to_hcd(udev->bus);
usb_destroy_configuration(udev);
usb_release_bos_descriptor(udev);
usb_put_hcd(hcd);
kfree(udev->product);
kfree(udev->manufacturer);
kfree(udev->serial);
kfree(udev);
}
static int usb_dev_uevent(struct device *dev, struct kobj_uevent_env *env)
{
struct usb_device *usb_dev;
usb_dev = to_usb_device(dev);
if (add_uevent_var(env, "BUSNUM=%03d", usb_dev->bus->busnum))
return -ENOMEM;
if (add_uevent_var(env, "DEVNUM=%03d", usb_dev->devnum))
return -ENOMEM;
return 0;
}
#ifdef CONFIG_PM
/* USB device Power-Management thunks.
* There's no need to distinguish here between quiescing a USB device
* and powering it down; the generic_suspend() routine takes care of
* it by skipping the usb_port_suspend() call for a quiesce. And for
* USB interfaces there's no difference at all.
*/
static int usb_dev_prepare(struct device *dev)
{
return 0; /* Implement eventually? */
}
static void usb_dev_complete(struct device *dev)
{
/* Currently used only for rebinding interfaces */
usb_resume_complete(dev);
}
static int usb_dev_suspend(struct device *dev)
{
return usb_suspend(dev, PMSG_SUSPEND);
}
static int usb_dev_resume(struct device *dev)
{
return usb_resume(dev, PMSG_RESUME);
}
static int usb_dev_freeze(struct device *dev)
{
return usb_suspend(dev, PMSG_FREEZE);
}
static int usb_dev_thaw(struct device *dev)
{
return usb_resume(dev, PMSG_THAW);
}
static int usb_dev_poweroff(struct device *dev)
{
return usb_suspend(dev, PMSG_HIBERNATE);
}
static int usb_dev_restore(struct device *dev)
{
return usb_resume(dev, PMSG_RESTORE);
}
static const struct dev_pm_ops usb_device_pm_ops = {
.prepare = usb_dev_prepare,
.complete = usb_dev_complete,
.suspend = usb_dev_suspend,
.resume = usb_dev_resume,
.freeze = usb_dev_freeze,
.thaw = usb_dev_thaw,
.poweroff = usb_dev_poweroff,
.restore = usb_dev_restore,
.runtime_suspend = usb_runtime_suspend,
.runtime_resume = usb_runtime_resume,
.runtime_idle = usb_runtime_idle,
};
#endif /* CONFIG_PM */
static char *usb_devnode(struct device *dev,
umode_t *mode, kuid_t *uid, kgid_t *gid)
{
struct usb_device *usb_dev;
usb_dev = to_usb_device(dev);
return kasprintf(GFP_KERNEL, "bus/usb/%03d/%03d",
usb_dev->bus->busnum, usb_dev->devnum);
}
struct device_type usb_device_type = {
.name = "usb_device",
.release = usb_release_dev,
.uevent = usb_dev_uevent,
.devnode = usb_devnode,
#ifdef CONFIG_PM
.pm = &usb_device_pm_ops,
#endif
};
/* Returns 1 if @usb_bus is WUSB, 0 otherwise */
static unsigned usb_bus_is_wusb(struct usb_bus *bus)
{
struct usb_hcd *hcd = bus_to_hcd(bus);
return hcd->wireless;
}
/**
* usb_alloc_dev - usb device constructor (usbcore-internal)
* @parent: hub to which device is connected; null to allocate a root hub
* @bus: bus used to access the device
* @port1: one-based index of port; ignored for root hubs
* Context: !in_interrupt()
*
* Only hub drivers (including virtual root hub drivers for host
* controllers) should ever call this.
*
* This call may not be used in a non-sleeping context.
*
* Return: On success, a pointer to the allocated usb device. %NULL on
* failure.
*/
struct usb_device *usb_alloc_dev(struct usb_device *parent,
struct usb_bus *bus, unsigned port1)
{
struct usb_device *dev;
struct usb_hcd *usb_hcd = bus_to_hcd(bus);
unsigned root_hub = 0;
unsigned raw_port = port1;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev)
return NULL;
if (!usb_get_hcd(usb_hcd)) {
kfree(dev);
return NULL;
}
/* Root hubs aren't true devices, so don't allocate HCD resources */
if (usb_hcd->driver->alloc_dev && parent &&
!usb_hcd->driver->alloc_dev(usb_hcd, dev)) {
usb_put_hcd(bus_to_hcd(bus));
kfree(dev);
return NULL;
}
device_initialize(&dev->dev);
dev->dev.bus = &usb_bus_type;
dev->dev.type = &usb_device_type;
dev->dev.groups = usb_device_groups;
/*
* Fake a dma_mask/offset for the USB device:
* We cannot really use the dma-mapping API (dma_alloc_* and
* dma_map_*) for USB devices but instead need to use
* usb_alloc_coherent and pass data in 'urb's, but some subsystems
* manually look into the mask/offset pair to determine whether
* they need bounce buffers.
* Note: calling dma_set_mask() on a USB device would set the
* mask for the entire HCD, so don't do that.
*/
dev->dev.dma_mask = bus->controller->dma_mask;
dev->dev.dma_pfn_offset = bus->controller->dma_pfn_offset;
set_dev_node(&dev->dev, dev_to_node(bus->controller));
dev->state = USB_STATE_ATTACHED;
dev->lpm_disable_count = 1;
atomic_set(&dev->urbnum, 0);
INIT_LIST_HEAD(&dev->ep0.urb_list);
dev->ep0.desc.bLength = USB_DT_ENDPOINT_SIZE;
dev->ep0.desc.bDescriptorType = USB_DT_ENDPOINT;
/* ep0 maxpacket comes later, from device descriptor */
usb_enable_endpoint(dev, &dev->ep0, false);
dev->can_submit = 1;
/* Save readable and stable topology id, distinguishing devices
* by location for diagnostics, tools, driver model, etc. The
* string is a path along hub ports, from the root. Each device's
* dev->devpath will be stable until USB is re-cabled, and hubs
* are often labeled with these port numbers. The name isn't
* as stable: bus->busnum changes easily from modprobe order,
* cardbus or pci hotplugging, and so on.
*/
if (unlikely(!parent)) {
dev->devpath[0] = '0';
dev->route = 0;
dev->dev.parent = bus->controller;
dev_set_name(&dev->dev, "usb%d", bus->busnum);
root_hub = 1;
} else {
/* match any labeling on the hubs; it's one-based */
if (parent->devpath[0] == '0') {
snprintf(dev->devpath, sizeof dev->devpath,
"%d", port1);
/* Root ports are not counted in route string */
dev->route = 0;
} else {
snprintf(dev->devpath, sizeof dev->devpath,
"%s.%d", parent->devpath, port1);
/* Route string assumes hubs have less than 16 ports */
if (port1 < 15)
dev->route = parent->route +
(port1 << ((parent->level - 1)*4));
else
dev->route = parent->route +
(15 << ((parent->level - 1)*4));
}
dev->dev.parent = &parent->dev;
dev_set_name(&dev->dev, "%d-%s", bus->busnum, dev->devpath);
if (!parent->parent) {
/* device under root hub's port */
raw_port = usb_hcd_find_raw_port_number(usb_hcd,
port1);
}
dev->dev.of_node = usb_of_get_child_node(parent->dev.of_node,
raw_port);
/* hub driver sets up TT records */
}
dev->portnum = port1;
dev->bus = bus;
dev->parent = parent;
INIT_LIST_HEAD(&dev->filelist);
#ifdef CONFIG_PM
pm_runtime_set_autosuspend_delay(&dev->dev,
usb_autosuspend_delay * 1000);
dev->connect_time = jiffies;
dev->active_duration = -jiffies;
#endif
if (root_hub) /* Root hub always ok [and always wired] */
dev->authorized = 1;
else {
dev->authorized = !!HCD_DEV_AUTHORIZED(usb_hcd);
dev->wusb = usb_bus_is_wusb(bus) ? 1 : 0;
}
return dev;
}
EXPORT_SYMBOL_GPL(usb_alloc_dev);
/**
* usb_get_dev - increments the reference count of the usb device structure
* @dev: the device being referenced
*
* Each live reference to a device should be refcounted.
*
* Drivers for USB interfaces should normally record such references in
* their probe() methods, when they bind to an interface, and release
* them by calling usb_put_dev(), in their disconnect() methods.
*
* Return: A pointer to the device with the incremented reference counter.
*/
struct usb_device *usb_get_dev(struct usb_device *dev)
{
if (dev)
get_device(&dev->dev);
return dev;
}
EXPORT_SYMBOL_GPL(usb_get_dev);
/**
* usb_put_dev - release a use of the usb device structure
* @dev: device that's been disconnected
*
* Must be called when a user of a device is finished with it. When the last
* user of the device calls this function, the memory of the device is freed.
*/
void usb_put_dev(struct usb_device *dev)
{
if (dev)
put_device(&dev->dev);
}
EXPORT_SYMBOL_GPL(usb_put_dev);
/**
* usb_get_intf - increments the reference count of the usb interface structure
* @intf: the interface being referenced
*
* Each live reference to a interface must be refcounted.
*
* Drivers for USB interfaces should normally record such references in
* their probe() methods, when they bind to an interface, and release
* them by calling usb_put_intf(), in their disconnect() methods.
*
* Return: A pointer to the interface with the incremented reference counter.
*/
struct usb_interface *usb_get_intf(struct usb_interface *intf)
{
if (intf)
get_device(&intf->dev);
return intf;
}
EXPORT_SYMBOL_GPL(usb_get_intf);
/**
* usb_put_intf - release a use of the usb interface structure
* @intf: interface that's been decremented
*
* Must be called when a user of an interface is finished with it. When the
* last user of the interface calls this function, the memory of the interface
* is freed.
*/
void usb_put_intf(struct usb_interface *intf)
{
if (intf)
put_device(&intf->dev);
}
EXPORT_SYMBOL_GPL(usb_put_intf);
/* USB device locking
*
* USB devices and interfaces are locked using the semaphore in their
* embedded struct device. The hub driver guarantees that whenever a
* device is connected or disconnected, drivers are called with the
* USB device locked as well as their particular interface.
*
* Complications arise when several devices are to be locked at the same
* time. Only hub-aware drivers that are part of usbcore ever have to
* do this; nobody else needs to worry about it. The rule for locking
* is simple:
*
* When locking both a device and its parent, always lock the
* the parent first.
*/
/**
* usb_lock_device_for_reset - cautiously acquire the lock for a usb device structure
* @udev: device that's being locked
* @iface: interface bound to the driver making the request (optional)
*
* Attempts to acquire the device lock, but fails if the device is
* NOTATTACHED or SUSPENDED, or if iface is specified and the interface
* is neither BINDING nor BOUND. Rather than sleeping to wait for the
* lock, the routine polls repeatedly. This is to prevent deadlock with
* disconnect; in some drivers (such as usb-storage) the disconnect()
* or suspend() method will block waiting for a device reset to complete.
*
* Return: A negative error code for failure, otherwise 0.
*/
int usb_lock_device_for_reset(struct usb_device *udev,
const struct usb_interface *iface)
{
unsigned long jiffies_expire = jiffies + HZ;
if (udev->state == USB_STATE_NOTATTACHED)
return -ENODEV;
if (udev->state == USB_STATE_SUSPENDED)
return -EHOSTUNREACH;
if (iface && (iface->condition == USB_INTERFACE_UNBINDING ||
iface->condition == USB_INTERFACE_UNBOUND))
return -EINTR;
while (!usb_trylock_device(udev)) {
/* If we can't acquire the lock after waiting one second,
* we're probably deadlocked */
if (time_after(jiffies, jiffies_expire))
return -EBUSY;
msleep(15);
if (udev->state == USB_STATE_NOTATTACHED)
return -ENODEV;
if (udev->state == USB_STATE_SUSPENDED)
return -EHOSTUNREACH;
if (iface && (iface->condition == USB_INTERFACE_UNBINDING ||
iface->condition == USB_INTERFACE_UNBOUND))
return -EINTR;
}
return 0;
}
EXPORT_SYMBOL_GPL(usb_lock_device_for_reset);
/**
* usb_get_current_frame_number - return current bus frame number
* @dev: the device whose bus is being queried
*
* Return: The current frame number for the USB host controller used
* with the given USB device. This can be used when scheduling
* isochronous requests.
*
* Note: Different kinds of host controller have different "scheduling
* horizons". While one type might support scheduling only 32 frames
* into the future, others could support scheduling up to 1024 frames
* into the future.
*
*/
int usb_get_current_frame_number(struct usb_device *dev)
{
return usb_hcd_get_frame_number(dev);
}
EXPORT_SYMBOL_GPL(usb_get_current_frame_number);
/*-------------------------------------------------------------------*/
/*
* __usb_get_extra_descriptor() finds a descriptor of specific type in the
* extra field of the interface and endpoint descriptor structs.
*/
EXPORT_SYMBOL_GPL(__usb_get_extra_descriptor);
/**
* usb_alloc_coherent - allocate dma-consistent buffer for URB_NO_xxx_DMA_MAP
* @dev: device the buffer will be used with
* @size: requested buffer size
* @mem_flags: affect whether allocation may block
* @dma: used to return DMA address of buffer
*
* Return: Either null (indicating no buffer could be allocated), or the
* cpu-space pointer to a buffer that may be used to perform DMA to the
* specified device. Such cpu-space buffers are returned along with the DMA
* address (through the pointer provided).
*
* Note:
* These buffers are used with URB_NO_xxx_DMA_MAP set in urb->transfer_flags
* to avoid behaviors like using "DMA bounce buffers", or thrashing IOMMU
* hardware during URB completion/resubmit. The implementation varies between
* platforms, depending on details of how DMA will work to this device.
* Using these buffers also eliminates cacheline sharing problems on
* architectures where CPU caches are not DMA-coherent. On systems without
* bus-snooping caches, these buffers are uncached.
*
* When the buffer is no longer used, free it with usb_free_coherent().
*/
void *usb_alloc_coherent(struct usb_device *dev, size_t size, gfp_t mem_flags,
dma_addr_t *dma)
{
if (!dev || !dev->bus)
return NULL;
return hcd_buffer_alloc(dev->bus, size, mem_flags, dma);
}
EXPORT_SYMBOL_GPL(usb_alloc_coherent);
/**
* usb_free_coherent - free memory allocated with usb_alloc_coherent()
* @dev: device the buffer was used with
* @size: requested buffer size
* @addr: CPU address of buffer
* @dma: DMA address of buffer
*
* This reclaims an I/O buffer, letting it be reused. The memory must have
* been allocated using usb_alloc_coherent(), and the parameters must match
* those provided in that allocation request.
*/
void usb_free_coherent(struct usb_device *dev, size_t size, void *addr,
dma_addr_t dma)
{
if (!dev || !dev->bus)
return;
if (!addr)
return;
hcd_buffer_free(dev->bus, size, addr, dma);
}
EXPORT_SYMBOL_GPL(usb_free_coherent);
/**
* usb_buffer_map - create DMA mapping(s) for an urb
* @urb: urb whose transfer_buffer/setup_packet will be mapped
*
* URB_NO_TRANSFER_DMA_MAP is added to urb->transfer_flags if the operation
* succeeds. If the device is connected to this system through a non-DMA
* controller, this operation always succeeds.
*
* This call would normally be used for an urb which is reused, perhaps
* as the target of a large periodic transfer, with usb_buffer_dmasync()
* calls to synchronize memory and dma state.
*
* Reverse the effect of this call with usb_buffer_unmap().
*
* Return: Either %NULL (indicating no buffer could be mapped), or @urb.
*
*/
#if 0
struct urb *usb_buffer_map(struct urb *urb)
{
struct usb_bus *bus;
struct device *controller;
if (!urb
|| !urb->dev
|| !(bus = urb->dev->bus)
|| !(controller = bus->controller))
return NULL;
if (controller->dma_mask) {
urb->transfer_dma = dma_map_single(controller,
urb->transfer_buffer, urb->transfer_buffer_length,
usb_pipein(urb->pipe)
? DMA_FROM_DEVICE : DMA_TO_DEVICE);
/* FIXME generic api broken like pci, can't report errors */
/* if (urb->transfer_dma == DMA_ADDR_INVALID) return 0; */
} else
urb->transfer_dma = ~0;
urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
return urb;
}
EXPORT_SYMBOL_GPL(usb_buffer_map);
#endif /* 0 */
/* XXX DISABLED, no users currently. If you wish to re-enable this
* XXX please determine whether the sync is to transfer ownership of
* XXX the buffer from device to cpu or vice verse, and thusly use the
* XXX appropriate _for_{cpu,device}() method. -DaveM
*/
#if 0
/**
* usb_buffer_dmasync - synchronize DMA and CPU view of buffer(s)
* @urb: urb whose transfer_buffer/setup_packet will be synchronized
*/
void usb_buffer_dmasync(struct urb *urb)
{
struct usb_bus *bus;
struct device *controller;
if (!urb
|| !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)
|| !urb->dev
|| !(bus = urb->dev->bus)
|| !(controller = bus->controller))
return;
if (controller->dma_mask) {
dma_sync_single_for_cpu(controller,
urb->transfer_dma, urb->transfer_buffer_length,
usb_pipein(urb->pipe)
? DMA_FROM_DEVICE : DMA_TO_DEVICE);
if (usb_pipecontrol(urb->pipe))
dma_sync_single_for_cpu(controller,
urb->setup_dma,
sizeof(struct usb_ctrlrequest),
DMA_TO_DEVICE);
}
}
EXPORT_SYMBOL_GPL(usb_buffer_dmasync);
#endif
/**
* usb_buffer_unmap - free DMA mapping(s) for an urb
* @urb: urb whose transfer_buffer will be unmapped
*
* Reverses the effect of usb_buffer_map().
*/
#if 0
void usb_buffer_unmap(struct urb *urb)
{
struct usb_bus *bus;
struct device *controller;
if (!urb
|| !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)
|| !urb->dev
|| !(bus = urb->dev->bus)
|| !(controller = bus->controller))
return;
if (controller->dma_mask) {
dma_unmap_single(controller,
urb->transfer_dma, urb->transfer_buffer_length,
usb_pipein(urb->pipe)
? DMA_FROM_DEVICE : DMA_TO_DEVICE);
}
urb->transfer_flags &= ~URB_NO_TRANSFER_DMA_MAP;
}
EXPORT_SYMBOL_GPL(usb_buffer_unmap);
#endif /* 0 */
#if 0
/**
* usb_buffer_map_sg - create scatterlist DMA mapping(s) for an endpoint
* @dev: device to which the scatterlist will be mapped
* @is_in: mapping transfer direction
* @sg: the scatterlist to map
* @nents: the number of entries in the scatterlist
*
* Return: Either < 0 (indicating no buffers could be mapped), or the
* number of DMA mapping array entries in the scatterlist.
*
* Note:
* The caller is responsible for placing the resulting DMA addresses from
* the scatterlist into URB transfer buffer pointers, and for setting the
* URB_NO_TRANSFER_DMA_MAP transfer flag in each of those URBs.
*
* Top I/O rates come from queuing URBs, instead of waiting for each one
* to complete before starting the next I/O. This is particularly easy
* to do with scatterlists. Just allocate and submit one URB for each DMA
* mapping entry returned, stopping on the first error or when all succeed.
* Better yet, use the usb_sg_*() calls, which do that (and more) for you.
*
* This call would normally be used when translating scatterlist requests,
* rather than usb_buffer_map(), since on some hardware (with IOMMUs) it
* may be able to coalesce mappings for improved I/O efficiency.
*
* Reverse the effect of this call with usb_buffer_unmap_sg().
*/
int usb_buffer_map_sg(const struct usb_device *dev, int is_in,
struct scatterlist *sg, int nents)
{
struct usb_bus *bus;
struct device *controller;
if (!dev
|| !(bus = dev->bus)
|| !(controller = bus->controller)
|| !controller->dma_mask)
return -EINVAL;
/* FIXME generic api broken like pci, can't report errors */
return dma_map_sg(controller, sg, nents,
is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE) ? : -ENOMEM;
}
EXPORT_SYMBOL_GPL(usb_buffer_map_sg);
#endif
/* XXX DISABLED, no users currently. If you wish to re-enable this
* XXX please determine whether the sync is to transfer ownership of
* XXX the buffer from device to cpu or vice verse, and thusly use the
* XXX appropriate _for_{cpu,device}() method. -DaveM
*/
#if 0
/**
* usb_buffer_dmasync_sg - synchronize DMA and CPU view of scatterlist buffer(s)
* @dev: device to which the scatterlist will be mapped
* @is_in: mapping transfer direction
* @sg: the scatterlist to synchronize
* @n_hw_ents: the positive return value from usb_buffer_map_sg
*
* Use this when you are re-using a scatterlist's data buffers for
* another USB request.
*/
void usb_buffer_dmasync_sg(const struct usb_device *dev, int is_in,
struct scatterlist *sg, int n_hw_ents)
{
struct usb_bus *bus;
struct device *controller;
if (!dev
|| !(bus = dev->bus)
|| !(controller = bus->controller)
|| !controller->dma_mask)
return;
dma_sync_sg_for_cpu(controller, sg, n_hw_ents,
is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
}
EXPORT_SYMBOL_GPL(usb_buffer_dmasync_sg);
#endif
#if 0
/**
* usb_buffer_unmap_sg - free DMA mapping(s) for a scatterlist
* @dev: device to which the scatterlist will be mapped
* @is_in: mapping transfer direction
* @sg: the scatterlist to unmap
* @n_hw_ents: the positive return value from usb_buffer_map_sg
*
* Reverses the effect of usb_buffer_map_sg().
*/
void usb_buffer_unmap_sg(const struct usb_device *dev, int is_in,
struct scatterlist *sg, int n_hw_ents)
{
struct usb_bus *bus;
struct device *controller;
if (!dev
|| !(bus = dev->bus)
|| !(controller = bus->controller)
|| !controller->dma_mask)
return;
dma_unmap_sg(controller, sg, n_hw_ents,
is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
}
EXPORT_SYMBOL_GPL(usb_buffer_unmap_sg);
#endif
/*
* Notifications of device and interface registration
*/
static int usb_bus_notify(struct notifier_block *nb, unsigned long action,
void *data)
{
struct device *dev = data;
switch (action) {
case BUS_NOTIFY_ADD_DEVICE:
if (dev->type == &usb_device_type)
(void) usb_create_sysfs_dev_files(to_usb_device(dev));
else if (dev->type == &usb_if_device_type)
usb_create_sysfs_intf_files(to_usb_interface(dev));
break;
case BUS_NOTIFY_DEL_DEVICE:
if (dev->type == &usb_device_type)
usb_remove_sysfs_dev_files(to_usb_device(dev));
else if (dev->type == &usb_if_device_type)
usb_remove_sysfs_intf_files(to_usb_interface(dev));
break;
}
return 0;
}
static struct notifier_block usb_bus_nb = {
.notifier_call = usb_bus_notify,
};
struct dentry *usb_debug_root;
EXPORT_SYMBOL_GPL(usb_debug_root);
static struct dentry *usb_debug_devices;
static int usb_debugfs_init(void)
{
usb_debug_root = debugfs_create_dir("usb", NULL);
if (!usb_debug_root)
return -ENOENT;
usb_debug_devices = debugfs_create_file("devices", 0444,
usb_debug_root, NULL,
&usbfs_devices_fops);
if (!usb_debug_devices) {
debugfs_remove(usb_debug_root);
usb_debug_root = NULL;
return -ENOENT;
}
return 0;
}
static void usb_debugfs_cleanup(void)
{
debugfs_remove(usb_debug_devices);
debugfs_remove(usb_debug_root);
}
/*
* Init
*/
static int __init usb_init(void)
{
int retval;
if (usb_disabled()) {
pr_info("%s: USB support disabled\n", usbcore_name);
return 0;
}
usb_init_pool_max();
retval = usb_debugfs_init();
if (retval)
goto out;
usb_acpi_register();
retval = bus_register(&usb_bus_type);
if (retval)
goto bus_register_failed;
retval = bus_register_notifier(&usb_bus_type, &usb_bus_nb);
if (retval)
goto bus_notifier_failed;
retval = usb_major_init();
if (retval)
goto major_init_failed;
retval = usb_register(&usbfs_driver);
if (retval)
goto driver_register_failed;
retval = usb_devio_init();
if (retval)
goto usb_devio_init_failed;
retval = usb_hub_init();
if (retval)
goto hub_init_failed;
retval = usb_register_device_driver(&usb_generic_driver, THIS_MODULE);
if (!retval)
goto out;
usb_hub_cleanup();
hub_init_failed:
usb_devio_cleanup();
usb_devio_init_failed:
usb_deregister(&usbfs_driver);
driver_register_failed:
usb_major_cleanup();
major_init_failed:
bus_unregister_notifier(&usb_bus_type, &usb_bus_nb);
bus_notifier_failed:
bus_unregister(&usb_bus_type);
bus_register_failed:
usb_acpi_unregister();
usb_debugfs_cleanup();
out:
return retval;
}
/*
* Cleanup
*/
static void __exit usb_exit(void)
{
/* This will matter if shutdown/reboot does exitcalls. */
if (usb_disabled())
return;
usb_deregister_device_driver(&usb_generic_driver);
usb_major_cleanup();
usb_deregister(&usbfs_driver);
usb_devio_cleanup();
usb_hub_cleanup();
bus_unregister_notifier(&usb_bus_type, &usb_bus_nb);
bus_unregister(&usb_bus_type);
usb_acpi_unregister();
usb_debugfs_cleanup();
idr_destroy(&usb_bus_idr);
}
subsys_initcall(usb_init);
module_exit(usb_exit);
MODULE_LICENSE("GPL");
| null | null | null | null | 103,018 |
30,530 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 30,530 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef THIRD_PARTY_WEBKIT_PUBLIC_PLATFORM_SCHEDULER_WEB_MAIN_THREAD_SCHEDULER_H_
#define THIRD_PARTY_WEBKIT_PUBLIC_PLATFORM_SCHEDULER_WEB_MAIN_THREAD_SCHEDULER_H_
#include <memory>
#include "base/macros.h"
#include "base/message_loop/message_loop.h"
#include "base/optional.h"
#include "base/single_thread_task_runner.h"
#include "base/threading/thread.h"
#include "base/time/time.h"
#include "build/build_config.h"
#include "third_party/blink/public/platform/scheduler/single_thread_idle_task_runner.h"
#include "third_party/blink/public/platform/scheduler/web_render_widget_scheduling_state.h"
#include "third_party/blink/public/platform/scheduler/web_thread_scheduler.h"
#include "third_party/blink/public/platform/web_common.h"
#include "third_party/blink/public/platform/web_input_event_result.h"
#include "third_party/blink/public/platform/web_scoped_virtual_time_pauser.h"
#include "v8/include/v8.h"
namespace base {
namespace trace_event {
class BlameContext;
}
} // namespace base
namespace blink {
class WebThread;
class WebInputEvent;
} // namespace blink
namespace viz {
struct BeginFrameArgs;
}
namespace blink {
namespace scheduler {
enum class RendererProcessType;
class WebRenderWidgetSchedulingState;
class BLINK_PLATFORM_EXPORT WebMainThreadScheduler : public WebThreadScheduler {
public:
class BLINK_PLATFORM_EXPORT RAILModeObserver {
public:
virtual ~RAILModeObserver();
virtual void OnRAILModeChanged(v8::RAILMode rail_mode) = 0;
};
~WebMainThreadScheduler() override;
// If |initial_virtual_time| is specified then the scheduler will be created
// with virtual time enabled and paused, and base::Time will be overridden to
// start at |initial_virtual_time|.
static std::unique_ptr<WebMainThreadScheduler> Create(
base::Optional<base::Time> initial_virtual_time = base::nullopt);
// Returns the compositor task runner.
virtual scoped_refptr<base::SingleThreadTaskRunner>
CompositorTaskRunner() = 0;
// Returns the input task runner.
virtual scoped_refptr<base::SingleThreadTaskRunner> InputTaskRunner() = 0;
// Creates a WebThread implementation for the renderer main thread.
virtual std::unique_ptr<WebThread> CreateMainThread() = 0;
// Returns a new WebRenderWidgetSchedulingState. The signals from this will
// be used to make scheduling decisions.
virtual std::unique_ptr<WebRenderWidgetSchedulingState>
NewRenderWidgetSchedulingState() = 0;
// Called to notify about the start of an extended period where no frames
// need to be drawn. Must be called from the main thread.
virtual void BeginFrameNotExpectedSoon() = 0;
// Called to notify about the start of a period where main frames are not
// scheduled and so short idle work can be scheduled. This will precede
// BeginFrameNotExpectedSoon and is also called when the compositor may be
// busy but the main thread is not.
virtual void BeginMainFrameNotExpectedUntil(base::TimeTicks time) = 0;
// Called to notify about the start of a new frame. Must be called from the
// main thread.
virtual void WillBeginFrame(const viz::BeginFrameArgs& args) = 0;
// Called to notify that a previously begun frame was committed. Must be
// called from the main thread.
virtual void DidCommitFrameToCompositor() = 0;
// Keep InputEventStateToString() in sync with this enum.
enum class InputEventState {
EVENT_CONSUMED_BY_COMPOSITOR,
EVENT_FORWARDED_TO_MAIN_THREAD,
};
static const char* InputEventStateToString(InputEventState input_event_state);
// Tells the scheduler that the system processed an input event. Called by the
// compositor (impl) thread. Note it's expected that every call to
// DidHandleInputEventOnCompositorThread where |event_state| is
// EVENT_FORWARDED_TO_MAIN_THREAD will be followed by a corresponding call
// to DidHandleInputEventOnMainThread.
virtual void DidHandleInputEventOnCompositorThread(
const WebInputEvent& web_input_event,
InputEventState event_state) = 0;
// Tells the scheduler that the system processed an input event. Must be
// called from the main thread.
virtual void DidHandleInputEventOnMainThread(
const WebInputEvent& web_input_event,
WebInputEventResult result) = 0;
// Returns the most recently reported expected queueing time, computed over
// the past 1 second window.
virtual base::TimeDelta MostRecentExpectedQueueingTime() = 0;
// Tells the scheduler that the system is displaying an input animation (e.g.
// a fling). Called by the compositor (impl) thread.
virtual void DidAnimateForInputOnCompositorThread() = 0;
// Tells the scheduler about the change of renderer visibility status (e.g.
// "all widgets are hidden" condition). Used mostly for metric purposes.
// Must be called on the main thread.
virtual void SetRendererHidden(bool hidden) = 0;
// Tells the scheduler about the change of renderer background status, i.e.,
// there are no critical, user facing activities (visual, audio, etc...)
// driven by this process. A stricter condition than |SetRendererHidden()|,
// the process is assumed to be foregrounded when the scheduler is
// constructed. Must be called on the main thread.
virtual void SetRendererBackgrounded(bool backgrounded) = 0;
// Tells the scheduler about "keep-alive" state which can be due to:
// service workers, shared workers, or fetch keep-alive.
// If set to true, then the scheduler should not freeze the renderer.
virtual void SetSchedulerKeepActive(bool keep_active) = 0;
#if defined(OS_ANDROID)
// Android WebView has very strange WebView.pauseTimers/resumeTimers API.
// It's very old and very inconsistent. The API promises that this
// "pauses all layout, parsing, and JavaScript timers for all WebViews".
// Also CTS tests expect that loading tasks continue to run.
// We should change it to something consistent (e.g. stop all javascript)
// but changing WebView and CTS is a slow and painful process, so for
// the time being we're doing our best.
// DO NOT USE FOR ANYTHING EXCEPT ANDROID WEBVIEW API IMPLEMENTATION.
virtual void PauseTimersForAndroidWebView() = 0;
virtual void ResumeTimersForAndroidWebView() = 0;
#endif // defined(OS_ANDROID)
// RAII handle for pausing the renderer. Renderer is paused while
// at least one pause handle exists.
class BLINK_PLATFORM_EXPORT RendererPauseHandle {
public:
RendererPauseHandle() = default;
virtual ~RendererPauseHandle() = default;
private:
DISALLOW_COPY_AND_ASSIGN(RendererPauseHandle);
};
// Tells the scheduler that the renderer process should be paused.
// Pausing means that all javascript callbacks should not fire.
// https://html.spec.whatwg.org/#pause
//
// Renderer will be resumed when the handle is destroyed.
// Handle should be destroyed before the renderer.
virtual std::unique_ptr<RendererPauseHandle> PauseRenderer()
WARN_UNUSED_RESULT = 0;
enum class NavigatingFrameType { kMainFrame, kChildFrame };
// Tells the scheduler that a navigation task is pending. While any main-frame
// navigation tasks are pending, the scheduler will ensure that loading tasks
// are not blocked even if they are expensive. Must be called on the main
// thread.
virtual void AddPendingNavigation(NavigatingFrameType type) = 0;
// Tells the scheduler that a navigation task is no longer pending.
// Must be called on the main thread.
virtual void RemovePendingNavigation(NavigatingFrameType type) = 0;
// Returns true if the scheduler has reason to believe that high priority work
// may soon arrive on the main thread, e.g., if gesture events were observed
// recently.
// Must be called from the main thread.
virtual bool IsHighPriorityWorkAnticipated() = 0;
// Sets whether to allow suspension of tasks after the backgrounded signal is
// received via SetRendererBackgrounded(true). Defaults to disabled.
virtual void SetStoppingWhenBackgroundedEnabled(bool enabled) = 0;
// Sets the default blame context to which top level work should be
// attributed in this renderer. |blame_context| must outlive this scheduler.
virtual void SetTopLevelBlameContext(
base::trace_event::BlameContext* blame_context) = 0;
// The renderer scheduler maintains an estimated RAIL mode[1]. This observer
// can be used to get notified when the mode changes. The observer will be
// called on the main thread and must outlive this class.
// [1]
// https://developers.google.com/web/tools/chrome-devtools/profile/evaluate-performance/rail
virtual void SetRAILModeObserver(RAILModeObserver* observer) = 0;
// Returns whether or not the main thread appears unresponsive, based on the
// length and frequency of recent main thread tasks. To be called from the
// compositor thread.
virtual bool MainThreadSeemsUnresponsive(
base::TimeDelta main_thread_responsiveness_threshold) = 0;
// Sets the kind of renderer process. Should be called on the main thread
// once.
virtual void SetRendererProcessType(RendererProcessType type) = 0;
// Returns a WebScopedVirtualTimePauser which can be used to vote for pausing
// virtual time. Virtual time will be paused if any WebScopedVirtualTimePauser
// votes to pause it, and only unpaused only if all
// WebScopedVirtualTimePausers are either destroyed or vote to unpause. Note
// the WebScopedVirtualTimePauser returned by this method is initially
// unpaused.
virtual WebScopedVirtualTimePauser CreateWebScopedVirtualTimePauser(
const char* name,
WebScopedVirtualTimePauser::VirtualTaskDuration duration =
WebScopedVirtualTimePauser::VirtualTaskDuration::kNonInstant) = 0;
protected:
WebMainThreadScheduler();
DISALLOW_COPY_AND_ASSIGN(WebMainThreadScheduler);
};
} // namespace scheduler
} // namespace blink
#endif // THIRD_PARTY_WEBKIT_PUBLIC_PLATFORM_SCHEDULER_WEB_MAIN_THREAD_SCHEDULER_H_
| null | null | null | null | 27,393 |
23,070 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 23,070 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2017 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "content/browser/service_worker/service_worker_navigation_loader.h"
#include "base/run_loop.h"
#include "base/test/scoped_feature_list.h"
#include "content/browser/loader/navigation_loader_interceptor.h"
#include "content/browser/service_worker/embedded_worker_test_helper.h"
#include "content/browser/service_worker/service_worker_context_core.h"
#include "content/browser/service_worker/service_worker_registration.h"
#include "content/browser/service_worker/service_worker_test_utils.h"
#include "content/browser/service_worker/service_worker_version.h"
#include "content/common/service_worker/service_worker_event_dispatcher.mojom.h"
#include "content/common/service_worker/service_worker_utils.h"
#include "content/common/single_request_url_loader_factory.h"
#include "content/public/test/test_browser_thread_bundle.h"
#include "mojo/public/cpp/bindings/strong_binding.h"
#include "mojo/public/cpp/system/data_pipe_utils.h"
#include "net/http/http_util.h"
#include "net/ssl/ssl_info.h"
#include "net/test/cert_test_util.h"
#include "net/test/test_data_directory.h"
#include "services/network/public/cpp/features.h"
#include "services/network/public/cpp/resource_response.h"
#include "services/network/public/mojom/fetch_api.mojom.h"
#include "services/network/test/test_url_loader_client.h"
#include "storage/browser/blob/blob_data_builder.h"
#include "storage/browser/blob/blob_data_handle.h"
#include "storage/browser/blob/blob_impl.h"
#include "storage/browser/blob/blob_storage_context.h"
#include "testing/gtest/include/gtest/gtest.h"
#include "third_party/blink/public/mojom/service_worker/service_worker_event_status.mojom.h"
#include "third_party/blink/public/mojom/service_worker/service_worker_registration.mojom.h"
namespace content {
namespace service_worker_navigation_loader_unittest {
void ReceiveRequestHandler(
SingleRequestURLLoaderFactory::RequestHandler* out_handler,
SingleRequestURLLoaderFactory::RequestHandler handler) {
*out_handler = std::move(handler);
}
// NavigationPreloadLoaderClient mocks the renderer-side URLLoaderClient for the
// navigation preload network request performed by the browser. In production
// code, this is ServiceWorkerContextClient::NavigationPreloadRequest,
// which it forwards the response to FetchEvent#preloadResponse. Here, it
// simulates passing the response to FetchEvent#respondWith.
//
// The navigation preload test is quite involved. The flow of data is:
// 1. ServiceWorkerNavigationLoader asks ServiceWorkerFetchDispatcher to start
// navigation preload.
// 2. ServiceWorkerFetchDispatcher starts the network request which is mocked
// by MockNetworkURLLoaderFactory. The response is sent to
// ServiceWorkerFetchDispatcher::DelegatingURLLoaderClient.
// 3. DelegatingURLLoaderClient sends the response to the |preload_handle|
// that was passed to Helper::OnFetchEvent().
// 4. Helper::OnFetchEvent() creates NavigationPreloadLoaderClient, which
// receives the response.
// 5. NavigationPreloadLoaderClient calls OnFetchEvent()'s callbacks
// with the response.
// 6. Like all FetchEvent responses, the response is sent to
// ServiceWorkerNavigationLoader::DidDispatchFetchEvent, and the
// RequestHandler is returned.
class NavigationPreloadLoaderClient final
: public network::mojom::URLLoaderClient {
public:
NavigationPreloadLoaderClient(
mojom::FetchEventPreloadHandlePtr preload_handle,
mojom::ServiceWorkerFetchResponseCallbackPtr response_callback,
mojom::ServiceWorkerEventDispatcher::DispatchFetchEventCallback
finish_callback)
: url_loader_(std::move(preload_handle->url_loader)),
binding_(this, std::move(preload_handle->url_loader_client_request)),
response_callback_(std::move(response_callback)),
finish_callback_(std::move(finish_callback)) {
binding_.set_connection_error_handler(
base::BindOnce(&NavigationPreloadLoaderClient::OnConnectionError,
base::Unretained(this)));
}
~NavigationPreloadLoaderClient() override = default;
// network::mojom::URLLoaderClient implementation
void OnReceiveResponse(
const network::ResourceResponseHead& response_head,
network::mojom::DownloadedTempFilePtr downloaded_file) override {
response_head_ = response_head;
}
void OnStartLoadingResponseBody(
mojo::ScopedDataPipeConsumerHandle body) override {
body_ = std::move(body);
// We could call OnResponseStream() here, but for simplicity, don't do
// anything until OnComplete().
}
void OnComplete(const network::URLLoaderCompletionStatus& status) override {
blink::mojom::ServiceWorkerStreamCallbackPtr stream_callback;
auto stream_handle = blink::mojom::ServiceWorkerStreamHandle::New();
stream_handle->callback_request = mojo::MakeRequest(&stream_callback);
stream_handle->stream = std::move(body_);
// Simulate passing the navigation preload response to
// FetchEvent#respondWith.
response_callback_->OnResponseStream(
ServiceWorkerResponse(
std::make_unique<std::vector<GURL>>(
response_head_.url_list_via_service_worker),
response_head_.headers->response_code(),
response_head_.headers->GetStatusText(),
response_head_.response_type_via_service_worker,
std::make_unique<ServiceWorkerHeaderMap>(), "" /* blob_uuid */,
0 /* blob_size */, nullptr /* blob */,
blink::mojom::ServiceWorkerResponseError::kUnknown, base::Time(),
false /* response_is_in_cache_storage */,
std::string() /* response_cache_storage_cache_name */,
std::make_unique<
ServiceWorkerHeaderList>() /* cors_exposed_header_names */),
std::move(stream_handle), base::Time::Now());
std::move(finish_callback_)
.Run(blink::mojom::ServiceWorkerEventStatus::COMPLETED,
base::Time::Now());
stream_callback->OnCompleted();
delete this;
}
void OnReceiveRedirect(
const net::RedirectInfo& redirect_info,
const network::ResourceResponseHead& response_head) override {}
void OnDataDownloaded(int64_t data_length,
int64_t encoded_data_length) override {}
void OnUploadProgress(int64_t current_position,
int64_t total_size,
OnUploadProgressCallback ack_callback) override {}
void OnReceiveCachedMetadata(const std::vector<uint8_t>& data) override {}
void OnTransferSizeUpdated(int32_t transfer_size_diff) override {}
void OnConnectionError() { delete this; }
private:
network::mojom::URLLoaderPtr url_loader_;
mojo::Binding<network::mojom::URLLoaderClient> binding_;
network::ResourceResponseHead response_head_;
mojo::ScopedDataPipeConsumerHandle body_;
// Callbacks that complete Helper::OnFetchEvent().
mojom::ServiceWorkerFetchResponseCallbackPtr response_callback_;
mojom::ServiceWorkerEventDispatcher::DispatchFetchEventCallback
finish_callback_;
DISALLOW_COPY_AND_ASSIGN(NavigationPreloadLoaderClient);
};
// A URLLoaderFactory that returns 200 OK with a simple body to any request.
//
// ServiceWorkerNavigationLoaderTest sets the network factory for
// ServiceWorkerContextCore to MockNetworkURLLoaderFactory. So far, it's only
// used for navigation preload in these tests.
class MockNetworkURLLoaderFactory final
: public network::mojom::URLLoaderFactory {
public:
MockNetworkURLLoaderFactory() = default;
// network::mojom::URLLoaderFactory implementation.
void CreateLoaderAndStart(network::mojom::URLLoaderRequest request,
int32_t routing_id,
int32_t request_id,
uint32_t options,
const network::ResourceRequest& url_request,
network::mojom::URLLoaderClientPtr client,
const net::MutableNetworkTrafficAnnotationTag&
traffic_annotation) override {
std::string headers = "HTTP/1.1 200 OK\n\n";
net::HttpResponseInfo info;
info.headers = new net::HttpResponseHeaders(
net::HttpUtil::AssembleRawHeaders(headers.c_str(), headers.length()));
network::ResourceResponseHead response;
response.headers = info.headers;
response.headers->GetMimeType(&response.mime_type);
client->OnReceiveResponse(response, nullptr);
std::string body = "this body came from the network";
uint32_t bytes_written = body.size();
mojo::DataPipe data_pipe;
data_pipe.producer_handle->WriteData(body.data(), &bytes_written,
MOJO_WRITE_DATA_FLAG_ALL_OR_NONE);
client->OnStartLoadingResponseBody(std::move(data_pipe.consumer_handle));
network::URLLoaderCompletionStatus status;
status.error_code = net::OK;
client->OnComplete(status);
}
void Clone(network::mojom::URLLoaderFactoryRequest factory) override {
NOTREACHED();
}
private:
DISALLOW_COPY_AND_ASSIGN(MockNetworkURLLoaderFactory);
};
// Helper simulates a service worker handling fetch events. The response can be
// customized via RespondWith* functions.
class Helper : public EmbeddedWorkerTestHelper {
public:
Helper()
: EmbeddedWorkerTestHelper(
base::FilePath(),
base::MakeRefCounted<URLLoaderFactoryGetter>()) {
url_loader_factory_getter()->SetNetworkFactoryForTesting(
&mock_url_loader_factory_);
}
~Helper() override = default;
// Tells this helper to respond to fetch events with the specified blob.
void RespondWithBlob(blink::mojom::BlobPtr blob) {
response_mode_ = ResponseMode::kBlob;
blob_body_ = std::move(blob);
}
// Tells this helper to respond to fetch events with the specified stream.
void RespondWithStream(
blink::mojom::ServiceWorkerStreamCallbackRequest callback_request,
mojo::ScopedDataPipeConsumerHandle consumer_handle) {
response_mode_ = ResponseMode::kStream;
stream_handle_ = blink::mojom::ServiceWorkerStreamHandle::New();
stream_handle_->callback_request = std::move(callback_request);
stream_handle_->stream = std::move(consumer_handle);
}
// Tells this helper to respond to fetch events with network fallback.
// i.e., simulate the service worker not calling respondWith().
void RespondWithFallback() {
response_mode_ = ResponseMode::kFallbackResponse;
}
// Tells this helper to respond to fetch events with an error response.
void RespondWithError() { response_mode_ = ResponseMode::kErrorResponse; }
// Tells this helper to respond to fetch events with
// FetchEvent#preloadResponse. See NavigationPreloadLoaderClient's
// documentation for details.
void RespondWithNavigationPreloadResponse() {
response_mode_ = ResponseMode::kNavigationPreloadResponse;
}
// Tells this helper to respond to fetch events with the redirect response.
void RespondWithRedirectResponse(const GURL& new_url) {
response_mode_ = ResponseMode::kRedirect;
redirected_url_ = new_url;
}
// Tells this helper to simulate failure to dispatch the fetch event to the
// service worker.
void FailToDispatchFetchEvent() {
response_mode_ = ResponseMode::kFailFetchEventDispatch;
}
// Tells this helper to simulate "early response", where the respondWith()
// promise resolves before the waitUntil() promise. In this mode, the
// helper sets the response mode to "early response", which simulates the
// promise passed to respondWith() resolving before the waitUntil() promise
// resolves. In this mode, the helper will respond to fetch events
// immediately, but will not finish the fetch event until FinishWaitUntil() is
// called.
void RespondEarly() { response_mode_ = ResponseMode::kEarlyResponse; }
void FinishWaitUntil() {
std::move(finish_callback_)
.Run(blink::mojom::ServiceWorkerEventStatus::COMPLETED,
base::Time::Now());
base::RunLoop().RunUntilIdle();
}
void ReadRequestBody(std::string* out_string) {
ASSERT_TRUE(request_body_);
const std::vector<network::DataElement>* elements =
request_body_->elements();
// So far this test expects a single bytes element.
ASSERT_EQ(1u, elements->size());
const network::DataElement& element = elements->front();
ASSERT_EQ(network::DataElement::TYPE_BYTES, element.type());
*out_string = std::string(element.bytes(), element.length());
}
protected:
void OnFetchEvent(
int embedded_worker_id,
const network::ResourceRequest& request,
mojom::FetchEventPreloadHandlePtr preload_handle,
mojom::ServiceWorkerFetchResponseCallbackPtr response_callback,
mojom::ServiceWorkerEventDispatcher::DispatchFetchEventCallback
finish_callback) override {
// Basic checks on DispatchFetchEvent parameters.
EXPECT_TRUE(ServiceWorkerUtils::IsMainResourceType(
static_cast<ResourceType>(request.resource_type)));
request_body_ = request.request_body;
switch (response_mode_) {
case ResponseMode::kDefault:
EmbeddedWorkerTestHelper::OnFetchEvent(
embedded_worker_id, request, std::move(preload_handle),
std::move(response_callback), std::move(finish_callback));
return;
case ResponseMode::kBlob:
response_callback->OnResponseBlob(
ServiceWorkerResponse(
std::make_unique<std::vector<GURL>>(), 200, "OK",
network::mojom::FetchResponseType::kDefault,
std::make_unique<ServiceWorkerHeaderMap>(), "" /* blob_uuid */,
0 /* blob_size */, nullptr /* blob */,
blink::mojom::ServiceWorkerResponseError::kUnknown,
base::Time(), false /* response_is_in_cache_storage */,
std::string() /* response_cache_storage_cache_name */,
std::make_unique<
ServiceWorkerHeaderList>() /* cors_exposed_header_names */),
std::move(blob_body_), base::Time::Now());
std::move(finish_callback)
.Run(blink::mojom::ServiceWorkerEventStatus::COMPLETED,
base::Time::Now());
return;
case ResponseMode::kStream:
response_callback->OnResponseStream(
ServiceWorkerResponse(
std::make_unique<std::vector<GURL>>(), 200, "OK",
network::mojom::FetchResponseType::kDefault,
std::make_unique<ServiceWorkerHeaderMap>(), "" /* blob_uuid */,
0 /* blob_size */, nullptr /* blob */,
blink::mojom::ServiceWorkerResponseError::kUnknown,
base::Time(), false /* response_is_in_cache_storage */,
std::string() /* response_cache_storage_cache_name */,
std::make_unique<
ServiceWorkerHeaderList>() /* cors_exposed_header_names */),
std::move(stream_handle_), base::Time::Now());
std::move(finish_callback)
.Run(blink::mojom::ServiceWorkerEventStatus::COMPLETED,
base::Time::Now());
return;
case ResponseMode::kFallbackResponse:
response_callback->OnFallback(base::Time::Now());
std::move(finish_callback)
.Run(blink::mojom::ServiceWorkerEventStatus::COMPLETED,
base::Time::Now());
return;
case ResponseMode::kErrorResponse:
response_callback->OnResponse(
ServiceWorkerResponse(
std::make_unique<std::vector<GURL>>(), 0 /* status_code */,
"" /* status_text */,
network::mojom::FetchResponseType::kDefault,
std::make_unique<ServiceWorkerHeaderMap>(), "" /* blob_uuid */,
0 /* blob_size */, nullptr /* blob */,
blink::mojom::ServiceWorkerResponseError::kPromiseRejected,
base::Time(), false /* response_is_in_cache_storage */,
std::string() /* response_cache_storage_cache_name */,
std::make_unique<
ServiceWorkerHeaderList>() /* cors_exposed_header_names */),
base::Time::Now());
std::move(finish_callback)
.Run(blink::mojom::ServiceWorkerEventStatus::REJECTED,
base::Time::Now());
return;
case ResponseMode::kNavigationPreloadResponse:
// Deletes itself when done.
new NavigationPreloadLoaderClient(std::move(preload_handle),
std::move(response_callback),
std::move(finish_callback));
return;
case ResponseMode::kFailFetchEventDispatch:
// Simulate failure by stopping the worker before the event finishes.
// This causes ServiceWorkerVersion::StartRequest() to call its error
// callback, which triggers ServiceWorkerNavigationLoader's dispatch
// failed behavior.
SimulateWorkerStopped(embedded_worker_id);
// Finish the event by calling |finish_callback|.
// This is the Mojo callback for
// mojom::ServiceWorkerEventDispatcher::DispatchFetchEvent().
// If this is not called, Mojo will complain. In production code,
// ServiceWorkerContextClient would call this when it aborts all
// callbacks after an unexpected stop.
std::move(finish_callback)
.Run(blink::mojom::ServiceWorkerEventStatus::ABORTED,
base::Time::Now());
return;
case ResponseMode::kEarlyResponse:
finish_callback_ = std::move(finish_callback);
response_callback->OnResponse(
ServiceWorkerResponse(
std::make_unique<std::vector<GURL>>(), 200, "OK",
network::mojom::FetchResponseType::kDefault,
std::make_unique<ServiceWorkerHeaderMap>(), "" /* blob_uuid */,
0 /* blob_size */, nullptr /* blob */,
blink::mojom::ServiceWorkerResponseError::kUnknown,
base::Time(), false /* response_is_in_cache_storage */,
std::string() /* response_cache_storage_cache_name */,
std::make_unique<
ServiceWorkerHeaderList>() /* cors_exposed_header_names */),
base::Time::Now());
// Now the caller must call FinishWaitUntil() to finish the event.
return;
case ResponseMode::kRedirect:
auto headers = std::make_unique<ServiceWorkerHeaderMap>();
(*headers)["location"] = redirected_url_.spec();
response_callback->OnResponse(
ServiceWorkerResponse(
std::make_unique<std::vector<GURL>>(), 301, "Moved Permanently",
network::mojom::FetchResponseType::kDefault, std::move(headers),
"" /* blob_uuid */, 0 /* blob_size */, nullptr /* blob */,
blink::mojom::ServiceWorkerResponseError::kUnknown,
base::Time(), false /* response_is_in_cache_storage */,
std::string() /* response_cache_storage_cache_name */,
std::make_unique<
ServiceWorkerHeaderList>() /* cors_exposed_header_names */),
base::Time::Now());
std::move(finish_callback)
.Run(blink::mojom::ServiceWorkerEventStatus::COMPLETED,
base::Time::Now());
return;
}
NOTREACHED();
}
private:
enum class ResponseMode {
kDefault,
kBlob,
kStream,
kFallbackResponse,
kErrorResponse,
kNavigationPreloadResponse,
kFailFetchEventDispatch,
kEarlyResponse,
kRedirect
};
ResponseMode response_mode_ = ResponseMode::kDefault;
scoped_refptr<network::ResourceRequestBody> request_body_;
// For ResponseMode::kBlob.
blink::mojom::BlobPtr blob_body_;
// For ResponseMode::kStream.
blink::mojom::ServiceWorkerStreamHandlePtr stream_handle_;
// For ResponseMode::kEarlyResponse.
mojom::ServiceWorkerEventDispatcher::DispatchFetchEventCallback
finish_callback_;
// For ResponseMode::kRedirect.
GURL redirected_url_;
MockNetworkURLLoaderFactory mock_url_loader_factory_;
DISALLOW_COPY_AND_ASSIGN(Helper);
};
// Returns typical response info for a resource load that went through a service
// worker.
std::unique_ptr<network::ResourceResponseHead>
CreateResponseInfoFromServiceWorker() {
auto head = std::make_unique<network::ResourceResponseHead>();
head->was_fetched_via_service_worker = true;
head->was_fallback_required_by_service_worker = false;
head->url_list_via_service_worker = std::vector<GURL>();
head->response_type_via_service_worker =
network::mojom::FetchResponseType::kDefault;
head->is_in_cache_storage = false;
head->cache_storage_cache_name = std::string();
head->did_service_worker_navigation_preload = false;
return head;
}
// ServiceWorkerNavigationLoaderTest is for testing the handling of requests
// by a service worker via ServiceWorkerNavigationLoader.
//
// Of course, no actual service worker runs in the unit test, it is simulated
// via EmbeddedWorkerTestHelper receiving IPC messages from the browser and
// responding as if a service worker is running in the renderer.
//
// ServiceWorkerNavigationLoaderTest is also a
// ServiceWorkerNavigationLoader::Delegate. In production code,
// ServiceWorkerControlleeRequestHandler is the Delegate. So this class also
// basically mocks that part of ServiceWorkerControlleeRequestHandler.
class ServiceWorkerNavigationLoaderTest
: public testing::Test,
public ServiceWorkerNavigationLoader::Delegate {
public:
ServiceWorkerNavigationLoaderTest()
: thread_bundle_(TestBrowserThreadBundle::IO_MAINLOOP),
helper_(std::make_unique<Helper>()) {}
~ServiceWorkerNavigationLoaderTest() override = default;
void SetUp() override {
feature_list_.InitAndEnableFeature(network::features::kNetworkService);
// Create an active service worker.
storage()->LazyInitializeForTest(base::DoNothing());
base::RunLoop().RunUntilIdle();
blink::mojom::ServiceWorkerRegistrationOptions options;
options.scope = GURL("https://example.com/");
registration_ =
new ServiceWorkerRegistration(options, storage()->NewRegistrationId(),
helper_->context()->AsWeakPtr());
version_ = new ServiceWorkerVersion(
registration_.get(), GURL("https://example.com/service_worker.js"),
storage()->NewVersionId(), helper_->context()->AsWeakPtr());
std::vector<ServiceWorkerDatabase::ResourceRecord> records;
records.push_back(WriteToDiskCacheSync(
storage(), version_->script_url(), storage()->NewResourceId(),
{} /* headers */, "I'm the body", "I'm the meta data"));
version_->script_cache_map()->SetResources(records);
version_->set_fetch_handler_existence(
ServiceWorkerVersion::FetchHandlerExistence::EXISTS);
version_->SetStatus(ServiceWorkerVersion::ACTIVATED);
registration_->SetActiveVersion(version_);
// Make the registration findable via storage functions.
registration_->set_last_update_check(base::Time::Now());
ServiceWorkerStatusCode status = SERVICE_WORKER_ERROR_FAILED;
storage()->StoreRegistration(registration_.get(), version_.get(),
CreateReceiverOnCurrentThread(&status));
base::RunLoop().RunUntilIdle();
ASSERT_EQ(SERVICE_WORKER_OK, status);
}
ServiceWorkerStorage* storage() { return helper_->context()->storage(); }
// Indicates whether ServiceWorkerNavigationLoader decided to handle a
// request, i.e., it returned a non-null RequestHandler for the request.
enum class LoaderResult {
kHandledRequest,
kDidNotHandleRequest,
};
// Returns whether ServiceWorkerNavigationLoader handled the request. If
// kHandledRequest was returned, the request is ongoing and the caller can use
// functions like client_.RunUntilComplete() to wait for completion.
LoaderResult StartRequest(std::unique_ptr<network::ResourceRequest> request) {
// Start a ServiceWorkerNavigationLoader. It should return a
// RequestHandler.
SingleRequestURLLoaderFactory::RequestHandler handler;
loader_ = std::make_unique<ServiceWorkerNavigationLoader>(
base::BindOnce(&ReceiveRequestHandler, &handler), this, *request,
base::WrapRefCounted<URLLoaderFactoryGetter>(
helper_->context()->loader_factory_getter()));
loader_->ForwardToServiceWorker();
base::RunLoop().RunUntilIdle();
if (!handler)
return LoaderResult::kDidNotHandleRequest;
// Run the handler. It will load |request.url|.
std::move(handler).Run(mojo::MakeRequest(&loader_ptr_),
client_.CreateInterfacePtr());
return LoaderResult::kHandledRequest;
}
void ExpectResponseInfo(const network::ResourceResponseHead& info,
const network::ResourceResponseHead& expected_info) {
EXPECT_EQ(expected_info.was_fetched_via_service_worker,
info.was_fetched_via_service_worker);
EXPECT_EQ(expected_info.was_fallback_required_by_service_worker,
info.was_fallback_required_by_service_worker);
EXPECT_EQ(expected_info.url_list_via_service_worker,
info.url_list_via_service_worker);
EXPECT_EQ(expected_info.response_type_via_service_worker,
info.response_type_via_service_worker);
EXPECT_FALSE(info.service_worker_start_time.is_null());
EXPECT_FALSE(info.service_worker_ready_time.is_null());
EXPECT_LT(info.service_worker_start_time, info.service_worker_ready_time);
EXPECT_EQ(expected_info.is_in_cache_storage, info.is_in_cache_storage);
EXPECT_EQ(expected_info.cache_storage_cache_name,
info.cache_storage_cache_name);
EXPECT_EQ(expected_info.did_service_worker_navigation_preload,
info.did_service_worker_navigation_preload);
}
std::unique_ptr<network::ResourceRequest> CreateRequest() {
std::unique_ptr<network::ResourceRequest> request =
std::make_unique<network::ResourceRequest>();
request->url = GURL("https://www.example.com/");
request->method = "GET";
request->fetch_request_mode = network::mojom::FetchRequestMode::kNavigate;
request->fetch_credentials_mode =
network::mojom::FetchCredentialsMode::kInclude;
request->fetch_redirect_mode = network::mojom::FetchRedirectMode::kManual;
return request;
}
protected:
// ServiceWorkerNavigationLoader::Delegate -----------------------------------
void OnPrepareToRestart() override {}
ServiceWorkerVersion* GetServiceWorkerVersion(
ServiceWorkerMetrics::URLRequestJobResult* result) override {
return version_.get();
}
bool RequestStillValid(
ServiceWorkerMetrics::URLRequestJobResult* result) override {
return true;
}
void MainResourceLoadFailed() override {
was_main_resource_load_failed_called_ = true;
}
// --------------------------------------------------------------------------
TestBrowserThreadBundle thread_bundle_;
std::unique_ptr<Helper> helper_;
scoped_refptr<ServiceWorkerRegistration> registration_;
scoped_refptr<ServiceWorkerVersion> version_;
storage::BlobStorageContext blob_context_;
network::TestURLLoaderClient client_;
bool was_main_resource_load_failed_called_ = false;
std::unique_ptr<ServiceWorkerNavigationLoader> loader_;
network::mojom::URLLoaderPtr loader_ptr_;
base::test::ScopedFeatureList feature_list_;
};
TEST_F(ServiceWorkerNavigationLoaderTest, Basic) {
// Perform the request
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kHandledRequest, result);
client_.RunUntilComplete();
EXPECT_EQ(net::OK, client_.completion_status().error_code);
const network::ResourceResponseHead& info = client_.response_head();
EXPECT_EQ(200, info.headers->response_code());
ExpectResponseInfo(info, *CreateResponseInfoFromServiceWorker());
}
TEST_F(ServiceWorkerNavigationLoaderTest, NoActiveWorker) {
// Clear |version_| to make GetServiceWorkerVersion() return null.
version_ = nullptr;
// Perform the request.
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kHandledRequest, result);
client_.RunUntilComplete();
EXPECT_EQ(net::ERR_FAILED, client_.completion_status().error_code);
}
// Test that the request body is passed to the fetch event.
TEST_F(ServiceWorkerNavigationLoaderTest, RequestBody) {
const std::string kData = "hi this is the request body";
// Create a request with a body.
auto request_body = base::MakeRefCounted<network::ResourceRequestBody>();
request_body->AppendBytes(kData.c_str(), kData.length());
std::unique_ptr<network::ResourceRequest> request = CreateRequest();
request->method = "POST";
request->request_body = request_body;
// This test doesn't use the response to the fetch event, so just have the
// service worker do simple network fallback.
helper_->RespondWithFallback();
LoaderResult result = StartRequest(std::move(request));
EXPECT_EQ(LoaderResult::kDidNotHandleRequest, result);
// Verify that the request body was passed to the fetch event.
std::string body;
helper_->ReadRequestBody(&body);
EXPECT_EQ(kData, body);
}
TEST_F(ServiceWorkerNavigationLoaderTest, BlobResponse) {
// Construct the blob to respond with.
const std::string kResponseBody = "Here is sample text for the blob.";
auto blob_data = std::make_unique<storage::BlobDataBuilder>("blob-id:myblob");
blob_data->AppendData(kResponseBody);
std::unique_ptr<storage::BlobDataHandle> blob_handle =
blob_context_.AddFinishedBlob(std::move(blob_data));
blink::mojom::BlobPtr blob_ptr;
blink::mojom::BlobRequest request = mojo::MakeRequest(&blob_ptr);
storage::BlobImpl::Create(std::move(blob_handle), std::move(request));
helper_->RespondWithBlob(std::move(blob_ptr));
// Perform the request.
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kHandledRequest, result);
client_.RunUntilComplete();
const network::ResourceResponseHead& info = client_.response_head();
EXPECT_EQ(200, info.headers->response_code());
ExpectResponseInfo(info, *CreateResponseInfoFromServiceWorker());
// Test the body.
std::string body;
EXPECT_TRUE(client_.response_body().is_valid());
EXPECT_TRUE(
mojo::BlockingCopyToString(client_.response_body_release(), &body));
EXPECT_EQ(kResponseBody, body);
EXPECT_EQ(net::OK, client_.completion_status().error_code);
}
// Tell the helper to respond with a non-existent Blob.
TEST_F(ServiceWorkerNavigationLoaderTest, BrokenBlobResponse) {
const std::string kBrokenUUID = "broken_uuid";
// Create the broken blob.
std::unique_ptr<storage::BlobDataHandle> blob_handle =
blob_context_.AddBrokenBlob(kBrokenUUID, "", "",
storage::BlobStatus::ERR_OUT_OF_MEMORY);
blink::mojom::BlobPtr blob_ptr;
blink::mojom::BlobRequest request = mojo::MakeRequest(&blob_ptr);
storage::BlobImpl::Create(std::move(blob_handle), std::move(request));
helper_->RespondWithBlob(std::move(blob_ptr));
// Perform the request.
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kHandledRequest, result);
// We should get a valid response once the headers arrive.
client_.RunUntilResponseReceived();
const network::ResourceResponseHead& info = client_.response_head();
EXPECT_EQ(200, info.headers->response_code());
ExpectResponseInfo(info, *CreateResponseInfoFromServiceWorker());
// However, since the blob is broken we should get an error while transferring
// the body.
client_.RunUntilComplete();
EXPECT_EQ(net::ERR_OUT_OF_MEMORY, client_.completion_status().error_code);
}
TEST_F(ServiceWorkerNavigationLoaderTest, StreamResponse) {
// Construct the Stream to respond with.
const char kResponseBody[] = "Here is sample text for the Stream.";
blink::mojom::ServiceWorkerStreamCallbackPtr stream_callback;
mojo::DataPipe data_pipe;
helper_->RespondWithStream(mojo::MakeRequest(&stream_callback),
std::move(data_pipe.consumer_handle));
// Perform the request.
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kHandledRequest, result);
client_.RunUntilResponseReceived();
const network::ResourceResponseHead& info = client_.response_head();
EXPECT_EQ(200, info.headers->response_code());
ExpectResponseInfo(info, *CreateResponseInfoFromServiceWorker());
EXPECT_TRUE(version_->HasWorkInBrowser());
// Write the body stream.
uint32_t written_bytes = sizeof(kResponseBody) - 1;
MojoResult mojo_result = data_pipe.producer_handle->WriteData(
kResponseBody, &written_bytes, MOJO_WRITE_DATA_FLAG_NONE);
ASSERT_EQ(MOJO_RESULT_OK, mojo_result);
EXPECT_EQ(sizeof(kResponseBody) - 1, written_bytes);
stream_callback->OnCompleted();
data_pipe.producer_handle.reset();
client_.RunUntilComplete();
EXPECT_EQ(net::OK, client_.completion_status().error_code);
// Test the body.
std::string response;
EXPECT_TRUE(client_.response_body().is_valid());
EXPECT_TRUE(
mojo::BlockingCopyToString(client_.response_body_release(), &response));
EXPECT_EQ(kResponseBody, response);
}
// Test when a stream response body is aborted.
TEST_F(ServiceWorkerNavigationLoaderTest, StreamResponse_Abort) {
// Construct the Stream to respond with.
const char kResponseBody[] = "Here is sample text for the Stream.";
blink::mojom::ServiceWorkerStreamCallbackPtr stream_callback;
mojo::DataPipe data_pipe;
helper_->RespondWithStream(mojo::MakeRequest(&stream_callback),
std::move(data_pipe.consumer_handle));
// Perform the request.
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kHandledRequest, result);
client_.RunUntilResponseReceived();
const network::ResourceResponseHead& info = client_.response_head();
EXPECT_EQ(200, info.headers->response_code());
ExpectResponseInfo(info, *CreateResponseInfoFromServiceWorker());
// Start writing the body stream, then abort before finishing.
uint32_t written_bytes = sizeof(kResponseBody) - 1;
MojoResult mojo_result = data_pipe.producer_handle->WriteData(
kResponseBody, &written_bytes, MOJO_WRITE_DATA_FLAG_NONE);
ASSERT_EQ(MOJO_RESULT_OK, mojo_result);
EXPECT_EQ(sizeof(kResponseBody) - 1, written_bytes);
stream_callback->OnAborted();
data_pipe.producer_handle.reset();
client_.RunUntilComplete();
EXPECT_EQ(net::ERR_ABORTED, client_.completion_status().error_code);
// Test the body.
std::string response;
EXPECT_TRUE(client_.response_body().is_valid());
EXPECT_TRUE(
mojo::BlockingCopyToString(client_.response_body_release(), &response));
EXPECT_EQ(kResponseBody, response);
}
// Test when the loader is cancelled while a stream response is being written.
TEST_F(ServiceWorkerNavigationLoaderTest, StreamResponseAndCancel) {
// Construct the Stream to respond with.
const char kResponseBody[] = "Here is sample text for the Stream.";
blink::mojom::ServiceWorkerStreamCallbackPtr stream_callback;
mojo::DataPipe data_pipe;
helper_->RespondWithStream(mojo::MakeRequest(&stream_callback),
std::move(data_pipe.consumer_handle));
// Perform the request.
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kHandledRequest, result);
client_.RunUntilResponseReceived();
const network::ResourceResponseHead& info = client_.response_head();
EXPECT_EQ(200, info.headers->response_code());
ExpectResponseInfo(info, *CreateResponseInfoFromServiceWorker());
// Start writing the body stream, then cancel the loader before finishing.
uint32_t written_bytes = sizeof(kResponseBody) - 1;
MojoResult mojo_result = data_pipe.producer_handle->WriteData(
kResponseBody, &written_bytes, MOJO_WRITE_DATA_FLAG_NONE);
ASSERT_EQ(MOJO_RESULT_OK, mojo_result);
EXPECT_EQ(sizeof(kResponseBody) - 1, written_bytes);
EXPECT_TRUE(data_pipe.producer_handle.is_valid());
EXPECT_FALSE(loader_->WasCanceled());
EXPECT_TRUE(version_->HasWorkInBrowser());
loader_->Cancel();
EXPECT_TRUE(loader_->WasCanceled());
EXPECT_FALSE(version_->HasWorkInBrowser());
// Although ServiceWorkerNavigationLoader resets its URLLoaderClient pointer
// in Cancel(), the URLLoaderClient still exists. In this test, it is
// |client_| which owns the data pipe, so it's still valid to write data to
// it.
mojo_result = data_pipe.producer_handle->WriteData(
kResponseBody, &written_bytes, MOJO_WRITE_DATA_FLAG_NONE);
// TODO(falken): This should probably be an error.
EXPECT_EQ(MOJO_RESULT_OK, mojo_result);
client_.RunUntilComplete();
EXPECT_FALSE(data_pipe.consumer_handle.is_valid());
EXPECT_EQ(net::ERR_ABORTED, client_.completion_status().error_code);
}
// Test when the service worker responds with network fallback.
// i.e., does not call respondWith().
TEST_F(ServiceWorkerNavigationLoaderTest, FallbackResponse) {
helper_->RespondWithFallback();
// Perform the request.
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kDidNotHandleRequest, result);
// The request should not be handled by the loader, but it shouldn't be a
// failure.
EXPECT_FALSE(was_main_resource_load_failed_called_);
}
// Test when the service worker rejects the FetchEvent.
TEST_F(ServiceWorkerNavigationLoaderTest, ErrorResponse) {
helper_->RespondWithError();
// Perform the request.
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kHandledRequest, result);
client_.RunUntilComplete();
EXPECT_EQ(net::ERR_FAILED, client_.completion_status().error_code);
}
// Test when dispatching the fetch event to the service worker failed.
TEST_F(ServiceWorkerNavigationLoaderTest, FailFetchDispatch) {
helper_->FailToDispatchFetchEvent();
// Perform the request.
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kDidNotHandleRequest, result);
EXPECT_TRUE(was_main_resource_load_failed_called_);
}
// Test when the respondWith() promise resolves before the waitUntil() promise
// resolves. The response should be received before the event finishes.
TEST_F(ServiceWorkerNavigationLoaderTest, EarlyResponse) {
helper_->RespondEarly();
// Perform the request.
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kHandledRequest, result);
client_.RunUntilComplete();
const network::ResourceResponseHead& info = client_.response_head();
EXPECT_EQ(200, info.headers->response_code());
ExpectResponseInfo(info, *CreateResponseInfoFromServiceWorker());
// Although the response was already received, the event remains outstanding
// until waitUntil() resolves.
EXPECT_TRUE(version_->HasWorkInBrowser());
helper_->FinishWaitUntil();
EXPECT_FALSE(version_->HasWorkInBrowser());
}
// Test asking the loader to fallback to network. In production code, this
// happens when there is no active service worker for the URL, or it must be
// skipped, etc.
TEST_F(ServiceWorkerNavigationLoaderTest, FallbackToNetwork) {
network::ResourceRequest request;
request.url = GURL("https://www.example.com/");
request.method = "GET";
request.fetch_request_mode = network::mojom::FetchRequestMode::kNavigate;
request.fetch_credentials_mode =
network::mojom::FetchCredentialsMode::kInclude;
request.fetch_redirect_mode = network::mojom::FetchRedirectMode::kManual;
SingleRequestURLLoaderFactory::RequestHandler handler;
auto loader = std::make_unique<ServiceWorkerNavigationLoader>(
base::BindOnce(&ReceiveRequestHandler, &handler), this, request,
base::WrapRefCounted<URLLoaderFactoryGetter>(
helper_->context()->loader_factory_getter()));
// Ask the loader to fallback to network. In production code,
// ServiceWorkerControlleeRequestHandler calls FallbackToNetwork() to do this.
loader->FallbackToNetwork();
base::RunLoop().RunUntilIdle();
EXPECT_FALSE(handler);
}
// Test responding to the fetch event with the navigation preload response.
TEST_F(ServiceWorkerNavigationLoaderTest, NavigationPreload) {
registration_->EnableNavigationPreload(true);
helper_->RespondWithNavigationPreloadResponse();
// Perform the request
LoaderResult result = StartRequest(CreateRequest());
ASSERT_EQ(LoaderResult::kHandledRequest, result);
client_.RunUntilComplete();
EXPECT_EQ(net::OK, client_.completion_status().error_code);
const network::ResourceResponseHead& info = client_.response_head();
EXPECT_EQ(200, info.headers->response_code());
std::unique_ptr<network::ResourceResponseHead> expected_info =
CreateResponseInfoFromServiceWorker();
expected_info->did_service_worker_navigation_preload = true;
ExpectResponseInfo(info, *expected_info);
std::string response;
EXPECT_TRUE(client_.response_body().is_valid());
EXPECT_TRUE(
mojo::BlockingCopyToString(client_.response_body_release(), &response));
EXPECT_EQ("this body came from the network", response);
}
// Test responding to the fetch event with a redirect response.
TEST_F(ServiceWorkerNavigationLoaderTest, Redirect) {
GURL new_url("https://example.com/redirected");
helper_->RespondWithRedirectResponse(new_url);
// Perform the request.
LoaderResult result = StartRequest(CreateRequest());
EXPECT_EQ(LoaderResult::kHandledRequest, result);
client_.RunUntilRedirectReceived();
const network::ResourceResponseHead& info = client_.response_head();
EXPECT_EQ(301, info.headers->response_code());
ExpectResponseInfo(info, *CreateResponseInfoFromServiceWorker());
const net::RedirectInfo& redirect_info = client_.redirect_info();
EXPECT_EQ(301, redirect_info.status_code);
EXPECT_EQ("GET", redirect_info.new_method);
EXPECT_EQ(new_url, redirect_info.new_url);
}
} // namespace service_worker_navigation_loader_unittest
} // namespace content
| null | null | null | null | 19,933 |
4,139 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 4,139 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2012 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef IOS_CHROME_BROWSER_INFOBARS_INFOBAR_CONTAINER_VIEW_H_
#define IOS_CHROME_BROWSER_INFOBARS_INFOBAR_CONTAINER_VIEW_H_
#import <UIKit/UIKit.h>
class InfoBarIOS;
@interface InfoBarContainerView : UIView {
}
// Add a new infobar to the container view at position |position|.
- (void)addInfoBar:(InfoBarIOS*)infoBarIOS position:(NSInteger)position;
// Height of the frontmost infobar that is not hidden.
- (CGFloat)topmostVisibleInfoBarHeight;
@end
#endif // IOS_CHROME_BROWSER_INFOBARS_INFOBAR_CONTAINER_VIEW_H_
| null | null | null | null | 1,002 |
15,720 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 15,720 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef COMPONENTS_COMPONENT_UPDATER_COMPONENT_UPDATER_SERVICE_H_
#define COMPONENTS_COMPONENT_UPDATER_COMPONENT_UPDATER_SERVICE_H_
#include <stdint.h>
#include <memory>
#include <string>
#include <vector>
#include "base/callback_forward.h"
#include "base/gtest_prod_util.h"
#include "base/memory/ref_counted.h"
#include "base/version.h"
#include "build/build_config.h"
#include "components/update_client/update_client.h"
#include "url/gurl.h"
class ComponentsUI;
class PluginObserver;
namespace policy {
class ComponentUpdaterPolicyTest;
}
namespace update_client {
class ComponentInstaller;
class Configurator;
struct CrxComponent;
struct CrxUpdateItem;
}
namespace component_updater {
// Called when a non-blocking call in this module completes.
using Callback = update_client::Callback;
class OnDemandUpdater;
using Configurator = update_client::Configurator;
using CrxComponent = update_client::CrxComponent;
using CrxUpdateItem = update_client::CrxUpdateItem;
struct ComponentInfo {
ComponentInfo(const std::string& id,
const std::string& fingerprint,
const base::string16& name,
const base::Version& version);
ComponentInfo(const ComponentInfo& other);
ComponentInfo(ComponentInfo&& other);
~ComponentInfo();
const std::string id;
const std::string fingerprint;
const base::string16 name;
const base::Version version;
};
// The component update service is in charge of installing or upgrading
// select parts of chrome. Each part is called a component and managed by
// instances of CrxComponent registered using RegisterComponent(). On the
// server, each component is packaged as a CRX which is the same format used
// to package extensions. To the update service each component is identified
// by its public key hash (CrxComponent::pk_hash). If there is an update
// available and its version is bigger than (CrxComponent::version), it will
// be downloaded, verified and unpacked. Then component-specific installer
// ComponentInstaller::Install (of CrxComponent::installer) will be called.
//
// During the normal operation of the component updater some specific
// notifications are fired, like COMPONENT_UPDATER_STARTED and
// COMPONENT_UPDATE_FOUND. See notification_type.h for more details.
//
// All methods are safe to call ONLY from the browser's main thread.
class ComponentUpdateService {
public:
using Observer = update_client::UpdateClient::Observer;
// Adds an observer for this class. An observer should not be added more
// than once. The caller retains the ownership of the observer object.
virtual void AddObserver(Observer* observer) = 0;
// Removes an observer. It is safe for an observer to be removed while
// the observers are being notified.
virtual void RemoveObserver(Observer* observer) = 0;
// Add component to be checked for updates.
virtual bool RegisterComponent(const CrxComponent& component) = 0;
// Unregisters the component with the given ID. This means that the component
// is not going to be included in future update checks. If a download or
// update operation for the component is currently in progress, it will
// silently finish without triggering the next step.
// Note that the installer for the component is responsible for removing any
// existing versions of the component from disk. Returns true if the
// uninstall has completed successfully and the component files have been
// removed, or if the uninstalled has been deferred because the component
// is being updated. Returns false if the component id is not known or the
/// uninstall encountered an error.
virtual bool UnregisterComponent(const std::string& id) = 0;
// Returns a list of registered components.
virtual std::vector<std::string> GetComponentIDs() const = 0;
// Returns a ComponentInfo describing a registered component that implements a
// handler for the specified |mime_type|. If multiple such components exist,
// returns information for the one that was most recently registered. If no
// such components exist, returns nullptr.
virtual std::unique_ptr<ComponentInfo> GetComponentForMimeType(
const std::string& mime_type) const = 0;
// Returns a list of ComponentInfo objects describing all registered
// components.
virtual std::vector<ComponentInfo> GetComponents() const = 0;
// Returns an interface for on-demand updates. On-demand updates are
// proactively triggered outside the normal component update service schedule.
virtual OnDemandUpdater& GetOnDemandUpdater() = 0;
// This method is used to trigger an on-demand update for component |id|.
// This can be used when loading a resource that depends on this component.
//
// |callback| is called on the main thread once the on-demand update is
// complete, regardless of success. |callback| may be called immediately
// within the method body.
//
// Additionally, this function implements an embedder-defined cooldown
// interval between on demand update attempts. This behavior is intended
// to be defensive against programming bugs, usually triggered by web fetches,
// where the on-demand functionality is invoked too often. If this function
// is called while still on cooldown, |callback| will be called immediately.
virtual void MaybeThrottle(const std::string& id,
base::OnceClosure callback) = 0;
virtual ~ComponentUpdateService() {}
private:
// Returns details about registered component in the |item| parameter. The
// function returns true in case of success and false in case of errors.
virtual bool GetComponentDetails(const std::string& id,
CrxUpdateItem* item) const = 0;
friend class ::ComponentsUI;
FRIEND_TEST_ALL_PREFIXES(ComponentInstallerTest, RegisterComponent);
};
using ServiceObserver = ComponentUpdateService::Observer;
class OnDemandUpdater {
public:
virtual ~OnDemandUpdater() {}
private:
friend class OnDemandTester;
friend class policy::ComponentUpdaterPolicyTest;
friend class SupervisedUserWhitelistInstaller;
friend class ::ComponentsUI;
friend class ::PluginObserver;
friend class SwReporterOnDemandFetcher;
#if defined(OS_CHROMEOS)
friend class CrOSComponentManager;
#endif // defined(OS_CHROMEOS)
friend class VrAssetsComponentInstallerPolicy;
// Triggers an update check for a component. |id| is a value
// returned by GetCrxComponentID(). If an update for this component is already
// in progress, the function returns |kInProgress|. If an update is available,
// the update will be applied. The caller can subscribe to component update
// service notifications and provide an optional callback to get the result
// of the call. The function does not implement any cooldown interval.
virtual void OnDemandUpdate(const std::string& id, Callback callback) = 0;
};
// Creates the component updater.
std::unique_ptr<ComponentUpdateService> ComponentUpdateServiceFactory(
scoped_refptr<Configurator> config);
} // namespace component_updater
#endif // COMPONENTS_COMPONENT_UPDATER_COMPONENT_UPDATER_SERVICE_H_
| null | null | null | null | 12,583 |
29,726 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 194,721 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /**
* gadget.h - DesignWare USB3 DRD Gadget Header
*
* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 of
* the License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DRIVERS_USB_DWC3_GADGET_H
#define __DRIVERS_USB_DWC3_GADGET_H
#include <linux/list.h>
#include <linux/usb/gadget.h>
#include "io.h"
struct dwc3;
#define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint))
#define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget))
/* DEPCFG parameter 1 */
#define DWC3_DEPCFG_INT_NUM(n) (((n) & 0x1f) << 0)
#define DWC3_DEPCFG_XFER_COMPLETE_EN (1 << 8)
#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9)
#define DWC3_DEPCFG_XFER_NOT_READY_EN (1 << 10)
#define DWC3_DEPCFG_FIFO_ERROR_EN (1 << 11)
#define DWC3_DEPCFG_STREAM_EVENT_EN (1 << 13)
#define DWC3_DEPCFG_BINTERVAL_M1(n) (((n) & 0xff) << 16)
#define DWC3_DEPCFG_STREAM_CAPABLE (1 << 24)
#define DWC3_DEPCFG_EP_NUMBER(n) (((n) & 0x1f) << 25)
#define DWC3_DEPCFG_BULK_BASED (1 << 30)
#define DWC3_DEPCFG_FIFO_BASED (1 << 31)
/* DEPCFG parameter 0 */
#define DWC3_DEPCFG_EP_TYPE(n) (((n) & 0x3) << 1)
#define DWC3_DEPCFG_MAX_PACKET_SIZE(n) (((n) & 0x7ff) << 3)
#define DWC3_DEPCFG_FIFO_NUMBER(n) (((n) & 0x1f) << 17)
#define DWC3_DEPCFG_BURST_SIZE(n) (((n) & 0xf) << 22)
#define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
/* This applies for core versions earlier than 1.94a */
#define DWC3_DEPCFG_IGN_SEQ_NUM (1 << 31)
/* These apply for core versions 1.94a and later */
#define DWC3_DEPCFG_ACTION_INIT (0 << 30)
#define DWC3_DEPCFG_ACTION_RESTORE (1 << 30)
#define DWC3_DEPCFG_ACTION_MODIFY (2 << 30)
/* DEPXFERCFG parameter 0 */
#define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
/* -------------------------------------------------------------------------- */
#define to_dwc3_request(r) (container_of(r, struct dwc3_request, request))
static inline struct dwc3_request *next_request(struct list_head *list)
{
return list_first_entry_or_null(list, struct dwc3_request, list);
}
static inline void dwc3_gadget_move_started_request(struct dwc3_request *req)
{
struct dwc3_ep *dep = req->dep;
req->started = true;
list_move_tail(&req->list, &dep->started_list);
}
void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
int status);
void dwc3_ep0_interrupt(struct dwc3 *dwc,
const struct dwc3_event_depevt *event);
void dwc3_ep0_out_start(struct dwc3 *dwc);
int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value);
int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value);
int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
gfp_t gfp_flags);
int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol);
/**
* dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW
* @dwc: DesignWare USB3 Pointer
* @number: DWC endpoint number
*
* Caller should take care of locking
*/
static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3_ep *dep)
{
u32 res_id;
res_id = dwc3_readl(dep->regs, DWC3_DEPCMD);
return DWC3_DEPCMD_GET_RSC_IDX(res_id);
}
#endif /* __DRIVERS_USB_DWC3_GADGET_H */
| null | null | null | null | 103,068 |
8,395 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 8,395 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2012 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef NET_DISK_CACHE_BLOCKFILE_IN_FLIGHT_IO_H_
#define NET_DISK_CACHE_BLOCKFILE_IN_FLIGHT_IO_H_
#include <set>
#include "base/logging.h"
#include "base/macros.h"
#include "base/memory/ref_counted.h"
#include "base/synchronization/lock.h"
#include "base/synchronization/waitable_event.h"
namespace base {
class TaskRunner;
} // namespace base
namespace disk_cache {
class InFlightIO;
// This class represents a single asynchronous IO operation while it is being
// bounced between threads.
class BackgroundIO : public base::RefCountedThreadSafe<BackgroundIO> {
public:
// Other than the actual parameters for the IO operation (including the
// |callback| that must be notified at the end), we need the controller that
// is keeping track of all operations. When done, we notify the controller
// (we do NOT invoke the callback), in the worker thead that completed the
// operation.
explicit BackgroundIO(InFlightIO* controller);
// This method signals the controller that this operation is finished, in the
// original thread. In practice, this is a RunableMethod that allows
// cancellation.
void OnIOSignalled();
// Allows the cancellation of the task to notify the controller (step number 8
// in the diagram below). In practice, if the controller waits for the
// operation to finish it doesn't have to wait for the final task to be
// processed by the message loop so calling this method prevents its delivery.
// Note that this method is not intended to cancel the actual IO operation or
// to prevent the first notification to take place (OnIOComplete).
void Cancel();
int result() { return result_; }
base::WaitableEvent* io_completed() {
return &io_completed_;
}
protected:
virtual ~BackgroundIO();
// Notifies the controller about the end of the operation, from the background
// thread.
void NotifyController();
int result_; // Final operation result.
private:
friend class base::RefCountedThreadSafe<BackgroundIO>;
// An event to signal when the operation completes.
base::WaitableEvent io_completed_;
InFlightIO* controller_; // The controller that tracks all operations.
base::Lock controller_lock_; // A lock protecting clearing of controller_.
DISALLOW_COPY_AND_ASSIGN(BackgroundIO);
};
// This class keeps track of asynchronous IO operations. A single instance
// of this class is meant to be used to start an asynchronous operation (using
// PostXX, exposed by a derived class). This class will post the operation to a
// worker thread, hanlde the notification when the operation finishes and
// perform the callback on the same thread that was used to start the operation.
//
// The regular sequence of calls is:
// Thread_1 Worker_thread
// 1. DerivedInFlightIO::PostXX()
// 2. -> PostTask ->
// 3. InFlightIO::OnOperationPosted()
// 4. DerivedBackgroundIO::XX()
// 5. IO operation completes
// 6. InFlightIO::OnIOComplete()
// 7. <- PostTask <-
// 8. BackgroundIO::OnIOSignalled()
// 9. InFlightIO::InvokeCallback()
// 10. DerivedInFlightIO::OnOperationComplete()
// 11. invoke callback
//
// Shutdown is a special case that is handled though WaitForPendingIO() instead
// of just waiting for step 7.
class InFlightIO {
public:
InFlightIO();
virtual ~InFlightIO();
// Blocks the current thread until all IO operations tracked by this object
// complete.
void WaitForPendingIO();
// Drops current pending operations without waiting for them to complete.
void DropPendingIO();
// Called on a background thread when |operation| completes.
void OnIOComplete(BackgroundIO* operation);
// Invokes the users' completion callback at the end of the IO operation.
// |cancel_task| is true if the actual task posted to the thread is still
// queued (because we are inside WaitForPendingIO), and false if said task is
// the one performing the call.
void InvokeCallback(BackgroundIO* operation, bool cancel_task);
protected:
// This method is called to signal the completion of the |operation|. |cancel|
// is true if the operation is being cancelled. This method is called on the
// thread that created this object.
virtual void OnOperationComplete(BackgroundIO* operation, bool cancel) = 0;
// Signals this object that the derived class just posted the |operation| to
// be executed on a background thread. This method must be called on the same
// thread used to create this object.
void OnOperationPosted(BackgroundIO* operation);
private:
typedef std::set<scoped_refptr<BackgroundIO> > IOList;
IOList io_list_; // List of pending, in-flight io operations.
scoped_refptr<base::TaskRunner> callback_task_runner_;
bool running_; // True after the first posted operation completes.
#if DCHECK_IS_ON()
bool single_thread_ = false; // True if we only have one thread.
#endif
DISALLOW_COPY_AND_ASSIGN(InFlightIO);
};
} // namespace disk_cache
#endif // NET_DISK_CACHE_BLOCKFILE_IN_FLIGHT_IO_H_
| null | null | null | null | 5,258 |
29,015 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 194,010 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* dell-smm-hwmon.c -- Linux driver for accessing the SMM BIOS on Dell laptops.
*
* Copyright (C) 2001 Massimo Dal Zotto <dz@debian.org>
*
* Hwmon integration:
* Copyright (C) 2011 Jean Delvare <jdelvare@suse.de>
* Copyright (C) 2013, 2014 Guenter Roeck <linux@roeck-us.net>
* Copyright (C) 2014, 2015 Pali Rohár <pali.rohar@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/dmi.h>
#include <linux/capability.h>
#include <linux/mutex.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <linux/sched.h>
#include <linux/ctype.h>
#include <linux/smp.h>
#include <linux/i8k.h>
#define I8K_SMM_FN_STATUS 0x0025
#define I8K_SMM_POWER_STATUS 0x0069
#define I8K_SMM_SET_FAN 0x01a3
#define I8K_SMM_GET_FAN 0x00a3
#define I8K_SMM_GET_SPEED 0x02a3
#define I8K_SMM_GET_FAN_TYPE 0x03a3
#define I8K_SMM_GET_NOM_SPEED 0x04a3
#define I8K_SMM_GET_TEMP 0x10a3
#define I8K_SMM_GET_TEMP_TYPE 0x11a3
#define I8K_SMM_GET_DELL_SIG1 0xfea3
#define I8K_SMM_GET_DELL_SIG2 0xffa3
#define I8K_FAN_MULT 30
#define I8K_FAN_MAX_RPM 30000
#define I8K_MAX_TEMP 127
#define I8K_FN_NONE 0x00
#define I8K_FN_UP 0x01
#define I8K_FN_DOWN 0x02
#define I8K_FN_MUTE 0x04
#define I8K_FN_MASK 0x07
#define I8K_FN_SHIFT 8
#define I8K_POWER_AC 0x05
#define I8K_POWER_BATTERY 0x01
static DEFINE_MUTEX(i8k_mutex);
static char bios_version[4];
static char bios_machineid[16];
static struct device *i8k_hwmon_dev;
static u32 i8k_hwmon_flags;
static uint i8k_fan_mult = I8K_FAN_MULT;
static uint i8k_pwm_mult;
static uint i8k_fan_max = I8K_FAN_HIGH;
static bool disallow_fan_type_call;
#define I8K_HWMON_HAVE_TEMP1 (1 << 0)
#define I8K_HWMON_HAVE_TEMP2 (1 << 1)
#define I8K_HWMON_HAVE_TEMP3 (1 << 2)
#define I8K_HWMON_HAVE_TEMP4 (1 << 3)
#define I8K_HWMON_HAVE_FAN1 (1 << 4)
#define I8K_HWMON_HAVE_FAN2 (1 << 5)
#define I8K_HWMON_HAVE_FAN3 (1 << 6)
MODULE_AUTHOR("Massimo Dal Zotto (dz@debian.org)");
MODULE_AUTHOR("Pali Rohár <pali.rohar@gmail.com>");
MODULE_DESCRIPTION("Dell laptop SMM BIOS hwmon driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("i8k");
static bool force;
module_param(force, bool, 0);
MODULE_PARM_DESC(force, "Force loading without checking for supported models");
static bool ignore_dmi;
module_param(ignore_dmi, bool, 0);
MODULE_PARM_DESC(ignore_dmi, "Continue probing hardware even if DMI data does not match");
#if IS_ENABLED(CONFIG_I8K)
static bool restricted = true;
module_param(restricted, bool, 0);
MODULE_PARM_DESC(restricted, "Restrict fan control and serial number to CAP_SYS_ADMIN (default: 1)");
static bool power_status;
module_param(power_status, bool, 0600);
MODULE_PARM_DESC(power_status, "Report power status in /proc/i8k (default: 0)");
#endif
static uint fan_mult;
module_param(fan_mult, uint, 0);
MODULE_PARM_DESC(fan_mult, "Factor to multiply fan speed with (default: autodetect)");
static uint fan_max;
module_param(fan_max, uint, 0);
MODULE_PARM_DESC(fan_max, "Maximum configurable fan speed (default: autodetect)");
struct smm_regs {
unsigned int eax;
unsigned int ebx __packed;
unsigned int ecx __packed;
unsigned int edx __packed;
unsigned int esi __packed;
unsigned int edi __packed;
};
static inline const char *i8k_get_dmi_data(int field)
{
const char *dmi_data = dmi_get_system_info(field);
return dmi_data && *dmi_data ? dmi_data : "?";
}
/*
* Call the System Management Mode BIOS. Code provided by Jonathan Buzzard.
*/
static int i8k_smm_func(void *par)
{
int rc;
struct smm_regs *regs = par;
int eax = regs->eax;
#ifdef DEBUG
int ebx = regs->ebx;
unsigned long duration;
ktime_t calltime, delta, rettime;
calltime = ktime_get();
#endif
/* SMM requires CPU 0 */
if (smp_processor_id() != 0)
return -EBUSY;
#if defined(CONFIG_X86_64)
asm volatile("pushq %%rax\n\t"
"movl 0(%%rax),%%edx\n\t"
"pushq %%rdx\n\t"
"movl 4(%%rax),%%ebx\n\t"
"movl 8(%%rax),%%ecx\n\t"
"movl 12(%%rax),%%edx\n\t"
"movl 16(%%rax),%%esi\n\t"
"movl 20(%%rax),%%edi\n\t"
"popq %%rax\n\t"
"out %%al,$0xb2\n\t"
"out %%al,$0x84\n\t"
"xchgq %%rax,(%%rsp)\n\t"
"movl %%ebx,4(%%rax)\n\t"
"movl %%ecx,8(%%rax)\n\t"
"movl %%edx,12(%%rax)\n\t"
"movl %%esi,16(%%rax)\n\t"
"movl %%edi,20(%%rax)\n\t"
"popq %%rdx\n\t"
"movl %%edx,0(%%rax)\n\t"
"pushfq\n\t"
"popq %%rax\n\t"
"andl $1,%%eax\n"
: "=a"(rc)
: "a"(regs)
: "%ebx", "%ecx", "%edx", "%esi", "%edi", "memory");
#else
asm volatile("pushl %%eax\n\t"
"movl 0(%%eax),%%edx\n\t"
"push %%edx\n\t"
"movl 4(%%eax),%%ebx\n\t"
"movl 8(%%eax),%%ecx\n\t"
"movl 12(%%eax),%%edx\n\t"
"movl 16(%%eax),%%esi\n\t"
"movl 20(%%eax),%%edi\n\t"
"popl %%eax\n\t"
"out %%al,$0xb2\n\t"
"out %%al,$0x84\n\t"
"xchgl %%eax,(%%esp)\n\t"
"movl %%ebx,4(%%eax)\n\t"
"movl %%ecx,8(%%eax)\n\t"
"movl %%edx,12(%%eax)\n\t"
"movl %%esi,16(%%eax)\n\t"
"movl %%edi,20(%%eax)\n\t"
"popl %%edx\n\t"
"movl %%edx,0(%%eax)\n\t"
"lahf\n\t"
"shrl $8,%%eax\n\t"
"andl $1,%%eax\n"
: "=a"(rc)
: "a"(regs)
: "%ebx", "%ecx", "%edx", "%esi", "%edi", "memory");
#endif
if (rc != 0 || (regs->eax & 0xffff) == 0xffff || regs->eax == eax)
rc = -EINVAL;
#ifdef DEBUG
rettime = ktime_get();
delta = ktime_sub(rettime, calltime);
duration = ktime_to_ns(delta) >> 10;
pr_debug("smm(0x%.4x 0x%.4x) = 0x%.4x (took %7lu usecs)\n", eax, ebx,
(rc ? 0xffff : regs->eax & 0xffff), duration);
#endif
return rc;
}
/*
* Call the System Management Mode BIOS.
*/
static int i8k_smm(struct smm_regs *regs)
{
int ret;
get_online_cpus();
ret = smp_call_on_cpu(0, i8k_smm_func, regs, true);
put_online_cpus();
return ret;
}
/*
* Read the fan status.
*/
static int i8k_get_fan_status(int fan)
{
struct smm_regs regs = { .eax = I8K_SMM_GET_FAN, };
regs.ebx = fan & 0xff;
return i8k_smm(®s) ? : regs.eax & 0xff;
}
/*
* Read the fan speed in RPM.
*/
static int i8k_get_fan_speed(int fan)
{
struct smm_regs regs = { .eax = I8K_SMM_GET_SPEED, };
regs.ebx = fan & 0xff;
return i8k_smm(®s) ? : (regs.eax & 0xffff) * i8k_fan_mult;
}
/*
* Read the fan type.
*/
static int _i8k_get_fan_type(int fan)
{
struct smm_regs regs = { .eax = I8K_SMM_GET_FAN_TYPE, };
if (disallow_fan_type_call)
return -EINVAL;
regs.ebx = fan & 0xff;
return i8k_smm(®s) ? : regs.eax & 0xff;
}
static int i8k_get_fan_type(int fan)
{
/* I8K_SMM_GET_FAN_TYPE SMM call is expensive, so cache values */
static int types[3] = { INT_MIN, INT_MIN, INT_MIN };
if (types[fan] == INT_MIN)
types[fan] = _i8k_get_fan_type(fan);
return types[fan];
}
/*
* Read the fan nominal rpm for specific fan speed.
*/
static int i8k_get_fan_nominal_speed(int fan, int speed)
{
struct smm_regs regs = { .eax = I8K_SMM_GET_NOM_SPEED, };
regs.ebx = (fan & 0xff) | (speed << 8);
return i8k_smm(®s) ? : (regs.eax & 0xffff) * i8k_fan_mult;
}
/*
* Set the fan speed (off, low, high). Returns the new fan status.
*/
static int i8k_set_fan(int fan, int speed)
{
struct smm_regs regs = { .eax = I8K_SMM_SET_FAN, };
speed = (speed < 0) ? 0 : ((speed > i8k_fan_max) ? i8k_fan_max : speed);
regs.ebx = (fan & 0xff) | (speed << 8);
return i8k_smm(®s) ? : i8k_get_fan_status(fan);
}
static int i8k_get_temp_type(int sensor)
{
struct smm_regs regs = { .eax = I8K_SMM_GET_TEMP_TYPE, };
regs.ebx = sensor & 0xff;
return i8k_smm(®s) ? : regs.eax & 0xff;
}
/*
* Read the cpu temperature.
*/
static int _i8k_get_temp(int sensor)
{
struct smm_regs regs = {
.eax = I8K_SMM_GET_TEMP,
.ebx = sensor & 0xff,
};
return i8k_smm(®s) ? : regs.eax & 0xff;
}
static int i8k_get_temp(int sensor)
{
int temp = _i8k_get_temp(sensor);
/*
* Sometimes the temperature sensor returns 0x99, which is out of range.
* In this case we retry (once) before returning an error.
# 1003655137 00000058 00005a4b
# 1003655138 00000099 00003a80 <--- 0x99 = 153 degrees
# 1003655139 00000054 00005c52
*/
if (temp == 0x99) {
msleep(100);
temp = _i8k_get_temp(sensor);
}
/*
* Return -ENODATA for all invalid temperatures.
*
* Known instances are the 0x99 value as seen above as well as
* 0xc1 (193), which may be returned when trying to read the GPU
* temperature if the system supports a GPU and it is currently
* turned off.
*/
if (temp > I8K_MAX_TEMP)
return -ENODATA;
return temp;
}
static int i8k_get_dell_signature(int req_fn)
{
struct smm_regs regs = { .eax = req_fn, };
int rc;
rc = i8k_smm(®s);
if (rc < 0)
return rc;
return regs.eax == 1145651527 && regs.edx == 1145392204 ? 0 : -1;
}
#if IS_ENABLED(CONFIG_I8K)
/*
* Read the Fn key status.
*/
static int i8k_get_fn_status(void)
{
struct smm_regs regs = { .eax = I8K_SMM_FN_STATUS, };
int rc;
rc = i8k_smm(®s);
if (rc < 0)
return rc;
switch ((regs.eax >> I8K_FN_SHIFT) & I8K_FN_MASK) {
case I8K_FN_UP:
return I8K_VOL_UP;
case I8K_FN_DOWN:
return I8K_VOL_DOWN;
case I8K_FN_MUTE:
return I8K_VOL_MUTE;
default:
return 0;
}
}
/*
* Read the power status.
*/
static int i8k_get_power_status(void)
{
struct smm_regs regs = { .eax = I8K_SMM_POWER_STATUS, };
int rc;
rc = i8k_smm(®s);
if (rc < 0)
return rc;
return (regs.eax & 0xff) == I8K_POWER_AC ? I8K_AC : I8K_BATTERY;
}
/*
* Procfs interface
*/
static int
i8k_ioctl_unlocked(struct file *fp, unsigned int cmd, unsigned long arg)
{
int val = 0;
int speed;
unsigned char buff[16];
int __user *argp = (int __user *)arg;
if (!argp)
return -EINVAL;
switch (cmd) {
case I8K_BIOS_VERSION:
if (!isdigit(bios_version[0]) || !isdigit(bios_version[1]) ||
!isdigit(bios_version[2]))
return -EINVAL;
val = (bios_version[0] << 16) |
(bios_version[1] << 8) | bios_version[2];
break;
case I8K_MACHINE_ID:
if (restricted && !capable(CAP_SYS_ADMIN))
return -EPERM;
memset(buff, 0, sizeof(buff));
strlcpy(buff, bios_machineid, sizeof(buff));
break;
case I8K_FN_STATUS:
val = i8k_get_fn_status();
break;
case I8K_POWER_STATUS:
val = i8k_get_power_status();
break;
case I8K_GET_TEMP:
val = i8k_get_temp(0);
break;
case I8K_GET_SPEED:
if (copy_from_user(&val, argp, sizeof(int)))
return -EFAULT;
val = i8k_get_fan_speed(val);
break;
case I8K_GET_FAN:
if (copy_from_user(&val, argp, sizeof(int)))
return -EFAULT;
val = i8k_get_fan_status(val);
break;
case I8K_SET_FAN:
if (restricted && !capable(CAP_SYS_ADMIN))
return -EPERM;
if (copy_from_user(&val, argp, sizeof(int)))
return -EFAULT;
if (copy_from_user(&speed, argp + 1, sizeof(int)))
return -EFAULT;
val = i8k_set_fan(val, speed);
break;
default:
return -EINVAL;
}
if (val < 0)
return val;
switch (cmd) {
case I8K_BIOS_VERSION:
if (copy_to_user(argp, &val, 4))
return -EFAULT;
break;
case I8K_MACHINE_ID:
if (copy_to_user(argp, buff, 16))
return -EFAULT;
break;
default:
if (copy_to_user(argp, &val, sizeof(int)))
return -EFAULT;
break;
}
return 0;
}
static long i8k_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
{
long ret;
mutex_lock(&i8k_mutex);
ret = i8k_ioctl_unlocked(fp, cmd, arg);
mutex_unlock(&i8k_mutex);
return ret;
}
/*
* Print the information for /proc/i8k.
*/
static int i8k_proc_show(struct seq_file *seq, void *offset)
{
int fn_key, cpu_temp, ac_power;
int left_fan, right_fan, left_speed, right_speed;
cpu_temp = i8k_get_temp(0); /* 11100 µs */
left_fan = i8k_get_fan_status(I8K_FAN_LEFT); /* 580 µs */
right_fan = i8k_get_fan_status(I8K_FAN_RIGHT); /* 580 µs */
left_speed = i8k_get_fan_speed(I8K_FAN_LEFT); /* 580 µs */
right_speed = i8k_get_fan_speed(I8K_FAN_RIGHT); /* 580 µs */
fn_key = i8k_get_fn_status(); /* 750 µs */
if (power_status)
ac_power = i8k_get_power_status(); /* 14700 µs */
else
ac_power = -1;
/*
* Info:
*
* 1) Format version (this will change if format changes)
* 2) BIOS version
* 3) BIOS machine ID
* 4) Cpu temperature
* 5) Left fan status
* 6) Right fan status
* 7) Left fan speed
* 8) Right fan speed
* 9) AC power
* 10) Fn Key status
*/
seq_printf(seq, "%s %s %s %d %d %d %d %d %d %d\n",
I8K_PROC_FMT,
bios_version,
(restricted && !capable(CAP_SYS_ADMIN)) ? "-1" : bios_machineid,
cpu_temp,
left_fan, right_fan, left_speed, right_speed,
ac_power, fn_key);
return 0;
}
static int i8k_open_fs(struct inode *inode, struct file *file)
{
return single_open(file, i8k_proc_show, NULL);
}
static const struct file_operations i8k_fops = {
.owner = THIS_MODULE,
.open = i8k_open_fs,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.unlocked_ioctl = i8k_ioctl,
};
static void __init i8k_init_procfs(void)
{
/* Register the proc entry */
proc_create("i8k", 0, NULL, &i8k_fops);
}
static void __exit i8k_exit_procfs(void)
{
remove_proc_entry("i8k", NULL);
}
#else
static inline void __init i8k_init_procfs(void)
{
}
static inline void __exit i8k_exit_procfs(void)
{
}
#endif
/*
* Hwmon interface
*/
static ssize_t i8k_hwmon_show_temp_label(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
static const char * const labels[] = {
"CPU",
"GPU",
"SODIMM",
"Other",
"Ambient",
"Other",
};
int index = to_sensor_dev_attr(devattr)->index;
int type;
type = i8k_get_temp_type(index);
if (type < 0)
return type;
if (type >= ARRAY_SIZE(labels))
type = ARRAY_SIZE(labels) - 1;
return sprintf(buf, "%s\n", labels[type]);
}
static ssize_t i8k_hwmon_show_temp(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
int index = to_sensor_dev_attr(devattr)->index;
int temp;
temp = i8k_get_temp(index);
if (temp < 0)
return temp;
return sprintf(buf, "%d\n", temp * 1000);
}
static ssize_t i8k_hwmon_show_fan_label(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
static const char * const labels[] = {
"Processor Fan",
"Motherboard Fan",
"Video Fan",
"Power Supply Fan",
"Chipset Fan",
"Other Fan",
};
int index = to_sensor_dev_attr(devattr)->index;
bool dock = false;
int type;
type = i8k_get_fan_type(index);
if (type < 0)
return type;
if (type & 0x10) {
dock = true;
type &= 0x0F;
}
if (type >= ARRAY_SIZE(labels))
type = (ARRAY_SIZE(labels) - 1);
return sprintf(buf, "%s%s\n", (dock ? "Docking " : ""), labels[type]);
}
static ssize_t i8k_hwmon_show_fan(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
int index = to_sensor_dev_attr(devattr)->index;
int fan_speed;
fan_speed = i8k_get_fan_speed(index);
if (fan_speed < 0)
return fan_speed;
return sprintf(buf, "%d\n", fan_speed);
}
static ssize_t i8k_hwmon_show_pwm(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
int index = to_sensor_dev_attr(devattr)->index;
int status;
status = i8k_get_fan_status(index);
if (status < 0)
return -EIO;
return sprintf(buf, "%d\n", clamp_val(status * i8k_pwm_mult, 0, 255));
}
static ssize_t i8k_hwmon_set_pwm(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
int index = to_sensor_dev_attr(attr)->index;
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err)
return err;
val = clamp_val(DIV_ROUND_CLOSEST(val, i8k_pwm_mult), 0, i8k_fan_max);
mutex_lock(&i8k_mutex);
err = i8k_set_fan(index, val);
mutex_unlock(&i8k_mutex);
return err < 0 ? -EIO : count;
}
static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, i8k_hwmon_show_temp, NULL, 0);
static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, i8k_hwmon_show_temp_label, NULL,
0);
static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, i8k_hwmon_show_temp, NULL, 1);
static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, i8k_hwmon_show_temp_label, NULL,
1);
static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, i8k_hwmon_show_temp, NULL, 2);
static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, i8k_hwmon_show_temp_label, NULL,
2);
static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, i8k_hwmon_show_temp, NULL, 3);
static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, i8k_hwmon_show_temp_label, NULL,
3);
static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, i8k_hwmon_show_fan, NULL, 0);
static SENSOR_DEVICE_ATTR(fan1_label, S_IRUGO, i8k_hwmon_show_fan_label, NULL,
0);
static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, i8k_hwmon_show_pwm,
i8k_hwmon_set_pwm, 0);
static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO, i8k_hwmon_show_fan, NULL,
1);
static SENSOR_DEVICE_ATTR(fan2_label, S_IRUGO, i8k_hwmon_show_fan_label, NULL,
1);
static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, i8k_hwmon_show_pwm,
i8k_hwmon_set_pwm, 1);
static SENSOR_DEVICE_ATTR(fan3_input, S_IRUGO, i8k_hwmon_show_fan, NULL,
2);
static SENSOR_DEVICE_ATTR(fan3_label, S_IRUGO, i8k_hwmon_show_fan_label, NULL,
2);
static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, i8k_hwmon_show_pwm,
i8k_hwmon_set_pwm, 2);
static struct attribute *i8k_attrs[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr, /* 0 */
&sensor_dev_attr_temp1_label.dev_attr.attr, /* 1 */
&sensor_dev_attr_temp2_input.dev_attr.attr, /* 2 */
&sensor_dev_attr_temp2_label.dev_attr.attr, /* 3 */
&sensor_dev_attr_temp3_input.dev_attr.attr, /* 4 */
&sensor_dev_attr_temp3_label.dev_attr.attr, /* 5 */
&sensor_dev_attr_temp4_input.dev_attr.attr, /* 6 */
&sensor_dev_attr_temp4_label.dev_attr.attr, /* 7 */
&sensor_dev_attr_fan1_input.dev_attr.attr, /* 8 */
&sensor_dev_attr_fan1_label.dev_attr.attr, /* 9 */
&sensor_dev_attr_pwm1.dev_attr.attr, /* 10 */
&sensor_dev_attr_fan2_input.dev_attr.attr, /* 11 */
&sensor_dev_attr_fan2_label.dev_attr.attr, /* 12 */
&sensor_dev_attr_pwm2.dev_attr.attr, /* 13 */
&sensor_dev_attr_fan3_input.dev_attr.attr, /* 14 */
&sensor_dev_attr_fan3_label.dev_attr.attr, /* 15 */
&sensor_dev_attr_pwm3.dev_attr.attr, /* 16 */
NULL
};
static umode_t i8k_is_visible(struct kobject *kobj, struct attribute *attr,
int index)
{
if (disallow_fan_type_call &&
(index == 9 || index == 12 || index == 15))
return 0;
if (index >= 0 && index <= 1 &&
!(i8k_hwmon_flags & I8K_HWMON_HAVE_TEMP1))
return 0;
if (index >= 2 && index <= 3 &&
!(i8k_hwmon_flags & I8K_HWMON_HAVE_TEMP2))
return 0;
if (index >= 4 && index <= 5 &&
!(i8k_hwmon_flags & I8K_HWMON_HAVE_TEMP3))
return 0;
if (index >= 6 && index <= 7 &&
!(i8k_hwmon_flags & I8K_HWMON_HAVE_TEMP4))
return 0;
if (index >= 8 && index <= 10 &&
!(i8k_hwmon_flags & I8K_HWMON_HAVE_FAN1))
return 0;
if (index >= 11 && index <= 13 &&
!(i8k_hwmon_flags & I8K_HWMON_HAVE_FAN2))
return 0;
if (index >= 14 && index <= 16 &&
!(i8k_hwmon_flags & I8K_HWMON_HAVE_FAN3))
return 0;
return attr->mode;
}
static const struct attribute_group i8k_group = {
.attrs = i8k_attrs,
.is_visible = i8k_is_visible,
};
__ATTRIBUTE_GROUPS(i8k);
static int __init i8k_init_hwmon(void)
{
int err;
i8k_hwmon_flags = 0;
/* CPU temperature attributes, if temperature type is OK */
err = i8k_get_temp_type(0);
if (err >= 0)
i8k_hwmon_flags |= I8K_HWMON_HAVE_TEMP1;
/* check for additional temperature sensors */
err = i8k_get_temp_type(1);
if (err >= 0)
i8k_hwmon_flags |= I8K_HWMON_HAVE_TEMP2;
err = i8k_get_temp_type(2);
if (err >= 0)
i8k_hwmon_flags |= I8K_HWMON_HAVE_TEMP3;
err = i8k_get_temp_type(3);
if (err >= 0)
i8k_hwmon_flags |= I8K_HWMON_HAVE_TEMP4;
/* First fan attributes, if fan status or type is OK */
err = i8k_get_fan_status(0);
if (err < 0)
err = i8k_get_fan_type(0);
if (err >= 0)
i8k_hwmon_flags |= I8K_HWMON_HAVE_FAN1;
/* Second fan attributes, if fan status or type is OK */
err = i8k_get_fan_status(1);
if (err < 0)
err = i8k_get_fan_type(1);
if (err >= 0)
i8k_hwmon_flags |= I8K_HWMON_HAVE_FAN2;
/* Third fan attributes, if fan status or type is OK */
err = i8k_get_fan_status(2);
if (err < 0)
err = i8k_get_fan_type(2);
if (err >= 0)
i8k_hwmon_flags |= I8K_HWMON_HAVE_FAN3;
i8k_hwmon_dev = hwmon_device_register_with_groups(NULL, "dell_smm",
NULL, i8k_groups);
if (IS_ERR(i8k_hwmon_dev)) {
err = PTR_ERR(i8k_hwmon_dev);
i8k_hwmon_dev = NULL;
pr_err("hwmon registration failed (%d)\n", err);
return err;
}
return 0;
}
struct i8k_config_data {
uint fan_mult;
uint fan_max;
};
enum i8k_configs {
DELL_LATITUDE_D520,
DELL_PRECISION_490,
DELL_STUDIO,
DELL_XPS,
};
static const struct i8k_config_data i8k_config_data[] = {
[DELL_LATITUDE_D520] = {
.fan_mult = 1,
.fan_max = I8K_FAN_TURBO,
},
[DELL_PRECISION_490] = {
.fan_mult = 1,
.fan_max = I8K_FAN_TURBO,
},
[DELL_STUDIO] = {
.fan_mult = 1,
.fan_max = I8K_FAN_HIGH,
},
[DELL_XPS] = {
.fan_mult = 1,
.fan_max = I8K_FAN_HIGH,
},
};
static struct dmi_system_id i8k_dmi_table[] __initdata = {
{
.ident = "Dell Inspiron",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Computer"),
DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron"),
},
},
{
.ident = "Dell Latitude",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Computer"),
DMI_MATCH(DMI_PRODUCT_NAME, "Latitude"),
},
},
{
.ident = "Dell Inspiron 2",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron"),
},
},
{
.ident = "Dell Latitude D520",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "Latitude D520"),
},
.driver_data = (void *)&i8k_config_data[DELL_LATITUDE_D520],
},
{
.ident = "Dell Latitude 2",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "Latitude"),
},
},
{ /* UK Inspiron 6400 */
.ident = "Dell Inspiron 3",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "MM061"),
},
},
{
.ident = "Dell Inspiron 3",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "MP061"),
},
},
{
.ident = "Dell Precision 490",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME,
"Precision WorkStation 490"),
},
.driver_data = (void *)&i8k_config_data[DELL_PRECISION_490],
},
{
.ident = "Dell Precision",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "Precision"),
},
},
{
.ident = "Dell Vostro",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "Vostro"),
},
},
{
.ident = "Dell XPS421",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "XPS L421X"),
},
},
{
.ident = "Dell Studio",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "Studio"),
},
.driver_data = (void *)&i8k_config_data[DELL_STUDIO],
},
{
.ident = "Dell XPS 13",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "XPS13"),
},
.driver_data = (void *)&i8k_config_data[DELL_XPS],
},
{
.ident = "Dell XPS M140",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "MXC051"),
},
.driver_data = (void *)&i8k_config_data[DELL_XPS],
},
{ }
};
MODULE_DEVICE_TABLE(dmi, i8k_dmi_table);
/*
* On some machines once I8K_SMM_GET_FAN_TYPE is issued then CPU fan speed
* randomly going up and down due to bug in Dell SMM or BIOS. Here is blacklist
* of affected Dell machines for which we disallow I8K_SMM_GET_FAN_TYPE call.
* See bug: https://bugzilla.kernel.org/show_bug.cgi?id=100121
*/
static struct dmi_system_id i8k_blacklist_fan_type_dmi_table[] __initdata = {
{
.ident = "Dell Studio XPS 8000",
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Studio XPS 8000"),
},
},
{
.ident = "Dell Studio XPS 8100",
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Studio XPS 8100"),
},
},
{
.ident = "Dell Inspiron 580",
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Inspiron 580 "),
},
},
{ }
};
/*
* Probe for the presence of a supported laptop.
*/
static int __init i8k_probe(void)
{
const struct dmi_system_id *id;
int fan, ret;
/*
* Get DMI information
*/
if (!dmi_check_system(i8k_dmi_table)) {
if (!ignore_dmi && !force)
return -ENODEV;
pr_info("not running on a supported Dell system.\n");
pr_info("vendor=%s, model=%s, version=%s\n",
i8k_get_dmi_data(DMI_SYS_VENDOR),
i8k_get_dmi_data(DMI_PRODUCT_NAME),
i8k_get_dmi_data(DMI_BIOS_VERSION));
}
if (dmi_check_system(i8k_blacklist_fan_type_dmi_table))
disallow_fan_type_call = true;
strlcpy(bios_version, i8k_get_dmi_data(DMI_BIOS_VERSION),
sizeof(bios_version));
strlcpy(bios_machineid, i8k_get_dmi_data(DMI_PRODUCT_SERIAL),
sizeof(bios_machineid));
/*
* Get SMM Dell signature
*/
if (i8k_get_dell_signature(I8K_SMM_GET_DELL_SIG1) &&
i8k_get_dell_signature(I8K_SMM_GET_DELL_SIG2)) {
pr_err("unable to get SMM Dell signature\n");
if (!force)
return -ENODEV;
}
/*
* Set fan multiplier and maximal fan speed from dmi config
* Values specified in module parameters override values from dmi
*/
id = dmi_first_match(i8k_dmi_table);
if (id && id->driver_data) {
const struct i8k_config_data *conf = id->driver_data;
if (!fan_mult && conf->fan_mult)
fan_mult = conf->fan_mult;
if (!fan_max && conf->fan_max)
fan_max = conf->fan_max;
}
i8k_fan_max = fan_max ? : I8K_FAN_HIGH; /* Must not be 0 */
i8k_pwm_mult = DIV_ROUND_UP(255, i8k_fan_max);
if (!fan_mult) {
/*
* Autodetect fan multiplier based on nominal rpm
* If fan reports rpm value too high then set multiplier to 1
*/
for (fan = 0; fan < 2; ++fan) {
ret = i8k_get_fan_nominal_speed(fan, i8k_fan_max);
if (ret < 0)
continue;
if (ret > I8K_FAN_MAX_RPM)
i8k_fan_mult = 1;
break;
}
} else {
/* Fan multiplier was specified in module param or in dmi */
i8k_fan_mult = fan_mult;
}
return 0;
}
static int __init i8k_init(void)
{
int err;
/* Are we running on an supported laptop? */
if (i8k_probe())
return -ENODEV;
err = i8k_init_hwmon();
if (err)
return err;
i8k_init_procfs();
return 0;
}
static void __exit i8k_exit(void)
{
hwmon_device_unregister(i8k_hwmon_dev);
i8k_exit_procfs();
}
module_init(i8k_init);
module_exit(i8k_exit);
| null | null | null | null | 102,357 |
9,011 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 9,011 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2016 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef NET_HTTP2_DECODER_PAYLOAD_DECODERS_WINDOW_UPDATE_PAYLOAD_DECODER_H_
#define NET_HTTP2_DECODER_PAYLOAD_DECODERS_WINDOW_UPDATE_PAYLOAD_DECODER_H_
// Decodes the payload of a WINDOW_UPDATE frame.
#include "net/http2/decoder/decode_buffer.h"
#include "net/http2/decoder/decode_status.h"
#include "net/http2/decoder/frame_decoder_state.h"
#include "net/http2/http2_structures.h"
#include "net/http2/platform/api/http2_export.h"
namespace net {
namespace test {
class WindowUpdatePayloadDecoderPeer;
} // namespace test
class HTTP2_EXPORT_PRIVATE WindowUpdatePayloadDecoder {
public:
// Starts decoding a WINDOW_UPDATE frame's payload, and completes it if
// the entire payload is in the provided decode buffer.
DecodeStatus StartDecodingPayload(FrameDecoderState* state, DecodeBuffer* db);
// Resumes decoding a WINDOW_UPDATE frame's payload that has been split across
// decode buffers.
DecodeStatus ResumeDecodingPayload(FrameDecoderState* state,
DecodeBuffer* db);
private:
friend class test::WindowUpdatePayloadDecoderPeer;
DecodeStatus HandleStatus(FrameDecoderState* state, DecodeStatus status);
Http2WindowUpdateFields window_update_fields_;
};
} // namespace net
#endif // NET_HTTP2_DECODER_PAYLOAD_DECODERS_WINDOW_UPDATE_PAYLOAD_DECODER_H_
| null | null | null | null | 5,874 |
13,148 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 13,148 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "components/password_manager/core/browser/password_store_sync.h"
namespace password_manager {
PasswordStoreSync::PasswordStoreSync() = default;
PasswordStoreSync::~PasswordStoreSync() = default;
} // namespace password_manager
| null | null | null | null | 10,011 |
32,353 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 197,348 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*******************************************************************************
* This file contains main functions related to iSCSI DataSequenceInOrder=No
* and DataPDUInOrder=No.
*
* (c) Copyright 2007-2013 Datera, Inc.
*
* Author: Nicholas A. Bellinger <nab@linux-iscsi.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
******************************************************************************/
#include <linux/slab.h>
#include <linux/random.h>
#include <target/iscsi/iscsi_target_core.h>
#include "iscsi_target_util.h"
#include "iscsi_target_tpg.h"
#include "iscsi_target_seq_pdu_list.h"
#define OFFLOAD_BUF_SIZE 32768
#ifdef DEBUG
static void iscsit_dump_seq_list(struct iscsi_cmd *cmd)
{
int i;
struct iscsi_seq *seq;
pr_debug("Dumping Sequence List for ITT: 0x%08x:\n",
cmd->init_task_tag);
for (i = 0; i < cmd->seq_count; i++) {
seq = &cmd->seq_list[i];
pr_debug("i: %d, pdu_start: %d, pdu_count: %d,"
" offset: %d, xfer_len: %d, seq_send_order: %d,"
" seq_no: %d\n", i, seq->pdu_start, seq->pdu_count,
seq->offset, seq->xfer_len, seq->seq_send_order,
seq->seq_no);
}
}
static void iscsit_dump_pdu_list(struct iscsi_cmd *cmd)
{
int i;
struct iscsi_pdu *pdu;
pr_debug("Dumping PDU List for ITT: 0x%08x:\n",
cmd->init_task_tag);
for (i = 0; i < cmd->pdu_count; i++) {
pdu = &cmd->pdu_list[i];
pr_debug("i: %d, offset: %d, length: %d,"
" pdu_send_order: %d, seq_no: %d\n", i, pdu->offset,
pdu->length, pdu->pdu_send_order, pdu->seq_no);
}
}
#else
static void iscsit_dump_seq_list(struct iscsi_cmd *cmd) {}
static void iscsit_dump_pdu_list(struct iscsi_cmd *cmd) {}
#endif
static void iscsit_ordered_seq_lists(
struct iscsi_cmd *cmd,
u8 type)
{
u32 i, seq_count = 0;
for (i = 0; i < cmd->seq_count; i++) {
if (cmd->seq_list[i].type != SEQTYPE_NORMAL)
continue;
cmd->seq_list[i].seq_send_order = seq_count++;
}
}
static void iscsit_ordered_pdu_lists(
struct iscsi_cmd *cmd,
u8 type)
{
u32 i, pdu_send_order = 0, seq_no = 0;
for (i = 0; i < cmd->pdu_count; i++) {
redo:
if (cmd->pdu_list[i].seq_no == seq_no) {
cmd->pdu_list[i].pdu_send_order = pdu_send_order++;
continue;
}
seq_no++;
pdu_send_order = 0;
goto redo;
}
}
/*
* Generate count random values into array.
* Use 0x80000000 to mark generates valued in array[].
*/
static void iscsit_create_random_array(u32 *array, u32 count)
{
int i, j, k;
if (count == 1) {
array[0] = 0;
return;
}
for (i = 0; i < count; i++) {
redo:
get_random_bytes(&j, sizeof(u32));
j = (1 + (int) (9999 + 1) - j) % count;
for (k = 0; k < i + 1; k++) {
j |= 0x80000000;
if ((array[k] & 0x80000000) && (array[k] == j))
goto redo;
}
array[i] = j;
}
for (i = 0; i < count; i++)
array[i] &= ~0x80000000;
}
static int iscsit_randomize_pdu_lists(
struct iscsi_cmd *cmd,
u8 type)
{
int i = 0;
u32 *array, pdu_count, seq_count = 0, seq_no = 0, seq_offset = 0;
for (pdu_count = 0; pdu_count < cmd->pdu_count; pdu_count++) {
redo:
if (cmd->pdu_list[pdu_count].seq_no == seq_no) {
seq_count++;
continue;
}
array = kcalloc(seq_count, sizeof(u32), GFP_KERNEL);
if (!array) {
pr_err("Unable to allocate memory"
" for random array.\n");
return -ENOMEM;
}
iscsit_create_random_array(array, seq_count);
for (i = 0; i < seq_count; i++)
cmd->pdu_list[seq_offset+i].pdu_send_order = array[i];
kfree(array);
seq_offset += seq_count;
seq_count = 0;
seq_no++;
goto redo;
}
if (seq_count) {
array = kcalloc(seq_count, sizeof(u32), GFP_KERNEL);
if (!array) {
pr_err("Unable to allocate memory for"
" random array.\n");
return -ENOMEM;
}
iscsit_create_random_array(array, seq_count);
for (i = 0; i < seq_count; i++)
cmd->pdu_list[seq_offset+i].pdu_send_order = array[i];
kfree(array);
}
return 0;
}
static int iscsit_randomize_seq_lists(
struct iscsi_cmd *cmd,
u8 type)
{
int i, j = 0;
u32 *array, seq_count = cmd->seq_count;
if ((type == PDULIST_IMMEDIATE) || (type == PDULIST_UNSOLICITED))
seq_count--;
else if (type == PDULIST_IMMEDIATE_AND_UNSOLICITED)
seq_count -= 2;
if (!seq_count)
return 0;
array = kcalloc(seq_count, sizeof(u32), GFP_KERNEL);
if (!array) {
pr_err("Unable to allocate memory for random array.\n");
return -ENOMEM;
}
iscsit_create_random_array(array, seq_count);
for (i = 0; i < cmd->seq_count; i++) {
if (cmd->seq_list[i].type != SEQTYPE_NORMAL)
continue;
cmd->seq_list[i].seq_send_order = array[j++];
}
kfree(array);
return 0;
}
static void iscsit_determine_counts_for_list(
struct iscsi_cmd *cmd,
struct iscsi_build_list *bl,
u32 *seq_count,
u32 *pdu_count)
{
int check_immediate = 0;
u32 burstlength = 0, offset = 0;
u32 unsolicited_data_length = 0;
u32 mdsl;
struct iscsi_conn *conn = cmd->conn;
if (cmd->se_cmd.data_direction == DMA_TO_DEVICE)
mdsl = cmd->conn->conn_ops->MaxXmitDataSegmentLength;
else
mdsl = cmd->conn->conn_ops->MaxRecvDataSegmentLength;
if ((bl->type == PDULIST_IMMEDIATE) ||
(bl->type == PDULIST_IMMEDIATE_AND_UNSOLICITED))
check_immediate = 1;
if ((bl->type == PDULIST_UNSOLICITED) ||
(bl->type == PDULIST_IMMEDIATE_AND_UNSOLICITED))
unsolicited_data_length = min(cmd->se_cmd.data_length,
conn->sess->sess_ops->FirstBurstLength);
while (offset < cmd->se_cmd.data_length) {
*pdu_count += 1;
if (check_immediate) {
check_immediate = 0;
offset += bl->immediate_data_length;
*seq_count += 1;
if (unsolicited_data_length)
unsolicited_data_length -=
bl->immediate_data_length;
continue;
}
if (unsolicited_data_length > 0) {
if ((offset + mdsl) >= cmd->se_cmd.data_length) {
unsolicited_data_length -=
(cmd->se_cmd.data_length - offset);
offset += (cmd->se_cmd.data_length - offset);
continue;
}
if ((offset + mdsl)
>= conn->sess->sess_ops->FirstBurstLength) {
unsolicited_data_length -=
(conn->sess->sess_ops->FirstBurstLength -
offset);
offset += (conn->sess->sess_ops->FirstBurstLength -
offset);
burstlength = 0;
*seq_count += 1;
continue;
}
offset += mdsl;
unsolicited_data_length -= mdsl;
continue;
}
if ((offset + mdsl) >= cmd->se_cmd.data_length) {
offset += (cmd->se_cmd.data_length - offset);
continue;
}
if ((burstlength + mdsl) >=
conn->sess->sess_ops->MaxBurstLength) {
offset += (conn->sess->sess_ops->MaxBurstLength -
burstlength);
burstlength = 0;
*seq_count += 1;
continue;
}
burstlength += mdsl;
offset += mdsl;
}
}
/*
* Builds PDU and/or Sequence list, called while DataSequenceInOrder=No
* or DataPDUInOrder=No.
*/
static int iscsit_do_build_pdu_and_seq_lists(
struct iscsi_cmd *cmd,
struct iscsi_build_list *bl)
{
int check_immediate = 0, datapduinorder, datasequenceinorder;
u32 burstlength = 0, offset = 0, i = 0, mdsl;
u32 pdu_count = 0, seq_no = 0, unsolicited_data_length = 0;
struct iscsi_conn *conn = cmd->conn;
struct iscsi_pdu *pdu = cmd->pdu_list;
struct iscsi_seq *seq = cmd->seq_list;
if (cmd->se_cmd.data_direction == DMA_TO_DEVICE)
mdsl = cmd->conn->conn_ops->MaxXmitDataSegmentLength;
else
mdsl = cmd->conn->conn_ops->MaxRecvDataSegmentLength;
datapduinorder = conn->sess->sess_ops->DataPDUInOrder;
datasequenceinorder = conn->sess->sess_ops->DataSequenceInOrder;
if ((bl->type == PDULIST_IMMEDIATE) ||
(bl->type == PDULIST_IMMEDIATE_AND_UNSOLICITED))
check_immediate = 1;
if ((bl->type == PDULIST_UNSOLICITED) ||
(bl->type == PDULIST_IMMEDIATE_AND_UNSOLICITED))
unsolicited_data_length = min(cmd->se_cmd.data_length,
conn->sess->sess_ops->FirstBurstLength);
while (offset < cmd->se_cmd.data_length) {
pdu_count++;
if (!datapduinorder) {
pdu[i].offset = offset;
pdu[i].seq_no = seq_no;
}
if (!datasequenceinorder && (pdu_count == 1)) {
seq[seq_no].pdu_start = i;
seq[seq_no].seq_no = seq_no;
seq[seq_no].offset = offset;
seq[seq_no].orig_offset = offset;
}
if (check_immediate) {
check_immediate = 0;
if (!datapduinorder) {
pdu[i].type = PDUTYPE_IMMEDIATE;
pdu[i++].length = bl->immediate_data_length;
}
if (!datasequenceinorder) {
seq[seq_no].type = SEQTYPE_IMMEDIATE;
seq[seq_no].pdu_count = 1;
seq[seq_no].xfer_len =
bl->immediate_data_length;
}
offset += bl->immediate_data_length;
pdu_count = 0;
seq_no++;
if (unsolicited_data_length)
unsolicited_data_length -=
bl->immediate_data_length;
continue;
}
if (unsolicited_data_length > 0) {
if ((offset + mdsl) >= cmd->se_cmd.data_length) {
if (!datapduinorder) {
pdu[i].type = PDUTYPE_UNSOLICITED;
pdu[i].length =
(cmd->se_cmd.data_length - offset);
}
if (!datasequenceinorder) {
seq[seq_no].type = SEQTYPE_UNSOLICITED;
seq[seq_no].pdu_count = pdu_count;
seq[seq_no].xfer_len = (burstlength +
(cmd->se_cmd.data_length - offset));
}
unsolicited_data_length -=
(cmd->se_cmd.data_length - offset);
offset += (cmd->se_cmd.data_length - offset);
continue;
}
if ((offset + mdsl) >=
conn->sess->sess_ops->FirstBurstLength) {
if (!datapduinorder) {
pdu[i].type = PDUTYPE_UNSOLICITED;
pdu[i++].length =
(conn->sess->sess_ops->FirstBurstLength -
offset);
}
if (!datasequenceinorder) {
seq[seq_no].type = SEQTYPE_UNSOLICITED;
seq[seq_no].pdu_count = pdu_count;
seq[seq_no].xfer_len = (burstlength +
(conn->sess->sess_ops->FirstBurstLength -
offset));
}
unsolicited_data_length -=
(conn->sess->sess_ops->FirstBurstLength -
offset);
offset += (conn->sess->sess_ops->FirstBurstLength -
offset);
burstlength = 0;
pdu_count = 0;
seq_no++;
continue;
}
if (!datapduinorder) {
pdu[i].type = PDUTYPE_UNSOLICITED;
pdu[i++].length = mdsl;
}
burstlength += mdsl;
offset += mdsl;
unsolicited_data_length -= mdsl;
continue;
}
if ((offset + mdsl) >= cmd->se_cmd.data_length) {
if (!datapduinorder) {
pdu[i].type = PDUTYPE_NORMAL;
pdu[i].length = (cmd->se_cmd.data_length - offset);
}
if (!datasequenceinorder) {
seq[seq_no].type = SEQTYPE_NORMAL;
seq[seq_no].pdu_count = pdu_count;
seq[seq_no].xfer_len = (burstlength +
(cmd->se_cmd.data_length - offset));
}
offset += (cmd->se_cmd.data_length - offset);
continue;
}
if ((burstlength + mdsl) >=
conn->sess->sess_ops->MaxBurstLength) {
if (!datapduinorder) {
pdu[i].type = PDUTYPE_NORMAL;
pdu[i++].length =
(conn->sess->sess_ops->MaxBurstLength -
burstlength);
}
if (!datasequenceinorder) {
seq[seq_no].type = SEQTYPE_NORMAL;
seq[seq_no].pdu_count = pdu_count;
seq[seq_no].xfer_len = (burstlength +
(conn->sess->sess_ops->MaxBurstLength -
burstlength));
}
offset += (conn->sess->sess_ops->MaxBurstLength -
burstlength);
burstlength = 0;
pdu_count = 0;
seq_no++;
continue;
}
if (!datapduinorder) {
pdu[i].type = PDUTYPE_NORMAL;
pdu[i++].length = mdsl;
}
burstlength += mdsl;
offset += mdsl;
}
if (!datasequenceinorder) {
if (bl->data_direction & ISCSI_PDU_WRITE) {
if (bl->randomize & RANDOM_R2T_OFFSETS) {
if (iscsit_randomize_seq_lists(cmd, bl->type)
< 0)
return -1;
} else
iscsit_ordered_seq_lists(cmd, bl->type);
} else if (bl->data_direction & ISCSI_PDU_READ) {
if (bl->randomize & RANDOM_DATAIN_SEQ_OFFSETS) {
if (iscsit_randomize_seq_lists(cmd, bl->type)
< 0)
return -1;
} else
iscsit_ordered_seq_lists(cmd, bl->type);
}
iscsit_dump_seq_list(cmd);
}
if (!datapduinorder) {
if (bl->data_direction & ISCSI_PDU_WRITE) {
if (bl->randomize & RANDOM_DATAOUT_PDU_OFFSETS) {
if (iscsit_randomize_pdu_lists(cmd, bl->type)
< 0)
return -1;
} else
iscsit_ordered_pdu_lists(cmd, bl->type);
} else if (bl->data_direction & ISCSI_PDU_READ) {
if (bl->randomize & RANDOM_DATAIN_PDU_OFFSETS) {
if (iscsit_randomize_pdu_lists(cmd, bl->type)
< 0)
return -1;
} else
iscsit_ordered_pdu_lists(cmd, bl->type);
}
iscsit_dump_pdu_list(cmd);
}
return 0;
}
int iscsit_build_pdu_and_seq_lists(
struct iscsi_cmd *cmd,
u32 immediate_data_length)
{
struct iscsi_build_list bl;
u32 pdu_count = 0, seq_count = 1;
struct iscsi_conn *conn = cmd->conn;
struct iscsi_pdu *pdu = NULL;
struct iscsi_seq *seq = NULL;
struct iscsi_session *sess = conn->sess;
struct iscsi_node_attrib *na;
/*
* Do nothing if no OOO shenanigans
*/
if (sess->sess_ops->DataSequenceInOrder &&
sess->sess_ops->DataPDUInOrder)
return 0;
if (cmd->data_direction == DMA_NONE)
return 0;
na = iscsit_tpg_get_node_attrib(sess);
memset(&bl, 0, sizeof(struct iscsi_build_list));
if (cmd->data_direction == DMA_FROM_DEVICE) {
bl.data_direction = ISCSI_PDU_READ;
bl.type = PDULIST_NORMAL;
if (na->random_datain_pdu_offsets)
bl.randomize |= RANDOM_DATAIN_PDU_OFFSETS;
if (na->random_datain_seq_offsets)
bl.randomize |= RANDOM_DATAIN_SEQ_OFFSETS;
} else {
bl.data_direction = ISCSI_PDU_WRITE;
bl.immediate_data_length = immediate_data_length;
if (na->random_r2t_offsets)
bl.randomize |= RANDOM_R2T_OFFSETS;
if (!cmd->immediate_data && !cmd->unsolicited_data)
bl.type = PDULIST_NORMAL;
else if (cmd->immediate_data && !cmd->unsolicited_data)
bl.type = PDULIST_IMMEDIATE;
else if (!cmd->immediate_data && cmd->unsolicited_data)
bl.type = PDULIST_UNSOLICITED;
else if (cmd->immediate_data && cmd->unsolicited_data)
bl.type = PDULIST_IMMEDIATE_AND_UNSOLICITED;
}
iscsit_determine_counts_for_list(cmd, &bl, &seq_count, &pdu_count);
if (!conn->sess->sess_ops->DataSequenceInOrder) {
seq = kcalloc(seq_count, sizeof(struct iscsi_seq), GFP_ATOMIC);
if (!seq) {
pr_err("Unable to allocate struct iscsi_seq list\n");
return -ENOMEM;
}
cmd->seq_list = seq;
cmd->seq_count = seq_count;
}
if (!conn->sess->sess_ops->DataPDUInOrder) {
pdu = kcalloc(pdu_count, sizeof(struct iscsi_pdu), GFP_ATOMIC);
if (!pdu) {
pr_err("Unable to allocate struct iscsi_pdu list.\n");
kfree(seq);
return -ENOMEM;
}
cmd->pdu_list = pdu;
cmd->pdu_count = pdu_count;
}
return iscsit_do_build_pdu_and_seq_lists(cmd, &bl);
}
struct iscsi_pdu *iscsit_get_pdu_holder(
struct iscsi_cmd *cmd,
u32 offset,
u32 length)
{
u32 i;
struct iscsi_pdu *pdu = NULL;
if (!cmd->pdu_list) {
pr_err("struct iscsi_cmd->pdu_list is NULL!\n");
return NULL;
}
pdu = &cmd->pdu_list[0];
for (i = 0; i < cmd->pdu_count; i++)
if ((pdu[i].offset == offset) && (pdu[i].length == length))
return &pdu[i];
pr_err("Unable to locate PDU holder for ITT: 0x%08x, Offset:"
" %u, Length: %u\n", cmd->init_task_tag, offset, length);
return NULL;
}
struct iscsi_pdu *iscsit_get_pdu_holder_for_seq(
struct iscsi_cmd *cmd,
struct iscsi_seq *seq)
{
u32 i;
struct iscsi_conn *conn = cmd->conn;
struct iscsi_pdu *pdu = NULL;
if (!cmd->pdu_list) {
pr_err("struct iscsi_cmd->pdu_list is NULL!\n");
return NULL;
}
if (conn->sess->sess_ops->DataSequenceInOrder) {
redo:
pdu = &cmd->pdu_list[cmd->pdu_start];
for (i = 0; pdu[i].seq_no != cmd->seq_no; i++) {
pr_debug("pdu[i].seq_no: %d, pdu[i].pdu"
"_send_order: %d, pdu[i].offset: %d,"
" pdu[i].length: %d\n", pdu[i].seq_no,
pdu[i].pdu_send_order, pdu[i].offset,
pdu[i].length);
if (pdu[i].pdu_send_order == cmd->pdu_send_order) {
cmd->pdu_send_order++;
return &pdu[i];
}
}
cmd->pdu_start += cmd->pdu_send_order;
cmd->pdu_send_order = 0;
cmd->seq_no++;
if (cmd->pdu_start < cmd->pdu_count)
goto redo;
pr_err("Command ITT: 0x%08x unable to locate"
" struct iscsi_pdu for cmd->pdu_send_order: %u.\n",
cmd->init_task_tag, cmd->pdu_send_order);
return NULL;
} else {
if (!seq) {
pr_err("struct iscsi_seq is NULL!\n");
return NULL;
}
pr_debug("seq->pdu_start: %d, seq->pdu_count: %d,"
" seq->seq_no: %d\n", seq->pdu_start, seq->pdu_count,
seq->seq_no);
pdu = &cmd->pdu_list[seq->pdu_start];
if (seq->pdu_send_order == seq->pdu_count) {
pr_err("Command ITT: 0x%08x seq->pdu_send"
"_order: %u equals seq->pdu_count: %u\n",
cmd->init_task_tag, seq->pdu_send_order,
seq->pdu_count);
return NULL;
}
for (i = 0; i < seq->pdu_count; i++) {
if (pdu[i].pdu_send_order == seq->pdu_send_order) {
seq->pdu_send_order++;
return &pdu[i];
}
}
pr_err("Command ITT: 0x%08x unable to locate iscsi"
"_pdu_t for seq->pdu_send_order: %u.\n",
cmd->init_task_tag, seq->pdu_send_order);
return NULL;
}
return NULL;
}
struct iscsi_seq *iscsit_get_seq_holder(
struct iscsi_cmd *cmd,
u32 offset,
u32 length)
{
u32 i;
if (!cmd->seq_list) {
pr_err("struct iscsi_cmd->seq_list is NULL!\n");
return NULL;
}
for (i = 0; i < cmd->seq_count; i++) {
pr_debug("seq_list[i].orig_offset: %d, seq_list[i]."
"xfer_len: %d, seq_list[i].seq_no %u\n",
cmd->seq_list[i].orig_offset, cmd->seq_list[i].xfer_len,
cmd->seq_list[i].seq_no);
if ((cmd->seq_list[i].orig_offset +
cmd->seq_list[i].xfer_len) >=
(offset + length))
return &cmd->seq_list[i];
}
pr_err("Unable to locate Sequence holder for ITT: 0x%08x,"
" Offset: %u, Length: %u\n", cmd->init_task_tag, offset,
length);
return NULL;
}
| null | null | null | null | 105,695 |
58,356 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 58,356 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2016 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chrome/browser/data_use_measurement/chrome_data_use_ascriber.h"
#include <list>
#include <memory>
#include "base/message_loop/message_loop.h"
#include "base/run_loop.h"
#include "base/test/scoped_feature_list.h"
#include "build/build_config.h"
#include "components/data_use_measurement/core/data_use_recorder.h"
#include "content/public/browser/resource_request_info.h"
#include "content/public/common/browser_side_navigation_policy.h"
#include "content/public/common/previews_state.h"
#include "content/public/common/process_type.h"
#include "content/public/test/mock_resource_context.h"
#include "content/public/test/test_browser_thread_bundle.h"
#include "net/traffic_annotation/network_traffic_annotation_test_helper.h"
#include "net/url_request/url_request_test_util.h"
#include "testing/gmock/include/gmock/gmock.h"
#include "testing/gtest/include/gtest/gtest.h"
namespace {
int kRenderProcessId = 1;
int kRenderFrameId = 2;
int kRequestId = 3;
uint32_t kPageTransition = 5;
void* kNavigationHandle = &kNavigationHandle;
class MockPageLoadObserver
: public data_use_measurement::DataUseAscriber::PageLoadObserver {
public:
MOCK_METHOD1(OnPageLoadCommit, void(data_use_measurement::DataUse* data_use));
MOCK_METHOD2(OnPageResourceLoad,
void(const net::URLRequest& request,
data_use_measurement::DataUse* data_use));
MOCK_METHOD1(OnPageDidFinishLoad,
void(data_use_measurement::DataUse* data_use));
MOCK_METHOD1(OnPageLoadConcluded,
void(data_use_measurement::DataUse* data_use));
MOCK_METHOD2(OnNetworkBytesUpdate,
void(const net::URLRequest& request,
data_use_measurement::DataUse* data_use));
};
} // namespace
namespace data_use_measurement {
class ChromeDataUseAscriberTest : public testing::Test {
protected:
ChromeDataUseAscriberTest()
: thread_bundle_(content::TestBrowserThreadBundle::IO_MAINLOOP),
resource_context_(new content::MockResourceContext(&context_)) {}
void SetUp() override {}
void TearDown() override { recorders().clear(); }
void CreateAscriber() {
ascriber_ = std::make_unique<ChromeDataUseAscriber>();
}
std::list<ChromeDataUseRecorder>& recorders() {
return ascriber_->data_use_recorders_;
}
net::TestURLRequestContext* context() { return &context_; }
content::MockResourceContext* resource_context() {
return resource_context_.get();
}
ChromeDataUseAscriber* ascriber() { return ascriber_.get(); }
std::unique_ptr<net::URLRequest> CreateNewRequest(std::string url,
bool is_main_frame,
int request_id,
int render_process_id,
int render_frame_id) {
std::unique_ptr<net::URLRequest> request = context()->CreateRequest(
GURL(url), net::IDLE, nullptr, TRAFFIC_ANNOTATION_FOR_TESTS);
// TODO(kundaji): Allow request_id to be specified in AllocateForTesting.
content::ResourceRequestInfo::AllocateForTesting(
request.get(),
is_main_frame ? content::RESOURCE_TYPE_MAIN_FRAME
: content::RESOURCE_TYPE_SCRIPT,
resource_context(), render_process_id,
/*render_view_id=*/-1, render_frame_id, is_main_frame,
/*allow_download=*/false,
/*is_async=*/true, content::PREVIEWS_OFF,
/*navigation_ui_data*/ nullptr);
return request;
}
private:
content::TestBrowserThreadBundle thread_bundle_;
std::unique_ptr<ChromeDataUseAscriber> ascriber_;
net::TestURLRequestContext context_;
std::unique_ptr<content::MockResourceContext> resource_context_;
};
TEST_F(ChromeDataUseAscriberTest, NoRecorderWithoutFrame) {
CreateAscriber();
std::unique_ptr<net::URLRequest> request = CreateNewRequest(
"http://test.com", true, kRequestId, kRenderProcessId, kRenderFrameId);
// Main frame request causes a recorder to be created.
ascriber()->OnBeforeUrlRequest(request.get());
EXPECT_EQ(1u, recorders().size());
// Frame is created.
ascriber()->RenderFrameCreated(kRenderProcessId, kRenderFrameId, -1, -1);
EXPECT_EQ(2u, recorders().size());
// Same mainframe request should not cause another recorder to be created.
ascriber()->OnBeforeUrlRequest(request.get());
EXPECT_EQ(2u, recorders().size());
ascriber()->OnUrlRequestDestroyed(request.get());
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://test.com"), false,
kPageTransition, base::TimeTicks::Now());
EXPECT_EQ(1u, recorders().size());
ascriber()->RenderFrameDeleted(kRenderProcessId, kRenderFrameId, -1, -1);
EXPECT_EQ(0u, recorders().size());
}
TEST_F(ChromeDataUseAscriberTest, RenderFrameShownAndHidden) {
CreateAscriber();
std::unique_ptr<net::URLRequest> request = CreateNewRequest(
"http://test.com", true, kRequestId, kRenderProcessId, kRenderFrameId);
ascriber()->RenderFrameCreated(kRenderProcessId, kRenderFrameId, -1, -1);
ascriber()->OnBeforeUrlRequest(request.get());
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://test.com"), false,
kPageTransition, base::TimeTicks::Now());
ascriber()->WasShownOrHidden(kRenderProcessId, kRenderFrameId, true);
EXPECT_TRUE(ascriber()->GetDataUseRecorder(*request)->is_visible());
// Hide the frame, and the visibility should be updated.
ascriber()->WasShownOrHidden(kRenderProcessId, kRenderFrameId, false);
EXPECT_FALSE(ascriber()->GetDataUseRecorder(*request)->is_visible());
ascriber()->RenderFrameDeleted(kRenderProcessId, kRenderFrameId, -1, -1);
ascriber()->OnUrlRequestDestroyed(request.get());
EXPECT_EQ(0u, recorders().size());
}
TEST_F(ChromeDataUseAscriberTest, RenderFrameHiddenAndShown) {
CreateAscriber();
std::unique_ptr<net::URLRequest> request = CreateNewRequest(
"http://test.com", true, kRequestId, kRenderProcessId, kRenderFrameId);
ascriber()->RenderFrameCreated(kRenderProcessId, kRenderFrameId, -1, -1);
ascriber()->OnBeforeUrlRequest(request.get());
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://test.com"), false,
kPageTransition, base::TimeTicks::Now());
ascriber()->WasShownOrHidden(kRenderProcessId, kRenderFrameId, false);
EXPECT_FALSE(ascriber()->GetDataUseRecorder(*request)->is_visible());
// Show the frame, and the visibility should be updated.
ascriber()->WasShownOrHidden(kRenderProcessId, kRenderFrameId, true);
EXPECT_TRUE(ascriber()->GetDataUseRecorder(*request)->is_visible());
ascriber()->RenderFrameDeleted(kRenderProcessId, kRenderFrameId, -1, -1);
ascriber()->OnUrlRequestDestroyed(request.get());
EXPECT_EQ(0u, recorders().size());
}
TEST_F(ChromeDataUseAscriberTest, RenderFrameHostChanged) {
CreateAscriber();
std::unique_ptr<net::URLRequest> request = CreateNewRequest(
"http://test.com", true, kRequestId, kRenderProcessId, kRenderFrameId);
ascriber()->RenderFrameCreated(kRenderProcessId, kRenderFrameId, -1, -1);
ascriber()->OnBeforeUrlRequest(request.get());
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://test.com"), false,
kPageTransition, base::TimeTicks::Now());
ascriber()->WasShownOrHidden(kRenderProcessId, kRenderFrameId, true);
EXPECT_TRUE(ascriber()->GetDataUseRecorder(*request)->is_visible());
// Create a new render frame and swap it.
ascriber()->RenderFrameCreated(kRenderProcessId + 1, kRenderFrameId + 1, -1,
-1);
ascriber()->RenderFrameHostChanged(kRenderProcessId, kRenderFrameId,
kRenderProcessId + 1, kRenderFrameId + 1);
ascriber()->RenderFrameDeleted(kRenderProcessId, kRenderFrameId, -1, -1);
ascriber()->WasShownOrHidden(kRenderProcessId + 1, kRenderFrameId + 1, true);
ascriber()->RenderFrameDeleted(kRenderProcessId + 1, kRenderFrameId + 1, -1,
-1);
ascriber()->OnUrlRequestDestroyed(request.get());
EXPECT_EQ(0u, recorders().size());
}
TEST_F(ChromeDataUseAscriberTest, MainFrameNavigation) {
CreateAscriber();
std::unique_ptr<net::URLRequest> request = CreateNewRequest(
"http://test.com", true, kRequestId, kRenderProcessId, kRenderFrameId);
// Mainframe is created.
ascriber()->RenderFrameCreated(kRenderProcessId, kRenderFrameId, -1, -1);
EXPECT_EQ(1u, recorders().size());
// Request should cause a recorder to be created.
ascriber()->OnBeforeUrlRequest(request.get());
EXPECT_EQ(2u, recorders().size());
// Navigation commits.
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://mobile.test.com"), false,
kPageTransition, base::TimeTicks::Now());
// Navigation commit should merge the two data use recorder entries.
EXPECT_EQ(1u, recorders().size());
auto& recorder_entry = recorders().front();
EXPECT_EQ(RenderFrameHostID(kRenderProcessId, kRenderFrameId),
recorder_entry.main_frame_id());
EXPECT_EQ(content::GlobalRequestID(kRenderProcessId, 0),
recorder_entry.main_frame_request_id());
EXPECT_EQ(GURL("http://mobile.test.com"), recorder_entry.data_use().url());
EXPECT_EQ(DataUse::TrafficType::USER_TRAFFIC,
recorder_entry.data_use().traffic_type());
ascriber()->RenderFrameDeleted(kRenderProcessId, kRenderFrameId, -1, -1);
ascriber()->OnUrlRequestDestroyed(request.get());
EXPECT_EQ(0u, recorders().size());
}
TEST_F(ChromeDataUseAscriberTest, SubResourceRequestsAttributed) {
CreateAscriber();
// A regression test that verifies that subframe requests in the second page
// load in the same frame get attributed to the entry correctly.
std::unique_ptr<net::URLRequest> page_load_a_main_frame_request =
CreateNewRequest("http://test.com", true, kRequestId, kRenderProcessId,
kRenderFrameId);
ascriber()->RenderFrameCreated(kRenderProcessId, kRenderFrameId, -1, -1);
// Start the main frame reuqest.
ascriber()->OnBeforeUrlRequest(page_load_a_main_frame_request.get());
// Commit the page load.
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://mobile.test.com"), false,
kPageTransition, base::TimeTicks::Now());
std::unique_ptr<net::URLRequest> page_load_b_main_frame_request =
CreateNewRequest("http://test_2.com", true, kRequestId + 1,
kRenderProcessId, kRenderFrameId);
std::unique_ptr<net::URLRequest> page_load_b_sub_request =
CreateNewRequest("http://test_2.com/s", false, kRequestId + 2,
kRenderProcessId, kRenderFrameId);
// Start the second main frame request.
ascriber()->OnBeforeUrlRequest(page_load_b_main_frame_request.get());
// Commit the second page load.
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://mobile.test_2.com"), false,
kPageTransition, base::TimeTicks::Now());
// Delete the first main frame request.
ascriber()->OnUrlRequestDestroyed(page_load_a_main_frame_request.get());
// Start the sub resource request for the second page load.
ascriber()->OnBeforeUrlRequest(page_load_b_sub_request.get());
ascriber()->OnNetworkBytesReceived(page_load_b_sub_request.get(), 100);
EXPECT_EQ(1u, recorders().size());
auto& recorder_entry = recorders().front();
EXPECT_EQ(RenderFrameHostID(kRenderProcessId, kRenderFrameId),
recorder_entry.main_frame_id());
EXPECT_EQ(content::GlobalRequestID(kRenderProcessId, 0),
recorder_entry.main_frame_request_id());
EXPECT_EQ(GURL("http://mobile.test_2.com"), recorder_entry.data_use().url());
EXPECT_EQ(DataUse::TrafficType::USER_TRAFFIC,
recorder_entry.data_use().traffic_type());
// Verify that the data usage for the sub-resource was counted towards the
// entry.
EXPECT_EQ(100, recorder_entry.data_use().total_bytes_received());
ascriber()->OnUrlRequestDestroyed(page_load_b_sub_request.get());
ascriber()->OnUrlRequestDestroyed(page_load_b_main_frame_request.get());
ascriber()->RenderFrameDeleted(kRenderProcessId, kRenderFrameId, -1, -1);
EXPECT_EQ(0u, recorders().size());
}
// Verifies that navigation finish acts as the event that separates pageloads.
// subresource requests started before the navigation commit has finished are
// ascribed to the previous page load at the time of the commit, and requests
// started after are ascribed to the next page load.
TEST_F(ChromeDataUseAscriberTest, SubResourceRequestsAfterNavigationFinish) {
CreateAscriber();
std::unique_ptr<net::URLRequest> page_load_a_mainresource = CreateNewRequest(
"http://test.com", true, kRequestId, kRenderProcessId, kRenderFrameId);
std::unique_ptr<net::URLRequest> page_load_a_subresource =
CreateNewRequest("http://test.com/subresource", false, kRequestId + 1,
kRenderProcessId, kRenderFrameId);
// First page load 'a'.
ascriber()->RenderFrameCreated(kRenderProcessId, kRenderFrameId, -1, -1);
ascriber()->OnBeforeUrlRequest(page_load_a_mainresource.get());
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://mobile.test.com"), false,
kPageTransition, base::TimeTicks::Now());
ascriber()->OnBeforeUrlRequest(page_load_a_subresource.get());
ascriber()->OnUrlRequestDestroyed(page_load_a_mainresource.get());
ascriber()->OnNetworkBytesReceived(page_load_a_subresource.get(), 100);
EXPECT_EQ(1u, recorders().size());
auto& page_load_a_recorder = recorders().front();
EXPECT_EQ(RenderFrameHostID(kRenderProcessId, kRenderFrameId),
page_load_a_recorder.main_frame_id());
EXPECT_EQ(content::GlobalRequestID(kRenderProcessId, 0),
page_load_a_recorder.main_frame_request_id());
EXPECT_EQ(GURL("http://mobile.test.com"),
page_load_a_recorder.data_use().url());
EXPECT_EQ(DataUse::TrafficType::USER_TRAFFIC,
page_load_a_recorder.data_use().traffic_type());
std::unique_ptr<net::URLRequest> page_load_b_mainresource =
CreateNewRequest("http://test_2.com", true, kRequestId + 2,
kRenderProcessId, kRenderFrameId);
std::unique_ptr<net::URLRequest> page_load_b_subresource =
CreateNewRequest("http://test_2.com/subresource", false, kRequestId + 3,
kRenderProcessId, kRenderFrameId);
// Second page load 'b' on the same main render frame.
ascriber()->OnBeforeUrlRequest(page_load_b_mainresource.get());
EXPECT_EQ(100, page_load_a_recorder.data_use().total_bytes_received());
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://mobile.test_2.com"), false,
kPageTransition, base::TimeTicks::Now());
ascriber()->OnBeforeUrlRequest(page_load_b_subresource.get());
ascriber()->OnNetworkBytesReceived(page_load_b_subresource.get(), 200);
ascriber()->OnNetworkBytesReceived(page_load_a_subresource.get(), 100);
// Previous page recorder is gone.
EXPECT_EQ(1u, recorders().size());
auto& page_load_b_recorder = recorders().back();
EXPECT_EQ(RenderFrameHostID(kRenderProcessId, kRenderFrameId),
page_load_b_recorder.main_frame_id());
EXPECT_EQ(content::GlobalRequestID(kRenderProcessId, 0),
page_load_b_recorder.main_frame_request_id());
EXPECT_EQ(GURL("http://mobile.test_2.com"),
page_load_b_recorder.data_use().url());
EXPECT_EQ(DataUse::TrafficType::USER_TRAFFIC,
page_load_b_recorder.data_use().traffic_type());
// Verify the data usage.
EXPECT_EQ(200, page_load_b_recorder.data_use().total_bytes_received());
std::unique_ptr<net::URLRequest> page_load_c_mainresource =
CreateNewRequest("http://test_c.com", true, kRequestId + 2,
kRenderProcessId, kRenderFrameId);
std::unique_ptr<net::URLRequest> page_load_c_subresource =
CreateNewRequest("http://test_c.com/subresource", false, kRequestId + 3,
kRenderProcessId, kRenderFrameId);
// Third page load 'c' on the same main render frame with
// same_document_navigation set.
ascriber()->OnBeforeUrlRequest(page_load_c_mainresource.get());
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://mobile.test_c.com"), true,
kPageTransition, base::TimeTicks::Now());
ascriber()->OnBeforeUrlRequest(page_load_c_subresource.get());
ascriber()->OnNetworkBytesReceived(page_load_c_subresource.get(), 2000);
ascriber()->OnNetworkBytesReceived(page_load_b_subresource.get(), 1000);
// Data usage of page load 'c' should get merged to page load 'b'.
EXPECT_EQ(3200, page_load_b_recorder.data_use().total_bytes_received());
ascriber()->OnUrlRequestDestroyed(page_load_a_subresource.get());
ascriber()->OnUrlRequestDestroyed(page_load_b_subresource.get());
ascriber()->OnUrlRequestDestroyed(page_load_b_mainresource.get());
ascriber()->OnUrlRequestDestroyed(page_load_c_subresource.get());
ascriber()->OnUrlRequestDestroyed(page_load_c_mainresource.get());
ascriber()->RenderFrameDeleted(kRenderProcessId, kRenderFrameId, -1, -1);
EXPECT_EQ(0u, recorders().size());
}
TEST_F(ChromeDataUseAscriberTest, FailedMainFrameNavigation) {
CreateAscriber();
std::unique_ptr<net::URLRequest> request = CreateNewRequest(
"http://test.com", true, kRequestId, kRenderProcessId, kRenderFrameId);
// Mainframe is created.
ascriber()->RenderFrameCreated(kRenderProcessId, kRenderFrameId, -1, -1);
EXPECT_EQ(1u, recorders().size());
// Request should cause a recorder to be created.
ascriber()->OnBeforeUrlRequest(request.get());
EXPECT_EQ(2u, recorders().size());
// Failed request will remove the pending entry.
request->Cancel();
ascriber()->OnUrlRequestCompleted(request.get(), false);
ascriber()->RenderFrameDeleted(kRenderProcessId, kRenderFrameId, -1, -1);
ascriber()->OnUrlRequestDestroyed(request.get());
EXPECT_EQ(0u, recorders().size());
}
TEST_F(ChromeDataUseAscriberTest, PageLoadObserverNotified) {
CreateAscriber();
// TODO(rajendrant): Handle PlzNavigate (http://crbug/664233).
MockPageLoadObserver mock_observer;
ascriber()->AddObserver(&mock_observer);
std::unique_ptr<net::URLRequest> request = CreateNewRequest(
"http://test.com", true, kRequestId, kRenderProcessId, kRenderFrameId);
// Mainframe is created.
ascriber()->RenderFrameCreated(kRenderProcessId, kRenderFrameId, -1, -1);
EXPECT_EQ(1u, recorders().size());
ascriber()->OnBeforeUrlRequest(request.get());
// Navigation starts and is ready to commit.
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
EXPECT_EQ(2u, recorders().size());
DataUse* data_use = &recorders().back().data_use();
EXPECT_CALL(mock_observer, OnNetworkBytesUpdate(testing::_, data_use))
.Times(2);
ascriber()->OnNetworkBytesSent(request.get(), 2);
ascriber()->OnNetworkBytesReceived(request.get(), 2);
EXPECT_CALL(mock_observer, OnPageResourceLoad(testing::_, data_use)).Times(1);
ascriber()->OnUrlRequestCompleted(request.get(), false);
EXPECT_CALL(mock_observer, OnPageLoadCommit(data_use)).Times(1);
EXPECT_CALL(mock_observer, OnPageLoadConcluded(testing::_)).Times(1);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://mobile.test.com"), false,
kPageTransition, base::TimeTicks::Now());
EXPECT_EQ(1u, recorders().size());
auto& recorder_entry = recorders().front();
EXPECT_EQ(RenderFrameHostID(kRenderProcessId, kRenderFrameId),
recorder_entry.main_frame_id());
EXPECT_EQ(content::GlobalRequestID(kRenderProcessId, 0),
recorder_entry.main_frame_request_id());
EXPECT_EQ(GURL("http://mobile.test.com"), recorder_entry.data_use().url());
EXPECT_CALL(mock_observer, OnPageDidFinishLoad(&recorder_entry.data_use()))
.Times(1);
ascriber()->DidFinishLoad(kRenderProcessId, kRenderFrameId,
GURL("http://mobile.test.com"));
EXPECT_CALL(mock_observer, OnPageLoadConcluded(&recorder_entry.data_use()))
.Times(1);
ascriber()->RenderFrameDeleted(kRenderProcessId, kRenderFrameId, -1, -1);
ascriber()->OnUrlRequestDestroyed(request.get());
EXPECT_EQ(0u, recorders().size());
}
TEST_F(ChromeDataUseAscriberTest, PageLoadObserverForErrorPageValidatedURL) {
CreateAscriber();
MockPageLoadObserver mock_observer;
ascriber()->AddObserver(&mock_observer);
std::unique_ptr<net::URLRequest> request = CreateNewRequest(
"http://test.com", true, kRequestId, kRenderProcessId, kRenderFrameId);
// Mainframe is created.
ascriber()->RenderFrameCreated(kRenderProcessId, kRenderFrameId, -1, -1);
EXPECT_EQ(1u, recorders().size());
ascriber()->OnBeforeUrlRequest(request.get());
// Navigation starts and is ready to commit.
ascriber()->ReadyToCommitMainFrameNavigation(
content::GlobalRequestID(kRenderProcessId, 0), kRenderProcessId,
kRenderFrameId);
EXPECT_EQ(2u, recorders().size());
DataUse* data_use = &recorders().back().data_use();
EXPECT_CALL(mock_observer, OnNetworkBytesUpdate(testing::_, data_use))
.Times(2);
ascriber()->OnNetworkBytesSent(request.get(), 2);
ascriber()->OnNetworkBytesReceived(request.get(), 2);
EXPECT_CALL(mock_observer, OnPageResourceLoad(testing::_, data_use)).Times(1);
ascriber()->OnUrlRequestCompleted(request.get(), false);
EXPECT_CALL(mock_observer, OnPageLoadCommit(data_use)).Times(1);
EXPECT_CALL(mock_observer, OnPageLoadConcluded(testing::_)).Times(1);
ascriber()->DidFinishMainFrameNavigation(
kRenderProcessId, kRenderFrameId, GURL("http://mobile.test.com"), false,
kPageTransition, base::TimeTicks::Now());
EXPECT_EQ(1u, recorders().size());
auto& recorder_entry = recorders().front();
EXPECT_EQ(RenderFrameHostID(kRenderProcessId, kRenderFrameId),
recorder_entry.main_frame_id());
EXPECT_EQ(content::GlobalRequestID(kRenderProcessId, 0),
recorder_entry.main_frame_request_id());
EXPECT_EQ(GURL("http://mobile.test.com"), recorder_entry.data_use().url());
// Now expect no DidFinishLoad observer call for "about:blank" validated URL.
EXPECT_CALL(mock_observer, OnPageDidFinishLoad(&recorder_entry.data_use()))
.Times(0);
ascriber()->DidFinishLoad(kRenderProcessId, kRenderFrameId,
GURL("about:blank"));
EXPECT_CALL(mock_observer, OnPageLoadConcluded(&recorder_entry.data_use()))
.Times(1);
ascriber()->RenderFrameDeleted(kRenderProcessId, kRenderFrameId, -1, -1);
ascriber()->OnUrlRequestDestroyed(request.get());
EXPECT_EQ(0u, recorders().size());
}
} // namespace data_use_measurement
| null | null | null | null | 55,219 |
5,469 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 5,469 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "ios/chrome/browser/sessions/ios_chrome_tab_restore_service_factory.h"
#include "base/memory/ptr_util.h"
#include "base/memory/singleton.h"
#include "components/keyed_service/ios/browser_state_dependency_manager.h"
#include "components/sessions/core/persistent_tab_restore_service.h"
#include "ios/chrome/browser/browser_state/chrome_browser_state.h"
#include "ios/chrome/browser/sessions/ios_chrome_tab_restore_service_client.h"
namespace {
std::unique_ptr<KeyedService> BuildTabRestoreService(
web::BrowserState* context) {
DCHECK(!context->IsOffTheRecord());
ios::ChromeBrowserState* browser_state =
ios::ChromeBrowserState::FromBrowserState(context);
return std::make_unique<sessions::PersistentTabRestoreService>(
base::WrapUnique(new IOSChromeTabRestoreServiceClient(browser_state)),
nullptr);
}
} // namespace
// static
sessions::TabRestoreService*
IOSChromeTabRestoreServiceFactory::GetForBrowserState(
ios::ChromeBrowserState* browser_state) {
return static_cast<sessions::TabRestoreService*>(
GetInstance()->GetServiceForBrowserState(browser_state, true));
}
// static
IOSChromeTabRestoreServiceFactory*
IOSChromeTabRestoreServiceFactory::GetInstance() {
return base::Singleton<IOSChromeTabRestoreServiceFactory>::get();
}
// static
BrowserStateKeyedServiceFactory::TestingFactoryFunction
IOSChromeTabRestoreServiceFactory::GetDefaultFactory() {
return &BuildTabRestoreService;
}
IOSChromeTabRestoreServiceFactory::IOSChromeTabRestoreServiceFactory()
: BrowserStateKeyedServiceFactory(
"TabRestoreService",
BrowserStateDependencyManager::GetInstance()) {}
IOSChromeTabRestoreServiceFactory::~IOSChromeTabRestoreServiceFactory() {}
bool IOSChromeTabRestoreServiceFactory::ServiceIsNULLWhileTesting() const {
return true;
}
std::unique_ptr<KeyedService>
IOSChromeTabRestoreServiceFactory::BuildServiceInstanceFor(
web::BrowserState* context) const {
return BuildTabRestoreService(context);
}
| null | null | null | null | 2,332 |
11,850 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 11,850 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef COMPONENTS_OMNIBOX_BROWSER_AUTOCOMPLETE_I18N_H_
#define COMPONENTS_OMNIBOX_BROWSER_AUTOCOMPLETE_I18N_H_
#include "base/strings/string16.h"
#include "third_party/icu/source/common/unicode/uchar.h"
// Functor for a simple 16-bit Unicode case-insensitive comparison. This is
// designed for the autocomplete system where we would rather get prefix lenths
// correct than handle all possible case sensitivity issues.
//
// Any time this is used the result will be incorrect in some cases that
// certain users will be able to discern. Ideally, this class would be deleted
// and we would do full Unicode case-sensitivity mappings using
// base::i18n::ToLower. However, ToLower can change the lengths of strings,
// making computations of offsets or prefix lengths difficult. Getting all
// edge cases correct will require careful implementation and testing. In the
// mean time, we use this simpler approach.
//
// This comparator will not handle combining accents properly since it compares
// 16-bit values in isolation. If the two strings use the same sequence of
// combining accents (this is the normal case) in both strings, it will work.
//
// Additionally, this comparator does not decode UTF sequences which is why it
// is called "UCS2". UTF-16 surrogates will be compared literally (i.e. "case-
// sensitively").
//
// There are also a few cases where the lower-case version of a character
// expands to more than one code point that will not be handled properly. Such
// characters will be compared case-sensitively.
struct SimpleCaseInsensitiveCompareUCS2 {
public:
bool operator()(base::char16 x, base::char16 y) const {
return u_tolower(x) == u_tolower(y);
}
};
#endif // COMPONENTS_OMNIBOX_BROWSER_AUTOCOMPLETE_I18N_H_
| null | null | null | null | 8,713 |
22,636 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 22,636 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "content/browser/renderer_host/render_widget_host_view_base.h"
#include "content/browser/renderer_host/display_util.h"
#include "testing/gtest/include/gtest/gtest.h"
#include "third_party/blink/public/platform/modules/screen_orientation/web_screen_orientation_type.h"
#include "ui/display/display.h"
namespace content {
namespace {
display::Display CreateDisplay(int width, int height, int angle) {
display::Display display;
display.SetRotationAsDegree(angle);
display.set_bounds(gfx::Rect(width, height));
return display;
}
} // anonymous namespace
TEST(RenderWidgetHostViewBaseTest, OrientationTypeForMobile) {
// Square display (width == height).
{
display::Display display = CreateDisplay(100, 100, 0);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_PORTRAIT_PRIMARY,
DisplayUtil::GetOrientationTypeForMobile(display));
display = CreateDisplay(200, 200, 90);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_LANDSCAPE_PRIMARY,
DisplayUtil::GetOrientationTypeForMobile(display));
display = CreateDisplay(0, 0, 180);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_PORTRAIT_SECONDARY,
DisplayUtil::GetOrientationTypeForMobile(display));
display = CreateDisplay(10000, 10000, 270);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_LANDSCAPE_SECONDARY,
DisplayUtil::GetOrientationTypeForMobile(display));
}
// natural width > natural height.
{
display::Display display = CreateDisplay(1, 0, 0);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_LANDSCAPE_PRIMARY,
DisplayUtil::GetOrientationTypeForMobile(display));
display = CreateDisplay(19999, 20000, 90);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_PORTRAIT_SECONDARY,
DisplayUtil::GetOrientationTypeForMobile(display));
display = CreateDisplay(200, 100, 180);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_LANDSCAPE_SECONDARY,
DisplayUtil::GetOrientationTypeForMobile(display));
display = CreateDisplay(1, 10000, 270);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_PORTRAIT_PRIMARY,
DisplayUtil::GetOrientationTypeForMobile(display));
}
// natural width < natural height.
{
display::Display display = CreateDisplay(0, 1, 0);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_PORTRAIT_PRIMARY,
DisplayUtil::GetOrientationTypeForMobile(display));
display = CreateDisplay(20000, 19999, 90);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_LANDSCAPE_PRIMARY,
DisplayUtil::GetOrientationTypeForMobile(display));
display = CreateDisplay(100, 200, 180);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_PORTRAIT_SECONDARY,
DisplayUtil::GetOrientationTypeForMobile(display));
display = CreateDisplay(10000, 1, 270);
EXPECT_EQ(SCREEN_ORIENTATION_VALUES_LANDSCAPE_SECONDARY,
DisplayUtil::GetOrientationTypeForMobile(display));
}
}
TEST(RenderWidgetHostViewBaseTest, OrientationTypeForDesktop) {
// On Desktop, the primary orientation is the first computed one so a test
// similar to OrientationTypeForMobile is not possible.
// Instead this test will only check one configuration and verify that the
// method reports two landscape and two portrait orientations with one primary
// and one secondary for each.
// natural width > natural height.
{
display::Display display = CreateDisplay(1, 0, 0);
ScreenOrientationValues landscape_1 =
DisplayUtil::GetOrientationTypeForDesktop(display);
EXPECT_TRUE(landscape_1 == SCREEN_ORIENTATION_VALUES_LANDSCAPE_PRIMARY ||
landscape_1 == SCREEN_ORIENTATION_VALUES_LANDSCAPE_SECONDARY);
display = CreateDisplay(200, 100, 180);
ScreenOrientationValues landscape_2 =
DisplayUtil::GetOrientationTypeForDesktop(display);
EXPECT_TRUE(landscape_2 == SCREEN_ORIENTATION_VALUES_LANDSCAPE_PRIMARY ||
landscape_2 == SCREEN_ORIENTATION_VALUES_LANDSCAPE_SECONDARY);
EXPECT_NE(landscape_1, landscape_2);
display = CreateDisplay(19999, 20000, 90);
ScreenOrientationValues portrait_1 =
DisplayUtil::GetOrientationTypeForDesktop(display);
EXPECT_TRUE(portrait_1 == SCREEN_ORIENTATION_VALUES_PORTRAIT_PRIMARY ||
portrait_1 == SCREEN_ORIENTATION_VALUES_PORTRAIT_SECONDARY);
display = CreateDisplay(1, 10000, 270);
ScreenOrientationValues portrait_2 =
DisplayUtil::GetOrientationTypeForDesktop(display);
EXPECT_TRUE(portrait_2 == SCREEN_ORIENTATION_VALUES_PORTRAIT_PRIMARY ||
portrait_2 == SCREEN_ORIENTATION_VALUES_PORTRAIT_SECONDARY);
EXPECT_NE(portrait_1, portrait_2);
}
}
} // namespace content
| null | null | null | null | 19,499 |
63,303 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 63,303 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chrome/browser/ui/views/permission_bubble/chooser_bubble_ui.h"
#include "base/strings/string16.h"
#include "chrome/browser/chooser_controller/chooser_controller.h"
#include "chrome/browser/ui/browser_dialogs.h"
#include "chrome/browser/ui/permission_bubble/chooser_bubble_delegate.h"
#include "chrome/browser/ui/views/bubble_anchor_util_views.h"
#include "chrome/browser/ui/views/device_chooser_content_view.h"
#include "components/bubble/bubble_controller.h"
#include "ui/views/bubble/bubble_dialog_delegate.h"
#include "ui/views/controls/button/label_button.h"
#include "ui/views/controls/styled_label.h"
#include "ui/views/controls/table/table_view_observer.h"
#include "ui/views/window/dialog_client_view.h"
namespace {
constexpr views::BubbleBorder::Arrow kChooserAnchorArrow =
views::BubbleBorder::TOP_LEFT;
views::View* GetChooserAnchorView(Browser* browser) {
return bubble_anchor_util::GetPageInfoAnchorView(browser);
}
gfx::Rect GetChooserAnchorRect(Browser* browser) {
return bubble_anchor_util::GetPageInfoAnchorRect(browser);
}
} // namespace
///////////////////////////////////////////////////////////////////////////////
// View implementation for the chooser bubble.
class ChooserBubbleUiViewDelegate : public views::BubbleDialogDelegateView,
public views::TableViewObserver {
public:
ChooserBubbleUiViewDelegate(
Browser* browser,
std::unique_ptr<ChooserController> chooser_controller);
~ChooserBubbleUiViewDelegate() override;
// views::WidgetDelegate:
base::string16 GetWindowTitle() const override;
// views::DialogDelegate:
base::string16 GetDialogButtonLabel(ui::DialogButton button) const override;
bool IsDialogButtonEnabled(ui::DialogButton button) const override;
views::View* GetInitiallyFocusedView() override;
views::View* CreateExtraView() override;
bool Accept() override;
bool Cancel() override;
bool Close() override;
// views::DialogDelegateView:
views::View* GetContentsView() override;
views::Widget* GetWidget() override;
const views::Widget* GetWidget() const override;
// views::TableViewObserver:
void OnSelectionChanged() override;
// Updates the anchor's arrow and view. Also repositions the bubble so it's
// displayed in the correct location.
void UpdateAnchor(Browser* browser);
void set_bubble_reference(BubbleReference bubble_reference);
void UpdateTableView() const;
private:
DeviceChooserContentView* device_chooser_content_view_;
BubbleReference bubble_reference_;
DISALLOW_COPY_AND_ASSIGN(ChooserBubbleUiViewDelegate);
};
ChooserBubbleUiViewDelegate::ChooserBubbleUiViewDelegate(
Browser* browser,
std::unique_ptr<ChooserController> chooser_controller)
: views::BubbleDialogDelegateView(GetChooserAnchorView(browser),
kChooserAnchorArrow),
device_chooser_content_view_(nullptr) {
// ------------------------------------
// | Chooser bubble title |
// | -------------------------------- |
// | | option 0 | |
// | | option 1 | |
// | | option 2 | |
// | | | |
// | | | |
// | | | |
// | -------------------------------- |
// | [ Connect ] [ Cancel ] |
// |----------------------------------|
// | Get help |
// ------------------------------------
device_chooser_content_view_ =
new DeviceChooserContentView(this, std::move(chooser_controller));
if (!GetAnchorView())
SetAnchorRect(GetChooserAnchorRect(browser));
chrome::RecordDialogCreation(chrome::DialogIdentifier::CHOOSER_UI);
}
ChooserBubbleUiViewDelegate::~ChooserBubbleUiViewDelegate() {}
base::string16 ChooserBubbleUiViewDelegate::GetWindowTitle() const {
return device_chooser_content_view_->GetWindowTitle();
}
views::View* ChooserBubbleUiViewDelegate::GetInitiallyFocusedView() {
return GetDialogClientView()->cancel_button();
}
base::string16 ChooserBubbleUiViewDelegate::GetDialogButtonLabel(
ui::DialogButton button) const {
return device_chooser_content_view_->GetDialogButtonLabel(button);
}
bool ChooserBubbleUiViewDelegate::IsDialogButtonEnabled(
ui::DialogButton button) const {
return device_chooser_content_view_->IsDialogButtonEnabled(button);
}
views::View* ChooserBubbleUiViewDelegate::CreateExtraView() {
std::unique_ptr<views::View> extra_view =
device_chooser_content_view_->CreateExtraView();
return extra_view ? extra_view.release() : nullptr;
}
bool ChooserBubbleUiViewDelegate::Accept() {
device_chooser_content_view_->Accept();
if (bubble_reference_)
bubble_reference_->CloseBubble(BUBBLE_CLOSE_ACCEPTED);
return true;
}
bool ChooserBubbleUiViewDelegate::Cancel() {
device_chooser_content_view_->Cancel();
if (bubble_reference_)
bubble_reference_->CloseBubble(BUBBLE_CLOSE_CANCELED);
return true;
}
bool ChooserBubbleUiViewDelegate::Close() {
device_chooser_content_view_->Close();
return true;
}
views::View* ChooserBubbleUiViewDelegate::GetContentsView() {
return device_chooser_content_view_;
}
views::Widget* ChooserBubbleUiViewDelegate::GetWidget() {
return device_chooser_content_view_->GetWidget();
}
const views::Widget* ChooserBubbleUiViewDelegate::GetWidget() const {
return device_chooser_content_view_->GetWidget();
}
void ChooserBubbleUiViewDelegate::OnSelectionChanged() {
DialogModelChanged();
}
void ChooserBubbleUiViewDelegate::UpdateAnchor(Browser* browser) {
views::View* anchor_view = GetChooserAnchorView(browser);
SetAnchorView(anchor_view);
if (!anchor_view)
SetAnchorRect(GetChooserAnchorRect(browser));
}
void ChooserBubbleUiViewDelegate::set_bubble_reference(
BubbleReference bubble_reference) {
bubble_reference_ = bubble_reference;
}
void ChooserBubbleUiViewDelegate::UpdateTableView() const {
device_chooser_content_view_->UpdateTableView();
}
//////////////////////////////////////////////////////////////////////////////
// ChooserBubbleUi
ChooserBubbleUi::ChooserBubbleUi(
Browser* browser,
std::unique_ptr<ChooserController> chooser_controller)
: browser_(browser), chooser_bubble_ui_view_delegate_(nullptr) {
DCHECK(browser_);
DCHECK(chooser_controller);
chooser_bubble_ui_view_delegate_ =
new ChooserBubbleUiViewDelegate(browser, std::move(chooser_controller));
}
ChooserBubbleUi::~ChooserBubbleUi() {
if (chooser_bubble_ui_view_delegate_ &&
chooser_bubble_ui_view_delegate_->GetWidget()) {
chooser_bubble_ui_view_delegate_->GetWidget()->RemoveObserver(this);
}
}
void ChooserBubbleUi::Show(BubbleReference bubble_reference) {
chooser_bubble_ui_view_delegate_->set_bubble_reference(bubble_reference);
CreateAndShow(chooser_bubble_ui_view_delegate_);
chooser_bubble_ui_view_delegate_->GetWidget()->AddObserver(this);
chooser_bubble_ui_view_delegate_->UpdateTableView();
}
void ChooserBubbleUi::Close() {
if (chooser_bubble_ui_view_delegate_ &&
!chooser_bubble_ui_view_delegate_->GetWidget()->IsClosed()) {
chooser_bubble_ui_view_delegate_->GetWidget()->Close();
}
}
void ChooserBubbleUi::UpdateAnchorPosition() {
if (chooser_bubble_ui_view_delegate_)
chooser_bubble_ui_view_delegate_->UpdateAnchor(browser_);
}
void ChooserBubbleUi::OnWidgetClosing(views::Widget* widget) {
widget->RemoveObserver(this);
chooser_bubble_ui_view_delegate_ = nullptr;
}
| null | null | null | null | 60,166 |
3,662 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 3,662 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef IOS_WEB_SHELL_SHELL_WEB_MAIN_PARTS_H_
#define IOS_WEB_SHELL_SHELL_WEB_MAIN_PARTS_H_
#include <memory>
#include "ios/web/public/app/web_main_parts.h"
namespace web {
class ShellBrowserState;
// Shell-specific implementation of WebMainParts.
class ShellWebMainParts : public WebMainParts {
public:
ShellWebMainParts();
~ShellWebMainParts() override;
ShellBrowserState* browser_state() const { return browser_state_.get(); }
// WebMainParts implementation.
void PreMainMessageLoopStart() override;
void PreMainMessageLoopRun() override;
private:
std::unique_ptr<ShellBrowserState> browser_state_;
};
} // namespace web
#endif // IOS_WEB_SHELL_SHELL_WEB_MAIN_PARTS_H_
| null | null | null | null | 525 |
20,085 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 20,085 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2017 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef CONTENT_PUBLIC_COMMON_MANIFEST_STRUCT_TRAITS_H_
#define CONTENT_PUBLIC_COMMON_MANIFEST_STRUCT_TRAITS_H_
#include "content/public/common/manifest.h"
#include "mojo/public/cpp/bindings/struct_traits.h"
#include "third_party/blink/public/platform/modules/manifest/manifest.mojom-shared.h"
namespace mojo {
namespace internal {
inline base::StringPiece16 TruncateString16(const base::string16& string) {
return base::StringPiece16(string).substr(
0, content::Manifest::kMaxIPCStringLength);
}
inline base::Optional<base::StringPiece16> TruncateNullableString16(
const base::NullableString16& string) {
if (string.is_null())
return base::nullopt;
return TruncateString16(string.string());
}
} // namespace internal
template <>
struct StructTraits<blink::mojom::ManifestDataView, content::Manifest> {
static bool IsNull(const content::Manifest& m) { return m.IsEmpty(); }
static void SetToNull(content::Manifest* m) { *m = content::Manifest(); }
static base::Optional<base::StringPiece16> name(const content::Manifest& m) {
return internal::TruncateNullableString16(m.name);
}
static base::Optional<base::StringPiece16> short_name(
const content::Manifest& m) {
return internal::TruncateNullableString16(m.short_name);
}
static base::Optional<base::StringPiece16> gcm_sender_id(
const content::Manifest& m) {
return internal::TruncateNullableString16(m.gcm_sender_id);
}
static const GURL& start_url(const content::Manifest& m) {
return m.start_url;
}
static const GURL& scope(const content::Manifest& m) { return m.scope; }
static blink::WebDisplayMode display(const content::Manifest& m) {
return m.display;
}
static blink::WebScreenOrientationLockType orientation(
const content::Manifest& m) {
return m.orientation;
}
static int64_t theme_color(const content::Manifest& m) {
return m.theme_color;
}
static int64_t background_color(const content::Manifest& m) {
return m.background_color;
}
static const GURL& splash_screen_url(const content::Manifest& m) {
return m.splash_screen_url;
}
static const std::vector<content::Manifest::Icon>& icons(
const content::Manifest& m) {
return m.icons;
}
static const base::Optional<content::Manifest::ShareTarget>& share_target(
const content::Manifest& m) {
return m.share_target;
}
static const std::vector<content::Manifest::RelatedApplication>&
related_applications(const content::Manifest& m) {
return m.related_applications;
}
static bool prefer_related_applications(const content::Manifest& m) {
return m.prefer_related_applications;
}
static bool Read(blink::mojom::ManifestDataView data, content::Manifest* out);
};
template <>
struct StructTraits<blink::mojom::ManifestIconDataView,
content::Manifest::Icon> {
static const GURL& src(const content::Manifest::Icon& m) { return m.src; }
static base::StringPiece16 type(const content::Manifest::Icon& m) {
return internal::TruncateString16(m.type);
}
static const std::vector<gfx::Size>& sizes(const content::Manifest::Icon& m) {
return m.sizes;
}
static const std::vector<content::Manifest::Icon::IconPurpose>& purpose(
const content::Manifest::Icon& m) {
return m.purpose;
}
static bool Read(blink::mojom::ManifestIconDataView data,
content::Manifest::Icon* out);
};
template <>
struct StructTraits<blink::mojom::ManifestRelatedApplicationDataView,
content::Manifest::RelatedApplication> {
static base::Optional<base::StringPiece16> platform(
const content::Manifest::RelatedApplication& m) {
return internal::TruncateNullableString16(m.platform);
}
static const GURL& url(const content::Manifest::RelatedApplication& m) {
return m.url;
}
static base::Optional<base::StringPiece16> id(
const content::Manifest::RelatedApplication& m) {
return internal::TruncateNullableString16(m.id);
}
static bool Read(blink::mojom::ManifestRelatedApplicationDataView data,
content::Manifest::RelatedApplication* out);
};
template <>
struct StructTraits<blink::mojom::ManifestShareTargetDataView,
content::Manifest::ShareTarget> {
static const GURL& url_template(const content::Manifest::ShareTarget& m) {
return m.url_template;
}
static bool Read(blink::mojom::ManifestShareTargetDataView data,
content::Manifest::ShareTarget* out);
};
template <>
struct EnumTraits<blink::mojom::ManifestIcon_Purpose,
content::Manifest::Icon::IconPurpose> {
static blink::mojom::ManifestIcon_Purpose ToMojom(
content::Manifest::Icon::IconPurpose purpose) {
switch (purpose) {
case content::Manifest::Icon::ANY:
return blink::mojom::ManifestIcon_Purpose::ANY;
case content::Manifest::Icon::BADGE:
return blink::mojom::ManifestIcon_Purpose::BADGE;
}
NOTREACHED();
return blink::mojom::ManifestIcon_Purpose::ANY;
}
static bool FromMojom(blink::mojom::ManifestIcon_Purpose input,
content::Manifest::Icon::IconPurpose* out) {
switch (input) {
case blink::mojom::ManifestIcon_Purpose::ANY:
*out = content::Manifest::Icon::ANY;
return true;
case blink::mojom::ManifestIcon_Purpose::BADGE:
*out = content::Manifest::Icon::BADGE;
return true;
}
return false;
}
};
} // namespace mojo
#endif // CONTENT_PUBLIC_COMMON_MANIFEST_STRUCT_TRAITS_H_
| null | null | null | null | 16,948 |
19,141 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 184,136 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*******************************************************************
* This file is part of the Emulex Linux Device Driver for *
* Fibre Channel Host Bus Adapters. *
* Copyright (C) 2017 Broadcom. All Rights Reserved. The term *
* “Broadcom” refers to Broadcom Limited and/or its subsidiaries. *
* Copyright (C) 2004-2016 Emulex. All rights reserved. *
* EMULEX and SLI are trademarks of Emulex. *
* www.broadcom.com *
* Portions Copyright (C) 2004-2005 Christoph Hellwig *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of version 2 of the GNU General *
* Public License as published by the Free Software Foundation. *
* This program is distributed in the hope that it will be useful. *
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
* TO BE LEGALLY INVALID. See the GNU General Public License for *
* more details, a copy of which can be found in the file COPYING *
* included with this package. *
*******************************************************************/
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/idr.h>
#include <linux/interrupt.h>
#include <linux/kthread.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/sched/signal.h>
#include <scsi/scsi.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_transport_fc.h>
#include "lpfc_hw4.h"
#include "lpfc_hw.h"
#include "lpfc_sli.h"
#include "lpfc_sli4.h"
#include "lpfc_nl.h"
#include "lpfc_disc.h"
#include "lpfc_scsi.h"
#include "lpfc.h"
#include "lpfc_logmsg.h"
#include "lpfc_crtn.h"
#include "lpfc_version.h"
#include "lpfc_vport.h"
inline void lpfc_vport_set_state(struct lpfc_vport *vport,
enum fc_vport_state new_state)
{
struct fc_vport *fc_vport = vport->fc_vport;
if (fc_vport) {
/*
* When the transport defines fc_vport_set state we will replace
* this code with the following line
*/
/* fc_vport_set_state(fc_vport, new_state); */
if (new_state != FC_VPORT_INITIALIZING)
fc_vport->vport_last_state = fc_vport->vport_state;
fc_vport->vport_state = new_state;
}
/* for all the error states we will set the invternal state to FAILED */
switch (new_state) {
case FC_VPORT_NO_FABRIC_SUPP:
case FC_VPORT_NO_FABRIC_RSCS:
case FC_VPORT_FABRIC_LOGOUT:
case FC_VPORT_FABRIC_REJ_WWN:
case FC_VPORT_FAILED:
vport->port_state = LPFC_VPORT_FAILED;
break;
case FC_VPORT_LINKDOWN:
vport->port_state = LPFC_VPORT_UNKNOWN;
break;
default:
/* do nothing */
break;
}
}
int
lpfc_alloc_vpi(struct lpfc_hba *phba)
{
unsigned long vpi;
spin_lock_irq(&phba->hbalock);
/* Start at bit 1 because vpi zero is reserved for the physical port */
vpi = find_next_zero_bit(phba->vpi_bmask, (phba->max_vpi + 1), 1);
if (vpi > phba->max_vpi)
vpi = 0;
else
set_bit(vpi, phba->vpi_bmask);
if (phba->sli_rev == LPFC_SLI_REV4)
phba->sli4_hba.max_cfg_param.vpi_used++;
spin_unlock_irq(&phba->hbalock);
return vpi;
}
static void
lpfc_free_vpi(struct lpfc_hba *phba, int vpi)
{
if (vpi == 0)
return;
spin_lock_irq(&phba->hbalock);
clear_bit(vpi, phba->vpi_bmask);
if (phba->sli_rev == LPFC_SLI_REV4)
phba->sli4_hba.max_cfg_param.vpi_used--;
spin_unlock_irq(&phba->hbalock);
}
static int
lpfc_vport_sparm(struct lpfc_hba *phba, struct lpfc_vport *vport)
{
LPFC_MBOXQ_t *pmb;
MAILBOX_t *mb;
struct lpfc_dmabuf *mp;
int rc;
pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
if (!pmb) {
return -ENOMEM;
}
mb = &pmb->u.mb;
rc = lpfc_read_sparam(phba, pmb, vport->vpi);
if (rc) {
mempool_free(pmb, phba->mbox_mem_pool);
return -ENOMEM;
}
/*
* Grab buffer pointer and clear context1 so we can use
* lpfc_sli_issue_box_wait
*/
mp = (struct lpfc_dmabuf *) pmb->context1;
pmb->context1 = NULL;
pmb->vport = vport;
rc = lpfc_sli_issue_mbox_wait(phba, pmb, phba->fc_ratov * 2);
if (rc != MBX_SUCCESS) {
if (signal_pending(current)) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT | LOG_VPORT,
"1830 Signal aborted mbxCmd x%x\n",
mb->mbxCommand);
lpfc_mbuf_free(phba, mp->virt, mp->phys);
kfree(mp);
if (rc != MBX_TIMEOUT)
mempool_free(pmb, phba->mbox_mem_pool);
return -EINTR;
} else {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT | LOG_VPORT,
"1818 VPort failed init, mbxCmd x%x "
"READ_SPARM mbxStatus x%x, rc = x%x\n",
mb->mbxCommand, mb->mbxStatus, rc);
lpfc_mbuf_free(phba, mp->virt, mp->phys);
kfree(mp);
if (rc != MBX_TIMEOUT)
mempool_free(pmb, phba->mbox_mem_pool);
return -EIO;
}
}
memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
sizeof (struct lpfc_name));
memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
sizeof (struct lpfc_name));
lpfc_mbuf_free(phba, mp->virt, mp->phys);
kfree(mp);
mempool_free(pmb, phba->mbox_mem_pool);
return 0;
}
static int
lpfc_valid_wwn_format(struct lpfc_hba *phba, struct lpfc_name *wwn,
const char *name_type)
{
/* ensure that IEEE format 1 addresses
* contain zeros in bits 59-48
*/
if (!((wwn->u.wwn[0] >> 4) == 1 &&
((wwn->u.wwn[0] & 0xf) != 0 || (wwn->u.wwn[1] & 0xf) != 0)))
return 1;
lpfc_printf_log(phba, KERN_ERR, LOG_VPORT,
"1822 Invalid %s: %02x:%02x:%02x:%02x:"
"%02x:%02x:%02x:%02x\n",
name_type,
wwn->u.wwn[0], wwn->u.wwn[1],
wwn->u.wwn[2], wwn->u.wwn[3],
wwn->u.wwn[4], wwn->u.wwn[5],
wwn->u.wwn[6], wwn->u.wwn[7]);
return 0;
}
static int
lpfc_unique_wwpn(struct lpfc_hba *phba, struct lpfc_vport *new_vport)
{
struct lpfc_vport *vport;
unsigned long flags;
spin_lock_irqsave(&phba->hbalock, flags);
list_for_each_entry(vport, &phba->port_list, listentry) {
if (vport == new_vport)
continue;
/* If they match, return not unique */
if (memcmp(&vport->fc_sparam.portName,
&new_vport->fc_sparam.portName,
sizeof(struct lpfc_name)) == 0) {
spin_unlock_irqrestore(&phba->hbalock, flags);
return 0;
}
}
spin_unlock_irqrestore(&phba->hbalock, flags);
return 1;
}
/**
* lpfc_discovery_wait - Wait for driver discovery to quiesce
* @vport: The virtual port for which this call is being executed.
*
* This driver calls this routine specifically from lpfc_vport_delete
* to enforce a synchronous execution of vport
* delete relative to discovery activities. The
* lpfc_vport_delete routine should not return until it
* can reasonably guarantee that discovery has quiesced.
* Post FDISC LOGO, the driver must wait until its SAN teardown is
* complete and all resources recovered before allowing
* cleanup.
*
* This routine does not require any locks held.
**/
static void lpfc_discovery_wait(struct lpfc_vport *vport)
{
struct lpfc_hba *phba = vport->phba;
uint32_t wait_flags = 0;
unsigned long wait_time_max;
unsigned long start_time;
wait_flags = FC_RSCN_MODE | FC_RSCN_DISCOVERY | FC_NLP_MORE |
FC_RSCN_DEFERRED | FC_NDISC_ACTIVE | FC_DISC_TMO;
/*
* The time constraint on this loop is a balance between the
* fabric RA_TOV value and dev_loss tmo. The driver's
* devloss_tmo is 10 giving this loop a 3x multiplier minimally.
*/
wait_time_max = msecs_to_jiffies(((phba->fc_ratov * 3) + 3) * 1000);
wait_time_max += jiffies;
start_time = jiffies;
while (time_before(jiffies, wait_time_max)) {
if ((vport->num_disc_nodes > 0) ||
(vport->fc_flag & wait_flags) ||
((vport->port_state > LPFC_VPORT_FAILED) &&
(vport->port_state < LPFC_VPORT_READY))) {
lpfc_printf_vlog(vport, KERN_INFO, LOG_VPORT,
"1833 Vport discovery quiesce Wait:"
" state x%x fc_flags x%x"
" num_nodes x%x, waiting 1000 msecs"
" total wait msecs x%x\n",
vport->port_state, vport->fc_flag,
vport->num_disc_nodes,
jiffies_to_msecs(jiffies - start_time));
msleep(1000);
} else {
/* Base case. Wait variants satisfied. Break out */
lpfc_printf_vlog(vport, KERN_INFO, LOG_VPORT,
"1834 Vport discovery quiesced:"
" state x%x fc_flags x%x"
" wait msecs x%x\n",
vport->port_state, vport->fc_flag,
jiffies_to_msecs(jiffies
- start_time));
break;
}
}
if (time_after(jiffies, wait_time_max))
lpfc_printf_vlog(vport, KERN_ERR, LOG_VPORT,
"1835 Vport discovery quiesce failed:"
" state x%x fc_flags x%x wait msecs x%x\n",
vport->port_state, vport->fc_flag,
jiffies_to_msecs(jiffies - start_time));
}
int
lpfc_vport_create(struct fc_vport *fc_vport, bool disable)
{
struct lpfc_nodelist *ndlp;
struct Scsi_Host *shost = fc_vport->shost;
struct lpfc_vport *pport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = pport->phba;
struct lpfc_vport *vport = NULL;
int instance;
int vpi;
int rc = VPORT_ERROR;
int status;
if ((phba->sli_rev < 3) || !(phba->cfg_enable_npiv)) {
lpfc_printf_log(phba, KERN_ERR, LOG_VPORT,
"1808 Create VPORT failed: "
"NPIV is not enabled: SLImode:%d\n",
phba->sli_rev);
rc = VPORT_INVAL;
goto error_out;
}
vpi = lpfc_alloc_vpi(phba);
if (vpi == 0) {
lpfc_printf_log(phba, KERN_ERR, LOG_VPORT,
"1809 Create VPORT failed: "
"Max VPORTs (%d) exceeded\n",
phba->max_vpi);
rc = VPORT_NORESOURCES;
goto error_out;
}
/* Assign an unused board number */
if ((instance = lpfc_get_instance()) < 0) {
lpfc_printf_log(phba, KERN_ERR, LOG_VPORT,
"1810 Create VPORT failed: Cannot get "
"instance number\n");
lpfc_free_vpi(phba, vpi);
rc = VPORT_NORESOURCES;
goto error_out;
}
vport = lpfc_create_port(phba, instance, &fc_vport->dev);
if (!vport) {
lpfc_printf_log(phba, KERN_ERR, LOG_VPORT,
"1811 Create VPORT failed: vpi x%x\n", vpi);
lpfc_free_vpi(phba, vpi);
rc = VPORT_NORESOURCES;
goto error_out;
}
vport->vpi = vpi;
lpfc_debugfs_initialize(vport);
if ((status = lpfc_vport_sparm(phba, vport))) {
if (status == -EINTR) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_VPORT,
"1831 Create VPORT Interrupted.\n");
rc = VPORT_ERROR;
} else {
lpfc_printf_vlog(vport, KERN_ERR, LOG_VPORT,
"1813 Create VPORT failed. "
"Cannot get sparam\n");
rc = VPORT_NORESOURCES;
}
lpfc_free_vpi(phba, vpi);
destroy_port(vport);
goto error_out;
}
u64_to_wwn(fc_vport->node_name, vport->fc_nodename.u.wwn);
u64_to_wwn(fc_vport->port_name, vport->fc_portname.u.wwn);
memcpy(&vport->fc_sparam.portName, vport->fc_portname.u.wwn, 8);
memcpy(&vport->fc_sparam.nodeName, vport->fc_nodename.u.wwn, 8);
if (!lpfc_valid_wwn_format(phba, &vport->fc_sparam.nodeName, "WWNN") ||
!lpfc_valid_wwn_format(phba, &vport->fc_sparam.portName, "WWPN")) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_VPORT,
"1821 Create VPORT failed. "
"Invalid WWN format\n");
lpfc_free_vpi(phba, vpi);
destroy_port(vport);
rc = VPORT_INVAL;
goto error_out;
}
if (!lpfc_unique_wwpn(phba, vport)) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_VPORT,
"1823 Create VPORT failed. "
"Duplicate WWN on HBA\n");
lpfc_free_vpi(phba, vpi);
destroy_port(vport);
rc = VPORT_INVAL;
goto error_out;
}
/* Create binary sysfs attribute for vport */
lpfc_alloc_sysfs_attr(vport);
/* Set the DFT_LUN_Q_DEPTH accordingly */
vport->cfg_lun_queue_depth = phba->pport->cfg_lun_queue_depth;
*(struct lpfc_vport **)fc_vport->dd_data = vport;
vport->fc_vport = fc_vport;
/* At this point we are fully registered with SCSI Layer. */
vport->load_flag |= FC_ALLOW_FDMI;
if (phba->cfg_enable_SmartSAN ||
(phba->cfg_fdmi_on == LPFC_FDMI_SUPPORT)) {
/* Setup appropriate attribute masks */
vport->fdmi_hba_mask = phba->pport->fdmi_hba_mask;
vport->fdmi_port_mask = phba->pport->fdmi_port_mask;
}
if ((phba->nvmet_support == 0) &&
((phba->cfg_enable_fc4_type == LPFC_ENABLE_BOTH) ||
(phba->cfg_enable_fc4_type == LPFC_ENABLE_NVME))) {
/* Create NVME binding with nvme_fc_transport. This
* ensures the vport is initialized.
*/
rc = lpfc_nvme_create_localport(vport);
if (rc) {
lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
"6003 %s status x%x\n",
"NVME registration failed, ",
rc);
goto error_out;
}
}
/*
* In SLI4, the vpi must be activated before it can be used
* by the port.
*/
if ((phba->sli_rev == LPFC_SLI_REV4) &&
(pport->fc_flag & FC_VFI_REGISTERED)) {
rc = lpfc_sli4_init_vpi(vport);
if (rc) {
lpfc_printf_log(phba, KERN_ERR, LOG_VPORT,
"1838 Failed to INIT_VPI on vpi %d "
"status %d\n", vpi, rc);
rc = VPORT_NORESOURCES;
lpfc_free_vpi(phba, vpi);
goto error_out;
}
} else if (phba->sli_rev == LPFC_SLI_REV4) {
/*
* Driver cannot INIT_VPI now. Set the flags to
* init_vpi when reg_vfi complete.
*/
vport->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
lpfc_vport_set_state(vport, FC_VPORT_LINKDOWN);
rc = VPORT_OK;
goto out;
}
if ((phba->link_state < LPFC_LINK_UP) ||
(pport->port_state < LPFC_FABRIC_CFG_LINK) ||
(phba->fc_topology == LPFC_TOPOLOGY_LOOP)) {
lpfc_vport_set_state(vport, FC_VPORT_LINKDOWN);
rc = VPORT_OK;
goto out;
}
if (disable) {
lpfc_vport_set_state(vport, FC_VPORT_DISABLED);
rc = VPORT_OK;
goto out;
}
/* Use the Physical nodes Fabric NDLP to determine if the link is
* up and ready to FDISC.
*/
ndlp = lpfc_findnode_did(phba->pport, Fabric_DID);
if (ndlp && NLP_CHK_NODE_ACT(ndlp) &&
ndlp->nlp_state == NLP_STE_UNMAPPED_NODE) {
if (phba->link_flag & LS_NPIV_FAB_SUPPORTED) {
lpfc_set_disctmo(vport);
lpfc_initial_fdisc(vport);
} else {
lpfc_vport_set_state(vport, FC_VPORT_NO_FABRIC_SUPP);
lpfc_printf_vlog(vport, KERN_ERR, LOG_ELS,
"0262 No NPIV Fabric support\n");
}
} else {
lpfc_vport_set_state(vport, FC_VPORT_FAILED);
}
rc = VPORT_OK;
out:
lpfc_printf_vlog(vport, KERN_ERR, LOG_VPORT,
"1825 Vport Created.\n");
lpfc_host_attrib_init(lpfc_shost_from_vport(vport));
error_out:
return rc;
}
static int
disable_vport(struct fc_vport *fc_vport)
{
struct lpfc_vport *vport = *(struct lpfc_vport **)fc_vport->dd_data;
struct lpfc_hba *phba = vport->phba;
struct lpfc_nodelist *ndlp = NULL, *next_ndlp = NULL;
long timeout;
struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
ndlp = lpfc_findnode_did(vport, Fabric_DID);
if (ndlp && NLP_CHK_NODE_ACT(ndlp)
&& phba->link_state >= LPFC_LINK_UP) {
vport->unreg_vpi_cmpl = VPORT_INVAL;
timeout = msecs_to_jiffies(phba->fc_ratov * 2000);
if (!lpfc_issue_els_npiv_logo(vport, ndlp))
while (vport->unreg_vpi_cmpl == VPORT_INVAL && timeout)
timeout = schedule_timeout(timeout);
}
lpfc_sli_host_down(vport);
/* Mark all nodes for discovery so we can remove them by
* calling lpfc_cleanup_rpis(vport, 1)
*/
list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
if (!NLP_CHK_NODE_ACT(ndlp))
continue;
if (ndlp->nlp_state == NLP_STE_UNUSED_NODE)
continue;
lpfc_disc_state_machine(vport, ndlp, NULL,
NLP_EVT_DEVICE_RECOVERY);
}
lpfc_cleanup_rpis(vport, 1);
lpfc_stop_vport_timers(vport);
lpfc_unreg_all_rpis(vport);
lpfc_unreg_default_rpis(vport);
/*
* Completion of unreg_vpi (lpfc_mbx_cmpl_unreg_vpi) does the
* scsi_host_put() to release the vport.
*/
lpfc_mbx_unreg_vpi(vport);
spin_lock_irq(shost->host_lock);
vport->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
spin_unlock_irq(shost->host_lock);
lpfc_vport_set_state(vport, FC_VPORT_DISABLED);
lpfc_printf_vlog(vport, KERN_ERR, LOG_VPORT,
"1826 Vport Disabled.\n");
return VPORT_OK;
}
static int
enable_vport(struct fc_vport *fc_vport)
{
struct lpfc_vport *vport = *(struct lpfc_vport **)fc_vport->dd_data;
struct lpfc_hba *phba = vport->phba;
struct lpfc_nodelist *ndlp = NULL;
struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
if ((phba->link_state < LPFC_LINK_UP) ||
(phba->fc_topology == LPFC_TOPOLOGY_LOOP)) {
lpfc_vport_set_state(vport, FC_VPORT_LINKDOWN);
return VPORT_OK;
}
spin_lock_irq(shost->host_lock);
vport->load_flag |= FC_LOADING;
if (vport->fc_flag & FC_VPORT_NEEDS_INIT_VPI) {
spin_unlock_irq(shost->host_lock);
lpfc_issue_init_vpi(vport);
goto out;
}
vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
spin_unlock_irq(shost->host_lock);
/* Use the Physical nodes Fabric NDLP to determine if the link is
* up and ready to FDISC.
*/
ndlp = lpfc_findnode_did(phba->pport, Fabric_DID);
if (ndlp && NLP_CHK_NODE_ACT(ndlp)
&& ndlp->nlp_state == NLP_STE_UNMAPPED_NODE) {
if (phba->link_flag & LS_NPIV_FAB_SUPPORTED) {
lpfc_set_disctmo(vport);
lpfc_initial_fdisc(vport);
} else {
lpfc_vport_set_state(vport, FC_VPORT_NO_FABRIC_SUPP);
lpfc_printf_vlog(vport, KERN_ERR, LOG_ELS,
"0264 No NPIV Fabric support\n");
}
} else {
lpfc_vport_set_state(vport, FC_VPORT_FAILED);
}
out:
lpfc_printf_vlog(vport, KERN_ERR, LOG_VPORT,
"1827 Vport Enabled.\n");
return VPORT_OK;
}
int
lpfc_vport_disable(struct fc_vport *fc_vport, bool disable)
{
if (disable)
return disable_vport(fc_vport);
else
return enable_vport(fc_vport);
}
int
lpfc_vport_delete(struct fc_vport *fc_vport)
{
struct lpfc_nodelist *ndlp = NULL;
struct lpfc_vport *vport = *(struct lpfc_vport **)fc_vport->dd_data;
struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
struct lpfc_hba *phba = vport->phba;
long timeout;
bool ns_ndlp_referenced = false;
if (vport->port_type == LPFC_PHYSICAL_PORT) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_VPORT,
"1812 vport_delete failed: Cannot delete "
"physical host\n");
return VPORT_ERROR;
}
/* If the vport is a static vport fail the deletion. */
if ((vport->vport_flag & STATIC_VPORT) &&
!(phba->pport->load_flag & FC_UNLOADING)) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_VPORT,
"1837 vport_delete failed: Cannot delete "
"static vport.\n");
return VPORT_ERROR;
}
spin_lock_irq(&phba->hbalock);
vport->load_flag |= FC_UNLOADING;
spin_unlock_irq(&phba->hbalock);
/*
* If we are not unloading the driver then prevent the vport_delete
* from happening until after this vport's discovery is finished.
*/
if (!(phba->pport->load_flag & FC_UNLOADING)) {
int check_count = 0;
while (check_count < ((phba->fc_ratov * 3) + 3) &&
vport->port_state > LPFC_VPORT_FAILED &&
vport->port_state < LPFC_VPORT_READY) {
check_count++;
msleep(1000);
}
if (vport->port_state > LPFC_VPORT_FAILED &&
vport->port_state < LPFC_VPORT_READY)
return -EAGAIN;
}
/*
* This is a bit of a mess. We want to ensure the shost doesn't get
* torn down until we're done with the embedded lpfc_vport structure.
*
* Beyond holding a reference for this function, we also need a
* reference for outstanding I/O requests we schedule during delete
* processing. But once we scsi_remove_host() we can no longer obtain
* a reference through scsi_host_get().
*
* So we take two references here. We release one reference at the
* bottom of the function -- after delinking the vport. And we
* release the other at the completion of the unreg_vpi that get's
* initiated after we've disposed of all other resources associated
* with the port.
*/
if (!scsi_host_get(shost))
return VPORT_INVAL;
if (!scsi_host_get(shost)) {
scsi_host_put(shost);
return VPORT_INVAL;
}
lpfc_free_sysfs_attr(vport);
lpfc_debugfs_terminate(vport);
/*
* The call to fc_remove_host might release the NameServer ndlp. Since
* we might need to use the ndlp to send the DA_ID CT command,
* increment the reference for the NameServer ndlp to prevent it from
* being released.
*/
ndlp = lpfc_findnode_did(vport, NameServer_DID);
if (ndlp && NLP_CHK_NODE_ACT(ndlp)) {
lpfc_nlp_get(ndlp);
ns_ndlp_referenced = true;
}
/* Remove FC host and then SCSI host with the vport */
fc_remove_host(shost);
scsi_remove_host(shost);
ndlp = lpfc_findnode_did(phba->pport, Fabric_DID);
/* In case of driver unload, we shall not perform fabric logo as the
* worker thread already stopped at this stage and, in this case, we
* can safely skip the fabric logo.
*/
if (phba->pport->load_flag & FC_UNLOADING) {
if (ndlp && NLP_CHK_NODE_ACT(ndlp) &&
ndlp->nlp_state == NLP_STE_UNMAPPED_NODE &&
phba->link_state >= LPFC_LINK_UP) {
/* First look for the Fabric ndlp */
ndlp = lpfc_findnode_did(vport, Fabric_DID);
if (!ndlp)
goto skip_logo;
else if (!NLP_CHK_NODE_ACT(ndlp)) {
ndlp = lpfc_enable_node(vport, ndlp,
NLP_STE_UNUSED_NODE);
if (!ndlp)
goto skip_logo;
}
/* Remove ndlp from vport npld list */
lpfc_dequeue_node(vport, ndlp);
/* Indicate free memory when release */
spin_lock_irq(&phba->ndlp_lock);
NLP_SET_FREE_REQ(ndlp);
spin_unlock_irq(&phba->ndlp_lock);
/* Kick off release ndlp when it can be safely done */
lpfc_nlp_put(ndlp);
}
goto skip_logo;
}
/* Otherwise, we will perform fabric logo as needed */
if (ndlp && NLP_CHK_NODE_ACT(ndlp) &&
ndlp->nlp_state == NLP_STE_UNMAPPED_NODE &&
phba->link_state >= LPFC_LINK_UP &&
phba->fc_topology != LPFC_TOPOLOGY_LOOP) {
if (vport->cfg_enable_da_id) {
timeout = msecs_to_jiffies(phba->fc_ratov * 2000);
if (!lpfc_ns_cmd(vport, SLI_CTNS_DA_ID, 0, 0))
while (vport->ct_flags && timeout)
timeout = schedule_timeout(timeout);
else
lpfc_printf_log(vport->phba, KERN_WARNING,
LOG_VPORT,
"1829 CT command failed to "
"delete objects on fabric\n");
}
/* First look for the Fabric ndlp */
ndlp = lpfc_findnode_did(vport, Fabric_DID);
if (!ndlp) {
/* Cannot find existing Fabric ndlp, allocate one */
ndlp = mempool_alloc(phba->nlp_mem_pool, GFP_KERNEL);
if (!ndlp)
goto skip_logo;
lpfc_nlp_init(vport, ndlp, Fabric_DID);
/* Indicate free memory when release */
NLP_SET_FREE_REQ(ndlp);
} else {
if (!NLP_CHK_NODE_ACT(ndlp)) {
ndlp = lpfc_enable_node(vport, ndlp,
NLP_STE_UNUSED_NODE);
if (!ndlp)
goto skip_logo;
}
/* Remove ndlp from vport list */
lpfc_dequeue_node(vport, ndlp);
spin_lock_irq(&phba->ndlp_lock);
if (!NLP_CHK_FREE_REQ(ndlp))
/* Indicate free memory when release */
NLP_SET_FREE_REQ(ndlp);
else {
/* Skip this if ndlp is already in free mode */
spin_unlock_irq(&phba->ndlp_lock);
goto skip_logo;
}
spin_unlock_irq(&phba->ndlp_lock);
}
/*
* If the vpi is not registered, then a valid FDISC doesn't
* exist and there is no need for a ELS LOGO. Just cleanup
* the ndlp.
*/
if (!(vport->vpi_state & LPFC_VPI_REGISTERED)) {
lpfc_nlp_put(ndlp);
goto skip_logo;
}
vport->unreg_vpi_cmpl = VPORT_INVAL;
timeout = msecs_to_jiffies(phba->fc_ratov * 2000);
if (!lpfc_issue_els_npiv_logo(vport, ndlp))
while (vport->unreg_vpi_cmpl == VPORT_INVAL && timeout)
timeout = schedule_timeout(timeout);
}
if (!(phba->pport->load_flag & FC_UNLOADING))
lpfc_discovery_wait(vport);
skip_logo:
/*
* If the NameServer ndlp has been incremented to allow the DA_ID CT
* command to be sent, decrement the ndlp now.
*/
if (ns_ndlp_referenced) {
ndlp = lpfc_findnode_did(vport, NameServer_DID);
lpfc_nlp_put(ndlp);
}
lpfc_cleanup(vport);
lpfc_sli_host_down(vport);
lpfc_stop_vport_timers(vport);
if (!(phba->pport->load_flag & FC_UNLOADING)) {
lpfc_unreg_all_rpis(vport);
lpfc_unreg_default_rpis(vport);
/*
* Completion of unreg_vpi (lpfc_mbx_cmpl_unreg_vpi)
* does the scsi_host_put() to release the vport.
*/
if (!(vport->vpi_state & LPFC_VPI_REGISTERED) ||
lpfc_mbx_unreg_vpi(vport))
scsi_host_put(shost);
} else
scsi_host_put(shost);
lpfc_free_vpi(phba, vport->vpi);
vport->work_port_events = 0;
spin_lock_irq(&phba->hbalock);
list_del_init(&vport->listentry);
spin_unlock_irq(&phba->hbalock);
lpfc_printf_vlog(vport, KERN_ERR, LOG_VPORT,
"1828 Vport Deleted.\n");
scsi_host_put(shost);
return VPORT_OK;
}
struct lpfc_vport **
lpfc_create_vport_work_array(struct lpfc_hba *phba)
{
struct lpfc_vport *port_iterator;
struct lpfc_vport **vports;
int index = 0;
vports = kzalloc((phba->max_vports + 1) * sizeof(struct lpfc_vport *),
GFP_KERNEL);
if (vports == NULL)
return NULL;
spin_lock_irq(&phba->hbalock);
list_for_each_entry(port_iterator, &phba->port_list, listentry) {
if (port_iterator->load_flag & FC_UNLOADING)
continue;
if (!scsi_host_get(lpfc_shost_from_vport(port_iterator))) {
lpfc_printf_vlog(port_iterator, KERN_ERR, LOG_VPORT,
"1801 Create vport work array FAILED: "
"cannot do scsi_host_get\n");
continue;
}
vports[index++] = port_iterator;
}
spin_unlock_irq(&phba->hbalock);
return vports;
}
void
lpfc_destroy_vport_work_array(struct lpfc_hba *phba, struct lpfc_vport **vports)
{
int i;
if (vports == NULL)
return;
for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
scsi_host_put(lpfc_shost_from_vport(vports[i]));
kfree(vports);
}
/**
* lpfc_vport_reset_stat_data - Reset the statistical data for the vport
* @vport: Pointer to vport object.
*
* This function resets the statistical data for the vport. This function
* is called with the host_lock held
**/
void
lpfc_vport_reset_stat_data(struct lpfc_vport *vport)
{
struct lpfc_nodelist *ndlp = NULL, *next_ndlp = NULL;
list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
if (!NLP_CHK_NODE_ACT(ndlp))
continue;
if (ndlp->lat_data)
memset(ndlp->lat_data, 0, LPFC_MAX_BUCKET_COUNT *
sizeof(struct lpfc_scsicmd_bkt));
}
}
/**
* lpfc_alloc_bucket - Allocate data buffer required for statistical data
* @vport: Pointer to vport object.
*
* This function allocates data buffer required for all the FC
* nodes of the vport to collect statistical data.
**/
void
lpfc_alloc_bucket(struct lpfc_vport *vport)
{
struct lpfc_nodelist *ndlp = NULL, *next_ndlp = NULL;
list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
if (!NLP_CHK_NODE_ACT(ndlp))
continue;
kfree(ndlp->lat_data);
ndlp->lat_data = NULL;
if (ndlp->nlp_state == NLP_STE_MAPPED_NODE) {
ndlp->lat_data = kcalloc(LPFC_MAX_BUCKET_COUNT,
sizeof(struct lpfc_scsicmd_bkt),
GFP_ATOMIC);
if (!ndlp->lat_data)
lpfc_printf_vlog(vport, KERN_ERR, LOG_NODE,
"0287 lpfc_alloc_bucket failed to "
"allocate statistical data buffer DID "
"0x%x\n", ndlp->nlp_DID);
}
}
}
/**
* lpfc_free_bucket - Free data buffer required for statistical data
* @vport: Pointer to vport object.
*
* Th function frees statistical data buffer of all the FC
* nodes of the vport.
**/
void
lpfc_free_bucket(struct lpfc_vport *vport)
{
struct lpfc_nodelist *ndlp = NULL, *next_ndlp = NULL;
list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
if (!NLP_CHK_NODE_ACT(ndlp))
continue;
kfree(ndlp->lat_data);
ndlp->lat_data = NULL;
}
}
| null | null | null | null | 92,483 |
4,332 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 169,327 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /* -*- mode: c; c-basic-offset: 8; -*-
* vim: noexpandtab sw=8 ts=8 sts=0:
*
* ocfs1_fs_compat.h
*
* OCFS1 volume header definitions. OCFS2 creates valid but unmountable
* OCFS1 volume headers on the first two sectors of an OCFS2 volume.
* This allows an OCFS1 volume to see the partition and cleanly fail to
* mount it.
*
* Copyright (C) 2002, 2004 Oracle. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License, version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this program; if not, write to the
* Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 021110-1307, USA.
*/
#ifndef _OCFS1_FS_COMPAT_H
#define _OCFS1_FS_COMPAT_H
#define OCFS1_MAX_VOL_SIGNATURE_LEN 128
#define OCFS1_MAX_MOUNT_POINT_LEN 128
#define OCFS1_MAX_VOL_ID_LENGTH 16
#define OCFS1_MAX_VOL_LABEL_LEN 64
#define OCFS1_MAX_CLUSTER_NAME_LEN 64
#define OCFS1_MAJOR_VERSION (2)
#define OCFS1_MINOR_VERSION (0)
#define OCFS1_VOLUME_SIGNATURE "OracleCFS"
/*
* OCFS1 superblock. Lives at sector 0.
*/
struct ocfs1_vol_disk_hdr
{
/*00*/ __u32 minor_version;
__u32 major_version;
/*08*/ __u8 signature[OCFS1_MAX_VOL_SIGNATURE_LEN];
/*88*/ __u8 mount_point[OCFS1_MAX_MOUNT_POINT_LEN];
/*108*/ __u64 serial_num;
/*110*/ __u64 device_size;
__u64 start_off;
/*120*/ __u64 bitmap_off;
__u64 publ_off;
/*130*/ __u64 vote_off;
__u64 root_bitmap_off;
/*140*/ __u64 data_start_off;
__u64 root_bitmap_size;
/*150*/ __u64 root_off;
__u64 root_size;
/*160*/ __u64 cluster_size;
__u64 num_nodes;
/*170*/ __u64 num_clusters;
__u64 dir_node_size;
/*180*/ __u64 file_node_size;
__u64 internal_off;
/*190*/ __u64 node_cfg_off;
__u64 node_cfg_size;
/*1A0*/ __u64 new_cfg_off;
__u32 prot_bits;
__s32 excl_mount;
/*1B0*/
};
struct ocfs1_disk_lock
{
/*00*/ __u32 curr_master;
__u8 file_lock;
__u8 compat_pad[3]; /* Not in original definition. Used to
make the already existing alignment
explicit */
__u64 last_write_time;
/*10*/ __u64 last_read_time;
__u32 writer_node_num;
__u32 reader_node_num;
/*20*/ __u64 oin_node_map;
__u64 dlock_seq_num;
/*30*/
};
/*
* OCFS1 volume label. Lives at sector 1.
*/
struct ocfs1_vol_label
{
/*00*/ struct ocfs1_disk_lock disk_lock;
/*30*/ __u8 label[OCFS1_MAX_VOL_LABEL_LEN];
/*70*/ __u16 label_len;
/*72*/ __u8 vol_id[OCFS1_MAX_VOL_ID_LENGTH];
/*82*/ __u16 vol_id_len;
/*84*/ __u8 cluster_name[OCFS1_MAX_CLUSTER_NAME_LEN];
/*A4*/ __u16 cluster_name_len;
/*A6*/
};
#endif /* _OCFS1_FS_COMPAT_H */
| null | null | null | null | 77,674 |
7,336 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 7,336 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2016 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef NET_QUIC_CORE_FRAMES_QUIC_PING_FRAME_H_
#define NET_QUIC_CORE_FRAMES_QUIC_PING_FRAME_H_
#include "net/quic/core/frames/quic_control_frame.h"
namespace net {
// A ping frame contains no payload, though it is retransmittable,
// and ACK'd just like other normal frames.
struct QUIC_EXPORT_PRIVATE QuicPingFrame : public QuicControlFrame {
QuicPingFrame();
explicit QuicPingFrame(QuicControlFrameId control_frame_id);
friend QUIC_EXPORT_PRIVATE std::ostream& operator<<(
std::ostream& os,
const QuicPingFrame& ping_frame);
};
} // namespace net
#endif // NET_QUIC_CORE_FRAMES_QUIC_PING_FRAME_H_
| null | null | null | null | 4,199 |
29,667 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 29,667 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | /*
** 2008 Jan 22
**
** The author disclaims copyright to this source code. In place of
** a legal notice, here is a blessing:
**
** May you do good and not evil.
** May you find forgiveness for yourself and forgive others.
** May you share freely, never taking more than you give.
**
*************************************************************************
**
** This file contains code to support the concept of "benign"
** malloc failures (when the xMalloc() or xRealloc() method of the
** sqlite3_mem_methods structure fails to allocate a block of memory
** and returns 0).
**
** Most malloc failures are non-benign. After they occur, SQLite
** abandons the current operation and returns an error code (usually
** SQLITE_NOMEM) to the user. However, sometimes a fault is not necessarily
** fatal. For example, if a malloc fails while resizing a hash table, this
** is completely recoverable simply by not carrying out the resize. The
** hash table will continue to function normally. So a malloc failure
** during a hash table resize is a benign fault.
*/
#include "sqliteInt.h"
#ifndef SQLITE_UNTESTABLE
/*
** Global variables.
*/
typedef struct BenignMallocHooks BenignMallocHooks;
static SQLITE_WSD struct BenignMallocHooks {
void (*xBenignBegin)(void);
void (*xBenignEnd)(void);
} sqlite3Hooks = { 0, 0 };
/* The "wsdHooks" macro will resolve to the appropriate BenignMallocHooks
** structure. If writable static data is unsupported on the target,
** we have to locate the state vector at run-time. In the more common
** case where writable static data is supported, wsdHooks can refer directly
** to the "sqlite3Hooks" state vector declared above.
*/
#ifdef SQLITE_OMIT_WSD
# define wsdHooksInit \
BenignMallocHooks *x = &GLOBAL(BenignMallocHooks,sqlite3Hooks)
# define wsdHooks x[0]
#else
# define wsdHooksInit
# define wsdHooks sqlite3Hooks
#endif
/*
** Register hooks to call when sqlite3BeginBenignMalloc() and
** sqlite3EndBenignMalloc() are called, respectively.
*/
void sqlite3BenignMallocHooks(
void (*xBenignBegin)(void),
void (*xBenignEnd)(void)
){
wsdHooksInit;
wsdHooks.xBenignBegin = xBenignBegin;
wsdHooks.xBenignEnd = xBenignEnd;
}
/*
** This (sqlite3EndBenignMalloc()) is called by SQLite code to indicate that
** subsequent malloc failures are benign. A call to sqlite3EndBenignMalloc()
** indicates that subsequent malloc failures are non-benign.
*/
void sqlite3BeginBenignMalloc(void){
wsdHooksInit;
if( wsdHooks.xBenignBegin ){
wsdHooks.xBenignBegin();
}
}
void sqlite3EndBenignMalloc(void){
wsdHooksInit;
if( wsdHooks.xBenignEnd ){
wsdHooks.xBenignEnd();
}
}
#endif /* #ifndef SQLITE_UNTESTABLE */
| null | null | null | null | 26,530 |
27,394 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 27,394 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "base/metrics/field_trial.h"
// Define webrtc::field_trial::FindFullName to provide webrtc with a field trial
// implementation.
namespace webrtc {
namespace field_trial {
std::string FindFullName(const std::string& trial_name) {
return base::FieldTrialList::FindFullName(trial_name);
}
} // namespace field_trial
} // namespace webrtc
| null | null | null | null | 24,257 |
29,269 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 194,264 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Intel MIC Platform Software Stack (MPSS)
*
* Copyright(c) 2013 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, version 2, as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* Intel MIC Host driver.
*
*/
#include <linux/pci.h>
#include <linux/interrupt.h>
#include "../common/mic_dev.h"
#include "mic_device.h"
static irqreturn_t mic_thread_fn(int irq, void *dev)
{
struct mic_device *mdev = dev;
struct mic_intr_info *intr_info = mdev->intr_info;
struct mic_irq_info *irq_info = &mdev->irq_info;
struct mic_intr_cb *intr_cb;
struct pci_dev *pdev = mdev->pdev;
int i;
spin_lock(&irq_info->mic_thread_lock);
for (i = intr_info->intr_start_idx[MIC_INTR_DB];
i < intr_info->intr_len[MIC_INTR_DB]; i++)
if (test_and_clear_bit(i, &irq_info->mask)) {
list_for_each_entry(intr_cb, &irq_info->cb_list[i],
list)
if (intr_cb->thread_fn)
intr_cb->thread_fn(pdev->irq,
intr_cb->data);
}
spin_unlock(&irq_info->mic_thread_lock);
return IRQ_HANDLED;
}
/**
* mic_interrupt - Generic interrupt handler for
* MSI and INTx based interrupts.
*/
static irqreturn_t mic_interrupt(int irq, void *dev)
{
struct mic_device *mdev = dev;
struct mic_intr_info *intr_info = mdev->intr_info;
struct mic_irq_info *irq_info = &mdev->irq_info;
struct mic_intr_cb *intr_cb;
struct pci_dev *pdev = mdev->pdev;
u32 mask;
int i;
mask = mdev->ops->ack_interrupt(mdev);
if (!mask)
return IRQ_NONE;
spin_lock(&irq_info->mic_intr_lock);
for (i = intr_info->intr_start_idx[MIC_INTR_DB];
i < intr_info->intr_len[MIC_INTR_DB]; i++)
if (mask & BIT(i)) {
list_for_each_entry(intr_cb, &irq_info->cb_list[i],
list)
if (intr_cb->handler)
intr_cb->handler(pdev->irq,
intr_cb->data);
set_bit(i, &irq_info->mask);
}
spin_unlock(&irq_info->mic_intr_lock);
return IRQ_WAKE_THREAD;
}
/* Return the interrupt offset from the index. Index is 0 based. */
static u16 mic_map_src_to_offset(struct mic_device *mdev,
int intr_src, enum mic_intr_type type)
{
if (type >= MIC_NUM_INTR_TYPES)
return MIC_NUM_OFFSETS;
if (intr_src >= mdev->intr_info->intr_len[type])
return MIC_NUM_OFFSETS;
return mdev->intr_info->intr_start_idx[type] + intr_src;
}
/* Return next available msix_entry. */
static struct msix_entry *mic_get_available_vector(struct mic_device *mdev)
{
int i;
struct mic_irq_info *info = &mdev->irq_info;
for (i = 0; i < info->num_vectors; i++)
if (!info->mic_msi_map[i])
return &info->msix_entries[i];
return NULL;
}
/**
* mic_register_intr_callback - Register a callback handler for the
* given source id.
*
* @mdev: pointer to the mic_device instance
* @idx: The source id to be registered.
* @handler: The function to be called when the source id receives
* the interrupt.
* @thread_fn: thread fn. corresponding to the handler
* @data: Private data of the requester.
* Return the callback structure that was registered or an
* appropriate error on failure.
*/
static struct mic_intr_cb *mic_register_intr_callback(struct mic_device *mdev,
u8 idx, irq_handler_t handler, irq_handler_t thread_fn,
void *data)
{
struct mic_intr_cb *intr_cb;
unsigned long flags;
int rc;
intr_cb = kmalloc(sizeof(*intr_cb), GFP_KERNEL);
if (!intr_cb)
return ERR_PTR(-ENOMEM);
intr_cb->handler = handler;
intr_cb->thread_fn = thread_fn;
intr_cb->data = data;
intr_cb->cb_id = ida_simple_get(&mdev->irq_info.cb_ida,
0, 0, GFP_KERNEL);
if (intr_cb->cb_id < 0) {
rc = intr_cb->cb_id;
goto ida_fail;
}
spin_lock(&mdev->irq_info.mic_thread_lock);
spin_lock_irqsave(&mdev->irq_info.mic_intr_lock, flags);
list_add_tail(&intr_cb->list, &mdev->irq_info.cb_list[idx]);
spin_unlock_irqrestore(&mdev->irq_info.mic_intr_lock, flags);
spin_unlock(&mdev->irq_info.mic_thread_lock);
return intr_cb;
ida_fail:
kfree(intr_cb);
return ERR_PTR(rc);
}
/**
* mic_unregister_intr_callback - Unregister the callback handler
* identified by its callback id.
*
* @mdev: pointer to the mic_device instance
* @idx: The callback structure id to be unregistered.
* Return the source id that was unregistered or MIC_NUM_OFFSETS if no
* such callback handler was found.
*/
static u8 mic_unregister_intr_callback(struct mic_device *mdev, u32 idx)
{
struct list_head *pos, *tmp;
struct mic_intr_cb *intr_cb;
unsigned long flags;
int i;
spin_lock(&mdev->irq_info.mic_thread_lock);
spin_lock_irqsave(&mdev->irq_info.mic_intr_lock, flags);
for (i = 0; i < MIC_NUM_OFFSETS; i++) {
list_for_each_safe(pos, tmp, &mdev->irq_info.cb_list[i]) {
intr_cb = list_entry(pos, struct mic_intr_cb, list);
if (intr_cb->cb_id == idx) {
list_del(pos);
ida_simple_remove(&mdev->irq_info.cb_ida,
intr_cb->cb_id);
kfree(intr_cb);
spin_unlock_irqrestore(
&mdev->irq_info.mic_intr_lock, flags);
spin_unlock(&mdev->irq_info.mic_thread_lock);
return i;
}
}
}
spin_unlock_irqrestore(&mdev->irq_info.mic_intr_lock, flags);
spin_unlock(&mdev->irq_info.mic_thread_lock);
return MIC_NUM_OFFSETS;
}
/**
* mic_setup_msix - Initializes MSIx interrupts.
*
* @mdev: pointer to mic_device instance
*
*
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
*/
static int mic_setup_msix(struct mic_device *mdev, struct pci_dev *pdev)
{
int rc, i;
int entry_size = sizeof(*mdev->irq_info.msix_entries);
mdev->irq_info.msix_entries = kmalloc_array(MIC_MIN_MSIX,
entry_size, GFP_KERNEL);
if (!mdev->irq_info.msix_entries) {
rc = -ENOMEM;
goto err_nomem1;
}
for (i = 0; i < MIC_MIN_MSIX; i++)
mdev->irq_info.msix_entries[i].entry = i;
rc = pci_enable_msix_exact(pdev, mdev->irq_info.msix_entries,
MIC_MIN_MSIX);
if (rc) {
dev_dbg(&pdev->dev, "Error enabling MSIx. rc = %d\n", rc);
goto err_enable_msix;
}
mdev->irq_info.num_vectors = MIC_MIN_MSIX;
mdev->irq_info.mic_msi_map = kzalloc((sizeof(u32) *
mdev->irq_info.num_vectors), GFP_KERNEL);
if (!mdev->irq_info.mic_msi_map) {
rc = -ENOMEM;
goto err_nomem2;
}
dev_dbg(&mdev->pdev->dev,
"%d MSIx irqs setup\n", mdev->irq_info.num_vectors);
return 0;
err_nomem2:
pci_disable_msix(pdev);
err_enable_msix:
kfree(mdev->irq_info.msix_entries);
err_nomem1:
mdev->irq_info.num_vectors = 0;
return rc;
}
/**
* mic_setup_callbacks - Initialize data structures needed
* to handle callbacks.
*
* @mdev: pointer to mic_device instance
*/
static int mic_setup_callbacks(struct mic_device *mdev)
{
int i;
mdev->irq_info.cb_list = kmalloc_array(MIC_NUM_OFFSETS,
sizeof(*mdev->irq_info.cb_list),
GFP_KERNEL);
if (!mdev->irq_info.cb_list)
return -ENOMEM;
for (i = 0; i < MIC_NUM_OFFSETS; i++)
INIT_LIST_HEAD(&mdev->irq_info.cb_list[i]);
ida_init(&mdev->irq_info.cb_ida);
spin_lock_init(&mdev->irq_info.mic_intr_lock);
spin_lock_init(&mdev->irq_info.mic_thread_lock);
return 0;
}
/**
* mic_release_callbacks - Uninitialize data structures needed
* to handle callbacks.
*
* @mdev: pointer to mic_device instance
*/
static void mic_release_callbacks(struct mic_device *mdev)
{
unsigned long flags;
struct list_head *pos, *tmp;
struct mic_intr_cb *intr_cb;
int i;
spin_lock(&mdev->irq_info.mic_thread_lock);
spin_lock_irqsave(&mdev->irq_info.mic_intr_lock, flags);
for (i = 0; i < MIC_NUM_OFFSETS; i++) {
if (list_empty(&mdev->irq_info.cb_list[i]))
break;
list_for_each_safe(pos, tmp, &mdev->irq_info.cb_list[i]) {
intr_cb = list_entry(pos, struct mic_intr_cb, list);
list_del(pos);
ida_simple_remove(&mdev->irq_info.cb_ida,
intr_cb->cb_id);
kfree(intr_cb);
}
}
spin_unlock_irqrestore(&mdev->irq_info.mic_intr_lock, flags);
spin_unlock(&mdev->irq_info.mic_thread_lock);
ida_destroy(&mdev->irq_info.cb_ida);
kfree(mdev->irq_info.cb_list);
}
/**
* mic_setup_msi - Initializes MSI interrupts.
*
* @mdev: pointer to mic_device instance
* @pdev: PCI device structure
*
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
*/
static int mic_setup_msi(struct mic_device *mdev, struct pci_dev *pdev)
{
int rc;
rc = pci_enable_msi(pdev);
if (rc) {
dev_dbg(&pdev->dev, "Error enabling MSI. rc = %d\n", rc);
return rc;
}
mdev->irq_info.num_vectors = 1;
mdev->irq_info.mic_msi_map = kzalloc((sizeof(u32) *
mdev->irq_info.num_vectors), GFP_KERNEL);
if (!mdev->irq_info.mic_msi_map) {
rc = -ENOMEM;
goto err_nomem1;
}
rc = mic_setup_callbacks(mdev);
if (rc) {
dev_err(&pdev->dev, "Error setting up callbacks\n");
goto err_nomem2;
}
rc = request_threaded_irq(pdev->irq, mic_interrupt, mic_thread_fn,
0, "mic-msi", mdev);
if (rc) {
dev_err(&pdev->dev, "Error allocating MSI interrupt\n");
goto err_irq_req_fail;
}
dev_dbg(&pdev->dev, "%d MSI irqs setup\n", mdev->irq_info.num_vectors);
return 0;
err_irq_req_fail:
mic_release_callbacks(mdev);
err_nomem2:
kfree(mdev->irq_info.mic_msi_map);
err_nomem1:
pci_disable_msi(pdev);
mdev->irq_info.num_vectors = 0;
return rc;
}
/**
* mic_setup_intx - Initializes legacy interrupts.
*
* @mdev: pointer to mic_device instance
* @pdev: PCI device structure
*
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
*/
static int mic_setup_intx(struct mic_device *mdev, struct pci_dev *pdev)
{
int rc;
/* Enable intx */
pci_intx(pdev, 1);
rc = mic_setup_callbacks(mdev);
if (rc) {
dev_err(&pdev->dev, "Error setting up callbacks\n");
goto err_nomem;
}
rc = request_threaded_irq(pdev->irq, mic_interrupt, mic_thread_fn,
IRQF_SHARED, "mic-intx", mdev);
if (rc)
goto err;
dev_dbg(&pdev->dev, "intx irq setup\n");
return 0;
err:
mic_release_callbacks(mdev);
err_nomem:
return rc;
}
/**
* mic_next_db - Retrieve the next doorbell interrupt source id.
* The id is picked sequentially from the available pool of
* doorlbell ids.
*
* @mdev: pointer to the mic_device instance.
*
* Returns the next doorbell interrupt source.
*/
int mic_next_db(struct mic_device *mdev)
{
int next_db;
next_db = mdev->irq_info.next_avail_src %
mdev->intr_info->intr_len[MIC_INTR_DB];
mdev->irq_info.next_avail_src++;
return next_db;
}
#define COOKIE_ID_SHIFT 16
#define GET_ENTRY(cookie) ((cookie) & 0xFFFF)
#define GET_OFFSET(cookie) ((cookie) >> COOKIE_ID_SHIFT)
#define MK_COOKIE(x, y) ((x) | (y) << COOKIE_ID_SHIFT)
/**
* mic_request_threaded_irq - request an irq. mic_mutex needs
* to be held before calling this function.
*
* @mdev: pointer to mic_device instance
* @handler: The callback function that handles the interrupt.
* The function needs to call ack_interrupts
* (mdev->ops->ack_interrupt(mdev)) when handling the interrupts.
* @thread_fn: thread fn required by request_threaded_irq.
* @name: The ASCII name of the callee requesting the irq.
* @data: private data that is returned back when calling the
* function handler.
* @intr_src: The source id of the requester. Its the doorbell id
* for Doorbell interrupts and DMA channel id for DMA interrupts.
* @type: The type of interrupt. Values defined in mic_intr_type
*
* returns: The cookie that is transparent to the caller. Passed
* back when calling mic_free_irq. An appropriate error code
* is returned on failure. Caller needs to use IS_ERR(return_val)
* to check for failure and PTR_ERR(return_val) to obtained the
* error code.
*
*/
struct mic_irq *
mic_request_threaded_irq(struct mic_device *mdev,
irq_handler_t handler, irq_handler_t thread_fn,
const char *name, void *data, int intr_src,
enum mic_intr_type type)
{
u16 offset;
int rc = 0;
struct msix_entry *msix = NULL;
unsigned long cookie = 0;
u16 entry;
struct mic_intr_cb *intr_cb;
struct pci_dev *pdev = mdev->pdev;
offset = mic_map_src_to_offset(mdev, intr_src, type);
if (offset >= MIC_NUM_OFFSETS) {
dev_err(&mdev->pdev->dev,
"Error mapping index %d to a valid source id.\n",
intr_src);
rc = -EINVAL;
goto err;
}
if (mdev->irq_info.num_vectors > 1) {
msix = mic_get_available_vector(mdev);
if (!msix) {
dev_err(&mdev->pdev->dev,
"No MSIx vectors available for use.\n");
rc = -ENOSPC;
goto err;
}
rc = request_threaded_irq(msix->vector, handler, thread_fn,
0, name, data);
if (rc) {
dev_dbg(&mdev->pdev->dev,
"request irq failed rc = %d\n", rc);
goto err;
}
entry = msix->entry;
mdev->irq_info.mic_msi_map[entry] |= BIT(offset);
mdev->intr_ops->program_msi_to_src_map(mdev,
entry, offset, true);
cookie = MK_COOKIE(entry, offset);
dev_dbg(&mdev->pdev->dev, "irq: %d assigned for src: %d\n",
msix->vector, intr_src);
} else {
intr_cb = mic_register_intr_callback(mdev, offset, handler,
thread_fn, data);
if (IS_ERR(intr_cb)) {
dev_err(&mdev->pdev->dev,
"No available callback entries for use\n");
rc = PTR_ERR(intr_cb);
goto err;
}
entry = 0;
if (pci_dev_msi_enabled(pdev)) {
mdev->irq_info.mic_msi_map[entry] |= (1 << offset);
mdev->intr_ops->program_msi_to_src_map(mdev,
entry, offset, true);
}
cookie = MK_COOKIE(entry, intr_cb->cb_id);
dev_dbg(&mdev->pdev->dev, "callback %d registered for src: %d\n",
intr_cb->cb_id, intr_src);
}
return (struct mic_irq *)cookie;
err:
return ERR_PTR(rc);
}
/**
* mic_free_irq - free irq. mic_mutex
* needs to be held before calling this function.
*
* @mdev: pointer to mic_device instance
* @cookie: cookie obtained during a successful call to mic_request_threaded_irq
* @data: private data specified by the calling function during the
* mic_request_threaded_irq
*
* returns: none.
*/
void mic_free_irq(struct mic_device *mdev,
struct mic_irq *cookie, void *data)
{
u32 offset;
u32 entry;
u8 src_id;
unsigned int irq;
struct pci_dev *pdev = mdev->pdev;
entry = GET_ENTRY((unsigned long)cookie);
offset = GET_OFFSET((unsigned long)cookie);
if (mdev->irq_info.num_vectors > 1) {
if (entry >= mdev->irq_info.num_vectors) {
dev_warn(&mdev->pdev->dev,
"entry %d should be < num_irq %d\n",
entry, mdev->irq_info.num_vectors);
return;
}
irq = mdev->irq_info.msix_entries[entry].vector;
free_irq(irq, data);
mdev->irq_info.mic_msi_map[entry] &= ~(BIT(offset));
mdev->intr_ops->program_msi_to_src_map(mdev,
entry, offset, false);
dev_dbg(&mdev->pdev->dev, "irq: %d freed\n", irq);
} else {
irq = pdev->irq;
src_id = mic_unregister_intr_callback(mdev, offset);
if (src_id >= MIC_NUM_OFFSETS) {
dev_warn(&mdev->pdev->dev, "Error unregistering callback\n");
return;
}
if (pci_dev_msi_enabled(pdev)) {
mdev->irq_info.mic_msi_map[entry] &= ~(BIT(src_id));
mdev->intr_ops->program_msi_to_src_map(mdev,
entry, src_id, false);
}
dev_dbg(&mdev->pdev->dev, "callback %d unregistered for src: %d\n",
offset, src_id);
}
}
/**
* mic_setup_interrupts - Initializes interrupts.
*
* @mdev: pointer to mic_device instance
* @pdev: PCI device structure
*
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
*/
int mic_setup_interrupts(struct mic_device *mdev, struct pci_dev *pdev)
{
int rc;
rc = mic_setup_msix(mdev, pdev);
if (!rc)
goto done;
rc = mic_setup_msi(mdev, pdev);
if (!rc)
goto done;
rc = mic_setup_intx(mdev, pdev);
if (rc) {
dev_err(&mdev->pdev->dev, "no usable interrupts\n");
return rc;
}
done:
mdev->intr_ops->enable_interrupts(mdev);
return 0;
}
/**
* mic_free_interrupts - Frees interrupts setup by mic_setup_interrupts
*
* @mdev: pointer to mic_device instance
* @pdev: PCI device structure
*
* returns none.
*/
void mic_free_interrupts(struct mic_device *mdev, struct pci_dev *pdev)
{
int i;
mdev->intr_ops->disable_interrupts(mdev);
if (mdev->irq_info.num_vectors > 1) {
for (i = 0; i < mdev->irq_info.num_vectors; i++) {
if (mdev->irq_info.mic_msi_map[i])
dev_warn(&pdev->dev, "irq %d may still be in use.\n",
mdev->irq_info.msix_entries[i].vector);
}
kfree(mdev->irq_info.mic_msi_map);
kfree(mdev->irq_info.msix_entries);
pci_disable_msix(pdev);
} else {
if (pci_dev_msi_enabled(pdev)) {
free_irq(pdev->irq, mdev);
kfree(mdev->irq_info.mic_msi_map);
pci_disable_msi(pdev);
} else {
free_irq(pdev->irq, mdev);
}
mic_release_callbacks(mdev);
}
}
/**
* mic_intr_restore - Restore MIC interrupt registers.
*
* @mdev: pointer to mic_device instance.
*
* Restore the interrupt registers to values previously
* stored in the SW data structures. mic_mutex needs to
* be held before calling this function.
*
* returns None.
*/
void mic_intr_restore(struct mic_device *mdev)
{
int entry, offset;
struct pci_dev *pdev = mdev->pdev;
if (!pci_dev_msi_enabled(pdev))
return;
for (entry = 0; entry < mdev->irq_info.num_vectors; entry++) {
for (offset = 0; offset < MIC_NUM_OFFSETS; offset++) {
if (mdev->irq_info.mic_msi_map[entry] & BIT(offset))
mdev->intr_ops->program_msi_to_src_map(mdev,
entry, offset, true);
}
}
}
| null | null | null | null | 102,611 |
42,788 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 207,783 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* linux/include/video/mmp_disp.h
* Header file for Marvell MMP Display Controller
*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Authors: Zhou Zhu <zzhu3@marvell.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef _MMP_DISP_H_
#define _MMP_DISP_H_
#include <linux/kthread.h>
enum {
PIXFMT_UYVY = 0,
PIXFMT_VYUY,
PIXFMT_YUYV,
PIXFMT_YUV422P,
PIXFMT_YVU422P,
PIXFMT_YUV420P,
PIXFMT_YVU420P,
PIXFMT_RGB565 = 0x100,
PIXFMT_BGR565,
PIXFMT_RGB1555,
PIXFMT_BGR1555,
PIXFMT_RGB888PACK,
PIXFMT_BGR888PACK,
PIXFMT_RGB888UNPACK,
PIXFMT_BGR888UNPACK,
PIXFMT_RGBA888,
PIXFMT_BGRA888,
PIXFMT_RGB666, /* for output usage */
PIXFMT_PSEUDOCOLOR = 0x200,
};
static inline int pixfmt_to_stride(int pix_fmt)
{
switch (pix_fmt) {
case PIXFMT_RGB565:
case PIXFMT_BGR565:
case PIXFMT_RGB1555:
case PIXFMT_BGR1555:
case PIXFMT_UYVY:
case PIXFMT_VYUY:
case PIXFMT_YUYV:
return 2;
case PIXFMT_RGB888UNPACK:
case PIXFMT_BGR888UNPACK:
case PIXFMT_RGBA888:
case PIXFMT_BGRA888:
return 4;
case PIXFMT_RGB888PACK:
case PIXFMT_BGR888PACK:
return 3;
case PIXFMT_YUV422P:
case PIXFMT_YVU422P:
case PIXFMT_YUV420P:
case PIXFMT_YVU420P:
case PIXFMT_PSEUDOCOLOR:
return 1;
default:
return 0;
}
}
/* parameters used by path/overlay */
/* overlay related para: win/addr */
struct mmp_win {
/* position/size of window */
u16 xsrc;
u16 ysrc;
u16 xdst;
u16 ydst;
u16 xpos;
u16 ypos;
u16 left_crop;
u16 right_crop;
u16 up_crop;
u16 bottom_crop;
int pix_fmt;
/*
* pitch[0]: graphics/video layer line length or y pitch
* pitch[1]/pitch[2]: video u/v pitch if non-zero
*/
u32 pitch[3];
};
struct mmp_addr {
/* phys address */
u32 phys[6];
};
/* path related para: mode */
struct mmp_mode {
const char *name;
u32 refresh;
u32 xres;
u32 yres;
u32 left_margin;
u32 right_margin;
u32 upper_margin;
u32 lower_margin;
u32 hsync_len;
u32 vsync_len;
u32 hsync_invert;
u32 vsync_invert;
u32 invert_pixclock;
u32 pixclock_freq;
int pix_fmt_out;
};
/* main structures */
struct mmp_path;
struct mmp_overlay;
struct mmp_panel;
/* status types */
enum {
MMP_OFF = 0,
MMP_ON,
};
static inline const char *stat_name(int stat)
{
switch (stat) {
case MMP_OFF:
return "OFF";
case MMP_ON:
return "ON";
default:
return "UNKNOWNSTAT";
}
}
struct mmp_overlay_ops {
/* should be provided by driver */
void (*set_fetch)(struct mmp_overlay *overlay, int fetch_id);
void (*set_onoff)(struct mmp_overlay *overlay, int status);
void (*set_win)(struct mmp_overlay *overlay, struct mmp_win *win);
int (*set_addr)(struct mmp_overlay *overlay, struct mmp_addr *addr);
};
/* overlay describes a z-order indexed slot in each path. */
struct mmp_overlay {
int id;
const char *name;
struct mmp_path *path;
/* overlay info: private data */
int dmafetch_id;
struct mmp_addr addr;
struct mmp_win win;
/* state */
int open_count;
int status;
struct mutex access_ok;
struct mmp_overlay_ops *ops;
};
/* panel type */
enum {
PANELTYPE_ACTIVE = 0,
PANELTYPE_SMART,
PANELTYPE_TV,
PANELTYPE_DSI_CMD,
PANELTYPE_DSI_VIDEO,
};
struct mmp_panel {
/* use node to register to list */
struct list_head node;
const char *name;
/* path name used to connect to proper path configed */
const char *plat_path_name;
struct device *dev;
int panel_type;
void *plat_data;
int (*get_modelist)(struct mmp_panel *panel,
struct mmp_mode **modelist);
void (*set_mode)(struct mmp_panel *panel,
struct mmp_mode *mode);
void (*set_onoff)(struct mmp_panel *panel,
int status);
};
struct mmp_path_ops {
int (*check_status)(struct mmp_path *path);
struct mmp_overlay *(*get_overlay)(struct mmp_path *path,
int overlay_id);
int (*get_modelist)(struct mmp_path *path,
struct mmp_mode **modelist);
/* follow ops should be provided by driver */
void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode);
void (*set_onoff)(struct mmp_path *path, int status);
/* todo: add query */
};
/* path output types */
enum {
PATH_OUT_PARALLEL,
PATH_OUT_DSI,
PATH_OUT_HDMI,
};
/* path is main part of mmp-disp */
struct mmp_path {
/* use node to register to list */
struct list_head node;
/* init data */
struct device *dev;
int id;
const char *name;
int output_type;
struct mmp_panel *panel;
void *plat_data;
/* dynamic use */
struct mmp_mode mode;
/* state */
int open_count;
int status;
struct mutex access_ok;
struct mmp_path_ops ops;
/* layers */
int overlay_num;
struct mmp_overlay overlays[0];
};
extern struct mmp_path *mmp_get_path(const char *name);
static inline void mmp_path_set_mode(struct mmp_path *path,
struct mmp_mode *mode)
{
if (path)
path->ops.set_mode(path, mode);
}
static inline void mmp_path_set_onoff(struct mmp_path *path, int status)
{
if (path)
path->ops.set_onoff(path, status);
}
static inline int mmp_path_get_modelist(struct mmp_path *path,
struct mmp_mode **modelist)
{
if (path)
return path->ops.get_modelist(path, modelist);
return 0;
}
static inline struct mmp_overlay *mmp_path_get_overlay(
struct mmp_path *path, int overlay_id)
{
if (path)
return path->ops.get_overlay(path, overlay_id);
return NULL;
}
static inline void mmp_overlay_set_fetch(struct mmp_overlay *overlay,
int fetch_id)
{
if (overlay)
overlay->ops->set_fetch(overlay, fetch_id);
}
static inline void mmp_overlay_set_onoff(struct mmp_overlay *overlay,
int status)
{
if (overlay)
overlay->ops->set_onoff(overlay, status);
}
static inline void mmp_overlay_set_win(struct mmp_overlay *overlay,
struct mmp_win *win)
{
if (overlay)
overlay->ops->set_win(overlay, win);
}
static inline int mmp_overlay_set_addr(struct mmp_overlay *overlay,
struct mmp_addr *addr)
{
if (overlay)
return overlay->ops->set_addr(overlay, addr);
return 0;
}
/*
* driver data is set from each detailed ctrl driver for path usage
* it defined a common interface that plat driver need to implement
*/
struct mmp_path_info {
/* driver data, set when registed*/
const char *name;
struct device *dev;
int id;
int output_type;
int overlay_num;
void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode);
void (*set_onoff)(struct mmp_path *path, int status);
struct mmp_overlay_ops *overlay_ops;
void *plat_data;
};
extern struct mmp_path *mmp_register_path(
struct mmp_path_info *info);
extern void mmp_unregister_path(struct mmp_path *path);
extern void mmp_register_panel(struct mmp_panel *panel);
extern void mmp_unregister_panel(struct mmp_panel *panel);
/* defintions for platform data */
/* interface for buffer driver */
struct mmp_buffer_driver_mach_info {
const char *name;
const char *path_name;
int overlay_id;
int dmafetch_id;
int default_pixfmt;
};
/* interface for controllers driver */
struct mmp_mach_path_config {
const char *name;
int overlay_num;
int output_type;
u32 path_config;
u32 link_config;
u32 dsi_rbswap;
};
struct mmp_mach_plat_info {
const char *name;
const char *clk_name;
int path_num;
struct mmp_mach_path_config *paths;
};
/* interface for panel drivers */
struct mmp_mach_panel_info {
const char *name;
void (*plat_set_onoff)(int status);
const char *plat_path_name;
};
#endif /* _MMP_DISP_H_ */
| null | null | null | null | 116,130 |
10,102 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 10,102 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2018 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef CHROMECAST_DEVICE_BLUETOOTH_LE_REMOTE_SERVICE_IMPL_H_
#define CHROMECAST_DEVICE_BLUETOOTH_LE_REMOTE_SERVICE_IMPL_H_
#include <map>
#include <memory>
#include <vector>
#include "base/memory/weak_ptr.h"
#include "base/single_thread_task_runner.h"
#include "chromecast/device/bluetooth/le/remote_service.h"
namespace chromecast {
namespace bluetooth {
class GattClientManagerImpl;
class RemoteServiceImpl : public RemoteService {
public:
// RemoteService implementation:
std::vector<scoped_refptr<RemoteCharacteristic>> GetCharacteristics()
override;
scoped_refptr<RemoteCharacteristic> GetCharacteristicByUuid(
const bluetooth_v2_shlib::Uuid& uuid) override;
const bluetooth_v2_shlib::Uuid& uuid() const override;
uint16_t handle() const override;
bool primary() const override;
private:
friend class RemoteDeviceImpl;
static std::map<bluetooth_v2_shlib::Uuid, scoped_refptr<RemoteCharacteristic>>
CreateCharMap(RemoteDevice* remote_device,
base::WeakPtr<GattClientManagerImpl> gatt_client_manager,
const bluetooth_v2_shlib::Gatt::Service& service,
scoped_refptr<base::SingleThreadTaskRunner> io_task_runner);
// May only be constructed by RemoteDevice.
explicit RemoteServiceImpl(
RemoteDevice* remote_device,
base::WeakPtr<GattClientManagerImpl> gatt_client_manager,
const bluetooth_v2_shlib::Gatt::Service& service,
scoped_refptr<base::SingleThreadTaskRunner> io_task_runner);
~RemoteServiceImpl() override;
const bluetooth_v2_shlib::Gatt::Service service_;
const std::map<bluetooth_v2_shlib::Uuid, scoped_refptr<RemoteCharacteristic>>
uuid_to_characteristic_;
DISALLOW_COPY_AND_ASSIGN(RemoteServiceImpl);
};
} // namespace bluetooth
} // namespace chromecast
#endif // CHROMECAST_DEVICE_BLUETOOTH_LE_REMOTE_SERVICE_IMPL_H_
| null | null | null | null | 6,965 |
69,326 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 69,326 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | /* Copyright (c) 2013 The Chromium Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file. */
#include "nacl_io/kernel_intercept.h"
#include "nacl_io/kernel_wrap.h"
#if !defined(__native_client__) || defined(__GLIBC__)
// GLIBC-only entry point.
// TODO(sbc): remove once this bug gets fixed:
// https://code.google.com/p/nativeclient/issues/detail?id=3709
int truncate(const char* pathname, off_t length) {
return ki_truncate(pathname, length);
}
#endif
| null | null | null | null | 66,189 |
50,398 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 50,398 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2012 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef UI_BASE_IME_CHROMEOS_MOCK_INPUT_METHOD_MANAGER_H_
#define UI_BASE_IME_CHROMEOS_MOCK_INPUT_METHOD_MANAGER_H_
#include "base/macros.h"
#include "ui/base/ime/chromeos/input_method_manager.h"
namespace chromeos {
namespace input_method {
class InputMethodUtil;
class ImeKeyboard;
// The mock InputMethodManager for testing.
class UI_BASE_IME_EXPORT MockInputMethodManager : public InputMethodManager {
public:
public:
class State : public InputMethodManager::State {
public:
State();
scoped_refptr<InputMethodManager::State> Clone() const override;
void AddInputMethodExtension(
const std::string& extension_id,
const InputMethodDescriptors& descriptors,
ui::IMEEngineHandlerInterface* instance) override;
void RemoveInputMethodExtension(const std::string& extension_id) override;
void ChangeInputMethod(const std::string& input_method_id,
bool show_message) override;
void ChangeInputMethodToJpKeyboard() override;
void ChangeInputMethodToJpIme() override;
void ToggleInputMethodForJpIme() override;
bool EnableInputMethod(
const std::string& new_active_input_method_id) override;
void EnableLoginLayouts(
const std::string& language_code,
const std::vector<std::string>& initial_layouts) override;
void EnableLockScreenLayouts() override;
void GetInputMethodExtensions(InputMethodDescriptors* result) override;
std::unique_ptr<InputMethodDescriptors> GetActiveInputMethods()
const override;
const std::vector<std::string>& GetActiveInputMethodIds() const override;
const InputMethodDescriptor* GetInputMethodFromId(
const std::string& input_method_id) const override;
size_t GetNumActiveInputMethods() const override;
void SetEnabledExtensionImes(std::vector<std::string>* ids) override;
void SetInputMethodLoginDefault() override;
void SetInputMethodLoginDefaultFromVPD(const std::string& locale,
const std::string& layout) override;
void SwitchToNextInputMethod() override;
void SwitchToPreviousInputMethod() override;
InputMethodDescriptor GetCurrentInputMethod() const override;
bool ReplaceEnabledInputMethods(
const std::vector<std::string>& new_active_input_method_ids) override;
bool SetAllowedInputMethods(
const std::vector<std::string>& new_allowed_input_method_ids) override;
const std::vector<std::string>& GetAllowedInputMethods() override;
void EnableInputView() override;
void DisableInputView() override;
const GURL& GetInputViewUrl() const override;
// The active input method ids cache (actually default only)
std::vector<std::string> active_input_method_ids;
protected:
friend base::RefCounted<InputMethodManager::State>;
~State() override;
private:
// Allowed input methods ids
std::vector<std::string> allowed_input_method_ids_;
DISALLOW_COPY_AND_ASSIGN(State);
};
MockInputMethodManager();
~MockInputMethodManager() override;
// InputMethodManager:
UISessionState GetUISessionState() override;
void AddObserver(InputMethodManager::Observer* observer) override;
void AddCandidateWindowObserver(
InputMethodManager::CandidateWindowObserver* observer) override;
void AddImeMenuObserver(
InputMethodManager::ImeMenuObserver* observer) override;
void RemoveObserver(InputMethodManager::Observer* observer) override;
void RemoveCandidateWindowObserver(
InputMethodManager::CandidateWindowObserver* observer) override;
void RemoveImeMenuObserver(
InputMethodManager::ImeMenuObserver* observer) override;
std::unique_ptr<InputMethodDescriptors> GetSupportedInputMethods()
const override;
void ActivateInputMethodMenuItem(const std::string& key) override;
bool IsISOLevel5ShiftUsedByCurrentInputMethod() const override;
bool IsAltGrUsedByCurrentInputMethod() const override;
ImeKeyboard* GetImeKeyboard() override;
InputMethodUtil* GetInputMethodUtil() override;
ComponentExtensionIMEManager* GetComponentExtensionIMEManager() override;
bool IsLoginKeyboard(const std::string& layout) const override;
bool MigrateInputMethods(std::vector<std::string>* input_method_ids) override;
scoped_refptr<InputMethodManager::State> CreateNewState(
Profile* profile) override;
scoped_refptr<InputMethodManager::State> GetActiveIMEState() override;
void SetState(scoped_refptr<InputMethodManager::State> state) override;
void ImeMenuActivationChanged(bool is_active) override;
void NotifyImeMenuItemsChanged(
const std::string& engine_id,
const std::vector<InputMethodManager::MenuItem>& items) override;
void MaybeNotifyImeMenuActivationChanged() override;
void OverrideKeyboardKeyset(mojom::ImeKeyset keyset) override;
void SetImeMenuFeatureEnabled(ImeMenuFeature feature, bool enabled) override;
bool GetImeMenuFeatureEnabled(ImeMenuFeature feature) const override;
void NotifyObserversImeExtraInputStateChange() override;
private:
uint32_t features_enabled_state_;
DISALLOW_COPY_AND_ASSIGN(MockInputMethodManager);
};
} // namespace input_method
} // namespace chromeos
#endif // UI_BASE_IME_CHROMEOS_MOCK_INPUT_METHOD_MANAGER_H_
| null | null | null | null | 47,261 |
3,122 | null | train_val | 04b570817b2b38e35675b17328239746212f4c3f | 156,179 | FFmpeg | 0 | https://github.com/FFmpeg/FFmpeg | 2018-06-01 01:23:12+05:30 | /*
* RTP definitions
* Copyright (c) 2002 Fabrice Bellard
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef AVFORMAT_RTP_H
#define AVFORMAT_RTP_H
#include "libavformat/avformat.h"
#include "libavcodec/avcodec.h"
#include "libavutil/mathematics.h"
/**
* Return the payload type for a given stream used in the given format context.
* Static payload types are derived from the codec.
* Dynamic payload type are derived from the id field in AVStream.
* The format context private option payload_type overrides both.
*
* @param fmt The context of the format
* @param par The codec parameters
* @param idx The stream index
* @return The payload type (the 'PT' field in the RTP header).
*/
int ff_rtp_get_payload_type(AVFormatContext *fmt, AVCodecParameters *par,
int idx);
/**
* Initialize a codec context based on the payload type.
*
* Fill the codec_type and codec_id fields of a codec context with
* information depending on the payload type; for audio codecs, the
* channels and sample_rate fields are also filled.
*
* @param par The codec parameters
* @param payload_type The payload type (the 'PT' field in the RTP header)
* @return In case of unknown payload type or dynamic payload type, a
* negative value is returned; otherwise, 0 is returned
*/
int ff_rtp_get_codec_info(AVCodecParameters *par, int payload_type);
/**
* Return the encoding name (as defined in
* http://www.iana.org/assignments/rtp-parameters) for a given payload type.
*
* @param payload_type The payload type (the 'PT' field in the RTP header)
* @return In case of unknown payload type or dynamic payload type, a pointer
* to an empty string is returned; otherwise, a pointer to a string containing
* the encoding name is returned
*/
const char *ff_rtp_enc_name(int payload_type);
/**
* Return the codec id for the given encoding name and codec type.
*
* @param buf A pointer to the string containing the encoding name
* @param codec_type The codec type
* @return In case of unknown encoding name, AV_CODEC_ID_NONE is returned;
* otherwise, the codec id is returned
*/
enum AVCodecID ff_rtp_codec_id(const char *buf, enum AVMediaType codec_type);
#define RTP_PT_PRIVATE 96
#define RTP_VERSION 2
#define RTP_MAX_SDES 256 /**< maximum text length for SDES */
/* RTCP packets use 0.5% of the bandwidth */
#define RTCP_TX_RATIO_NUM 5
#define RTCP_TX_RATIO_DEN 1000
/* An arbitrary id value for RTP Xiph streams - only relevant to indicate
* that the configuration has changed within a stream (by changing the
* ident value sent).
*/
#define RTP_XIPH_IDENT 0xfecdba
/* RTCP packet types */
enum RTCPType {
RTCP_FIR = 192,
RTCP_NACK, // 193
RTCP_SMPTETC,// 194
RTCP_IJ, // 195
RTCP_SR = 200,
RTCP_RR, // 201
RTCP_SDES, // 202
RTCP_BYE, // 203
RTCP_APP, // 204
RTCP_RTPFB,// 205
RTCP_PSFB, // 206
RTCP_XR, // 207
RTCP_AVB, // 208
RTCP_RSI, // 209
RTCP_TOKEN,// 210
};
#define RTP_PT_IS_RTCP(x) (((x) >= RTCP_FIR && (x) <= RTCP_IJ) || \
((x) >= RTCP_SR && (x) <= RTCP_TOKEN))
#define NTP_TO_RTP_FORMAT(x) av_rescale((x), INT64_C(1) << 32, 1000000)
#endif /* AVFORMAT_RTP_H */
| null | null | null | null | 72,234 |
60,180 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 60,180 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef CHROME_BROWSER_USB_USB_TAB_HELPER_H_
#define CHROME_BROWSER_USB_USB_TAB_HELPER_H_
#include <map>
#include "base/macros.h"
#include "content/public/browser/web_contents_observer.h"
#include "content/public/browser/web_contents_user_data.h"
#include "mojo/public/cpp/bindings/interface_request.h"
namespace device {
namespace mojom {
class UsbChooserService;
class UsbDeviceManager;
}
namespace usb {
class PermissionProvider;
}
}
struct FrameUsbServices;
typedef std::map<content::RenderFrameHost*, std::unique_ptr<FrameUsbServices>>
FrameUsbServicesMap;
// Per-tab owner of USB services provided to render frames within that tab.
class UsbTabHelper : public content::WebContentsObserver,
public content::WebContentsUserData<UsbTabHelper> {
public:
static UsbTabHelper* GetOrCreateForWebContents(
content::WebContents* web_contents);
~UsbTabHelper() override;
void CreateDeviceManager(
content::RenderFrameHost* render_frame_host,
mojo::InterfaceRequest<device::mojom::UsbDeviceManager> request);
void CreateChooserService(
content::RenderFrameHost* render_frame_host,
mojo::InterfaceRequest<device::mojom::UsbChooserService> request);
void IncrementConnectionCount(content::RenderFrameHost* render_frame_host);
void DecrementConnectionCount(content::RenderFrameHost* render_frame_host);
bool IsDeviceConnected() const;
private:
explicit UsbTabHelper(content::WebContents* web_contents);
friend class content::WebContentsUserData<UsbTabHelper>;
// content::WebContentsObserver overrides:
void RenderFrameDeleted(content::RenderFrameHost* render_frame_host) override;
FrameUsbServices* GetFrameUsbService(
content::RenderFrameHost* render_frame_host);
base::WeakPtr<device::usb::PermissionProvider> GetPermissionProvider(
content::RenderFrameHost* render_frame_host);
void GetChooserService(
content::RenderFrameHost* render_frame_host,
mojo::InterfaceRequest<device::mojom::UsbChooserService> request);
void NotifyTabStateChanged() const;
bool AllowedByFeaturePolicy(
content::RenderFrameHost* render_frame_host) const;
FrameUsbServicesMap frame_usb_services_;
DISALLOW_COPY_AND_ASSIGN(UsbTabHelper);
};
#endif // CHROME_BROWSER_USB_USB_TAB_HELPER_H_
| null | null | null | null | 57,043 |
67,590 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 67,590 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chrome/browser/safe_browsing/incident_reporting/binary_integrity_analyzer_win.h"
#include <stddef.h>
#include <memory>
#include <utility>
#include "base/files/file_path.h"
#include "base/files/file_util.h"
#include "base/logging.h"
#include "base/macros.h"
#include "base/path_service.h"
#include "chrome/browser/safe_browsing/incident_reporting/binary_integrity_incident.h"
#include "chrome/browser/safe_browsing/incident_reporting/incident_receiver.h"
#include "chrome/common/chrome_version.h"
#include "chrome/common/safe_browsing/binary_feature_extractor.h"
#include "components/safe_browsing/proto/csd.pb.h"
namespace safe_browsing {
std::vector<base::FilePath> GetCriticalBinariesPath() {
static const base::FilePath::CharType* const kUnversionedFiles[] = {
FILE_PATH_LITERAL("chrome.exe"),
};
static const base::FilePath::CharType* const kVersionedFiles[] = {
FILE_PATH_LITERAL("chrome.dll"),
FILE_PATH_LITERAL("chrome_child.dll"),
FILE_PATH_LITERAL("chrome_elf.dll"),
};
// Find where chrome.exe is installed.
base::FilePath chrome_exe_dir;
if (!PathService::Get(base::DIR_EXE, &chrome_exe_dir))
NOTREACHED();
std::vector<base::FilePath> critical_binaries;
critical_binaries.reserve(arraysize(kUnversionedFiles) +
arraysize(kVersionedFiles));
for (size_t i = 0; i < arraysize(kUnversionedFiles); ++i) {
critical_binaries.push_back(chrome_exe_dir.Append(kUnversionedFiles[i]));
}
base::FilePath version_dir(
chrome_exe_dir.AppendASCII(CHROME_VERSION_STRING));
for (size_t i = 0; i < arraysize(kVersionedFiles); ++i) {
critical_binaries.push_back(version_dir.Append(kVersionedFiles[i]));
}
return critical_binaries;
}
void VerifyBinaryIntegrity(
std::unique_ptr<IncidentReceiver> incident_receiver) {
scoped_refptr<BinaryFeatureExtractor> binary_feature_extractor(
new BinaryFeatureExtractor());
std::vector<base::FilePath> critical_binaries = GetCriticalBinariesPath();
for (size_t i = 0; i < critical_binaries.size(); ++i) {
base::FilePath binary_path(critical_binaries[i]);
if (!base::PathExists(binary_path))
continue;
std::unique_ptr<ClientDownloadRequest_SignatureInfo> signature_info(
new ClientDownloadRequest_SignatureInfo());
base::TimeTicks time_before = base::TimeTicks::Now();
binary_feature_extractor->CheckSignature(binary_path, signature_info.get());
RecordSignatureVerificationTime(i, base::TimeTicks::Now() - time_before);
// Only create a report if the signature is untrusted.
if (!signature_info->trusted()) {
std::unique_ptr<ClientIncidentReport_IncidentData_BinaryIntegrityIncident>
incident(
new ClientIncidentReport_IncidentData_BinaryIntegrityIncident());
incident->set_file_basename(binary_path.BaseName().AsUTF8Unsafe());
incident->set_allocated_signature(signature_info.release());
// Send the report.
incident_receiver->AddIncidentForProcess(
std::make_unique<BinaryIntegrityIncident>(std::move(incident)));
} else {
// The binary is integral, remove previous report so that next incidents
// for the binary will be reported.
ClearBinaryIntegrityForFile(incident_receiver.get(),
binary_path.BaseName().AsUTF8Unsafe());
}
}
}
} // namespace safe_browsing
| null | null | null | null | 64,453 |
2,350 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 167,345 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* net/tipc/bcast.h: Include file for TIPC broadcast code
*
* Copyright (c) 2003-2006, 2014-2015, Ericsson AB
* Copyright (c) 2005, 2010-2011, Wind River Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the names of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _TIPC_BCAST_H
#define _TIPC_BCAST_H
#include "core.h"
struct tipc_node;
struct tipc_msg;
struct tipc_nl_msg;
struct tipc_nlist;
struct tipc_nitem;
extern const char tipc_bclink_name[];
#define TIPC_METHOD_EXPIRE msecs_to_jiffies(5000)
struct tipc_nlist {
struct list_head list;
u32 self;
u16 remote;
bool local;
};
void tipc_nlist_init(struct tipc_nlist *nl, u32 self);
void tipc_nlist_purge(struct tipc_nlist *nl);
void tipc_nlist_add(struct tipc_nlist *nl, u32 node);
void tipc_nlist_del(struct tipc_nlist *nl, u32 node);
/* Cookie to be used between socket and broadcast layer
* @rcast: replicast (instead of broadcast) was used at previous xmit
* @mandatory: broadcast/replicast indication was set by user
* @expires: re-evaluate non-mandatory transmit method if we are past this
*/
struct tipc_mc_method {
bool rcast;
bool mandatory;
unsigned long expires;
};
int tipc_bcast_init(struct net *net);
void tipc_bcast_stop(struct net *net);
void tipc_bcast_add_peer(struct net *net, struct tipc_link *l,
struct sk_buff_head *xmitq);
void tipc_bcast_remove_peer(struct net *net, struct tipc_link *rcv_bcl);
void tipc_bcast_inc_bearer_dst_cnt(struct net *net, int bearer_id);
void tipc_bcast_dec_bearer_dst_cnt(struct net *net, int bearer_id);
int tipc_bcast_get_mtu(struct net *net);
void tipc_bcast_disable_rcast(struct net *net);
int tipc_mcast_xmit(struct net *net, struct sk_buff_head *pkts,
struct tipc_mc_method *method, struct tipc_nlist *dests,
u16 *cong_link_cnt);
int tipc_bcast_rcv(struct net *net, struct tipc_link *l, struct sk_buff *skb);
void tipc_bcast_ack_rcv(struct net *net, struct tipc_link *l,
struct tipc_msg *hdr);
int tipc_bcast_sync_rcv(struct net *net, struct tipc_link *l,
struct tipc_msg *hdr);
int tipc_nl_add_bc_link(struct net *net, struct tipc_nl_msg *msg);
int tipc_nl_bc_link_set(struct net *net, struct nlattr *attrs[]);
int tipc_bclink_reset_stats(struct net *net);
static inline void tipc_bcast_lock(struct net *net)
{
spin_lock_bh(&tipc_net(net)->bclock);
}
static inline void tipc_bcast_unlock(struct net *net)
{
spin_unlock_bh(&tipc_net(net)->bclock);
}
static inline struct tipc_link *tipc_bc_sndlink(struct net *net)
{
return tipc_net(net)->bcl;
}
#endif
| null | null | null | null | 75,693 |
1,416 | null | train_val | 04b570817b2b38e35675b17328239746212f4c3f | 154,473 | FFmpeg | 0 | https://github.com/FFmpeg/FFmpeg | 2018-06-01 01:23:12+05:30 | /*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef AVCODEC_WMV2DSP_H
#define AVCODEC_WMV2DSP_H
#include <stdint.h>
#include "qpeldsp.h"
typedef struct WMV2DSPContext {
void (*idct_add)(uint8_t *dest, ptrdiff_t line_size, int16_t *block);
void (*idct_put)(uint8_t *dest, ptrdiff_t line_size, int16_t *block);
qpel_mc_func put_mspel_pixels_tab[8];
int idct_perm;
} WMV2DSPContext;
void ff_wmv2dsp_init(WMV2DSPContext *c);
void ff_wmv2dsp_init_mips(WMV2DSPContext *c);
#endif /* AVCODEC_WMV2DSP_H */
| null | null | null | null | 70,528 |
49,949 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 49,949 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2017 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef UI_BASE_UI_BASE_FEATURES_H_
#define UI_BASE_UI_BASE_FEATURES_H_
#include "base/feature_list.h"
#include "build/build_config.h"
#include "ui/base/ui_base_export.h"
#include "ui/base/ui_features.h"
namespace features {
// Keep sorted!
UI_BASE_EXPORT extern const base::Feature kEnableEmojiContextMenu;
UI_BASE_EXPORT extern const base::Feature kEnableFloatingVirtualKeyboard;
UI_BASE_EXPORT extern const base::Feature
kEnableFullscreenHandwritingVirtualKeyboard;
UI_BASE_EXPORT extern const base::Feature kEnableStylusVirtualKeyboard;
UI_BASE_EXPORT extern const base::Feature kSecondaryUiMd;
UI_BASE_EXPORT extern const base::Feature kTouchableAppContextMenu;
UI_BASE_EXPORT bool IsTouchableAppContextMenuEnabled();
#if defined(OS_WIN)
UI_BASE_EXPORT extern const base::Feature kDirectManipulationStylus;
UI_BASE_EXPORT extern const base::Feature kPointerEventsForTouch;
UI_BASE_EXPORT extern const base::Feature kPrecisionTouchpad;
UI_BASE_EXPORT extern const base::Feature kPrecisionTouchpadScrollPhase;
UI_BASE_EXPORT extern const base::Feature kTSFImeSupport;
// Returns true if the system should use WM_POINTER events for touch events.
UI_BASE_EXPORT bool IsUsingWMPointerForTouch();
#endif // defined(OS_WIN)
// TODO(sky): rename this to something that better conveys what it means.
UI_BASE_EXPORT extern const base::Feature kMash;
// WARNING: generally you should only use this in tests to enable the feature.
// Outside of tests use IsMusEnabled() to detect if mus is enabled.
// TODO(sky): rename this to kWindowService.
UI_BASE_EXPORT extern const base::Feature kMus;
// Returns true if mus (the Window Service) is enabled.
// NOTE: this returns true if either kMus or kMash is specified.
// TODO(sky): rename this to IsWindowServiceEnabled().
UI_BASE_EXPORT bool IsMusEnabled();
#if defined(OS_MACOSX)
// Returns true if the NSWindows for apps will be created in the app's process,
// and will forward input to the browser process.
UI_BASE_EXPORT bool HostWindowsInAppShimProcess();
#if BUILDFLAG(MAC_VIEWS_BROWSER)
UI_BASE_EXPORT extern const base::Feature kViewsBrowserWindows;
// Returns whether a Views-capable browser build should use the Cocoa browser
// UI.
UI_BASE_EXPORT bool IsViewsBrowserCocoa();
#endif // BUILDFLAG(MAC_VIEWS_BROWSER)
#endif // defined(OS_MACOSX)
} // namespace features
#endif // UI_BASE_UI_BASE_FEATURES_H_
| null | null | null | null | 46,812 |
33,861 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 198,856 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Zoran ZR36060 basic configuration functions
*
* Copyright (C) 2002 Laurent Pinchart <laurent.pinchart@skynet.be>
*
* $Id: zr36060.c,v 1.1.2.22 2003/05/06 09:35:36 rbultje Exp $
*
* ------------------------------------------------------------------------
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* ------------------------------------------------------------------------
*/
#define ZR060_VERSION "v0.7"
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/wait.h>
/* I/O commands, error codes */
#include <asm/io.h>
/* headerfile of this module */
#include "zr36060.h"
/* codec io API */
#include "videocodec.h"
/* it doesn't make sense to have more than 20 or so,
just to prevent some unwanted loops */
#define MAX_CODECS 20
/* amount of chips attached via this driver */
static int zr36060_codecs;
static bool low_bitrate;
module_param(low_bitrate, bool, 0);
MODULE_PARM_DESC(low_bitrate, "Buz compatibility option, halves bitrate");
/* debugging is available via module parameter */
static int debug;
module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Debug level (0-4)");
#define dprintk(num, format, args...) \
do { \
if (debug >= num) \
printk(format, ##args); \
} while (0)
/* =========================================================================
Local hardware I/O functions:
read/write via codec layer (registers are located in the master device)
========================================================================= */
/* read and write functions */
static u8
zr36060_read (struct zr36060 *ptr,
u16 reg)
{
u8 value = 0;
// just in case something is wrong...
if (ptr->codec->master_data->readreg)
value = (ptr->codec->master_data->readreg(ptr->codec,
reg)) & 0xff;
else
dprintk(1,
KERN_ERR "%s: invalid I/O setup, nothing read!\n",
ptr->name);
//dprintk(4, "%s: reading from 0x%04x: %02x\n",ptr->name,reg,value);
return value;
}
static void
zr36060_write(struct zr36060 *ptr,
u16 reg,
u8 value)
{
//dprintk(4, "%s: writing 0x%02x to 0x%04x\n",ptr->name,value,reg);
dprintk(4, "0x%02x @0x%04x\n", value, reg);
// just in case something is wrong...
if (ptr->codec->master_data->writereg)
ptr->codec->master_data->writereg(ptr->codec, reg, value);
else
dprintk(1,
KERN_ERR
"%s: invalid I/O setup, nothing written!\n",
ptr->name);
}
/* =========================================================================
Local helper function:
status read
========================================================================= */
/* status is kept in datastructure */
static u8
zr36060_read_status (struct zr36060 *ptr)
{
ptr->status = zr36060_read(ptr, ZR060_CFSR);
zr36060_read(ptr, 0);
return ptr->status;
}
/* =========================================================================
Local helper function:
scale factor read
========================================================================= */
/* scale factor is kept in datastructure */
static u16
zr36060_read_scalefactor (struct zr36060 *ptr)
{
ptr->scalefact = (zr36060_read(ptr, ZR060_SF_HI) << 8) |
(zr36060_read(ptr, ZR060_SF_LO) & 0xFF);
/* leave 0 selected for an eventually GO from master */
zr36060_read(ptr, 0);
return ptr->scalefact;
}
/* =========================================================================
Local helper function:
wait if codec is ready to proceed (end of processing) or time is over
========================================================================= */
static void
zr36060_wait_end (struct zr36060 *ptr)
{
int i = 0;
while (zr36060_read_status(ptr) & ZR060_CFSR_Busy) {
udelay(1);
if (i++ > 200000) { // 200ms, there is for sure something wrong!!!
dprintk(1,
"%s: timeout at wait_end (last status: 0x%02x)\n",
ptr->name, ptr->status);
break;
}
}
}
/* =========================================================================
Local helper function:
basic test of "connectivity", writes/reads to/from memory the SOF marker
========================================================================= */
static int
zr36060_basic_test (struct zr36060 *ptr)
{
if ((zr36060_read(ptr, ZR060_IDR_DEV) != 0x33) &&
(zr36060_read(ptr, ZR060_IDR_REV) != 0x01)) {
dprintk(1,
KERN_ERR
"%s: attach failed, can't connect to jpeg processor!\n",
ptr->name);
return -ENXIO;
}
zr36060_wait_end(ptr);
if (ptr->status & ZR060_CFSR_Busy) {
dprintk(1,
KERN_ERR
"%s: attach failed, jpeg processor failed (end flag)!\n",
ptr->name);
return -EBUSY;
}
return 0; /* looks good! */
}
/* =========================================================================
Local helper function:
simple loop for pushing the init datasets
========================================================================= */
static int
zr36060_pushit (struct zr36060 *ptr,
u16 startreg,
u16 len,
const char *data)
{
int i = 0;
dprintk(4, "%s: write data block to 0x%04x (len=%d)\n", ptr->name,
startreg, len);
while (i < len) {
zr36060_write(ptr, startreg++, data[i++]);
}
return i;
}
/* =========================================================================
Basic datasets:
jpeg baseline setup data (you find it on lots places in internet, or just
extract it from any regular .jpg image...)
Could be variable, but until it's not needed it they are just fixed to save
memory. Otherwise expand zr36060 structure with arrays, push the values to
it and initialize from there, as e.g. the linux zr36057/60 driver does it.
========================================================================= */
static const char zr36060_dqt[0x86] = {
0xff, 0xdb, //Marker: DQT
0x00, 0x84, //Length: 2*65+2
0x00, //Pq,Tq first table
0x10, 0x0b, 0x0c, 0x0e, 0x0c, 0x0a, 0x10, 0x0e,
0x0d, 0x0e, 0x12, 0x11, 0x10, 0x13, 0x18, 0x28,
0x1a, 0x18, 0x16, 0x16, 0x18, 0x31, 0x23, 0x25,
0x1d, 0x28, 0x3a, 0x33, 0x3d, 0x3c, 0x39, 0x33,
0x38, 0x37, 0x40, 0x48, 0x5c, 0x4e, 0x40, 0x44,
0x57, 0x45, 0x37, 0x38, 0x50, 0x6d, 0x51, 0x57,
0x5f, 0x62, 0x67, 0x68, 0x67, 0x3e, 0x4d, 0x71,
0x79, 0x70, 0x64, 0x78, 0x5c, 0x65, 0x67, 0x63,
0x01, //Pq,Tq second table
0x11, 0x12, 0x12, 0x18, 0x15, 0x18, 0x2f, 0x1a,
0x1a, 0x2f, 0x63, 0x42, 0x38, 0x42, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63
};
static const char zr36060_dht[0x1a4] = {
0xff, 0xc4, //Marker: DHT
0x01, 0xa2, //Length: 2*AC, 2*DC
0x00, //DC first table
0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x01, //DC second table
0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x10, //AC first table
0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03,
0x05, 0x05, 0x04, 0x04, 0x00, 0x00,
0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04, 0x11,
0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61,
0x07, 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1,
0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24,
0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17,
0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34,
0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44,
0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66,
0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88,
0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99,
0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8,
0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9,
0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8,
0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9,
0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
0xF8, 0xF9, 0xFA,
0x11, //AC second table
0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04,
0x07, 0x05, 0x04, 0x04, 0x00, 0x01,
0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04,
0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
0xA1, 0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0, 0x15, 0x62,
0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25,
0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A,
0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44,
0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66,
0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
0x79, 0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7,
0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8,
0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8,
0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8,
0xF9, 0xFA
};
/* jpeg baseline setup, this is just fixed in this driver (YUV pictures) */
#define NO_OF_COMPONENTS 0x3 //Y,U,V
#define BASELINE_PRECISION 0x8 //MCU size (?)
static const char zr36060_tq[8] = { 0, 1, 1, 0, 0, 0, 0, 0 }; //table idx's QT
static const char zr36060_td[8] = { 0, 1, 1, 0, 0, 0, 0, 0 }; //table idx's DC
static const char zr36060_ta[8] = { 0, 1, 1, 0, 0, 0, 0, 0 }; //table idx's AC
/* horizontal 422 decimation setup (maybe we support 411 or so later, too) */
static const char zr36060_decimation_h[8] = { 2, 1, 1, 0, 0, 0, 0, 0 };
static const char zr36060_decimation_v[8] = { 1, 1, 1, 0, 0, 0, 0, 0 };
/* =========================================================================
Local helper functions:
calculation and setup of parameter-dependent JPEG baseline segments
(needed for compression only)
========================================================================= */
/* ------------------------------------------------------------------------- */
/* SOF (start of frame) segment depends on width, height and sampling ratio
of each color component */
static int
zr36060_set_sof (struct zr36060 *ptr)
{
char sof_data[34]; // max. size of register set
int i;
dprintk(3, "%s: write SOF (%dx%d, %d components)\n", ptr->name,
ptr->width, ptr->height, NO_OF_COMPONENTS);
sof_data[0] = 0xff;
sof_data[1] = 0xc0;
sof_data[2] = 0x00;
sof_data[3] = (3 * NO_OF_COMPONENTS) + 8;
sof_data[4] = BASELINE_PRECISION; // only '8' possible with zr36060
sof_data[5] = (ptr->height) >> 8;
sof_data[6] = (ptr->height) & 0xff;
sof_data[7] = (ptr->width) >> 8;
sof_data[8] = (ptr->width) & 0xff;
sof_data[9] = NO_OF_COMPONENTS;
for (i = 0; i < NO_OF_COMPONENTS; i++) {
sof_data[10 + (i * 3)] = i; // index identifier
sof_data[11 + (i * 3)] = (ptr->h_samp_ratio[i] << 4) |
(ptr->v_samp_ratio[i]); // sampling ratios
sof_data[12 + (i * 3)] = zr36060_tq[i]; // Q table selection
}
return zr36060_pushit(ptr, ZR060_SOF_IDX,
(3 * NO_OF_COMPONENTS) + 10, sof_data);
}
/* ------------------------------------------------------------------------- */
/* SOS (start of scan) segment depends on the used scan components
of each color component */
static int
zr36060_set_sos (struct zr36060 *ptr)
{
char sos_data[16]; // max. size of register set
int i;
dprintk(3, "%s: write SOS\n", ptr->name);
sos_data[0] = 0xff;
sos_data[1] = 0xda;
sos_data[2] = 0x00;
sos_data[3] = 2 + 1 + (2 * NO_OF_COMPONENTS) + 3;
sos_data[4] = NO_OF_COMPONENTS;
for (i = 0; i < NO_OF_COMPONENTS; i++) {
sos_data[5 + (i * 2)] = i; // index
sos_data[6 + (i * 2)] = (zr36060_td[i] << 4) |
zr36060_ta[i]; // AC/DC tbl.sel.
}
sos_data[2 + 1 + (2 * NO_OF_COMPONENTS) + 2] = 00; // scan start
sos_data[2 + 1 + (2 * NO_OF_COMPONENTS) + 3] = 0x3f;
sos_data[2 + 1 + (2 * NO_OF_COMPONENTS) + 4] = 00;
return zr36060_pushit(ptr, ZR060_SOS_IDX,
4 + 1 + (2 * NO_OF_COMPONENTS) + 3,
sos_data);
}
/* ------------------------------------------------------------------------- */
/* DRI (define restart interval) */
static int
zr36060_set_dri (struct zr36060 *ptr)
{
char dri_data[6]; // max. size of register set
dprintk(3, "%s: write DRI\n", ptr->name);
dri_data[0] = 0xff;
dri_data[1] = 0xdd;
dri_data[2] = 0x00;
dri_data[3] = 0x04;
dri_data[4] = (ptr->dri) >> 8;
dri_data[5] = (ptr->dri) & 0xff;
return zr36060_pushit(ptr, ZR060_DRI_IDX, 6, dri_data);
}
/* =========================================================================
Setup function:
Setup compression/decompression of Zoran's JPEG processor
( see also zoran 36060 manual )
... sorry for the spaghetti code ...
========================================================================= */
static void
zr36060_init (struct zr36060 *ptr)
{
int sum = 0;
long bitcnt, tmp;
if (ptr->mode == CODEC_DO_COMPRESSION) {
dprintk(2, "%s: COMPRESSION SETUP\n", ptr->name);
zr36060_write(ptr, ZR060_LOAD, ZR060_LOAD_SyncRst);
/* 060 communicates with 067 in master mode */
zr36060_write(ptr, ZR060_CIR, ZR060_CIR_CodeMstr);
/* Compression with or without variable scale factor */
/*FIXME: What about ptr->bitrate_ctrl? */
zr36060_write(ptr, ZR060_CMR,
ZR060_CMR_Comp | ZR060_CMR_Pass2 |
ZR060_CMR_BRB);
/* Must be zero */
zr36060_write(ptr, ZR060_MBZ, 0x00);
zr36060_write(ptr, ZR060_TCR_HI, 0x00);
zr36060_write(ptr, ZR060_TCR_LO, 0x00);
/* Disable all IRQs - no DataErr means autoreset */
zr36060_write(ptr, ZR060_IMR, 0);
/* volume control settings */
zr36060_write(ptr, ZR060_SF_HI, ptr->scalefact >> 8);
zr36060_write(ptr, ZR060_SF_LO, ptr->scalefact & 0xff);
zr36060_write(ptr, ZR060_AF_HI, 0xff);
zr36060_write(ptr, ZR060_AF_M, 0xff);
zr36060_write(ptr, ZR060_AF_LO, 0xff);
/* setup the variable jpeg tables */
sum += zr36060_set_sof(ptr);
sum += zr36060_set_sos(ptr);
sum += zr36060_set_dri(ptr);
/* setup the fixed jpeg tables - maybe variable, though -
* (see table init section above) */
sum +=
zr36060_pushit(ptr, ZR060_DQT_IDX, sizeof(zr36060_dqt),
zr36060_dqt);
sum +=
zr36060_pushit(ptr, ZR060_DHT_IDX, sizeof(zr36060_dht),
zr36060_dht);
zr36060_write(ptr, ZR060_APP_IDX, 0xff);
zr36060_write(ptr, ZR060_APP_IDX + 1, 0xe0 + ptr->app.appn);
zr36060_write(ptr, ZR060_APP_IDX + 2, 0x00);
zr36060_write(ptr, ZR060_APP_IDX + 3, ptr->app.len + 2);
sum += zr36060_pushit(ptr, ZR060_APP_IDX + 4, 60,
ptr->app.data) + 4;
zr36060_write(ptr, ZR060_COM_IDX, 0xff);
zr36060_write(ptr, ZR060_COM_IDX + 1, 0xfe);
zr36060_write(ptr, ZR060_COM_IDX + 2, 0x00);
zr36060_write(ptr, ZR060_COM_IDX + 3, ptr->com.len + 2);
sum += zr36060_pushit(ptr, ZR060_COM_IDX + 4, 60,
ptr->com.data) + 4;
/* setup misc. data for compression (target code sizes) */
/* size of compressed code to reach without header data */
sum = ptr->real_code_vol - sum;
bitcnt = sum << 3; /* need the size in bits */
tmp = bitcnt >> 16;
dprintk(3,
"%s: code: csize=%d, tot=%d, bit=%ld, highbits=%ld\n",
ptr->name, sum, ptr->real_code_vol, bitcnt, tmp);
zr36060_write(ptr, ZR060_TCV_NET_HI, tmp >> 8);
zr36060_write(ptr, ZR060_TCV_NET_MH, tmp & 0xff);
tmp = bitcnt & 0xffff;
zr36060_write(ptr, ZR060_TCV_NET_ML, tmp >> 8);
zr36060_write(ptr, ZR060_TCV_NET_LO, tmp & 0xff);
bitcnt -= bitcnt >> 7; // bits without stuffing
bitcnt -= ((bitcnt * 5) >> 6); // bits without eob
tmp = bitcnt >> 16;
dprintk(3, "%s: code: nettobit=%ld, highnettobits=%ld\n",
ptr->name, bitcnt, tmp);
zr36060_write(ptr, ZR060_TCV_DATA_HI, tmp >> 8);
zr36060_write(ptr, ZR060_TCV_DATA_MH, tmp & 0xff);
tmp = bitcnt & 0xffff;
zr36060_write(ptr, ZR060_TCV_DATA_ML, tmp >> 8);
zr36060_write(ptr, ZR060_TCV_DATA_LO, tmp & 0xff);
/* JPEG markers to be included in the compressed stream */
zr36060_write(ptr, ZR060_MER,
ZR060_MER_DQT | ZR060_MER_DHT |
((ptr->com.len > 0) ? ZR060_MER_Com : 0) |
((ptr->app.len > 0) ? ZR060_MER_App : 0));
/* Setup the Video Frontend */
/* Limit pixel range to 16..235 as per CCIR-601 */
zr36060_write(ptr, ZR060_VCR, ZR060_VCR_Range);
} else {
dprintk(2, "%s: EXPANSION SETUP\n", ptr->name);
zr36060_write(ptr, ZR060_LOAD, ZR060_LOAD_SyncRst);
/* 060 communicates with 067 in master mode */
zr36060_write(ptr, ZR060_CIR, ZR060_CIR_CodeMstr);
/* Decompression */
zr36060_write(ptr, ZR060_CMR, 0);
/* Must be zero */
zr36060_write(ptr, ZR060_MBZ, 0x00);
zr36060_write(ptr, ZR060_TCR_HI, 0x00);
zr36060_write(ptr, ZR060_TCR_LO, 0x00);
/* Disable all IRQs - no DataErr means autoreset */
zr36060_write(ptr, ZR060_IMR, 0);
/* setup misc. data for expansion */
zr36060_write(ptr, ZR060_MER, 0);
/* setup the fixed jpeg tables - maybe variable, though -
* (see table init section above) */
zr36060_pushit(ptr, ZR060_DHT_IDX, sizeof(zr36060_dht),
zr36060_dht);
/* Setup the Video Frontend */
//zr36060_write(ptr, ZR060_VCR, ZR060_VCR_FIExt);
//this doesn't seem right and doesn't work...
zr36060_write(ptr, ZR060_VCR, ZR060_VCR_Range);
}
/* Load the tables */
zr36060_write(ptr, ZR060_LOAD,
ZR060_LOAD_SyncRst | ZR060_LOAD_Load);
zr36060_wait_end(ptr);
dprintk(2, "%s: Status after table preload: 0x%02x\n", ptr->name,
ptr->status);
if (ptr->status & ZR060_CFSR_Busy) {
dprintk(1, KERN_ERR "%s: init aborted!\n", ptr->name);
return; // something is wrong, its timed out!!!!
}
}
/* =========================================================================
CODEC API FUNCTIONS
this functions are accessed by the master via the API structure
========================================================================= */
/* set compression/expansion mode and launches codec -
this should be the last call from the master before starting processing */
static int
zr36060_set_mode (struct videocodec *codec,
int mode)
{
struct zr36060 *ptr = (struct zr36060 *) codec->data;
dprintk(2, "%s: set_mode %d call\n", ptr->name, mode);
if ((mode != CODEC_DO_EXPANSION) && (mode != CODEC_DO_COMPRESSION))
return -EINVAL;
ptr->mode = mode;
zr36060_init(ptr);
return 0;
}
/* set picture size (norm is ignored as the codec doesn't know about it) */
static int
zr36060_set_video (struct videocodec *codec,
struct tvnorm *norm,
struct vfe_settings *cap,
struct vfe_polarity *pol)
{
struct zr36060 *ptr = (struct zr36060 *) codec->data;
u32 reg;
int size;
dprintk(2, "%s: set_video %d/%d-%dx%d (%%%d) call\n", ptr->name,
cap->x, cap->y, cap->width, cap->height, cap->decimation);
/* if () return -EINVAL;
* trust the master driver that it knows what it does - so
* we allow invalid startx/y and norm for now ... */
ptr->width = cap->width / (cap->decimation & 0xff);
ptr->height = cap->height / (cap->decimation >> 8);
zr36060_write(ptr, ZR060_LOAD, ZR060_LOAD_SyncRst);
/* Note that VSPol/HSPol bits in zr36060 have the opposite
* meaning of their zr360x7 counterparts with the same names
* N.b. for VSPol this is only true if FIVEdge = 0 (default,
* left unchanged here - in accordance with datasheet).
*/
reg = (!pol->vsync_pol ? ZR060_VPR_VSPol : 0)
| (!pol->hsync_pol ? ZR060_VPR_HSPol : 0)
| (pol->field_pol ? ZR060_VPR_FIPol : 0)
| (pol->blank_pol ? ZR060_VPR_BLPol : 0)
| (pol->subimg_pol ? ZR060_VPR_SImgPol : 0)
| (pol->poe_pol ? ZR060_VPR_PoePol : 0)
| (pol->pvalid_pol ? ZR060_VPR_PValPol : 0)
| (pol->vclk_pol ? ZR060_VPR_VCLKPol : 0);
zr36060_write(ptr, ZR060_VPR, reg);
reg = 0;
switch (cap->decimation & 0xff) {
default:
case 1:
break;
case 2:
reg |= ZR060_SR_HScale2;
break;
case 4:
reg |= ZR060_SR_HScale4;
break;
}
switch (cap->decimation >> 8) {
default:
case 1:
break;
case 2:
reg |= ZR060_SR_VScale;
break;
}
zr36060_write(ptr, ZR060_SR, reg);
zr36060_write(ptr, ZR060_BCR_Y, 0x00);
zr36060_write(ptr, ZR060_BCR_U, 0x80);
zr36060_write(ptr, ZR060_BCR_V, 0x80);
/* sync generator */
reg = norm->Ht - 1; /* Vtotal */
zr36060_write(ptr, ZR060_SGR_VTOTAL_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SGR_VTOTAL_LO, (reg >> 0) & 0xff);
reg = norm->Wt - 1; /* Htotal */
zr36060_write(ptr, ZR060_SGR_HTOTAL_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SGR_HTOTAL_LO, (reg >> 0) & 0xff);
reg = 6 - 1; /* VsyncSize */
zr36060_write(ptr, ZR060_SGR_VSYNC, reg);
//reg = 30 - 1; /* HsyncSize */
///*CP*/ reg = (zr->params.norm == 1 ? 57 : 68);
reg = 68;
zr36060_write(ptr, ZR060_SGR_HSYNC, reg);
reg = norm->VStart - 1; /* BVstart */
zr36060_write(ptr, ZR060_SGR_BVSTART, reg);
reg += norm->Ha / 2; /* BVend */
zr36060_write(ptr, ZR060_SGR_BVEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SGR_BVEND_LO, (reg >> 0) & 0xff);
reg = norm->HStart - 1; /* BHstart */
zr36060_write(ptr, ZR060_SGR_BHSTART, reg);
reg += norm->Wa; /* BHend */
zr36060_write(ptr, ZR060_SGR_BHEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SGR_BHEND_LO, (reg >> 0) & 0xff);
/* active area */
reg = cap->y + norm->VStart; /* Vstart */
zr36060_write(ptr, ZR060_AAR_VSTART_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_AAR_VSTART_LO, (reg >> 0) & 0xff);
reg += cap->height; /* Vend */
zr36060_write(ptr, ZR060_AAR_VEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_AAR_VEND_LO, (reg >> 0) & 0xff);
reg = cap->x + norm->HStart; /* Hstart */
zr36060_write(ptr, ZR060_AAR_HSTART_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_AAR_HSTART_LO, (reg >> 0) & 0xff);
reg += cap->width; /* Hend */
zr36060_write(ptr, ZR060_AAR_HEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_AAR_HEND_LO, (reg >> 0) & 0xff);
/* subimage area */
reg = norm->VStart - 4; /* SVstart */
zr36060_write(ptr, ZR060_SWR_VSTART_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SWR_VSTART_LO, (reg >> 0) & 0xff);
reg += norm->Ha / 2 + 8; /* SVend */
zr36060_write(ptr, ZR060_SWR_VEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SWR_VEND_LO, (reg >> 0) & 0xff);
reg = norm->HStart /*+ 64 */ - 4; /* SHstart */
zr36060_write(ptr, ZR060_SWR_HSTART_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SWR_HSTART_LO, (reg >> 0) & 0xff);
reg += norm->Wa + 8; /* SHend */
zr36060_write(ptr, ZR060_SWR_HEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SWR_HEND_LO, (reg >> 0) & 0xff);
size = ptr->width * ptr->height;
/* Target compressed field size in bits: */
size = size * 16; /* uncompressed size in bits */
/* (Ronald) by default, quality = 100 is a compression
* ratio 1:2. Setting low_bitrate (insmod option) sets
* it to 1:4 (instead of 1:2, zr36060 max) as limit because the
* buz can't handle more at decimation=1... Use low_bitrate if
* you have a Buz, unless you know what you're doing */
size = size * cap->quality / (low_bitrate ? 400 : 200);
/* Lower limit (arbitrary, 1 KB) */
if (size < 8192)
size = 8192;
/* Upper limit: 7/8 of the code buffers */
if (size > ptr->total_code_vol * 7)
size = ptr->total_code_vol * 7;
ptr->real_code_vol = size >> 3; /* in bytes */
/* the MBCVR is the *maximum* block volume, according to the
* JPEG ISO specs, this shouldn't be used, since that allows
* for the best encoding quality. So set it to it's max value */
reg = ptr->max_block_vol;
zr36060_write(ptr, ZR060_MBCVR, reg);
return 0;
}
/* additional control functions */
static int
zr36060_control (struct videocodec *codec,
int type,
int size,
void *data)
{
struct zr36060 *ptr = (struct zr36060 *) codec->data;
int *ival = (int *) data;
dprintk(2, "%s: control %d call with %d byte\n", ptr->name, type,
size);
switch (type) {
case CODEC_G_STATUS: /* get last status */
if (size != sizeof(int))
return -EFAULT;
zr36060_read_status(ptr);
*ival = ptr->status;
break;
case CODEC_G_CODEC_MODE:
if (size != sizeof(int))
return -EFAULT;
*ival = CODEC_MODE_BJPG;
break;
case CODEC_S_CODEC_MODE:
if (size != sizeof(int))
return -EFAULT;
if (*ival != CODEC_MODE_BJPG)
return -EINVAL;
/* not needed, do nothing */
return 0;
case CODEC_G_VFE:
case CODEC_S_VFE:
/* not needed, do nothing */
return 0;
case CODEC_S_MMAP:
/* not available, give an error */
return -ENXIO;
case CODEC_G_JPEG_TDS_BYTE: /* get target volume in byte */
if (size != sizeof(int))
return -EFAULT;
*ival = ptr->total_code_vol;
break;
case CODEC_S_JPEG_TDS_BYTE: /* get target volume in byte */
if (size != sizeof(int))
return -EFAULT;
ptr->total_code_vol = *ival;
ptr->real_code_vol = (ptr->total_code_vol * 6) >> 3;
break;
case CODEC_G_JPEG_SCALE: /* get scaling factor */
if (size != sizeof(int))
return -EFAULT;
*ival = zr36060_read_scalefactor(ptr);
break;
case CODEC_S_JPEG_SCALE: /* set scaling factor */
if (size != sizeof(int))
return -EFAULT;
ptr->scalefact = *ival;
break;
case CODEC_G_JPEG_APP_DATA: { /* get appn marker data */
struct jpeg_app_marker *app = data;
if (size != sizeof(struct jpeg_app_marker))
return -EFAULT;
*app = ptr->app;
break;
}
case CODEC_S_JPEG_APP_DATA: { /* set appn marker data */
struct jpeg_app_marker *app = data;
if (size != sizeof(struct jpeg_app_marker))
return -EFAULT;
ptr->app = *app;
break;
}
case CODEC_G_JPEG_COM_DATA: { /* get comment marker data */
struct jpeg_com_marker *com = data;
if (size != sizeof(struct jpeg_com_marker))
return -EFAULT;
*com = ptr->com;
break;
}
case CODEC_S_JPEG_COM_DATA: { /* set comment marker data */
struct jpeg_com_marker *com = data;
if (size != sizeof(struct jpeg_com_marker))
return -EFAULT;
ptr->com = *com;
break;
}
default:
return -EINVAL;
}
return size;
}
/* =========================================================================
Exit and unregister function:
Deinitializes Zoran's JPEG processor
========================================================================= */
static int
zr36060_unset (struct videocodec *codec)
{
struct zr36060 *ptr = codec->data;
if (ptr) {
/* do wee need some codec deinit here, too ???? */
dprintk(1, "%s: finished codec #%d\n", ptr->name,
ptr->num);
kfree(ptr);
codec->data = NULL;
zr36060_codecs--;
return 0;
}
return -EFAULT;
}
/* =========================================================================
Setup and registry function:
Initializes Zoran's JPEG processor
Also sets pixel size, average code size, mode (compr./decompr.)
(the given size is determined by the processor with the video interface)
========================================================================= */
static int
zr36060_setup (struct videocodec *codec)
{
struct zr36060 *ptr;
int res;
dprintk(2, "zr36060: initializing MJPEG subsystem #%d.\n",
zr36060_codecs);
if (zr36060_codecs == MAX_CODECS) {
dprintk(1,
KERN_ERR "zr36060: Can't attach more codecs!\n");
return -ENOSPC;
}
//mem structure init
codec->data = ptr = kzalloc(sizeof(struct zr36060), GFP_KERNEL);
if (NULL == ptr) {
dprintk(1, KERN_ERR "zr36060: Can't get enough memory!\n");
return -ENOMEM;
}
snprintf(ptr->name, sizeof(ptr->name), "zr36060[%d]",
zr36060_codecs);
ptr->num = zr36060_codecs++;
ptr->codec = codec;
//testing
res = zr36060_basic_test(ptr);
if (res < 0) {
zr36060_unset(codec);
return res;
}
//final setup
memcpy(ptr->h_samp_ratio, zr36060_decimation_h, 8);
memcpy(ptr->v_samp_ratio, zr36060_decimation_v, 8);
ptr->bitrate_ctrl = 0; /* 0 or 1 - fixed file size flag
* (what is the difference?) */
ptr->mode = CODEC_DO_COMPRESSION;
ptr->width = 384;
ptr->height = 288;
ptr->total_code_vol = 16000; /* CHECKME */
ptr->real_code_vol = (ptr->total_code_vol * 6) >> 3;
ptr->max_block_vol = 240; /* CHECKME, was 120 is 240 */
ptr->scalefact = 0x100;
ptr->dri = 1; /* CHECKME, was 8 is 1 */
/* by default, no COM or APP markers - app should set those */
ptr->com.len = 0;
ptr->app.appn = 0;
ptr->app.len = 0;
zr36060_init(ptr);
dprintk(1, KERN_INFO "%s: codec attached and running\n",
ptr->name);
return 0;
}
static const struct videocodec zr36060_codec = {
.owner = THIS_MODULE,
.name = "zr36060",
.magic = 0L, // magic not used
.flags =
CODEC_FLAG_JPEG | CODEC_FLAG_HARDWARE | CODEC_FLAG_ENCODER |
CODEC_FLAG_DECODER | CODEC_FLAG_VFE,
.type = CODEC_TYPE_ZR36060,
.setup = zr36060_setup, // functionality
.unset = zr36060_unset,
.set_mode = zr36060_set_mode,
.set_video = zr36060_set_video,
.control = zr36060_control,
// others are not used
};
/* =========================================================================
HOOK IN DRIVER AS KERNEL MODULE
========================================================================= */
static int __init
zr36060_init_module (void)
{
//dprintk(1, "zr36060 driver %s\n",ZR060_VERSION);
zr36060_codecs = 0;
return videocodec_register(&zr36060_codec);
}
static void __exit
zr36060_cleanup_module (void)
{
if (zr36060_codecs) {
dprintk(1,
"zr36060: something's wrong - %d codecs left somehow.\n",
zr36060_codecs);
}
/* however, we can't just stay alive */
videocodec_unregister(&zr36060_codec);
}
module_init(zr36060_init_module);
module_exit(zr36060_cleanup_module);
MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@skynet.be>");
MODULE_DESCRIPTION("Driver module for ZR36060 jpeg processors "
ZR060_VERSION);
MODULE_LICENSE("GPL");
| null | null | null | null | 107,203 |
10,014 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 175,009 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX6SX_PINFUNC_H
#define __DTS_IMX6SX_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1
#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1
#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1
#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1
#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024 0x036C 0x0830 0x0 0x0
#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024 0x036C 0x0000 0x0 0x0
#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0
#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0
#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028 0x0370 0x0830 0x0 0x1
#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028 0x0370 0x0000 0x0 0x0
#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0
#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0
#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0
#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C 0x0374 0x0838 0x0 0x0
#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C 0x0374 0x0000 0x0 0x0
#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1
#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0
#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030 0x0378 0x0838 0x0 0x1
#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030 0x0378 0x0000 0x0 0x0
#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1
#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0
#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0
#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0
#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0
#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1
#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0
#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0
#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0
#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0
#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0
#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0
#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0
#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1
#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0
#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0
#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2
#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0
#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0
#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0
#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0
#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0
#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0
#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0
#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0
#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0
#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0
#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0
#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0
#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1
#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1
#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0
#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0
#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0
#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0
#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1
#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1
#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0
#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0
#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0
#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0
#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1
#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1
#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0
#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0
#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0
#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0
#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1
#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1
#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0
#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0
#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0
#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0
#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1
#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0
#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0
#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C 0x03A4 0x0858 0x4 0x0
#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C 0x03A4 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0
#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0
#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0
#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1
#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1
#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0
#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060 0x03A8 0x0858 0x4 0x1
#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060 0x03A8 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0
#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0
#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0
#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1
#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2
#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0
#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0
#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0
#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0
#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0
#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1
#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0
#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0
#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0
#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0
#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1
#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1
#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2
#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0
#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0
#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0
#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1
#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0
#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2
#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070 0x03B8 0x0000 0x3 0x0
#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0
#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0
#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0
#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1
#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0
#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074 0x03BC 0x0848 0x3 0x3
#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074 0x03BC 0x0000 0x3 0x0
#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2
#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0
#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0
#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1
#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0
#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0
#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0
#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0
#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0
#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0
#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1
#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0
#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1
#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0
#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0
#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0
#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0
#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0
#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0
#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1
#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1
#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0
#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0
#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0
#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0
#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0
#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0
#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0
#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0
#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0
#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1
#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0
#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0
#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0
#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0
#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0
#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1
#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2
#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0
#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0
#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0
#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0
#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1
#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0
#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0
#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0
#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1
#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0
#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0
#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0
#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0
#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0
#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0
#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0
#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0
/*
* SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is
* used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a
* PHY in RMII mode. This configuration is valid if:
* - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set
* - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset
* It seems to be a silicon bug that in this configuration ENET1_TX reference
* clock isn't provided automatically. According to i.MX6SX reference manual
* (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it
* should be the case.
* So this might have unwanted side effects for other hardware units that are
* also connected to that pin and using respective function as input (e.g.
* UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B).
*/
#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1
#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1
#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0
#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0
#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0
#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0
#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0
#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0
#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0
#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0
#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0
#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1
#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2
#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094 0x03DC 0x0000 0x3 0x0
#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3
#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0
#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1
#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0
#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0
#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0
#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0
#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2
#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1
#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098 0x03E0 0x0830 0x3 0x3
#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098 0x03E0 0x0000 0x3 0x0
#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1
#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0
#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1
#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0
#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0
#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0
#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0
#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0
#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1
#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2
#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1
#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0
#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1
#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0
#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0
#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0
#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0
#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1
#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0
#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1
#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0
#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0
#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0
#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0
#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0
#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0
#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2
#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0
#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0
#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0
#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1
#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0
#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0
#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0
#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2
#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0
#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0
#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0
#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0
#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0
#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1
#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2
#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0
#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0
#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0
#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0
#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0
#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0
#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2
#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0
#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0
#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0
#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0
#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0
#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0
#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2
#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0
#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0
#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0
#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0
#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0
#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0
#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0
#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0
#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0
#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1
#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0
#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0
#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0
#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3
#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0
#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0
#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0
#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0
#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0
#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0
#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1
#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1
#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1
#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0
#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0
#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0
#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0
#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3
#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1
#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1
#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0
#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0
#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0
#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3
#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2
#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0
#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0
#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0
#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0
#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0
#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1
#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0
#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0
#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0
#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0
#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0
#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0
#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0
#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0
#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0
#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0
#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1
#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1
#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1
#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0
#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1
#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1
#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1
#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1
#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1
#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1
#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1
#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1
#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0
#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0
#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0
#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0
#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0
#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0
#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0
#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0
#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0
#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0
#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0
#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0
#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0
#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0
#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0
#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0
#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1
#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0
#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0
#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0
#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1
#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0
#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0
#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0
#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1
#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0
#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0
#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0
#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0
#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1
#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1
#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0
#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0
#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0
#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0
#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0
#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0
#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0
#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0
#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0
#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0
#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0
#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0
#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0
#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0
#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0
#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0
#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0
#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0
#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0
#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0
#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0
#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0
#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0
#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0
#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0
#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0
#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0
#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0
#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168 0x04B0 0x0840 0x3 0x0
#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168 0x04B0 0x0000 0x3 0x0
#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0
#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C 0x04B4 0x0840 0x3 0x1
#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C 0x04B4 0x0000 0x3 0x0
#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0
#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0
#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0
#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0
#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0
#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0
#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0
#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0
#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0
#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0
#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0
#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0
#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0
#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0
#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0
#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2
#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1
#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2
#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1
#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0
#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2
#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1
#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2
#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1
#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0
#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0
#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0
#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2
#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1
#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0
#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2
#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0
#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2
#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1
#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0
#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0
#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0
#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1
#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1
#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0
#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2
#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1
#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2
#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1
#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0
#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0
#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1
#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2
#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1
#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0
#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2
#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2
#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1
#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1
#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0
#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0
#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1
#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5
#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1
#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2
#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1
#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2
#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0
#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2
#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1
#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2
#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0
#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2
#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1
#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0
#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0
#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1
#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1
#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4 0x04FC 0x0840 0x1 0x4
#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4 0x04FC 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1
#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2
#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1
#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8 0x0500 0x0840 0x1 0x5
#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8 0x0500 0x0000 0x1 0x0
#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1
#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3
#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1
#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2
#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2
#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1
#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1
#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0
#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1
#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0
#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1
#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1
#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1
#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1
#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1
#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0
#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0
#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0
#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0
#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0
#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0
#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1
#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0
#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1
#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0
#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1
#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0
#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1
#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0
#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1
#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0
#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1
#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0
#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0
#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0
#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0
#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0
#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0
#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0
#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0
#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0
#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0
#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1
#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0
#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0
#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0
#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0
#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0
#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0
#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0
#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1
#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0
#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0
#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0
#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0
#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0
#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0
#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0
#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1
#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0
#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0
#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2
#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228 0x0570 0x0000 0x4 0x0
#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0
#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0
#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0
#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0
#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1
#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0
#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0
#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C 0x0574 0x0838 0x4 0x3
#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C 0x0574 0x0000 0x4 0x0
#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0
#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0
#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0
#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0
#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1
#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0
#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0
#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0
#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0
#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0
#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1
#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2
#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0
#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3
#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2
#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0
#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0
#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2
#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1
#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1
#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2
#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0
#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0
#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0
#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0
#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0
#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0
#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2
#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1
#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1
#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2
#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0
#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0
#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0
#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0
#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0
#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0
#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2
#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1
#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0
#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3
#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0
#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0
#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240 0x0588 0x0848 0x7 0x4
#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240 0x0588 0x0000 0x7 0x0
#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0
#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0
#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0
#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2
#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1
#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0
#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3
#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0
#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0
#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244 0x058C 0x0848 0x7 0x5
#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244 0x058C 0x0000 0x7 0x0
#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0
#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0
#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0
#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2
#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1
#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1
#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2
#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0
#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0
#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248 0x0590 0x0858 0x7 0x4
#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248 0x0590 0x0000 0x7 0x0
#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0
#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0
#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0
#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2
#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1
#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1
#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2
#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0
#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4
#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C 0x0594 0x0858 0x7 0x5
#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C 0x0594 0x0000 0x7 0x0
#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0
#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0
#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0
#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0
#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254 0x059C 0x0848 0x1 0x0
#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254 0x059C 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0
#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0
#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1
#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0
#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0
#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0
#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0
#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0
#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0
#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0
#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0
#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0
#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0
#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0
#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0
#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0
#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0
#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1
#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0
#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0
#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0
#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0
#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0
#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264 0x05AC 0x0848 0x1 0x1
#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264 0x05AC 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0
#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0
#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0
#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0
#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0
#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0
#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0
#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2
#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268 0x05B0 0x0000 0x3 0x0
#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0
#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0
#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0
#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0
#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C 0x05B4 0x0840 0x3 0x3
#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C 0x05B4 0x0000 0x3 0x0
#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0
#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0
#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0
#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0
#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2
#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0
#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0
#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0
#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0
#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0
#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0
#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0
#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0
#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1
#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0
#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0
#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0
#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0
#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0
#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1
#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0
#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0
#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0
#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0
#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0
#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1
#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0
#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0
#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0
#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0
#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0
#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1
#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0
#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0
#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0
#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0
#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0
#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0
#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0
#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0
#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0
#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0
#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0
#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0
#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0
#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0
#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0
#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0
#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0
#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0
#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0
#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0
#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0
#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0
#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0
#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0
#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1
#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0
#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0
#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0
#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0
#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0
#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0
#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0
#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0
#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0
#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0
#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0
#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0
#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0
#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0
#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0
#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0
#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0
#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0
#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0
#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0
#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0
#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0
#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0
#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0
#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0
#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0
#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0
#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0
#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0
#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1
#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0
#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0
#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0
#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0
#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0
#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1
#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0
#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0
#endif /* __DTS_IMX6SX_PINFUNC_H */
| null | null | null | null | 83,356 |
25,753 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 190,748 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_SMC_H
#define PP_SMC_H
#pragma pack(push, 1)
#define SMU_UCODE_VERSION 0x001c0800
/* SMU Response Codes: */
#define PPSMC_Result_OK 0x1
#define PPSMC_Result_Failed 0xFF
#define PPSMC_Result_UnknownCmd 0xFE
#define PPSMC_Result_CmdRejectedPrereq 0xFD
#define PPSMC_Result_CmdRejectedBusy 0xFC
typedef uint16_t PPSMC_Result;
/* Message Definitions */
#define PPSMC_MSG_TestMessage 0x1
#define PPSMC_MSG_GetSmuVersion 0x2
#define PPSMC_MSG_GetDriverIfVersion 0x3
#define PPSMC_MSG_EnableSmuFeatures 0x4
#define PPSMC_MSG_DisableSmuFeatures 0x5
#define PPSMC_MSG_GetEnabledSmuFeatures 0x6
#define PPSMC_MSG_SetWorkloadMask 0x7
#define PPSMC_MSG_SetPptLimit 0x8
#define PPSMC_MSG_SetDriverDramAddrHigh 0x9
#define PPSMC_MSG_SetDriverDramAddrLow 0xA
#define PPSMC_MSG_SetToolsDramAddrHigh 0xB
#define PPSMC_MSG_SetToolsDramAddrLow 0xC
#define PPSMC_MSG_TransferTableSmu2Dram 0xD
#define PPSMC_MSG_TransferTableDram2Smu 0xE
#define PPSMC_MSG_UseDefaultPPTable 0xF
#define PPSMC_MSG_UseBackupPPTable 0x10
#define PPSMC_MSG_RunBtc 0x11
#define PPSMC_MSG_RequestI2CBus 0x12
#define PPSMC_MSG_ReleaseI2CBus 0x13
#define PPSMC_MSG_ConfigureTelemetry 0x14
#define PPSMC_MSG_SetUlvIpMask 0x15
#define PPSMC_MSG_SetSocVidOffset 0x16
#define PPSMC_MSG_SetMemVidOffset 0x17
#define PPSMC_MSG_GetSocVidOffset 0x18
#define PPSMC_MSG_GetMemVidOffset 0x19
#define PPSMC_MSG_SetFloorSocVoltage 0x1A
#define PPSMC_MSG_SoftReset 0x1B
#define PPSMC_MSG_StartBacoMonitor 0x1C
#define PPSMC_MSG_CancelBacoMonitor 0x1D
#define PPSMC_MSG_EnterBaco 0x1E
#define PPSMC_MSG_AllowLowGfxclkInterrupt 0x1F
#define PPSMC_MSG_SetLowGfxclkInterruptThreshold 0x20
#define PPSMC_MSG_SetSoftMinGfxclkByIndex 0x21
#define PPSMC_MSG_SetSoftMaxGfxclkByIndex 0x22
#define PPSMC_MSG_GetCurrentGfxclkIndex 0x23
#define PPSMC_MSG_SetSoftMinUclkByIndex 0x24
#define PPSMC_MSG_SetSoftMaxUclkByIndex 0x25
#define PPSMC_MSG_GetCurrentUclkIndex 0x26
#define PPSMC_MSG_SetSoftMinUvdByIndex 0x27
#define PPSMC_MSG_SetSoftMaxUvdByIndex 0x28
#define PPSMC_MSG_GetCurrentUvdIndex 0x29
#define PPSMC_MSG_SetSoftMinVceByIndex 0x2A
#define PPSMC_MSG_SetSoftMaxVceByIndex 0x2B
#define PPSMC_MSG_SetHardMinVceByIndex 0x2C
#define PPSMC_MSG_GetCurrentVceIndex 0x2D
#define PPSMC_MSG_SetSoftMinSocclkByIndex 0x2E
#define PPSMC_MSG_SetHardMinSocclkByIndex 0x2F
#define PPSMC_MSG_SetSoftMaxSocclkByIndex 0x30
#define PPSMC_MSG_GetCurrentSocclkIndex 0x31
#define PPSMC_MSG_SetMinLinkDpmByIndex 0x32
#define PPSMC_MSG_GetCurrentLinkIndex 0x33
#define PPSMC_MSG_GetAverageGfxclkFrequency 0x34
#define PPSMC_MSG_GetAverageSocclkFrequency 0x35
#define PPSMC_MSG_GetAverageUclkFrequency 0x36
#define PPSMC_MSG_GetAverageGfxActivity 0x37
#define PPSMC_MSG_GetTemperatureEdge 0x38
#define PPSMC_MSG_GetTemperatureHotspot 0x39
#define PPSMC_MSG_GetTemperatureHBM 0x3A
#define PPSMC_MSG_GetTemperatureVrSoc 0x3B
#define PPSMC_MSG_GetTemperatureVrMem 0x3C
#define PPSMC_MSG_GetTemperatureLiquid 0x3D
#define PPSMC_MSG_GetTemperaturePlx 0x3E
#define PPSMC_MSG_OverDriveSetPercentage 0x3F
#define PPSMC_MSG_SetMinDeepSleepDcefclk 0x40
#define PPSMC_MSG_SwitchToAC 0x41
#define PPSMC_MSG_SetUclkFastSwitch 0x42
#define PPSMC_MSG_SetUclkDownHyst 0x43
#define PPSMC_MSG_RemoveDCClamp 0x44
#define PPSMC_MSG_GfxDeviceDriverReset 0x45
#define PPSMC_MSG_GetCurrentRpm 0x46
#define PPSMC_MSG_SetVideoFps 0x47
#define PPSMC_MSG_SetCustomGfxDpmParameters 0x48
#define PPSMC_MSG_SetTjMax 0x49
#define PPSMC_MSG_SetFanTemperatureTarget 0x4A
#define PPSMC_MSG_PrepareMp1ForUnload 0x4B
#define PPSMC_MSG_RequestDisplayClockByFreq 0x4C
#define PPSMC_MSG_GetClockFreqMHz 0x4D
#define PPSMC_MSG_DramLogSetDramAddrHigh 0x4E
#define PPSMC_MSG_DramLogSetDramAddrLow 0x4F
#define PPSMC_MSG_DramLogSetDramSize 0x50
#define PPSMC_MSG_SetFanMaxRpm 0x51
#define PPSMC_MSG_SetFanMinPwm 0x52
#define PPSMC_MSG_ConfigureGfxDidt 0x55
#define PPSMC_MSG_NumOfDisplays 0x56
#define PPSMC_Message_Count 0x57
typedef int PPSMC_Msg;
#pragma pack(pop)
#endif
| null | null | null | null | 99,095 |
68,405 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 68,405 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2017 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef REMOTING_HOST_FILE_TRANSFER_MESSAGE_HANDLER_H_
#define REMOTING_HOST_FILE_TRANSFER_MESSAGE_HANDLER_H_
#include <cstdint>
#include <memory>
#include <string>
#include "remoting/host/file_proxy_wrapper.h"
#include "remoting/proto/file_transfer.pb.h"
#include "remoting/protocol/named_message_pipe_handler.h"
namespace remoting {
constexpr char kFileTransferDataChannelPrefix[] = "filetransfer-";
class FileTransferMessageHandler : public protocol::NamedMessagePipeHandler {
public:
FileTransferMessageHandler(const std::string& name,
std::unique_ptr<protocol::MessagePipe> pipe,
std::unique_ptr<FileProxyWrapper> file_proxy);
~FileTransferMessageHandler() override;
// protocol::NamedMessagePipeHandler implementation.
void OnConnected() override;
void OnIncomingMessage(std::unique_ptr<CompoundBuffer> message) override;
void OnDisconnecting() override;
private:
void StatusCallback(
FileProxyWrapper::State state,
base::Optional<protocol::FileTransferResponse_ErrorCode> error);
void SendToFileProxy(std::unique_ptr<CompoundBuffer> buffer);
void ParseNewRequest(std::unique_ptr<CompoundBuffer> buffer);
void CancelAndSendError(const std::string& error);
std::unique_ptr<FileProxyWrapper> file_proxy_wrapper_;
std::unique_ptr<protocol::FileTransferRequest> request_;
uint64_t total_bytes_written_ = 0;
};
} // namespace remoting
#endif // REMOTING_HOST_FILE_TRANSFER_MESSAGE_HANDLER_H_
| null | null | null | null | 65,268 |
10,154 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 10,154 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2016 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chromecast/browser/cast_media_blocker.h"
#include "base/threading/thread_checker.h"
#include "content/public/browser/media_session.h"
#include "content/public/browser/web_contents.h"
namespace chromecast {
namespace shell {
CastMediaBlocker::CastMediaBlocker(content::MediaSession* media_session)
: content::MediaSessionObserver(media_session),
blocked_(false),
paused_by_user_(true),
suspended_(true),
controllable_(false) {}
CastMediaBlocker::~CastMediaBlocker() {}
void CastMediaBlocker::BlockMediaLoading(bool blocked) {
if (blocked_ == blocked)
return;
blocked_ = blocked;
UpdateMediaBlockedState();
LOG(INFO) << __FUNCTION__ << " blocked=" << blocked_
<< " suspended=" << suspended_ << " controllable=" << controllable_
<< " paused_by_user=" << paused_by_user_;
// If blocking media, suspend if possible.
if (blocked_) {
if (!suspended_ && controllable_) {
Suspend();
}
return;
}
// If unblocking media, resume if media was not paused by user.
if (!paused_by_user_ && suspended_ && controllable_) {
paused_by_user_ = true;
Resume();
}
}
void CastMediaBlocker::MediaSessionStateChanged(bool is_controllable,
bool is_suspended) {
LOG(INFO) << __FUNCTION__ << " blocked=" << blocked_
<< " is_suspended=" << is_suspended
<< " is_controllable=" << is_controllable
<< " paused_by_user=" << paused_by_user_;
// Process controllability first.
if (controllable_ != is_controllable) {
controllable_ = is_controllable;
// If not blocked, and we regain control and the media wasn't paused when
// blocked, resume media if suspended.
if (!blocked_ && !paused_by_user_ && is_suspended && controllable_) {
paused_by_user_ = true;
Resume();
}
// Suspend if blocked and the session becomes controllable.
if (blocked_ && !is_suspended && controllable_) {
// Only suspend if suspended_ doesn't change. Otherwise, this will be
// handled in the suspended changed block.
if (suspended_ == is_suspended)
Suspend();
}
}
// Process suspended state next.
if (suspended_ != is_suspended) {
suspended_ = is_suspended;
// If blocking, suspend media whenever possible.
if (blocked_ && !suspended_) {
// If media was resumed when blocked, the user tried to play music.
paused_by_user_ = false;
if (controllable_)
Suspend();
}
// If not blocking, cache the user's play intent.
if (!blocked_)
paused_by_user_ = suspended_;
}
}
void CastMediaBlocker::Suspend() {
if (!media_session())
return;
LOG(INFO) << "Suspending media session.";
media_session()->Suspend(content::MediaSession::SuspendType::SYSTEM);
}
void CastMediaBlocker::Resume() {
if (!media_session())
return;
LOG(INFO) << "Resuming media session.";
media_session()->Resume(content::MediaSession::SuspendType::SYSTEM);
}
} // namespace shell
} // namespace chromecast
| null | null | null | null | 7,017 |
27,003 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 27,003 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | /* Copyright (c) 2005-2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following disclaimer
* in the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google Inc. nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ---
* Author: Markus Gutschke, Carl Crous
*/
#ifndef _ELFCORE_H
#define _ELFCORE_H
#ifdef __cplusplus
extern "C" {
#endif
/* We currently only support x86-32, x86-64, ARM, and MIPS on Linux.
* Porting to other related platforms should not be difficult.
*/
#if (defined(__i386__) || defined(__x86_64__) || defined(__ARM_ARCH_3__) || \
defined(__mips__)) && defined(__linux)
#include <stdarg.h>
#include <stdint.h>
#include <sys/types.h>
#include <config.h>
/* Define the DUMPER symbol to make sure that there is exactly one
* core dumper built into the library.
*/
#define DUMPER "ELF"
/* By the time that we get a chance to read CPU registers in the
* calling thread, they are already in a not particularly useful
* state. Besides, there will be multiple frames on the stack that are
* just making the core file confusing. To fix this problem, we take a
* snapshot of the frame pointer, stack pointer, and instruction
* pointer at an earlier time, and then insert these values into the
* core file.
*/
#if defined(__i386__) || defined(__x86_64__)
typedef struct i386_regs { /* Normal (non-FPU) CPU registers */
#ifdef __x86_64__
#define BP rbp
#define SP rsp
#define IP rip
uint64_t r15,r14,r13,r12,rbp,rbx,r11,r10;
uint64_t r9,r8,rax,rcx,rdx,rsi,rdi,orig_rax;
uint64_t rip,cs,eflags;
uint64_t rsp,ss;
uint64_t fs_base, gs_base;
uint64_t ds,es,fs,gs;
#else
#define BP ebp
#define SP esp
#define IP eip
uint32_t ebx, ecx, edx, esi, edi, ebp, eax;
uint16_t ds, __ds, es, __es;
uint16_t fs, __fs, gs, __gs;
uint32_t orig_eax, eip;
uint16_t cs, __cs;
uint32_t eflags, esp;
uint16_t ss, __ss;
#endif
} i386_regs;
#elif defined(__ARM_ARCH_3__)
typedef struct arm_regs { /* General purpose registers */
#define BP uregs[11] /* Frame pointer */
#define SP uregs[13] /* Stack pointer */
#define IP uregs[15] /* Program counter */
#define LR uregs[14] /* Link register */
long uregs[18];
} arm_regs;
#elif defined(__mips__)
typedef struct mips_regs {
unsigned long pad[6]; /* Unused padding to match kernel structures */
unsigned long uregs[32]; /* General purpose registers. */
unsigned long hi; /* Used for multiplication and division. */
unsigned long lo;
unsigned long cp0_epc; /* Program counter. */
unsigned long cp0_badvaddr;
unsigned long cp0_status;
unsigned long cp0_cause;
unsigned long unused;
} mips_regs;
#endif
#if defined(__i386__) && defined(__GNUC__)
/* On x86 we provide an optimized version of the FRAME() macro, if the
* compiler supports a GCC-style asm() directive. This results in somewhat
* more accurate values for CPU registers.
*/
typedef struct Frame {
struct i386_regs uregs;
int errno_;
pid_t tid;
} Frame;
#define FRAME(f) Frame f; \
do { \
f.errno_ = errno; \
f.tid = sys_gettid(); \
__asm__ volatile ( \
"push %%ebp\n" \
"push %%ebx\n" \
"mov %%ebx,0(%%eax)\n" \
"mov %%ecx,4(%%eax)\n" \
"mov %%edx,8(%%eax)\n" \
"mov %%esi,12(%%eax)\n" \
"mov %%edi,16(%%eax)\n" \
"mov %%ebp,20(%%eax)\n" \
"mov %%eax,24(%%eax)\n" \
"mov %%ds,%%ebx\n" \
"mov %%ebx,28(%%eax)\n" \
"mov %%es,%%ebx\n" \
"mov %%ebx,32(%%eax)\n" \
"mov %%fs,%%ebx\n" \
"mov %%ebx,36(%%eax)\n" \
"mov %%gs,%%ebx\n" \
"mov %%ebx, 40(%%eax)\n" \
"call 0f\n" \
"0:pop %%ebx\n" \
"add $1f-0b,%%ebx\n" \
"mov %%ebx,48(%%eax)\n" \
"mov %%cs,%%ebx\n" \
"mov %%ebx,52(%%eax)\n" \
"pushf\n" \
"pop %%ebx\n" \
"mov %%ebx,56(%%eax)\n" \
"mov %%esp,%%ebx\n" \
"add $8,%%ebx\n" \
"mov %%ebx,60(%%eax)\n" \
"mov %%ss,%%ebx\n" \
"mov %%ebx,64(%%eax)\n" \
"pop %%ebx\n" \
"pop %%ebp\n" \
"1:" \
: : "a" (&f) : "memory"); \
} while (0)
#define SET_FRAME(f,r) \
do { \
errno = (f).errno_; \
(r) = (f).uregs; \
} while (0)
#elif defined(__x86_64__) && defined(__GNUC__)
/* The FRAME and SET_FRAME macros for x86_64. */
typedef struct Frame {
struct i386_regs uregs;
int errno_;
pid_t tid;
} Frame;
#define FRAME(f) Frame f; \
do { \
f.errno_ = errno; \
f.tid = sys_gettid(); \
__asm__ volatile ( \
"push %%rbp\n" \
"push %%rbx\n" \
"mov %%r15,0(%%rax)\n" \
"mov %%r14,8(%%rax)\n" \
"mov %%r13,16(%%rax)\n" \
"mov %%r12,24(%%rax)\n" \
"mov %%rbp,32(%%rax)\n" \
"mov %%rbx,40(%%rax)\n" \
"mov %%r11,48(%%rax)\n" \
"mov %%r10,56(%%rax)\n" \
"mov %%r9,64(%%rax)\n" \
"mov %%r8,72(%%rax)\n" \
"mov %%rax,80(%%rax)\n" \
"mov %%rcx,88(%%rax)\n" \
"mov %%rdx,96(%%rax)\n" \
"mov %%rsi,104(%%rax)\n" \
"mov %%rdi,112(%%rax)\n" \
"mov %%ds,%%rbx\n" \
"mov %%rbx,184(%%rax)\n" \
"mov %%es,%%rbx\n" \
"mov %%rbx,192(%%rax)\n" \
"mov %%fs,%%rbx\n" \
"mov %%rbx,200(%%rax)\n" \
"mov %%gs,%%rbx\n" \
"mov %%rbx,208(%%rax)\n" \
"call 0f\n" \
"0:pop %%rbx\n" \
"add $1f-0b,%%rbx\n" \
"mov %%rbx,128(%%rax)\n" \
"mov %%cs,%%rbx\n" \
"mov %%rbx,136(%%rax)\n" \
"pushf\n" \
"pop %%rbx\n" \
"mov %%rbx,144(%%rax)\n" \
"mov %%rsp,%%rbx\n" \
"add $16,%%ebx\n" \
"mov %%rbx,152(%%rax)\n" \
"mov %%ss,%%rbx\n" \
"mov %%rbx,160(%%rax)\n" \
"pop %%rbx\n" \
"pop %%rbp\n" \
"1:" \
: : "a" (&f) : "memory"); \
} while (0)
#define SET_FRAME(f,r) \
do { \
errno = (f).errno_; \
(f).uregs.fs_base = (r).fs_base; \
(f).uregs.gs_base = (r).gs_base; \
(r) = (f).uregs; \
} while (0)
#elif defined(__ARM_ARCH_3__) && defined(__GNUC__)
/* ARM calling conventions are a little more tricky. A little assembly
* helps in obtaining an accurate snapshot of all registers.
*/
typedef struct Frame {
struct arm_regs arm;
int errno_;
pid_t tid;
} Frame;
#define FRAME(f) Frame f; \
do { \
long cpsr; \
f.errno_ = errno; \
f.tid = sys_gettid(); \
__asm__ volatile( \
"stmia %0, {r0-r15}\n" /* All integer regs */\
: : "r"(&f.arm) : "memory"); \
f.arm.uregs[16] = 0; \
__asm__ volatile( \
"mrs %0, cpsr\n" /* Condition code reg */\
: "=r"(cpsr)); \
f.arm.uregs[17] = cpsr; \
} while (0)
#define SET_FRAME(f,r) \
do { \
/* Don't override the FPU status register. */\
/* Use the value obtained from ptrace(). This*/\
/* works, because our code does not perform */\
/* any FPU operations, itself. */\
long fps = (f).arm.uregs[16]; \
errno = (f).errno_; \
(r) = (f).arm; \
(r).uregs[16] = fps; \
} while (0)
#elif defined(__mips__) && defined(__GNUC__)
typedef struct Frame {
struct mips_regs mips_regs;
int errno_;
pid_t tid;
} Frame;
#define MIPSREG(n) ({ register unsigned long r __asm__("$"#n); r; })
#define FRAME(f) Frame f = { 0 }; \
do { \
unsigned long hi, lo; \
register unsigned long pc __asm__("$31"); \
f.mips_regs.uregs[ 0] = MIPSREG( 0); \
f.mips_regs.uregs[ 1] = MIPSREG( 1); \
f.mips_regs.uregs[ 2] = MIPSREG( 2); \
f.mips_regs.uregs[ 3] = MIPSREG( 3); \
f.mips_regs.uregs[ 4] = MIPSREG( 4); \
f.mips_regs.uregs[ 5] = MIPSREG( 5); \
f.mips_regs.uregs[ 6] = MIPSREG( 6); \
f.mips_regs.uregs[ 7] = MIPSREG( 7); \
f.mips_regs.uregs[ 8] = MIPSREG( 8); \
f.mips_regs.uregs[ 9] = MIPSREG( 9); \
f.mips_regs.uregs[10] = MIPSREG(10); \
f.mips_regs.uregs[11] = MIPSREG(11); \
f.mips_regs.uregs[12] = MIPSREG(12); \
f.mips_regs.uregs[13] = MIPSREG(13); \
f.mips_regs.uregs[14] = MIPSREG(14); \
f.mips_regs.uregs[15] = MIPSREG(15); \
f.mips_regs.uregs[16] = MIPSREG(16); \
f.mips_regs.uregs[17] = MIPSREG(17); \
f.mips_regs.uregs[18] = MIPSREG(18); \
f.mips_regs.uregs[19] = MIPSREG(19); \
f.mips_regs.uregs[20] = MIPSREG(20); \
f.mips_regs.uregs[21] = MIPSREG(21); \
f.mips_regs.uregs[22] = MIPSREG(22); \
f.mips_regs.uregs[23] = MIPSREG(23); \
f.mips_regs.uregs[24] = MIPSREG(24); \
f.mips_regs.uregs[25] = MIPSREG(25); \
f.mips_regs.uregs[26] = MIPSREG(26); \
f.mips_regs.uregs[27] = MIPSREG(27); \
f.mips_regs.uregs[28] = MIPSREG(28); \
f.mips_regs.uregs[29] = MIPSREG(29); \
f.mips_regs.uregs[30] = MIPSREG(30); \
f.mips_regs.uregs[31] = MIPSREG(31); \
__asm__ volatile ("mfhi %0" : "=r"(hi)); \
__asm__ volatile ("mflo %0" : "=r"(lo)); \
__asm__ volatile ("jal 1f; 1:nop" : "=r"(pc)); \
f.mips_regs.hi = hi; \
f.mips_regs.lo = lo; \
f.mips_regs.cp0_epc = pc; \
f.errno_ = errno; \
f.tid = sys_gettid(); \
} while (0)
#define SET_FRAME(f,r) \
do { \
errno = (f).errno_; \
memcpy((r).uregs, (f).mips_regs.uregs, \
32*sizeof(unsigned long)); \
(r).hi = (f).mips_regs.hi; \
(r).lo = (f).mips_regs.lo; \
(r).cp0_epc = (f).mips_regs.cp0_epc; \
} while (0)
#else
/* If we do not have a hand-optimized assembly version of the FRAME()
* macro, we cannot reliably unroll the stack. So, we show a few additional
* stack frames for the coredumper.
*/
typedef struct Frame {
pid_t tid;
} Frame;
#define FRAME(f) Frame f; do { f.tid = sys_gettid(); } while (0)
#define SET_FRAME(f,r) do { } while (0)
#endif
/* Internal function for generating a core file. This API can change without
* notice and is only supposed to be used internally by the core dumper.
*
* This function works for both single- and multi-threaded core
* dumps. If called as
*
* FRAME(frame);
* InternalGetCoreDump(&frame, 0, NULL, ap);
*
* it creates a core file that only contains information about the
* calling thread.
*
* Optionally, the caller can provide information about other threads
* by passing their process ids in "thread_pids". The process id of
* the caller should not be included in this array. All of the threads
* must have been attached to with ptrace(), prior to calling this
* function. They will be detached when "InternalGetCoreDump()" returns.
*
* This function either returns a file handle that can be read for obtaining
* a core dump, or "-1" in case of an error. In the latter case, "errno"
* will be set appropriately.
*
* While "InternalGetCoreDump()" is not technically async signal safe, you
* might be tempted to invoke it from a signal handler. The code goes to
* great lengths to make a best effort that this will actually work. But in
* any case, you must make sure that you preserve the value of "errno"
* yourself. It is guaranteed to be clobbered otherwise.
*
* Also, "InternalGetCoreDump" is not strictly speaking re-entrant. Again,
* it makes a best effort to behave reasonably when called in a multi-
* threaded environment, but it is ultimately the caller's responsibility
* to provide locking.
*/
int InternalGetCoreDump(void *frame, int num_threads, pid_t *thread_pids,
va_list ap
/* const struct CoreDumpParameters *params,
const char *file_name,
const char *PATH
*/);
#endif
#ifdef __cplusplus
}
#endif
#endif /* _ELFCORE_H */
| null | null | null | null | 23,866 |
41,717 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 41,717 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2013 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include <iterator>
#include <map>
#include <string>
#include "scoped_refptr.h"
struct Foo {
int dummy;
};
typedef std::map<std::string, scoped_refptr<const Foo>> MyMap;
class MyIter
: public std::iterator<std::input_iterator_tag, scoped_refptr<const Foo>> {
public:
MyIter() {}
MyIter(const MyIter& other) : it_(other.it_) {}
explicit MyIter(MyMap::const_iterator it) : it_(it) {}
MyIter& operator++() {
++it_;
return *this;
}
const scoped_refptr<const Foo> operator*() { return it_->second; }
bool operator!=(const MyIter& other) { return it_ != other.it_; }
bool operator==(const MyIter& other) { return it_ == other.it_; }
private:
MyMap::const_iterator it_;
};
void TestsAScopedRefptr() {
MyMap map;
map["foo"] = new Foo;
map["bar"] = new Foo;
MyIter my_begin(map.begin());
MyIter my_end(map.end());
for (MyIter it = my_begin; it != my_end; ++it) {
const Foo* item = NULL;
if (*it)
item = *it;
}
}
| null | null | null | null | 38,580 |
29,184 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 29,184 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef THIRD_PARTY_LIBADDRESSINPUT_CHROMIUM_CHROME_ADDRESS_VALIDATOR_H_
#define THIRD_PARTY_LIBADDRESSINPUT_CHROMIUM_CHROME_ADDRESS_VALIDATOR_H_
#include <stddef.h>
#include <map>
#include <memory>
#include <string>
#include <utility>
#include <vector>
#include "base/macros.h"
#include "base/memory/weak_ptr.h"
#include "base/time/time.h"
#include "third_party/libaddressinput/src/cpp/include/libaddressinput/address_field.h"
#include "third_party/libaddressinput/src/cpp/include/libaddressinput/address_validator.h"
#include "third_party/libaddressinput/src/cpp/include/libaddressinput/callback.h"
#include "third_party/libaddressinput/src/cpp/include/libaddressinput/preload_supplier.h"
namespace i18n {
namespace addressinput {
class AddressNormalizer;
class Source;
class Storage;
struct AddressData;
}
}
namespace autofill {
class InputSuggester;
// The object to be notified when loading of address validation rules is
// finished.
class LoadRulesListener {
public:
virtual ~LoadRulesListener() {}
// Called when the validation rules for the |region_code| have been loaded.
// The validation rules include the generic rules for the |region_code| and
// specific rules for the country's administrative areas, localities, and
// dependent localities. If a country has language-specific validation rules,
// then these are also loaded.
//
// The |success| parameter is true when the rules were loaded successfully.
virtual void OnAddressValidationRulesLoaded(const std::string& region_code,
bool success) = 0;
};
// Interface to the libaddressinput AddressValidator for Chromium Autofill. The
// class is named AddressValidator to simplify switching between libaddressinput
// and this version.
//
// It's not possible to name this file address_validator.h because some
// compilers do not handle multiple files with the same name (although in
// different directories) gracefully. This class is a shim between upstream
// libaddressinput API and the API that Chrome expects, hence the file name
// chrome_address_validator.h.
class AddressValidator {
public:
// The status of address validation.
enum Status {
// Address validation completed successfully. Check |problems| to see if any
// problems were found.
SUCCESS,
// The validation rules are not available, because LoadRules() was not
// called or failed. Reload the rules.
RULES_UNAVAILABLE,
// The validation rules are being loaded. Try again later.
RULES_NOT_READY
};
// Takes ownership of |source| and |storage|.
AddressValidator(std::unique_ptr<::i18n::addressinput::Source> source,
std::unique_ptr<::i18n::addressinput::Storage> storage,
LoadRulesListener* load_rules_listener);
virtual ~AddressValidator();
// Loads the generic validation rules for |region_code| and specific rules
// for the region's administrative areas, localities, and dependent
// localities. A typical data size is 10KB. The largest is 250KB. If a region
// has language-specific validation rules, then these are also loaded.
//
// Example rule:
// https://i18napis.appspot.com/ssl-aggregate-address/data/US
//
// If the rules are already in progress of being loaded, it does nothing.
// Invokes |load_rules_listener| when the loading has finished.
virtual void LoadRules(const std::string& region_code);
// Returns the list of sub-regions (recorded as sub-keys) of the region
// (recorded as rule) indicated by |region_code|, while the device language
// is set to |language|. So, if the |region_code| is
// a country code, sub-region means the country's admin area.
// This function should be called when the rules are loaded.
virtual std::vector<std::pair<std::string, std::string>> GetRegionSubKeys(
const std::string& region_code,
const std::string& language);
// Validates the |address| and populates |problems| with the validation
// problems, filtered according to the |filter| parameter.
//
// If the |filter| is empty, then all discovered validation problems are
// returned. If the |filter| contains problem elements, then only the problems
// in the |filter| may be returned.
virtual Status ValidateAddress(
const ::i18n::addressinput::AddressData& address,
const ::i18n::addressinput::FieldProblemMap* filter,
::i18n::addressinput::FieldProblemMap* problems) const;
// Fills in |suggestions| for the partially typed in |user_input|, assuming
// the user is typing in the |focused_field|. If the number of |suggestions|
// is over the |suggestion_limit|, then returns no |suggestions| at all.
//
// If the |solutions| parameter is NULL, the checks whether the validation
// rules are available, but does not fill in suggestions.
//
// Sample user input 1:
// country code = "US"
// postal code = "90066"
// focused field = POSTAL_CODE
// suggestions limit = 1
// Suggestion:
// [{administrative_area: "CA"}]
//
// Sample user input 2:
// country code = "CN"
// dependent locality = "Zongyang"
// focused field = DEPENDENT_LOCALITY
// suggestions limit = 10
// Suggestion:
// [{dependent_locality: "Zongyang Xian",
// locality: "Anqing Shi",
// administrative_area: "Anhui Sheng"}]
virtual Status GetSuggestions(
const ::i18n::addressinput::AddressData& user_input,
::i18n::addressinput::AddressField focused_field,
size_t suggestion_limit,
std::vector< ::i18n::addressinput::AddressData>* suggestions) const;
// Normalizes the |address_data|. For example, "texas" changes to "TX".
// Returns true on success, otherwise leaves |address_data| alone and returns
// false.
virtual bool NormalizeAddress(
::i18n::addressinput::AddressData* address) const;
// Returns whether the rules associated with the |region_code| are loaded.
virtual bool AreRulesLoadedForRegion(const std::string& region_code);
protected:
// Constructor used only for MockAddressValidator.
AddressValidator();
// Returns the period of time to wait between the first attempt's failure and
// the second attempt's initiation to load rules. Exposed for testing.
virtual base::TimeDelta GetBaseRetryPeriod() const;
private:
// Verifies that |validator_| succeeded. Invoked by |validated_| callback.
void Validated(bool success,
const ::i18n::addressinput::AddressData&,
const ::i18n::addressinput::FieldProblemMap&);
// Invokes the |load_rules_listener_|, if it's not NULL. Called by
// |rules_loaded_| callback.
void RulesLoaded(bool success, const std::string& region_code, int);
// Retries loading rules without resetting the retry counter.
void RetryLoadRules(const std::string& region_code);
// Loads and stores aggregate rules at COUNTRY level.
const std::unique_ptr<::i18n::addressinput::PreloadSupplier> supplier_;
// Suggests addresses based on user input.
const std::unique_ptr<InputSuggester> input_suggester_;
// Normalizes addresses into a canonical form.
const std::unique_ptr<::i18n::addressinput::AddressNormalizer> normalizer_;
// Validates addresses.
const std::unique_ptr<const ::i18n::addressinput::AddressValidator>
validator_;
// The callback that |validator_| invokes when it finished validating an
// address.
const std::unique_ptr<const ::i18n::addressinput::AddressValidator::Callback>
validated_;
// The callback that |supplier_| invokes when it finished loading rules.
const std::unique_ptr<const ::i18n::addressinput::PreloadSupplier::Callback>
rules_loaded_;
// Not owned delegate to invoke when |suppler_| finished loading rules. Can be
// NULL.
LoadRulesListener* const load_rules_listener_;
// A mapping of region codes to the number of attempts to retry loading rules.
std::map<std::string, int> attempts_number_;
// Member variables should appear before the WeakPtrFactory, to ensure that
// any WeakPtrs to AddressValidator are invalidated before its members
// variable's destructors are executed, rendering them invalid.
base::WeakPtrFactory<AddressValidator> weak_factory_;
DISALLOW_COPY_AND_ASSIGN(AddressValidator);
};
} // namespace autofill
#endif // THIRD_PARTY_LIBADDRESSINPUT_CHROMIUM_CHROME_ADDRESS_VALIDATOR_H_
| null | null | null | null | 26,047 |
14,778 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 179,773 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Copyright 2004-2007 Analog Devices Inc.
* 2005 National ICT Australia (NICTA)
* Aidan Williams <aidan@nicta.com.au>
*
* Thanks to Jamey Hicks.
*
* Only SMSC91C1111 was registered, may do more later.
*
* Licensed under the GPL-2
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
const char bfin_board_name[] = "Tepla-BF561";
/*
* Driver needs to know address, irq and flag pin.
*/
static struct resource smc91x_resources[] = {
{
.start = 0x2C000300,
.end = 0x2C000320,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PROG_INTB,
.end = IRQ_PROG_INTB,
.flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
}, {
.start = IRQ_PF7,
.end = IRQ_PF7,
.flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
#ifdef CONFIG_SERIAL_BFIN_UART0
static struct resource bfin_uart0_resources[] = {
{
.start = BFIN_UART_THR,
.end = BFIN_UART_GCTL+2,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_UART_TX,
.end = IRQ_UART_TX,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_UART_RX,
.end = IRQ_UART_RX,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_UART_ERROR,
.end = IRQ_UART_ERROR,
.flags = IORESOURCE_IRQ,
},
{
.start = CH_UART_TX,
.end = CH_UART_TX,
.flags = IORESOURCE_DMA,
},
{
.start = CH_UART_RX,
.end = CH_UART_RX,
.flags = IORESOURCE_DMA,
},
};
static unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
static struct platform_device bfin_uart0_device = {
.name = "bfin-uart",
.id = 0,
.num_resources = ARRAY_SIZE(bfin_uart0_resources),
.resource = bfin_uart0_resources,
.dev = {
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
},
};
#endif
#endif
#if IS_ENABLED(CONFIG_BFIN_SIR)
#ifdef CONFIG_BFIN_SIR0
static struct resource bfin_sir0_resources[] = {
{
.start = 0xFFC00400,
.end = 0xFFC004FF,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_UART0_RX,
.end = IRQ_UART0_RX+1,
.flags = IORESOURCE_IRQ,
},
{
.start = CH_UART0_RX,
.end = CH_UART0_RX+1,
.flags = IORESOURCE_DMA,
},
};
static struct platform_device bfin_sir0_device = {
.name = "bfin_sir",
.id = 0,
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
.resource = bfin_sir0_resources,
};
#endif
#endif
static struct platform_device *tepla_devices[] __initdata = {
&smc91x_device,
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
#ifdef CONFIG_SERIAL_BFIN_UART0
&bfin_uart0_device,
#endif
#endif
#if IS_ENABLED(CONFIG_BFIN_SIR)
#ifdef CONFIG_BFIN_SIR0
&bfin_sir0_device,
#endif
#endif
};
static int __init tepla_init(void)
{
printk(KERN_INFO "%s(): registering device resources\n", __func__);
return platform_add_devices(tepla_devices, ARRAY_SIZE(tepla_devices));
}
arch_initcall(tepla_init);
static struct platform_device *tepla_early_devices[] __initdata = {
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
#ifdef CONFIG_SERIAL_BFIN_UART0
&bfin_uart0_device,
#endif
#endif
};
void __init native_machine_early_platform_add_devices(void)
{
printk(KERN_INFO "register early platform devices\n");
early_platform_add_devices(tepla_early_devices,
ARRAY_SIZE(tepla_early_devices));
}
| null | null | null | null | 88,120 |
355 | null | train_val | a6802e21d824e786d1e2a8440cf749a6e1a8d95f | 160,483 | ImageMagick | 0 | https://github.com/ImageMagick/ImageMagick | 2017-07-18 18:28:29-04:00 | /*
Copyright 1999-2017 ImageMagick Studio LLC, a non-profit organization
dedicated to making software imaging solutions freely available.
You may not use this file except in compliance with the License.
obtain a copy of the License at
https://www.imagemagick.org/script/license.php
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
MagickCore image constitute methods.
*/
#ifndef MAGICKCORE_CONSTITUTE_H
#define MAGICKCORE_CONSTITUTE_H
#include "MagickCore/pixel.h"
#if defined(__cplusplus) || defined(c_plusplus)
extern "C" {
#endif
extern MagickExport Image
*ConstituteImage(const size_t,const size_t,const char *,const StorageType,
const void *,ExceptionInfo *),
*PingImage(const ImageInfo *,ExceptionInfo *),
*PingImages(ImageInfo *,const char *,ExceptionInfo *),
*ReadImage(const ImageInfo *,ExceptionInfo *),
*ReadImages(ImageInfo *,const char *,ExceptionInfo *),
*ReadInlineImage(const ImageInfo *,const char *,ExceptionInfo *);
extern MagickExport MagickBooleanType
WriteImage(const ImageInfo *,Image *,ExceptionInfo *),
WriteImages(const ImageInfo *,Image *,const char *,ExceptionInfo *);
#if defined(__cplusplus) || defined(c_plusplus)
}
#endif
#endif
| null | null | null | null | 72,776 |
28,751 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 193,746 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/random.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/sys_soc.h>
#include <asm/cputype.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
#include <asm/mach/map.h>
/**
* struct dbx500_asic_id - fields of the ASIC ID
* @process: the manufacturing process, 0x40 is 40 nm 0x00 is "standard"
* @partnumber: hithereto 0x8500 for DB8500
* @revision: version code in the series
*/
struct dbx500_asic_id {
u16 partnumber;
u8 revision;
u8 process;
};
static struct dbx500_asic_id dbx500_id;
static unsigned int __init ux500_read_asicid(phys_addr_t addr)
{
void __iomem *virt = ioremap(addr, 4);
unsigned int asicid;
if (!virt)
return 0;
asicid = readl(virt);
iounmap(virt);
return asicid;
}
static void ux500_print_soc_info(unsigned int asicid)
{
unsigned int rev = dbx500_id.revision;
pr_info("DB%4x ", dbx500_id.partnumber);
if (rev == 0x01)
pr_cont("Early Drop");
else if (rev >= 0xA0)
pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf);
else
pr_cont("Unknown");
pr_cont(" [%#010x]\n", asicid);
}
static unsigned int partnumber(unsigned int asicid)
{
return (asicid >> 8) & 0xffff;
}
/*
* SOC MIDR ASICID ADDRESS ASICID VALUE
* DB8500ed 0x410fc090 0x9001FFF4 0x00850001
* DB8500v1 0x411fc091 0x9001FFF4 0x008500A0
* DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1
* DB8500v2 0x412fc091 0x9001DBF4 0x008500B0
* DB8520v2.2 0x412fc091 0x9001DBF4 0x008500B2
* DB5500v1 0x412fc091 0x9001FFF4 0x005500A0
* DB9540 0x413fc090 0xFFFFDBF4 0x009540xx
*/
static void __init ux500_setup_id(void)
{
unsigned int cpuid = read_cpuid_id();
unsigned int asicid = 0;
phys_addr_t addr = 0;
switch (cpuid) {
case 0x410fc090: /* DB8500ed */
case 0x411fc091: /* DB8500v1 */
addr = 0x9001FFF4;
break;
case 0x412fc091: /* DB8520 / DB8500v2 / DB5500v1 */
asicid = ux500_read_asicid(0x9001DBF4);
if (partnumber(asicid) == 0x8500 ||
partnumber(asicid) == 0x8520)
/* DB8500v2 */
break;
/* DB5500v1 */
addr = 0x9001FFF4;
break;
case 0x413fc090: /* DB9540 */
addr = 0xFFFFDBF4;
break;
}
if (addr)
asicid = ux500_read_asicid(addr);
if (!asicid) {
pr_err("Unable to identify SoC\n");
BUG();
}
dbx500_id.process = asicid >> 24;
dbx500_id.partnumber = partnumber(asicid);
dbx500_id.revision = asicid & 0xff;
ux500_print_soc_info(asicid);
}
static const char * __init ux500_get_machine(void)
{
return kasprintf(GFP_KERNEL, "DB%4x", dbx500_id.partnumber);
}
static const char * __init ux500_get_family(void)
{
return kasprintf(GFP_KERNEL, "ux500");
}
static const char * __init ux500_get_revision(void)
{
unsigned int rev = dbx500_id.revision;
if (rev == 0x01)
return kasprintf(GFP_KERNEL, "%s", "ED");
else if (rev >= 0xA0)
return kasprintf(GFP_KERNEL, "%d.%d",
(rev >> 4) - 0xA + 1, rev & 0xf);
return kasprintf(GFP_KERNEL, "%s", "Unknown");
}
static ssize_t ux500_get_process(struct device *dev,
struct device_attribute *attr,
char *buf)
{
if (dbx500_id.process == 0x00)
return sprintf(buf, "Standard\n");
return sprintf(buf, "%02xnm\n", dbx500_id.process);
}
static const char *db8500_read_soc_id(struct device_node *backupram)
{
void __iomem *base;
void __iomem *uid;
const char *retstr;
base = of_iomap(backupram, 0);
if (!base)
return NULL;
uid = base + 0x1fc0;
/* Throw these device-specific numbers into the entropy pool */
add_device_randomness(uid, 0x14);
retstr = kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
readl((u32 *)uid+0),
readl((u32 *)uid+1), readl((u32 *)uid+2),
readl((u32 *)uid+3), readl((u32 *)uid+4));
iounmap(base);
return retstr;
}
static void __init soc_info_populate(struct soc_device_attribute *soc_dev_attr,
struct device_node *backupram)
{
soc_dev_attr->soc_id = db8500_read_soc_id(backupram);
soc_dev_attr->machine = ux500_get_machine();
soc_dev_attr->family = ux500_get_family();
soc_dev_attr->revision = ux500_get_revision();
}
static const struct device_attribute ux500_soc_attr =
__ATTR(process, S_IRUGO, ux500_get_process, NULL);
static int __init ux500_soc_device_init(void)
{
struct device *parent;
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
struct device_node *backupram;
backupram = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
if (!backupram)
return 0;
ux500_setup_id();
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return -ENOMEM;
soc_info_populate(soc_dev_attr, backupram);
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr);
return PTR_ERR(soc_dev);
}
parent = soc_device_to_device(soc_dev);
device_create_file(parent, &ux500_soc_attr);
return 0;
}
subsys_initcall(ux500_soc_device_init);
| null | null | null | null | 102,093 |
133 | null | train_val | 31e986bc171719c9e6d40d0c2cb1501796a69e6c | 259,088 | php-src | 0 | https://github.com/php/php-src | 2016-10-24 10:37:20+01:00 | /*
+----------------------------------------------------------------------+
| PHP Version 7 |
+----------------------------------------------------------------------+
| Copyright (c) 1997-2016 The PHP Group |
+----------------------------------------------------------------------+
| This source file is subject to version 3.01 of the PHP license, |
| that is bundled with this package in the file LICENSE, and is |
| available through the world-wide-web at the following url: |
| http://www.php.net/license/3_01.txt |
| If you did not receive a copy of the PHP license and are unable to |
| obtain it through the world-wide-web, please send a note to |
| license@php.net so we can mail you a copy immediately. |
+----------------------------------------------------------------------+
| Authors: Felipe Pena <felipe@php.net> |
| Authors: Joe Watkins <joe.watkins@live.co.uk> |
| Authors: Bob Weinand <bwoebi@php.net> |
+----------------------------------------------------------------------+
*/
#include "phpdbg.h"
#include "phpdbg_cmd.h"
#include "phpdbg_set.h"
#include "phpdbg_utils.h"
#include "phpdbg_bp.h"
#include "phpdbg_prompt.h"
ZEND_EXTERN_MODULE_GLOBALS(phpdbg)
#define PHPDBG_SET_COMMAND_D(f, h, a, m, l, s, flags) \
PHPDBG_COMMAND_D_EXP(f, h, a, m, l, s, &phpdbg_prompt_commands[17], flags)
const phpdbg_command_t phpdbg_set_commands[] = {
PHPDBG_SET_COMMAND_D(prompt, "usage: set prompt [<string>]", 'p', set_prompt, NULL, "|s", 0),
PHPDBG_SET_COMMAND_D(pagination, "usage: set pagination [<on|off>]", 'P', set_pagination, NULL, "|b", PHPDBG_ASYNC_SAFE),
#ifndef _WIN32
PHPDBG_SET_COMMAND_D(color, "usage: set color <element> <color>", 'c', set_color, NULL, "ss", PHPDBG_ASYNC_SAFE),
PHPDBG_SET_COMMAND_D(colors, "usage: set colors [<on|off>]", 'C', set_colors, NULL, "|b", PHPDBG_ASYNC_SAFE),
#endif
PHPDBG_SET_COMMAND_D(oplog, "usage: set oplog [<output>]", 'O', set_oplog, NULL, "|s", 0),
PHPDBG_SET_COMMAND_D(break, "usage: set break id [<on|off>]", 'b', set_break, NULL, "l|b", PHPDBG_ASYNC_SAFE),
PHPDBG_SET_COMMAND_D(breaks, "usage: set breaks [<on|off>]", 'B', set_breaks, NULL, "|b", PHPDBG_ASYNC_SAFE),
PHPDBG_SET_COMMAND_D(quiet, "usage: set quiet [<on|off>]", 'q', set_quiet, NULL, "|b", PHPDBG_ASYNC_SAFE),
PHPDBG_SET_COMMAND_D(stepping, "usage: set stepping [<line|op>]", 's', set_stepping, NULL, "|s", PHPDBG_ASYNC_SAFE),
PHPDBG_SET_COMMAND_D(refcount, "usage: set refcount [<on|off>]", 'r', set_refcount, NULL, "|b", PHPDBG_ASYNC_SAFE),
PHPDBG_SET_COMMAND_D(lines, "usage: set lines [<number>]", 'l', set_lines, NULL, "|l", PHPDBG_ASYNC_SAFE),
PHPDBG_END_COMMAND
};
PHPDBG_SET(prompt) /* {{{ */
{
if (!param || param->type == EMPTY_PARAM) {
phpdbg_writeln("setprompt", "str=\"%s\"", "Current prompt: %s", phpdbg_get_prompt());
} else {
phpdbg_set_prompt(param->str);
}
return SUCCESS;
} /* }}} */
PHPDBG_SET(pagination) /* {{{ */
{
if (!param || param->type == EMPTY_PARAM) {
phpdbg_writeln("setpagination", "active=\"%s\"", "Pagination %s", PHPDBG_G(flags) & PHPDBG_HAS_PAGINATION ? "on" : "off");
} else switch (param->type) {
case NUMERIC_PARAM: {
if (param->num) {
PHPDBG_G(flags) |= PHPDBG_HAS_PAGINATION;
} else {
PHPDBG_G(flags) &= ~PHPDBG_HAS_PAGINATION;
}
} break;
default:
phpdbg_error("setpagination", "type=\"wrongargs\"", "set pagination used incorrectly: set pagination <on|off>");
}
return SUCCESS;
} /* }}} */
PHPDBG_SET(lines) /* {{{ */
{
if (!param || param->type == EMPTY_PARAM) {
phpdbg_writeln("setlines", "active=\"%s\"", "Lines %ld", PHPDBG_G(lines));
} else switch (param->type) {
case NUMERIC_PARAM: {
PHPDBG_G(lines) = param->num;
} break;
default:
phpdbg_error("setlines", "type=\"wrongargs\"", "set lines used incorrectly: set lines <number>");
}
return SUCCESS;
} /* }}} */
PHPDBG_SET(break) /* {{{ */
{
switch (param->type) {
case NUMERIC_PARAM: {
if (param->next) {
if (param->next->num) {
phpdbg_enable_breakpoint(param->num);
} else {
phpdbg_disable_breakpoint(param->num);
}
} else {
phpdbg_breakbase_t *brake = phpdbg_find_breakbase(param->num);
if (brake) {
phpdbg_writeln("setbreak", "id=\"%ld\" active=\"%s\"", "Breakpoint #%ld %s", param->num, brake->disabled ? "off" : "on");
} else {
phpdbg_error("setbreak", "type=\"nobreak\" id=\"%ld\"", "Failed to find breakpoint #%ld", param->num);
}
}
} break;
default:
phpdbg_error("setbreak", "type=\"wrongargs\"", "set break used incorrectly: set break [id] <on|off>");
}
return SUCCESS;
} /* }}} */
PHPDBG_SET(breaks) /* {{{ */
{
if (!param || param->type == EMPTY_PARAM) {
phpdbg_writeln("setbreaks", "active=\"%s\"", "Breakpoints %s",PHPDBG_G(flags) & PHPDBG_IS_BP_ENABLED ? "on" : "off");
} else switch (param->type) {
case NUMERIC_PARAM: {
if (param->num) {
phpdbg_enable_breakpoints();
} else {
phpdbg_disable_breakpoints();
}
} break;
default:
phpdbg_error("setbreaks", "type=\"wrongargs\"", "set breaks used incorrectly: set breaks <on|off>");
}
return SUCCESS;
} /* }}} */
#ifndef _WIN32
PHPDBG_SET(color) /* {{{ */
{
const phpdbg_color_t *color = phpdbg_get_color(param->next->str, param->next->len);
if (!color) {
phpdbg_error("setcolor", "type=\"nocolor\"", "Failed to find the requested color (%s)", param->next->str);
return SUCCESS;
}
switch (phpdbg_get_element(param->str, param->len)) {
case PHPDBG_COLOR_PROMPT:
phpdbg_notice("setcolor", "type=\"prompt\" color=\"%s\" code=\"%s\"", "setting prompt color to %s (%s)", color->name, color->code);
if (PHPDBG_G(prompt)[1]) {
free(PHPDBG_G(prompt)[1]);
PHPDBG_G(prompt)[1]=NULL;
}
phpdbg_set_color(PHPDBG_COLOR_PROMPT, color);
break;
case PHPDBG_COLOR_ERROR:
phpdbg_notice("setcolor", "type=\"error\" color=\"%s\" code=\"%s\"", "setting error color to %s (%s)", color->name, color->code);
phpdbg_set_color(PHPDBG_COLOR_ERROR, color);
break;
case PHPDBG_COLOR_NOTICE:
phpdbg_notice("setcolor", "type=\"notice\" color=\"%s\" code=\"%s\"", "setting notice color to %s (%s)", color->name, color->code);
phpdbg_set_color(PHPDBG_COLOR_NOTICE, color);
break;
default:
phpdbg_error("setcolor", "type=\"invalidtype\"", "Failed to find the requested element (%s)", param->str);
}
return SUCCESS;
} /* }}} */
PHPDBG_SET(colors) /* {{{ */
{
if (!param || param->type == EMPTY_PARAM) {
phpdbg_writeln("setcolors", "active=\"%s\"", "Colors %s", PHPDBG_G(flags) & PHPDBG_IS_COLOURED ? "on" : "off");
} else switch (param->type) {
case NUMERIC_PARAM: {
if (param->num) {
PHPDBG_G(flags) |= PHPDBG_IS_COLOURED;
} else {
PHPDBG_G(flags) &= ~PHPDBG_IS_COLOURED;
}
} break;
default:
phpdbg_error("setcolors", "type=\"wrongargs\"", "set colors used incorrectly: set colors <on|off>");
}
return SUCCESS;
} /* }}} */
#endif
PHPDBG_SET(oplog) /* {{{ */
{
if (!param || param->type == EMPTY_PARAM) {
phpdbg_notice("setoplog", "active=\"%s\"", "Oplog %s", PHPDBG_G(oplog) ? "on" : "off");
} else switch (param->type) {
case STR_PARAM: {
/* open oplog */
FILE *old = PHPDBG_G(oplog);
PHPDBG_G(oplog) = fopen(param->str, "w+");
if (!PHPDBG_G(oplog)) {
phpdbg_error("setoplog", "type=\"openfailure\" file=\"%s\"", "Failed to open %s for oplog", param->str);
PHPDBG_G(oplog) = old;
} else {
if (old) {
phpdbg_notice("setoplog", "type=\"closingold\"", "Closing previously open oplog");
fclose(old);
}
phpdbg_notice("setoplog", "file=\"%s\"", "Successfully opened oplog %s", param->str);
}
} break;
phpdbg_default_switch_case();
}
return SUCCESS;
} /* }}} */
PHPDBG_SET(quiet) /* {{{ */
{
if (!param || param->type == EMPTY_PARAM) {
phpdbg_writeln("setquiet", "active=\"%s\"", "Quietness %s", PHPDBG_G(flags) & PHPDBG_IS_QUIET ? "on" : "off");
} else switch (param->type) {
case NUMERIC_PARAM: {
if (param->num) {
PHPDBG_G(flags) |= PHPDBG_IS_QUIET;
} else {
PHPDBG_G(flags) &= ~PHPDBG_IS_QUIET;
}
} break;
phpdbg_default_switch_case();
}
return SUCCESS;
} /* }}} */
PHPDBG_SET(stepping) /* {{{ */
{
if (!param || param->type == EMPTY_PARAM) {
phpdbg_writeln("setstepping", "type=\"%s\"", "Stepping %s", PHPDBG_G(flags) & PHPDBG_STEP_OPCODE ? "opcode" : "line");
} else switch (param->type) {
case STR_PARAM: {
if (param->len == sizeof("opcode") - 1 && !memcmp(param->str, "opcode", sizeof("opcode"))) {
PHPDBG_G(flags) |= PHPDBG_STEP_OPCODE;
} else if (param->len == sizeof("line") - 1 && !memcmp(param->str, "line", sizeof("line"))) {
PHPDBG_G(flags) &= ~PHPDBG_STEP_OPCODE;
} else {
phpdbg_error("setstepping", "type=\"wrongargs\"", "usage set stepping [<opcode|line>]");
}
} break;
phpdbg_default_switch_case();
}
return SUCCESS;
} /* }}} */
PHPDBG_SET(refcount) /* {{{ */
{
if (!param || param->type == EMPTY_PARAM) {
phpdbg_writeln("setrefcount", "active=\"%s\"", "Showing refcounts %s", PHPDBG_G(flags) & PHPDBG_IS_QUIET ? "on" : "off");
} else switch (param->type) {
case NUMERIC_PARAM: {
if (param->num) {
PHPDBG_G(flags) |= PHPDBG_SHOW_REFCOUNTS;
} else {
PHPDBG_G(flags) &= ~PHPDBG_SHOW_REFCOUNTS;
}
} break;
phpdbg_default_switch_case();
}
return SUCCESS;
} /* }}} */
| null | null | null | null | 119,009 |
15,793 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 15,793 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "components/sync/syncable/entry_kernel.h"
#include "testing/gtest/include/gtest/gtest.h"
namespace syncer {
namespace syncable {
class EntryKernelTest : public testing::Test {};
TEST_F(EntryKernelTest, ToValue) {
EntryKernel kernel;
std::unique_ptr<base::DictionaryValue> value(kernel.ToValue(nullptr));
if (value) {
// Not much to check without repeating the ToValue() code.
EXPECT_TRUE(value->HasKey("isDirty"));
// The extra +2 is for "isDirty" and "modelType".
EXPECT_EQ(BIT_TEMPS_END - BEGIN_FIELDS + 2,
static_cast<int>(value->size()));
} else {
ADD_FAILURE();
}
}
bool ProtoFieldValuesEqual(const sync_pb::EntitySpecifics& v1,
const sync_pb::EntitySpecifics& v2) {
return v1.SerializeAsString() == v2.SerializeAsString();
}
bool ProtoFieldValuesAreSame(const sync_pb::EntitySpecifics& v1,
const sync_pb::EntitySpecifics& v2) {
return &v1 == &v2;
}
bool ProtoFieldValueIsDefault(const sync_pb::EntitySpecifics& v) {
return ProtoFieldValuesAreSame(v,
sync_pb::EntitySpecifics::default_instance());
}
// Tests default value, assignment, and sharing of proto fields.
TEST_F(EntryKernelTest, ProtoFieldTest) {
EntryKernel kernel;
// Check default values.
EXPECT_TRUE(ProtoFieldValueIsDefault(kernel.ref(SPECIFICS)));
EXPECT_TRUE(ProtoFieldValueIsDefault(kernel.ref(SERVER_SPECIFICS)));
EXPECT_TRUE(ProtoFieldValueIsDefault(kernel.ref(BASE_SERVER_SPECIFICS)));
sync_pb::EntitySpecifics specifics;
// Assign empty value and verify that the field still returns the
// default value.
kernel.put(SPECIFICS, specifics);
EXPECT_TRUE(ProtoFieldValueIsDefault(kernel.ref(SPECIFICS)));
EXPECT_TRUE(ProtoFieldValuesEqual(kernel.ref(SPECIFICS), specifics));
// Verifies that the kernel holds the copy of the value assigned to it.
specifics.mutable_bookmark()->set_url("http://demo/");
EXPECT_FALSE(ProtoFieldValuesEqual(kernel.ref(SPECIFICS), specifics));
// Put the new value and verify the equality.
kernel.put(SPECIFICS, specifics);
EXPECT_TRUE(ProtoFieldValuesEqual(kernel.ref(SPECIFICS), specifics));
EXPECT_FALSE(ProtoFieldValueIsDefault(kernel.ref(SPECIFICS)));
// Copy the value between the fields and verify that exactly the same
// underlying value is shared.
kernel.copy(SPECIFICS, SERVER_SPECIFICS);
EXPECT_TRUE(ProtoFieldValuesEqual(kernel.ref(SERVER_SPECIFICS), specifics));
EXPECT_TRUE(ProtoFieldValuesAreSame(kernel.ref(SPECIFICS),
kernel.ref(SERVER_SPECIFICS)));
// Put the new value into SPECIFICS and verify that that stops sharing even
// though the values are still equal.
kernel.put(SPECIFICS, specifics);
EXPECT_FALSE(ProtoFieldValuesAreSame(kernel.ref(SPECIFICS),
kernel.ref(SERVER_SPECIFICS)));
}
} // namespace syncable
} // namespace syncer
| null | null | null | null | 12,656 |
19,368 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 184,363 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Loopback IEEE 802.15.4 interface
*
* Copyright 2007-2012 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Written by:
* Sergey Lapin <slapin@ossfans.org>
* Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
* Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
*/
#include <linux/module.h>
#include <linux/timer.h>
#include <linux/platform_device.h>
#include <linux/netdevice.h>
#include <linux/device.h>
#include <linux/spinlock.h>
#include <net/mac802154.h>
#include <net/cfg802154.h>
static int numlbs = 2;
static LIST_HEAD(fakelb_phys);
static DEFINE_MUTEX(fakelb_phys_lock);
static LIST_HEAD(fakelb_ifup_phys);
static DEFINE_RWLOCK(fakelb_ifup_phys_lock);
struct fakelb_phy {
struct ieee802154_hw *hw;
u8 page;
u8 channel;
bool suspended;
struct list_head list;
struct list_head list_ifup;
};
static int fakelb_hw_ed(struct ieee802154_hw *hw, u8 *level)
{
BUG_ON(!level);
*level = 0xbe;
return 0;
}
static int fakelb_hw_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
{
struct fakelb_phy *phy = hw->priv;
write_lock_bh(&fakelb_ifup_phys_lock);
phy->page = page;
phy->channel = channel;
write_unlock_bh(&fakelb_ifup_phys_lock);
return 0;
}
static int fakelb_hw_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
{
struct fakelb_phy *current_phy = hw->priv, *phy;
read_lock_bh(&fakelb_ifup_phys_lock);
WARN_ON(current_phy->suspended);
list_for_each_entry(phy, &fakelb_ifup_phys, list_ifup) {
if (current_phy == phy)
continue;
if (current_phy->page == phy->page &&
current_phy->channel == phy->channel) {
struct sk_buff *newskb = pskb_copy(skb, GFP_ATOMIC);
if (newskb)
ieee802154_rx_irqsafe(phy->hw, newskb, 0xcc);
}
}
read_unlock_bh(&fakelb_ifup_phys_lock);
ieee802154_xmit_complete(hw, skb, false);
return 0;
}
static int fakelb_hw_start(struct ieee802154_hw *hw)
{
struct fakelb_phy *phy = hw->priv;
write_lock_bh(&fakelb_ifup_phys_lock);
phy->suspended = false;
list_add(&phy->list_ifup, &fakelb_ifup_phys);
write_unlock_bh(&fakelb_ifup_phys_lock);
return 0;
}
static void fakelb_hw_stop(struct ieee802154_hw *hw)
{
struct fakelb_phy *phy = hw->priv;
write_lock_bh(&fakelb_ifup_phys_lock);
phy->suspended = true;
list_del(&phy->list_ifup);
write_unlock_bh(&fakelb_ifup_phys_lock);
}
static int
fakelb_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
{
return 0;
}
static const struct ieee802154_ops fakelb_ops = {
.owner = THIS_MODULE,
.xmit_async = fakelb_hw_xmit,
.ed = fakelb_hw_ed,
.set_channel = fakelb_hw_channel,
.start = fakelb_hw_start,
.stop = fakelb_hw_stop,
.set_promiscuous_mode = fakelb_set_promiscuous_mode,
};
/* Number of dummy devices to be set up by this module. */
module_param(numlbs, int, 0);
MODULE_PARM_DESC(numlbs, " number of pseudo devices");
static int fakelb_add_one(struct device *dev)
{
struct ieee802154_hw *hw;
struct fakelb_phy *phy;
int err;
hw = ieee802154_alloc_hw(sizeof(*phy), &fakelb_ops);
if (!hw)
return -ENOMEM;
phy = hw->priv;
phy->hw = hw;
/* 868 MHz BPSK 802.15.4-2003 */
hw->phy->supported.channels[0] |= 1;
/* 915 MHz BPSK 802.15.4-2003 */
hw->phy->supported.channels[0] |= 0x7fe;
/* 2.4 GHz O-QPSK 802.15.4-2003 */
hw->phy->supported.channels[0] |= 0x7FFF800;
/* 868 MHz ASK 802.15.4-2006 */
hw->phy->supported.channels[1] |= 1;
/* 915 MHz ASK 802.15.4-2006 */
hw->phy->supported.channels[1] |= 0x7fe;
/* 868 MHz O-QPSK 802.15.4-2006 */
hw->phy->supported.channels[2] |= 1;
/* 915 MHz O-QPSK 802.15.4-2006 */
hw->phy->supported.channels[2] |= 0x7fe;
/* 2.4 GHz CSS 802.15.4a-2007 */
hw->phy->supported.channels[3] |= 0x3fff;
/* UWB Sub-gigahertz 802.15.4a-2007 */
hw->phy->supported.channels[4] |= 1;
/* UWB Low band 802.15.4a-2007 */
hw->phy->supported.channels[4] |= 0x1e;
/* UWB High band 802.15.4a-2007 */
hw->phy->supported.channels[4] |= 0xffe0;
/* 750 MHz O-QPSK 802.15.4c-2009 */
hw->phy->supported.channels[5] |= 0xf;
/* 750 MHz MPSK 802.15.4c-2009 */
hw->phy->supported.channels[5] |= 0xf0;
/* 950 MHz BPSK 802.15.4d-2009 */
hw->phy->supported.channels[6] |= 0x3ff;
/* 950 MHz GFSK 802.15.4d-2009 */
hw->phy->supported.channels[6] |= 0x3ffc00;
ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
/* fake phy channel 13 as default */
hw->phy->current_channel = 13;
phy->channel = hw->phy->current_channel;
hw->flags = IEEE802154_HW_PROMISCUOUS;
hw->parent = dev;
err = ieee802154_register_hw(hw);
if (err)
goto err_reg;
mutex_lock(&fakelb_phys_lock);
list_add_tail(&phy->list, &fakelb_phys);
mutex_unlock(&fakelb_phys_lock);
return 0;
err_reg:
ieee802154_free_hw(phy->hw);
return err;
}
static void fakelb_del(struct fakelb_phy *phy)
{
list_del(&phy->list);
ieee802154_unregister_hw(phy->hw);
ieee802154_free_hw(phy->hw);
}
static int fakelb_probe(struct platform_device *pdev)
{
struct fakelb_phy *phy, *tmp;
int err, i;
for (i = 0; i < numlbs; i++) {
err = fakelb_add_one(&pdev->dev);
if (err < 0)
goto err_slave;
}
dev_info(&pdev->dev, "added %i fake ieee802154 hardware devices\n", numlbs);
return 0;
err_slave:
mutex_lock(&fakelb_phys_lock);
list_for_each_entry_safe(phy, tmp, &fakelb_phys, list)
fakelb_del(phy);
mutex_unlock(&fakelb_phys_lock);
return err;
}
static int fakelb_remove(struct platform_device *pdev)
{
struct fakelb_phy *phy, *tmp;
mutex_lock(&fakelb_phys_lock);
list_for_each_entry_safe(phy, tmp, &fakelb_phys, list)
fakelb_del(phy);
mutex_unlock(&fakelb_phys_lock);
return 0;
}
static struct platform_device *ieee802154fake_dev;
static struct platform_driver ieee802154fake_driver = {
.probe = fakelb_probe,
.remove = fakelb_remove,
.driver = {
.name = "ieee802154fakelb",
},
};
static __init int fakelb_init_module(void)
{
ieee802154fake_dev = platform_device_register_simple(
"ieee802154fakelb", -1, NULL, 0);
return platform_driver_register(&ieee802154fake_driver);
}
static __exit void fake_remove_module(void)
{
platform_driver_unregister(&ieee802154fake_driver);
platform_device_unregister(ieee802154fake_dev);
}
module_init(fakelb_init_module);
module_exit(fake_remove_module);
MODULE_LICENSE("GPL");
| null | null | null | null | 92,710 |
10,756 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 175,751 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /* pci_fire.c: Sun4u platform PCI-E controller support.
*
* Copyright (C) 2007 David S. Miller (davem@davemloft.net)
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/msi.h>
#include <linux/export.h>
#include <linux/irq.h>
#include <linux/of_device.h>
#include <asm/prom.h>
#include <asm/irq.h>
#include <asm/upa.h>
#include "pci_impl.h"
#define DRIVER_NAME "fire"
#define PFX DRIVER_NAME ": "
#define FIRE_IOMMU_CONTROL 0x40000UL
#define FIRE_IOMMU_TSBBASE 0x40008UL
#define FIRE_IOMMU_FLUSH 0x40100UL
#define FIRE_IOMMU_FLUSHINV 0x40108UL
static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
{
struct iommu *iommu = pbm->iommu;
u32 vdma[2], dma_mask;
u64 control;
int tsbsize, err;
/* No virtual-dma property on these guys, use largest size. */
vdma[0] = 0xc0000000; /* base */
vdma[1] = 0x40000000; /* size */
dma_mask = 0xffffffff;
tsbsize = 128;
/* Register addresses. */
iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
/* We use the main control/status register of FIRE as the write
* completion register.
*/
iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
/*
* Invalidate TLB Entries.
*/
upa_writeq(~(u64)0, iommu->iommu_flushinv);
err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
pbm->numa_node);
if (err)
return err;
upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase);
control = upa_readq(iommu->iommu_control);
control |= (0x00000400 /* TSB cache snoop enable */ |
0x00000300 /* Cache mode */ |
0x00000002 /* Bypass enable */ |
0x00000001 /* Translation enable */);
upa_writeq(control, iommu->iommu_control);
return 0;
}
#ifdef CONFIG_PCI_MSI
struct pci_msiq_entry {
u64 word0;
#define MSIQ_WORD0_RESV 0x8000000000000000UL
#define MSIQ_WORD0_FMT_TYPE 0x7f00000000000000UL
#define MSIQ_WORD0_FMT_TYPE_SHIFT 56
#define MSIQ_WORD0_LEN 0x00ffc00000000000UL
#define MSIQ_WORD0_LEN_SHIFT 46
#define MSIQ_WORD0_ADDR0 0x00003fff00000000UL
#define MSIQ_WORD0_ADDR0_SHIFT 32
#define MSIQ_WORD0_RID 0x00000000ffff0000UL
#define MSIQ_WORD0_RID_SHIFT 16
#define MSIQ_WORD0_DATA0 0x000000000000ffffUL
#define MSIQ_WORD0_DATA0_SHIFT 0
#define MSIQ_TYPE_MSG 0x6
#define MSIQ_TYPE_MSI32 0xb
#define MSIQ_TYPE_MSI64 0xf
u64 word1;
#define MSIQ_WORD1_ADDR1 0xffffffffffff0000UL
#define MSIQ_WORD1_ADDR1_SHIFT 16
#define MSIQ_WORD1_DATA1 0x000000000000ffffUL
#define MSIQ_WORD1_DATA1_SHIFT 0
u64 resv[6];
};
/* All MSI registers are offset from pbm->pbm_regs */
#define EVENT_QUEUE_BASE_ADDR_REG 0x010000UL
#define EVENT_QUEUE_BASE_ADDR_ALL_ONES 0xfffc000000000000UL
#define EVENT_QUEUE_CONTROL_SET(EQ) (0x011000UL + (EQ) * 0x8UL)
#define EVENT_QUEUE_CONTROL_SET_OFLOW 0x0200000000000000UL
#define EVENT_QUEUE_CONTROL_SET_EN 0x0000100000000000UL
#define EVENT_QUEUE_CONTROL_CLEAR(EQ) (0x011200UL + (EQ) * 0x8UL)
#define EVENT_QUEUE_CONTROL_CLEAR_OF 0x0200000000000000UL
#define EVENT_QUEUE_CONTROL_CLEAR_E2I 0x0000800000000000UL
#define EVENT_QUEUE_CONTROL_CLEAR_DIS 0x0000100000000000UL
#define EVENT_QUEUE_STATE(EQ) (0x011400UL + (EQ) * 0x8UL)
#define EVENT_QUEUE_STATE_MASK 0x0000000000000007UL
#define EVENT_QUEUE_STATE_IDLE 0x0000000000000001UL
#define EVENT_QUEUE_STATE_ACTIVE 0x0000000000000002UL
#define EVENT_QUEUE_STATE_ERROR 0x0000000000000004UL
#define EVENT_QUEUE_TAIL(EQ) (0x011600UL + (EQ) * 0x8UL)
#define EVENT_QUEUE_TAIL_OFLOW 0x0200000000000000UL
#define EVENT_QUEUE_TAIL_VAL 0x000000000000007fUL
#define EVENT_QUEUE_HEAD(EQ) (0x011800UL + (EQ) * 0x8UL)
#define EVENT_QUEUE_HEAD_VAL 0x000000000000007fUL
#define MSI_MAP(MSI) (0x020000UL + (MSI) * 0x8UL)
#define MSI_MAP_VALID 0x8000000000000000UL
#define MSI_MAP_EQWR_N 0x4000000000000000UL
#define MSI_MAP_EQNUM 0x000000000000003fUL
#define MSI_CLEAR(MSI) (0x028000UL + (MSI) * 0x8UL)
#define MSI_CLEAR_EQWR_N 0x4000000000000000UL
#define IMONDO_DATA0 0x02C000UL
#define IMONDO_DATA0_DATA 0xffffffffffffffc0UL
#define IMONDO_DATA1 0x02C008UL
#define IMONDO_DATA1_DATA 0xffffffffffffffffUL
#define MSI_32BIT_ADDR 0x034000UL
#define MSI_32BIT_ADDR_VAL 0x00000000ffff0000UL
#define MSI_64BIT_ADDR 0x034008UL
#define MSI_64BIT_ADDR_VAL 0xffffffffffff0000UL
static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
unsigned long *head)
{
*head = upa_readq(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
return 0;
}
static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
unsigned long *head, unsigned long *msi)
{
unsigned long type_fmt, type, msi_num;
struct pci_msiq_entry *base, *ep;
base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192));
ep = &base[*head];
if ((ep->word0 & MSIQ_WORD0_FMT_TYPE) == 0)
return 0;
type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >>
MSIQ_WORD0_FMT_TYPE_SHIFT);
type = (type_fmt >> 3);
if (unlikely(type != MSIQ_TYPE_MSI32 &&
type != MSIQ_TYPE_MSI64))
return -EINVAL;
*msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
MSIQ_WORD0_DATA0_SHIFT);
upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num));
/* Clear the entry. */
ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;
/* Go to next entry in ring. */
(*head)++;
if (*head >= pbm->msiq_ent_count)
*head = 0;
return 1;
}
static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
unsigned long head)
{
upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
return 0;
}
static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
unsigned long msi, int is_msi64)
{
u64 val;
val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
val &= ~(MSI_MAP_EQNUM);
val |= msiqid;
upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi));
val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
val |= MSI_MAP_VALID;
upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
return 0;
}
static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
{
u64 val;
val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
val &= ~MSI_MAP_VALID;
upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
return 0;
}
static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm)
{
unsigned long pages, order, i;
order = get_order(512 * 1024);
pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
if (pages == 0UL) {
printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
order);
return -ENOMEM;
}
memset((char *)pages, 0, PAGE_SIZE << order);
pbm->msi_queues = (void *) pages;
upa_writeq((EVENT_QUEUE_BASE_ADDR_ALL_ONES |
__pa(pbm->msi_queues)),
pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG);
upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0);
upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1);
upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR);
upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR);
for (i = 0; i < pbm->msiq_num; i++) {
upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i));
upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i));
}
return 0;
}
static void pci_fire_msiq_free(struct pci_pbm_info *pbm)
{
unsigned long pages, order;
order = get_order(512 * 1024);
pages = (unsigned long) pbm->msi_queues;
free_pages(pages, order);
pbm->msi_queues = NULL;
}
static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
unsigned long msiqid,
unsigned long devino)
{
unsigned long cregs = (unsigned long) pbm->pbm_regs;
unsigned long imap_reg, iclr_reg, int_ctrlr;
unsigned int irq;
int fixup;
u64 val;
imap_reg = cregs + (0x001000UL + (devino * 0x08UL));
iclr_reg = cregs + (0x001400UL + (devino * 0x08UL));
/* XXX iterate amongst the 4 IRQ controllers XXX */
int_ctrlr = (1UL << 6);
val = upa_readq(imap_reg);
val |= (1UL << 63) | int_ctrlr;
upa_writeq(val, imap_reg);
fixup = ((pbm->portid << 6) | devino) - int_ctrlr;
irq = build_irq(fixup, iclr_reg, imap_reg);
if (!irq)
return -ENOMEM;
upa_writeq(EVENT_QUEUE_CONTROL_SET_EN,
pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid));
return irq;
}
static const struct sparc64_msiq_ops pci_fire_msiq_ops = {
.get_head = pci_fire_get_head,
.dequeue_msi = pci_fire_dequeue_msi,
.set_head = pci_fire_set_head,
.msi_setup = pci_fire_msi_setup,
.msi_teardown = pci_fire_msi_teardown,
.msiq_alloc = pci_fire_msiq_alloc,
.msiq_free = pci_fire_msiq_free,
.msiq_build_irq = pci_fire_msiq_build_irq,
};
static void pci_fire_msi_init(struct pci_pbm_info *pbm)
{
sparc64_pbm_msi_init(pbm, &pci_fire_msiq_ops);
}
#else /* CONFIG_PCI_MSI */
static void pci_fire_msi_init(struct pci_pbm_info *pbm)
{
}
#endif /* !(CONFIG_PCI_MSI) */
/* Based at pbm->controller_regs */
#define FIRE_PARITY_CONTROL 0x470010UL
#define FIRE_PARITY_ENAB 0x8000000000000000UL
#define FIRE_FATAL_RESET_CTL 0x471028UL
#define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
#define FIRE_FATAL_RESET_MB 0x0000000002000000UL
#define FIRE_FATAL_RESET_CPE 0x0000000000008000UL
#define FIRE_FATAL_RESET_APE 0x0000000000004000UL
#define FIRE_FATAL_RESET_PIO 0x0000000000000040UL
#define FIRE_FATAL_RESET_JW 0x0000000000000004UL
#define FIRE_FATAL_RESET_JI 0x0000000000000002UL
#define FIRE_FATAL_RESET_JR 0x0000000000000001UL
#define FIRE_CORE_INTR_ENABLE 0x471800UL
/* Based at pbm->pbm_regs */
#define FIRE_TLU_CTRL 0x80000UL
#define FIRE_TLU_CTRL_TIM 0x00000000da000000UL
#define FIRE_TLU_CTRL_QDET 0x0000000000000100UL
#define FIRE_TLU_CTRL_CFG 0x0000000000000001UL
#define FIRE_TLU_DEV_CTRL 0x90008UL
#define FIRE_TLU_LINK_CTRL 0x90020UL
#define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL
#define FIRE_LPU_RESET 0xe2008UL
#define FIRE_LPU_LLCFG 0xe2200UL
#define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL
#define FIRE_LPU_FCTRL_UCTRL 0xe2240UL
#define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
#define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
#define FIRE_LPU_TXL_FIFOP 0xe2430UL
#define FIRE_LPU_LTSSM_CFG2 0xe2788UL
#define FIRE_LPU_LTSSM_CFG3 0xe2790UL
#define FIRE_LPU_LTSSM_CFG4 0xe2798UL
#define FIRE_LPU_LTSSM_CFG5 0xe27a0UL
#define FIRE_DMC_IENAB 0x31800UL
#define FIRE_DMC_DBG_SEL_A 0x53000UL
#define FIRE_DMC_DBG_SEL_B 0x53008UL
#define FIRE_PEC_IENAB 0x51800UL
static void pci_fire_hw_init(struct pci_pbm_info *pbm)
{
u64 val;
upa_writeq(FIRE_PARITY_ENAB,
pbm->controller_regs + FIRE_PARITY_CONTROL);
upa_writeq((FIRE_FATAL_RESET_SPARE |
FIRE_FATAL_RESET_MB |
FIRE_FATAL_RESET_CPE |
FIRE_FATAL_RESET_APE |
FIRE_FATAL_RESET_PIO |
FIRE_FATAL_RESET_JW |
FIRE_FATAL_RESET_JI |
FIRE_FATAL_RESET_JR),
pbm->controller_regs + FIRE_FATAL_RESET_CTL);
upa_writeq(~(u64)0, pbm->controller_regs + FIRE_CORE_INTR_ENABLE);
val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL);
val |= (FIRE_TLU_CTRL_TIM |
FIRE_TLU_CTRL_QDET |
FIRE_TLU_CTRL_CFG);
upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL);
upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL);
upa_writeq(FIRE_TLU_LINK_CTRL_CLK,
pbm->pbm_regs + FIRE_TLU_LINK_CTRL);
upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET);
upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG);
upa_writeq((FIRE_LPU_FCTRL_UCTRL_N | FIRE_LPU_FCTRL_UCTRL_P),
pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL);
upa_writeq(((0xffff << 16) | (0x0000 << 0)),
pbm->pbm_regs + FIRE_LPU_TXL_FIFOP);
upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2);
upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3);
upa_writeq((2 << 16) | (140 << 8),
pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4);
upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5);
upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB);
upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A);
upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B);
upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB);
}
static int pci_fire_pbm_init(struct pci_pbm_info *pbm,
struct platform_device *op, u32 portid)
{
const struct linux_prom64_registers *regs;
struct device_node *dp = op->dev.of_node;
int err;
pbm->numa_node = -1;
pbm->pci_ops = &sun4u_pci_ops;
pbm->config_space_reg_bits = 12;
pbm->index = pci_num_pbms++;
pbm->portid = portid;
pbm->op = op;
pbm->name = dp->full_name;
regs = of_get_property(dp, "reg", NULL);
pbm->pbm_regs = regs[0].phys_addr;
pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
pci_determine_mem_io_space(pbm);
pci_get_pbm_props(pbm);
pci_fire_hw_init(pbm);
err = pci_fire_pbm_iommu_init(pbm);
if (err)
return err;
pci_fire_msi_init(pbm);
pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev);
/* XXX register error interrupt handlers XXX */
pbm->next = pci_pbm_root;
pci_pbm_root = pbm;
return 0;
}
static int fire_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct pci_pbm_info *pbm;
struct iommu *iommu;
u32 portid;
int err;
portid = of_getintprop_default(dp, "portid", 0xff);
err = -ENOMEM;
pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
if (!pbm) {
printk(KERN_ERR PFX "Cannot allocate pci_pbminfo.\n");
goto out_err;
}
iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
if (!iommu) {
printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
goto out_free_controller;
}
pbm->iommu = iommu;
err = pci_fire_pbm_init(pbm, op, portid);
if (err)
goto out_free_iommu;
dev_set_drvdata(&op->dev, pbm);
return 0;
out_free_iommu:
kfree(pbm->iommu);
out_free_controller:
kfree(pbm);
out_err:
return err;
}
static const struct of_device_id fire_match[] = {
{
.name = "pci",
.compatible = "pciex108e,80f0",
},
{},
};
static struct platform_driver fire_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = fire_match,
},
.probe = fire_probe,
};
static int __init fire_init(void)
{
return platform_driver_register(&fire_driver);
}
subsys_initcall(fire_init);
| null | null | null | null | 84,098 |
33,865 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 198,860 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* SMI PCIe driver for DVBSky cards.
*
* Copyright (C) 2014 Max nibble <nibble.max@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "smipcie.h"
#include "m88ds3103.h"
#include "ts2020.h"
#include "m88rs6000t.h"
#include "si2168.h"
#include "si2157.h"
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
static int smi_hw_init(struct smi_dev *dev)
{
u32 port_mux, port_ctrl, int_stat;
/* set port mux.*/
port_mux = smi_read(MUX_MODE_CTRL);
port_mux &= ~(rbPaMSMask);
port_mux |= rbPaMSDtvNoGpio;
port_mux &= ~(rbPbMSMask);
port_mux |= rbPbMSDtvNoGpio;
port_mux &= ~(0x0f0000);
port_mux |= 0x50000;
smi_write(MUX_MODE_CTRL, port_mux);
/* set DTV register.*/
/* Port A */
port_ctrl = smi_read(VIDEO_CTRL_STATUS_A);
port_ctrl &= ~0x01;
smi_write(VIDEO_CTRL_STATUS_A, port_ctrl);
port_ctrl = smi_read(MPEG2_CTRL_A);
port_ctrl &= ~0x40;
port_ctrl |= 0x80;
smi_write(MPEG2_CTRL_A, port_ctrl);
/* Port B */
port_ctrl = smi_read(VIDEO_CTRL_STATUS_B);
port_ctrl &= ~0x01;
smi_write(VIDEO_CTRL_STATUS_B, port_ctrl);
port_ctrl = smi_read(MPEG2_CTRL_B);
port_ctrl &= ~0x40;
port_ctrl |= 0x80;
smi_write(MPEG2_CTRL_B, port_ctrl);
/* disable and clear interrupt.*/
smi_write(MSI_INT_ENA_CLR, ALL_INT);
int_stat = smi_read(MSI_INT_STATUS);
smi_write(MSI_INT_STATUS_CLR, int_stat);
/* reset demod.*/
smi_clear(PERIPHERAL_CTRL, 0x0303);
msleep(50);
smi_set(PERIPHERAL_CTRL, 0x0101);
return 0;
}
/* i2c bit bus.*/
static void smi_i2c_cfg(struct smi_dev *dev, u32 sw_ctl)
{
u32 dwCtrl;
dwCtrl = smi_read(sw_ctl);
dwCtrl &= ~0x18; /* disable output.*/
dwCtrl |= 0x21; /* reset and software mode.*/
dwCtrl &= ~0xff00;
dwCtrl |= 0x6400;
smi_write(sw_ctl, dwCtrl);
msleep(20);
dwCtrl = smi_read(sw_ctl);
dwCtrl &= ~0x20;
smi_write(sw_ctl, dwCtrl);
}
static void smi_i2c_setsda(struct smi_dev *dev, int state, u32 sw_ctl)
{
if (state) {
/* set as input.*/
smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
} else {
smi_clear(sw_ctl, SW_I2C_MSK_DAT_OUT);
/* set as output.*/
smi_set(sw_ctl, SW_I2C_MSK_DAT_EN);
}
}
static void smi_i2c_setscl(void *data, int state, u32 sw_ctl)
{
struct smi_dev *dev = data;
if (state) {
/* set as input.*/
smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
} else {
smi_clear(sw_ctl, SW_I2C_MSK_CLK_OUT);
/* set as output.*/
smi_set(sw_ctl, SW_I2C_MSK_CLK_EN);
}
}
static int smi_i2c_getsda(void *data, u32 sw_ctl)
{
struct smi_dev *dev = data;
/* set as input.*/
smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
udelay(1);
return (smi_read(sw_ctl) & SW_I2C_MSK_DAT_IN) ? 1 : 0;
}
static int smi_i2c_getscl(void *data, u32 sw_ctl)
{
struct smi_dev *dev = data;
/* set as input.*/
smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
udelay(1);
return (smi_read(sw_ctl) & SW_I2C_MSK_CLK_IN) ? 1 : 0;
}
/* i2c 0.*/
static void smi_i2c0_setsda(void *data, int state)
{
struct smi_dev *dev = data;
smi_i2c_setsda(dev, state, I2C_A_SW_CTL);
}
static void smi_i2c0_setscl(void *data, int state)
{
struct smi_dev *dev = data;
smi_i2c_setscl(dev, state, I2C_A_SW_CTL);
}
static int smi_i2c0_getsda(void *data)
{
struct smi_dev *dev = data;
return smi_i2c_getsda(dev, I2C_A_SW_CTL);
}
static int smi_i2c0_getscl(void *data)
{
struct smi_dev *dev = data;
return smi_i2c_getscl(dev, I2C_A_SW_CTL);
}
/* i2c 1.*/
static void smi_i2c1_setsda(void *data, int state)
{
struct smi_dev *dev = data;
smi_i2c_setsda(dev, state, I2C_B_SW_CTL);
}
static void smi_i2c1_setscl(void *data, int state)
{
struct smi_dev *dev = data;
smi_i2c_setscl(dev, state, I2C_B_SW_CTL);
}
static int smi_i2c1_getsda(void *data)
{
struct smi_dev *dev = data;
return smi_i2c_getsda(dev, I2C_B_SW_CTL);
}
static int smi_i2c1_getscl(void *data)
{
struct smi_dev *dev = data;
return smi_i2c_getscl(dev, I2C_B_SW_CTL);
}
static int smi_i2c_init(struct smi_dev *dev)
{
int ret;
/* i2c bus 0 */
smi_i2c_cfg(dev, I2C_A_SW_CTL);
i2c_set_adapdata(&dev->i2c_bus[0], dev);
strcpy(dev->i2c_bus[0].name, "SMI-I2C0");
dev->i2c_bus[0].owner = THIS_MODULE;
dev->i2c_bus[0].dev.parent = &dev->pci_dev->dev;
dev->i2c_bus[0].algo_data = &dev->i2c_bit[0];
dev->i2c_bit[0].data = dev;
dev->i2c_bit[0].setsda = smi_i2c0_setsda;
dev->i2c_bit[0].setscl = smi_i2c0_setscl;
dev->i2c_bit[0].getsda = smi_i2c0_getsda;
dev->i2c_bit[0].getscl = smi_i2c0_getscl;
dev->i2c_bit[0].udelay = 12;
dev->i2c_bit[0].timeout = 10;
/* Raise SCL and SDA */
smi_i2c0_setsda(dev, 1);
smi_i2c0_setscl(dev, 1);
ret = i2c_bit_add_bus(&dev->i2c_bus[0]);
if (ret < 0)
return ret;
/* i2c bus 1 */
smi_i2c_cfg(dev, I2C_B_SW_CTL);
i2c_set_adapdata(&dev->i2c_bus[1], dev);
strcpy(dev->i2c_bus[1].name, "SMI-I2C1");
dev->i2c_bus[1].owner = THIS_MODULE;
dev->i2c_bus[1].dev.parent = &dev->pci_dev->dev;
dev->i2c_bus[1].algo_data = &dev->i2c_bit[1];
dev->i2c_bit[1].data = dev;
dev->i2c_bit[1].setsda = smi_i2c1_setsda;
dev->i2c_bit[1].setscl = smi_i2c1_setscl;
dev->i2c_bit[1].getsda = smi_i2c1_getsda;
dev->i2c_bit[1].getscl = smi_i2c1_getscl;
dev->i2c_bit[1].udelay = 12;
dev->i2c_bit[1].timeout = 10;
/* Raise SCL and SDA */
smi_i2c1_setsda(dev, 1);
smi_i2c1_setscl(dev, 1);
ret = i2c_bit_add_bus(&dev->i2c_bus[1]);
if (ret < 0)
i2c_del_adapter(&dev->i2c_bus[0]);
return ret;
}
static void smi_i2c_exit(struct smi_dev *dev)
{
i2c_del_adapter(&dev->i2c_bus[0]);
i2c_del_adapter(&dev->i2c_bus[1]);
}
static int smi_read_eeprom(struct i2c_adapter *i2c, u16 reg, u8 *data, u16 size)
{
int ret;
u8 b0[2] = { (reg >> 8) & 0xff, reg & 0xff };
struct i2c_msg msg[] = {
{ .addr = 0x50, .flags = 0,
.buf = b0, .len = 2 },
{ .addr = 0x50, .flags = I2C_M_RD,
.buf = data, .len = size }
};
ret = i2c_transfer(i2c, msg, 2);
if (ret != 2) {
dev_err(&i2c->dev, "%s: reg=0x%x (error=%d)\n",
__func__, reg, ret);
return ret;
}
return ret;
}
/* ts port interrupt operations */
static void smi_port_disableInterrupt(struct smi_port *port)
{
struct smi_dev *dev = port->dev;
smi_write(MSI_INT_ENA_CLR,
(port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
}
static void smi_port_enableInterrupt(struct smi_port *port)
{
struct smi_dev *dev = port->dev;
smi_write(MSI_INT_ENA_SET,
(port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
}
static void smi_port_clearInterrupt(struct smi_port *port)
{
struct smi_dev *dev = port->dev;
smi_write(MSI_INT_STATUS_CLR,
(port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
}
/* tasklet handler: DMA data to dmx.*/
static void smi_dma_xfer(unsigned long data)
{
struct smi_port *port = (struct smi_port *) data;
struct smi_dev *dev = port->dev;
u32 intr_status, finishedData, dmaManagement;
u8 dmaChan0State, dmaChan1State;
intr_status = port->_int_status;
dmaManagement = smi_read(port->DMA_MANAGEMENT);
dmaChan0State = (u8)((dmaManagement & 0x00000030) >> 4);
dmaChan1State = (u8)((dmaManagement & 0x00300000) >> 20);
/* CH-0 DMA interrupt.*/
if ((intr_status & port->_dmaInterruptCH0) && (dmaChan0State == 0x01)) {
dev_dbg(&dev->pci_dev->dev,
"Port[%d]-DMA CH0 engine complete successful !\n",
port->idx);
finishedData = smi_read(port->DMA_CHAN0_TRANS_STATE);
finishedData &= 0x003FFFFF;
/* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
* indicate dma total transfer length and
* zero of [21:0] indicate dma total transfer length
* equal to 0x400000 (4MB)*/
if (finishedData == 0)
finishedData = 0x00400000;
if (finishedData != SMI_TS_DMA_BUF_SIZE) {
dev_dbg(&dev->pci_dev->dev,
"DMA CH0 engine complete length mismatched, finish data=%d !\n",
finishedData);
}
dvb_dmx_swfilter_packets(&port->demux,
port->cpu_addr[0], (finishedData / 188));
/*dvb_dmx_swfilter(&port->demux,
port->cpu_addr[0], finishedData);*/
}
/* CH-1 DMA interrupt.*/
if ((intr_status & port->_dmaInterruptCH1) && (dmaChan1State == 0x01)) {
dev_dbg(&dev->pci_dev->dev,
"Port[%d]-DMA CH1 engine complete successful !\n",
port->idx);
finishedData = smi_read(port->DMA_CHAN1_TRANS_STATE);
finishedData &= 0x003FFFFF;
/* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
* indicate dma total transfer length and
* zero of [21:0] indicate dma total transfer length
* equal to 0x400000 (4MB)*/
if (finishedData == 0)
finishedData = 0x00400000;
if (finishedData != SMI_TS_DMA_BUF_SIZE) {
dev_dbg(&dev->pci_dev->dev,
"DMA CH1 engine complete length mismatched, finish data=%d !\n",
finishedData);
}
dvb_dmx_swfilter_packets(&port->demux,
port->cpu_addr[1], (finishedData / 188));
/*dvb_dmx_swfilter(&port->demux,
port->cpu_addr[1], finishedData);*/
}
/* restart DMA.*/
if (intr_status & port->_dmaInterruptCH0)
dmaManagement |= 0x00000002;
if (intr_status & port->_dmaInterruptCH1)
dmaManagement |= 0x00020000;
smi_write(port->DMA_MANAGEMENT, dmaManagement);
/* Re-enable interrupts */
smi_port_enableInterrupt(port);
}
static void smi_port_dma_free(struct smi_port *port)
{
if (port->cpu_addr[0]) {
pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE,
port->cpu_addr[0], port->dma_addr[0]);
port->cpu_addr[0] = NULL;
}
if (port->cpu_addr[1]) {
pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE,
port->cpu_addr[1], port->dma_addr[1]);
port->cpu_addr[1] = NULL;
}
}
static int smi_port_init(struct smi_port *port, int dmaChanUsed)
{
dev_dbg(&port->dev->pci_dev->dev,
"%s, port %d, dmaused %d\n", __func__, port->idx, dmaChanUsed);
port->enable = 0;
if (port->idx == 0) {
/* Port A */
port->_dmaInterruptCH0 = dmaChanUsed & 0x01;
port->_dmaInterruptCH1 = dmaChanUsed & 0x02;
port->DMA_CHAN0_ADDR_LOW = DMA_PORTA_CHAN0_ADDR_LOW;
port->DMA_CHAN0_ADDR_HI = DMA_PORTA_CHAN0_ADDR_HI;
port->DMA_CHAN0_TRANS_STATE = DMA_PORTA_CHAN0_TRANS_STATE;
port->DMA_CHAN0_CONTROL = DMA_PORTA_CHAN0_CONTROL;
port->DMA_CHAN1_ADDR_LOW = DMA_PORTA_CHAN1_ADDR_LOW;
port->DMA_CHAN1_ADDR_HI = DMA_PORTA_CHAN1_ADDR_HI;
port->DMA_CHAN1_TRANS_STATE = DMA_PORTA_CHAN1_TRANS_STATE;
port->DMA_CHAN1_CONTROL = DMA_PORTA_CHAN1_CONTROL;
port->DMA_MANAGEMENT = DMA_PORTA_MANAGEMENT;
} else {
/* Port B */
port->_dmaInterruptCH0 = (dmaChanUsed << 2) & 0x04;
port->_dmaInterruptCH1 = (dmaChanUsed << 2) & 0x08;
port->DMA_CHAN0_ADDR_LOW = DMA_PORTB_CHAN0_ADDR_LOW;
port->DMA_CHAN0_ADDR_HI = DMA_PORTB_CHAN0_ADDR_HI;
port->DMA_CHAN0_TRANS_STATE = DMA_PORTB_CHAN0_TRANS_STATE;
port->DMA_CHAN0_CONTROL = DMA_PORTB_CHAN0_CONTROL;
port->DMA_CHAN1_ADDR_LOW = DMA_PORTB_CHAN1_ADDR_LOW;
port->DMA_CHAN1_ADDR_HI = DMA_PORTB_CHAN1_ADDR_HI;
port->DMA_CHAN1_TRANS_STATE = DMA_PORTB_CHAN1_TRANS_STATE;
port->DMA_CHAN1_CONTROL = DMA_PORTB_CHAN1_CONTROL;
port->DMA_MANAGEMENT = DMA_PORTB_MANAGEMENT;
}
if (port->_dmaInterruptCH0) {
port->cpu_addr[0] = pci_alloc_consistent(port->dev->pci_dev,
SMI_TS_DMA_BUF_SIZE,
&port->dma_addr[0]);
if (!port->cpu_addr[0]) {
dev_err(&port->dev->pci_dev->dev,
"Port[%d] DMA CH0 memory allocation failed!\n",
port->idx);
goto err;
}
}
if (port->_dmaInterruptCH1) {
port->cpu_addr[1] = pci_alloc_consistent(port->dev->pci_dev,
SMI_TS_DMA_BUF_SIZE,
&port->dma_addr[1]);
if (!port->cpu_addr[1]) {
dev_err(&port->dev->pci_dev->dev,
"Port[%d] DMA CH1 memory allocation failed!\n",
port->idx);
goto err;
}
}
smi_port_disableInterrupt(port);
tasklet_init(&port->tasklet, smi_dma_xfer, (unsigned long)port);
tasklet_disable(&port->tasklet);
port->enable = 1;
return 0;
err:
smi_port_dma_free(port);
return -ENOMEM;
}
static void smi_port_exit(struct smi_port *port)
{
smi_port_disableInterrupt(port);
tasklet_kill(&port->tasklet);
smi_port_dma_free(port);
port->enable = 0;
}
static int smi_port_irq(struct smi_port *port, u32 int_status)
{
u32 port_req_irq = port->_dmaInterruptCH0 | port->_dmaInterruptCH1;
int handled = 0;
if (int_status & port_req_irq) {
smi_port_disableInterrupt(port);
port->_int_status = int_status;
smi_port_clearInterrupt(port);
tasklet_schedule(&port->tasklet);
handled = 1;
}
return handled;
}
static irqreturn_t smi_irq_handler(int irq, void *dev_id)
{
struct smi_dev *dev = dev_id;
struct smi_port *port0 = &dev->ts_port[0];
struct smi_port *port1 = &dev->ts_port[1];
struct smi_rc *ir = &dev->ir;
int handled = 0;
u32 intr_status = smi_read(MSI_INT_STATUS);
/* ts0 interrupt.*/
if (dev->info->ts_0)
handled += smi_port_irq(port0, intr_status);
/* ts1 interrupt.*/
if (dev->info->ts_1)
handled += smi_port_irq(port1, intr_status);
/* ir interrupt.*/
handled += smi_ir_irq(ir, intr_status);
return IRQ_RETVAL(handled);
}
static struct i2c_client *smi_add_i2c_client(struct i2c_adapter *adapter,
struct i2c_board_info *info)
{
struct i2c_client *client;
request_module(info->type);
client = i2c_new_device(adapter, info);
if (client == NULL || client->dev.driver == NULL)
goto err_add_i2c_client;
if (!try_module_get(client->dev.driver->owner)) {
i2c_unregister_device(client);
goto err_add_i2c_client;
}
return client;
err_add_i2c_client:
client = NULL;
return client;
}
static void smi_del_i2c_client(struct i2c_client *client)
{
module_put(client->dev.driver->owner);
i2c_unregister_device(client);
}
static const struct m88ds3103_config smi_dvbsky_m88ds3103_cfg = {
.i2c_addr = 0x68,
.clock = 27000000,
.i2c_wr_max = 33,
.clock_out = 0,
.ts_mode = M88DS3103_TS_PARALLEL,
.ts_clk = 16000,
.ts_clk_pol = 1,
.agc = 0x99,
.lnb_hv_pol = 0,
.lnb_en_pol = 1,
};
static int smi_dvbsky_m88ds3103_fe_attach(struct smi_port *port)
{
int ret = 0;
struct smi_dev *dev = port->dev;
struct i2c_adapter *i2c;
/* tuner I2C module */
struct i2c_adapter *tuner_i2c_adapter;
struct i2c_client *tuner_client;
struct i2c_board_info tuner_info;
struct ts2020_config ts2020_config = {};
memset(&tuner_info, 0, sizeof(struct i2c_board_info));
i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
/* attach demod */
port->fe = dvb_attach(m88ds3103_attach,
&smi_dvbsky_m88ds3103_cfg, i2c, &tuner_i2c_adapter);
if (!port->fe) {
ret = -ENODEV;
return ret;
}
/* attach tuner */
ts2020_config.fe = port->fe;
strlcpy(tuner_info.type, "ts2020", I2C_NAME_SIZE);
tuner_info.addr = 0x60;
tuner_info.platform_data = &ts2020_config;
tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
if (!tuner_client) {
ret = -ENODEV;
goto err_tuner_i2c_device;
}
/* delegate signal strength measurement to tuner */
port->fe->ops.read_signal_strength =
port->fe->ops.tuner_ops.get_rf_strength;
port->i2c_client_tuner = tuner_client;
return ret;
err_tuner_i2c_device:
dvb_frontend_detach(port->fe);
return ret;
}
static const struct m88ds3103_config smi_dvbsky_m88rs6000_cfg = {
.i2c_addr = 0x69,
.clock = 27000000,
.i2c_wr_max = 33,
.ts_mode = M88DS3103_TS_PARALLEL,
.ts_clk = 16000,
.ts_clk_pol = 1,
.agc = 0x99,
.lnb_hv_pol = 0,
.lnb_en_pol = 1,
};
static int smi_dvbsky_m88rs6000_fe_attach(struct smi_port *port)
{
int ret = 0;
struct smi_dev *dev = port->dev;
struct i2c_adapter *i2c;
/* tuner I2C module */
struct i2c_adapter *tuner_i2c_adapter;
struct i2c_client *tuner_client;
struct i2c_board_info tuner_info;
struct m88rs6000t_config m88rs6000t_config;
memset(&tuner_info, 0, sizeof(struct i2c_board_info));
i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
/* attach demod */
port->fe = dvb_attach(m88ds3103_attach,
&smi_dvbsky_m88rs6000_cfg, i2c, &tuner_i2c_adapter);
if (!port->fe) {
ret = -ENODEV;
return ret;
}
/* attach tuner */
m88rs6000t_config.fe = port->fe;
strlcpy(tuner_info.type, "m88rs6000t", I2C_NAME_SIZE);
tuner_info.addr = 0x21;
tuner_info.platform_data = &m88rs6000t_config;
tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
if (!tuner_client) {
ret = -ENODEV;
goto err_tuner_i2c_device;
}
/* delegate signal strength measurement to tuner */
port->fe->ops.read_signal_strength =
port->fe->ops.tuner_ops.get_rf_strength;
port->i2c_client_tuner = tuner_client;
return ret;
err_tuner_i2c_device:
dvb_frontend_detach(port->fe);
return ret;
}
static int smi_dvbsky_sit2_fe_attach(struct smi_port *port)
{
int ret = 0;
struct smi_dev *dev = port->dev;
struct i2c_adapter *i2c;
struct i2c_adapter *tuner_i2c_adapter;
struct i2c_client *client_tuner, *client_demod;
struct i2c_board_info client_info;
struct si2168_config si2168_config;
struct si2157_config si2157_config;
/* select i2c bus */
i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
/* attach demod */
memset(&si2168_config, 0, sizeof(si2168_config));
si2168_config.i2c_adapter = &tuner_i2c_adapter;
si2168_config.fe = &port->fe;
si2168_config.ts_mode = SI2168_TS_PARALLEL;
memset(&client_info, 0, sizeof(struct i2c_board_info));
strlcpy(client_info.type, "si2168", I2C_NAME_SIZE);
client_info.addr = 0x64;
client_info.platform_data = &si2168_config;
client_demod = smi_add_i2c_client(i2c, &client_info);
if (!client_demod) {
ret = -ENODEV;
return ret;
}
port->i2c_client_demod = client_demod;
/* attach tuner */
memset(&si2157_config, 0, sizeof(si2157_config));
si2157_config.fe = port->fe;
si2157_config.if_port = 1;
memset(&client_info, 0, sizeof(struct i2c_board_info));
strlcpy(client_info.type, "si2157", I2C_NAME_SIZE);
client_info.addr = 0x60;
client_info.platform_data = &si2157_config;
client_tuner = smi_add_i2c_client(tuner_i2c_adapter, &client_info);
if (!client_tuner) {
smi_del_i2c_client(port->i2c_client_demod);
port->i2c_client_demod = NULL;
ret = -ENODEV;
return ret;
}
port->i2c_client_tuner = client_tuner;
return ret;
}
static int smi_fe_init(struct smi_port *port)
{
int ret = 0;
struct smi_dev *dev = port->dev;
struct dvb_adapter *adap = &port->dvb_adapter;
u8 mac_ee[16];
dev_dbg(&port->dev->pci_dev->dev,
"%s: port %d, fe_type = %d\n",
__func__, port->idx, port->fe_type);
switch (port->fe_type) {
case DVBSKY_FE_M88DS3103:
ret = smi_dvbsky_m88ds3103_fe_attach(port);
break;
case DVBSKY_FE_M88RS6000:
ret = smi_dvbsky_m88rs6000_fe_attach(port);
break;
case DVBSKY_FE_SIT2:
ret = smi_dvbsky_sit2_fe_attach(port);
break;
}
if (ret < 0)
return ret;
/* register dvb frontend */
ret = dvb_register_frontend(adap, port->fe);
if (ret < 0) {
if (port->i2c_client_tuner)
smi_del_i2c_client(port->i2c_client_tuner);
if (port->i2c_client_demod)
smi_del_i2c_client(port->i2c_client_demod);
dvb_frontend_detach(port->fe);
return ret;
}
/* init MAC.*/
ret = smi_read_eeprom(&dev->i2c_bus[0], 0xc0, mac_ee, 16);
dev_info(&port->dev->pci_dev->dev,
"%s port %d MAC: %pM\n", dev->info->name,
port->idx, mac_ee + (port->idx)*8);
memcpy(adap->proposed_mac, mac_ee + (port->idx)*8, 6);
return ret;
}
static void smi_fe_exit(struct smi_port *port)
{
dvb_unregister_frontend(port->fe);
/* remove I2C demod and tuner */
if (port->i2c_client_tuner)
smi_del_i2c_client(port->i2c_client_tuner);
if (port->i2c_client_demod)
smi_del_i2c_client(port->i2c_client_demod);
dvb_frontend_detach(port->fe);
}
static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
int (*start_feed)(struct dvb_demux_feed *),
int (*stop_feed)(struct dvb_demux_feed *),
void *priv)
{
dvbdemux->priv = priv;
dvbdemux->filternum = 256;
dvbdemux->feednum = 256;
dvbdemux->start_feed = start_feed;
dvbdemux->stop_feed = stop_feed;
dvbdemux->write_to_decoder = NULL;
dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
DMX_SECTION_FILTERING |
DMX_MEMORY_BASED_FILTERING);
return dvb_dmx_init(dvbdemux);
}
static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
struct dvb_demux *dvbdemux,
struct dmx_frontend *hw_frontend,
struct dmx_frontend *mem_frontend,
struct dvb_adapter *dvb_adapter)
{
int ret;
dmxdev->filternum = 256;
dmxdev->demux = &dvbdemux->dmx;
dmxdev->capabilities = 0;
ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
if (ret < 0)
return ret;
hw_frontend->source = DMX_FRONTEND_0;
dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
mem_frontend->source = DMX_MEMORY_FE;
dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
}
static u32 smi_config_DMA(struct smi_port *port)
{
struct smi_dev *dev = port->dev;
u32 totalLength = 0, dmaMemPtrLow, dmaMemPtrHi, dmaCtlReg;
u8 chanLatencyTimer = 0, dmaChanEnable = 1, dmaTransStart = 1;
u32 dmaManagement = 0, tlpTransUnit = DMA_TRANS_UNIT_188;
u8 tlpTc = 0, tlpTd = 1, tlpEp = 0, tlpAttr = 0;
u64 mem;
dmaManagement = smi_read(port->DMA_MANAGEMENT);
/* Setup Channel-0 */
if (port->_dmaInterruptCH0) {
totalLength = SMI_TS_DMA_BUF_SIZE;
mem = port->dma_addr[0];
dmaMemPtrLow = mem & 0xffffffff;
dmaMemPtrHi = mem >> 32;
dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
| (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
dmaManagement |= dmaChanEnable | (dmaTransStart << 1)
| (chanLatencyTimer << 8);
/* write DMA register, start DMA engine */
smi_write(port->DMA_CHAN0_ADDR_LOW, dmaMemPtrLow);
smi_write(port->DMA_CHAN0_ADDR_HI, dmaMemPtrHi);
smi_write(port->DMA_CHAN0_CONTROL, dmaCtlReg);
}
/* Setup Channel-1 */
if (port->_dmaInterruptCH1) {
totalLength = SMI_TS_DMA_BUF_SIZE;
mem = port->dma_addr[1];
dmaMemPtrLow = mem & 0xffffffff;
dmaMemPtrHi = mem >> 32;
dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
| (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
dmaManagement |= (dmaChanEnable << 16) | (dmaTransStart << 17)
| (chanLatencyTimer << 24);
/* write DMA register, start DMA engine */
smi_write(port->DMA_CHAN1_ADDR_LOW, dmaMemPtrLow);
smi_write(port->DMA_CHAN1_ADDR_HI, dmaMemPtrHi);
smi_write(port->DMA_CHAN1_CONTROL, dmaCtlReg);
}
return dmaManagement;
}
static int smi_start_feed(struct dvb_demux_feed *dvbdmxfeed)
{
struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
struct smi_port *port = dvbdmx->priv;
struct smi_dev *dev = port->dev;
u32 dmaManagement;
if (port->users++ == 0) {
dmaManagement = smi_config_DMA(port);
smi_port_clearInterrupt(port);
smi_port_enableInterrupt(port);
smi_write(port->DMA_MANAGEMENT, dmaManagement);
tasklet_enable(&port->tasklet);
}
return port->users;
}
static int smi_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
{
struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
struct smi_port *port = dvbdmx->priv;
struct smi_dev *dev = port->dev;
if (--port->users)
return port->users;
tasklet_disable(&port->tasklet);
smi_port_disableInterrupt(port);
smi_clear(port->DMA_MANAGEMENT, 0x30003);
return 0;
}
static int smi_dvb_init(struct smi_port *port)
{
int ret;
struct dvb_adapter *adap = &port->dvb_adapter;
struct dvb_demux *dvbdemux = &port->demux;
dev_dbg(&port->dev->pci_dev->dev,
"%s, port %d\n", __func__, port->idx);
ret = dvb_register_adapter(adap, "SMI_DVB", THIS_MODULE,
&port->dev->pci_dev->dev,
adapter_nr);
if (ret < 0) {
dev_err(&port->dev->pci_dev->dev, "Fail to register DVB adapter.\n");
return ret;
}
ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
smi_start_feed,
smi_stop_feed, port);
if (ret < 0)
goto err_del_dvb_register_adapter;
ret = my_dvb_dmxdev_ts_card_init(&port->dmxdev, &port->demux,
&port->hw_frontend,
&port->mem_frontend, adap);
if (ret < 0)
goto err_del_dvb_dmx;
ret = dvb_net_init(adap, &port->dvbnet, port->dmxdev.demux);
if (ret < 0)
goto err_del_dvb_dmxdev;
return 0;
err_del_dvb_dmxdev:
dvbdemux->dmx.close(&dvbdemux->dmx);
dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
dvb_dmxdev_release(&port->dmxdev);
err_del_dvb_dmx:
dvb_dmx_release(&port->demux);
err_del_dvb_register_adapter:
dvb_unregister_adapter(&port->dvb_adapter);
return ret;
}
static void smi_dvb_exit(struct smi_port *port)
{
struct dvb_demux *dvbdemux = &port->demux;
dvb_net_release(&port->dvbnet);
dvbdemux->dmx.close(&dvbdemux->dmx);
dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
dvb_dmxdev_release(&port->dmxdev);
dvb_dmx_release(&port->demux);
dvb_unregister_adapter(&port->dvb_adapter);
}
static int smi_port_attach(struct smi_dev *dev,
struct smi_port *port, int index)
{
int ret, dmachs;
port->dev = dev;
port->idx = index;
port->fe_type = (index == 0) ? dev->info->fe_0 : dev->info->fe_1;
dmachs = (index == 0) ? dev->info->ts_0 : dev->info->ts_1;
/* port init.*/
ret = smi_port_init(port, dmachs);
if (ret < 0)
return ret;
/* dvb init.*/
ret = smi_dvb_init(port);
if (ret < 0)
goto err_del_port_init;
/* fe init.*/
ret = smi_fe_init(port);
if (ret < 0)
goto err_del_dvb_init;
return 0;
err_del_dvb_init:
smi_dvb_exit(port);
err_del_port_init:
smi_port_exit(port);
return ret;
}
static void smi_port_detach(struct smi_port *port)
{
smi_fe_exit(port);
smi_dvb_exit(port);
smi_port_exit(port);
}
static int smi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct smi_dev *dev;
int ret = -ENOMEM;
if (pci_enable_device(pdev) < 0)
return -ENODEV;
dev = kzalloc(sizeof(struct smi_dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
goto err_pci_disable_device;
}
dev->pci_dev = pdev;
pci_set_drvdata(pdev, dev);
dev->info = (struct smi_cfg_info *) id->driver_data;
dev_info(&dev->pci_dev->dev,
"card detected: %s\n", dev->info->name);
dev->nr = dev->info->type;
dev->lmmio = ioremap(pci_resource_start(dev->pci_dev, 0),
pci_resource_len(dev->pci_dev, 0));
if (!dev->lmmio) {
ret = -ENOMEM;
goto err_kfree;
}
/* should we set to 32bit DMA? */
ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
if (ret < 0)
goto err_pci_iounmap;
pci_set_master(pdev);
ret = smi_hw_init(dev);
if (ret < 0)
goto err_pci_iounmap;
ret = smi_i2c_init(dev);
if (ret < 0)
goto err_pci_iounmap;
if (dev->info->ts_0) {
ret = smi_port_attach(dev, &dev->ts_port[0], 0);
if (ret < 0)
goto err_del_i2c_adaptor;
}
if (dev->info->ts_1) {
ret = smi_port_attach(dev, &dev->ts_port[1], 1);
if (ret < 0)
goto err_del_port0_attach;
}
ret = smi_ir_init(dev);
if (ret < 0)
goto err_del_port1_attach;
#ifdef CONFIG_PCI_MSI /* to do msi interrupt.???*/
if (pci_msi_enabled())
ret = pci_enable_msi(dev->pci_dev);
if (ret)
dev_info(&dev->pci_dev->dev, "MSI not available.\n");
#endif
ret = request_irq(dev->pci_dev->irq, smi_irq_handler,
IRQF_SHARED, "SMI_PCIE", dev);
if (ret < 0)
goto err_del_ir;
smi_ir_start(&dev->ir);
return 0;
err_del_ir:
smi_ir_exit(dev);
err_del_port1_attach:
if (dev->info->ts_1)
smi_port_detach(&dev->ts_port[1]);
err_del_port0_attach:
if (dev->info->ts_0)
smi_port_detach(&dev->ts_port[0]);
err_del_i2c_adaptor:
smi_i2c_exit(dev);
err_pci_iounmap:
iounmap(dev->lmmio);
err_kfree:
pci_set_drvdata(pdev, NULL);
kfree(dev);
err_pci_disable_device:
pci_disable_device(pdev);
return ret;
}
static void smi_remove(struct pci_dev *pdev)
{
struct smi_dev *dev = pci_get_drvdata(pdev);
smi_write(MSI_INT_ENA_CLR, ALL_INT);
free_irq(dev->pci_dev->irq, dev);
#ifdef CONFIG_PCI_MSI
pci_disable_msi(dev->pci_dev);
#endif
if (dev->info->ts_1)
smi_port_detach(&dev->ts_port[1]);
if (dev->info->ts_0)
smi_port_detach(&dev->ts_port[0]);
smi_ir_exit(dev);
smi_i2c_exit(dev);
iounmap(dev->lmmio);
pci_set_drvdata(pdev, NULL);
pci_disable_device(pdev);
kfree(dev);
}
/* DVBSky cards */
static const struct smi_cfg_info dvbsky_s950_cfg = {
.type = SMI_DVBSKY_S950,
.name = "DVBSky S950 V3",
.ts_0 = SMI_TS_NULL,
.ts_1 = SMI_TS_DMA_BOTH,
.fe_0 = DVBSKY_FE_NULL,
.fe_1 = DVBSKY_FE_M88DS3103,
.rc_map = RC_MAP_DVBSKY,
};
static const struct smi_cfg_info dvbsky_s952_cfg = {
.type = SMI_DVBSKY_S952,
.name = "DVBSky S952 V3",
.ts_0 = SMI_TS_DMA_BOTH,
.ts_1 = SMI_TS_DMA_BOTH,
.fe_0 = DVBSKY_FE_M88RS6000,
.fe_1 = DVBSKY_FE_M88RS6000,
.rc_map = RC_MAP_DVBSKY,
};
static const struct smi_cfg_info dvbsky_t9580_cfg = {
.type = SMI_DVBSKY_T9580,
.name = "DVBSky T9580 V3",
.ts_0 = SMI_TS_DMA_BOTH,
.ts_1 = SMI_TS_DMA_BOTH,
.fe_0 = DVBSKY_FE_SIT2,
.fe_1 = DVBSKY_FE_M88DS3103,
.rc_map = RC_MAP_DVBSKY,
};
static const struct smi_cfg_info technotrend_s2_4200_cfg = {
.type = SMI_TECHNOTREND_S2_4200,
.name = "TechnoTrend TT-budget S2-4200 Twin",
.ts_0 = SMI_TS_DMA_BOTH,
.ts_1 = SMI_TS_DMA_BOTH,
.fe_0 = DVBSKY_FE_M88RS6000,
.fe_1 = DVBSKY_FE_M88RS6000,
.rc_map = RC_MAP_TT_1500,
};
/* PCI IDs */
#define SMI_ID(_subvend, _subdev, _driverdata) { \
.vendor = SMI_VID, .device = SMI_PID, \
.subvendor = _subvend, .subdevice = _subdev, \
.driver_data = (unsigned long)&_driverdata }
static const struct pci_device_id smi_id_table[] = {
SMI_ID(0x4254, 0x0550, dvbsky_s950_cfg),
SMI_ID(0x4254, 0x0552, dvbsky_s952_cfg),
SMI_ID(0x4254, 0x5580, dvbsky_t9580_cfg),
SMI_ID(0x13c2, 0x3016, technotrend_s2_4200_cfg),
{0}
};
MODULE_DEVICE_TABLE(pci, smi_id_table);
static struct pci_driver smipcie_driver = {
.name = "SMI PCIe driver",
.id_table = smi_id_table,
.probe = smi_probe,
.remove = smi_remove,
};
module_pci_driver(smipcie_driver);
MODULE_AUTHOR("Max nibble <nibble.max@gmail.com>");
MODULE_DESCRIPTION("SMI PCIe driver");
MODULE_LICENSE("GPL");
| null | null | null | null | 107,207 |
44,167 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 44,167 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2012 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef PPAPI_CPP_AUDIO_CONFIG_H_
#define PPAPI_CPP_AUDIO_CONFIG_H_
#include "ppapi/c/ppb_audio_config.h"
#include "ppapi/c/pp_stdint.h"
#include "ppapi/cpp/resource.h"
/// @file
/// This file defines the interface for establishing an
/// audio configuration resource within the browser.
namespace pp {
class InstanceHandle;
/// A 16 bit stereo AudioConfig resource. Refer to the
/// <a href="/native-client/devguide/coding/audio.html">Audio
/// </a>chapter in the Developer's Guide for information on using this
/// interface.
///
/// A single sample frame on a stereo device means one value for the left
/// channel and one value for the right channel.
///
/// Buffer layout for a stereo int16 configuration:
///
/// <code>int16_t *buffer16;</code>
/// <code>buffer16[0]</code> is the first left channel sample.
/// <code>buffer16[1]</code> is the first right channel sample.
/// <code>buffer16[2]</code> is the second left channel sample.
/// <code>buffer16[3]</code> is the second right channel sample.
/// <code>...</code>
/// <code>buffer16[2 * (sample_frame_count - 1)]</code> is the last left
/// channel sample.
/// <code>buffer16[2 * (sample_frame_count - 1) + 1]</code> is the last right
/// channel sample.
/// Data will always be in the native endian format of the platform.
///
/// <strong>Example:</strong>
/// @code
///
/// // Create an audio config with a supported frame count.
/// uint32_t sample_frame_count = AudioConfig::RecommendSampleFrameCount(
/// PP_AUDIOSAMPLERATE_44100, 4096);
/// AudioConfig config(PP_AUDIOSAMPLERATE_44100, sample_frame_count);
/// if (config.is_null())
/// return false; // Couldn't configure audio.
///
/// // Then use the config to create your audio resource.
/// Audio audio(instance, config, callback, user_data);
/// if (audio.is_null())
/// return false; // Couldn't create audio.
/// @endcode
class AudioConfig : public Resource {
public:
/// An empty constructor for an <code>AudioConfig</code> resource.
AudioConfig();
/// A constructor that creates an audio config based on the given sample rate
/// and frame count. If the rate and frame count aren't supported, the
/// resulting resource will be is_null(). You can pass the result of
/// RecommendSampleFrameCount() as the sample frame count.
///
/// @param[in] instance The instance associated with this resource.
///
/// @param[in] sample_rate A <code>PP_AudioSampleRate</code> which is either
/// <code>PP_AUDIOSAMPLERATE_44100</code> or
/// <code>PP_AUDIOSAMPLERATE_48000</code>.
///
/// @param[in] sample_frame_count A uint32_t frame count returned from the
/// <code>RecommendSampleFrameCount</code> function.
AudioConfig(const InstanceHandle& instance,
PP_AudioSampleRate sample_rate,
uint32_t sample_frame_count);
/// RecommendSampleRate() returns the native sample rate used by the
/// audio system. Applications that use the recommended sample rate might
/// obtain lower latency and higher fidelity output.
///
/// @param[in] instance The instance associated with this resource.
static PP_AudioSampleRate RecommendSampleRate(
const InstanceHandle& instance);
/// RecommendSampleFrameCount() returns a supported frame count closest to
/// the requested count. The sample frame count determines the overall
/// latency of audio. Smaller frame counts will yield lower latency, but
/// higher CPU utilization. Supported sample frame counts will vary by
/// hardware and system (consider that the local system might be anywhere
/// from a cell phone or a high-end audio workstation). Sample counts less
/// than <code>PP_AUDIOMINSAMPLEFRAMECOUNT</code> and greater than
/// <code>PP_AUDIOMAXSAMPLEFRAMECOUNT</code> are never supported on any
/// system, but values in between aren't necessarily valid. This function
/// will return a supported count closest to the requested value for use in
/// the constructor.
///
/// @param[in] instance The instance associated with this resource.
/// @param[in] sample_rate A <code>PP_AudioSampleRate</code> which is either
/// <code>PP_AUDIOSAMPLERATE_44100</code> or
/// <code>PP_AUDIOSAMPLERATE_48000</code>.
/// @param[in] requested_sample_frame_count A uint32_t requested frame count.
///
/// @return A uint32_t containing the recommended sample frame count if
/// successful. If the sample frame count or bit rate is not supported,
/// this function will fail and return 0.
static uint32_t RecommendSampleFrameCount(
const InstanceHandle& instance,
PP_AudioSampleRate sample_rate,
uint32_t requested_sample_frame_count);
/// Getter function for returning the internal
/// <code>PP_AudioSampleRate</code> enum.
///
/// @return The <code>PP_AudioSampleRate</code> enum.
PP_AudioSampleRate sample_rate() const { return sample_rate_; }
/// Getter function for returning the internal sample frame count.
///
/// @return A uint32_t containing the sample frame count.
uint32_t sample_frame_count() const { return sample_frame_count_; }
private:
PP_AudioSampleRate sample_rate_;
uint32_t sample_frame_count_;
};
} // namespace pp
#endif // PPAPI_CPP_AUDIO_CONFIG_H_
| null | null | null | null | 41,030 |
46,046 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 46,046 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "ash/wm/always_on_top_controller.h"
#include "ash/public/cpp/shell_window_ids.h"
#include "ash/root_window_controller.h"
#include "ash/shell.h"
#include "ash/test/ash_test_base.h"
#include "ash/wm/workspace/workspace_layout_manager.h"
#include "base/command_line.h"
#include "base/memory/ptr_util.h"
#include "ui/keyboard/keyboard_controller.h"
#include "ui/keyboard/keyboard_switches.h"
#include "ui/keyboard/keyboard_test_util.h"
#include "ui/keyboard/keyboard_ui.h"
namespace ash {
class VirtualKeyboardAlwaysOnTopControllerTest : public AshTestBase {
public:
VirtualKeyboardAlwaysOnTopControllerTest() = default;
~VirtualKeyboardAlwaysOnTopControllerTest() override = default;
void SetUp() override {
base::CommandLine::ForCurrentProcess()->AppendSwitch(
keyboard::switches::kEnableVirtualKeyboard);
AshTestBase::SetUp();
}
private:
DISALLOW_COPY_AND_ASSIGN(VirtualKeyboardAlwaysOnTopControllerTest);
};
class TestLayoutManager : public WorkspaceLayoutManager {
public:
explicit TestLayoutManager(aura::Window* window)
: WorkspaceLayoutManager(window), keyboard_bounds_changed_(false) {}
~TestLayoutManager() override = default;
void OnKeyboardWorkspaceDisplacingBoundsChanged(
const gfx::Rect& bounds) override {
keyboard_bounds_changed_ = true;
WorkspaceLayoutManager::OnKeyboardWorkspaceDisplacingBoundsChanged(bounds);
}
bool keyboard_bounds_changed() const { return keyboard_bounds_changed_; }
private:
bool keyboard_bounds_changed_;
DISALLOW_COPY_AND_ASSIGN(TestLayoutManager);
};
// Verifies that the always on top controller is notified of keyboard bounds
// changing events.
TEST_F(VirtualKeyboardAlwaysOnTopControllerTest, NotifyKeyboardBoundsChanged) {
keyboard::KeyboardController* keyboard_controller =
keyboard::KeyboardController::GetInstance();
aura::Window* root_window = Shell::GetPrimaryRootWindow();
aura::Window* always_on_top_container =
Shell::GetContainer(root_window, kShellWindowId_AlwaysOnTopContainer);
// Install test layout manager.
TestLayoutManager* manager = new TestLayoutManager(always_on_top_container);
RootWindowController* controller = Shell::GetPrimaryRootWindowController();
// Deactivates keyboard to unregister existing listeners.
controller->DeactivateKeyboard(keyboard_controller);
AlwaysOnTopController* always_on_top_controller =
controller->always_on_top_controller();
always_on_top_controller->SetLayoutManagerForTest(base::WrapUnique(manager));
// Activate keyboard. This triggers keyboard listeners to be registered.
controller->ActivateKeyboard(keyboard_controller);
// Mock a keyboard appearing.
aura::Window* keyboard_container = keyboard_controller->GetContainerWindow();
ASSERT_TRUE(keyboard_container);
keyboard_container->Show();
aura::Window* contents_window =
keyboard_controller->ui()->GetContentsWindow();
const int kKeyboardHeight = 200;
gfx::Rect keyboard_bounds = keyboard::KeyboardBoundsFromRootBounds(
root_window->bounds(), kKeyboardHeight);
contents_window->SetBounds(keyboard_bounds);
contents_window->Show();
keyboard_controller->NotifyContentsBoundsChanging(keyboard_bounds);
// Verify that test manager was notified of bounds change.
ASSERT_TRUE(manager->keyboard_bounds_changed());
}
} // namespace ash
| null | null | null | null | 42,909 |
6,121 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 6,121 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2017 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef CHROMEOS_COMPONENTS_TETHER_KEEP_ALIVE_OPERATION_H_
#define CHROMEOS_COMPONENTS_TETHER_KEEP_ALIVE_OPERATION_H_
#include "base/observer_list.h"
#include "base/time/clock.h"
#include "chromeos/components/tether/message_transfer_operation.h"
namespace chromeos {
namespace tether {
class BleConnectionManager;
// Operation which sends a keep-alive message to a tether host and receives an
// update about the host's status.
class KeepAliveOperation : public MessageTransferOperation {
public:
class Factory {
public:
static std::unique_ptr<KeepAliveOperation> NewInstance(
const cryptauth::RemoteDevice& device_to_connect,
BleConnectionManager* connection_manager);
static void SetInstanceForTesting(Factory* factory);
protected:
virtual std::unique_ptr<KeepAliveOperation> BuildInstance(
const cryptauth::RemoteDevice& device_to_connect,
BleConnectionManager* connection_manager);
private:
static Factory* factory_instance_;
};
class Observer {
public:
// |device_status| points to a valid DeviceStatus if the operation completed
// successfully and is null if the operation was not successful.
virtual void OnOperationFinished(
const cryptauth::RemoteDevice& remote_device,
std::unique_ptr<DeviceStatus> device_status) = 0;
};
~KeepAliveOperation() override;
void AddObserver(Observer* observer);
void RemoveObserver(Observer* observer);
protected:
KeepAliveOperation(const cryptauth::RemoteDevice& device_to_connect,
BleConnectionManager* connection_manager);
// MessageTransferOperation:
void OnDeviceAuthenticated(
const cryptauth::RemoteDevice& remote_device) override;
void OnMessageReceived(std::unique_ptr<MessageWrapper> message_wrapper,
const cryptauth::RemoteDevice& remote_device) override;
void OnOperationFinished() override;
MessageType GetMessageTypeForConnection() override;
std::unique_ptr<DeviceStatus> device_status_;
private:
friend class KeepAliveOperationTest;
void SetClockForTest(base::Clock* clock_for_test);
cryptauth::RemoteDevice remote_device_;
base::Clock* clock_;
base::ObserverList<Observer> observer_list_;
base::Time keep_alive_tickle_request_start_time_;
DISALLOW_COPY_AND_ASSIGN(KeepAliveOperation);
};
} // namespace tether
} // namespace chromeos
#endif // CHROMEOS_COMPONENTS_TETHER_KEEP_ALIVE_OPERATION_H_
| null | null | null | null | 2,984 |
22,916 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 187,911 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Driver for PowerMac Z85c30 based ESCC cell found in the
* "macio" ASICs of various PowerMac models
*
* Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
*
* Derived from drivers/macintosh/macserial.c by Paul Mackerras
* and drivers/serial/sunzilog.c by David S. Miller
*
* Hrm... actually, I ripped most of sunzilog (Thanks David !) and
* adapted special tweaks needed for us. I don't think it's worth
* merging back those though. The DMA code still has to get in
* and once done, I expect that driver to remain fairly stable in
* the long term, unless we change the driver model again...
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* 2004-08-06 Harald Welte <laforge@gnumonks.org>
* - Enable BREAK interrupt
* - Add support for sysreq
*
* TODO: - Add DMA support
* - Defer port shutdown to a few seconds after close
* - maybe put something right into uap->clk_divisor
*/
#undef DEBUG
#undef DEBUG_HARD
#undef USE_CTRL_O_SYSRQ
#include <linux/module.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/fcntl.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/adb.h>
#include <linux/pmu.h>
#include <linux/bitops.h>
#include <linux/sysrq.h>
#include <linux/mutex.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/sections.h>
#include <asm/io.h>
#include <asm/irq.h>
#ifdef CONFIG_PPC_PMAC
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/pmac_feature.h>
#include <asm/dbdma.h>
#include <asm/macio.h>
#else
#include <linux/platform_device.h>
#define of_machine_is_compatible(x) (0)
#endif
#if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif
#include <linux/serial.h>
#include <linux/serial_core.h>
#include "pmac_zilog.h"
/* Not yet implemented */
#undef HAS_DBDMA
static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
MODULE_LICENSE("GPL");
#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
#define PMACZILOG_MAJOR TTY_MAJOR
#define PMACZILOG_MINOR 64
#define PMACZILOG_NAME "ttyS"
#else
#define PMACZILOG_MAJOR 204
#define PMACZILOG_MINOR 192
#define PMACZILOG_NAME "ttyPZ"
#endif
#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
/*
* For the sake of early serial console, we can do a pre-probe
* (optional) of the ports at rather early boot time.
*/
static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
static int pmz_ports_count;
static struct uart_driver pmz_uart_reg = {
.owner = THIS_MODULE,
.driver_name = PMACZILOG_NAME,
.dev_name = PMACZILOG_NAME,
.major = PMACZILOG_MAJOR,
.minor = PMACZILOG_MINOR,
};
/*
* Load all registers to reprogram the port
* This function must only be called when the TX is not busy. The UART
* port lock must be held and local interrupts disabled.
*/
static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
{
int i;
/* Let pending transmits finish. */
for (i = 0; i < 1000; i++) {
unsigned char stat = read_zsreg(uap, R1);
if (stat & ALL_SNT)
break;
udelay(100);
}
ZS_CLEARERR(uap);
zssync(uap);
ZS_CLEARFIFO(uap);
zssync(uap);
ZS_CLEARERR(uap);
/* Disable all interrupts. */
write_zsreg(uap, R1,
regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
/* Set parity, sync config, stop bits, and clock divisor. */
write_zsreg(uap, R4, regs[R4]);
/* Set misc. TX/RX control bits. */
write_zsreg(uap, R10, regs[R10]);
/* Set TX/RX controls sans the enable bits. */
write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
/* now set R7 "prime" on ESCC */
write_zsreg(uap, R15, regs[R15] | EN85C30);
write_zsreg(uap, R7, regs[R7P]);
/* make sure we use R7 "non-prime" on ESCC */
write_zsreg(uap, R15, regs[R15] & ~EN85C30);
/* Synchronous mode config. */
write_zsreg(uap, R6, regs[R6]);
write_zsreg(uap, R7, regs[R7]);
/* Disable baud generator. */
write_zsreg(uap, R14, regs[R14] & ~BRENAB);
/* Clock mode control. */
write_zsreg(uap, R11, regs[R11]);
/* Lower and upper byte of baud rate generator divisor. */
write_zsreg(uap, R12, regs[R12]);
write_zsreg(uap, R13, regs[R13]);
/* Now rewrite R14, with BRENAB (if set). */
write_zsreg(uap, R14, regs[R14]);
/* Reset external status interrupts. */
write_zsreg(uap, R0, RES_EXT_INT);
write_zsreg(uap, R0, RES_EXT_INT);
/* Rewrite R3/R5, this time without enables masked. */
write_zsreg(uap, R3, regs[R3]);
write_zsreg(uap, R5, regs[R5]);
/* Rewrite R1, this time without IRQ enabled masked. */
write_zsreg(uap, R1, regs[R1]);
/* Enable interrupts */
write_zsreg(uap, R9, regs[R9]);
}
/*
* We do like sunzilog to avoid disrupting pending Tx
* Reprogram the Zilog channel HW registers with the copies found in the
* software state struct. If the transmitter is busy, we defer this update
* until the next TX complete interrupt. Else, we do it right now.
*
* The UART port lock must be held and local interrupts disabled.
*/
static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
{
if (!ZS_REGS_HELD(uap)) {
if (ZS_TX_ACTIVE(uap)) {
uap->flags |= PMACZILOG_FLAG_REGS_HELD;
} else {
pmz_debug("pmz: maybe_update_regs: updating\n");
pmz_load_zsregs(uap, uap->curregs);
}
}
}
static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
{
if (enable) {
uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
if (!ZS_IS_EXTCLK(uap))
uap->curregs[1] |= EXT_INT_ENAB;
} else {
uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
}
write_zsreg(uap, R1, uap->curregs[1]);
}
static bool pmz_receive_chars(struct uart_pmac_port *uap)
{
struct tty_port *port;
unsigned char ch, r1, drop, error, flag;
int loops = 0;
/* Sanity check, make sure the old bug is no longer happening */
if (uap->port.state == NULL) {
WARN_ON(1);
(void)read_zsdata(uap);
return false;
}
port = &uap->port.state->port;
while (1) {
error = 0;
drop = 0;
r1 = read_zsreg(uap, R1);
ch = read_zsdata(uap);
if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
write_zsreg(uap, R0, ERR_RES);
zssync(uap);
}
ch &= uap->parity_mask;
if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
uap->flags &= ~PMACZILOG_FLAG_BREAK;
}
#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
#ifdef USE_CTRL_O_SYSRQ
/* Handle the SysRq ^O Hack */
if (ch == '\x0f') {
uap->port.sysrq = jiffies + HZ*5;
goto next_char;
}
#endif /* USE_CTRL_O_SYSRQ */
if (uap->port.sysrq) {
int swallow;
spin_unlock(&uap->port.lock);
swallow = uart_handle_sysrq_char(&uap->port, ch);
spin_lock(&uap->port.lock);
if (swallow)
goto next_char;
}
#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
/* A real serial line, record the character and status. */
if (drop)
goto next_char;
flag = TTY_NORMAL;
uap->port.icount.rx++;
if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
error = 1;
if (r1 & BRK_ABRT) {
pmz_debug("pmz: got break !\n");
r1 &= ~(PAR_ERR | CRC_ERR);
uap->port.icount.brk++;
if (uart_handle_break(&uap->port))
goto next_char;
}
else if (r1 & PAR_ERR)
uap->port.icount.parity++;
else if (r1 & CRC_ERR)
uap->port.icount.frame++;
if (r1 & Rx_OVR)
uap->port.icount.overrun++;
r1 &= uap->port.read_status_mask;
if (r1 & BRK_ABRT)
flag = TTY_BREAK;
else if (r1 & PAR_ERR)
flag = TTY_PARITY;
else if (r1 & CRC_ERR)
flag = TTY_FRAME;
}
if (uap->port.ignore_status_mask == 0xff ||
(r1 & uap->port.ignore_status_mask) == 0) {
tty_insert_flip_char(port, ch, flag);
}
if (r1 & Rx_OVR)
tty_insert_flip_char(port, 0, TTY_OVERRUN);
next_char:
/* We can get stuck in an infinite loop getting char 0 when the
* line is in a wrong HW state, we break that here.
* When that happens, I disable the receive side of the driver.
* Note that what I've been experiencing is a real irq loop where
* I'm getting flooded regardless of the actual port speed.
* Something strange is going on with the HW
*/
if ((++loops) > 1000)
goto flood;
ch = read_zsreg(uap, R0);
if (!(ch & Rx_CH_AV))
break;
}
return true;
flood:
pmz_interrupt_control(uap, 0);
pmz_error("pmz: rx irq flood !\n");
return true;
}
static void pmz_status_handle(struct uart_pmac_port *uap)
{
unsigned char status;
status = read_zsreg(uap, R0);
write_zsreg(uap, R0, RES_EXT_INT);
zssync(uap);
if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
if (status & SYNC_HUNT)
uap->port.icount.dsr++;
/* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
* But it does not tell us which bit has changed, we have to keep
* track of this ourselves.
* The CTS input is inverted for some reason. -- paulus
*/
if ((status ^ uap->prev_status) & DCD)
uart_handle_dcd_change(&uap->port,
(status & DCD));
if ((status ^ uap->prev_status) & CTS)
uart_handle_cts_change(&uap->port,
!(status & CTS));
wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
}
if (status & BRK_ABRT)
uap->flags |= PMACZILOG_FLAG_BREAK;
uap->prev_status = status;
}
static void pmz_transmit_chars(struct uart_pmac_port *uap)
{
struct circ_buf *xmit;
if (ZS_IS_CONS(uap)) {
unsigned char status = read_zsreg(uap, R0);
/* TX still busy? Just wait for the next TX done interrupt.
*
* It can occur because of how we do serial console writes. It would
* be nice to transmit console writes just like we normally would for
* a TTY line. (ie. buffered and TX interrupt driven). That is not
* easy because console writes cannot sleep. One solution might be
* to poll on enough port->xmit space becoming free. -DaveM
*/
if (!(status & Tx_BUF_EMP))
return;
}
uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
if (ZS_REGS_HELD(uap)) {
pmz_load_zsregs(uap, uap->curregs);
uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
}
if (ZS_TX_STOPPED(uap)) {
uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
goto ack_tx_int;
}
/* Under some circumstances, we see interrupts reported for
* a closed channel. The interrupt mask in R1 is clear, but
* R3 still signals the interrupts and we see them when taking
* an interrupt for the other channel (this could be a qemu
* bug but since the ESCC doc doesn't specify precsiely whether
* R3 interrup status bits are masked by R1 interrupt enable
* bits, better safe than sorry). --BenH.
*/
if (!ZS_IS_OPEN(uap))
goto ack_tx_int;
if (uap->port.x_char) {
uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
write_zsdata(uap, uap->port.x_char);
zssync(uap);
uap->port.icount.tx++;
uap->port.x_char = 0;
return;
}
if (uap->port.state == NULL)
goto ack_tx_int;
xmit = &uap->port.state->xmit;
if (uart_circ_empty(xmit)) {
uart_write_wakeup(&uap->port);
goto ack_tx_int;
}
if (uart_tx_stopped(&uap->port))
goto ack_tx_int;
uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
write_zsdata(uap, xmit->buf[xmit->tail]);
zssync(uap);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
uap->port.icount.tx++;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&uap->port);
return;
ack_tx_int:
write_zsreg(uap, R0, RES_Tx_P);
zssync(uap);
}
/* Hrm... we register that twice, fixme later.... */
static irqreturn_t pmz_interrupt(int irq, void *dev_id)
{
struct uart_pmac_port *uap = dev_id;
struct uart_pmac_port *uap_a;
struct uart_pmac_port *uap_b;
int rc = IRQ_NONE;
bool push;
u8 r3;
uap_a = pmz_get_port_A(uap);
uap_b = uap_a->mate;
spin_lock(&uap_a->port.lock);
r3 = read_zsreg(uap_a, R3);
#ifdef DEBUG_HARD
pmz_debug("irq, r3: %x\n", r3);
#endif
/* Channel A */
push = false;
if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
if (!ZS_IS_OPEN(uap_a)) {
pmz_debug("ChanA interrupt while not open !\n");
goto skip_a;
}
write_zsreg(uap_a, R0, RES_H_IUS);
zssync(uap_a);
if (r3 & CHAEXT)
pmz_status_handle(uap_a);
if (r3 & CHARxIP)
push = pmz_receive_chars(uap_a);
if (r3 & CHATxIP)
pmz_transmit_chars(uap_a);
rc = IRQ_HANDLED;
}
skip_a:
spin_unlock(&uap_a->port.lock);
if (push)
tty_flip_buffer_push(&uap->port.state->port);
if (!uap_b)
goto out;
spin_lock(&uap_b->port.lock);
push = false;
if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
if (!ZS_IS_OPEN(uap_b)) {
pmz_debug("ChanB interrupt while not open !\n");
goto skip_b;
}
write_zsreg(uap_b, R0, RES_H_IUS);
zssync(uap_b);
if (r3 & CHBEXT)
pmz_status_handle(uap_b);
if (r3 & CHBRxIP)
push = pmz_receive_chars(uap_b);
if (r3 & CHBTxIP)
pmz_transmit_chars(uap_b);
rc = IRQ_HANDLED;
}
skip_b:
spin_unlock(&uap_b->port.lock);
if (push)
tty_flip_buffer_push(&uap->port.state->port);
out:
return rc;
}
/*
* Peek the status register, lock not held by caller
*/
static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
{
unsigned long flags;
u8 status;
spin_lock_irqsave(&uap->port.lock, flags);
status = read_zsreg(uap, R0);
spin_unlock_irqrestore(&uap->port.lock, flags);
return status;
}
/*
* Check if transmitter is empty
* The port lock is not held.
*/
static unsigned int pmz_tx_empty(struct uart_port *port)
{
unsigned char status;
status = pmz_peek_status(to_pmz(port));
if (status & Tx_BUF_EMP)
return TIOCSER_TEMT;
return 0;
}
/*
* Set Modem Control (RTS & DTR) bits
* The port lock is held and interrupts are disabled.
* Note: Shall we really filter out RTS on external ports or
* should that be dealt at higher level only ?
*/
static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned char set_bits, clear_bits;
/* Do nothing for irda for now... */
if (ZS_IS_IRDA(uap))
return;
/* We get called during boot with a port not up yet */
if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
return;
set_bits = clear_bits = 0;
if (ZS_IS_INTMODEM(uap)) {
if (mctrl & TIOCM_RTS)
set_bits |= RTS;
else
clear_bits |= RTS;
}
if (mctrl & TIOCM_DTR)
set_bits |= DTR;
else
clear_bits |= DTR;
/* NOTE: Not subject to 'transmitter active' rule. */
uap->curregs[R5] |= set_bits;
uap->curregs[R5] &= ~clear_bits;
write_zsreg(uap, R5, uap->curregs[R5]);
pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
set_bits, clear_bits, uap->curregs[R5]);
zssync(uap);
}
/*
* Get Modem Control bits (only the input ones, the core will
* or that with a cached value of the control ones)
* The port lock is held and interrupts are disabled.
*/
static unsigned int pmz_get_mctrl(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned char status;
unsigned int ret;
status = read_zsreg(uap, R0);
ret = 0;
if (status & DCD)
ret |= TIOCM_CAR;
if (status & SYNC_HUNT)
ret |= TIOCM_DSR;
if (!(status & CTS))
ret |= TIOCM_CTS;
return ret;
}
/*
* Stop TX side. Dealt like sunzilog at next Tx interrupt,
* though for DMA, we will have to do a bit more.
* The port lock is held and interrupts are disabled.
*/
static void pmz_stop_tx(struct uart_port *port)
{
to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
}
/*
* Kick the Tx side.
* The port lock is held and interrupts are disabled.
*/
static void pmz_start_tx(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned char status;
pmz_debug("pmz: start_tx()\n");
uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
status = read_zsreg(uap, R0);
/* TX busy? Just wait for the TX done interrupt. */
if (!(status & Tx_BUF_EMP))
return;
/* Send the first character to jump-start the TX done
* IRQ sending engine.
*/
if (port->x_char) {
write_zsdata(uap, port->x_char);
zssync(uap);
port->icount.tx++;
port->x_char = 0;
} else {
struct circ_buf *xmit = &port->state->xmit;
if (uart_circ_empty(xmit))
goto out;
write_zsdata(uap, xmit->buf[xmit->tail]);
zssync(uap);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&uap->port);
}
out:
pmz_debug("pmz: start_tx() done.\n");
}
/*
* Stop Rx side, basically disable emitting of
* Rx interrupts on the port. We don't disable the rx
* side of the chip proper though
* The port lock is held.
*/
static void pmz_stop_rx(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
pmz_debug("pmz: stop_rx()()\n");
/* Disable all RX interrupts. */
uap->curregs[R1] &= ~RxINT_MASK;
pmz_maybe_update_regs(uap);
pmz_debug("pmz: stop_rx() done.\n");
}
/*
* Enable modem status change interrupts
* The port lock is held.
*/
static void pmz_enable_ms(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned char new_reg;
if (ZS_IS_IRDA(uap))
return;
new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
if (new_reg != uap->curregs[R15]) {
uap->curregs[R15] = new_reg;
/* NOTE: Not subject to 'transmitter active' rule. */
write_zsreg(uap, R15, uap->curregs[R15]);
}
}
/*
* Control break state emission
* The port lock is not held.
*/
static void pmz_break_ctl(struct uart_port *port, int break_state)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned char set_bits, clear_bits, new_reg;
unsigned long flags;
set_bits = clear_bits = 0;
if (break_state)
set_bits |= SND_BRK;
else
clear_bits |= SND_BRK;
spin_lock_irqsave(&port->lock, flags);
new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
if (new_reg != uap->curregs[R5]) {
uap->curregs[R5] = new_reg;
write_zsreg(uap, R5, uap->curregs[R5]);
}
spin_unlock_irqrestore(&port->lock, flags);
}
#ifdef CONFIG_PPC_PMAC
/*
* Turn power on or off to the SCC and associated stuff
* (port drivers, modem, IR port, etc.)
* Returns the number of milliseconds we should wait before
* trying to use the port.
*/
static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
{
int delay = 0;
int rc;
if (state) {
rc = pmac_call_feature(
PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
pmz_debug("port power on result: %d\n", rc);
if (ZS_IS_INTMODEM(uap)) {
rc = pmac_call_feature(
PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
delay = 2500; /* wait for 2.5s before using */
pmz_debug("modem power result: %d\n", rc);
}
} else {
/* TODO: Make that depend on a timer, don't power down
* immediately
*/
if (ZS_IS_INTMODEM(uap)) {
rc = pmac_call_feature(
PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
pmz_debug("port power off result: %d\n", rc);
}
pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
}
return delay;
}
#else
static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
{
return 0;
}
#endif /* !CONFIG_PPC_PMAC */
/*
* FixZeroBug....Works around a bug in the SCC receiving channel.
* Inspired from Darwin code, 15 Sept. 2000 -DanM
*
* The following sequence prevents a problem that is seen with O'Hare ASICs
* (most versions -- also with some Heathrow and Hydra ASICs) where a zero
* at the input to the receiver becomes 'stuck' and locks up the receiver.
* This problem can occur as a result of a zero bit at the receiver input
* coincident with any of the following events:
*
* The SCC is initialized (hardware or software).
* A framing error is detected.
* The clocking option changes from synchronous or X1 asynchronous
* clocking to X16, X32, or X64 asynchronous clocking.
* The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
*
* This workaround attempts to recover from the lockup condition by placing
* the SCC in synchronous loopback mode with a fast clock before programming
* any of the asynchronous modes.
*/
static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
{
write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
zssync(uap);
udelay(10);
write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
zssync(uap);
write_zsreg(uap, 4, X1CLK | MONSYNC);
write_zsreg(uap, 3, Rx8);
write_zsreg(uap, 5, Tx8 | RTS);
write_zsreg(uap, 9, NV); /* Didn't we already do this? */
write_zsreg(uap, 11, RCBR | TCBR);
write_zsreg(uap, 12, 0);
write_zsreg(uap, 13, 0);
write_zsreg(uap, 14, (LOOPBAK | BRSRC));
write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
write_zsreg(uap, 3, Rx8 | RxENABLE);
write_zsreg(uap, 0, RES_EXT_INT);
write_zsreg(uap, 0, RES_EXT_INT);
write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
/* The channel should be OK now, but it is probably receiving
* loopback garbage.
* Switch to asynchronous mode, disable the receiver,
* and discard everything in the receive buffer.
*/
write_zsreg(uap, 9, NV);
write_zsreg(uap, 4, X16CLK | SB_MASK);
write_zsreg(uap, 3, Rx8);
while (read_zsreg(uap, 0) & Rx_CH_AV) {
(void)read_zsreg(uap, 8);
write_zsreg(uap, 0, RES_EXT_INT);
write_zsreg(uap, 0, ERR_RES);
}
}
/*
* Real startup routine, powers up the hardware and sets up
* the SCC. Returns a delay in ms where you need to wait before
* actually using the port, this is typically the internal modem
* powerup delay. This routine expect the lock to be taken.
*/
static int __pmz_startup(struct uart_pmac_port *uap)
{
int pwr_delay = 0;
memset(&uap->curregs, 0, sizeof(uap->curregs));
/* Power up the SCC & underlying hardware (modem/irda) */
pwr_delay = pmz_set_scc_power(uap, 1);
/* Nice buggy HW ... */
pmz_fix_zero_bug_scc(uap);
/* Reset the channel */
uap->curregs[R9] = 0;
write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
zssync(uap);
udelay(10);
write_zsreg(uap, 9, 0);
zssync(uap);
/* Clear the interrupt registers */
write_zsreg(uap, R1, 0);
write_zsreg(uap, R0, ERR_RES);
write_zsreg(uap, R0, ERR_RES);
write_zsreg(uap, R0, RES_H_IUS);
write_zsreg(uap, R0, RES_H_IUS);
/* Setup some valid baud rate */
uap->curregs[R4] = X16CLK | SB1;
uap->curregs[R3] = Rx8;
uap->curregs[R5] = Tx8 | RTS;
if (!ZS_IS_IRDA(uap))
uap->curregs[R5] |= DTR;
uap->curregs[R12] = 0;
uap->curregs[R13] = 0;
uap->curregs[R14] = BRENAB;
/* Clear handshaking, enable BREAK interrupts */
uap->curregs[R15] = BRKIE;
/* Master interrupt enable */
uap->curregs[R9] |= NV | MIE;
pmz_load_zsregs(uap, uap->curregs);
/* Enable receiver and transmitter. */
write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
/* Remember status for DCD/CTS changes */
uap->prev_status = read_zsreg(uap, R0);
return pwr_delay;
}
static void pmz_irda_reset(struct uart_pmac_port *uap)
{
unsigned long flags;
spin_lock_irqsave(&uap->port.lock, flags);
uap->curregs[R5] |= DTR;
write_zsreg(uap, R5, uap->curregs[R5]);
zssync(uap);
spin_unlock_irqrestore(&uap->port.lock, flags);
msleep(110);
spin_lock_irqsave(&uap->port.lock, flags);
uap->curregs[R5] &= ~DTR;
write_zsreg(uap, R5, uap->curregs[R5]);
zssync(uap);
spin_unlock_irqrestore(&uap->port.lock, flags);
msleep(10);
}
/*
* This is the "normal" startup routine, using the above one
* wrapped with the lock and doing a schedule delay
*/
static int pmz_startup(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned long flags;
int pwr_delay = 0;
pmz_debug("pmz: startup()\n");
uap->flags |= PMACZILOG_FLAG_IS_OPEN;
/* A console is never powered down. Else, power up and
* initialize the chip
*/
if (!ZS_IS_CONS(uap)) {
spin_lock_irqsave(&port->lock, flags);
pwr_delay = __pmz_startup(uap);
spin_unlock_irqrestore(&port->lock, flags);
}
sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
uap->irq_name, uap)) {
pmz_error("Unable to register zs interrupt handler.\n");
pmz_set_scc_power(uap, 0);
return -ENXIO;
}
/* Right now, we deal with delay by blocking here, I'll be
* smarter later on
*/
if (pwr_delay != 0) {
pmz_debug("pmz: delaying %d ms\n", pwr_delay);
msleep(pwr_delay);
}
/* IrDA reset is done now */
if (ZS_IS_IRDA(uap))
pmz_irda_reset(uap);
/* Enable interrupt requests for the channel */
spin_lock_irqsave(&port->lock, flags);
pmz_interrupt_control(uap, 1);
spin_unlock_irqrestore(&port->lock, flags);
pmz_debug("pmz: startup() done.\n");
return 0;
}
static void pmz_shutdown(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned long flags;
pmz_debug("pmz: shutdown()\n");
spin_lock_irqsave(&port->lock, flags);
/* Disable interrupt requests for the channel */
pmz_interrupt_control(uap, 0);
if (!ZS_IS_CONS(uap)) {
/* Disable receiver and transmitter */
uap->curregs[R3] &= ~RxENABLE;
uap->curregs[R5] &= ~TxENABLE;
/* Disable break assertion */
uap->curregs[R5] &= ~SND_BRK;
pmz_maybe_update_regs(uap);
}
spin_unlock_irqrestore(&port->lock, flags);
/* Release interrupt handler */
free_irq(uap->port.irq, uap);
spin_lock_irqsave(&port->lock, flags);
uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
if (!ZS_IS_CONS(uap))
pmz_set_scc_power(uap, 0); /* Shut the chip down */
spin_unlock_irqrestore(&port->lock, flags);
pmz_debug("pmz: shutdown() done.\n");
}
/* Shared by TTY driver and serial console setup. The port lock is held
* and local interrupts are disabled.
*/
static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
unsigned int iflag, unsigned long baud)
{
int brg;
/* Switch to external clocking for IrDA high clock rates. That
* code could be re-used for Midi interfaces with different
* multipliers
*/
if (baud >= 115200 && ZS_IS_IRDA(uap)) {
uap->curregs[R4] = X1CLK;
uap->curregs[R11] = RCTRxCP | TCTRxCP;
uap->curregs[R14] = 0; /* BRG off */
uap->curregs[R12] = 0;
uap->curregs[R13] = 0;
uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
} else {
switch (baud) {
case ZS_CLOCK/16: /* 230400 */
uap->curregs[R4] = X16CLK;
uap->curregs[R11] = 0;
uap->curregs[R14] = 0;
break;
case ZS_CLOCK/32: /* 115200 */
uap->curregs[R4] = X32CLK;
uap->curregs[R11] = 0;
uap->curregs[R14] = 0;
break;
default:
uap->curregs[R4] = X16CLK;
uap->curregs[R11] = TCBR | RCBR;
brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
uap->curregs[R12] = (brg & 255);
uap->curregs[R13] = ((brg >> 8) & 255);
uap->curregs[R14] = BRENAB;
}
uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
}
/* Character size, stop bits, and parity. */
uap->curregs[3] &= ~RxN_MASK;
uap->curregs[5] &= ~TxN_MASK;
switch (cflag & CSIZE) {
case CS5:
uap->curregs[3] |= Rx5;
uap->curregs[5] |= Tx5;
uap->parity_mask = 0x1f;
break;
case CS6:
uap->curregs[3] |= Rx6;
uap->curregs[5] |= Tx6;
uap->parity_mask = 0x3f;
break;
case CS7:
uap->curregs[3] |= Rx7;
uap->curregs[5] |= Tx7;
uap->parity_mask = 0x7f;
break;
case CS8:
default:
uap->curregs[3] |= Rx8;
uap->curregs[5] |= Tx8;
uap->parity_mask = 0xff;
break;
}
uap->curregs[4] &= ~(SB_MASK);
if (cflag & CSTOPB)
uap->curregs[4] |= SB2;
else
uap->curregs[4] |= SB1;
if (cflag & PARENB)
uap->curregs[4] |= PAR_ENAB;
else
uap->curregs[4] &= ~PAR_ENAB;
if (!(cflag & PARODD))
uap->curregs[4] |= PAR_EVEN;
else
uap->curregs[4] &= ~PAR_EVEN;
uap->port.read_status_mask = Rx_OVR;
if (iflag & INPCK)
uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
if (iflag & (IGNBRK | BRKINT | PARMRK))
uap->port.read_status_mask |= BRK_ABRT;
uap->port.ignore_status_mask = 0;
if (iflag & IGNPAR)
uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
if (iflag & IGNBRK) {
uap->port.ignore_status_mask |= BRK_ABRT;
if (iflag & IGNPAR)
uap->port.ignore_status_mask |= Rx_OVR;
}
if ((cflag & CREAD) == 0)
uap->port.ignore_status_mask = 0xff;
}
/*
* Set the irda codec on the imac to the specified baud rate.
*/
static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
{
u8 cmdbyte;
int t, version;
switch (*baud) {
/* SIR modes */
case 2400:
cmdbyte = 0x53;
break;
case 4800:
cmdbyte = 0x52;
break;
case 9600:
cmdbyte = 0x51;
break;
case 19200:
cmdbyte = 0x50;
break;
case 38400:
cmdbyte = 0x4f;
break;
case 57600:
cmdbyte = 0x4e;
break;
case 115200:
cmdbyte = 0x4d;
break;
/* The FIR modes aren't really supported at this point, how
* do we select the speed ? via the FCR on KeyLargo ?
*/
case 1152000:
cmdbyte = 0;
break;
case 4000000:
cmdbyte = 0;
break;
default: /* 9600 */
cmdbyte = 0x51;
*baud = 9600;
break;
}
/* Wait for transmitter to drain */
t = 10000;
while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
|| (read_zsreg(uap, R1) & ALL_SNT) == 0) {
if (--t <= 0) {
pmz_error("transmitter didn't drain\n");
return;
}
udelay(10);
}
/* Drain the receiver too */
t = 100;
(void)read_zsdata(uap);
(void)read_zsdata(uap);
(void)read_zsdata(uap);
mdelay(10);
while (read_zsreg(uap, R0) & Rx_CH_AV) {
read_zsdata(uap);
mdelay(10);
if (--t <= 0) {
pmz_error("receiver didn't drain\n");
return;
}
}
/* Switch to command mode */
uap->curregs[R5] |= DTR;
write_zsreg(uap, R5, uap->curregs[R5]);
zssync(uap);
mdelay(1);
/* Switch SCC to 19200 */
pmz_convert_to_zs(uap, CS8, 0, 19200);
pmz_load_zsregs(uap, uap->curregs);
mdelay(1);
/* Write get_version command byte */
write_zsdata(uap, 1);
t = 5000;
while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
if (--t <= 0) {
pmz_error("irda_setup timed out on get_version byte\n");
goto out;
}
udelay(10);
}
version = read_zsdata(uap);
if (version < 4) {
pmz_info("IrDA: dongle version %d not supported\n", version);
goto out;
}
/* Send speed mode */
write_zsdata(uap, cmdbyte);
t = 5000;
while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
if (--t <= 0) {
pmz_error("irda_setup timed out on speed mode byte\n");
goto out;
}
udelay(10);
}
t = read_zsdata(uap);
if (t != cmdbyte)
pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
*baud, version);
(void)read_zsdata(uap);
(void)read_zsdata(uap);
(void)read_zsdata(uap);
out:
/* Switch back to data mode */
uap->curregs[R5] &= ~DTR;
write_zsreg(uap, R5, uap->curregs[R5]);
zssync(uap);
(void)read_zsdata(uap);
(void)read_zsdata(uap);
(void)read_zsdata(uap);
}
static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
struct ktermios *old)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned long baud;
pmz_debug("pmz: set_termios()\n");
memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
/* XXX Check which revs of machines actually allow 1 and 4Mb speeds
* on the IR dongle. Note that the IRTTY driver currently doesn't know
* about the FIR mode and high speed modes. So these are unused. For
* implementing proper support for these, we should probably add some
* DMA as well, at least on the Rx side, which isn't a simple thing
* at this point.
*/
if (ZS_IS_IRDA(uap)) {
/* Calc baud rate */
baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
/* Cet the irda codec to the right rate */
pmz_irda_setup(uap, &baud);
/* Set final baud rate */
pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
pmz_load_zsregs(uap, uap->curregs);
zssync(uap);
} else {
baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
/* Make sure modem status interrupts are correctly configured */
if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
} else {
uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
}
/* Load registers to the chip */
pmz_maybe_update_regs(uap);
}
uart_update_timeout(port, termios->c_cflag, baud);
pmz_debug("pmz: set_termios() done.\n");
}
/* The port lock is not held. */
static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
struct ktermios *old)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
/* Disable IRQs on the port */
pmz_interrupt_control(uap, 0);
/* Setup new port configuration */
__pmz_set_termios(port, termios, old);
/* Re-enable IRQs on the port */
if (ZS_IS_OPEN(uap))
pmz_interrupt_control(uap, 1);
spin_unlock_irqrestore(&port->lock, flags);
}
static const char *pmz_type(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
if (ZS_IS_IRDA(uap))
return "Z85c30 ESCC - Infrared port";
else if (ZS_IS_INTMODEM(uap))
return "Z85c30 ESCC - Internal modem";
return "Z85c30 ESCC - Serial port";
}
/* We do not request/release mappings of the registers here, this
* happens at early serial probe time.
*/
static void pmz_release_port(struct uart_port *port)
{
}
static int pmz_request_port(struct uart_port *port)
{
return 0;
}
/* These do not need to do anything interesting either. */
static void pmz_config_port(struct uart_port *port, int flags)
{
}
/* We do not support letting the user mess with the divisor, IRQ, etc. */
static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
{
return -EINVAL;
}
#ifdef CONFIG_CONSOLE_POLL
static int pmz_poll_get_char(struct uart_port *port)
{
struct uart_pmac_port *uap =
container_of(port, struct uart_pmac_port, port);
int tries = 2;
while (tries) {
if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)
return read_zsdata(uap);
if (tries--)
udelay(5);
}
return NO_POLL_CHAR;
}
static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
{
struct uart_pmac_port *uap =
container_of(port, struct uart_pmac_port, port);
/* Wait for the transmit buffer to empty. */
while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
udelay(5);
write_zsdata(uap, c);
}
#endif /* CONFIG_CONSOLE_POLL */
static const struct uart_ops pmz_pops = {
.tx_empty = pmz_tx_empty,
.set_mctrl = pmz_set_mctrl,
.get_mctrl = pmz_get_mctrl,
.stop_tx = pmz_stop_tx,
.start_tx = pmz_start_tx,
.stop_rx = pmz_stop_rx,
.enable_ms = pmz_enable_ms,
.break_ctl = pmz_break_ctl,
.startup = pmz_startup,
.shutdown = pmz_shutdown,
.set_termios = pmz_set_termios,
.type = pmz_type,
.release_port = pmz_release_port,
.request_port = pmz_request_port,
.config_port = pmz_config_port,
.verify_port = pmz_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = pmz_poll_get_char,
.poll_put_char = pmz_poll_put_char,
#endif
};
#ifdef CONFIG_PPC_PMAC
/*
* Setup one port structure after probing, HW is down at this point,
* Unlike sunzilog, we don't need to pre-init the spinlock as we don't
* register our console before uart_add_one_port() is called
*/
static int __init pmz_init_port(struct uart_pmac_port *uap)
{
struct device_node *np = uap->node;
const char *conn;
const struct slot_names_prop {
int count;
char name[1];
} *slots;
int len;
struct resource r_ports, r_rxdma, r_txdma;
/*
* Request & map chip registers
*/
if (of_address_to_resource(np, 0, &r_ports))
return -ENODEV;
uap->port.mapbase = r_ports.start;
uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
uap->control_reg = uap->port.membase;
uap->data_reg = uap->control_reg + 0x10;
/*
* Request & map DBDMA registers
*/
#ifdef HAS_DBDMA
if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
of_address_to_resource(np, 2, &r_rxdma) == 0)
uap->flags |= PMACZILOG_FLAG_HAS_DMA;
#else
memset(&r_txdma, 0, sizeof(struct resource));
memset(&r_rxdma, 0, sizeof(struct resource));
#endif
if (ZS_HAS_DMA(uap)) {
uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
if (uap->tx_dma_regs == NULL) {
uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
goto no_dma;
}
uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
if (uap->rx_dma_regs == NULL) {
iounmap(uap->tx_dma_regs);
uap->tx_dma_regs = NULL;
uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
goto no_dma;
}
uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
}
no_dma:
/*
* Detect port type
*/
if (of_device_is_compatible(np, "cobalt"))
uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
conn = of_get_property(np, "AAPL,connector", &len);
if (conn && (strcmp(conn, "infrared") == 0))
uap->flags |= PMACZILOG_FLAG_IS_IRDA;
uap->port_type = PMAC_SCC_ASYNC;
/* 1999 Powerbook G3 has slot-names property instead */
slots = of_get_property(np, "slot-names", &len);
if (slots && slots->count > 0) {
if (strcmp(slots->name, "IrDA") == 0)
uap->flags |= PMACZILOG_FLAG_IS_IRDA;
else if (strcmp(slots->name, "Modem") == 0)
uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
}
if (ZS_IS_IRDA(uap))
uap->port_type = PMAC_SCC_IRDA;
if (ZS_IS_INTMODEM(uap)) {
struct device_node* i2c_modem =
of_find_node_by_name(NULL, "i2c-modem");
if (i2c_modem) {
const char* mid =
of_get_property(i2c_modem, "modem-id", NULL);
if (mid) switch(*mid) {
case 0x04 :
case 0x05 :
case 0x07 :
case 0x08 :
case 0x0b :
case 0x0c :
uap->port_type = PMAC_SCC_I2S1;
}
printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
mid ? (*mid) : 0);
of_node_put(i2c_modem);
} else {
printk(KERN_INFO "pmac_zilog: serial modem detected\n");
}
}
/*
* Init remaining bits of "port" structure
*/
uap->port.iotype = UPIO_MEM;
uap->port.irq = irq_of_parse_and_map(np, 0);
uap->port.uartclk = ZS_CLOCK;
uap->port.fifosize = 1;
uap->port.ops = &pmz_pops;
uap->port.type = PORT_PMAC_ZILOG;
uap->port.flags = 0;
/*
* Fixup for the port on Gatwick for which the device-tree has
* missing interrupts. Normally, the macio_dev would contain
* fixed up interrupt info, but we use the device-tree directly
* here due to early probing so we need the fixup too.
*/
if (uap->port.irq == 0 &&
np->parent && np->parent->parent &&
of_device_is_compatible(np->parent->parent, "gatwick")) {
/* IRQs on gatwick are offset by 64 */
uap->port.irq = irq_create_mapping(NULL, 64 + 15);
uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
}
/* Setup some valid baud rate information in the register
* shadows so we don't write crap there before baud rate is
* first initialized.
*/
pmz_convert_to_zs(uap, CS8, 0, 9600);
return 0;
}
/*
* Get rid of a port on module removal
*/
static void pmz_dispose_port(struct uart_pmac_port *uap)
{
struct device_node *np;
np = uap->node;
iounmap(uap->rx_dma_regs);
iounmap(uap->tx_dma_regs);
iounmap(uap->control_reg);
uap->node = NULL;
of_node_put(np);
memset(uap, 0, sizeof(struct uart_pmac_port));
}
/*
* Called upon match with an escc node in the device-tree.
*/
static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
{
struct uart_pmac_port *uap;
int i;
/* Iterate the pmz_ports array to find a matching entry
*/
for (i = 0; i < MAX_ZS_PORTS; i++)
if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
break;
if (i >= MAX_ZS_PORTS)
return -ENODEV;
uap = &pmz_ports[i];
uap->dev = mdev;
uap->port.dev = &mdev->ofdev.dev;
dev_set_drvdata(&mdev->ofdev.dev, uap);
/* We still activate the port even when failing to request resources
* to work around bugs in ancient Apple device-trees
*/
if (macio_request_resources(uap->dev, "pmac_zilog"))
printk(KERN_WARNING "%s: Failed to request resource"
", port still active\n",
uap->node->name);
else
uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
return uart_add_one_port(&pmz_uart_reg, &uap->port);
}
/*
* That one should not be called, macio isn't really a hotswap device,
* we don't expect one of those serial ports to go away...
*/
static int pmz_detach(struct macio_dev *mdev)
{
struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
if (!uap)
return -ENODEV;
uart_remove_one_port(&pmz_uart_reg, &uap->port);
if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
macio_release_resources(uap->dev);
uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
}
dev_set_drvdata(&mdev->ofdev.dev, NULL);
uap->dev = NULL;
uap->port.dev = NULL;
return 0;
}
static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
{
struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
if (uap == NULL) {
printk("HRM... pmz_suspend with NULL uap\n");
return 0;
}
uart_suspend_port(&pmz_uart_reg, &uap->port);
return 0;
}
static int pmz_resume(struct macio_dev *mdev)
{
struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
if (uap == NULL)
return 0;
uart_resume_port(&pmz_uart_reg, &uap->port);
return 0;
}
/*
* Probe all ports in the system and build the ports array, we register
* with the serial layer later, so we get a proper struct device which
* allows the tty to attach properly. This is later than it used to be
* but the tty layer really wants it that way.
*/
static int __init pmz_probe(void)
{
struct device_node *node_p, *node_a, *node_b, *np;
int count = 0;
int rc;
/*
* Find all escc chips in the system
*/
for_each_node_by_name(node_p, "escc") {
/*
* First get channel A/B node pointers
*
* TODO: Add routines with proper locking to do that...
*/
node_a = node_b = NULL;
for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
if (strncmp(np->name, "ch-a", 4) == 0)
node_a = of_node_get(np);
else if (strncmp(np->name, "ch-b", 4) == 0)
node_b = of_node_get(np);
}
if (!node_a && !node_b) {
of_node_put(node_a);
of_node_put(node_b);
printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
(!node_a) ? 'a' : 'b', node_p->full_name);
continue;
}
/*
* Fill basic fields in the port structures
*/
if (node_b != NULL) {
pmz_ports[count].mate = &pmz_ports[count+1];
pmz_ports[count+1].mate = &pmz_ports[count];
}
pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
pmz_ports[count].node = node_a;
pmz_ports[count+1].node = node_b;
pmz_ports[count].port.line = count;
pmz_ports[count+1].port.line = count+1;
/*
* Setup the ports for real
*/
rc = pmz_init_port(&pmz_ports[count]);
if (rc == 0 && node_b != NULL)
rc = pmz_init_port(&pmz_ports[count+1]);
if (rc != 0) {
of_node_put(node_a);
of_node_put(node_b);
memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
continue;
}
count += 2;
}
pmz_ports_count = count;
return 0;
}
#else
extern struct platform_device scc_a_pdev, scc_b_pdev;
static int __init pmz_init_port(struct uart_pmac_port *uap)
{
struct resource *r_ports;
int irq;
r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(uap->pdev, 0);
if (!r_ports || irq <= 0)
return -ENODEV;
uap->port.mapbase = r_ports->start;
uap->port.membase = (unsigned char __iomem *) r_ports->start;
uap->port.iotype = UPIO_MEM;
uap->port.irq = irq;
uap->port.uartclk = ZS_CLOCK;
uap->port.fifosize = 1;
uap->port.ops = &pmz_pops;
uap->port.type = PORT_PMAC_ZILOG;
uap->port.flags = 0;
uap->control_reg = uap->port.membase;
uap->data_reg = uap->control_reg + 4;
uap->port_type = 0;
pmz_convert_to_zs(uap, CS8, 0, 9600);
return 0;
}
static int __init pmz_probe(void)
{
int err;
pmz_ports_count = 0;
pmz_ports[0].port.line = 0;
pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
pmz_ports[0].pdev = &scc_a_pdev;
err = pmz_init_port(&pmz_ports[0]);
if (err)
return err;
pmz_ports_count++;
pmz_ports[0].mate = &pmz_ports[1];
pmz_ports[1].mate = &pmz_ports[0];
pmz_ports[1].port.line = 1;
pmz_ports[1].flags = 0;
pmz_ports[1].pdev = &scc_b_pdev;
err = pmz_init_port(&pmz_ports[1]);
if (err)
return err;
pmz_ports_count++;
return 0;
}
static void pmz_dispose_port(struct uart_pmac_port *uap)
{
memset(uap, 0, sizeof(struct uart_pmac_port));
}
static int __init pmz_attach(struct platform_device *pdev)
{
struct uart_pmac_port *uap;
int i;
/* Iterate the pmz_ports array to find a matching entry */
for (i = 0; i < pmz_ports_count; i++)
if (pmz_ports[i].pdev == pdev)
break;
if (i >= pmz_ports_count)
return -ENODEV;
uap = &pmz_ports[i];
uap->port.dev = &pdev->dev;
platform_set_drvdata(pdev, uap);
return uart_add_one_port(&pmz_uart_reg, &uap->port);
}
static int __exit pmz_detach(struct platform_device *pdev)
{
struct uart_pmac_port *uap = platform_get_drvdata(pdev);
if (!uap)
return -ENODEV;
uart_remove_one_port(&pmz_uart_reg, &uap->port);
uap->port.dev = NULL;
return 0;
}
#endif /* !CONFIG_PPC_PMAC */
#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
static void pmz_console_write(struct console *con, const char *s, unsigned int count);
static int __init pmz_console_setup(struct console *co, char *options);
static struct console pmz_console = {
.name = PMACZILOG_NAME,
.write = pmz_console_write,
.device = uart_console_device,
.setup = pmz_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &pmz_uart_reg,
};
#define PMACZILOG_CONSOLE &pmz_console
#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
#define PMACZILOG_CONSOLE (NULL)
#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
/*
* Register the driver, console driver and ports with the serial
* core
*/
static int __init pmz_register(void)
{
pmz_uart_reg.nr = pmz_ports_count;
pmz_uart_reg.cons = PMACZILOG_CONSOLE;
/*
* Register this driver with the serial core
*/
return uart_register_driver(&pmz_uart_reg);
}
#ifdef CONFIG_PPC_PMAC
static const struct of_device_id pmz_match[] =
{
{
.name = "ch-a",
},
{
.name = "ch-b",
},
{},
};
MODULE_DEVICE_TABLE (of, pmz_match);
static struct macio_driver pmz_driver = {
.driver = {
.name = "pmac_zilog",
.owner = THIS_MODULE,
.of_match_table = pmz_match,
},
.probe = pmz_attach,
.remove = pmz_detach,
.suspend = pmz_suspend,
.resume = pmz_resume,
};
#else
static struct platform_driver pmz_driver = {
.remove = __exit_p(pmz_detach),
.driver = {
.name = "scc",
},
};
#endif /* !CONFIG_PPC_PMAC */
static int __init init_pmz(void)
{
int rc, i;
printk(KERN_INFO "%s\n", version);
/*
* First, we need to do a direct OF-based probe pass. We
* do that because we want serial console up before the
* macio stuffs calls us back, and since that makes it
* easier to pass the proper number of channels to
* uart_register_driver()
*/
if (pmz_ports_count == 0)
pmz_probe();
/*
* Bail early if no port found
*/
if (pmz_ports_count == 0)
return -ENODEV;
/*
* Now we register with the serial layer
*/
rc = pmz_register();
if (rc) {
printk(KERN_ERR
"pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
"pmac_zilog: Did another serial driver already claim the minors?\n");
/* effectively "pmz_unprobe()" */
for (i=0; i < pmz_ports_count; i++)
pmz_dispose_port(&pmz_ports[i]);
return rc;
}
/*
* Then we register the macio driver itself
*/
#ifdef CONFIG_PPC_PMAC
return macio_register_driver(&pmz_driver);
#else
return platform_driver_probe(&pmz_driver, pmz_attach);
#endif
}
static void __exit exit_pmz(void)
{
int i;
#ifdef CONFIG_PPC_PMAC
/* Get rid of macio-driver (detach from macio) */
macio_unregister_driver(&pmz_driver);
#else
platform_driver_unregister(&pmz_driver);
#endif
for (i = 0; i < pmz_ports_count; i++) {
struct uart_pmac_port *uport = &pmz_ports[i];
#ifdef CONFIG_PPC_PMAC
if (uport->node != NULL)
pmz_dispose_port(uport);
#else
if (uport->pdev != NULL)
pmz_dispose_port(uport);
#endif
}
/* Unregister UART driver */
uart_unregister_driver(&pmz_uart_reg);
}
#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
static void pmz_console_putchar(struct uart_port *port, int ch)
{
struct uart_pmac_port *uap =
container_of(port, struct uart_pmac_port, port);
/* Wait for the transmit buffer to empty. */
while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
udelay(5);
write_zsdata(uap, ch);
}
/*
* Print a string to the serial port trying not to disturb
* any possible real use of the port...
*/
static void pmz_console_write(struct console *con, const char *s, unsigned int count)
{
struct uart_pmac_port *uap = &pmz_ports[con->index];
unsigned long flags;
spin_lock_irqsave(&uap->port.lock, flags);
/* Turn of interrupts and enable the transmitter. */
write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
uart_console_write(&uap->port, s, count, pmz_console_putchar);
/* Restore the values in the registers. */
write_zsreg(uap, R1, uap->curregs[1]);
/* Don't disable the transmitter. */
spin_unlock_irqrestore(&uap->port.lock, flags);
}
/*
* Setup the serial console
*/
static int __init pmz_console_setup(struct console *co, char *options)
{
struct uart_pmac_port *uap;
struct uart_port *port;
int baud = 38400;
int bits = 8;
int parity = 'n';
int flow = 'n';
unsigned long pwr_delay;
/*
* XServe's default to 57600 bps
*/
if (of_machine_is_compatible("RackMac1,1")
|| of_machine_is_compatible("RackMac1,2")
|| of_machine_is_compatible("MacRISC4"))
baud = 57600;
/*
* Check whether an invalid uart number has been specified, and
* if so, search for the first available port that does have
* console support.
*/
if (co->index >= pmz_ports_count)
co->index = 0;
uap = &pmz_ports[co->index];
#ifdef CONFIG_PPC_PMAC
if (uap->node == NULL)
return -ENODEV;
#else
if (uap->pdev == NULL)
return -ENODEV;
#endif
port = &uap->port;
/*
* Mark port as beeing a console
*/
uap->flags |= PMACZILOG_FLAG_IS_CONS;
/*
* Temporary fix for uart layer who didn't setup the spinlock yet
*/
spin_lock_init(&port->lock);
/*
* Enable the hardware
*/
pwr_delay = __pmz_startup(uap);
if (pwr_delay)
mdelay(pwr_delay);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
return uart_set_options(port, co, baud, parity, bits, flow);
}
static int __init pmz_console_init(void)
{
/* Probe ports */
pmz_probe();
if (pmz_ports_count == 0)
return -ENODEV;
/* TODO: Autoprobe console based on OF */
/* pmz_console.index = i; */
register_console(&pmz_console);
return 0;
}
console_initcall(pmz_console_init);
#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
module_init(init_pmz);
module_exit(exit_pmz);
| null | null | null | null | 96,258 |
38,121 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 203,116 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* tmon.c Thermal Monitor (TMON) main function and entry point
*
* Copyright (C) 2012 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 or later as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Author: Jacob Pan <jacob.jun.pan@linux.intel.com>
*
*/
#include <getopt.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <ncurses.h>
#include <ctype.h>
#include <time.h>
#include <signal.h>
#include <limits.h>
#include <sys/time.h>
#include <pthread.h>
#include <math.h>
#include <stdarg.h>
#include <syslog.h>
#include "tmon.h"
unsigned long ticktime = 1; /* seconds */
unsigned long no_control = 1; /* monitoring only or use cooling device for
* temperature control.
*/
double time_elapsed = 0.0;
unsigned long target_temp_user = 65; /* can be select by tui later */
int dialogue_on;
int tmon_exit;
static short daemon_mode;
static int logging; /* for recording thermal data to a file */
static int debug_on;
FILE *tmon_log;
/*cooling device used for the PID controller */
char ctrl_cdev[CDEV_NAME_SIZE] = "None";
int target_thermal_zone; /* user selected target zone instance */
static void start_daemon_mode(void);
pthread_t event_tid;
pthread_mutex_t input_lock;
void usage()
{
printf("Usage: tmon [OPTION...]\n");
printf(" -c, --control cooling device in control\n");
printf(" -d, --daemon run as daemon, no TUI\n");
printf(" -g, --debug debug message in syslog\n");
printf(" -h, --help show this help message\n");
printf(" -l, --log log data to /var/tmp/tmon.log\n");
printf(" -t, --time-interval sampling time interval, > 1 sec.\n");
printf(" -T, --target-temp initial target temperature\n");
printf(" -v, --version show version\n");
printf(" -z, --zone target thermal zone id\n");
exit(0);
}
void version()
{
printf("TMON version %s\n", VERSION);
exit(EXIT_SUCCESS);
}
static void tmon_cleanup(void)
{
syslog(LOG_INFO, "TMON exit cleanup\n");
fflush(stdout);
refresh();
if (tmon_log)
fclose(tmon_log);
if (event_tid) {
pthread_mutex_lock(&input_lock);
pthread_cancel(event_tid);
pthread_mutex_unlock(&input_lock);
pthread_mutex_destroy(&input_lock);
}
closelog();
/* relax control knobs, undo throttling */
set_ctrl_state(0);
keypad(stdscr, FALSE);
echo();
nocbreak();
close_windows();
endwin();
free_thermal_data();
exit(1);
}
static void tmon_sig_handler(int sig)
{
syslog(LOG_INFO, "TMON caught signal %d\n", sig);
refresh();
switch (sig) {
case SIGTERM:
printf("sigterm, exit and clean up\n");
fflush(stdout);
break;
case SIGKILL:
printf("sigkill, exit and clean up\n");
fflush(stdout);
break;
case SIGINT:
printf("ctrl-c, exit and clean up\n");
fflush(stdout);
break;
default:
break;
}
tmon_exit = true;
}
static void start_syslog(void)
{
if (debug_on)
setlogmask(LOG_UPTO(LOG_DEBUG));
else
setlogmask(LOG_UPTO(LOG_ERR));
openlog("tmon.log", LOG_CONS | LOG_PID | LOG_NDELAY, LOG_LOCAL0);
syslog(LOG_NOTICE, "TMON started by User %d", getuid());
}
static void prepare_logging(void)
{
int i;
struct stat logstat;
if (!logging)
return;
/* open local data log file */
tmon_log = fopen(TMON_LOG_FILE, "w+");
if (!tmon_log) {
syslog(LOG_ERR, "failed to open log file %s\n", TMON_LOG_FILE);
return;
}
if (lstat(TMON_LOG_FILE, &logstat) < 0) {
syslog(LOG_ERR, "Unable to stat log file %s\n", TMON_LOG_FILE);
fclose(tmon_log);
tmon_log = NULL;
return;
}
/* The log file must be a regular file owned by us */
if (S_ISLNK(logstat.st_mode)) {
syslog(LOG_ERR, "Log file is a symlink. Will not log\n");
fclose(tmon_log);
tmon_log = NULL;
return;
}
if (logstat.st_uid != getuid()) {
syslog(LOG_ERR, "We don't own the log file. Not logging\n");
fclose(tmon_log);
tmon_log = NULL;
return;
}
fprintf(tmon_log, "#----------- THERMAL SYSTEM CONFIG -------------\n");
for (i = 0; i < ptdata.nr_tz_sensor; i++) {
char binding_str[33]; /* size of long + 1 */
int j;
memset(binding_str, 0, sizeof(binding_str));
for (j = 0; j < 32; j++)
binding_str[j] = (ptdata.tzi[i].cdev_binding & 1<<j) ?
'1' : '0';
fprintf(tmon_log, "#thermal zone %s%02d cdevs binding: %32s\n",
ptdata.tzi[i].type,
ptdata.tzi[i].instance,
binding_str);
for (j = 0; j < ptdata.tzi[i].nr_trip_pts; j++) {
fprintf(tmon_log, "#\tTP%02d type:%s, temp:%lu\n", j,
trip_type_name[ptdata.tzi[i].tp[j].type],
ptdata.tzi[i].tp[j].temp);
}
}
for (i = 0; i < ptdata.nr_cooling_dev; i++)
fprintf(tmon_log, "#cooling devices%02d: %s\n",
i, ptdata.cdi[i].type);
fprintf(tmon_log, "#---------- THERMAL DATA LOG STARTED -----------\n");
fprintf(tmon_log, "Samples TargetTemp ");
for (i = 0; i < ptdata.nr_tz_sensor; i++) {
fprintf(tmon_log, "%s%d ", ptdata.tzi[i].type,
ptdata.tzi[i].instance);
}
for (i = 0; i < ptdata.nr_cooling_dev; i++)
fprintf(tmon_log, "%s%d ", ptdata.cdi[i].type,
ptdata.cdi[i].instance);
fprintf(tmon_log, "\n");
}
static struct option opts[] = {
{ "control", 1, NULL, 'c' },
{ "daemon", 0, NULL, 'd' },
{ "time-interval", 1, NULL, 't' },
{ "target-temp", 1, NULL, 'T' },
{ "log", 0, NULL, 'l' },
{ "help", 0, NULL, 'h' },
{ "version", 0, NULL, 'v' },
{ "debug", 0, NULL, 'g' },
{ 0, 0, NULL, 0 }
};
int main(int argc, char **argv)
{
int err = 0;
int id2 = 0, c;
double yk = 0.0, temp; /* controller output */
int target_tz_index;
if (geteuid() != 0) {
printf("TMON needs to be run as root\n");
exit(EXIT_FAILURE);
}
while ((c = getopt_long(argc, argv, "c:dlht:T:vgz:", opts, &id2)) != -1) {
switch (c) {
case 'c':
no_control = 0;
strncpy(ctrl_cdev, optarg, CDEV_NAME_SIZE);
break;
case 'd':
start_daemon_mode();
printf("Run TMON in daemon mode\n");
break;
case 't':
ticktime = strtod(optarg, NULL);
if (ticktime < 1)
ticktime = 1;
break;
case 'T':
temp = strtod(optarg, NULL);
if (temp < 0) {
fprintf(stderr, "error: temperature must be positive\n");
return 1;
}
target_temp_user = temp;
break;
case 'l':
printf("Logging data to /var/tmp/tmon.log\n");
logging = 1;
break;
case 'h':
usage();
break;
case 'v':
version();
break;
case 'g':
debug_on = 1;
break;
case 'z':
target_thermal_zone = strtod(optarg, NULL);
break;
default:
break;
}
}
if (pthread_mutex_init(&input_lock, NULL) != 0) {
fprintf(stderr, "\n mutex init failed, exit\n");
return 1;
}
start_syslog();
if (signal(SIGINT, tmon_sig_handler) == SIG_ERR)
syslog(LOG_DEBUG, "Cannot handle SIGINT\n");
if (signal(SIGTERM, tmon_sig_handler) == SIG_ERR)
syslog(LOG_DEBUG, "Cannot handle SIGINT\n");
if (probe_thermal_sysfs()) {
pthread_mutex_destroy(&input_lock);
closelog();
return -1;
}
initialize_curses();
setup_windows();
signal(SIGWINCH, resize_handler);
show_title_bar();
show_sensors_w();
show_cooling_device();
update_thermal_data();
show_data_w();
prepare_logging();
init_thermal_controller();
nodelay(stdscr, TRUE);
err = pthread_create(&event_tid, NULL, &handle_tui_events, NULL);
if (err != 0) {
printf("\ncan't create thread :[%s]", strerror(err));
tmon_cleanup();
exit(EXIT_FAILURE);
}
/* validate range of user selected target zone, default to the first
* instance if out of range
*/
target_tz_index = zone_instance_to_index(target_thermal_zone);
if (target_tz_index < 0) {
target_thermal_zone = ptdata.tzi[0].instance;
syslog(LOG_ERR, "target zone is not found, default to %d\n",
target_thermal_zone);
}
while (1) {
sleep(ticktime);
show_title_bar();
show_sensors_w();
update_thermal_data();
if (!dialogue_on) {
show_data_w();
show_cooling_device();
}
cur_thermal_record++;
time_elapsed += ticktime;
controller_handler(trec[0].temp[target_tz_index] / 1000,
&yk);
trec[0].pid_out_pct = yk;
if (!dialogue_on)
show_control_w();
if (tmon_exit)
break;
}
tmon_cleanup();
return 0;
}
static void start_daemon_mode()
{
daemon_mode = 1;
/* fork */
pid_t sid, pid = fork();
if (pid < 0) {
exit(EXIT_FAILURE);
} else if (pid > 0)
/* kill parent */
exit(EXIT_SUCCESS);
/* disable TUI, it may not be necessary, but saves some resource */
disable_tui();
/* change the file mode mask */
umask(S_IWGRP | S_IWOTH);
/* new SID for the daemon process */
sid = setsid();
if (sid < 0)
exit(EXIT_FAILURE);
/* change working directory */
if ((chdir("/")) < 0)
exit(EXIT_FAILURE);
sleep(10);
close(STDIN_FILENO);
close(STDOUT_FILENO);
close(STDERR_FILENO);
}
| null | null | null | null | 111,463 |
56,004 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 56,004 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chrome/browser/pdf/pdf_extension_util.h"
#include "base/strings/string_util.h"
#include "chrome/common/chrome_content_client.h"
#include "chrome/grit/browser_resources.h"
#include "ui/base/resource/resource_bundle.h"
namespace pdf_extension_util {
namespace {
// Tags in the manifest to be replaced.
const char kNameTag[] = "<NAME>";
} // namespace
std::string GetManifest() {
std::string manifest_contents = ui::ResourceBundle::GetSharedInstance()
.GetRawDataResource(IDR_PDF_MANIFEST)
.as_string();
DCHECK(manifest_contents.find(kNameTag) != std::string::npos);
base::ReplaceFirstSubstringAfterOffset(
&manifest_contents, 0, kNameTag,
ChromeContentClient::kPDFExtensionPluginName);
return manifest_contents;
}
} // namespace pdf_extension_util
| null | null | null | null | 52,867 |
16,599 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 16,599 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
// This class defines tests that implementations of InvalidationService should
// pass in order to be conformant. Here's how you use it to test your
// implementation.
//
// Say your class is called MyInvalidationService. Then you need to define a
// class called MyInvalidationServiceTestDelegate in
// my_invalidation_frontend_unittest.cc like this:
//
// class MyInvalidationServiceTestDelegate {
// public:
// MyInvalidationServiceTestDelegate() ...
//
// ~MyInvalidationServiceTestDelegate() {
// // DestroyInvalidator() may not be explicitly called by tests.
// DestroyInvalidator();
// }
//
// // Create the InvalidationService implementation with the given params.
// void CreateInvalidationService() {
// ...
// }
//
// // Should return the InvalidationService implementation. Only called
// // after CreateInvalidator and before DestroyInvalidator.
// MyInvalidationService* GetInvalidationService() {
// ...
// }
//
// // Destroy the InvalidationService implementation.
// void DestroyInvalidationService() {
// ...
// }
//
// // The Trigger* functions below should block until the effects of
// // the call are visible on the current thread.
//
// // Should cause OnInvalidatorStateChange() to be called on all
// // observers of the InvalidationService implementation with the given
// // parameters.
// void TriggerOnInvalidatorStateChange(InvalidatorState state) {
// ...
// }
//
// // Should cause OnIncomingInvalidation() to be called on all
// // observers of the InvalidationService implementation with the given
// // parameters.
// void TriggerOnIncomingInvalidation(
// const ObjectIdInvalidationMap& invalidation_map) {
// ...
// }
// };
//
// The InvalidationServiceTest test harness will have a member variable of
// this delegate type and will call its functions in the various
// tests.
//
// Then you simply #include this file as well as gtest.h and add the
// following statement to my_sync_notifier_unittest.cc:
//
// INSTANTIATE_TYPED_TEST_CASE_P(
// MyInvalidationService,
// InvalidationServiceTest,
// MyInvalidatorTestDelegate);
//
// Easy!
#ifndef COMPONENTS_INVALIDATION_IMPL_INVALIDATION_SERVICE_TEST_TEMPLATE_H_
#define COMPONENTS_INVALIDATION_IMPL_INVALIDATION_SERVICE_TEST_TEMPLATE_H_
#include "base/compiler_specific.h"
#include "base/macros.h"
#include "components/invalidation/impl/fake_invalidation_handler.h"
#include "components/invalidation/impl/object_id_invalidation_map_test_util.h"
#include "components/invalidation/public/ack_handle.h"
#include "components/invalidation/public/invalidation.h"
#include "components/invalidation/public/invalidation_service.h"
#include "components/invalidation/public/object_id_invalidation_map.h"
#include "google/cacheinvalidation/include/types.h"
#include "google/cacheinvalidation/types.pb.h"
#include "testing/gtest/include/gtest/gtest.h"
template <typename InvalidatorTestDelegate>
class InvalidationServiceTest : public testing::Test {
protected:
InvalidationServiceTest()
: id1(ipc::invalidation::ObjectSource::CHROME_SYNC, "BOOKMARK"),
id2(ipc::invalidation::ObjectSource::CHROME_SYNC, "PREFERENCE"),
id3(ipc::invalidation::ObjectSource::CHROME_SYNC, "AUTOFILL"),
id4(ipc::invalidation::ObjectSource::CHROME_PUSH_MESSAGING,
"PUSH_MESSAGE") {
}
invalidation::InvalidationService*
CreateAndInitializeInvalidationService() {
this->delegate_.CreateInvalidationService();
return this->delegate_.GetInvalidationService();
}
InvalidatorTestDelegate delegate_;
const invalidation::ObjectId id1;
const invalidation::ObjectId id2;
const invalidation::ObjectId id3;
const invalidation::ObjectId id4;
};
TYPED_TEST_CASE_P(InvalidationServiceTest);
// Initialize the invalidator, register a handler, register some IDs for that
// handler, and then unregister the handler, dispatching invalidations in
// between. The handler should only see invalidations when its registered and
// its IDs are registered.
TYPED_TEST_P(InvalidationServiceTest, Basic) {
invalidation::InvalidationService* const invalidator =
this->CreateAndInitializeInvalidationService();
syncer::FakeInvalidationHandler handler;
invalidator->RegisterInvalidationHandler(&handler);
syncer::ObjectIdInvalidationMap invalidation_map;
invalidation_map.Insert(syncer::Invalidation::Init(this->id1, 1, "1"));
invalidation_map.Insert(syncer::Invalidation::Init(this->id2, 2, "2"));
invalidation_map.Insert(syncer::Invalidation::Init(this->id3, 3, "3"));
// Should be ignored since no IDs are registered to |handler|.
this->delegate_.TriggerOnIncomingInvalidation(invalidation_map);
EXPECT_EQ(0, handler.GetInvalidationCount());
syncer::ObjectIdSet ids;
ids.insert(this->id1);
ids.insert(this->id2);
EXPECT_TRUE(invalidator->UpdateRegisteredInvalidationIds(&handler, ids));
this->delegate_.TriggerOnInvalidatorStateChange(
syncer::INVALIDATIONS_ENABLED);
EXPECT_EQ(syncer::INVALIDATIONS_ENABLED, handler.GetInvalidatorState());
syncer::ObjectIdInvalidationMap expected_invalidations;
expected_invalidations.Insert(syncer::Invalidation::Init(this->id1, 1, "1"));
expected_invalidations.Insert(syncer::Invalidation::Init(this->id2, 2, "2"));
this->delegate_.TriggerOnIncomingInvalidation(invalidation_map);
EXPECT_EQ(1, handler.GetInvalidationCount());
EXPECT_THAT(expected_invalidations, Eq(handler.GetLastInvalidationMap()));
ids.erase(this->id1);
ids.insert(this->id3);
EXPECT_TRUE(invalidator->UpdateRegisteredInvalidationIds(&handler, ids));
expected_invalidations = syncer::ObjectIdInvalidationMap();
expected_invalidations.Insert(syncer::Invalidation::Init(this->id2, 2, "2"));
expected_invalidations.Insert(syncer::Invalidation::Init(this->id3, 3, "3"));
// Removed object IDs should not be notified, newly-added ones should.
this->delegate_.TriggerOnIncomingInvalidation(invalidation_map);
EXPECT_EQ(2, handler.GetInvalidationCount());
EXPECT_THAT(expected_invalidations, Eq(handler.GetLastInvalidationMap()));
this->delegate_.TriggerOnInvalidatorStateChange(
syncer::TRANSIENT_INVALIDATION_ERROR);
EXPECT_EQ(syncer::TRANSIENT_INVALIDATION_ERROR,
handler.GetInvalidatorState());
this->delegate_.TriggerOnInvalidatorStateChange(
syncer::INVALIDATIONS_ENABLED);
EXPECT_EQ(syncer::INVALIDATIONS_ENABLED,
handler.GetInvalidatorState());
invalidator->UnregisterInvalidationHandler(&handler);
// Should be ignored since |handler| isn't registered anymore.
this->delegate_.TriggerOnIncomingInvalidation(invalidation_map);
EXPECT_EQ(2, handler.GetInvalidationCount());
}
// Register handlers and some IDs for those handlers, register a handler with
// no IDs, and register a handler with some IDs but unregister it. Then,
// dispatch some invalidations and invalidations. Handlers that are registered
// should get invalidations, and the ones that have registered IDs should
// receive invalidations for those IDs.
TYPED_TEST_P(InvalidationServiceTest, MultipleHandlers) {
invalidation::InvalidationService* const invalidator =
this->CreateAndInitializeInvalidationService();
syncer::FakeInvalidationHandler handler1;
syncer::FakeInvalidationHandler handler2;
syncer::FakeInvalidationHandler handler3;
syncer::FakeInvalidationHandler handler4;
invalidator->RegisterInvalidationHandler(&handler1);
invalidator->RegisterInvalidationHandler(&handler2);
invalidator->RegisterInvalidationHandler(&handler3);
invalidator->RegisterInvalidationHandler(&handler4);
{
syncer::ObjectIdSet ids;
ids.insert(this->id1);
ids.insert(this->id2);
EXPECT_TRUE(invalidator->UpdateRegisteredInvalidationIds(&handler1, ids));
}
{
syncer::ObjectIdSet ids;
ids.insert(this->id3);
EXPECT_TRUE(invalidator->UpdateRegisteredInvalidationIds(&handler2, ids));
}
// Don't register any IDs for handler3.
{
syncer::ObjectIdSet ids;
ids.insert(this->id4);
EXPECT_TRUE(invalidator->UpdateRegisteredInvalidationIds(&handler4, ids));
}
invalidator->UnregisterInvalidationHandler(&handler4);
this->delegate_.TriggerOnInvalidatorStateChange(
syncer::INVALIDATIONS_ENABLED);
EXPECT_EQ(syncer::INVALIDATIONS_ENABLED, handler1.GetInvalidatorState());
EXPECT_EQ(syncer::INVALIDATIONS_ENABLED, handler2.GetInvalidatorState());
EXPECT_EQ(syncer::INVALIDATIONS_ENABLED, handler3.GetInvalidatorState());
EXPECT_EQ(syncer::TRANSIENT_INVALIDATION_ERROR,
handler4.GetInvalidatorState());
{
syncer::ObjectIdInvalidationMap invalidation_map;
invalidation_map.Insert(syncer::Invalidation::Init(this->id1, 1, "1"));
invalidation_map.Insert(syncer::Invalidation::Init(this->id2, 2, "2"));
invalidation_map.Insert(syncer::Invalidation::Init(this->id3, 3, "3"));
invalidation_map.Insert(syncer::Invalidation::Init(this->id4, 4, "4"));
this->delegate_.TriggerOnIncomingInvalidation(invalidation_map);
syncer::ObjectIdInvalidationMap expected_invalidations;
expected_invalidations.Insert(
syncer::Invalidation::Init(this->id1, 1, "1"));
expected_invalidations.Insert(
syncer::Invalidation::Init(this->id2, 2, "2"));
EXPECT_EQ(1, handler1.GetInvalidationCount());
EXPECT_THAT(expected_invalidations, Eq(handler1.GetLastInvalidationMap()));
expected_invalidations = syncer::ObjectIdInvalidationMap();
expected_invalidations.Insert(
syncer::Invalidation::Init(this->id3, 3, "3"));
EXPECT_EQ(1, handler2.GetInvalidationCount());
EXPECT_THAT(expected_invalidations, Eq(handler2.GetLastInvalidationMap()));
EXPECT_EQ(0, handler3.GetInvalidationCount());
EXPECT_EQ(0, handler4.GetInvalidationCount());
}
this->delegate_.TriggerOnInvalidatorStateChange(
syncer::TRANSIENT_INVALIDATION_ERROR);
EXPECT_EQ(syncer::TRANSIENT_INVALIDATION_ERROR,
handler1.GetInvalidatorState());
EXPECT_EQ(syncer::TRANSIENT_INVALIDATION_ERROR,
handler2.GetInvalidatorState());
EXPECT_EQ(syncer::TRANSIENT_INVALIDATION_ERROR,
handler3.GetInvalidatorState());
EXPECT_EQ(syncer::TRANSIENT_INVALIDATION_ERROR,
handler4.GetInvalidatorState());
invalidator->UnregisterInvalidationHandler(&handler3);
invalidator->UnregisterInvalidationHandler(&handler2);
invalidator->UnregisterInvalidationHandler(&handler1);
}
// Multiple registrations by different handlers on the same object ID should
// return false.
TYPED_TEST_P(InvalidationServiceTest, MultipleRegistrations) {
invalidation::InvalidationService* const invalidator =
this->CreateAndInitializeInvalidationService();
syncer::FakeInvalidationHandler handler1;
syncer::FakeInvalidationHandler handler2;
invalidator->RegisterInvalidationHandler(&handler1);
invalidator->RegisterInvalidationHandler(&handler2);
// Registering both handlers for the same ObjectId. First call should succeed,
// second should fail.
syncer::ObjectIdSet ids;
ids.insert(this->id1);
EXPECT_TRUE(invalidator->UpdateRegisteredInvalidationIds(&handler1, ids));
EXPECT_FALSE(invalidator->UpdateRegisteredInvalidationIds(&handler2, ids));
invalidator->UnregisterInvalidationHandler(&handler2);
invalidator->UnregisterInvalidationHandler(&handler1);
}
// Make sure that passing an empty set to UpdateRegisteredInvalidationIds clears
// the corresponding entries for the handler.
TYPED_TEST_P(InvalidationServiceTest, EmptySetUnregisters) {
invalidation::InvalidationService* const invalidator =
this->CreateAndInitializeInvalidationService();
syncer::FakeInvalidationHandler handler1;
// Control observer.
syncer::FakeInvalidationHandler handler2;
invalidator->RegisterInvalidationHandler(&handler1);
invalidator->RegisterInvalidationHandler(&handler2);
{
syncer::ObjectIdSet ids;
ids.insert(this->id1);
ids.insert(this->id2);
EXPECT_TRUE(invalidator->UpdateRegisteredInvalidationIds(&handler1, ids));
}
{
syncer::ObjectIdSet ids;
ids.insert(this->id3);
EXPECT_TRUE(invalidator->UpdateRegisteredInvalidationIds(&handler2, ids));
}
// Unregister the IDs for the first observer. It should not receive any
// further invalidations.
EXPECT_TRUE(invalidator->UpdateRegisteredInvalidationIds(
&handler1, syncer::ObjectIdSet()));
this->delegate_.TriggerOnInvalidatorStateChange(
syncer::INVALIDATIONS_ENABLED);
EXPECT_EQ(syncer::INVALIDATIONS_ENABLED, handler1.GetInvalidatorState());
EXPECT_EQ(syncer::INVALIDATIONS_ENABLED, handler2.GetInvalidatorState());
{
syncer::ObjectIdInvalidationMap invalidation_map;
invalidation_map.Insert(syncer::Invalidation::Init(this->id1, 1, "1"));
invalidation_map.Insert(syncer::Invalidation::Init(this->id2, 2, "2"));
invalidation_map.Insert(syncer::Invalidation::Init(this->id3, 3, "3"));
this->delegate_.TriggerOnIncomingInvalidation(invalidation_map);
EXPECT_EQ(0, handler1.GetInvalidationCount());
EXPECT_EQ(1, handler2.GetInvalidationCount());
}
this->delegate_.TriggerOnInvalidatorStateChange(
syncer::TRANSIENT_INVALIDATION_ERROR);
EXPECT_EQ(syncer::TRANSIENT_INVALIDATION_ERROR,
handler1.GetInvalidatorState());
EXPECT_EQ(syncer::TRANSIENT_INVALIDATION_ERROR,
handler2.GetInvalidatorState());
invalidator->UnregisterInvalidationHandler(&handler2);
invalidator->UnregisterInvalidationHandler(&handler1);
}
namespace internal {
// A FakeInvalidationHandler that is "bound" to a specific
// InvalidationService. This is for cross-referencing state information with
// the bound InvalidationService.
class BoundFakeInvalidationHandler : public syncer::FakeInvalidationHandler {
public:
explicit BoundFakeInvalidationHandler(
const invalidation::InvalidationService& invalidator);
~BoundFakeInvalidationHandler() override;
// Returns the last return value of GetInvalidatorState() on the
// bound invalidator from the last time the invalidator state
// changed.
syncer::InvalidatorState GetLastRetrievedState() const;
// InvalidationHandler implementation.
void OnInvalidatorStateChange(syncer::InvalidatorState state) override;
private:
const invalidation::InvalidationService& invalidator_;
syncer::InvalidatorState last_retrieved_state_;
DISALLOW_COPY_AND_ASSIGN(BoundFakeInvalidationHandler);
};
} // namespace internal
TYPED_TEST_P(InvalidationServiceTest, GetInvalidatorStateAlwaysCurrent) {
invalidation::InvalidationService* const invalidator =
this->CreateAndInitializeInvalidationService();
internal::BoundFakeInvalidationHandler handler(*invalidator);
invalidator->RegisterInvalidationHandler(&handler);
this->delegate_.TriggerOnInvalidatorStateChange(
syncer::INVALIDATIONS_ENABLED);
EXPECT_EQ(syncer::INVALIDATIONS_ENABLED, handler.GetInvalidatorState());
EXPECT_EQ(syncer::INVALIDATIONS_ENABLED, handler.GetLastRetrievedState());
this->delegate_.TriggerOnInvalidatorStateChange(
syncer::TRANSIENT_INVALIDATION_ERROR);
EXPECT_EQ(syncer::TRANSIENT_INVALIDATION_ERROR,
handler.GetInvalidatorState());
EXPECT_EQ(syncer::TRANSIENT_INVALIDATION_ERROR,
handler.GetLastRetrievedState());
invalidator->UnregisterInvalidationHandler(&handler);
}
REGISTER_TYPED_TEST_CASE_P(InvalidationServiceTest,
Basic,
MultipleHandlers,
MultipleRegistrations,
EmptySetUnregisters,
GetInvalidatorStateAlwaysCurrent);
#endif // COMPONENTS_INVALIDATION_IMPL_INVALIDATION_SERVICE_TEST_TEMPLATE_H_
| null | null | null | null | 13,462 |
23,935 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 23,935 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2013 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "content/browser/streams/stream_context.h"
#include "base/bind.h"
#include "base/memory/ptr_util.h"
#include "content/browser/streams/stream_registry.h"
#include "content/public/browser/browser_context.h"
#include "content/public/browser/browser_thread.h"
using base::UserDataAdapter;
namespace {
const char kStreamContextKeyName[] = "content_stream_context";
} // namespace
namespace content {
StreamContext::StreamContext() {}
StreamContext* StreamContext::GetFor(BrowserContext* context) {
if (!context->GetUserData(kStreamContextKeyName)) {
scoped_refptr<StreamContext> stream = new StreamContext();
context->SetUserData(
kStreamContextKeyName,
std::make_unique<UserDataAdapter<StreamContext>>(stream.get()));
// Check first to avoid memory leak in unittests.
if (BrowserThread::IsThreadInitialized(BrowserThread::IO)) {
BrowserThread::PostTask(
BrowserThread::IO, FROM_HERE,
base::BindOnce(&StreamContext::InitializeOnIOThread, stream));
}
}
return UserDataAdapter<StreamContext>::Get(context, kStreamContextKeyName);
}
void StreamContext::InitializeOnIOThread() {
DCHECK_CURRENTLY_ON(BrowserThread::IO);
registry_.reset(new StreamRegistry());
}
StreamContext::~StreamContext() {}
void StreamContext::DeleteOnCorrectThread() const {
// In many tests, there isn't a valid IO thread. In that case, just delete on
// the current thread.
// TODO(zork): Remove this custom deleter, and fix the leaks in all the
// tests.
if (BrowserThread::IsThreadInitialized(BrowserThread::IO) &&
!BrowserThread::CurrentlyOn(BrowserThread::IO)) {
BrowserThread::DeleteSoon(BrowserThread::IO, FROM_HERE, this);
return;
}
delete this;
}
} // namespace content
| null | null | null | null | 20,798 |
8,731 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 173,726 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* arch/arm/mach-netx/nxdkn.c
*
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mtd/plat-ram.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/netx-regs.h>
#include <linux/platform_data/eth-netx.h>
#include "generic.h"
static struct netxeth_platform_data eth0_platform_data = {
.xcno = 0,
};
static struct platform_device nxdkn_eth0_device = {
.name = "netx-eth",
.id = 0,
.num_resources = 0,
.resource = NULL,
.dev = {
.platform_data = ð0_platform_data,
}
};
static struct netxeth_platform_data eth1_platform_data = {
.xcno = 1,
};
static struct platform_device nxdkn_eth1_device = {
.name = "netx-eth",
.id = 1,
.num_resources = 0,
.resource = NULL,
.dev = {
.platform_data = ð1_platform_data,
}
};
static struct resource netx_uart0_resources[] = {
[0] = {
.start = 0x00100A00,
.end = 0x00100A3F,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = (NETX_IRQ_UART0),
.end = (NETX_IRQ_UART0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device netx_uart0_device = {
.name = "netx-uart",
.id = 0,
.num_resources = ARRAY_SIZE(netx_uart0_resources),
.resource = netx_uart0_resources,
};
static struct platform_device *devices[] __initdata = {
&nxdkn_eth0_device,
&nxdkn_eth1_device,
&netx_uart0_device,
};
static void __init nxdkn_init(void)
{
platform_add_devices(devices, ARRAY_SIZE(devices));
}
MACHINE_START(NXDKN, "Hilscher nxdkn")
.atag_offset = 0x100,
.map_io = netx_map_io,
.init_irq = netx_init_irq,
.init_time = netx_timer_init,
.init_machine = nxdkn_init,
.restart = netx_restart,
MACHINE_END
| null | null | null | null | 82,073 |
35,427 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 200,422 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Copyright (c) 2015, Linaro Limited, Shannon Zhao
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/platform_device.h>
#include <linux/acpi.h>
#include <xen/xen.h>
#include <xen/page.h>
#include <xen/interface/memory.h>
#include <asm/xen/hypervisor.h>
#include <asm/xen/hypercall.h>
static int xen_unmap_device_mmio(const struct resource *resources,
unsigned int count)
{
unsigned int i, j, nr;
int rc = 0;
const struct resource *r;
struct xen_remove_from_physmap xrp;
for (i = 0; i < count; i++) {
r = &resources[i];
nr = DIV_ROUND_UP(resource_size(r), XEN_PAGE_SIZE);
if ((resource_type(r) != IORESOURCE_MEM) || (nr == 0))
continue;
for (j = 0; j < nr; j++) {
xrp.domid = DOMID_SELF;
xrp.gpfn = XEN_PFN_DOWN(r->start) + j;
rc = HYPERVISOR_memory_op(XENMEM_remove_from_physmap,
&xrp);
if (rc)
return rc;
}
}
return rc;
}
static int xen_map_device_mmio(const struct resource *resources,
unsigned int count)
{
unsigned int i, j, nr;
int rc = 0;
const struct resource *r;
xen_pfn_t *gpfns;
xen_ulong_t *idxs;
int *errs;
for (i = 0; i < count; i++) {
struct xen_add_to_physmap_range xatp = {
.domid = DOMID_SELF,
.space = XENMAPSPACE_dev_mmio
};
r = &resources[i];
nr = DIV_ROUND_UP(resource_size(r), XEN_PAGE_SIZE);
if ((resource_type(r) != IORESOURCE_MEM) || (nr == 0))
continue;
gpfns = kzalloc(sizeof(xen_pfn_t) * nr, GFP_KERNEL);
idxs = kzalloc(sizeof(xen_ulong_t) * nr, GFP_KERNEL);
errs = kzalloc(sizeof(int) * nr, GFP_KERNEL);
if (!gpfns || !idxs || !errs) {
kfree(gpfns);
kfree(idxs);
kfree(errs);
rc = -ENOMEM;
goto unmap;
}
for (j = 0; j < nr; j++) {
/*
* The regions are always mapped 1:1 to DOM0 and this is
* fine because the memory map for DOM0 is the same as
* the host (except for the RAM).
*/
gpfns[j] = XEN_PFN_DOWN(r->start) + j;
idxs[j] = XEN_PFN_DOWN(r->start) + j;
}
xatp.size = nr;
set_xen_guest_handle(xatp.gpfns, gpfns);
set_xen_guest_handle(xatp.idxs, idxs);
set_xen_guest_handle(xatp.errs, errs);
rc = HYPERVISOR_memory_op(XENMEM_add_to_physmap_range, &xatp);
kfree(gpfns);
kfree(idxs);
kfree(errs);
if (rc)
goto unmap;
}
return rc;
unmap:
xen_unmap_device_mmio(resources, i);
return rc;
}
static int xen_platform_notifier(struct notifier_block *nb,
unsigned long action, void *data)
{
struct platform_device *pdev = to_platform_device(data);
int r = 0;
if (pdev->num_resources == 0 || pdev->resource == NULL)
return NOTIFY_OK;
switch (action) {
case BUS_NOTIFY_ADD_DEVICE:
r = xen_map_device_mmio(pdev->resource, pdev->num_resources);
break;
case BUS_NOTIFY_DEL_DEVICE:
r = xen_unmap_device_mmio(pdev->resource, pdev->num_resources);
break;
default:
return NOTIFY_DONE;
}
if (r)
dev_err(&pdev->dev, "Platform: Failed to %s device %s MMIO!\n",
action == BUS_NOTIFY_ADD_DEVICE ? "map" :
(action == BUS_NOTIFY_DEL_DEVICE ? "unmap" : "?"),
pdev->name);
return NOTIFY_OK;
}
static struct notifier_block platform_device_nb = {
.notifier_call = xen_platform_notifier,
};
static int __init register_xen_platform_notifier(void)
{
if (!xen_initial_domain() || acpi_disabled)
return 0;
return bus_register_notifier(&platform_bus_type, &platform_device_nb);
}
arch_initcall(register_xen_platform_notifier);
#ifdef CONFIG_ARM_AMBA
#include <linux/amba/bus.h>
static int xen_amba_notifier(struct notifier_block *nb,
unsigned long action, void *data)
{
struct amba_device *adev = to_amba_device(data);
int r = 0;
switch (action) {
case BUS_NOTIFY_ADD_DEVICE:
r = xen_map_device_mmio(&adev->res, 1);
break;
case BUS_NOTIFY_DEL_DEVICE:
r = xen_unmap_device_mmio(&adev->res, 1);
break;
default:
return NOTIFY_DONE;
}
if (r)
dev_err(&adev->dev, "AMBA: Failed to %s device %s MMIO!\n",
action == BUS_NOTIFY_ADD_DEVICE ? "map" :
(action == BUS_NOTIFY_DEL_DEVICE ? "unmap" : "?"),
adev->dev.init_name);
return NOTIFY_OK;
}
static struct notifier_block amba_device_nb = {
.notifier_call = xen_amba_notifier,
};
static int __init register_xen_amba_notifier(void)
{
if (!xen_initial_domain() || acpi_disabled)
return 0;
return bus_register_notifier(&amba_bustype, &amba_device_nb);
}
arch_initcall(register_xen_amba_notifier);
#endif
| null | null | null | null | 108,769 |
26,048 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 26,048 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "extensions/browser/api/system_cpu/cpu_info_provider.h"
#include <windows.h>
#include <winternl.h>
#include <memory>
#include "base/sys_info.h"
namespace extensions {
namespace {
const wchar_t kNtdll[] = L"ntdll.dll";
const char kNtQuerySystemInformationName[] = "NtQuerySystemInformation";
// See MSDN about NtQuerySystemInformation definition.
typedef DWORD(WINAPI* NtQuerySystemInformationPF)(DWORD system_info_class,
PVOID system_info,
ULONG system_info_length,
PULONG return_length);
} // namespace
bool CpuInfoProvider::QueryCpuTimePerProcessor(
std::vector<api::system_cpu::ProcessorInfo>* infos) {
DCHECK(infos);
HMODULE ntdll = GetModuleHandle(kNtdll);
CHECK(ntdll != NULL);
NtQuerySystemInformationPF NtQuerySystemInformation =
reinterpret_cast<NtQuerySystemInformationPF>(
::GetProcAddress(ntdll, kNtQuerySystemInformationName));
CHECK(NtQuerySystemInformation != NULL);
int num_of_processors = base::SysInfo::NumberOfProcessors();
std::unique_ptr<SYSTEM_PROCESSOR_PERFORMANCE_INFORMATION[]> processor_info(
new SYSTEM_PROCESSOR_PERFORMANCE_INFORMATION[num_of_processors]);
ULONG returned_bytes = 0,
bytes = sizeof(SYSTEM_PROCESSOR_PERFORMANCE_INFORMATION) *
num_of_processors;
if (!NT_SUCCESS(
NtQuerySystemInformation(SystemProcessorPerformanceInformation,
processor_info.get(),
bytes,
&returned_bytes)))
return false;
int returned_num_of_processors =
returned_bytes / sizeof(SYSTEM_PROCESSOR_PERFORMANCE_INFORMATION);
if (returned_num_of_processors != num_of_processors)
return false;
DCHECK_EQ(num_of_processors, static_cast<int>(infos->size()));
for (int i = 0; i < returned_num_of_processors; ++i) {
double kernel = static_cast<double>(processor_info[i].KernelTime.QuadPart),
user = static_cast<double>(processor_info[i].UserTime.QuadPart),
idle = static_cast<double>(processor_info[i].IdleTime.QuadPart);
// KernelTime needs to be fixed-up, because it includes both idle time and
// real kernel time.
infos->at(i).usage.kernel = kernel - idle;
infos->at(i).usage.user = user;
infos->at(i).usage.idle = idle;
infos->at(i).usage.total = kernel + user;
}
return true;
}
} // namespace extensions
| null | null | null | null | 22,911 |
29,063 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 29,063 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | /*
* testSchemas.c : a small tester program for Schema validation
*
* See Copyright for the status of this software.
*
* Daniel.Veillard@w3.org
*/
#include "libxml.h"
#ifdef LIBXML_SCHEMAS_ENABLED
#include <libxml/xmlversion.h>
#include <libxml/parser.h>
#include <stdio.h>
#include <string.h>
#include <stdarg.h>
#ifdef HAVE_SYS_TYPES_H
#include <sys/types.h>
#endif
#ifdef HAVE_SYS_STAT_H
#include <sys/stat.h>
#endif
#ifdef HAVE_FCNTL_H
#include <fcntl.h>
#endif
#ifdef HAVE_UNISTD_H
#include <unistd.h>
#endif
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
#ifdef HAVE_SYS_MMAN_H
#include <sys/mman.h>
/* seems needed for Solaris */
#ifndef MAP_FAILED
#define MAP_FAILED ((void *) -1)
#endif
#endif
#include <libxml/xmlmemory.h>
#include <libxml/debugXML.h>
#include <libxml/xmlschemas.h>
#include <libxml/xmlschemastypes.h>
#ifdef LIBXML_DEBUG_ENABLED
static int debug = 0;
#endif
static int noout = 0;
#ifdef HAVE_MMAP
static int memory = 0;
#endif
int main(int argc, char **argv) {
int i;
int files = 0;
xmlSchemaPtr schema = NULL;
for (i = 1; i < argc ; i++) {
#ifdef LIBXML_DEBUG_ENABLED
if ((!strcmp(argv[i], "-debug")) || (!strcmp(argv[i], "--debug")))
debug++;
else
#endif
#ifdef HAVE_MMAP
if ((!strcmp(argv[i], "-memory")) || (!strcmp(argv[i], "--memory"))) {
memory++;
} else
#endif
if ((!strcmp(argv[i], "-noout")) || (!strcmp(argv[i], "--noout"))) {
noout++;
}
}
xmlLineNumbersDefault(1);
for (i = 1; i < argc ; i++) {
if (argv[i][0] != '-') {
if (schema == NULL) {
xmlSchemaParserCtxtPtr ctxt;
#ifdef HAVE_MMAP
if (memory) {
int fd;
struct stat info;
const char *base;
if (stat(argv[i], &info) < 0)
break;
if ((fd = open(argv[i], O_RDONLY)) < 0)
break;
base = mmap(NULL, info.st_size, PROT_READ,
MAP_SHARED, fd, 0) ;
if (base == (void *) MAP_FAILED)
break;
ctxt = xmlSchemaNewMemParserCtxt((char *)base,info.st_size);
xmlSchemaSetParserErrors(ctxt,
(xmlSchemaValidityErrorFunc) fprintf,
(xmlSchemaValidityWarningFunc) fprintf,
stderr);
schema = xmlSchemaParse(ctxt);
xmlSchemaFreeParserCtxt(ctxt);
munmap((char *) base, info.st_size);
} else
#endif
{
ctxt = xmlSchemaNewParserCtxt(argv[i]);
xmlSchemaSetParserErrors(ctxt,
(xmlSchemaValidityErrorFunc) fprintf,
(xmlSchemaValidityWarningFunc) fprintf,
stderr);
schema = xmlSchemaParse(ctxt);
xmlSchemaFreeParserCtxt(ctxt);
}
#ifdef LIBXML_OUTPUT_ENABLED
#ifdef LIBXML_DEBUG_ENABLED
if (debug)
xmlSchemaDump(stdout, schema);
#endif
#endif /* LIBXML_OUTPUT_ENABLED */
if (schema == NULL)
goto failed_schemas;
} else {
xmlDocPtr doc;
doc = xmlReadFile(argv[i],NULL,0);
if (doc == NULL) {
fprintf(stderr, "Could not parse %s\n", argv[i]);
} else {
xmlSchemaValidCtxtPtr ctxt;
int ret;
ctxt = xmlSchemaNewValidCtxt(schema);
xmlSchemaSetValidErrors(ctxt,
(xmlSchemaValidityErrorFunc) fprintf,
(xmlSchemaValidityWarningFunc) fprintf,
stderr);
ret = xmlSchemaValidateDoc(ctxt, doc);
if (ret == 0) {
printf("%s validates\n", argv[i]);
} else if (ret > 0) {
printf("%s fails to validate\n", argv[i]);
} else {
printf("%s validation generated an internal error\n",
argv[i]);
}
xmlSchemaFreeValidCtxt(ctxt);
xmlFreeDoc(doc);
}
}
files ++;
}
}
if (schema != NULL)
xmlSchemaFree(schema);
if (files == 0) {
printf("Usage : %s [--debug] [--noout] schemas XMLfiles ...\n",
argv[0]);
printf("\tParse the HTML files and output the result of the parsing\n");
#ifdef LIBXML_DEBUG_ENABLED
printf("\t--debug : dump a debug tree of the in-memory document\n");
#endif
printf("\t--noout : do not print the result\n");
#ifdef HAVE_MMAP
printf("\t--memory : test the schemas in memory parsing\n");
#endif
}
failed_schemas:
xmlSchemaCleanupTypes();
xmlCleanupParser();
xmlMemoryDump();
return(0);
}
#else
#include <stdio.h>
int main(int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED) {
printf("%s : Schemas support not compiled in\n", argv[0]);
return(0);
}
#endif /* LIBXML_SCHEMAS_ENABLED */
| null | null | null | null | 25,926 |
2,556 | null | train_val | 04b570817b2b38e35675b17328239746212f4c3f | 155,613 | FFmpeg | 0 | https://github.com/FFmpeg/FFmpeg | 2018-06-01 01:23:12+05:30 | /*
* Copyright (c) 2009 David Conrad <lessen42@gmail.com>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include "libavutil/attributes.h"
#include "libavutil/cpu.h"
#include "libavutil/x86/cpu.h"
#include "libavcodec/avcodec.h"
#include "libavcodec/vp3dsp.h"
void ff_vp3_idct_put_mmx(uint8_t *dest, ptrdiff_t stride, int16_t *block);
void ff_vp3_idct_add_mmx(uint8_t *dest, ptrdiff_t stride, int16_t *block);
void ff_vp3_idct_put_sse2(uint8_t *dest, ptrdiff_t stride, int16_t *block);
void ff_vp3_idct_add_sse2(uint8_t *dest, ptrdiff_t stride, int16_t *block);
void ff_vp3_idct_dc_add_mmxext(uint8_t *dest, ptrdiff_t stride, int16_t *block);
void ff_vp3_v_loop_filter_mmxext(uint8_t *src, ptrdiff_t stride,
int *bounding_values);
void ff_vp3_h_loop_filter_mmxext(uint8_t *src, ptrdiff_t stride,
int *bounding_values);
void ff_put_vp_no_rnd_pixels8_l2_mmx(uint8_t *dst, const uint8_t *a,
const uint8_t *b, ptrdiff_t stride,
int h);
av_cold void ff_vp3dsp_init_x86(VP3DSPContext *c, int flags)
{
int cpu_flags = av_get_cpu_flags();
if (EXTERNAL_MMX(cpu_flags)) {
c->put_no_rnd_pixels_l2 = ff_put_vp_no_rnd_pixels8_l2_mmx;
#if ARCH_X86_32
c->idct_put = ff_vp3_idct_put_mmx;
c->idct_add = ff_vp3_idct_add_mmx;
#endif
}
if (EXTERNAL_MMXEXT(cpu_flags)) {
c->idct_dc_add = ff_vp3_idct_dc_add_mmxext;
if (!(flags & AV_CODEC_FLAG_BITEXACT)) {
c->v_loop_filter = ff_vp3_v_loop_filter_mmxext;
c->h_loop_filter = ff_vp3_h_loop_filter_mmxext;
}
}
if (EXTERNAL_SSE2(cpu_flags)) {
c->idct_put = ff_vp3_idct_put_sse2;
c->idct_add = ff_vp3_idct_add_sse2;
}
}
| null | null | null | null | 71,668 |
16,855 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 181,850 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* arch/sh/kernel/stacktrace.c
*
* Stack trace management functions
*
* Copyright (C) 2006 - 2008 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/sched.h>
#include <linux/sched/debug.h>
#include <linux/stacktrace.h>
#include <linux/thread_info.h>
#include <linux/module.h>
#include <asm/unwinder.h>
#include <asm/ptrace.h>
#include <asm/stacktrace.h>
static int save_stack_stack(void *data, char *name)
{
return 0;
}
/*
* Save stack-backtrace addresses into a stack_trace buffer.
*/
static void save_stack_address(void *data, unsigned long addr, int reliable)
{
struct stack_trace *trace = data;
if (!reliable)
return;
if (trace->skip > 0) {
trace->skip--;
return;
}
if (trace->nr_entries < trace->max_entries)
trace->entries[trace->nr_entries++] = addr;
}
static const struct stacktrace_ops save_stack_ops = {
.stack = save_stack_stack,
.address = save_stack_address,
};
void save_stack_trace(struct stack_trace *trace)
{
unsigned long *sp = (unsigned long *)current_stack_pointer;
unwind_stack(current, NULL, sp, &save_stack_ops, trace);
if (trace->nr_entries < trace->max_entries)
trace->entries[trace->nr_entries++] = ULONG_MAX;
}
EXPORT_SYMBOL_GPL(save_stack_trace);
static void
save_stack_address_nosched(void *data, unsigned long addr, int reliable)
{
struct stack_trace *trace = (struct stack_trace *)data;
if (!reliable)
return;
if (in_sched_functions(addr))
return;
if (trace->skip > 0) {
trace->skip--;
return;
}
if (trace->nr_entries < trace->max_entries)
trace->entries[trace->nr_entries++] = addr;
}
static const struct stacktrace_ops save_stack_ops_nosched = {
.stack = save_stack_stack,
.address = save_stack_address_nosched,
};
void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
{
unsigned long *sp = (unsigned long *)tsk->thread.sp;
unwind_stack(current, NULL, sp, &save_stack_ops_nosched, trace);
if (trace->nr_entries < trace->max_entries)
trace->entries[trace->nr_entries++] = ULONG_MAX;
}
EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
| null | null | null | null | 90,197 |
56,457 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 56,457 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chrome/browser/chromeos/login/users/avatar/user_image_manager_test_util.h"
#include <stddef.h>
#include <stdint.h>
#include <string>
#include <utility>
#include "base/files/file_util.h"
#include "base/memory/ref_counted.h"
#include "base/threading/thread_task_runner_handle.h"
#include "third_party/skia/include/core/SkBitmap.h"
#include "ui/gfx/image/image_skia.h"
#include "ui/gfx/image/image_skia_rep.h"
namespace chromeos {
namespace test {
const char kUserAvatarImage1RelativePath[] = "chromeos/avatar1.jpg";
const char kUserAvatarImage2RelativePath[] = "chromeos/avatar2.jpg";
const char kUserAvatarImage3RelativePath[] = "chromeos/avatar3.png";
bool AreImagesEqual(const gfx::ImageSkia& first, const gfx::ImageSkia& second) {
if (first.width() != second.width() || first.height() != second.height())
return false;
const SkBitmap* first_bitmap = first.bitmap();
const SkBitmap* second_bitmap = second.bitmap();
if (!first_bitmap && !second_bitmap)
return true;
if (!first_bitmap || !second_bitmap)
return false;
const size_t size = first_bitmap->computeByteSize();
if (second_bitmap->computeByteSize() != size)
return false;
uint8_t* first_data = reinterpret_cast<uint8_t*>(first_bitmap->getPixels());
uint8_t* second_data = reinterpret_cast<uint8_t*>(second_bitmap->getPixels());
for (size_t i = 0; i < size; ++i) {
if (first_data[i] != second_data[i])
return false;
}
return true;
}
ImageLoader::ImageLoader(const base::FilePath& path) : path_(path) {}
ImageLoader::~ImageLoader() {}
std::unique_ptr<gfx::ImageSkia> ImageLoader::Load() {
std::string image_data;
ReadFileToString(path_, &image_data);
const ImageDecoder::ImageCodec codec =
(path_.Extension() == FILE_PATH_LITERAL(".jpg")
? ImageDecoder::ROBUST_JPEG_CODEC
: ImageDecoder::ROBUST_PNG_CODEC);
ImageDecoder::StartWithOptions(this, image_data, codec, false);
run_loop_.Run();
return std::move(decoded_image_);
}
void ImageLoader::OnImageDecoded(const SkBitmap& decoded_image) {
decoded_image_.reset(
new gfx::ImageSkia(gfx::ImageSkiaRep(decoded_image, 1.0f)));
run_loop_.Quit();
}
void ImageLoader::OnDecodeImageFailed() {
run_loop_.Quit();
}
} // namespace test
} // namespace chromeos
| null | null | null | null | 53,320 |
16,101 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 16,101 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include <string>
#include "base/android/jni_android.h"
#include "base/android/jni_string.h"
#include "components/sync/base/model_type.h"
#include "jni/ModelTypeHelper_jni.h"
using base::android::JavaParamRef;
using base::android::ScopedJavaLocalRef;
namespace syncer {
static ScopedJavaLocalRef<jstring>
JNI_ModelTypeHelper_ModelTypeToNotificationType(
JNIEnv* env,
const JavaParamRef<jclass>& clazz,
jint model_type_int) {
std::string model_type_string;
ModelType model_type = static_cast<ModelType>(model_type_int);
if (!RealModelTypeToNotificationType(model_type, &model_type_string)) {
NOTREACHED() << "No string representation of model type " << model_type;
}
return base::android::ConvertUTF8ToJavaString(env, model_type_string);
}
} // namespace syncer
| null | null | null | null | 12,964 |
672 | null | train_val | 1b0d3845b454eaaac0b2064c78926ca4d739a080 | 263,240 | qemu | 0 | https://github.com/bonzini/qemu | 2016-10-18 11:40:27+01:00 |
void glue(glue(test_, OP), b)(long op0, long op1)
{
long res, s1, s0, flags;
s0 = op0;
s1 = op1;
res = s0;
flags = 0;
asm ("push %4\n\t"
"popf\n\t"
stringify(OP)"b %b2\n\t"
"pushf\n\t"
"pop %1\n\t"
: "=a" (res), "=g" (flags)
: "q" (s1), "0" (res), "1" (flags));
printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
stringify(OP) "b", s0, s1, res, flags & CC_MASK);
}
void glue(glue(test_, OP), w)(long op0h, long op0, long op1)
{
long res, s1, flags, resh;
s1 = op1;
resh = op0h;
res = op0;
flags = 0;
asm ("push %5\n\t"
"popf\n\t"
stringify(OP) "w %w3\n\t"
"pushf\n\t"
"pop %1\n\t"
: "=a" (res), "=g" (flags), "=d" (resh)
: "q" (s1), "0" (res), "1" (flags), "2" (resh));
printf("%-10s AH=" FMTLX " AL=" FMTLX " B=" FMTLX " RH=" FMTLX " RL=" FMTLX " CC=%04lx\n",
stringify(OP) "w", op0h, op0, s1, resh, res, flags & CC_MASK);
}
void glue(glue(test_, OP), l)(long op0h, long op0, long op1)
{
long res, s1, flags, resh;
s1 = op1;
resh = op0h;
res = op0;
flags = 0;
asm ("push %5\n\t"
"popf\n\t"
stringify(OP) "l %k3\n\t"
"pushf\n\t"
"pop %1\n\t"
: "=a" (res), "=g" (flags), "=d" (resh)
: "q" (s1), "0" (res), "1" (flags), "2" (resh));
printf("%-10s AH=" FMTLX " AL=" FMTLX " B=" FMTLX " RH=" FMTLX " RL=" FMTLX " CC=%04lx\n",
stringify(OP) "l", op0h, op0, s1, resh, res, flags & CC_MASK);
}
#if defined(__x86_64__)
void glue(glue(test_, OP), q)(long op0h, long op0, long op1)
{
long res, s1, flags, resh;
s1 = op1;
resh = op0h;
res = op0;
flags = 0;
asm ("push %5\n\t"
"popf\n\t"
stringify(OP) "q %3\n\t"
"pushf\n\t"
"pop %1\n\t"
: "=a" (res), "=g" (flags), "=d" (resh)
: "q" (s1), "0" (res), "1" (flags), "2" (resh));
printf("%-10s AH=" FMTLX " AL=" FMTLX " B=" FMTLX " RH=" FMTLX " RL=" FMTLX " CC=%04lx\n",
stringify(OP) "q", op0h, op0, s1, resh, res, flags & CC_MASK);
}
#endif
#undef OP
| null | null | null | null | 121,364 |
42,237 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 42,237 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2011 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef BASE_BIND_INTERNAL_H_
#define BASE_BIND_INTERNAL_H_
#include <stddef.h>
#include <type_traits>
#include <utility>
#include "base/callback_internal.h"
#include "base/memory/raw_scoped_refptr_mismatch_checker.h"
#include "base/memory/weak_ptr.h"
#include "base/template_util.h"
#include "build/build_config.h"
// See base/callback.h for user documentation.
//
//
// CONCEPTS:
// Functor -- A movable type representing something that should be called.
// All function pointers and Callback<> are functors even if the
// invocation syntax differs.
// RunType -- A function type (as opposed to function _pointer_ type) for
// a Callback<>::Run(). Usually just a convenience typedef.
// (Bound)Args -- A set of types that stores the arguments.
//
// Types:
// ForceVoidReturn<> -- Helper class for translating function signatures to
// equivalent forms with a "void" return type.
// FunctorTraits<> -- Type traits used to determine the correct RunType and
// invocation manner for a Functor. This is where function
// signature adapters are applied.
// InvokeHelper<> -- Take a Functor + arguments and actully invokes it.
// Handle the differing syntaxes needed for WeakPtr<>
// support. This is separate from Invoker to avoid creating
// multiple version of Invoker<>.
// Invoker<> -- Unwraps the curried parameters and executes the Functor.
// BindState<> -- Stores the curried parameters, and is the main entry point
// into the Bind() system.
namespace base {
template <typename T>
struct IsWeakReceiver;
template <typename>
struct BindUnwrapTraits;
template <typename Functor, typename BoundArgsTuple, typename SFINAE = void>
struct CallbackCancellationTraits;
namespace internal {
template <typename Functor, typename SFINAE = void>
struct FunctorTraits;
template <typename T>
class UnretainedWrapper {
public:
explicit UnretainedWrapper(T* o) : ptr_(o) {}
T* get() const { return ptr_; }
private:
T* ptr_;
};
template <typename T>
class ConstRefWrapper {
public:
explicit ConstRefWrapper(const T& o) : ptr_(&o) {}
const T& get() const { return *ptr_; }
private:
const T* ptr_;
};
template <typename T>
class RetainedRefWrapper {
public:
explicit RetainedRefWrapper(T* o) : ptr_(o) {}
explicit RetainedRefWrapper(scoped_refptr<T> o) : ptr_(std::move(o)) {}
T* get() const { return ptr_.get(); }
private:
scoped_refptr<T> ptr_;
};
template <typename T>
struct IgnoreResultHelper {
explicit IgnoreResultHelper(T functor) : functor_(std::move(functor)) {}
explicit operator bool() const { return !!functor_; }
T functor_;
};
// An alternate implementation is to avoid the destructive copy, and instead
// specialize ParamTraits<> for OwnedWrapper<> to change the StorageType to
// a class that is essentially a std::unique_ptr<>.
//
// The current implementation has the benefit though of leaving ParamTraits<>
// fully in callback_internal.h as well as avoiding type conversions during
// storage.
template <typename T>
class OwnedWrapper {
public:
explicit OwnedWrapper(T* o) : ptr_(o) {}
~OwnedWrapper() { delete ptr_; }
T* get() const { return ptr_; }
OwnedWrapper(OwnedWrapper&& other) {
ptr_ = other.ptr_;
other.ptr_ = NULL;
}
private:
mutable T* ptr_;
};
// PassedWrapper is a copyable adapter for a scoper that ignores const.
//
// It is needed to get around the fact that Bind() takes a const reference to
// all its arguments. Because Bind() takes a const reference to avoid
// unnecessary copies, it is incompatible with movable-but-not-copyable
// types; doing a destructive "move" of the type into Bind() would violate
// the const correctness.
//
// This conundrum cannot be solved without either C++11 rvalue references or
// a O(2^n) blowup of Bind() templates to handle each combination of regular
// types and movable-but-not-copyable types. Thus we introduce a wrapper type
// that is copyable to transmit the correct type information down into
// BindState<>. Ignoring const in this type makes sense because it is only
// created when we are explicitly trying to do a destructive move.
//
// Two notes:
// 1) PassedWrapper supports any type that has a move constructor, however
// the type will need to be specifically whitelisted in order for it to be
// bound to a Callback. We guard this explicitly at the call of Passed()
// to make for clear errors. Things not given to Passed() will be forwarded
// and stored by value which will not work for general move-only types.
// 2) is_valid_ is distinct from NULL because it is valid to bind a "NULL"
// scoper to a Callback and allow the Callback to execute once.
template <typename T>
class PassedWrapper {
public:
explicit PassedWrapper(T&& scoper)
: is_valid_(true), scoper_(std::move(scoper)) {}
PassedWrapper(PassedWrapper&& other)
: is_valid_(other.is_valid_), scoper_(std::move(other.scoper_)) {}
T Take() const {
CHECK(is_valid_);
is_valid_ = false;
return std::move(scoper_);
}
private:
mutable bool is_valid_;
mutable T scoper_;
};
template <typename T>
using Unwrapper = BindUnwrapTraits<std::decay_t<T>>;
template <typename T>
decltype(auto) Unwrap(T&& o) {
return Unwrapper<T>::Unwrap(std::forward<T>(o));
}
// IsWeakMethod is a helper that determine if we are binding a WeakPtr<> to a
// method. It is used internally by Bind() to select the correct
// InvokeHelper that will no-op itself in the event the WeakPtr<> for
// the target object is invalidated.
//
// The first argument should be the type of the object that will be received by
// the method.
template <bool is_method, typename... Args>
struct IsWeakMethod : std::false_type {};
template <typename T, typename... Args>
struct IsWeakMethod<true, T, Args...> : IsWeakReceiver<T> {};
// Packs a list of types to hold them in a single type.
template <typename... Types>
struct TypeList {};
// Used for DropTypeListItem implementation.
template <size_t n, typename List>
struct DropTypeListItemImpl;
// Do not use enable_if and SFINAE here to avoid MSVC2013 compile failure.
template <size_t n, typename T, typename... List>
struct DropTypeListItemImpl<n, TypeList<T, List...>>
: DropTypeListItemImpl<n - 1, TypeList<List...>> {};
template <typename T, typename... List>
struct DropTypeListItemImpl<0, TypeList<T, List...>> {
using Type = TypeList<T, List...>;
};
template <>
struct DropTypeListItemImpl<0, TypeList<>> {
using Type = TypeList<>;
};
// A type-level function that drops |n| list item from given TypeList.
template <size_t n, typename List>
using DropTypeListItem = typename DropTypeListItemImpl<n, List>::Type;
// Used for TakeTypeListItem implementation.
template <size_t n, typename List, typename... Accum>
struct TakeTypeListItemImpl;
// Do not use enable_if and SFINAE here to avoid MSVC2013 compile failure.
template <size_t n, typename T, typename... List, typename... Accum>
struct TakeTypeListItemImpl<n, TypeList<T, List...>, Accum...>
: TakeTypeListItemImpl<n - 1, TypeList<List...>, Accum..., T> {};
template <typename T, typename... List, typename... Accum>
struct TakeTypeListItemImpl<0, TypeList<T, List...>, Accum...> {
using Type = TypeList<Accum...>;
};
template <typename... Accum>
struct TakeTypeListItemImpl<0, TypeList<>, Accum...> {
using Type = TypeList<Accum...>;
};
// A type-level function that takes first |n| list item from given TypeList.
// E.g. TakeTypeListItem<3, TypeList<A, B, C, D>> is evaluated to
// TypeList<A, B, C>.
template <size_t n, typename List>
using TakeTypeListItem = typename TakeTypeListItemImpl<n, List>::Type;
// Used for ConcatTypeLists implementation.
template <typename List1, typename List2>
struct ConcatTypeListsImpl;
template <typename... Types1, typename... Types2>
struct ConcatTypeListsImpl<TypeList<Types1...>, TypeList<Types2...>> {
using Type = TypeList<Types1..., Types2...>;
};
// A type-level function that concats two TypeLists.
template <typename List1, typename List2>
using ConcatTypeLists = typename ConcatTypeListsImpl<List1, List2>::Type;
// Used for MakeFunctionType implementation.
template <typename R, typename ArgList>
struct MakeFunctionTypeImpl;
template <typename R, typename... Args>
struct MakeFunctionTypeImpl<R, TypeList<Args...>> {
// MSVC 2013 doesn't support Type Alias of function types.
// Revisit this after we update it to newer version.
typedef R Type(Args...);
};
// A type-level function that constructs a function type that has |R| as its
// return type and has TypeLists items as its arguments.
template <typename R, typename ArgList>
using MakeFunctionType = typename MakeFunctionTypeImpl<R, ArgList>::Type;
// Used for ExtractArgs and ExtractReturnType.
template <typename Signature>
struct ExtractArgsImpl;
template <typename R, typename... Args>
struct ExtractArgsImpl<R(Args...)> {
using ReturnType = R;
using ArgsList = TypeList<Args...>;
};
// A type-level function that extracts function arguments into a TypeList.
// E.g. ExtractArgs<R(A, B, C)> is evaluated to TypeList<A, B, C>.
template <typename Signature>
using ExtractArgs = typename ExtractArgsImpl<Signature>::ArgsList;
// A type-level function that extracts the return type of a function.
// E.g. ExtractReturnType<R(A, B, C)> is evaluated to R.
template <typename Signature>
using ExtractReturnType = typename ExtractArgsImpl<Signature>::ReturnType;
template <typename Callable,
typename Signature = decltype(&Callable::operator())>
struct ExtractCallableRunTypeImpl;
template <typename Callable, typename R, typename... Args>
struct ExtractCallableRunTypeImpl<Callable, R (Callable::*)(Args...)> {
using Type = R(Args...);
};
template <typename Callable, typename R, typename... Args>
struct ExtractCallableRunTypeImpl<Callable, R (Callable::*)(Args...) const> {
using Type = R(Args...);
};
// Evaluated to RunType of the given callable type.
// Example:
// auto f = [](int, char*) { return 0.1; };
// ExtractCallableRunType<decltype(f)>
// is evaluated to
// double(int, char*);
template <typename Callable>
using ExtractCallableRunType =
typename ExtractCallableRunTypeImpl<Callable>::Type;
// IsCallableObject<Functor> is std::true_type if |Functor| has operator().
// Otherwise, it's std::false_type.
// Example:
// IsCallableObject<void(*)()>::value is false.
//
// struct Foo {};
// IsCallableObject<void(Foo::*)()>::value is false.
//
// int i = 0;
// auto f = [i]() {};
// IsCallableObject<decltype(f)>::value is false.
template <typename Functor, typename SFINAE = void>
struct IsCallableObject : std::false_type {};
template <typename Callable>
struct IsCallableObject<Callable, void_t<decltype(&Callable::operator())>>
: std::true_type {};
// HasRefCountedTypeAsRawPtr selects true_type when any of the |Args| is a raw
// pointer to a RefCounted type.
// Implementation note: This non-specialized case handles zero-arity case only.
// Non-zero-arity cases should be handled by the specialization below.
template <typename... Args>
struct HasRefCountedTypeAsRawPtr : std::false_type {};
// Implementation note: Select true_type if the first parameter is a raw pointer
// to a RefCounted type. Otherwise, skip the first parameter and check rest of
// parameters recursively.
template <typename T, typename... Args>
struct HasRefCountedTypeAsRawPtr<T, Args...>
: std::conditional_t<NeedsScopedRefptrButGetsRawPtr<T>::value,
std::true_type,
HasRefCountedTypeAsRawPtr<Args...>> {};
// ForceVoidReturn<>
//
// Set of templates that support forcing the function return type to void.
template <typename Sig>
struct ForceVoidReturn;
template <typename R, typename... Args>
struct ForceVoidReturn<R(Args...)> {
using RunType = void(Args...);
};
// FunctorTraits<>
//
// See description at top of file.
template <typename Functor, typename SFINAE>
struct FunctorTraits;
// For empty callable types.
// This specialization is intended to allow binding captureless lambdas by
// base::Bind(), based on the fact that captureless lambdas are empty while
// capturing lambdas are not. This also allows any functors as far as it's an
// empty class.
// Example:
//
// // Captureless lambdas are allowed.
// []() {return 42;};
//
// // Capturing lambdas are *not* allowed.
// int x;
// [x]() {return x;};
//
// // Any empty class with operator() is allowed.
// struct Foo {
// void operator()() const {}
// // No non-static member variable and no virtual functions.
// };
template <typename Functor>
struct FunctorTraits<Functor,
std::enable_if_t<IsCallableObject<Functor>::value &&
std::is_empty<Functor>::value>> {
using RunType = ExtractCallableRunType<Functor>;
static constexpr bool is_method = false;
static constexpr bool is_nullable = false;
template <typename RunFunctor, typename... RunArgs>
static ExtractReturnType<RunType> Invoke(RunFunctor&& functor,
RunArgs&&... args) {
return std::forward<RunFunctor>(functor)(std::forward<RunArgs>(args)...);
}
};
// For functions.
template <typename R, typename... Args>
struct FunctorTraits<R (*)(Args...)> {
using RunType = R(Args...);
static constexpr bool is_method = false;
static constexpr bool is_nullable = true;
template <typename... RunArgs>
static R Invoke(R (*function)(Args...), RunArgs&&... args) {
return function(std::forward<RunArgs>(args)...);
}
};
#if defined(OS_WIN) && !defined(ARCH_CPU_X86_64)
// For functions.
template <typename R, typename... Args>
struct FunctorTraits<R(__stdcall*)(Args...)> {
using RunType = R(Args...);
static constexpr bool is_method = false;
static constexpr bool is_nullable = true;
template <typename... RunArgs>
static R Invoke(R(__stdcall* function)(Args...), RunArgs&&... args) {
return function(std::forward<RunArgs>(args)...);
}
};
// For functions.
template <typename R, typename... Args>
struct FunctorTraits<R(__fastcall*)(Args...)> {
using RunType = R(Args...);
static constexpr bool is_method = false;
static constexpr bool is_nullable = true;
template <typename... RunArgs>
static R Invoke(R(__fastcall* function)(Args...), RunArgs&&... args) {
return function(std::forward<RunArgs>(args)...);
}
};
#endif // defined(OS_WIN) && !defined(ARCH_CPU_X86_64)
// For methods.
template <typename R, typename Receiver, typename... Args>
struct FunctorTraits<R (Receiver::*)(Args...)> {
using RunType = R(Receiver*, Args...);
static constexpr bool is_method = true;
static constexpr bool is_nullable = true;
template <typename ReceiverPtr, typename... RunArgs>
static R Invoke(R (Receiver::*method)(Args...),
ReceiverPtr&& receiver_ptr,
RunArgs&&... args) {
return ((*receiver_ptr).*method)(std::forward<RunArgs>(args)...);
}
};
// For const methods.
template <typename R, typename Receiver, typename... Args>
struct FunctorTraits<R (Receiver::*)(Args...) const> {
using RunType = R(const Receiver*, Args...);
static constexpr bool is_method = true;
static constexpr bool is_nullable = true;
template <typename ReceiverPtr, typename... RunArgs>
static R Invoke(R (Receiver::*method)(Args...) const,
ReceiverPtr&& receiver_ptr,
RunArgs&&... args) {
return ((*receiver_ptr).*method)(std::forward<RunArgs>(args)...);
}
};
// For IgnoreResults.
template <typename T>
struct FunctorTraits<IgnoreResultHelper<T>> : FunctorTraits<T> {
using RunType =
typename ForceVoidReturn<typename FunctorTraits<T>::RunType>::RunType;
template <typename IgnoreResultType, typename... RunArgs>
static void Invoke(IgnoreResultType&& ignore_result_helper,
RunArgs&&... args) {
FunctorTraits<T>::Invoke(
std::forward<IgnoreResultType>(ignore_result_helper).functor_,
std::forward<RunArgs>(args)...);
}
};
// For OnceCallbacks.
template <typename R, typename... Args>
struct FunctorTraits<OnceCallback<R(Args...)>> {
using RunType = R(Args...);
static constexpr bool is_method = false;
static constexpr bool is_nullable = true;
template <typename CallbackType, typename... RunArgs>
static R Invoke(CallbackType&& callback, RunArgs&&... args) {
DCHECK(!callback.is_null());
return std::forward<CallbackType>(callback).Run(
std::forward<RunArgs>(args)...);
}
};
// For RepeatingCallbacks.
template <typename R, typename... Args>
struct FunctorTraits<RepeatingCallback<R(Args...)>> {
using RunType = R(Args...);
static constexpr bool is_method = false;
static constexpr bool is_nullable = true;
template <typename CallbackType, typename... RunArgs>
static R Invoke(CallbackType&& callback, RunArgs&&... args) {
DCHECK(!callback.is_null());
return std::forward<CallbackType>(callback).Run(
std::forward<RunArgs>(args)...);
}
};
template <typename Functor>
using MakeFunctorTraits = FunctorTraits<std::decay_t<Functor>>;
// InvokeHelper<>
//
// There are 2 logical InvokeHelper<> specializations: normal, WeakCalls.
//
// The normal type just calls the underlying runnable.
//
// WeakCalls need special syntax that is applied to the first argument to check
// if they should no-op themselves.
template <bool is_weak_call, typename ReturnType>
struct InvokeHelper;
template <typename ReturnType>
struct InvokeHelper<false, ReturnType> {
template <typename Functor, typename... RunArgs>
static inline ReturnType MakeItSo(Functor&& functor, RunArgs&&... args) {
using Traits = MakeFunctorTraits<Functor>;
return Traits::Invoke(std::forward<Functor>(functor),
std::forward<RunArgs>(args)...);
}
};
template <typename ReturnType>
struct InvokeHelper<true, ReturnType> {
// WeakCalls are only supported for functions with a void return type.
// Otherwise, the function result would be undefined if the the WeakPtr<>
// is invalidated.
static_assert(std::is_void<ReturnType>::value,
"weak_ptrs can only bind to methods without return values");
template <typename Functor, typename BoundWeakPtr, typename... RunArgs>
static inline void MakeItSo(Functor&& functor,
BoundWeakPtr&& weak_ptr,
RunArgs&&... args) {
if (!weak_ptr)
return;
using Traits = MakeFunctorTraits<Functor>;
Traits::Invoke(std::forward<Functor>(functor),
std::forward<BoundWeakPtr>(weak_ptr),
std::forward<RunArgs>(args)...);
}
};
// Invoker<>
//
// See description at the top of the file.
template <typename StorageType, typename UnboundRunType>
struct Invoker;
template <typename StorageType, typename R, typename... UnboundArgs>
struct Invoker<StorageType, R(UnboundArgs...)> {
static R RunOnce(BindStateBase* base,
PassingTraitsType<UnboundArgs>... unbound_args) {
// Local references to make debugger stepping easier. If in a debugger,
// you really want to warp ahead and step through the
// InvokeHelper<>::MakeItSo() call below.
StorageType* storage = static_cast<StorageType*>(base);
static constexpr size_t num_bound_args =
std::tuple_size<decltype(storage->bound_args_)>::value;
return RunImpl(std::move(storage->functor_),
std::move(storage->bound_args_),
std::make_index_sequence<num_bound_args>(),
std::forward<UnboundArgs>(unbound_args)...);
}
static R Run(BindStateBase* base,
PassingTraitsType<UnboundArgs>... unbound_args) {
// Local references to make debugger stepping easier. If in a debugger,
// you really want to warp ahead and step through the
// InvokeHelper<>::MakeItSo() call below.
const StorageType* storage = static_cast<StorageType*>(base);
static constexpr size_t num_bound_args =
std::tuple_size<decltype(storage->bound_args_)>::value;
return RunImpl(storage->functor_, storage->bound_args_,
std::make_index_sequence<num_bound_args>(),
std::forward<UnboundArgs>(unbound_args)...);
}
private:
template <typename Functor, typename BoundArgsTuple, size_t... indices>
static inline R RunImpl(Functor&& functor,
BoundArgsTuple&& bound,
std::index_sequence<indices...>,
UnboundArgs&&... unbound_args) {
static constexpr bool is_method = MakeFunctorTraits<Functor>::is_method;
using DecayedArgsTuple = std::decay_t<BoundArgsTuple>;
static constexpr bool is_weak_call =
IsWeakMethod<is_method,
std::tuple_element_t<indices, DecayedArgsTuple>...>();
return InvokeHelper<is_weak_call, R>::MakeItSo(
std::forward<Functor>(functor),
Unwrap(std::get<indices>(std::forward<BoundArgsTuple>(bound)))...,
std::forward<UnboundArgs>(unbound_args)...);
}
};
// Extracts necessary type info from Functor and BoundArgs.
// Used to implement MakeUnboundRunType, BindOnce and BindRepeating.
template <typename Functor, typename... BoundArgs>
struct BindTypeHelper {
static constexpr size_t num_bounds = sizeof...(BoundArgs);
using FunctorTraits = MakeFunctorTraits<Functor>;
// Example:
// When Functor is `double (Foo::*)(int, const std::string&)`, and BoundArgs
// is a template pack of `Foo*` and `int16_t`:
// - RunType is `double(Foo*, int, const std::string&)`,
// - ReturnType is `double`,
// - RunParamsList is `TypeList<Foo*, int, const std::string&>`,
// - BoundParamsList is `TypeList<Foo*, int>`,
// - UnboundParamsList is `TypeList<const std::string&>`,
// - BoundArgsList is `TypeList<Foo*, int16_t>`,
// - UnboundRunType is `double(const std::string&)`.
using RunType = typename FunctorTraits::RunType;
using ReturnType = ExtractReturnType<RunType>;
using RunParamsList = ExtractArgs<RunType>;
using BoundParamsList = TakeTypeListItem<num_bounds, RunParamsList>;
using UnboundParamsList = DropTypeListItem<num_bounds, RunParamsList>;
using BoundArgsList = TypeList<BoundArgs...>;
using UnboundRunType = MakeFunctionType<ReturnType, UnboundParamsList>;
};
template <typename Functor>
std::enable_if_t<FunctorTraits<Functor>::is_nullable, bool> IsNull(
const Functor& functor) {
return !functor;
}
template <typename Functor>
std::enable_if_t<!FunctorTraits<Functor>::is_nullable, bool> IsNull(
const Functor&) {
return false;
}
// Used by ApplyCancellationTraits below.
template <typename Functor, typename BoundArgsTuple, size_t... indices>
bool ApplyCancellationTraitsImpl(const Functor& functor,
const BoundArgsTuple& bound_args,
std::index_sequence<indices...>) {
return CallbackCancellationTraits<Functor, BoundArgsTuple>::IsCancelled(
functor, std::get<indices>(bound_args)...);
}
// Relays |base| to corresponding CallbackCancellationTraits<>::Run(). Returns
// true if the callback |base| represents is canceled.
template <typename BindStateType>
bool ApplyCancellationTraits(const BindStateBase* base) {
const BindStateType* storage = static_cast<const BindStateType*>(base);
static constexpr size_t num_bound_args =
std::tuple_size<decltype(storage->bound_args_)>::value;
return ApplyCancellationTraitsImpl(
storage->functor_, storage->bound_args_,
std::make_index_sequence<num_bound_args>());
};
// BindState<>
//
// This stores all the state passed into Bind().
template <typename Functor, typename... BoundArgs>
struct BindState final : BindStateBase {
using IsCancellable = std::integral_constant<
bool,
CallbackCancellationTraits<Functor,
std::tuple<BoundArgs...>>::is_cancellable>;
template <typename ForwardFunctor, typename... ForwardBoundArgs>
explicit BindState(BindStateBase::InvokeFuncStorage invoke_func,
ForwardFunctor&& functor,
ForwardBoundArgs&&... bound_args)
// IsCancellable is std::false_type if
// CallbackCancellationTraits<>::IsCancelled returns always false.
// Otherwise, it's std::true_type.
: BindState(IsCancellable{},
invoke_func,
std::forward<ForwardFunctor>(functor),
std::forward<ForwardBoundArgs>(bound_args)...) {}
Functor functor_;
std::tuple<BoundArgs...> bound_args_;
private:
template <typename ForwardFunctor, typename... ForwardBoundArgs>
explicit BindState(std::true_type,
BindStateBase::InvokeFuncStorage invoke_func,
ForwardFunctor&& functor,
ForwardBoundArgs&&... bound_args)
: BindStateBase(invoke_func,
&Destroy,
&ApplyCancellationTraits<BindState>),
functor_(std::forward<ForwardFunctor>(functor)),
bound_args_(std::forward<ForwardBoundArgs>(bound_args)...) {
DCHECK(!IsNull(functor_));
}
template <typename ForwardFunctor, typename... ForwardBoundArgs>
explicit BindState(std::false_type,
BindStateBase::InvokeFuncStorage invoke_func,
ForwardFunctor&& functor,
ForwardBoundArgs&&... bound_args)
: BindStateBase(invoke_func, &Destroy),
functor_(std::forward<ForwardFunctor>(functor)),
bound_args_(std::forward<ForwardBoundArgs>(bound_args)...) {
DCHECK(!IsNull(functor_));
}
~BindState() = default;
static void Destroy(const BindStateBase* self) {
delete static_cast<const BindState*>(self);
}
};
// Used to implement MakeBindStateType.
template <bool is_method, typename Functor, typename... BoundArgs>
struct MakeBindStateTypeImpl;
template <typename Functor, typename... BoundArgs>
struct MakeBindStateTypeImpl<false, Functor, BoundArgs...> {
static_assert(!HasRefCountedTypeAsRawPtr<std::decay_t<BoundArgs>...>::value,
"A parameter is a refcounted type and needs scoped_refptr.");
using Type = BindState<std::decay_t<Functor>, std::decay_t<BoundArgs>...>;
};
template <typename Functor>
struct MakeBindStateTypeImpl<true, Functor> {
using Type = BindState<std::decay_t<Functor>>;
};
template <typename Functor, typename Receiver, typename... BoundArgs>
struct MakeBindStateTypeImpl<true, Functor, Receiver, BoundArgs...> {
private:
using DecayedReceiver = std::decay_t<Receiver>;
static_assert(!std::is_array<std::remove_reference_t<Receiver>>::value,
"First bound argument to a method cannot be an array.");
static_assert(
!std::is_pointer<DecayedReceiver>::value ||
IsRefCountedType<std::remove_pointer_t<DecayedReceiver>>::value,
"Receivers may not be raw pointers. If using a raw pointer here is safe"
" and has no lifetime concerns, use base::Unretained() and document why"
" it's safe.");
static_assert(!HasRefCountedTypeAsRawPtr<std::decay_t<BoundArgs>...>::value,
"A parameter is a refcounted type and needs scoped_refptr.");
public:
using Type = BindState<
std::decay_t<Functor>,
std::conditional_t<std::is_pointer<DecayedReceiver>::value,
scoped_refptr<std::remove_pointer_t<DecayedReceiver>>,
DecayedReceiver>,
std::decay_t<BoundArgs>...>;
};
template <typename Functor, typename... BoundArgs>
using MakeBindStateType =
typename MakeBindStateTypeImpl<MakeFunctorTraits<Functor>::is_method,
Functor,
BoundArgs...>::Type;
} // namespace internal
// An injection point to control |this| pointer behavior on a method invocation.
// If IsWeakReceiver<> is true_type for |T| and |T| is used for a receiver of a
// method, base::Bind cancels the method invocation if the receiver is tested as
// false.
// E.g. Foo::bar() is not called:
// struct Foo : base::SupportsWeakPtr<Foo> {
// void bar() {}
// };
//
// WeakPtr<Foo> oo = nullptr;
// base::Bind(&Foo::bar, oo).Run();
template <typename T>
struct IsWeakReceiver : std::false_type {};
template <typename T>
struct IsWeakReceiver<internal::ConstRefWrapper<T>> : IsWeakReceiver<T> {};
template <typename T>
struct IsWeakReceiver<WeakPtr<T>> : std::true_type {};
// An injection point to control how bound objects passed to the target
// function. BindUnwrapTraits<>::Unwrap() is called for each bound objects right
// before the target function is invoked.
template <typename>
struct BindUnwrapTraits {
template <typename T>
static T&& Unwrap(T&& o) {
return std::forward<T>(o);
}
};
template <typename T>
struct BindUnwrapTraits<internal::UnretainedWrapper<T>> {
static T* Unwrap(const internal::UnretainedWrapper<T>& o) { return o.get(); }
};
template <typename T>
struct BindUnwrapTraits<internal::ConstRefWrapper<T>> {
static const T& Unwrap(const internal::ConstRefWrapper<T>& o) {
return o.get();
}
};
template <typename T>
struct BindUnwrapTraits<internal::RetainedRefWrapper<T>> {
static T* Unwrap(const internal::RetainedRefWrapper<T>& o) { return o.get(); }
};
template <typename T>
struct BindUnwrapTraits<internal::OwnedWrapper<T>> {
static T* Unwrap(const internal::OwnedWrapper<T>& o) { return o.get(); }
};
template <typename T>
struct BindUnwrapTraits<internal::PassedWrapper<T>> {
static T Unwrap(const internal::PassedWrapper<T>& o) { return o.Take(); }
};
// CallbackCancellationTraits allows customization of Callback's cancellation
// semantics. By default, callbacks are not cancellable. A specialization should
// set is_cancellable = true and implement an IsCancelled() that returns if the
// callback should be cancelled.
template <typename Functor, typename BoundArgsTuple, typename SFINAE>
struct CallbackCancellationTraits {
static constexpr bool is_cancellable = false;
};
// Specialization for method bound to weak pointer receiver.
template <typename Functor, typename... BoundArgs>
struct CallbackCancellationTraits<
Functor,
std::tuple<BoundArgs...>,
std::enable_if_t<
internal::IsWeakMethod<internal::FunctorTraits<Functor>::is_method,
BoundArgs...>::value>> {
static constexpr bool is_cancellable = true;
template <typename Receiver, typename... Args>
static bool IsCancelled(const Functor&,
const Receiver& receiver,
const Args&...) {
return !receiver;
}
};
// Specialization for a nested bind.
template <typename Signature, typename... BoundArgs>
struct CallbackCancellationTraits<OnceCallback<Signature>,
std::tuple<BoundArgs...>> {
static constexpr bool is_cancellable = true;
template <typename Functor>
static bool IsCancelled(const Functor& functor, const BoundArgs&...) {
return functor.IsCancelled();
}
};
template <typename Signature, typename... BoundArgs>
struct CallbackCancellationTraits<RepeatingCallback<Signature>,
std::tuple<BoundArgs...>> {
static constexpr bool is_cancellable = true;
template <typename Functor>
static bool IsCancelled(const Functor& functor, const BoundArgs&...) {
return functor.IsCancelled();
}
};
// Returns a RunType of bound functor.
// E.g. MakeUnboundRunType<R(A, B, C), A, B> is evaluated to R(C).
template <typename Functor, typename... BoundArgs>
using MakeUnboundRunType =
typename internal::BindTypeHelper<Functor, BoundArgs...>::UnboundRunType;
} // namespace base
#endif // BASE_BIND_INTERNAL_H_
| null | null | null | null | 39,100 |
25,908 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 190,903 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* DCE_8_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef DCE_8_0_D_H
#define DCE_8_0_D_H
#define mmPIPE0_PG_CONFIG 0x1760
#define mmPIPE0_PG_ENABLE 0x1761
#define mmPIPE0_PG_STATUS 0x1762
#define mmPIPE1_PG_CONFIG 0x1764
#define mmPIPE1_PG_ENABLE 0x1765
#define mmPIPE1_PG_STATUS 0x1766
#define mmPIPE2_PG_CONFIG 0x1768
#define mmPIPE2_PG_ENABLE 0x1769
#define mmPIPE2_PG_STATUS 0x176a
#define mmPIPE3_PG_CONFIG 0x176c
#define mmPIPE3_PG_ENABLE 0x176d
#define mmPIPE3_PG_STATUS 0x176e
#define mmPIPE4_PG_CONFIG 0x1770
#define mmPIPE4_PG_ENABLE 0x1771
#define mmPIPE4_PG_STATUS 0x1772
#define mmPIPE5_PG_CONFIG 0x1774
#define mmPIPE5_PG_ENABLE 0x1775
#define mmPIPE5_PG_STATUS 0x1776
#define mmDC_IP_REQUEST_CNTL 0x1778
#define mmDC_PGFSM_CONFIG_REG 0x177c
#define mmDC_PGFSM_WRITE_REG 0x177d
#define mmDC_PGCNTL_STATUS_REG 0x177e
#define mmDCPG_TEST_DEBUG_INDEX 0x1779
#define mmDCPG_TEST_DEBUG_DATA 0x177b
#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628
#define mmBL1_PWM_USER_LEVEL 0x1629
#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a
#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b
#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c
#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d
#define mmBL1_PWM_ABM_CNTL 0x162e
#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f
#define mmBL1_PWM_GRP2_REG_LOCK 0x1630
#define mmDC_ABM1_CNTL 0x1638
#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639
#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a
#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b
#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c
#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d
#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e
#define mmDC_ABM1_ACE_THRES_12 0x163f
#define mmDC_ABM1_ACE_THRES_34 0x1640
#define mmDC_ABM1_ACE_CNTL_MISC 0x1641
#define mmDC_ABM1_DEBUG_MISC 0x1649
#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a
#define mmDC_ABM1_HG_MISC_CTRL 0x164b
#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c
#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d
#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e
#define mmDC_ABM1_LS_PIXEL_COUNT 0x164f
#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650
#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651
#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652
#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653
#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654
#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655
#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656
#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657
#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658
#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659
#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a
#define mmDC_ABM1_HG_RESULT_1 0x165b
#define mmDC_ABM1_HG_RESULT_2 0x165c
#define mmDC_ABM1_HG_RESULT_3 0x165d
#define mmDC_ABM1_HG_RESULT_4 0x165e
#define mmDC_ABM1_HG_RESULT_5 0x165f
#define mmDC_ABM1_HG_RESULT_6 0x1660
#define mmDC_ABM1_HG_RESULT_7 0x1661
#define mmDC_ABM1_HG_RESULT_8 0x1662
#define mmDC_ABM1_HG_RESULT_9 0x1663
#define mmDC_ABM1_HG_RESULT_10 0x1664
#define mmDC_ABM1_HG_RESULT_11 0x1665
#define mmDC_ABM1_HG_RESULT_12 0x1666
#define mmDC_ABM1_HG_RESULT_13 0x1667
#define mmDC_ABM1_HG_RESULT_14 0x1668
#define mmDC_ABM1_HG_RESULT_15 0x1669
#define mmDC_ABM1_HG_RESULT_16 0x166a
#define mmDC_ABM1_HG_RESULT_17 0x166b
#define mmDC_ABM1_HG_RESULT_18 0x166c
#define mmDC_ABM1_HG_RESULT_19 0x166d
#define mmDC_ABM1_HG_RESULT_20 0x166e
#define mmDC_ABM1_HG_RESULT_21 0x166f
#define mmDC_ABM1_HG_RESULT_22 0x1670
#define mmDC_ABM1_HG_RESULT_23 0x1671
#define mmDC_ABM1_HG_RESULT_24 0x1672
#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b
#define mmDC_ABM1_BL_MASTER_LOCK 0x169c
#define mmABM_TEST_DEBUG_INDEX 0x169e
#define mmABM_TEST_DEBUG_DATA 0x169f
#define mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c
#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c
#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1e7c
#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417c
#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447c
#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477c
#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4a7c
#define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d
#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d
#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1e7d
#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417d
#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447d
#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477d
#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4a7d
#define mmDCFE_DBG_SEL 0x1b7e
#define mmCRTC0_DCFE_DBG_SEL 0x1b7e
#define mmCRTC1_DCFE_DBG_SEL 0x1e7e
#define mmCRTC2_DCFE_DBG_SEL 0x417e
#define mmCRTC3_DCFE_DBG_SEL 0x447e
#define mmCRTC4_DCFE_DBG_SEL 0x477e
#define mmCRTC5_DCFE_DBG_SEL 0x4a7e
#define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f
#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f
#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1e7f
#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417f
#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447f
#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477f
#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4a7f
#define mmCRTC_H_TOTAL 0x1b80
#define mmCRTC0_CRTC_H_TOTAL 0x1b80
#define mmCRTC1_CRTC_H_TOTAL 0x1e80
#define mmCRTC2_CRTC_H_TOTAL 0x4180
#define mmCRTC3_CRTC_H_TOTAL 0x4480
#define mmCRTC4_CRTC_H_TOTAL 0x4780
#define mmCRTC5_CRTC_H_TOTAL 0x4a80
#define mmCRTC_H_BLANK_START_END 0x1b81
#define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81
#define mmCRTC1_CRTC_H_BLANK_START_END 0x1e81
#define mmCRTC2_CRTC_H_BLANK_START_END 0x4181
#define mmCRTC3_CRTC_H_BLANK_START_END 0x4481
#define mmCRTC4_CRTC_H_BLANK_START_END 0x4781
#define mmCRTC5_CRTC_H_BLANK_START_END 0x4a81
#define mmCRTC_H_SYNC_A 0x1b82
#define mmCRTC0_CRTC_H_SYNC_A 0x1b82
#define mmCRTC1_CRTC_H_SYNC_A 0x1e82
#define mmCRTC2_CRTC_H_SYNC_A 0x4182
#define mmCRTC3_CRTC_H_SYNC_A 0x4482
#define mmCRTC4_CRTC_H_SYNC_A 0x4782
#define mmCRTC5_CRTC_H_SYNC_A 0x4a82
#define mmCRTC_H_SYNC_A_CNTL 0x1b83
#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83
#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1e83
#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183
#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483
#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783
#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4a83
#define mmCRTC_H_SYNC_B 0x1b84
#define mmCRTC0_CRTC_H_SYNC_B 0x1b84
#define mmCRTC1_CRTC_H_SYNC_B 0x1e84
#define mmCRTC2_CRTC_H_SYNC_B 0x4184
#define mmCRTC3_CRTC_H_SYNC_B 0x4484
#define mmCRTC4_CRTC_H_SYNC_B 0x4784
#define mmCRTC5_CRTC_H_SYNC_B 0x4a84
#define mmCRTC_H_SYNC_B_CNTL 0x1b85
#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85
#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1e85
#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185
#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485
#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785
#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4a85
#define mmCRTC_VBI_END 0x1b86
#define mmCRTC0_CRTC_VBI_END 0x1b86
#define mmCRTC1_CRTC_VBI_END 0x1e86
#define mmCRTC2_CRTC_VBI_END 0x4186
#define mmCRTC3_CRTC_VBI_END 0x4486
#define mmCRTC4_CRTC_VBI_END 0x4786
#define mmCRTC5_CRTC_VBI_END 0x4a86
#define mmCRTC_V_TOTAL 0x1b87
#define mmCRTC0_CRTC_V_TOTAL 0x1b87
#define mmCRTC1_CRTC_V_TOTAL 0x1e87
#define mmCRTC2_CRTC_V_TOTAL 0x4187
#define mmCRTC3_CRTC_V_TOTAL 0x4487
#define mmCRTC4_CRTC_V_TOTAL 0x4787
#define mmCRTC5_CRTC_V_TOTAL 0x4a87
#define mmCRTC_V_TOTAL_MIN 0x1b88
#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88
#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1e88
#define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188
#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488
#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788
#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4a88
#define mmCRTC_V_TOTAL_MAX 0x1b89
#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89
#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1e89
#define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189
#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489
#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789
#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4a89
#define mmCRTC_V_TOTAL_CONTROL 0x1b8a
#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a
#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1e8a
#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418a
#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448a
#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478a
#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4a8a
#define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b
#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b
#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1e8b
#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418b
#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448b
#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478b
#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4a8b
#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c
#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c
#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1e8c
#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418c
#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448c
#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478c
#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4a8c
#define mmCRTC_V_BLANK_START_END 0x1b8d
#define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d
#define mmCRTC1_CRTC_V_BLANK_START_END 0x1e8d
#define mmCRTC2_CRTC_V_BLANK_START_END 0x418d
#define mmCRTC3_CRTC_V_BLANK_START_END 0x448d
#define mmCRTC4_CRTC_V_BLANK_START_END 0x478d
#define mmCRTC5_CRTC_V_BLANK_START_END 0x4a8d
#define mmCRTC_V_SYNC_A 0x1b8e
#define mmCRTC0_CRTC_V_SYNC_A 0x1b8e
#define mmCRTC1_CRTC_V_SYNC_A 0x1e8e
#define mmCRTC2_CRTC_V_SYNC_A 0x418e
#define mmCRTC3_CRTC_V_SYNC_A 0x448e
#define mmCRTC4_CRTC_V_SYNC_A 0x478e
#define mmCRTC5_CRTC_V_SYNC_A 0x4a8e
#define mmCRTC_V_SYNC_A_CNTL 0x1b8f
#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f
#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1e8f
#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418f
#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448f
#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478f
#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4a8f
#define mmCRTC_V_SYNC_B 0x1b90
#define mmCRTC0_CRTC_V_SYNC_B 0x1b90
#define mmCRTC1_CRTC_V_SYNC_B 0x1e90
#define mmCRTC2_CRTC_V_SYNC_B 0x4190
#define mmCRTC3_CRTC_V_SYNC_B 0x4490
#define mmCRTC4_CRTC_V_SYNC_B 0x4790
#define mmCRTC5_CRTC_V_SYNC_B 0x4a90
#define mmCRTC_V_SYNC_B_CNTL 0x1b91
#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91
#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1e91
#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191
#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491
#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791
#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4a91
#define mmCRTC_DTMTEST_CNTL 0x1b92
#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92
#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1e92
#define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192
#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492
#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792
#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4a92
#define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93
#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93
#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1e93
#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193
#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493
#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793
#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4a93
#define mmCRTC_TRIGA_CNTL 0x1b94
#define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94
#define mmCRTC1_CRTC_TRIGA_CNTL 0x1e94
#define mmCRTC2_CRTC_TRIGA_CNTL 0x4194
#define mmCRTC3_CRTC_TRIGA_CNTL 0x4494
#define mmCRTC4_CRTC_TRIGA_CNTL 0x4794
#define mmCRTC5_CRTC_TRIGA_CNTL 0x4a94
#define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95
#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95
#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1e95
#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195
#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495
#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795
#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4a95
#define mmCRTC_TRIGB_CNTL 0x1b96
#define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96
#define mmCRTC1_CRTC_TRIGB_CNTL 0x1e96
#define mmCRTC2_CRTC_TRIGB_CNTL 0x4196
#define mmCRTC3_CRTC_TRIGB_CNTL 0x4496
#define mmCRTC4_CRTC_TRIGB_CNTL 0x4796
#define mmCRTC5_CRTC_TRIGB_CNTL 0x4a96
#define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97
#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97
#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1e97
#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197
#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497
#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797
#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4a97
#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98
#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98
#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1e98
#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198
#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498
#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798
#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4a98
#define mmCRTC_FLOW_CONTROL 0x1b99
#define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99
#define mmCRTC1_CRTC_FLOW_CONTROL 0x1e99
#define mmCRTC2_CRTC_FLOW_CONTROL 0x4199
#define mmCRTC3_CRTC_FLOW_CONTROL 0x4499
#define mmCRTC4_CRTC_FLOW_CONTROL 0x4799
#define mmCRTC5_CRTC_FLOW_CONTROL 0x4a99
#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9b
#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9b
#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1e9b
#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419b
#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449b
#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479b
#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4a9b
#define mmCRTC_CONTROL 0x1b9c
#define mmCRTC0_CRTC_CONTROL 0x1b9c
#define mmCRTC1_CRTC_CONTROL 0x1e9c
#define mmCRTC2_CRTC_CONTROL 0x419c
#define mmCRTC3_CRTC_CONTROL 0x449c
#define mmCRTC4_CRTC_CONTROL 0x479c
#define mmCRTC5_CRTC_CONTROL 0x4a9c
#define mmCRTC_BLANK_CONTROL 0x1b9d
#define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d
#define mmCRTC1_CRTC_BLANK_CONTROL 0x1e9d
#define mmCRTC2_CRTC_BLANK_CONTROL 0x419d
#define mmCRTC3_CRTC_BLANK_CONTROL 0x449d
#define mmCRTC4_CRTC_BLANK_CONTROL 0x479d
#define mmCRTC5_CRTC_BLANK_CONTROL 0x4a9d
#define mmCRTC_INTERLACE_CONTROL 0x1b9e
#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e
#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1e9e
#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419e
#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449e
#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479e
#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4a9e
#define mmCRTC_INTERLACE_STATUS 0x1b9f
#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f
#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1e9f
#define mmCRTC2_CRTC_INTERLACE_STATUS 0x419f
#define mmCRTC3_CRTC_INTERLACE_STATUS 0x449f
#define mmCRTC4_CRTC_INTERLACE_STATUS 0x479f
#define mmCRTC5_CRTC_INTERLACE_STATUS 0x4a9f
#define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0
#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0
#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1ea0
#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x41a0
#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x44a0
#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x47a0
#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x4aa0
#define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1ea1
#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x41a1
#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x44a1
#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x47a1
#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x4aa1
#define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1ea2
#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x41a2
#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x44a2
#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x47a2
#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x4aa2
#define mmCRTC_STATUS 0x1ba3
#define mmCRTC0_CRTC_STATUS 0x1ba3
#define mmCRTC1_CRTC_STATUS 0x1ea3
#define mmCRTC2_CRTC_STATUS 0x41a3
#define mmCRTC3_CRTC_STATUS 0x44a3
#define mmCRTC4_CRTC_STATUS 0x47a3
#define mmCRTC5_CRTC_STATUS 0x4aa3
#define mmCRTC_STATUS_POSITION 0x1ba4
#define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4
#define mmCRTC1_CRTC_STATUS_POSITION 0x1ea4
#define mmCRTC2_CRTC_STATUS_POSITION 0x41a4
#define mmCRTC3_CRTC_STATUS_POSITION 0x44a4
#define mmCRTC4_CRTC_STATUS_POSITION 0x47a4
#define mmCRTC5_CRTC_STATUS_POSITION 0x4aa4
#define mmCRTC_NOM_VERT_POSITION 0x1ba5
#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5
#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1ea5
#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41a5
#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44a5
#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47a5
#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4aa5
#define mmCRTC_STATUS_FRAME_COUNT 0x1ba6
#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6
#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1ea6
#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41a6
#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44a6
#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47a6
#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4aa6
#define mmCRTC_STATUS_VF_COUNT 0x1ba7
#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7
#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1ea7
#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41a7
#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44a7
#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47a7
#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4aa7
#define mmCRTC_STATUS_HV_COUNT 0x1ba8
#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8
#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1ea8
#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41a8
#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44a8
#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47a8
#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4aa8
#define mmCRTC_COUNT_CONTROL 0x1ba9
#define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9
#define mmCRTC1_CRTC_COUNT_CONTROL 0x1ea9
#define mmCRTC2_CRTC_COUNT_CONTROL 0x41a9
#define mmCRTC3_CRTC_COUNT_CONTROL 0x44a9
#define mmCRTC4_CRTC_COUNT_CONTROL 0x47a9
#define mmCRTC5_CRTC_COUNT_CONTROL 0x4aa9
#define mmCRTC_COUNT_RESET 0x1baa
#define mmCRTC0_CRTC_COUNT_RESET 0x1baa
#define mmCRTC1_CRTC_COUNT_RESET 0x1eaa
#define mmCRTC2_CRTC_COUNT_RESET 0x41aa
#define mmCRTC3_CRTC_COUNT_RESET 0x44aa
#define mmCRTC4_CRTC_COUNT_RESET 0x47aa
#define mmCRTC5_CRTC_COUNT_RESET 0x4aaa
#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1eab
#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab
#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44ab
#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab
#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4aab
#define mmCRTC_VERT_SYNC_CONTROL 0x1bac
#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac
#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1eac
#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41ac
#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44ac
#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47ac
#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4aac
#define mmCRTC_STEREO_STATUS 0x1bad
#define mmCRTC0_CRTC_STEREO_STATUS 0x1bad
#define mmCRTC1_CRTC_STEREO_STATUS 0x1ead
#define mmCRTC2_CRTC_STEREO_STATUS 0x41ad
#define mmCRTC3_CRTC_STEREO_STATUS 0x44ad
#define mmCRTC4_CRTC_STEREO_STATUS 0x47ad
#define mmCRTC5_CRTC_STEREO_STATUS 0x4aad
#define mmCRTC_STEREO_CONTROL 0x1bae
#define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae
#define mmCRTC1_CRTC_STEREO_CONTROL 0x1eae
#define mmCRTC2_CRTC_STEREO_CONTROL 0x41ae
#define mmCRTC3_CRTC_STEREO_CONTROL 0x44ae
#define mmCRTC4_CRTC_STEREO_CONTROL 0x47ae
#define mmCRTC5_CRTC_STEREO_CONTROL 0x4aae
#define mmCRTC_SNAPSHOT_STATUS 0x1baf
#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf
#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1eaf
#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41af
#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44af
#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47af
#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4aaf
#define mmCRTC_SNAPSHOT_CONTROL 0x1bb0
#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0
#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1eb0
#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41b0
#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44b0
#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47b0
#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4ab0
#define mmCRTC_SNAPSHOT_POSITION 0x1bb1
#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1
#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1eb1
#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41b1
#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44b1
#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47b1
#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4ab1
#define mmCRTC_SNAPSHOT_FRAME 0x1bb2
#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2
#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1eb2
#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41b2
#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44b2
#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47b2
#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4ab2
#define mmCRTC_START_LINE_CONTROL 0x1bb3
#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3
#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1eb3
#define mmCRTC2_CRTC_START_LINE_CONTROL 0x41b3
#define mmCRTC3_CRTC_START_LINE_CONTROL 0x44b3
#define mmCRTC4_CRTC_START_LINE_CONTROL 0x47b3
#define mmCRTC5_CRTC_START_LINE_CONTROL 0x4ab3
#define mmCRTC_INTERRUPT_CONTROL 0x1bb4
#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4
#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1eb4
#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41b4
#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44b4
#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47b4
#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4ab4
#define mmCRTC_UPDATE_LOCK 0x1bb5
#define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5
#define mmCRTC1_CRTC_UPDATE_LOCK 0x1eb5
#define mmCRTC2_CRTC_UPDATE_LOCK 0x41b5
#define mmCRTC3_CRTC_UPDATE_LOCK 0x44b5
#define mmCRTC4_CRTC_UPDATE_LOCK 0x47b5
#define mmCRTC5_CRTC_UPDATE_LOCK 0x4ab5
#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1eb6
#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6
#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44b6
#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6
#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4ab6
#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1eb7
#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7
#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44b7
#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7
#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4ab7
#define mmCRTC_TEST_PATTERN_CONTROL 0x1bba
#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba
#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1eba
#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41ba
#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44ba
#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47ba
#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4aba
#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb
#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb
#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1ebb
#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41bb
#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44bb
#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47bb
#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4abb
#define mmCRTC_TEST_PATTERN_COLOR 0x1bbc
#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc
#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1ebc
#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41bc
#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44bc
#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47bc
#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4abc
#define mmMASTER_UPDATE_LOCK 0x1bbd
#define mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd
#define mmCRTC1_MASTER_UPDATE_LOCK 0x1ebd
#define mmCRTC2_MASTER_UPDATE_LOCK 0x41bd
#define mmCRTC3_MASTER_UPDATE_LOCK 0x44bd
#define mmCRTC4_MASTER_UPDATE_LOCK 0x47bd
#define mmCRTC5_MASTER_UPDATE_LOCK 0x4abd
#define mmMASTER_UPDATE_MODE 0x1bbe
#define mmCRTC0_MASTER_UPDATE_MODE 0x1bbe
#define mmCRTC1_MASTER_UPDATE_MODE 0x1ebe
#define mmCRTC2_MASTER_UPDATE_MODE 0x41be
#define mmCRTC3_MASTER_UPDATE_MODE 0x44be
#define mmCRTC4_MASTER_UPDATE_MODE 0x47be
#define mmCRTC5_MASTER_UPDATE_MODE 0x4abe
#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1ebf
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44bf
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4abf
#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1ec0
#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0
#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44c0
#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0
#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4ac0
#define mmCRTC_MVP_STATUS 0x1bc1
#define mmCRTC0_CRTC_MVP_STATUS 0x1bc1
#define mmCRTC1_CRTC_MVP_STATUS 0x1ec1
#define mmCRTC2_CRTC_MVP_STATUS 0x41c1
#define mmCRTC3_CRTC_MVP_STATUS 0x44c1
#define mmCRTC4_CRTC_MVP_STATUS 0x47c1
#define mmCRTC5_CRTC_MVP_STATUS 0x4ac1
#define mmCRTC_MASTER_EN 0x1bc2
#define mmCRTC0_CRTC_MASTER_EN 0x1bc2
#define mmCRTC1_CRTC_MASTER_EN 0x1ec2
#define mmCRTC2_CRTC_MASTER_EN 0x41c2
#define mmCRTC3_CRTC_MASTER_EN 0x44c2
#define mmCRTC4_CRTC_MASTER_EN 0x47c2
#define mmCRTC5_CRTC_MASTER_EN 0x4ac2
#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1ec3
#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3
#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44c3
#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3
#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4ac3
#define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4
#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4
#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1ec4
#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41c4
#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44c4
#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47c4
#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4ac4
#define mmCRTC_OVERSCAN_COLOR 0x1bc8
#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8
#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1ec8
#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41c8
#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44c8
#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47c8
#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4ac8
#define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9
#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9
#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1ec9
#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x41c9
#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x44c9
#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x47c9
#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x4ac9
#define mmCRTC_BLANK_DATA_COLOR 0x1bca
#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca
#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1eca
#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41ca
#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44ca
#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47ca
#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4aca
#define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb
#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb
#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1ecb
#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x41cb
#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x44cb
#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x47cb
#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x4acb
#define mmCRTC_BLACK_COLOR 0x1bcc
#define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc
#define mmCRTC1_CRTC_BLACK_COLOR 0x1ecc
#define mmCRTC2_CRTC_BLACK_COLOR 0x41cc
#define mmCRTC3_CRTC_BLACK_COLOR 0x44cc
#define mmCRTC4_CRTC_BLACK_COLOR 0x47cc
#define mmCRTC5_CRTC_BLACK_COLOR 0x4acc
#define mmCRTC_BLACK_COLOR_EXT 0x1bcd
#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd
#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1ecd
#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x41cd
#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x44cd
#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x47cd
#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x4acd
#define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1ece
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x44ce
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x4ace
#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1ecf
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x44cf
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x4acf
#define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1ed0
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x44d0
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x4ad0
#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1ed1
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x44d1
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x4ad1
#define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1ed2
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x44d2
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x4ad2
#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1ed3
#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3
#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x44d3
#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3
#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x4ad3
#define mmCRTC_CRC_CNTL 0x1bd4
#define mmCRTC0_CRTC_CRC_CNTL 0x1bd4
#define mmCRTC1_CRTC_CRC_CNTL 0x1ed4
#define mmCRTC2_CRTC_CRC_CNTL 0x41d4
#define mmCRTC3_CRTC_CRC_CNTL 0x44d4
#define mmCRTC4_CRTC_CRC_CNTL 0x47d4
#define mmCRTC5_CRTC_CRC_CNTL 0x4ad4
#define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1ed5
#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5
#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x44d5
#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5
#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x4ad5
#define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1ed6
#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6
#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x44d6
#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6
#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x4ad6
#define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1ed7
#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7
#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x44d7
#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7
#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x4ad7
#define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1ed8
#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8
#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x44d8
#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8
#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x4ad8
#define mmCRTC_CRC0_DATA_RG 0x1bd9
#define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9
#define mmCRTC1_CRTC_CRC0_DATA_RG 0x1ed9
#define mmCRTC2_CRTC_CRC0_DATA_RG 0x41d9
#define mmCRTC3_CRTC_CRC0_DATA_RG 0x44d9
#define mmCRTC4_CRTC_CRC0_DATA_RG 0x47d9
#define mmCRTC5_CRTC_CRC0_DATA_RG 0x4ad9
#define mmCRTC_CRC0_DATA_B 0x1bda
#define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda
#define mmCRTC1_CRTC_CRC0_DATA_B 0x1eda
#define mmCRTC2_CRTC_CRC0_DATA_B 0x41da
#define mmCRTC3_CRTC_CRC0_DATA_B 0x44da
#define mmCRTC4_CRTC_CRC0_DATA_B 0x47da
#define mmCRTC5_CRTC_CRC0_DATA_B 0x4ada
#define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1edb
#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db
#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x44db
#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db
#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x4adb
#define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1edc
#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc
#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x44dc
#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc
#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x4adc
#define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1edd
#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd
#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x44dd
#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd
#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x4add
#define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1ede
#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de
#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x44de
#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de
#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x4ade
#define mmCRTC_CRC1_DATA_RG 0x1bdf
#define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf
#define mmCRTC1_CRTC_CRC1_DATA_RG 0x1edf
#define mmCRTC2_CRTC_CRC1_DATA_RG 0x41df
#define mmCRTC3_CRTC_CRC1_DATA_RG 0x44df
#define mmCRTC4_CRTC_CRC1_DATA_RG 0x47df
#define mmCRTC5_CRTC_CRC1_DATA_RG 0x4adf
#define mmCRTC_CRC1_DATA_B 0x1be0
#define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0
#define mmCRTC1_CRTC_CRC1_DATA_B 0x1ee0
#define mmCRTC2_CRTC_CRC1_DATA_B 0x41e0
#define mmCRTC3_CRTC_CRC1_DATA_B 0x44e0
#define mmCRTC4_CRTC_CRC1_DATA_B 0x47e0
#define mmCRTC5_CRTC_CRC1_DATA_B 0x4ae0
#define mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1ee1
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x44e1
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x4ae1
#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1ee2
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x44e2
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x4ae2
#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1ee3
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x44e3
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x4ae3
#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1ee4
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x44e4
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x4ae4
#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1ee5
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x44e5
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x4ae5
#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6
#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6
#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1ee6
#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6
#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x44e6
#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6
#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x4ae6
#define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7
#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7
#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1ee7
#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x41e7
#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x44e7
#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x47e7
#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x4ae7
#define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78
#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78
#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1e78
#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178
#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478
#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778
#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4a78
#define mmCRTC_GSL_VSYNC_GAP 0x1b79
#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79
#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1e79
#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179
#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479
#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779
#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4a79
#define mmCRTC_GSL_WINDOW 0x1b7a
#define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a
#define mmCRTC1_CRTC_GSL_WINDOW 0x1e7a
#define mmCRTC2_CRTC_GSL_WINDOW 0x417a
#define mmCRTC3_CRTC_GSL_WINDOW 0x447a
#define mmCRTC4_CRTC_GSL_WINDOW 0x477a
#define mmCRTC5_CRTC_GSL_WINDOW 0x4a7a
#define mmCRTC_GSL_CONTROL 0x1b7b
#define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b
#define mmCRTC1_CRTC_GSL_CONTROL 0x1e7b
#define mmCRTC2_CRTC_GSL_CONTROL 0x417b
#define mmCRTC3_CRTC_GSL_CONTROL 0x447b
#define mmCRTC4_CRTC_GSL_CONTROL 0x477b
#define mmCRTC5_CRTC_GSL_CONTROL 0x4a7b
#define mmCRTC_TEST_DEBUG_INDEX 0x1bc6
#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6
#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1ec6
#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41c6
#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44c6
#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47c6
#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4ac6
#define mmCRTC_TEST_DEBUG_DATA 0x1bc7
#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7
#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1ec7
#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41c7
#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44c7
#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47c7
#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4ac7
#define mmDAC_ENABLE 0x19e4
#define mmDAC_SOURCE_SELECT 0x19e5
#define mmDAC_CRC_EN 0x19e6
#define mmDAC_CRC_CONTROL 0x19e7
#define mmDAC_CRC_SIG_RGB_MASK 0x19e8
#define mmDAC_CRC_SIG_CONTROL_MASK 0x19e9
#define mmDAC_CRC_SIG_RGB 0x19ea
#define mmDAC_CRC_SIG_CONTROL 0x19eb
#define mmDAC_SYNC_TRISTATE_CONTROL 0x19ec
#define mmDAC_STEREOSYNC_SELECT 0x19ed
#define mmDAC_AUTODETECT_CONTROL 0x19ee
#define mmDAC_AUTODETECT_CONTROL2 0x19ef
#define mmDAC_AUTODETECT_CONTROL3 0x19f0
#define mmDAC_AUTODETECT_STATUS 0x19f1
#define mmDAC_AUTODETECT_INT_CONTROL 0x19f2
#define mmDAC_FORCE_OUTPUT_CNTL 0x19f3
#define mmDAC_FORCE_DATA 0x19f4
#define mmDAC_POWERDOWN 0x19f5
#define mmDAC_CONTROL 0x19f6
#define mmDAC_COMPARATOR_ENABLE 0x19f7
#define mmDAC_COMPARATOR_OUTPUT 0x19f8
#define mmDAC_PWR_CNTL 0x19f9
#define mmDAC_DFT_CONFIG 0x19fa
#define mmDAC_FIFO_STATUS 0x19fb
#define mmPERFCOUNTER_CNTL 0x170
#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170
#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x1870
#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1b24
#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1e24
#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x4124
#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x4424
#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4724
#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4a24
#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4c40
#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4d14
#define mmPERFCOUNTER_STATE 0x171
#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171
#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x1871
#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x1b25
#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1e25
#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x4125
#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x4425
#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4725
#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4a25
#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4c41
#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4d15
#define mmPERFMON_CNTL 0x173
#define mmDC_PERFMON0_PERFMON_CNTL 0x173
#define mmDC_PERFMON1_PERFMON_CNTL 0x1873
#define mmDC_PERFMON2_PERFMON_CNTL 0x1b27
#define mmDC_PERFMON3_PERFMON_CNTL 0x1e27
#define mmDC_PERFMON4_PERFMON_CNTL 0x4127
#define mmDC_PERFMON5_PERFMON_CNTL 0x4427
#define mmDC_PERFMON6_PERFMON_CNTL 0x4727
#define mmDC_PERFMON7_PERFMON_CNTL 0x4a27
#define mmDC_PERFMON8_PERFMON_CNTL 0x4c43
#define mmDC_PERFMON9_PERFMON_CNTL 0x4d17
#define mmPERFMON_CVALUE_INT_MISC 0x172
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x1872
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1b26
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1e26
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x4126
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x4426
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4726
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4a26
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4c42
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4d16
#define mmPERFMON_CVALUE_LOW 0x174
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x1874
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1b28
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1e28
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x4128
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x4428
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4728
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4a28
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4c44
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4d18
#define mmPERFMON_HI 0x175
#define mmDC_PERFMON0_PERFMON_HI 0x175
#define mmDC_PERFMON1_PERFMON_HI 0x1875
#define mmDC_PERFMON2_PERFMON_HI 0x1b29
#define mmDC_PERFMON3_PERFMON_HI 0x1e29
#define mmDC_PERFMON4_PERFMON_HI 0x4129
#define mmDC_PERFMON5_PERFMON_HI 0x4429
#define mmDC_PERFMON6_PERFMON_HI 0x4729
#define mmDC_PERFMON7_PERFMON_HI 0x4a29
#define mmDC_PERFMON8_PERFMON_HI 0x4c45
#define mmDC_PERFMON9_PERFMON_HI 0x4d19
#define mmPERFMON_LOW 0x176
#define mmDC_PERFMON0_PERFMON_LOW 0x176
#define mmDC_PERFMON1_PERFMON_LOW 0x1876
#define mmDC_PERFMON2_PERFMON_LOW 0x1b2a
#define mmDC_PERFMON3_PERFMON_LOW 0x1e2a
#define mmDC_PERFMON4_PERFMON_LOW 0x412a
#define mmDC_PERFMON5_PERFMON_LOW 0x442a
#define mmDC_PERFMON6_PERFMON_LOW 0x472a
#define mmDC_PERFMON7_PERFMON_LOW 0x4a2a
#define mmDC_PERFMON8_PERFMON_LOW 0x4c46
#define mmDC_PERFMON9_PERFMON_LOW 0x4d1a
#define mmPERFMON_TEST_DEBUG_INDEX 0x177
#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177
#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x1877
#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x1b2b
#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1e2b
#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x412b
#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x442b
#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x472b
#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x4a2b
#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x4c47
#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x4d1b
#define mmPERFMON_TEST_DEBUG_DATA 0x178
#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178
#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x1878
#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x1b2c
#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1e2c
#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x412c
#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x442c
#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x472c
#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x4a2c
#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x4c48
#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x4d1c
#define mmVGA25_PPLL_REF_DIV 0xd8
#define mmVGA28_PPLL_REF_DIV 0xd9
#define mmVGA41_PPLL_REF_DIV 0xda
#define mmVGA25_PPLL_FB_DIV 0xdc
#define mmVGA28_PPLL_FB_DIV 0xdd
#define mmVGA41_PPLL_FB_DIV 0xde
#define mmVGA25_PPLL_POST_DIV 0xe0
#define mmVGA28_PPLL_POST_DIV 0xe1
#define mmVGA41_PPLL_POST_DIV 0xe2
#define mmVGA25_PPLL_ANALOG 0xe4
#define mmVGA28_PPLL_ANALOG 0xe5
#define mmVGA41_PPLL_ANALOG 0xe6
#define mmDPREFCLK_CNTL 0x118
#define mmSCANIN_SOFT_RESET 0x11e
#define mmDCCG_GTC_CNTL 0x120
#define mmDCCG_GTC_DTO_INCR 0x121
#define mmDCCG_GTC_DTO_MODULO 0x122
#define mmDCCG_GTC_CURRENT 0x123
#define mmDCCG_DS_DTO_INCR 0x113
#define mmDCCG_DS_DTO_MODULO 0x114
#define mmDCCG_DS_CNTL 0x115
#define mmDCCG_DS_HW_CAL_INTERVAL 0x116
#define mmDCCG_DS_DEBUG_CNTL 0x112
#define mmDMCU_SMU_INTERRUPT_CNTL 0x12c
#define mmSMU_CONTROL 0x12d
#define mmSMU_INTERRUPT_CONTROL 0x12e
#define mmDAC_CLK_ENABLE 0x128
#define mmDVO_CLK_ENABLE 0x129
#define mmDCCG_GATE_DISABLE_CNTL 0x134
#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135
#define mmSCLK_CGTT_BLK_CTRL_REG 0x136
#define mmDCCG_CAC_STATUS 0x137
#define mmPIXCLK1_RESYNC_CNTL 0x138
#define mmPIXCLK2_RESYNC_CNTL 0x139
#define mmPIXCLK0_RESYNC_CNTL 0x13a
#define mmMICROSECOND_TIME_BASE_DIV 0x13b
#define mmDCCG_DISP_CNTL_REG 0x13f
#define mmDISPPLL_BG_CNTL 0x13c
#define mmDIG_SOFT_RESET 0x13d
#define mmMILLISECOND_TIME_BASE_DIV 0x130
#define mmDISPCLK_FREQ_CHANGE_CNTL 0x131
#define mmLIGHT_SLEEP_CNTL 0x132
#define mmDCCG_PERFMON_CNTL 0x133
#define mmCRTC0_PIXEL_RATE_CNTL 0x140
#define mmDP_DTO0_PHASE 0x141
#define mmDP_DTO0_MODULO 0x142
#define mmCRTC1_PIXEL_RATE_CNTL 0x144
#define mmDP_DTO1_PHASE 0x145
#define mmDP_DTO1_MODULO 0x146
#define mmCRTC2_PIXEL_RATE_CNTL 0x148
#define mmDP_DTO2_PHASE 0x149
#define mmDP_DTO2_MODULO 0x14a
#define mmCRTC3_PIXEL_RATE_CNTL 0x14c
#define mmDP_DTO3_PHASE 0x14d
#define mmDP_DTO3_MODULO 0x14e
#define mmCRTC4_PIXEL_RATE_CNTL 0x150
#define mmDP_DTO4_PHASE 0x151
#define mmDP_DTO4_MODULO 0x152
#define mmCRTC5_PIXEL_RATE_CNTL 0x154
#define mmDP_DTO5_PHASE 0x155
#define mmDP_DTO5_MODULO 0x156
#define mmDCFE0_SOFT_RESET 0x158
#define mmDCFE1_SOFT_RESET 0x159
#define mmDCFE2_SOFT_RESET 0x15a
#define mmDCFE3_SOFT_RESET 0x15b
#define mmDCFE4_SOFT_RESET 0x15c
#define mmDCFE5_SOFT_RESET 0x15d
#define mmDCI_SOFT_RESET 0x15e
#define mmDCCG_SOFT_RESET 0x15f
#define mmSYMCLKA_CLOCK_ENABLE 0x160
#define mmSYMCLKB_CLOCK_ENABLE 0x161
#define mmSYMCLKC_CLOCK_ENABLE 0x162
#define mmSYMCLKD_CLOCK_ENABLE 0x163
#define mmSYMCLKE_CLOCK_ENABLE 0x164
#define mmSYMCLKF_CLOCK_ENABLE 0x165
#define mmSYMCLKG_CLOCK_ENABLE 0x117
#define mmUNIPHY_SOFT_RESET 0x166
#define mmDCO_SOFT_RESET 0x167
#define mmDVOACLKD_CNTL 0x168
#define mmDVOACLKC_MVP_CNTL 0x169
#define mmDVOACLKC_CNTL 0x16a
#define mmDCCG_AUDIO_DTO_SOURCE 0x16b
#define mmDCCG_AUDIO_DTO0_PHASE 0x16c
#define mmDCCG_AUDIO_DTO0_MODULE 0x16d
#define mmDCCG_AUDIO_DTO1_PHASE 0x16e
#define mmDCCG_AUDIO_DTO1_MODULE 0x16f
#define mmDCCG_TEST_DEBUG_INDEX 0x17c
#define mmDCCG_TEST_DEBUG_DATA 0x17d
#define mmDCCG_TEST_CLK_SEL 0x17e
#define mmPLL_REF_DIV 0x1700
#define mmDCCG_PLL0_PLL_REF_DIV 0x1700
#define mmDCCG_PLL1_PLL_REF_DIV 0x1714
#define mmDCCG_PLL2_PLL_REF_DIV 0x1728
#define mmDCCG_PLL3_PLL_REF_DIV 0x173c
#define mmPLL_FB_DIV 0x1701
#define mmDCCG_PLL0_PLL_FB_DIV 0x1701
#define mmDCCG_PLL1_PLL_FB_DIV 0x1715
#define mmDCCG_PLL2_PLL_FB_DIV 0x1729
#define mmDCCG_PLL3_PLL_FB_DIV 0x173d
#define mmPLL_POST_DIV 0x1702
#define mmDCCG_PLL0_PLL_POST_DIV 0x1702
#define mmDCCG_PLL1_PLL_POST_DIV 0x1716
#define mmDCCG_PLL2_PLL_POST_DIV 0x172a
#define mmDCCG_PLL3_PLL_POST_DIV 0x173e
#define mmPLL_SS_AMOUNT_DSFRAC 0x1703
#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703
#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1717
#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x172b
#define mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC 0x173f
#define mmPLL_SS_CNTL 0x1704
#define mmDCCG_PLL0_PLL_SS_CNTL 0x1704
#define mmDCCG_PLL1_PLL_SS_CNTL 0x1718
#define mmDCCG_PLL2_PLL_SS_CNTL 0x172c
#define mmDCCG_PLL3_PLL_SS_CNTL 0x1740
#define mmPLL_DS_CNTL 0x1705
#define mmDCCG_PLL0_PLL_DS_CNTL 0x1705
#define mmDCCG_PLL1_PLL_DS_CNTL 0x1719
#define mmDCCG_PLL2_PLL_DS_CNTL 0x172d
#define mmDCCG_PLL3_PLL_DS_CNTL 0x1741
#define mmPLL_IDCLK_CNTL 0x1706
#define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706
#define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x171a
#define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x172e
#define mmDCCG_PLL3_PLL_IDCLK_CNTL 0x1742
#define mmPLL_CNTL 0x1707
#define mmDCCG_PLL0_PLL_CNTL 0x1707
#define mmDCCG_PLL1_PLL_CNTL 0x171b
#define mmDCCG_PLL2_PLL_CNTL 0x172f
#define mmDCCG_PLL3_PLL_CNTL 0x1743
#define mmPLL_ANALOG 0x1708
#define mmDCCG_PLL0_PLL_ANALOG 0x1708
#define mmDCCG_PLL1_PLL_ANALOG 0x171c
#define mmDCCG_PLL2_PLL_ANALOG 0x1730
#define mmDCCG_PLL3_PLL_ANALOG 0x1744
#define mmPLL_ANALOG_CNTL 0x1711
#define mmDCCG_PLL0_PLL_ANALOG_CNTL 0x1711
#define mmDCCG_PLL1_PLL_ANALOG_CNTL 0x1725
#define mmDCCG_PLL2_PLL_ANALOG_CNTL 0x1739
#define mmDCCG_PLL3_PLL_ANALOG_CNTL 0x174d
#define mmPLL_VREG_CNTL 0x1709
#define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709
#define mmDCCG_PLL1_PLL_VREG_CNTL 0x171d
#define mmDCCG_PLL2_PLL_VREG_CNTL 0x1731
#define mmDCCG_PLL3_PLL_VREG_CNTL 0x1745
#define mmPLL_XOR_LOCK 0x1710
#define mmDCCG_PLL0_PLL_XOR_LOCK 0x1710
#define mmDCCG_PLL1_PLL_XOR_LOCK 0x1724
#define mmDCCG_PLL2_PLL_XOR_LOCK 0x1738
#define mmDCCG_PLL3_PLL_XOR_LOCK 0x174c
#define mmPLL_UNLOCK_DETECT_CNTL 0x170a
#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a
#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171e
#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x1732
#define mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL 0x1746
#define mmPLL_DEBUG_CNTL 0x170b
#define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170b
#define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171f
#define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x1733
#define mmDCCG_PLL3_PLL_DEBUG_CNTL 0x1747
#define mmPLL_UPDATE_LOCK 0x170c
#define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170c
#define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x1720
#define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x1734
#define mmDCCG_PLL3_PLL_UPDATE_LOCK 0x1748
#define mmPLL_UPDATE_CNTL 0x170d
#define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170d
#define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x1721
#define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x1735
#define mmDCCG_PLL3_PLL_UPDATE_CNTL 0x1749
#define mmPLL_DISPCLK_DTO_CNTL 0x170e
#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170e
#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x1722
#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x1736
#define mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL 0x174a
#define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170f
#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170f
#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1723
#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1737
#define mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE 0x174b
#define mmDENTIST_DISPCLK_CNTL 0x124
#define mmDCDEBUG_BUS_CLK1_SEL 0x1860
#define mmDCDEBUG_BUS_CLK2_SEL 0x1861
#define mmDCDEBUG_BUS_CLK3_SEL 0x1862
#define mmDCDEBUG_BUS_CLK4_SEL 0x1863
#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186a
#define mmDCDEBUG_OUT_CNTL 0x186b
#define mmDCDEBUG_OUT_DATA 0x186e
#define mmDMIF_ADDR_CONFIG 0x2f5
#define mmDMIF_CONTROL 0x2f6
#define mmDMIF_STATUS 0x2f7
#define mmDMIF_HW_DEBUG 0x2f8
#define mmDMIF_ARBITRATION_CONTROL 0x2f9
#define mmPIPE0_ARBITRATION_CONTROL3 0x2fa
#define mmPIPE1_ARBITRATION_CONTROL3 0x2fb
#define mmPIPE2_ARBITRATION_CONTROL3 0x2fc
#define mmPIPE3_ARBITRATION_CONTROL3 0x2fd
#define mmPIPE4_ARBITRATION_CONTROL3 0x2fe
#define mmPIPE5_ARBITRATION_CONTROL3 0x2ff
#define mmDMIF_TEST_DEBUG_INDEX 0x312
#define mmDMIF_TEST_DEBUG_DATA 0x313
#define ixDMIF_DEBUG02_CORE0 0x2
#define ixDMIF_DEBUG02_CORE1 0xa
#define mmDMIF_ADDR_CALC 0x300
#define mmDMIF_STATUS2 0x301
#define mmPIPE0_MAX_REQUESTS 0x302
#define mmPIPE1_MAX_REQUESTS 0x303
#define mmPIPE2_MAX_REQUESTS 0x304
#define mmPIPE3_MAX_REQUESTS 0x305
#define mmPIPE4_MAX_REQUESTS 0x306
#define mmPIPE5_MAX_REQUESTS 0x307
#define mmLOW_POWER_TILING_CONTROL 0x325
#define mmMCIF_CONTROL 0x314
#define mmMCIF_WRITE_COMBINE_CONTROL 0x315
#define mmMCIF_TEST_DEBUG_INDEX 0x316
#define mmMCIF_TEST_DEBUG_DATA 0x317
#define ixIDDCCIF02_DBG_DCCIF_C 0x9
#define ixIDDCCIF04_DBG_DCCIF_E 0xb
#define ixIDDCCIF05_DBG_DCCIF_F 0xc
#define mmMCIF_VMID 0x318
#define mmMCIF_MEM_CONTROL 0x319
#define mmCC_DC_PIPE_DIS 0x177f
#define mmMC_DC_INTERFACE_NACK_STATUS 0x31c
#define mmDC_RBBMIF_RDWR_CNTL1 0x31a
#define mmDC_RBBMIF_RDWR_CNTL2 0x31d
#define mmDC_RBBMIF_RDWR_CNTL3 0x311
#define mmDCI_MEM_PWR_STATE 0x31b
#define mmDCI_MEM_PWR_STATE2 0x322
#define mmDCI_CLK_CNTL 0x31e
#define mmDCCG_VPCLK_CNTL 0x31f
#define mmDCI_MEM_PWR_CNTL 0x326
#define mmDC_XDMA_INTERFACE_CNTL 0x327
#define mmDCI_TEST_DEBUG_INDEX 0x320
#define mmDCI_TEST_DEBUG_DATA 0x321
#define mmDCI_DEBUG_CONFIG 0x323
#define mmPIPE0_DMIF_BUFFER_CONTROL 0x328
#define mmPIPE1_DMIF_BUFFER_CONTROL 0x330
#define mmPIPE2_DMIF_BUFFER_CONTROL 0x338
#define mmPIPE3_DMIF_BUFFER_CONTROL 0x340
#define mmPIPE4_DMIF_BUFFER_CONTROL 0x348
#define mmPIPE5_DMIF_BUFFER_CONTROL 0x350
#define mmMCIF_BUFMGR_SW_CONTROL 0x358
#define mmMCIF_BUFMGR_STATUS 0x35a
#define mmMCIF_BUF_PITCH 0x35b
#define mmMCIF_BUF_1_ADDR_Y_LOW 0x35c
#define mmMCIF_BUF_2_ADDR_Y_LOW 0x360
#define mmMCIF_BUF_3_ADDR_Y_LOW 0x364
#define mmMCIF_BUF_4_ADDR_Y_LOW 0x368
#define mmMCIF_BUF_1_ADDR_UP 0x35d
#define mmMCIF_BUF_2_ADDR_UP 0x361
#define mmMCIF_BUF_3_ADDR_UP 0x365
#define mmMCIF_BUF_4_ADDR_UP 0x369
#define mmMCIF_BUF_1_ADDR_C_LOW 0x35e
#define mmMCIF_BUF_2_ADDR_C_LOW 0x362
#define mmMCIF_BUF_3_ADDR_C_LOW 0x366
#define mmMCIF_BUF_4_ADDR_C_LOW 0x36a
#define mmMCIF_BUF_1_STATUS 0x35f
#define mmMCIF_BUF_2_STATUS 0x363
#define mmMCIF_BUF_3_STATUS 0x367
#define mmMCIF_BUF_4_STATUS 0x36b
#define mmMCIF_SI_ARBITRATION_CONTROL 0x36c
#define mmMCIF_URGENCY_WATERMARK 0x36d
#define mmDC_GENERICA 0x1900
#define mmDC_GENERICB 0x1901
#define mmDC_PAD_EXTERN_SIG 0x1902
#define mmDC_REF_CLK_CNTL 0x1903
#define mmDC_GPIO_DEBUG 0x1904
#define mmDCO_MEM_POWER_STATE 0x1906
#define mmDCO_MEM_POWER_STATE_2 0x193a
#define mmDCO_LIGHT_SLEEP_DIS 0x1907
#define mmUNIPHY_IMPCAL_LINKA 0x1908
#define mmUNIPHY_IMPCAL_LINKB 0x1909
#define mmUNIPHY_IMPCAL_PERIOD 0x190a
#define mmAUXP_IMPCAL 0x190b
#define mmAUXN_IMPCAL 0x190c
#define mmDCIO_IMPCAL_CNTL_AB 0x190d
#define mmUNIPHY_IMPCAL_PSW_AB 0x190e
#define mmUNIPHY_IMPCAL_LINKC 0x190f
#define mmUNIPHY_IMPCAL_LINKD 0x1910
#define mmDCIO_IMPCAL_CNTL_CD 0x1911
#define mmUNIPHY_IMPCAL_PSW_CD 0x1912
#define mmUNIPHY_IMPCAL_LINKE 0x1913
#define mmUNIPHY_IMPCAL_LINKF 0x1914
#define mmDCIO_IMPCAL_CNTL_EF 0x1915
#define mmUNIPHY_IMPCAL_PSW_EF 0x1916
#define mmDC_PINSTRAPS 0x1917
#define mmDC_DVODATA_CONFIG 0x1905
#define mmLVTMA_PWRSEQ_CNTL 0x1919
#define mmLVTMA_PWRSEQ_STATE 0x191a
#define mmLVTMA_PWRSEQ_REF_DIV 0x191b
#define mmLVTMA_PWRSEQ_DELAY1 0x191c
#define mmLVTMA_PWRSEQ_DELAY2 0x191d
#define mmBL_PWM_CNTL 0x191e
#define mmBL_PWM_CNTL2 0x191f
#define mmBL_PWM_PERIOD_CNTL 0x1920
#define mmBL_PWM_GRP1_REG_LOCK 0x1921
#define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923
#define mmDCIO_GSL0_CNTL 0x1924
#define mmDCIO_GSL1_CNTL 0x1925
#define mmDCIO_GSL2_CNTL 0x1926
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927
#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928
#define mmDC_GPU_TIMER_READ 0x1929
#define mmDC_GPU_TIMER_READ_CNTL 0x192a
#define mmDCO_CLK_CNTL 0x192b
#define mmDCO_CLK_RAMP_CNTL 0x192c
#define mmDCIO_DEBUG 0x192e
#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x1937
#define mmDCIO_TEST_DEBUG_INDEX 0x192f
#define mmDCIO_TEST_DEBUG_DATA 0x1930
#define ixDCIO_DEBUG1 0x1
#define ixDCIO_DEBUG2 0x2
#define ixDCIO_DEBUG3 0x3
#define ixDCIO_DEBUG4 0x4
#define ixDCIO_DEBUG5 0x5
#define ixDCIO_DEBUG6 0x6
#define ixDCIO_DEBUG7 0x7
#define ixDCIO_DEBUG8 0x8
#define ixDCIO_DEBUG9 0x9
#define ixDCIO_DEBUGA 0xa
#define ixDCIO_DEBUGB 0xb
#define ixDCIO_DEBUGC 0xc
#define ixDCIO_DEBUGD 0xd
#define ixDCIO_DEBUGE 0xe
#define ixDCIO_DEBUGF 0xf
#define ixDCIO_DEBUG10 0x10
#define ixDCIO_DEBUG11 0x11
#define ixDCIO_DEBUG12 0x12
#define ixDCIO_DEBUG13 0x13
#define ixDCIO_DEBUG14 0x14
#define ixDCIO_DEBUG15 0x15
#define ixDCIO_DEBUG_ID 0x0
#define mmDC_GPIO_GENERIC_MASK 0x1944
#define mmDC_GPIO_GENERIC_A 0x1945
#define mmDC_GPIO_GENERIC_EN 0x1946
#define mmDC_GPIO_GENERIC_Y 0x1947
#define mmDC_GPIO_DVODATA_MASK 0x1948
#define mmDC_GPIO_DVODATA_A 0x1949
#define mmDC_GPIO_DVODATA_EN 0x194a
#define mmDC_GPIO_DVODATA_Y 0x194b
#define mmDC_GPIO_DDC1_MASK 0x194c
#define mmDC_GPIO_DDC1_A 0x194d
#define mmDC_GPIO_DDC1_EN 0x194e
#define mmDC_GPIO_DDC1_Y 0x194f
#define mmDC_GPIO_DDC2_MASK 0x1950
#define mmDC_GPIO_DDC2_A 0x1951
#define mmDC_GPIO_DDC2_EN 0x1952
#define mmDC_GPIO_DDC2_Y 0x1953
#define mmDC_GPIO_DDC3_MASK 0x1954
#define mmDC_GPIO_DDC3_A 0x1955
#define mmDC_GPIO_DDC3_EN 0x1956
#define mmDC_GPIO_DDC3_Y 0x1957
#define mmDC_GPIO_DDC4_MASK 0x1958
#define mmDC_GPIO_DDC4_A 0x1959
#define mmDC_GPIO_DDC4_EN 0x195a
#define mmDC_GPIO_DDC4_Y 0x195b
#define mmDC_GPIO_DDC5_MASK 0x195c
#define mmDC_GPIO_DDC5_A 0x195d
#define mmDC_GPIO_DDC5_EN 0x195e
#define mmDC_GPIO_DDC5_Y 0x195f
#define mmDC_GPIO_DDC6_MASK 0x1960
#define mmDC_GPIO_DDC6_A 0x1961
#define mmDC_GPIO_DDC6_EN 0x1962
#define mmDC_GPIO_DDC6_Y 0x1963
#define mmDC_GPIO_DDCVGA_MASK 0x1970
#define mmDC_GPIO_DDCVGA_A 0x1971
#define mmDC_GPIO_DDCVGA_EN 0x1972
#define mmDC_GPIO_DDCVGA_Y 0x1973
#define mmDC_GPIO_SYNCA_MASK 0x1964
#define mmDC_GPIO_SYNCA_A 0x1965
#define mmDC_GPIO_SYNCA_EN 0x1966
#define mmDC_GPIO_SYNCA_Y 0x1967
#define mmDC_GPIO_GENLK_MASK 0x1968
#define mmDC_GPIO_GENLK_A 0x1969
#define mmDC_GPIO_GENLK_EN 0x196a
#define mmDC_GPIO_GENLK_Y 0x196b
#define mmDC_GPIO_HPD_MASK 0x196c
#define mmDC_GPIO_HPD_A 0x196d
#define mmDC_GPIO_HPD_EN 0x196e
#define mmDC_GPIO_HPD_Y 0x196f
#define mmDC_GPIO_PWRSEQ_MASK 0x1940
#define mmDC_GPIO_PWRSEQ_A 0x1941
#define mmDC_GPIO_PWRSEQ_EN 0x1942
#define mmDC_GPIO_PWRSEQ_Y 0x1943
#define mmDC_GPIO_PAD_STRENGTH_1 0x1978
#define mmDC_GPIO_PAD_STRENGTH_2 0x1979
#define mmPHY_AUX_CNTL 0x197f
#define mmDC_GPIO_I2CPAD_MASK 0x1974
#define mmDC_GPIO_I2CPAD_A 0x1975
#define mmDC_GPIO_I2CPAD_EN 0x1976
#define mmDC_GPIO_I2CPAD_Y 0x1977
#define mmDC_GPIO_I2CPAD_STRENGTH 0x197a
#define mmDVO_STRENGTH_CONTROL 0x197b
#define mmDVO_VREF_CONTROL 0x197c
#define mmDVO_SKEW_ADJUST 0x197d
#define mmUNIPHYAB_TPG_CONTROL 0x1931
#define mmUNIPHYAB_TPG_SEED 0x1932
#define mmUNIPHYCD_TPG_CONTROL 0x1933
#define mmUNIPHYCD_TPG_SEED 0x1934
#define mmUNIPHYEF_TPG_CONTROL 0x1935
#define mmUNIPHYEF_TPG_SEED 0x1936
#define mmUNIPHYGH_TPG_CONTROL 0x1938
#define mmUNIPHYGH_TPG_SEED 0x1939
#define mmDC_GPIO_I2S_SPDIF_MASK 0x193c
#define mmDC_GPIO_I2S_SPDIF_A 0x193d
#define mmDC_GPIO_I2S_SPDIF_EN 0x193e
#define mmDC_GPIO_I2S_SPDIF_Y 0x193f
#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x193b
#define mmDAC_MACRO_CNTL_RESERVED0 0x19fc
#define mmDAC_MACRO_CNTL_RESERVED1 0x19fd
#define mmDAC_MACRO_CNTL_RESERVED2 0x19fe
#define mmDAC_MACRO_CNTL_RESERVED3 0x19ff
#define mmUNIPHY_TX_CONTROL1 0x1980
#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980
#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990
#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19a0
#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19b0
#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19c0
#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19d0
#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1 0x4df0
#define mmUNIPHY_TX_CONTROL2 0x1981
#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981
#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991
#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19a1
#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19b1
#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19c1
#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19d1
#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2 0x4df1
#define mmUNIPHY_TX_CONTROL3 0x1982
#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982
#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992
#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19a2
#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19b2
#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19c2
#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19d2
#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3 0x4df2
#define mmUNIPHY_TX_CONTROL4 0x1983
#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983
#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993
#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19a3
#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19b3
#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19c3
#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19d3
#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4 0x4df3
#define mmUNIPHY_POWER_CONTROL 0x1984
#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984
#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994
#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19a4
#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19b4
#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19c4
#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19d4
#define mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL 0x4df4
#define mmUNIPHY_PLL_FBDIV 0x1985
#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985
#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995
#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19a5
#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19b5
#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19c5
#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19d5
#define mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV 0x4df5
#define mmUNIPHY_PLL_CONTROL1 0x1986
#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986
#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996
#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19a6
#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19b6
#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19c6
#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19d6
#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4df6
#define mmUNIPHY_PLL_CONTROL2 0x1987
#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987
#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997
#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19a7
#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19b7
#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19c7
#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19d7
#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4df7
#define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988
#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988
#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998
#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19a8
#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19b8
#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19c8
#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19d8
#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4df8
#define mmUNIPHY_PLL_SS_CNTL 0x1989
#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989
#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999
#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19a9
#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19b9
#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19c9
#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19d9
#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4df9
#define mmUNIPHY_DATA_SYNCHRONIZATION 0x198a
#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198a
#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199a
#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19aa
#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19ba
#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19ca
#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19da
#define mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x4dfa
#define mmUNIPHY_REG_TEST_OUTPUT 0x198b
#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198b
#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199b
#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19ab
#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19bb
#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19cb
#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19db
#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x4dfb
#define mmUNIPHY_ANG_BIST_CNTL 0x198c
#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198c
#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199c
#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19ac
#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19bc
#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19cc
#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19dc
#define mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x4dfc
#define mmUNIPHY_LINK_CNTL 0x198d
#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198d
#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199d
#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19ad
#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19bd
#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19cd
#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19dd
#define mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL 0x4dfd
#define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198e
#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198e
#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199e
#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19ae
#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19be
#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19ce
#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19de
#define mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL 0x4dfe
#define mmUNIPHY_REG_TEST_OUTPUT2 0x198f
#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x198f
#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x199f
#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x19af
#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x19bf
#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x19cf
#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x19df
#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x4dff
#define mmGRPH_ENABLE 0x1a00
#define mmDCP0_GRPH_ENABLE 0x1a00
#define mmDCP1_GRPH_ENABLE 0x1d00
#define mmDCP2_GRPH_ENABLE 0x4000
#define mmDCP3_GRPH_ENABLE 0x4300
#define mmDCP4_GRPH_ENABLE 0x4600
#define mmDCP5_GRPH_ENABLE 0x4900
#define mmGRPH_CONTROL 0x1a01
#define mmDCP0_GRPH_CONTROL 0x1a01
#define mmDCP1_GRPH_CONTROL 0x1d01
#define mmDCP2_GRPH_CONTROL 0x4001
#define mmDCP3_GRPH_CONTROL 0x4301
#define mmDCP4_GRPH_CONTROL 0x4601
#define mmDCP5_GRPH_CONTROL 0x4901
#define mmGRPH_LUT_10BIT_BYPASS 0x1a02
#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02
#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1d02
#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002
#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302
#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602
#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902
#define mmGRPH_SWAP_CNTL 0x1a03
#define mmDCP0_GRPH_SWAP_CNTL 0x1a03
#define mmDCP1_GRPH_SWAP_CNTL 0x1d03
#define mmDCP2_GRPH_SWAP_CNTL 0x4003
#define mmDCP3_GRPH_SWAP_CNTL 0x4303
#define mmDCP4_GRPH_SWAP_CNTL 0x4603
#define mmDCP5_GRPH_SWAP_CNTL 0x4903
#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1d04
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904
#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1d05
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905
#define mmGRPH_PITCH 0x1a06
#define mmDCP0_GRPH_PITCH 0x1a06
#define mmDCP1_GRPH_PITCH 0x1d06
#define mmDCP2_GRPH_PITCH 0x4006
#define mmDCP3_GRPH_PITCH 0x4306
#define mmDCP4_GRPH_PITCH 0x4606
#define mmDCP5_GRPH_PITCH 0x4906
#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1d07
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007
#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607
#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907
#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d08
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008
#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308
#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608
#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908
#define mmGRPH_SURFACE_OFFSET_X 0x1a09
#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09
#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1d09
#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009
#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309
#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609
#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909
#define mmGRPH_SURFACE_OFFSET_Y 0x1a0a
#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a
#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1d0a
#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400a
#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430a
#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460a
#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490a
#define mmGRPH_X_START 0x1a0b
#define mmDCP0_GRPH_X_START 0x1a0b
#define mmDCP1_GRPH_X_START 0x1d0b
#define mmDCP2_GRPH_X_START 0x400b
#define mmDCP3_GRPH_X_START 0x430b
#define mmDCP4_GRPH_X_START 0x460b
#define mmDCP5_GRPH_X_START 0x490b
#define mmGRPH_Y_START 0x1a0c
#define mmDCP0_GRPH_Y_START 0x1a0c
#define mmDCP1_GRPH_Y_START 0x1d0c
#define mmDCP2_GRPH_Y_START 0x400c
#define mmDCP3_GRPH_Y_START 0x430c
#define mmDCP4_GRPH_Y_START 0x460c
#define mmDCP5_GRPH_Y_START 0x490c
#define mmGRPH_X_END 0x1a0d
#define mmDCP0_GRPH_X_END 0x1a0d
#define mmDCP1_GRPH_X_END 0x1d0d
#define mmDCP2_GRPH_X_END 0x400d
#define mmDCP3_GRPH_X_END 0x430d
#define mmDCP4_GRPH_X_END 0x460d
#define mmDCP5_GRPH_X_END 0x490d
#define mmGRPH_Y_END 0x1a0e
#define mmDCP0_GRPH_Y_END 0x1a0e
#define mmDCP1_GRPH_Y_END 0x1d0e
#define mmDCP2_GRPH_Y_END 0x400e
#define mmDCP3_GRPH_Y_END 0x430e
#define mmDCP4_GRPH_Y_END 0x460e
#define mmDCP5_GRPH_Y_END 0x490e
#define mmINPUT_GAMMA_CONTROL 0x1a10
#define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10
#define mmDCP1_INPUT_GAMMA_CONTROL 0x1d10
#define mmDCP2_INPUT_GAMMA_CONTROL 0x4010
#define mmDCP3_INPUT_GAMMA_CONTROL 0x4310
#define mmDCP4_INPUT_GAMMA_CONTROL 0x4610
#define mmDCP5_INPUT_GAMMA_CONTROL 0x4910
#define mmGRPH_UPDATE 0x1a11
#define mmDCP0_GRPH_UPDATE 0x1a11
#define mmDCP1_GRPH_UPDATE 0x1d11
#define mmDCP2_GRPH_UPDATE 0x4011
#define mmDCP3_GRPH_UPDATE 0x4311
#define mmDCP4_GRPH_UPDATE 0x4611
#define mmDCP5_GRPH_UPDATE 0x4911
#define mmGRPH_FLIP_CONTROL 0x1a12
#define mmDCP0_GRPH_FLIP_CONTROL 0x1a12
#define mmDCP1_GRPH_FLIP_CONTROL 0x1d12
#define mmDCP2_GRPH_FLIP_CONTROL 0x4012
#define mmDCP3_GRPH_FLIP_CONTROL 0x4312
#define mmDCP4_GRPH_FLIP_CONTROL 0x4612
#define mmDCP5_GRPH_FLIP_CONTROL 0x4912
#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13
#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13
#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1d13
#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013
#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313
#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613
#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913
#define mmGRPH_DFQ_CONTROL 0x1a14
#define mmDCP0_GRPH_DFQ_CONTROL 0x1a14
#define mmDCP1_GRPH_DFQ_CONTROL 0x1d14
#define mmDCP2_GRPH_DFQ_CONTROL 0x4014
#define mmDCP3_GRPH_DFQ_CONTROL 0x4314
#define mmDCP4_GRPH_DFQ_CONTROL 0x4614
#define mmDCP5_GRPH_DFQ_CONTROL 0x4914
#define mmGRPH_DFQ_STATUS 0x1a15
#define mmDCP0_GRPH_DFQ_STATUS 0x1a15
#define mmDCP1_GRPH_DFQ_STATUS 0x1d15
#define mmDCP2_GRPH_DFQ_STATUS 0x4015
#define mmDCP3_GRPH_DFQ_STATUS 0x4315
#define mmDCP4_GRPH_DFQ_STATUS 0x4615
#define mmDCP5_GRPH_DFQ_STATUS 0x4915
#define mmGRPH_INTERRUPT_STATUS 0x1a16
#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16
#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1d16
#define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016
#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316
#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616
#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916
#define mmGRPH_INTERRUPT_CONTROL 0x1a17
#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17
#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1d17
#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017
#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317
#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617
#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917
#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1d18
#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018
#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318
#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618
#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918
#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1d19
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919
#define mmGRPH_COMPRESS_PITCH 0x1a1a
#define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a
#define mmDCP1_GRPH_COMPRESS_PITCH 0x1d1a
#define mmDCP2_GRPH_COMPRESS_PITCH 0x401a
#define mmDCP3_GRPH_COMPRESS_PITCH 0x431a
#define mmDCP4_GRPH_COMPRESS_PITCH 0x461a
#define mmDCP5_GRPH_COMPRESS_PITCH 0x491a
#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1d1b
#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b
#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431b
#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461b
#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491b
#define mmOVL_ENABLE 0x1a1c
#define mmDCP0_OVL_ENABLE 0x1a1c
#define mmDCP1_OVL_ENABLE 0x1d1c
#define mmDCP2_OVL_ENABLE 0x401c
#define mmDCP3_OVL_ENABLE 0x431c
#define mmDCP4_OVL_ENABLE 0x461c
#define mmDCP5_OVL_ENABLE 0x491c
#define mmOVL_CONTROL1 0x1a1d
#define mmDCP0_OVL_CONTROL1 0x1a1d
#define mmDCP1_OVL_CONTROL1 0x1d1d
#define mmDCP2_OVL_CONTROL1 0x401d
#define mmDCP3_OVL_CONTROL1 0x431d
#define mmDCP4_OVL_CONTROL1 0x461d
#define mmDCP5_OVL_CONTROL1 0x491d
#define mmOVL_CONTROL2 0x1a1e
#define mmDCP0_OVL_CONTROL2 0x1a1e
#define mmDCP1_OVL_CONTROL2 0x1d1e
#define mmDCP2_OVL_CONTROL2 0x401e
#define mmDCP3_OVL_CONTROL2 0x431e
#define mmDCP4_OVL_CONTROL2 0x461e
#define mmDCP5_OVL_CONTROL2 0x491e
#define mmOVL_SWAP_CNTL 0x1a1f
#define mmDCP0_OVL_SWAP_CNTL 0x1a1f
#define mmDCP1_OVL_SWAP_CNTL 0x1d1f
#define mmDCP2_OVL_SWAP_CNTL 0x401f
#define mmDCP3_OVL_SWAP_CNTL 0x431f
#define mmDCP4_OVL_SWAP_CNTL 0x461f
#define mmDCP5_OVL_SWAP_CNTL 0x491f
#define mmOVL_SURFACE_ADDRESS 0x1a20
#define mmDCP0_OVL_SURFACE_ADDRESS 0x1a20
#define mmDCP1_OVL_SURFACE_ADDRESS 0x1d20
#define mmDCP2_OVL_SURFACE_ADDRESS 0x4020
#define mmDCP3_OVL_SURFACE_ADDRESS 0x4320
#define mmDCP4_OVL_SURFACE_ADDRESS 0x4620
#define mmDCP5_OVL_SURFACE_ADDRESS 0x4920
#define mmOVL_PITCH 0x1a21
#define mmDCP0_OVL_PITCH 0x1a21
#define mmDCP1_OVL_PITCH 0x1d21
#define mmDCP2_OVL_PITCH 0x4021
#define mmDCP3_OVL_PITCH 0x4321
#define mmDCP4_OVL_PITCH 0x4621
#define mmDCP5_OVL_PITCH 0x4921
#define mmOVL_SURFACE_ADDRESS_HIGH 0x1a22
#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22
#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1d22
#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022
#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322
#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622
#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922
#define mmOVL_SURFACE_OFFSET_X 0x1a23
#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23
#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1d23
#define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023
#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323
#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623
#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923
#define mmOVL_SURFACE_OFFSET_Y 0x1a24
#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24
#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1d24
#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024
#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324
#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624
#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924
#define mmOVL_START 0x1a25
#define mmDCP0_OVL_START 0x1a25
#define mmDCP1_OVL_START 0x1d25
#define mmDCP2_OVL_START 0x4025
#define mmDCP3_OVL_START 0x4325
#define mmDCP4_OVL_START 0x4625
#define mmDCP5_OVL_START 0x4925
#define mmOVL_END 0x1a26
#define mmDCP0_OVL_END 0x1a26
#define mmDCP1_OVL_END 0x1d26
#define mmDCP2_OVL_END 0x4026
#define mmDCP3_OVL_END 0x4326
#define mmDCP4_OVL_END 0x4626
#define mmDCP5_OVL_END 0x4926
#define mmOVL_UPDATE 0x1a27
#define mmDCP0_OVL_UPDATE 0x1a27
#define mmDCP1_OVL_UPDATE 0x1d27
#define mmDCP2_OVL_UPDATE 0x4027
#define mmDCP3_OVL_UPDATE 0x4327
#define mmDCP4_OVL_UPDATE 0x4627
#define mmDCP5_OVL_UPDATE 0x4927
#define mmOVL_SURFACE_ADDRESS_INUSE 0x1a28
#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28
#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1d28
#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028
#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328
#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628
#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928
#define mmOVL_DFQ_CONTROL 0x1a29
#define mmDCP0_OVL_DFQ_CONTROL 0x1a29
#define mmDCP1_OVL_DFQ_CONTROL 0x1d29
#define mmDCP2_OVL_DFQ_CONTROL 0x4029
#define mmDCP3_OVL_DFQ_CONTROL 0x4329
#define mmDCP4_OVL_DFQ_CONTROL 0x4629
#define mmDCP5_OVL_DFQ_CONTROL 0x4929
#define mmOVL_DFQ_STATUS 0x1a2a
#define mmDCP0_OVL_DFQ_STATUS 0x1a2a
#define mmDCP1_OVL_DFQ_STATUS 0x1d2a
#define mmDCP2_OVL_DFQ_STATUS 0x402a
#define mmDCP3_OVL_DFQ_STATUS 0x432a
#define mmDCP4_OVL_DFQ_STATUS 0x462a
#define mmDCP5_OVL_DFQ_STATUS 0x492a
#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b
#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b
#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1d2b
#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b
#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432b
#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462b
#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492b
#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c
#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c
#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1d2c
#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402c
#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432c
#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462c
#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492c
#define mmPRESCALE_GRPH_CONTROL 0x1a2d
#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d
#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1d2d
#define mmDCP2_PRESCALE_GRPH_CONTROL 0x402d
#define mmDCP3_PRESCALE_GRPH_CONTROL 0x432d
#define mmDCP4_PRESCALE_GRPH_CONTROL 0x462d
#define mmDCP5_PRESCALE_GRPH_CONTROL 0x492d
#define mmPRESCALE_VALUES_GRPH_R 0x1a2e
#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e
#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1d2e
#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402e
#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432e
#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462e
#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492e
#define mmPRESCALE_VALUES_GRPH_G 0x1a2f
#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f
#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1d2f
#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402f
#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432f
#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462f
#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492f
#define mmPRESCALE_VALUES_GRPH_B 0x1a30
#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30
#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1d30
#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030
#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330
#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630
#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930
#define mmPRESCALE_OVL_CONTROL 0x1a31
#define mmDCP0_PRESCALE_OVL_CONTROL 0x1a31
#define mmDCP1_PRESCALE_OVL_CONTROL 0x1d31
#define mmDCP2_PRESCALE_OVL_CONTROL 0x4031
#define mmDCP3_PRESCALE_OVL_CONTROL 0x4331
#define mmDCP4_PRESCALE_OVL_CONTROL 0x4631
#define mmDCP5_PRESCALE_OVL_CONTROL 0x4931
#define mmPRESCALE_VALUES_OVL_CB 0x1a32
#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32
#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1d32
#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032
#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332
#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632
#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932
#define mmPRESCALE_VALUES_OVL_Y 0x1a33
#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33
#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1d33
#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033
#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333
#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633
#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933
#define mmPRESCALE_VALUES_OVL_CR 0x1a34
#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34
#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1d34
#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034
#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334
#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634
#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934
#define mmINPUT_CSC_CONTROL 0x1a35
#define mmDCP0_INPUT_CSC_CONTROL 0x1a35
#define mmDCP1_INPUT_CSC_CONTROL 0x1d35
#define mmDCP2_INPUT_CSC_CONTROL 0x4035
#define mmDCP3_INPUT_CSC_CONTROL 0x4335
#define mmDCP4_INPUT_CSC_CONTROL 0x4635
#define mmDCP5_INPUT_CSC_CONTROL 0x4935
#define mmINPUT_CSC_C11_C12 0x1a36
#define mmDCP0_INPUT_CSC_C11_C12 0x1a36
#define mmDCP1_INPUT_CSC_C11_C12 0x1d36
#define mmDCP2_INPUT_CSC_C11_C12 0x4036
#define mmDCP3_INPUT_CSC_C11_C12 0x4336
#define mmDCP4_INPUT_CSC_C11_C12 0x4636
#define mmDCP5_INPUT_CSC_C11_C12 0x4936
#define mmINPUT_CSC_C13_C14 0x1a37
#define mmDCP0_INPUT_CSC_C13_C14 0x1a37
#define mmDCP1_INPUT_CSC_C13_C14 0x1d37
#define mmDCP2_INPUT_CSC_C13_C14 0x4037
#define mmDCP3_INPUT_CSC_C13_C14 0x4337
#define mmDCP4_INPUT_CSC_C13_C14 0x4637
#define mmDCP5_INPUT_CSC_C13_C14 0x4937
#define mmINPUT_CSC_C21_C22 0x1a38
#define mmDCP0_INPUT_CSC_C21_C22 0x1a38
#define mmDCP1_INPUT_CSC_C21_C22 0x1d38
#define mmDCP2_INPUT_CSC_C21_C22 0x4038
#define mmDCP3_INPUT_CSC_C21_C22 0x4338
#define mmDCP4_INPUT_CSC_C21_C22 0x4638
#define mmDCP5_INPUT_CSC_C21_C22 0x4938
#define mmINPUT_CSC_C23_C24 0x1a39
#define mmDCP0_INPUT_CSC_C23_C24 0x1a39
#define mmDCP1_INPUT_CSC_C23_C24 0x1d39
#define mmDCP2_INPUT_CSC_C23_C24 0x4039
#define mmDCP3_INPUT_CSC_C23_C24 0x4339
#define mmDCP4_INPUT_CSC_C23_C24 0x4639
#define mmDCP5_INPUT_CSC_C23_C24 0x4939
#define mmINPUT_CSC_C31_C32 0x1a3a
#define mmDCP0_INPUT_CSC_C31_C32 0x1a3a
#define mmDCP1_INPUT_CSC_C31_C32 0x1d3a
#define mmDCP2_INPUT_CSC_C31_C32 0x403a
#define mmDCP3_INPUT_CSC_C31_C32 0x433a
#define mmDCP4_INPUT_CSC_C31_C32 0x463a
#define mmDCP5_INPUT_CSC_C31_C32 0x493a
#define mmINPUT_CSC_C33_C34 0x1a3b
#define mmDCP0_INPUT_CSC_C33_C34 0x1a3b
#define mmDCP1_INPUT_CSC_C33_C34 0x1d3b
#define mmDCP2_INPUT_CSC_C33_C34 0x403b
#define mmDCP3_INPUT_CSC_C33_C34 0x433b
#define mmDCP4_INPUT_CSC_C33_C34 0x463b
#define mmDCP5_INPUT_CSC_C33_C34 0x493b
#define mmOUTPUT_CSC_CONTROL 0x1a3c
#define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c
#define mmDCP1_OUTPUT_CSC_CONTROL 0x1d3c
#define mmDCP2_OUTPUT_CSC_CONTROL 0x403c
#define mmDCP3_OUTPUT_CSC_CONTROL 0x433c
#define mmDCP4_OUTPUT_CSC_CONTROL 0x463c
#define mmDCP5_OUTPUT_CSC_CONTROL 0x493c
#define mmOUTPUT_CSC_C11_C12 0x1a3d
#define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d
#define mmDCP1_OUTPUT_CSC_C11_C12 0x1d3d
#define mmDCP2_OUTPUT_CSC_C11_C12 0x403d
#define mmDCP3_OUTPUT_CSC_C11_C12 0x433d
#define mmDCP4_OUTPUT_CSC_C11_C12 0x463d
#define mmDCP5_OUTPUT_CSC_C11_C12 0x493d
#define mmOUTPUT_CSC_C13_C14 0x1a3e
#define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e
#define mmDCP1_OUTPUT_CSC_C13_C14 0x1d3e
#define mmDCP2_OUTPUT_CSC_C13_C14 0x403e
#define mmDCP3_OUTPUT_CSC_C13_C14 0x433e
#define mmDCP4_OUTPUT_CSC_C13_C14 0x463e
#define mmDCP5_OUTPUT_CSC_C13_C14 0x493e
#define mmOUTPUT_CSC_C21_C22 0x1a3f
#define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f
#define mmDCP1_OUTPUT_CSC_C21_C22 0x1d3f
#define mmDCP2_OUTPUT_CSC_C21_C22 0x403f
#define mmDCP3_OUTPUT_CSC_C21_C22 0x433f
#define mmDCP4_OUTPUT_CSC_C21_C22 0x463f
#define mmDCP5_OUTPUT_CSC_C21_C22 0x493f
#define mmOUTPUT_CSC_C23_C24 0x1a40
#define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40
#define mmDCP1_OUTPUT_CSC_C23_C24 0x1d40
#define mmDCP2_OUTPUT_CSC_C23_C24 0x4040
#define mmDCP3_OUTPUT_CSC_C23_C24 0x4340
#define mmDCP4_OUTPUT_CSC_C23_C24 0x4640
#define mmDCP5_OUTPUT_CSC_C23_C24 0x4940
#define mmOUTPUT_CSC_C31_C32 0x1a41
#define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41
#define mmDCP1_OUTPUT_CSC_C31_C32 0x1d41
#define mmDCP2_OUTPUT_CSC_C31_C32 0x4041
#define mmDCP3_OUTPUT_CSC_C31_C32 0x4341
#define mmDCP4_OUTPUT_CSC_C31_C32 0x4641
#define mmDCP5_OUTPUT_CSC_C31_C32 0x4941
#define mmOUTPUT_CSC_C33_C34 0x1a42
#define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42
#define mmDCP1_OUTPUT_CSC_C33_C34 0x1d42
#define mmDCP2_OUTPUT_CSC_C33_C34 0x4042
#define mmDCP3_OUTPUT_CSC_C33_C34 0x4342
#define mmDCP4_OUTPUT_CSC_C33_C34 0x4642
#define mmDCP5_OUTPUT_CSC_C33_C34 0x4942
#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43
#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43
#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1d43
#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043
#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343
#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643
#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943
#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44
#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44
#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1d44
#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044
#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344
#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644
#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944
#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45
#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45
#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1d45
#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045
#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345
#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645
#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945
#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46
#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46
#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1d46
#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046
#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346
#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646
#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946
#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47
#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47
#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1d47
#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047
#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347
#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647
#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947
#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48
#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48
#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1d48
#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048
#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348
#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648
#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948
#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49
#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49
#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1d49
#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049
#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349
#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649
#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949
#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a
#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a
#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1d4a
#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404a
#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434a
#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464a
#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494a
#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b
#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b
#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1d4b
#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404b
#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434b
#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464b
#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494b
#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c
#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c
#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1d4c
#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404c
#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434c
#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464c
#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494c
#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d
#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d
#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1d4d
#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404d
#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434d
#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464d
#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494d
#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e
#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e
#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1d4e
#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404e
#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434e
#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464e
#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494e
#define mmDENORM_CONTROL 0x1a50
#define mmDCP0_DENORM_CONTROL 0x1a50
#define mmDCP1_DENORM_CONTROL 0x1d50
#define mmDCP2_DENORM_CONTROL 0x4050
#define mmDCP3_DENORM_CONTROL 0x4350
#define mmDCP4_DENORM_CONTROL 0x4650
#define mmDCP5_DENORM_CONTROL 0x4950
#define mmOUT_ROUND_CONTROL 0x1a51
#define mmDCP0_OUT_ROUND_CONTROL 0x1a51
#define mmDCP1_OUT_ROUND_CONTROL 0x1d51
#define mmDCP2_OUT_ROUND_CONTROL 0x4051
#define mmDCP3_OUT_ROUND_CONTROL 0x4351
#define mmDCP4_OUT_ROUND_CONTROL 0x4651
#define mmDCP5_OUT_ROUND_CONTROL 0x4951
#define mmOUT_CLAMP_CONTROL_R_CR 0x1a52
#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52
#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1d52
#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x4052
#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4352
#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4652
#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4952
#define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c
#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c
#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1d9c
#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x409c
#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x439c
#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x469c
#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x499c
#define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d
#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d
#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1d9d
#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x409d
#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x439d
#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x469d
#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x499d
#define mmKEY_CONTROL 0x1a53
#define mmDCP0_KEY_CONTROL 0x1a53
#define mmDCP1_KEY_CONTROL 0x1d53
#define mmDCP2_KEY_CONTROL 0x4053
#define mmDCP3_KEY_CONTROL 0x4353
#define mmDCP4_KEY_CONTROL 0x4653
#define mmDCP5_KEY_CONTROL 0x4953
#define mmKEY_RANGE_ALPHA 0x1a54
#define mmDCP0_KEY_RANGE_ALPHA 0x1a54
#define mmDCP1_KEY_RANGE_ALPHA 0x1d54
#define mmDCP2_KEY_RANGE_ALPHA 0x4054
#define mmDCP3_KEY_RANGE_ALPHA 0x4354
#define mmDCP4_KEY_RANGE_ALPHA 0x4654
#define mmDCP5_KEY_RANGE_ALPHA 0x4954
#define mmKEY_RANGE_RED 0x1a55
#define mmDCP0_KEY_RANGE_RED 0x1a55
#define mmDCP1_KEY_RANGE_RED 0x1d55
#define mmDCP2_KEY_RANGE_RED 0x4055
#define mmDCP3_KEY_RANGE_RED 0x4355
#define mmDCP4_KEY_RANGE_RED 0x4655
#define mmDCP5_KEY_RANGE_RED 0x4955
#define mmKEY_RANGE_GREEN 0x1a56
#define mmDCP0_KEY_RANGE_GREEN 0x1a56
#define mmDCP1_KEY_RANGE_GREEN 0x1d56
#define mmDCP2_KEY_RANGE_GREEN 0x4056
#define mmDCP3_KEY_RANGE_GREEN 0x4356
#define mmDCP4_KEY_RANGE_GREEN 0x4656
#define mmDCP5_KEY_RANGE_GREEN 0x4956
#define mmKEY_RANGE_BLUE 0x1a57
#define mmDCP0_KEY_RANGE_BLUE 0x1a57
#define mmDCP1_KEY_RANGE_BLUE 0x1d57
#define mmDCP2_KEY_RANGE_BLUE 0x4057
#define mmDCP3_KEY_RANGE_BLUE 0x4357
#define mmDCP4_KEY_RANGE_BLUE 0x4657
#define mmDCP5_KEY_RANGE_BLUE 0x4957
#define mmDEGAMMA_CONTROL 0x1a58
#define mmDCP0_DEGAMMA_CONTROL 0x1a58
#define mmDCP1_DEGAMMA_CONTROL 0x1d58
#define mmDCP2_DEGAMMA_CONTROL 0x4058
#define mmDCP3_DEGAMMA_CONTROL 0x4358
#define mmDCP4_DEGAMMA_CONTROL 0x4658
#define mmDCP5_DEGAMMA_CONTROL 0x4958
#define mmGAMUT_REMAP_CONTROL 0x1a59
#define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59
#define mmDCP1_GAMUT_REMAP_CONTROL 0x1d59
#define mmDCP2_GAMUT_REMAP_CONTROL 0x4059
#define mmDCP3_GAMUT_REMAP_CONTROL 0x4359
#define mmDCP4_GAMUT_REMAP_CONTROL 0x4659
#define mmDCP5_GAMUT_REMAP_CONTROL 0x4959
#define mmGAMUT_REMAP_C11_C12 0x1a5a
#define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a
#define mmDCP1_GAMUT_REMAP_C11_C12 0x1d5a
#define mmDCP2_GAMUT_REMAP_C11_C12 0x405a
#define mmDCP3_GAMUT_REMAP_C11_C12 0x435a
#define mmDCP4_GAMUT_REMAP_C11_C12 0x465a
#define mmDCP5_GAMUT_REMAP_C11_C12 0x495a
#define mmGAMUT_REMAP_C13_C14 0x1a5b
#define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b
#define mmDCP1_GAMUT_REMAP_C13_C14 0x1d5b
#define mmDCP2_GAMUT_REMAP_C13_C14 0x405b
#define mmDCP3_GAMUT_REMAP_C13_C14 0x435b
#define mmDCP4_GAMUT_REMAP_C13_C14 0x465b
#define mmDCP5_GAMUT_REMAP_C13_C14 0x495b
#define mmGAMUT_REMAP_C21_C22 0x1a5c
#define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c
#define mmDCP1_GAMUT_REMAP_C21_C22 0x1d5c
#define mmDCP2_GAMUT_REMAP_C21_C22 0x405c
#define mmDCP3_GAMUT_REMAP_C21_C22 0x435c
#define mmDCP4_GAMUT_REMAP_C21_C22 0x465c
#define mmDCP5_GAMUT_REMAP_C21_C22 0x495c
#define mmGAMUT_REMAP_C23_C24 0x1a5d
#define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d
#define mmDCP1_GAMUT_REMAP_C23_C24 0x1d5d
#define mmDCP2_GAMUT_REMAP_C23_C24 0x405d
#define mmDCP3_GAMUT_REMAP_C23_C24 0x435d
#define mmDCP4_GAMUT_REMAP_C23_C24 0x465d
#define mmDCP5_GAMUT_REMAP_C23_C24 0x495d
#define mmGAMUT_REMAP_C31_C32 0x1a5e
#define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e
#define mmDCP1_GAMUT_REMAP_C31_C32 0x1d5e
#define mmDCP2_GAMUT_REMAP_C31_C32 0x405e
#define mmDCP3_GAMUT_REMAP_C31_C32 0x435e
#define mmDCP4_GAMUT_REMAP_C31_C32 0x465e
#define mmDCP5_GAMUT_REMAP_C31_C32 0x495e
#define mmGAMUT_REMAP_C33_C34 0x1a5f
#define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f
#define mmDCP1_GAMUT_REMAP_C33_C34 0x1d5f
#define mmDCP2_GAMUT_REMAP_C33_C34 0x405f
#define mmDCP3_GAMUT_REMAP_C33_C34 0x435f
#define mmDCP4_GAMUT_REMAP_C33_C34 0x465f
#define mmDCP5_GAMUT_REMAP_C33_C34 0x495f
#define mmDCP_SPATIAL_DITHER_CNTL 0x1a60
#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60
#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1d60
#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060
#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360
#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660
#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960
#define mmDCP_RANDOM_SEEDS 0x1a61
#define mmDCP0_DCP_RANDOM_SEEDS 0x1a61
#define mmDCP1_DCP_RANDOM_SEEDS 0x1d61
#define mmDCP2_DCP_RANDOM_SEEDS 0x4061
#define mmDCP3_DCP_RANDOM_SEEDS 0x4361
#define mmDCP4_DCP_RANDOM_SEEDS 0x4661
#define mmDCP5_DCP_RANDOM_SEEDS 0x4961
#define mmDCP_FP_CONVERTED_FIELD 0x1a65
#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65
#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1d65
#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065
#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365
#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665
#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965
#define mmCUR_CONTROL 0x1a66
#define mmDCP0_CUR_CONTROL 0x1a66
#define mmDCP1_CUR_CONTROL 0x1d66
#define mmDCP2_CUR_CONTROL 0x4066
#define mmDCP3_CUR_CONTROL 0x4366
#define mmDCP4_CUR_CONTROL 0x4666
#define mmDCP5_CUR_CONTROL 0x4966
#define mmCUR_SURFACE_ADDRESS 0x1a67
#define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67
#define mmDCP1_CUR_SURFACE_ADDRESS 0x1d67
#define mmDCP2_CUR_SURFACE_ADDRESS 0x4067
#define mmDCP3_CUR_SURFACE_ADDRESS 0x4367
#define mmDCP4_CUR_SURFACE_ADDRESS 0x4667
#define mmDCP5_CUR_SURFACE_ADDRESS 0x4967
#define mmCUR_SIZE 0x1a68
#define mmDCP0_CUR_SIZE 0x1a68
#define mmDCP1_CUR_SIZE 0x1d68
#define mmDCP2_CUR_SIZE 0x4068
#define mmDCP3_CUR_SIZE 0x4368
#define mmDCP4_CUR_SIZE 0x4668
#define mmDCP5_CUR_SIZE 0x4968
#define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69
#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69
#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1d69
#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069
#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369
#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669
#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969
#define mmCUR_POSITION 0x1a6a
#define mmDCP0_CUR_POSITION 0x1a6a
#define mmDCP1_CUR_POSITION 0x1d6a
#define mmDCP2_CUR_POSITION 0x406a
#define mmDCP3_CUR_POSITION 0x436a
#define mmDCP4_CUR_POSITION 0x466a
#define mmDCP5_CUR_POSITION 0x496a
#define mmCUR_HOT_SPOT 0x1a6b
#define mmDCP0_CUR_HOT_SPOT 0x1a6b
#define mmDCP1_CUR_HOT_SPOT 0x1d6b
#define mmDCP2_CUR_HOT_SPOT 0x406b
#define mmDCP3_CUR_HOT_SPOT 0x436b
#define mmDCP4_CUR_HOT_SPOT 0x466b
#define mmDCP5_CUR_HOT_SPOT 0x496b
#define mmCUR_COLOR1 0x1a6c
#define mmDCP0_CUR_COLOR1 0x1a6c
#define mmDCP1_CUR_COLOR1 0x1d6c
#define mmDCP2_CUR_COLOR1 0x406c
#define mmDCP3_CUR_COLOR1 0x436c
#define mmDCP4_CUR_COLOR1 0x466c
#define mmDCP5_CUR_COLOR1 0x496c
#define mmCUR_COLOR2 0x1a6d
#define mmDCP0_CUR_COLOR2 0x1a6d
#define mmDCP1_CUR_COLOR2 0x1d6d
#define mmDCP2_CUR_COLOR2 0x406d
#define mmDCP3_CUR_COLOR2 0x436d
#define mmDCP4_CUR_COLOR2 0x466d
#define mmDCP5_CUR_COLOR2 0x496d
#define mmCUR_UPDATE 0x1a6e
#define mmDCP0_CUR_UPDATE 0x1a6e
#define mmDCP1_CUR_UPDATE 0x1d6e
#define mmDCP2_CUR_UPDATE 0x406e
#define mmDCP3_CUR_UPDATE 0x436e
#define mmDCP4_CUR_UPDATE 0x466e
#define mmDCP5_CUR_UPDATE 0x496e
#define mmCUR2_CONTROL 0x1a6f
#define mmDCP0_CUR2_CONTROL 0x1a6f
#define mmDCP1_CUR2_CONTROL 0x1d6f
#define mmDCP2_CUR2_CONTROL 0x406f
#define mmDCP3_CUR2_CONTROL 0x436f
#define mmDCP4_CUR2_CONTROL 0x466f
#define mmDCP5_CUR2_CONTROL 0x496f
#define mmCUR2_SURFACE_ADDRESS 0x1a70
#define mmDCP0_CUR2_SURFACE_ADDRESS 0x1a70
#define mmDCP1_CUR2_SURFACE_ADDRESS 0x1d70
#define mmDCP2_CUR2_SURFACE_ADDRESS 0x4070
#define mmDCP3_CUR2_SURFACE_ADDRESS 0x4370
#define mmDCP4_CUR2_SURFACE_ADDRESS 0x4670
#define mmDCP5_CUR2_SURFACE_ADDRESS 0x4970
#define mmCUR2_SIZE 0x1a71
#define mmDCP0_CUR2_SIZE 0x1a71
#define mmDCP1_CUR2_SIZE 0x1d71
#define mmDCP2_CUR2_SIZE 0x4071
#define mmDCP3_CUR2_SIZE 0x4371
#define mmDCP4_CUR2_SIZE 0x4671
#define mmDCP5_CUR2_SIZE 0x4971
#define mmCUR2_SURFACE_ADDRESS_HIGH 0x1a72
#define mmDCP0_CUR2_SURFACE_ADDRESS_HIGH 0x1a72
#define mmDCP1_CUR2_SURFACE_ADDRESS_HIGH 0x1d72
#define mmDCP2_CUR2_SURFACE_ADDRESS_HIGH 0x4072
#define mmDCP3_CUR2_SURFACE_ADDRESS_HIGH 0x4372
#define mmDCP4_CUR2_SURFACE_ADDRESS_HIGH 0x4672
#define mmDCP5_CUR2_SURFACE_ADDRESS_HIGH 0x4972
#define mmCUR2_POSITION 0x1a73
#define mmDCP0_CUR2_POSITION 0x1a73
#define mmDCP1_CUR2_POSITION 0x1d73
#define mmDCP2_CUR2_POSITION 0x4073
#define mmDCP3_CUR2_POSITION 0x4373
#define mmDCP4_CUR2_POSITION 0x4673
#define mmDCP5_CUR2_POSITION 0x4973
#define mmCUR2_HOT_SPOT 0x1a74
#define mmDCP0_CUR2_HOT_SPOT 0x1a74
#define mmDCP1_CUR2_HOT_SPOT 0x1d74
#define mmDCP2_CUR2_HOT_SPOT 0x4074
#define mmDCP3_CUR2_HOT_SPOT 0x4374
#define mmDCP4_CUR2_HOT_SPOT 0x4674
#define mmDCP5_CUR2_HOT_SPOT 0x4974
#define mmCUR2_COLOR1 0x1a75
#define mmDCP0_CUR2_COLOR1 0x1a75
#define mmDCP1_CUR2_COLOR1 0x1d75
#define mmDCP2_CUR2_COLOR1 0x4075
#define mmDCP3_CUR2_COLOR1 0x4375
#define mmDCP4_CUR2_COLOR1 0x4675
#define mmDCP5_CUR2_COLOR1 0x4975
#define mmCUR2_COLOR2 0x1a76
#define mmDCP0_CUR2_COLOR2 0x1a76
#define mmDCP1_CUR2_COLOR2 0x1d76
#define mmDCP2_CUR2_COLOR2 0x4076
#define mmDCP3_CUR2_COLOR2 0x4376
#define mmDCP4_CUR2_COLOR2 0x4676
#define mmDCP5_CUR2_COLOR2 0x4976
#define mmCUR2_UPDATE 0x1a77
#define mmDCP0_CUR2_UPDATE 0x1a77
#define mmDCP1_CUR2_UPDATE 0x1d77
#define mmDCP2_CUR2_UPDATE 0x4077
#define mmDCP3_CUR2_UPDATE 0x4377
#define mmDCP4_CUR2_UPDATE 0x4677
#define mmDCP5_CUR2_UPDATE 0x4977
#define mmCUR_REQUEST_FILTER_CNTL 0x1a99
#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99
#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1d99
#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099
#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399
#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699
#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999
#define mmCUR_STEREO_CONTROL 0x1a9a
#define mmDCP0_CUR_STEREO_CONTROL 0x1a9a
#define mmDCP1_CUR_STEREO_CONTROL 0x1d9a
#define mmDCP2_CUR_STEREO_CONTROL 0x409a
#define mmDCP3_CUR_STEREO_CONTROL 0x439a
#define mmDCP4_CUR_STEREO_CONTROL 0x469a
#define mmDCP5_CUR_STEREO_CONTROL 0x499a
#define mmCUR2_STEREO_CONTROL 0x1a9b
#define mmDCP0_CUR2_STEREO_CONTROL 0x1a9b
#define mmDCP1_CUR2_STEREO_CONTROL 0x1d9b
#define mmDCP2_CUR2_STEREO_CONTROL 0x409b
#define mmDCP3_CUR2_STEREO_CONTROL 0x439b
#define mmDCP4_CUR2_STEREO_CONTROL 0x469b
#define mmDCP5_CUR2_STEREO_CONTROL 0x499b
#define mmDC_LUT_RW_MODE 0x1a78
#define mmDCP0_DC_LUT_RW_MODE 0x1a78
#define mmDCP1_DC_LUT_RW_MODE 0x1d78
#define mmDCP2_DC_LUT_RW_MODE 0x4078
#define mmDCP3_DC_LUT_RW_MODE 0x4378
#define mmDCP4_DC_LUT_RW_MODE 0x4678
#define mmDCP5_DC_LUT_RW_MODE 0x4978
#define mmDC_LUT_RW_INDEX 0x1a79
#define mmDCP0_DC_LUT_RW_INDEX 0x1a79
#define mmDCP1_DC_LUT_RW_INDEX 0x1d79
#define mmDCP2_DC_LUT_RW_INDEX 0x4079
#define mmDCP3_DC_LUT_RW_INDEX 0x4379
#define mmDCP4_DC_LUT_RW_INDEX 0x4679
#define mmDCP5_DC_LUT_RW_INDEX 0x4979
#define mmDC_LUT_SEQ_COLOR 0x1a7a
#define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a
#define mmDCP1_DC_LUT_SEQ_COLOR 0x1d7a
#define mmDCP2_DC_LUT_SEQ_COLOR 0x407a
#define mmDCP3_DC_LUT_SEQ_COLOR 0x437a
#define mmDCP4_DC_LUT_SEQ_COLOR 0x467a
#define mmDCP5_DC_LUT_SEQ_COLOR 0x497a
#define mmDC_LUT_PWL_DATA 0x1a7b
#define mmDCP0_DC_LUT_PWL_DATA 0x1a7b
#define mmDCP1_DC_LUT_PWL_DATA 0x1d7b
#define mmDCP2_DC_LUT_PWL_DATA 0x407b
#define mmDCP3_DC_LUT_PWL_DATA 0x437b
#define mmDCP4_DC_LUT_PWL_DATA 0x467b
#define mmDCP5_DC_LUT_PWL_DATA 0x497b
#define mmDC_LUT_30_COLOR 0x1a7c
#define mmDCP0_DC_LUT_30_COLOR 0x1a7c
#define mmDCP1_DC_LUT_30_COLOR 0x1d7c
#define mmDCP2_DC_LUT_30_COLOR 0x407c
#define mmDCP3_DC_LUT_30_COLOR 0x437c
#define mmDCP4_DC_LUT_30_COLOR 0x467c
#define mmDCP5_DC_LUT_30_COLOR 0x497c
#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d
#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d
#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1d7d
#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407d
#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437d
#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467d
#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497d
#define mmDC_LUT_WRITE_EN_MASK 0x1a7e
#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e
#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1d7e
#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407e
#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437e
#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467e
#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497e
#define mmDC_LUT_AUTOFILL 0x1a7f
#define mmDCP0_DC_LUT_AUTOFILL 0x1a7f
#define mmDCP1_DC_LUT_AUTOFILL 0x1d7f
#define mmDCP2_DC_LUT_AUTOFILL 0x407f
#define mmDCP3_DC_LUT_AUTOFILL 0x437f
#define mmDCP4_DC_LUT_AUTOFILL 0x467f
#define mmDCP5_DC_LUT_AUTOFILL 0x497f
#define mmDC_LUT_CONTROL 0x1a80
#define mmDCP0_DC_LUT_CONTROL 0x1a80
#define mmDCP1_DC_LUT_CONTROL 0x1d80
#define mmDCP2_DC_LUT_CONTROL 0x4080
#define mmDCP3_DC_LUT_CONTROL 0x4380
#define mmDCP4_DC_LUT_CONTROL 0x4680
#define mmDCP5_DC_LUT_CONTROL 0x4980
#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81
#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81
#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1d81
#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081
#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381
#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681
#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981
#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82
#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82
#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1d82
#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082
#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382
#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682
#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982
#define mmDC_LUT_BLACK_OFFSET_RED 0x1a83
#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83
#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1d83
#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083
#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383
#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683
#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983
#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84
#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84
#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1d84
#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084
#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384
#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684
#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984
#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85
#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85
#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1d85
#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085
#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385
#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685
#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985
#define mmDC_LUT_WHITE_OFFSET_RED 0x1a86
#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86
#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1d86
#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086
#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386
#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686
#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986
#define mmDCP_CRC_CONTROL 0x1a87
#define mmDCP0_DCP_CRC_CONTROL 0x1a87
#define mmDCP1_DCP_CRC_CONTROL 0x1d87
#define mmDCP2_DCP_CRC_CONTROL 0x4087
#define mmDCP3_DCP_CRC_CONTROL 0x4387
#define mmDCP4_DCP_CRC_CONTROL 0x4687
#define mmDCP5_DCP_CRC_CONTROL 0x4987
#define mmDCP_CRC_MASK 0x1a88
#define mmDCP0_DCP_CRC_MASK 0x1a88
#define mmDCP1_DCP_CRC_MASK 0x1d88
#define mmDCP2_DCP_CRC_MASK 0x4088
#define mmDCP3_DCP_CRC_MASK 0x4388
#define mmDCP4_DCP_CRC_MASK 0x4688
#define mmDCP5_DCP_CRC_MASK 0x4988
#define mmDCP_CRC_CURRENT 0x1a89
#define mmDCP0_DCP_CRC_CURRENT 0x1a89
#define mmDCP1_DCP_CRC_CURRENT 0x1d89
#define mmDCP2_DCP_CRC_CURRENT 0x4089
#define mmDCP3_DCP_CRC_CURRENT 0x4389
#define mmDCP4_DCP_CRC_CURRENT 0x4689
#define mmDCP5_DCP_CRC_CURRENT 0x4989
#define mmDCP_CRC_LAST 0x1a8b
#define mmDCP0_DCP_CRC_LAST 0x1a8b
#define mmDCP1_DCP_CRC_LAST 0x1d8b
#define mmDCP2_DCP_CRC_LAST 0x408b
#define mmDCP3_DCP_CRC_LAST 0x438b
#define mmDCP4_DCP_CRC_LAST 0x468b
#define mmDCP5_DCP_CRC_LAST 0x498b
#define mmDCP_DEBUG 0x1a8d
#define mmDCP0_DCP_DEBUG 0x1a8d
#define mmDCP1_DCP_DEBUG 0x1d8d
#define mmDCP2_DCP_DEBUG 0x408d
#define mmDCP3_DCP_DEBUG 0x438d
#define mmDCP4_DCP_DEBUG 0x468d
#define mmDCP5_DCP_DEBUG 0x498d
#define mmGRPH_FLIP_RATE_CNTL 0x1a8e
#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e
#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1d8e
#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x408e
#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x438e
#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x468e
#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x498e
#define mmDCP_GSL_CONTROL 0x1a90
#define mmDCP0_DCP_GSL_CONTROL 0x1a90
#define mmDCP1_DCP_GSL_CONTROL 0x1d90
#define mmDCP2_DCP_GSL_CONTROL 0x4090
#define mmDCP3_DCP_GSL_CONTROL 0x4390
#define mmDCP4_DCP_GSL_CONTROL 0x4690
#define mmDCP5_DCP_GSL_CONTROL 0x4990
#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1d91
#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091
#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391
#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691
#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991
#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92
#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92
#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1d92
#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092
#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392
#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692
#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992
#define mmOVL_STEREOSYNC_FLIP 0x1a93
#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93
#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1d93
#define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093
#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393
#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693
#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993
#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94
#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94
#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d94
#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094
#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394
#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694
#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994
#define mmDCP_TEST_DEBUG_INDEX 0x1a95
#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95
#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1d95
#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095
#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395
#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695
#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995
#define mmDCP_TEST_DEBUG_DATA 0x1a96
#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96
#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1d96
#define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096
#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396
#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696
#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996
#define mmGRPH_STEREOSYNC_FLIP 0x1a97
#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97
#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1d97
#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097
#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397
#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697
#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997
#define mmDCP_DEBUG2 0x1a98
#define mmDCP0_DCP_DEBUG2 0x1a98
#define mmDCP1_DCP_DEBUG2 0x1d98
#define mmDCP2_DCP_DEBUG2 0x4098
#define mmDCP3_DCP_DEBUG2 0x4398
#define mmDCP4_DCP_DEBUG2 0x4698
#define mmDCP5_DCP_DEBUG2 0x4998
#define mmHW_ROTATION 0x1a9e
#define mmDCP0_HW_ROTATION 0x1a9e
#define mmDCP1_HW_ROTATION 0x1d9e
#define mmDCP2_HW_ROTATION 0x409e
#define mmDCP3_HW_ROTATION 0x439e
#define mmDCP4_HW_ROTATION 0x469e
#define mmDCP5_HW_ROTATION 0x499e
#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1d9f
#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f
#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x439f
#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x469f
#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x499f
#define mmREGAMMA_CONTROL 0x1aa0
#define mmDCP0_REGAMMA_CONTROL 0x1aa0
#define mmDCP1_REGAMMA_CONTROL 0x1da0
#define mmDCP2_REGAMMA_CONTROL 0x40a0
#define mmDCP3_REGAMMA_CONTROL 0x43a0
#define mmDCP4_REGAMMA_CONTROL 0x46a0
#define mmDCP5_REGAMMA_CONTROL 0x49a0
#define mmREGAMMA_LUT_INDEX 0x1aa1
#define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1
#define mmDCP1_REGAMMA_LUT_INDEX 0x1da1
#define mmDCP2_REGAMMA_LUT_INDEX 0x40a1
#define mmDCP3_REGAMMA_LUT_INDEX 0x43a1
#define mmDCP4_REGAMMA_LUT_INDEX 0x46a1
#define mmDCP5_REGAMMA_LUT_INDEX 0x49a1
#define mmREGAMMA_LUT_DATA 0x1aa2
#define mmDCP0_REGAMMA_LUT_DATA 0x1aa2
#define mmDCP1_REGAMMA_LUT_DATA 0x1da2
#define mmDCP2_REGAMMA_LUT_DATA 0x40a2
#define mmDCP3_REGAMMA_LUT_DATA 0x43a2
#define mmDCP4_REGAMMA_LUT_DATA 0x46a2
#define mmDCP5_REGAMMA_LUT_DATA 0x49a2
#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3
#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3
#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1da3
#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40a3
#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43a3
#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46a3
#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49a3
#define mmREGAMMA_CNTLA_START_CNTL 0x1aa4
#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4
#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1da4
#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40a4
#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43a4
#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46a4
#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49a4
#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1da5
#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5
#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43a5
#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46a5
#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49a5
#define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6
#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6
#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1da6
#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40a6
#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43a6
#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46a6
#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49a6
#define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7
#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7
#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1da7
#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40a7
#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43a7
#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46a7
#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49a7
#define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8
#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8
#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1da8
#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40a8
#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43a8
#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46a8
#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49a8
#define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9
#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9
#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1da9
#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40a9
#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43a9
#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46a9
#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49a9
#define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa
#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa
#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1daa
#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40aa
#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43aa
#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46aa
#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49aa
#define mmREGAMMA_CNTLA_REGION_6_7 0x1aab
#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab
#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1dab
#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40ab
#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43ab
#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46ab
#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49ab
#define mmREGAMMA_CNTLA_REGION_8_9 0x1aac
#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac
#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1dac
#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40ac
#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43ac
#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46ac
#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49ac
#define mmREGAMMA_CNTLA_REGION_10_11 0x1aad
#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad
#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1dad
#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40ad
#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43ad
#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46ad
#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49ad
#define mmREGAMMA_CNTLA_REGION_12_13 0x1aae
#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae
#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1dae
#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40ae
#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43ae
#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46ae
#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49ae
#define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf
#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf
#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1daf
#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40af
#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43af
#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46af
#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49af
#define mmREGAMMA_CNTLB_START_CNTL 0x1ab0
#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0
#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1db0
#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40b0
#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43b0
#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46b0
#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49b0
#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1db1
#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1
#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43b1
#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46b1
#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49b1
#define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2
#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2
#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1db2
#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40b2
#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43b2
#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46b2
#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49b2
#define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3
#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3
#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1db3
#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40b3
#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43b3
#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46b3
#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49b3
#define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4
#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4
#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1db4
#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40b4
#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43b4
#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46b4
#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49b4
#define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5
#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5
#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1db5
#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40b5
#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43b5
#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46b5
#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49b5
#define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6
#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6
#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1db6
#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40b6
#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43b6
#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46b6
#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49b6
#define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7
#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7
#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1db7
#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40b7
#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43b7
#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46b7
#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49b7
#define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8
#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8
#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1db8
#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40b8
#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43b8
#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46b8
#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49b8
#define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9
#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9
#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1db9
#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40b9
#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43b9
#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46b9
#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49b9
#define mmREGAMMA_CNTLB_REGION_12_13 0x1aba
#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba
#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1dba
#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40ba
#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43ba
#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46ba
#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49ba
#define mmREGAMMA_CNTLB_REGION_14_15 0x1abb
#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb
#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1dbb
#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40bb
#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43bb
#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46bb
#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49bb
#define mmALPHA_CONTROL 0x1abc
#define mmDCP0_ALPHA_CONTROL 0x1abc
#define mmDCP1_ALPHA_CONTROL 0x1dbc
#define mmDCP2_ALPHA_CONTROL 0x40bc
#define mmDCP3_ALPHA_CONTROL 0x43bc
#define mmDCP4_ALPHA_CONTROL 0x46bc
#define mmDCP5_ALPHA_CONTROL 0x49bc
#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1dbd
#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd
#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x43bd
#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x46bd
#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x49bd
#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1dbe
#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be
#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x43be
#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x46be
#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x49be
#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1dbf
#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf
#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x43bf
#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x46bf
#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x49bf
#define mmDIG_FE_CNTL 0x1c00
#define mmDIG0_DIG_FE_CNTL 0x1c00
#define mmDIG1_DIG_FE_CNTL 0x1f00
#define mmDIG2_DIG_FE_CNTL 0x4200
#define mmDIG3_DIG_FE_CNTL 0x4500
#define mmDIG4_DIG_FE_CNTL 0x4800
#define mmDIG5_DIG_FE_CNTL 0x4b00
#define mmDIG6_DIG_FE_CNTL 0x4e00
#define mmDIG_OUTPUT_CRC_CNTL 0x1c01
#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1c01
#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1f01
#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201
#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501
#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801
#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4b01
#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x4e01
#define mmDIG_OUTPUT_CRC_RESULT 0x1c02
#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1c02
#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1f02
#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202
#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502
#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802
#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4b02
#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x4e02
#define mmDIG_CLOCK_PATTERN 0x1c03
#define mmDIG0_DIG_CLOCK_PATTERN 0x1c03
#define mmDIG1_DIG_CLOCK_PATTERN 0x1f03
#define mmDIG2_DIG_CLOCK_PATTERN 0x4203
#define mmDIG3_DIG_CLOCK_PATTERN 0x4503
#define mmDIG4_DIG_CLOCK_PATTERN 0x4803
#define mmDIG5_DIG_CLOCK_PATTERN 0x4b03
#define mmDIG6_DIG_CLOCK_PATTERN 0x4e03
#define mmDIG_TEST_PATTERN 0x1c04
#define mmDIG0_DIG_TEST_PATTERN 0x1c04
#define mmDIG1_DIG_TEST_PATTERN 0x1f04
#define mmDIG2_DIG_TEST_PATTERN 0x4204
#define mmDIG3_DIG_TEST_PATTERN 0x4504
#define mmDIG4_DIG_TEST_PATTERN 0x4804
#define mmDIG5_DIG_TEST_PATTERN 0x4b04
#define mmDIG6_DIG_TEST_PATTERN 0x4e04
#define mmDIG_RANDOM_PATTERN_SEED 0x1c05
#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1c05
#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1f05
#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205
#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505
#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805
#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4b05
#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x4e05
#define mmDIG_FIFO_STATUS 0x1c0a
#define mmDIG0_DIG_FIFO_STATUS 0x1c0a
#define mmDIG1_DIG_FIFO_STATUS 0x1f0a
#define mmDIG2_DIG_FIFO_STATUS 0x420a
#define mmDIG3_DIG_FIFO_STATUS 0x450a
#define mmDIG4_DIG_FIFO_STATUS 0x480a
#define mmDIG5_DIG_FIFO_STATUS 0x4b0a
#define mmDIG6_DIG_FIFO_STATUS 0x4e0a
#define mmDIG_DISPCLK_SWITCH_CNTL 0x1c08
#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1c08
#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1f08
#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208
#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508
#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808
#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4b08
#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x4e08
#define mmDIG_DISPCLK_SWITCH_STATUS 0x1c09
#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1c09
#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1f09
#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209
#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509
#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809
#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4b09
#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x4e09
#define mmHDMI_CONTROL 0x1c0c
#define mmDIG0_HDMI_CONTROL 0x1c0c
#define mmDIG1_HDMI_CONTROL 0x1f0c
#define mmDIG2_HDMI_CONTROL 0x420c
#define mmDIG3_HDMI_CONTROL 0x450c
#define mmDIG4_HDMI_CONTROL 0x480c
#define mmDIG5_HDMI_CONTROL 0x4b0c
#define mmDIG6_HDMI_CONTROL 0x4e0c
#define mmHDMI_STATUS 0x1c0d
#define mmDIG0_HDMI_STATUS 0x1c0d
#define mmDIG1_HDMI_STATUS 0x1f0d
#define mmDIG2_HDMI_STATUS 0x420d
#define mmDIG3_HDMI_STATUS 0x450d
#define mmDIG4_HDMI_STATUS 0x480d
#define mmDIG5_HDMI_STATUS 0x4b0d
#define mmDIG6_HDMI_STATUS 0x4e0d
#define mmHDMI_AUDIO_PACKET_CONTROL 0x1c0e
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1c0e
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1f0e
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420e
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450e
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480e
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4b0e
#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x4e0e
#define mmHDMI_ACR_PACKET_CONTROL 0x1c0f
#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1c0f
#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1f0f
#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420f
#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450f
#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480f
#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4b0f
#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x4e0f
#define mmHDMI_VBI_PACKET_CONTROL 0x1c10
#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1c10
#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1f10
#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210
#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510
#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810
#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4b10
#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x4e10
#define mmHDMI_INFOFRAME_CONTROL0 0x1c11
#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1c11
#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1f11
#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211
#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511
#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811
#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4b11
#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x4e11
#define mmHDMI_INFOFRAME_CONTROL1 0x1c12
#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1c12
#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1f12
#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212
#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512
#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812
#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4b12
#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x4e12
#define mmHDMI_GENERIC_PACKET_CONTROL0 0x1c13
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1c13
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1f13
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4b13
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x4e13
#define mmAFMT_INTERRUPT_STATUS 0x1c14
#define mmDIG0_AFMT_INTERRUPT_STATUS 0x1c14
#define mmDIG1_AFMT_INTERRUPT_STATUS 0x1f14
#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214
#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514
#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814
#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4b14
#define mmDIG6_AFMT_INTERRUPT_STATUS 0x4e14
#define mmHDMI_GC 0x1c16
#define mmDIG0_HDMI_GC 0x1c16
#define mmDIG1_HDMI_GC 0x1f16
#define mmDIG2_HDMI_GC 0x4216
#define mmDIG3_HDMI_GC 0x4516
#define mmDIG4_HDMI_GC 0x4816
#define mmDIG5_HDMI_GC 0x4b16
#define mmDIG6_HDMI_GC 0x4e16
#define mmAFMT_AUDIO_PACKET_CONTROL2 0x1c17
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1c17
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1f17
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4b17
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x4e17
#define mmAFMT_ISRC1_0 0x1c18
#define mmDIG0_AFMT_ISRC1_0 0x1c18
#define mmDIG1_AFMT_ISRC1_0 0x1f18
#define mmDIG2_AFMT_ISRC1_0 0x4218
#define mmDIG3_AFMT_ISRC1_0 0x4518
#define mmDIG4_AFMT_ISRC1_0 0x4818
#define mmDIG5_AFMT_ISRC1_0 0x4b18
#define mmDIG6_AFMT_ISRC1_0 0x4e18
#define mmAFMT_ISRC1_1 0x1c19
#define mmDIG0_AFMT_ISRC1_1 0x1c19
#define mmDIG1_AFMT_ISRC1_1 0x1f19
#define mmDIG2_AFMT_ISRC1_1 0x4219
#define mmDIG3_AFMT_ISRC1_1 0x4519
#define mmDIG4_AFMT_ISRC1_1 0x4819
#define mmDIG5_AFMT_ISRC1_1 0x4b19
#define mmDIG6_AFMT_ISRC1_1 0x4e19
#define mmAFMT_ISRC1_2 0x1c1a
#define mmDIG0_AFMT_ISRC1_2 0x1c1a
#define mmDIG1_AFMT_ISRC1_2 0x1f1a
#define mmDIG2_AFMT_ISRC1_2 0x421a
#define mmDIG3_AFMT_ISRC1_2 0x451a
#define mmDIG4_AFMT_ISRC1_2 0x481a
#define mmDIG5_AFMT_ISRC1_2 0x4b1a
#define mmDIG6_AFMT_ISRC1_2 0x4e1a
#define mmAFMT_ISRC1_3 0x1c1b
#define mmDIG0_AFMT_ISRC1_3 0x1c1b
#define mmDIG1_AFMT_ISRC1_3 0x1f1b
#define mmDIG2_AFMT_ISRC1_3 0x421b
#define mmDIG3_AFMT_ISRC1_3 0x451b
#define mmDIG4_AFMT_ISRC1_3 0x481b
#define mmDIG5_AFMT_ISRC1_3 0x4b1b
#define mmDIG6_AFMT_ISRC1_3 0x4e1b
#define mmAFMT_ISRC1_4 0x1c1c
#define mmDIG0_AFMT_ISRC1_4 0x1c1c
#define mmDIG1_AFMT_ISRC1_4 0x1f1c
#define mmDIG2_AFMT_ISRC1_4 0x421c
#define mmDIG3_AFMT_ISRC1_4 0x451c
#define mmDIG4_AFMT_ISRC1_4 0x481c
#define mmDIG5_AFMT_ISRC1_4 0x4b1c
#define mmDIG6_AFMT_ISRC1_4 0x4e1c
#define mmAFMT_ISRC2_0 0x1c1d
#define mmDIG0_AFMT_ISRC2_0 0x1c1d
#define mmDIG1_AFMT_ISRC2_0 0x1f1d
#define mmDIG2_AFMT_ISRC2_0 0x421d
#define mmDIG3_AFMT_ISRC2_0 0x451d
#define mmDIG4_AFMT_ISRC2_0 0x481d
#define mmDIG5_AFMT_ISRC2_0 0x4b1d
#define mmDIG6_AFMT_ISRC2_0 0x4e1d
#define mmAFMT_ISRC2_1 0x1c1e
#define mmDIG0_AFMT_ISRC2_1 0x1c1e
#define mmDIG1_AFMT_ISRC2_1 0x1f1e
#define mmDIG2_AFMT_ISRC2_1 0x421e
#define mmDIG3_AFMT_ISRC2_1 0x451e
#define mmDIG4_AFMT_ISRC2_1 0x481e
#define mmDIG5_AFMT_ISRC2_1 0x4b1e
#define mmDIG6_AFMT_ISRC2_1 0x4e1e
#define mmAFMT_ISRC2_2 0x1c1f
#define mmDIG0_AFMT_ISRC2_2 0x1c1f
#define mmDIG1_AFMT_ISRC2_2 0x1f1f
#define mmDIG2_AFMT_ISRC2_2 0x421f
#define mmDIG3_AFMT_ISRC2_2 0x451f
#define mmDIG4_AFMT_ISRC2_2 0x481f
#define mmDIG5_AFMT_ISRC2_2 0x4b1f
#define mmDIG6_AFMT_ISRC2_2 0x4e1f
#define mmAFMT_ISRC2_3 0x1c20
#define mmDIG0_AFMT_ISRC2_3 0x1c20
#define mmDIG1_AFMT_ISRC2_3 0x1f20
#define mmDIG2_AFMT_ISRC2_3 0x4220
#define mmDIG3_AFMT_ISRC2_3 0x4520
#define mmDIG4_AFMT_ISRC2_3 0x4820
#define mmDIG5_AFMT_ISRC2_3 0x4b20
#define mmDIG6_AFMT_ISRC2_3 0x4e20
#define mmAFMT_AVI_INFO0 0x1c21
#define mmDIG0_AFMT_AVI_INFO0 0x1c21
#define mmDIG1_AFMT_AVI_INFO0 0x1f21
#define mmDIG2_AFMT_AVI_INFO0 0x4221
#define mmDIG3_AFMT_AVI_INFO0 0x4521
#define mmDIG4_AFMT_AVI_INFO0 0x4821
#define mmDIG5_AFMT_AVI_INFO0 0x4b21
#define mmDIG6_AFMT_AVI_INFO0 0x4e21
#define mmAFMT_AVI_INFO1 0x1c22
#define mmDIG0_AFMT_AVI_INFO1 0x1c22
#define mmDIG1_AFMT_AVI_INFO1 0x1f22
#define mmDIG2_AFMT_AVI_INFO1 0x4222
#define mmDIG3_AFMT_AVI_INFO1 0x4522
#define mmDIG4_AFMT_AVI_INFO1 0x4822
#define mmDIG5_AFMT_AVI_INFO1 0x4b22
#define mmDIG6_AFMT_AVI_INFO1 0x4e22
#define mmAFMT_AVI_INFO2 0x1c23
#define mmDIG0_AFMT_AVI_INFO2 0x1c23
#define mmDIG1_AFMT_AVI_INFO2 0x1f23
#define mmDIG2_AFMT_AVI_INFO2 0x4223
#define mmDIG3_AFMT_AVI_INFO2 0x4523
#define mmDIG4_AFMT_AVI_INFO2 0x4823
#define mmDIG5_AFMT_AVI_INFO2 0x4b23
#define mmDIG6_AFMT_AVI_INFO2 0x4e23
#define mmAFMT_AVI_INFO3 0x1c24
#define mmDIG0_AFMT_AVI_INFO3 0x1c24
#define mmDIG1_AFMT_AVI_INFO3 0x1f24
#define mmDIG2_AFMT_AVI_INFO3 0x4224
#define mmDIG3_AFMT_AVI_INFO3 0x4524
#define mmDIG4_AFMT_AVI_INFO3 0x4824
#define mmDIG5_AFMT_AVI_INFO3 0x4b24
#define mmDIG6_AFMT_AVI_INFO3 0x4e24
#define mmAFMT_MPEG_INFO0 0x1c25
#define mmDIG0_AFMT_MPEG_INFO0 0x1c25
#define mmDIG1_AFMT_MPEG_INFO0 0x1f25
#define mmDIG2_AFMT_MPEG_INFO0 0x4225
#define mmDIG3_AFMT_MPEG_INFO0 0x4525
#define mmDIG4_AFMT_MPEG_INFO0 0x4825
#define mmDIG5_AFMT_MPEG_INFO0 0x4b25
#define mmDIG6_AFMT_MPEG_INFO0 0x4e25
#define mmAFMT_MPEG_INFO1 0x1c26
#define mmDIG0_AFMT_MPEG_INFO1 0x1c26
#define mmDIG1_AFMT_MPEG_INFO1 0x1f26
#define mmDIG2_AFMT_MPEG_INFO1 0x4226
#define mmDIG3_AFMT_MPEG_INFO1 0x4526
#define mmDIG4_AFMT_MPEG_INFO1 0x4826
#define mmDIG5_AFMT_MPEG_INFO1 0x4b26
#define mmDIG6_AFMT_MPEG_INFO1 0x4e26
#define mmAFMT_GENERIC_HDR 0x1c27
#define mmDIG0_AFMT_GENERIC_HDR 0x1c27
#define mmDIG1_AFMT_GENERIC_HDR 0x1f27
#define mmDIG2_AFMT_GENERIC_HDR 0x4227
#define mmDIG3_AFMT_GENERIC_HDR 0x4527
#define mmDIG4_AFMT_GENERIC_HDR 0x4827
#define mmDIG5_AFMT_GENERIC_HDR 0x4b27
#define mmDIG6_AFMT_GENERIC_HDR 0x4e27
#define mmAFMT_GENERIC_0 0x1c28
#define mmDIG0_AFMT_GENERIC_0 0x1c28
#define mmDIG1_AFMT_GENERIC_0 0x1f28
#define mmDIG2_AFMT_GENERIC_0 0x4228
#define mmDIG3_AFMT_GENERIC_0 0x4528
#define mmDIG4_AFMT_GENERIC_0 0x4828
#define mmDIG5_AFMT_GENERIC_0 0x4b28
#define mmDIG6_AFMT_GENERIC_0 0x4e28
#define mmAFMT_GENERIC_1 0x1c29
#define mmDIG0_AFMT_GENERIC_1 0x1c29
#define mmDIG1_AFMT_GENERIC_1 0x1f29
#define mmDIG2_AFMT_GENERIC_1 0x4229
#define mmDIG3_AFMT_GENERIC_1 0x4529
#define mmDIG4_AFMT_GENERIC_1 0x4829
#define mmDIG5_AFMT_GENERIC_1 0x4b29
#define mmDIG6_AFMT_GENERIC_1 0x4e29
#define mmAFMT_GENERIC_2 0x1c2a
#define mmDIG0_AFMT_GENERIC_2 0x1c2a
#define mmDIG1_AFMT_GENERIC_2 0x1f2a
#define mmDIG2_AFMT_GENERIC_2 0x422a
#define mmDIG3_AFMT_GENERIC_2 0x452a
#define mmDIG4_AFMT_GENERIC_2 0x482a
#define mmDIG5_AFMT_GENERIC_2 0x4b2a
#define mmDIG6_AFMT_GENERIC_2 0x4e2a
#define mmAFMT_GENERIC_3 0x1c2b
#define mmDIG0_AFMT_GENERIC_3 0x1c2b
#define mmDIG1_AFMT_GENERIC_3 0x1f2b
#define mmDIG2_AFMT_GENERIC_3 0x422b
#define mmDIG3_AFMT_GENERIC_3 0x452b
#define mmDIG4_AFMT_GENERIC_3 0x482b
#define mmDIG5_AFMT_GENERIC_3 0x4b2b
#define mmDIG6_AFMT_GENERIC_3 0x4e2b
#define mmAFMT_GENERIC_4 0x1c2c
#define mmDIG0_AFMT_GENERIC_4 0x1c2c
#define mmDIG1_AFMT_GENERIC_4 0x1f2c
#define mmDIG2_AFMT_GENERIC_4 0x422c
#define mmDIG3_AFMT_GENERIC_4 0x452c
#define mmDIG4_AFMT_GENERIC_4 0x482c
#define mmDIG5_AFMT_GENERIC_4 0x4b2c
#define mmDIG6_AFMT_GENERIC_4 0x4e2c
#define mmAFMT_GENERIC_5 0x1c2d
#define mmDIG0_AFMT_GENERIC_5 0x1c2d
#define mmDIG1_AFMT_GENERIC_5 0x1f2d
#define mmDIG2_AFMT_GENERIC_5 0x422d
#define mmDIG3_AFMT_GENERIC_5 0x452d
#define mmDIG4_AFMT_GENERIC_5 0x482d
#define mmDIG5_AFMT_GENERIC_5 0x4b2d
#define mmDIG6_AFMT_GENERIC_5 0x4e2d
#define mmAFMT_GENERIC_6 0x1c2e
#define mmDIG0_AFMT_GENERIC_6 0x1c2e
#define mmDIG1_AFMT_GENERIC_6 0x1f2e
#define mmDIG2_AFMT_GENERIC_6 0x422e
#define mmDIG3_AFMT_GENERIC_6 0x452e
#define mmDIG4_AFMT_GENERIC_6 0x482e
#define mmDIG5_AFMT_GENERIC_6 0x4b2e
#define mmDIG6_AFMT_GENERIC_6 0x4e2e
#define mmAFMT_GENERIC_7 0x1c2f
#define mmDIG0_AFMT_GENERIC_7 0x1c2f
#define mmDIG1_AFMT_GENERIC_7 0x1f2f
#define mmDIG2_AFMT_GENERIC_7 0x422f
#define mmDIG3_AFMT_GENERIC_7 0x452f
#define mmDIG4_AFMT_GENERIC_7 0x482f
#define mmDIG5_AFMT_GENERIC_7 0x4b2f
#define mmDIG6_AFMT_GENERIC_7 0x4e2f
#define mmHDMI_GENERIC_PACKET_CONTROL1 0x1c30
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1c30
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1f30
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4b30
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x4e30
#define mmHDMI_ACR_32_0 0x1c37
#define mmDIG0_HDMI_ACR_32_0 0x1c37
#define mmDIG1_HDMI_ACR_32_0 0x1f37
#define mmDIG2_HDMI_ACR_32_0 0x4237
#define mmDIG3_HDMI_ACR_32_0 0x4537
#define mmDIG4_HDMI_ACR_32_0 0x4837
#define mmDIG5_HDMI_ACR_32_0 0x4b37
#define mmDIG6_HDMI_ACR_32_0 0x4e37
#define mmHDMI_ACR_32_1 0x1c38
#define mmDIG0_HDMI_ACR_32_1 0x1c38
#define mmDIG1_HDMI_ACR_32_1 0x1f38
#define mmDIG2_HDMI_ACR_32_1 0x4238
#define mmDIG3_HDMI_ACR_32_1 0x4538
#define mmDIG4_HDMI_ACR_32_1 0x4838
#define mmDIG5_HDMI_ACR_32_1 0x4b38
#define mmDIG6_HDMI_ACR_32_1 0x4e38
#define mmHDMI_ACR_44_0 0x1c39
#define mmDIG0_HDMI_ACR_44_0 0x1c39
#define mmDIG1_HDMI_ACR_44_0 0x1f39
#define mmDIG2_HDMI_ACR_44_0 0x4239
#define mmDIG3_HDMI_ACR_44_0 0x4539
#define mmDIG4_HDMI_ACR_44_0 0x4839
#define mmDIG5_HDMI_ACR_44_0 0x4b39
#define mmDIG6_HDMI_ACR_44_0 0x4e39
#define mmHDMI_ACR_44_1 0x1c3a
#define mmDIG0_HDMI_ACR_44_1 0x1c3a
#define mmDIG1_HDMI_ACR_44_1 0x1f3a
#define mmDIG2_HDMI_ACR_44_1 0x423a
#define mmDIG3_HDMI_ACR_44_1 0x453a
#define mmDIG4_HDMI_ACR_44_1 0x483a
#define mmDIG5_HDMI_ACR_44_1 0x4b3a
#define mmDIG6_HDMI_ACR_44_1 0x4e3a
#define mmHDMI_ACR_48_0 0x1c3b
#define mmDIG0_HDMI_ACR_48_0 0x1c3b
#define mmDIG1_HDMI_ACR_48_0 0x1f3b
#define mmDIG2_HDMI_ACR_48_0 0x423b
#define mmDIG3_HDMI_ACR_48_0 0x453b
#define mmDIG4_HDMI_ACR_48_0 0x483b
#define mmDIG5_HDMI_ACR_48_0 0x4b3b
#define mmDIG6_HDMI_ACR_48_0 0x4e3b
#define mmHDMI_ACR_48_1 0x1c3c
#define mmDIG0_HDMI_ACR_48_1 0x1c3c
#define mmDIG1_HDMI_ACR_48_1 0x1f3c
#define mmDIG2_HDMI_ACR_48_1 0x423c
#define mmDIG3_HDMI_ACR_48_1 0x453c
#define mmDIG4_HDMI_ACR_48_1 0x483c
#define mmDIG5_HDMI_ACR_48_1 0x4b3c
#define mmDIG6_HDMI_ACR_48_1 0x4e3c
#define mmHDMI_ACR_STATUS_0 0x1c3d
#define mmDIG0_HDMI_ACR_STATUS_0 0x1c3d
#define mmDIG1_HDMI_ACR_STATUS_0 0x1f3d
#define mmDIG2_HDMI_ACR_STATUS_0 0x423d
#define mmDIG3_HDMI_ACR_STATUS_0 0x453d
#define mmDIG4_HDMI_ACR_STATUS_0 0x483d
#define mmDIG5_HDMI_ACR_STATUS_0 0x4b3d
#define mmDIG6_HDMI_ACR_STATUS_0 0x4e3d
#define mmHDMI_ACR_STATUS_1 0x1c3e
#define mmDIG0_HDMI_ACR_STATUS_1 0x1c3e
#define mmDIG1_HDMI_ACR_STATUS_1 0x1f3e
#define mmDIG2_HDMI_ACR_STATUS_1 0x423e
#define mmDIG3_HDMI_ACR_STATUS_1 0x453e
#define mmDIG4_HDMI_ACR_STATUS_1 0x483e
#define mmDIG5_HDMI_ACR_STATUS_1 0x4b3e
#define mmDIG6_HDMI_ACR_STATUS_1 0x4e3e
#define mmAFMT_AUDIO_INFO0 0x1c3f
#define mmDIG0_AFMT_AUDIO_INFO0 0x1c3f
#define mmDIG1_AFMT_AUDIO_INFO0 0x1f3f
#define mmDIG2_AFMT_AUDIO_INFO0 0x423f
#define mmDIG3_AFMT_AUDIO_INFO0 0x453f
#define mmDIG4_AFMT_AUDIO_INFO0 0x483f
#define mmDIG5_AFMT_AUDIO_INFO0 0x4b3f
#define mmDIG6_AFMT_AUDIO_INFO0 0x4e3f
#define mmAFMT_AUDIO_INFO1 0x1c40
#define mmDIG0_AFMT_AUDIO_INFO1 0x1c40
#define mmDIG1_AFMT_AUDIO_INFO1 0x1f40
#define mmDIG2_AFMT_AUDIO_INFO1 0x4240
#define mmDIG3_AFMT_AUDIO_INFO1 0x4540
#define mmDIG4_AFMT_AUDIO_INFO1 0x4840
#define mmDIG5_AFMT_AUDIO_INFO1 0x4b40
#define mmDIG6_AFMT_AUDIO_INFO1 0x4e40
#define mmAFMT_60958_0 0x1c41
#define mmDIG0_AFMT_60958_0 0x1c41
#define mmDIG1_AFMT_60958_0 0x1f41
#define mmDIG2_AFMT_60958_0 0x4241
#define mmDIG3_AFMT_60958_0 0x4541
#define mmDIG4_AFMT_60958_0 0x4841
#define mmDIG5_AFMT_60958_0 0x4b41
#define mmDIG6_AFMT_60958_0 0x4e41
#define mmAFMT_60958_1 0x1c42
#define mmDIG0_AFMT_60958_1 0x1c42
#define mmDIG1_AFMT_60958_1 0x1f42
#define mmDIG2_AFMT_60958_1 0x4242
#define mmDIG3_AFMT_60958_1 0x4542
#define mmDIG4_AFMT_60958_1 0x4842
#define mmDIG5_AFMT_60958_1 0x4b42
#define mmDIG6_AFMT_60958_1 0x4e42
#define mmAFMT_AUDIO_CRC_CONTROL 0x1c43
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1c43
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1f43
#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243
#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543
#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843
#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4b43
#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x4e43
#define mmAFMT_RAMP_CONTROL0 0x1c44
#define mmDIG0_AFMT_RAMP_CONTROL0 0x1c44
#define mmDIG1_AFMT_RAMP_CONTROL0 0x1f44
#define mmDIG2_AFMT_RAMP_CONTROL0 0x4244
#define mmDIG3_AFMT_RAMP_CONTROL0 0x4544
#define mmDIG4_AFMT_RAMP_CONTROL0 0x4844
#define mmDIG5_AFMT_RAMP_CONTROL0 0x4b44
#define mmDIG6_AFMT_RAMP_CONTROL0 0x4e44
#define mmAFMT_RAMP_CONTROL1 0x1c45
#define mmDIG0_AFMT_RAMP_CONTROL1 0x1c45
#define mmDIG1_AFMT_RAMP_CONTROL1 0x1f45
#define mmDIG2_AFMT_RAMP_CONTROL1 0x4245
#define mmDIG3_AFMT_RAMP_CONTROL1 0x4545
#define mmDIG4_AFMT_RAMP_CONTROL1 0x4845
#define mmDIG5_AFMT_RAMP_CONTROL1 0x4b45
#define mmDIG6_AFMT_RAMP_CONTROL1 0x4e45
#define mmAFMT_RAMP_CONTROL2 0x1c46
#define mmDIG0_AFMT_RAMP_CONTROL2 0x1c46
#define mmDIG1_AFMT_RAMP_CONTROL2 0x1f46
#define mmDIG2_AFMT_RAMP_CONTROL2 0x4246
#define mmDIG3_AFMT_RAMP_CONTROL2 0x4546
#define mmDIG4_AFMT_RAMP_CONTROL2 0x4846
#define mmDIG5_AFMT_RAMP_CONTROL2 0x4b46
#define mmDIG6_AFMT_RAMP_CONTROL2 0x4e46
#define mmAFMT_RAMP_CONTROL3 0x1c47
#define mmDIG0_AFMT_RAMP_CONTROL3 0x1c47
#define mmDIG1_AFMT_RAMP_CONTROL3 0x1f47
#define mmDIG2_AFMT_RAMP_CONTROL3 0x4247
#define mmDIG3_AFMT_RAMP_CONTROL3 0x4547
#define mmDIG4_AFMT_RAMP_CONTROL3 0x4847
#define mmDIG5_AFMT_RAMP_CONTROL3 0x4b47
#define mmDIG6_AFMT_RAMP_CONTROL3 0x4e47
#define mmAFMT_60958_2 0x1c48
#define mmDIG0_AFMT_60958_2 0x1c48
#define mmDIG1_AFMT_60958_2 0x1f48
#define mmDIG2_AFMT_60958_2 0x4248
#define mmDIG3_AFMT_60958_2 0x4548
#define mmDIG4_AFMT_60958_2 0x4848
#define mmDIG5_AFMT_60958_2 0x4b48
#define mmDIG6_AFMT_60958_2 0x4e48
#define mmAFMT_AUDIO_CRC_RESULT 0x1c49
#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1c49
#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1f49
#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249
#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549
#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849
#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4b49
#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x4e49
#define mmAFMT_STATUS 0x1c4a
#define mmDIG0_AFMT_STATUS 0x1c4a
#define mmDIG1_AFMT_STATUS 0x1f4a
#define mmDIG2_AFMT_STATUS 0x424a
#define mmDIG3_AFMT_STATUS 0x454a
#define mmDIG4_AFMT_STATUS 0x484a
#define mmDIG5_AFMT_STATUS 0x4b4a
#define mmDIG6_AFMT_STATUS 0x4e4a
#define mmAFMT_AUDIO_PACKET_CONTROL 0x1c4b
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1c4b
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1f4b
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424b
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454b
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484b
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4b4b
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x4e4b
#define mmAFMT_VBI_PACKET_CONTROL 0x1c4c
#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1c4c
#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1f4c
#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424c
#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454c
#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484c
#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4b4c
#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x4e4c
#define mmAFMT_INFOFRAME_CONTROL0 0x1c4d
#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1c4d
#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1f4d
#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424d
#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454d
#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484d
#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4b4d
#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x4e4d
#define mmAFMT_AUDIO_SRC_CONTROL 0x1c4f
#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1c4f
#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1f4f
#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424f
#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454f
#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484f
#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4b4f
#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x4e4f
#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1c52
#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1c52
#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1f52
#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252
#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552
#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852
#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4b52
#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x4e52
#define mmDIG_BE_CNTL 0x1c50
#define mmDIG0_DIG_BE_CNTL 0x1c50
#define mmDIG1_DIG_BE_CNTL 0x1f50
#define mmDIG2_DIG_BE_CNTL 0x4250
#define mmDIG3_DIG_BE_CNTL 0x4550
#define mmDIG4_DIG_BE_CNTL 0x4850
#define mmDIG5_DIG_BE_CNTL 0x4b50
#define mmDIG6_DIG_BE_CNTL 0x4e50
#define mmDIG_BE_EN_CNTL 0x1c51
#define mmDIG0_DIG_BE_EN_CNTL 0x1c51
#define mmDIG1_DIG_BE_EN_CNTL 0x1f51
#define mmDIG2_DIG_BE_EN_CNTL 0x4251
#define mmDIG3_DIG_BE_EN_CNTL 0x4551
#define mmDIG4_DIG_BE_EN_CNTL 0x4851
#define mmDIG5_DIG_BE_EN_CNTL 0x4b51
#define mmDIG6_DIG_BE_EN_CNTL 0x4e51
#define mmTMDS_CNTL 0x1c7c
#define mmDIG0_TMDS_CNTL 0x1c7c
#define mmDIG1_TMDS_CNTL 0x1f7c
#define mmDIG2_TMDS_CNTL 0x427c
#define mmDIG3_TMDS_CNTL 0x457c
#define mmDIG4_TMDS_CNTL 0x487c
#define mmDIG5_TMDS_CNTL 0x4b7c
#define mmDIG6_TMDS_CNTL 0x4e7c
#define mmTMDS_CONTROL_CHAR 0x1c7d
#define mmDIG0_TMDS_CONTROL_CHAR 0x1c7d
#define mmDIG1_TMDS_CONTROL_CHAR 0x1f7d
#define mmDIG2_TMDS_CONTROL_CHAR 0x427d
#define mmDIG3_TMDS_CONTROL_CHAR 0x457d
#define mmDIG4_TMDS_CONTROL_CHAR 0x487d
#define mmDIG5_TMDS_CONTROL_CHAR 0x4b7d
#define mmDIG6_TMDS_CONTROL_CHAR 0x4e7d
#define mmTMDS_CONTROL0_FEEDBACK 0x1c7e
#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1c7e
#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1f7e
#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427e
#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457e
#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487e
#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4b7e
#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x4e7e
#define mmTMDS_STEREOSYNC_CTL_SEL 0x1c7f
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1c7f
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1f7f
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427f
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457f
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487f
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4b7f
#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x4e7f
#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1c80
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1c80
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1f80
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b80
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e80
#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1c81
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1c81
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1f81
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b81
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e81
#define mmTMDS_DEBUG 0x1c82
#define mmDIG0_TMDS_DEBUG 0x1c82
#define mmDIG1_TMDS_DEBUG 0x1f82
#define mmDIG2_TMDS_DEBUG 0x4282
#define mmDIG3_TMDS_DEBUG 0x4582
#define mmDIG4_TMDS_DEBUG 0x4882
#define mmDIG5_TMDS_DEBUG 0x4b82
#define mmDIG6_TMDS_DEBUG 0x4e82
#define mmTMDS_CTL_BITS 0x1c83
#define mmDIG0_TMDS_CTL_BITS 0x1c83
#define mmDIG1_TMDS_CTL_BITS 0x1f83
#define mmDIG2_TMDS_CTL_BITS 0x4283
#define mmDIG3_TMDS_CTL_BITS 0x4583
#define mmDIG4_TMDS_CTL_BITS 0x4883
#define mmDIG5_TMDS_CTL_BITS 0x4b83
#define mmDIG6_TMDS_CTL_BITS 0x4e83
#define mmTMDS_DCBALANCER_CONTROL 0x1c84
#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1c84
#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1f84
#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284
#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584
#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884
#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4b84
#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x4e84
#define mmTMDS_CTL0_1_GEN_CNTL 0x1c86
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1c86
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1f86
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4b86
#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x4e86
#define mmTMDS_CTL2_3_GEN_CNTL 0x1c87
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1c87
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1f87
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4b87
#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x4e87
#define mmLVDS_DATA_CNTL 0x1c8c
#define mmDIG0_LVDS_DATA_CNTL 0x1c8c
#define mmDIG1_LVDS_DATA_CNTL 0x1f8c
#define mmDIG2_LVDS_DATA_CNTL 0x428c
#define mmDIG3_LVDS_DATA_CNTL 0x458c
#define mmDIG4_LVDS_DATA_CNTL 0x488c
#define mmDIG5_LVDS_DATA_CNTL 0x4b8c
#define mmDIG6_LVDS_DATA_CNTL 0x4e8c
#define mmDIG_LANE_ENABLE 0x1c8d
#define mmDIG0_DIG_LANE_ENABLE 0x1c8d
#define mmDIG1_DIG_LANE_ENABLE 0x1f8d
#define mmDIG2_DIG_LANE_ENABLE 0x428d
#define mmDIG3_DIG_LANE_ENABLE 0x458d
#define mmDIG4_DIG_LANE_ENABLE 0x488d
#define mmDIG5_DIG_LANE_ENABLE 0x4b8d
#define mmDIG6_DIG_LANE_ENABLE 0x4e8d
#define mmDOUT_SCRATCH0 0x1844
#define mmDOUT_SCRATCH1 0x1845
#define mmDOUT_SCRATCH2 0x1846
#define mmDOUT_SCRATCH3 0x1847
#define mmDOUT_SCRATCH4 0x1848
#define mmDOUT_SCRATCH5 0x1849
#define mmDOUT_SCRATCH6 0x184a
#define mmDOUT_SCRATCH7 0x184b
#define mmDOUT_DCE_VCE_CONTROL 0x18ff
#define mmDC_HPD1_INT_STATUS 0x1807
#define mmDC_HPD1_INT_CONTROL 0x1808
#define mmDC_HPD1_CONTROL 0x1809
#define mmDC_HPD2_INT_STATUS 0x180a
#define mmDC_HPD2_INT_CONTROL 0x180b
#define mmDC_HPD2_CONTROL 0x180c
#define mmDC_HPD3_INT_STATUS 0x180d
#define mmDC_HPD3_INT_CONTROL 0x180e
#define mmDC_HPD3_CONTROL 0x180f
#define mmDC_HPD4_INT_STATUS 0x1810
#define mmDC_HPD4_INT_CONTROL 0x1811
#define mmDC_HPD4_CONTROL 0x1812
#define mmDC_HPD5_INT_STATUS 0x1813
#define mmDC_HPD5_INT_CONTROL 0x1814
#define mmDC_HPD5_CONTROL 0x1815
#define mmDC_HPD6_INT_STATUS 0x1816
#define mmDC_HPD6_INT_CONTROL 0x1817
#define mmDC_HPD6_CONTROL 0x1818
#define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864
#define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865
#define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866
#define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867
#define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868
#define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869
#define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18bc
#define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18bd
#define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18be
#define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18fc
#define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18fd
#define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18fe
#define mmDC_I2C_CONTROL 0x1819
#define mmDC_I2C_ARBITRATION 0x181a
#define mmDC_I2C_INTERRUPT_CONTROL 0x181b
#define mmDC_I2C_SW_STATUS 0x181c
#define mmDC_I2C_DDC1_HW_STATUS 0x181d
#define mmDC_I2C_DDC2_HW_STATUS 0x181e
#define mmDC_I2C_DDC3_HW_STATUS 0x181f
#define mmDC_I2C_DDC4_HW_STATUS 0x1820
#define mmDC_I2C_DDC5_HW_STATUS 0x1821
#define mmDC_I2C_DDC6_HW_STATUS 0x1822
#define mmDC_I2C_DDC1_SPEED 0x1823
#define mmDC_I2C_DDC1_SETUP 0x1824
#define mmDC_I2C_DDC2_SPEED 0x1825
#define mmDC_I2C_DDC2_SETUP 0x1826
#define mmDC_I2C_DDC3_SPEED 0x1827
#define mmDC_I2C_DDC3_SETUP 0x1828
#define mmDC_I2C_DDC4_SPEED 0x1829
#define mmDC_I2C_DDC4_SETUP 0x182a
#define mmDC_I2C_DDC5_SPEED 0x182b
#define mmDC_I2C_DDC5_SETUP 0x182c
#define mmDC_I2C_DDC6_SPEED 0x182d
#define mmDC_I2C_DDC6_SETUP 0x182e
#define mmDC_I2C_TRANSACTION0 0x182f
#define mmDC_I2C_TRANSACTION1 0x1830
#define mmDC_I2C_TRANSACTION2 0x1831
#define mmDC_I2C_TRANSACTION3 0x1832
#define mmDC_I2C_DATA 0x1833
#define mmGENERIC_I2C_CONTROL 0x1834
#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835
#define mmGENERIC_I2C_STATUS 0x1836
#define mmGENERIC_I2C_SPEED 0x1837
#define mmGENERIC_I2C_SETUP 0x1838
#define mmGENERIC_I2C_TRANSACTION 0x1839
#define mmGENERIC_I2C_DATA 0x183a
#define mmGENERIC_I2C_PIN_SELECTION 0x183b
#define mmGENERIC_I2C_PIN_DEBUG 0x183c
#define mmDISP_INTERRUPT_STATUS 0x183d
#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183e
#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183f
#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840
#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853
#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854
#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x19e0
#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x19e1
#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x19e2
#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x19e3
#define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841
#define mmDISP_TIMER_CONTROL 0x1842
#define mmDC_I2C_DDCVGA_HW_STATUS 0x1855
#define mmDC_I2C_DDCVGA_SPEED 0x1856
#define mmDC_I2C_DDCVGA_SETUP 0x1857
#define mmDC_I2C_EDID_DETECT_CTRL 0x186f
#define mmDISPOUT_STEREOSYNC_SEL 0x18bf
#define mmDOUT_TEST_DEBUG_INDEX 0x184d
#define mmDOUT_TEST_DEBUG_DATA 0x184e
#define ixDP_AUX1_DEBUG_A 0x10
#define ixDP_AUX1_DEBUG_B 0x11
#define ixDP_AUX1_DEBUG_C 0x12
#define ixDP_AUX1_DEBUG_D 0x13
#define ixDP_AUX1_DEBUG_E 0x14
#define ixDP_AUX1_DEBUG_F 0x15
#define ixDP_AUX1_DEBUG_G 0x16
#define ixDP_AUX1_DEBUG_H 0x17
#define ixDP_AUX1_DEBUG_I 0x18
#define ixDP_AUX1_DEBUG_J 0x19
#define ixDP_AUX1_DEBUG_K 0x1a
#define ixDP_AUX1_DEBUG_L 0x1b
#define ixDP_AUX1_DEBUG_M 0x1c
#define ixDP_AUX1_DEBUG_N 0x1d
#define ixDP_AUX1_DEBUG_O 0x1e
#define ixDP_AUX1_DEBUG_P 0x1f
#define ixDP_AUX1_DEBUG_Q 0x90
#define ixDP_AUX2_DEBUG_A 0x20
#define ixDP_AUX2_DEBUG_B 0x21
#define ixDP_AUX2_DEBUG_C 0x22
#define ixDP_AUX2_DEBUG_D 0x23
#define ixDP_AUX2_DEBUG_E 0x24
#define ixDP_AUX2_DEBUG_F 0x25
#define ixDP_AUX2_DEBUG_G 0x26
#define ixDP_AUX2_DEBUG_H 0x27
#define ixDP_AUX2_DEBUG_I 0x28
#define ixDP_AUX2_DEBUG_J 0x29
#define ixDP_AUX2_DEBUG_K 0x2a
#define ixDP_AUX2_DEBUG_L 0x2b
#define ixDP_AUX2_DEBUG_M 0x2c
#define ixDP_AUX2_DEBUG_N 0x2d
#define ixDP_AUX2_DEBUG_O 0x2e
#define ixDP_AUX2_DEBUG_P 0x2f
#define ixDP_AUX2_DEBUG_Q 0x91
#define ixDP_AUX3_DEBUG_A 0x30
#define ixDP_AUX3_DEBUG_B 0x31
#define ixDP_AUX3_DEBUG_C 0x32
#define ixDP_AUX3_DEBUG_D 0x33
#define ixDP_AUX3_DEBUG_E 0x34
#define ixDP_AUX3_DEBUG_F 0x35
#define ixDP_AUX3_DEBUG_G 0x36
#define ixDP_AUX3_DEBUG_H 0x37
#define ixDP_AUX3_DEBUG_I 0x38
#define ixDP_AUX3_DEBUG_J 0x39
#define ixDP_AUX3_DEBUG_K 0x3a
#define ixDP_AUX3_DEBUG_L 0x3b
#define ixDP_AUX3_DEBUG_M 0x3c
#define ixDP_AUX3_DEBUG_N 0x3d
#define ixDP_AUX3_DEBUG_O 0x3e
#define ixDP_AUX3_DEBUG_P 0x3f
#define ixDP_AUX3_DEBUG_Q 0x92
#define ixDP_AUX4_DEBUG_A 0x40
#define ixDP_AUX4_DEBUG_B 0x41
#define ixDP_AUX4_DEBUG_C 0x42
#define ixDP_AUX4_DEBUG_D 0x43
#define ixDP_AUX4_DEBUG_E 0x44
#define ixDP_AUX4_DEBUG_F 0x45
#define ixDP_AUX4_DEBUG_G 0x46
#define ixDP_AUX4_DEBUG_H 0x47
#define ixDP_AUX4_DEBUG_I 0x48
#define ixDP_AUX4_DEBUG_J 0x49
#define ixDP_AUX4_DEBUG_K 0x4a
#define ixDP_AUX4_DEBUG_L 0x4b
#define ixDP_AUX4_DEBUG_M 0x4c
#define ixDP_AUX4_DEBUG_N 0x4d
#define ixDP_AUX4_DEBUG_O 0x4e
#define ixDP_AUX4_DEBUG_P 0x4f
#define ixDP_AUX4_DEBUG_Q 0x93
#define ixDP_AUX5_DEBUG_A 0x70
#define ixDP_AUX5_DEBUG_B 0x71
#define ixDP_AUX5_DEBUG_C 0x72
#define ixDP_AUX5_DEBUG_D 0x73
#define ixDP_AUX5_DEBUG_E 0x74
#define ixDP_AUX5_DEBUG_F 0x75
#define ixDP_AUX5_DEBUG_G 0x76
#define ixDP_AUX5_DEBUG_H 0x77
#define ixDP_AUX5_DEBUG_I 0x78
#define ixDP_AUX5_DEBUG_J 0x79
#define ixDP_AUX5_DEBUG_K 0x7a
#define ixDP_AUX5_DEBUG_L 0x7b
#define ixDP_AUX5_DEBUG_M 0x7c
#define ixDP_AUX5_DEBUG_N 0x7d
#define ixDP_AUX5_DEBUG_O 0x7f
#define ixDP_AUX5_DEBUG_P 0x94
#define ixDP_AUX5_DEBUG_Q 0x95
#define ixDP_AUX6_DEBUG_A 0x80
#define ixDP_AUX6_DEBUG_B 0x81
#define ixDP_AUX6_DEBUG_C 0x82
#define ixDP_AUX6_DEBUG_D 0x83
#define ixDP_AUX6_DEBUG_E 0x84
#define ixDP_AUX6_DEBUG_F 0x85
#define ixDP_AUX6_DEBUG_G 0x86
#define ixDP_AUX6_DEBUG_H 0x87
#define ixDP_AUX6_DEBUG_I 0x88
#define ixDP_AUX6_DEBUG_J 0x89
#define ixDP_AUX6_DEBUG_K 0x8a
#define ixDP_AUX6_DEBUG_L 0x8b
#define ixDP_AUX6_DEBUG_M 0x8c
#define ixDP_AUX6_DEBUG_N 0x8d
#define ixDP_AUX6_DEBUG_O 0x8f
#define ixDP_AUX6_DEBUG_P 0x96
#define ixDP_AUX6_DEBUG_Q 0x97
#define mmDMCU_CTRL 0x1600
#define mmDMCU_STATUS 0x1601
#define mmDMCU_PC_START_ADDR 0x1602
#define mmDMCU_FW_START_ADDR 0x1603
#define mmDMCU_FW_END_ADDR 0x1604
#define mmDMCU_FW_ISR_START_ADDR 0x1605
#define mmDMCU_FW_CS_HI 0x1606
#define mmDMCU_FW_CS_LO 0x1607
#define mmDMCU_RAM_ACCESS_CTRL 0x1608
#define mmDMCU_ERAM_WR_CTRL 0x1609
#define mmDMCU_ERAM_WR_DATA 0x160a
#define mmDMCU_ERAM_RD_CTRL 0x160b
#define mmDMCU_ERAM_RD_DATA 0x160c
#define mmDMCU_IRAM_WR_CTRL 0x160d
#define mmDMCU_IRAM_WR_DATA 0x160e
#define mmDMCU_IRAM_RD_CTRL 0x160f
#define mmDMCU_IRAM_RD_DATA 0x1610
#define mmDMCU_EVENT_TRIGGER 0x1611
#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613
#define mmDMCU_INTERRUPT_STATUS 0x1614
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617
#define mmDC_DMCU_SCRATCH 0x1618
#define mmDMCU_INT_CNT 0x1619
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a
#define mmDMCU_UC_CLK_GATING_CNTL 0x161b
#define mmMASTER_COMM_DATA_REG1 0x161c
#define mmMASTER_COMM_DATA_REG2 0x161d
#define mmMASTER_COMM_DATA_REG3 0x161e
#define mmMASTER_COMM_CMD_REG 0x161f
#define mmMASTER_COMM_CNTL_REG 0x1620
#define mmSLAVE_COMM_DATA_REG1 0x1621
#define mmSLAVE_COMM_DATA_REG2 0x1622
#define mmSLAVE_COMM_DATA_REG3 0x1623
#define mmSLAVE_COMM_CMD_REG 0x1624
#define mmSLAVE_COMM_CNTL_REG 0x1625
#define mmDMCU_TEST_DEBUG_INDEX 0x1626
#define mmDMCU_TEST_DEBUG_DATA 0x1627
#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1750
#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1751
#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1752
#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1753
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1754
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1755
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1756
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1757
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1758
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1759
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x175a
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x175b
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x175c
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x175d
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x175e
#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x175f
#define mmDP_LINK_CNTL 0x1cc0
#define mmDP0_DP_LINK_CNTL 0x1cc0
#define mmDP1_DP_LINK_CNTL 0x1fc0
#define mmDP2_DP_LINK_CNTL 0x42c0
#define mmDP3_DP_LINK_CNTL 0x45c0
#define mmDP4_DP_LINK_CNTL 0x48c0
#define mmDP5_DP_LINK_CNTL 0x4bc0
#define mmDP6_DP_LINK_CNTL 0x4ec0
#define mmDP_PIXEL_FORMAT 0x1cc1
#define mmDP0_DP_PIXEL_FORMAT 0x1cc1
#define mmDP1_DP_PIXEL_FORMAT 0x1fc1
#define mmDP2_DP_PIXEL_FORMAT 0x42c1
#define mmDP3_DP_PIXEL_FORMAT 0x45c1
#define mmDP4_DP_PIXEL_FORMAT 0x48c1
#define mmDP5_DP_PIXEL_FORMAT 0x4bc1
#define mmDP6_DP_PIXEL_FORMAT 0x4ec1
#define mmDP_MSA_COLORIMETRY 0x1cda
#define mmDP0_DP_MSA_COLORIMETRY 0x1cda
#define mmDP1_DP_MSA_COLORIMETRY 0x1fda
#define mmDP2_DP_MSA_COLORIMETRY 0x42da
#define mmDP3_DP_MSA_COLORIMETRY 0x45da
#define mmDP4_DP_MSA_COLORIMETRY 0x48da
#define mmDP5_DP_MSA_COLORIMETRY 0x4bda
#define mmDP6_DP_MSA_COLORIMETRY 0x4eda
#define mmDP_CONFIG 0x1cc2
#define mmDP0_DP_CONFIG 0x1cc2
#define mmDP1_DP_CONFIG 0x1fc2
#define mmDP2_DP_CONFIG 0x42c2
#define mmDP3_DP_CONFIG 0x45c2
#define mmDP4_DP_CONFIG 0x48c2
#define mmDP5_DP_CONFIG 0x4bc2
#define mmDP6_DP_CONFIG 0x4ec2
#define mmDP_VID_STREAM_CNTL 0x1cc3
#define mmDP0_DP_VID_STREAM_CNTL 0x1cc3
#define mmDP1_DP_VID_STREAM_CNTL 0x1fc3
#define mmDP2_DP_VID_STREAM_CNTL 0x42c3
#define mmDP3_DP_VID_STREAM_CNTL 0x45c3
#define mmDP4_DP_VID_STREAM_CNTL 0x48c3
#define mmDP5_DP_VID_STREAM_CNTL 0x4bc3
#define mmDP6_DP_VID_STREAM_CNTL 0x4ec3
#define mmDP_STEER_FIFO 0x1cc4
#define mmDP0_DP_STEER_FIFO 0x1cc4
#define mmDP1_DP_STEER_FIFO 0x1fc4
#define mmDP2_DP_STEER_FIFO 0x42c4
#define mmDP3_DP_STEER_FIFO 0x45c4
#define mmDP4_DP_STEER_FIFO 0x48c4
#define mmDP5_DP_STEER_FIFO 0x4bc4
#define mmDP6_DP_STEER_FIFO 0x4ec4
#define mmDP_MSA_MISC 0x1cc5
#define mmDP0_DP_MSA_MISC 0x1cc5
#define mmDP1_DP_MSA_MISC 0x1fc5
#define mmDP2_DP_MSA_MISC 0x42c5
#define mmDP3_DP_MSA_MISC 0x45c5
#define mmDP4_DP_MSA_MISC 0x48c5
#define mmDP5_DP_MSA_MISC 0x4bc5
#define mmDP6_DP_MSA_MISC 0x4ec5
#define mmDP_VID_TIMING 0x1cc9
#define mmDP0_DP_VID_TIMING 0x1cc9
#define mmDP1_DP_VID_TIMING 0x1fc9
#define mmDP2_DP_VID_TIMING 0x42c9
#define mmDP3_DP_VID_TIMING 0x45c9
#define mmDP4_DP_VID_TIMING 0x48c9
#define mmDP5_DP_VID_TIMING 0x4bc9
#define mmDP6_DP_VID_TIMING 0x4ec9
#define mmDP_VID_N 0x1cca
#define mmDP0_DP_VID_N 0x1cca
#define mmDP1_DP_VID_N 0x1fca
#define mmDP2_DP_VID_N 0x42ca
#define mmDP3_DP_VID_N 0x45ca
#define mmDP4_DP_VID_N 0x48ca
#define mmDP5_DP_VID_N 0x4bca
#define mmDP6_DP_VID_N 0x4eca
#define mmDP_VID_M 0x1ccb
#define mmDP0_DP_VID_M 0x1ccb
#define mmDP1_DP_VID_M 0x1fcb
#define mmDP2_DP_VID_M 0x42cb
#define mmDP3_DP_VID_M 0x45cb
#define mmDP4_DP_VID_M 0x48cb
#define mmDP5_DP_VID_M 0x4bcb
#define mmDP6_DP_VID_M 0x4ecb
#define mmDP_LINK_FRAMING_CNTL 0x1ccc
#define mmDP0_DP_LINK_FRAMING_CNTL 0x1ccc
#define mmDP1_DP_LINK_FRAMING_CNTL 0x1fcc
#define mmDP2_DP_LINK_FRAMING_CNTL 0x42cc
#define mmDP3_DP_LINK_FRAMING_CNTL 0x45cc
#define mmDP4_DP_LINK_FRAMING_CNTL 0x48cc
#define mmDP5_DP_LINK_FRAMING_CNTL 0x4bcc
#define mmDP6_DP_LINK_FRAMING_CNTL 0x4ecc
#define mmDP_HBR2_EYE_PATTERN 0x1cc8
#define mmDP0_DP_HBR2_EYE_PATTERN 0x1cc8
#define mmDP1_DP_HBR2_EYE_PATTERN 0x1fc8
#define mmDP2_DP_HBR2_EYE_PATTERN 0x42c8
#define mmDP3_DP_HBR2_EYE_PATTERN 0x45c8
#define mmDP4_DP_HBR2_EYE_PATTERN 0x48c8
#define mmDP5_DP_HBR2_EYE_PATTERN 0x4bc8
#define mmDP6_DP_HBR2_EYE_PATTERN 0x4ec8
#define mmDP_VID_MSA_VBID 0x1ccd
#define mmDP0_DP_VID_MSA_VBID 0x1ccd
#define mmDP1_DP_VID_MSA_VBID 0x1fcd
#define mmDP2_DP_VID_MSA_VBID 0x42cd
#define mmDP3_DP_VID_MSA_VBID 0x45cd
#define mmDP4_DP_VID_MSA_VBID 0x48cd
#define mmDP5_DP_VID_MSA_VBID 0x4bcd
#define mmDP6_DP_VID_MSA_VBID 0x4ecd
#define mmDP_VID_INTERRUPT_CNTL 0x1ccf
#define mmDP0_DP_VID_INTERRUPT_CNTL 0x1ccf
#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1fcf
#define mmDP2_DP_VID_INTERRUPT_CNTL 0x42cf
#define mmDP3_DP_VID_INTERRUPT_CNTL 0x45cf
#define mmDP4_DP_VID_INTERRUPT_CNTL 0x48cf
#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4bcf
#define mmDP6_DP_VID_INTERRUPT_CNTL 0x4ecf
#define mmDP_DPHY_CNTL 0x1cd0
#define mmDP0_DP_DPHY_CNTL 0x1cd0
#define mmDP1_DP_DPHY_CNTL 0x1fd0
#define mmDP2_DP_DPHY_CNTL 0x42d0
#define mmDP3_DP_DPHY_CNTL 0x45d0
#define mmDP4_DP_DPHY_CNTL 0x48d0
#define mmDP5_DP_DPHY_CNTL 0x4bd0
#define mmDP6_DP_DPHY_CNTL 0x4ed0
#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1cd1
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1cd1
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1fd1
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42d1
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45d1
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48d1
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4bd1
#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x4ed1
#define mmDP_DPHY_SYM0 0x1cd2
#define mmDP0_DP_DPHY_SYM0 0x1cd2
#define mmDP1_DP_DPHY_SYM0 0x1fd2
#define mmDP2_DP_DPHY_SYM0 0x42d2
#define mmDP3_DP_DPHY_SYM0 0x45d2
#define mmDP4_DP_DPHY_SYM0 0x48d2
#define mmDP5_DP_DPHY_SYM0 0x4bd2
#define mmDP6_DP_DPHY_SYM0 0x4ed2
#define mmDP_DPHY_SYM1 0x1ce0
#define mmDP0_DP_DPHY_SYM1 0x1ce0
#define mmDP1_DP_DPHY_SYM1 0x1fe0
#define mmDP2_DP_DPHY_SYM1 0x42e0
#define mmDP3_DP_DPHY_SYM1 0x45e0
#define mmDP4_DP_DPHY_SYM1 0x48e0
#define mmDP5_DP_DPHY_SYM1 0x4be0
#define mmDP6_DP_DPHY_SYM1 0x4ee0
#define mmDP_DPHY_SYM2 0x1cdf
#define mmDP0_DP_DPHY_SYM2 0x1cdf
#define mmDP1_DP_DPHY_SYM2 0x1fdf
#define mmDP2_DP_DPHY_SYM2 0x42df
#define mmDP3_DP_DPHY_SYM2 0x45df
#define mmDP4_DP_DPHY_SYM2 0x48df
#define mmDP5_DP_DPHY_SYM2 0x4bdf
#define mmDP6_DP_DPHY_SYM2 0x4edf
#define mmDP_DPHY_8B10B_CNTL 0x1cd3
#define mmDP0_DP_DPHY_8B10B_CNTL 0x1cd3
#define mmDP1_DP_DPHY_8B10B_CNTL 0x1fd3
#define mmDP2_DP_DPHY_8B10B_CNTL 0x42d3
#define mmDP3_DP_DPHY_8B10B_CNTL 0x45d3
#define mmDP4_DP_DPHY_8B10B_CNTL 0x48d3
#define mmDP5_DP_DPHY_8B10B_CNTL 0x4bd3
#define mmDP6_DP_DPHY_8B10B_CNTL 0x4ed3
#define mmDP_DPHY_PRBS_CNTL 0x1cd4
#define mmDP0_DP_DPHY_PRBS_CNTL 0x1cd4
#define mmDP1_DP_DPHY_PRBS_CNTL 0x1fd4
#define mmDP2_DP_DPHY_PRBS_CNTL 0x42d4
#define mmDP3_DP_DPHY_PRBS_CNTL 0x45d4
#define mmDP4_DP_DPHY_PRBS_CNTL 0x48d4
#define mmDP5_DP_DPHY_PRBS_CNTL 0x4bd4
#define mmDP6_DP_DPHY_PRBS_CNTL 0x4ed4
#define mmDP_DPHY_SCRAM_CNTL 0x1cd5
#define mmDP0_DP_DPHY_SCRAM_CNTL 0x1cd5
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x1fd5
#define mmDP2_DP_DPHY_SCRAM_CNTL 0x42d5
#define mmDP3_DP_DPHY_SCRAM_CNTL 0x45d5
#define mmDP4_DP_DPHY_SCRAM_CNTL 0x48d5
#define mmDP5_DP_DPHY_SCRAM_CNTL 0x4bd5
#define mmDP6_DP_DPHY_SCRAM_CNTL 0x4ed5
#define mmDP_DPHY_CRC_EN 0x1cd6
#define mmDP0_DP_DPHY_CRC_EN 0x1cd6
#define mmDP1_DP_DPHY_CRC_EN 0x1fd6
#define mmDP2_DP_DPHY_CRC_EN 0x42d6
#define mmDP3_DP_DPHY_CRC_EN 0x45d6
#define mmDP4_DP_DPHY_CRC_EN 0x48d6
#define mmDP5_DP_DPHY_CRC_EN 0x4bd6
#define mmDP6_DP_DPHY_CRC_EN 0x4ed6
#define mmDP_DPHY_CRC_CNTL 0x1cd7
#define mmDP0_DP_DPHY_CRC_CNTL 0x1cd7
#define mmDP1_DP_DPHY_CRC_CNTL 0x1fd7
#define mmDP2_DP_DPHY_CRC_CNTL 0x42d7
#define mmDP3_DP_DPHY_CRC_CNTL 0x45d7
#define mmDP4_DP_DPHY_CRC_CNTL 0x48d7
#define mmDP5_DP_DPHY_CRC_CNTL 0x4bd7
#define mmDP6_DP_DPHY_CRC_CNTL 0x4ed7
#define mmDP_DPHY_CRC_RESULT 0x1cd8
#define mmDP0_DP_DPHY_CRC_RESULT 0x1cd8
#define mmDP1_DP_DPHY_CRC_RESULT 0x1fd8
#define mmDP2_DP_DPHY_CRC_RESULT 0x42d8
#define mmDP3_DP_DPHY_CRC_RESULT 0x45d8
#define mmDP4_DP_DPHY_CRC_RESULT 0x48d8
#define mmDP5_DP_DPHY_CRC_RESULT 0x4bd8
#define mmDP6_DP_DPHY_CRC_RESULT 0x4ed8
#define mmDP_DPHY_CRC_MST_CNTL 0x1cc6
#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1cc6
#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1fc6
#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42c6
#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45c6
#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48c6
#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4bc6
#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x4ec6
#define mmDP_DPHY_CRC_MST_STATUS 0x1cc7
#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1cc7
#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1fc7
#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42c7
#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45c7
#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48c7
#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4bc7
#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x4ec7
#define mmDP_DPHY_FAST_TRAINING 0x1cce
#define mmDP0_DP_DPHY_FAST_TRAINING 0x1cce
#define mmDP1_DP_DPHY_FAST_TRAINING 0x1fce
#define mmDP2_DP_DPHY_FAST_TRAINING 0x42ce
#define mmDP3_DP_DPHY_FAST_TRAINING 0x45ce
#define mmDP4_DP_DPHY_FAST_TRAINING 0x48ce
#define mmDP5_DP_DPHY_FAST_TRAINING 0x4bce
#define mmDP6_DP_DPHY_FAST_TRAINING 0x4ece
#define mmDP_DPHY_FAST_TRAINING_STATUS 0x1ce9
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1ce9
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1fe9
#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42e9
#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45e9
#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48e9
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4be9
#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x4ee9
#define mmDP_MSA_V_TIMING_OVERRIDE1 0x1cea
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1cea
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1fea
#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42ea
#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45ea
#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48ea
#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4bea
#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x4eea
#define mmDP_MSA_V_TIMING_OVERRIDE2 0x1ceb
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1ceb
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1feb
#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42eb
#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45eb
#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48eb
#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4beb
#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x4eeb
#define mmDP_SEC_CNTL 0x1ca0
#define mmDP0_DP_SEC_CNTL 0x1ca0
#define mmDP1_DP_SEC_CNTL 0x1fa0
#define mmDP2_DP_SEC_CNTL 0x42a0
#define mmDP3_DP_SEC_CNTL 0x45a0
#define mmDP4_DP_SEC_CNTL 0x48a0
#define mmDP5_DP_SEC_CNTL 0x4ba0
#define mmDP6_DP_SEC_CNTL 0x4ea0
#define mmDP_SEC_CNTL1 0x1cab
#define mmDP0_DP_SEC_CNTL1 0x1cab
#define mmDP1_DP_SEC_CNTL1 0x1fab
#define mmDP2_DP_SEC_CNTL1 0x42ab
#define mmDP3_DP_SEC_CNTL1 0x45ab
#define mmDP4_DP_SEC_CNTL1 0x48ab
#define mmDP5_DP_SEC_CNTL1 0x4bab
#define mmDP6_DP_SEC_CNTL1 0x4eab
#define mmDP_SEC_FRAMING1 0x1ca1
#define mmDP0_DP_SEC_FRAMING1 0x1ca1
#define mmDP1_DP_SEC_FRAMING1 0x1fa1
#define mmDP2_DP_SEC_FRAMING1 0x42a1
#define mmDP3_DP_SEC_FRAMING1 0x45a1
#define mmDP4_DP_SEC_FRAMING1 0x48a1
#define mmDP5_DP_SEC_FRAMING1 0x4ba1
#define mmDP6_DP_SEC_FRAMING1 0x4ea1
#define mmDP_SEC_FRAMING2 0x1ca2
#define mmDP0_DP_SEC_FRAMING2 0x1ca2
#define mmDP1_DP_SEC_FRAMING2 0x1fa2
#define mmDP2_DP_SEC_FRAMING2 0x42a2
#define mmDP3_DP_SEC_FRAMING2 0x45a2
#define mmDP4_DP_SEC_FRAMING2 0x48a2
#define mmDP5_DP_SEC_FRAMING2 0x4ba2
#define mmDP6_DP_SEC_FRAMING2 0x4ea2
#define mmDP_SEC_FRAMING3 0x1ca3
#define mmDP0_DP_SEC_FRAMING3 0x1ca3
#define mmDP1_DP_SEC_FRAMING3 0x1fa3
#define mmDP2_DP_SEC_FRAMING3 0x42a3
#define mmDP3_DP_SEC_FRAMING3 0x45a3
#define mmDP4_DP_SEC_FRAMING3 0x48a3
#define mmDP5_DP_SEC_FRAMING3 0x4ba3
#define mmDP6_DP_SEC_FRAMING3 0x4ea3
#define mmDP_SEC_FRAMING4 0x1ca4
#define mmDP0_DP_SEC_FRAMING4 0x1ca4
#define mmDP1_DP_SEC_FRAMING4 0x1fa4
#define mmDP2_DP_SEC_FRAMING4 0x42a4
#define mmDP3_DP_SEC_FRAMING4 0x45a4
#define mmDP4_DP_SEC_FRAMING4 0x48a4
#define mmDP5_DP_SEC_FRAMING4 0x4ba4
#define mmDP6_DP_SEC_FRAMING4 0x4ea4
#define mmDP_SEC_AUD_N 0x1ca5
#define mmDP0_DP_SEC_AUD_N 0x1ca5
#define mmDP1_DP_SEC_AUD_N 0x1fa5
#define mmDP2_DP_SEC_AUD_N 0x42a5
#define mmDP3_DP_SEC_AUD_N 0x45a5
#define mmDP4_DP_SEC_AUD_N 0x48a5
#define mmDP5_DP_SEC_AUD_N 0x4ba5
#define mmDP6_DP_SEC_AUD_N 0x4ea5
#define mmDP_SEC_AUD_N_READBACK 0x1ca6
#define mmDP0_DP_SEC_AUD_N_READBACK 0x1ca6
#define mmDP1_DP_SEC_AUD_N_READBACK 0x1fa6
#define mmDP2_DP_SEC_AUD_N_READBACK 0x42a6
#define mmDP3_DP_SEC_AUD_N_READBACK 0x45a6
#define mmDP4_DP_SEC_AUD_N_READBACK 0x48a6
#define mmDP5_DP_SEC_AUD_N_READBACK 0x4ba6
#define mmDP6_DP_SEC_AUD_N_READBACK 0x4ea6
#define mmDP_SEC_AUD_M 0x1ca7
#define mmDP0_DP_SEC_AUD_M 0x1ca7
#define mmDP1_DP_SEC_AUD_M 0x1fa7
#define mmDP2_DP_SEC_AUD_M 0x42a7
#define mmDP3_DP_SEC_AUD_M 0x45a7
#define mmDP4_DP_SEC_AUD_M 0x48a7
#define mmDP5_DP_SEC_AUD_M 0x4ba7
#define mmDP6_DP_SEC_AUD_M 0x4ea7
#define mmDP_SEC_AUD_M_READBACK 0x1ca8
#define mmDP0_DP_SEC_AUD_M_READBACK 0x1ca8
#define mmDP1_DP_SEC_AUD_M_READBACK 0x1fa8
#define mmDP2_DP_SEC_AUD_M_READBACK 0x42a8
#define mmDP3_DP_SEC_AUD_M_READBACK 0x45a8
#define mmDP4_DP_SEC_AUD_M_READBACK 0x48a8
#define mmDP5_DP_SEC_AUD_M_READBACK 0x4ba8
#define mmDP6_DP_SEC_AUD_M_READBACK 0x4ea8
#define mmDP_SEC_TIMESTAMP 0x1ca9
#define mmDP0_DP_SEC_TIMESTAMP 0x1ca9
#define mmDP1_DP_SEC_TIMESTAMP 0x1fa9
#define mmDP2_DP_SEC_TIMESTAMP 0x42a9
#define mmDP3_DP_SEC_TIMESTAMP 0x45a9
#define mmDP4_DP_SEC_TIMESTAMP 0x48a9
#define mmDP5_DP_SEC_TIMESTAMP 0x4ba9
#define mmDP6_DP_SEC_TIMESTAMP 0x4ea9
#define mmDP_SEC_PACKET_CNTL 0x1caa
#define mmDP0_DP_SEC_PACKET_CNTL 0x1caa
#define mmDP1_DP_SEC_PACKET_CNTL 0x1faa
#define mmDP2_DP_SEC_PACKET_CNTL 0x42aa
#define mmDP3_DP_SEC_PACKET_CNTL 0x45aa
#define mmDP4_DP_SEC_PACKET_CNTL 0x48aa
#define mmDP5_DP_SEC_PACKET_CNTL 0x4baa
#define mmDP6_DP_SEC_PACKET_CNTL 0x4eaa
#define mmDP_MSE_RATE_CNTL 0x1ce1
#define mmDP0_DP_MSE_RATE_CNTL 0x1ce1
#define mmDP1_DP_MSE_RATE_CNTL 0x1fe1
#define mmDP2_DP_MSE_RATE_CNTL 0x42e1
#define mmDP3_DP_MSE_RATE_CNTL 0x45e1
#define mmDP4_DP_MSE_RATE_CNTL 0x48e1
#define mmDP5_DP_MSE_RATE_CNTL 0x4be1
#define mmDP6_DP_MSE_RATE_CNTL 0x4ee1
#define mmDP_MSE_RATE_UPDATE 0x1ce3
#define mmDP0_DP_MSE_RATE_UPDATE 0x1ce3
#define mmDP1_DP_MSE_RATE_UPDATE 0x1fe3
#define mmDP2_DP_MSE_RATE_UPDATE 0x42e3
#define mmDP3_DP_MSE_RATE_UPDATE 0x45e3
#define mmDP4_DP_MSE_RATE_UPDATE 0x48e3
#define mmDP5_DP_MSE_RATE_UPDATE 0x4be3
#define mmDP6_DP_MSE_RATE_UPDATE 0x4ee3
#define mmDP_MSE_SAT0 0x1ce4
#define mmDP0_DP_MSE_SAT0 0x1ce4
#define mmDP1_DP_MSE_SAT0 0x1fe4
#define mmDP2_DP_MSE_SAT0 0x42e4
#define mmDP3_DP_MSE_SAT0 0x45e4
#define mmDP4_DP_MSE_SAT0 0x48e4
#define mmDP5_DP_MSE_SAT0 0x4be4
#define mmDP6_DP_MSE_SAT0 0x4ee4
#define mmDP_MSE_SAT1 0x1ce5
#define mmDP0_DP_MSE_SAT1 0x1ce5
#define mmDP1_DP_MSE_SAT1 0x1fe5
#define mmDP2_DP_MSE_SAT1 0x42e5
#define mmDP3_DP_MSE_SAT1 0x45e5
#define mmDP4_DP_MSE_SAT1 0x48e5
#define mmDP5_DP_MSE_SAT1 0x4be5
#define mmDP6_DP_MSE_SAT1 0x4ee5
#define mmDP_MSE_SAT2 0x1ce6
#define mmDP0_DP_MSE_SAT2 0x1ce6
#define mmDP1_DP_MSE_SAT2 0x1fe6
#define mmDP2_DP_MSE_SAT2 0x42e6
#define mmDP3_DP_MSE_SAT2 0x45e6
#define mmDP4_DP_MSE_SAT2 0x48e6
#define mmDP5_DP_MSE_SAT2 0x4be6
#define mmDP6_DP_MSE_SAT2 0x4ee6
#define mmDP_MSE_SAT_UPDATE 0x1ce7
#define mmDP0_DP_MSE_SAT_UPDATE 0x1ce7
#define mmDP1_DP_MSE_SAT_UPDATE 0x1fe7
#define mmDP2_DP_MSE_SAT_UPDATE 0x42e7
#define mmDP3_DP_MSE_SAT_UPDATE 0x45e7
#define mmDP4_DP_MSE_SAT_UPDATE 0x48e7
#define mmDP5_DP_MSE_SAT_UPDATE 0x4be7
#define mmDP6_DP_MSE_SAT_UPDATE 0x4ee7
#define mmDP_MSE_LINK_TIMING 0x1ce8
#define mmDP0_DP_MSE_LINK_TIMING 0x1ce8
#define mmDP1_DP_MSE_LINK_TIMING 0x1fe8
#define mmDP2_DP_MSE_LINK_TIMING 0x42e8
#define mmDP3_DP_MSE_LINK_TIMING 0x45e8
#define mmDP4_DP_MSE_LINK_TIMING 0x48e8
#define mmDP5_DP_MSE_LINK_TIMING 0x4be8
#define mmDP6_DP_MSE_LINK_TIMING 0x4ee8
#define mmDP_MSE_MISC_CNTL 0x1cdb
#define mmDP0_DP_MSE_MISC_CNTL 0x1cdb
#define mmDP1_DP_MSE_MISC_CNTL 0x1fdb
#define mmDP2_DP_MSE_MISC_CNTL 0x42db
#define mmDP3_DP_MSE_MISC_CNTL 0x45db
#define mmDP4_DP_MSE_MISC_CNTL 0x48db
#define mmDP5_DP_MSE_MISC_CNTL 0x4bdb
#define mmDP6_DP_MSE_MISC_CNTL 0x4edb
#define mmDP_TEST_DEBUG_INDEX 0x1cfc
#define mmDP0_DP_TEST_DEBUG_INDEX 0x1cfc
#define mmDP1_DP_TEST_DEBUG_INDEX 0x1ffc
#define mmDP2_DP_TEST_DEBUG_INDEX 0x42fc
#define mmDP3_DP_TEST_DEBUG_INDEX 0x45fc
#define mmDP4_DP_TEST_DEBUG_INDEX 0x48fc
#define mmDP5_DP_TEST_DEBUG_INDEX 0x4bfc
#define mmDP6_DP_TEST_DEBUG_INDEX 0x4efc
#define mmDP_TEST_DEBUG_DATA 0x1cfd
#define mmDP0_DP_TEST_DEBUG_DATA 0x1cfd
#define mmDP1_DP_TEST_DEBUG_DATA 0x1ffd
#define mmDP2_DP_TEST_DEBUG_DATA 0x42fd
#define mmDP3_DP_TEST_DEBUG_DATA 0x45fd
#define mmDP4_DP_TEST_DEBUG_DATA 0x48fd
#define mmDP5_DP_TEST_DEBUG_DATA 0x4bfd
#define mmDP6_DP_TEST_DEBUG_DATA 0x4efd
#define mmAUX_CONTROL 0x1880
#define mmDP_AUX0_AUX_CONTROL 0x1880
#define mmDP_AUX1_AUX_CONTROL 0x1894
#define mmDP_AUX2_AUX_CONTROL 0x18a8
#define mmDP_AUX3_AUX_CONTROL 0x18c0
#define mmDP_AUX4_AUX_CONTROL 0x18d4
#define mmDP_AUX5_AUX_CONTROL 0x18e8
#define mmAUX_SW_CONTROL 0x1881
#define mmDP_AUX0_AUX_SW_CONTROL 0x1881
#define mmDP_AUX1_AUX_SW_CONTROL 0x1895
#define mmDP_AUX2_AUX_SW_CONTROL 0x18a9
#define mmDP_AUX3_AUX_SW_CONTROL 0x18c1
#define mmDP_AUX4_AUX_SW_CONTROL 0x18d5
#define mmDP_AUX5_AUX_SW_CONTROL 0x18e9
#define mmAUX_ARB_CONTROL 0x1882
#define mmDP_AUX0_AUX_ARB_CONTROL 0x1882
#define mmDP_AUX1_AUX_ARB_CONTROL 0x1896
#define mmDP_AUX2_AUX_ARB_CONTROL 0x18aa
#define mmDP_AUX3_AUX_ARB_CONTROL 0x18c2
#define mmDP_AUX4_AUX_ARB_CONTROL 0x18d6
#define mmDP_AUX5_AUX_ARB_CONTROL 0x18ea
#define mmAUX_INTERRUPT_CONTROL 0x1883
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18ab
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18c3
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18d7
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18eb
#define mmAUX_SW_STATUS 0x1884
#define mmDP_AUX0_AUX_SW_STATUS 0x1884
#define mmDP_AUX1_AUX_SW_STATUS 0x1898
#define mmDP_AUX2_AUX_SW_STATUS 0x18ac
#define mmDP_AUX3_AUX_SW_STATUS 0x18c4
#define mmDP_AUX4_AUX_SW_STATUS 0x18d8
#define mmDP_AUX5_AUX_SW_STATUS 0x18ec
#define mmAUX_LS_STATUS 0x1885
#define mmDP_AUX0_AUX_LS_STATUS 0x1885
#define mmDP_AUX1_AUX_LS_STATUS 0x1899
#define mmDP_AUX2_AUX_LS_STATUS 0x18ad
#define mmDP_AUX3_AUX_LS_STATUS 0x18c5
#define mmDP_AUX4_AUX_LS_STATUS 0x18d9
#define mmDP_AUX5_AUX_LS_STATUS 0x18ed
#define mmAUX_SW_DATA 0x1886
#define mmDP_AUX0_AUX_SW_DATA 0x1886
#define mmDP_AUX1_AUX_SW_DATA 0x189a
#define mmDP_AUX2_AUX_SW_DATA 0x18ae
#define mmDP_AUX3_AUX_SW_DATA 0x18c6
#define mmDP_AUX4_AUX_SW_DATA 0x18da
#define mmDP_AUX5_AUX_SW_DATA 0x18ee
#define mmAUX_LS_DATA 0x1887
#define mmDP_AUX0_AUX_LS_DATA 0x1887
#define mmDP_AUX1_AUX_LS_DATA 0x189b
#define mmDP_AUX2_AUX_LS_DATA 0x18af
#define mmDP_AUX3_AUX_LS_DATA 0x18c7
#define mmDP_AUX4_AUX_LS_DATA 0x18db
#define mmDP_AUX5_AUX_LS_DATA 0x18ef
#define mmAUX_DPHY_TX_REF_CONTROL 0x1888
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189c
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18b0
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18c8
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18dc
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18f0
#define mmAUX_DPHY_TX_CONTROL 0x1889
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189d
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18b1
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18c9
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18dd
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18f1
#define mmAUX_DPHY_RX_CONTROL0 0x188a
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188a
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189e
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18b2
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18ca
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18de
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18f2
#define mmAUX_DPHY_RX_CONTROL1 0x188b
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188b
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189f
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18b3
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18cb
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18df
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18f3
#define mmAUX_DPHY_TX_STATUS 0x188c
#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188c
#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18a0
#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18b4
#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18cc
#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18e0
#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18f4
#define mmAUX_DPHY_RX_STATUS 0x188d
#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188d
#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18a1
#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18b5
#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18cd
#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18e1
#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18f5
#define mmAUX_GTC_SYNC_CONTROL 0x188e
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188e
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18a2
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18b6
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18ce
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18e2
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18f6
#define mmAUX_GTC_SYNC_ERROR_CONTROL 0x188f
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x188f
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x18a3
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x18b7
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x18cf
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x18e3
#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x18f7
#define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x1890
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1890
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18a4
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18b8
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18d0
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18e4
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18f8
#define mmAUX_GTC_SYNC_STATUS 0x1891
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1891
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x18a5
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x18b9
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x18d1
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x18e5
#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x18f9
#define mmAUX_GTC_SYNC_DATA 0x1892
#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1892
#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18a6
#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18ba
#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18d2
#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18e6
#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18fa
#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893
#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893
#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18a7
#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18bb
#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18d3
#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18e7
#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18fb
#define mmDVO_ENABLE 0x1858
#define mmDVO_SOURCE_SELECT 0x1859
#define mmDVO_OUTPUT 0x185a
#define mmDVO_CONTROL 0x185b
#define mmDVO_CRC_EN 0x185c
#define mmDVO_CRC2_SIG_MASK 0x185d
#define mmDVO_CRC2_SIG_RESULT 0x185e
#define mmDVO_FIFO_ERROR_STATUS 0x185f
#define mmFBC_CNTL 0x16d0
#define mmFBC_IDLE_MASK 0x16d1
#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16d2
#define mmFBC_START_STOP_DELAY 0x16d3
#define mmFBC_COMP_CNTL 0x16d4
#define mmFBC_COMP_MODE 0x16d5
#define mmFBC_DEBUG0 0x16d6
#define mmFBC_DEBUG1 0x16d7
#define mmFBC_DEBUG2 0x16d8
#define mmFBC_IND_LUT0 0x16d9
#define mmFBC_IND_LUT1 0x16da
#define mmFBC_IND_LUT2 0x16db
#define mmFBC_IND_LUT3 0x16dc
#define mmFBC_IND_LUT4 0x16dd
#define mmFBC_IND_LUT5 0x16de
#define mmFBC_IND_LUT6 0x16df
#define mmFBC_IND_LUT7 0x16e0
#define mmFBC_IND_LUT8 0x16e1
#define mmFBC_IND_LUT9 0x16e2
#define mmFBC_IND_LUT10 0x16e3
#define mmFBC_IND_LUT11 0x16e4
#define mmFBC_IND_LUT12 0x16e5
#define mmFBC_IND_LUT13 0x16e6
#define mmFBC_IND_LUT14 0x16e7
#define mmFBC_IND_LUT15 0x16e8
#define mmFBC_CSM_REGION_OFFSET_01 0x16e9
#define mmFBC_CSM_REGION_OFFSET_23 0x16ea
#define mmFBC_CLIENT_REGION_MASK 0x16eb
#define mmFBC_DEBUG_COMP 0x16ec
#define mmFBC_DEBUG_CSR 0x16ed
#define mmFBC_DEBUG_CSR_RDATA 0x16ee
#define mmFBC_DEBUG_CSR_WDATA 0x16ef
#define mmFBC_DEBUG_CSR_RDATA_HI 0x16f6
#define mmFBC_DEBUG_CSR_WDATA_HI 0x16f7
#define mmFBC_MISC 0x16f0
#define mmFBC_STATUS 0x16f1
#define mmFBC_TEST_DEBUG_INDEX 0x16f4
#define mmFBC_TEST_DEBUG_DATA 0x16f5
#define mmFMT_CLAMP_COMPONENT_R 0x1be8
#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8
#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1ee8
#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x41e8
#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x44e8
#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x47e8
#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x4ae8
#define mmFMT_CLAMP_COMPONENT_G 0x1be9
#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9
#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1ee9
#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x41e9
#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x44e9
#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x47e9
#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x4ae9
#define mmFMT_CLAMP_COMPONENT_B 0x1bea
#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea
#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1eea
#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x41ea
#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x44ea
#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x47ea
#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x4aea
#define mmFMT_DYNAMIC_EXP_CNTL 0x1bed
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1eed
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ed
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ed
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ed
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4aed
#define mmFMT_CONTROL 0x1bee
#define mmFMT0_FMT_CONTROL 0x1bee
#define mmFMT1_FMT_CONTROL 0x1eee
#define mmFMT2_FMT_CONTROL 0x41ee
#define mmFMT3_FMT_CONTROL 0x44ee
#define mmFMT4_FMT_CONTROL 0x47ee
#define mmFMT5_FMT_CONTROL 0x4aee
#define mmFMT_FORCE_OUTPUT_CNTL 0x1bef
#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef
#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1eef
#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41ef
#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44ef
#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47ef
#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4aef
#define mmFMT_FORCE_DATA_0_1 0x1bf0
#define mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0
#define mmFMT1_FMT_FORCE_DATA_0_1 0x1ef0
#define mmFMT2_FMT_FORCE_DATA_0_1 0x41f0
#define mmFMT3_FMT_FORCE_DATA_0_1 0x44f0
#define mmFMT4_FMT_FORCE_DATA_0_1 0x47f0
#define mmFMT5_FMT_FORCE_DATA_0_1 0x4af0
#define mmFMT_FORCE_DATA_2_3 0x1bf1
#define mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1
#define mmFMT1_FMT_FORCE_DATA_2_3 0x1ef1
#define mmFMT2_FMT_FORCE_DATA_2_3 0x41f1
#define mmFMT3_FMT_FORCE_DATA_2_3 0x44f1
#define mmFMT4_FMT_FORCE_DATA_2_3 0x47f1
#define mmFMT5_FMT_FORCE_DATA_2_3 0x4af1
#define mmFMT_BIT_DEPTH_CONTROL 0x1bf2
#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2
#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1ef2
#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41f2
#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44f2
#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47f2
#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4af2
#define mmFMT_DITHER_RAND_R_SEED 0x1bf3
#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3
#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1ef3
#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41f3
#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44f3
#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47f3
#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4af3
#define mmFMT_DITHER_RAND_G_SEED 0x1bf4
#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4
#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1ef4
#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41f4
#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44f4
#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47f4
#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4af4
#define mmFMT_DITHER_RAND_B_SEED 0x1bf5
#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5
#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1ef5
#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41f5
#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44f5
#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47f5
#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4af5
#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ef6
#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6
#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44f6
#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47f6
#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4af6
#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ef7
#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7
#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44f7
#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47f7
#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4af7
#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ef8
#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8
#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44f8
#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47f8
#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4af8
#define mmFMT_CLAMP_CNTL 0x1bf9
#define mmFMT0_FMT_CLAMP_CNTL 0x1bf9
#define mmFMT1_FMT_CLAMP_CNTL 0x1ef9
#define mmFMT2_FMT_CLAMP_CNTL 0x41f9
#define mmFMT3_FMT_CLAMP_CNTL 0x44f9
#define mmFMT4_FMT_CLAMP_CNTL 0x47f9
#define mmFMT5_FMT_CLAMP_CNTL 0x4af9
#define mmFMT_CRC_CNTL 0x1bfa
#define mmFMT0_FMT_CRC_CNTL 0x1bfa
#define mmFMT1_FMT_CRC_CNTL 0x1efa
#define mmFMT2_FMT_CRC_CNTL 0x41fa
#define mmFMT3_FMT_CRC_CNTL 0x44fa
#define mmFMT4_FMT_CRC_CNTL 0x47fa
#define mmFMT5_FMT_CRC_CNTL 0x4afa
#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1efb
#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb
#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44fb
#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47fb
#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4afb
#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1efc
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44fc
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47fc
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4afc
#define mmFMT_CRC_SIG_RED_GREEN 0x1bfd
#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd
#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1efd
#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41fd
#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44fd
#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47fd
#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4afd
#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe
#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1efe
#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41fe
#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44fe
#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47fe
#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4afe
#define mmFMT_DEBUG_CNTL 0x1bff
#define mmFMT0_FMT_DEBUG_CNTL 0x1bff
#define mmFMT1_FMT_DEBUG_CNTL 0x1eff
#define mmFMT2_FMT_DEBUG_CNTL 0x41ff
#define mmFMT3_FMT_DEBUG_CNTL 0x44ff
#define mmFMT4_FMT_DEBUG_CNTL 0x47ff
#define mmFMT5_FMT_DEBUG_CNTL 0x4aff
#define mmFMT_TEST_DEBUG_INDEX 0x1beb
#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb
#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1eeb
#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41eb
#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44eb
#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47eb
#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4aeb
#define mmFMT_TEST_DEBUG_DATA 0x1bec
#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec
#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1eec
#define mmFMT2_FMT_TEST_DEBUG_DATA 0x41ec
#define mmFMT3_FMT_TEST_DEBUG_DATA 0x44ec
#define mmFMT4_FMT_TEST_DEBUG_DATA 0x47ec
#define mmFMT5_FMT_TEST_DEBUG_DATA 0x4aec
#define ixFMT_DEBUG0 0x1
#define ixFMT_DEBUG1 0x2
#define ixFMT_DEBUG2 0x3
#define ixFMT_DEBUG_ID 0x0
#define mmLB_DATA_FORMAT 0x1ac0
#define mmLB0_LB_DATA_FORMAT 0x1ac0
#define mmLB1_LB_DATA_FORMAT 0x1dc0
#define mmLB2_LB_DATA_FORMAT 0x40c0
#define mmLB3_LB_DATA_FORMAT 0x43c0
#define mmLB4_LB_DATA_FORMAT 0x46c0
#define mmLB5_LB_DATA_FORMAT 0x49c0
#define mmLB_MEMORY_CTRL 0x1ac1
#define mmLB0_LB_MEMORY_CTRL 0x1ac1
#define mmLB1_LB_MEMORY_CTRL 0x1dc1
#define mmLB2_LB_MEMORY_CTRL 0x40c1
#define mmLB3_LB_MEMORY_CTRL 0x43c1
#define mmLB4_LB_MEMORY_CTRL 0x46c1
#define mmLB5_LB_MEMORY_CTRL 0x49c1
#define mmLB_MEMORY_SIZE_STATUS 0x1ac2
#define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2
#define mmLB1_LB_MEMORY_SIZE_STATUS 0x1dc2
#define mmLB2_LB_MEMORY_SIZE_STATUS 0x40c2
#define mmLB3_LB_MEMORY_SIZE_STATUS 0x43c2
#define mmLB4_LB_MEMORY_SIZE_STATUS 0x46c2
#define mmLB5_LB_MEMORY_SIZE_STATUS 0x49c2
#define mmLB_DESKTOP_HEIGHT 0x1ac3
#define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3
#define mmLB1_LB_DESKTOP_HEIGHT 0x1dc3
#define mmLB2_LB_DESKTOP_HEIGHT 0x40c3
#define mmLB3_LB_DESKTOP_HEIGHT 0x43c3
#define mmLB4_LB_DESKTOP_HEIGHT 0x46c3
#define mmLB5_LB_DESKTOP_HEIGHT 0x49c3
#define mmLB_VLINE_START_END 0x1ac4
#define mmLB0_LB_VLINE_START_END 0x1ac4
#define mmLB1_LB_VLINE_START_END 0x1dc4
#define mmLB2_LB_VLINE_START_END 0x40c4
#define mmLB3_LB_VLINE_START_END 0x43c4
#define mmLB4_LB_VLINE_START_END 0x46c4
#define mmLB5_LB_VLINE_START_END 0x49c4
#define mmLB_VLINE2_START_END 0x1ac5
#define mmLB0_LB_VLINE2_START_END 0x1ac5
#define mmLB1_LB_VLINE2_START_END 0x1dc5
#define mmLB2_LB_VLINE2_START_END 0x40c5
#define mmLB3_LB_VLINE2_START_END 0x43c5
#define mmLB4_LB_VLINE2_START_END 0x46c5
#define mmLB5_LB_VLINE2_START_END 0x49c5
#define mmLB_V_COUNTER 0x1ac6
#define mmLB0_LB_V_COUNTER 0x1ac6
#define mmLB1_LB_V_COUNTER 0x1dc6
#define mmLB2_LB_V_COUNTER 0x40c6
#define mmLB3_LB_V_COUNTER 0x43c6
#define mmLB4_LB_V_COUNTER 0x46c6
#define mmLB5_LB_V_COUNTER 0x49c6
#define mmLB_SNAPSHOT_V_COUNTER 0x1ac7
#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7
#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1dc7
#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x40c7
#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x43c7
#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x46c7
#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x49c7
#define mmLB_INTERRUPT_MASK 0x1ac8
#define mmLB0_LB_INTERRUPT_MASK 0x1ac8
#define mmLB1_LB_INTERRUPT_MASK 0x1dc8
#define mmLB2_LB_INTERRUPT_MASK 0x40c8
#define mmLB3_LB_INTERRUPT_MASK 0x43c8
#define mmLB4_LB_INTERRUPT_MASK 0x46c8
#define mmLB5_LB_INTERRUPT_MASK 0x49c8
#define mmLB_VLINE_STATUS 0x1ac9
#define mmLB0_LB_VLINE_STATUS 0x1ac9
#define mmLB1_LB_VLINE_STATUS 0x1dc9
#define mmLB2_LB_VLINE_STATUS 0x40c9
#define mmLB3_LB_VLINE_STATUS 0x43c9
#define mmLB4_LB_VLINE_STATUS 0x46c9
#define mmLB5_LB_VLINE_STATUS 0x49c9
#define mmLB_VLINE2_STATUS 0x1aca
#define mmLB0_LB_VLINE2_STATUS 0x1aca
#define mmLB1_LB_VLINE2_STATUS 0x1dca
#define mmLB2_LB_VLINE2_STATUS 0x40ca
#define mmLB3_LB_VLINE2_STATUS 0x43ca
#define mmLB4_LB_VLINE2_STATUS 0x46ca
#define mmLB5_LB_VLINE2_STATUS 0x49ca
#define mmLB_VBLANK_STATUS 0x1acb
#define mmLB0_LB_VBLANK_STATUS 0x1acb
#define mmLB1_LB_VBLANK_STATUS 0x1dcb
#define mmLB2_LB_VBLANK_STATUS 0x40cb
#define mmLB3_LB_VBLANK_STATUS 0x43cb
#define mmLB4_LB_VBLANK_STATUS 0x46cb
#define mmLB5_LB_VBLANK_STATUS 0x49cb
#define mmLB_SYNC_RESET_SEL 0x1acc
#define mmLB0_LB_SYNC_RESET_SEL 0x1acc
#define mmLB1_LB_SYNC_RESET_SEL 0x1dcc
#define mmLB2_LB_SYNC_RESET_SEL 0x40cc
#define mmLB3_LB_SYNC_RESET_SEL 0x43cc
#define mmLB4_LB_SYNC_RESET_SEL 0x46cc
#define mmLB5_LB_SYNC_RESET_SEL 0x49cc
#define mmLB_BLACK_KEYER_R_CR 0x1acd
#define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd
#define mmLB1_LB_BLACK_KEYER_R_CR 0x1dcd
#define mmLB2_LB_BLACK_KEYER_R_CR 0x40cd
#define mmLB3_LB_BLACK_KEYER_R_CR 0x43cd
#define mmLB4_LB_BLACK_KEYER_R_CR 0x46cd
#define mmLB5_LB_BLACK_KEYER_R_CR 0x49cd
#define mmLB_BLACK_KEYER_G_Y 0x1ace
#define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace
#define mmLB1_LB_BLACK_KEYER_G_Y 0x1dce
#define mmLB2_LB_BLACK_KEYER_G_Y 0x40ce
#define mmLB3_LB_BLACK_KEYER_G_Y 0x43ce
#define mmLB4_LB_BLACK_KEYER_G_Y 0x46ce
#define mmLB5_LB_BLACK_KEYER_G_Y 0x49ce
#define mmLB_BLACK_KEYER_B_CB 0x1acf
#define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf
#define mmLB1_LB_BLACK_KEYER_B_CB 0x1dcf
#define mmLB2_LB_BLACK_KEYER_B_CB 0x40cf
#define mmLB3_LB_BLACK_KEYER_B_CB 0x43cf
#define mmLB4_LB_BLACK_KEYER_B_CB 0x46cf
#define mmLB5_LB_BLACK_KEYER_B_CB 0x49cf
#define mmLB_KEYER_COLOR_CTRL 0x1ad0
#define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0
#define mmLB1_LB_KEYER_COLOR_CTRL 0x1dd0
#define mmLB2_LB_KEYER_COLOR_CTRL 0x40d0
#define mmLB3_LB_KEYER_COLOR_CTRL 0x43d0
#define mmLB4_LB_KEYER_COLOR_CTRL 0x46d0
#define mmLB5_LB_KEYER_COLOR_CTRL 0x49d0
#define mmLB_KEYER_COLOR_R_CR 0x1ad1
#define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1
#define mmLB1_LB_KEYER_COLOR_R_CR 0x1dd1
#define mmLB2_LB_KEYER_COLOR_R_CR 0x40d1
#define mmLB3_LB_KEYER_COLOR_R_CR 0x43d1
#define mmLB4_LB_KEYER_COLOR_R_CR 0x46d1
#define mmLB5_LB_KEYER_COLOR_R_CR 0x49d1
#define mmLB_KEYER_COLOR_G_Y 0x1ad2
#define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2
#define mmLB1_LB_KEYER_COLOR_G_Y 0x1dd2
#define mmLB2_LB_KEYER_COLOR_G_Y 0x40d2
#define mmLB3_LB_KEYER_COLOR_G_Y 0x43d2
#define mmLB4_LB_KEYER_COLOR_G_Y 0x46d2
#define mmLB5_LB_KEYER_COLOR_G_Y 0x49d2
#define mmLB_KEYER_COLOR_B_CB 0x1ad3
#define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3
#define mmLB1_LB_KEYER_COLOR_B_CB 0x1dd3
#define mmLB2_LB_KEYER_COLOR_B_CB 0x40d3
#define mmLB3_LB_KEYER_COLOR_B_CB 0x43d3
#define mmLB4_LB_KEYER_COLOR_B_CB 0x46d3
#define mmLB5_LB_KEYER_COLOR_B_CB 0x49d3
#define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4
#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4
#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1dd4
#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x40d4
#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x43d4
#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x46d4
#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x49d4
#define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5
#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5
#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1dd5
#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x40d5
#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x43d5
#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x46d5
#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x49d5
#define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6
#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6
#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1dd6
#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x40d6
#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x43d6
#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x46d6
#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x49d6
#define mmLB_BUFFER_LEVEL_STATUS 0x1ad7
#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7
#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1dd7
#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x40d7
#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x43d7
#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x46d7
#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x49d7
#define mmLB_BUFFER_URGENCY_CTRL 0x1ad8
#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8
#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1dd8
#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x40d8
#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x43d8
#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x46d8
#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x49d8
#define mmLB_BUFFER_URGENCY_STATUS 0x1ad9
#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9
#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1dd9
#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x40d9
#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x43d9
#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x46d9
#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x49d9
#define mmLB_BUFFER_STATUS 0x1ada
#define mmLB0_LB_BUFFER_STATUS 0x1ada
#define mmLB1_LB_BUFFER_STATUS 0x1dda
#define mmLB2_LB_BUFFER_STATUS 0x40da
#define mmLB3_LB_BUFFER_STATUS 0x43da
#define mmLB4_LB_BUFFER_STATUS 0x46da
#define mmLB5_LB_BUFFER_STATUS 0x49da
#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc
#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc
#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1ddc
#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc
#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43dc
#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46dc
#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49dc
#define mmMVP_AFR_FLIP_MODE 0x1ae0
#define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0
#define mmLB1_MVP_AFR_FLIP_MODE 0x1de0
#define mmLB2_MVP_AFR_FLIP_MODE 0x40e0
#define mmLB3_MVP_AFR_FLIP_MODE 0x43e0
#define mmLB4_MVP_AFR_FLIP_MODE 0x46e0
#define mmLB5_MVP_AFR_FLIP_MODE 0x49e0
#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1
#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1
#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1de1
#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40e1
#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43e1
#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46e1
#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49e1
#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2
#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2
#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1de2
#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40e2
#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43e2
#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46e2
#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49e2
#define mmDC_MVP_LB_CONTROL 0x1ae3
#define mmLB0_DC_MVP_LB_CONTROL 0x1ae3
#define mmLB1_DC_MVP_LB_CONTROL 0x1de3
#define mmLB2_DC_MVP_LB_CONTROL 0x40e3
#define mmLB3_DC_MVP_LB_CONTROL 0x43e3
#define mmLB4_DC_MVP_LB_CONTROL 0x46e3
#define mmLB5_DC_MVP_LB_CONTROL 0x49e3
#define mmLB_DEBUG 0x1ae4
#define mmLB0_LB_DEBUG 0x1ae4
#define mmLB1_LB_DEBUG 0x1de4
#define mmLB2_LB_DEBUG 0x40e4
#define mmLB3_LB_DEBUG 0x43e4
#define mmLB4_LB_DEBUG 0x46e4
#define mmLB5_LB_DEBUG 0x49e4
#define mmLB_DEBUG2 0x1ae5
#define mmLB0_LB_DEBUG2 0x1ae5
#define mmLB1_LB_DEBUG2 0x1de5
#define mmLB2_LB_DEBUG2 0x40e5
#define mmLB3_LB_DEBUG2 0x43e5
#define mmLB4_LB_DEBUG2 0x46e5
#define mmLB5_LB_DEBUG2 0x49e5
#define mmLB_DEBUG3 0x1ae6
#define mmLB0_LB_DEBUG3 0x1ae6
#define mmLB1_LB_DEBUG3 0x1de6
#define mmLB2_LB_DEBUG3 0x40e6
#define mmLB3_LB_DEBUG3 0x43e6
#define mmLB4_LB_DEBUG3 0x46e6
#define mmLB5_LB_DEBUG3 0x49e6
#define mmLB_TEST_DEBUG_INDEX 0x1afe
#define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe
#define mmLB1_LB_TEST_DEBUG_INDEX 0x1dfe
#define mmLB2_LB_TEST_DEBUG_INDEX 0x40fe
#define mmLB3_LB_TEST_DEBUG_INDEX 0x43fe
#define mmLB4_LB_TEST_DEBUG_INDEX 0x46fe
#define mmLB5_LB_TEST_DEBUG_INDEX 0x49fe
#define mmLB_TEST_DEBUG_DATA 0x1aff
#define mmLB0_LB_TEST_DEBUG_DATA 0x1aff
#define mmLB1_LB_TEST_DEBUG_DATA 0x1dff
#define mmLB2_LB_TEST_DEBUG_DATA 0x40ff
#define mmLB3_LB_TEST_DEBUG_DATA 0x43ff
#define mmLB4_LB_TEST_DEBUG_DATA 0x46ff
#define mmLB5_LB_TEST_DEBUG_DATA 0x49ff
#define mmMVP_CONTROL1 0x1680
#define mmMVP_CONTROL2 0x1681
#define mmMVP_FIFO_CONTROL 0x1682
#define mmMVP_FIFO_STATUS 0x1683
#define mmMVP_SLAVE_STATUS 0x1684
#define mmMVP_INBAND_CNTL_CAP 0x1685
#define mmMVP_BLACK_KEYER 0x1686
#define mmMVP_CRC_CNTL 0x1687
#define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688
#define mmMVP_CRC_RESULT_RED 0x1689
#define mmMVP_CONTROL3 0x168a
#define mmMVP_RECEIVE_CNT_CNTL1 0x168b
#define mmMVP_RECEIVE_CNT_CNTL2 0x168c
#define mmMVP_DEBUG 0x168f
#define mmMVP_TEST_DEBUG_INDEX 0x168d
#define mmMVP_TEST_DEBUG_DATA 0x168e
#define ixMVP_DEBUG_12 0xc
#define ixMVP_DEBUG_13 0xd
#define ixMVP_DEBUG_14 0xe
#define ixMVP_DEBUG_15 0xf
#define ixMVP_DEBUG_16 0x10
#define ixMVP_DEBUG_17 0x11
#define mmSCL_COEF_RAM_SELECT 0x1b40
#define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40
#define mmSCL1_SCL_COEF_RAM_SELECT 0x1e40
#define mmSCL2_SCL_COEF_RAM_SELECT 0x4140
#define mmSCL3_SCL_COEF_RAM_SELECT 0x4440
#define mmSCL4_SCL_COEF_RAM_SELECT 0x4740
#define mmSCL5_SCL_COEF_RAM_SELECT 0x4a40
#define mmSCL_COEF_RAM_TAP_DATA 0x1b41
#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41
#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1e41
#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141
#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441
#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741
#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4a41
#define mmSCL_MODE 0x1b42
#define mmSCL0_SCL_MODE 0x1b42
#define mmSCL1_SCL_MODE 0x1e42
#define mmSCL2_SCL_MODE 0x4142
#define mmSCL3_SCL_MODE 0x4442
#define mmSCL4_SCL_MODE 0x4742
#define mmSCL5_SCL_MODE 0x4a42
#define mmSCL_TAP_CONTROL 0x1b43
#define mmSCL0_SCL_TAP_CONTROL 0x1b43
#define mmSCL1_SCL_TAP_CONTROL 0x1e43
#define mmSCL2_SCL_TAP_CONTROL 0x4143
#define mmSCL3_SCL_TAP_CONTROL 0x4443
#define mmSCL4_SCL_TAP_CONTROL 0x4743
#define mmSCL5_SCL_TAP_CONTROL 0x4a43
#define mmSCL_CONTROL 0x1b44
#define mmSCL0_SCL_CONTROL 0x1b44
#define mmSCL1_SCL_CONTROL 0x1e44
#define mmSCL2_SCL_CONTROL 0x4144
#define mmSCL3_SCL_CONTROL 0x4444
#define mmSCL4_SCL_CONTROL 0x4744
#define mmSCL5_SCL_CONTROL 0x4a44
#define mmSCL_BYPASS_CONTROL 0x1b45
#define mmSCL0_SCL_BYPASS_CONTROL 0x1b45
#define mmSCL1_SCL_BYPASS_CONTROL 0x1e45
#define mmSCL2_SCL_BYPASS_CONTROL 0x4145
#define mmSCL3_SCL_BYPASS_CONTROL 0x4445
#define mmSCL4_SCL_BYPASS_CONTROL 0x4745
#define mmSCL5_SCL_BYPASS_CONTROL 0x4a45
#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46
#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46
#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1e46
#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146
#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446
#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746
#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4a46
#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47
#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47
#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1e47
#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147
#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447
#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747
#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4a47
#define mmSCL_HORZ_FILTER_CONTROL 0x1b48
#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48
#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1e48
#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x4148
#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4448
#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4748
#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4a48
#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49
#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49
#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1e49
#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x4149
#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4449
#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4749
#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4a49
#define mmSCL_HORZ_FILTER_INIT 0x1b4a
#define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a
#define mmSCL1_SCL_HORZ_FILTER_INIT 0x1e4a
#define mmSCL2_SCL_HORZ_FILTER_INIT 0x414a
#define mmSCL3_SCL_HORZ_FILTER_INIT 0x444a
#define mmSCL4_SCL_HORZ_FILTER_INIT 0x474a
#define mmSCL5_SCL_HORZ_FILTER_INIT 0x4a4a
#define mmSCL_VERT_FILTER_CONTROL 0x1b4b
#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b
#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1e4b
#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414b
#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444b
#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474b
#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4a4b
#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c
#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c
#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1e4c
#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414c
#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444c
#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474c
#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4a4c
#define mmSCL_VERT_FILTER_INIT 0x1b4d
#define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d
#define mmSCL1_SCL_VERT_FILTER_INIT 0x1e4d
#define mmSCL2_SCL_VERT_FILTER_INIT 0x414d
#define mmSCL3_SCL_VERT_FILTER_INIT 0x444d
#define mmSCL4_SCL_VERT_FILTER_INIT 0x474d
#define mmSCL5_SCL_VERT_FILTER_INIT 0x4a4d
#define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e
#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e
#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1e4e
#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x414e
#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x444e
#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x474e
#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4a4e
#define mmSCL_ROUND_OFFSET 0x1b4f
#define mmSCL0_SCL_ROUND_OFFSET 0x1b4f
#define mmSCL1_SCL_ROUND_OFFSET 0x1e4f
#define mmSCL2_SCL_ROUND_OFFSET 0x414f
#define mmSCL3_SCL_ROUND_OFFSET 0x444f
#define mmSCL4_SCL_ROUND_OFFSET 0x474f
#define mmSCL5_SCL_ROUND_OFFSET 0x4a4f
#define mmSCL_UPDATE 0x1b51
#define mmSCL0_SCL_UPDATE 0x1b51
#define mmSCL1_SCL_UPDATE 0x1e51
#define mmSCL2_SCL_UPDATE 0x4151
#define mmSCL3_SCL_UPDATE 0x4451
#define mmSCL4_SCL_UPDATE 0x4751
#define mmSCL5_SCL_UPDATE 0x4a51
#define mmSCL_F_SHARP_CONTROL 0x1b53
#define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53
#define mmSCL1_SCL_F_SHARP_CONTROL 0x1e53
#define mmSCL2_SCL_F_SHARP_CONTROL 0x4153
#define mmSCL3_SCL_F_SHARP_CONTROL 0x4453
#define mmSCL4_SCL_F_SHARP_CONTROL 0x4753
#define mmSCL5_SCL_F_SHARP_CONTROL 0x4a53
#define mmSCL_ALU_CONTROL 0x1b54
#define mmSCL0_SCL_ALU_CONTROL 0x1b54
#define mmSCL1_SCL_ALU_CONTROL 0x1e54
#define mmSCL2_SCL_ALU_CONTROL 0x4154
#define mmSCL3_SCL_ALU_CONTROL 0x4454
#define mmSCL4_SCL_ALU_CONTROL 0x4754
#define mmSCL5_SCL_ALU_CONTROL 0x4a54
#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55
#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55
#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1e55
#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155
#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455
#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755
#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4a55
#define mmVIEWPORT_START 0x1b5c
#define mmSCL0_VIEWPORT_START 0x1b5c
#define mmSCL1_VIEWPORT_START 0x1e5c
#define mmSCL2_VIEWPORT_START 0x415c
#define mmSCL3_VIEWPORT_START 0x445c
#define mmSCL4_VIEWPORT_START 0x475c
#define mmSCL5_VIEWPORT_START 0x4a5c
#define mmVIEWPORT_SIZE 0x1b5d
#define mmSCL0_VIEWPORT_SIZE 0x1b5d
#define mmSCL1_VIEWPORT_SIZE 0x1e5d
#define mmSCL2_VIEWPORT_SIZE 0x415d
#define mmSCL3_VIEWPORT_SIZE 0x445d
#define mmSCL4_VIEWPORT_SIZE 0x475d
#define mmSCL5_VIEWPORT_SIZE 0x4a5d
#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e
#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e
#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1e5e
#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415e
#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445e
#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475e
#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4a5e
#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f
#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f
#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1e5f
#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415f
#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445f
#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475f
#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4a5f
#define mmSCL_MODE_CHANGE_DET1 0x1b60
#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60
#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1e60
#define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160
#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460
#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760
#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4a60
#define mmSCL_MODE_CHANGE_DET2 0x1b61
#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61
#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1e61
#define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161
#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461
#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761
#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4a61
#define mmSCL_MODE_CHANGE_DET3 0x1b62
#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62
#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1e62
#define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162
#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462
#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762
#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4a62
#define mmSCL_MODE_CHANGE_MASK 0x1b63
#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63
#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1e63
#define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163
#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463
#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763
#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4a63
#define mmSCL_DEBUG2 0x1b69
#define mmSCL0_SCL_DEBUG2 0x1b69
#define mmSCL1_SCL_DEBUG2 0x1e69
#define mmSCL2_SCL_DEBUG2 0x4169
#define mmSCL3_SCL_DEBUG2 0x4469
#define mmSCL4_SCL_DEBUG2 0x4769
#define mmSCL5_SCL_DEBUG2 0x4a69
#define mmSCL_DEBUG 0x1b6a
#define mmSCL0_SCL_DEBUG 0x1b6a
#define mmSCL1_SCL_DEBUG 0x1e6a
#define mmSCL2_SCL_DEBUG 0x416a
#define mmSCL3_SCL_DEBUG 0x446a
#define mmSCL4_SCL_DEBUG 0x476a
#define mmSCL5_SCL_DEBUG 0x4a6a
#define mmSCL_TEST_DEBUG_INDEX 0x1b6b
#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b
#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1e6b
#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416b
#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446b
#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476b
#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4a6b
#define mmSCL_TEST_DEBUG_DATA 0x1b6c
#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c
#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1e6c
#define mmSCL2_SCL_TEST_DEBUG_DATA 0x416c
#define mmSCL3_SCL_TEST_DEBUG_DATA 0x446c
#define mmSCL4_SCL_TEST_DEBUG_DATA 0x476c
#define mmSCL5_SCL_TEST_DEBUG_DATA 0x4a6c
#define mmGENMO_WT 0xf0
#define mmGENMO_RD 0xf3
#define mmGENENB 0xf0
#define mmGENFC_WT 0xee
#define mmVGA0_GENFC_WT 0xee
#define mmVGA1_GENFC_WT 0xf6
#define mmGENFC_RD 0xf2
#define mmGENS0 0xf0
#define mmGENS1 0xee
#define mmVGA0_GENS1 0xee
#define mmVGA1_GENS1 0xf6
#define mmDAC_DATA 0xf2
#define mmDAC_MASK 0xf1
#define mmDAC_R_INDEX 0xf1
#define mmDAC_W_INDEX 0xf2
#define mmSEQ8_IDX 0xf1
#define mmSEQ8_DATA 0xf1
#define ixSEQ00 0x0
#define ixSEQ01 0x1
#define ixSEQ02 0x2
#define ixSEQ03 0x3
#define ixSEQ04 0x4
#define mmCRTC8_IDX 0xed
#define mmVGA0_CRTC8_IDX 0xed
#define mmVGA1_CRTC8_IDX 0xf5
#define mmCRTC8_DATA 0xed
#define mmVGA0_CRTC8_DATA 0xed
#define mmVGA1_CRTC8_DATA 0xf5
#define ixCRT00 0x0
#define ixCRT01 0x1
#define ixCRT02 0x2
#define ixCRT03 0x3
#define ixCRT04 0x4
#define ixCRT05 0x5
#define ixCRT06 0x6
#define ixCRT07 0x7
#define ixCRT08 0x8
#define ixCRT09 0x9
#define ixCRT0A 0xa
#define ixCRT0B 0xb
#define ixCRT0C 0xc
#define ixCRT0D 0xd
#define ixCRT0E 0xe
#define ixCRT0F 0xf
#define ixCRT10 0x10
#define ixCRT11 0x11
#define ixCRT12 0x12
#define ixCRT13 0x13
#define ixCRT14 0x14
#define ixCRT15 0x15
#define ixCRT16 0x16
#define ixCRT17 0x17
#define ixCRT18 0x18
#define ixCRT1E 0x1e
#define ixCRT1F 0x1f
#define ixCRT22 0x22
#define mmGRPH8_IDX 0xf3
#define mmGRPH8_DATA 0xf3
#define ixGRA00 0x0
#define ixGRA01 0x1
#define ixGRA02 0x2
#define ixGRA03 0x3
#define ixGRA04 0x4
#define ixGRA05 0x5
#define ixGRA06 0x6
#define ixGRA07 0x7
#define ixGRA08 0x8
#define mmATTRX 0xf0
#define mmATTRDW 0xf0
#define mmATTRDR 0xf0
#define ixATTR00 0x0
#define ixATTR01 0x1
#define ixATTR02 0x2
#define ixATTR03 0x3
#define ixATTR04 0x4
#define ixATTR05 0x5
#define ixATTR06 0x6
#define ixATTR07 0x7
#define ixATTR08 0x8
#define ixATTR09 0x9
#define ixATTR0A 0xa
#define ixATTR0B 0xb
#define ixATTR0C 0xc
#define ixATTR0D 0xd
#define ixATTR0E 0xe
#define ixATTR0F 0xf
#define ixATTR10 0x10
#define ixATTR11 0x11
#define ixATTR12 0x12
#define ixATTR13 0x13
#define ixATTR14 0x14
#define mmVGA_RENDER_CONTROL 0xc0
#define mmVGA_SOURCE_SELECT 0xfc
#define mmVGA_SEQUENCER_RESET_CONTROL 0xc1
#define mmVGA_MODE_CONTROL 0xc2
#define mmVGA_SURFACE_PITCH_SELECT 0xc3
#define mmVGA_MEMORY_BASE_ADDRESS 0xc4
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9
#define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6
#define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8
#define mmVGA_HDP_CONTROL 0xca
#define mmVGA_CACHE_CONTROL 0xcb
#define mmD1VGA_CONTROL 0xcc
#define mmD2VGA_CONTROL 0xce
#define mmD3VGA_CONTROL 0xf8
#define mmD4VGA_CONTROL 0xf9
#define mmD5VGA_CONTROL 0xfa
#define mmD6VGA_CONTROL 0xfb
#define mmVGA_HW_DEBUG 0xcf
#define mmVGA_STATUS 0xd0
#define mmVGA_INTERRUPT_CONTROL 0xd1
#define mmVGA_STATUS_CLEAR 0xd2
#define mmVGA_INTERRUPT_STATUS 0xd3
#define mmVGA_MAIN_CONTROL 0xd4
#define mmVGA_TEST_CONTROL 0xd5
#define mmVGA_DEBUG_READBACK_INDEX 0xd6
#define mmVGA_DEBUG_READBACK_DATA 0xd7
#define mmVGA_MEM_WRITE_PAGE_ADDR 0x12
#define mmVGA_MEM_READ_PAGE_ADDR 0x13
#define mmVGA_TEST_DEBUG_INDEX 0xc5
#define mmVGA_TEST_DEBUG_DATA 0xc7
#define ixVGADCC_DBG_DCCIF_C 0x7e
#define mmBPHYC_DAC_MACRO_CNTL 0x19fd
#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19fe
#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30
#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1e30
#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130
#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430
#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4a30
#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31
#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1e31
#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131
#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431
#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4a31
#define mmDPG_WATERMARK_MASK_CONTROL 0x1b32
#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32
#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1e32
#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x4132
#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4432
#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4732
#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4a32
#define mmDPG_PIPE_URGENCY_CONTROL 0x1b33
#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33
#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1e33
#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133
#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433
#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733
#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4a33
#define mmDPG_PIPE_DPM_CONTROL 0x1b34
#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34
#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1e34
#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134
#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434
#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734
#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4a34
#define mmDPG_PIPE_STUTTER_CONTROL 0x1b35
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35
#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1e35
#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135
#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435
#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4a35
#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1e36
#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136
#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436
#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736
#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4a36
#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1e37
#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137
#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437
#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4a37
#define mmDPG_REPEATER_PROGRAM 0x1b3a
#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a
#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1e3a
#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x413a
#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x443a
#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x473a
#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x4a3a
#define mmDPG_HW_DEBUG_A 0x1b3b
#define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b
#define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1e3b
#define mmDMIF_PG2_DPG_HW_DEBUG_A 0x413b
#define mmDMIF_PG3_DPG_HW_DEBUG_A 0x443b
#define mmDMIF_PG4_DPG_HW_DEBUG_A 0x473b
#define mmDMIF_PG5_DPG_HW_DEBUG_A 0x4a3b
#define mmDPG_HW_DEBUG_B 0x1b3c
#define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c
#define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1e3c
#define mmDMIF_PG2_DPG_HW_DEBUG_B 0x413c
#define mmDMIF_PG3_DPG_HW_DEBUG_B 0x443c
#define mmDMIF_PG4_DPG_HW_DEBUG_B 0x473c
#define mmDMIF_PG5_DPG_HW_DEBUG_B 0x4a3c
#define mmDPG_TEST_DEBUG_INDEX 0x1b38
#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38
#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1e38
#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138
#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438
#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738
#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4a38
#define mmDPG_TEST_DEBUG_DATA 0x1b39
#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39
#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1e39
#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139
#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439
#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739
#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4a39
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17d2
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17d3
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17d5
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17d6
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17d7
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17d8
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17d9
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17da
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17db
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17dc
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17dd
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17de
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17d4
#define mmAZALIA_F0_CODEC_DEBUG 0x17df
#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x17e1
#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x17e2
#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x17e3
#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x17e4
#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x17e5
#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x17e6
#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x17e7
#define mmGLOBAL_CAPABILITIES 0x0
#define mmMINOR_VERSION 0x0
#define mmMAJOR_VERSION 0x0
#define mmOUTPUT_PAYLOAD_CAPABILITY 0x1
#define mmINPUT_PAYLOAD_CAPABILITY 0x1
#define mmGLOBAL_CONTROL 0x2
#define mmWAKE_ENABLE 0x3
#define mmSTATE_CHANGE_STATUS 0x3
#define mmGLOBAL_STATUS 0x4
#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6
#define mmINTERRUPT_CONTROL 0x8
#define mmINTERRUPT_STATUS 0x9
#define mmWALL_CLOCK_COUNTER 0xc
#define mmSTREAM_SYNCHRONIZATION 0xe
#define mmCORB_LOWER_BASE_ADDRESS 0x10
#define mmCORB_UPPER_BASE_ADDRESS 0x11
#define mmCORB_WRITE_POINTER 0x12
#define mmCORB_READ_POINTER 0x12
#define mmCORB_CONTROL 0x13
#define mmCORB_STATUS 0x13
#define mmCORB_SIZE 0x13
#define mmRIRB_LOWER_BASE_ADDRESS 0x14
#define mmRIRB_UPPER_BASE_ADDRESS 0x15
#define mmRIRB_WRITE_POINTER 0x16
#define mmRESPONSE_INTERRUPT_COUNT 0x16
#define mmRIRB_CONTROL 0x17
#define mmRIRB_STATUS 0x17
#define mmRIRB_SIZE 0x17
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19
#define mmIMMEDIATE_COMMAND_STATUS 0x1a
#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c
#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d
#define mmWALL_CLOCK_COUNTER_ALIAS 0x80c
#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20
#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21
#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22
#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23
#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24
#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24
#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26
#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27
#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
#define ixAUDIO_DESCRIPTOR0 0x1
#define ixAUDIO_DESCRIPTOR1 0x2
#define ixAUDIO_DESCRIPTOR2 0x3
#define ixAUDIO_DESCRIPTOR3 0x4
#define ixAUDIO_DESCRIPTOR4 0x5
#define ixAUDIO_DESCRIPTOR5 0x6
#define ixAUDIO_DESCRIPTOR6 0x7
#define ixAUDIO_DESCRIPTOR7 0x8
#define ixAUDIO_DESCRIPTOR8 0x9
#define ixAUDIO_DESCRIPTOR9 0xa
#define ixAUDIO_DESCRIPTOR10 0xb
#define ixAUDIO_DESCRIPTOR11 0xc
#define ixAUDIO_DESCRIPTOR12 0xd
#define ixAUDIO_DESCRIPTOR13 0xe
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4
#define ixSINK_DESCRIPTION0 0x5
#define ixSINK_DESCRIPTION1 0x6
#define ixSINK_DESCRIPTION2 0x7
#define ixSINK_DESCRIPTION3 0x8
#define ixSINK_DESCRIPTION4 0x9
#define ixSINK_DESCRIPTION5 0xa
#define ixSINK_DESCRIPTION6 0xb
#define ixSINK_DESCRIPTION7 0xc
#define ixSINK_DESCRIPTION8 0xd
#define ixSINK_DESCRIPTION9 0xe
#define ixSINK_DESCRIPTION10 0xf
#define ixSINK_DESCRIPTION11 0x10
#define ixSINK_DESCRIPTION12 0x11
#define ixSINK_DESCRIPTION13 0x12
#define ixSINK_DESCRIPTION14 0x13
#define ixSINK_DESCRIPTION15 0x14
#define ixSINK_DESCRIPTION16 0x15
#define ixSINK_DESCRIPTION17 0x16
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17b9
#define mmAZALIA_AUDIO_DTO 0x17ba
#define mmAZALIA_AUDIO_DTO_CONTROL 0x17bb
#define mmAZALIA_SCLK_CONTROL 0x17bc
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17bd
#define mmAZALIA_DATA_DMA_CONTROL 0x17be
#define mmAZALIA_BDL_DMA_CONTROL 0x17bf
#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17c0
#define mmAZALIA_CORB_DMA_CONTROL 0x17c1
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17c9
#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17ca
#define mmAZALIA_GLOBAL_CAPABILITIES 0x17cb
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17cc
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17cd
#define mmAZALIA_CONTROLLER_DEBUG 0x17cf
#define mmAZALIA_CRC0_CONTROL0 0x17ae
#define mmAZALIA_CRC0_CONTROL1 0x17af
#define mmAZALIA_CRC0_CONTROL2 0x17b0
#define mmAZALIA_CRC0_CONTROL3 0x17b1
#define mmAZALIA_CRC0_RESULT 0x17b2
#define ixAZALIA_CRC0_CHANNEL0 0x0
#define ixAZALIA_CRC0_CHANNEL1 0x1
#define ixAZALIA_CRC0_CHANNEL2 0x2
#define ixAZALIA_CRC0_CHANNEL3 0x3
#define ixAZALIA_CRC0_CHANNEL4 0x4
#define ixAZALIA_CRC0_CHANNEL5 0x5
#define ixAZALIA_CRC0_CHANNEL6 0x6
#define ixAZALIA_CRC0_CHANNEL7 0x7
#define mmAZALIA_CRC1_CONTROL0 0x17b3
#define mmAZALIA_CRC1_CONTROL1 0x17b4
#define mmAZALIA_CRC1_CONTROL2 0x17b5
#define mmAZALIA_CRC1_CONTROL3 0x17b6
#define mmAZALIA_CRC1_RESULT 0x17b7
#define ixAZALIA_CRC1_CHANNEL0 0x0
#define ixAZALIA_CRC1_CHANNEL1 0x1
#define ixAZALIA_CRC1_CHANNEL2 0x2
#define ixAZALIA_CRC1_CHANNEL3 0x3
#define ixAZALIA_CRC1_CHANNEL4 0x4
#define ixAZALIA_CRC1_CHANNEL5 0x5
#define ixAZALIA_CRC1_CHANNEL6 0x6
#define ixAZALIA_CRC1_CHANNEL7 0x7
#define mmAZ_TEST_DEBUG_INDEX 0x17d0
#define mmAZ_TEST_DEBUG_DATA 0x17d1
#define mmAZALIA_STREAM_INDEX 0x17e8
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17e8
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17ec
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17f0
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17f4
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17f8
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17fc
#define mmAZALIA_STREAM_DATA 0x17e9
#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17e9
#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ed
#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17f1
#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17f5
#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17f9
#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17fd
#define ixAZALIA_FIFO_SIZE_CONTROL 0x0
#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1
#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2
#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3
#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4
#define ixAZALIA_STREAM_DEBUG 0x5
#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178c
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179e
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a4
#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178d
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179f
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a5
#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0
#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4
#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5
#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6
#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9
#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa
#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc
#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd
#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe
#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20
#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21
#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22
#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23
#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24
#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34
#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35
#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36
#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57
#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58
#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55
#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60
#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61
#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62
#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63
#define mmBLND_CONTROL 0x1b6d
#define mmBLND0_BLND_CONTROL 0x1b6d
#define mmBLND1_BLND_CONTROL 0x1e6d
#define mmBLND2_BLND_CONTROL 0x416d
#define mmBLND3_BLND_CONTROL 0x446d
#define mmBLND4_BLND_CONTROL 0x476d
#define mmBLND5_BLND_CONTROL 0x4a6d
#define mmSM_CONTROL2 0x1b6e
#define mmBLND0_SM_CONTROL2 0x1b6e
#define mmBLND1_SM_CONTROL2 0x1e6e
#define mmBLND2_SM_CONTROL2 0x416e
#define mmBLND3_SM_CONTROL2 0x446e
#define mmBLND4_SM_CONTROL2 0x476e
#define mmBLND5_SM_CONTROL2 0x4a6e
#define mmPTI_CONTROL 0x1b6f
#define mmBLND0_PTI_CONTROL 0x1b6f
#define mmBLND1_PTI_CONTROL 0x1e6f
#define mmBLND2_PTI_CONTROL 0x416f
#define mmBLND3_PTI_CONTROL 0x446f
#define mmBLND4_PTI_CONTROL 0x476f
#define mmBLND5_PTI_CONTROL 0x4a6f
#define mmBLND_UPDATE 0x1b70
#define mmBLND0_BLND_UPDATE 0x1b70
#define mmBLND1_BLND_UPDATE 0x1e70
#define mmBLND2_BLND_UPDATE 0x4170
#define mmBLND3_BLND_UPDATE 0x4470
#define mmBLND4_BLND_UPDATE 0x4770
#define mmBLND5_BLND_UPDATE 0x4a70
#define mmBLND_UNDERFLOW_INTERRUPT 0x1b71
#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71
#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1e71
#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x4171
#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4471
#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4771
#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4a71
#define mmBLND_V_UPDATE_LOCK 0x1b73
#define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73
#define mmBLND1_BLND_V_UPDATE_LOCK 0x1e73
#define mmBLND2_BLND_V_UPDATE_LOCK 0x4173
#define mmBLND3_BLND_V_UPDATE_LOCK 0x4473
#define mmBLND4_BLND_V_UPDATE_LOCK 0x4773
#define mmBLND5_BLND_V_UPDATE_LOCK 0x4a73
#define mmBLND_REG_UPDATE_STATUS 0x1b77
#define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77
#define mmBLND1_BLND_REG_UPDATE_STATUS 0x1e77
#define mmBLND2_BLND_REG_UPDATE_STATUS 0x4177
#define mmBLND3_BLND_REG_UPDATE_STATUS 0x4477
#define mmBLND4_BLND_REG_UPDATE_STATUS 0x4777
#define mmBLND5_BLND_REG_UPDATE_STATUS 0x4a77
#define mmBLND_DEBUG 0x1b74
#define mmBLND0_BLND_DEBUG 0x1b74
#define mmBLND1_BLND_DEBUG 0x1e74
#define mmBLND2_BLND_DEBUG 0x4174
#define mmBLND3_BLND_DEBUG 0x4474
#define mmBLND4_BLND_DEBUG 0x4774
#define mmBLND5_BLND_DEBUG 0x4a74
#define mmBLND_TEST_DEBUG_INDEX 0x1b75
#define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75
#define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1e75
#define mmBLND2_BLND_TEST_DEBUG_INDEX 0x4175
#define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4475
#define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4775
#define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4a75
#define mmBLND_TEST_DEBUG_DATA 0x1b76
#define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76
#define mmBLND1_BLND_TEST_DEBUG_DATA 0x1e76
#define mmBLND2_BLND_TEST_DEBUG_DATA 0x4176
#define mmBLND3_BLND_TEST_DEBUG_DATA 0x4476
#define mmBLND4_BLND_TEST_DEBUG_DATA 0x4776
#define mmBLND5_BLND_TEST_DEBUG_DATA 0x4a76
#define mmSI_ENABLE 0x4c00
#define mmSI_EC_CONFIG 0x4c01
#define mmCNV_MODE 0x4c02
#define mmCNV_WINDOW_START 0x4c03
#define mmCNV_WINDOW_SIZE 0x4c04
#define mmCNV_UPDATE 0x4c05
#define mmCNV_SOURCE_SIZE 0x4c06
#define mmCNV_CSC_CONTROL 0x4c07
#define mmCNV_CSC_C11_C12 0x4c08
#define mmCNV_CSC_C13_C14 0x4c09
#define mmCNV_CSC_C21_C22 0x4c0a
#define mmCNV_CSC_C23_C24 0x4c0b
#define mmCNV_CSC_C31_C32 0x4c0c
#define mmCNV_CSC_C33_C34 0x4c0d
#define mmCNV_CSC_ROUND_OFFSET_R 0x4c0e
#define mmCNV_CSC_ROUND_OFFSET_G 0x4c0f
#define mmCNV_CSC_ROUND_OFFSET_B 0x4c10
#define mmCNV_CSC_CLAMP_R 0x4c11
#define mmCNV_CSC_CLAMP_G 0x4c12
#define mmCNV_CSC_CLAMP_B 0x4c13
#define mmCNV_TEST_CNTL 0x4c14
#define mmCNV_TEST_CRC_RED 0x4c15
#define mmCNV_TEST_CRC_GREEN 0x4c16
#define mmCNV_TEST_CRC_BLUE 0x4c17
#define mmSI_DEBUG_CTRL 0x4c18
#define mmSI_DBG_MODE 0x4c1b
#define mmSI_HARD_DEBUG 0x4c1c
#define mmCNV_TEST_DEBUG_INDEX 0x4c19
#define mmCNV_TEST_DEBUG_DATA 0x4c1a
#define mmSISCL_COEF_RAM_SELECT 0x4c20
#define mmSISCL_COEF_RAM_TAP_DATA 0x4c21
#define mmSISCL_MODE 0x4c22
#define mmSISCL_TAP_CONTROL 0x4c23
#define mmSISCL_DEST_SIZE 0x4c24
#define mmSISCL_HORZ_FILTER_SCALE_RATIO 0x4c25
#define mmSISCL_HORZ_FILTER_INIT_Y_RGB 0x4c26
#define mmSISCL_HORZ_FILTER_INIT_CBCR 0x4c27
#define mmSISCL_VERT_FILTER_SCALE_RATIO 0x4c28
#define mmSISCL_VERT_FILTER_INIT_Y_RGB 0x4c29
#define mmSISCL_VERT_FILTER_INIT_CBCR 0x4c2a
#define mmSISCL_ROUND_OFFSET 0x4c2b
#define mmSISCL_CLAMP 0x4c2c
#define mmSISCL_OVERFLOW_STATUS 0x4c2d
#define mmSISCL_COEF_RAM_CONFLICT_STATUS 0x4c2e
#define mmSISCL_OUTSIDE_PIX_STRATEGY 0x4c2f
#define mmSISCL_TEST_CNTL 0x4c30
#define mmSISCL_TEST_CRC_RED 0x4c31
#define mmSISCL_TEST_CRC_GREEN 0x4c32
#define mmSISCL_TEST_CRC_BLUE 0x4c33
#define mmSISCL_BACKPRESSURE_CNT_EN 0x4c36
#define mmSISCL_MCIF_BACKPRESSURE_CNT 0x4c37
#define mmSISCL_TEST_DEBUG_INDEX 0x4c34
#define mmSISCL_TEST_DEBUG_DATA 0x4c35
#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0
#define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1
#define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2
#define mmXDMA_INTERRUPT 0x3e3
#define mmXDMA_CLOCK_GATING_CNTL 0x3e4
#define mmXDMA_MEM_POWER_CNTL 0x3e6
#define mmXDMA_IF_BIF_STATUS 0x3e7
#define mmXDMA_PERF_MEAS_STATUS 0x3e8
#define mmXDMA_IF_STATUS 0x3e9
#define mmXDMA_TEST_DEBUG_INDEX 0x3ea
#define mmXDMA_TEST_DEBUG_DATA 0x3eb
#define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8
#define mmXDMA_PG_CONTROL 0x3f9
#define mmXDMA_PG_WDATA 0x3fa
#define mmXDMA_PG_STATUS 0x3fb
#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc
#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd
#endif /* DCE_8_0_D_H */
| null | null | null | null | 99,250 |
9,342 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 9,342 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2012 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "net/http/http_auth_handler.h"
#include "base/strings/string_util.h"
#include "base/strings/utf_string_conversions.h"
#include "net/base/net_errors.h"
#include "net/base/test_completion_callback.h"
#include "net/http/http_auth_challenge_tokenizer.h"
#include "net/http/http_auth_handler_mock.h"
#include "net/http/http_request_info.h"
#include "net/log/net_log_event_type.h"
#include "net/log/net_log_source_type.h"
#include "net/log/test_net_log.h"
#include "net/log/test_net_log_entry.h"
#include "net/log/test_net_log_util.h"
#include "net/ssl/ssl_info.h"
#include "testing/gtest/include/gtest/gtest.h"
namespace net {
TEST(HttpAuthHandlerTest, NetLog) {
GURL origin("http://www.example.com");
std::string challenge = "Mock asdf";
AuthCredentials credentials(base::ASCIIToUTF16("user"),
base::ASCIIToUTF16("pass"));
std::string auth_token;
HttpRequestInfo request;
for (int i = 0; i < 2; ++i) {
bool async = (i == 0);
for (int j = 0; j < 2; ++j) {
int rv = (j == 0) ? OK : ERR_UNEXPECTED;
for (int k = 0; k < 2; ++k) {
TestCompletionCallback test_callback;
HttpAuth::Target target =
(k == 0) ? HttpAuth::AUTH_PROXY : HttpAuth::AUTH_SERVER;
NetLogEventType event_type = (k == 0) ? NetLogEventType::AUTH_PROXY
: NetLogEventType::AUTH_SERVER;
HttpAuthChallengeTokenizer tokenizer(
challenge.begin(), challenge.end());
HttpAuthHandlerMock mock_handler;
TestNetLog test_net_log;
NetLogWithSource net_log(
NetLogWithSource::Make(&test_net_log, NetLogSourceType::NONE));
SSLInfo empty_ssl_info;
mock_handler.InitFromChallenge(&tokenizer, target, empty_ssl_info,
origin, net_log);
mock_handler.SetGenerateExpectation(async, rv);
mock_handler.GenerateAuthToken(&credentials, &request,
test_callback.callback(), &auth_token);
if (async)
test_callback.WaitForResult();
TestNetLogEntry::List entries;
test_net_log.GetEntries(&entries);
EXPECT_EQ(2u, entries.size());
EXPECT_TRUE(LogContainsBeginEvent(entries, 0, event_type));
EXPECT_TRUE(LogContainsEndEvent(entries, 1, event_type));
}
}
}
}
} // namespace net
| null | null | null | null | 6,205 |
61,604 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 61,604 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef CHROME_BROWSER_MEDIA_GALLERIES_MEDIA_GALLERIES_PERMISSION_CONTROLLER_H_
#define CHROME_BROWSER_MEDIA_GALLERIES_MEDIA_GALLERIES_PERMISSION_CONTROLLER_H_
#include <stddef.h>
#include <map>
#include <memory>
#include <string>
#include <vector>
#include "base/callback.h"
#include "base/macros.h"
#include "base/strings/string16.h"
#include "chrome/browser/media_galleries/media_galleries_dialog_controller.h"
#include "chrome/browser/media_galleries/media_galleries_preferences.h"
#include "components/storage_monitor/removable_storage_observer.h"
#include "ui/gfx/native_widget_types.h"
#include "ui/shell_dialogs/select_file_dialog.h"
namespace content {
class WebContents;
}
namespace extensions {
class Extension;
}
namespace ui {
class MenuModel;
}
class MediaGalleriesDialogController;
class MediaGalleryContextMenu;
class Profile;
// Newly added galleries are not added to preferences until the dialog commits,
// so they do not have a pref id while the dialog is open; leading to
// complicated code in the dialogs. To solve this complication, the controller
// maps pref ids into a new space where it can also assign ids to new galleries.
// The new number space is only valid for the lifetime of the controller. To
// make it more clear where real pref ids are used and where the fake ids are
// used, the GalleryDialogId type is used where fake ids are needed.
typedef MediaGalleryPrefId GalleryDialogId;
class MediaGalleriesPermissionController
: public MediaGalleriesDialogController,
public ui::SelectFileDialog::Listener,
public storage_monitor::RemovableStorageObserver,
public MediaGalleriesPreferences::GalleryChangeObserver {
public:
// The constructor creates a dialog controller which owns itself.
MediaGalleriesPermissionController(content::WebContents* web_contents,
const extensions::Extension& extension,
const base::Closure& on_finish);
// MediaGalleriesDialogController implementation.
base::string16 GetHeader() const override;
base::string16 GetSubtext() const override;
bool IsAcceptAllowed() const override;
std::vector<base::string16> GetSectionHeaders() const override;
Entries GetSectionEntries(size_t index) const override;
// Auxiliary button for this dialog is the 'Add Folder' button.
base::string16 GetAuxiliaryButtonText() const override;
void DidClickAuxiliaryButton() override;
void DidToggleEntry(GalleryDialogId gallery_id, bool selected) override;
void DidForgetEntry(GalleryDialogId gallery_id) override;
base::string16 GetAcceptButtonText() const override;
void DialogFinished(bool accepted) override;
ui::MenuModel* GetContextMenu(GalleryDialogId gallery_id) override;
content::WebContents* WebContents() override;
protected:
friend class MediaGalleriesPermissionControllerTest;
typedef base::Callback<MediaGalleriesDialog* (
MediaGalleriesDialogController*)> CreateDialogCallback;
// For use with tests.
MediaGalleriesPermissionController(
const extensions::Extension& extension,
MediaGalleriesPreferences* preferences,
const CreateDialogCallback& create_dialog_callback,
const base::Closure& on_finish);
~MediaGalleriesPermissionController() override;
private:
// This type keeps track of media galleries already known to the prefs system.
typedef std::map<GalleryDialogId, Entry> GalleryPermissionsMap;
typedef std::map<GalleryDialogId, bool /*permitted*/> ToggledGalleryMap;
class DialogIdMap {
public:
DialogIdMap();
~DialogIdMap();
GalleryDialogId GetDialogId(MediaGalleryPrefId pref_id);
MediaGalleryPrefId GetPrefId(GalleryDialogId id) const;
private:
GalleryDialogId next_dialog_id_;
std::map<MediaGalleryPrefId, GalleryDialogId> back_map_;
std::vector<MediaGalleryPrefId> forward_mapping_;
DISALLOW_COPY_AND_ASSIGN(DialogIdMap);
};
// Bottom half of constructor -- called when |preferences_| is initialized.
void OnPreferencesInitialized();
// SelectFileDialog::Listener implementation:
void FileSelected(const base::FilePath& path,
int index,
void* params) override;
// RemovableStorageObserver implementation.
// Used to keep dialog in sync with removable device status.
void OnRemovableStorageAttached(
const storage_monitor::StorageInfo& info) override;
void OnRemovableStorageDetached(
const storage_monitor::StorageInfo& info) override;
// MediaGalleriesPreferences::GalleryChangeObserver implementations.
// Used to keep the dialog in sync when the preferences change.
void OnPermissionAdded(MediaGalleriesPreferences* pref,
const std::string& extension_id,
MediaGalleryPrefId pref_id) override;
void OnPermissionRemoved(MediaGalleriesPreferences* pref,
const std::string& extension_id,
MediaGalleryPrefId pref_id) override;
void OnGalleryAdded(MediaGalleriesPreferences* pref,
MediaGalleryPrefId pref_id) override;
void OnGalleryRemoved(MediaGalleriesPreferences* pref,
MediaGalleryPrefId pref_id) override;
void OnGalleryInfoUpdated(MediaGalleriesPreferences* pref,
MediaGalleryPrefId pref_id) override;
// Populates |known_galleries_| from |preferences_|. Subsequent calls merge
// into |known_galleries_| and do not change permissions for user toggled
// galleries.
void InitializePermissions();
// Saves state of |known_galleries_|, |new_galleries_| and
// |forgotten_galleries_| to model.
//
// NOTE: possible states for a gallery:
// K N F (K = Known, N = New, F = Forgotten)
// +---+---+---+
// | Y | N | N |
// +---+---+---+
// | N | Y | N |
// +---+---+---+
// | Y | N | Y |
// +---+---+---+
void SavePermissions();
// Updates the model and view when |preferences_| changes. Some of the
// possible changes includes a gallery getting blacklisted, or a new
// auto detected gallery becoming available.
void UpdateGalleriesOnPreferencesEvent();
// Updates the model and view when a device is attached or detached.
void UpdateGalleriesOnDeviceEvent(const std::string& device_id);
GalleryDialogId GetDialogId(MediaGalleryPrefId pref_id);
MediaGalleryPrefId GetPrefId(GalleryDialogId id) const;
Profile* GetProfile();
// The web contents from which the request originated.
content::WebContents* web_contents_;
// This is just a reference, but it's assumed that it won't become invalid
// while the dialog is showing.
const extensions::Extension* extension_;
// Mapping between pref ids and dialog ids.
DialogIdMap id_map_;
// This map excludes those galleries which have been blacklisted; it only
// counts active known galleries.
GalleryPermissionsMap known_galleries_;
// Galleries in |known_galleries_| that the user have toggled.
ToggledGalleryMap toggled_galleries_;
// The current set of permitted galleries (according to prefs).
MediaGalleryPrefIdSet pref_permitted_galleries_;
// Map of new galleries the user added, but have not saved. This list should
// never overlap with |known_galleries_|.
GalleryPermissionsMap new_galleries_;
// Galleries in |known_galleries_| that the user has forgotten.
std::set<GalleryDialogId> forgotten_galleries_;
// Callback to run when the dialog closes.
base::Closure on_finish_;
// The model that tracks galleries and extensions' permissions.
// This is the authoritative source for gallery information.
MediaGalleriesPreferences* preferences_;
// The view that's showing.
std::unique_ptr<MediaGalleriesDialog> dialog_;
scoped_refptr<ui::SelectFileDialog> select_folder_dialog_;
std::unique_ptr<MediaGalleryContextMenu> context_menu_;
// Creates the dialog. Only changed for unit tests.
CreateDialogCallback create_dialog_callback_;
DISALLOW_COPY_AND_ASSIGN(MediaGalleriesPermissionController);
};
#endif // CHROME_BROWSER_MEDIA_GALLERIES_MEDIA_GALLERIES_PERMISSION_CONTROLLER_H_
| null | null | null | null | 58,467 |
5,744 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 170,739 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* wm8904.c -- WM8904 ALSA SoC Audio driver
*
* Copyright 2009-12 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/wm8904.h>
#include "wm8904.h"
enum wm8904_type {
WM8904,
WM8912,
};
#define WM8904_NUM_DCS_CHANNELS 4
#define WM8904_NUM_SUPPLIES 5
static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
"DCVDD",
"DBVDD",
"AVDD",
"CPVDD",
"MICVDD",
};
/* codec private data */
struct wm8904_priv {
struct regmap *regmap;
struct clk *mclk;
enum wm8904_type devtype;
struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
struct wm8904_pdata *pdata;
int deemph;
/* Platform provided DRC configuration */
const char **drc_texts;
int drc_cfg;
struct soc_enum drc_enum;
/* Platform provided ReTune mobile configuration */
int num_retune_mobile_texts;
const char **retune_mobile_texts;
int retune_mobile_cfg;
struct soc_enum retune_mobile_enum;
/* FLL setup */
int fll_src;
int fll_fref;
int fll_fout;
/* Clocking configuration */
unsigned int mclk_rate;
int sysclk_src;
unsigned int sysclk_rate;
int tdm_width;
int tdm_slots;
int bclk;
int fs;
/* DC servo configuration - cached offset values */
int dcs_state[WM8904_NUM_DCS_CHANNELS];
};
static const struct reg_default wm8904_reg_defaults[] = {
{ 4, 0x0018 }, /* R4 - Bias Control 0 */
{ 5, 0x0000 }, /* R5 - VMID Control 0 */
{ 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
{ 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
{ 8, 0x0001 }, /* R8 - Analogue DAC 0 */
{ 9, 0x9696 }, /* R9 - mic Filter Control */
{ 10, 0x0001 }, /* R10 - Analogue ADC 0 */
{ 12, 0x0000 }, /* R12 - Power Management 0 */
{ 14, 0x0000 }, /* R14 - Power Management 2 */
{ 15, 0x0000 }, /* R15 - Power Management 3 */
{ 18, 0x0000 }, /* R18 - Power Management 6 */
{ 20, 0x945E }, /* R20 - Clock Rates 0 */
{ 21, 0x0C05 }, /* R21 - Clock Rates 1 */
{ 22, 0x0006 }, /* R22 - Clock Rates 2 */
{ 24, 0x0050 }, /* R24 - Audio Interface 0 */
{ 25, 0x000A }, /* R25 - Audio Interface 1 */
{ 26, 0x00E4 }, /* R26 - Audio Interface 2 */
{ 27, 0x0040 }, /* R27 - Audio Interface 3 */
{ 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
{ 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
{ 32, 0x0000 }, /* R32 - DAC Digital 0 */
{ 33, 0x0008 }, /* R33 - DAC Digital 1 */
{ 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
{ 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
{ 38, 0x0010 }, /* R38 - ADC Digital 0 */
{ 39, 0x0000 }, /* R39 - Digital Microphone 0 */
{ 40, 0x01AF }, /* R40 - DRC 0 */
{ 41, 0x3248 }, /* R41 - DRC 1 */
{ 42, 0x0000 }, /* R42 - DRC 2 */
{ 43, 0x0000 }, /* R43 - DRC 3 */
{ 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
{ 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
{ 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
{ 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
{ 57, 0x002D }, /* R57 - Analogue OUT1 Left */
{ 58, 0x002D }, /* R58 - Analogue OUT1 Right */
{ 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
{ 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
{ 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
{ 67, 0x0000 }, /* R67 - DC Servo 0 */
{ 69, 0xAAAA }, /* R69 - DC Servo 2 */
{ 71, 0xAAAA }, /* R71 - DC Servo 4 */
{ 72, 0xAAAA }, /* R72 - DC Servo 5 */
{ 90, 0x0000 }, /* R90 - Analogue HP 0 */
{ 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
{ 98, 0x0000 }, /* R98 - Charge Pump 0 */
{ 104, 0x0004 }, /* R104 - Class W 0 */
{ 108, 0x0000 }, /* R108 - Write Sequencer 0 */
{ 109, 0x0000 }, /* R109 - Write Sequencer 1 */
{ 110, 0x0000 }, /* R110 - Write Sequencer 2 */
{ 111, 0x0000 }, /* R111 - Write Sequencer 3 */
{ 112, 0x0000 }, /* R112 - Write Sequencer 4 */
{ 116, 0x0000 }, /* R116 - FLL Control 1 */
{ 117, 0x0007 }, /* R117 - FLL Control 2 */
{ 118, 0x0000 }, /* R118 - FLL Control 3 */
{ 119, 0x2EE0 }, /* R119 - FLL Control 4 */
{ 120, 0x0004 }, /* R120 - FLL Control 5 */
{ 121, 0x0014 }, /* R121 - GPIO Control 1 */
{ 122, 0x0010 }, /* R122 - GPIO Control 2 */
{ 123, 0x0010 }, /* R123 - GPIO Control 3 */
{ 124, 0x0000 }, /* R124 - GPIO Control 4 */
{ 126, 0x0000 }, /* R126 - Digital Pulls */
{ 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
{ 129, 0x0000 }, /* R129 - Interrupt Polarity */
{ 130, 0x0000 }, /* R130 - Interrupt Debounce */
{ 134, 0x0000 }, /* R134 - EQ1 */
{ 135, 0x000C }, /* R135 - EQ2 */
{ 136, 0x000C }, /* R136 - EQ3 */
{ 137, 0x000C }, /* R137 - EQ4 */
{ 138, 0x000C }, /* R138 - EQ5 */
{ 139, 0x000C }, /* R139 - EQ6 */
{ 140, 0x0FCA }, /* R140 - EQ7 */
{ 141, 0x0400 }, /* R141 - EQ8 */
{ 142, 0x00D8 }, /* R142 - EQ9 */
{ 143, 0x1EB5 }, /* R143 - EQ10 */
{ 144, 0xF145 }, /* R144 - EQ11 */
{ 145, 0x0B75 }, /* R145 - EQ12 */
{ 146, 0x01C5 }, /* R146 - EQ13 */
{ 147, 0x1C58 }, /* R147 - EQ14 */
{ 148, 0xF373 }, /* R148 - EQ15 */
{ 149, 0x0A54 }, /* R149 - EQ16 */
{ 150, 0x0558 }, /* R150 - EQ17 */
{ 151, 0x168E }, /* R151 - EQ18 */
{ 152, 0xF829 }, /* R152 - EQ19 */
{ 153, 0x07AD }, /* R153 - EQ20 */
{ 154, 0x1103 }, /* R154 - EQ21 */
{ 155, 0x0564 }, /* R155 - EQ22 */
{ 156, 0x0559 }, /* R156 - EQ23 */
{ 157, 0x4000 }, /* R157 - EQ24 */
{ 161, 0x0000 }, /* R161 - Control Interface Test 1 */
{ 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
{ 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
{ 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
};
static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8904_SW_RESET_AND_ID:
case WM8904_REVISION:
case WM8904_DC_SERVO_1:
case WM8904_DC_SERVO_6:
case WM8904_DC_SERVO_7:
case WM8904_DC_SERVO_8:
case WM8904_DC_SERVO_9:
case WM8904_DC_SERVO_READBACK_0:
case WM8904_INTERRUPT_STATUS:
return true;
default:
return false;
}
}
static bool wm8904_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8904_SW_RESET_AND_ID:
case WM8904_REVISION:
case WM8904_BIAS_CONTROL_0:
case WM8904_VMID_CONTROL_0:
case WM8904_MIC_BIAS_CONTROL_0:
case WM8904_MIC_BIAS_CONTROL_1:
case WM8904_ANALOGUE_DAC_0:
case WM8904_MIC_FILTER_CONTROL:
case WM8904_ANALOGUE_ADC_0:
case WM8904_POWER_MANAGEMENT_0:
case WM8904_POWER_MANAGEMENT_2:
case WM8904_POWER_MANAGEMENT_3:
case WM8904_POWER_MANAGEMENT_6:
case WM8904_CLOCK_RATES_0:
case WM8904_CLOCK_RATES_1:
case WM8904_CLOCK_RATES_2:
case WM8904_AUDIO_INTERFACE_0:
case WM8904_AUDIO_INTERFACE_1:
case WM8904_AUDIO_INTERFACE_2:
case WM8904_AUDIO_INTERFACE_3:
case WM8904_DAC_DIGITAL_VOLUME_LEFT:
case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
case WM8904_DAC_DIGITAL_0:
case WM8904_DAC_DIGITAL_1:
case WM8904_ADC_DIGITAL_VOLUME_LEFT:
case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
case WM8904_ADC_DIGITAL_0:
case WM8904_DIGITAL_MICROPHONE_0:
case WM8904_DRC_0:
case WM8904_DRC_1:
case WM8904_DRC_2:
case WM8904_DRC_3:
case WM8904_ANALOGUE_LEFT_INPUT_0:
case WM8904_ANALOGUE_RIGHT_INPUT_0:
case WM8904_ANALOGUE_LEFT_INPUT_1:
case WM8904_ANALOGUE_RIGHT_INPUT_1:
case WM8904_ANALOGUE_OUT1_LEFT:
case WM8904_ANALOGUE_OUT1_RIGHT:
case WM8904_ANALOGUE_OUT2_LEFT:
case WM8904_ANALOGUE_OUT2_RIGHT:
case WM8904_ANALOGUE_OUT12_ZC:
case WM8904_DC_SERVO_0:
case WM8904_DC_SERVO_1:
case WM8904_DC_SERVO_2:
case WM8904_DC_SERVO_4:
case WM8904_DC_SERVO_5:
case WM8904_DC_SERVO_6:
case WM8904_DC_SERVO_7:
case WM8904_DC_SERVO_8:
case WM8904_DC_SERVO_9:
case WM8904_DC_SERVO_READBACK_0:
case WM8904_ANALOGUE_HP_0:
case WM8904_ANALOGUE_LINEOUT_0:
case WM8904_CHARGE_PUMP_0:
case WM8904_CLASS_W_0:
case WM8904_WRITE_SEQUENCER_0:
case WM8904_WRITE_SEQUENCER_1:
case WM8904_WRITE_SEQUENCER_2:
case WM8904_WRITE_SEQUENCER_3:
case WM8904_WRITE_SEQUENCER_4:
case WM8904_FLL_CONTROL_1:
case WM8904_FLL_CONTROL_2:
case WM8904_FLL_CONTROL_3:
case WM8904_FLL_CONTROL_4:
case WM8904_FLL_CONTROL_5:
case WM8904_GPIO_CONTROL_1:
case WM8904_GPIO_CONTROL_2:
case WM8904_GPIO_CONTROL_3:
case WM8904_GPIO_CONTROL_4:
case WM8904_DIGITAL_PULLS:
case WM8904_INTERRUPT_STATUS:
case WM8904_INTERRUPT_STATUS_MASK:
case WM8904_INTERRUPT_POLARITY:
case WM8904_INTERRUPT_DEBOUNCE:
case WM8904_EQ1:
case WM8904_EQ2:
case WM8904_EQ3:
case WM8904_EQ4:
case WM8904_EQ5:
case WM8904_EQ6:
case WM8904_EQ7:
case WM8904_EQ8:
case WM8904_EQ9:
case WM8904_EQ10:
case WM8904_EQ11:
case WM8904_EQ12:
case WM8904_EQ13:
case WM8904_EQ14:
case WM8904_EQ15:
case WM8904_EQ16:
case WM8904_EQ17:
case WM8904_EQ18:
case WM8904_EQ19:
case WM8904_EQ20:
case WM8904_EQ21:
case WM8904_EQ22:
case WM8904_EQ23:
case WM8904_EQ24:
case WM8904_CONTROL_INTERFACE_TEST_1:
case WM8904_ADC_TEST_0:
case WM8904_ANALOGUE_OUTPUT_BIAS_0:
case WM8904_FLL_NCO_TEST_0:
case WM8904_FLL_NCO_TEST_1:
return true;
default:
return false;
}
}
static int wm8904_configure_clocking(struct snd_soc_codec *codec)
{
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
unsigned int clock0, clock2, rate;
/* Gate the clock while we're updating to avoid misclocking */
clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
WM8904_SYSCLK_SRC, 0);
/* This should be done on init() for bypass paths */
switch (wm8904->sysclk_src) {
case WM8904_CLK_MCLK:
dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
clock2 &= ~WM8904_SYSCLK_SRC;
rate = wm8904->mclk_rate;
/* Ensure the FLL is stopped */
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
break;
case WM8904_CLK_FLL:
dev_dbg(codec->dev, "Using %dHz FLL clock\n",
wm8904->fll_fout);
clock2 |= WM8904_SYSCLK_SRC;
rate = wm8904->fll_fout;
break;
default:
dev_err(codec->dev, "System clock not configured\n");
return -EINVAL;
}
/* SYSCLK shouldn't be over 13.5MHz */
if (rate > 13500000) {
clock0 = WM8904_MCLK_DIV;
wm8904->sysclk_rate = rate / 2;
} else {
clock0 = 0;
wm8904->sysclk_rate = rate;
}
snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
clock0);
snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
return 0;
}
static void wm8904_set_drc(struct snd_soc_codec *codec)
{
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
struct wm8904_pdata *pdata = wm8904->pdata;
int save, i;
/* Save any enables; the configuration should clear them. */
save = snd_soc_read(codec, WM8904_DRC_0);
for (i = 0; i < WM8904_DRC_REGS; i++)
snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff,
pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
/* Reenable the DRC */
snd_soc_update_bits(codec, WM8904_DRC_0,
WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
}
static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
struct wm8904_pdata *pdata = wm8904->pdata;
int value = ucontrol->value.enumerated.item[0];
if (value >= pdata->num_drc_cfgs)
return -EINVAL;
wm8904->drc_cfg = value;
wm8904_set_drc(codec);
return 0;
}
static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
return 0;
}
static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
{
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
struct wm8904_pdata *pdata = wm8904->pdata;
int best, best_val, save, i, cfg;
if (!pdata || !wm8904->num_retune_mobile_texts)
return;
/* Find the version of the currently selected configuration
* with the nearest sample rate. */
cfg = wm8904->retune_mobile_cfg;
best = 0;
best_val = INT_MAX;
for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
if (strcmp(pdata->retune_mobile_cfgs[i].name,
wm8904->retune_mobile_texts[cfg]) == 0 &&
abs(pdata->retune_mobile_cfgs[i].rate
- wm8904->fs) < best_val) {
best = i;
best_val = abs(pdata->retune_mobile_cfgs[i].rate
- wm8904->fs);
}
}
dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
pdata->retune_mobile_cfgs[best].name,
pdata->retune_mobile_cfgs[best].rate,
wm8904->fs);
/* The EQ will be disabled while reconfiguring it, remember the
* current configuration.
*/
save = snd_soc_read(codec, WM8904_EQ1);
for (i = 0; i < WM8904_EQ_REGS; i++)
snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff,
pdata->retune_mobile_cfgs[best].regs[i]);
snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save);
}
static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
struct wm8904_pdata *pdata = wm8904->pdata;
int value = ucontrol->value.enumerated.item[0];
if (value >= pdata->num_retune_mobile_cfgs)
return -EINVAL;
wm8904->retune_mobile_cfg = value;
wm8904_set_retune_mobile(codec);
return 0;
}
static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
return 0;
}
static int deemph_settings[] = { 0, 32000, 44100, 48000 };
static int wm8904_set_deemph(struct snd_soc_codec *codec)
{
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
int val, i, best;
/* If we're using deemphasis select the nearest available sample
* rate.
*/
if (wm8904->deemph) {
best = 1;
for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
if (abs(deemph_settings[i] - wm8904->fs) <
abs(deemph_settings[best] - wm8904->fs))
best = i;
}
val = best << WM8904_DEEMPH_SHIFT;
} else {
val = 0;
}
dev_dbg(codec->dev, "Set deemphasis %d\n", val);
return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
WM8904_DEEMPH_MASK, val);
}
static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
ucontrol->value.integer.value[0] = wm8904->deemph;
return 0;
}
static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
unsigned int deemph = ucontrol->value.integer.value[0];
if (deemph > 1)
return -EINVAL;
wm8904->deemph = deemph;
return wm8904_set_deemph(codec);
}
static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const char *input_mode_text[] = {
"Single-Ended", "Differential Line", "Differential Mic"
};
static SOC_ENUM_SINGLE_DECL(lin_mode,
WM8904_ANALOGUE_LEFT_INPUT_1, 0,
input_mode_text);
static SOC_ENUM_SINGLE_DECL(rin_mode,
WM8904_ANALOGUE_RIGHT_INPUT_1, 0,
input_mode_text);
static const char *hpf_mode_text[] = {
"Hi-fi", "Voice 1", "Voice 2", "Voice 3"
};
static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5,
hpf_mode_text);
static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
unsigned int val;
int ret;
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret < 0)
return ret;
if (ucontrol->value.integer.value[0])
val = 0;
else
val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
snd_soc_update_bits(codec, WM8904_ADC_TEST_0,
WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
val);
return ret;
}
static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
SOC_ENUM("Left Caputure Mode", lin_mode),
SOC_ENUM("Right Capture Mode", rin_mode),
/* No TLV since it depends on mode */
SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
SOC_ENUM("High Pass Filter Mode", hpf_mode),
SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0,
snd_soc_get_volsw, wm8904_adc_osr_put),
};
static const char *drc_path_text[] = {
"ADC", "DAC"
};
static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text);
static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
SOC_SINGLE_TLV("Digital Playback Boost Volume",
WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
SOC_ENUM("DRC Path", drc_path),
SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
wm8904_get_deemph, wm8904_put_deemph),
};
static const struct snd_kcontrol_new wm8904_snd_controls[] = {
SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
sidetone_tlv),
};
static const struct snd_kcontrol_new wm8904_eq_controls[] = {
SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
};
static int cp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
if (WARN_ON(event != SND_SOC_DAPM_POST_PMU))
return -EINVAL;
/* Maximum startup time */
udelay(500);
return 0;
}
static int sysclk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* If we're using the FLL then we only start it when
* required; we assume that the configuration has been
* done previously and all we need to do is kick it
* off.
*/
switch (wm8904->sysclk_src) {
case WM8904_CLK_FLL:
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA,
WM8904_FLL_OSC_ENA);
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
WM8904_FLL_ENA,
WM8904_FLL_ENA);
break;
default:
break;
}
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
break;
}
return 0;
}
static int out_pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
int reg, val;
int dcs_mask;
int dcs_l, dcs_r;
int dcs_l_reg, dcs_r_reg;
int timeout;
int pwr_reg;
/* This code is shared between HP and LINEOUT; we do all our
* power management in stereo pairs to avoid latency issues so
* we reuse shift to identify which rather than strcmp() the
* name. */
reg = w->shift;
switch (reg) {
case WM8904_ANALOGUE_HP_0:
pwr_reg = WM8904_POWER_MANAGEMENT_2;
dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
dcs_r_reg = WM8904_DC_SERVO_8;
dcs_l_reg = WM8904_DC_SERVO_9;
dcs_l = 0;
dcs_r = 1;
break;
case WM8904_ANALOGUE_LINEOUT_0:
pwr_reg = WM8904_POWER_MANAGEMENT_3;
dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
dcs_r_reg = WM8904_DC_SERVO_6;
dcs_l_reg = WM8904_DC_SERVO_7;
dcs_l = 2;
dcs_r = 3;
break;
default:
WARN(1, "Invalid reg %d\n", reg);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Power on the PGAs */
snd_soc_update_bits(codec, pwr_reg,
WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
/* Power on the amplifier */
snd_soc_update_bits(codec, reg,
WM8904_HPL_ENA | WM8904_HPR_ENA,
WM8904_HPL_ENA | WM8904_HPR_ENA);
/* Enable the first stage */
snd_soc_update_bits(codec, reg,
WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
/* Power up the DC servo */
snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
dcs_mask, dcs_mask);
/* Either calibrate the DC servo or restore cached state
* if we have that.
*/
if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
dev_dbg(codec->dev, "Restoring DC servo state\n");
snd_soc_write(codec, dcs_l_reg,
wm8904->dcs_state[dcs_l]);
snd_soc_write(codec, dcs_r_reg,
wm8904->dcs_state[dcs_r]);
snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask);
timeout = 20;
} else {
dev_dbg(codec->dev, "Calibrating DC servo\n");
snd_soc_write(codec, WM8904_DC_SERVO_1,
dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
timeout = 500;
}
/* Wait for DC servo to complete */
dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
do {
val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0);
if ((val & dcs_mask) == dcs_mask)
break;
msleep(1);
} while (--timeout);
if ((val & dcs_mask) != dcs_mask)
dev_warn(codec->dev, "DC servo timed out\n");
else
dev_dbg(codec->dev, "DC servo ready\n");
/* Enable the output stage */
snd_soc_update_bits(codec, reg,
WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
break;
case SND_SOC_DAPM_POST_PMU:
/* Unshort the output itself */
snd_soc_update_bits(codec, reg,
WM8904_HPL_RMV_SHORT |
WM8904_HPR_RMV_SHORT,
WM8904_HPL_RMV_SHORT |
WM8904_HPR_RMV_SHORT);
break;
case SND_SOC_DAPM_PRE_PMD:
/* Short the output */
snd_soc_update_bits(codec, reg,
WM8904_HPL_RMV_SHORT |
WM8904_HPR_RMV_SHORT, 0);
break;
case SND_SOC_DAPM_POST_PMD:
/* Cache the DC servo configuration; this will be
* invalidated if we change the configuration. */
wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg);
wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg);
snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
dcs_mask, 0);
/* Disable the amplifier input and output stages */
snd_soc_update_bits(codec, reg,
WM8904_HPL_ENA | WM8904_HPR_ENA |
WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
0);
/* PGAs too */
snd_soc_update_bits(codec, pwr_reg,
WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
0);
break;
}
return 0;
}
static const char *lin_text[] = {
"IN1L", "IN2L", "IN3L"
};
static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2,
lin_text);
static const struct snd_kcontrol_new lin_mux =
SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4,
lin_text);
static const struct snd_kcontrol_new lin_inv_mux =
SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
static const char *rin_text[] = {
"IN1R", "IN2R", "IN3R"
};
static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2,
rin_text);
static const struct snd_kcontrol_new rin_mux =
SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4,
rin_text);
static const struct snd_kcontrol_new rin_inv_mux =
SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
static const char *aif_text[] = {
"Left", "Right"
};
static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7,
aif_text);
static const struct snd_kcontrol_new aifoutl_mux =
SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6,
aif_text);
static const struct snd_kcontrol_new aifoutr_mux =
SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5,
aif_text);
static const struct snd_kcontrol_new aifinl_mux =
SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4,
aif_text);
static const struct snd_kcontrol_new aifinr_mux =
SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
};
static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1L"),
SND_SOC_DAPM_INPUT("IN1R"),
SND_SOC_DAPM_INPUT("IN2L"),
SND_SOC_DAPM_INPUT("IN2R"),
SND_SOC_DAPM_INPUT("IN3L"),
SND_SOC_DAPM_INPUT("IN3R"),
SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
&lin_inv_mux),
SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
&rin_inv_mux),
SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
NULL, 0),
SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
NULL, 0),
SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
0, NULL, 0, out_pga_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
0, NULL, 0, out_pga_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("LINEOUTL"),
SND_SOC_DAPM_OUTPUT("LINEOUTR"),
};
static const char *out_mux_text[] = {
"DAC", "Bypass"
};
static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3,
out_mux_text);
static const struct snd_kcontrol_new hpl_mux =
SOC_DAPM_ENUM("HPL Mux", hpl_enum);
static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2,
out_mux_text);
static const struct snd_kcontrol_new hpr_mux =
SOC_DAPM_ENUM("HPR Mux", hpr_enum);
static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1,
out_mux_text);
static const struct snd_kcontrol_new linel_mux =
SOC_DAPM_ENUM("LINEL Mux", linel_enum);
static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0,
out_mux_text);
static const struct snd_kcontrol_new liner_mux =
SOC_DAPM_ENUM("LINER Mux", liner_enum);
static const char *sidetone_text[] = {
"None", "Left", "Right"
};
static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2,
sidetone_text);
static const struct snd_kcontrol_new dacl_sidetone_mux =
SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0,
sidetone_text);
static const struct snd_kcontrol_new dacr_sidetone_mux =
SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
};
static const struct snd_soc_dapm_route core_intercon[] = {
{ "CLK_DSP", NULL, "SYSCLK" },
{ "TOCLK", NULL, "SYSCLK" },
};
static const struct snd_soc_dapm_route adc_intercon[] = {
{ "Left Capture Mux", "IN1L", "IN1L" },
{ "Left Capture Mux", "IN2L", "IN2L" },
{ "Left Capture Mux", "IN3L", "IN3L" },
{ "Left Capture Inverting Mux", "IN1L", "IN1L" },
{ "Left Capture Inverting Mux", "IN2L", "IN2L" },
{ "Left Capture Inverting Mux", "IN3L", "IN3L" },
{ "Right Capture Mux", "IN1R", "IN1R" },
{ "Right Capture Mux", "IN2R", "IN2R" },
{ "Right Capture Mux", "IN3R", "IN3R" },
{ "Right Capture Inverting Mux", "IN1R", "IN1R" },
{ "Right Capture Inverting Mux", "IN2R", "IN2R" },
{ "Right Capture Inverting Mux", "IN3R", "IN3R" },
{ "Left Capture PGA", NULL, "Left Capture Mux" },
{ "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
{ "Right Capture PGA", NULL, "Right Capture Mux" },
{ "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
{ "AIFOUTL Mux", "Left", "ADCL" },
{ "AIFOUTL Mux", "Right", "ADCR" },
{ "AIFOUTR Mux", "Left", "ADCL" },
{ "AIFOUTR Mux", "Right", "ADCR" },
{ "AIFOUTL", NULL, "AIFOUTL Mux" },
{ "AIFOUTR", NULL, "AIFOUTR Mux" },
{ "ADCL", NULL, "CLK_DSP" },
{ "ADCL", NULL, "Left Capture PGA" },
{ "ADCR", NULL, "CLK_DSP" },
{ "ADCR", NULL, "Right Capture PGA" },
};
static const struct snd_soc_dapm_route dac_intercon[] = {
{ "DACL Mux", "Left", "AIFINL" },
{ "DACL Mux", "Right", "AIFINR" },
{ "DACR Mux", "Left", "AIFINL" },
{ "DACR Mux", "Right", "AIFINR" },
{ "DACL", NULL, "DACL Mux" },
{ "DACL", NULL, "CLK_DSP" },
{ "DACR", NULL, "DACR Mux" },
{ "DACR", NULL, "CLK_DSP" },
{ "Charge pump", NULL, "SYSCLK" },
{ "Headphone Output", NULL, "HPL PGA" },
{ "Headphone Output", NULL, "HPR PGA" },
{ "Headphone Output", NULL, "Charge pump" },
{ "Headphone Output", NULL, "TOCLK" },
{ "Line Output", NULL, "LINEL PGA" },
{ "Line Output", NULL, "LINER PGA" },
{ "Line Output", NULL, "Charge pump" },
{ "Line Output", NULL, "TOCLK" },
{ "HPOUTL", NULL, "Headphone Output" },
{ "HPOUTR", NULL, "Headphone Output" },
{ "LINEOUTL", NULL, "Line Output" },
{ "LINEOUTR", NULL, "Line Output" },
};
static const struct snd_soc_dapm_route wm8904_intercon[] = {
{ "Left Sidetone", "Left", "ADCL" },
{ "Left Sidetone", "Right", "ADCR" },
{ "DACL", NULL, "Left Sidetone" },
{ "Right Sidetone", "Left", "ADCL" },
{ "Right Sidetone", "Right", "ADCR" },
{ "DACR", NULL, "Right Sidetone" },
{ "Left Bypass", NULL, "Class G" },
{ "Left Bypass", NULL, "Left Capture PGA" },
{ "Right Bypass", NULL, "Class G" },
{ "Right Bypass", NULL, "Right Capture PGA" },
{ "HPL Mux", "DAC", "DACL" },
{ "HPL Mux", "Bypass", "Left Bypass" },
{ "HPR Mux", "DAC", "DACR" },
{ "HPR Mux", "Bypass", "Right Bypass" },
{ "LINEL Mux", "DAC", "DACL" },
{ "LINEL Mux", "Bypass", "Left Bypass" },
{ "LINER Mux", "DAC", "DACR" },
{ "LINER Mux", "Bypass", "Right Bypass" },
{ "HPL PGA", NULL, "HPL Mux" },
{ "HPR PGA", NULL, "HPR Mux" },
{ "LINEL PGA", NULL, "LINEL Mux" },
{ "LINER PGA", NULL, "LINER Mux" },
};
static const struct snd_soc_dapm_route wm8912_intercon[] = {
{ "HPL PGA", NULL, "DACL" },
{ "HPR PGA", NULL, "DACR" },
{ "LINEL PGA", NULL, "DACL" },
{ "LINER PGA", NULL, "DACR" },
};
static int wm8904_add_widgets(struct snd_soc_codec *codec)
{
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
ARRAY_SIZE(wm8904_core_dapm_widgets));
snd_soc_dapm_add_routes(dapm, core_intercon,
ARRAY_SIZE(core_intercon));
switch (wm8904->devtype) {
case WM8904:
snd_soc_add_codec_controls(codec, wm8904_adc_snd_controls,
ARRAY_SIZE(wm8904_adc_snd_controls));
snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
ARRAY_SIZE(wm8904_dac_snd_controls));
snd_soc_add_codec_controls(codec, wm8904_snd_controls,
ARRAY_SIZE(wm8904_snd_controls));
snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
ARRAY_SIZE(wm8904_adc_dapm_widgets));
snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
ARRAY_SIZE(wm8904_dac_dapm_widgets));
snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
ARRAY_SIZE(wm8904_dapm_widgets));
snd_soc_dapm_add_routes(dapm, adc_intercon,
ARRAY_SIZE(adc_intercon));
snd_soc_dapm_add_routes(dapm, dac_intercon,
ARRAY_SIZE(dac_intercon));
snd_soc_dapm_add_routes(dapm, wm8904_intercon,
ARRAY_SIZE(wm8904_intercon));
break;
case WM8912:
snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
ARRAY_SIZE(wm8904_dac_snd_controls));
snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
ARRAY_SIZE(wm8904_dac_dapm_widgets));
snd_soc_dapm_add_routes(dapm, dac_intercon,
ARRAY_SIZE(dac_intercon));
snd_soc_dapm_add_routes(dapm, wm8912_intercon,
ARRAY_SIZE(wm8912_intercon));
break;
}
return 0;
}
static struct {
int ratio;
unsigned int clk_sys_rate;
} clk_sys_rates[] = {
{ 64, 0 },
{ 128, 1 },
{ 192, 2 },
{ 256, 3 },
{ 384, 4 },
{ 512, 5 },
{ 786, 6 },
{ 1024, 7 },
{ 1408, 8 },
{ 1536, 9 },
};
static struct {
int rate;
int sample_rate;
} sample_rates[] = {
{ 8000, 0 },
{ 11025, 1 },
{ 12000, 1 },
{ 16000, 2 },
{ 22050, 3 },
{ 24000, 3 },
{ 32000, 4 },
{ 44100, 5 },
{ 48000, 5 },
};
static struct {
int div; /* *10 due to .5s */
int bclk_div;
} bclk_divs[] = {
{ 10, 0 },
{ 15, 1 },
{ 20, 2 },
{ 30, 3 },
{ 40, 4 },
{ 50, 5 },
{ 55, 6 },
{ 60, 7 },
{ 80, 8 },
{ 100, 9 },
{ 110, 10 },
{ 120, 11 },
{ 160, 12 },
{ 200, 13 },
{ 220, 14 },
{ 240, 16 },
{ 200, 17 },
{ 320, 18 },
{ 440, 19 },
{ 480, 20 },
};
static int wm8904_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
int ret, i, best, best_val, cur_val;
unsigned int aif1 = 0;
unsigned int aif2 = 0;
unsigned int aif3 = 0;
unsigned int clock1 = 0;
unsigned int dac_digital1 = 0;
/* What BCLK do we need? */
wm8904->fs = params_rate(params);
if (wm8904->tdm_slots) {
dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
wm8904->tdm_slots, wm8904->tdm_width);
wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
wm8904->tdm_width, 2,
wm8904->tdm_slots);
} else {
wm8904->bclk = snd_soc_params_to_bclk(params);
}
switch (params_width(params)) {
case 16:
break;
case 20:
aif1 |= 0x40;
break;
case 24:
aif1 |= 0x80;
break;
case 32:
aif1 |= 0xc0;
break;
default:
return -EINVAL;
}
dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk);
ret = wm8904_configure_clocking(codec);
if (ret != 0)
return ret;
/* Select nearest CLK_SYS_RATE */
best = 0;
best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
- wm8904->fs);
for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
cur_val = abs((wm8904->sysclk_rate /
clk_sys_rates[i].ratio) - wm8904->fs);
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
clk_sys_rates[best].ratio);
clock1 |= (clk_sys_rates[best].clk_sys_rate
<< WM8904_CLK_SYS_RATE_SHIFT);
/* SAMPLE_RATE */
best = 0;
best_val = abs(wm8904->fs - sample_rates[0].rate);
for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
/* Closest match */
cur_val = abs(wm8904->fs - sample_rates[i].rate);
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
sample_rates[best].rate);
clock1 |= (sample_rates[best].sample_rate
<< WM8904_SAMPLE_RATE_SHIFT);
/* Enable sloping stopband filter for low sample rates */
if (wm8904->fs <= 24000)
dac_digital1 |= WM8904_DAC_SB_FILT;
/* BCLK_DIV */
best = 0;
best_val = INT_MAX;
for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
- wm8904->bclk;
if (cur_val < 0) /* Table is sorted */
break;
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
bclk_divs[best].div, wm8904->bclk);
aif2 |= bclk_divs[best].bclk_div;
/* LRCLK is a simple fraction of BCLK */
dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
aif3 |= wm8904->bclk / wm8904->fs;
/* Apply the settings */
snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
WM8904_DAC_SB_FILT, dac_digital1);
snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
WM8904_AIF_WL_MASK, aif1);
snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2,
WM8904_BCLK_DIV_MASK, aif2);
snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
WM8904_LRCLK_RATE_MASK, aif3);
snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1,
WM8904_SAMPLE_RATE_MASK |
WM8904_CLK_SYS_RATE_MASK, clock1);
/* Update filters for the new settings */
wm8904_set_retune_mobile(codec);
wm8904_set_deemph(codec);
return 0;
}
static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_codec *codec = dai->codec;
struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec);
switch (clk_id) {
case WM8904_CLK_MCLK:
priv->sysclk_src = clk_id;
priv->mclk_rate = freq;
break;
case WM8904_CLK_FLL:
priv->sysclk_src = clk_id;
break;
default:
return -EINVAL;
}
dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
wm8904_configure_clocking(codec);
return 0;
}
static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_codec *codec = dai->codec;
unsigned int aif1 = 0;
unsigned int aif3 = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBS_CFM:
aif3 |= WM8904_LRCLK_DIR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
aif1 |= WM8904_BCLK_DIR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
aif1 |= WM8904_BCLK_DIR;
aif3 |= WM8904_LRCLK_DIR;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_B:
aif1 |= 0x3 | WM8904_AIF_LRCLK_INV;
case SND_SOC_DAIFMT_DSP_A:
aif1 |= 0x3;
break;
case SND_SOC_DAIFMT_I2S:
aif1 |= 0x2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aif1 |= 0x1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8904_AIF_BCLK_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8904_AIF_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif1 |= WM8904_AIF_LRCLK_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
WM8904_LRCLK_DIR, aif3);
return 0;
}
static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_codec *codec = dai->codec;
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
int aif1 = 0;
/* Don't need to validate anything if we're turning off TDM */
if (slots == 0)
goto out;
/* Note that we allow configurations we can't handle ourselves -
* for example, we can generate clocks for slots 2 and up even if
* we can't use those slots ourselves.
*/
aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
switch (rx_mask) {
case 3:
break;
case 0xc:
aif1 |= WM8904_AIFADC_TDM_CHAN;
break;
default:
return -EINVAL;
}
switch (tx_mask) {
case 3:
break;
case 0xc:
aif1 |= WM8904_AIFDAC_TDM_CHAN;
break;
default:
return -EINVAL;
}
out:
wm8904->tdm_width = slot_width;
wm8904->tdm_slots = slots / 2;
snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
return 0;
}
struct _fll_div {
u16 fll_fratio;
u16 fll_outdiv;
u16 fll_clk_ref_div;
u16 n;
u16 k;
};
/* The size in bits of the FLL divide multiplied by 10
* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 16) * 10)
static struct {
unsigned int min;
unsigned int max;
u16 fll_fratio;
int ratio;
} fll_fratios[] = {
{ 0, 64000, 4, 16 },
{ 64000, 128000, 3, 8 },
{ 128000, 256000, 2, 4 },
{ 256000, 1000000, 1, 2 },
{ 1000000, 13500000, 0, 1 },
};
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
unsigned int Fout)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod, target;
unsigned int div;
int i;
/* Fref must be <=13.5MHz */
div = 1;
fll_div->fll_clk_ref_div = 0;
while ((Fref / div) > 13500000) {
div *= 2;
fll_div->fll_clk_ref_div++;
if (div > 8) {
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
Fref);
return -EINVAL;
}
}
pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
/* Apply the division for our remaining calculations */
Fref /= div;
/* Fvco should be 90-100MHz; don't check the upper bound */
div = 4;
while (Fout * div < 90000000) {
div++;
if (div > 64) {
pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
Fout);
return -EINVAL;
}
}
target = Fout * div;
fll_div->fll_outdiv = div - 1;
pr_debug("Fvco=%dHz\n", target);
/* Find an appropriate FLL_FRATIO and factor it out of the target */
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
fll_div->fll_fratio = fll_fratios[i].fll_fratio;
target /= fll_fratios[i].ratio;
break;
}
}
if (i == ARRAY_SIZE(fll_fratios)) {
pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
return -EINVAL;
}
/* Now, calculate N.K */
Ndiv = target / Fref;
fll_div->n = Ndiv;
Nmod = target % Fref;
pr_debug("Nmod=%d\n", Nmod);
/* Calculate fractional part - scale up so we can round. */
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
do_div(Kpart, Fref);
K = Kpart & 0xFFFFFFFF;
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
fll_div->k = K / 10;
pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
fll_div->n, fll_div->k,
fll_div->fll_fratio, fll_div->fll_outdiv,
fll_div->fll_clk_ref_div);
return 0;
}
static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
unsigned int Fref, unsigned int Fout)
{
struct snd_soc_codec *codec = dai->codec;
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
struct _fll_div fll_div;
int ret, val;
int clock2, fll1;
/* Any change? */
if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
Fout == wm8904->fll_fout)
return 0;
clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
if (Fout == 0) {
dev_dbg(codec->dev, "FLL disabled\n");
wm8904->fll_fref = 0;
wm8904->fll_fout = 0;
/* Gate SYSCLK to avoid glitches */
snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
WM8904_CLK_SYS_ENA, 0);
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
goto out;
}
/* Validate the FLL ID */
switch (source) {
case WM8904_FLL_MCLK:
case WM8904_FLL_LRCLK:
case WM8904_FLL_BCLK:
ret = fll_factors(&fll_div, Fref, Fout);
if (ret != 0)
return ret;
break;
case WM8904_FLL_FREE_RUNNING:
dev_dbg(codec->dev, "Using free running FLL\n");
/* Force 12MHz and output/4 for now */
Fout = 12000000;
Fref = 12000000;
memset(&fll_div, 0, sizeof(fll_div));
fll_div.fll_outdiv = 3;
break;
default:
dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
return -EINVAL;
}
/* Save current state then disable the FLL and SYSCLK to avoid
* misclocking */
fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1);
snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
WM8904_CLK_SYS_ENA, 0);
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
/* Unlock forced oscilator control to switch it on/off */
snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
WM8904_USER_KEY, WM8904_USER_KEY);
if (fll_id == WM8904_FLL_FREE_RUNNING) {
val = WM8904_FLL_FRC_NCO;
} else {
val = 0;
}
snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
val);
snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
WM8904_USER_KEY, 0);
switch (fll_id) {
case WM8904_FLL_MCLK:
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
WM8904_FLL_CLK_REF_SRC_MASK, 0);
break;
case WM8904_FLL_LRCLK:
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
WM8904_FLL_CLK_REF_SRC_MASK, 1);
break;
case WM8904_FLL_BCLK:
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
WM8904_FLL_CLK_REF_SRC_MASK, 2);
break;
}
if (fll_div.k)
val = WM8904_FLL_FRACN_ENA;
else
val = 0;
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
WM8904_FLL_FRACN_ENA, val);
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2,
WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
(fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
(fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k);
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
fll_div.n << WM8904_FLL_N_SHIFT);
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
WM8904_FLL_CLK_REF_DIV_MASK,
fll_div.fll_clk_ref_div
<< WM8904_FLL_CLK_REF_DIV_SHIFT);
dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
wm8904->fll_fref = Fref;
wm8904->fll_fout = Fout;
wm8904->fll_src = source;
/* Enable the FLL if it was previously active */
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
WM8904_FLL_OSC_ENA, fll1);
snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
WM8904_FLL_ENA, fll1);
out:
/* Reenable SYSCLK if it was previously active */
snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
WM8904_CLK_SYS_ENA, clock2);
return 0;
}
static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
{
struct snd_soc_codec *codec = codec_dai->codec;
int val;
if (mute)
val = WM8904_DAC_MUTE;
else
val = 0;
snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
return 0;
}
static int wm8904_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
ret = clk_prepare_enable(wm8904->mclk);
if (ret)
return ret;
break;
case SND_SOC_BIAS_PREPARE:
/* VMID resistance 2*50k */
snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
WM8904_VMID_RES_MASK,
0x1 << WM8904_VMID_RES_SHIFT);
/* Normal bias current */
snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
wm8904->supplies);
if (ret != 0) {
dev_err(codec->dev,
"Failed to enable supplies: %d\n",
ret);
return ret;
}
regcache_cache_only(wm8904->regmap, false);
regcache_sync(wm8904->regmap);
/* Enable bias */
snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
WM8904_BIAS_ENA, WM8904_BIAS_ENA);
/* Enable VMID, VMID buffering, 2*5k resistance */
snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
WM8904_VMID_ENA |
WM8904_VMID_RES_MASK,
WM8904_VMID_ENA |
0x3 << WM8904_VMID_RES_SHIFT);
/* Let VMID ramp */
msleep(1);
}
/* Maintain VMID with 2*250k */
snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
WM8904_VMID_RES_MASK,
0x2 << WM8904_VMID_RES_SHIFT);
/* Bias current *0.5 */
snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
WM8904_ISEL_MASK, 0);
break;
case SND_SOC_BIAS_OFF:
/* Turn off VMID */
snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
/* Stop bias generation */
snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
WM8904_BIAS_ENA, 0);
regcache_cache_only(wm8904->regmap, true);
regcache_mark_dirty(wm8904->regmap);
regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
wm8904->supplies);
clk_disable_unprepare(wm8904->mclk);
break;
}
return 0;
}
#define WM8904_RATES SNDRV_PCM_RATE_8000_96000
#define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8904_dai_ops = {
.set_sysclk = wm8904_set_sysclk,
.set_fmt = wm8904_set_fmt,
.set_tdm_slot = wm8904_set_tdm_slot,
.set_pll = wm8904_set_fll,
.hw_params = wm8904_hw_params,
.digital_mute = wm8904_digital_mute,
};
static struct snd_soc_dai_driver wm8904_dai = {
.name = "wm8904-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8904_RATES,
.formats = WM8904_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = WM8904_RATES,
.formats = WM8904_FORMATS,
},
.ops = &wm8904_dai_ops,
.symmetric_rates = 1,
};
static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec)
{
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
struct wm8904_pdata *pdata = wm8904->pdata;
struct snd_kcontrol_new control =
SOC_ENUM_EXT("EQ Mode",
wm8904->retune_mobile_enum,
wm8904_get_retune_mobile_enum,
wm8904_put_retune_mobile_enum);
int ret, i, j;
const char **t;
/* We need an array of texts for the enum API but the number
* of texts is likely to be less than the number of
* configurations due to the sample rate dependency of the
* configurations. */
wm8904->num_retune_mobile_texts = 0;
wm8904->retune_mobile_texts = NULL;
for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
if (strcmp(pdata->retune_mobile_cfgs[i].name,
wm8904->retune_mobile_texts[j]) == 0)
break;
}
if (j != wm8904->num_retune_mobile_texts)
continue;
/* Expand the array... */
t = krealloc(wm8904->retune_mobile_texts,
sizeof(char *) *
(wm8904->num_retune_mobile_texts + 1),
GFP_KERNEL);
if (t == NULL)
continue;
/* ...store the new entry... */
t[wm8904->num_retune_mobile_texts] =
pdata->retune_mobile_cfgs[i].name;
/* ...and remember the new version. */
wm8904->num_retune_mobile_texts++;
wm8904->retune_mobile_texts = t;
}
dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
wm8904->num_retune_mobile_texts);
wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts;
wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
ret = snd_soc_add_codec_controls(codec, &control, 1);
if (ret != 0)
dev_err(codec->dev,
"Failed to add ReTune Mobile control: %d\n", ret);
}
static void wm8904_handle_pdata(struct snd_soc_codec *codec)
{
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
struct wm8904_pdata *pdata = wm8904->pdata;
int ret, i;
if (!pdata) {
snd_soc_add_codec_controls(codec, wm8904_eq_controls,
ARRAY_SIZE(wm8904_eq_controls));
return;
}
dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
if (pdata->num_drc_cfgs) {
struct snd_kcontrol_new control =
SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
wm8904_get_drc_enum, wm8904_put_drc_enum);
/* We need an array of texts for the enum API */
wm8904->drc_texts = kmalloc(sizeof(char *)
* pdata->num_drc_cfgs, GFP_KERNEL);
if (!wm8904->drc_texts)
return;
for (i = 0; i < pdata->num_drc_cfgs; i++)
wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
wm8904->drc_enum.items = pdata->num_drc_cfgs;
wm8904->drc_enum.texts = wm8904->drc_texts;
ret = snd_soc_add_codec_controls(codec, &control, 1);
if (ret != 0)
dev_err(codec->dev,
"Failed to add DRC mode control: %d\n", ret);
wm8904_set_drc(codec);
}
dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
pdata->num_retune_mobile_cfgs);
if (pdata->num_retune_mobile_cfgs)
wm8904_handle_retune_mobile_pdata(codec);
else
snd_soc_add_codec_controls(codec, wm8904_eq_controls,
ARRAY_SIZE(wm8904_eq_controls));
}
static int wm8904_probe(struct snd_soc_codec *codec)
{
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
switch (wm8904->devtype) {
case WM8904:
break;
case WM8912:
memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
break;
default:
dev_err(codec->dev, "Unknown device type %d\n",
wm8904->devtype);
return -EINVAL;
}
wm8904_handle_pdata(codec);
wm8904_add_widgets(codec);
return 0;
}
static int wm8904_remove(struct snd_soc_codec *codec)
{
struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
kfree(wm8904->retune_mobile_texts);
kfree(wm8904->drc_texts);
return 0;
}
static const struct snd_soc_codec_driver soc_codec_dev_wm8904 = {
.probe = wm8904_probe,
.remove = wm8904_remove,
.set_bias_level = wm8904_set_bias_level,
.idle_bias_off = true,
};
static const struct regmap_config wm8904_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM8904_MAX_REGISTER,
.volatile_reg = wm8904_volatile_register,
.readable_reg = wm8904_readable_register,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = wm8904_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
};
#ifdef CONFIG_OF
static enum wm8904_type wm8904_data = WM8904;
static enum wm8904_type wm8912_data = WM8912;
static const struct of_device_id wm8904_of_match[] = {
{
.compatible = "wlf,wm8904",
.data = &wm8904_data,
}, {
.compatible = "wlf,wm8912",
.data = &wm8912_data,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, wm8904_of_match);
#endif
static int wm8904_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct wm8904_priv *wm8904;
unsigned int val;
int ret, i;
wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
GFP_KERNEL);
if (wm8904 == NULL)
return -ENOMEM;
wm8904->mclk = devm_clk_get(&i2c->dev, "mclk");
if (IS_ERR(wm8904->mclk)) {
ret = PTR_ERR(wm8904->mclk);
dev_err(&i2c->dev, "Failed to get MCLK\n");
return ret;
}
wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
if (IS_ERR(wm8904->regmap)) {
ret = PTR_ERR(wm8904->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
if (i2c->dev.of_node) {
const struct of_device_id *match;
match = of_match_node(wm8904_of_match, i2c->dev.of_node);
if (match == NULL)
return -EINVAL;
wm8904->devtype = *((enum wm8904_type *)match->data);
} else {
wm8904->devtype = id->driver_data;
}
i2c_set_clientdata(i2c, wm8904);
wm8904->pdata = i2c->dev.platform_data;
for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
wm8904->supplies[i].supply = wm8904_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
wm8904->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
wm8904->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
goto err_enable;
}
if (val != 0x8904) {
dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
ret = -EINVAL;
goto err_enable;
}
ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read device revision: %d\n",
ret);
goto err_enable;
}
dev_info(&i2c->dev, "revision %c\n", val + 'A');
ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
goto err_enable;
}
/* Change some default settings - latch VU and enable ZC */
regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
WM8904_ADC_VU, WM8904_ADC_VU);
regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
WM8904_ADC_VU, WM8904_ADC_VU);
regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
WM8904_DAC_VU, WM8904_DAC_VU);
regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
WM8904_DAC_VU, WM8904_DAC_VU);
regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
WM8904_HPOUT_VU | WM8904_HPOUTLZC,
WM8904_HPOUT_VU | WM8904_HPOUTLZC);
regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
WM8904_HPOUT_VU | WM8904_HPOUTRZC,
WM8904_HPOUT_VU | WM8904_HPOUTRZC);
regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
WM8904_SR_MODE, 0);
/* Apply configuration from the platform data. */
if (wm8904->pdata) {
for (i = 0; i < WM8904_GPIO_REGS; i++) {
if (!wm8904->pdata->gpio_cfg[i])
continue;
regmap_update_bits(wm8904->regmap,
WM8904_GPIO_CONTROL_1 + i,
0xffff,
wm8904->pdata->gpio_cfg[i]);
}
/* Zero is the default value for these anyway */
for (i = 0; i < WM8904_MIC_REGS; i++)
regmap_update_bits(wm8904->regmap,
WM8904_MIC_BIAS_CONTROL_0 + i,
0xffff,
wm8904->pdata->mic_cfg[i]);
}
/* Set Class W by default - this will be managed by the Class
* G widget at runtime where bypass paths are available.
*/
regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
/* Use normal bias source */
regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
WM8904_POBCTRL, 0);
/* Can leave the device powered off until we need it */
regcache_cache_only(wm8904->regmap, true);
regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
ret = snd_soc_register_codec(&i2c->dev,
&soc_codec_dev_wm8904, &wm8904_dai, 1);
if (ret != 0)
return ret;
return 0;
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
return ret;
}
static int wm8904_i2c_remove(struct i2c_client *client)
{
snd_soc_unregister_codec(&client->dev);
return 0;
}
static const struct i2c_device_id wm8904_i2c_id[] = {
{ "wm8904", WM8904 },
{ "wm8912", WM8912 },
{ "wm8918", WM8904 }, /* Actually a subset, updates to follow */
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
static struct i2c_driver wm8904_i2c_driver = {
.driver = {
.name = "wm8904",
.of_match_table = of_match_ptr(wm8904_of_match),
},
.probe = wm8904_i2c_probe,
.remove = wm8904_i2c_remove,
.id_table = wm8904_i2c_id,
};
module_i2c_driver(wm8904_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8904 driver");
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
MODULE_LICENSE("GPL");
| null | null | null | null | 79,086 |
61,528 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 61,528 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2012 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chrome/browser/plugins/plugin_prefs_factory.h"
#include "base/path_service.h"
#include "chrome/browser/plugins/plugin_prefs.h"
#include "chrome/browser/profiles/incognito_helpers.h"
#include "chrome/browser/profiles/profile.h"
#include "chrome/common/chrome_paths.h"
#include "chrome/common/pref_names.h"
#include "components/keyed_service/content/browser_context_dependency_manager.h"
#include "components/keyed_service/core/keyed_service.h"
#include "components/pref_registry/pref_registry_syncable.h"
#include "components/prefs/pref_service.h"
// static
PluginPrefsFactory* PluginPrefsFactory::GetInstance() {
return base::Singleton<PluginPrefsFactory>::get();
}
// static
scoped_refptr<PluginPrefs> PluginPrefsFactory::GetPrefsForProfile(
Profile* profile) {
return static_cast<PluginPrefs*>(
GetInstance()->GetServiceForBrowserContext(profile, true).get());
}
// static
scoped_refptr<RefcountedKeyedService>
PluginPrefsFactory::CreateForTestingProfile(content::BrowserContext* profile) {
return static_cast<PluginPrefs*>(
GetInstance()->BuildServiceInstanceFor(profile).get());
}
PluginPrefsFactory::PluginPrefsFactory()
: RefcountedBrowserContextKeyedServiceFactory(
"PluginPrefs", BrowserContextDependencyManager::GetInstance()) {
}
PluginPrefsFactory::~PluginPrefsFactory() {}
scoped_refptr<RefcountedKeyedService>
PluginPrefsFactory::BuildServiceInstanceFor(
content::BrowserContext* context) const {
Profile* profile = static_cast<Profile*>(context);
scoped_refptr<PluginPrefs> plugin_prefs(new PluginPrefs());
plugin_prefs->set_profile(profile->GetOriginalProfile());
plugin_prefs->SetPrefs(profile->GetPrefs());
return plugin_prefs;
}
void PluginPrefsFactory::RegisterProfilePrefs(
user_prefs::PrefRegistrySyncable* registry) {
base::FilePath internal_dir;
PathService::Get(chrome::DIR_INTERNAL_PLUGINS, &internal_dir);
registry->RegisterFilePathPref(prefs::kPluginsLastInternalDirectory,
internal_dir);
registry->RegisterListPref(prefs::kPluginsPluginsList);
registry->RegisterListPref(prefs::kPluginsDisabledPlugins);
registry->RegisterListPref(prefs::kPluginsDisabledPluginsExceptions);
registry->RegisterListPref(prefs::kPluginsEnabledPlugins);
registry->RegisterBooleanPref(prefs::kPluginsAlwaysOpenPdfExternally, false);
}
content::BrowserContext* PluginPrefsFactory::GetBrowserContextToUse(
content::BrowserContext* context) const {
return chrome::GetBrowserContextRedirectedInIncognito(context);
}
bool PluginPrefsFactory::ServiceIsNULLWhileTesting() const {
return true;
}
bool PluginPrefsFactory::ServiceIsCreatedWithBrowserContext() const {
return true;
}
| null | null | null | null | 58,391 |
56,388 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 56,388 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2012 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef CHROME_BROWSER_CHROMEOS_LOGIN_ENROLLMENT_ENROLLMENT_SCREEN_H_
#define CHROME_BROWSER_CHROMEOS_LOGIN_ENROLLMENT_ENROLLMENT_SCREEN_H_
#include <memory>
#include <string>
#include "base/callback_forward.h"
#include "base/cancelable_callback.h"
#include "base/compiler_specific.h"
#include "base/gtest_prod_util.h"
#include "base/macros.h"
#include "base/memory/weak_ptr.h"
#include "chrome/browser/chromeos/login/enrollment/enrollment_screen_view.h"
#include "chrome/browser/chromeos/login/enrollment/enterprise_enrollment_helper.h"
#include "chrome/browser/chromeos/login/screens/base_screen.h"
#include "chrome/browser/chromeos/policy/active_directory_join_delegate.h"
#include "chrome/browser/chromeos/policy/enrollment_config.h"
#include "components/policy/core/common/cloud/cloud_policy_constants.h"
#include "components/policy/core/common/cloud/enterprise_metrics.h"
#include "net/base/backoff_entry.h"
namespace base {
class ElapsedTimer;
}
namespace pairing_chromeos {
class ControllerPairingController;
}
namespace chromeos {
class BaseScreenDelegate;
class ScreenManager;
// The screen implementation that links the enterprise enrollment UI into the
// OOBE wizard.
class EnrollmentScreen
: public BaseScreen,
public EnterpriseEnrollmentHelper::EnrollmentStatusConsumer,
public EnrollmentScreenView::Controller,
public ActiveDirectoryJoinDelegate {
public:
EnrollmentScreen(BaseScreenDelegate* base_screen_delegate,
EnrollmentScreenView* view);
~EnrollmentScreen() override;
static EnrollmentScreen* Get(ScreenManager* manager);
// Setup how this screen will handle enrollment.
// |shark_controller| is an interface that is used to communicate with a
// remora device or a slave device for remote enrollment.
void SetParameters(
const policy::EnrollmentConfig& enrollment_config,
pairing_chromeos::ControllerPairingController* shark_controller);
// BaseScreen implementation:
void Show() override;
void Hide() override;
// EnrollmentScreenView::Controller implementation:
void OnLoginDone(const std::string& user,
const std::string& auth_code) override;
void OnLicenseTypeSelected(const std::string& license_type) override;
void OnRetry() override;
void OnCancel() override;
void OnConfirmationClosed() override;
void OnAdJoined(const std::string& realm) override;
void OnDeviceAttributeProvided(const std::string& asset_id,
const std::string& location) override;
// EnterpriseEnrollmentHelper::EnrollmentStatusConsumer implementation:
void OnAuthError(const GoogleServiceAuthError& error) override;
void OnMultipleLicensesAvailable(
const EnrollmentLicenseMap& licenses) override;
void OnEnrollmentError(policy::EnrollmentStatus status) override;
void OnOtherError(EnterpriseEnrollmentHelper::OtherError error) override;
void OnDeviceEnrolled(const std::string& additional_token) override;
void OnDeviceAttributeUploadCompleted(bool success) override;
void OnDeviceAttributeUpdatePermission(bool granted) override;
// ActiveDirectoryJoinDelegate implementation:
void JoinDomain(OnDomainJoinedCallback on_joined_callback) override;
// Used for testing.
EnrollmentScreenView* GetView() { return view_; }
private:
friend class MultiLicenseEnrollmentScreenUnitTest;
friend class ZeroTouchEnrollmentScreenUnitTest;
friend class AutomaticReenrollmentScreenUnitTest;
FRIEND_TEST_ALL_PREFIXES(AttestationAuthEnrollmentScreenTest, TestCancel);
FRIEND_TEST_ALL_PREFIXES(ForcedAttestationAuthEnrollmentScreenTest,
TestCancel);
FRIEND_TEST_ALL_PREFIXES(MultiAuthEnrollmentScreenTest, TestCancel);
FRIEND_TEST_ALL_PREFIXES(EnterpriseEnrollmentTest,
TestProperPageGetsLoadedOnEnrollmentSuccess);
FRIEND_TEST_ALL_PREFIXES(EnterpriseEnrollmentTest,
TestAttributePromptPageGetsLoaded);
FRIEND_TEST_ALL_PREFIXES(EnterpriseEnrollmentTest,
TestAuthCodeGetsProperlyReceivedFromGaia);
FRIEND_TEST_ALL_PREFIXES(EnterpriseEnrollmentTest,
TestActiveDirectoryEnrollment_Success);
FRIEND_TEST_ALL_PREFIXES(EnterpriseEnrollmentTest,
TestActiveDirectoryEnrollment_DistinguishedName);
FRIEND_TEST_ALL_PREFIXES(EnterpriseEnrollmentTest,
TestActiveDirectoryEnrollment_UIErrors);
FRIEND_TEST_ALL_PREFIXES(HandsOffNetworkScreenTest, RequiresNoInput);
FRIEND_TEST_ALL_PREFIXES(HandsOffNetworkScreenTest, ContinueClickedOnlyOnce);
FRIEND_TEST_ALL_PREFIXES(ZeroTouchEnrollmentScreenUnitTest, Retry);
FRIEND_TEST_ALL_PREFIXES(ZeroTouchEnrollmentScreenUnitTest, TestSuccess);
FRIEND_TEST_ALL_PREFIXES(ZeroTouchEnrollmentScreenUnitTest,
DoNotRetryOnTopOfUser);
FRIEND_TEST_ALL_PREFIXES(ZeroTouchEnrollmentScreenUnitTest,
DoNotRetryAfterSuccess);
// The authentication mechanisms that this class can use.
enum Auth {
AUTH_ATTESTATION,
AUTH_OAUTH,
};
// Sets the current config to use for enrollment.
void SetConfig();
// Creates an enrollment helper if needed.
void CreateEnrollmentHelper();
// Clears auth in |enrollment_helper_|. Deletes |enrollment_helper_| and runs
// |callback| on completion. See the comment for
// EnterpriseEnrollmentHelper::ClearAuth for details.
void ClearAuth(const base::Closure& callback);
// Used as a callback for EnterpriseEnrollmentHelper::ClearAuth.
virtual void OnAuthCleared(const base::Closure& callback);
// Sends an enrollment access token to a remote device.
void SendEnrollmentAuthToken(const std::string& token);
// Shows successful enrollment status after all enrollment related file
// operations are completed.
void ShowEnrollmentStatusOnSuccess();
// Logs an UMA event in one of the "Enrollment.*" histograms, depending on
// |enrollment_mode_|.
void UMA(policy::MetricEnrollment sample);
// Do attestation based enrollment.
void AuthenticateUsingAttestation();
// Shows the interactive screen. Resets auth then shows the signin screen.
void ShowInteractiveScreen();
// Shows the signin screen. Used as a callback to run after auth reset.
void ShowSigninScreen();
// Shows the device attribute prompt screen.
// Used as a callback to run after successful enrollment.
void ShowAttributePromptScreen();
// Record metrics when we encounter an enrollment error.
void RecordEnrollmentErrorMetrics();
// Advance to the next authentication mechanism if possible.
bool AdvanceToNextAuth();
// Similar to OnRetry(), but responds to a timer instead of the user
// pressing the Retry button.
void AutomaticRetry();
// Processes a request to retry enrollment.
// Called by OnRetry() and AutomaticRetry().
void ProcessRetry();
pairing_chromeos::ControllerPairingController* shark_controller_ = nullptr;
EnrollmentScreenView* view_;
policy::EnrollmentConfig config_;
policy::EnrollmentConfig enrollment_config_;
Auth current_auth_ = AUTH_OAUTH;
Auth last_auth_ = AUTH_OAUTH;
bool enrollment_failed_once_ = false;
std::string enrolling_user_domain_;
std::unique_ptr<base::ElapsedTimer> elapsed_timer_;
net::BackoffEntry::Policy retry_policy_;
std::unique_ptr<net::BackoffEntry> retry_backoff_;
base::CancelableClosure retry_task_;
int num_retries_ = 0;
std::unique_ptr<EnterpriseEnrollmentHelper> enrollment_helper_;
OnDomainJoinedCallback on_joined_callback_;
base::WeakPtrFactory<EnrollmentScreen> weak_ptr_factory_;
DISALLOW_COPY_AND_ASSIGN(EnrollmentScreen);
};
} // namespace chromeos
#endif // CHROME_BROWSER_CHROMEOS_LOGIN_ENROLLMENT_ENROLLMENT_SCREEN_H_
| null | null | null | null | 53,251 |
69,681 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 69,681 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include <math.h>
#include <stdio.h>
#include <string.h>
#include <algorithm>
#include <deque>
#include <iostream>
#include <map>
#include <sstream>
#include <vector>
#include "ppapi/c/pp_errors.h"
#include "ppapi/c/ppb_console.h"
#include "ppapi/cpp/input_event.h"
#include "ppapi/cpp/instance.h"
#include "ppapi/cpp/media_stream_video_track.h"
#include "ppapi/cpp/module.h"
#include "ppapi/cpp/rect.h"
#include "ppapi/cpp/var.h"
#include "ppapi/cpp/var_array_buffer.h"
#include "ppapi/cpp/var_dictionary.h"
#include "ppapi/cpp/video_encoder.h"
#include "ppapi/cpp/video_frame.h"
#include "ppapi/utility/completion_callback_factory.h"
// When compiling natively on Windows, PostMessage, min and max can be
// #define-d to something else.
#ifdef WIN32
#undef min
#undef max
#undef PostMessage
#endif
// Use assert as a makeshift CHECK, even in non-debug mode.
// Since <assert.h> redefines assert on every inclusion (it doesn't use
// include-guards), make sure this is the last file #include'd in this file.
#undef NDEBUG
#include <assert.h>
#define fourcc(a, b, c, d) \
(((uint32_t)(a) << 0) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | \
((uint32_t)(d) << 24))
namespace {
double clamp(double min, double max, double value) {
return std::max(std::min(value, max), min);
}
std::string ToUpperString(const std::string& str) {
std::string ret;
for (uint32_t i = 0; i < str.size(); i++)
ret.push_back(static_cast<char>(toupper(str[i])));
return ret;
}
// IVF container writer. It is possible to parse H264 bitstream using
// NAL units but for VP8 we need a container to at least find encoded
// pictures as well as the picture sizes.
class IVFWriter {
public:
IVFWriter() {}
~IVFWriter() {}
uint32_t GetFileHeaderSize() const { return 32; }
uint32_t GetFrameHeaderSize() const { return 12; }
uint32_t WriteFileHeader(uint8_t* mem,
const std::string& codec,
int32_t width,
int32_t height);
uint32_t WriteFrameHeader(uint8_t* mem, uint64_t pts, size_t frame_size);
private:
void PutLE16(uint8_t* mem, int val) const {
mem[0] = (val >> 0) & 0xff;
mem[1] = (val >> 8) & 0xff;
}
void PutLE32(uint8_t* mem, int val) const {
mem[0] = (val >> 0) & 0xff;
mem[1] = (val >> 8) & 0xff;
mem[2] = (val >> 16) & 0xff;
mem[3] = (val >> 24) & 0xff;
}
};
uint32_t IVFWriter::WriteFileHeader(uint8_t* mem,
const std::string& codec,
int32_t width,
int32_t height) {
mem[0] = 'D';
mem[1] = 'K';
mem[2] = 'I';
mem[3] = 'F';
PutLE16(mem + 4, 0); // version
PutLE16(mem + 6, 32); // header size
PutLE32(mem + 8, fourcc(codec[0], codec[1], codec[2], '0')); // fourcc
PutLE16(mem + 12, static_cast<uint16_t>(width)); // width
PutLE16(mem + 14, static_cast<uint16_t>(height)); // height
PutLE32(mem + 16, 1000); // rate
PutLE32(mem + 20, 1); // scale
PutLE32(mem + 24, 0xffffffff); // length
PutLE32(mem + 28, 0); // unused
return 32;
}
uint32_t IVFWriter::WriteFrameHeader(uint8_t* mem,
uint64_t pts,
size_t frame_size) {
PutLE32(mem, (int)frame_size);
PutLE32(mem + 4, (int)(pts & 0xFFFFFFFF));
PutLE32(mem + 8, (int)(pts >> 32));
return 12;
}
// This object is the global object representing this plugin library as long
// as it is loaded.
class VideoEncoderModule : public pp::Module {
public:
VideoEncoderModule() : pp::Module() {}
virtual ~VideoEncoderModule() {}
virtual pp::Instance* CreateInstance(PP_Instance instance);
};
class VideoEncoderInstance : public pp::Instance {
public:
VideoEncoderInstance(PP_Instance instance, pp::Module* module);
virtual ~VideoEncoderInstance();
// pp::Instance implementation.
virtual void HandleMessage(const pp::Var& var_message);
private:
void AddVideoProfile(PP_VideoProfile profile, const std::string& profile_str);
void InitializeVideoProfiles();
PP_VideoProfile VideoProfileFromString(const std::string& str);
std::string VideoProfileToString(PP_VideoProfile profile);
void ConfigureTrack();
void OnConfiguredTrack(int32_t result);
void ProbeEncoder();
void OnEncoderProbed(int32_t result,
const std::vector<PP_VideoProfileDescription> profiles);
void StartEncoder();
void OnInitializedEncoder(int32_t result);
void ScheduleNextEncode();
void GetEncoderFrameTick(int32_t result);
void GetEncoderFrame(const pp::VideoFrame& track_frame);
void OnEncoderFrame(int32_t result,
pp::VideoFrame encoder_frame,
pp::VideoFrame track_frame);
int32_t CopyVideoFrame(pp::VideoFrame dest, pp::VideoFrame src);
void EncodeFrame(const pp::VideoFrame& frame);
void OnEncodeDone(int32_t result);
void OnGetBitstreamBuffer(int32_t result, PP_BitstreamBuffer buffer);
void StartTrackFrames();
void StopTrackFrames();
void OnTrackFrame(int32_t result, pp::VideoFrame frame);
void StopEncode();
void LogError(int32_t error, const std::string& message);
void Log(const std::string& message);
void PostDataMessage(const void* buffer, uint32_t size);
typedef std::map<std::string, PP_VideoProfile> VideoProfileFromStringMap;
VideoProfileFromStringMap profile_from_string_;
typedef std::map<PP_VideoProfile, std::string> VideoProfileToStringMap;
VideoProfileToStringMap profile_to_string_;
bool is_encoding_;
bool is_encode_ticking_;
bool is_receiving_track_frames_;
pp::VideoEncoder video_encoder_;
pp::MediaStreamVideoTrack video_track_;
pp::CompletionCallbackFactory<VideoEncoderInstance> callback_factory_;
PP_VideoProfile video_profile_;
PP_VideoFrame_Format frame_format_;
pp::Size requested_size_;
pp::Size frame_size_;
pp::Size encoder_size_;
uint32_t encoded_frames_;
std::deque<uint64_t> frames_timestamps_;
pp::VideoFrame current_track_frame_;
IVFWriter ivf_writer_;
PP_Time last_encode_tick_;
};
VideoEncoderInstance::VideoEncoderInstance(PP_Instance instance,
pp::Module* module)
: pp::Instance(instance),
is_encoding_(false),
is_encode_ticking_(false),
callback_factory_(this),
#if defined(USE_VP8_INSTEAD_OF_H264)
video_profile_(PP_VIDEOPROFILE_VP8_ANY),
#else
video_profile_(PP_VIDEOPROFILE_H264MAIN),
#endif
frame_format_(PP_VIDEOFRAME_FORMAT_I420),
encoded_frames_(0),
last_encode_tick_(0) {
InitializeVideoProfiles();
ProbeEncoder();
}
VideoEncoderInstance::~VideoEncoderInstance() {
}
void VideoEncoderInstance::AddVideoProfile(PP_VideoProfile profile,
const std::string& profile_str) {
profile_to_string_.insert(std::make_pair(profile, profile_str));
profile_from_string_.insert(std::make_pair(profile_str, profile));
}
void VideoEncoderInstance::InitializeVideoProfiles() {
AddVideoProfile(PP_VIDEOPROFILE_H264BASELINE, "h264baseline");
AddVideoProfile(PP_VIDEOPROFILE_H264MAIN, "h264main");
AddVideoProfile(PP_VIDEOPROFILE_H264EXTENDED, "h264extended");
AddVideoProfile(PP_VIDEOPROFILE_H264HIGH, "h264high");
AddVideoProfile(PP_VIDEOPROFILE_H264HIGH10PROFILE, "h264high10");
AddVideoProfile(PP_VIDEOPROFILE_H264HIGH422PROFILE, "h264high422");
AddVideoProfile(PP_VIDEOPROFILE_H264HIGH444PREDICTIVEPROFILE,
"h264high444predictive");
AddVideoProfile(PP_VIDEOPROFILE_H264SCALABLEBASELINE, "h264scalablebaseline");
AddVideoProfile(PP_VIDEOPROFILE_H264SCALABLEHIGH, "h264scalablehigh");
AddVideoProfile(PP_VIDEOPROFILE_H264STEREOHIGH, "h264stereohigh");
AddVideoProfile(PP_VIDEOPROFILE_H264MULTIVIEWHIGH, "h264multiviewhigh");
AddVideoProfile(PP_VIDEOPROFILE_VP8_ANY, "vp8");
AddVideoProfile(PP_VIDEOPROFILE_VP9_ANY, "vp9");
}
PP_VideoProfile VideoEncoderInstance::VideoProfileFromString(
const std::string& str) {
VideoProfileFromStringMap::iterator it = profile_from_string_.find(str);
if (it == profile_from_string_.end())
return PP_VIDEOPROFILE_VP8_ANY;
return it->second;
}
std::string VideoEncoderInstance::VideoProfileToString(
PP_VideoProfile profile) {
VideoProfileToStringMap::iterator it = profile_to_string_.find(profile);
if (it == profile_to_string_.end())
return "unknown";
return it->second;
}
void VideoEncoderInstance::ConfigureTrack() {
if (encoder_size_.IsEmpty())
frame_size_ = requested_size_;
else
frame_size_ = encoder_size_;
int32_t attrib_list[] = {PP_MEDIASTREAMVIDEOTRACK_ATTRIB_FORMAT,
frame_format_,
PP_MEDIASTREAMVIDEOTRACK_ATTRIB_WIDTH,
frame_size_.width(),
PP_MEDIASTREAMVIDEOTRACK_ATTRIB_HEIGHT,
frame_size_.height(),
PP_MEDIASTREAMVIDEOTRACK_ATTRIB_NONE};
video_track_.Configure(
attrib_list,
callback_factory_.NewCallback(&VideoEncoderInstance::OnConfiguredTrack));
}
void VideoEncoderInstance::OnConfiguredTrack(int32_t result) {
if (result != PP_OK) {
LogError(result, "Cannot configure track");
return;
}
if (is_encoding_) {
StartTrackFrames();
ScheduleNextEncode();
} else
StartEncoder();
}
void VideoEncoderInstance::ProbeEncoder() {
video_encoder_ = pp::VideoEncoder(this);
video_encoder_.GetSupportedProfiles(callback_factory_.NewCallbackWithOutput(
&VideoEncoderInstance::OnEncoderProbed));
}
void VideoEncoderInstance::OnEncoderProbed(
int32_t result,
const std::vector<PP_VideoProfileDescription> profiles) {
pp::VarDictionary dict;
dict.Set(pp::Var("name"), pp::Var("supportedProfiles"));
pp::VarArray js_profiles;
dict.Set(pp::Var("profiles"), js_profiles);
if (result < 0) {
LogError(result, "Cannot get supported profiles");
PostMessage(dict);
}
int32_t idx = 0;
for (uint32_t i = 0; i < profiles.size(); i++) {
const PP_VideoProfileDescription& profile = profiles[i];
js_profiles.Set(idx++, pp::Var(VideoProfileToString(profile.profile)));
}
PostMessage(dict);
}
void VideoEncoderInstance::StartEncoder() {
video_encoder_ = pp::VideoEncoder(this);
frames_timestamps_.clear();
int32_t error = video_encoder_.Initialize(
frame_format_, frame_size_, video_profile_, 2000000,
PP_HARDWAREACCELERATION_WITHFALLBACK,
callback_factory_.NewCallback(
&VideoEncoderInstance::OnInitializedEncoder));
if (error != PP_OK_COMPLETIONPENDING) {
LogError(error, "Cannot initialize encoder");
return;
}
}
void VideoEncoderInstance::OnInitializedEncoder(int32_t result) {
if (result != PP_OK) {
LogError(result, "Encoder initialization failed");
return;
}
is_encoding_ = true;
Log("started");
if (video_encoder_.GetFrameCodedSize(&encoder_size_) != PP_OK) {
LogError(result, "Cannot get encoder coded frame size");
return;
}
video_encoder_.GetBitstreamBuffer(callback_factory_.NewCallbackWithOutput(
&VideoEncoderInstance::OnGetBitstreamBuffer));
if (encoder_size_ != frame_size_)
ConfigureTrack();
else {
StartTrackFrames();
ScheduleNextEncode();
}
}
void VideoEncoderInstance::ScheduleNextEncode() {
// Avoid scheduling more than once at a time.
if (is_encode_ticking_)
return;
PP_Time now = pp::Module::Get()->core()->GetTime();
PP_Time tick = 1.0 / 30;
// If the callback was triggered late, we need to account for that
// delay for the next tick.
PP_Time delta = tick - clamp(0, tick, now - last_encode_tick_ - tick);
pp::Module::Get()->core()->CallOnMainThread(
delta * 1000,
callback_factory_.NewCallback(&VideoEncoderInstance::GetEncoderFrameTick),
0);
last_encode_tick_ = now;
is_encode_ticking_ = true;
}
void VideoEncoderInstance::GetEncoderFrameTick(int32_t result) {
is_encode_ticking_ = false;
if (is_encoding_) {
if (!current_track_frame_.is_null()) {
pp::VideoFrame frame = current_track_frame_;
current_track_frame_.detach();
GetEncoderFrame(frame);
}
ScheduleNextEncode();
}
}
void VideoEncoderInstance::GetEncoderFrame(const pp::VideoFrame& track_frame) {
video_encoder_.GetVideoFrame(callback_factory_.NewCallbackWithOutput(
&VideoEncoderInstance::OnEncoderFrame, track_frame));
}
void VideoEncoderInstance::OnEncoderFrame(int32_t result,
pp::VideoFrame encoder_frame,
pp::VideoFrame track_frame) {
if (result == PP_ERROR_ABORTED) {
video_track_.RecycleFrame(track_frame);
return;
}
if (result != PP_OK) {
video_track_.RecycleFrame(track_frame);
LogError(result, "Cannot get video frame from video encoder");
return;
}
track_frame.GetSize(&frame_size_);
if (frame_size_ != encoder_size_) {
video_track_.RecycleFrame(track_frame);
LogError(PP_ERROR_FAILED, "MediaStreamVideoTrack frame size incorrect");
return;
}
if (CopyVideoFrame(encoder_frame, track_frame) == PP_OK)
EncodeFrame(encoder_frame);
video_track_.RecycleFrame(track_frame);
}
int32_t VideoEncoderInstance::CopyVideoFrame(pp::VideoFrame dest,
pp::VideoFrame src) {
if (dest.GetDataBufferSize() < src.GetDataBufferSize()) {
std::ostringstream oss;
oss << "Incorrect destination video frame buffer size : "
<< dest.GetDataBufferSize() << " < " << src.GetDataBufferSize();
LogError(PP_ERROR_FAILED, oss.str());
return PP_ERROR_FAILED;
}
dest.SetTimestamp(src.GetTimestamp());
memcpy(dest.GetDataBuffer(), src.GetDataBuffer(), src.GetDataBufferSize());
return PP_OK;
}
void VideoEncoderInstance::EncodeFrame(const pp::VideoFrame& frame) {
frames_timestamps_.push_back(
static_cast<uint64_t>(frame.GetTimestamp() * 1000));
video_encoder_.Encode(
frame, PP_FALSE,
callback_factory_.NewCallback(&VideoEncoderInstance::OnEncodeDone));
}
void VideoEncoderInstance::OnEncodeDone(int32_t result) {
if (result == PP_ERROR_ABORTED)
return;
if (result != PP_OK)
LogError(result, "Encode failed");
}
void VideoEncoderInstance::OnGetBitstreamBuffer(int32_t result,
PP_BitstreamBuffer buffer) {
if (result == PP_ERROR_ABORTED)
return;
if (result != PP_OK) {
LogError(result, "Cannot get bitstream buffer");
return;
}
encoded_frames_++;
PostDataMessage(buffer.buffer, buffer.size);
video_encoder_.RecycleBitstreamBuffer(buffer);
video_encoder_.GetBitstreamBuffer(callback_factory_.NewCallbackWithOutput(
&VideoEncoderInstance::OnGetBitstreamBuffer));
}
void VideoEncoderInstance::StartTrackFrames() {
is_receiving_track_frames_ = true;
video_track_.GetFrame(callback_factory_.NewCallbackWithOutput(
&VideoEncoderInstance::OnTrackFrame));
}
void VideoEncoderInstance::StopTrackFrames() {
is_receiving_track_frames_ = false;
if (!current_track_frame_.is_null()) {
video_track_.RecycleFrame(current_track_frame_);
current_track_frame_.detach();
}
}
void VideoEncoderInstance::OnTrackFrame(int32_t result, pp::VideoFrame frame) {
if (result == PP_ERROR_ABORTED)
return;
if (!current_track_frame_.is_null()) {
video_track_.RecycleFrame(current_track_frame_);
current_track_frame_.detach();
}
if (result != PP_OK) {
LogError(result, "Cannot get video frame from video track");
return;
}
current_track_frame_ = frame;
if (is_receiving_track_frames_)
video_track_.GetFrame(callback_factory_.NewCallbackWithOutput(
&VideoEncoderInstance::OnTrackFrame));
}
void VideoEncoderInstance::StopEncode() {
video_encoder_.Close();
StopTrackFrames();
video_track_.Close();
is_encoding_ = false;
encoded_frames_ = 0;
}
//
void VideoEncoderInstance::HandleMessage(const pp::Var& var_message) {
if (!var_message.is_dictionary()) {
LogToConsole(PP_LOGLEVEL_ERROR, pp::Var("Invalid message!"));
return;
}
pp::VarDictionary dict_message(var_message);
std::string command = dict_message.Get("command").AsString();
if (command == "start") {
requested_size_ = pp::Size(dict_message.Get("width").AsInt(),
dict_message.Get("height").AsInt());
pp::Var var_track = dict_message.Get("track");
if (!var_track.is_resource()) {
LogToConsole(PP_LOGLEVEL_ERROR, pp::Var("Given track is not a resource"));
return;
}
pp::Resource resource_track = var_track.AsResource();
video_track_ = pp::MediaStreamVideoTrack(resource_track);
video_encoder_ = pp::VideoEncoder();
video_profile_ = VideoProfileFromString(
dict_message.Get("profile").AsString());
ConfigureTrack();
} else if (command == "stop") {
StopEncode();
Log("stopped");
} else {
LogToConsole(PP_LOGLEVEL_ERROR, pp::Var("Invalid command!"));
}
}
void VideoEncoderInstance::PostDataMessage(const void* buffer, uint32_t size) {
pp::VarDictionary dictionary;
dictionary.Set(pp::Var("name"), pp::Var("data"));
pp::VarArrayBuffer array_buffer;
uint8_t* data_ptr;
uint32_t data_offset = 0;
if (video_profile_ == PP_VIDEOPROFILE_VP8_ANY ||
video_profile_ == PP_VIDEOPROFILE_VP9_ANY) {
uint32_t frame_offset = 0;
if (encoded_frames_ == 1) {
array_buffer = pp::VarArrayBuffer(
size + ivf_writer_.GetFileHeaderSize() +
ivf_writer_.GetFrameHeaderSize());
data_ptr = static_cast<uint8_t*>(array_buffer.Map());
frame_offset = ivf_writer_.WriteFileHeader(
data_ptr, ToUpperString(VideoProfileToString(video_profile_)),
frame_size_.width(), frame_size_.height());
} else {
array_buffer = pp::VarArrayBuffer(
size + ivf_writer_.GetFrameHeaderSize());
data_ptr = static_cast<uint8_t*>(array_buffer.Map());
}
uint64_t timestamp = frames_timestamps_.front();
frames_timestamps_.pop_front();
data_offset =
frame_offset +
ivf_writer_.WriteFrameHeader(data_ptr + frame_offset, timestamp, size);
} else {
array_buffer = pp::VarArrayBuffer(size);
data_ptr = static_cast<uint8_t*>(array_buffer.Map());
}
memcpy(data_ptr + data_offset, buffer, size);
array_buffer.Unmap();
dictionary.Set(pp::Var("data"), array_buffer);
PostMessage(dictionary);
}
void VideoEncoderInstance::LogError(int32_t error, const std::string& message) {
std::string msg("Error: ");
msg.append(pp::Var(error).DebugString());
msg.append(" : ");
msg.append(message);
Log(msg);
}
void VideoEncoderInstance::Log(const std::string& message) {
pp::VarDictionary dictionary;
dictionary.Set(pp::Var("name"), pp::Var("log"));
dictionary.Set(pp::Var("message"), pp::Var(message));
PostMessage(dictionary);
}
pp::Instance* VideoEncoderModule::CreateInstance(PP_Instance instance) {
return new VideoEncoderInstance(instance, this);
}
} // anonymous namespace
namespace pp {
// Factory function for your specialization of the Module object.
Module* CreateModule() {
return new VideoEncoderModule();
}
} // namespace pp
| null | null | null | null | 66,544 |
37,066 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 202,061 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <soc/imx/revision.h>
#include <dt-bindings/clock/imx5-clock.h>
#include "clk.h"
#define MX51_DPLL1_BASE 0x83f80000
#define MX51_DPLL2_BASE 0x83f84000
#define MX51_DPLL3_BASE 0x83f88000
#define MX53_DPLL1_BASE 0x63f80000
#define MX53_DPLL2_BASE 0x63f84000
#define MX53_DPLL3_BASE 0x63f88000
#define MX53_DPLL4_BASE 0x63f8c000
#define MXC_CCM_CCR (ccm_base + 0x00)
#define MXC_CCM_CCDR (ccm_base + 0x04)
#define MXC_CCM_CSR (ccm_base + 0x08)
#define MXC_CCM_CCSR (ccm_base + 0x0c)
#define MXC_CCM_CACRR (ccm_base + 0x10)
#define MXC_CCM_CBCDR (ccm_base + 0x14)
#define MXC_CCM_CBCMR (ccm_base + 0x18)
#define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
#define MXC_CCM_CSCMR2 (ccm_base + 0x20)
#define MXC_CCM_CSCDR1 (ccm_base + 0x24)
#define MXC_CCM_CS1CDR (ccm_base + 0x28)
#define MXC_CCM_CS2CDR (ccm_base + 0x2c)
#define MXC_CCM_CDCDR (ccm_base + 0x30)
#define MXC_CCM_CHSCDR (ccm_base + 0x34)
#define MXC_CCM_CSCDR2 (ccm_base + 0x38)
#define MXC_CCM_CSCDR3 (ccm_base + 0x3c)
#define MXC_CCM_CSCDR4 (ccm_base + 0x40)
#define MXC_CCM_CWDR (ccm_base + 0x44)
#define MXC_CCM_CDHIPR (ccm_base + 0x48)
#define MXC_CCM_CDCR (ccm_base + 0x4c)
#define MXC_CCM_CTOR (ccm_base + 0x50)
#define MXC_CCM_CLPCR (ccm_base + 0x54)
#define MXC_CCM_CISR (ccm_base + 0x58)
#define MXC_CCM_CIMR (ccm_base + 0x5c)
#define MXC_CCM_CCOSR (ccm_base + 0x60)
#define MXC_CCM_CGPR (ccm_base + 0x64)
#define MXC_CCM_CCGR0 (ccm_base + 0x68)
#define MXC_CCM_CCGR1 (ccm_base + 0x6c)
#define MXC_CCM_CCGR2 (ccm_base + 0x70)
#define MXC_CCM_CCGR3 (ccm_base + 0x74)
#define MXC_CCM_CCGR4 (ccm_base + 0x78)
#define MXC_CCM_CCGR5 (ccm_base + 0x7c)
#define MXC_CCM_CCGR6 (ccm_base + 0x80)
#define MXC_CCM_CCGR7 (ccm_base + 0x84)
/* Low-power Audio Playback Mode clock */
static const char *lp_apm_sel[] = { "osc", };
/* This is used multiple times */
static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
static const char *per_root_sel[] = { "per_podf", "ipg", };
static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
static const char *emi_slow_sel[] = { "main_bus", "ahb", };
static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", };
static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
static const char *mx53_cko1_sel[] = {
"cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
"emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
"di_pred", "dummy", "dummy", "ahb",
"ipg", "per_root", "ckil", "dummy",};
static const char *mx53_cko2_sel[] = {
"dummy"/* dptc_core */, "dummy"/* dptc_perich */,
"dummy", "esdhc_a_podf",
"usboh3_podf", "dummy"/* wrck_clk_root */,
"ecspi_podf", "dummy"/* pll1_ref_clk */,
"esdhc_b_podf", "dummy"/* ddr_clk_root */,
"dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
"vpu_sel", "ipu_sel",
"osc", "ckih1",
"dummy", "esdhc_c_sel",
"ssi1_root_podf", "ssi2_root_podf",
"dummy", "dummy",
"dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
"dummy"/* tve_out */, "usb_phy_sel",
"tve_sel", "lp_apm",
"uart_root", "dummy"/* spdif0_clk_root */,
"dummy", "dummy", };
static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
static const char *step_sels[] = { "lp_apm", };
static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_clk */, "dummy" /* fec_phy_clk */ };
static struct clk *clk[IMX5_CLK_END];
static struct clk_onecell_data clk_data;
static struct clk ** const uart_clks[] __initconst = {
&clk[IMX5_CLK_UART1_IPG_GATE],
&clk[IMX5_CLK_UART1_PER_GATE],
&clk[IMX5_CLK_UART2_IPG_GATE],
&clk[IMX5_CLK_UART2_PER_GATE],
&clk[IMX5_CLK_UART3_IPG_GATE],
&clk[IMX5_CLK_UART3_PER_GATE],
&clk[IMX5_CLK_UART4_IPG_GATE],
&clk[IMX5_CLK_UART4_PER_GATE],
&clk[IMX5_CLK_UART5_IPG_GATE],
&clk[IMX5_CLK_UART5_PER_GATE],
NULL
};
static void __init mx5_clocks_common_init(void __iomem *ccm_base)
{
clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0);
clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0);
clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
main_bus_sel, ARRAY_SIZE(main_bus_sel));
clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
per_root_sel, ARRAY_SIZE(per_root_sel));
clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
clk[IMX5_CLK_STEP_SEL] = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
clk[IMX5_CLK_CPU_PODF_SEL] = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
/* Set SDHC parents to be PLL2 */
clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
/* move usb phy clk to 24MHz */
clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */
clk_prepare_enable(clk[IMX5_CLK_SPBA]);
clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */
clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */
clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]);
clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]);
clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]);
clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]);
clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
imx_register_uart_clocks(uart_clks);
}
static void __init mx50_clocks_init(struct device_node *np)
{
void __iomem *ccm_base;
void __iomem *pll_base;
unsigned long r;
pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
ccm_base = of_iomap(np, 0);
WARN_ON(!ccm_base);
mx5_clocks_common_init(ccm_base);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
/* set SDHC root clock to 200MHZ*/
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
}
CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
static void __init mx51_clocks_init(struct device_node *np)
{
void __iomem *ccm_base;
void __iomem *pll_base;
u32 val;
pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
ccm_base = of_iomap(np, 0);
WARN_ON(!ccm_base);
mx5_clocks_common_init(ccm_base);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
spdif_sel, ARRAY_SIZE(spdif_sel));
clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
/* set the usboh3 parent to pll2_sw */
clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
/* set SDHC root clock to 166.25MHZ*/
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
imx_print_silicon_rev("i.MX51", mx51_revision());
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
/*
* Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
* longer supported. Set to one for better power saving.
*
* The effect of not setting these bits is that MIPI clocks can't be
* enabled without the IPU clock being enabled aswell.
*/
val = readl(MXC_CCM_CCDR);
val |= 1 << 18;
writel(val, MXC_CCM_CCDR);
val = readl(MXC_CCM_CLPCR);
val |= 1 << 23;
writel(val, MXC_CCM_CLPCR);
}
CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
static void __init mx53_clocks_init(struct device_node *np)
{
void __iomem *ccm_base;
void __iomem *pll_base;
unsigned long r;
pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base);
ccm_base = of_iomap(np, 0);
WARN_ON(!ccm_base);
mx5_clocks_common_init(ccm_base);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
clk[IMX5_CLK_FIRI_SEL] = imx_clk_mux("firi_sel", MXC_CCM_CSCMR2, 12, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_FIRI_PRED] = imx_clk_divider("firi_pred", "firi_sel", MXC_CCM_CSCDR3, 6, 3);
clk[IMX5_CLK_FIRI_PODF] = imx_clk_divider("firi_podf", "firi_pred", MXC_CCM_CSCDR3, 0, 6);
clk[IMX5_CLK_FIRI_SERIAL_GATE] = imx_clk_gate2("firi_serial_gate", "firi_podf", MXC_CCM_CCGR1, 28);
clk[IMX5_CLK_FIRI_IPG_GATE] = imx_clk_gate2("firi_ipg_gate", "ipg", MXC_CCM_CCGR1, 26);
clk[IMX5_CLK_CSI0_MCLK1_SEL] = imx_clk_mux("csi0_mclk1_sel", MXC_CCM_CSCMR2, 22, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_CSI0_MCLK1_PRED] = imx_clk_divider("csi0_mclk1_pred", "csi0_mclk1_sel", MXC_CCM_CSCDR4, 6, 3);
clk[IMX5_CLK_CSI0_MCLK1_PODF] = imx_clk_divider("csi0_mclk1_podf", "csi0_mclk1_pred", MXC_CCM_CSCDR4, 0, 6);
clk[IMX5_CLK_CSI0_MCLK1_GATE] = imx_clk_gate2("csi0_mclk1_serial_gate", "csi0_mclk1_podf", MXC_CCM_CCGR6, 4);
clk[IMX5_CLK_IEEE1588_SEL] = imx_clk_mux("ieee1588_sel", MXC_CCM_CSCMR2, 14, 2,
ieee1588_sels, ARRAY_SIZE(ieee1588_sels));
clk[IMX5_CLK_IEEE1588_PRED] = imx_clk_divider("ieee1588_pred", "ieee1588_sel", MXC_CCM_CSCDR2, 6, 3);
clk[IMX5_CLK_IEEE1588_PODF] = imx_clk_divider("ieee1588_podf", "ieee1588_pred", MXC_CCM_CSCDR2, 0, 6);
clk[IMX5_CLK_IEEE1588_GATE] = imx_clk_gate2("ieee1588_serial_gate", "ieee1588_podf", MXC_CCM_CCGR7, 6);
clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
clk[IMX5_CLK_ARM] = imx_clk_cpu("arm", "cpu_podf",
clk[IMX5_CLK_CPU_PODF],
clk[IMX5_CLK_CPU_PODF_SEL],
clk[IMX5_CLK_PLL1_SW],
clk[IMX5_CLK_STEP_SEL]);
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
/* set SDHC root clock to 200MHZ*/
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
/* move can bus clk to 24MHz */
clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
/* make sure step clock is running from 24MHz */
clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
imx_print_silicon_rev("i.MX53", mx53_revision());
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
}
CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
| null | null | null | null | 110,408 |
356 | null | train_val | a6802e21d824e786d1e2a8440cf749a6e1a8d95f | 160,484 | ImageMagick | 0 | https://github.com/ImageMagick/ImageMagick | 2017-07-18 18:28:29-04:00 | /*
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% %
% %
% %
% M M OOO N N TTTTT AAA GGGG EEEEE %
% MM MM O O NN N T A A G E %
% M M M O O N N N T AAAAA G GG EEE %
% M M O O N NN T A A G G E %
% M M OOO N N T A A GGG EEEEE %
% %
% %
% MagickCore Methods to Create Image Thumbnails %
% %
% Software Design %
% Cristy %
% July 1992 %
% %
% %
% Copyright 1999-2017 ImageMagick Studio LLC, a non-profit organization %
% dedicated to making software imaging solutions freely available. %
% %
% You may not use this file except in compliance with the License. You may %
% obtain a copy of the License at %
% %
% https://www.imagemagick.org/script/license.php %
% %
% Unless required by applicable law or agreed to in writing, software %
% distributed under the License is distributed on an "AS IS" BASIS, %
% WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. %
% See the License for the specific language governing permissions and %
% limitations under the License. %
% %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%
%
%
*/
/*
Include declarations.
*/
#include "MagickCore/studio.h"
#include "MagickCore/annotate.h"
#include "MagickCore/client.h"
#include "MagickCore/color.h"
#include "MagickCore/composite.h"
#include "MagickCore/constitute.h"
#include "MagickCore/decorate.h"
#include "MagickCore/draw.h"
#include "MagickCore/effect.h"
#include "MagickCore/enhance.h"
#include "MagickCore/exception.h"
#include "MagickCore/exception-private.h"
#include "MagickCore/fx.h"
#include "MagickCore/gem.h"
#include "MagickCore/geometry.h"
#include "MagickCore/image.h"
#include "MagickCore/image-private.h"
#include "MagickCore/list.h"
#include "MagickCore/memory_.h"
#include "MagickCore/monitor.h"
#include "MagickCore/monitor-private.h"
#include "MagickCore/montage.h"
#include "MagickCore/option.h"
#include "MagickCore/pixel.h"
#include "MagickCore/quantize.h"
#include "MagickCore/property.h"
#include "MagickCore/resize.h"
#include "MagickCore/resource_.h"
#include "MagickCore/string_.h"
#include "MagickCore/utility.h"
#include "MagickCore/utility-private.h"
#include "MagickCore/version.h"
/*
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% %
% %
% %
% C l o n e M o n t a g e I n f o %
% %
% %
% %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%
% CloneMontageInfo() makes a copy of the given montage info structure. If
% NULL is specified, a new image info structure is created initialized to
% default values.
%
% The format of the CloneMontageInfo method is:
%
% MontageInfo *CloneMontageInfo(const ImageInfo *image_info,
% const MontageInfo *montage_info)
%
% A description of each parameter follows:
%
% o image_info: the image info.
%
% o montage_info: the montage info.
%
*/
MagickExport MontageInfo *CloneMontageInfo(const ImageInfo *image_info,
const MontageInfo *montage_info)
{
MontageInfo
*clone_info;
clone_info=(MontageInfo *) AcquireMagickMemory(sizeof(*clone_info));
if (clone_info == (MontageInfo *) NULL)
ThrowFatalException(ResourceLimitFatalError,"MemoryAllocationFailed");
GetMontageInfo(image_info,clone_info);
if (montage_info == (MontageInfo *) NULL)
return(clone_info);
if (montage_info->geometry != (char *) NULL)
clone_info->geometry=AcquireString(montage_info->geometry);
if (montage_info->tile != (char *) NULL)
clone_info->tile=AcquireString(montage_info->tile);
if (montage_info->title != (char *) NULL)
clone_info->title=AcquireString(montage_info->title);
if (montage_info->frame != (char *) NULL)
clone_info->frame=AcquireString(montage_info->frame);
if (montage_info->texture != (char *) NULL)
clone_info->texture=AcquireString(montage_info->texture);
if (montage_info->font != (char *) NULL)
clone_info->font=AcquireString(montage_info->font);
clone_info->pointsize=montage_info->pointsize;
clone_info->border_width=montage_info->border_width;
clone_info->shadow=montage_info->shadow;
clone_info->fill=montage_info->fill;
clone_info->stroke=montage_info->stroke;
clone_info->matte_color=montage_info->matte_color;
clone_info->background_color=montage_info->background_color;
clone_info->border_color=montage_info->border_color;
clone_info->gravity=montage_info->gravity;
(void) CopyMagickString(clone_info->filename,montage_info->filename,
MagickPathExtent);
clone_info->debug=IsEventLogging();
return(clone_info);
}
/*
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% %
% %
% %
% D e s t r o y M o n t a g e I n f o %
% %
% %
% %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%
% DestroyMontageInfo() deallocates memory associated with montage_info.
%
% The format of the DestroyMontageInfo method is:
%
% MontageInfo *DestroyMontageInfo(MontageInfo *montage_info)
%
% A description of each parameter follows:
%
% o montage_info: Specifies a pointer to an MontageInfo structure.
%
%
*/
MagickExport MontageInfo *DestroyMontageInfo(MontageInfo *montage_info)
{
if (montage_info->debug != MagickFalse)
(void) LogMagickEvent(TraceEvent,GetMagickModule(),"...");
assert(montage_info != (MontageInfo *) NULL);
assert(montage_info->signature == MagickCoreSignature);
if (montage_info->geometry != (char *) NULL)
montage_info->geometry=(char *)
RelinquishMagickMemory(montage_info->geometry);
if (montage_info->tile != (char *) NULL)
montage_info->tile=DestroyString(montage_info->tile);
if (montage_info->title != (char *) NULL)
montage_info->title=DestroyString(montage_info->title);
if (montage_info->frame != (char *) NULL)
montage_info->frame=DestroyString(montage_info->frame);
if (montage_info->texture != (char *) NULL)
montage_info->texture=(char *) RelinquishMagickMemory(
montage_info->texture);
if (montage_info->font != (char *) NULL)
montage_info->font=DestroyString(montage_info->font);
montage_info->signature=(~MagickCoreSignature);
montage_info=(MontageInfo *) RelinquishMagickMemory(montage_info);
return(montage_info);
}
/*
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% %
% %
% %
% G e t M o n t a g e I n f o %
% %
% %
% %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%
% GetMontageInfo() initializes montage_info to default values.
%
% The format of the GetMontageInfo method is:
%
% void GetMontageInfo(const ImageInfo *image_info,
% MontageInfo *montage_info)
%
% A description of each parameter follows:
%
% o image_info: a structure of type ImageInfo.
%
% o montage_info: Specifies a pointer to a MontageInfo structure.
%
*/
MagickExport void GetMontageInfo(const ImageInfo *image_info,
MontageInfo *montage_info)
{
assert(image_info != (const ImageInfo *) NULL);
assert(image_info->signature == MagickCoreSignature);
if (image_info->debug != MagickFalse)
(void) LogMagickEvent(TraceEvent,GetMagickModule(),"%s",
image_info->filename);
assert(montage_info != (MontageInfo *) NULL);
(void) ResetMagickMemory(montage_info,0,sizeof(*montage_info));
(void) CopyMagickString(montage_info->filename,image_info->filename,
MagickPathExtent);
montage_info->geometry=AcquireString(DefaultTileGeometry);
if (image_info->font != (char *) NULL)
montage_info->font=AcquireString(image_info->font);
montage_info->gravity=CenterGravity;
montage_info->pointsize=image_info->pointsize;
montage_info->fill.alpha=OpaqueAlpha;
montage_info->stroke.alpha=(Quantum) TransparentAlpha;
montage_info->matte_color=image_info->matte_color;
montage_info->background_color=image_info->background_color;
montage_info->border_color=image_info->border_color;
montage_info->debug=IsEventLogging();
montage_info->signature=MagickCoreSignature;
}
/*
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% %
% %
% %
% M o n t a g e I m a g e L i s t %
% %
% %
% %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%
% MontageImageList() is a layout manager that lets you tile one or more
% thumbnails across an image canvas.
%
% The format of the MontageImageList method is:
%
% Image *MontageImageList(const ImageInfo *image_info,
% const MontageInfo *montage_info,Image *images,
% ExceptionInfo *exception)
%
% A description of each parameter follows:
%
% o image_info: the image info.
%
% o montage_info: Specifies a pointer to a MontageInfo structure.
%
% o images: Specifies a pointer to an array of Image structures.
%
% o exception: return any errors or warnings in this structure.
%
*/
static void GetMontageGeometry(char *geometry,const size_t number_images,
ssize_t *x_offset,ssize_t *y_offset,size_t *tiles_per_column,
size_t *tiles_per_row)
{
*tiles_per_column=0;
*tiles_per_row=0;
(void) GetGeometry(geometry,x_offset,y_offset,tiles_per_row,tiles_per_column);
if ((*tiles_per_column == 0) && (*tiles_per_row == 0))
*tiles_per_column=(size_t) sqrt((double) number_images);
if ((*tiles_per_column == 0) && (*tiles_per_row != 0))
*tiles_per_column=(size_t) ceil((double) number_images/(*tiles_per_row));
if ((*tiles_per_row == 0) && (*tiles_per_column != 0))
*tiles_per_row=(size_t) ceil((double) number_images/(*tiles_per_column));
}
#if defined(__cplusplus) || defined(c_plusplus)
extern "C" {
#endif
static int SceneCompare(const void *x,const void *y)
{
Image
**image_1,
**image_2;
image_1=(Image **) x;
image_2=(Image **) y;
return((int) ((*image_1)->scene-(*image_2)->scene));
}
#if defined(__cplusplus) || defined(c_plusplus)
}
#endif
MagickExport Image *MontageImages(const Image *images,
const MontageInfo *montage_info,ExceptionInfo *exception)
{
Image
*montage_image;
ImageInfo
*image_info;
image_info=AcquireImageInfo();
montage_image=MontageImageList(image_info,montage_info,images,exception);
image_info=DestroyImageInfo(image_info);
return(montage_image);
}
MagickExport Image *MontageImageList(const ImageInfo *image_info,
const MontageInfo *montage_info,const Image *images,ExceptionInfo *exception)
{
#define MontageImageTag "Montage/Image"
#define TileImageTag "Tile/Image"
char
tile_geometry[MagickPathExtent],
*title;
const char
*value;
DrawInfo
*draw_info;
FrameInfo
frame_info;
Image
*image,
**image_list,
**master_list,
*montage,
*texture,
*tile_image,
*thumbnail;
ImageInfo
*clone_info;
MagickBooleanType
concatenate,
proceed,
status;
MagickOffsetType
tiles;
MagickProgressMonitor
progress_monitor;
MagickStatusType
flags;
register ssize_t
i;
RectangleInfo
bounds,
geometry,
extract_info;
size_t
bevel_width,
border_width,
extent,
height,
images_per_page,
max_height,
number_images,
number_lines,
sans,
tiles_per_column,
tiles_per_page,
tiles_per_row,
title_offset,
total_tiles,
width;
ssize_t
tile,
x,
x_offset,
y,
y_offset;
TypeMetric
metrics;
/*
Create image tiles.
*/
assert(images != (Image *) NULL);
assert(images->signature == MagickCoreSignature);
if (images->debug != MagickFalse)
(void) LogMagickEvent(TraceEvent,GetMagickModule(),"%s",images->filename);
assert(montage_info != (MontageInfo *) NULL);
assert(montage_info->signature == MagickCoreSignature);
assert(exception != (ExceptionInfo *) NULL);
assert(exception->signature == MagickCoreSignature);
number_images=GetImageListLength(images);
master_list=ImageListToArray(images,exception);
image_list=master_list;
image=image_list[0];
if (master_list == (Image **) NULL)
ThrowImageException(ResourceLimitError,"MemoryAllocationFailed");
thumbnail=NewImageList();
for (i=0; i < (ssize_t) number_images; i++)
{
image=CloneImage(image_list[i],0,0,MagickTrue,exception);
if (image == (Image *) NULL)
break;
(void) ParseAbsoluteGeometry("0x0+0+0",&image->page);
progress_monitor=SetImageProgressMonitor(image,(MagickProgressMonitor) NULL,
image->client_data);
flags=ParseRegionGeometry(image,montage_info->geometry,&geometry,exception);
thumbnail=ThumbnailImage(image,geometry.width,geometry.height,exception);
if (thumbnail == (Image *) NULL)
break;
image_list[i]=thumbnail;
(void) SetImageProgressMonitor(image,progress_monitor,image->client_data);
proceed=SetImageProgress(image,TileImageTag,(MagickOffsetType) i,
number_images);
if (proceed == MagickFalse)
break;
image=DestroyImage(image);
}
if (i < (ssize_t) number_images)
{
if (thumbnail == (Image *) NULL)
i--;
for (tile=0; (ssize_t) tile <= i; tile++)
if (image_list[tile] != (Image *) NULL)
image_list[tile]=DestroyImage(image_list[tile]);
master_list=(Image **) RelinquishMagickMemory(master_list);
return((Image *) NULL);
}
/*
Sort image list by increasing tile number.
*/
for (i=0; i < (ssize_t) number_images; i++)
if (image_list[i]->scene == 0)
break;
if (i == (ssize_t) number_images)
qsort((void *) image_list,(size_t) number_images,sizeof(*image_list),
SceneCompare);
/*
Determine tiles per row and column.
*/
tiles_per_column=(size_t) sqrt((double) number_images);
tiles_per_row=(size_t) ceil((double) number_images/tiles_per_column);
x_offset=0;
y_offset=0;
if (montage_info->tile != (char *) NULL)
GetMontageGeometry(montage_info->tile,number_images,&x_offset,&y_offset,
&tiles_per_column,&tiles_per_row);
/*
Determine tile sizes.
*/
concatenate=MagickFalse;
SetGeometry(image_list[0],&extract_info);
extract_info.x=(ssize_t) montage_info->border_width;
extract_info.y=(ssize_t) montage_info->border_width;
if (montage_info->geometry != (char *) NULL)
{
/*
Initialize tile geometry.
*/
flags=GetGeometry(montage_info->geometry,&extract_info.x,&extract_info.y,
&extract_info.width,&extract_info.height);
concatenate=((flags & RhoValue) == 0) && ((flags & SigmaValue) == 0) ?
MagickTrue : MagickFalse;
}
border_width=montage_info->border_width;
bevel_width=0;
(void) ResetMagickMemory(&frame_info,0,sizeof(frame_info));
if (montage_info->frame != (char *) NULL)
{
char
absolute_geometry[MagickPathExtent];
frame_info.width=extract_info.width;
frame_info.height=extract_info.height;
(void) FormatLocaleString(absolute_geometry,MagickPathExtent,"%s!",
montage_info->frame);
flags=ParseMetaGeometry(absolute_geometry,&frame_info.outer_bevel,
&frame_info.inner_bevel,&frame_info.width,&frame_info.height);
if ((flags & HeightValue) == 0)
frame_info.height=frame_info.width;
if ((flags & XiValue) == 0)
frame_info.outer_bevel=(ssize_t) frame_info.width/2;
if ((flags & PsiValue) == 0)
frame_info.inner_bevel=frame_info.outer_bevel;
frame_info.x=(ssize_t) frame_info.width;
frame_info.y=(ssize_t) frame_info.height;
bevel_width=(size_t) MagickMax(frame_info.inner_bevel,
frame_info.outer_bevel);
border_width=(size_t) MagickMax((ssize_t) frame_info.width,
(ssize_t) frame_info.height);
}
for (i=0; i < (ssize_t) number_images; i++)
{
if (image_list[i]->columns > extract_info.width)
extract_info.width=image_list[i]->columns;
if (image_list[i]->rows > extract_info.height)
extract_info.height=image_list[i]->rows;
}
/*
Initialize draw attributes.
*/
clone_info=CloneImageInfo(image_info);
clone_info->background_color=montage_info->background_color;
clone_info->border_color=montage_info->border_color;
draw_info=CloneDrawInfo(clone_info,(DrawInfo *) NULL);
if (montage_info->font != (char *) NULL)
(void) CloneString(&draw_info->font,montage_info->font);
if (montage_info->pointsize != 0.0)
draw_info->pointsize=montage_info->pointsize;
draw_info->gravity=CenterGravity;
draw_info->stroke=montage_info->stroke;
draw_info->fill=montage_info->fill;
draw_info->text=AcquireString("");
(void) GetTypeMetrics(image_list[0],draw_info,&metrics,exception);
texture=NewImageList();
if (montage_info->texture != (char *) NULL)
{
(void) CopyMagickString(clone_info->filename,montage_info->texture,
MagickPathExtent);
texture=ReadImage(clone_info,exception);
}
/*
Determine the number of lines in an next label.
*/
title=InterpretImageProperties(clone_info,image_list[0],montage_info->title,
exception);
title_offset=0;
if (montage_info->title != (char *) NULL)
title_offset=(size_t) (2*(metrics.ascent-metrics.descent)*
MultilineCensus(title)+2*extract_info.y);
number_lines=0;
for (i=0; i < (ssize_t) number_images; i++)
{
value=GetImageProperty(image_list[i],"label",exception);
if (value == (const char *) NULL)
continue;
if (MultilineCensus(value) > number_lines)
number_lines=MultilineCensus(value);
}
/*
Allocate next structure.
*/
tile_image=AcquireImage((ImageInfo *) NULL,exception);
montage=AcquireImage(clone_info,exception);
montage->background_color=montage_info->background_color;
montage->scene=0;
images_per_page=(number_images-1)/(tiles_per_row*tiles_per_column)+1;
tiles=0;
total_tiles=(size_t) number_images;
for (i=0; i < (ssize_t) images_per_page; i++)
{
/*
Determine bounding box.
*/
tiles_per_page=tiles_per_row*tiles_per_column;
x_offset=0;
y_offset=0;
if (montage_info->tile != (char *) NULL)
GetMontageGeometry(montage_info->tile,number_images,&x_offset,&y_offset,
&sans,&sans);
tiles_per_page=tiles_per_row*tiles_per_column;
y_offset+=(ssize_t) title_offset;
max_height=0;
bounds.width=0;
bounds.height=0;
width=0;
for (tile=0; tile < (ssize_t) tiles_per_page; tile++)
{
if (tile < (ssize_t) number_images)
{
width=concatenate != MagickFalse ? image_list[tile]->columns :
extract_info.width;
if (image_list[tile]->rows > max_height)
max_height=image_list[tile]->rows;
}
x_offset+=(ssize_t) (width+2*(extract_info.x+border_width));
if (x_offset > (ssize_t) bounds.width)
bounds.width=(size_t) x_offset;
if (((tile+1) == (ssize_t) tiles_per_page) ||
(((tile+1) % tiles_per_row) == 0))
{
x_offset=0;
if (montage_info->tile != (char *) NULL)
GetMontageGeometry(montage_info->tile,number_images,&x_offset,&y,
&sans,&sans);
height=concatenate != MagickFalse ? max_height : extract_info.height;
y_offset+=(ssize_t) (height+(extract_info.y+(ssize_t) border_width)*2+
(metrics.ascent-metrics.descent+4)*number_lines+
(montage_info->shadow != MagickFalse ? 4 : 0));
if (y_offset > (ssize_t) bounds.height)
bounds.height=(size_t) y_offset;
max_height=0;
}
}
if (montage_info->shadow != MagickFalse)
bounds.width+=4;
/*
Initialize montage image.
*/
(void) CopyMagickString(montage->filename,montage_info->filename,
MagickPathExtent);
montage->columns=(size_t) MagickMax((ssize_t) bounds.width,1);
montage->rows=(size_t) MagickMax((ssize_t) bounds.height,1);
(void) SetImageBackgroundColor(montage,exception);
/*
Set montage geometry.
*/
montage->montage=AcquireString((char *) NULL);
tile=0;
extent=1;
while (tile < MagickMin((ssize_t) tiles_per_page,(ssize_t) number_images))
{
extent+=strlen(image_list[tile]->filename)+1;
tile++;
}
montage->directory=(char *) AcquireQuantumMemory(extent,
sizeof(*montage->directory));
if ((montage->montage == (char *) NULL) ||
(montage->directory == (char *) NULL))
ThrowImageException(ResourceLimitError,"MemoryAllocationFailed");
x_offset=0;
y_offset=0;
if (montage_info->tile != (char *) NULL)
GetMontageGeometry(montage_info->tile,number_images,&x_offset,&y_offset,
&sans,&sans);
y_offset+=(ssize_t) title_offset;
(void) FormatLocaleString(montage->montage,MagickPathExtent,
"%.20gx%.20g%+.20g%+.20g",(double) (extract_info.width+
(extract_info.x+border_width)*2),(double) (extract_info.height+
(extract_info.y+border_width)*2+(double) ((metrics.ascent-
metrics.descent+4)*number_lines+(montage_info->shadow != MagickFalse ? 4 :
0))),(double) x_offset,(double) y_offset);
*montage->directory='\0';
tile=0;
while (tile < MagickMin((ssize_t) tiles_per_page,(ssize_t) number_images))
{
(void) ConcatenateMagickString(montage->directory,
image_list[tile]->filename,extent);
(void) ConcatenateMagickString(montage->directory,"\n",extent);
tile++;
}
progress_monitor=SetImageProgressMonitor(montage,(MagickProgressMonitor)
NULL,montage->client_data);
if (texture != (Image *) NULL)
(void) TextureImage(montage,texture,exception);
if (montage_info->title != (char *) NULL)
{
DrawInfo
*draw_clone_info;
TypeMetric
tile_metrics;
/*
Annotate composite image with title.
*/
draw_clone_info=CloneDrawInfo(image_info,draw_info);
draw_clone_info->gravity=CenterGravity;
draw_clone_info->pointsize*=2.0;
(void) GetTypeMetrics(image_list[0],draw_clone_info,&tile_metrics,
exception);
(void) FormatLocaleString(tile_geometry,MagickPathExtent,
"%.20gx%.20g%+.20g%+.20g",(double) montage->columns,(double)
(tile_metrics.ascent-tile_metrics.descent),0.0,
(double) extract_info.y+4);
(void) CloneString(&draw_clone_info->geometry,tile_geometry);
(void) CloneString(&draw_clone_info->text,title);
(void) AnnotateImage(montage,draw_clone_info,exception);
draw_clone_info=DestroyDrawInfo(draw_clone_info);
}
(void) SetImageProgressMonitor(montage,progress_monitor,
montage->client_data);
/*
Copy tile to the composite.
*/
x_offset=0;
y_offset=0;
if (montage_info->tile != (char *) NULL)
GetMontageGeometry(montage_info->tile,number_images,&x_offset,&y_offset,
&sans,&sans);
x_offset+=extract_info.x;
y_offset+=(ssize_t) title_offset+extract_info.y;
max_height=0;
status=MagickTrue;
for (tile=0; tile < MagickMin((ssize_t) tiles_per_page,(ssize_t) number_images); tile++)
{
/*
Copy this tile to the composite.
*/
image=CloneImage(image_list[tile],0,0,MagickTrue,exception);
progress_monitor=SetImageProgressMonitor(image,
(MagickProgressMonitor) NULL,image->client_data);
width=concatenate != MagickFalse ? image->columns : extract_info.width;
if (image->rows > max_height)
max_height=image->rows;
height=concatenate != MagickFalse ? max_height : extract_info.height;
if (border_width != 0)
{
Image
*border_image;
RectangleInfo
border_info;
/*
Put a border around the image.
*/
border_info.width=border_width;
border_info.height=border_width;
if (montage_info->frame != (char *) NULL)
{
border_info.width=(width-image->columns+1)/2;
border_info.height=(height-image->rows+1)/2;
}
border_image=BorderImage(image,&border_info,image->compose,exception);
if (border_image != (Image *) NULL)
{
image=DestroyImage(image);
image=border_image;
}
if ((montage_info->frame != (char *) NULL) &&
(image->compose == DstOutCompositeOp))
{
(void) SetPixelChannelMask(image,AlphaChannel);
(void) NegateImage(image,MagickFalse,exception);
(void) SetPixelChannelMask(image,DefaultChannels);
}
}
/*
Gravitate as specified by the tile gravity.
*/
tile_image->columns=width;
tile_image->rows=height;
tile_image->gravity=montage_info->gravity;
if (image->gravity != UndefinedGravity)
tile_image->gravity=image->gravity;
(void) FormatLocaleString(tile_geometry,MagickPathExtent,"%.20gx%.20g+0+0",
(double) image->columns,(double) image->rows);
flags=ParseGravityGeometry(tile_image,tile_geometry,&geometry,exception);
x=(ssize_t) (geometry.x+border_width);
y=(ssize_t) (geometry.y+border_width);
if ((montage_info->frame != (char *) NULL) && (bevel_width != 0))
{
FrameInfo
frame_clone;
Image
*frame_image;
/*
Put an ornamental border around this tile.
*/
frame_clone=frame_info;
frame_clone.width=width+2*frame_info.width;
frame_clone.height=height+2*frame_info.height;
value=GetImageProperty(image,"label",exception);
if (value != (const char *) NULL)
frame_clone.height+=(size_t) ((metrics.ascent-metrics.descent+4)*
MultilineCensus(value));
frame_image=FrameImage(image,&frame_clone,image->compose,exception);
if (frame_image != (Image *) NULL)
{
image=DestroyImage(image);
image=frame_image;
}
x=0;
y=0;
}
if (LocaleCompare(image->magick,"NULL") != 0)
{
/*
Composite background with tile.
*/
if (montage_info->shadow != MagickFalse)
{
Image
*shadow_image;
/*
Shadow image.
*/
(void) QueryColorCompliance("#0000",AllCompliance,
&image->background_color,exception);
shadow_image=ShadowImage(image,80.0,2.0,5,5,exception);
if (shadow_image != (Image *) NULL)
{
(void) CompositeImage(shadow_image,image,OverCompositeOp,
MagickTrue,0,0,exception);
image=DestroyImage(image);
image=shadow_image;
}
}
(void) CompositeImage(montage,image,image->compose,MagickTrue,
x_offset+x,y_offset+y,exception);
value=GetImageProperty(image,"label",exception);
if (value != (const char *) NULL)
{
/*
Annotate composite tile with label.
*/
(void) FormatLocaleString(tile_geometry,MagickPathExtent,
"%.20gx%.20g%+.20g%+.20g",(double) ((montage_info->frame ?
image->columns : width)-2*border_width),(double)
(metrics.ascent-metrics.descent+4)*MultilineCensus(value),
(double) (x_offset+border_width),(double)
((montage_info->frame ? y_offset+height+border_width+4 :
y_offset+extract_info.height+border_width+
(montage_info->shadow != MagickFalse ? 4 : 0))+bevel_width));
(void) CloneString(&draw_info->geometry,tile_geometry);
(void) CloneString(&draw_info->text,value);
(void) AnnotateImage(montage,draw_info,exception);
}
}
x_offset+=(ssize_t) (width+2*(extract_info.x+border_width));
if (((tile+1) == (ssize_t) tiles_per_page) ||
(((tile+1) % tiles_per_row) == 0))
{
x_offset=extract_info.x;
y_offset+=(ssize_t) (height+(extract_info.y+border_width)*2+
(metrics.ascent-metrics.descent+4)*number_lines+
(montage_info->shadow != MagickFalse ? 4 : 0));
max_height=0;
}
if (images->progress_monitor != (MagickProgressMonitor) NULL)
{
proceed=SetImageProgress(image,MontageImageTag,tiles,total_tiles);
if (proceed == MagickFalse)
status=MagickFalse;
}
image_list[tile]=DestroyImage(image_list[tile]);
image=DestroyImage(image);
tiles++;
}
(void) status;
if ((i+1) < (ssize_t) images_per_page)
{
/*
Allocate next image structure.
*/
AcquireNextImage(clone_info,montage,exception);
if (GetNextImageInList(montage) == (Image *) NULL)
{
montage=DestroyImageList(montage);
return((Image *) NULL);
}
montage=GetNextImageInList(montage);
montage->background_color=montage_info->background_color;
image_list+=tiles_per_page;
number_images-=tiles_per_page;
}
}
tile_image=DestroyImage(tile_image);
if (texture != (Image *) NULL)
texture=DestroyImage(texture);
title=DestroyString(title);
master_list=(Image **) RelinquishMagickMemory(master_list);
draw_info=DestroyDrawInfo(draw_info);
clone_info=DestroyImageInfo(clone_info);
return(GetFirstImageInList(montage));
}
| null | null | null | null | 72,777 |
64,575 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 64,575 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright (c) 2012 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef CHROME_BROWSER_UI_COCOA_INFO_BUBBLE_VIEW_H_
#define CHROME_BROWSER_UI_COCOA_INFO_BUBBLE_VIEW_H_
#import <Cocoa/Cocoa.h>
#include "base/mac/scoped_nsobject.h"
namespace info_bubble {
// These values are in view coordinates.
const CGFloat kBubbleArrowHeight = 8.0;
const CGFloat kBubbleArrowWidth = 15.0;
const CGFloat kBubbleCornerRadius = 2.0;
const CGFloat kBubbleArrowXOffset = kBubbleArrowWidth + kBubbleCornerRadius;
// Constants that define where the bubble will have rounded corners.
enum CornerFlags {
kRoundedTopCorners = 1,
kRoundedBottomCorners = 1 << 1,
kRoundedAllCorners = kRoundedTopCorners | kRoundedBottomCorners,
};
enum BubbleArrowLocation {
kTopLeading,
kTopCenter,
kTopTrailing,
kNoArrow,
};
enum BubbleAlignment {
// The tip of the arrow points to the anchor point.
kAlignArrowToAnchor,
// The edge nearest to the arrow is lined up with the anchor point.
kAlignEdgeToAnchorEdge,
// Align the trailing edge (right in LTR, left in RTL) to the anchor point.
kAlignTrailingEdgeToAnchorEdge,
// Align the leading edge (left in LTR, right in RTL) to the anchor point.
kAlignLeadingEdgeToAnchorEdge,
};
} // namespace info_bubble
// Content view for a bubble with an arrow showing arbitrary content.
// This is where nonrectangular drawing happens.
@interface InfoBubbleView : NSView {
@private
info_bubble::BubbleArrowLocation arrowLocation_;
info_bubble::BubbleAlignment alignment_;
info_bubble::CornerFlags cornerFlags_;
base::scoped_nsobject<NSColor> backgroundColor_;
}
@property(assign, nonatomic) info_bubble::BubbleArrowLocation arrowLocation;
@property(assign, nonatomic) info_bubble::BubbleAlignment alignment;
@property(assign, nonatomic) info_bubble::CornerFlags cornerFlags;
// Returns the point location in view coordinates of the tip of the arrow.
- (NSPoint)arrowTip;
// Gets and sets the bubble's background color.
- (NSColor*)backgroundColor;
- (void)setBackgroundColor:(NSColor*)backgroundColor;
@end
#endif // CHROME_BROWSER_UI_COCOA_INFO_BUBBLE_VIEW_H_
| null | null | null | null | 61,438 |
34,233 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 199,228 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <soc/mediatek/smi.h>
#include "mtk_mdp_comp.h"
static const char * const mtk_mdp_comp_stem[MTK_MDP_COMP_TYPE_MAX] = {
"mdp_rdma",
"mdp_rsz",
"mdp_wdma",
"mdp_wrot",
};
struct mtk_mdp_comp_match {
enum mtk_mdp_comp_type type;
int alias_id;
};
static const struct mtk_mdp_comp_match mtk_mdp_matches[MTK_MDP_COMP_ID_MAX] = {
{ MTK_MDP_RDMA, 0 },
{ MTK_MDP_RDMA, 1 },
{ MTK_MDP_RSZ, 0 },
{ MTK_MDP_RSZ, 1 },
{ MTK_MDP_RSZ, 2 },
{ MTK_MDP_WDMA, 0 },
{ MTK_MDP_WROT, 0 },
{ MTK_MDP_WROT, 1 },
};
int mtk_mdp_comp_get_id(struct device *dev, struct device_node *node,
enum mtk_mdp_comp_type comp_type)
{
int id = of_alias_get_id(node, mtk_mdp_comp_stem[comp_type]);
int i;
for (i = 0; i < ARRAY_SIZE(mtk_mdp_matches); i++) {
if (comp_type == mtk_mdp_matches[i].type &&
id == mtk_mdp_matches[i].alias_id)
return i;
}
dev_err(dev, "Failed to get id. type: %d, id: %d\n", comp_type, id);
return -EINVAL;
}
void mtk_mdp_comp_clock_on(struct device *dev, struct mtk_mdp_comp *comp)
{
int i, err;
if (comp->larb_dev) {
err = mtk_smi_larb_get(comp->larb_dev);
if (err)
dev_err(dev,
"failed to get larb, err %d. type:%d id:%d\n",
err, comp->type, comp->id);
}
for (i = 0; i < ARRAY_SIZE(comp->clk); i++) {
if (!comp->clk[i])
continue;
err = clk_prepare_enable(comp->clk[i]);
if (err)
dev_err(dev,
"failed to enable clock, err %d. type:%d id:%d i:%d\n",
err, comp->type, comp->id, i);
}
}
void mtk_mdp_comp_clock_off(struct device *dev, struct mtk_mdp_comp *comp)
{
int i;
for (i = 0; i < ARRAY_SIZE(comp->clk); i++) {
if (!comp->clk[i])
continue;
clk_disable_unprepare(comp->clk[i]);
}
if (comp->larb_dev)
mtk_smi_larb_put(comp->larb_dev);
}
int mtk_mdp_comp_init(struct device *dev, struct device_node *node,
struct mtk_mdp_comp *comp, enum mtk_mdp_comp_id comp_id)
{
struct device_node *larb_node;
struct platform_device *larb_pdev;
int i;
if (comp_id < 0 || comp_id >= MTK_MDP_COMP_ID_MAX) {
dev_err(dev, "Invalid comp_id %d\n", comp_id);
return -EINVAL;
}
comp->dev_node = of_node_get(node);
comp->id = comp_id;
comp->type = mtk_mdp_matches[comp_id].type;
comp->regs = of_iomap(node, 0);
for (i = 0; i < ARRAY_SIZE(comp->clk); i++) {
comp->clk[i] = of_clk_get(node, i);
/* Only RDMA needs two clocks */
if (comp->type != MTK_MDP_RDMA)
break;
}
/* Only DMA capable components need the LARB property */
comp->larb_dev = NULL;
if (comp->type != MTK_MDP_RDMA &&
comp->type != MTK_MDP_WDMA &&
comp->type != MTK_MDP_WROT)
return 0;
larb_node = of_parse_phandle(node, "mediatek,larb", 0);
if (!larb_node) {
dev_err(dev,
"Missing mediadek,larb phandle in %s node\n",
node->full_name);
return -EINVAL;
}
larb_pdev = of_find_device_by_node(larb_node);
if (!larb_pdev) {
dev_warn(dev, "Waiting for larb device %s\n",
larb_node->full_name);
of_node_put(larb_node);
return -EPROBE_DEFER;
}
of_node_put(larb_node);
comp->larb_dev = &larb_pdev->dev;
return 0;
}
void mtk_mdp_comp_deinit(struct device *dev, struct mtk_mdp_comp *comp)
{
of_node_put(comp->dev_node);
}
| null | null | null | null | 107,575 |
27,248 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 192,243 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* Command support for NI general purpose counters
*
* Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Module: ni_tiocmd
* Description: National Instruments general purpose counters command support
* Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
* Herman.Bruyninckx@mech.kuleuven.ac.be,
* Wim.Meeussen@mech.kuleuven.ac.be,
* Klaas.Gadeyne@mech.kuleuven.ac.be,
* Frank Mori Hess <fmhess@users.sourceforge.net>
* Updated: Fri, 11 Apr 2008 12:32:35 +0100
* Status: works
*
* This module is not used directly by end-users. Rather, it
* is used by other drivers (for example ni_660x and ni_pcimio)
* to provide command support for NI's general purpose counters.
* It was originally split out of ni_tio.c to stop the 'ni_tio'
* module depending on the 'mite' module.
*
* References:
* DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
* DAQ 6601/6602 User Manual (NI 322137B-01)
* 340934b.pdf DAQ-STC reference manual
*
* TODO: Support use of both banks X and Y
*/
#include <linux/module.h>
#include "ni_tio_internal.h"
#include "mite.h"
static void ni_tio_configure_dma(struct ni_gpct *counter,
bool enable, bool read)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned int cidx = counter->counter_index;
unsigned int mask;
unsigned int bits;
mask = GI_READ_ACKS_IRQ | GI_WRITE_ACKS_IRQ;
bits = 0;
if (enable) {
if (read)
bits |= GI_READ_ACKS_IRQ;
else
bits |= GI_WRITE_ACKS_IRQ;
}
ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), mask, bits);
switch (counter_dev->variant) {
case ni_gpct_variant_e_series:
break;
case ni_gpct_variant_m_series:
case ni_gpct_variant_660x:
mask = GI_DMA_ENABLE | GI_DMA_INT_ENA | GI_DMA_WRITE;
bits = 0;
if (enable)
bits |= GI_DMA_ENABLE | GI_DMA_INT_ENA;
if (!read)
bits |= GI_DMA_WRITE;
ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), mask, bits);
break;
}
}
static int ni_tio_input_inttrig(struct comedi_device *dev,
struct comedi_subdevice *s,
unsigned int trig_num)
{
struct ni_gpct *counter = s->private;
struct comedi_cmd *cmd = &s->async->cmd;
unsigned long flags;
int ret = 0;
if (trig_num != cmd->start_arg)
return -EINVAL;
spin_lock_irqsave(&counter->lock, flags);
if (counter->mite_chan)
mite_dma_arm(counter->mite_chan);
else
ret = -EIO;
spin_unlock_irqrestore(&counter->lock, flags);
if (ret < 0)
return ret;
ret = ni_tio_arm(counter, true, NI_GPCT_ARM_IMMEDIATE);
s->async->inttrig = NULL;
return ret;
}
static int ni_tio_input_cmd(struct comedi_subdevice *s)
{
struct ni_gpct *counter = s->private;
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned int cidx = counter->counter_index;
struct comedi_async *async = s->async;
struct comedi_cmd *cmd = &async->cmd;
int ret = 0;
/* write alloc the entire buffer */
comedi_buf_write_alloc(s, async->prealloc_bufsz);
counter->mite_chan->dir = COMEDI_INPUT;
switch (counter_dev->variant) {
case ni_gpct_variant_m_series:
case ni_gpct_variant_660x:
mite_prep_dma(counter->mite_chan, 32, 32);
break;
case ni_gpct_variant_e_series:
mite_prep_dma(counter->mite_chan, 16, 32);
break;
}
ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
ni_tio_configure_dma(counter, true, true);
if (cmd->start_src == TRIG_INT) {
async->inttrig = &ni_tio_input_inttrig;
} else { /* TRIG_NOW || TRIG_EXT || TRIG_OTHER */
async->inttrig = NULL;
mite_dma_arm(counter->mite_chan);
if (cmd->start_src == TRIG_NOW)
ret = ni_tio_arm(counter, true, NI_GPCT_ARM_IMMEDIATE);
else if (cmd->start_src == TRIG_EXT)
ret = ni_tio_arm(counter, true, cmd->start_arg);
}
return ret;
}
static int ni_tio_output_cmd(struct comedi_subdevice *s)
{
struct ni_gpct *counter = s->private;
dev_err(counter->counter_dev->dev->class_dev,
"output commands not yet implemented.\n");
return -ENOTSUPP;
}
static int ni_tio_cmd_setup(struct comedi_subdevice *s)
{
struct comedi_cmd *cmd = &s->async->cmd;
struct ni_gpct *counter = s->private;
unsigned int cidx = counter->counter_index;
int set_gate_source = 0;
unsigned int gate_source;
int retval = 0;
if (cmd->scan_begin_src == TRIG_EXT) {
set_gate_source = 1;
gate_source = cmd->scan_begin_arg;
} else if (cmd->convert_src == TRIG_EXT) {
set_gate_source = 1;
gate_source = cmd->convert_arg;
}
if (set_gate_source)
retval = ni_tio_set_gate_src(counter, 0, gate_source);
if (cmd->flags & CMDF_WAKE_EOS) {
ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
GI_GATE_INTERRUPT_ENABLE(cidx),
GI_GATE_INTERRUPT_ENABLE(cidx));
}
return retval;
}
int ni_tio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
{
struct ni_gpct *counter = s->private;
struct comedi_async *async = s->async;
struct comedi_cmd *cmd = &async->cmd;
int retval = 0;
unsigned long flags;
spin_lock_irqsave(&counter->lock, flags);
if (!counter->mite_chan) {
dev_err(counter->counter_dev->dev->class_dev,
"commands only supported with DMA. ");
dev_err(counter->counter_dev->dev->class_dev,
"Interrupt-driven commands not yet implemented.\n");
retval = -EIO;
} else {
retval = ni_tio_cmd_setup(s);
if (retval == 0) {
if (cmd->flags & CMDF_WRITE)
retval = ni_tio_output_cmd(s);
else
retval = ni_tio_input_cmd(s);
}
}
spin_unlock_irqrestore(&counter->lock, flags);
return retval;
}
EXPORT_SYMBOL_GPL(ni_tio_cmd);
int ni_tio_cmdtest(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_cmd *cmd)
{
struct ni_gpct *counter = s->private;
int err = 0;
unsigned int sources;
/* Step 1 : check if triggers are trivially valid */
sources = TRIG_NOW | TRIG_INT | TRIG_OTHER;
if (ni_tio_counting_mode_registers_present(counter->counter_dev))
sources |= TRIG_EXT;
err |= comedi_check_trigger_src(&cmd->start_src, sources);
err |= comedi_check_trigger_src(&cmd->scan_begin_src,
TRIG_FOLLOW | TRIG_EXT | TRIG_OTHER);
err |= comedi_check_trigger_src(&cmd->convert_src,
TRIG_NOW | TRIG_EXT | TRIG_OTHER);
err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
if (err)
return 1;
/* Step 2a : make sure trigger sources are unique */
err |= comedi_check_trigger_is_unique(cmd->start_src);
err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
err |= comedi_check_trigger_is_unique(cmd->convert_src);
/* Step 2b : and mutually compatible */
if (cmd->convert_src != TRIG_NOW && cmd->scan_begin_src != TRIG_FOLLOW)
err |= -EINVAL;
if (err)
return 2;
/* Step 3: check if arguments are trivially valid */
switch (cmd->start_src) {
case TRIG_NOW:
case TRIG_INT:
case TRIG_OTHER:
err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
break;
case TRIG_EXT:
/* start_arg is the start_trigger passed to ni_tio_arm() */
break;
}
if (cmd->scan_begin_src != TRIG_EXT)
err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
if (cmd->convert_src != TRIG_EXT)
err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
cmd->chanlist_len);
err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
if (err)
return 3;
/* Step 4: fix up any arguments */
/* Step 5: check channel list if it exists */
return 0;
}
EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
int ni_tio_cancel(struct ni_gpct *counter)
{
unsigned int cidx = counter->counter_index;
unsigned long flags;
ni_tio_arm(counter, false, 0);
spin_lock_irqsave(&counter->lock, flags);
if (counter->mite_chan)
mite_dma_disarm(counter->mite_chan);
spin_unlock_irqrestore(&counter->lock, flags);
ni_tio_configure_dma(counter, false, false);
ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
GI_GATE_INTERRUPT_ENABLE(cidx), 0x0);
return 0;
}
EXPORT_SYMBOL_GPL(ni_tio_cancel);
static int should_ack_gate(struct ni_gpct *counter)
{
unsigned long flags;
int retval = 0;
switch (counter->counter_dev->variant) {
case ni_gpct_variant_m_series:
case ni_gpct_variant_660x:
/*
* not sure if 660x really supports gate interrupts
* (the bits are not listed in register-level manual)
*/
return 1;
case ni_gpct_variant_e_series:
/*
* During buffered input counter operation for e-series,
* the gate interrupt is acked automatically by the dma
* controller, due to the Gi_Read/Write_Acknowledges_IRQ
* bits in the input select register.
*/
spin_lock_irqsave(&counter->lock, flags);
{
if (!counter->mite_chan ||
counter->mite_chan->dir != COMEDI_INPUT ||
(mite_done(counter->mite_chan))) {
retval = 1;
}
}
spin_unlock_irqrestore(&counter->lock, flags);
break;
}
return retval;
}
static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter,
int *gate_error,
int *tc_error,
int *perm_stale_data)
{
unsigned int cidx = counter->counter_index;
const unsigned short gxx_status = ni_tio_read(counter,
NITIO_SHARED_STATUS_REG(cidx));
const unsigned short gi_status = ni_tio_read(counter,
NITIO_STATUS_REG(cidx));
unsigned int ack = 0;
if (gate_error)
*gate_error = 0;
if (tc_error)
*tc_error = 0;
if (perm_stale_data)
*perm_stale_data = 0;
if (gxx_status & GI_GATE_ERROR(cidx)) {
ack |= GI_GATE_ERROR_CONFIRM(cidx);
if (gate_error) {
/*
* 660x don't support automatic acknowledgment
* of gate interrupt via dma read/write
* and report bogus gate errors
*/
if (counter->counter_dev->variant !=
ni_gpct_variant_660x)
*gate_error = 1;
}
}
if (gxx_status & GI_TC_ERROR(cidx)) {
ack |= GI_TC_ERROR_CONFIRM(cidx);
if (tc_error)
*tc_error = 1;
}
if (gi_status & GI_TC)
ack |= GI_TC_INTERRUPT_ACK;
if (gi_status & GI_GATE_INTERRUPT) {
if (should_ack_gate(counter))
ack |= GI_GATE_INTERRUPT_ACK;
}
if (ack)
ni_tio_write(counter, ack, NITIO_INT_ACK_REG(cidx));
if (ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)) &
GI_LOADING_ON_GATE) {
if (ni_tio_read(counter, NITIO_STATUS2_REG(cidx)) &
GI_PERMANENT_STALE(cidx)) {
dev_info(counter->counter_dev->dev->class_dev,
"%s: Gi_Permanent_Stale_Data detected.\n",
__func__);
if (perm_stale_data)
*perm_stale_data = 1;
}
}
}
void ni_tio_acknowledge(struct ni_gpct *counter)
{
ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL);
}
EXPORT_SYMBOL_GPL(ni_tio_acknowledge);
void ni_tio_handle_interrupt(struct ni_gpct *counter,
struct comedi_subdevice *s)
{
unsigned int cidx = counter->counter_index;
unsigned long flags;
int gate_error;
int tc_error;
int perm_stale_data;
ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error,
&perm_stale_data);
if (gate_error) {
dev_notice(counter->counter_dev->dev->class_dev,
"%s: Gi_Gate_Error detected.\n", __func__);
s->async->events |= COMEDI_CB_OVERFLOW;
}
if (perm_stale_data)
s->async->events |= COMEDI_CB_ERROR;
switch (counter->counter_dev->variant) {
case ni_gpct_variant_m_series:
case ni_gpct_variant_660x:
if (ni_tio_read(counter, NITIO_DMA_STATUS_REG(cidx)) &
GI_DRQ_ERROR) {
dev_notice(counter->counter_dev->dev->class_dev,
"%s: Gi_DRQ_Error detected.\n", __func__);
s->async->events |= COMEDI_CB_OVERFLOW;
}
break;
case ni_gpct_variant_e_series:
break;
}
spin_lock_irqsave(&counter->lock, flags);
if (counter->mite_chan)
mite_ack_linkc(counter->mite_chan, s, true);
spin_unlock_irqrestore(&counter->lock, flags);
}
EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt);
void ni_tio_set_mite_channel(struct ni_gpct *counter,
struct mite_channel *mite_chan)
{
unsigned long flags;
spin_lock_irqsave(&counter->lock, flags);
counter->mite_chan = mite_chan;
spin_unlock_irqrestore(&counter->lock, flags);
}
EXPORT_SYMBOL_GPL(ni_tio_set_mite_channel);
static int __init ni_tiocmd_init_module(void)
{
return 0;
}
module_init(ni_tiocmd_init_module);
static void __exit ni_tiocmd_cleanup_module(void)
{
}
module_exit(ni_tiocmd_cleanup_module);
MODULE_AUTHOR("Comedi <comedi@comedi.org>");
MODULE_DESCRIPTION("Comedi command support for NI general-purpose counters");
MODULE_LICENSE("GPL");
| null | null | null | null | 100,590 |
66,719 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 66,719 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chrome/browser/safe_search_api/safe_search_url_checker.h"
#include <stddef.h>
#include <memory>
#include <string>
#include <utility>
#include "base/callback.h"
#include "base/json/json_writer.h"
#include "base/macros.h"
#include "base/message_loop/message_loop.h"
#include "base/threading/thread_task_runner_handle.h"
#include "base/values.h"
#include "net/base/net_errors.h"
#include "net/traffic_annotation/network_traffic_annotation_test_helper.h"
#include "net/url_request/test_url_fetcher_factory.h"
#include "net/url_request/url_request_test_util.h"
#include "testing/gmock/include/gmock/gmock.h"
#include "testing/gtest/include/gtest/gtest.h"
#include "url/gurl.h"
using Classification = SafeSearchURLChecker::Classification;
using testing::_;
namespace {
const size_t kCacheSize = 2;
const int kSafeSearchURLCheckerURLFetcherID = 0;
const char* kURLs[] = {
"http://www.randomsite1.com",
"http://www.randomsite2.com",
"http://www.randomsite3.com",
"http://www.randomsite4.com",
"http://www.randomsite5.com",
"http://www.randomsite6.com",
"http://www.randomsite7.com",
"http://www.randomsite8.com",
"http://www.randomsite9.com",
};
std::string BuildResponse(bool is_porn) {
base::DictionaryValue dict;
std::unique_ptr<base::DictionaryValue> classification_dict(
new base::DictionaryValue);
if (is_porn)
classification_dict->SetBoolean("pornography", is_porn);
auto classifications_list = std::make_unique<base::ListValue>();
classifications_list->Append(std::move(classification_dict));
dict.SetWithoutPathExpansion("classifications",
std::move(classifications_list));
std::string result;
base::JSONWriter::Write(dict, &result);
return result;
}
} // namespace
class SafeSearchURLCheckerTest : public testing::Test {
public:
SafeSearchURLCheckerTest()
: next_url_(0),
request_context_(new net::TestURLRequestContextGetter(
base::ThreadTaskRunnerHandle::Get())),
checker_(request_context_.get(),
TRAFFIC_ANNOTATION_FOR_TESTS,
kCacheSize) {}
MOCK_METHOD3(OnCheckDone,
void(const GURL& url,
Classification classification,
bool uncertain));
protected:
GURL GetNewURL() {
CHECK(next_url_ < arraysize(kURLs));
return GURL(kURLs[next_url_++]);
}
// Returns true if the result was returned synchronously (cache hit).
bool CheckURL(const GURL& url) {
return checker_.CheckURL(url,
base::Bind(&SafeSearchURLCheckerTest::OnCheckDone,
base::Unretained(this)));
}
net::TestURLFetcher* GetURLFetcher() {
net::TestURLFetcher* url_fetcher =
url_fetcher_factory_.GetFetcherByID(kSafeSearchURLCheckerURLFetcherID);
EXPECT_TRUE(url_fetcher);
return url_fetcher;
}
void SendResponse(net::Error error, const std::string& response) {
net::TestURLFetcher* url_fetcher = GetURLFetcher();
url_fetcher->set_status(net::URLRequestStatus::FromError(error));
url_fetcher->set_response_code(net::HTTP_OK);
url_fetcher->SetResponseString(response);
url_fetcher->delegate()->OnURLFetchComplete(url_fetcher);
}
void SendValidResponse(bool is_porn) {
SendResponse(net::OK, BuildResponse(is_porn));
}
void SendFailedResponse() { SendResponse(net::ERR_ABORTED, std::string()); }
size_t next_url_;
base::MessageLoop message_loop_;
scoped_refptr<net::TestURLRequestContextGetter> request_context_;
net::TestURLFetcherFactory url_fetcher_factory_;
SafeSearchURLChecker checker_;
};
TEST_F(SafeSearchURLCheckerTest, Simple) {
{
GURL url(GetNewURL());
ASSERT_FALSE(CheckURL(url));
EXPECT_CALL(*this, OnCheckDone(url, Classification::SAFE, false));
SendValidResponse(false);
}
{
GURL url(GetNewURL());
ASSERT_FALSE(CheckURL(url));
EXPECT_CALL(*this, OnCheckDone(url, Classification::UNSAFE, false));
SendValidResponse(true);
}
{
GURL url(GetNewURL());
ASSERT_FALSE(CheckURL(url));
EXPECT_CALL(*this, OnCheckDone(url, Classification::SAFE, true));
SendFailedResponse();
}
}
TEST_F(SafeSearchURLCheckerTest, Cache) {
// One more URL than fit in the cache.
ASSERT_EQ(2u, kCacheSize);
GURL url1(GetNewURL());
GURL url2(GetNewURL());
GURL url3(GetNewURL());
// Populate the cache.
ASSERT_FALSE(CheckURL(url1));
EXPECT_CALL(*this, OnCheckDone(url1, Classification::SAFE, false));
SendValidResponse(false);
ASSERT_FALSE(CheckURL(url2));
EXPECT_CALL(*this, OnCheckDone(url2, Classification::SAFE, false));
SendValidResponse(false);
// Now we should get results synchronously.
EXPECT_CALL(*this, OnCheckDone(url2, Classification::SAFE, false));
ASSERT_TRUE(CheckURL(url2));
EXPECT_CALL(*this, OnCheckDone(url1, Classification::SAFE, false));
ASSERT_TRUE(CheckURL(url1));
// Now |url2| is the LRU and should be evicted on the next check.
ASSERT_FALSE(CheckURL(url3));
EXPECT_CALL(*this, OnCheckDone(url3, Classification::SAFE, false));
SendValidResponse(false);
ASSERT_FALSE(CheckURL(url2));
EXPECT_CALL(*this, OnCheckDone(url2, Classification::SAFE, false));
SendValidResponse(false);
}
TEST_F(SafeSearchURLCheckerTest, CoalesceRequestsToSameURL) {
GURL url(GetNewURL());
// Start two checks for the same URL.
ASSERT_FALSE(CheckURL(url));
ASSERT_FALSE(CheckURL(url));
// A single response should answer both checks.
EXPECT_CALL(*this, OnCheckDone(url, Classification::SAFE, false)).Times(2);
SendValidResponse(false);
}
TEST_F(SafeSearchURLCheckerTest, CacheTimeout) {
GURL url(GetNewURL());
checker_.SetCacheTimeoutForTesting(base::TimeDelta::FromSeconds(0));
ASSERT_FALSE(CheckURL(url));
EXPECT_CALL(*this, OnCheckDone(url, Classification::SAFE, false));
SendValidResponse(false);
// Since the cache timeout is zero, the cache entry should be invalidated
// immediately.
ASSERT_FALSE(CheckURL(url));
EXPECT_CALL(*this, OnCheckDone(url, Classification::UNSAFE, false));
SendValidResponse(true);
}
| null | null | null | null | 63,582 |
51,243 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 51,243 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef UI_EVENTS_ANDROID_SCROLLER_H_
#define UI_EVENTS_ANDROID_SCROLLER_H_
#include "base/time/time.h"
#include "ui/events/events_base_export.h"
#include "ui/events/gesture_curve.h"
#include "ui/gfx/geometry/vector2d_f.h"
namespace ui {
// Native port of android.widget.Scroller.
// * Change-Id: I4365946f890a76fcfa78ca9d69f2a8e0848095a9
// * Please update the Change-Id as upstream Android changes are pulled.
class EVENTS_BASE_EXPORT Scroller : public GestureCurve {
public:
struct Config {
Config();
// Controls fling deceleration. Defaults to 0.015f.
float fling_friction;
// Controls fling accumulation. Defaults to disabled.
bool flywheel_enabled;
};
explicit Scroller(const Config& config);
~Scroller() override;
// GestureCurve implementation.
bool ComputeScrollOffset(base::TimeTicks time,
gfx::Vector2dF* offset,
gfx::Vector2dF* velocity) override;
// Start scrolling by providing a starting point and the distance to travel.
// The default value of 250 milliseconds will be used for the duration.
void StartScroll(float start_x,
float start_y,
float dx,
float dy,
base::TimeTicks start_time);
// Start scrolling by providing a starting point, the distance to travel,
// and the duration of the scroll.
void StartScroll(float start_x,
float start_y,
float dx,
float dy,
base::TimeTicks start_time,
base::TimeDelta duration);
// Start scrolling based on a fling gesture. The distance travelled will
// depend on the initial velocity of the fling.
void Fling(float start_x,
float start_y,
float velocity_x,
float velocity_y,
float min_x,
float max_x,
float min_y,
float max_y,
base::TimeTicks start_time);
// Extend the scroll animation by |extend|. This allows a running animation
// to scroll further and longer when used with |SetFinalX()| or |SetFinalY()|.
void ExtendDuration(base::TimeDelta extend);
void SetFinalX(float new_x);
void SetFinalY(float new_y);
// Stops the animation. Contrary to |ForceFinished()|, aborting the animation
// causes the scroller to move to the final x and y position.
void AbortAnimation();
// Terminate the scroll without affecting the current x and y positions.
void ForceFinished(bool finished);
// Returns whether the scroller has finished scrolling.
bool IsFinished() const;
// Returns the time elapsed since the beginning of the scrolling.
base::TimeDelta GetTimePassed() const;
// Returns how long the scroll event will take.
base::TimeDelta GetDuration() const;
float GetStartX() const;
float GetStartY() const;
float GetCurrX() const;
float GetCurrY() const;
float GetCurrVelocity() const;
float GetCurrVelocityX() const;
float GetCurrVelocityY() const;
float GetFinalX() const;
float GetFinalY() const;
bool IsScrollingInDirection(float xvel, float yvel) const;
private:
enum Mode {
UNDEFINED,
SCROLL_MODE,
FLING_MODE,
};
bool ComputeScrollOffsetInternal(base::TimeTicks time);
void RecomputeDeltas();
double GetSplineDeceleration(float velocity) const;
base::TimeDelta GetSplineFlingDuration(float velocity) const;
double GetSplineFlingDistance(float velocity) const;
Mode mode_;
float start_x_;
float start_y_;
float final_x_;
float final_y_;
float min_x_;
float max_x_;
float min_y_;
float max_y_;
float curr_x_;
float curr_y_;
base::TimeTicks start_time_;
base::TimeTicks curr_time_;
base::TimeDelta duration_;
double duration_seconds_reciprocal_;
float delta_x_;
float delta_x_norm_;
float delta_y_;
float delta_y_norm_;
bool finished_;
bool flywheel_enabled_;
float velocity_;
float curr_velocity_;
float distance_;
float fling_friction_;
float deceleration_;
float tuning_coeff_;
};
} // namespace ui
#endif // UI_EVENTS_ANDROID_SCROLLER_H_
| null | null | null | null | 48,106 |
6,279 | null | train_val | e4311ee51d1e2676001b2d8fcefd92bdd79aad85 | 171,274 | linux | 0 | https://github.com/torvalds/linux | 2017-05-12 08:32:58+10:00 | /*
* US-X2Y AUDIO
* Copyright (c) 2002-2004 by Karsten Wiese
*
* based on
*
* (Tentative) USB Audio Driver for ALSA
*
* Main and PCM part
*
* Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
*
* Many codes borrowed from audio.c by
* Alan Cox (alan@lxorguk.ukuu.org.uk)
* Thomas Sailer (sailer@ife.ee.ethz.ch)
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/usb.h>
#include <linux/moduleparam.h>
#include <sound/core.h>
#include <sound/info.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include "usx2y.h"
#include "usbusx2y.h"
#define USX2Y_NRPACKS 4 /* Default value used for nr of packs per urb.
1 to 4 have been tested ok on uhci.
To use 3 on ohci, you'd need a patch:
look for "0000425-linux-2.6.9-rc4-mm1_ohci-hcd.patch.gz" on
"https://bugtrack.alsa-project.org/alsa-bug/bug_view_page.php?bug_id=0000425"
.
1, 2 and 4 work out of the box on ohci, if I recall correctly.
Bigger is safer operation,
smaller gives lower latencies.
*/
#define USX2Y_NRPACKS_VARIABLE y /* If your system works ok with this module's parameter
nrpacks set to 1, you might as well comment
this #define out, and thereby produce smaller, faster code.
You'd also set USX2Y_NRPACKS to 1 then.
*/
#ifdef USX2Y_NRPACKS_VARIABLE
static int nrpacks = USX2Y_NRPACKS; /* number of packets per urb */
#define nr_of_packs() nrpacks
module_param(nrpacks, int, 0444);
MODULE_PARM_DESC(nrpacks, "Number of packets per URB.");
#else
#define nr_of_packs() USX2Y_NRPACKS
#endif
static int usX2Y_urb_capt_retire(struct snd_usX2Y_substream *subs)
{
struct urb *urb = subs->completed_urb;
struct snd_pcm_runtime *runtime = subs->pcm_substream->runtime;
unsigned char *cp;
int i, len, lens = 0, hwptr_done = subs->hwptr_done;
struct usX2Ydev *usX2Y = subs->usX2Y;
for (i = 0; i < nr_of_packs(); i++) {
cp = (unsigned char*)urb->transfer_buffer + urb->iso_frame_desc[i].offset;
if (urb->iso_frame_desc[i].status) { /* active? hmm, skip this */
snd_printk(KERN_ERR "active frame status %i. "
"Most probably some hardware problem.\n",
urb->iso_frame_desc[i].status);
return urb->iso_frame_desc[i].status;
}
len = urb->iso_frame_desc[i].actual_length / usX2Y->stride;
if (! len) {
snd_printd("0 == len ERROR!\n");
continue;
}
/* copy a data chunk */
if ((hwptr_done + len) > runtime->buffer_size) {
int cnt = runtime->buffer_size - hwptr_done;
int blen = cnt * usX2Y->stride;
memcpy(runtime->dma_area + hwptr_done * usX2Y->stride, cp, blen);
memcpy(runtime->dma_area, cp + blen, len * usX2Y->stride - blen);
} else {
memcpy(runtime->dma_area + hwptr_done * usX2Y->stride, cp,
len * usX2Y->stride);
}
lens += len;
if ((hwptr_done += len) >= runtime->buffer_size)
hwptr_done -= runtime->buffer_size;
}
subs->hwptr_done = hwptr_done;
subs->transfer_done += lens;
/* update the pointer, call callback if necessary */
if (subs->transfer_done >= runtime->period_size) {
subs->transfer_done -= runtime->period_size;
snd_pcm_period_elapsed(subs->pcm_substream);
}
return 0;
}
/*
* prepare urb for playback data pipe
*
* we copy the data directly from the pcm buffer.
* the current position to be copied is held in hwptr field.
* since a urb can handle only a single linear buffer, if the total
* transferred area overflows the buffer boundary, we cannot send
* it directly from the buffer. thus the data is once copied to
* a temporary buffer and urb points to that.
*/
static int usX2Y_urb_play_prepare(struct snd_usX2Y_substream *subs,
struct urb *cap_urb,
struct urb *urb)
{
int count, counts, pack;
struct usX2Ydev *usX2Y = subs->usX2Y;
struct snd_pcm_runtime *runtime = subs->pcm_substream->runtime;
count = 0;
for (pack = 0; pack < nr_of_packs(); pack++) {
/* calculate the size of a packet */
counts = cap_urb->iso_frame_desc[pack].actual_length / usX2Y->stride;
count += counts;
if (counts < 43 || counts > 50) {
snd_printk(KERN_ERR "should not be here with counts=%i\n", counts);
return -EPIPE;
}
/* set up descriptor */
urb->iso_frame_desc[pack].offset = pack ?
urb->iso_frame_desc[pack - 1].offset +
urb->iso_frame_desc[pack - 1].length :
0;
urb->iso_frame_desc[pack].length = cap_urb->iso_frame_desc[pack].actual_length;
}
if (atomic_read(&subs->state) >= state_PRERUNNING)
if (subs->hwptr + count > runtime->buffer_size) {
/* err, the transferred area goes over buffer boundary.
* copy the data to the temp buffer.
*/
int len;
len = runtime->buffer_size - subs->hwptr;
urb->transfer_buffer = subs->tmpbuf;
memcpy(subs->tmpbuf, runtime->dma_area +
subs->hwptr * usX2Y->stride, len * usX2Y->stride);
memcpy(subs->tmpbuf + len * usX2Y->stride,
runtime->dma_area, (count - len) * usX2Y->stride);
subs->hwptr += count;
subs->hwptr -= runtime->buffer_size;
} else {
/* set the buffer pointer */
urb->transfer_buffer = runtime->dma_area + subs->hwptr * usX2Y->stride;
if ((subs->hwptr += count) >= runtime->buffer_size)
subs->hwptr -= runtime->buffer_size;
}
else
urb->transfer_buffer = subs->tmpbuf;
urb->transfer_buffer_length = count * usX2Y->stride;
return 0;
}
/*
* process after playback data complete
*
* update the current position and call callback if a period is processed.
*/
static void usX2Y_urb_play_retire(struct snd_usX2Y_substream *subs, struct urb *urb)
{
struct snd_pcm_runtime *runtime = subs->pcm_substream->runtime;
int len = urb->actual_length / subs->usX2Y->stride;
subs->transfer_done += len;
subs->hwptr_done += len;
if (subs->hwptr_done >= runtime->buffer_size)
subs->hwptr_done -= runtime->buffer_size;
if (subs->transfer_done >= runtime->period_size) {
subs->transfer_done -= runtime->period_size;
snd_pcm_period_elapsed(subs->pcm_substream);
}
}
static int usX2Y_urb_submit(struct snd_usX2Y_substream *subs, struct urb *urb, int frame)
{
int err;
if (!urb)
return -ENODEV;
urb->start_frame = (frame + NRURBS * nr_of_packs()); // let hcd do rollover sanity checks
urb->hcpriv = NULL;
urb->dev = subs->usX2Y->dev; /* we need to set this at each time */
if ((err = usb_submit_urb(urb, GFP_ATOMIC)) < 0) {
snd_printk(KERN_ERR "usb_submit_urb() returned %i\n", err);
return err;
}
return 0;
}
static inline int usX2Y_usbframe_complete(struct snd_usX2Y_substream *capsubs,
struct snd_usX2Y_substream *playbacksubs,
int frame)
{
int err, state;
struct urb *urb = playbacksubs->completed_urb;
state = atomic_read(&playbacksubs->state);
if (NULL != urb) {
if (state == state_RUNNING)
usX2Y_urb_play_retire(playbacksubs, urb);
else if (state >= state_PRERUNNING)
atomic_inc(&playbacksubs->state);
} else {
switch (state) {
case state_STARTING1:
urb = playbacksubs->urb[0];
atomic_inc(&playbacksubs->state);
break;
case state_STARTING2:
urb = playbacksubs->urb[1];
atomic_inc(&playbacksubs->state);
break;
}
}
if (urb) {
if ((err = usX2Y_urb_play_prepare(playbacksubs, capsubs->completed_urb, urb)) ||
(err = usX2Y_urb_submit(playbacksubs, urb, frame))) {
return err;
}
}
playbacksubs->completed_urb = NULL;
state = atomic_read(&capsubs->state);
if (state >= state_PREPARED) {
if (state == state_RUNNING) {
if ((err = usX2Y_urb_capt_retire(capsubs)))
return err;
} else if (state >= state_PRERUNNING)
atomic_inc(&capsubs->state);
if ((err = usX2Y_urb_submit(capsubs, capsubs->completed_urb, frame)))
return err;
}
capsubs->completed_urb = NULL;
return 0;
}
static void usX2Y_clients_stop(struct usX2Ydev *usX2Y)
{
int s, u;
for (s = 0; s < 4; s++) {
struct snd_usX2Y_substream *subs = usX2Y->subs[s];
if (subs) {
snd_printdd("%i %p state=%i\n", s, subs, atomic_read(&subs->state));
atomic_set(&subs->state, state_STOPPED);
}
}
for (s = 0; s < 4; s++) {
struct snd_usX2Y_substream *subs = usX2Y->subs[s];
if (subs) {
if (atomic_read(&subs->state) >= state_PRERUNNING)
snd_pcm_stop_xrun(subs->pcm_substream);
for (u = 0; u < NRURBS; u++) {
struct urb *urb = subs->urb[u];
if (NULL != urb)
snd_printdd("%i status=%i start_frame=%i\n",
u, urb->status, urb->start_frame);
}
}
}
usX2Y->prepare_subs = NULL;
wake_up(&usX2Y->prepare_wait_queue);
}
static void usX2Y_error_urb_status(struct usX2Ydev *usX2Y,
struct snd_usX2Y_substream *subs, struct urb *urb)
{
snd_printk(KERN_ERR "ep=%i stalled with status=%i\n", subs->endpoint, urb->status);
urb->status = 0;
usX2Y_clients_stop(usX2Y);
}
static void i_usX2Y_urb_complete(struct urb *urb)
{
struct snd_usX2Y_substream *subs = urb->context;
struct usX2Ydev *usX2Y = subs->usX2Y;
if (unlikely(atomic_read(&subs->state) < state_PREPARED)) {
snd_printdd("hcd_frame=%i ep=%i%s status=%i start_frame=%i\n",
usb_get_current_frame_number(usX2Y->dev),
subs->endpoint, usb_pipein(urb->pipe) ? "in" : "out",
urb->status, urb->start_frame);
return;
}
if (unlikely(urb->status)) {
usX2Y_error_urb_status(usX2Y, subs, urb);
return;
}
subs->completed_urb = urb;
{
struct snd_usX2Y_substream *capsubs = usX2Y->subs[SNDRV_PCM_STREAM_CAPTURE],
*playbacksubs = usX2Y->subs[SNDRV_PCM_STREAM_PLAYBACK];
if (capsubs->completed_urb &&
atomic_read(&capsubs->state) >= state_PREPARED &&
(playbacksubs->completed_urb ||
atomic_read(&playbacksubs->state) < state_PREPARED)) {
if (!usX2Y_usbframe_complete(capsubs, playbacksubs, urb->start_frame))
usX2Y->wait_iso_frame += nr_of_packs();
else {
snd_printdd("\n");
usX2Y_clients_stop(usX2Y);
}
}
}
}
static void usX2Y_urbs_set_complete(struct usX2Ydev * usX2Y,
void (*complete)(struct urb *))
{
int s, u;
for (s = 0; s < 4; s++) {
struct snd_usX2Y_substream *subs = usX2Y->subs[s];
if (NULL != subs)
for (u = 0; u < NRURBS; u++) {
struct urb * urb = subs->urb[u];
if (NULL != urb)
urb->complete = complete;
}
}
}
static void usX2Y_subs_startup_finish(struct usX2Ydev * usX2Y)
{
usX2Y_urbs_set_complete(usX2Y, i_usX2Y_urb_complete);
usX2Y->prepare_subs = NULL;
}
static void i_usX2Y_subs_startup(struct urb *urb)
{
struct snd_usX2Y_substream *subs = urb->context;
struct usX2Ydev *usX2Y = subs->usX2Y;
struct snd_usX2Y_substream *prepare_subs = usX2Y->prepare_subs;
if (NULL != prepare_subs)
if (urb->start_frame == prepare_subs->urb[0]->start_frame) {
usX2Y_subs_startup_finish(usX2Y);
atomic_inc(&prepare_subs->state);
wake_up(&usX2Y->prepare_wait_queue);
}
i_usX2Y_urb_complete(urb);
}
static void usX2Y_subs_prepare(struct snd_usX2Y_substream *subs)
{
snd_printdd("usX2Y_substream_prepare(%p) ep=%i urb0=%p urb1=%p\n",
subs, subs->endpoint, subs->urb[0], subs->urb[1]);
/* reset the pointer */
subs->hwptr = 0;
subs->hwptr_done = 0;
subs->transfer_done = 0;
}
static void usX2Y_urb_release(struct urb **urb, int free_tb)
{
if (*urb) {
usb_kill_urb(*urb);
if (free_tb)
kfree((*urb)->transfer_buffer);
usb_free_urb(*urb);
*urb = NULL;
}
}
/*
* release a substreams urbs
*/
static void usX2Y_urbs_release(struct snd_usX2Y_substream *subs)
{
int i;
snd_printdd("usX2Y_urbs_release() %i\n", subs->endpoint);
for (i = 0; i < NRURBS; i++)
usX2Y_urb_release(subs->urb + i,
subs != subs->usX2Y->subs[SNDRV_PCM_STREAM_PLAYBACK]);
kfree(subs->tmpbuf);
subs->tmpbuf = NULL;
}
/*
* initialize a substream's urbs
*/
static int usX2Y_urbs_allocate(struct snd_usX2Y_substream *subs)
{
int i;
unsigned int pipe;
int is_playback = subs == subs->usX2Y->subs[SNDRV_PCM_STREAM_PLAYBACK];
struct usb_device *dev = subs->usX2Y->dev;
pipe = is_playback ? usb_sndisocpipe(dev, subs->endpoint) :
usb_rcvisocpipe(dev, subs->endpoint);
subs->maxpacksize = usb_maxpacket(dev, pipe, is_playback);
if (!subs->maxpacksize)
return -EINVAL;
if (is_playback && NULL == subs->tmpbuf) { /* allocate a temporary buffer for playback */
subs->tmpbuf = kcalloc(nr_of_packs(), subs->maxpacksize, GFP_KERNEL);
if (NULL == subs->tmpbuf) {
snd_printk(KERN_ERR "cannot malloc tmpbuf\n");
return -ENOMEM;
}
}
/* allocate and initialize data urbs */
for (i = 0; i < NRURBS; i++) {
struct urb **purb = subs->urb + i;
if (*purb) {
usb_kill_urb(*purb);
continue;
}
*purb = usb_alloc_urb(nr_of_packs(), GFP_KERNEL);
if (NULL == *purb) {
usX2Y_urbs_release(subs);
return -ENOMEM;
}
if (!is_playback && !(*purb)->transfer_buffer) {
/* allocate a capture buffer per urb */
(*purb)->transfer_buffer = kmalloc(subs->maxpacksize * nr_of_packs(), GFP_KERNEL);
if (NULL == (*purb)->transfer_buffer) {
usX2Y_urbs_release(subs);
return -ENOMEM;
}
}
(*purb)->dev = dev;
(*purb)->pipe = pipe;
(*purb)->number_of_packets = nr_of_packs();
(*purb)->context = subs;
(*purb)->interval = 1;
(*purb)->complete = i_usX2Y_subs_startup;
}
return 0;
}
static void usX2Y_subs_startup(struct snd_usX2Y_substream *subs)
{
struct usX2Ydev *usX2Y = subs->usX2Y;
usX2Y->prepare_subs = subs;
subs->urb[0]->start_frame = -1;
wmb();
usX2Y_urbs_set_complete(usX2Y, i_usX2Y_subs_startup);
}
static int usX2Y_urbs_start(struct snd_usX2Y_substream *subs)
{
int i, err;
struct usX2Ydev *usX2Y = subs->usX2Y;
if ((err = usX2Y_urbs_allocate(subs)) < 0)
return err;
subs->completed_urb = NULL;
for (i = 0; i < 4; i++) {
struct snd_usX2Y_substream *subs = usX2Y->subs[i];
if (subs != NULL && atomic_read(&subs->state) >= state_PREPARED)
goto start;
}
start:
usX2Y_subs_startup(subs);
for (i = 0; i < NRURBS; i++) {
struct urb *urb = subs->urb[i];
if (usb_pipein(urb->pipe)) {
unsigned long pack;
if (0 == i)
atomic_set(&subs->state, state_STARTING3);
urb->dev = usX2Y->dev;
for (pack = 0; pack < nr_of_packs(); pack++) {
urb->iso_frame_desc[pack].offset = subs->maxpacksize * pack;
urb->iso_frame_desc[pack].length = subs->maxpacksize;
}
urb->transfer_buffer_length = subs->maxpacksize * nr_of_packs();
if ((err = usb_submit_urb(urb, GFP_ATOMIC)) < 0) {
snd_printk (KERN_ERR "cannot submit datapipe for urb %d, err = %d\n", i, err);
err = -EPIPE;
goto cleanup;
} else
if (i == 0)
usX2Y->wait_iso_frame = urb->start_frame;
urb->transfer_flags = 0;
} else {
atomic_set(&subs->state, state_STARTING1);
break;
}
}
err = 0;
wait_event(usX2Y->prepare_wait_queue, NULL == usX2Y->prepare_subs);
if (atomic_read(&subs->state) != state_PREPARED)
err = -EPIPE;
cleanup:
if (err) {
usX2Y_subs_startup_finish(usX2Y);
usX2Y_clients_stop(usX2Y); // something is completely wroong > stop evrything
}
return err;
}
/*
* return the current pcm pointer. just return the hwptr_done value.
*/
static snd_pcm_uframes_t snd_usX2Y_pcm_pointer(struct snd_pcm_substream *substream)
{
struct snd_usX2Y_substream *subs = substream->runtime->private_data;
return subs->hwptr_done;
}
/*
* start/stop substream
*/
static int snd_usX2Y_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
{
struct snd_usX2Y_substream *subs = substream->runtime->private_data;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
snd_printdd("snd_usX2Y_pcm_trigger(START)\n");
if (atomic_read(&subs->state) == state_PREPARED &&
atomic_read(&subs->usX2Y->subs[SNDRV_PCM_STREAM_CAPTURE]->state) >= state_PREPARED) {
atomic_set(&subs->state, state_PRERUNNING);
} else {
snd_printdd("\n");
return -EPIPE;
}
break;
case SNDRV_PCM_TRIGGER_STOP:
snd_printdd("snd_usX2Y_pcm_trigger(STOP)\n");
if (atomic_read(&subs->state) >= state_PRERUNNING)
atomic_set(&subs->state, state_PREPARED);
break;
default:
return -EINVAL;
}
return 0;
}
/*
* allocate a buffer, setup samplerate
*
* so far we use a physically linear buffer although packetize transfer
* doesn't need a continuous area.
* if sg buffer is supported on the later version of alsa, we'll follow
* that.
*/
static struct s_c2
{
char c1, c2;
}
SetRate44100[] =
{
{ 0x14, 0x08}, // this line sets 44100, well actually a little less
{ 0x18, 0x40}, // only tascam / frontier design knows the further lines .......
{ 0x18, 0x42},
{ 0x18, 0x45},
{ 0x18, 0x46},
{ 0x18, 0x48},
{ 0x18, 0x4A},
{ 0x18, 0x4C},
{ 0x18, 0x4E},
{ 0x18, 0x50},
{ 0x18, 0x52},
{ 0x18, 0x54},
{ 0x18, 0x56},
{ 0x18, 0x58},
{ 0x18, 0x5A},
{ 0x18, 0x5C},
{ 0x18, 0x5E},
{ 0x18, 0x60},
{ 0x18, 0x62},
{ 0x18, 0x64},
{ 0x18, 0x66},
{ 0x18, 0x68},
{ 0x18, 0x6A},
{ 0x18, 0x6C},
{ 0x18, 0x6E},
{ 0x18, 0x70},
{ 0x18, 0x72},
{ 0x18, 0x74},
{ 0x18, 0x76},
{ 0x18, 0x78},
{ 0x18, 0x7A},
{ 0x18, 0x7C},
{ 0x18, 0x7E}
};
static struct s_c2 SetRate48000[] =
{
{ 0x14, 0x09}, // this line sets 48000, well actually a little less
{ 0x18, 0x40}, // only tascam / frontier design knows the further lines .......
{ 0x18, 0x42},
{ 0x18, 0x45},
{ 0x18, 0x46},
{ 0x18, 0x48},
{ 0x18, 0x4A},
{ 0x18, 0x4C},
{ 0x18, 0x4E},
{ 0x18, 0x50},
{ 0x18, 0x52},
{ 0x18, 0x54},
{ 0x18, 0x56},
{ 0x18, 0x58},
{ 0x18, 0x5A},
{ 0x18, 0x5C},
{ 0x18, 0x5E},
{ 0x18, 0x60},
{ 0x18, 0x62},
{ 0x18, 0x64},
{ 0x18, 0x66},
{ 0x18, 0x68},
{ 0x18, 0x6A},
{ 0x18, 0x6C},
{ 0x18, 0x6E},
{ 0x18, 0x70},
{ 0x18, 0x73},
{ 0x18, 0x74},
{ 0x18, 0x76},
{ 0x18, 0x78},
{ 0x18, 0x7A},
{ 0x18, 0x7C},
{ 0x18, 0x7E}
};
#define NOOF_SETRATE_URBS ARRAY_SIZE(SetRate48000)
static void i_usX2Y_04Int(struct urb *urb)
{
struct usX2Ydev *usX2Y = urb->context;
if (urb->status)
snd_printk(KERN_ERR "snd_usX2Y_04Int() urb->status=%i\n", urb->status);
if (0 == --usX2Y->US04->len)
wake_up(&usX2Y->In04WaitQueue);
}
static int usX2Y_rate_set(struct usX2Ydev *usX2Y, int rate)
{
int err = 0, i;
struct snd_usX2Y_urbSeq *us = NULL;
int *usbdata = NULL;
struct s_c2 *ra = rate == 48000 ? SetRate48000 : SetRate44100;
if (usX2Y->rate != rate) {
us = kzalloc(sizeof(*us) + sizeof(struct urb*) * NOOF_SETRATE_URBS, GFP_KERNEL);
if (NULL == us) {
err = -ENOMEM;
goto cleanup;
}
usbdata = kmalloc(sizeof(int) * NOOF_SETRATE_URBS, GFP_KERNEL);
if (NULL == usbdata) {
err = -ENOMEM;
goto cleanup;
}
for (i = 0; i < NOOF_SETRATE_URBS; ++i) {
if (NULL == (us->urb[i] = usb_alloc_urb(0, GFP_KERNEL))) {
err = -ENOMEM;
goto cleanup;
}
((char*)(usbdata + i))[0] = ra[i].c1;
((char*)(usbdata + i))[1] = ra[i].c2;
usb_fill_bulk_urb(us->urb[i], usX2Y->dev, usb_sndbulkpipe(usX2Y->dev, 4),
usbdata + i, 2, i_usX2Y_04Int, usX2Y);
}
us->submitted = 0;
us->len = NOOF_SETRATE_URBS;
usX2Y->US04 = us;
wait_event_timeout(usX2Y->In04WaitQueue, 0 == us->len, HZ);
usX2Y->US04 = NULL;
if (us->len)
err = -ENODEV;
cleanup:
if (us) {
us->submitted = 2*NOOF_SETRATE_URBS;
for (i = 0; i < NOOF_SETRATE_URBS; ++i) {
struct urb *urb = us->urb[i];
if (urb->status) {
if (!err)
err = -ENODEV;
usb_kill_urb(urb);
}
usb_free_urb(urb);
}
usX2Y->US04 = NULL;
kfree(usbdata);
kfree(us);
if (!err)
usX2Y->rate = rate;
}
}
return err;
}
static int usX2Y_format_set(struct usX2Ydev *usX2Y, snd_pcm_format_t format)
{
int alternate, err;
struct list_head* p;
if (format == SNDRV_PCM_FORMAT_S24_3LE) {
alternate = 2;
usX2Y->stride = 6;
} else {
alternate = 1;
usX2Y->stride = 4;
}
list_for_each(p, &usX2Y->midi_list) {
snd_usbmidi_input_stop(p);
}
usb_kill_urb(usX2Y->In04urb);
if ((err = usb_set_interface(usX2Y->dev, 0, alternate))) {
snd_printk(KERN_ERR "usb_set_interface error \n");
return err;
}
usX2Y->In04urb->dev = usX2Y->dev;
err = usb_submit_urb(usX2Y->In04urb, GFP_KERNEL);
list_for_each(p, &usX2Y->midi_list) {
snd_usbmidi_input_start(p);
}
usX2Y->format = format;
usX2Y->rate = 0;
return err;
}
static int snd_usX2Y_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
int err = 0;
unsigned int rate = params_rate(hw_params);
snd_pcm_format_t format = params_format(hw_params);
struct snd_card *card = substream->pstr->pcm->card;
struct usX2Ydev *dev = usX2Y(card);
int i;
mutex_lock(&usX2Y(card)->pcm_mutex);
snd_printdd("snd_usX2Y_hw_params(%p, %p)\n", substream, hw_params);
/* all pcm substreams off one usX2Y have to operate at the same
* rate & format
*/
for (i = 0; i < dev->pcm_devs * 2; i++) {
struct snd_usX2Y_substream *subs = dev->subs[i];
struct snd_pcm_substream *test_substream;
if (!subs)
continue;
test_substream = subs->pcm_substream;
if (!test_substream || test_substream == substream ||
!test_substream->runtime)
continue;
if ((test_substream->runtime->format &&
test_substream->runtime->format != format) ||
(test_substream->runtime->rate &&
test_substream->runtime->rate != rate)) {
err = -EINVAL;
goto error;
}
}
err = snd_pcm_lib_malloc_pages(substream,
params_buffer_bytes(hw_params));
if (err < 0) {
snd_printk(KERN_ERR "snd_pcm_lib_malloc_pages(%p, %i) returned %i\n",
substream, params_buffer_bytes(hw_params), err);
goto error;
}
error:
mutex_unlock(&usX2Y(card)->pcm_mutex);
return err;
}
/*
* free the buffer
*/
static int snd_usX2Y_pcm_hw_free(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_usX2Y_substream *subs = runtime->private_data;
mutex_lock(&subs->usX2Y->pcm_mutex);
snd_printdd("snd_usX2Y_hw_free(%p)\n", substream);
if (SNDRV_PCM_STREAM_PLAYBACK == substream->stream) {
struct snd_usX2Y_substream *cap_subs = subs->usX2Y->subs[SNDRV_PCM_STREAM_CAPTURE];
atomic_set(&subs->state, state_STOPPED);
usX2Y_urbs_release(subs);
if (!cap_subs->pcm_substream ||
!cap_subs->pcm_substream->runtime ||
!cap_subs->pcm_substream->runtime->status ||
cap_subs->pcm_substream->runtime->status->state < SNDRV_PCM_STATE_PREPARED) {
atomic_set(&cap_subs->state, state_STOPPED);
usX2Y_urbs_release(cap_subs);
}
} else {
struct snd_usX2Y_substream *playback_subs = subs->usX2Y->subs[SNDRV_PCM_STREAM_PLAYBACK];
if (atomic_read(&playback_subs->state) < state_PREPARED) {
atomic_set(&subs->state, state_STOPPED);
usX2Y_urbs_release(subs);
}
}
mutex_unlock(&subs->usX2Y->pcm_mutex);
return snd_pcm_lib_free_pages(substream);
}
/*
* prepare callback
*
* set format and initialize urbs
*/
static int snd_usX2Y_pcm_prepare(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_usX2Y_substream *subs = runtime->private_data;
struct usX2Ydev *usX2Y = subs->usX2Y;
struct snd_usX2Y_substream *capsubs = subs->usX2Y->subs[SNDRV_PCM_STREAM_CAPTURE];
int err = 0;
snd_printdd("snd_usX2Y_pcm_prepare(%p)\n", substream);
mutex_lock(&usX2Y->pcm_mutex);
usX2Y_subs_prepare(subs);
// Start hardware streams
// SyncStream first....
if (atomic_read(&capsubs->state) < state_PREPARED) {
if (usX2Y->format != runtime->format)
if ((err = usX2Y_format_set(usX2Y, runtime->format)) < 0)
goto up_prepare_mutex;
if (usX2Y->rate != runtime->rate)
if ((err = usX2Y_rate_set(usX2Y, runtime->rate)) < 0)
goto up_prepare_mutex;
snd_printdd("starting capture pipe for %s\n", subs == capsubs ? "self" : "playpipe");
if (0 > (err = usX2Y_urbs_start(capsubs)))
goto up_prepare_mutex;
}
if (subs != capsubs && atomic_read(&subs->state) < state_PREPARED)
err = usX2Y_urbs_start(subs);
up_prepare_mutex:
mutex_unlock(&usX2Y->pcm_mutex);
return err;
}
static struct snd_pcm_hardware snd_usX2Y_2c =
{
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_BATCH),
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_3LE,
.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
.rate_min = 44100,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
.buffer_bytes_max = (2*128*1024),
.period_bytes_min = 64,
.period_bytes_max = (128*1024),
.periods_min = 2,
.periods_max = 1024,
.fifo_size = 0
};
static int snd_usX2Y_pcm_open(struct snd_pcm_substream *substream)
{
struct snd_usX2Y_substream *subs = ((struct snd_usX2Y_substream **)
snd_pcm_substream_chip(substream))[substream->stream];
struct snd_pcm_runtime *runtime = substream->runtime;
if (subs->usX2Y->chip_status & USX2Y_STAT_CHIP_MMAP_PCM_URBS)
return -EBUSY;
runtime->hw = snd_usX2Y_2c;
runtime->private_data = subs;
subs->pcm_substream = substream;
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 1000, 200000);
return 0;
}
static int snd_usX2Y_pcm_close(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_usX2Y_substream *subs = runtime->private_data;
subs->pcm_substream = NULL;
return 0;
}
static struct snd_pcm_ops snd_usX2Y_pcm_ops =
{
.open = snd_usX2Y_pcm_open,
.close = snd_usX2Y_pcm_close,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = snd_usX2Y_pcm_hw_params,
.hw_free = snd_usX2Y_pcm_hw_free,
.prepare = snd_usX2Y_pcm_prepare,
.trigger = snd_usX2Y_pcm_trigger,
.pointer = snd_usX2Y_pcm_pointer,
};
/*
* free a usb stream instance
*/
static void usX2Y_audio_stream_free(struct snd_usX2Y_substream **usX2Y_substream)
{
kfree(usX2Y_substream[SNDRV_PCM_STREAM_PLAYBACK]);
usX2Y_substream[SNDRV_PCM_STREAM_PLAYBACK] = NULL;
kfree(usX2Y_substream[SNDRV_PCM_STREAM_CAPTURE]);
usX2Y_substream[SNDRV_PCM_STREAM_CAPTURE] = NULL;
}
static void snd_usX2Y_pcm_private_free(struct snd_pcm *pcm)
{
struct snd_usX2Y_substream **usX2Y_stream = pcm->private_data;
if (usX2Y_stream)
usX2Y_audio_stream_free(usX2Y_stream);
}
static int usX2Y_audio_stream_new(struct snd_card *card, int playback_endpoint, int capture_endpoint)
{
struct snd_pcm *pcm;
int err, i;
struct snd_usX2Y_substream **usX2Y_substream =
usX2Y(card)->subs + 2 * usX2Y(card)->pcm_devs;
for (i = playback_endpoint ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
i <= SNDRV_PCM_STREAM_CAPTURE; ++i) {
usX2Y_substream[i] = kzalloc(sizeof(struct snd_usX2Y_substream), GFP_KERNEL);
if (NULL == usX2Y_substream[i]) {
snd_printk(KERN_ERR "cannot malloc\n");
return -ENOMEM;
}
usX2Y_substream[i]->usX2Y = usX2Y(card);
}
if (playback_endpoint)
usX2Y_substream[SNDRV_PCM_STREAM_PLAYBACK]->endpoint = playback_endpoint;
usX2Y_substream[SNDRV_PCM_STREAM_CAPTURE]->endpoint = capture_endpoint;
err = snd_pcm_new(card, NAME_ALLCAPS" Audio", usX2Y(card)->pcm_devs,
playback_endpoint ? 1 : 0, 1,
&pcm);
if (err < 0) {
usX2Y_audio_stream_free(usX2Y_substream);
return err;
}
if (playback_endpoint)
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_usX2Y_pcm_ops);
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_usX2Y_pcm_ops);
pcm->private_data = usX2Y_substream;
pcm->private_free = snd_usX2Y_pcm_private_free;
pcm->info_flags = 0;
sprintf(pcm->name, NAME_ALLCAPS" Audio #%d", usX2Y(card)->pcm_devs);
if ((playback_endpoint &&
0 > (err = snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
SNDRV_DMA_TYPE_CONTINUOUS,
snd_dma_continuous_data(GFP_KERNEL),
64*1024, 128*1024))) ||
0 > (err = snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
SNDRV_DMA_TYPE_CONTINUOUS,
snd_dma_continuous_data(GFP_KERNEL),
64*1024, 128*1024))) {
snd_usX2Y_pcm_private_free(pcm);
return err;
}
usX2Y(card)->pcm_devs++;
return 0;
}
/*
* create a chip instance and set its names.
*/
int usX2Y_audio_create(struct snd_card *card)
{
int err = 0;
INIT_LIST_HEAD(&usX2Y(card)->pcm_list);
if (0 > (err = usX2Y_audio_stream_new(card, 0xA, 0x8)))
return err;
if (le16_to_cpu(usX2Y(card)->dev->descriptor.idProduct) == USB_ID_US428)
if (0 > (err = usX2Y_audio_stream_new(card, 0, 0xA)))
return err;
if (le16_to_cpu(usX2Y(card)->dev->descriptor.idProduct) != USB_ID_US122)
err = usX2Y_rate_set(usX2Y(card), 44100); // Lets us428 recognize output-volume settings, disturbs us122.
return err;
}
| null | null | null | null | 79,621 |
26,195 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 26,195 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef EXTENSIONS_BROWSER_UPDATER_UPDATE_SERVICE_H_
#define EXTENSIONS_BROWSER_UPDATER_UPDATE_SERVICE_H_
#include <map>
#include <memory>
#include <set>
#include <string>
#include <vector>
#include "base/callback.h"
#include "base/macros.h"
#include "base/memory/weak_ptr.h"
#include "base/threading/thread_checker.h"
#include "components/keyed_service/core/keyed_service.h"
#include "components/update_client/update_client.h"
namespace base {
class Version;
}
namespace content {
class BrowserContext;
}
namespace update_client {
enum class Error;
class UpdateClient;
}
namespace extensions {
class UpdateDataProvider;
class UpdateServiceFactory;
struct ExtensionUpdateCheckParams;
// This service manages the autoupdate of extensions. It should eventually
// replace ExtensionUpdater in Chrome.
// TODO(rockot): Replace ExtensionUpdater with this service.
class UpdateService : public KeyedService,
update_client::UpdateClient::Observer {
public:
static UpdateService* Get(content::BrowserContext* context);
void Shutdown() override;
void SendUninstallPing(const std::string& id,
const base::Version& version,
int reason);
// Starts an update check for each of extensions stored in |update_params|.
// If there are any updates available, they will be downloaded, checked for
// integrity, unpacked, and then passed off to the
// ExtensionSystem::InstallUpdate method for install completion.
void StartUpdateCheck(const ExtensionUpdateCheckParams& update_params,
base::OnceClosure callback);
// This function verifies if the current implementation can update
// |extension_id|.
bool CanUpdate(const std::string& extension_id) const;
// Overriden from update_client::UpdateClient::Observer.
void OnEvent(Events event, const std::string& id) override;
private:
friend class UpdateServiceFactory;
friend std::unique_ptr<UpdateService>::deleter_type;
UpdateService(content::BrowserContext* context,
scoped_refptr<update_client::UpdateClient> update_client);
~UpdateService() override;
// This function is executed by the update client after an update check
// request has completed.
void UpdateCheckComplete(update_client::Error error);
struct InProgressUpdate {
InProgressUpdate(base::OnceClosure cb);
~InProgressUpdate();
InProgressUpdate(const InProgressUpdate& other) = delete;
InProgressUpdate& operator=(const InProgressUpdate& other) = delete;
InProgressUpdate(InProgressUpdate&& other);
InProgressUpdate& operator=(InProgressUpdate&& other);
base::OnceClosure callback;
std::set<std::string> pending_extension_ids;
};
content::BrowserContext* browser_context_;
scoped_refptr<update_client::UpdateClient> update_client_;
scoped_refptr<UpdateDataProvider> update_data_provider_;
// The set of extension IDs that are being checked for update.
std::set<std::string> updating_extension_ids_;
std::vector<InProgressUpdate> in_progress_updates_;
THREAD_CHECKER(thread_checker_);
// used to create WeakPtrs to |this|.
base::WeakPtrFactory<UpdateService> weak_ptr_factory_;
DISALLOW_COPY_AND_ASSIGN(UpdateService);
};
} // namespace extensions
#endif // EXTENSIONS_BROWSER_UPDATER_UPDATE_SERVICE_H_
| null | null | null | null | 23,058 |
59,706 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 59,706 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | // Copyright 2017 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chrome/browser/extensions/api/networking_cast_private/networking_cast_private_api.h"
#include <utility>
#include "base/bind.h"
#include "chrome/common/extensions/api/networking_cast_private.h"
#include "extensions/browser/api/extensions_api_client.h"
#include "extensions/browser/api/networking_private/networking_cast_private_delegate.h"
#if defined(OS_CHROMEOS)
#include "chromeos/network/network_device_handler.h"
#include "chromeos/network/network_handler.h"
#include "third_party/cros_system_api/dbus/shill/dbus-constants.h"
#endif
namespace private_api = extensions::api::networking_private;
namespace cast_api = extensions::api::networking_cast_private;
namespace extensions {
namespace {
#if defined(OS_CHROMEOS)
// Parses TDLS status returned by network handler to networking_cast_private
// TDLS status type.
cast_api::TDLSStatus ParseTDLSStatus(const std::string& status) {
if (status == shill::kTDLSConnectedState)
return cast_api::TDLS_STATUS_CONNECTED;
if (status == shill::kTDLSNonexistentState)
return cast_api::TDLS_STATUS_NONEXISTENT;
if (status == shill::kTDLSDisabledState)
return cast_api::TDLS_STATUS_DISABLED;
if (status == shill::kTDLSDisconnectedState)
return cast_api::TDLS_STATUS_DISCONNECTED;
if (status == shill::kTDLSUnknownState)
return cast_api::TDLS_STATUS_UNKNOWN;
NOTREACHED() << "Unknown TDLS status " << status;
return cast_api::TDLS_STATUS_UNKNOWN;
}
#endif
std::unique_ptr<NetworkingCastPrivateDelegate::Credentials> AsCastCredentials(
api::networking_cast_private::VerificationProperties& properties) {
return std::make_unique<NetworkingCastPrivateDelegate::Credentials>(
properties.certificate,
properties.intermediate_certificates
? *properties.intermediate_certificates
: std::vector<std::string>(),
properties.signed_data, properties.device_ssid, properties.device_serial,
properties.device_bssid, properties.public_key, properties.nonce);
}
} // namespace
NetworkingCastPrivateVerifyDestinationFunction::
~NetworkingCastPrivateVerifyDestinationFunction() {}
ExtensionFunction::ResponseAction
NetworkingCastPrivateVerifyDestinationFunction::Run() {
std::unique_ptr<cast_api::VerifyDestination::Params> params =
cast_api::VerifyDestination::Params::Create(*args_);
EXTENSION_FUNCTION_VALIDATE(params);
NetworkingCastPrivateDelegate* delegate =
ExtensionsAPIClient::Get()->GetNetworkingCastPrivateDelegate();
delegate->VerifyDestination(
AsCastCredentials(params->properties),
base::Bind(&NetworkingCastPrivateVerifyDestinationFunction::Success,
this),
base::Bind(&NetworkingCastPrivateVerifyDestinationFunction::Failure,
this));
// VerifyDestination might respond synchronously, e.g. in tests.
return did_respond() ? AlreadyResponded() : RespondLater();
}
void NetworkingCastPrivateVerifyDestinationFunction::Success(bool result) {
Respond(ArgumentList(cast_api::VerifyDestination::Results::Create(result)));
}
void NetworkingCastPrivateVerifyDestinationFunction::Failure(
const std::string& error) {
Respond(Error(error));
}
NetworkingCastPrivateVerifyAndEncryptCredentialsFunction::
~NetworkingCastPrivateVerifyAndEncryptCredentialsFunction() {}
ExtensionFunction::ResponseAction
NetworkingCastPrivateVerifyAndEncryptCredentialsFunction::Run() {
std::unique_ptr<cast_api::VerifyAndEncryptCredentials::Params> params =
cast_api::VerifyAndEncryptCredentials::Params::Create(*args_);
EXTENSION_FUNCTION_VALIDATE(params);
NetworkingCastPrivateDelegate* delegate =
ExtensionsAPIClient::Get()->GetNetworkingCastPrivateDelegate();
delegate->VerifyAndEncryptCredentials(
params->network_guid, AsCastCredentials(params->properties),
base::Bind(
&NetworkingCastPrivateVerifyAndEncryptCredentialsFunction::Success,
this),
base::Bind(
&NetworkingCastPrivateVerifyAndEncryptCredentialsFunction::Failure,
this));
// VerifyAndEncryptCredentials might respond synchronously, e.g. in tests.
return did_respond() ? AlreadyResponded() : RespondLater();
}
void NetworkingCastPrivateVerifyAndEncryptCredentialsFunction::Success(
const std::string& result) {
Respond(ArgumentList(
cast_api::VerifyAndEncryptCredentials::Results::Create(result)));
}
void NetworkingCastPrivateVerifyAndEncryptCredentialsFunction::Failure(
const std::string& error) {
Respond(Error(error));
}
NetworkingCastPrivateVerifyAndEncryptDataFunction::
~NetworkingCastPrivateVerifyAndEncryptDataFunction() {}
ExtensionFunction::ResponseAction
NetworkingCastPrivateVerifyAndEncryptDataFunction::Run() {
std::unique_ptr<cast_api::VerifyAndEncryptData::Params> params =
cast_api::VerifyAndEncryptData::Params::Create(*args_);
EXTENSION_FUNCTION_VALIDATE(params);
NetworkingCastPrivateDelegate* delegate =
ExtensionsAPIClient::Get()->GetNetworkingCastPrivateDelegate();
delegate->VerifyAndEncryptData(
params->data, AsCastCredentials(params->properties),
base::Bind(&NetworkingCastPrivateVerifyAndEncryptDataFunction::Success,
this),
base::Bind(&NetworkingCastPrivateVerifyAndEncryptDataFunction::Failure,
this));
// VerifyAndEncryptData might respond synchronously, e.g. in tests.
return did_respond() ? AlreadyResponded() : RespondLater();
}
void NetworkingCastPrivateVerifyAndEncryptDataFunction::Success(
const std::string& result) {
Respond(
ArgumentList(cast_api::VerifyAndEncryptData::Results::Create(result)));
}
void NetworkingCastPrivateVerifyAndEncryptDataFunction::Failure(
const std::string& error) {
Respond(Error(error));
}
NetworkingCastPrivateSetWifiTDLSEnabledStateFunction::
~NetworkingCastPrivateSetWifiTDLSEnabledStateFunction() {}
ExtensionFunction::ResponseAction
NetworkingCastPrivateSetWifiTDLSEnabledStateFunction::Run() {
std::unique_ptr<cast_api::SetWifiTDLSEnabledState::Params> params =
cast_api::SetWifiTDLSEnabledState::Params::Create(*args_);
EXTENSION_FUNCTION_VALIDATE(params);
#if defined(OS_CHROMEOS)
chromeos::NetworkHandler::Get()->network_device_handler()->SetWifiTDLSEnabled(
params->ip_or_mac_address, params->enabled,
base::Bind(&NetworkingCastPrivateSetWifiTDLSEnabledStateFunction::Success,
this),
base::Bind(&NetworkingCastPrivateSetWifiTDLSEnabledStateFunction::Failure,
this));
// SetWifiTDLSEnabled might respond synchronously, e.g. in tests.
return did_respond() ? AlreadyResponded() : RespondLater();
#else
return RespondNow(Error("Not supported"));
#endif
}
#if defined(OS_CHROMEOS)
void NetworkingCastPrivateSetWifiTDLSEnabledStateFunction::Success(
const std::string& result) {
Respond(ArgumentList(cast_api::SetWifiTDLSEnabledState::Results::Create(
ParseTDLSStatus(result))));
}
void NetworkingCastPrivateSetWifiTDLSEnabledStateFunction::Failure(
const std::string& error,
std::unique_ptr<base::DictionaryValue> error_data) {
Respond(Error(error));
}
#endif
NetworkingCastPrivateGetWifiTDLSStatusFunction::
~NetworkingCastPrivateGetWifiTDLSStatusFunction() {}
ExtensionFunction::ResponseAction
NetworkingCastPrivateGetWifiTDLSStatusFunction::Run() {
std::unique_ptr<cast_api::GetWifiTDLSStatus::Params> params =
cast_api::GetWifiTDLSStatus::Params::Create(*args_);
EXTENSION_FUNCTION_VALIDATE(params);
#if defined(OS_CHROMEOS)
chromeos::NetworkHandler::Get()->network_device_handler()->GetWifiTDLSStatus(
params->ip_or_mac_address,
base::Bind(&NetworkingCastPrivateGetWifiTDLSStatusFunction::Success,
this),
base::Bind(&NetworkingCastPrivateGetWifiTDLSStatusFunction::Failure,
this));
// GetWifiTDLSStatus might respond synchronously, e.g. in tests.
return did_respond() ? AlreadyResponded() : RespondLater();
#else
return RespondNow(Error("Not supported"));
#endif
}
#if defined(OS_CHROMEOS)
void NetworkingCastPrivateGetWifiTDLSStatusFunction::Success(
const std::string& result) {
Respond(ArgumentList(
cast_api::GetWifiTDLSStatus::Results::Create(ParseTDLSStatus(result))));
}
void NetworkingCastPrivateGetWifiTDLSStatusFunction::Failure(
const std::string& error,
std::unique_ptr<base::DictionaryValue> error_data) {
Respond(Error(error));
}
#endif
} // namespace extensions
| null | null | null | null | 56,569 |
27,647 | null | train_val | 796a0e014bc3985709c0a35538d606ef1da31e1b | 27,647 | Chrome | 0 | https://github.com/chromium/chromium | 2018-04-07 23:43:03+00:00 | /* Generated by wayland-scanner 1.13.0 */
/*
* Copyright 2016 The Chromium Authors.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <stdint.h>
#include "wayland-util.h"
extern const struct wl_interface wl_keyboard_interface;
extern const struct wl_interface zcr_keyboard_device_configuration_v1_interface;
static const struct wl_interface *types[] = {
NULL,
&zcr_keyboard_device_configuration_v1_interface,
&wl_keyboard_interface,
};
static const struct wl_message zcr_keyboard_configuration_v1_requests[] = {
{ "get_keyboard_device_configuration", "no", types + 1 },
};
WL_EXPORT const struct wl_interface zcr_keyboard_configuration_v1_interface = {
"zcr_keyboard_configuration_v1", 2,
1, zcr_keyboard_configuration_v1_requests,
0, NULL,
};
static const struct wl_message zcr_keyboard_device_configuration_v1_requests[] = {
{ "destroy", "", types + 0 },
};
static const struct wl_message zcr_keyboard_device_configuration_v1_events[] = {
{ "type_change", "u", types + 0 },
};
WL_EXPORT const struct wl_interface zcr_keyboard_device_configuration_v1_interface = {
"zcr_keyboard_device_configuration_v1", 1,
1, zcr_keyboard_device_configuration_v1_requests,
1, zcr_keyboard_device_configuration_v1_events,
};
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