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Partha117

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RealVul

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train_val

e4311ee51d1e2676001b2d8fcefd92bdd79aad85

linux

https://github.com/torvalds/linux

2017-05-12 08:32:58+10:00

#ifndef _ASM_X86_PGTABLE_2LEVEL_H #define _ASM_X86_PGTABLE_2LEVEL_H #define pte_ERROR(e) \ pr_err("%s:%d: bad pte %08lx\n", __FILE__, __LINE__, (e).pte_low) #define pgd_ERROR(e) \ pr_err("%s:%d: bad pgd %08lx\n", __FILE__, __LINE__, pgd_val(e)) /* * Certain architectures need to do special things when PTEs * within a page table are directly modified. Thus, the following * hook is made available. */ static inline void native_set_pte(pte_t *ptep , pte_t pte) { *ptep = pte; } static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd) { *pmdp = pmd; } static inline void native_set_pud(pud_t *pudp, pud_t pud) { } static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte) { native_set_pte(ptep, pte); } static inline void native_pmd_clear(pmd_t *pmdp) { native_set_pmd(pmdp, __pmd(0)); } static inline void native_pud_clear(pud_t *pudp) { } static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *xp) { *xp = native_make_pte(0); } #ifdef CONFIG_SMP static inline pte_t native_ptep_get_and_clear(pte_t *xp) { return __pte(xchg(&xp->pte_low, 0)); } #else #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp) #endif #ifdef CONFIG_SMP static inline pmd_t native_pmdp_get_and_clear(pmd_t *xp) { return __pmd(xchg((pmdval_t *)xp, 0)); } #else #define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp) #endif #ifdef CONFIG_SMP static inline pud_t native_pudp_get_and_clear(pud_t *xp) { return __pud(xchg((pudval_t *)xp, 0)); } #else #define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp) #endif /* Bit manipulation helper on pte/pgoff entry */ static inline unsigned long pte_bitop(unsigned long value, unsigned int rightshift, unsigned long mask, unsigned int leftshift) { return ((value >> rightshift) & mask) << leftshift; } /* Encode and de-code a swap entry */ #define SWP_TYPE_BITS 5 #define SWP_OFFSET_SHIFT (_PAGE_BIT_PROTNONE + 1) #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS) #define __swp_type(x) (((x).val >> (_PAGE_BIT_PRESENT + 1)) \ & ((1U << SWP_TYPE_BITS) - 1)) #define __swp_offset(x) ((x).val >> SWP_OFFSET_SHIFT) #define __swp_entry(type, offset) ((swp_entry_t) { \ ((type) << (_PAGE_BIT_PRESENT + 1)) \ | ((offset) << SWP_OFFSET_SHIFT) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low }) #define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val }) #endif /* _ASM_X86_PGTABLE_2LEVEL_H */

train_val

796a0e014bc3985709c0a35538d606ef1da31e1b

Chrome

https://github.com/chromium/chromium

2018-04-07 23:43:03+00:00

// Copyright (c) 2012 The Chromium Authors. All rights reserved. // Use of this source code is governed by a BSD-style license that can be // found in the LICENSE file. #ifndef UI_VIEWS_DRAG_UTILS_H_ #define UI_VIEWS_DRAG_UTILS_H_ #include "ui/base/dragdrop/drag_drop_types.h" #include "ui/gfx/native_widget_types.h" #include "ui/views/views_export.h" namespace gfx { class Point; } namespace ui { class OSExchangeData; } namespace views { class Widget; // Starts a drag operation. This blocks until the drag operation completes. VIEWS_EXPORT void RunShellDrag(gfx::NativeView view, const ui::OSExchangeData& data, const gfx::Point& location, int operation, ui::DragDropTypes::DragEventSource source); // Returns the device scale for the display associated with this |widget|'s // native view. VIEWS_EXPORT float ScaleFactorForDragFromWidget(const Widget* widget); } // namespace views #endif // UI_VIEWS_DRAG_UTILS_H_

train_val

796a0e014bc3985709c0a35538d606ef1da31e1b

Chrome

https://github.com/chromium/chromium

2018-04-07 23:43:03+00:00

// Copyright 2016 The Chromium Authors. All rights reserved. // Use of this source code is governed by a BSD-style license that can be // found in the LICENSE file. #ifndef MOJO_PUBLIC_CPP_BINDINGS_RAW_PTR_IMPL_REF_TRAITS_H_ #define MOJO_PUBLIC_CPP_BINDINGS_RAW_PTR_IMPL_REF_TRAITS_H_ namespace mojo { // Default traits for a binding's implementation reference type. This // corresponds to a raw pointer. template <typename Interface> struct RawPtrImplRefTraits { using PointerType = Interface*; static bool IsNull(PointerType ptr) { return !ptr; } static Interface* GetRawPointer(PointerType* ptr) { return *ptr; } }; } // namespace mojo #endif // MOJO_PUBLIC_CPP_BINDINGS_LIB_RAW_PTR_IMPL_REF_TRAITS_H_

train_val

e4311ee51d1e2676001b2d8fcefd92bdd79aad85

linux

https://github.com/torvalds/linux

2017-05-12 08:32:58+10:00

/* * IDE Chipset driver for the Compaq TriFlex IDE controller. * * Known to work with the Compaq Workstation 5x00 series. * * Copyright (C) 2002 Hewlett-Packard Development Group, L.P. * Author: Torben Mathiasen <torben.mathiasen@hp.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * * Loosely based on the piix & svwks drivers. * * Documentation: * Not publicly available. */ #include <linux/types.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/pci.h> #include <linux/ide.h> #include <linux/init.h> #define DRV_NAME "triflex" static void triflex_set_mode(ide_hwif_t *hwif, ide_drive_t *drive) { struct pci_dev *dev = to_pci_dev(hwif->dev); u32 triflex_timings = 0; u16 timing = 0; u8 channel_offset = hwif->channel ? 0x74 : 0x70, unit = drive->dn & 1; pci_read_config_dword(dev, channel_offset, &triflex_timings); switch (drive->dma_mode) { case XFER_MW_DMA_2: timing = 0x0103; break; case XFER_MW_DMA_1: timing = 0x0203; break; case XFER_MW_DMA_0: timing = 0x0808; break; case XFER_SW_DMA_2: case XFER_SW_DMA_1: case XFER_SW_DMA_0: timing = 0x0f0f; break; case XFER_PIO_4: timing = 0x0202; break; case XFER_PIO_3: timing = 0x0204; break; case XFER_PIO_2: timing = 0x0404; break; case XFER_PIO_1: timing = 0x0508; break; case XFER_PIO_0: timing = 0x0808; break; } triflex_timings &= ~(0xFFFF << (16 * unit)); triflex_timings |= (timing << (16 * unit)); pci_write_config_dword(dev, channel_offset, triflex_timings); } static void triflex_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { drive->dma_mode = drive->pio_mode; triflex_set_mode(hwif, drive); } static const struct ide_port_ops triflex_port_ops = { .set_pio_mode = triflex_set_pio_mode, .set_dma_mode = triflex_set_mode, }; static const struct ide_port_info triflex_device = { .name = DRV_NAME, .enablebits = {{0x80, 0x01, 0x01}, {0x80, 0x02, 0x02}}, .port_ops = &triflex_port_ops, .pio_mask = ATA_PIO4, .swdma_mask = ATA_SWDMA2, .mwdma_mask = ATA_MWDMA2, }; static int triflex_init_one(struct pci_dev *dev, const struct pci_device_id *id) { return ide_pci_init_one(dev, &triflex_device, NULL); } static const struct pci_device_id triflex_pci_tbl[] = { { PCI_VDEVICE(COMPAQ, PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE), 0 }, { 0, }, }; MODULE_DEVICE_TABLE(pci, triflex_pci_tbl); #ifdef CONFIG_PM static int triflex_ide_pci_suspend(struct pci_dev *dev, pm_message_t state) { /* * We must not disable or powerdown the device. * APM bios refuses to suspend if IDE is not accessible. */ pci_save_state(dev); return 0; } #else #define triflex_ide_pci_suspend NULL #endif static struct pci_driver triflex_pci_driver = { .name = "TRIFLEX_IDE", .id_table = triflex_pci_tbl, .probe = triflex_init_one, .remove = ide_pci_remove, .suspend = triflex_ide_pci_suspend, .resume = ide_pci_resume, }; static int __init triflex_ide_init(void) { return ide_pci_register_driver(&triflex_pci_driver); } static void __exit triflex_ide_exit(void) { pci_unregister_driver(&triflex_pci_driver); } module_init(triflex_ide_init); module_exit(triflex_ide_exit); MODULE_AUTHOR("Torben Mathiasen"); MODULE_DESCRIPTION("PCI driver module for Compaq Triflex IDE"); MODULE_LICENSE("GPL");

train_val

e4311ee51d1e2676001b2d8fcefd92bdd79aad85

linux

https://github.com/torvalds/linux

2017-05-12 08:32:58+10:00

/* * PCI bus driver for Bosch C_CAN/D_CAN controller * * Copyright (C) 2012 Federico Vaga <federico.vaga@gmail.com> * * Borrowed from c_can_platform.c * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/netdevice.h> #include <linux/pci.h> #include <linux/can/dev.h> #include "c_can.h" #define PCI_DEVICE_ID_PCH_CAN 0x8818 #define PCH_PCI_SOFT_RESET 0x01fc enum c_can_pci_reg_align { C_CAN_REG_ALIGN_16, C_CAN_REG_ALIGN_32, C_CAN_REG_32, }; struct c_can_pci_data { /* Specify if is C_CAN or D_CAN */ enum c_can_dev_id type; /* Set the register alignment in the memory */ enum c_can_pci_reg_align reg_align; /* Set the frequency */ unsigned int freq; /* PCI bar number */ int bar; /* Callback for reset */ void (*init)(const struct c_can_priv *priv, bool enable); }; /* * 16-bit c_can registers can be arranged differently in the memory * architecture of different implementations. For example: 16-bit * registers can be aligned to a 16-bit boundary or 32-bit boundary etc. * Handle the same by providing a common read/write interface. */ static u16 c_can_pci_read_reg_aligned_to_16bit(const struct c_can_priv *priv, enum reg index) { return readw(priv->base + priv->regs[index]); } static void c_can_pci_write_reg_aligned_to_16bit(const struct c_can_priv *priv, enum reg index, u16 val) { writew(val, priv->base + priv->regs[index]); } static u16 c_can_pci_read_reg_aligned_to_32bit(const struct c_can_priv *priv, enum reg index) { return readw(priv->base + 2 * priv->regs[index]); } static void c_can_pci_write_reg_aligned_to_32bit(const struct c_can_priv *priv, enum reg index, u16 val) { writew(val, priv->base + 2 * priv->regs[index]); } static u16 c_can_pci_read_reg_32bit(const struct c_can_priv *priv, enum reg index) { return (u16)ioread32(priv->base + 2 * priv->regs[index]); } static void c_can_pci_write_reg_32bit(const struct c_can_priv *priv, enum reg index, u16 val) { iowrite32((u32)val, priv->base + 2 * priv->regs[index]); } static u32 c_can_pci_read_reg32(const struct c_can_priv *priv, enum reg index) { u32 val; val = priv->read_reg(priv, index); val |= ((u32) priv->read_reg(priv, index + 1)) << 16; return val; } static void c_can_pci_write_reg32(const struct c_can_priv *priv, enum reg index, u32 val) { priv->write_reg(priv, index + 1, val >> 16); priv->write_reg(priv, index, val); } static void c_can_pci_reset_pch(const struct c_can_priv *priv, bool enable) { if (enable) { u32 __iomem *addr = priv->base + PCH_PCI_SOFT_RESET; /* write to sw reset register */ iowrite32(1, addr); iowrite32(0, addr); } } static int c_can_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct c_can_pci_data *c_can_pci_data = (void *)ent->driver_data; struct c_can_priv *priv; struct net_device *dev; void __iomem *addr; int ret; ret = pci_enable_device(pdev); if (ret) { dev_err(&pdev->dev, "pci_enable_device FAILED\n"); goto out; } ret = pci_request_regions(pdev, KBUILD_MODNAME); if (ret) { dev_err(&pdev->dev, "pci_request_regions FAILED\n"); goto out_disable_device; } ret = pci_enable_msi(pdev); if (!ret) { dev_info(&pdev->dev, "MSI enabled\n"); pci_set_master(pdev); } addr = pci_iomap(pdev, c_can_pci_data->bar, pci_resource_len(pdev, c_can_pci_data->bar)); if (!addr) { dev_err(&pdev->dev, "device has no PCI memory resources, " "failing adapter\n"); ret = -ENOMEM; goto out_release_regions; } /* allocate the c_can device */ dev = alloc_c_can_dev(); if (!dev) { ret = -ENOMEM; goto out_iounmap; } priv = netdev_priv(dev); pci_set_drvdata(pdev, dev); SET_NETDEV_DEV(dev, &pdev->dev); dev->irq = pdev->irq; priv->base = addr; priv->device = &pdev->dev; if (!c_can_pci_data->freq) { dev_err(&pdev->dev, "no clock frequency defined\n"); ret = -ENODEV; goto out_free_c_can; } else { priv->can.clock.freq = c_can_pci_data->freq; } /* Configure CAN type */ switch (c_can_pci_data->type) { case BOSCH_C_CAN: priv->regs = reg_map_c_can; break; case BOSCH_D_CAN: priv->regs = reg_map_d_can; priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES; break; default: ret = -EINVAL; goto out_free_c_can; } priv->type = c_can_pci_data->type; /* Configure access to registers */ switch (c_can_pci_data->reg_align) { case C_CAN_REG_ALIGN_32: priv->read_reg = c_can_pci_read_reg_aligned_to_32bit; priv->write_reg = c_can_pci_write_reg_aligned_to_32bit; break; case C_CAN_REG_ALIGN_16: priv->read_reg = c_can_pci_read_reg_aligned_to_16bit; priv->write_reg = c_can_pci_write_reg_aligned_to_16bit; break; case C_CAN_REG_32: priv->read_reg = c_can_pci_read_reg_32bit; priv->write_reg = c_can_pci_write_reg_32bit; break; default: ret = -EINVAL; goto out_free_c_can; } priv->read_reg32 = c_can_pci_read_reg32; priv->write_reg32 = c_can_pci_write_reg32; priv->raminit = c_can_pci_data->init; ret = register_c_can_dev(dev); if (ret) { dev_err(&pdev->dev, "registering %s failed (err=%d)\n", KBUILD_MODNAME, ret); goto out_free_c_can; } dev_dbg(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n", KBUILD_MODNAME, priv->regs, dev->irq); return 0; out_free_c_can: free_c_can_dev(dev); out_iounmap: pci_iounmap(pdev, addr); out_release_regions: pci_disable_msi(pdev); pci_clear_master(pdev); pci_release_regions(pdev); out_disable_device: pci_disable_device(pdev); out: return ret; } static void c_can_pci_remove(struct pci_dev *pdev) { struct net_device *dev = pci_get_drvdata(pdev); struct c_can_priv *priv = netdev_priv(dev); unregister_c_can_dev(dev); free_c_can_dev(dev); pci_iounmap(pdev, priv->base); pci_disable_msi(pdev); pci_clear_master(pdev); pci_release_regions(pdev); pci_disable_device(pdev); } static struct c_can_pci_data c_can_sta2x11= { .type = BOSCH_C_CAN, .reg_align = C_CAN_REG_ALIGN_32, .freq = 52000000, /* 52 Mhz */ .bar = 0, }; static struct c_can_pci_data c_can_pch = { .type = BOSCH_C_CAN, .reg_align = C_CAN_REG_32, .freq = 50000000, /* 50 MHz */ .init = c_can_pci_reset_pch, .bar = 1, }; #define C_CAN_ID(_vend, _dev, _driverdata) { \ PCI_DEVICE(_vend, _dev), \ .driver_data = (unsigned long)&_driverdata, \ } static const struct pci_device_id c_can_pci_tbl[] = { C_CAN_ID(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_CAN, c_can_sta2x11), C_CAN_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_CAN, c_can_pch), {}, }; static struct pci_driver c_can_pci_driver = { .name = KBUILD_MODNAME, .id_table = c_can_pci_tbl, .probe = c_can_pci_probe, .remove = c_can_pci_remove, }; module_pci_driver(c_can_pci_driver); MODULE_AUTHOR("Federico Vaga <federico.vaga@gmail.com>"); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("PCI CAN bus driver for Bosch C_CAN/D_CAN controller"); MODULE_DEVICE_TABLE(pci, c_can_pci_tbl);