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	{"text":"\n#include <linux/err.h>\n#include <linux/errno.h>\n#include <linux/delay.h>\n#include <linux/fs.h>\n#include <linux/input.h>\n#include <linux/uaccess.h>\n#include <linux/workqueue.h>\n#include <linux/irq.h>\n#include <linux/gpio.h>\n#include <linux/interrupt.h>\n#include <linux/slab.h>\n#include <linux/module.h>\n\n#include \"ais328dq.h\"\n\n#define SENSITIVITY_2G 1 /** mg/LSB /\n#define SENSITIVITY_4G 2 /* mg/LSB /\n#define SENSITIVITY_8G 4 /* mg/LSB /\n\n#define AXISDATA_REG 0x28\n#define WHOAMI_AIS328DQ_ACC 0x32 / Expctd content for WAI /\n\n/ CONTROL REGISTERS ADDRESSES /\n#define WHO_AM_I 0x0F / WhoAmI register /\n#define CTRL_REG1 0x20 / /\n#define CTRL_REG2 0x21 / /\n#define CTRL_REG3 0x22 / /\n#define CTRL_REG4 0x23 / /\n#define CTRL_REG5 0x24 / /\n\n#define INT_CFG1 0x30 / interrupt 1 config /\n#define INT_SRC1 0x31 / interrupt 1 source /\n#define INT_THS1 0x32 / interrupt 1 threshold /\n#define INT_DUR1 0x33 / interrupt 1 duration /\n\n#define INT_CFG2 0x34 / interrupt 2 config /\n#define INT_SRC2 0x35 / interrupt 2 source /\n#define INT_THS2 0x36 / interrupt 2 threshold /\n#define INT_DUR2 0x37 / interrupt 2 duration /\n/ end CONTROL REGISTRES ADDRESSES /\n\n#define AIS328DQ_ACC_ENABLE_ALL_AXES 0x07\n#define AIS328DQ_SELFTEST_EN 0x02\n#define AIS328DQ_SELFTEST_DIS 0x00\n#define AIS328DQ_SELFTEST_POS 0x00\n#define AIS328DQ_SELFTEST_NEG 0x08\n\n#define AIS328DQ_ACC_BDU_EN 0x80\n\n/ Accelerometer output data rate /\n#define AIS328DQ_ACC_ODRHALF 0x40 / 0.5Hz output data rate /\n#define AIS328DQ_ACC_ODR1 0x60 / 1Hz output data rate /\n#define AIS328DQ_ACC_ODR2 0x80 / 2Hz output data rate /\n#define AIS328DQ_ACC_ODR5 0xA0 / 5Hz output data rate /\n#define AIS328DQ_ACC_ODR10 0xC0 / 10Hz output data rate /\n#define AIS328DQ_ACC_ODR50 0x00 / 50Hz output data rate /\n#define AIS328DQ_ACC_ODR100 0x08 / 100Hz output data rate /\n#define AIS328DQ_ACC_ODR400 0x10 / 400Hz output data rate /\n#define AIS328DQ_ACC_ODR1000 0x18 / 1000Hz output data rate /\n\n/ RESUME STATE INDICES /\n#define RES_CTRL_REG1 0\n#define RES_CTRL_REG2 1\n#define RES_CTRL_REG3 2\n#define RES_CTRL_REG4 3\n#define RES_CTRL_REG5 4\n#define RES_REFERENCE 5\n\n#define RES_INT_CFG1 6\n#define RES_INT_THS1 7\n#define RES_INT_DUR1 8\n#define RES_INT_CFG2 9\n#define RES_INT_THS2 10\n#define RES_INT_DUR2 11\n\n/ end RESUME STATE INDICES /\n\n#define INPUT_EVENT_TYPE EV_MSC\n#define INPUT_EVENT_X MSC_SERIAL\n#define INPUT_EVENT_Y MSC_PULSELED\n#define INPUT_EVENT_Z MSC_GESTURE\n#define INPUT_EVENT_TIME_MSB MSC_SCAN\n#define INPUT_EVENT_TIME_LSB MSC_MAX\n\n#define MS_TO_NS(x) ((x)1000000L)\n\nstatic struct {\nunsigned int cutoff_ms;\nunsigned int mask;\n} ais328dq_acc_odr_table[] = {\n{1, AIS328DQ_ACC_PM_NORMAL \| AIS328DQ_ACC_ODR1000},\n{3, AIS328DQ_ACC_PM_NORMAL \| AIS328DQ_ACC_ODR400},\n{10, AIS328DQ_ACC_PM_NORMAL \| AIS328DQ_ACC_ODR100},\n{20, AIS328DQ_ACC_PM_NORMAL \| AIS328DQ_ACC_ODR50},\n/* low power settings, max low pass filter cut-off freq /\n{100, AIS328DQ_ACC_ODR10 \| AIS328DQ_ACC_ODR1000},\n{200, AIS328DQ_ACC_ODR5 \| AIS328DQ_ACC_ODR1000},\n{5000, AIS328DQ_ACC_ODR2 \| AIS328DQ_ACC_ODR1000 },\n{1000, AIS328DQ_ACC_ODR1 \| AIS328DQ_ACC_ODR1000 },\n{2000, AIS328DQ_ACC_ODRHALF \| AIS328DQ_ACC_ODR1000 },\n};\n\nstatic struct ais328dq_acc_platform_data def_pdata = {\n.poll_interval = 100,\n.min_interval = 1,\n.g_range = 2,\n\n.axis_map_x = 0,\n.axis_map_y = 1,\n.axis_map_z = 2,\n\n.gpio_int1 = -1,\n.gpio_int2 = -1,\n};\n\nstatic inline s64 ais328dq_get_time_ns(void)\n{\nreturn ktime_to_ns(ktime_get_boottime());\n}\n\nstatic int ais328dq_acc_hw_init(struct ais328dq_acc_data acc)\n{\nint err = -1;\nu8 buf[4];\n\nprintk(KERN_INFO \"%s: hw init start\n\", AIS328DQ_ACC_DEV_NAME);\n\nerr = acc->tf->read(acc->dev, WHO_AM_I, 1, buf);\nif (err < 0){\ndev_warn(acc->dev, \"Error reading WHO_AM_I: is device \"\n\"available/working?\n\");\ngoto err_firstread;\n} else\nacc->hw_working = 1;\nif (buf[0] != WHOAMI_AIS328DQ_ACC) {\ndev_err(acc->dev,\n\"device unknown. Expected: 0x%x,\"\n\" Replies: 0x%x\n\", WHOAMI_AIS328DQ_ACC, buf[0]);\nerr = -1; /* choose the right coded error /\ngoto err_unknown_device;\n}\n\nbuf[0] = acc->resume_state[RES_CTRL_REG1];\nerr = acc->tf->write(acc->dev, CTRL_REG1, 1, buf);\nif (err < 0)\ngoto err_resume_state;\n\nbuf[0] = acc->resume_state[RES_INT_THS1];\nbuf[1] = acc->resume_state[RES_INT_DUR1];\nerr = acc->tf->write(acc->dev, INT_THS1, 2, buf);\nif (err < 0)\ngoto err_resume_state;\n\nbuf[0] = acc->resume_state[RES_INT_CFG1];\nerr = acc->tf->write(acc->dev, INT_CFG1, 1, buf);\nif (err < 0)\ngoto err_resume_state;\n\nbuf[0] = acc->resume_state[RES_INT_THS2];\nbuf[1] = acc->resume_state[RES_INT_DUR2];\nerr = acc->tf->write(acc->dev, INT_THS2, 2, buf);\nif (err < 0)\ngoto err_resume_state;\n\nbuf[0] = acc->resume_state[RES_INT_CFG2];\nerr = acc->tf->write(acc->dev, INT_CFG2, 1, buf);\nif (err < 0)\ngoto err_resume_state;\n\nbuf[0] = acc->resume_state[RES_CTRL_REG2];\nbuf[1] = acc->resume_state[RES_CTRL_REG3];\nbuf[2] = acc->resume_state[RES_CTRL_REG4];\nbuf[3] = acc->resume_state[RES_CTRL_REG5];\nerr = acc->tf->write(acc->dev, CTRL_REG2, 4, buf);\nif (err < 0)\ngoto err_resume_state;\n\nacc->hw_initialized = 1;\nprintk(KERN_INFO \"%s: hw init done\n\", AIS328DQ_ACC_DEV_NAME);\nreturn 0;\n\nerr_firstread:\nacc->hw_working = 0;\nerr_unknown_device:\nerr_resume_state:\nacc->hw_initialized = 0;\ndev_err(acc->dev, \"hw init error 0x%x,0x%x: %d\n\", buf[0],\nbuf[1], err);\nreturn err;\n}\n\nstatic void ais328dq_acc_device_power_off(struct ais328dq_acc_data acc)\n{\nint err;\nu8 buf[1] = {AIS328DQ_ACC_PM_OFF};\n\nerr = acc->tf->write(acc->dev, CTRL_REG1, 1, buf);\nif (err < 0)\ndev_err(acc->dev, \"soft power off failed: %d\n\", err);\n\nif (acc->pdata->power_off) {\nif(acc->pdata->gpio_int1 >= 0)\ndisable_irq_nosync(acc->irq1);\nif(acc->pdata->gpio_int2 >= 0)\ndisable_irq_nosync(acc->irq2);\nacc->pdata->power_off();\nacc->hw_initialized = 0;\n}\nif (acc->hw_initialized) {\nif(acc->pdata->gpio_int1 >= 0)\ndisable_irq_nosync(acc->irq1);\nif(acc->pdata->gpio_int2 >= 0)\ndisable_irq_nosync(acc->irq2);\nacc->hw_initialized = 0;\n}\n\n}\n\nstatic int ais328dq_acc_device_power_on(struct ais328dq_acc_data acc)\n{\nint err = -1;\n\nif (acc->pdata->power_on) {\nerr = acc->pdata->power_on();\nif (err < 0) {\ndev_err(acc->dev,\n\"power_on failed: %d\n\", err);\nreturn err;\n}\nif(acc->pdata->gpio_int1 >= 0)\nenable_irq(acc->irq1);\nif(acc->pdata->gpio_int2 >= 0)\nenable_irq(acc->irq2);\n}\n\nif (!acc->hw_initialized) {\nerr = ais328dq_acc_hw_init(acc);\nif (acc->hw_working == 1 && err < 0) {\nais328dq_acc_device_power_off(acc);\nreturn err;\n}\n}\n\nif (acc->hw_initialized) {\nif(acc->pdata->gpio_int1 >= 0)\nenable_irq(acc->irq1);\nif(acc->pdata->gpio_int2 >= 0)\nenable_irq(acc->irq2);\n}\nreturn 0;\n}\n\nstatic irqreturn_t ais328dq_acc_isr1(int irq, void dev)\n{\nstruct ais328dq_acc_data acc = dev;\n\ndisable_irq_nosync(irq);\nqueue_work(acc->irq1_work_queue, &acc->irq1_work);\nprintk(KERN_INFO \"%s: isr1 queued\n\", AIS328DQ_ACC_DEV_NAME);\n\nreturn IRQ_HANDLED;\n}\n\nstatic irqreturn_t ais328dq_acc_isr2(int irq, void dev)\n{\nstruct ais328dq_acc_data acc = dev;\n\ndisable_irq_nosync(irq);\nqueue_work(acc->irq2_work_queue, &acc->irq2_work);\nprintk(KERN_INFO \"%s: isr2 queued\n\", AIS328DQ_ACC_DEV_NAME);\n\nreturn IRQ_HANDLED;\n}\n\nstatic void ais328dq_acc_irq1_work_func(struct work_struct work)\n{\n\nstruct ais328dq_acc_data acc =\ncontainer_of(work, struct ais328dq_acc_data, irq1_work);\n/ TODO add interrupt service procedure.\nie:ais328dq_acc_get_int1_source(acc); /\n;\n/ /\nenable_irq(acc->irq1);\n}\n\nstatic void ais328dq_acc_irq2_work_func(struct work_struct work)\n{\n\nstruct ais328dq_acc_data acc =\ncontainer_of(work, struct ais328dq_acc_data, irq2_work);\n/ TODO add interrupt service procedure.\nie:ais328dq_acc_get_tap_source(acc); /\n;\n/ /\n\nenable_irq(acc->irq2);\n}\n\nint ais328dq_acc_update_g_range(struct ais328dq_acc_data acc, u8 range)\n{\nint err = -1;\n\nu8 sensitivity;\nu8 buf[1];\nu8 updated_val;\nu8 init_val;\nu8 new_val, new_g_range;\nu8 mask = AIS328DQ_ACC_FS_MASK;\n\nswitch (range) {\ncase 2:\nnew_g_range = AIS328DQ_ACC_G_2G;\nsensitivity = SENSITIVITY_2G;\nbreak;\ncase 4:\nnew_g_range = AIS328DQ_ACC_G_4G;\nsensitivity = SENSITIVITY_4G;\nbreak;\ncase 8:\nnew_g_range = AIS328DQ_ACC_G_8G;\nsensitivity = SENSITIVITY_8G;\nbreak;\ndefault:\ndev_err(acc->dev, \"invalid g range requested: %u\n\", range);\nreturn -EINVAL;\n}\n\n/* Set configuration register 4, which contains g range setting\n* NOTE: this is a straight overwrite because this driver does\n* not use any of the other configuration bits in this\n* register. Should this become untrue, we will have to read\n* out the value and only change the relevant bits --XX----\n* (marked by X) /\nerr = acc->tf->read(acc->dev, CTRL_REG4, 1, buf);\nif (err < 0)\ngoto error;\n\ninit_val = buf[0];\nnew_val = new_g_range;\nupdated_val = ((mask & new_val) \| ((~mask) & init_val));\n\nif (atomic_read(&acc->enabled)) {\nbuf[0] = updated_val;\nerr = acc->tf->write(acc->dev, CTRL_REG4, 1, buf);\nif (err < 0)\ngoto error;\n}\n\nacc->resume_state[RES_CTRL_REG4] = updated_val;\nacc->sensitivity = sensitivity;\n\nreturn 0;\n\nerror:\ndev_err(acc->dev, \"update g range failed 0x%x: %d\n\",\nbuf[0], err);\n\nreturn err;\n}\n\nint ais328dq_acc_update_odr(struct ais328dq_acc_data acc,\nint poll_interval_ms)\n{\nint err = -1;\nint i;\nu8 config[1];\n\n/* Following, looks for the longest possible odr interval scrolling the\n* odr_table vector from the end (shortest interval) backward (longest\n* interval), to support the poll_interval requested by the system.\n* It must be the longest interval lower then the poll interval./\nfor (i = ARRAY_SIZE(ais328dq_acc_odr_table) - 1; i >= 0; i--) {\nif (ais328dq_acc_odr_table[i].cutoff_ms <= poll_interval_ms)\nbreak;\n}\n\nconfig[0] = ais328dq_acc_odr_table[i].mask;\nconfig[0] \|= AIS328DQ_ACC_ENABLE_ALL_AXES;\n\n/ If device is currently enabled, we need to write new\n* configuration out to it /\nif (atomic_read(&acc->enabled)) {\nerr = acc->tf->write(acc->dev, CTRL_REG1, 1, config);\nif (err < 0)\ngoto error;\n}\nacc->resume_state[RES_CTRL_REG1] = config[0];\nacc->delta_ts = MS_TO_NS(poll_interval_ms);\n\nreturn err;\n\nerror:\ndev_err(acc->dev, \"update odr failed 0x%x: %d\n\",\nconfig[0], err);\n\nreturn err;\n}\n\nstatic int ais328dq_acc_register_update(struct ais328dq_acc_data acc,\nu8 buf, u8 reg_address, u8 mask, u8 new_bit_values)\n{\nint err = -1;\nu8 init_val;\nu8 updated_val;\nerr = acc->tf->read(acc->dev, reg_address, 1, buf);\nif (!(err < 0)) {\ninit_val = buf[1];\nupdated_val = ((mask & new_bit_values) \| (~mask & init_val));\nerr = acc->tf->write(acc->dev, reg_address, 1, &updated_val);\n}\n\nreturn err;\n}\n\n\n\nstatic int ais328dq_acc_selftest(struct ais328dq_acc_data acc, u8 enable)\n{\nint err = -1;\nu8 buf[2]={0x00,0x00};\nchar reg_address, mask, bit_values;\n\nreg_address = CTRL_REG4;\nmask = 0x0A;\nif (enable > 0)\nbit_values = AIS328DQ_SELFTEST_EN \|\nAIS328DQ_SELFTEST_POS;\nelse\nbit_values = AIS328DQ_SELFTEST_DIS \|\nAIS328DQ_SELFTEST_POS;\nif (atomic_read(&acc->enabled)) {\nmutex_lock(&acc->lock);\nerr = ais328dq_acc_register_update(acc, buf, reg_address,\nmask, bit_values);\nacc->selftest_enabled = enable;\nmutex_unlock(&acc->lock);\nif (err < 0)\nreturn err;\nacc->resume_state[RES_CTRL_REG4] = ((mask & bit_values) \|\n( ~mask & acc->resume_state[RES_CTRL_REG4]));\n}\nreturn err;\n}\n\nstatic int ais328dq_acc_get_acceleration_data(struct ais328dq_acc_data acc,\nint xyz)\n{\nint err = -1;\n/* Data bytes from hardware xL, xH, yL, yH, zL, zH /\nu8 acc_data[6];\n/ x,y,z hardware data /\ns16 hw_d[3] = { 0 };\n\nerr = acc->tf->read(acc->dev, AXISDATA_REG, 6, acc_data);\nif (err < 0)\nreturn err;\n\nhw_d[0] = (((s16) ((acc_data[1] << 8) \| acc_data[0])) >> 4);\nhw_d[1] = (((s16) ((acc_data[3] << 8) \| acc_data[2])) >> 4);\nhw_d[2] = (((s16) ((acc_data[5] << 8) \| acc_data[4])) >> 4);\n\nhw_d[0] = hw_d[0] acc->sensitivity;\nhw_d[1] = hw_d[1] * acc->sensitivity;\nhw_d[2] = hw_d[2] * acc->sensitivity;\n\nxyz[0] = ((acc->pdata->negate_x) ? (-hw_d[acc->pdata->axis_map_x])\n: (hw_d[acc->pdata->axis_map_x]));\nxyz[1] = ((acc->pdata->negate_y) ? (-hw_d[acc->pdata->axis_map_y])\n: (hw_d[acc->pdata->axis_map_y]));\nxyz[2] = ((acc->pdata->negate_z) ? (-hw_d[acc->pdata->axis_map_z])\n: (hw_d[acc->pdata->axis_map_z]));\n\nreturn err;\n}\n\nstatic void ais328dq_acc_report_values(struct ais328dq_acc_data acc,\nint xyz)\n{\ninput_event(acc->input_dev, INPUT_EVENT_TYPE, INPUT_EVENT_X,\nxyz[0]);\ninput_event(acc->input_dev, INPUT_EVENT_TYPE, INPUT_EVENT_Y,\nxyz[1]);\ninput_event(acc->input_dev, INPUT_EVENT_TYPE, INPUT_EVENT_Z,\nxyz[2]);\ninput_event(acc->input_dev, INPUT_EVENT_TYPE, INPUT_EVENT_TIME_MSB,\nacc->timestamp >> 32);\ninput_event(acc->input_dev, INPUT_EVENT_TYPE, INPUT_EVENT_TIME_LSB,\nacc->timestamp & 0xffffffff);\ninput_sync(acc->input_dev);\n}\n\nint ais328dq_acc_enable(struct ais328dq_acc_data acc)\n{\nif (!atomic_cmpxchg(&acc->enabled, 0, 1)) {\nint err;\n\nmutex_lock(&acc->lock);\nerr = ais328dq_acc_device_power_on(acc);\nif (err < 0) {\natomic_set(&acc->enabled, 0);\nmutex_unlock(&acc->lock);\nreturn err;\n}\n\nhrtimer_start(&acc->hr_timer, ktime_set(0, acc->delta_ts),\nHRTIMER_MODE_REL);\n\nmutex_unlock(&acc->lock);\n}\n\nreturn 0;\n}\nEXPORT_SYMBOL(ais328dq_acc_enable);\n\nint ais328dq_acc_disable(struct ais328dq_acc_data acc)\n{\nif (atomic_cmpxchg(&acc->enabled, 1, 0)) {\nmutex_lock(&acc->lock);\nais328dq_acc_device_power_off(acc);\nmutex_unlock(&acc->lock);\n\ncancel_work_sync(&acc->poll_work);\nhrtimer_cancel(&acc->hr_timer);\n}\n\nreturn 0;\n}\nEXPORT_SYMBOL(ais328dq_acc_disable);\n\nstatic ssize_t read_single_reg(struct device dev, char buf, u8 reg)\n{\nu8 data;\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nint rc = 0;\n\nmutex_lock(&acc->lock);\nrc = acc->tf->read(acc->dev, reg, 1, &data);\nmutex_unlock(&acc->lock);\n\n/TODO: error need to be managed /\nreturn sprintf(buf, \"0x%02x\n\", data);\n\n}\n\nstatic int write_reg(struct device dev, const char buf, u8 reg)\n{\nint rc = 0;\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nu8 x[1];\nunsigned long val;\n\nif (kstrtoul(buf, 16, &val))\nreturn -EINVAL;\n\nmutex_lock(&acc->lock);\nx[0] = val;\nrc = acc->tf->write(acc->dev, reg, 1, x);\nmutex_unlock(&acc->lock);\n\n/TODO: error need to be managed /\nreturn rc;\n}\n\nstatic ssize_t attr_get_polling_rate(struct device dev,\nstruct device_attribute attr,\nchar buf)\n{\nint val;\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nmutex_lock(&acc->lock);\nval = acc->pdata->poll_interval;\nmutex_unlock(&acc->lock);\nreturn sprintf(buf, \"%d\n\", val);\n}\n\nstatic ssize_t attr_set_polling_rate(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nunsigned long interval_ms;\n\nif (kstrtoul(buf, 10, &interval_ms))\nreturn -EINVAL;\nif (!interval_ms)\nreturn -EINVAL;\nmutex_lock(&acc->lock);\nacc->pdata->poll_interval = interval_ms;\nais328dq_acc_update_odr(acc, interval_ms);\nmutex_unlock(&acc->lock);\n\nreturn size;\n}\n\nstatic ssize_t attr_get_range(struct device dev,\nstruct device_attribute attr, char buf)\n{\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nchar range = 2;\n\nmutex_lock(&acc->lock);\nrange = acc->pdata->g_range ;\nmutex_unlock(&acc->lock);\n\nreturn sprintf(buf, \"%d\n\", range);\n}\n\nstatic ssize_t attr_set_range(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nint err;\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nunsigned long val;\n\nif (kstrtoul(buf, 10, &val))\nreturn -EINVAL;\n\nmutex_lock(&acc->lock);\nerr = ais328dq_acc_update_g_range(acc, val);\nif (err == 0)\nacc->pdata->g_range = val;\nmutex_unlock(&acc->lock);\n\nreturn !err ? size : err;\n}\n\nstatic ssize_t attr_get_enable(struct device dev,\nstruct device_attribute attr, char buf)\n{\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nint val = atomic_read(&acc->enabled);\nreturn sprintf(buf, \"%d\n\", val);\n}\n\nstatic ssize_t attr_set_enable(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nunsigned long val;\n\nif (kstrtoul(buf, 10, &val))\nreturn -EINVAL;\n\nif (val)\nais328dq_acc_enable(acc);\nelse\nais328dq_acc_disable(acc);\n\nreturn size;\n}\n\nstatic ssize_t attr_get_selftest(struct device dev,\nstruct device_attribute attr, char buf)\n{\nint val;\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nmutex_lock(&acc->lock);\nval = acc->selftest_enabled;\nmutex_unlock(&acc->lock);\nreturn sprintf(buf, \"%d\n\", val);\n}\n\nstatic ssize_t attr_set_selftest(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nunsigned long val;\n\nif (kstrtoul(buf, 10, &val))\nreturn -EINVAL;\n\nais328dq_acc_selftest(acc, val);\n\nreturn size;\n}\n\nstatic ssize_t attr_set_intconfig1(struct device dev,\nstruct device_attribute attr, const char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_CFG1);\n}\n\nstatic ssize_t attr_get_intconfig1(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_CFG1);\n}\n\nstatic ssize_t attr_set_duration1(struct device dev,\nstruct device_attribute attr, const char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_DUR1);\n}\n\nstatic ssize_t attr_get_duration1(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_DUR1);\n}\n\nstatic ssize_t attr_set_thresh1(struct device dev,\nstruct device_attribute attr, const char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_THS1);\n}\n\nstatic ssize_t attr_get_thresh1(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_THS1);\n}\n\nstatic ssize_t attr_get_source1(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_SRC1);\n}\n\nstatic ssize_t attr_set_intconfig2(struct device dev,\nstruct device_attribute attr, const char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_CFG2);\n}\n\nstatic ssize_t attr_get_intconfig2(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_CFG2);\n}\n\nstatic ssize_t attr_set_duration2(struct device dev,\nstruct device_attribute attr, const char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_DUR2);\n}\n\nstatic ssize_t attr_get_duration2(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_DUR2);\n}\n\nstatic ssize_t attr_set_thresh2(struct device dev,\nstruct device_attribute attr, const char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_THS2);\n}\n\nstatic ssize_t attr_get_thresh2(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_THS2);\n}\nstatic ssize_t attr_get_source2(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_SRC2);\n}\n\n\n\n\n#ifdef AIS328DQ_DEBUG\n/* PAY ATTENTION: These AIS328DQ_DEBUG funtions don't manage resume_state /\nstatic ssize_t attr_reg_set(struct device dev, struct device_attribute attr,\nconst char buf, size_t size)\n{\nint rc;\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nu8 x[2];\nunsigned long val;\n\nif (kstrtoul(buf, 16, &val))\nreturn -EINVAL;\nmutex_lock(&acc->lock);\nx[0] = val;\nrc = acc->tf->write(acc->dev, acc->reg_addr, 1, x);\nmutex_unlock(&acc->lock);\n\n/TODO: error need to be managed /\nreturn size;\n}\n\nstatic ssize_t attr_reg_get(struct device dev, struct device_attribute attr,\nchar buf)\n{\nssize_t ret;\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nint rc;\nu8 data;\n\nmutex_lock(&acc->lock);\nerr = acc->tf->read(acc->dev, acc->reg_addr, 1, &data);\nmutex_unlock(&acc->lock);\n\n/TODO: error need to be managed /\nret = sprintf(buf, \"0x%02x\n\", data);\nreturn ret;\n}\n\nstatic ssize_t attr_addr_set(struct device dev, struct device_attribute attr,\nconst char buf, size_t size)\n{\nstruct ais328dq_acc_data acc = dev_get_drvdata(dev);\nunsigned long val;\nif (kstrtoul(buf, 16, &val))\nreturn -EINVAL;\nmutex_lock(&acc->lock);\nacc->reg_addr = val;\nmutex_unlock(&acc->lock);\nreturn size;\n}\n#endif\n\nstatic struct device_attribute attributes[] = {\n\n__ATTR(pollrate_ms, 0664, attr_get_polling_rate, attr_set_polling_rate),\n__ATTR(range, 0664, attr_get_range, attr_set_range),\n__ATTR(enable_device, 0664, attr_get_enable, attr_set_enable),\n__ATTR(enable_selftest, 0664, attr_get_selftest, attr_set_selftest),\n__ATTR(int1_config, 0664, attr_get_intconfig1, attr_set_intconfig1),\n__ATTR(int1_duration, 0664, attr_get_duration1, attr_set_duration1),\n__ATTR(int1_threshold, 0664, attr_get_thresh1, attr_set_thresh1),\n__ATTR(int1_source, 0444, attr_get_source1, NULL),\n__ATTR(int2_config, 0664, attr_get_intconfig2, attr_set_intconfig2),\n__ATTR(int2_duration, 0664, attr_get_duration2, attr_set_duration2),\n__ATTR(int2_threshold, 0664, attr_get_thresh2, attr_set_thresh2),\n__ATTR(int2_source, 0444, attr_get_source2, NULL),\n#ifdef AIS328DQ_DEBUG\n__ATTR(reg_value, 0600, attr_reg_get, attr_reg_set),\n__ATTR(reg_addr, 0200, NULL, attr_addr_set),\n#endif\n};\n\nstatic int create_sysfs_interfaces(struct device dev)\n{\nint i;\nfor (i = 0; i < ARRAY_SIZE(attributes); i++)\nif (device_create_file(dev, attributes + i))\ngoto error;\nreturn 0;\n\nerror:\nfor ( ; i >= 0; i--)\ndevice_remove_file(dev, attributes + i);\ndev_err(dev, \"%s:Unable to create interface\n\", __func__);\nreturn -1;\n}\n\nstatic int remove_sysfs_interfaces(struct device dev)\n{\nint i;\nfor (i = 0; i < ARRAY_SIZE(attributes); i++)\ndevice_remove_file(dev, attributes + i);\nreturn 0;\n}\n\nstatic enum hrtimer_restart ais328dq_timer_poll(struct hrtimer timer)\n{\nstruct ais328dq_acc_data acc;\n\nacc = container_of((struct hrtimer )timer, struct ais328dq_acc_data,\nhr_timer);\n\nacc->timestamp = ais328dq_get_time_ns();\n\nqueue_work(acc->work_queue, &acc->poll_work);\n\nreturn HRTIMER_NORESTART;\n}\n\nstatic void ais328dq_poll_work_func(struct work_struct work)\n{\nstruct ais328dq_acc_data acc;\nint xyz[3] = { 0 };\nint err;\ns64 ts, delta;\n\nacc = container_of((struct work_struct )work,\nstruct ais328dq_acc_data, poll_work);\n\nts = ais328dq_get_time_ns();\ndelta = acc->delta_ts - (ts - acc->timestamp);\nhrtimer_start(&acc->hr_timer, ktime_set(0, delta),\nHRTIMER_MODE_REL);\n\nmutex_lock(&acc->lock);\nerr = ais328dq_acc_get_acceleration_data(acc, xyz);\nif (err < 0)\ndev_err(acc->dev, \"get_acceleration_data failed\n\");\nelse\nais328dq_acc_report_values(acc, xyz);\n\nmutex_unlock(&acc->lock);\n}\n\nstatic int ais328dq_acc_validate_pdata(struct ais328dq_acc_data acc)\n{\nacc->pdata->poll_interval = max(acc->pdata->poll_interval,\nacc->pdata->min_interval);\n\nif (acc->pdata->axis_map_x > 2 \|\|\nacc->pdata->axis_map_y > 2 \|\| acc->pdata->axis_map_z > 2) {\ndev_err(acc->dev,\n\"invalid axis_map value x:%u y:%u z%u\n\",\nacc->pdata->axis_map_x, acc->pdata->axis_map_y,\nacc->pdata->axis_map_z);\nreturn -EINVAL;\n}\n\n/* Only allow 0 and 1 for negation boolean flag /\nif (acc->pdata->negate_x > 1 \|\| acc->pdata->negate_y > 1 \|\|\nacc->pdata->negate_z > 1) {\ndev_err(acc->dev,\n\"invalid negate value x:%u y:%u z:%u\n\",\nacc->pdata->negate_x, acc->pdata->negate_y,\nacc->pdata->negate_z);\nreturn -EINVAL;\n}\n\n/ Enforce minimum polling interval /\nif (acc->pdata->poll_interval < acc->pdata->min_interval) {\ndev_err(acc->dev, \"minimum poll interval violated\n\");\nreturn -EINVAL;\n}\n\nreturn 0;\n}\n\nstatic int ais328dq_acc_input_init(struct ais328dq_acc_data acc)\n{\nint err;\n\nacc->work_queue = create_workqueue(\"ais328dq_wq\");\nif (!acc->work_queue)\nreturn -ENOMEM;\n\nhrtimer_init(&acc->hr_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);\nacc->hr_timer.function = &ais328dq_timer_poll;\n\nINIT_WORK(&acc->poll_work, ais328dq_poll_work_func);\n\nacc->input_dev = input_allocate_device();\nif (!acc->input_dev) {\nerr = -ENOMEM;\ndev_err(acc->dev, \"input device allocation failed\n\");\ngoto err0;\n}\n\nacc->input_dev->name = AIS328DQ_ACC_DEV_NAME;\nacc->input_dev->id.bustype = acc->bus_type;\nacc->input_dev->dev.parent = acc->dev;\n\ninput_set_drvdata(acc->input_dev, acc);\n\nset_bit(INPUT_EVENT_TYPE, acc->input_dev->evbit);\nset_bit(INPUT_EVENT_X, acc->input_dev->mscbit);\nset_bit(INPUT_EVENT_Y, acc->input_dev->mscbit);\nset_bit(INPUT_EVENT_Z, acc->input_dev->mscbit);\nset_bit(INPUT_EVENT_TIME_MSB, acc->input_dev->mscbit);\nset_bit(INPUT_EVENT_TIME_LSB, acc->input_dev->mscbit);\n\n\nerr = input_register_device(acc->input_dev);\nif (err) {\ndev_err(acc->dev,\n\"unable to register input device %s\n\",\nacc->input_dev->name);\ngoto err1;\n}\n\nreturn 0;\n\nerr1:\ninput_free_device(acc->input_dev);\nerr0:\nreturn err;\n}\n\nstatic void ais328dq_acc_input_cleanup(struct ais328dq_acc_data acc)\n{\nif (acc->work_queue) {\nflush_workqueue(acc->work_queue);\ndestroy_workqueue(acc->work_queue);\nacc->work_queue = NULL;\n}\ninput_unregister_device(acc->input_dev);\ninput_free_device(acc->input_dev);\n}\n\nint ais328dq_acc_probe(struct ais328dq_acc_data acc)\n{\nint err = -1;\n\nif (acc->dev->platform_data == NULL) {\ndev_info(acc->dev,\n\"platform data is NULL. using default one.\n\");\nacc->dev->platform_data = &def_pdata;\n}\n\nmutex_init(&acc->lock);\nmutex_lock(&acc->lock);\n\nacc->pdata = kmalloc(sizeof(acc->pdata), GFP_KERNEL);\nif (acc->pdata == NULL) {\nerr = -ENOMEM;\ndev_err(acc->dev,\n\"failed to allocate memory for pdata: %d\n\",\nerr);\ngoto err_mutexunlock;\n}\n\nmemcpy(acc->pdata, acc->dev->platform_data, sizeof(acc->pdata));\n\nerr = ais328dq_acc_validate_pdata(acc);\nif (err < 0) {\ndev_err(acc->dev, \"failed to validate platform data\n\");\ngoto exit_kfree_pdata;\n}\n\nif (acc->pdata->init) {\nerr = acc->pdata->init();\nif (err < 0) {\ndev_err(acc->dev, \"init failed: %d\n\", err);\ngoto err_pdata_init;\n}\n}\n\nif(acc->pdata->gpio_int1 >= 0){\nacc->irq1 = gpio_to_irq(acc->pdata->gpio_int1);\nprintk(KERN_INFO \"%s: %s has set irq1 to irq: %d \"\n\"mapped on gpio:%d\n\",\nAIS328DQ_ACC_DEV_NAME, __func__, acc->irq1,\nacc->pdata->gpio_int1);\n}\n\nif(acc->pdata->gpio_int2 >= 0){\nacc->irq2 = gpio_to_irq(acc->pdata->gpio_int2);\nprintk(KERN_INFO \"%s: %s has set irq2 to irq: %d \"\n\"mapped on gpio:%d\n\",\nAIS328DQ_ACC_DEV_NAME, __func__, acc->irq2,\nacc->pdata->gpio_int2);\n}\n\nmemset(acc->resume_state, 0, ARRAY_SIZE(acc->resume_state));\n\nacc->resume_state[RES_CTRL_REG1] = AIS328DQ_ACC_ENABLE_ALL_AXES;\nacc->resume_state[RES_CTRL_REG4] = AIS328DQ_ACC_BDU_EN;\n\nerr = ais328dq_acc_device_power_on(acc);\nif (err < 0) {\ndev_err(acc->dev, \"power on failed: %d\n\", err);\ngoto err_pdata_init;\n}\n\natomic_set(&acc->enabled, 1);\n\nerr = ais328dq_acc_update_g_range(acc, acc->pdata->g_range);\nif (err < 0) {\ndev_err(acc->dev, \"update_g_range failed\n\");\ngoto err_power_off;\n}\n\nerr = ais328dq_acc_update_odr(acc, acc->pdata->poll_interval);\nif (err < 0) {\ndev_err(acc->dev, \"update_odr failed\n\");\ngoto err_power_off;\n}\n\nerr = ais328dq_acc_input_init(acc);\nif (err < 0) {\ndev_err(acc->dev, \"input init failed\n\");\ngoto err_power_off;\n}\n\n\nerr = create_sysfs_interfaces(acc->dev);\nif (err < 0) {\ndev_err(acc->dev,\n\"device AIS328DQ_ACC_DEV_NAME \"\n\"sysfs register failed\n\");\ngoto err_input_cleanup;\n}\n\nais328dq_acc_device_power_off(acc);\n\n/* As default, do not report information /\natomic_set(&acc->enabled, 0);\n\nif(acc->pdata->gpio_int1 >= 0){\nINIT_WORK(&acc->irq1_work, ais328dq_acc_irq1_work_func);\nacc->irq1_work_queue =\ncreate_singlethread_workqueue(\"ais328dq_acc_wq1\");\nif (!acc->irq1_work_queue) {\nerr = -ENOMEM;\ndev_err(acc->dev,\n\"cannot create work queue1: %d\n\", err);\ngoto err_remove_sysfs_int;\n}\nerr = request_irq(acc->irq1, ais328dq_acc_isr1,\nIRQF_TRIGGER_RISING, \"ais328dq_acc_irq1\", acc);\nif (err < 0) {\ndev_err(acc->dev, \"request irq1 failed: %d\n\", err);\ngoto err_destoyworkqueue1;\n}\ndisable_irq_nosync(acc->irq1);\n}\n\nif(acc->pdata->gpio_int2 >= 0){\nINIT_WORK(&acc->irq2_work, ais328dq_acc_irq2_work_func);\nacc->irq2_work_queue =\ncreate_singlethread_workqueue(\"ais328dq_acc_wq2\");\nif (!acc->irq2_work_queue) {\nerr = -ENOMEM;\ndev_err(acc->dev,\n\"cannot create work queue2: %d\n\", err);\ngoto err_free_irq1;\n}\nerr = request_irq(acc->irq2, ais328dq_acc_isr2,\nIRQF_TRIGGER_RISING, \"ais328dq_acc_irq2\", acc);\nif (err < 0) {\ndev_err(acc->dev, \"request irq2 failed: %d\n\", err);\ngoto err_destoyworkqueue2;\n}\ndisable_irq_nosync(acc->irq2);\n}\n\nmutex_unlock(&acc->lock);\n\nreturn 0;\n\nerr_destoyworkqueue2:\nif(acc->pdata->gpio_int2 >= 0)\ndestroy_workqueue(acc->irq2_work_queue);\nerr_free_irq1:\nfree_irq(acc->irq1, acc);\nerr_destoyworkqueue1:\nif(acc->pdata->gpio_int1 >= 0)\ndestroy_workqueue(acc->irq1_work_queue);\nerr_remove_sysfs_int:\nremove_sysfs_interfaces(acc->dev);\nerr_input_cleanup:\nais328dq_acc_input_cleanup(acc);\nerr_power_off:\nais328dq_acc_device_power_off(acc);\nerr_pdata_init:\nif (acc->pdata->exit)\nacc->pdata->exit();\nexit_kfree_pdata:\nkfree(acc->pdata);\nerr_mutexunlock:\nmutex_unlock(&acc->lock);\n\nreturn err;\n}\nEXPORT_SYMBOL(ais328dq_acc_probe);\n\nint ais328dq_acc_remove(struct ais328dq_acc_data acc)\n{\nif (acc->pdata->gpio_int1 >= 0){\nfree_irq(acc->irq1, acc);\ngpio_free(acc->pdata->gpio_int1);\ndestroy_workqueue(acc->irq1_work_queue);\n}\n\nif (acc->pdata->gpio_int2 >= 0){\nfree_irq(acc->irq2, acc);\ngpio_free(acc->pdata->gpio_int2);\ndestroy_workqueue(acc->irq2_work_queue);\n}\n\nais328dq_acc_input_cleanup(acc);\nais328dq_acc_device_power_off(acc);\nremove_sysfs_interfaces(acc->dev);\n\nif (acc->pdata->exit)\nacc->pdata->exit();\nkfree(acc->pdata);\n\nreturn 0;\n}\nEXPORT_SYMBOL(ais328dq_acc_remove);\n\nMODULE_DESCRIPTION(\"ais328dq accelerometer sysfs driver\");\nMODULE_AUTHOR(\"Matteo Dameno, STMicroelectronics\");\nMODULE_AUTHOR(\"Lorenzo Bianconi, STMicroelectronics\");\nMODULE_LICENSE(\"GPL v2\");"}
	{"text":"#include <linux/module.h>\n#include <linux/err.h>\n#include <linux/errno.h>\n#include <linux/delay.h>\n#include <linux/fs.h>\n#include <linux/i2c.h>\n#include <linux/input.h>\n#include <linux/uaccess.h>\n#include <linux/workqueue.h>\n#include <linux/irq.h>\n#include <linux/gpio.h>\n#include <linux/interrupt.h>\n#include <linux/slab.h>\n#include <linux/version.h>\n#include <linux/hrtimer.h>\n#include <linux/ktime.h>\n\n#ifdef CONFIG_OF\n#include <linux/of.h>\n#include <linux/of_device.h>\n#include <linux/of_gpio.h>\n#endif\n\n#include \"h3lis100dl.h\"\n\n#define MS_TO_NS(msec) ((msec) * 1000 * 1000)\n\n//#define DEBUG 1\n\n#define SENSITIVITY_100G 780 /** mg/LSB /\n\n#define AXISDATA_REG 0x28\n#define WHOAMI_H3LIS100DL 0x32 / Expctd content for WAI /\n\n/ CONTROL REGISTERS /\n#define WHO_AM_I 0x0F / WhoAmI register /\n#define CTRL_REG1 0x20 / /\n#define CTRL_REG2 0x21 / /\n#define CTRL_REG3 0x22 / /\n#define CTRL_REG4 0x23 / /\n#define CTRL_REG5 0x24 / /\n\n#define INT_CFG1 0x30 / interrupt 1 config /\n#define INT_SRC1 0x31 / interrupt 1 source /\n#define INT_THS1 0x32 / interrupt 1 threshold /\n#define INT_DUR1 0x33 / interrupt 1 duration /\n\n#define INT_CFG2 0x34 / interrupt 2 config /\n#define INT_SRC2 0x35 / interrupt 2 source /\n#define INT_THS2 0x36 / interrupt 2 threshold /\n#define INT_DUR2 0x37 / interrupt 2 duration /\n/ end CONTROL REGISTRES /\n\n#define H3LIS100DL_ENABLE_ALL_AXES 0x07\n#define H3LIS100DL_SELFTEST_EN 0x02\n#define H3LIS100DL_SELFTEST_DIS 0x00\n#define H3LIS100DL_SELFTEST_POS 0x00\n#define H3LIS100DL_SELFTEST_NEG 0x08\n\n/ Accelerometer output data rate /\n#define H3LIS100DL_ODRHALF 0x40 / 0.5Hz output data rate /\n#define H3LIS100DL_ODR1 0x60 / 1Hz output data rate /\n#define H3LIS100DL_ODR2 0x80 / 2Hz output data rate /\n#define H3LIS100DL_ODR5 0xA0 / 5Hz output data rate /\n#define H3LIS100DL_ODR10 0xC0 / 10Hz output data rate /\n#define H3LIS100DL_ODR50 0x00 / 50Hz output data rate /\n#define H3LIS100DL_ODR100 0x08 / 100Hz output data rate /\n#define H3LIS100DL_ODR400 0x10 / 400Hz output data rate /\n#define H3LIS100DL_ODR1000 0x18 / 1000Hz output data rate /\n\n/ RESUME STATE INDICES /\n#define RES_CTRL_REG1 0\n#define RES_CTRL_REG2 1\n#define RES_CTRL_REG3 2\n#define RES_CTRL_REG4 3\n#define RES_CTRL_REG5 4\n#define RES_REFERENCE 5\n\n#define RES_INT_CFG1 6\n#define RES_INT_THS1 7\n#define RES_INT_DUR1 8\n#define RES_INT_CFG2 9\n#define RES_INT_THS2 10\n#define RES_INT_DUR2 11\n\n/ end RESUME STATE INDICES /\n\nstatic struct {\nunsigned int cutoff_ms;\nunsigned int mask;\n} h3lis100dl_odr_table[] = {\n{1, H3LIS100DL_PM_NORMAL \| H3LIS100DL_ODR1000},\n{3, H3LIS100DL_PM_NORMAL \| H3LIS100DL_ODR400},\n{10, H3LIS100DL_PM_NORMAL \| H3LIS100DL_ODR100},\n{20, H3LIS100DL_PM_NORMAL \| H3LIS100DL_ODR50},\n/ low power settings, max low pass filter cut-off freq /\n{100, H3LIS100DL_ODR10 \| H3LIS100DL_ODR1000},\n{200, H3LIS100DL_ODR5 \| H3LIS100DL_ODR1000},\n{5000, H3LIS100DL_ODR2 \| H3LIS100DL_ODR1000 },\n{1000, H3LIS100DL_ODR1 \| H3LIS100DL_ODR1000 },\n{2000, H3LIS100DL_ODRHALF \| H3LIS100DL_ODR1000 },\n};\n\nstatic inline int64_t h3lis100dl_get_time_ns(void)\n{\nreturn ktime_to_ns(ktime_get_boottime());\n}\n\nstatic struct workqueue_struct h3lis100dl_workqueue;\n\nstatic int h3lis100dl_hw_init(struct h3lis100dl_data acc)\n{\nint err = -1;\nu8 buf[6];\n\n#ifdef DEBUG\nprintk(KERN_INFO \"%s: hw init start\n\", H3LIS100DL_DEV_NAME);\n#endif\n\nerr = acc->tf->read(acc, WHO_AM_I, 1, buf);\nif (err < 0){\ndev_warn(acc->dev, \"Error reading WHO_AM_I: is device \"\n\"available/working?\n\");\ngoto err_firstread;\n} else {\nacc->hw_working = 1;\n}\nif (buf[0] != WHOAMI_H3LIS100DL) {\ndev_err(acc->dev,\n\"device unknown. Expected: 0x%x,\"\n\" Replies: 0x%x\n\", WHOAMI_H3LIS100DL, buf[0]);\nerr = -1; / choose the right coded error /\ngoto err_unknown_device;\n}\n\nbuf[0] = acc->resume_state[RES_CTRL_REG1];\nerr = acc->tf->write(acc, CTRL_REG1, 1, buf);\nif (err < 0)\ngoto err_resume_state;\n\nbuf[0] = acc->resume_state[RES_INT_THS1];\nbuf[1] = acc->resume_state[RES_INT_DUR1];\nerr = acc->tf->write(acc, (AUTO_INCREMENT \| INT_THS1), 2, buf);\nif (err < 0)\ngoto err_resume_state;\n\nbuf[0] = acc->resume_state[RES_INT_CFG1];\nerr = acc->tf->write(acc, INT_CFG1, 1, buf);\nif (err < 0)\ngoto err_resume_state;\n\nbuf[0] = acc->resume_state[RES_INT_THS2];\nbuf[1] = acc->resume_state[RES_INT_DUR2];\nerr = acc->tf->write(acc, (AUTO_INCREMENT \| INT_THS2), 2, buf);\nif (err < 0)\ngoto err_resume_state;\n\nbuf[0] = acc->resume_state[RES_INT_CFG2];\nerr = acc->tf->write(acc, INT_CFG2, 1, buf);\nif (err < 0)\ngoto err_resume_state;\n\nbuf[0] = acc->resume_state[RES_CTRL_REG2];\nbuf[1] = acc->resume_state[RES_CTRL_REG3];\nbuf[2] = acc->resume_state[RES_CTRL_REG4];\nbuf[3] = acc->resume_state[RES_CTRL_REG5];\nerr = acc->tf->write(acc, (AUTO_INCREMENT \| CTRL_REG2), 4, buf);\nif (err < 0)\ngoto err_resume_state;\n\nacc->hw_initialized = 1;\n\n#ifdef DEBUG\nprintk(KERN_INFO \"%s: hw init done\n\", H3LIS100DL_DEV_NAME);\n#endif\nreturn 0;\n\nerr_firstread:\nacc->hw_working = 0;\nerr_unknown_device:\nerr_resume_state:\nacc->hw_initialized = 0;\ndev_err(acc->dev, \"hw init error 0x%x,0x%x: %d\n\", buf[0],\nbuf[1], err);\nreturn err;\n}\n\nstatic void h3lis100dl_device_power_off(struct h3lis100dl_data acc)\n{\nint err;\nu8 buf = H3LIS100DL_PM_OFF;\n\nerr = acc->tf->write(acc, CTRL_REG1, 1, &buf);\nif (err < 0)\ndev_err(acc->dev, \"soft power off failed: %d\n\", err);\n\nif (acc->pdata->power_off) {\nacc->pdata->power_off();\nacc->hw_initialized = 0;\n}\nif (acc->hw_initialized)\nacc->hw_initialized = 0;\n}\n\nstatic int h3lis100dl_device_power_on(struct h3lis100dl_data acc)\n{\nint err = -1;\n\nif (acc->pdata->power_on) {\nerr = acc->pdata->power_on();\nif (err < 0) {\ndev_err(acc->dev, \"power_on failed: %d\n\", err);\nreturn err;\n}\n}\n\nif (!acc->hw_initialized) {\nerr = h3lis100dl_hw_init(acc);\nif (acc->hw_working == 1 && err < 0) {\nh3lis100dl_device_power_off(acc);\nreturn err;\n}\n}\n\nreturn 0;\n}\n\n/\n* hrtimer callback - it is called every polling_rate msec.\n/\nenum hrtimer_restart h3lis100dl_timer_func_queue_work(struct hrtimer timer)\n{\nstruct h3lis100dl_data acc;\n\n\nacc = container_of((struct hrtimer )timer,\nstruct h3lis100dl_data, hr_timer);\n\nacc->timestamp = h3lis100dl_get_time_ns();\nqueue_work(h3lis100dl_workqueue, &acc->input_work);\n\nreturn HRTIMER_NORESTART;\n}\n\nint h3lis100dl_update_g_range(struct h3lis100dl_data acc, u8 new_g_range)\n{\nint err = -1;\n\nu16 sensitivity;\nu8 buf;\nu8 updated_val;\nu8 init_val;\nu8 new_val;\nu8 mask = H3LIS100DL_FS_MASK;\n\nsensitivity = SENSITIVITY_100G;\n\nif (atomic_read(&acc->enabled)) {\n/ Set configuration register 4, which contains g range setting\n* NOTE: this is a straight overwrite because this driver does\n* not use any of the other configuration bits in this\n* register. Should this become untrue, we will have to read\n* out the value and only change the relevant bits --XX----\n* (marked by X) /\nerr = acc->tf->read(acc, CTRL_REG4, 1, &buf);\nif (err < 0)\ngoto error;\n\ninit_val = buf;\nacc->resume_state[RES_CTRL_REG4] = init_val;\nnew_val = new_g_range;\nupdated_val = ((mask & new_val) \| ((~mask) & init_val));\nbuf = updated_val;\nerr = acc->tf->write(acc, CTRL_REG4, 1, &buf);\nif (err < 0)\ngoto error;\nacc->resume_state[RES_CTRL_REG4] = updated_val;\nacc->sensitivity = sensitivity;\n}\n\nreturn err;\nerror:\ndev_err(acc->dev, \"update g range failed 0x%x,0x%x: %d\n\",\nCTRL_REG4, buf, err);\n\nreturn err;\n}\n\nint h3lis100dl_update_odr(struct h3lis100dl_data acc,\nint poll_interval_ms)\n{\nint err = -1;\nint i;\nu8 config;\n\n/* Following, looks for the longest possible odr interval scrolling the\n* odr_table vector from the end (shortest interval) backward (longest\n* interval), to support the poll_interval requested by the system.\n* It must be the longest interval lower then the poll interval./\nfor (i = ARRAY_SIZE(h3lis100dl_odr_table) - 1; i >= 0; i--) {\nif (h3lis100dl_odr_table[i].cutoff_ms <= poll_interval_ms)\nbreak;\n}\nconfig = h3lis100dl_odr_table[i].mask;\n\nconfig \|= H3LIS100DL_ENABLE_ALL_AXES;\n\n/ If device is currently enabled, we need to write new\n* configuration out to it /\nif (atomic_read(&acc->enabled)) {\nflush_workqueue(h3lis100dl_workqueue);\n\nerr = acc->tf->write(acc, CTRL_REG1, 1, &config);\nif (err < 0)\ngoto error;\n}\nacc->resume_state[RES_CTRL_REG1] = config;\nacc->ktime = ktime_set(0, MS_TO_NS(poll_interval_ms));\n\nreturn err;\n\nerror:\ndev_err(acc->dev, \"update odr failed 0x%x,0x%x: %d\n\",\nCTRL_REG1, config, err);\n\nreturn err;\n}\n\nstatic int h3lis100dl_register_write(struct h3lis100dl_data acc, u8 buf,\nu8 reg_address, u8 new_value)\n{\nint err = -1;\n\n/ Sets configuration register at reg_address\n* NOTE: this is a straight overwrite /\nbuf[0] = new_value;\nerr = acc->tf->write(acc, reg_address, 1, buf);\nif (err < 0)\nreturn err;\n\nreturn err;\n}\n\nstatic int h3lis100dl_register_read(struct h3lis100dl_data acc, u8 buf,\nu8 reg_address)\n{\n\nint err = -1;\n\nerr = acc->tf->read(acc, reg_address, 1, buf);\n\nreturn err;\n}\n\nstatic int h3lis100dl_register_update(struct h3lis100dl_data acc,\nu8 buf, u8 reg_address, u8 mask, u8 new_bit_values)\n{\nint err = -1;\nu8 init_val;\nu8 updated_val;\nerr = h3lis100dl_register_read(acc, buf, reg_address);\nif (!(err < 0)) {\ninit_val = buf[1];\nupdated_val = ((mask & new_bit_values) \| ((~mask) & init_val));\nerr = h3lis100dl_register_write(acc, buf, reg_address,\nupdated_val);\n}\nreturn err;\n}\n\nstatic int h3lis100dl_selftest(struct h3lis100dl_data acc, u8 enable)\n{\nint err = -1;\nu8 buf[2] = { 0x00, 0x00 };\nchar reg_address, mask, bit_values;\n\nreg_address = CTRL_REG4;\nmask = 0x0A;\nif (enable > 0)\nbit_values = H3LIS100DL_SELFTEST_EN \|\nH3LIS100DL_SELFTEST_POS;\nelse\nbit_values = H3LIS100DL_SELFTEST_DIS \|\nH3LIS100DL_SELFTEST_POS;\nif (atomic_read(&acc->enabled)) {\nmutex_lock(&acc->lock);\nerr = h3lis100dl_register_update(acc, buf, reg_address,\nmask, bit_values);\nacc->selftest_enabled = enable;\nmutex_unlock(&acc->lock);\nif (err < 0)\nreturn err;\nacc->resume_state[RES_CTRL_REG4] = ((mask & bit_values) \|\n(~mask & acc->resume_state[RES_CTRL_REG4]));\n}\nreturn err;\n}\n\nstatic int h3lis100dl_get_acceleration_data(struct h3lis100dl_data acc,\nint xyz)\n{\nint err = -1;\n/* Data bytes from hardware xL, xH, yL, yH, zL, zH /\nu8 acc_data[6];\n/ x,y,z hardware data /\ns16 hw_d[3] = { 0 };\n\nerr = acc->tf->read(acc, (AUTO_INCREMENT \| AXISDATA_REG), 6, acc_data);\nif (err < 0)\nreturn err;\n\nhw_d[0] = (s8)acc_data[1];\nhw_d[1] = (s8)acc_data[3];\nhw_d[2] = (s8)acc_data[5];\n\nxyz[0] = hw_d[0] acc->sensitivity;\nxyz[1] = hw_d[1] * acc->sensitivity;\nxyz[2] = hw_d[2] * acc->sensitivity;\n\n#ifdef DEBUG\nprintk(KERN_INFO \"%s read x=%d, y=%d, z=%d\n\",\nH3LIS100DL_DEV_NAME, xyz[0], xyz[1], xyz[2]);\n#endif\nreturn err;\n}\n\nstatic void h3lis100dl_report_values(struct h3lis100dl_data acc,\nint xyz)\n{\nstruct input_dev input = acc->input_dev;\n\ninput_event(input, INPUT_EVENT_TYPE, INPUT_EVENT_X, xyz[0]);\ninput_event(input, INPUT_EVENT_TYPE, INPUT_EVENT_Y, xyz[1]);\ninput_event(input, INPUT_EVENT_TYPE, INPUT_EVENT_Z, xyz[2]);\ninput_event(input, INPUT_EVENT_TYPE, INPUT_EVENT_TIME_MSB,\nacc->timestamp >> 32);\ninput_event(input, INPUT_EVENT_TYPE, INPUT_EVENT_TIME_LSB,\nacc->timestamp & 0xffffffff);\ninput_sync(input);\n}\n\nstatic int h3lis100dl_enable(struct h3lis100dl_data acc)\n{\nint err;\n\nif (!atomic_cmpxchg(&acc->enabled, 0, 1)) {\nerr = h3lis100dl_device_power_on(acc);\nif (err < 0) {\natomic_set(&acc->enabled, 0);\nreturn err;\n}\n\nhrtimer_start(&acc->hr_timer, acc->ktime, HRTIMER_MODE_REL);\n}\n\nreturn 0;\n}\n\nstatic int h3lis100dl_disable(struct h3lis100dl_data acc)\n{\nif (atomic_cmpxchg(&acc->enabled, 1, 0)) {\ncancel_work_sync(&acc->input_work);\nhrtimer_cancel(&acc->hr_timer);\nh3lis100dl_device_power_off(acc);\n}\n\nreturn 0;\n}\n\nstatic ssize_t read_single_reg(struct device dev, char buf, u8 reg)\n{\nssize_t ret;\nstruct h3lis100dl_data acc = dev_get_drvdata(dev);\nint rc = 0;\nu8 data;\n\nrc = acc->tf->read(acc, reg, 1, &data);\n/TODO: error need to be managed /\nret = sprintf(buf, \"0x%02x\n\", data);\n\nreturn ret;\n}\n\nstatic int write_reg(struct device dev, const char buf, u8 reg)\n{\nint rc = 0;\nstruct h3lis100dl_data acc = dev_get_drvdata(dev);\nunsigned long val;\nu8 x[2];\n\nif (kstrtoul(buf, 16, &val))\nreturn -EINVAL;\n\nx[0] = val;\nrc = acc->tf->write(acc, reg, 1, x);\n/TODO: error need to be managed /\nreturn rc;\n}\n\nstatic ssize_t attr_get_polling_rate(struct device dev,\nstruct device_attribute attr,\nchar buf)\n{\nint val;\nstruct h3lis100dl_data acc = dev_get_drvdata(dev);\n\nmutex_lock(&acc->lock);\nval = acc->pdata->poll_interval;\nmutex_unlock(&acc->lock);\nreturn sprintf(buf, \"%d\n\", val);\n}\n\nstatic ssize_t attr_set_polling_rate(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nstruct h3lis100dl_data acc = dev_get_drvdata(dev);\nunsigned long interval_ms;\n\nif (kstrtoul(buf, 10, &interval_ms))\nreturn -EINVAL;\nif (!interval_ms)\nreturn -EINVAL;\nmutex_lock(&acc->lock);\nacc->pdata->poll_interval = interval_ms;\nh3lis100dl_update_odr(acc, interval_ms);\nmutex_unlock(&acc->lock);\nreturn size;\n}\n\nstatic ssize_t attr_get_enable(struct device dev,\nstruct device_attribute attr, char buf)\n{\nstruct h3lis100dl_data acc = dev_get_drvdata(dev);\nint val = atomic_read(&acc->enabled);\nreturn sprintf(buf, \"%d\n\", val);\n}\n\nstatic ssize_t attr_set_enable(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nstruct h3lis100dl_data acc = dev_get_drvdata(dev);\nunsigned long val;\n\nif (kstrtoul(buf, 10, &val))\nreturn -EINVAL;\n\nif (val)\nh3lis100dl_enable(acc);\nelse\nh3lis100dl_disable(acc);\n\nreturn size;\n}\n\nstatic ssize_t attr_get_selftest(struct device dev,\nstruct device_attribute attr, char buf)\n{\nint val;\nstruct h3lis100dl_data acc = dev_get_drvdata(dev);\n\nmutex_lock(&acc->lock);\nval = acc->selftest_enabled;\nmutex_unlock(&acc->lock);\nreturn sprintf(buf, \"%d\n\", val);\n}\n\nstatic ssize_t attr_set_selftest(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nstruct h3lis100dl_data acc = dev_get_drvdata(dev);\nunsigned long val;\n\nif (kstrtoul(buf, 10, &val))\nreturn -EINVAL;\n\nh3lis100dl_selftest(acc, val);\n\nreturn size;\n}\n\nstatic ssize_t attr_set_intconfig1(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_CFG1);\n}\n\nstatic ssize_t attr_get_intconfig1(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_CFG1);\n}\n\nstatic ssize_t attr_set_duration1(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_DUR1);\n}\n\nstatic ssize_t attr_get_duration1(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_DUR1);\n}\n\nstatic ssize_t attr_set_thresh1(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_THS1);\n}\n\nstatic ssize_t attr_get_thresh1(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_THS1);\n}\n\nstatic ssize_t attr_get_source1(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_SRC1);\n}\n\nstatic ssize_t attr_set_intconfig2(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_CFG2);\n}\n\nstatic ssize_t attr_get_intconfig2(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_CFG2);\n}\n\nstatic ssize_t attr_set_duration2(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_DUR2);\n}\n\nstatic ssize_t attr_get_duration2(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_DUR2);\n}\n\nstatic ssize_t attr_set_thresh2(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nreturn write_reg(dev, buf, INT_THS2);\n}\n\nstatic ssize_t attr_get_thresh2(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_THS2);\n}\nstatic ssize_t attr_get_source2(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn read_single_reg(dev, buf, INT_SRC2);\n}\n\n#ifdef DEBUG\n/ PAY ATTENTION: These DEBUG funtions don't manage resume_state /\nstatic ssize_t attr_reg_set(struct device dev, struct device_attribute attr,\nconst char buf, size_t size)\n{\nint rc;\nstruct h3lis100dl_data acc = dev_get_drvdata(dev);\nu8 reg;\nunsigned long val;\n\nif (kstrtoul(buf, 16, &val))\nreturn -EINVAL;\n\nmutex_lock(&acc->lock);\nreg = acc->reg_addr;\nmutex_unlock(&acc->lock);\n\nrc = acc->tf->write(acc, reg, 1, &val);\n/TODO: error need to be managed /\nreturn size;\n}\n\nstatic ssize_t attr_reg_get(struct device dev, struct device_attribute attr,\nchar buf)\n{\nssize_t ret;\nstruct h3lis100dl_data acc = dev_get_drvdata(dev);\nint rc;\nu8 reg, val;\n\nmutex_lock(&acc->lock);\nreg = acc->reg_addr;\nmutex_unlock(&acc->lock);\nrc = acc->tf->read(acc, reg, 1, val);\n/TODO: error need to be managed /\nret = sprintf(buf, \"0x%02x\n\", val);\n\nreturn ret;\n}\n\nstatic ssize_t attr_addr_set(struct device dev, struct device_attribute attr,\nconst char buf, size_t size)\n{\nstruct h3lis100dl_data acc = dev_get_drvdata(dev);\nunsigned long val;\n\nif (kstrtoul(buf, 16, &val))\nreturn -EINVAL;\n\nmutex_lock(&acc->lock);\nacc->reg_addr = val;\nmutex_unlock(&acc->lock);\nreturn size;\n}\n#endif\n\nstatic struct device_attribute attributes[] = {\n__ATTR(pollrate_ms, 0664, attr_get_polling_rate, attr_set_polling_rate),\n__ATTR(enable_device, 0664, attr_get_enable, attr_set_enable),\n__ATTR(enable_selftest, 0664, attr_get_selftest, attr_set_selftest),\n__ATTR(int1_config, 0664, attr_get_intconfig1, attr_set_intconfig1),\n__ATTR(int1_duration, 0664, attr_get_duration1, attr_set_duration1),\n__ATTR(int1_threshold, 0664, attr_get_thresh1, attr_set_thresh1),\n__ATTR(int1_source, 0444, attr_get_source1, NULL),\n__ATTR(int2_config, 0664, attr_get_intconfig2, attr_set_intconfig2),\n__ATTR(int2_duration, 0664, attr_get_duration2, attr_set_duration2),\n__ATTR(int2_threshold, 0664, attr_get_thresh2, attr_set_thresh2),\n__ATTR(int2_source, 0444, attr_get_source2, NULL),\n#ifdef DEBUG\n__ATTR(reg_value, 0600, attr_reg_get, attr_reg_set),\n__ATTR(reg_addr, 0200, NULL, attr_addr_set),\n#endif\n};\n\nstatic int create_sysfs_interfaces(struct device dev)\n{\nint i;\nfor (i = 0; i < ARRAY_SIZE(attributes); i++)\nif (device_create_file(dev, attributes + i))\ngoto error;\nreturn 0;\n\nerror:\nfor ( ; i >= 0; i--)\ndevice_remove_file(dev, attributes + i);\ndev_err(dev, \"%s:Unable to create interface\n\", __func__);\nreturn -1;\n}\n\nstatic int remove_sysfs_interfaces(struct device dev)\n{\nint i;\nfor (i = 0; i < ARRAY_SIZE(attributes); i++)\ndevice_remove_file(dev, attributes + i);\nreturn 0;\n}\n\n/\n* Workqueue callback - it is called as soon as a job in the queue\n* is scheduled.\n/\nstatic void h3lis100dl_input_work_func(struct work_struct work)\n{\nstruct h3lis100dl_data acc;\nint xyz[3] = { 0 };\nint err;\n\nacc = container_of((struct work_struct )work,\nstruct h3lis100dl_data, input_work);\n\nhrtimer_start(&acc->hr_timer, acc->ktime, HRTIMER_MODE_REL);\n\nerr = h3lis100dl_get_acceleration_data(acc, xyz);\nif (err < 0)\ndev_err(acc->dev, \"get_acceleration_data failed\n\");\nelse\nh3lis100dl_report_values(acc, xyz);\n}\n\nstatic int h3lis100dl_validate_pdata(struct h3lis100dl_data acc)\n{\nacc->pdata->poll_interval = max(acc->pdata->poll_interval,\nacc->pdata->min_interval);\n\n/ Enforce minimum polling interval /\nif (acc->pdata->poll_interval < acc->pdata->min_interval) {\ndev_err(acc->dev, \"minimum poll interval violated\n\");\nreturn -EINVAL;\n}\n\nreturn 0;\n}\n\nstatic int h3lis100dl_input_init(struct h3lis100dl_data acc)\n{\nint err;\n\nif (!h3lis100dl_workqueue)\nh3lis100dl_workqueue = create_workqueue(acc->name);\n\nif (!h3lis100dl_workqueue)\nreturn -EINVAL;\n\nINIT_WORK(&acc->input_work, h3lis100dl_input_work_func);\nacc->input_dev = input_allocate_device();\nif (!acc->input_dev) {\nerr = -ENOMEM;\ndev_err(acc->dev, \"input device allocation failed\n\");\ngoto err0;\n}\n\nacc->input_dev->name = H3LIS100DL_DEV_NAME;\nacc->input_dev->id.bustype = acc->bustype;\nacc->input_dev->dev.parent = acc->dev;\n\ninput_set_drvdata(acc->input_dev, acc);\n\nset_bit(INPUT_EVENT_TYPE, acc->input_dev->evbit);\n__set_bit(INPUT_EVENT_X, acc->input_dev->mscbit);\n__set_bit(INPUT_EVENT_Y, acc->input_dev->mscbit);\n__set_bit(INPUT_EVENT_Z, acc->input_dev->mscbit);\n__set_bit(INPUT_EVENT_TIME_MSB, acc->input_dev->mscbit);\n__set_bit(INPUT_EVENT_TIME_LSB, acc->input_dev->mscbit);\n\nerr = input_register_device(acc->input_dev);\nif (err) {\ndev_err(acc->dev,\n\"unable to register input device %s\n\",\nacc->input_dev->name);\ngoto err1;\n}\n\nreturn 0;\n\nerr1:\ninput_free_device(acc->input_dev);\nerr0:\nreturn err;\n}\n\nstatic void h3lis100dl_input_cleanup(struct h3lis100dl_data acc)\n{\ninput_unregister_device(acc->input_dev);\ninput_free_device(acc->input_dev);\n}\n\n#ifdef CONFIG_OF\nstatic u32 h3lis100dl_parse_dt(struct h3lis100dl_data cdata, struct device* dev)\n{\nu32 val;\nstruct device_node np;\n\nnp = dev->of_node;\nif (!np)\nreturn -EINVAL;\n\nif (!of_property_read_u32(np, \"poll-interval\", &val))\ncdata->pdata->poll_interval = val;\nelse\ncdata->pdata->poll_interval = 10;\n\ncdata->pdata->init = NULL;\ncdata->pdata->exit = NULL;\ncdata->pdata->power_on = NULL;\ncdata->pdata->power_off = NULL;\n\nreturn 0;\n}\n#endif\n\nint h3lis100dl_common_probe(struct h3lis100dl_data acc)\n{\nint err = -1;\n\npr_info(\"%s: probe start.\n\", H3LIS100DL_DEV_NAME);\n\n#ifndef CONFIG_OF\nif (acc->dev->platform_data == NULL) {\ndev_err(acc->dev, \"platform data is NULL. exiting.\n\");\nerr = -ENODEV;\ngoto exit_check_functionality_failed;\n\n}\n#else\nacc->dev->platform_data = NULL;\n#endif\n\nmutex_init(&acc->lock);\nmutex_init(&acc->tb.buf_lock);\nmutex_lock(&acc->lock);\n\nacc->pdata = kzalloc(sizeof(struct h3lis100dl_platform_data), GFP_KERNEL);\nif (acc->pdata == NULL) {\nerr = -ENOMEM;\ndev_err(acc->dev,\n\"failed to allocate memory for pdata: %d\n\", err);\ngoto err_mutexunlock;\n}\n\n#ifdef CONFIG_OF\nh3lis100dl_parse_dt(acc, acc->dev);\n#else\nmemcpy(acc->pdata, acc->dev->platform_data, sizeof(acc->pdata));\n#endif\n\nerr = h3lis100dl_validate_pdata(acc);\nif (err < 0) {\ndev_err(acc->dev, \"failed to validate platform data\n\");\ngoto exit_kfree_pdata;\n}\n\nacc->pdata->g_range = H3LIS100DL_G_100G;\n\nif (acc->pdata->init) {\nerr = acc->pdata->init();\nif (err < 0) {\ndev_err(acc->dev, \"init failed: %d\n\", err);\ngoto err_pdata_init;\n}\n}\n\nmemset(acc->resume_state, 0, ARRAY_SIZE(acc->resume_state));\n\nacc->resume_state[RES_CTRL_REG1] = H3LIS100DL_ENABLE_ALL_AXES;\n\nerr = h3lis100dl_input_init(acc);\nif (err < 0) {\ndev_err(acc->dev, \"input init failed\n\");\ngoto err_power_off;\n}\n\nerr = h3lis100dl_device_power_on(acc);\nif (err < 0) {\ndev_err(acc->dev, \"power on failed: %d\n\", err);\ngoto err_pdata_init;\n}\n\natomic_set(&acc->enabled, 1);\n\nerr = h3lis100dl_update_g_range(acc, acc->pdata->g_range);\nif (err < 0) {\ndev_err(acc->dev, \"update_g_range failed\n\");\ngoto err_power_off;\n}\n\nerr = h3lis100dl_update_odr(acc, acc->pdata->poll_interval);\nif (err < 0) {\ndev_err(acc->dev, \"update_odr failed\n\");\ngoto err_power_off;\n}\n\nerr = create_sysfs_interfaces(acc->dev);\nif (err < 0) {\ndev_err(acc->dev,\n\"device H3LIS100DL_DEV_NAME \"\n\"sysfs register failed\n\");\ngoto err_input_cleanup;\n}\n\nh3lis100dl_device_power_off(acc);\n\n/ As default, do not report information /\natomic_set(&acc->enabled, 0);\n\nhrtimer_init(&acc->hr_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);\nacc->hr_timer.function = &h3lis100dl_timer_func_queue_work;\n\nmutex_unlock(&acc->lock);\n\ndev_info(acc->dev, \"%s: probed\n\", H3LIS100DL_DEV_NAME);\n\nreturn 0;\n\nerr_input_cleanup:\nh3lis100dl_input_cleanup(acc);\nerr_power_off:\nh3lis100dl_device_power_off(acc);\nerr_pdata_init:\nif (acc->pdata->exit)\nacc->pdata->exit();\nexit_kfree_pdata:\nkfree(acc->pdata);\nerr_mutexunlock:\nmutex_unlock(&acc->lock);\n#ifndef CONFIG_OF\nexit_check_functionality_failed:\n#endif\nprintk(KERN_ERR \"%s: Driver Init failed\n\", H3LIS100DL_DEV_NAME);\n\nreturn err;\n}\nEXPORT_SYMBOL(h3lis100dl_common_probe);\n\nint h3lis100dl_common_remove(struct h3lis100dl_data acc)\n{\nh3lis100dl_input_cleanup(acc);\nh3lis100dl_device_power_off(acc);\nremove_sysfs_interfaces(acc->dev);\n\nif (acc->pdata->exit)\nacc->pdata->exit();\nkfree(acc->pdata);\n\nif(h3lis100dl_workqueue) {\nflush_workqueue(h3lis100dl_workqueue);\ndestroy_workqueue(h3lis100dl_workqueue);\nh3lis100dl_workqueue = NULL;\n}\n\nreturn 0;\n}\nEXPORT_SYMBOL(h3lis100dl_common_remove);\n\n#ifdef CONFIG_PM_SLEEP\nint h3lis100dl_common_resume(struct h3lis100dl_data acc)\n{\nif (acc->on_before_suspend)\nreturn h3lis100dl_enable(acc);\nreturn 0;\n}\nEXPORT_SYMBOL(h3lis100dl_common_resume);\n\nint h3lis100dl_common_suspend(struct h3lis100dl_data acc)\n{\nacc->on_before_suspend = atomic_read(&acc->enabled);\nreturn h3lis100dl_disable(acc);\n}\nEXPORT_SYMBOL(h3lis100dl_common_suspend);\n#endif /* CONFIG_PM_SLEEP */\n\nMODULE_DESCRIPTION(\"h3lis100dl accelerometer driver\");\nMODULE_AUTHOR(\"Armando Visconti, STMicroelectronics\");\nMODULE_LICENSE(\"GPL v2\");"}
	{"text":"#include <linux/err.h>\n#include <linux/errno.h>\n#include <linux/delay.h>\n#include <linux/fs.h>\n#include <linux/input.h>\n#include <linux/uaccess.h>\n#include <linux/workqueue.h>\n#include <linux/irq.h>\n#include <linux/gpio.h>\n#include <linux/interrupt.h>\n#include <linux/slab.h>\n#include <linux/kernel.h>\n#include <linux/device.h>\n#include <linux/module.h>\n#include <linux/moduleparam.h>\n#include <linux/version.h>\n\n#include \"lis3dhh.h\"\n\n/* Acc. full scale fixed /\n#define LIS3DHH_ACC_FULL_SCALE \"2.5\"\n\n/ Acc. sensitivity in ug/LSB /\n#define LIS3DHH_SENSITIVITY 76\n\n/ Acc. number of samples to discard for stable data /\n#define LIS3DHH_DISC_SAMPLE 10\n\n/ Acc. operating mode /\n#define LIS3DHH_ENABLE 0x80\n#define LIS3DHH_DISABLE 0x00\n\n/ Acc. ID /\n#define LIS3DHH_WHOAMI 0x11\n\n/ Device registers /\n#define WHO_AM_I 0x0F\n#define CTRL1 0x20\n#define STATUS 0x27\n#define AXISDATA_REG 0x28\n\n/ Register bitmasks /\n#define CTRL1_EN_MODE 0x80\n#define CTRL1_EN_MASK 0x80\n\n#define CTRL1_BDU_ENABLE 0x08\n#define CTRL1_BDU_MASK 0x08\n\n#define CTRL1_IF_ADD_INC 0x40\n#define CTRL1_IF_ADD_INC_MASK 0x40\n\nstatic inline int64_t lis3dhh_acc_get_time_ns(void)\n{\nreturn ktime_to_ns(ktime_get_boottime());\n}\n\nstatic int lis3dhh_acc_hw_init(struct lis3dhh_acc_status stat)\n{\nint err;\n\nstat->resume_state \|= CTRL1_EN_MODE;\n\nerr = stat->tf->write(stat, CTRL1, 1, &stat->resume_state);\nif (err < 0)\nreturn err;\n\nstat->hw_initialized = 1;\n\nreturn 0;\n}\n\nstatic void lis3dhh_acc_device_power_off(struct lis3dhh_acc_status stat)\n{\nint err;\nu8 buf = (CTRL1_BDU_ENABLE \| CTRL1_IF_ADD_INC);\n\nerr = stat->tf->write(stat, CTRL1, 1, &buf);\nif (err < 0)\ndev_err(stat->dev, \"soft power off failed: %d\n\", err);\n\nif (stat->pdata->power_off) {\nstat->pdata->power_off();\nstat->hw_initialized = 0;\n}\n\nif (stat->hw_initialized) {\nstat->hw_initialized = 0;\n}\n}\n\nstatic int lis3dhh_acc_device_power_on(struct lis3dhh_acc_status stat)\n{\nint err;\n\nif (stat->pdata->power_on) {\nerr = stat->pdata->power_on();\nif (err < 0) {\ndev_err(stat->dev,\n\"power_on failed: %d\n\", err);\nreturn err;\n}\n}\n\nif (!stat->hw_initialized) {\nerr = lis3dhh_acc_hw_init(stat);\nif (stat->hw_working == 1 && err < 0) {\nlis3dhh_acc_device_power_off(stat);\nreturn err;\n}\n}\n\nreturn 0;\n}\n\nstatic void lis3dhh_acc_report_values(struct lis3dhh_acc_status stat,\nint xyz, int64_t timestamp)\n{\ninput_event(stat->input_dev, INPUT_EVENT_TYPE, INPUT_EVENT_X, xyz[0]);\ninput_event(stat->input_dev, INPUT_EVENT_TYPE, INPUT_EVENT_Y, xyz[1]);\ninput_event(stat->input_dev, INPUT_EVENT_TYPE, INPUT_EVENT_Z, xyz[2]);\ninput_event(stat->input_dev, INPUT_EVENT_TYPE, INPUT_EVENT_TIME_MSB,\ntimestamp >> 32);\ninput_event(stat->input_dev, INPUT_EVENT_TYPE, INPUT_EVENT_TIME_LSB,\ntimestamp & 0xffffffff);\ninput_sync(stat->input_dev);\n}\n\nstatic void lis3dhh_acc_report_triple(struct lis3dhh_acc_status stat)\n{\nint err;\nu8 acc_data[6];\nint xyz[3] = { 0 };\n\nerr = stat->tf->read(stat, AXISDATA_REG, 6, acc_data);\nif (err < 0)\nreturn;\n\nxyz[0] = (s32)((s16)(acc_data[0] \| (acc_data[1] << 8)));\nxyz[1] = (s32)((s16)(acc_data[2] \| (acc_data[3] << 8)));\nxyz[2] = (s32)((s16)(acc_data[4] \| (acc_data[5] << 8)));\nxyz[0] = LIS3DHH_SENSITIVITY;\nxyz[1] = LIS3DHH_SENSITIVITY;\nxyz[2] = LIS3DHH_SENSITIVITY;\n\nif (stat->sample_to_discard)\nstat->sample_to_discard--;\nelse\nlis3dhh_acc_report_values(stat, xyz, stat->timestamp);\n}\n\nstatic int lis3dhh_acc_enable(struct lis3dhh_acc_status stat)\n{\nint err;\n\nif (!atomic_cmpxchg(&stat->enabled, 0, 1)) {\nerr = lis3dhh_acc_device_power_on(stat);\nif (err < 0) {\natomic_set(&stat->enabled, 0);\nreturn err;\n}\n\n/ Dischard first # samples. /\nstat->sample_to_discard = LIS3DHH_DISC_SAMPLE;\nstat->polling_ktime = ktime_set(0,\n(LIS3DHH_MIN_POLL_PERIOD_NS % 1000000));\nhrtimer_start(&stat->hr_timer_poll,\nstat->polling_ktime, HRTIMER_MODE_REL);\n}\n\nreturn 0;\n}\n\nstatic int lis3dhh_acc_disable(struct lis3dhh_acc_status stat)\n{\nif (atomic_cmpxchg(&stat->enabled, 1, 0)) {\ncancel_work_sync(&stat->input_poll_work);\nlis3dhh_acc_device_power_off(stat);\n}\n\nreturn 0;\n}\n\n/\n Device doesn't support change in ODR HW so we left it run at 1.1 kHz\n* and change only the timer period\n/\nstatic ssize_t attr_set_polling_rate(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nreturn size;\n}\n\nstatic ssize_t attr_get_polling_rate(struct device dev,\nstruct device_attribute attr,\nchar buf)\n{\nreturn sprintf(buf, \"%d.%d\n\", LIS3DHH_MIN_POLL_PERIOD_NS / 1000000,\n(LIS3DHH_MIN_POLL_PERIOD_NS % 1000000) / 1000);\n}\n\nstatic ssize_t attr_set_range(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nstruct lis3dhh_acc_status stat = dev_get_drvdata(dev);\n\ndev_info(stat->dev, \"range set fixed to %s\n\", LIS3DHH_ACC_FULL_SCALE);\n\nreturn size;\n}\n\nstatic ssize_t attr_get_range(struct device dev,\nstruct device_attribute attr, char buf)\n{\nreturn sprintf(buf, \"%s\n\", LIS3DHH_ACC_FULL_SCALE);\n}\n\nstatic ssize_t attr_get_enable(struct device dev,\nstruct device_attribute attr, char buf)\n{\nstruct lis3dhh_acc_status stat = dev_get_drvdata(dev);\nint val = atomic_read(&stat->enabled);\n\nreturn sprintf(buf, \"%d\n\", val);\n}\n\nstatic ssize_t attr_set_enable(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t size)\n{\nstruct lis3dhh_acc_status stat = dev_get_drvdata(dev);\nunsigned long val;\n\nif (kstrtoul(buf, 10, &val))\nreturn -EINVAL;\n\nif (val)\nlis3dhh_acc_enable(stat);\nelse\nlis3dhh_acc_disable(stat);\n\nreturn size;\n}\n\nstatic struct device_attribute attributes[] = {\n__ATTR(pollrate_ms, 0664, attr_get_polling_rate, attr_set_polling_rate),\n__ATTR(enable_device, 0664, attr_get_enable, attr_set_enable),\n__ATTR(range, 0664, attr_get_range, attr_set_range),\n};\n\nstatic int create_sysfs_interfaces(struct device dev)\n{\nint i;\n\nfor (i = 0; i < ARRAY_SIZE(attributes); i++)\nif (device_create_file(dev, attributes + i))\ngoto error;\n\nreturn 0;\n\nerror:\nfor ( ; i >= 0; i--)\ndevice_remove_file(dev, attributes + i);\ndev_err(dev, \"%s:Unable to create interface\n\", __func__);\n\nreturn -1;\n}\n\nstatic int remove_sysfs_interfaces(struct device dev)\n{\nint i;\n\nfor (i = 0; i < ARRAY_SIZE(attributes); i++)\ndevice_remove_file(dev, attributes + i);\n\nreturn 0;\n}\n\nstatic void lis3dhh_acc_input_poll_work_func(struct work_struct work)\n{\nstruct lis3dhh_acc_status stat;\nktime_t tmpkt, ktdelta;\n\nstat = container_of((struct work_struct ) work,\nstruct lis3dhh_acc_status, input_poll_work);\n\nif (atomic_read(&stat->enabled)) {\n/ Adjust new timeout. /\nktdelta = ktime_set(0, lis3dhh_acc_get_time_ns() - stat->timestamp);\n/ Avoid negative value in case of High ODR. /\nif (ktime_after(stat->polling_ktime, ktdelta))\ntmpkt = ktime_sub(stat->polling_ktime, ktdelta);\nelse\ntmpkt = stat->polling_ktime;\n\nhrtimer_start(&stat->hr_timer_poll, tmpkt, HRTIMER_MODE_REL);\n}\n\nlis3dhh_acc_report_triple(stat);\n}\n\nenum hrtimer_restart lis3dhh_acc_hr_timer_poll_function(struct hrtimer timer)\n{\nstruct lis3dhh_acc_status stat;\n\nstat = container_of((struct hrtimer )timer,\nstruct lis3dhh_acc_status, hr_timer_poll);\n\nstat->timestamp = lis3dhh_acc_get_time_ns();\n\nqueue_work(stat->hr_timer_poll_work_queue, &stat->input_poll_work);\n\nreturn HRTIMER_NORESTART;\n}\n\nint lis3dhh_acc_input_open(struct input_dev input)\n{\nstruct lis3dhh_acc_status stat = input_get_drvdata(input);\n\nreturn lis3dhh_acc_enable(stat);\n}\n\nvoid lis3dhh_acc_input_close(struct input_dev dev)\n{\nstruct lis3dhh_acc_status stat = input_get_drvdata(dev);\n\nlis3dhh_acc_disable(stat);\n}\n\nstatic int lis3dhh_acc_input_init(struct lis3dhh_acc_status stat)\n{\nint err;\n\nINIT_WORK(&stat->input_poll_work, lis3dhh_acc_input_poll_work_func);\nstat->input_dev = input_allocate_device();\nif (!stat->input_dev) {\nerr = -ENOMEM;\ndev_err(stat->dev, \"input device allocation failed\n\");\nreturn err;\n}\n\nstat->input_dev->open = lis3dhh_acc_input_open;\nstat->input_dev->close = lis3dhh_acc_input_close;\nstat->input_dev->name = stat->name;\nstat->input_dev->id.bustype = stat->bustype;\nstat->input_dev->dev.parent = stat->dev;\ninput_set_drvdata(stat->input_dev, stat);\n\n/ Set Misc event type /\n__set_bit(INPUT_EVENT_TYPE, stat->input_dev->evbit);\n__set_bit(INPUT_EVENT_X, stat->input_dev->mscbit);\n__set_bit(INPUT_EVENT_Y, stat->input_dev->mscbit);\n__set_bit(INPUT_EVENT_Z, stat->input_dev->mscbit);\n__set_bit(INPUT_EVENT_TIME_MSB, stat->input_dev->mscbit);\n__set_bit(INPUT_EVENT_TIME_LSB, stat->input_dev->mscbit);\n\nerr = input_register_device(stat->input_dev);\nif (err) {\ndev_err(stat->dev, \"unable to register input device %s\n\",\nstat->input_dev->name);\ninput_free_device(stat->input_dev);\nreturn err;\n}\n\nreturn 0;\n}\n\nstatic void lis3dhh_acc_input_cleanup(struct lis3dhh_acc_status stat)\n{\ninput_unregister_device(stat->input_dev);\ninput_free_device(stat->input_dev);\n}\n\nstatic int lis3dhh_discover(struct lis3dhh_acc_status stat)\n{\nint err;\nu8 wai = 0x00;\n\nerr = stat->tf->read(stat, WHO_AM_I, 1, &wai);\nif (err < 0) {\ndev_warn(stat->dev, \"failed to read Who-Am-I register\");\nreturn err;\n}\n\nif (wai != LIS3DHH_WHOAMI) {\ndev_err(stat->dev, \"device unknown. Expected: 0x%02x,\"\n\" Replies: 0x%02x\n\", LIS3DHH_WHOAMI, wai);\nreturn -ENODEV;\n}\n\nstat->hw_working = 1;\n\nreturn 0;\n}\n\nint lis3dhh_common_probe(struct lis3dhh_acc_status stat)\n{\nint err;\n\nmutex_init(&stat->tb.buf_lock);\n\nerr = lis3dhh_discover(stat);\nif (err < 0)\nreturn err;\n\nstat->pdata = kzalloc(sizeof(stat->pdata), GFP_KERNEL);\nif (stat->pdata == NULL) {\ndev_err(stat->dev, \"failed to allocate memory for pdata: %d\n\", err);\nreturn -ENOMEM;\n}\n\n/ Attach if exists custom platform data/functions /\nif (stat->dev->platform_data != NULL)\nmemcpy(stat->pdata, stat->dev->platform_data, sizeof(stat->pdata));\n\nif (stat->pdata->init) {\nerr = stat->pdata->init();\nif (err < 0) {\ndev_err(stat->dev, \"init failed: %d\n\", err);\ngoto err_pdata_init;\n}\n}\n\n/* Set registers initial value /\nstat->resume_state = (CTRL1_BDU_ENABLE \| CTRL1_IF_ADD_INC);\n\nerr = lis3dhh_acc_device_power_on(stat);\nif (err < 0) {\ndev_err(stat->dev, \"power on failed: %d\n\", err);\ngoto err_pdata_init;\n}\n\natomic_set(&stat->enabled, 1);\n\n/ Init polling workqueue /\nstat->hr_timer_poll_work_queue =\ncreate_workqueue(\"lis3dhh_acc_hr_timer_poll_wq\");\nif (!stat->hr_timer_poll_work_queue) {\ndev_err(stat->dev, \"create workqueue failed\n\");\nerr = -ENOMEM;\ngoto err_wk_null;\n}\n\nhrtimer_init(&stat->hr_timer_poll, CLOCK_MONOTONIC, HRTIMER_MODE_REL);\nstat->hr_timer_poll.function = &lis3dhh_acc_hr_timer_poll_function;\n\nerr = lis3dhh_acc_input_init(stat);\nif (err < 0) {\ndev_err(stat->dev, \"input init failed\n\");\ngoto err_remove_hr_work_queue;\n}\n\nerr = create_sysfs_interfaces(stat->dev);\nif (err < 0) {\ndev_err(stat->dev, \"device %s sysfs register failed\n\",\nLIS3DHH_ACC_DEV_NAME);\ngoto err_input_cleanup;\n}\n\nlis3dhh_acc_device_power_off(stat);\n\n/ As default, do not report information /\natomic_set(&stat->enabled, 0);\n\ndev_info(stat->dev, \"%s: probed\n\", LIS3DHH_ACC_DEV_NAME);\n\nreturn 0;\n\nerr_input_cleanup:\nlis3dhh_acc_input_cleanup(stat);\n\nerr_remove_hr_work_queue:\nif (stat->hr_timer_poll_work_queue) {\nflush_workqueue(stat->hr_timer_poll_work_queue);\ndestroy_workqueue(stat->hr_timer_poll_work_queue);\nstat->hr_timer_poll_work_queue = NULL;\n}\n\nerr_wk_null:\nlis3dhh_acc_device_power_off(stat);\n\nerr_pdata_init:\nif (stat->pdata->exit)\nstat->pdata->exit();\nkfree(stat->pdata);\npr_err(\"%s: Driver Init failed\n\", LIS3DHH_ACC_DEV_NAME);\n\nreturn err;\n}\nEXPORT_SYMBOL(lis3dhh_common_probe);\n\nint lis3dhh_common_remove(struct lis3dhh_acc_status stat)\n{\ndev_info(stat->dev, \"driver removing\n\");\n\nlis3dhh_acc_disable(stat);\nlis3dhh_acc_input_cleanup(stat);\nremove_sysfs_interfaces(stat->dev);\n\nif (stat->hr_timer_poll_work_queue) {\nflush_workqueue(stat->hr_timer_poll_work_queue);\ndestroy_workqueue(stat->hr_timer_poll_work_queue);\nstat->hr_timer_poll_work_queue = NULL;\n}\n\nif (stat->pdata->exit)\nstat->pdata->exit();\n\nif (stat->pdata) {\nkfree(stat->pdata);\nstat->pdata = NULL;\n}\n\nreturn 0;\n}\nEXPORT_SYMBOL(lis3dhh_common_remove);\n\n#ifdef CONFIG_PM_SLEEP\nint lis3dhh_common_resume(struct lis3dhh_acc_status stat)\n{\nif (stat->on_before_suspend)\nreturn lis3dhh_acc_enable(stat);\n\nreturn 0;\n}\nEXPORT_SYMBOL(lis3dhh_common_resume);\n\nint lis3dhh_common_suspend(struct lis3dhh_acc_status stat)\n{\nstat->on_before_suspend = atomic_read(&stat->enabled);\n\nreturn lis3dhh_acc_disable(stat);\n}\nEXPORT_SYMBOL(lis3dhh_common_suspend);\n#endif /* CONFIG_PM_SLEEP */\n\nMODULE_DESCRIPTION(\"lis3dhh acc driver\");\nMODULE_AUTHOR(\"Mario Tesi, STMicroelectronics\");\nMODULE_LICENSE(\"GPL v2\");"}
	{"text":"#include <linux/bitfield.h>\n#include <linux/module.h>\n#include <linux/regmap.h>\n\n#include \"adxl313.h\"\n\nstatic const struct regmap_range adxl312_readable_reg_range[] = {\nregmap_reg_range(ADXL313_REG_DEVID0, ADXL313_REG_DEVID0),\nregmap_reg_range(ADXL313_REG_OFS_AXIS(0), ADXL313_REG_OFS_AXIS(2)),\nregmap_reg_range(ADXL313_REG_THRESH_ACT, ADXL313_REG_ACT_INACT_CTL),\nregmap_reg_range(ADXL313_REG_BW_RATE, ADXL313_REG_FIFO_STATUS),\n};\n\nstatic const struct regmap_range adxl313_readable_reg_range[] = {\nregmap_reg_range(ADXL313_REG_DEVID0, ADXL313_REG_XID),\nregmap_reg_range(ADXL313_REG_SOFT_RESET, ADXL313_REG_SOFT_RESET),\nregmap_reg_range(ADXL313_REG_OFS_AXIS(0), ADXL313_REG_OFS_AXIS(2)),\nregmap_reg_range(ADXL313_REG_THRESH_ACT, ADXL313_REG_ACT_INACT_CTL),\nregmap_reg_range(ADXL313_REG_BW_RATE, ADXL313_REG_FIFO_STATUS),\n};\n\nconst struct regmap_access_table adxl312_readable_regs_table = {\n.yes_ranges = adxl312_readable_reg_range,\n.n_yes_ranges = ARRAY_SIZE(adxl312_readable_reg_range),\n};\nEXPORT_SYMBOL_NS_GPL(adxl312_readable_regs_table, IIO_ADXL313);\n\nconst struct regmap_access_table adxl313_readable_regs_table = {\n.yes_ranges = adxl313_readable_reg_range,\n.n_yes_ranges = ARRAY_SIZE(adxl313_readable_reg_range),\n};\nEXPORT_SYMBOL_NS_GPL(adxl313_readable_regs_table, IIO_ADXL313);\n\nconst struct regmap_access_table adxl314_readable_regs_table = {\n.yes_ranges = adxl312_readable_reg_range,\n.n_yes_ranges = ARRAY_SIZE(adxl312_readable_reg_range),\n};\nEXPORT_SYMBOL_NS_GPL(adxl314_readable_regs_table, IIO_ADXL313);\n\nstatic int adxl312_check_id(struct device dev,\nstruct adxl313_data data)\n{\nunsigned int regval;\nint ret;\n\nret = regmap_read(data->regmap, ADXL313_REG_DEVID0, &regval);\nif (ret)\nreturn ret;\n\nif (regval != ADXL313_DEVID0_ADXL312_314)\ndev_warn(dev, \"Invalid manufacturer ID: %#02x\n\", regval);\n\nreturn 0;\n}\n\nstatic int adxl313_check_id(struct device dev,\nstruct adxl313_data data)\n{\nunsigned int regval;\nint ret;\n\nret = regmap_read(data->regmap, ADXL313_REG_DEVID0, &regval);\nif (ret)\nreturn ret;\n\nif (regval != ADXL313_DEVID0)\ndev_warn(dev, \"Invalid manufacturer ID: 0x%02x\n\", regval);\n\n/* Check DEVID1 and PARTID /\nif (regval == ADXL313_DEVID0) {\nret = regmap_read(data->regmap, ADXL313_REG_DEVID1, &regval);\nif (ret)\nreturn ret;\n\nif (regval != ADXL313_DEVID1)\ndev_warn(dev, \"Invalid mems ID: 0x%02x\n\", regval);\n\nret = regmap_read(data->regmap, ADXL313_REG_PARTID, &regval);\nif (ret)\nreturn ret;\n\nif (regval != ADXL313_PARTID)\ndev_warn(dev, \"Invalid device ID: 0x%02x\n\", regval);\n}\n\nreturn 0;\n}\n\nconst struct adxl313_chip_info adxl31x_chip_info[] = {\n[ADXL312] = {\n.name = \"adxl312\",\n.type = ADXL312,\n.scale_factor = 28425072,\n.variable_range = true,\n.soft_reset = false,\n.check_id = &adxl312_check_id,\n},\n[ADXL313] = {\n.name = \"adxl313\",\n.type = ADXL313,\n.scale_factor = 9576806,\n.variable_range = true,\n.soft_reset = true,\n.check_id = &adxl313_check_id,\n},\n[ADXL314] = {\n.name = \"adxl314\",\n.type = ADXL314,\n.scale_factor = 478858719,\n.variable_range = false,\n.soft_reset = false,\n.check_id = &adxl312_check_id,\n},\n};\nEXPORT_SYMBOL_NS_GPL(adxl31x_chip_info, IIO_ADXL313);\n\nstatic const struct regmap_range adxl312_writable_reg_range[] = {\nregmap_reg_range(ADXL313_REG_OFS_AXIS(0), ADXL313_REG_OFS_AXIS(2)),\nregmap_reg_range(ADXL313_REG_THRESH_ACT, ADXL313_REG_ACT_INACT_CTL),\nregmap_reg_range(ADXL313_REG_BW_RATE, ADXL313_REG_INT_MAP),\nregmap_reg_range(ADXL313_REG_DATA_FORMAT, ADXL313_REG_DATA_FORMAT),\nregmap_reg_range(ADXL313_REG_FIFO_CTL, ADXL313_REG_FIFO_CTL),\n};\n\nstatic const struct regmap_range adxl313_writable_reg_range[] = {\nregmap_reg_range(ADXL313_REG_SOFT_RESET, ADXL313_REG_SOFT_RESET),\nregmap_reg_range(ADXL313_REG_OFS_AXIS(0), ADXL313_REG_OFS_AXIS(2)),\nregmap_reg_range(ADXL313_REG_THRESH_ACT, ADXL313_REG_ACT_INACT_CTL),\nregmap_reg_range(ADXL313_REG_BW_RATE, ADXL313_REG_INT_MAP),\nregmap_reg_range(ADXL313_REG_DATA_FORMAT, ADXL313_REG_DATA_FORMAT),\nregmap_reg_range(ADXL313_REG_FIFO_CTL, ADXL313_REG_FIFO_CTL),\n};\n\nconst struct regmap_access_table adxl312_writable_regs_table = {\n.yes_ranges = adxl312_writable_reg_range,\n.n_yes_ranges = ARRAY_SIZE(adxl312_writable_reg_range),\n};\nEXPORT_SYMBOL_NS_GPL(adxl312_writable_regs_table, IIO_ADXL313);\n\nconst struct regmap_access_table adxl313_writable_regs_table = {\n.yes_ranges = adxl313_writable_reg_range,\n.n_yes_ranges = ARRAY_SIZE(adxl313_writable_reg_range),\n};\nEXPORT_SYMBOL_NS_GPL(adxl313_writable_regs_table, IIO_ADXL313);\n\nconst struct regmap_access_table adxl314_writable_regs_table = {\n.yes_ranges = adxl312_writable_reg_range,\n.n_yes_ranges = ARRAY_SIZE(adxl312_writable_reg_range),\n};\nEXPORT_SYMBOL_NS_GPL(adxl314_writable_regs_table, IIO_ADXL313);\n\nstatic const int adxl313_odr_freqs[][2] = {\n[0] = { 6, 250000 },\n[1] = { 12, 500000 },\n[2] = { 25, 0 },\n[3] = { 50, 0 },\n[4] = { 100, 0 },\n[5] = { 200, 0 },\n[6] = { 400, 0 },\n[7] = { 800, 0 },\n[8] = { 1600, 0 },\n[9] = { 3200, 0 },\n};\n\n#define ADXL313_ACCEL_CHANNEL(index, axis) { \\n.type = IIO_ACCEL, \\n.address = index, \\n.modified = 1, \\n.channel2 = IIO_MOD_##axis, \\n.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \\nBIT(IIO_CHAN_INFO_CALIBBIAS), \\n.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \| \\nBIT(IIO_CHAN_INFO_SAMP_FREQ), \\n.info_mask_shared_by_type_available = \\nBIT(IIO_CHAN_INFO_SAMP_FREQ), \\n.scan_type = { \\n.realbits = 13, \\n}, \\n}\n\nstatic const struct iio_chan_spec adxl313_channels[] = {\nADXL313_ACCEL_CHANNEL(0, X),\nADXL313_ACCEL_CHANNEL(1, Y),\nADXL313_ACCEL_CHANNEL(2, Z),\n};\n\nstatic int adxl313_set_odr(struct adxl313_data data,\nunsigned int freq1, unsigned int freq2)\n{\nunsigned int i;\n\nfor (i = 0; i < ARRAY_SIZE(adxl313_odr_freqs); i++) {\nif (adxl313_odr_freqs[i][0] == freq1 &&\nadxl313_odr_freqs[i][1] == freq2)\nbreak;\n}\n\nif (i == ARRAY_SIZE(adxl313_odr_freqs))\nreturn -EINVAL;\n\nreturn regmap_update_bits(data->regmap, ADXL313_REG_BW_RATE,\nADXL313_RATE_MSK,\nFIELD_PREP(ADXL313_RATE_MSK, ADXL313_RATE_BASE + i));\n}\n\nstatic int adxl313_read_axis(struct adxl313_data data,\nstruct iio_chan_spec const chan)\n{\nint ret;\n\nmutex_lock(&data->lock);\n\nret = regmap_bulk_read(data->regmap,\nADXL313_REG_DATA_AXIS(chan->address),\n&data->transf_buf, sizeof(data->transf_buf));\nif (ret)\ngoto unlock_ret;\n\nret = le16_to_cpu(data->transf_buf);\n\nunlock_ret:\nmutex_unlock(&data->lock);\nreturn ret;\n}\n\nstatic int adxl313_read_freq_avail(struct iio_dev indio_dev,\nstruct iio_chan_spec const chan,\nconst int *vals, int type, int length,\nlong mask)\n{\nswitch (mask) {\ncase IIO_CHAN_INFO_SAMP_FREQ:\nvals = (const int )adxl313_odr_freqs;\nlength = ARRAY_SIZE(adxl313_odr_freqs) * 2;\ntype = IIO_VAL_INT_PLUS_MICRO;\nreturn IIO_AVAIL_LIST;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int adxl313_read_raw(struct iio_dev indio_dev,\nstruct iio_chan_spec const chan,\nint val, int val2, long mask)\n{\nstruct adxl313_data data = iio_priv(indio_dev);\nunsigned int regval;\nint ret;\n\nswitch (mask) {\ncase IIO_CHAN_INFO_RAW:\nret = adxl313_read_axis(data, chan);\nif (ret < 0)\nreturn ret;\n\nval = sign_extend32(ret, chan->scan_type.realbits - 1);\nreturn IIO_VAL_INT;\ncase IIO_CHAN_INFO_SCALE:\nval = 0;\n\nval2 = data->chip_info->scale_factor;\n\nreturn IIO_VAL_INT_PLUS_NANO;\ncase IIO_CHAN_INFO_CALIBBIAS:\nret = regmap_read(data->regmap,\nADXL313_REG_OFS_AXIS(chan->address), &regval);\nif (ret)\nreturn ret;\n\n/\n* 8-bit resolution at minimum range, that is 4x accel data scale\n* factor at full resolution\n/\nval = sign_extend32(regval, 7) * 4;\nreturn IIO_VAL_INT;\ncase IIO_CHAN_INFO_SAMP_FREQ:\nret = regmap_read(data->regmap, ADXL313_REG_BW_RATE, &regval);\nif (ret)\nreturn ret;\n\nret = FIELD_GET(ADXL313_RATE_MSK, regval) - ADXL313_RATE_BASE;\nval = adxl313_odr_freqs[ret][0];\nval2 = adxl313_odr_freqs[ret][1];\nreturn IIO_VAL_INT_PLUS_MICRO;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int adxl313_write_raw(struct iio_dev indio_dev,\nstruct iio_chan_spec const chan,\nint val, int val2, long mask)\n{\nstruct adxl313_data data = iio_priv(indio_dev);\n\nswitch (mask) {\ncase IIO_CHAN_INFO_CALIBBIAS:\n/\n* 8-bit resolution at minimum range, that is 4x accel data scale\n* factor at full resolution\n/\nif (clamp_val(val, -128 4, 127 * 4) != val)\nreturn -EINVAL;\n\nreturn regmap_write(data->regmap,\nADXL313_REG_OFS_AXIS(chan->address),\nval / 4);\ncase IIO_CHAN_INFO_SAMP_FREQ:\nreturn adxl313_set_odr(data, val, val2);\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic const struct iio_info adxl313_info = {\n.read_raw = adxl313_read_raw,\n.write_raw = adxl313_write_raw,\n.read_avail = adxl313_read_freq_avail,\n};\n\nstatic int adxl313_setup(struct device dev, struct adxl313_data data,\nint (setup)(struct device , struct regmap ))\n{\nint ret;\n\n/\n* If sw reset available, ensures the device is in a consistent\n* state after start up\n/\nif (data->chip_info->soft_reset) {\nret = regmap_write(data->regmap, ADXL313_REG_SOFT_RESET,\nADXL313_SOFT_RESET);\nif (ret)\nreturn ret;\n}\n\nif (setup) {\nret = setup(dev, data->regmap);\nif (ret)\nreturn ret;\n}\n\nret = data->chip_info->check_id(dev, data);\nif (ret)\nreturn ret;\n\n/ Sets the range to maximum, full resolution, if applicable /\nif (data->chip_info->variable_range) {\nret = regmap_update_bits(data->regmap, ADXL313_REG_DATA_FORMAT,\nADXL313_RANGE_MSK,\nFIELD_PREP(ADXL313_RANGE_MSK, ADXL313_RANGE_MAX));\nif (ret)\nreturn ret;\n\n/ Enables full resolution /\nret = regmap_update_bits(data->regmap, ADXL313_REG_DATA_FORMAT,\nADXL313_FULL_RES, ADXL313_FULL_RES);\nif (ret)\nreturn ret;\n}\n\n/ Enables measurement mode /\nreturn regmap_update_bits(data->regmap, ADXL313_REG_POWER_CTL,\nADXL313_POWER_CTL_MSK,\nADXL313_MEASUREMENT_MODE);\n}\n\n/\n adxl313_core_probe() - probe and setup for adxl313 accelerometer\n* @dev: Driver model representation of the device\n* @regmap: Register map of the device\n* @chip_info: Structure containing device specific data\n* @setup: Setup routine to be executed right before the standard device\n* setup, can also be set to NULL if not required\n\n Return: 0 on success, negative errno on error cases\n/\nint adxl313_core_probe(struct device dev,\nstruct regmap regmap,\nconst struct adxl313_chip_info chip_info,\nint (setup)(struct device , struct regmap ))\n{\nstruct adxl313_data data;\nstruct iio_dev indio_dev;\nint ret;\n\nindio_dev = devm_iio_device_alloc(dev, sizeof(data));\nif (!indio_dev)\nreturn -ENOMEM;\n\ndata = iio_priv(indio_dev);\ndata->regmap = regmap;\ndata->chip_info = chip_info;\n\nmutex_init(&data->lock);\n\nindio_dev->name = chip_info->name;\nindio_dev->info = &adxl313_info;\nindio_dev->modes = INDIO_DIRECT_MODE;\nindio_dev->channels = adxl313_channels;\nindio_dev->num_channels = ARRAY_SIZE(adxl313_channels);\n\nret = adxl313_setup(dev, data, setup);\nif (ret) {\ndev_err(dev, \"ADXL313 setup failed\n\");\nreturn ret;\n}\n\nreturn devm_iio_device_register(dev, indio_dev);\n}\nEXPORT_SYMBOL_NS_GPL(adxl313_core_probe, IIO_ADXL313);\n\nMODULE_AUTHOR(\"Lucas Stankus <lucas.p.stankus@gmail.com>\");\nMODULE_DESCRIPTION(\"ADXL313 3-Axis Digital Accelerometer core driver\");\nMODULE_LICENSE(\"GPL v2\");"}
	{"text":"#include <linux/bits.h>\n#include <linux/bitfield.h>\n#include <linux/i2c.h>\n#include <linux/module.h>\n#include <linux/of_irq.h>\n#include <linux/pm_runtime.h>\n#include <linux/regulator/consumer.h>\n#include <linux/regmap.h>\n\n#include <linux/iio/buffer.h>\n#include <linux/iio/events.h>\n#include <linux/iio/iio.h>\n#include <linux/iio/kfifo_buf.h>\n#include <linux/iio/sysfs.h>\n\n#include \"fxls8962af.h\"\n\n#define FXLS8962AF_INT_STATUS 0x00\n#define FXLS8962AF_INT_STATUS_SRC_BOOT BIT(0)\n#define FXLS8962AF_INT_STATUS_SRC_SDCD_OT BIT(4)\n#define FXLS8962AF_INT_STATUS_SRC_BUF BIT(5)\n#define FXLS8962AF_INT_STATUS_SRC_DRDY BIT(7)\n#define FXLS8962AF_TEMP_OUT 0x01\n#define FXLS8962AF_VECM_LSB 0x02\n#define FXLS8962AF_OUT_X_LSB 0x04\n#define FXLS8962AF_OUT_Y_LSB 0x06\n#define FXLS8962AF_OUT_Z_LSB 0x08\n#define FXLS8962AF_BUF_STATUS 0x0b\n#define FXLS8962AF_BUF_STATUS_BUF_CNT GENMASK(5, 0)\n#define FXLS8962AF_BUF_STATUS_BUF_OVF BIT(6)\n#define FXLS8962AF_BUF_STATUS_BUF_WMRK BIT(7)\n#define FXLS8962AF_BUF_X_LSB 0x0c\n#define FXLS8962AF_BUF_Y_LSB 0x0e\n#define FXLS8962AF_BUF_Z_LSB 0x10\n\n#define FXLS8962AF_PROD_REV 0x12\n#define FXLS8962AF_WHO_AM_I 0x13\n\n#define FXLS8962AF_SYS_MODE 0x14\n#define FXLS8962AF_SENS_CONFIG1 0x15\n#define FXLS8962AF_SENS_CONFIG1_ACTIVE BIT(0)\n#define FXLS8962AF_SENS_CONFIG1_RST BIT(7)\n#define FXLS8962AF_SC1_FSR_MASK GENMASK(2, 1)\n#define FXLS8962AF_SC1_FSR_PREP(x) FIELD_PREP(FXLS8962AF_SC1_FSR_MASK, (x))\n#define FXLS8962AF_SC1_FSR_GET(x) FIELD_GET(FXLS8962AF_SC1_FSR_MASK, (x))\n\n#define FXLS8962AF_SENS_CONFIG2 0x16\n#define FXLS8962AF_SENS_CONFIG3 0x17\n#define FXLS8962AF_SC3_WAKE_ODR_MASK GENMASK(7, 4)\n#define FXLS8962AF_SC3_WAKE_ODR_PREP(x) FIELD_PREP(FXLS8962AF_SC3_WAKE_ODR_MASK, (x))\n#define FXLS8962AF_SC3_WAKE_ODR_GET(x) FIELD_GET(FXLS8962AF_SC3_WAKE_ODR_MASK, (x))\n#define FXLS8962AF_SENS_CONFIG4 0x18\n#define FXLS8962AF_SC4_INT_PP_OD_MASK BIT(1)\n#define FXLS8962AF_SC4_INT_PP_OD_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_PP_OD_MASK, (x))\n#define FXLS8962AF_SC4_INT_POL_MASK BIT(0)\n#define FXLS8962AF_SC4_INT_POL_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_POL_MASK, (x))\n#define FXLS8962AF_SENS_CONFIG5 0x19\n\n#define FXLS8962AF_WAKE_IDLE_LSB 0x1b\n#define FXLS8962AF_SLEEP_IDLE_LSB 0x1c\n#define FXLS8962AF_ASLP_COUNT_LSB 0x1e\n\n#define FXLS8962AF_INT_EN 0x20\n#define FXLS8962AF_INT_EN_SDCD_OT_EN BIT(5)\n#define FXLS8962AF_INT_EN_BUF_EN BIT(6)\n#define FXLS8962AF_INT_PIN_SEL 0x21\n#define FXLS8962AF_INT_PIN_SEL_MASK GENMASK(7, 0)\n#define FXLS8962AF_INT_PIN_SEL_INT1 0x00\n#define FXLS8962AF_INT_PIN_SEL_INT2 GENMASK(7, 0)\n\n#define FXLS8962AF_OFF_X 0x22\n#define FXLS8962AF_OFF_Y 0x23\n#define FXLS8962AF_OFF_Z 0x24\n\n#define FXLS8962AF_BUF_CONFIG1 0x26\n#define FXLS8962AF_BC1_BUF_MODE_MASK GENMASK(6, 5)\n#define FXLS8962AF_BC1_BUF_MODE_PREP(x) FIELD_PREP(FXLS8962AF_BC1_BUF_MODE_MASK, (x))\n#define FXLS8962AF_BUF_CONFIG2 0x27\n#define FXLS8962AF_BUF_CONFIG2_BUF_WMRK GENMASK(5, 0)\n\n#define FXLS8962AF_ORIENT_STATUS 0x28\n#define FXLS8962AF_ORIENT_CONFIG 0x29\n#define FXLS8962AF_ORIENT_DBCOUNT 0x2a\n#define FXLS8962AF_ORIENT_BF_ZCOMP 0x2b\n#define FXLS8962AF_ORIENT_THS_REG 0x2c\n\n#define FXLS8962AF_SDCD_INT_SRC1 0x2d\n#define FXLS8962AF_SDCD_INT_SRC1_X_OT BIT(5)\n#define FXLS8962AF_SDCD_INT_SRC1_X_POL BIT(4)\n#define FXLS8962AF_SDCD_INT_SRC1_Y_OT BIT(3)\n#define FXLS8962AF_SDCD_INT_SRC1_Y_POL BIT(2)\n#define FXLS8962AF_SDCD_INT_SRC1_Z_OT BIT(1)\n#define FXLS8962AF_SDCD_INT_SRC1_Z_POL BIT(0)\n#define FXLS8962AF_SDCD_INT_SRC2 0x2e\n#define FXLS8962AF_SDCD_CONFIG1 0x2f\n#define FXLS8962AF_SDCD_CONFIG1_Z_OT_EN BIT(3)\n#define FXLS8962AF_SDCD_CONFIG1_Y_OT_EN BIT(4)\n#define FXLS8962AF_SDCD_CONFIG1_X_OT_EN BIT(5)\n#define FXLS8962AF_SDCD_CONFIG1_OT_ELE BIT(7)\n#define FXLS8962AF_SDCD_CONFIG2 0x30\n#define FXLS8962AF_SDCD_CONFIG2_SDCD_EN BIT(7)\n#define FXLS8962AF_SC2_REF_UPDM_AC GENMASK(6, 5)\n#define FXLS8962AF_SDCD_OT_DBCNT 0x31\n#define FXLS8962AF_SDCD_WT_DBCNT 0x32\n#define FXLS8962AF_SDCD_LTHS_LSB 0x33\n#define FXLS8962AF_SDCD_UTHS_LSB 0x35\n\n#define FXLS8962AF_SELF_TEST_CONFIG1 0x37\n#define FXLS8962AF_SELF_TEST_CONFIG2 0x38\n\n#define FXLS8962AF_MAX_REG 0x38\n\n#define FXLS8962AF_DEVICE_ID 0x62\n#define FXLS8964AF_DEVICE_ID 0x84\n\n/* Raw temp channel offset /\n#define FXLS8962AF_TEMP_CENTER_VAL 25\n\n#define FXLS8962AF_AUTO_SUSPEND_DELAY_MS 2000\n\n#define FXLS8962AF_FIFO_LENGTH 32\n#define FXLS8962AF_SCALE_TABLE_LEN 4\n#define FXLS8962AF_SAMP_FREQ_TABLE_LEN 13\n\nstatic const int fxls8962af_scale_table[FXLS8962AF_SCALE_TABLE_LEN][2] = {\n{0, IIO_G_TO_M_S_2(980000)},\n{0, IIO_G_TO_M_S_2(1950000)},\n{0, IIO_G_TO_M_S_2(3910000)},\n{0, IIO_G_TO_M_S_2(7810000)},\n};\n\nstatic const int fxls8962af_samp_freq_table[FXLS8962AF_SAMP_FREQ_TABLE_LEN][2] = {\n{3200, 0}, {1600, 0}, {800, 0}, {400, 0}, {200, 0}, {100, 0},\n{50, 0}, {25, 0}, {12, 500000}, {6, 250000}, {3, 125000},\n{1, 563000}, {0, 781000},\n};\n\nstruct fxls8962af_chip_info {\nconst char name;\nconst struct iio_chan_spec channels;\nint num_channels;\nu8 chip_id;\n};\n\nstruct fxls8962af_data {\nstruct regmap regmap;\nconst struct fxls8962af_chip_info chip_info;\nstruct {\n__le16 channels[3];\ns64 ts __aligned(8);\n} scan;\nint64_t timestamp, old_timestamp; / Only used in hw fifo mode. /\nstruct iio_mount_matrix orientation;\nint irq;\nu8 watermark;\nu8 enable_event;\nu16 lower_thres;\nu16 upper_thres;\n};\n\nconst struct regmap_config fxls8962af_i2c_regmap_conf = {\n.reg_bits = 8,\n.val_bits = 8,\n.max_register = FXLS8962AF_MAX_REG,\n};\nEXPORT_SYMBOL_NS_GPL(fxls8962af_i2c_regmap_conf, IIO_FXLS8962AF);\n\nconst struct regmap_config fxls8962af_spi_regmap_conf = {\n.reg_bits = 8,\n.pad_bits = 8,\n.val_bits = 8,\n.max_register = FXLS8962AF_MAX_REG,\n};\nEXPORT_SYMBOL_NS_GPL(fxls8962af_spi_regmap_conf, IIO_FXLS8962AF);\n\nenum {\nfxls8962af_idx_x,\nfxls8962af_idx_y,\nfxls8962af_idx_z,\nfxls8962af_idx_ts,\n};\n\nenum fxls8962af_int_pin {\nFXLS8962AF_PIN_INT1,\nFXLS8962AF_PIN_INT2,\n};\n\nstatic int fxls8962af_power_on(struct fxls8962af_data data)\n{\nstruct device dev = regmap_get_device(data->regmap);\nint ret;\n\nret = pm_runtime_resume_and_get(dev);\nif (ret)\ndev_err(dev, \"failed to power on\n\");\n\nreturn ret;\n}\n\nstatic int fxls8962af_power_off(struct fxls8962af_data data)\n{\nstruct device dev = regmap_get_device(data->regmap);\nint ret;\n\npm_runtime_mark_last_busy(dev);\nret = pm_runtime_put_autosuspend(dev);\nif (ret)\ndev_err(dev, \"failed to power off\n\");\n\nreturn ret;\n}\n\nstatic int fxls8962af_standby(struct fxls8962af_data data)\n{\nreturn regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1,\nFXLS8962AF_SENS_CONFIG1_ACTIVE, 0);\n}\n\nstatic int fxls8962af_active(struct fxls8962af_data data)\n{\nreturn regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1,\nFXLS8962AF_SENS_CONFIG1_ACTIVE, 1);\n}\n\nstatic int fxls8962af_is_active(struct fxls8962af_data data)\n{\nunsigned int reg;\nint ret;\n\nret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, &reg);\nif (ret)\nreturn ret;\n\nreturn reg & FXLS8962AF_SENS_CONFIG1_ACTIVE;\n}\n\nstatic int fxls8962af_get_out(struct fxls8962af_data data,\nstruct iio_chan_spec const chan, int val)\n{\nstruct device dev = regmap_get_device(data->regmap);\n__le16 raw_val;\nint is_active;\nint ret;\n\nis_active = fxls8962af_is_active(data);\nif (!is_active) {\nret = fxls8962af_power_on(data);\nif (ret)\nreturn ret;\n}\n\nret = regmap_bulk_read(data->regmap, chan->address,\n&raw_val, sizeof(data->lower_thres));\n\nif (!is_active)\nfxls8962af_power_off(data);\n\nif (ret) {\ndev_err(dev, \"failed to get out reg 0x%lx\n\", chan->address);\nreturn ret;\n}\n\nval = sign_extend32(le16_to_cpu(raw_val),\nchan->scan_type.realbits - 1);\n\nreturn IIO_VAL_INT;\n}\n\nstatic int fxls8962af_read_avail(struct iio_dev indio_dev,\nstruct iio_chan_spec const chan,\nconst int vals, int type, int length,\nlong mask)\n{\nswitch (mask) {\ncase IIO_CHAN_INFO_SCALE:\ntype = IIO_VAL_INT_PLUS_NANO;\nvals = (int )fxls8962af_scale_table;\nlength = ARRAY_SIZE(fxls8962af_scale_table) 2;\nreturn IIO_AVAIL_LIST;\ncase IIO_CHAN_INFO_SAMP_FREQ:\ntype = IIO_VAL_INT_PLUS_MICRO;\nvals = (int )fxls8962af_samp_freq_table;\nlength = ARRAY_SIZE(fxls8962af_samp_freq_table) * 2;\nreturn IIO_AVAIL_LIST;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int fxls8962af_write_raw_get_fmt(struct iio_dev indio_dev,\nstruct iio_chan_spec const chan,\nlong mask)\n{\nswitch (mask) {\ncase IIO_CHAN_INFO_SCALE:\nreturn IIO_VAL_INT_PLUS_NANO;\ncase IIO_CHAN_INFO_SAMP_FREQ:\nreturn IIO_VAL_INT_PLUS_MICRO;\ndefault:\nreturn IIO_VAL_INT_PLUS_NANO;\n}\n}\n\nstatic int fxls8962af_update_config(struct fxls8962af_data data, u8 reg,\nu8 mask, u8 val)\n{\nint ret;\nint is_active;\n\nis_active = fxls8962af_is_active(data);\nif (is_active) {\nret = fxls8962af_standby(data);\nif (ret)\nreturn ret;\n}\n\nret = regmap_update_bits(data->regmap, reg, mask, val);\nif (ret)\nreturn ret;\n\nif (is_active) {\nret = fxls8962af_active(data);\nif (ret)\nreturn ret;\n}\n\nreturn 0;\n}\n\nstatic int fxls8962af_set_full_scale(struct fxls8962af_data data, u32 scale)\n{\nint i;\n\nfor (i = 0; i < ARRAY_SIZE(fxls8962af_scale_table); i++)\nif (scale == fxls8962af_scale_table[i][1])\nbreak;\n\nif (i == ARRAY_SIZE(fxls8962af_scale_table))\nreturn -EINVAL;\n\nreturn fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG1,\nFXLS8962AF_SC1_FSR_MASK,\nFXLS8962AF_SC1_FSR_PREP(i));\n}\n\nstatic unsigned int fxls8962af_read_full_scale(struct fxls8962af_data data,\nint val)\n{\nint ret;\nunsigned int reg;\nu8 range_idx;\n\nret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, &reg);\nif (ret)\nreturn ret;\n\nrange_idx = FXLS8962AF_SC1_FSR_GET(reg);\n\nval = fxls8962af_scale_table[range_idx][1];\n\nreturn IIO_VAL_INT_PLUS_NANO;\n}\n\nstatic int fxls8962af_set_samp_freq(struct fxls8962af_data data, u32 val,\nu32 val2)\n{\nint i;\n\nfor (i = 0; i < ARRAY_SIZE(fxls8962af_samp_freq_table); i++)\nif (val == fxls8962af_samp_freq_table[i][0] &&\nval2 == fxls8962af_samp_freq_table[i][1])\nbreak;\n\nif (i == ARRAY_SIZE(fxls8962af_samp_freq_table))\nreturn -EINVAL;\n\nreturn fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG3,\nFXLS8962AF_SC3_WAKE_ODR_MASK,\nFXLS8962AF_SC3_WAKE_ODR_PREP(i));\n}\n\nstatic unsigned int fxls8962af_read_samp_freq(struct fxls8962af_data data,\nint val, int val2)\n{\nint ret;\nunsigned int reg;\nu8 range_idx;\n\nret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG3, &reg);\nif (ret)\nreturn ret;\n\nrange_idx = FXLS8962AF_SC3_WAKE_ODR_GET(reg);\n\nval = fxls8962af_samp_freq_table[range_idx][0];\nval2 = fxls8962af_samp_freq_table[range_idx][1];\n\nreturn IIO_VAL_INT_PLUS_MICRO;\n}\n\nstatic int fxls8962af_read_raw(struct iio_dev indio_dev,\nstruct iio_chan_spec const chan,\nint val, int val2, long mask)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\n\nswitch (mask) {\ncase IIO_CHAN_INFO_RAW:\nswitch (chan->type) {\ncase IIO_TEMP:\ncase IIO_ACCEL:\nreturn fxls8962af_get_out(data, chan, val);\ndefault:\nreturn -EINVAL;\n}\ncase IIO_CHAN_INFO_OFFSET:\nif (chan->type != IIO_TEMP)\nreturn -EINVAL;\n\nval = FXLS8962AF_TEMP_CENTER_VAL;\nreturn IIO_VAL_INT;\ncase IIO_CHAN_INFO_SCALE:\nval = 0;\nreturn fxls8962af_read_full_scale(data, val2);\ncase IIO_CHAN_INFO_SAMP_FREQ:\nreturn fxls8962af_read_samp_freq(data, val, val2);\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int fxls8962af_write_raw(struct iio_dev indio_dev,\nstruct iio_chan_spec const chan,\nint val, int val2, long mask)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\nint ret;\n\nswitch (mask) {\ncase IIO_CHAN_INFO_SCALE:\nif (val != 0)\nreturn -EINVAL;\n\nret = iio_device_claim_direct_mode(indio_dev);\nif (ret)\nreturn ret;\n\nret = fxls8962af_set_full_scale(data, val2);\n\niio_device_release_direct_mode(indio_dev);\nreturn ret;\ncase IIO_CHAN_INFO_SAMP_FREQ:\nret = iio_device_claim_direct_mode(indio_dev);\nif (ret)\nreturn ret;\n\nret = fxls8962af_set_samp_freq(data, val, val2);\n\niio_device_release_direct_mode(indio_dev);\nreturn ret;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int fxls8962af_event_setup(struct fxls8962af_data data, int state)\n{\n/* Enable wakeup interrupt /\nint mask = FXLS8962AF_INT_EN_SDCD_OT_EN;\nint value = state ? mask : 0;\n\nreturn regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, mask, value);\n}\n\nstatic int fxls8962af_set_watermark(struct iio_dev indio_dev, unsigned val)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\n\nif (val > FXLS8962AF_FIFO_LENGTH)\nval = FXLS8962AF_FIFO_LENGTH;\n\ndata->watermark = val;\n\nreturn 0;\n}\n\nstatic int __fxls8962af_set_thresholds(struct fxls8962af_data data,\nconst struct iio_chan_spec chan,\nenum iio_event_direction dir,\nint val)\n{\nswitch (dir) {\ncase IIO_EV_DIR_FALLING:\ndata->lower_thres = val;\nreturn regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_LTHS_LSB,\n&data->lower_thres, sizeof(data->lower_thres));\ncase IIO_EV_DIR_RISING:\ndata->upper_thres = val;\nreturn regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_UTHS_LSB,\n&data->upper_thres, sizeof(data->upper_thres));\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int fxls8962af_read_event(struct iio_dev indio_dev,\nconst struct iio_chan_spec chan,\nenum iio_event_type type,\nenum iio_event_direction dir,\nenum iio_event_info info,\nint val, int val2)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\nint ret;\n\nif (type != IIO_EV_TYPE_THRESH)\nreturn -EINVAL;\n\nswitch (dir) {\ncase IIO_EV_DIR_FALLING:\nret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_LTHS_LSB,\n&data->lower_thres, sizeof(data->lower_thres));\nif (ret)\nreturn ret;\n\nval = sign_extend32(data->lower_thres, chan->scan_type.realbits - 1);\nreturn IIO_VAL_INT;\ncase IIO_EV_DIR_RISING:\nret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_UTHS_LSB,\n&data->upper_thres, sizeof(data->upper_thres));\nif (ret)\nreturn ret;\n\nval = sign_extend32(data->upper_thres, chan->scan_type.realbits - 1);\nreturn IIO_VAL_INT;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int fxls8962af_write_event(struct iio_dev indio_dev,\nconst struct iio_chan_spec chan,\nenum iio_event_type type,\nenum iio_event_direction dir,\nenum iio_event_info info,\nint val, int val2)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\nint ret, val_masked;\n\nif (type != IIO_EV_TYPE_THRESH)\nreturn -EINVAL;\n\nif (val < -2048 \|\| val > 2047)\nreturn -EINVAL;\n\nif (data->enable_event)\nreturn -EBUSY;\n\nval_masked = val & GENMASK(11, 0);\nif (fxls8962af_is_active(data)) {\nret = fxls8962af_standby(data);\nif (ret)\nreturn ret;\n\nret = __fxls8962af_set_thresholds(data, chan, dir, val_masked);\nif (ret)\nreturn ret;\n\nreturn fxls8962af_active(data);\n} else {\nreturn __fxls8962af_set_thresholds(data, chan, dir, val_masked);\n}\n}\n\nstatic int\nfxls8962af_read_event_config(struct iio_dev indio_dev,\nconst struct iio_chan_spec chan,\nenum iio_event_type type,\nenum iio_event_direction dir)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\n\nif (type != IIO_EV_TYPE_THRESH)\nreturn -EINVAL;\n\nswitch (chan->channel2) {\ncase IIO_MOD_X:\nreturn !!(FXLS8962AF_SDCD_CONFIG1_X_OT_EN & data->enable_event);\ncase IIO_MOD_Y:\nreturn !!(FXLS8962AF_SDCD_CONFIG1_Y_OT_EN & data->enable_event);\ncase IIO_MOD_Z:\nreturn !!(FXLS8962AF_SDCD_CONFIG1_Z_OT_EN & data->enable_event);\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int\nfxls8962af_write_event_config(struct iio_dev indio_dev,\nconst struct iio_chan_spec chan,\nenum iio_event_type type,\nenum iio_event_direction dir, int state)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\nu8 enable_event, enable_bits;\nint ret, value;\n\nif (type != IIO_EV_TYPE_THRESH)\nreturn -EINVAL;\n\nswitch (chan->channel2) {\ncase IIO_MOD_X:\nenable_bits = FXLS8962AF_SDCD_CONFIG1_X_OT_EN;\nbreak;\ncase IIO_MOD_Y:\nenable_bits = FXLS8962AF_SDCD_CONFIG1_Y_OT_EN;\nbreak;\ncase IIO_MOD_Z:\nenable_bits = FXLS8962AF_SDCD_CONFIG1_Z_OT_EN;\nbreak;\ndefault:\nreturn -EINVAL;\n}\n\nif (state)\nenable_event = data->enable_event \| enable_bits;\nelse\nenable_event = data->enable_event & ~enable_bits;\n\nif (data->enable_event == enable_event)\nreturn 0;\n\nret = fxls8962af_standby(data);\nif (ret)\nreturn ret;\n\n/ Enable events /\nvalue = enable_event \| FXLS8962AF_SDCD_CONFIG1_OT_ELE;\nret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG1, value);\nif (ret)\nreturn ret;\n\n/\n* Enable update of SDCD_REF_X/Y/Z values with the current decimated and\n* trimmed X/Y/Z acceleration input data. This allows for acceleration\n* slope detection with Data(n) to Data(n–1) always used as the input\n* to the window comparator.\n/\nvalue = enable_event ?\nFXLS8962AF_SDCD_CONFIG2_SDCD_EN \| FXLS8962AF_SC2_REF_UPDM_AC :\n0x00;\nret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG2, value);\nif (ret)\nreturn ret;\n\nret = fxls8962af_event_setup(data, state);\nif (ret)\nreturn ret;\n\ndata->enable_event = enable_event;\n\nif (data->enable_event) {\nfxls8962af_active(data);\nret = fxls8962af_power_on(data);\n} else {\nret = iio_device_claim_direct_mode(indio_dev);\nif (ret)\nreturn ret;\n\n/ Not in buffered mode so disable power /\nret = fxls8962af_power_off(data);\n\niio_device_release_direct_mode(indio_dev);\n}\n\nreturn ret;\n}\n\nstatic const struct iio_event_spec fxls8962af_event[] = {\n{\n.type = IIO_EV_TYPE_THRESH,\n.dir = IIO_EV_DIR_EITHER,\n.mask_separate = BIT(IIO_EV_INFO_ENABLE),\n},\n{\n.type = IIO_EV_TYPE_THRESH,\n.dir = IIO_EV_DIR_FALLING,\n.mask_separate = BIT(IIO_EV_INFO_VALUE),\n},\n{\n.type = IIO_EV_TYPE_THRESH,\n.dir = IIO_EV_DIR_RISING,\n.mask_separate = BIT(IIO_EV_INFO_VALUE),\n},\n};\n\n#define FXLS8962AF_CHANNEL(axis, reg, idx) { \\n.type = IIO_ACCEL, \\n.address = reg, \\n.modified = 1, \\n.channel2 = IIO_MOD_##axis, \\n.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \\n.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \| \\nBIT(IIO_CHAN_INFO_SAMP_FREQ), \\n.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) \| \\nBIT(IIO_CHAN_INFO_SAMP_FREQ), \\n.scan_index = idx, \\n.scan_type = { \\n.sign = 's', \\n.realbits = 12, \\n.storagebits = 16, \\n.endianness = IIO_LE, \\n}, \\n.event_spec = fxls8962af_event, \\n.num_event_specs = ARRAY_SIZE(fxls8962af_event), \\n}\n\n#define FXLS8962AF_TEMP_CHANNEL { \\n.type = IIO_TEMP, \\n.address = FXLS8962AF_TEMP_OUT, \\n.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \\nBIT(IIO_CHAN_INFO_OFFSET),\\n.scan_index = -1, \\n.scan_type = { \\n.realbits = 8, \\n.storagebits = 8, \\n}, \\n}\n\nstatic const struct iio_chan_spec fxls8962af_channels[] = {\nFXLS8962AF_CHANNEL(X, FXLS8962AF_OUT_X_LSB, fxls8962af_idx_x),\nFXLS8962AF_CHANNEL(Y, FXLS8962AF_OUT_Y_LSB, fxls8962af_idx_y),\nFXLS8962AF_CHANNEL(Z, FXLS8962AF_OUT_Z_LSB, fxls8962af_idx_z),\nIIO_CHAN_SOFT_TIMESTAMP(fxls8962af_idx_ts),\nFXLS8962AF_TEMP_CHANNEL,\n};\n\nstatic const struct fxls8962af_chip_info fxls_chip_info_table[] = {\n[fxls8962af] = {\n.chip_id = FXLS8962AF_DEVICE_ID,\n.name = \"fxls8962af\",\n.channels = fxls8962af_channels,\n.num_channels = ARRAY_SIZE(fxls8962af_channels),\n},\n[fxls8964af] = {\n.chip_id = FXLS8964AF_DEVICE_ID,\n.name = \"fxls8964af\",\n.channels = fxls8962af_channels,\n.num_channels = ARRAY_SIZE(fxls8962af_channels),\n},\n};\n\nstatic const struct iio_info fxls8962af_info = {\n.read_raw = &fxls8962af_read_raw,\n.write_raw = &fxls8962af_write_raw,\n.write_raw_get_fmt = fxls8962af_write_raw_get_fmt,\n.read_event_value = fxls8962af_read_event,\n.write_event_value = fxls8962af_write_event,\n.read_event_config = fxls8962af_read_event_config,\n.write_event_config = fxls8962af_write_event_config,\n.read_avail = fxls8962af_read_avail,\n.hwfifo_set_watermark = fxls8962af_set_watermark,\n};\n\nstatic int fxls8962af_reset(struct fxls8962af_data data)\n{\nstruct device dev = regmap_get_device(data->regmap);\nunsigned int reg;\nint ret;\n\nret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1,\nFXLS8962AF_SENS_CONFIG1_RST,\nFXLS8962AF_SENS_CONFIG1_RST);\nif (ret)\nreturn ret;\n\n/ TBOOT1, TBOOT2, specifies we have to wait between 1 - 17.7ms /\nret = regmap_read_poll_timeout(data->regmap, FXLS8962AF_INT_STATUS, reg,\n(reg & FXLS8962AF_INT_STATUS_SRC_BOOT),\n1000, 18000);\nif (ret == -ETIMEDOUT)\ndev_err(dev, \"reset timeout, int_status = 0x%x\n\", reg);\n\nreturn ret;\n}\n\nstatic int __fxls8962af_fifo_set_mode(struct fxls8962af_data data, bool onoff)\n{\nint ret;\n\n/* Enable watermark at max fifo size /\nret = regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG2,\nFXLS8962AF_BUF_CONFIG2_BUF_WMRK,\ndata->watermark);\nif (ret)\nreturn ret;\n\nreturn regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG1,\nFXLS8962AF_BC1_BUF_MODE_MASK,\nFXLS8962AF_BC1_BUF_MODE_PREP(onoff));\n}\n\nstatic int fxls8962af_buffer_preenable(struct iio_dev indio_dev)\n{\nreturn fxls8962af_power_on(iio_priv(indio_dev));\n}\n\nstatic int fxls8962af_buffer_postenable(struct iio_dev indio_dev)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\nint ret;\n\nfxls8962af_standby(data);\n\n/* Enable buffer interrupt /\nret = regmap_update_bits(data->regmap, FXLS8962AF_INT_EN,\nFXLS8962AF_INT_EN_BUF_EN,\nFXLS8962AF_INT_EN_BUF_EN);\nif (ret)\nreturn ret;\n\nret = __fxls8962af_fifo_set_mode(data, true);\n\nfxls8962af_active(data);\n\nreturn ret;\n}\n\nstatic int fxls8962af_buffer_predisable(struct iio_dev indio_dev)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\nint ret;\n\nfxls8962af_standby(data);\n\n/ Disable buffer interrupt /\nret = regmap_update_bits(data->regmap, FXLS8962AF_INT_EN,\nFXLS8962AF_INT_EN_BUF_EN, 0);\nif (ret)\nreturn ret;\n\nret = __fxls8962af_fifo_set_mode(data, false);\n\nif (data->enable_event)\nfxls8962af_active(data);\n\nreturn ret;\n}\n\nstatic int fxls8962af_buffer_postdisable(struct iio_dev indio_dev)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\n\nif (!data->enable_event)\nfxls8962af_power_off(data);\n\nreturn 0;\n}\n\nstatic const struct iio_buffer_setup_ops fxls8962af_buffer_ops = {\n.preenable = fxls8962af_buffer_preenable,\n.postenable = fxls8962af_buffer_postenable,\n.predisable = fxls8962af_buffer_predisable,\n.postdisable = fxls8962af_buffer_postdisable,\n};\n\nstatic int fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data data,\nu16 buffer, int samples,\nint sample_length)\n{\nint i, ret;\n\nfor (i = 0; i < samples; i++) {\nret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB,\n&buffer[i 3], sample_length);\nif (ret)\nreturn ret;\n}\n\nreturn 0;\n}\n\nstatic int fxls8962af_fifo_transfer(struct fxls8962af_data data,\nu16 buffer, int samples)\n{\nstruct device dev = regmap_get_device(data->regmap);\nint sample_length = 3 sizeof(buffer);\nint total_length = samples sample_length;\nint ret;\n\nif (i2c_verify_client(dev) &&\ndata->chip_info->chip_id == FXLS8962AF_DEVICE_ID)\n/\n Due to errata bug (only applicable on fxls8962af):\n* E3: FIFO burst read operation error using I2C interface\n* We have to avoid burst reads on I2C..\n/\nret = fxls8962af_i2c_raw_read_errata3(data, buffer, samples,\nsample_length);\nelse\nret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, buffer,\ntotal_length);\n\nif (ret)\ndev_err(dev, \"Error transferring data from fifo: %d\n\", ret);\n\nreturn ret;\n}\n\nstatic int fxls8962af_fifo_flush(struct iio_dev indio_dev)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\nstruct device dev = regmap_get_device(data->regmap);\nu16 buffer[FXLS8962AF_FIFO_LENGTH * 3];\nuint64_t sample_period;\nunsigned int reg;\nint64_t tstamp;\nint ret, i;\nu8 count;\n\nret = regmap_read(data->regmap, FXLS8962AF_BUF_STATUS, &reg);\nif (ret)\nreturn ret;\n\nif (reg & FXLS8962AF_BUF_STATUS_BUF_OVF) {\ndev_err(dev, \"Buffer overflow\");\nreturn -EOVERFLOW;\n}\n\ncount = reg & FXLS8962AF_BUF_STATUS_BUF_CNT;\nif (!count)\nreturn 0;\n\ndata->old_timestamp = data->timestamp;\ndata->timestamp = iio_get_time_ns(indio_dev);\n\n/\n Approximate timestamps for each of the sample based on the sampling,\n* frequency, timestamp for last sample and number of samples.\n/\nsample_period = (data->timestamp - data->old_timestamp);\ndo_div(sample_period, count);\ntstamp = data->timestamp - (count - 1) sample_period;\n\nret = fxls8962af_fifo_transfer(data, buffer, count);\nif (ret)\nreturn ret;\n\n/* Demux hw FIFO into kfifo. /\nfor (i = 0; i < count; i++) {\nint j, bit;\n\nj = 0;\nfor_each_set_bit(bit, indio_dev->active_scan_mask,\nindio_dev->masklength) {\nmemcpy(&data->scan.channels[j++], &buffer[i 3 + bit],\nsizeof(data->scan.channels[0]));\n}\n\niio_push_to_buffers_with_timestamp(indio_dev, &data->scan,\ntstamp);\n\ntstamp += sample_period;\n}\n\nreturn count;\n}\n\nstatic int fxls8962af_event_interrupt(struct iio_dev indio_dev)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\ns64 ts = iio_get_time_ns(indio_dev);\nunsigned int reg;\nu64 ev_code;\nint ret;\n\nret = regmap_read(data->regmap, FXLS8962AF_SDCD_INT_SRC1, &reg);\nif (ret)\nreturn ret;\n\nif (reg & FXLS8962AF_SDCD_INT_SRC1_X_OT) {\nev_code = reg & FXLS8962AF_SDCD_INT_SRC1_X_POL ?\nIIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;\niio_push_event(indio_dev,\nIIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,\nIIO_EV_TYPE_THRESH, ev_code), ts);\n}\n\nif (reg & FXLS8962AF_SDCD_INT_SRC1_Y_OT) {\nev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Y_POL ?\nIIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;\niio_push_event(indio_dev,\nIIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,\nIIO_EV_TYPE_THRESH, ev_code), ts);\n}\n\nif (reg & FXLS8962AF_SDCD_INT_SRC1_Z_OT) {\nev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Z_POL ?\nIIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;\niio_push_event(indio_dev,\nIIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,\nIIO_EV_TYPE_THRESH, ev_code), ts);\n}\n\nreturn 0;\n}\n\nstatic irqreturn_t fxls8962af_interrupt(int irq, void p)\n{\nstruct iio_dev indio_dev = p;\nstruct fxls8962af_data data = iio_priv(indio_dev);\nunsigned int reg;\nint ret;\n\nret = regmap_read(data->regmap, FXLS8962AF_INT_STATUS, &reg);\nif (ret)\nreturn IRQ_NONE;\n\nif (reg & FXLS8962AF_INT_STATUS_SRC_BUF) {\nret = fxls8962af_fifo_flush(indio_dev);\nif (ret < 0)\nreturn IRQ_NONE;\n\nreturn IRQ_HANDLED;\n}\n\nif (reg & FXLS8962AF_INT_STATUS_SRC_SDCD_OT) {\nret = fxls8962af_event_interrupt(indio_dev);\nif (ret < 0)\nreturn IRQ_NONE;\n\nreturn IRQ_HANDLED;\n}\n\nreturn IRQ_NONE;\n}\n\nstatic void fxls8962af_pm_disable(void dev_ptr)\n{\nstruct device dev = dev_ptr;\nstruct iio_dev indio_dev = dev_get_drvdata(dev);\n\npm_runtime_disable(dev);\npm_runtime_set_suspended(dev);\npm_runtime_put_noidle(dev);\n\nfxls8962af_standby(iio_priv(indio_dev));\n}\n\nstatic void fxls8962af_get_irq(struct device_node of_node,\nenum fxls8962af_int_pin pin)\n{\nint irq;\n\nirq = of_irq_get_byname(of_node, \"INT2\");\nif (irq > 0) {\npin = FXLS8962AF_PIN_INT2;\nreturn;\n}\n\npin = FXLS8962AF_PIN_INT1;\n}\n\nstatic int fxls8962af_irq_setup(struct iio_dev indio_dev, int irq)\n{\nstruct fxls8962af_data data = iio_priv(indio_dev);\nstruct device dev = regmap_get_device(data->regmap);\nunsigned long irq_type;\nbool irq_active_high;\nenum fxls8962af_int_pin int_pin;\nu8 int_pin_sel;\nint ret;\n\nfxls8962af_get_irq(dev->of_node, &int_pin);\nswitch (int_pin) {\ncase FXLS8962AF_PIN_INT1:\nint_pin_sel = FXLS8962AF_INT_PIN_SEL_INT1;\nbreak;\ncase FXLS8962AF_PIN_INT2:\nint_pin_sel = FXLS8962AF_INT_PIN_SEL_INT2;\nbreak;\ndefault:\ndev_err(dev, \"unsupported int pin selected\n\");\nreturn -EINVAL;\n}\n\nret = regmap_update_bits(data->regmap, FXLS8962AF_INT_PIN_SEL,\nFXLS8962AF_INT_PIN_SEL_MASK, int_pin_sel);\nif (ret)\nreturn ret;\n\nirq_type = irqd_get_trigger_type(irq_get_irq_data(irq));\n\nswitch (irq_type) {\ncase IRQF_TRIGGER_HIGH:\ncase IRQF_TRIGGER_RISING:\nirq_active_high = true;\nbreak;\ncase IRQF_TRIGGER_LOW:\ncase IRQF_TRIGGER_FALLING:\nirq_active_high = false;\nbreak;\ndefault:\ndev_info(dev, \"mode %lx unsupported\n\", irq_type);\nreturn -EINVAL;\n}\n\nret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4,\nFXLS8962AF_SC4_INT_POL_MASK,\nFXLS8962AF_SC4_INT_POL_PREP(irq_active_high));\nif (ret)\nreturn ret;\n\nif (device_property_read_bool(dev, \"drive-open-drain\")) {\nret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4,\nFXLS8962AF_SC4_INT_PP_OD_MASK,\nFXLS8962AF_SC4_INT_PP_OD_PREP(1));\nif (ret)\nreturn ret;\n\nirq_type \|= IRQF_SHARED;\n}\n\nreturn devm_request_threaded_irq(dev,\nirq,\nNULL, fxls8962af_interrupt,\nirq_type \| IRQF_ONESHOT,\nindio_dev->name, indio_dev);\n}\n\nint fxls8962af_core_probe(struct device dev, struct regmap regmap, int irq)\n{\nstruct fxls8962af_data data;\nstruct iio_dev indio_dev;\nunsigned int reg;\nint ret, i;\n\nindio_dev = devm_iio_device_alloc(dev, sizeof(data));\nif (!indio_dev)\nreturn -ENOMEM;\n\ndata = iio_priv(indio_dev);\ndev_set_drvdata(dev, indio_dev);\ndata->regmap = regmap;\ndata->irq = irq;\n\nret = iio_read_mount_matrix(dev, &data->orientation);\nif (ret)\nreturn ret;\n\nret = devm_regulator_get_enable(dev, \"vdd\");\nif (ret)\nreturn dev_err_probe(dev, ret,\n\"Failed to get vdd regulator\n\");\n\nret = regmap_read(data->regmap, FXLS8962AF_WHO_AM_I, &reg);\nif (ret)\nreturn ret;\n\nfor (i = 0; i < ARRAY_SIZE(fxls_chip_info_table); i++) {\nif (fxls_chip_info_table[i].chip_id == reg) {\ndata->chip_info = &fxls_chip_info_table[i];\nbreak;\n}\n}\nif (i == ARRAY_SIZE(fxls_chip_info_table)) {\ndev_err(dev, \"failed to match device in table\n\");\nreturn -ENXIO;\n}\n\nindio_dev->channels = data->chip_info->channels;\nindio_dev->num_channels = data->chip_info->num_channels;\nindio_dev->name = data->chip_info->name;\nindio_dev->info = &fxls8962af_info;\nindio_dev->modes = INDIO_DIRECT_MODE;\n\nret = fxls8962af_reset(data);\nif (ret)\nreturn ret;\n\nif (irq) {\nret = fxls8962af_irq_setup(indio_dev, irq);\nif (ret)\nreturn ret;\n\nret = devm_iio_kfifo_buffer_setup(dev, indio_dev,\n&fxls8962af_buffer_ops);\nif (ret)\nreturn ret;\n}\n\nret = pm_runtime_set_active(dev);\nif (ret)\nreturn ret;\n\npm_runtime_enable(dev);\npm_runtime_set_autosuspend_delay(dev, FXLS8962AF_AUTO_SUSPEND_DELAY_MS);\npm_runtime_use_autosuspend(dev);\n\nret = devm_add_action_or_reset(dev, fxls8962af_pm_disable, dev);\nif (ret)\nreturn ret;\n\nif (device_property_read_bool(dev, \"wakeup-source\"))\ndevice_init_wakeup(dev, true);\n\nreturn devm_iio_device_register(dev, indio_dev);\n}\nEXPORT_SYMBOL_NS_GPL(fxls8962af_core_probe, IIO_FXLS8962AF);\n\nstatic int fxls8962af_runtime_suspend(struct device dev)\n{\nstruct fxls8962af_data data = iio_priv(dev_get_drvdata(dev));\nint ret;\n\nret = fxls8962af_standby(data);\nif (ret) {\ndev_err(dev, \"powering off device failed\n\");\nreturn ret;\n}\n\nreturn 0;\n}\n\nstatic int fxls8962af_runtime_resume(struct device dev)\n{\nstruct fxls8962af_data data = iio_priv(dev_get_drvdata(dev));\n\nreturn fxls8962af_active(data);\n}\n\nstatic int fxls8962af_suspend(struct device dev)\n{\nstruct iio_dev indio_dev = dev_get_drvdata(dev);\nstruct fxls8962af_data data = iio_priv(indio_dev);\n\nif (device_may_wakeup(dev) && data->enable_event) {\nenable_irq_wake(data->irq);\n\n/\n* Disable buffer, as the buffer is so small the device will wake\n* almost immediately.\n/\nif (iio_buffer_enabled(indio_dev))\nfxls8962af_buffer_predisable(indio_dev);\n} else {\nfxls8962af_runtime_suspend(dev);\n}\n\nreturn 0;\n}\n\nstatic int fxls8962af_resume(struct device dev)\n{\nstruct iio_dev indio_dev = dev_get_drvdata(dev);\nstruct fxls8962af_data data = iio_priv(indio_dev);\n\nif (device_may_wakeup(dev) && data->enable_event) {\ndisable_irq_wake(data->irq);\n\nif (iio_buffer_enabled(indio_dev))\nfxls8962af_buffer_postenable(indio_dev);\n} else {\nfxls8962af_runtime_resume(dev);\n}\n\nreturn 0;\n}\n\nEXPORT_NS_GPL_DEV_PM_OPS(fxls8962af_pm_ops, IIO_FXLS8962AF) = {\nSYSTEM_SLEEP_PM_OPS(fxls8962af_suspend, fxls8962af_resume)\nRUNTIME_PM_OPS(fxls8962af_runtime_suspend, fxls8962af_runtime_resume, NULL)\n};\n\nMODULE_AUTHOR(\"Sean Nyekjaer <sean@geanix.com>\");\nMODULE_DESCRIPTION(\"NXP FXLS8962AF/FXLS8964AF accelerometer driver\");\nMODULE_LICENSE(\"GPL v2\");"}
	{"text":"#include <linux/bitfield.h>\n#include <linux/bitops.h>\n#include <linux/device.h>\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/mutex.h>\n#include <linux/regmap.h>\n#include <linux/regulator/consumer.h>\n#include <linux/slab.h>\n\n#include <asm/unaligned.h>\n\n#include <linux/iio/iio.h>\n#include <linux/iio/buffer.h>\n#include <linux/iio/events.h>\n#include <linux/iio/sysfs.h>\n#include <linux/iio/trigger.h>\n#include <linux/iio/trigger_consumer.h>\n#include <linux/iio/triggered_buffer.h>\n\n#include \"bma400.h\"\n\n/\n The G-range selection may be one of 2g, 4g, 8, or 16g. The scale may\n* be selected with the acc_range bits of the ACC_CONFIG1 register.\n* NB: This buffer is populated in the device init.\n/\nstatic int bma400_scales[8];\n\n/\n* See the ACC_CONFIG1 section of the datasheet.\n* NB: This buffer is populated in the device init.\n/\nstatic int bma400_sample_freqs[14];\n\nstatic const int bma400_osr_range[] = { 0, 1, 3 };\n\nstatic int tap_reset_timeout[BMA400_TAP_TIM_LIST_LEN] = {\n300000,\n400000,\n500000,\n600000\n};\n\nstatic int tap_max2min_time[BMA400_TAP_TIM_LIST_LEN] = {\n30000,\n45000,\n60000,\n90000\n};\n\nstatic int double_tap2_min_delay[BMA400_TAP_TIM_LIST_LEN] = {\n20000,\n40000,\n60000,\n80000\n};\n\n/ See the ACC_CONFIG0 section of the datasheet /\nenum bma400_power_mode {\nPOWER_MODE_SLEEP = 0x00,\nPOWER_MODE_LOW = 0x01,\nPOWER_MODE_NORMAL = 0x02,\nPOWER_MODE_INVALID = 0x03,\n};\n\nenum bma400_scan {\nBMA400_ACCL_X,\nBMA400_ACCL_Y,\nBMA400_ACCL_Z,\nBMA400_TEMP,\n};\n\nstruct bma400_sample_freq {\nint hz;\nint uhz;\n};\n\nenum bma400_activity {\nBMA400_STILL,\nBMA400_WALKING,\nBMA400_RUNNING,\n};\n\nstruct bma400_data {\nstruct device dev;\nstruct regmap regmap;\nstruct mutex mutex; / data register lock /\nstruct iio_mount_matrix orientation;\nenum bma400_power_mode power_mode;\nstruct bma400_sample_freq sample_freq;\nint oversampling_ratio;\nint scale;\nstruct iio_trigger trig;\nint steps_enabled;\nbool step_event_en;\nbool activity_event_en;\nunsigned int generic_event_en;\nunsigned int tap_event_en_bitmask;\n/* Correct time stamp alignment /\nstruct {\n__le16 buff[3];\nu8 temperature;\ns64 ts __aligned(8);\n} buffer __aligned(IIO_DMA_MINALIGN);\n__le16 status;\n__be16 duration;\n};\n\nstatic bool bma400_is_writable_reg(struct device dev, unsigned int reg)\n{\nswitch (reg) {\ncase BMA400_CHIP_ID_REG:\ncase BMA400_ERR_REG:\ncase BMA400_STATUS_REG:\ncase BMA400_X_AXIS_LSB_REG:\ncase BMA400_X_AXIS_MSB_REG:\ncase BMA400_Y_AXIS_LSB_REG:\ncase BMA400_Y_AXIS_MSB_REG:\ncase BMA400_Z_AXIS_LSB_REG:\ncase BMA400_Z_AXIS_MSB_REG:\ncase BMA400_SENSOR_TIME0:\ncase BMA400_SENSOR_TIME1:\ncase BMA400_SENSOR_TIME2:\ncase BMA400_EVENT_REG:\ncase BMA400_INT_STAT0_REG:\ncase BMA400_INT_STAT1_REG:\ncase BMA400_INT_STAT2_REG:\ncase BMA400_TEMP_DATA_REG:\ncase BMA400_FIFO_LENGTH0_REG:\ncase BMA400_FIFO_LENGTH1_REG:\ncase BMA400_FIFO_DATA_REG:\ncase BMA400_STEP_CNT0_REG:\ncase BMA400_STEP_CNT1_REG:\ncase BMA400_STEP_CNT3_REG:\ncase BMA400_STEP_STAT_REG:\nreturn false;\ndefault:\nreturn true;\n}\n}\n\nstatic bool bma400_is_volatile_reg(struct device dev, unsigned int reg)\n{\nswitch (reg) {\ncase BMA400_ERR_REG:\ncase BMA400_STATUS_REG:\ncase BMA400_X_AXIS_LSB_REG:\ncase BMA400_X_AXIS_MSB_REG:\ncase BMA400_Y_AXIS_LSB_REG:\ncase BMA400_Y_AXIS_MSB_REG:\ncase BMA400_Z_AXIS_LSB_REG:\ncase BMA400_Z_AXIS_MSB_REG:\ncase BMA400_SENSOR_TIME0:\ncase BMA400_SENSOR_TIME1:\ncase BMA400_SENSOR_TIME2:\ncase BMA400_EVENT_REG:\ncase BMA400_INT_STAT0_REG:\ncase BMA400_INT_STAT1_REG:\ncase BMA400_INT_STAT2_REG:\ncase BMA400_TEMP_DATA_REG:\ncase BMA400_FIFO_LENGTH0_REG:\ncase BMA400_FIFO_LENGTH1_REG:\ncase BMA400_FIFO_DATA_REG:\ncase BMA400_STEP_CNT0_REG:\ncase BMA400_STEP_CNT1_REG:\ncase BMA400_STEP_CNT3_REG:\ncase BMA400_STEP_STAT_REG:\nreturn true;\ndefault:\nreturn false;\n}\n}\n\nconst struct regmap_config bma400_regmap_config = {\n.reg_bits = 8,\n.val_bits = 8,\n.max_register = BMA400_CMD_REG,\n.cache_type = REGCACHE_RBTREE,\n.writeable_reg = bma400_is_writable_reg,\n.volatile_reg = bma400_is_volatile_reg,\n};\nEXPORT_SYMBOL_NS(bma400_regmap_config, IIO_BMA400);\n\nstatic const struct iio_mount_matrix \nbma400_accel_get_mount_matrix(const struct iio_dev indio_dev,\nconst struct iio_chan_spec chan)\n{\nstruct bma400_data data = iio_priv(indio_dev);\n\nreturn &data->orientation;\n}\n\nstatic const struct iio_chan_spec_ext_info bma400_ext_info[] = {\nIIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma400_accel_get_mount_matrix),\n{ }\n};\n\nstatic const struct iio_event_spec bma400_step_detect_event = {\n.type = IIO_EV_TYPE_CHANGE,\n.dir = IIO_EV_DIR_NONE,\n.mask_separate = BIT(IIO_EV_INFO_ENABLE),\n};\n\nstatic const struct iio_event_spec bma400_activity_event = {\n.type = IIO_EV_TYPE_CHANGE,\n.dir = IIO_EV_DIR_NONE,\n.mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE),\n};\n\nstatic const struct iio_event_spec bma400_accel_event[] = {\n{\n.type = IIO_EV_TYPE_MAG,\n.dir = IIO_EV_DIR_FALLING,\n.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) \|\nBIT(IIO_EV_INFO_PERIOD) \|\nBIT(IIO_EV_INFO_HYSTERESIS) \|\nBIT(IIO_EV_INFO_ENABLE),\n},\n{\n.type = IIO_EV_TYPE_MAG,\n.dir = IIO_EV_DIR_RISING,\n.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) \|\nBIT(IIO_EV_INFO_PERIOD) \|\nBIT(IIO_EV_INFO_HYSTERESIS) \|\nBIT(IIO_EV_INFO_ENABLE),\n},\n{\n.type = IIO_EV_TYPE_GESTURE,\n.dir = IIO_EV_DIR_SINGLETAP,\n.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) \|\nBIT(IIO_EV_INFO_ENABLE) \|\nBIT(IIO_EV_INFO_RESET_TIMEOUT),\n},\n{\n.type = IIO_EV_TYPE_GESTURE,\n.dir = IIO_EV_DIR_DOUBLETAP,\n.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) \|\nBIT(IIO_EV_INFO_ENABLE) \|\nBIT(IIO_EV_INFO_RESET_TIMEOUT) \|\nBIT(IIO_EV_INFO_TAP2_MIN_DELAY),\n},\n};\n\nstatic int usec_to_tapreg_raw(int usec, const int time_list)\n{\nint index;\n\nfor (index = 0; index < BMA400_TAP_TIM_LIST_LEN; index++) {\nif (usec == time_list[index])\nreturn index;\n}\nreturn -EINVAL;\n}\n\nstatic ssize_t in_accel_gesture_tap_maxtomin_time_show(struct device dev,\nstruct device_attribute attr,\nchar buf)\n{\nstruct iio_dev indio_dev = dev_to_iio_dev(dev);\nstruct bma400_data data = iio_priv(indio_dev);\nint ret, reg_val, raw, vals[2];\n\nret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, &reg_val);\nif (ret)\nreturn ret;\n\nraw = FIELD_GET(BMA400_TAP_TICSTH_MSK, reg_val);\nvals[0] = 0;\nvals[1] = tap_max2min_time[raw];\n\nreturn iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);\n}\n\nstatic ssize_t in_accel_gesture_tap_maxtomin_time_store(struct device dev,\nstruct device_attribute attr,\nconst char buf, size_t len)\n{\nstruct iio_dev indio_dev = dev_to_iio_dev(dev);\nstruct bma400_data data = iio_priv(indio_dev);\nint ret, val_int, val_fract, raw;\n\nret = iio_str_to_fixpoint(buf, 100000, &val_int, &val_fract);\nif (ret)\nreturn ret;\n\nraw = usec_to_tapreg_raw(val_fract, tap_max2min_time);\nif (raw < 0)\nreturn -EINVAL;\n\nret = regmap_update_bits(data->regmap, BMA400_TAP_CONFIG1,\nBMA400_TAP_TICSTH_MSK,\nFIELD_PREP(BMA400_TAP_TICSTH_MSK, raw));\nif (ret)\nreturn ret;\n\nreturn len;\n}\n\nstatic IIO_DEVICE_ATTR_RW(in_accel_gesture_tap_maxtomin_time, 0);\n\n/\n Tap interrupts works with 200 Hz input data rate and the time based tap\n* controls are in the terms of data samples so the below calculation is\n* used to convert the configuration values into seconds.\n* e.g.:\n* 60 data samples * 0.005 ms = 0.3 seconds.\n* 80 data samples * 0.005 ms = 0.4 seconds.\n/\n\n/ quiet configuration values in seconds /\nstatic IIO_CONST_ATTR(in_accel_gesture_tap_reset_timeout_available,\n\"0.3 0.4 0.5 0.6\");\n\n/ tics_th configuration values in seconds /\nstatic IIO_CONST_ATTR(in_accel_gesture_tap_maxtomin_time_available,\n\"0.03 0.045 0.06 0.09\");\n\n/ quiet_dt configuration values in seconds /\nstatic IIO_CONST_ATTR(in_accel_gesture_doubletap_tap2_min_delay_available,\n\"0.02 0.04 0.06 0.08\");\n\n/ List of sensitivity values available to configure tap interrupts /\nstatic IIO_CONST_ATTR(in_accel_gesture_tap_value_available, \"0 1 2 3 4 5 6 7\");\n\nstatic struct attribute bma400_event_attributes[] = {\n&iio_const_attr_in_accel_gesture_tap_value_available.dev_attr.attr,\n&iio_const_attr_in_accel_gesture_tap_reset_timeout_available.dev_attr.attr,\n&iio_const_attr_in_accel_gesture_tap_maxtomin_time_available.dev_attr.attr,\n&iio_const_attr_in_accel_gesture_doubletap_tap2_min_delay_available.dev_attr.attr,\n&iio_dev_attr_in_accel_gesture_tap_maxtomin_time.dev_attr.attr,\nNULL\n};\n\nstatic const struct attribute_group bma400_event_attribute_group = {\n.attrs = bma400_event_attributes,\n};\n\n#define BMA400_ACC_CHANNEL(_index, _axis) { \\n.type = IIO_ACCEL, \\n.modified = 1, \\n.channel2 = IIO_MOD_##_axis, \\n.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \\n.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) \| \\nBIT(IIO_CHAN_INFO_SCALE) \| \\nBIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \\n.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) \| \\nBIT(IIO_CHAN_INFO_SCALE) \| \\nBIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \\n.ext_info = bma400_ext_info, \\n.scan_index = _index, \\n.scan_type = { \\n.sign = 's', \\n.realbits = 12, \\n.storagebits = 16, \\n.endianness = IIO_LE, \\n}, \\n.event_spec = bma400_accel_event, \\n.num_event_specs = ARRAY_SIZE(bma400_accel_event) \\n}\n\n#define BMA400_ACTIVITY_CHANNEL(_chan2) { \\n.type = IIO_ACTIVITY, \\n.modified = 1, \\n.channel2 = _chan2, \\n.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \\n.scan_index = -1, /* No buffer support / \\n.event_spec = &bma400_activity_event, \\n.num_event_specs = 1, \\n}\n\nstatic const struct iio_chan_spec bma400_channels[] = {\nBMA400_ACC_CHANNEL(0, X),\nBMA400_ACC_CHANNEL(1, Y),\nBMA400_ACC_CHANNEL(2, Z),\n{\n.type = IIO_TEMP,\n.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),\n.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ),\n.scan_index = 3,\n.scan_type = {\n.sign = 's',\n.realbits = 8,\n.storagebits = 8,\n.endianness = IIO_LE,\n},\n},\n{\n.type = IIO_STEPS,\n.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) \|\nBIT(IIO_CHAN_INFO_ENABLE),\n.scan_index = -1, / No buffer support /\n.event_spec = &bma400_step_detect_event,\n.num_event_specs = 1,\n},\nBMA400_ACTIVITY_CHANNEL(IIO_MOD_STILL),\nBMA400_ACTIVITY_CHANNEL(IIO_MOD_WALKING),\nBMA400_ACTIVITY_CHANNEL(IIO_MOD_RUNNING),\nIIO_CHAN_SOFT_TIMESTAMP(4),\n};\n\nstatic int bma400_get_temp_reg(struct bma400_data data, int val, int val2)\n{\nunsigned int raw_temp;\nint host_temp;\nint ret;\n\nif (data->power_mode == POWER_MODE_SLEEP)\nreturn -EBUSY;\n\nret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &raw_temp);\nif (ret)\nreturn ret;\n\nhost_temp = sign_extend32(raw_temp, 7);\n/\n The formula for the TEMP_DATA register in the datasheet\n* is: x * 0.5 + 23\n/\nval = (host_temp >> 1) + 23;\nval2 = (host_temp & 0x1) 500000;\nreturn IIO_VAL_INT_PLUS_MICRO;\n}\n\nstatic int bma400_get_accel_reg(struct bma400_data data,\nconst struct iio_chan_spec chan,\nint val)\n{\n__le16 raw_accel;\nint lsb_reg;\nint ret;\n\nif (data->power_mode == POWER_MODE_SLEEP)\nreturn -EBUSY;\n\nswitch (chan->channel2) {\ncase IIO_MOD_X:\nlsb_reg = BMA400_X_AXIS_LSB_REG;\nbreak;\ncase IIO_MOD_Y:\nlsb_reg = BMA400_Y_AXIS_LSB_REG;\nbreak;\ncase IIO_MOD_Z:\nlsb_reg = BMA400_Z_AXIS_LSB_REG;\nbreak;\ndefault:\ndev_err(data->dev, \"invalid axis channel modifier\n\");\nreturn -EINVAL;\n}\n\n/ bulk read two registers, with the base being the LSB register /\nret = regmap_bulk_read(data->regmap, lsb_reg, &raw_accel,\nsizeof(raw_accel));\nif (ret)\nreturn ret;\n\nval = sign_extend32(le16_to_cpu(raw_accel), 11);\nreturn IIO_VAL_INT;\n}\n\nstatic void bma400_output_data_rate_from_raw(int raw, unsigned int val,\nunsigned int val2)\n{\nval = BMA400_ACC_ODR_MAX_HZ >> (BMA400_ACC_ODR_MAX_RAW - raw);\nif (raw > BMA400_ACC_ODR_MIN_RAW)\nval2 = 0;\nelse\nval2 = 500000;\n}\n\nstatic int bma400_get_accel_output_data_rate(struct bma400_data data)\n{\nunsigned int val;\nunsigned int odr;\nint ret;\n\nswitch (data->power_mode) {\ncase POWER_MODE_LOW:\n/\n Runs at a fixed rate in low-power mode. See section 4.3\n* in the datasheet.\n/\nbma400_output_data_rate_from_raw(BMA400_ACC_ODR_LP_RAW,\n&data->sample_freq.hz,\n&data->sample_freq.uhz);\nreturn 0;\ncase POWER_MODE_NORMAL:\n/\n* In normal mode the ODR can be found in the ACC_CONFIG1\n* register.\n/\nret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);\nif (ret)\ngoto error;\n\nodr = val & BMA400_ACC_ODR_MASK;\nif (odr < BMA400_ACC_ODR_MIN_RAW \|\|\nodr > BMA400_ACC_ODR_MAX_RAW) {\nret = -EINVAL;\ngoto error;\n}\n\nbma400_output_data_rate_from_raw(odr, &data->sample_freq.hz,\n&data->sample_freq.uhz);\nreturn 0;\ncase POWER_MODE_SLEEP:\ndata->sample_freq.hz = 0;\ndata->sample_freq.uhz = 0;\nreturn 0;\ndefault:\nret = 0;\ngoto error;\n}\nerror:\ndata->sample_freq.hz = -1;\ndata->sample_freq.uhz = -1;\nreturn ret;\n}\n\nstatic int bma400_set_accel_output_data_rate(struct bma400_data data,\nint hz, int uhz)\n{\nunsigned int idx;\nunsigned int odr;\nunsigned int val;\nint ret;\n\nif (hz >= BMA400_ACC_ODR_MIN_WHOLE_HZ) {\nif (uhz \|\| hz > BMA400_ACC_ODR_MAX_HZ)\nreturn -EINVAL;\n\n/* Note this works because MIN_WHOLE_HZ is odd /\nidx = __ffs(hz);\n\nif (hz >> idx != BMA400_ACC_ODR_MIN_WHOLE_HZ)\nreturn -EINVAL;\n\nidx += BMA400_ACC_ODR_MIN_RAW + 1;\n} else if (hz == BMA400_ACC_ODR_MIN_HZ && uhz == 500000) {\nidx = BMA400_ACC_ODR_MIN_RAW;\n} else {\nreturn -EINVAL;\n}\n\nret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);\nif (ret)\nreturn ret;\n\n/ preserve the range and normal mode osr /\nodr = (~BMA400_ACC_ODR_MASK & val) \| idx;\n\nret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, odr);\nif (ret)\nreturn ret;\n\nbma400_output_data_rate_from_raw(idx, &data->sample_freq.hz,\n&data->sample_freq.uhz);\nreturn 0;\n}\n\nstatic int bma400_get_accel_oversampling_ratio(struct bma400_data data)\n{\nunsigned int val;\nunsigned int osr;\nint ret;\n\n/\n The oversampling ratio is stored in a different register\n* based on the power-mode. In normal mode the OSR is stored\n* in ACC_CONFIG1. In low-power mode it is stored in\n* ACC_CONFIG0.\n/\nswitch (data->power_mode) {\ncase POWER_MODE_LOW:\nret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val);\nif (ret) {\ndata->oversampling_ratio = -1;\nreturn ret;\n}\n\nosr = (val & BMA400_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT;\n\ndata->oversampling_ratio = osr;\nreturn 0;\ncase POWER_MODE_NORMAL:\nret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);\nif (ret) {\ndata->oversampling_ratio = -1;\nreturn ret;\n}\n\nosr = (val & BMA400_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT;\n\ndata->oversampling_ratio = osr;\nreturn 0;\ncase POWER_MODE_SLEEP:\ndata->oversampling_ratio = 0;\nreturn 0;\ndefault:\ndata->oversampling_ratio = -1;\nreturn -EINVAL;\n}\n}\n\nstatic int bma400_set_accel_oversampling_ratio(struct bma400_data data,\nint val)\n{\nunsigned int acc_config;\nint ret;\n\nif (val & ~BMA400_TWO_BITS_MASK)\nreturn -EINVAL;\n\n/\n The oversampling ratio is stored in a different register\n* based on the power-mode.\n/\nswitch (data->power_mode) {\ncase POWER_MODE_LOW:\nret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG,\n&acc_config);\nif (ret)\nreturn ret;\n\nret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG,\n(acc_config & ~BMA400_LP_OSR_MASK) \|\n(val << BMA400_LP_OSR_SHIFT));\nif (ret) {\ndev_err(data->dev, \"Failed to write out OSR\n\");\nreturn ret;\n}\n\ndata->oversampling_ratio = val;\nreturn 0;\ncase POWER_MODE_NORMAL:\nret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG,\n&acc_config);\nif (ret)\nreturn ret;\n\nret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG,\n(acc_config & ~BMA400_NP_OSR_MASK) \|\n(val << BMA400_NP_OSR_SHIFT));\nif (ret) {\ndev_err(data->dev, \"Failed to write out OSR\n\");\nreturn ret;\n}\n\ndata->oversampling_ratio = val;\nreturn 0;\ndefault:\nreturn -EINVAL;\n}\nreturn ret;\n}\n\nstatic int bma400_accel_scale_to_raw(struct bma400_data data,\nunsigned int val)\n{\nint raw;\n\nif (val == 0)\nreturn -EINVAL;\n\n/* Note this works because BMA400_SCALE_MIN is odd /\nraw = __ffs(val);\n\nif (val >> raw != BMA400_SCALE_MIN)\nreturn -EINVAL;\n\nreturn raw;\n}\n\nstatic int bma400_get_accel_scale(struct bma400_data data)\n{\nunsigned int raw_scale;\nunsigned int val;\nint ret;\n\nret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);\nif (ret)\nreturn ret;\n\nraw_scale = (val & BMA400_ACC_SCALE_MASK) >> BMA400_SCALE_SHIFT;\nif (raw_scale > BMA400_TWO_BITS_MASK)\nreturn -EINVAL;\n\ndata->scale = BMA400_SCALE_MIN << raw_scale;\n\nreturn 0;\n}\n\nstatic int bma400_set_accel_scale(struct bma400_data data, unsigned int val)\n{\nunsigned int acc_config;\nint raw;\nint ret;\n\nret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &acc_config);\nif (ret)\nreturn ret;\n\nraw = bma400_accel_scale_to_raw(data, val);\nif (raw < 0)\nreturn raw;\n\nret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG,\n(acc_config & ~BMA400_ACC_SCALE_MASK) \|\n(raw << BMA400_SCALE_SHIFT));\nif (ret)\nreturn ret;\n\ndata->scale = val;\nreturn 0;\n}\n\nstatic int bma400_get_power_mode(struct bma400_data data)\n{\nunsigned int val;\nint ret;\n\nret = regmap_read(data->regmap, BMA400_STATUS_REG, &val);\nif (ret) {\ndev_err(data->dev, \"Failed to read status register\n\");\nreturn ret;\n}\n\ndata->power_mode = (val >> 1) & BMA400_TWO_BITS_MASK;\nreturn 0;\n}\n\nstatic int bma400_set_power_mode(struct bma400_data data,\nenum bma400_power_mode mode)\n{\nunsigned int val;\nint ret;\n\nret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val);\nif (ret)\nreturn ret;\n\nif (data->power_mode == mode)\nreturn 0;\n\nif (mode == POWER_MODE_INVALID)\nreturn -EINVAL;\n\n/ Preserve the low-power oversample ratio etc /\nret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG,\nmode \| (val & ~BMA400_TWO_BITS_MASK));\nif (ret) {\ndev_err(data->dev, \"Failed to write to power-mode\n\");\nreturn ret;\n}\n\ndata->power_mode = mode;\n\n/\n* Update our cached osr and odr based on the new\n* power-mode.\n/\nbma400_get_accel_output_data_rate(data);\nbma400_get_accel_oversampling_ratio(data);\nreturn 0;\n}\n\nstatic int bma400_enable_steps(struct bma400_data data, int val)\n{\nint ret;\n\nif (data->steps_enabled == val)\nreturn 0;\n\nret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG,\nBMA400_STEP_INT_MSK,\nFIELD_PREP(BMA400_STEP_INT_MSK, val ? 1 : 0));\nif (ret)\nreturn ret;\ndata->steps_enabled = val;\nreturn ret;\n}\n\nstatic int bma400_get_steps_reg(struct bma400_data data, int val)\n{\nu8 steps_raw;\nint ret;\n\nsteps_raw = kmalloc(BMA400_STEP_RAW_LEN, GFP_KERNEL);\nif (!steps_raw)\nreturn -ENOMEM;\n\nret = regmap_bulk_read(data->regmap, BMA400_STEP_CNT0_REG,\nsteps_raw, BMA400_STEP_RAW_LEN);\nif (ret) {\nkfree(steps_raw);\nreturn ret;\n}\nval = get_unaligned_le24(steps_raw);\nkfree(steps_raw);\nreturn IIO_VAL_INT;\n}\n\nstatic void bma400_init_tables(void)\n{\nint raw;\nint i;\n\nfor (i = 0; i + 1 < ARRAY_SIZE(bma400_sample_freqs); i += 2) {\nraw = (i / 2) + 5;\nbma400_output_data_rate_from_raw(raw, &bma400_sample_freqs[i],\n&bma400_sample_freqs[i + 1]);\n}\n\nfor (i = 0; i + 1 < ARRAY_SIZE(bma400_scales); i += 2) {\nraw = i / 2;\nbma400_scales[i] = 0;\nbma400_scales[i + 1] = BMA400_SCALE_MIN << raw;\n}\n}\n\nstatic void bma400_power_disable(void data_ptr)\n{\nstruct bma400_data data = data_ptr;\nint ret;\n\nmutex_lock(&data->mutex);\nret = bma400_set_power_mode(data, POWER_MODE_SLEEP);\nmutex_unlock(&data->mutex);\nif (ret)\ndev_warn(data->dev, \"Failed to put device into sleep mode (%pe)\n\",\nERR_PTR(ret));\n}\n\nstatic enum iio_modifier bma400_act_to_mod(enum bma400_activity activity)\n{\nswitch (activity) {\ncase BMA400_STILL:\nreturn IIO_MOD_STILL;\ncase BMA400_WALKING:\nreturn IIO_MOD_WALKING;\ncase BMA400_RUNNING:\nreturn IIO_MOD_RUNNING;\ndefault:\nreturn IIO_NO_MOD;\n}\n}\n\nstatic int bma400_init(struct bma400_data data)\n{\nstatic const char const regulator_names[] = { \"vdd\", \"vddio\" };\nunsigned int val;\nint ret;\n\nret = devm_regulator_bulk_get_enable(data->dev,\nARRAY_SIZE(regulator_names),\nregulator_names);\nif (ret)\nreturn dev_err_probe(data->dev, ret, \"Failed to get regulators\n\");\n\n/* Try to read chip_id register. It must return 0x90. /\nret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val);\nif (ret) {\ndev_err(data->dev, \"Failed to read chip id register\n\");\nreturn ret;\n}\n\nif (val != BMA400_ID_REG_VAL) {\ndev_err(data->dev, \"Chip ID mismatch\n\");\nreturn -ENODEV;\n}\n\nret = bma400_get_power_mode(data);\nif (ret) {\ndev_err(data->dev, \"Failed to get the initial power-mode\n\");\nreturn ret;\n}\n\nif (data->power_mode != POWER_MODE_NORMAL) {\nret = bma400_set_power_mode(data, POWER_MODE_NORMAL);\nif (ret) {\ndev_err(data->dev, \"Failed to wake up the device\n\");\nreturn ret;\n}\n/\n* TODO: The datasheet waits 1500us here in the example, but\n* lists 2/ODR as the wakeup time.\n/\nusleep_range(1500, 2000);\n}\n\nret = devm_add_action_or_reset(data->dev, bma400_power_disable, data);\nif (ret)\nreturn ret;\n\nbma400_init_tables();\n\nret = bma400_get_accel_output_data_rate(data);\nif (ret)\nreturn ret;\n\nret = bma400_get_accel_oversampling_ratio(data);\nif (ret)\nreturn ret;\n\nret = bma400_get_accel_scale(data);\nif (ret)\nreturn ret;\n\n/ Configure INT1 pin to open drain /\nret = regmap_write(data->regmap, BMA400_INT_IO_CTRL_REG, 0x06);\nif (ret)\nreturn ret;\n/\n* Once the interrupt engine is supported we might use the\n* data_src_reg, but for now ensure this is set to the\n* variable ODR filter selectable by the sample frequency\n* channel.\n/\nreturn regmap_write(data->regmap, BMA400_ACC_CONFIG2_REG, 0x00);\n}\n\nstatic int bma400_read_raw(struct iio_dev indio_dev,\nstruct iio_chan_spec const chan, int val,\nint val2, long mask)\n{\nstruct bma400_data data = iio_priv(indio_dev);\nunsigned int activity;\nint ret;\n\nswitch (mask) {\ncase IIO_CHAN_INFO_PROCESSED:\nswitch (chan->type) {\ncase IIO_TEMP:\nmutex_lock(&data->mutex);\nret = bma400_get_temp_reg(data, val, val2);\nmutex_unlock(&data->mutex);\nreturn ret;\ncase IIO_STEPS:\nreturn bma400_get_steps_reg(data, val);\ncase IIO_ACTIVITY:\nret = regmap_read(data->regmap, BMA400_STEP_STAT_REG,\n&activity);\nif (ret)\nreturn ret;\n/\n The device does not support confidence value levels,\n* so we will always have 100% for current activity and\n* 0% for the others.\n/\nif (chan->channel2 == bma400_act_to_mod(activity))\nval = 100;\nelse\nval = 0;\nreturn IIO_VAL_INT;\ndefault:\nreturn -EINVAL;\n}\ncase IIO_CHAN_INFO_RAW:\nmutex_lock(&data->mutex);\nret = bma400_get_accel_reg(data, chan, val);\nmutex_unlock(&data->mutex);\nreturn ret;\ncase IIO_CHAN_INFO_SAMP_FREQ:\nswitch (chan->type) {\ncase IIO_ACCEL:\nif (data->sample_freq.hz < 0)\nreturn -EINVAL;\n\nval = data->sample_freq.hz;\nval2 = data->sample_freq.uhz;\nreturn IIO_VAL_INT_PLUS_MICRO;\ncase IIO_TEMP:\n/\n* Runs at a fixed sampling frequency. See Section 4.4\n* of the datasheet.\n/\nval = 6;\nval2 = 250000;\nreturn IIO_VAL_INT_PLUS_MICRO;\ndefault:\nreturn -EINVAL;\n}\ncase IIO_CHAN_INFO_SCALE:\nval = 0;\nval2 = data->scale;\nreturn IIO_VAL_INT_PLUS_MICRO;\ncase IIO_CHAN_INFO_OVERSAMPLING_RATIO:\n/\n* TODO: We could avoid this logic and returning -EINVAL here if\n* we set both the low-power and normal mode OSR registers when\n* we configure the device.\n/\nif (data->oversampling_ratio < 0)\nreturn -EINVAL;\n\nval = data->oversampling_ratio;\nreturn IIO_VAL_INT;\ncase IIO_CHAN_INFO_ENABLE:\nval = data->steps_enabled;\nreturn IIO_VAL_INT;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int bma400_read_avail(struct iio_dev indio_dev,\nstruct iio_chan_spec const chan,\nconst int vals, int type, int length,\nlong mask)\n{\nswitch (mask) {\ncase IIO_CHAN_INFO_SCALE:\ntype = IIO_VAL_INT_PLUS_MICRO;\nvals = bma400_scales;\nlength = ARRAY_SIZE(bma400_scales);\nreturn IIO_AVAIL_LIST;\ncase IIO_CHAN_INFO_OVERSAMPLING_RATIO:\ntype = IIO_VAL_INT;\nvals = bma400_osr_range;\nlength = ARRAY_SIZE(bma400_osr_range);\nreturn IIO_AVAIL_RANGE;\ncase IIO_CHAN_INFO_SAMP_FREQ:\ntype = IIO_VAL_INT_PLUS_MICRO;\nvals = bma400_sample_freqs;\nlength = ARRAY_SIZE(bma400_sample_freqs);\nreturn IIO_AVAIL_LIST;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int bma400_write_raw(struct iio_dev indio_dev,\nstruct iio_chan_spec const chan, int val, int val2,\nlong mask)\n{\nstruct bma400_data data = iio_priv(indio_dev);\nint ret;\n\nswitch (mask) {\ncase IIO_CHAN_INFO_SAMP_FREQ:\n/\n* The sample frequency is readonly for the temperature\n* register and a fixed value in low-power mode.\n/\nif (chan->type != IIO_ACCEL)\nreturn -EINVAL;\n\nmutex_lock(&data->mutex);\nret = bma400_set_accel_output_data_rate(data, val, val2);\nmutex_unlock(&data->mutex);\nreturn ret;\ncase IIO_CHAN_INFO_SCALE:\nif (val != 0 \|\|\nval2 < BMA400_SCALE_MIN \|\| val2 > BMA400_SCALE_MAX)\nreturn -EINVAL;\n\nmutex_lock(&data->mutex);\nret = bma400_set_accel_scale(data, val2);\nmutex_unlock(&data->mutex);\nreturn ret;\ncase IIO_CHAN_INFO_OVERSAMPLING_RATIO:\nmutex_lock(&data->mutex);\nret = bma400_set_accel_oversampling_ratio(data, val);\nmutex_unlock(&data->mutex);\nreturn ret;\ncase IIO_CHAN_INFO_ENABLE:\nmutex_lock(&data->mutex);\nret = bma400_enable_steps(data, val);\nmutex_unlock(&data->mutex);\nreturn ret;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int bma400_write_raw_get_fmt(struct iio_dev indio_dev,\nstruct iio_chan_spec const chan,\nlong mask)\n{\nswitch (mask) {\ncase IIO_CHAN_INFO_SAMP_FREQ:\nreturn IIO_VAL_INT_PLUS_MICRO;\ncase IIO_CHAN_INFO_SCALE:\nreturn IIO_VAL_INT_PLUS_MICRO;\ncase IIO_CHAN_INFO_OVERSAMPLING_RATIO:\nreturn IIO_VAL_INT;\ncase IIO_CHAN_INFO_ENABLE:\nreturn IIO_VAL_INT;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int bma400_read_event_config(struct iio_dev indio_dev,\nconst struct iio_chan_spec chan,\nenum iio_event_type type,\nenum iio_event_direction dir)\n{\nstruct bma400_data data = iio_priv(indio_dev);\n\nswitch (chan->type) {\ncase IIO_ACCEL:\nswitch (dir) {\ncase IIO_EV_DIR_RISING:\nreturn FIELD_GET(BMA400_INT_GEN1_MSK,\ndata->generic_event_en);\ncase IIO_EV_DIR_FALLING:\nreturn FIELD_GET(BMA400_INT_GEN2_MSK,\ndata->generic_event_en);\ncase IIO_EV_DIR_SINGLETAP:\nreturn FIELD_GET(BMA400_S_TAP_MSK,\ndata->tap_event_en_bitmask);\ncase IIO_EV_DIR_DOUBLETAP:\nreturn FIELD_GET(BMA400_D_TAP_MSK,\ndata->tap_event_en_bitmask);\ndefault:\nreturn -EINVAL;\n}\ncase IIO_STEPS:\nreturn data->step_event_en;\ncase IIO_ACTIVITY:\nreturn data->activity_event_en;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int bma400_steps_event_enable(struct bma400_data data, int state)\n{\nint ret;\n\nret = bma400_enable_steps(data, 1);\nif (ret)\nreturn ret;\n\nret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG,\nBMA400_STEP_INT_MSK,\nFIELD_PREP(BMA400_STEP_INT_MSK,\nstate));\nif (ret)\nreturn ret;\ndata->step_event_en = state;\nreturn 0;\n}\n\nstatic int bma400_activity_event_en(struct bma400_data data,\nenum iio_event_direction dir,\nint state)\n{\nint ret, reg, msk, value;\nint field_value = 0;\n\nswitch (dir) {\ncase IIO_EV_DIR_RISING:\nreg = BMA400_GEN1INT_CONFIG0;\nmsk = BMA400_INT_GEN1_MSK;\nvalue = 2;\nset_mask_bits(&field_value, BMA400_INT_GEN1_MSK,\nFIELD_PREP(BMA400_INT_GEN1_MSK, state));\nbreak;\ncase IIO_EV_DIR_FALLING:\nreg = BMA400_GEN2INT_CONFIG0;\nmsk = BMA400_INT_GEN2_MSK;\nvalue = 0;\nset_mask_bits(&field_value, BMA400_INT_GEN2_MSK,\nFIELD_PREP(BMA400_INT_GEN2_MSK, state));\nbreak;\ndefault:\nreturn -EINVAL;\n}\n\n/* Enabling all axis for interrupt evaluation /\nret = regmap_write(data->regmap, reg, 0xF8);\nif (ret)\nreturn ret;\n\n/ OR combination of all axis for interrupt evaluation /\nret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value);\nif (ret)\nreturn ret;\n\n/ Initial value to avoid interrupts while enabling/\nret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A);\nif (ret)\nreturn ret;\n\n/ Initial duration value to avoid interrupts while enabling/\nret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F);\nif (ret)\nreturn ret;\n\nret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk,\nfield_value);\nif (ret)\nreturn ret;\n\nret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk,\nfield_value);\nif (ret)\nreturn ret;\n\nset_mask_bits(&data->generic_event_en, msk, field_value);\nreturn 0;\n}\n\nstatic int bma400_tap_event_en(struct bma400_data data,\nenum iio_event_direction dir, int state)\n{\nunsigned int mask, field_value;\nint ret;\n\n/\n Tap interrupts can be configured only in normal mode.\n* See table in section 4.3 \"Power modes - performance modes\" of\n* datasheet v1.2.\n/\nif (data->power_mode != POWER_MODE_NORMAL)\nreturn -EINVAL;\n\n/\n* Tap interrupts are operating with a data rate of 200Hz.\n* See section 4.7 \"Tap sensing interrupt\" in datasheet v1.2.\n/\nif (data->sample_freq.hz != 200 && state) {\ndev_err(data->dev, \"Invalid data rate for tap interrupts.\n\");\nreturn -EINVAL;\n}\n\nret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG,\nBMA400_S_TAP_MSK,\nFIELD_PREP(BMA400_S_TAP_MSK, state));\nif (ret)\nreturn ret;\n\nswitch (dir) {\ncase IIO_EV_DIR_SINGLETAP:\nmask = BMA400_S_TAP_MSK;\nset_mask_bits(&field_value, BMA400_S_TAP_MSK,\nFIELD_PREP(BMA400_S_TAP_MSK, state));\nbreak;\ncase IIO_EV_DIR_DOUBLETAP:\nmask = BMA400_D_TAP_MSK;\nset_mask_bits(&field_value, BMA400_D_TAP_MSK,\nFIELD_PREP(BMA400_D_TAP_MSK, state));\nbreak;\ndefault:\nreturn -EINVAL;\n}\n\nret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, mask,\nfield_value);\nif (ret)\nreturn ret;\n\nset_mask_bits(&data->tap_event_en_bitmask, mask, field_value);\n\nreturn 0;\n}\n\nstatic int bma400_disable_adv_interrupt(struct bma400_data data)\n{\nint ret;\n\nret = regmap_write(data->regmap, BMA400_INT_CONFIG0_REG, 0);\nif (ret)\nreturn ret;\n\nret = regmap_write(data->regmap, BMA400_INT_CONFIG1_REG, 0);\nif (ret)\nreturn ret;\n\ndata->tap_event_en_bitmask = 0;\ndata->generic_event_en = 0;\ndata->step_event_en = false;\ndata->activity_event_en = false;\n\nreturn 0;\n}\n\nstatic int bma400_write_event_config(struct iio_dev indio_dev,\nconst struct iio_chan_spec chan,\nenum iio_event_type type,\nenum iio_event_direction dir, int state)\n{\nstruct bma400_data data = iio_priv(indio_dev);\nint ret;\n\nswitch (chan->type) {\ncase IIO_ACCEL:\nswitch (type) {\ncase IIO_EV_TYPE_MAG:\nmutex_lock(&data->mutex);\nret = bma400_activity_event_en(data, dir, state);\nmutex_unlock(&data->mutex);\nreturn ret;\ncase IIO_EV_TYPE_GESTURE:\nmutex_lock(&data->mutex);\nret = bma400_tap_event_en(data, dir, state);\nmutex_unlock(&data->mutex);\nreturn ret;\ndefault:\nreturn -EINVAL;\n}\ncase IIO_STEPS:\nmutex_lock(&data->mutex);\nret = bma400_steps_event_enable(data, state);\nmutex_unlock(&data->mutex);\nreturn ret;\ncase IIO_ACTIVITY:\nmutex_lock(&data->mutex);\nif (!data->step_event_en) {\nret = bma400_steps_event_enable(data, true);\nif (ret) {\nmutex_unlock(&data->mutex);\nreturn ret;\n}\n}\ndata->activity_event_en = state;\nmutex_unlock(&data->mutex);\nreturn 0;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int get_gen_config_reg(enum iio_event_direction dir)\n{\nswitch (dir) {\ncase IIO_EV_DIR_FALLING:\nreturn BMA400_GEN2INT_CONFIG0;\ncase IIO_EV_DIR_RISING:\nreturn BMA400_GEN1INT_CONFIG0;\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int bma400_read_event_value(struct iio_dev indio_dev,\nconst struct iio_chan_spec chan,\nenum iio_event_type type,\nenum iio_event_direction dir,\nenum iio_event_info info,\nint val, int val2)\n{\nstruct bma400_data data = iio_priv(indio_dev);\nint ret, reg, reg_val, raw;\n\nif (chan->type != IIO_ACCEL)\nreturn -EINVAL;\n\nswitch (type) {\ncase IIO_EV_TYPE_MAG:\nreg = get_gen_config_reg(dir);\nif (reg < 0)\nreturn -EINVAL;\n\nval2 = 0;\nswitch (info) {\ncase IIO_EV_INFO_VALUE:\nret = regmap_read(data->regmap,\nreg + BMA400_GEN_CONFIG2_OFF,\nval);\nif (ret)\nreturn ret;\nreturn IIO_VAL_INT;\ncase IIO_EV_INFO_PERIOD:\nmutex_lock(&data->mutex);\nret = regmap_bulk_read(data->regmap,\nreg + BMA400_GEN_CONFIG3_OFF,\n&data->duration,\nsizeof(data->duration));\nif (ret) {\nmutex_unlock(&data->mutex);\nreturn ret;\n}\nval = be16_to_cpu(data->duration);\nmutex_unlock(&data->mutex);\nreturn IIO_VAL_INT;\ncase IIO_EV_INFO_HYSTERESIS:\nret = regmap_read(data->regmap, reg, val);\nif (ret)\nreturn ret;\nval = FIELD_GET(BMA400_GEN_HYST_MSK, val);\nreturn IIO_VAL_INT;\ndefault:\nreturn -EINVAL;\n}\ncase IIO_EV_TYPE_GESTURE:\nswitch (info) {\ncase IIO_EV_INFO_VALUE:\nret = regmap_read(data->regmap, BMA400_TAP_CONFIG,\n&reg_val);\nif (ret)\nreturn ret;\n\nval = FIELD_GET(BMA400_TAP_SEN_MSK, reg_val);\nreturn IIO_VAL_INT;\ncase IIO_EV_INFO_RESET_TIMEOUT:\nret = regmap_read(data->regmap, BMA400_TAP_CONFIG1,\n&reg_val);\nif (ret)\nreturn ret;\n\nraw = FIELD_GET(BMA400_TAP_QUIET_MSK, reg_val);\nval = 0;\nval2 = tap_reset_timeout[raw];\nreturn IIO_VAL_INT_PLUS_MICRO;\ncase IIO_EV_INFO_TAP2_MIN_DELAY:\nret = regmap_read(data->regmap, BMA400_TAP_CONFIG1,\n&reg_val);\nif (ret)\nreturn ret;\n\nraw = FIELD_GET(BMA400_TAP_QUIETDT_MSK, reg_val);\nval = 0;\nval2 = double_tap2_min_delay[raw];\nreturn IIO_VAL_INT_PLUS_MICRO;\ndefault:\nreturn -EINVAL;\n}\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int bma400_write_event_value(struct iio_dev indio_dev,\nconst struct iio_chan_spec chan,\nenum iio_event_type type,\nenum iio_event_direction dir,\nenum iio_event_info info,\nint val, int val2)\n{\nstruct bma400_data data = iio_priv(indio_dev);\nint reg, ret, raw;\n\nif (chan->type != IIO_ACCEL)\nreturn -EINVAL;\n\nswitch (type) {\ncase IIO_EV_TYPE_MAG:\nreg = get_gen_config_reg(dir);\nif (reg < 0)\nreturn -EINVAL;\n\nswitch (info) {\ncase IIO_EV_INFO_VALUE:\nif (val < 1 \|\| val > 255)\nreturn -EINVAL;\n\nreturn regmap_write(data->regmap,\nreg + BMA400_GEN_CONFIG2_OFF,\nval);\ncase IIO_EV_INFO_PERIOD:\nif (val < 1 \|\| val > 65535)\nreturn -EINVAL;\n\nmutex_lock(&data->mutex);\nput_unaligned_be16(val, &data->duration);\nret = regmap_bulk_write(data->regmap,\nreg + BMA400_GEN_CONFIG3_OFF,\n&data->duration,\nsizeof(data->duration));\nmutex_unlock(&data->mutex);\nreturn ret;\ncase IIO_EV_INFO_HYSTERESIS:\nif (val < 0 \|\| val > 3)\nreturn -EINVAL;\n\nreturn regmap_update_bits(data->regmap, reg,\nBMA400_GEN_HYST_MSK,\nFIELD_PREP(BMA400_GEN_HYST_MSK,\nval));\ndefault:\nreturn -EINVAL;\n}\ncase IIO_EV_TYPE_GESTURE:\nswitch (info) {\ncase IIO_EV_INFO_VALUE:\nif (val < 0 \|\| val > 7)\nreturn -EINVAL;\n\nreturn regmap_update_bits(data->regmap,\nBMA400_TAP_CONFIG,\nBMA400_TAP_SEN_MSK,\nFIELD_PREP(BMA400_TAP_SEN_MSK,\nval));\ncase IIO_EV_INFO_RESET_TIMEOUT:\nraw = usec_to_tapreg_raw(val2, tap_reset_timeout);\nif (raw < 0)\nreturn -EINVAL;\n\nreturn regmap_update_bits(data->regmap,\nBMA400_TAP_CONFIG1,\nBMA400_TAP_QUIET_MSK,\nFIELD_PREP(BMA400_TAP_QUIET_MSK,\nraw));\ncase IIO_EV_INFO_TAP2_MIN_DELAY:\nraw = usec_to_tapreg_raw(val2, double_tap2_min_delay);\nif (raw < 0)\nreturn -EINVAL;\n\nreturn regmap_update_bits(data->regmap,\nBMA400_TAP_CONFIG1,\nBMA400_TAP_QUIETDT_MSK,\nFIELD_PREP(BMA400_TAP_QUIETDT_MSK,\nraw));\ndefault:\nreturn -EINVAL;\n}\ndefault:\nreturn -EINVAL;\n}\n}\n\nstatic int bma400_data_rdy_trigger_set_state(struct iio_trigger trig,\nbool state)\n{\nstruct iio_dev indio_dev = iio_trigger_get_drvdata(trig);\nstruct bma400_data data = iio_priv(indio_dev);\nint ret;\n\nret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG,\nBMA400_INT_DRDY_MSK,\nFIELD_PREP(BMA400_INT_DRDY_MSK, state));\nif (ret)\nreturn ret;\n\nreturn regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG,\nBMA400_INT_DRDY_MSK,\nFIELD_PREP(BMA400_INT_DRDY_MSK, state));\n}\n\nstatic const unsigned long bma400_avail_scan_masks[] = {\nBIT(BMA400_ACCL_X) \| BIT(BMA400_ACCL_Y) \| BIT(BMA400_ACCL_Z),\nBIT(BMA400_ACCL_X) \| BIT(BMA400_ACCL_Y) \| BIT(BMA400_ACCL_Z)\n\| BIT(BMA400_TEMP),\n0\n};\n\nstatic const struct iio_info bma400_info = {\n.read_raw = bma400_read_raw,\n.read_avail = bma400_read_avail,\n.write_raw = bma400_write_raw,\n.write_raw_get_fmt = bma400_write_raw_get_fmt,\n.read_event_config = bma400_read_event_config,\n.write_event_config = bma400_write_event_config,\n.write_event_value = bma400_write_event_value,\n.read_event_value = bma400_read_event_value,\n.event_attrs = &bma400_event_attribute_group,\n};\n\nstatic const struct iio_trigger_ops bma400_trigger_ops = {\n.set_trigger_state = &bma400_data_rdy_trigger_set_state,\n.validate_device = &iio_trigger_validate_own_device,\n};\n\nstatic irqreturn_t bma400_trigger_handler(int irq, void p)\n{\nstruct iio_poll_func pf = p;\nstruct iio_dev indio_dev = pf->indio_dev;\nstruct bma400_data data = iio_priv(indio_dev);\nint ret, temp;\n\n/ Lock to protect the data->buffer /\nmutex_lock(&data->mutex);\n\n/ bulk read six registers, with the base being the LSB register /\nret = regmap_bulk_read(data->regmap, BMA400_X_AXIS_LSB_REG,\n&data->buffer.buff, sizeof(data->buffer.buff));\nif (ret)\ngoto unlock_err;\n\nif (test_bit(BMA400_TEMP, indio_dev->active_scan_mask)) {\nret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &temp);\nif (ret)\ngoto unlock_err;\n\ndata->buffer.temperature = temp;\n}\n\niio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,\niio_get_time_ns(indio_dev));\n\nmutex_unlock(&data->mutex);\niio_trigger_notify_done(indio_dev->trig);\nreturn IRQ_HANDLED;\n\nunlock_err:\nmutex_unlock(&data->mutex);\nreturn IRQ_NONE;\n}\n\nstatic irqreturn_t bma400_interrupt(int irq, void private)\n{\nstruct iio_dev indio_dev = private;\nstruct bma400_data data = iio_priv(indio_dev);\ns64 timestamp = iio_get_time_ns(indio_dev);\nunsigned int act, ev_dir = IIO_EV_DIR_NONE;\nint ret;\n\n/* Lock to protect the data->status /\nmutex_lock(&data->mutex);\nret = regmap_bulk_read(data->regmap, BMA400_INT_STAT0_REG,\n&data->status,\nsizeof(data->status));\n/\n* if none of the bit is set in the status register then it is\n* spurious interrupt.\n/\nif (ret \|\| !data->status)\ngoto unlock_err;\n\n/\n* Disable all advance interrupts if interrupt engine overrun occurs.\n* See section 4.7 \"Interrupt engine overrun\" in datasheet v1.2.\n/\nif (FIELD_GET(BMA400_INT_ENG_OVRUN_MSK, le16_to_cpu(data->status))) {\nbma400_disable_adv_interrupt(data);\ndev_err(data->dev, \"Interrupt engine overrun\n\");\ngoto unlock_err;\n}\n\nif (FIELD_GET(BMA400_INT_S_TAP_MSK, le16_to_cpu(data->status)))\niio_push_event(indio_dev,\nIIO_MOD_EVENT_CODE(IIO_ACCEL, 0,\nIIO_MOD_X_OR_Y_OR_Z,\nIIO_EV_TYPE_GESTURE,\nIIO_EV_DIR_SINGLETAP),\ntimestamp);\n\nif (FIELD_GET(BMA400_INT_D_TAP_MSK, le16_to_cpu(data->status)))\niio_push_event(indio_dev,\nIIO_MOD_EVENT_CODE(IIO_ACCEL, 0,\nIIO_MOD_X_OR_Y_OR_Z,\nIIO_EV_TYPE_GESTURE,\nIIO_EV_DIR_DOUBLETAP),\ntimestamp);\n\nif (FIELD_GET(BMA400_INT_GEN1_MSK, le16_to_cpu(data->status)))\nev_dir = IIO_EV_DIR_RISING;\n\nif (FIELD_GET(BMA400_INT_GEN2_MSK, le16_to_cpu(data->status)))\nev_dir = IIO_EV_DIR_FALLING;\n\nif (ev_dir != IIO_EV_DIR_NONE) {\niio_push_event(indio_dev,\nIIO_MOD_EVENT_CODE(IIO_ACCEL, 0,\nIIO_MOD_X_OR_Y_OR_Z,\nIIO_EV_TYPE_MAG, ev_dir),\ntimestamp);\n}\n\nif (FIELD_GET(BMA400_STEP_STAT_MASK, le16_to_cpu(data->status))) {\niio_push_event(indio_dev,\nIIO_MOD_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD,\nIIO_EV_TYPE_CHANGE,\nIIO_EV_DIR_NONE),\ntimestamp);\n\nif (data->activity_event_en) {\nret = regmap_read(data->regmap, BMA400_STEP_STAT_REG,\n&act);\nif (ret)\ngoto unlock_err;\n\niio_push_event(indio_dev,\nIIO_MOD_EVENT_CODE(IIO_ACTIVITY, 0,\nbma400_act_to_mod(act),\nIIO_EV_TYPE_CHANGE,\nIIO_EV_DIR_NONE),\ntimestamp);\n}\n}\n\nif (FIELD_GET(BMA400_INT_DRDY_MSK, le16_to_cpu(data->status))) {\nmutex_unlock(&data->mutex);\niio_trigger_poll_nested(data->trig);\nreturn IRQ_HANDLED;\n}\n\nmutex_unlock(&data->mutex);\nreturn IRQ_HANDLED;\n\nunlock_err:\nmutex_unlock(&data->mutex);\nreturn IRQ_NONE;\n}\n\nint bma400_probe(struct device dev, struct regmap regmap, int irq,\nconst char name)\n{\nstruct iio_dev indio_dev;\nstruct bma400_data data;\nint ret;\n\nindio_dev = devm_iio_device_alloc(dev, sizeof(*data));\nif (!indio_dev)\nreturn -ENOMEM;\n\ndata = iio_priv(indio_dev);\ndata->regmap = regmap;\ndata->dev = dev;\n\nret = bma400_init(data);\nif (ret)\nreturn ret;\n\nret = iio_read_mount_matrix(dev, &data->orientation);\nif (ret)\nreturn ret;\n\nmutex_init(&data->mutex);\nindio_dev->name = name;\nindio_dev->info = &bma400_info;\nindio_dev->channels = bma400_channels;\nindio_dev->num_channels = ARRAY_SIZE(bma400_channels);\nindio_dev->available_scan_masks = bma400_avail_scan_masks;\nindio_dev->modes = INDIO_DIRECT_MODE;\n\nif (irq > 0) {\ndata->trig = devm_iio_trigger_alloc(dev, \"%s-dev%d\",\nindio_dev->name,\niio_device_id(indio_dev));\nif (!data->trig)\nreturn -ENOMEM;\n\ndata->trig->ops = &bma400_trigger_ops;\niio_trigger_set_drvdata(data->trig, indio_dev);\n\nret = devm_iio_trigger_register(data->dev, data->trig);\nif (ret)\nreturn dev_err_probe(data->dev, ret,\n\"iio trigger register fail\n\");\n\nindio_dev->trig = iio_trigger_get(data->trig);\nret = devm_request_threaded_irq(dev, irq, NULL,\n&bma400_interrupt,\nIRQF_TRIGGER_RISING \| IRQF_ONESHOT,\nindio_dev->name, indio_dev);\nif (ret)\nreturn dev_err_probe(data->dev, ret,\n\"request irq %d failed\n\", irq);\n}\n\nret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,\n&bma400_trigger_handler, NULL);\nif (ret)\nreturn dev_err_probe(data->dev, ret,\n\"iio triggered buffer setup failed\n\");\n\nreturn devm_iio_device_register(dev, indio_dev);\n}\nEXPORT_SYMBOL_NS(bma400_probe, IIO_BMA400);\n\nMODULE_AUTHOR(\"Dan Robertson <dan@dlrobertson.com>\");\nMODULE_AUTHOR(\"Jagath Jog J <jagathjog1996@gmail.com>\");\nMODULE_DESCRIPTION(\"Bosch BMA400 triaxial acceleration sensor core\");\nMODULE_LICENSE(\"GPL\");"}