A New Read-Disturb Failure Mechanism Caused by Boosting Hot-Carrier Injection Effect in MLC NAND Flash Memory

In this paper, we have reported a new failure phenomenon of read-disturb in MLC NAND flash memory caused by boosting hot-carrier injection effect. 1) The read-disturb failure occurred on unselected WL (WLn+1) after the adjacent selected WL (WLn) was performed with more than 1K read cycles. 2) The read-disturb failure of WLn+1 depends on WLn cell’s Vth and its applied voltage. 3) The mechanism of this kind of failure can be explained by hot carrier injection that is generated by discharging from boosting voltage in unselected cell area (Drain of WLn) to ground (Source of WLn). Experiment A NAND Flash memory was fabricated based on 70nm technology. In order to investigate the mechanisms of readdisturb, 3 different read voltages and 4 different cell data states (S0, S1, S2 and S3) were applied on the selected WL with SGS/SGD rising time shift scheme [1]. Fig. 1 and Fig. 2 show the operation condition and waveform for readdisturb evaluation. In the evaluation, the selected WLn was performed with more than 100K read cycles. Result And Discussion Fig. 3 shows the measured results of WL2 Vth shift (i.e. read-disturb failure) during WL1 read-didturb cycles with different WL1 voltages (VWL1) and cell data states (S0~S3). From these data, a serious WL2 Vth shift can be observed in VWL1=0.5V and VWL1=1.8V after 1K read cycles. In Fig. 3(a), the magnitude of Vth shift with WL1=S2 state is larger than that with WL1=S3 state. However, obviously WL2 Vth shift can be found only when WL1 is at S3 state in Fig. 3(b). In Fig. 3(c), WL2 Vth is unchanged while VWL1 is set to 3.6V. To precisely analyze the phenomenon, further TCAD simulation and analysis were carried out to clarify the mechanism of the read-disturb failure. Based on simulation results of Fig. 4, the channel potential difference between selected WLn (e.g. WL1) and unselected WLn+1 (e.g. WL2) is related to cell data states (S0~S3) and the read voltage of the selected WL (VWL1). Fig. 4(a) exhibits that the selected WL1 channel was tuned off and the channel potential of unselected WL2~31 was boosted to high level when the WL1 cell data state is S2 or S3. Therefore, a sufficient potential difference appears between WLn and WLn+1 and provides a high transverse electric field. When VWL1 is increased to 1.8V as Fig. 4(b), a high programming cell state (S3) is required to support the potential boosting of unselected WL2~31. In addition, from Fig. 4(c) and the case of WL1=S2 in Fig. 4(b), we can find that the potential difference were depressed since the WL1 channel is turned on by high WL1 voltage. Therefore, the potential difference can be reduced by sharing effect. These simulation results are well corresponding with read disturb results of Fig. 3. Electron current density is another factor to cause the Vth shift of WLn+1. From Fig. 3(a), the current density of WL1=S2 should higher than that of WL=S3 since its Vth is lower. Consequently, the probability of impact ionization can be increased due to the high current density in case of WL1=S2. According to the model, we can clearly explain the phenomenon of serious WL2 Vth shift occurs in the condition of WL 1=S2 rather than WL1=S3. Fig. 5 shows the schematic diagram of the mechanism of Boosting Hot-carrier Injection in MLC NAND flash memories. The transverse E-field can be enhanced by the channel potential difference and consequently make a high probability of impact ionization. As a result, electron-hole pairs will be generated, and then electrons will inject into the adjacent cell (WL2) since the higher vertical field of VWL2. Thus, the Vth of adjacent cell will be changed after 1K cycles with the continual injecting of the hot electrons. Table 1 shows the measured result of cell array Vth shift for WL1 to WL4 after the read-disturb cycles on WL1 or WL2. From the data, it concretely indicates that the WLn read cycles could only causes WLn+1 Vth shift even if WLn+1 did not apply the read cycles. The result is consistent with measured data and also supports that the read-disturb on adjacent cell results from boosting hotcarrier injection. Conclusion A new read-disturb failure mechanism caused by boosting hot-carrier injection effect in MLC NAND flash memory has been reported and clarified. Simulation and measured data describe that the electrostatic potential difference between reading cell and the adjacent cell plays a significant role to enhance hot-carrier injection effect. Reference [1] Ken Takeuchi, “A 56nm CMOS 99mm2 8Gb Multilevel NAND Flash Memory with 10MB/s Program Throughput ,” ISSCC, 2006. 978-1-4244-3761-0/09/$25.00 ©2009 IEEE R ead D isturbance Test R esult W L0 W L1 W L2 W L3 W L4 W L1= S0 Pass Pass Pass Pass Pass W L1= S1 Pass Pass Pass Pass Pass W L1= S2 Pass Pass Fail Pass Pass W L1= S3 Pass Pass Fail Pass Pass W L1= S0 Pass Pass Pass Pass Pass W L1= S1 Pass Pass Pass Pass Pass W L1= S2 Pass Pass Pass Pass Pass W L1= S3 Pass Pass Fail Pass Pass W L1= S0 Pass Pass Pass Pass Pass W L1= S1 Pass Pass Pass Pass Pass W L1= S2 Pass Pass Pass Pass Pass W L1= S3 Pass Pass Pass Pass Pass W L2= S0 Pass Pass Pass Pass Pass W L2= S1 Pass Pass Pass Pass Pass W L2= S2 Pass Pass Pass Fail Pass W L2= S3 Pass Pass Pass Fail Pass W L1 Read= 0.5V (C ase 1 ) W L1 Read= 1.8V (C ase 2 ) W L1 Read= 3.6V (C ase 3 )