DESIGN OF 9 BIT SAR ADC USING HIGH SPEED AND HIGH RESOLUTION OPEN LOOP CMOS COMPARATOR IN 180 NM TECHNOLOGY WITH R-2 R DAC TOPOLOGY

A Successive approximation analog to digital converter (ADC) for data acquisition using fully CMOS high speed self-biased comparator circuit is discussed in this paper. ASIC finds greater demand when area and speed optimization are major concern and here the entire optimized design is done in CADENCE virtuoso EDA tool in 180nm technology. Towerjazz semiconductor foundry is the base for layout design and GDSII extraction. Comparison of different DAC architecture and the precise architecture with minimum DNL and INL are chosen for the design procedure. This paper describes the design of a fully customized 9 bit SAR ADC with input voltage ranging from 0 to 2.5V and sampling frequency 16.67 KHz. Hspice simulators is used for the simulations. Keywords— SAR ADC, Comparator, CADENCE, CMOS, DAC. [1] INTRODUCTION With the development of sensors, portable devices and high speed computing systems, comparable growth is seen in the optimization of Analog to digital converters (ADC) to assist in the technology growth. All the natural signals are analog and the present digital world require the signal in digital format for storing, processing and transmitting and thereby ADC becomes an integral part of almost all electronic devices 8 . This leads to the need for power, area and speed optimized design of ADCs. There are different ADC architectures like Flash ADC, SAR ADC, sigma-delta ADC etc., with each having its own pros and cons. The designer selects the desired architecture according to the requirements 1 . Flash ADC is the fasted ADC structure where the output is obtained in a single cycle but requires a large number of resistors and comparators for the design. For an N bit 2 flash ADC 2 N resistors and 2 N-1 comparators are required consuming large amount of area and power. Modifications are done on flash ADC to form pipelined flash ADC where the number of components can be reduced but the power consumption cannot be further reduced beyond a level. Sigma-delta ADC or integrating type of ADC is used when the resolution required is very high. This is the slowest architecture compared to other architectures. Design of sigma-delta requires analog design of integrator circuit making its design complex. SAR ADC architecture gives the output in N cycles for an N-bit ADC. SAR ADC being one of the pioneer ADC architecture is been commonly used due to its good trade-off between area, power and speed, which is the required criteria for CMOS deep submicron circuits. SAR ADC consists of a Track and Hold (TH) circuit, comparator, DAC and a SAR register and control logic. Figure 1 shows the block diagram of a SAR ADC. This paper is organized into six sections. Section II describes the analog design of TH and comparator. Section III compares the DAC architecture. Section IV explains the SAR logic. Section V gives the simulation results and section VI is the conclusion. Fig 1 Block Diagram of SAR ADC [2] ANALOG DESIGN OF TH AND COMPARATOR A. Track and Hold In general, Sample and hold circuit or Track and Hold contain a switch and a capacitor. In the tracking mode, when the sampling signal (strobe pulse) is high and the switch is connected, it tracks the analog input signal 3 . Then, it holds the value when the sampling signal turns to low in the hold mode. In this case, sample and hold provides a constant voltage at the input of the ADC during conversion 7 . Figure 2 shows a simple Track and hold Vol 05, Article 11492, November 2014 International Journal of VLSI and Embedded Systems-IJVES http://ijves.com ISSN: 2249 – 6556 2010-2014 – IJVES Indexing in Process EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc., 1392 circuit with a NMOS transistor as switch. The capacitance value is selected as 100pF and aspect ratio of the transistor as 28 based on the design steps. Fig 2 Track and hold circuit B. Latched comparator Comparator with high resolution and high speed is the desired design criteria and here dynamic latched comparator topology and self-biased open loop comparator topology are studied and implemented. From the comparison results, the best topology considering speed and better resolution is selected. Figure 3 shows a latched comparator. Static latch consumes static power which is not attractive for low power applications. A major disadvantage of latch is low resolution. Fig 3Latched comparator C. Self-biased open loop comparator A self-biased open loop comparator is a differential input high gain amplifier with an output stage. A currentmirror acts as the load for the differential pair and converts the double ended circuit to a single ended. Since precise gain is not required for comparator circuit, no compensation techniques are required 4 . Figure 4 shows a self-biased open loop comparator. Schematic of the circuit implementation and simulation result shows that selfbiased open loop comparator has better speed of operation compared to latched comparator. The simulation results are tabulated below in table 1. Thought there are two capacitors in open loop comparator resulting in more power consumption, speed of operation and resolution is better compared to latched comparator. So open loop comparator circuit is selected for the design advancement. Both the comparator design is done based of a specific output current and slew rate. Fig 4 Self-biased open loop comparator Conversion time No of transistors Resolution Power Latched comparator 426.6ns 11 4mv 80nw Self-biased open loop comparator 712.7ns 10 15mv 58nw Table 1 Comparator simulation results [3] DAC ARCHITECTURE A. R-2R DAC The digital data bits are entered through the input lines (d0 to d(N-1)) which is to be converted to an equivalent analog voltage (Vout) using R/2R resistor network 5 . The R/2R network is built by a set of resistors of two Vol 05, Article 11492, November 2014 International Journal of VLSI and Embedded Systems-IJVES http://ijves.com ISSN: 2249 – 6556 2010-2014 – IJVES Indexing in Process EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc., 1393 values, with values of one sets being twice of the other. Here for simulation purpose 1K and 2K resistors are used, there by resulting R/2R ratio. Accuracy or precision of DAC depends on the values of resistors chosen, higher precision can be obtained with an exact match of the R/2R ratio. B. C-2C DAC The schematic diagram of 3bit C2C ladder is shown in figure 4.3 which is similar to that of the R2R type. The capacitor value selected as 20 fF and 40 fF for C and 2C respectively such that the impedance value of C is twice that of 2C. C. Charge scaling DAC The voltage division principle is same as that of C-2C 6 . The value of unit capacitance is selected as 20fF for the simulation purpose. In order to obtain precision between the capacitance value parallel combinations of unit capacitance is implemented for the binary weighted value. Compared to C-2C the capacitance area is considerably large. DAC type Integral Non-Linearity INL Differential Non-Linearity DNL Offset