Statistical analysis of integrated passive delay lines

Statistical properties of integrated passive LC delay lines are investigated. A new variation using spiral inductors and vertical parallel plate (VPP) capacitors is introduced whose delay is primarily determined by the lateral dimensions, resulting in very accurate and repeatable delays. An MIM-based version of this line is also fabricated for comparison. Additionally, LC delay-based oscillators are implemented to compare the variations in active and passive delay elements. Experimental data is obtained from measurement of 27 and 47 sites on two wafers from two different process runs, respectively. The measurements show 0.6% delay variations for VPPbased delay line compared to 1.0% for its MIM-based counterpart. Introduction Accurate timing is the underlying principal used in communication and computation systems. The timing accuracy directly affects the performance of these systems. Integrated delay elements are arguably one of the most critical building blocks whose accuracy and repeatability directly affect the timing accuracy of digital and mixed-mode systems. Various forms of active and passive delay elements have been used in different circuits and systems such as delay-based oscillators (e.g., [1][3]), delay-locked loops (DLLs) (e.g., [4]), digital-to-phase convertors (e.g., [5]), and transversal filters and equalizers (e.g., [6]). As the frequency of these applications increases, the requirement on the absolute accuracy of the delay elements tightens. It is important to control the delay of these elements in the presence of variations in process parameters, supply voltage, and temperature to achieve higher yield and reliability for the specified performance. In systems using active non-linear (e.g., digital) delay elements, this is usually done through a feedback system relating the delay accuracy to an external reference. While practical for many digital systems, applications such as transversal filters and equalizers (e.g., [6]) require linear wideband delay elements not to introduce distortion on the signal. This can be achieved more readily by using integrated passive delay lines with practically no sensitivity to the supply voltage while maintaining a low sensitivity to process variations and temperature. It has been shown [2] that using building blocks that depend only on the lateral dimensions, such as vertical parallel plate (VPP) capacitors, one can achieve a tighter tolerance and better matching across the chip, wafer, and process lots. This is primarily due to the inherently higher accuracy of the lithography and etching processes used to define the lateral dimensions of these components. Interestingly, the inductance of spiral inductors is primarily determined by its lateral dimensions, encouraging the design of passive LC delay lines using these lateral components. It eliminates the delay dependency on less accurate process steps such as deposition and planarization that control the vertical dimensions. This work presents the experimental results of a set of measurements and statistical analysis on fabricated passive delay lines and delay-based oscillators. It verifies low sensitivity of LC delay lines to process variations. In the rest of the paper, we review the theory of LC delay lines, and introduce our implementation of integrated LC delay lines. Then, we discuss the measurement setup and results. LC Passive Delay Lines There are several structures comprising inductors, L, and capacitors, C, that can be used as delay lines. Perhaps, the best known is Bessel-Thomson filter [7][8] that has maximally flat delay response. However, it is not suitable for integration since it results in delay values that are small for today’s applications and also because its component values become unrealistic for integration, as the filter order increases. Constant-k LC ladder structures on the other hand consist of identical interconnected inductors and capacitors in a ladder form, as shown in Fig. 1a. The ladder is a lumped approximation of transmission line and hence, can be used as a delay line. It can be shown that the delay of the structure is approximately: