High Performance Cognitive Radio Platform with Integrated Physical and Network Layer Capabilities

This is an interim technical report on the “network centric cognitive radio platform” being developed under the NSF NeTS ProWIN (programmable wireless networks) grant CNS0435370. This is a 4-year collaborative research project which started in Oct 2004 with the objective of developing a prototype cognitive radio platform that meets the requirements described above. The network-centric cognitive radio architecture under consideration in this project is aimed at providing a high-performance platform for experimentation with various adaptive wireless network protocols ranging from simple etiquettes to more complex ad-hoc collaboration. Particular emphasis has been placed on high performance in a networked environment where each node may be required to carry out high throughput packet forwarding functions between multiple physical layers. Key design objectives for the cognitive radio platform include:  multi-band operation, fast frequency scanning and agility;  software-defined modem including waveforms such as DSSS/QPSK and OFDM operating at speeds up to 50 Mbps;  packet processor capable of ad-hoc packet routing with aggregate throughput ~100 Mbps;  spectrum policy processor that implements etiquette protocols and algorithms for dynamic spectrum sharing. The cognitive radio prototype’s architecture is based on four major elements: (1) MEMS-based tri-band agile RF front-end, (2) FPGA-based software defined radio (SDR); (3) FPGA-based packet processing engine; and (4) embedded CPU core for control and management. These components will be integrated into a single prototype board which leverages an SDR implementation from Lucent Bell Labs as the starting point. A proof-of-concept demonstration board is planned for the end of year 2 (Sept 2006), and several prototype boards will full functionality are expected to be ready at the end of year 3 (Sept 2007). Copyright, Rutgers University, 2005 Network Centric Cognitive Radio Page: 2 1. Cognitive Radio Architecture & Design: The network-centric cognitive radio architecture under consideration in this project is aimed at providing a high-performance platform for experimentation with various adaptive wireless network protocols ranging from simple etiquettes to more complex ad-hoc collaboration. The basic design provides for fast RF scanning capability, an agile RF transceiver working over a range of frequency bands, a software-defined radio modem capable of supporting a variety of waveforms including OFDM and DSSS/QPSK, a packet processing engine for protocol and routing functionality, and a general purpose processor for implementation of spectrum etiquette policies and algorithms. The proposed architecture along with the associated partitioning of design/prototyping responsibilities between Rutgers, GA Tech and Lucent is shown in Figure 1.1 below: Figure 1.1 Architecture of network-centric cognitive radio platform In the original proposal, we identified the need for a baseband and network processor board that would interface to the RF front-end and allow dynamically reconfigurable software and hardware implementations of multiple wireless links supporting individual data rates up to 50Mb/s and a maximum aggregate data rate of 100 Mb/s. It was expected that this board would contain some mix of DSP and FPGA blocks together with their required memories. At the first coordination meeting in 4Q2004, we made a decision to avoid the use of DSP’s because of the difficulty associated with programming these devices. Rather, we decided to use a combination of FPGA for hardware implementation and embedded RISC for software implementation. Embedded RISC cannot match the cost and power efficiency of a DSP, but it was felt that ease of programming was of more importance in an experimental platform – especially one that would be used by students. The group also decided to aim for tri-band (700 Mhz, 2.4 GHz and 5.1 Ghz) capabilities using a novel MEMS device from GA Tech – this was viewed as an important flexibility feature for an experimental platform of this type. The analog front-end would also support two channels, one for measurement and one for data, with bandwidths selectable in 1 Mhz increments. 1.1 Hardware architecture: Even though the prototyping effort is focused on an FPGA-based design, we are also exploring the architectural benefits of custom integrated circuitry, primarily related to power consumption Copyright, Rutgers University, 2005 Flexible RF