Code Generation Techniques

Optimal instruction scheduling and register allocation are NP-complete problems that require heuristic solutions. By restricting the problem of register allocation and instruction scheduling for delayed-load architectures to expression trees we are able to nd optimal schedules quickly. This thesis presents a fast, optimal code scheduling algorithm for processors with a delayed load of 1 instruction cycle. The algorithm minimizes both execution time and register use and runs in time proportional to the size of the expression tree. In addition, the algorithm is simple; it ts on one page. The dominant paradigm in modern global register allocation is graph coloring. Unlike graph-coloring, our technique, Probabilistic Register Allocation, is unique in its ability to quantify the likelihood that a particular value might actually be allocated a register before allocation actually completes. By computing the likelihood that a value will be assigned a register by a register allocator, register candidates that are competing heavily for scarce registers can be isolated from those that have less competition. Probabilities allow the register allocator to concentrate its e orts where bene t is high and the likelihood of a successful allocation is also high. Probabilistic register allocation also avoids backtracking and complicated live-range splitting heuristics that plague graph-coloring algorithms. ii Optimal algorithms for instruction selection in tree-structured intermediate representations rely on dynamic programming techniques. Bottom-Up Rewrite System (BURS) technology produces extremely fast code generators by doing all possible dynamic programming before code generation. Thus, the dynamic programming process can be very slow. To make BURS technology more attractive, much e ort has gone into reducing the time to produce BURS code generators. Current techniques often require a signi cant amount of time to process a complex machine description (over 10 minutes on a fast workstation). This thesis presents an improved, faster BURS table generation algorithm that makes BURS technology more attractive for instruction selection. The optimized techniques have increased the speed to generate BURS code generators by a factor of 10 to 30. In addition, the algorithms simplify previous techniques, and were implemented in fewer than 2000 lines of C. iii Acknowledgements I have bene ted from the help and support of many people while attending the University of Wisconsin. They deserve my thanks. My mother encouraged me to pursue a PhD, and supported me, in too many ways to list, throughout the process. Professor Charles Fischer, my advisor, generously shared his time, guidance, and ideas with me. Professors Susan Horwitz and James Larus patiently read (and re-read) my thesis. Chris Fraser's zealous quest for small, simple and fast programs was a welcome change from the prevailing trend towards bloated, complex and slow software. Robert Henry explained his early BURS research and made his Codegen system available to me. Lorenz Huelsbergen distracted me with enough creative research ideas to keep graduate school fun. National Science Foundation grant CCR{8908355 provided my nancial support. Some computer resources were obtained through Digital Equipment Corporation External Research Grant 48428. iv