Datasets:

AWfaw

/

ai-hdlcoder-dataset-clean

like 0

jpidancet/mips

rtl/hazard.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity hazard is port (branch_d : in std_logic; rs_d : in std_logic_vector(4 downto 0); rt_d : in std_logic_vector(4 downto 0); rs_e : in std_logic_vector(4 downto 0); rt_e : in std_logic_vector(4 downto 0); writereg_e : in std_logic_vector(4 downto 0); memtoreg_e : in std_logic; regwrite_e : in std_logic; writereg_m : in std_logic_vector(4 downto 0); memtoreg_m : in std_logic; regwrite_m : in std_logic; writereg_w : in std_logic_vector(4 downto 0); regwrite_w : in std_logic; forward_ad : out std_logic; forward_bd : out std_logic; forward_ae : out std_logic_vector(1 downto 0); forward_be : out std_logic_vector(1 downto 0); stall : out std_logic); end entity hazard; architecture rtl of hazard is signal branchstall : std_logic; signal loadstall : std_logic; begin forward_ae <= "10" when (rs_e /= 0) and regwrite_m = '1' and (writereg_m = rs_e) else "01" when (rs_e /= 0) and regwrite_w = '1' and (writereg_w = rs_e) else "00"; forward_be <= "10" when (rt_e /= 0) and regwrite_m = '1' and (writereg_m = rt_e) else "01" when (rt_e /= 0) and regwrite_w = '1' and (writereg_w = rt_e) else "00"; forward_ad <= '1' when (rs_d /= 0) and regwrite_m = '1' and (writereg_m = rs_d) else '0'; forward_bd <= '1' when (rt_d /= 0) and regwrite_m = '1' and (writereg_m = rt_d) else '0'; branchstall <= '1' when branch_d = '1' and regwrite_e = '1' and ((writereg_e = rs_d) or (writereg_e = rt_d)) else '1' when branch_d = '1' and memtoreg_m = '1' and ((writereg_m = rs_d) or (writereg_m = rt_d)) else '0'; loadstall <= '1' when (memtoreg_e = '1') and ((rs_d = rt_e) or (rt_d = rt_e)) else '0'; stall <= branchstall or loadstall; end architecture rtl;

isc

5504bd1422ae6594e67f79a9f348251e

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_hdl_node_user_params.vhd

-- File: dyplo_hdl_node_user_params.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic�s maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package hdl_node_user_params is constant c_vendor_id : integer range 0 to 255 := 1; constant c_product_id : integer range 0 to 255 := 4; constant c_version_id : integer range 0 to 255 := 1; constant c_revision_id : integer range 0 to 255 := 1; constant c_input_streams : integer range 0 to 4 := 4; constant c_hdl_in_fifo_depth : integer range 7 to 12 := 8; -- specify power of 2. FIFO size = 2^x. 7 = 128, 12 = 4096 constant c_hdl_in_fifo_type : string := "DISTRIBUTED"; constant c_output_streams : integer range 0 to 4 := 4; end hdl_node_user_params;

gpl-2.0

2761ae9e0e9ce208d103e3d05c5430c4

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_2AXI_4CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 2; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

a2b523e4f4fe0bf9e574e95236935830

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_write_fsm.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block IHxkGpWEInM/BoGXBAEZYpVnkSCZxZAesmVubZbyazFANRNV77NX7ZWE14tZ8Vps711wDoFE4h9i YKyRsHC08g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block esWGwXLncnFGIJNJq1TkZqEtlK/5WAzC5YCdzQO/sEMt7GtUn3Aafmhyi7Gg9EDyD1YlcDejtAAb A9W3URRYM3i7BJEEdGsKsxgPAmCZQZg6aAg2c6Yt2qUQcQpvHnIEMVcHTLpZFSjghhfM32BJO74Q JJ2dv3HBI3rrE79B9Gk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block klKlRlcF2S9UDloyNnX1GmbfIQ91I6xYo1PVtUDOOm+pWA3MfuIMSPwLvva2EGYe1Rz9IbHJjc2X G/2fmlIv4YxwrmHDBDMFV49NKL++IkYyJQON4uQn89mAp8yamMBAcFtjWevzNaqMNDN44zT5gqj4 1s9BvQuhf5+61+2FggTpYcjc6MT3ZIrYI2zonWbBbQjj4UEbqAj50hfGdf7bJWahEX8rl3fFevnH y3yCfDfAqpC7FPiZa1C6cM4RjWJcDsPVq/BUC81rjEi2YXzinXxiIcgjgpbKc/b6rVCVB5FyiJXs rqn73+v2LGPsbyps4SDO6etlFQJ/isrUFQ6liA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block lzn42OFqzH2qrEFktMw3FzVLGgQNjNCL0WHRTN7bE5z9tGMqYAQP6vbn7uFfq8Fce8Utx1s0+fDV ii9cpgCXbRWp+2G/0vVDPBMF2fakPjsKm/kXhRYw0jkOgzMA/AEwIiT9K6QWrZvMPTF6kwkgqOgN Zf9Pi1xYz2jq6JpBlLw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ja2I0qJeK8roO+WnIy2/3EF7DFi0yP1wJymY1mZoaBjKAxi8SUjqa1oYuWt7pmbWPs1bgaODMXdE Fvntn2/dhENJ71xMQ3WVsalBhJIe05w5hdql9faH4dHwTp2MSSlqPH/VTdjd8hCMMazAKXN+8n0v CF1z3XVppnVhklMbirazKUveSBLOPnK9HDEtKWfHeuivJ5Y54b6ThwLt4rLZwIWveb/4A9XaMzSQ 3pJB7rcW+YWq6BYWsp0VHLtJ8KBdHGHkW22mJjxc27PHDf3EnQmPvDVPZQfmeuktDvSZmeMaLVrT NWVbaZUTrULrIYwihFd/2MpUQBciOSYEqX9jTA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 43760) `protect data_block qqY3BZOjCg+XIbpBNtsosJwLNmXTDGqIcjWXovFSuFMhlOM0eGGmUSe1YrqR+GQ3/7kIZ9XmDHIm QMzGTbHqWSDQGkJU4BKCQ6mvUg8pLYomrxpp60KO3vv51AFKHHGsiF4bbaKJ6Ca9V0byeZ9+dnWR 9DnVY5bYzaLRUa7HJYdfthd0sgCwt51z9NWbCJX58vKbwowXVrHfqUpbH7kfjIVKdm1RC8+Xsucf OUw0bj8eCJbLRt6fyp20t6C3NRSlHCeKpXk+djXA1jKRBromTmQ6BoF8a4egmGpaECIQx/v9HH3Z 5InVZQnA415NfICY+AyTWvHBTayxQvd5Z+BDZKmwP4eOo9uZYeJtZrB1cW+YaYk9k+8a1vgNNTCV ID9L5VqZLbylVUuJ/0mI51NIph3Lgi4raBcdkTAt2KCeDE1x2h7wkxDrvnKDlCnq5Aqw8mAVwWhZ gJTyRvVSgElD8TiBU1AezmSTY65MET/oVp499XZsFajGoUeZjyrgQ/d8gr9DD/JKMykpEkUj8nqv 5rxURFV+n8g4sJLCluKJPB7jEr8UXM95+3q9Zqb4D6W0QZrkSRNLJOpoUOfIDBfTKqMUX/hnw/29 RUttBv8BMGKy1Jgip78qhGOohjrSaRnhRIAvDCzJopuV5WY43Ig98A+gdI8RwLKQt1Np1qCPt5w0 QE4q9qNK+v6ltD7vUb3SxTPDKf3i3Fi1zF4lnILHteMz+RqKMq8N7imq/kBW9bF8XAnRf1ds4L16 kO3/WvZUeIZcNV3tEZhMMTT0XV0DbkpD8KUAwKuj8KUdtLZLa4eajM1lb2REcre9ALW8xqW3035j vBEqgSsGIcv0Q+UpVWyL0gasvwWpte0+9oeYzpIXDKJ/ieYmm8hg0Y0QOCiCU9Px+vTG+S4AbaMt l3w6ZLU5+lPc6k0jHq3sbH7zu+DGBCIiYsvkXlMOQXNaXe44MZhz4d1jGhQ0J2TPp/GW0KZa+78r xuTCqbkHTVGd6sp5+t+2LO3TNNbQCf9Dzdn6HOveiAfAfZ0NFgmFP3CsA1xXpd563QrX78lqdzBC Z2yLKtp3vnP8Fll1snKN4cMqn9QiZzjsLu5/V6ewx1iaNdJw4QgQhxemPm/XJD05aZcKybG2EyIg jbHWwfUmhrZGzTHjPU5U23zkBu9vkD+5/KW2PMr8KKMbndKyedq8eDEwI+oTamZZ5vW5RQR7OAjB cv23PPaUdrUDFsx8d/IQS+p9NnccS0qu+r/Rcl1aivFVnXHVWkWyhN63MRkTL1ctSdDcHepDx1qV CE5ZOAzmUlU0+Q9RCxtvTBA6kYZGztsqOylqbfnyP4vArHz5IwfffdWXAC7E8cCdauhBMmx6SGYa HoFgVEe4sSbqPoLQEK94ng0Fbat4ULIOcd6tTBndIg1HNc30I7oTz8lBAXD8wIhelq1ToBJpJlcr 7JbaQIvi+8hu0Ih1oHPaNkkeps7MCdWFQtMuate85wYZvsnMHNQK5USB/2IwKDhgLiCn1zFv0ofY YaRhW5YG74mGS/ZbUZhJDlDuO9u1HvCK/8POG77BEim5QIoixgNskE3UEoc0rq6Om5DCQTI8ejY5 7YzCrQs0B7QsfmGgUi/lhVF/irHLg4XVf2ZEd/b0IpTToHTVld9YeZW4GlS2zrwbmAGEWS7LcBpE NfIpJnWIZI5xZeVV//DcB6VZjNAjfz4JSMGB7nBOrmwt+9CCE/KofxyIDUnsfY9SqOItA/A0asVy 0pJVIGmwOmXYreGrvJN6DUtxeqlviwafQTW+Sst+MVR+akl82FqVaqQyywq9iBdQx03kuheYKs8o CRvhhsv5tKkfCoCqcsFxdCQ5qmgTiw/VwAP8MV9iNSntrZA4YdQ4x+fyixzo58AArwwZ4mSb55AJ cds6w8TE1IjKZeSQvss0RWjDqxE9svdlZL7K6sxLGVV5L2v0kW9ZvJj98DnhHdVoSRGMFmZYKa0/ RF+lQDAlawc2x1T6yAIX6oVNpzB2actIbbzCak/ZzIYSo+J72AidCo5Lj2Jmd6Tn53Yj6q0dqDVV figtQ0YCgv9iIhXD3b8zEQqnGmGuPG8Iu4wGz57lU7JkbegWoY0Jp+GWU0JhtGls46PIQCC/bjel KeSRceqVc9SfRx6x4nV/EvaL8uuOku2BXn8uKtDtnimu2YkxmDcl3+HS9En56IFTJakElUMy2Xaf 5ImCUAS79nmonmKT4k4jUGn6QZwKuM1hz/+Kj2ZifY1WbFxovFxCoJkycSp5nZ2bG9+kdckJ4qso yBMSsLo/7OVRj3Y6vg7SryoAEB50txqGTiS2gfbRcI8DjM9F3IRbGPAZaVSq/lMcZEbzOHtvdWXa IRwo4kK31U65p5H1oVcld7YfUvNWoiL0WSnqhuqVJt33Gykw/6L6C7Od3kKl2lvwnqOfnkv/ESI3 WW2O4PMRTfd6MTfQhQRa/1oCjoPttaH6JwNIVArVjW70yeBvFfwvq+7xuDo81/L7HbTaSHgTzAdO qc8G7VVfdAzYb8P/9d4fSS8kuTas2EkvZQ+rCkscNeuqZUfoAT0v6+m1bKqgomaSD2xYWCvKW3eP gVWyRiavpoMd7aq/eNHw5Mxlm6EXx302dyyVpdLbUdYzqIyv9uJCtYaTRTbicLOlqjMtjluhnzDB EzObzNW+Ndho73smnBrOTi34MoRHy0DOhnGwxiWYJVlcwBU/PjZNVHjwrnynPE0OdDGLQkZvRPgJ VO+ew4KogO9obMa0oAx6BnRScs79FOhkma6Q8btubGdch9e/JfYDgV8hAcrnTkiG2uxxWRXogDt8 sa2OlafaVKlNLfSQFa2ccKlgwWcusslYKdIsibwbUakqcbizE04LIngN/stRoZFIL3o8N6ia8nyG l50+VKlaT9FTKtfSiL5HwZ93DeUmf1p5MFf2ZyN1GqbVKLc85RveXzIQiFqDwA0gBo68WkRUWRB3 im+7g/V4HxtyzzeCp+82ypAE4ruUlw61Sq2v/r0jhgaMpc1UQFzqHz4EgIhvQ/MNWtfh26gljJL9 pS0Rl/uZnuU9Y9DmL3XIpliNnNj/lGsApzZe4ZD7PK4Fjc8xFcXVZkAsxth5Yt79KA7nNIKxJWXl uSTLanu0aHB7yaiTe2R69in8KDFP6EzqaLjB/6KspD+SRiXqerj0qW78GaSTST1keeGKVznUfx/c MpqAYjBHFO2zSdH3A+swfauradWKLZ/tWLh7H8Oxg2ECJLS4a9v4Tm5pyiqOU+a/QAw1QULVjQaz uIXnmc7H/fvVMmdN7LsLO/60GcVTpEIf6hHG2gLL8aSRIkyw5U8U8Cshv44jgD31aQ1RQ96ebxwZ rKiOPPZ9pt5hgGDKVIWRLLKnFnkTYc5KyqCvw83TiRPfQx+NxfNfcPYuKEoUIxwQwpvPEnFN+M44 hrHgZQLDsz7Xsi6mhU8YSngkeI1aRsdPnngYXklT0ylGbMljGsqJQW5D/SJCLA/Gew4BfcjXm++K dac1wzE4Ic02Vgcx7HqEYQfF06l/53UqLlo/U9wvH+GqswQNDXl0Tz561N9cdxlnrAdbh7WYwjF1 lSSIdfMIFMgly6JAsHfpDuJWosKpoGZIIeiyLfAyZTSgF4cqEP8Z89ESiXlkoX7cejFO7MyjmWZK c0XK1HwH0xddPr14OPRQTFbwQg9IhEUtLyPANUF/5D3W8DMmjrriGFGXyhnNKUo2tKG2AD2TR9+I cK11zUSKue0N2toSd0wAc+T4LrP6XbDwd79fEozobuxllxRA7WawVd36m5kVPlIWysPAD5WKKhUQ M1D+8m8OIEBX+CtwetHrwBXGNeBQx32Cvc5LxTLYfLm80f/0IFnPKTDaFZ0pA0CZpvj6U8tJfLWD G0ubEavgxx5ClfuBJi0l24wOFzPsFXiUz8Dh1hUaSgJ4Kd7uY2ijLk0mCnSAHOtDA+KOBWQK8LhY 2cDaXJcrjSWzNRirWaAVjvj4kr4B0SyW6qzunhw/Zp124O9EhHyAkyGEDMgNhMyI3oPn4FX4E2J2 AGYgZ4ZnRPc6hnJvdzIgz5AFZcQO3CUDbaGop9R867SMUNx7jg81eL4yAlXe022fugNw72tr6w4m UnWGDgw+ewx87UA2tI3u4WqWBaDXQWpQEGaBZ3aLsmq5wnnlezRBeRpWlrAsE3Rxu51MSq/Ut9Ku 3T8HG8aKKYXwXZkzMlrEWcGAX0d0BL8DF1DrMFPgrdJS1A/QGtZO04Mh7YjEt06q7W9r2p9HJ+oK HcTr0wOqCOr2lsIJt6gY98CjpxEPU4YTYm+XiOByw8cwkrwNlxtp66UjHc4nrFimsX69vanV4UNb 0BoXH3PdjkZo0lkU7bE+gHHNq668vyGn7qxUMdpAEXbRAX2OETbJxsVp/JsI/nU3fUxus+5go/qB UD5c6t0sLLcd1bA99792ZbQmRQixnVfmfaEfLhGSyHixBFE3W6M1ZZxiE0YXf7xJMbgAj2JPWO4d CUeaRZc9J0p/25IhQCvkWhWHoOdQvEdX6ltxWt6KtCI3pX7tzar3VViqCGBOyJvVaWnVvA4+tmYA gWkt+e+3g3bh/kdTHLz6XgbD9VzPhtaFHDYyXNnLOR8oqP0MA9xy20kyjJl6TNwgi9UbXF7WSwta nBkyVqtqxMpb+zoY+GFdOoqlvntF8TDSwE6m5YpyS2Ctf6q6a2M+B/m5ErPu+BvDPb3Khnu1qcWi 3xICJat++azH42orxr1pdz2o4dDWyxqfL25xziYKB3R4WDxQLLT91hssIbPUwbFUsYL2+nHsza3g pu5SHrWxiue+VmnMu3/VOMwqkSg6hDY07w7N2CUDiwnQ3dBQUSvKyLHztmIBdVVMxFSt4sDv3zwE AqHIABjHUAxEVInKJ4ORY9Iis1OXBIEVph/xnoJD8u3e3fFAsZFU3mjkvUbEwdvEWTDReS5qC2u5 0KuZoMmgDefgfiFZV8DljmrPDl/eOKwpBg6NM9lFmpAWphJMR/Wg3gKdEOythDgjWXlk/MLUvBFf gZKAbjuHK7hP+eYgtZmzNvR9FxTeLUeb5SAYZiRlRymZ2zQ2NHl7fnV3LsVTIMenRYqBWSHuMAuE xj+9Kps+k7aHg06X+7pLR9ALrFnRPpWWy2R7DWO2+83P1pXZkM+8w77Uu3TJj6TiV3ShwpOJgVN3 jTxI+3mhuusN7k5hXkt8fiLQxw4XO7PtD2QunJH/qmicIgEzvYwmsvXRn9kg5OyUaD5YvxuajMTB r/xLO24I4jGRTK9HjHUS3UqCTTNTC+C3Rqfd0SeqC92dXn15U+ISPfBjFAYMuoIeUl128DjWr1eV ycITq19k7oOkONAWMCLIz7uP0iuksy7G6I4IEYjgasGF5i8X9NY//KXRLm+0Gz9nXrr4Z1GfRWfM tNLsHI9y2A3PBDqJGEfWmAmeqBz+BMDL/Y20vkgN4FAPWWBd6ypIKcOZTbSlvzInNZrnAb7GSK5Z BhnAobSieJQe8sc7q1mXh4pLPbN6Y6nTjITGnzOr+7HMNeUSqbHmzdSQPzqD21Uo0rZYAJYOMO05 C/Vdmogu1PtyfjtdHBBFQHEv5xOSRSNy908BXsgRPsZGKM/oZZPZpf7Z1Cm4600KvNETqL5D22gZ RIEtH4DrjOaMNmVz3QOr0yk+IGrhWBBRhXazkUJje/Xp0olsJub0eonqEyHs1K7/6PBvOQoborpd HTbbiZDC3Lh9NjLg6r6HqtsglaDi+ieQ8xu8q7ejJc3wTd6hxjCHqI7hLojznXsvp/CHp4g52O0D qta2RRXcEKF0mXWP4KvO8z1LynCr6/mFvPXobxAtGPpP18NfNkTdlw4HwjanF8e0/k5v3kImCTWS Kqtg1DvUOBzp8oONjWFa8mT1RaF/v2sW5DibbhqUZ6fKTLx3ye6S+m9HCEe9wq0l9QGNsqWcZkc2 AdYIaVVgTl27mDACZ8jRyAxDW5iW9kPbFDD4wGnOb0YbfEjxlErjXvrqyesGPUPydf0o6NA9K/tP LvdabXt2cTSEKMgpI4xXknmCvKarEcJS+5vwEaie8EjFjIrn8eNs4DjsGLmczvVoeL1+eRRprHDZ bcEKyv6lnuo568KQ0UOSzTMCzxlTDpJhgSu6wpxCi/2uMzDt/lyFc95ogz5aKVO3+btwlE69acW6 xXrz1UJR0ngU+zOy2almkzY/yx+oYnI0KJ6aetvawl9AunvBARkFboAIUws7dgSyRJX0rPr1gsim or4utxK5cJzYMPZ56uqcRi407M3hoNJ/Vzav4xiR1lX0bFDlGaupj/xAxMLZqWpKQQC9if8231aA S9KVhHtdj5ur05KaKxrdvYKc6oGgWzPOTM4WcMQm5C5aqyHrkTZ3qRKbpnE5802pG7iN7ipZXlOm Y1dCBMc8FTksQCi2yiM2GHKv20zm/P2kXx4y0+tSdQTqzZRJPRXPHZehnBIQXL/Uw6Hfb0Zw/qXL I+0Ym/tzgpcMiHxQ0m27v9o17erQKvDL8+7SqwGQ0y/o2IhhM+bSlaoq7D8CZeH9LYj2+s3Zynk6 YakXkqLervu90C8+iBX6aVhRknw1n7qwPNdItoXTxK5UNAs2exi9+DU+3kREeM+AkGoeWp3h2YEy mGe3u65OQnUyIxD3dQG6REo1pjvQooEWb/QlBzbX29wUFPjw3UANiIAurpvtfo2l3y0G2IvrDGR9 H+GFZ2m0CEAsMS2/BBDEcSqmV3xOGsjDAbGQIBrdLP9NDCbVjbKmOewkAYmg4wIqQVLl2Qs+5ZdM f+FBHJL2Xwlv1v3u4uPlhXwJJzXPmxE1J5StaCRZprqWrD9Vl4ofs52z1j5G2W0Rgn/GFoATYNhP EBycznCZGKsza3BzULhpXFAv04VTfV/T5OBAY7X4DBfeAFSvE3hSk8lBpC9p59EVEFoJoJh4pKvV aEq8ZMh29/GgnVRzUXC8KKPAg+NVwM2S/uA0uawjmW4iOy+1WJqJuzaF71BjaSM2JduSO6qONTP9 mChWu7h2YbOVq89swMNZnBjx8Yj17JOGPIKmvVSUvRkuONzr90VQ/zqpJyG3j5jTXb1HM6EnTneS MBruQ64/J3BR6z4ShFvWdjnM6wnJ5v/N361Nb4RqTkBDGyHy3sPrcuqQeHjSs9TMohLyuFkZplOf qUVOrSPVICQ2UEG8Vl2Dd27phVtqeha1zZP5yGvpTFuGsJhykYMRqpHh3+5ykyjH2PaGjCe04uj7 zWttliovC48EiR4EKLSJj9FaAvD78RFtN+3U9zwnlrAuzUuQzNRBYe1wfgJgStFjrxyEmit41UQS Yf4HLwP80OXrDP4yHe4p/vgZAQZcVmF/3xxd5Xadrfge1Eo8vXovHrPw06L5HTRwH8UNlPTPyVHd paVOLtvDfeGh6rzTnbNHD1SNQJ0l+kNGrB6Jozr7nGxwJdgxuFxT/uk5U6IWh04Nhpq7kHghclvi VkwhdW41FWXvZA3cKW+i+nx+pwjbnGlHFPg+NGKThSTiuPQPFWzHAop/grXhBBYD6UEZtez0i5XW NypYXpI+zVHy3nRF1jxJOg4drMjD5K/c+I3F6LPcqB2m3EQa454vE+lcVeKnKBjVwQ6184KiZuZ5 TU4jrXVcPKZeNWO2YkQq/Uhdflta2PSC2j5arj4DKcdCp6F5ujc7LAEIYt1aOd7Vx8BrcUt8LUqC DOpxYIGG15lUTu6QCl3FvzFdg4BYJDaxbWOIDaH1qVVUKF0gNZWxhjMINFj6xmBK7jFznXcd9Z4L 2rwqmiAtL/aLPcFcasXmvF8BmQnmBCSY/gJOtFfHMBHp3vn/Fem5s6lujxSLgdvIO6Hk3rfm2i71 HF3iFTL44p0c7JlpGSvk0gvtHDeVhRNmfP247Cql3aiedH3ezksu8t+37SyOcf/p97bXdroT/t/i +di+Wmf1naZu+MKHHtFTQDSha6TVAU6O5x1aYA09nUkLUhMOU8ALCOiFTKmHiQg8k3gcVfEmo08l Qx5X4nRamD5GtOw9m3sXwhXRX4lBFfWkBXcpAPBbat2/9EvFmSQ6Ymcds2WBEJg+9KOWdL24X3uW jrv3vjxdBRrzwm04eHNFQBxTZnLf15xGWEsBYVGay88YbdXAujgMCcuosunRCZzG47NrEx44D0LM uvnG5hTOJCXOVJDFmoQJ/Xyv0eg4IiGeGotQlohOHpQnTOaE9qm3ThN4pZu3NZOv8eIQLmjy4BYB jAAK6wEvzBer53GRO/iQkoA231Yl1mbyUJrUHClu5FLuN+346S3/hB+ESfUS6xrwot9inwuUqFXB GciCK1SS+BWPEirZ/ipb/TvU/Ton9ZpcH+fP7YCb/rJEnC5TvJTDDgf/XLIilsgprQw9x7q4f09M 4I4Kmr5jkJ7uLWMC4FB/0M73JhnXMszLFaLpH8oBzV+wo1Ux7SVZG92n4R9UVuIWz9wENdzCE031 eNBBBH8uQJNS5p9k9XGx0XV3EYp2YY5nTs+pdKswPBva2q5RCTxZ249c81mv1BjAfdzG6iXeH8e+ q7EpB3GhTs/jaeJ1rzWV20HaUo/jShEycDmcIpZTgAGnwa+Ii+7ZODlfKeiS4ExFQgCJkXeoMCSE 6mel8HEhQ2NBD2Q4d4l9fY4K4mNi33asaio81PyebY9mZR/dYe+nqWL7V1mrQqQDScWtkbaWGWvL V7KnSjPT94sla3Cmfxhd2LvfvY63+0Mx7gSE6iNPQuGMJOqtEi7iMb2pZu4prJo0ho/oaCu0N3s3 ruJkLv59jB3aSM+J+I1oyPB1aAYWvJK94AiP9BjNQLOS+m7hNFz1Q/2TQTHYFsOoy/JLTazbWf7K iHaMt9QZo7tFVPD7d/Url2Y0GnierX9saYmSlYySK7UXYIeET4W4DtQxS6Wa04b9laqeCNXZvQft RfarTyEl39Ehf0o3cn0T+EsYClHsgAj6D8gBPA3CKcFZUsjd0HuIaZOJGk6UVss3IgbYkP1a4Baw wpDUQb8nmBJYVCamPULv3DuQsXzSNu89+vsirg1hsAP9VA2SmbcvPHore9eYwoX11GXcu1XvlUVD fZHz7UqUuNEPjQt0FE1HtypFFTjz+mKjpj91AHI5eg3L7wm9M9DHChN93JxMRszMnDqRFVLrFU6d V2TEg+wl4i+vJJIhvUWcwGZoXKTlpU7JGE2X/K91NG4+hY4+fo8fEO31qY+mIii+3sOMmBZ858OE MCzk5PJJxb3++RNg8jIzp/BKWG7KjEP0cz7hFnp9tBJ/vFZDuQVHLX8DkNriAqZB3ldO6Shwipp8 tMEoeOYHAS7kNJloQIncg159O+LnoCYnUMzlsv7bpo+kqRpU3LR8lAJyRlprLAKZqgAvvHjPf9z5 tvGP+gdiBavqPVnGJmw+EhQV21H/XvNm32PTgYD/9QO9hUZ/eqNyHL3f84YcFca9A13sqZ2S2+aC U71EapGhq/2fmto2UtCJgUZXKkn+GDq3a3mxAT6OtM+rda6RFGNXGv4pZYwDcczk4XJRSnu4e8MP 5HFlINa/INkDWJ3sBiz9nTxsrHnhiGfesBmzjPvsCGg4metMapTOvMBCg4oSrW6Ln9D9v2uNZwn7 wEu+n97t4/01NaWbH+70wufYVXPDare7DP2hSBlUVriUfs60XsFi6oACXOT+LBhGaHcf5JbE+Aol jzWRQYxt6rDpw8gyScI/PZWLmC8lPg9K83THeFl/tSWpRJFnGJm1ddCAS3iPaIVdM8v3SgRhnMF8 LfLMUXeVeFfGecvrdJQ0twMIzEzVaE8EzW+tg7Q1zEEbQ+exxQoGB4oxxDyoMl0Kg3PYA5q56lPF 3AEi3JxWaNyPRQ+IWmZ4elGIFUa8IwGGppT2w7Jkxuy+lnuLLHN2jFpJ+ZUnly4wmjPJNEpXllAh qpVddttc1YTSrVL3lzR6FHmqIYT8reL1zCgHtHGJxxuzRX+BEE4SL0oA4oklEROls+2zTeI3sYzI WM9rsFGOuQ0/U9BzApKVV3KwaaKVkt34+o0+FtaJo2+e2crYL8OkiIiQUwhMciu37MJg1SSbDEE/ zjfXFzh2B43a+xYz4UwkZ813+scT9j0K4JCmY8GMklDg/85YWM7hIKSUlRpvcAwKjyaJG06I6cn6 VtUZQShr1MLRaY2Ykpnzxfrv8bXDU/G3ziF50G0TPtuQPn6TWnUvt/lxMdAipc8IfkjnGBTrLWDY 2moAg+XVSF5i6XBto93SJqG3OD39L3Nr7pJ3F1931ejvuZZHwio8gjIZgPOP25/61a69Zu8lM/wn zj9vW2pW7oFcN36hGbfzJyvKjRponZa9IgHCac6ysEc6SxZ5BzwXbwJRH6/nTYLIJiTHXlQe+VYT wi38u7DLg10GALduqqex8D9LHp3xyp/WepmOMNKRkeo7pusiH/wxLQ15kMLuekx9/cPM6e+UAtPa TCWOF5++P+H6pxlLlZqWamc82+xtkl40zt3QLu75uolhPRbKDWcDi46gqT8H9oXGdJp0o+XSWtcu Jo51b3zSDbW0hFRjaX3YsFWOWo4hsWJlyfKxmgX0iVOSl7Xz7gWn/mqjyp8H0pBmHgptiV00Ljy3 GNNcsW4JIHmqYRlO1M3mFVsekil/CtaXBe+aUqCIhgASrkXD5s8k7SN7Ed4GGIXe4N7Cu1JspKRk TmxMyci1Ms1iLnGz4KACFP/Cu+MFvppeumphHAbPasKArEQgT1ENWO5qtOvSGghNdBk8RhR4xl/S csD0TzCPwex9C6Azg/xoi9IPKlsa2xW75rjoeu0NbfQ20I2vsgRzIOt0jHulnoTPgWy95Wh3dLl6 qK/nYmENc0OpH6tGvocgLdLRtTn+zbmeLUdHb70Fg7wpqauF789vi/z0kq5J6ie0llXezZOjFhQJ 7YY8CCIbBc3Tr03J/i19nEa9BvkXgHz6FJ+CPoyMmZMsLZ5EK4MWYHG+fry+7RPeUEIQMezPDTcr 4v4ua2ASZqMbLq5zGgsYqF6YxU1MOQX40nxX0eLYZFCcCVbNqc90nPl2FMUMGbM9ZxDnxnNDrA8q oG1/tPeHYCGsv4GaXWF7WwkEmqx2xMkKfZIHGsyDSpeXuVzpX/AL81QQ3IA4L8vlrJSIa2/XanJH hx7z6eFh2NcQ0990IIqRDycCuI3hL/2JSoOTg83BYZKexdd44miqp7oNgwcp8P6+GC0zbjTae8PO DB6WgmkRNZwgX5Zs/ZCUVr5pd4fwPGpGUIZJ0wva4dpBGFQgyY+/3nrW4+MgWXYmrHt8vRxoL99J QYEkBEOq9mS+2THAwSLYhecqaN9MhACq3Q1Sw8GwOKBuU8UpzUcbKW1G3OT6yvV0huoxeqzSM00O DLgDV2i3TEMn10+vZ55G1gXJeHwa8C+vSJNfXQm2dwLIVSFt9JpxT1AbRNd9S1fzp47+IQZAHq7+ uj5cmWBYNYl2xSdLJEebIi1KqAr9jqjyjUpaPIL5+sPwbCHzY7rda8+ZlON+drxuu0gn4jb7v8zm swlUsIvWwTUgcwzsWrlcMjvu3utnUtgFbYd71KbjQoeesON3nOaUrwgU5lFfcWzOaXqyQ8A+TUDb nNOma/18Zi+DlCPzjzHYTmTSCvSMNzwZIgtBLHP2GxJWe6dripchP1Onl9/xlLfVyQHvB7uGDJMz ue+GB/xKWoefQOR2dn3C23P6y9uDB0zhgnOkp4Wl8TapDSmdMkOdtMNr61/uT3ASReqDhD6yTS26 NQqbLD43bAfxVpTqLDYOE73SWM9FLJ9cYnmE6E32+btBChY0H/Slu6t9//IcEfmZE4XNe5sCsHus Lym9amJALZifv4KEbGl4M3W4ndPKbl30Ng8viFDIxTy3MmhplZGaFgs5yVzEtklH6Jqi4eMxxWO6 fOkfGlONdutrzCn677fXE7fVimMr3SYibk+k/l+QK++6WX988hu0hsFoSz+HIljuso1SoSlFaESp CGWbFd6ZRCCnsCUDE+nYe5fw7YwPuI4vTPJ0GOyS+DqVutjvn0dOd2f11Wns9clu1gmuttUiTF9H gJeeHcluBMbeqcP9npWFLKHBaTaKibOBIt01EgB155sx2rBqUgASzbUIgmhhJbZMq/EY8Uupf54w Yeu3gTdOdZEGEkKLifw7MHY7JOUGrjgvV/e7kIVt3rJ9KvcJNJLUGmvkAJDW+mcn89FVIdis35vx +YRTTlZm5riTX08uEKTXw42FIMwCMgifkibO3gf6OoI3QJxsq8iTpIAlnJR5/JdJke2GWmQ2LcgS hDdprveD1mBsnlCJgEV+HEnz+gapFrYM1ks5FYIjjLJ3Zc/GekEj19bURIIGHujgS2FCCiplfyVr S5mLrMPKFjk3BMpfMOuYKvGPW/zQEZrk4ybRCIFhWc1M7sPk+5bYWKTm2Ic8tfz6oJNmR/LHf+gG cOT5tdRmNUcaiRFD00DfKsfLssW+wj8nqDFKbQtSEwxrp1ONKkemLnK6Q9F/CcIT0ZDFVX/9+ddw 8N/LGAy+1uWoy8dFh3ioTmZuMWYtAtIZuGYRw/qH+3xs9JmdTyJ1IfuB5sfbg6QoA+vzeZa2e9Hb 5y/ADiuOaj5+VYW58A261dTvufMCAgp6b+f0+Nc1PD13u4kR7NI5+spEJ65NLGUiSYjFvfWQap8r RmIZnvndSAg/e0wiuQ3fTC+ez8CnnIs5yNvWJfK+ppTQo1kHsmYpcWmbxTKEc2CTlimizvn9nEaO 3etbVS4sKfEa/bQoyPVfwtKg685lbhTYZe+ClwF6/djK3ChOZrVzBdUOvL8CTeL/lslouSmj7CE3 8q40RwssN4ClHhM5IJu1slOopTOZzuLs8UsSkBae2HEmtUz+bOIL2R0p9G/U12aD7LnLkcXyIj53 kRpnUVodHmGkOcLdnEQp6hJ3sBZG5Mg9j0frc/PsH3E4Jeeab162aNEIWZsqxXjcrn0dE+BtBG7T G9VB39wTlozDusmFnVN/aV5+/QSuPBaAMsHs8utpCJLmua8HXlm6kpMIMcsI+S0TwWtAXC4ttrRK Uesq+VNWutrg9/DZj7C1HhWryfrkqPa1Bf9oMD5bGmRqHb/PZdCtwg+QcKnkd0DO2gaD7uKP1x6W DItWxAfOjzGS4r5wO8NYb/KNzfZdKLx2HhHMMDQYs8VZoXFiuUjTdNRBEZy4bLCAPwbqIjMGuLJe gtBgztXQf45RCI4urNPD3iYfxetLOMn5lt4grRTLmjzZwSkHqq8pxWrY5+cXSw57IsfKlAZP8RrR UMcNtouOUmVGJFke7bMlyD2x7XM47CofJGdpk42XPLOBVM17Ez3VTPJ4C3SfawFmk6QUokkKM6+s VDb3pDUrodTjeMJi0U+ydQShK8KQPjWKA9eA35vYBFTIthcAu7i+5Ld+BNfHCvyPYbwEawLagUIv 7U/hdfq/Py4DKh/CRgc3VYFo3Tvi/5aUFo0a4VHtDl/6jE+JBJz3TSfuLdGvqDz62eGpEIYfjv/N gtTc4UlO5QTqTqfmTdvDSKjiEiv2at5gtQ2ov2hgaI6AZVGpef5LhV5lBW/LRBxERSs4kkJS5uX3 XT8mraEIkWLriH5T3ICxcdc6TnamgsbIDr7pqlQUeSDdxvFrBA42FwN0Z3qj1MjoivMpwT4Ndmab iInzqjyayPUmaoPlezDCdhUVEsBnNUTf1MAxxrxh85D9Sk/jb98wFEk7w8lMzqRKyrlDQVo1hhDM Q7PMA4UgcwcpUF9k2+1UhmTluDIWD0S1X8uDsS0ktr6XnYYFlbi/c4Iqf0gyWl4nHfTdL7y3xsv0 6S2htcuMVRY4CEKDYnQpOGwHI9v+ocHC6b6kF8Lk4m4I+Mg89deYvHqcSwM/sgZldc3g3iX4/ukG HsJU66i5DWI765yQ2q8K2GL0rN+Th9MDFmAtJEX/fawCrlOzbZvUKJZurAtB5DuNtv32Q26m9h45 eNdLDJDwBtRZNQJbbpBMJuCx6SIvm/lzXapLZR9Bk0xzdzC0js9F6fIbquZ7wezdcbmlRQdWp38o YHBS4YM4CzaoGwdygSbdHAJH7uyE3og9QbofR76iKKhiRCQsRSo445G9KmQN52aMpSBHLwt2lELS BjW2rUoEiKR6LnfAc6hPSn6G+qdDhpZzi2UJzLi5RBhY//Khd88qp2mxMCi8HJ2ZXtoNler4Lnl3 99Q8MEmb8G8vxFy5B25VUZFb/9Z33YgnEj9/2lrjh2VXRjJ/cxOXkNUJxQePnwGRpR3te1tqkCiL p+lBxDqN+BRz6xC4AlH0g3f8/eF2i8iXYhWeEpEZflAy5bnYoXqKTVLrVBTHWYaRPUjlviNevn5n LMPcOzybnYx4SkDOsDRAfmkOABghSPN3IbjONvBLXp/fKvaLTMteXbzR+X7EcSYagedJ97qxY97C H5imEQ1BrbTu02ohsBW1GbiKCyjZfKOzOkIwy0zPJ4jfJKkReferdiverlBqbVCkq0WuhWOATA2Z 7U+0NkmNEnSdTxwD6MAXmyeo8/FPZuLmNsH9El+4CWoHgAHkx3VL2LPdH2nQGq9XemcTCMFXs0OX tC2bvlxMy9f8lyg5P6931A3JrKCFuUM0KwuwSMNNE8IqMGht3x09mqzmheEIVz/MLBDxa9L6VME0 ouoAW6AM5fehFOJL5R5dUm+fMCrQ3fUb/P7QuuaM3wTt1KFOQ6s8ewv+LtUkEvMAtWfyitY2/J+j J6PtisgTWLRZ3B3zBx7NMYYdtJtNS7bmlj3SqhEJQwHOEw9SvEW/hAb73uOZ/Bhl3Fz4OrF10g6o dlNMaj0PfYDcEfb5GmyIWenAvXPS14v6do4gemY31z/sj3l4Nu+YuMXEEauLL+z5/DI2a4OJCCr1 ADyLT/Onga0YXNNKmsrcPn2KhofxjbYJGSXhJmMz8sIjoprDLxlr5lfWqygn8utZQEWT8p7F9i9U Hv8+6S9oGt0YPIBZhy42yP+4WoIEL4cVPvXv18y8uYBqg5QHZKSLkp9JIASWmVDvIxe/f++MkHZE 4zQF5KCTGYdHUxcJpFdHyxSdIOYFkpD6TXZfNMGW3ZIms14dpYKAo5ELSILr5YqnrQAZw7lvh9px wHSQMjFh7/6eaL4C9l2j1nfjvHAZLymVzS+hl1J6a2Q9ZKFeej2Nz75c3l4bKa8LqkRkQroTbR16 2A8ZEhDyi4JsUb7M5HSinbUWjDVcuuyhxjO2TUp3wXTvJ90iKC/cz/bYCsnBW0mpSMOWPekT9KCs We7iBCYDgGMDOFsd1wvJeUAuNgkHACBQe6CSvJWzlBBQX6oLckzWOtzROr1XiAoS7CHBqxcjskf1 oKNuSHyg4X3ni1MBOZvyt3gKl5WZa4Nmq+fbAs9kszv55FsAUoZ1T/YNy7GOdoeUiIfQUrBNCPNZ TijKqkJB8RzYjfCqaUKV+e5cNWZvpBxxw2HHZ7Jfl38GZcl2oAUTGfavhe0ENLFhvgeSY9WfWpBH o4/fc9plX/rrVeWl8C68F+2FZzhpAem7mMHRrfcYNxl0exWuaWppnz/3MKShZsw+SMQ7QBVbBHhd qEYsP6afMc/MmeMh9Lu2fYoTlyGmpPokk3ilt6PhxaV3q6f6yOO41tf/T9VOB8P9gx1gK9I1MCcM zMkfa8DjxfWLxqSFb7mbCRQLsnyeaRKcQ9bnKtYhhb3m/dc/d5v+gAHsvrPV9h4uef3FYW6zP/y6 +qDnnzPqgLGF9tYjfy463l/0OIxvAOV9z3QaEbBdzWbyQxBE3nM5Q081u1uKvKlSEmc4/tWqgavS Kb4fm/iy48MeM300hwOCSQQChyWTx5wuccji7nOl/hS5Fq8eUEPz2JYzpIlY9I8JWQCpLXJlRhS7 Z7Y6WnDlOTaur6C0aR5WO5yHWyVyC9xZIc3LJFipZ5CBrhvGMaZFG/EJnKX+s8WfVbugGff+18Uc yWfOalyCa0GkF4Ln8DTFY5PNYYoAC+nE6RnenMHrrHpgL6TLk1RD6D9lbkMmw4vvUJhCwn1PQxd5 dVJOPgB7mIQHH+Yzcu/2Zc4mIConpqJHURyFRuJvo/af4sRdg0xYNs2O0TtfGDKPeZ4zWOqBIRzX dby654kbbo2yKvzlLsTGvjmARyOZbidlGpxuIVuDrDQLKdSPus4ig7zpQJvqTNMnv36o+1rUxdK3 Ho4A8y/8gsW29u4DTjsFJkKGvXyAsleqTG9iBiWW+Cd45DIaXdzr1kPEwsUaKe2UjGv4lwZ/tauq qEIKYofL15KyYNmEgU9H6DOND1uh7z1qAZOWk2qT26HrR4g7I8Cca2Z7DbkpeSy7NMkeYbUhW8d3 /CeUq5iE/831uToM2KPntjPGsAqNYPbMJjsqLTleW9No2GapVp2eurmPePx1RgVAJdGVAef0SWHe /2QgHJR4InEZ6KUl175VxCfCqAtLbd/n22sxlIfU/WmwFYTOAYQyb/uUqBk5oTBKEehFesMKPk5C HE2SXuOLZIhIxpWXIv7pUAROlcq/ikk71rjvOHfiiUwvTYpYlz0viHvA1II7hoEzWMFTb8WxSKVi f+TPS50EZ2kLy8ohDLrHqtzUhcgovJNIXDOGPS7AamGX4rWh6L6PvkgaQt3l5m1BNHfRBhTBOIYE K4RKNIgJN8jCOEFdhfuLBKC0sFx2JFf7H35gLC3EaOiBVEBsIWA63MPYB39IONQrbh87cunyGGSQ d+LsBkb+zMjrsFHzzgSb7Hod+CS3G2hT9p+q/uu0S5nYeemksQfg+sAI37pX3BMdaTKovyhqLjhi Lm+1E7s0m24Fs5Qu3OuRu9tXCBDkCtf0nEkajb2OZeWdppPljjBM9BDD9MUFDleyTufdweXEeUJg mzeiDGJOJaadFH8P/4YdkzlUyx84ULJ4uSolT9uQFHcfVcFL3hOICLt9YdDX3cDTSvlkVgv3CEFt RznIx9oVHyhY3KGaa8Pi1dDkW4FnMgFO76kc37lBkCdVinAlLbhpbtNjf9be/VnR2KhjX7+kwUp7 dWkPYLSGsicIm341AWn+1nqf+pJtby5QM7sCd23o2fDNFdqEhuzomqw9dRPqsBNsKzEzRFwhmnus sFi11vcitvvToKyjgaCn3oGp7ZR8p2ceDc7G/OfkB3KavlMIpsFsXGKyb8EmRo6hcIB00MUn6Cje 6n5fa0DQaJNSsqYyPs1O0/RplU1HeK8HkSWdwf2icZWi8yOUQ8Q+duKh4jQiQm2hbW+lBlMbp2qm M/tGT4AgaCM4ms8IlzKD5sVYzIOIRKW+hHStsqcLDUe9INuNHkLmQZCFAP15T17h5zsY8XsRrJCa Ia+lZ4uo/0V+Wx+eGqzdA7X4v+rs2zNWd1huF+dtd2aXXxOCzZ9+HK4xu+PhLSQAOq/epqhInQIM tg1uB3WcpbkQUuOIwxeZuWBUFl/jay7wYqDVj20bsptMecZTF+CERfsxNr94LAn5AJX1KIsd9WOd 7S4ZfGnQL2TcLaQk00o7lSyUw1XbEmj/ZiQc1wTOZ3rlF0o+OQm5V30YgaXvZ+d5/Tm582sTgwHF 1Rp+ejwgn6fRLSDfxfq8W/5ZJZfIJ9s/bRTVSnIjnvKCCYZzNDl3tPOCt3TmWVAigXSZdcH2pYDg oeDUJ4pDI7M31Xo/tUIu5AhyXHvxMh8B35atIZNysdbQXnIMFMa77i+0Xa5RMeaJHOsPvu3ZsZjT IWCkjWQfmX59dIZ+98h3N26HATESxMEMAS/oyh9pvi0ALDi4DUmWi6E5V9WGgdK+i54Q/lARM79c um+wfHrtZmRA6Zqtbm7wl9QH7AEfKuunY6y6Q0DQ6mdUmrPyV2tbyNmr+CS6ZuHd+izxjR+jE/sk 3vuUrMf5ASYTwUNVhEW+VC2wJnXWnhuF5YGd19z36Oo6C17WBGiCovvcHe3jKTmoE45p9xnoPRt4 D/gBWD32keDc90Y0S1QDZMFe2OSpcCrKeqAfcu7IsKDTuWgA55FQ3mhi6jIqkFk60g2rqMTkJAuJ GpvkbA6odz5JCGygBnUpNZfZo0Hu3k5DySAf6YsFmOynqPqHm9852bjdaGYQkqTMrXSRN6VBHGbs 2NxF+B5ROl8IHZWCaBwm8J9xO8ROLmegYMDJgVjigJv1zwtbUVKwXwx0yAx02uyHINuNtgP6aQIR Syl17XNqidQfTuUOH0tOkeXG8eHeaJvtHL+9xwSOHu7eAMC7OeYXAYYFHWzW5Yfrl5adXN8oApXU xymUCy4dMM9+EZ0Ixmq3Weljmtj05KLRYtHlF+iVBKHmElFu3ysKIZFtZEZgpQ7rSVJeL7eh/r7+ XjXw29llrsFdt4fnwgg5oLJNItDg96hLW7jxypwJj5uB3Ey8mG3lrbaptFGpPuK/1YcEL7Fyi3dO jxmYirjIPVP65TOG/bojW2BMNRfuGOejDbDPLthDH+M3LBWagAbsaf9R5mrLcB3THfJAMkNaukzN gqyoJ4hSF1F+sO/GEfZ/0pXzFJvE6Lit7NKBQds0vRB+iJRmCDzw9dLfX6YpbMf2ZuMFPmOvhohS sYREw/yezTDlLfbtsqmpKvhB11tptUoZ11h9MsVAS4wJch0gNOKcNpGPPOrbF3TUOwPP8OVwdoC2 PaAOX8AsHB8etsoL5dTSyxwX4ZLynC8YKRDpfV9TQZrzz3GfTKq3ZdfrQhHIRSdSIoWNF+PM17Js Dh2IvDF2E0q8v72jsNAopvuCHJHErat2S6/tMhLrp79Cl/QKoTaT3lzeKKNS548CBoGVwiFuS9Wn Dy6HweXtcl1A/dmsgkKGP4q0q3aCsTQsozLM1ZNhxnqV1doBImquK5ZRkht5gbnVGuMuIX9MrBkA LtQ9UNsrwbXgcDwO+FMlWQ7AInp30Mx9tfNFIfkdCCEUMvKRfzB2TuZawZ/8odhEnD9hnCodnxpa 8Sg1QPGYNWgcH9APYG6z8kRZT7PAIw57CXpCh7bodVPoOcaVLk7JKNoS4ZTS4jHnHdf5pUSsGfxK WY/W+j/6GCntpSx0pjXN4lJKjBzv0LtFebBXHIY2TfnwMi6RV00hZqO3dmUbSr/gZv75s1tF6Eng aADjq43Bc3IQ0JFAMhReSxIjTwmPzjdKFrCTc/u73SiwRWtpVfVAeplVtUWjzguLZPgXZEMPbamz vQbCjViV4aOnEEjT3CGJLKPdeP5MRQSar+2LtLHA4jFa5IQw0LCyi/IWBL4Cthy4/RUDscTzs+bP uhCdwe/Y2omuNd50uoBEyikDwsnL2NW+8cAvd/IgZCup5VO/lGzodegVWsolZzth2rDMvse6vN0r F2D30RWStBPNKHgYNcRE5rM9A0y4dzg2xN7RI8XjCOs7Di6kyl+yOHdzrsC1MjIQgXFdG4Fs1N9/ 7iBS5RMknIxlOCPQZ/0h3f/yvTgiTeoX6k9NuqhTRd84/2yI/zfVRmoFdAVQQyrjr9eE9LMNe4ih ijeiBiw8WTAnRrUVC18SpVZPIrQY+soYYGtgPhsosFPw2nhg8MLgM/CCwZXaiDmI4uwXnub+mDpt qwmRGYwoAATCZ0R2pyZNwDj7fYudnozdaGDG52OkoCDsYvrR5ciPh8D50uPrVbEUsF0dE5PCzVdN sebv49l9u0D8TFunJ7sNLX/K/yYmaCJBRtRGNs82G0hwaqhDVoY/Pxz3m1cgra7fUdiqJog58VNm To6/DPGRS35F69grQwrCAi9D3VmX+25mpjt3bMGP/EAopPBiQ1JBkVtdb8Gr9QTtBm/MpM5r2HF9 z+JyDKBZwsdc9Ry56qWv3FLeqJNybFHnpHPFklYtbkglZr0PNRcLheXmCrkiVib3yPUZYwcS3kFL 0h7NGQuAmKMRprMRy0ypbpDEd2uNttIgn9rsq1RN+iXH0zs2OQ5mAHZUvyqQxf6zv+jtvHGvqpsF 6fPVQaoUIvYVpe1AfyWC9KHPJrlbKTAaLYVcJBz38OzV/JxUdoVjUP9/eTJc2NYjbpG8+9NBWCmw 6BAocQ+EpEreEWAQLTow3cBwEdDpCrBtGGaQRB6vxkVuLVsh/ZnPBwI0+nmyP7FPoChSuXPyjvCd XZDI8NN6NWoqVXD4/ORHKp25oyx0tmBw32jjnl4YcCJNChXXVF9BgEEkafDhKkAICrlAH9T3nRxN U9BzJMpWlekECU3zKFcMVsrfN3nAYJx3onAdItCNmzblwcxzaFa7wAP7aXFu9qCKzvQfAepAxOSX 2/F/oAVnkaGEDB42ZqJpGRE3pFpB+23qlGV2Er8rfNyw3G0aU9d8GK5yeHW/Ix4Y7FqN+pzb45eZ Ng7n0Cr0S/TkbSW0pCBQU5X5XtKxz69ey5CGdUGslbk4yqNh+mw6xbptUEAfErFQPWh59p+1eRmb xsv5fE8v1jhsB6uBFI1oExOz83fyKtJfuQfIZvlfDiI9lxF5g71a7x3mzjP2JrzZR5ELBgColPXg 7SuOe7PioD1ASCQuiNczuqIrF9jBPUfMoM4xF/S/LT43V5HiBcuoKGJxXLYjlJMDrPAHaAf4ovXD 5P+Eg9r8WpUHPf+2EfYdL40CHT9LnOsc5WC+I3iKp7x6Tw8ohlrXA1bFSjTad60zoD9f1YEvwt8Z EA5Si0rl410MQRaLgbyW3JM+JHhI8Dc4trZB7R66xMqWpKD/8TUW1accUPyAj0FgNOX0gWxdPXoy 3uXSh6zbIXC58P72eAd0+tDow2jZdEb+Xtg13OtSFXDBYAOflpZ/khhjt/HfM6HOGqIXAYMgydxa 0saD7XoqkSQs7UH4n1+/v38+ztQZ4wV+x8Lb3/eVQ0v01e5rAtsMHOxChx0Bo2QV5k15d7S19P6Y sb/n5gGXH9q93gFsFo7uyEjOMd1D2GIIGQU700IVc2afUNwGh9e3W/itwLzjEC3tH7NzJsxIXofh QZ29VcWwiZLxNf9cx4hdfIth9MAdA2IqXr8WGYXm7EUq3/rD24NqXsZQzDXLkdDDMBDdYSJuDkTe rJqFO97rqD8IfHN1t+rSfxQ2HmWdp98p2Bfyzs4WZQ/sJzMQIiGskwSUViDHLLhyTpp6DJ7FGBml jBZWRUO5pScVKSethItzI6cp1Xy906UAc52UiFfd853DSPbfHUDafmm2DmgNg/joryZAnV6z732k At+DwClWWw0EktDpV256HjEGFQtAKbInwXo9cot2aUjzKOErpdkPqEYAEoqZoRiTiGisIJ1+ygTw DaZQlrQ2LqkKuv/ewP88WSZp80vwRY2EidZftdbAxc5qSTUKX4cPoIyDdrPyxcFqpjdVUB7IUfWh E7mQk4Rbq161hTqPq9HKvWdH/JXkuvSR/Ckg+nCvtWFRJSAzsB3ZNji9v6QNBZ/djKwXU9C9RLNT 3r6O4yu3mK+L3xDdwMYuYNjNiVOT+YzWwHTddI2DQV1QZ9P5f3tXdNHjHg4EfeQWyC8x1TxS2rqT g7UhcwIsvuwqIZ98tX2UvC3IuB9JSMCxr524Uo/GTz/gVqWdA/nlrCfPnwiZuV3ZHFxtfqYmpV8n PhfaiDi4Qh1QdXrMaD+TYp2mjmLLuz1bprA21grFe8gWM9AuPYt1MCGV4k8xO5D41efFj4ywp1v3 FcdZ9eezZrclTBk228spHBDk4NWS0gUG/xp+VwZR+Y9VBxecldy50fZJ824vWRSiiLTGAGdHN6lk 7pOkR0iXYycWTFj3Izg8Vfw28WTri1pWqH5FSdJ1RvF/fdMMOVZ8iiG9VGUjDI5JM791SfNulXIL LCCo2mCoxvI1FzfnYMfNG1jLld52gxAsdM+yHS1LaL/SKrRmIyRpS0PUeRNlmz9E6Uzrje+wV41P eFzMhaHp4ZLNj4UHrIKbJQjxlAnjXyFsDDkUZs3kgKkW1hhN9Iic8kHWV+nL5xDKYiumAazZKtGD 657AZgTzDVuPV1fXadXvJrTBM4p9fp3LncPDns/S+w7oy/FMBfm6FQjR4v3jAS9C/LoFzx1+Dy+n D3LuNiqIDjusB4rH6EiMtAmDsDCHp8S1KoNwCrSATnlCKDFk7BDWOSFiic9i9IKzyEZd5TtUgW0h 9EaEZmEYgPIyYg3dEDlY/qM0vmLBYHDf5thSjvvw3WxTZaoi5Ufke5lnpanA630etUOYnT2Vgn7X u+eJuDG9jk4jb4c3NqbdTdFwfuBjw14qUsbMBGtJ9rKH7e6+CfIV3wR7edvkBeo9fEftSI3+Fcfu MOaLR/PhgJ6y3klo/euL2g5uA1siLxPoT/TZQUjev5rYKP8LNzWOsis1rVtkleWP+yvfh1zxytBL wbOJqpac8g0jFFr9mJ1/KI2q6Sx+RNU4+Aj4e68VdV5qkL07p5zqBvZscyIliKG10Ly1BIZglr8O d0OA0Zaq6QpQ7hCbGZsP5Eb3wSFC7uYSVCnwOEOV+0YAOGdu70TS4QGau3NlilH/xrASmGUIQ/QO myxKkQPdNXSAQlDV32FS3j7GhBpmLCKGTgEonBe+11U026r7YJp4ulpJbfpWz+/XWvF8nO+BQfFW kXHon+8fhMUUJQs1MlXYQmLrpTnvFVl1YUS9H3ltQfJyi0q4M3s3kCh55xkqySwDUbVoOBTjDtIH iXCBFw0w5LhECLZvNG4IKqNuNWXWtcpP+z3b0FL1SRErJFl/CYaZzRxT7M7NvVlV2Ca1R+vhqYCx AThiOBHL2T3SGvrBSCffOHTg9YXNIyHkDIDLtAQvMBjjTA/oZ6nLG7SkMpq6E0Z1HUuuDk286Y3D uok0MP4+kWR8XCzWCghrXcNdoxJd5yaC9guJFYwSy12t7/jrN3iJ8F6nZYG7RYVErT5c3cjKSmuK avS7j9ioIGTw7Me2KllahJeKvepjt0G69Mq3ATg2+uY0nNmxa9NlDKNZ1JjcrV7ikPCcNBlbQQIb 7fV7nlhdyBWXn943kLgezN29g1khSVcSQzMJ/Ye/g4ZNwTD6gd0stQEVb7ER9390MBZzXzmzCtJx LwUgSjHPsCare/x0UemkHawcTo/2tEgqT0uLMObnTk/QtYPQKvlVHW0vWkdA5IMEUgrulie+NkX2 BJBFUx4hSMI/2diqDBex+E208HR8QmviAbmiQiIDxuGNWR44reMVHaqBEHZ6aERsWSExMqEScEVG H3dGFZ7Sb7lzcUY5Z92JilJtgEKHgmsb5xN5jBEkqF6LKniBvS9XcfDzC9TzlZT2XVBCSkp3+wzo jHS55t+tUgg/EPPCP1nZpHf5sJECWtFKoSB2dXXIjiByvtv9cHzLqxMQ/38KFCII0ehHzzIsLasK YaEUNJ4uszx9FfEU3OOVcssoY0jAYbbaJws6AGSdVPdpA4GzWsmLsNunlK8r4fnquDn+iUj0pnFf 8SOb4cLmuKDMR0KYo12j0E0zzcRNu1YVLhXpCK4lWeJ9U4v8mV84SPSAZW/h3kFnJfMvUmLUO/Gj U32vLr+F08sEMXLmZz4CyV3MKue0x0sDZR1oZoxKLyQAqcmQOfKvksTy0gtMPh99uSPYqqEmbCdV AKg8Z///CcZVeRiMAL4cmytT7gpExaYdAU/NOXWPvBK8w2vVnL8xL0CN5iIpgOkQ9T9nL0+m81dU YJFZqEg2FKbl0QS4cSoT3Ug8dZXa32ewAV7XZgQVcYZ4W1i1YWyjUvIEvU3Lr5xQTayb/VlHVSY+ ybqECfY8+btUFTE2qgJ8sK4S6CIZpZFXHOOtlj6fbhK2zXetOCpazIG4Y+dCE8WvDuo6h3PFjcOM qV3/V+QbL6GecrUmawhWGAUn+jOwbGlIUvhyvirQgFwfcAltPu2YQHCTMtwOo7gHgGiK84ly0CmJ Mc58T9gZizlzmwsKLts+Txcf4amNDrgpxflyC5UVrCXt7uiGNHClcnJOEZutdqYnjJGY9AN+OUd6 J252mkv7vM9edFrbfSelvfClUbTkNC8ylx8L9+1tkZ9nttF2xdYex9XOc0YK+kQhKmu1Uc+JehfO IjQ2NKadFOzPsanq9JGbGg3UDu1ArJm2wlC1rWftU5syyav21Ud1/Y9TUKr16+9QlVFHuwYhDyqQ KU0zkdUn7fa1mqHJitcSammo+sy58OS4HNbo/IQgevfo8F449+N1YLE1fXA6fS34e/Cmh+isvT8t TUmJXqY8ksx0M5odolj4dUN7NIusDo3gqhcvvRVv0iUkfL+LoA4k5KuiTtApX9plyJ0gfTeqaDGM ceQs7ulGSW8U7n/SE6qUS+Laz64g77ztHTAcr7NyOwdp8C+lbpZDdLVd8jjZWJ5qSMEJxynVzEXS cdl5BtJhi7RSybq+L3cWKu+apaQhrY6K6VfmGHDRnmdHQ7ckI+F/vCfYOnja701spy6xTpNhLgjx 5c2RG63rUI/pKHNmZ1hQJLU4bys052CnBYiHHcxQLSrBgzBVz4z5ldydn6rdQ3KhHMLiMs0zHd39 3u46wSVZgXuTNZzKfxdt9CbsR71hv2fF7Tt2x52uP4jkiQvKxERoqTQ/uJbdvpEVavCMnhLoh9qe chZBEvD+EWYX9TX/98UtRO/AlqkRqnug4QND0oiXQzHQi/pXzHQX/O5LnX5QJIxy5jHqWsesgjNi y6h5s20EyfUx+XnJIXMWD98Gi9QZdgcZ8SKkY1r58sTkNf3lG73LMtHyIVA4xGYPWvUZA/pUCrB4 SHpXYWk5iWRdar4tWtURr7FNXg2NPzQgxjsnGvrXWOJ6B+NN4cZ7b1QBiFjh4fN2ekCY9O/mELI1 5YV9K5LjelM6ZnxbexKQvHXg8GFrzpAfnd8WGXmvj7ERhqt3W8MitVihnLgdQCc6u6KmvZpTZ8bg Gpk9TV+5NAcpcB4SZke3ljoUECu3tcCOqadOKWqGddzAVkzTq9zvguF44sTwvDZCx+dYK/amaDx2 pShXBhqKL90Zgg1RTJBicczqjBm51UcLjiM8ll87i2acmh7sMD5a4Uy4HaEnZtFmts3BySd6HHC2 Qs6qLWRdKTP26xIHpQBd5oEtSeRFdZgyGBEr0C26QiXpX4RaSspvRlFNmjVOvyPdWJm3wFiecLAf dlE2iKd7xdrZrhBlQK+Uv2N+ib2lIOwkpkWioa+1N/iKkyqyDWLq1QNAHVl2YM5Y6SzfcXC/EYCo Y1A7l26+Een2Ous0ryPjGeyts/C20EJ609VkMyuNclqcYSbhhgEB1CkJOkOhwsJVDlMT2nFo0o2R Mnzmtzmx4rvMxjbcuxydwN0IypFn15vxRI8y/elyZBFom8x5TIYZs0tRrlbnLHnliiN79e7M/ZRr 0t/dtp5xgVFabXDdWJ/5O6VH5jnHWGihDioZOjlqY2oWvuypy7a48cZzO/WL+Jn9ZwmvxuCkQgfR B1ld1i/tt7S5089JAu5FH+qeJU1vzKfmoaSAg7G8ZEql8UxICsmLdOTOsIn0vqT28151fte4yKSv 1lBo/tj1B9hgHvYsTimmd1tiJV+5hBqFA3BuLlA2gTxnQ4w0ZRBickdeebdR/Q3PE/2ONNkjPIDb ADgGMUPqF3Jm1iS40vQ6Pq5Ora2t/AKARBPq3tzh4v5IHO5K+IP6L53j/Foo0kCQYCvehf7+vjQC wjFiHoXSgptLmswCcHKAQDkKYJ60hB1xn5T+czx2fokJNBzImLcGX/rw94/tJC+jSJS40hCCm/Vw aPuMXOQB2szm4jKEwPBTZ13FKhbHcK2gHyShkgfn3Lq8Gm4Lx3iaZB4P8vZDKPXLVpfEJNBFRqFv VVZpudH8gtfpUFT+62Es/rB4Ogw5CPfCSfePjloqUixxd69s80jwZlcoeHIZgF1ZtNP4NVQBDTC2 8UXbW703CJKcVsbWOGHuaJxn9IOmPOAlnjKhNZxIUI7ViWmSZ+xdLc8Ep11PVl0596JOvMhII7Du UeNV0Rz5PogHg7L3pyRWAsaGfhIxBn6O0fI8BJ71kn7KjbTSR/kWC4gOZ5eY8MpINKCV9PsLMFXp RIaf1gSY/YeeC0iyc5VhHn3LedDdAhnlVDSAY0KRQBkSAlYWyWHN8PkLLTvp/yPlAaOoOUryfNxj +SJGdUbibAeiwvvR8+TRRuhTy1uIvxNVef1YysDDV3AVf/5KKojPQJUEYtLbeAARFykv8odezWsW D1MsYT1QMJ4M2HJPMZJ0aEU2CXrUPCdXOdyd8X02hybmsisbnNPdUN1e8IqesSTyQIFlHi392ik5 bzzZnZhrDAVsDu0FiibRdsKR7q6eN9tTSYG2CoEJ9SXZIa1IpKmySoEq5JmwnckneiMfqttcVMjK aCPgPV6YOWo2FgdCHL2X/YPDMt1VXAlq0tdERVW/qcONcKD0MyissscSd3MAk+1bHYVSixFjRJ33 byhBIBiDyKZw7ASJ3pvzQGTqoYJKlUfFHiCu5z/oBjQa5FQjWc6UjciRZlLvuQruoamjd8F9HOoq F6bJA10kiSkiQnWqRXxPP9QaOXx4q1rft71TiIR1Wmt7aK86DXBWH5PPaLIvgWqBev9wh3m2SyBv pg7rJtTNxtvaxvMPEFjzHkiL4yX818vTkRDMZr/JCSI0b9azSeqlB90kzHdyKU+WtUqeJ8Us4LGo 1wpyyrsSrut00vKzqQYn5bf2E0J0QNvgmu4Rs4dE9UDAtYjUlfUo9tTUUMa3ejyzqqGPLUDURehR qeP8aU5PMrS5i21s2s8Q31w241ME7qSyMJgEDi1nC9RZnosDS/bOs/+995391/elvyUj/axJhCHs FFCjV0uLB6x/L8Wu6rbINjUTm+XVg0O1ZaWfFXS3KaMEMYpHdnJSdvbCB5dQIFp2x/8CNENh0nVy fczVa0TkK73SgJ9+vg7eTCcW0jTa4cUSSH49B3j5GS5OlYwChttb59Qa8b4mUONXF8XfJNKhr5EH tkoxAsGHlqMPRvW8CCtZr8958pVcYWkURNQlLHFhTlWtWgOMpY2q8rqJd3vn7xLcyRgAjazt3CGq oJ86tzMh4AvhFrtFiUSg4w7bxW1jPLndli7T/gGcYH7+jlWRYh3jG4mSzbRYD7sG/RC/WUL1tYQm QqcWHp/+L4WxhPNT6OxcTHtl8/genycy9wzzd/gIuDib/K3n24CFmMQMnAwgr/8RkH0NolFYDL0D ncTP2cgh5lHMdNYt+Ejlyp6Z5IILMFJvs5H05EhKCkPLMKWZqIRX/NGLEWlm1FPz4KEqMcM7or9o d701i95+D8UuNzwyBJwkE0g5fdxhpZ4Zy2WwU5iP/epU2Lnocd6lLS2mv1VrGrLTfhWBV0/xMq5r 3xICxu81xdz1ZojOQX9wTtAGJ3R/GPx+OQrpzEjJz9NEA8A81DGSqDfPs8WAKgh890VLNnH5DnvN Iio/L+qhamMAoPVggPxzhnyFRihGmki0VB7LhtgQxk0w3iZz+IEdIjBRVzX42vs8yNP5WsmVdf+l ikGkUCWSQWWcJlKXSGvrffTlX//W5F8hvxpsHR3W5bOW24yDW/Yss81Z7tdFDqwwfXC4O+BCyKbv 9bcXVvMuZV0n0fOnQBf/xwDqpSSOo+pjrvXMgA6CdRdNq5OQIz0LnFNmDn5XXkxW330YQDUV1jrY aRCUk7K4husk9NrMFMNaTeUjCQ3NQXNUw6MOOp+H49RuQyCrl0Hk6YoWuIsJTJ1u4mQMFgS2XohF KXEQpF56MJ1yAhbafr7odNfAwJUNSF9R4IfSm8pvyKQq9oF8sRrO0tZ8I6QRwfrbRDLh5OTMbrXg E+RsrWDCb641r7ydukBel5KM3Mcai+x/W+YpxQUBSSCsnmdSis5nW6vewACq4ynvYHjPus6F6YOu z50zuw0ViNa8Nzpg/0ETQ300+pI0cFjfPtEkrTUakQgNCG3jwzHBTFU+TU+gA3fXGeTnkBWsaviE F121CWYO7MELU7lD2zrov0ibssmbMP1Zq224dolMeOECZ8zNYeRvlnDGyeR6x7t32/wy9SMorZsa O6tozRLcUIf2S0MPbzuyfPBxllDAmtSzLljVowcF7WW8XfBS7zPaCkf8lGRarikFI41vIpW/nIp1 ttewQKkou3gNUahFSGYiPROM08Gl3BCJiKSfEoEWdHJmjVOrYPPH3NgOUgFPgsHgGDwW6p3bKqOO wwMQ1trAy0T1l/w0GhRRWhB0slylpr4OL7xUi3t/X13QPJCVLVBiBbDV/sjsgea6ICN9rzVK14Rc MkA2p5ERowqaO1+4YcCUBVCXcKgza9y77cGkyGKwClwKQmMv+/Bovd9NnaaL0SnQ1ka3cJVyi8lh jfzQ/8Gw2ZvmGZz2/tORfy80pJX+4cDNFXS+OgwwkchWw7+MLmcdiWQQJB0WvfCvTK9pnQ4rfzNY wOCNDQIZE5gHv3U28OWxDpGPrO1zkqINYxAZclCSirdFwyUKiiz1BNXxXViz6tt5jFx6YOpxRRRA efrTwwXCTdVu0x/Kywu75IIm+uoDC7SkghE3P6dc5K68nAzHxnF83aMx15b9941hiC2KDHGb6/8m zTvpq82xRACRC/2/VDsl0Hh8Oc4MlOAqMRWH9knBYjIcnWvgQye5zV83H6Fnk6XsBXmyXH40zIpP OGpRYY7DHx4dnq/ST6sq753H/jUH84uB//rtsJ1p0/4x0ZgVDiDaRBaTRDuW179qZTKpdN65oTbn WNa7H+NrFZeLFC4IbHrHICErwC/xM223BQz6Xr8ByCmpMPsVuzmTnAYQw8ayt8yCF51W/YZTTAWj uSRb04tkU632zeT0KibRtUPdZslpy9eL5inzCUZDBlXSakyNtpKHZiHROMDQgTjl6YZXiFlfFjCZ 87d0KttAtr/eddDnZrOA+CVXWxHBHJU+0wzi3cNV7zV/kgTMIEAyji0YaGDau99KFZMYD+8a8dSr snHP/pdpFNJLiUehJ9/4NuyDVoPy3rfcys7INyysB2kxUemuZmE/KQ0MZ/sYzuLxOWBxyOAvAmE2 /NY091c0CT56iZDcqTWIUe5la6CirkfMYr5o9X5XJiysBEMf1ZWM99LxJNPIWO0ppEFm0Oirr49B NrrFiVJ5LdZ1pizBQ2WyoBC3ugL7IBS0z0//qrUrZ3sP3GCzcxGVbmpMw9HwR+ZFzEcuDIwK+5vm eT7pmdy4UfDtIBz994yQzocAaaffCPHjXJgqthWsH7N6hcd7MqTHx8PRzI+6PzuZD4ugZI8p4uAf OjrzyLkwqQ5Yzz3ejMg6Q52+BDY9SzGq5XKCAEtosXuurF0aZ+WxBiXnQLgoXT4lQxqIAp2RgAFl PlbnYrPdwNJ5yPaZkuHOPNWueGP9lYwg9RMSHxcc5D65Y2Q4AyPKmEfX2xhqTpPpnMDHj2ud67gA ++utUuh4SafUjH5J+7PRSZwgpHVxanT2ibOHB2g3YqwrFhnYdvau3QixDueDWDCGNFD02whVZC5d cWr/eEdOr45t+aNum3V5/CqGqSTivpUBaM46HNAZUPF2WUibm5yC73HDdE0XXRPjFABXAgrexvxS 4ybq7aCAVEe2BLqUgwbyKqvblouiM8WRfBDriu7e7NfQ80LTUOaBOWqFCQfUaQpK/60t78XntcML 61VQ93imSWx3DVtZz6nJpObpLps+qFuOBMBWgd0kdLNmZQeEt3onfYPthCHEeZS1CeRw8EMDExr/ xhu0Zb35Hg94Xj7OIRCTmn9XhIosYynQZrtRlJTezLWp4pZ6suBbhSpDP+dfQss/Tzm783Drg9cG 7GidafmY0OAt4h5pmtXjA3CQKklQC5OBWizT3ljxhfKrC9uWTFzr85CKcF1kRY61BY/Dl2Fcp/zs vd2YqrOUk8K6Zznmxz1hkzr3IZLoiCY4iDUWkfhmajFpQyeneCImoLAPlWN0/Hn6v5t5t7e3PQIm g+uG3LqyH7Si8w8rxYWMX7eiQ0o1CQbBMrMiWIAl13Nv6dkj21WxbFqcycqbL9GjHlXZDCJOeUaD isxvap8iZh6I81j64AYbcNhZjqYFTns4RSCNo/4HYCXk3d3c+QPWN57QjBVVDgGESXX+hcT+NmJh dy50qrtnPEjyojw1HCd0I1RWM8KmLkj1m+508SXskX/5Sj2JLxW4aQ3a5K83HlCA3VnF8YNA24Vu IJQQtdjCEDrQh6zVgeVE7kXVxLef5ofqJL5m1SI8JgCiivXSENKbxKYoEqsg0DYKhf4MeWrtSFCY YHNPKLA+86Wq5TdBPWKbJf7CbXvh31+RKZmFGxs/NbRSxp5Qy+Ks9s1kgfQNJf+6tX2Ycc/7/Hmr 8cPTLqWbzwF8XJpPGnZHLVznm5CDouTchl7q3UG6tfVEtIn6Ok0E0SIyylyN2hbH6c/luz8r5wWB 6lP2+jGtcM1x2F/Sr8YRJ9zvuJ3oITxIxoYp0HCRDmH1XG82vrZ1o7KndoegPMToy6o4hY/84/wO F/sigQrqrJ2+zC93Gg+TeaL8zmqo3qjbbbTpJiwPvf2XXJB/C189nRWJ5n85xGMfXndMmKuLVsF+ JIDZrKV/FjVCOjtU1KIsdzr4Vklv57qMwf0Br1L1pkhkWzy9iil7XS/3q1OAjLOrnRljdQbMoAXt wxgfkt6uCzQ8VNbE7u0FPxTKfwatw7W2LBSK3mbZp48nfKmwHMcM7vVQWMVqUCQnB+f1pikUYs1k NQ2k8Vsdprjo7RBNQJT4J2YZ90dWseTCIfPE9UvzPimraKLUj7D2bVZHrI2FqJdaiNR3ZcG1UV2b Z4gn4M5JdKTgDxqi16TIZi7E776V4nRGJ0qd3l9hcTEb+uupxfmdbu8Ajv8XN6vBRc6Ke6n6tYCw ST2g+sSKn87DOKnsyZ1C8XBHy6hivfsZGbpUi5dl/VniH21NrQBSImqmRoMKsFHAB+yexkS+5pkS 1Z+j7QmYbPYQqnB87//amtvobzPAcWAZdoEY/7waFr1voOV/my7FB+wwXP+qs0LSu0nEtSdK3uDt O38z9N5ZswBA4FzSQjol0Iil7iXB0j9t+n7gP55DASvv1UxDotq1LUysBLzARoDd9EDlvg5XMSsF QAUlzbjolcRmj0NuWuS66D4Ja/QkqMYoIe/jiJiHGOIYDVgu0xiFmi2tD8qZbGXjIhiqN+ueONPY IMaa1ob/5rw18bg0hYVyBlzzolYDlLi5G45+O1f9V+TIFfI/U5Fj1YDULtEITxb6F/eVNmxILo6q BlvONKw6QnkpI0j3JdmXpVH0GJHm6/90fM3bgcNITYrB/NJY84PNyjtZ9TdcFfRCz41wN7o/V6B9 DgKB6U+kzuKkyu+e/08UAOhR2afb2AzYgUyLMWkF8WSzleQbsJdffwtklkFaXqabpjhhoGdeYTSp uhGNjEu2XRXKHRy79kC4cLsmQu3Btfo4S9baR5bVxdHTYjTq5w6gB0+FxvjQ6ZsHaHcLj+VhQSHk xY7253Hr/22tqMhEuFY7RlXw2xJR5NrfFERKlSoOiCiEvL3ATOEv/yfT9sKCeLbt/+PTLEzpNeYl DDuA7dQPYDM6Ryu5t9njZ1qOzKKbJ8z+KF+3xx1wOi9bFaylTUFn2fjYUYkKIIzd+FxzAXbG5Aek hU5FFF8IsQ4oML5BeVjQTmi0y2Vdz6AZnoodZNbBGbV6rk/4TedmnAgjK1OxlxksVIWIscMfXfz/ djlL0Bc+9D/bdj1aKr0rpNB3+tb+9AHaqnkRjHNa4hmtZZX+qF99PaJqLxxiczu69GwPUAHejIQ9 BEmjlM36/2NuFoBUobNZmBd5yFW9J+tAS4Kx+PlD9tj6iwKEVefKXVUhN4rs8Lg1szgsGOWbuAij YQLBaSmuOvR55PDSeY/VCq6sJVq3Ue5D5LwqleLr7WcUKFPCKyw6EAdGpvEUVrYvn8EQM1nBbOjM MGDNYZyzM9+Fw1aq1Jd2qbgbtCOROWU/C6SW5jIn5w31oSCLqVRX3kgTRLeRkTMqMmB8IdUhxMMO 3cmkavjkxoIy2cay7ZPnnQP2Elr3ZsL12hZL6xvgL3ETiAN3zFF65OWTrjPVi1pBkTylpbJdS0wU BqTyCzK4fgllOt9arlH+XMsGN42VWGj4kZs1DnhmR2UlZwLSP/w66knKzX1+PmJ+h8vUzSyOL/9i zO5AFXJJbcWk5ulKGIUBXSw+NxQcpWWAvDAUDCSUiui315Ykt6zt+V/wyCMlMutisDLjer/WYn8f YpOzzfkxGVXyveXlgCrjfp32gXvH0qjaFGvv93pORp0zGjY1+IClfL8jf3fTSjHqKgvV8TBTwpzB FIryh/nfp+MyoRcP/zKYpQmQS+XtDiEGpML6g2kfjV73GpF7UZKW77Aki8nGHuu5+aHHN94e9Ip0 yyg0p7RBCl36sVy9hjCL14mAFG3zvxKxfP0FztL01K+0U7B3vjsWOpiE8wjygDheqRzX9fUWDF56 qyX5Xb1obYXHXJsHG3YEB/sEOAXgdkEXKEfc6d7rFCxAvsOJsSTNvVvP+CL+kGrTf/95SFi+KQp7 2ewE3GLrJVT9YrEMSYvoScH4K+Q/2wwkEQ4sZODBnuT+fx1GmLrPVfOlKzV6bnYBmROEYJ7P78Ql RtAik/WBopZa0T2t4is0Fifa55pTLucIJrCaAibvTn5orgGoI10NSS9e+Pc+xOOrOkXYjkRAXzPK XIktv9CQKIjrjs1+TX9W8lpzNW73iiIHsj+puhC0w6maFx4cd2AMjGwU4d7PLvrbtd6pGSTTlmse rcbuRTV3N7xC6lUDv3yvcNN6JSV8ee1DyS7WdtmMbpBHWnCY3sWHCvKeXB8Vg3aJ+Vrb9u3jdEqW fYmiioV39FFTxV+sUq2Ccbufy6nzVGM9yu+WhThvmAGL8bF88keDuh/F0azz6xjugG1U8XNstO51 7DuxvPs+Ych3hf38krIJ4tCaVziXarlSpUGLPyQ/htxqreR/2RXId820jVwRE/h3NR/BcOlhnnUL 1FG0pogC12nPu5xB2WU2PP2KOFifxAKNmsM6xnqeX3nF2qdATkEk//IB+JDqPM9jKP1WZBPtQSfB l71z27A+UBigKnoNEywdXqoGFn3+bwDZK91zg1npHXzbS3I7COgT/jtYBS+eod8bnQERcSaLqKtr QbkVr1/IT8NOYUIKdnEWtmrhgq5b9DhUEg48G/RoaOpAWIVSSD2SHqY3wPqf6O4ncWKMMXpQUM9C M6fbtYv+peZ8u+EEzRGhi+6UmR2VjBgitvTIpWMC7QNoXKuXbg5yTE1oISId3YFecoPC3E1uvtvc jgjcVIsajtIb9+1QEaxcF378u1BJMGGnSyZ+tSrm/HYyHCWdPWbVGQvB5ateUNv+uBHei91oC8K/ KbWT3bxsVqbtSng/6ShijgpSVRYd7S/Bxogj0RC3Rcj1/7vCM16gVQeicTQltIOnM1wc5+tim3zw on8h5JG2+qxMxOmCb1i0H/8jRmgVBjxDY3MKfCMZO7t8LLxozLCWQA0Us+2k/lZUH3sdhrWQfBJs EmuC39jM85tySi7ujqwV4O6i/2U5Vbw7DknJmfaDEhGsgpnEVdp+5LjwQN1H0Fx7a3ueQ4oaJXOi /eDaLFWxHHg6CglHDGc17EPzQO5XG+ziH5KVi0UGW1s03wZ9Au1bb+es3u4gsn+qXfhO4W9rsEi7 oofi31Gq8eTm2iDM6pSTc4LM7mBHqMawYbIWvEUts58qrI4NXzZCmxxvopWILFnLVGvbS8IdSMf9 IHaLXZMBauoiOyd6LRzd//d0i/sTdu/gZLbWk1yVzZAIWQM37fA15/6p6mPrNndwcPhtBYpUMqVA a3GTAdz02z3m5GKVbf53+c28582UFOP8muMmpP1u4ATfx0RQ0++qvGbjJ2C2EMk7+Y6L8WZbR7P9 I25e98DpTMfkZgMt11hFraRtypVINUd9Rwz3Pq0H3g332yk0Uic/jRIs0Uwd7yq+51qjO5ARz2gl RbkJfbWiGmbRBJnW1jrkj6aGObkrBD9hilrnpUB/3D0LVuthByRHeggOMswD3HLQY4RQTpkoS3FU odzisKWebn9iGXzMottYI//2cvgOREjBbRPNN74qDiu3FihqtryRGRHwiYM7sdSPBwQFioe/f9Ru 1n/vYG1o3j+IharXAYPNi1+3KdRKOcc3DlhdXi1yP4I7IYI0jtQapUOQLjkAupFnZC6gQ1RG4S3x a3isesNJzi/18smaNTMj+cWLuxlCXrxcUzhDdtz9Orsvc0kMAoPCnpL6S6uzK5TTSgx4MwTl7LqX B2ccnwvnAiIds0HjWCq9HPPxUZNoaG8u6htAVhuwFxdvB1MSJ+ixakELSLpnW3uiGnms/G2nT2rZ xqfCciTF3CA/v3UYdInALmw1hVVYcqMHhXKjYa0b1jbEAUEFpLge23H8fKfKPwB07JhquioGtcpT VGL+LgW8YaHHUR0G4qV9GkMF4nLxX66GcpHeXlMZJRC05I7dAScldL7R9RK/dqszVwWu6NyYPpQ0 yTFvfivmKlShCFnUQPN5yRxsS0aFnjzzJFK+W+SGYFVbux3m0CKAeDtQv/9uGue3iQbX9eVaa2pE obON6D20el7NRuGjRNQxvOnJOFG1/6CqLd9YF/g4NVWMrojUakh3gjT3d/Lyzw/RkLOECzPpnM+R MyYK36zDKw88SAG1v6yUqv/jeheVi0ggiIa1XRCthh7E0LXfD7neZCzOKJ6ZL8ppEvbA3qrEMrEE GYM4B1FEzj0d2PShe+4DwFdJqZLlKbvRqjuqpopkR+PokLDEpObS8kSXaKzUEzeecKUiHMuXSTFx nmF3ehiYH5S+IK6K3eZSgoxuoDgpP3FdMYooa13aSxrhMMhypz5MOCfvZ7646u5d7hFv30wAxNtS 0b3ivryG5zdYYkX8SeSE5X3k1vcRZobaT8yLKbqb4v5NVKvqmq+faML8EN9wiSgV/F6R+hom2eCl 7Nky/iv6E2yaRtuBhYyGZLVG8t7QtQxHOa/QhDeAH68093YSCzSLoZ34ZgVpT8lxMoWKRk5p6nnq pXX+moEZPPN0COQT3sA42fHT0w2j1cXecFhOuj2DFp0g/VtJPvJLejnoi8P+85vBJvfrMA4txlaa eJ34q3hCQXoo6pgnVsPuF5tDjNOXNuui2QbpEimi1L3+8DXpCJbD3RAoeXY01TSS8RHiFWgPC/sj EviZlUW1L/3q3FvYTiw2UJIVuFHKCICYHnSCzM04U88rLVEk6c8fCUbI7DtlOcP7RGsQJPjJYOxG 1qGWT0O0EaGDWgKHCjnKK4DgUajV2+ovGGa2trk8Yc5Y/2WY/XCMd2gYdAIlZF/Dz2czcPSzWaCf rBOqCpXRfb9UKe6z9EMED3egdStK7k5CobFNNn0vcGZ38i+Zwnk+KHvcrCN4GZo03LfFdXCu9WrK K3M0kVGxHKB/d69m9JctqQk674a9CabdhXyAXDhhR+8uq8zWg8TahkU+4pNvYtu/ciLn+KKXbdT5 LPo1aglTZWc0XdujR1AfrFRv10fHdIigmKwtD8bSg02EvCRxX0ygcQLolhvfF0KuFEb1+h+rvSFT izsm7XCwEJ2iDV5oIPjitKV3KXZjdSHnKYap1Ya7L+mPE3TAG9bLwr38pGxwaDH+aw/96S1tamqc cUFIbwKhhJ3BnpE2TX3zuYPVTo+hzKqmMty+gsCJMAFARQwsc4axVG012wXjsfy72r2C9YovYAHl qz10Ww5lMBK/jFp4KZnaahfmZ4rBFsDOQ/HeuLbi1WmbuLZY+tyKHfinKjo8U3lcKJk3Tbke8eoa PAZpLKWxBHKUNSV2B5/E1xzEUwp+9R9iX10WajSFMvwarM80hzdT4nA0Yzr7W0kp0Dxv4XwG2mos sXfyA8jgYS5vcIcT6bXqNXwLv1ff6bfj2h8jJUT/YUA2S+HtugZuGavwTDvSpO6aEB9dtijyBQ+w OCH8B/3AIj/YzFjDWl+NjjwmXYp27xOyVDNO0mB98VWSMXURO1l10tZxlRZjv3i5qpzPAchNyN2P FHSuAZnmIVbQiD5sKHBCzC4FyjTbvWnBNqdFEvPhNmmriurZm/Vur6fVYzelsAY6nqSM6RiQQ8fc 7M8vuHtKqEh6PHuMQ3QTCj6YiINksAAFqohwzPmKc5ja0m+7oHP00Cb/u55WN54FW3Czr+p8YdWa tVC1TVpfHoMwj3dT1V4wxJ0EICr8rbejruFt07mZpwhzUR6ImvUFeS5vcN6/t0IgeVsUnMSk5fJl oRCExVmATpLkrhnzA/QXxjWf+6sdl9YEphtXBNazEzlofFJtFW3tLeP5sxvOyekl910ymub/GeO+ OUq+lB1BFYphMQKFEeWB2V/BVh+gcY21wO+pbGhfJnQlIq9GZh1IgUm79mK/wCMrtZqBTWdpxTMy UMHLnrUiLZoh+7465ff2cHMbWFyjdE8qn4aAG869EOANyfw2vDNfC788zo6/BxGWtrr6CO/7T7Gr OMOGwb9ur+78tgVL/aEAiVF0wWLC2UHLN2YHLGkk55XMGZvqMvSC/zvrSDqRClsfqpXkghsJskC7 JJx0T8M+dIPXYWxyDzChuHT5wlWZ0M+nXGuuqG5NpHv9DT19C+rSAVNOWk6PsMNMX6H2OkYlVVHg 2XzhrrYiQOWGq6dleGtBqPwMOb5cltl7ydHWX0q7op4bsqZYDiXFlUhU3aEj0ljSdFXxBw4DWgAu xgXq13qF41csm3PF/Yzi8RmEDTuFe4SbCImxOhRIWi2pttAJUiJVHJzkZ/joullTbowS5AH6HPFY RSS1JJbboZwxD5/KmyU9JgFNNcbtQxfflVEu3hVqD9qEhhLWIkmH77WFXKCz/mJI4S7pvl07weAh i7/sIHVFGTpCc1VPOwXln1jD3hFwYqOSkrGB0NR+tzM7YU8ZG2Sk+UXnGufJMyg5DFHSwA46zgVU 3HzXetzaAjytyru6LOVP40iJRSShXEKR0nL2/Zuu9Lbj2I9gv70AENiJX7X3aQOHCaotvRAgEgzl eyLlkYwF+mcj9hT9PDahhHdf+aIkNym2YbB5IZpiCQwl0wTcx7Xt9J4VeG0cLkM8fUBK3DfBwxk7 NfF/mCfj2gO7EVLGEgteV7NgRNB9qZCZWizB/pV14jj5+5BG+nnmVhG8CCRyujOQ3y7AoGD7v7cr D+1oQtRpblRoVZ8ML6aCjBwsfd9vpuVuZJWJ6nbVTxRBPcIgi6flYsWYIgCzSw+m34oJZvNwLwwS o15+SJD5ga9HPlg42WF4+jEz58Rp+s+R/Mx8zxBlIuVkGrfkqDQjj6zejC6Yj5RuoeH7fN9cbVaW O4fJ9eFTt2480Z3uNNwArMZKH9HLgDe33mx6FEZkQ+Y5N+k+5OXtoMEXE28+nujdvLpRiutWV4cs /XTjRztywsd10NFoY/uzHKpvNECmV7djWcvimdpV79JeEh46jipI1xn1iXLw3s4X3VwHlbiLfoPj OL5XVAfT0xrbIf/QbgvHeuFigQAWfKSbwT67OdiY2seeiGfWhMv559G5nPnF7qE9C9CRoqiBJWEt nVLI/F0tvX7WxP+wMwNxYNw74gnHbJkCZ6Q4zWybJ9ytyqZED9nNx6c9e3roJwpm6YJ68Alw7jHn uom0yNBRLT58K5mt9I7CgX/VGojOoADH9jzf+1VW3rOt1SJ8csV2UdzfO4J/AwBAl8r0bovT6VxW CRZIOu8P8zQFm4kKRmwMSbKQiXciZXzmxrxfjb7oW0bMsgSVXilFb1INxGd+O+elOL4WSeL1YF6G bVmmB1qJ9GNrD4WTXb/lhhNWhhabK8cSpS6+q0UwH1OdqearKt3K2tHINwIRSjTpSMVtIpOYrrLj boyWpWM1Ijg1pKUcUrUCBnyaCZsBWNW56Al9sw9JiGWmkDTPRu+2bqchxgXAKPRgDwMswSi54E3s dZqpl3MW3tpZCMNu3Ki9LcrWJ0/3otKROOQoYVQ3FgkBC80VA5gNy/iBwmpVFoG7UQCUT33BUbVD lfzCfQnZpawhva/9YrNq+SPbytC+CD+nOJdBRb2a1uMuKYc6DVVw6k95lEzYm7zOvCHM5/5OZcWP gGkfuB+0IE9khlFr6soooZsaPB2RkYYW5WVHmzhUzjtwDq7ZwNFTUE8AXTjtcUldy84wG6MXQR/z g6Ow1afzccxTKLffUAzb6gtQ78MXTe53Qh2AxhGTzmfs9f6lZK+C9+e3p/ngqdyT34A/hY6N4nrL SKdzv53QMD5xNJshsRiMlYSsvT1GovDZq8hJz7aq2a9s5cJ7gg4bDd65pJijw6Cab6N/lH+M4VGL OSFaEaicAaTxUcrBBjQffRyzDUZ2AftzzQIjlT/p2qG/zBNpjaVqU5lC+kx8xtNQFecPyPH4X9FQ TrRW5lB3V94+/hJIMypoPKdOA3HBKe2ZYz2fu3GFqES4UXvb9e1zcViMHI7klFncZsl3X4kIcvF+ NERDMMF5ivOZxDSJAJt2fTrOMOh7/AhYromaM4Eel/Mo00JSMYR79BH5DuzshizF+iG/GMUyIBzu ywR1Pz0Jj+hXWGDl5Z4jCM8cljZswgq4R30aRAgJXEm5rGuP+PycAzqz1svWdRqqXB/VcOBMg90a swfsvgKUdplZAoPi8UyA/bzbN5XUvuDkh901fTJW+K79mdU5Gj/Hk05oDToFBalBQX5NYn47pOP1 EuDS8691LQAk5vyEIDTdaiozutccaItt3U2Yq7GEe5BX+QIWoM/Z81zK1V7qYFtVbSs9pBfuDSgp L4dx9Pi0nfz9ksrVIRkWyCCxaL2v9gJxWYIl8CZoSSvFkqvBktMu7rMxzQQSXRCf8zHmbN+7wCST vKfMYhyGUPMuM/2+pB2DTdJ9e/T7HAth9p06dnbkaz0wZeoBKKO6olGEFAw8M7wFV3bToB1iWg5Z WfhCQTcmG7mhszZTpRkRIrNDtAxdSDKVNQagG2rwfuXMHEhdo+OeA78J2H8SlibWR6eiq4X3i1S9 WA9K9Z3RWP7Jv8jByvQnWy++82tpK4qxLh0iW2uM96sRVVeXV4Vb+2mEfaMIwJaIlE2f6La+vxPV P2g427FPqIa4NLelB2xwh4hPPw0phGuUZXDL5SMxYU+kHV0OZ0aWfcm2VKKyv8L+WEs6AFrjO+Lk oINuM0owPl7UlzMiLag31uqHEEyWB7QULpkysf7w4nyoJByppKwapJA1R9kInPzDgeh3PVERQmwd EYPxG+4sg8QMWUGpPT0bQ4xl+AEJh1JBsalxoz6UqISWi9dAuZ+goy6sAEpRalhQcZ300bX1KyAd PuGzs3700rTmEnl2GvQbJdgxpU9nvIXfBIPfMBL2b2eb1rNVihNpjUt3PUMVTFY8pAdfAZsFtSDd su3loCIEa+muwdIAHHZpoqvsvdl3Pp3jI95JLLXdJtqjBVS3lu9ZSuEA6hVnr9dIYuyElfiaCRCf 8DNxFbJPU48IAtaGJ+cHuGeFMBwcK/VRbmjp104WFTAPoOS1m/Z+fL6joh0mXTYeaNsxfhdoVN/c UadKTyxbNXBu2iyYX/A+LxZNQAdegsrTr2lKO+jNMM453MVCjVHYDvLTZKQ/AME638EFP5vUjsOv kJdiS/HyLwZejipBXNrROiUhE7iEdu+oACPcneVoUUyhWLDXFhWnMtlFG6KSB8FXicPSy7wLHNvb 3YiiWTdBe3TZgLDh3OUiF9Or5ct2tbTNABmaZIh1Fzmm5+rstdgPFjjP6l0mbLVlCgQSn1MoO89q Wb13kCIbgBELEleiTGV6Hs7mdNV43vVwOflNE8g8KwtOWDtMHIvYaNPRwgS7XUq/6vQL9Sqp6/+B Cx3fvbIRHvKUcIbwfa+GPOmlKmtismsKzL2gNSPxyRzDjnGrgr+fohktqmAFEA8tU9bD3cA11+wf O2/veA5SxA772i7K1jm6hSRYKTCZgJ708q3sGrETDvVY8ySvAIL7pGG9Oo2FNqJwQB54THnq16XK 8/7f8by89hnKdRHeX6vGi8x9oK4++DHoC83Yw/VrrR+W7PfIWGz6IdNRKPiLLXlrmoYHkNcP2wzx JHlb6okClV6ZGt9xe92wVWrScO+t+P/WOZUmU6U9gv0wo5hNKjthHXlgA3HSW7mnbtWYDKqjyt/4 +YjSVnljUd3KrJuDb9jKGOu40RvVKH1RbSOMRFiLlKNtqujazzuLgI0JTeDFd+usT1+4fOTBNneV E0T2OLkOIt5O9ehNUTsZDGnIjDKTty3PxnyOPXuPCefYTjsmXPBGxPRCs64SBOwDZOr6QTk8EqcG 7JpzB/iv3DtLQVPKxbY/eM7ZgVrdWc6Jp1wWAkmJNRloLmuRRJ70az2qQAqRTgOjk+vRvzptrNw8 eB3HYbQR+Ur6ztuN2GION4iFyJcg//2mO9TWGxSWr6m99FiVe3J25WZZCI7FYinxLzGy7YRS1ERu vAh/MKVyFYAMFyxdkjAhlSS7iJEGzzzFPLAJ9qsmQR8wGG+6xOdDetYLpw+Q7V5nvMLx+8WLpJu8 ULcpk5oUw98J7bnwnIwvdFRRlGJTt3cHhzD91o9h/p5A9zV0Fkcurr4e+uJxC/HqQoCZuadiotHO AwlrRKhcBmONI9FqpwHoicICciBHwgE6N/JTSB0D+UHwiWpOBxEnagEfAc7prdINsgmUC6OWf6Sh a3ANzZrsGtjqcUVLZRSMwJkIkXd/scmPW8CmD21JfweEscbyNc1X/8YP1jamMaozNW6Nf9Vq2Thb GutLibfa0uzdj51D4kpmvrq+Njg9oq19aAoMO0+uQtmMjNIGOyYBvKxdb2ECau1N+5fcUX/pgUJ+ qatf2GCf5j+dcuUdMjH6dwFkfKNkjLsuKGtvTCRWMgdBJFFA2t7TR0rLjyB4J0gr22oOASbW/hWs IBZU3owqBXjEC/oYvzGMCNuTHLtoZ6YLmMLQh4JLR0twbywPaWuvubQX+XBfDvr8NgLZSfQBwJFX MmwGe/k8FT4OQTTt5RD46YSnqxen3rWOo1JSZyC2xlf9KQKlv7y4RAOyCMadbeGjN+SPJuiAbQFk dES86YQ8GMB9fPPGnO5y1oEQJLyMvaqdPxRSvmXTqbg2/UQcLJChUBTsyQBEnt7SIOV9zlYCalnj wgz9IYVAPJUPZ9n+OAZDJJTKBCaCuKm4L7nezGT9/bTJ7D4c40fd44a2ake310hCj6YvePQWjmzI +ndsB4EoEfZq0fwifNG4XFtKZEg8WY5mmScA+ciH8x5ssWfLpWv+r8rxu1pROLWTdYp7tnq879GG KPwcha0Kb7eN+kUimRY0A3LfZDZRRIhtJvwa78YDrRH0hpHaaFCsgbwJlFd/yyUcIqUBBMVBG3yi ovaKdnsgGaCxQmWVSbY0fOO3WC2Bw9kB7XpX/StrJ3SS7htr+lI7EZjc2TLytHi5ysyC2ivMjpLf +ww3CMEhLWoR6cA4jyHyeOtj5AQdbx0ON/6fqCq8WKjTTVyd8PS3oBK1bqeBt3gJK4vE6JXb1YTu yi5q4z54/7se8mbPfiGveBEmX6N1uEufqG/qYgxd1uf4EBXAZr9qp8867ThluLm8YP8UnZxcml2I 8l+evv15zqInVnkhdis9RyCbGAo8w+hQhLmTBoTRXQBxNqholKEd99pi19HWXtDDbXuS973LAHH8 /aCHkbJwC7q76YHonxswraytdpCkj0lh/n/DdO6r19RB+X4WWL5JgmbcVaRIexWIiVGjkN6VTdOe zhT6v6rd5LNZl5ts2GwHr2Oi1kIFnYWCuKaloNWj1wt971brN3ckdIwLi13O2owRWXHPzzhLdwK2 UdkJuQy9GrhYlhVKWSSvFVSQeIQLrQhz92DKQerOgQR+UAtbBfieNjUq8fM/+Kc+Dtc/ub5Fy0ug EAggtqLMVB+dQaIEg/WOlhYNN5F+uTpZsbTwR4b9AADeFGZbpw0Mx1OFq+ehK0aFPS+U8zaVPoVT wBaK4DBvwxmC0inVmUbsz99nZXG5UOxIRfpIqPTAH8E0xl77gSwhxQAxIR2ChsiiL577S4asUlSg wmSc5diVIFM1y2dJ3fKcvqVdp0x4gk/3Rx/DCdP9xhBgWr9R1qbJk8A10WiG5H6ZvQsMwIKtov8f w3bV58jGktbdc3u/GBI8aJovQOFGabDUjCZzrT/2KfEbRJq+rJWO1+JJUL5bDucJOvIOTSOYp9CF 53GD2glL5IdtXhUfx1+5mUT/yCRd6MhQ5L/pZ5H7y57DuRo43CXqdDp38g1XlH11ezIBqEC2Fol2 HpoitLIstgktx4llKX25L5HAFIt7CWXB0c9l43lPaSYBxc6Rvrc7N2bZUnU+eDO3Mytq4E0Boq4i irXJN8mZeyZ1CyZhqG1Gis4X8ZX1OyFhyMu+TCVy2j+LETuxBukyzoPMWs1znIhJw/Ss/USOYfqx SkjijQAHIMUk+8GzMuoQ5/O3syEQcGpAceDv4FyY+LUYo9cSviZRX5QJ3IgZYYVdaouMTXNJUCSr t2/ZAj9HV4IfKbSW9lEtTgjR4+5/qJ+ijHPJH68XE+azx3MtCjj2wH92iSj5p2Na0MUvpiioT4cn RTLRHGSV1JJHchrwH9GE5Ax7pkv9qIWCZnfrVqm9Wq+df1wFsqFqRyuwhWAfvgRO/Zgtw0pu3ycd 5GpXh0fef0wDaG2puWrwEaPmJOSQBsPKZz7g+Jo+YhfmYezLAWjO8+SKNs7bqzaDZaLq0xRb9WOM bk3dYdh15wooPCqFcrI6BS0ZwQQMXgS3F14oMxW7XjAkEefxsxvF8k2E4IUORwbvhJ6tnfhorlCI 4K8AuaErHcF3TWiOdeO7a2HbVsqEEfrXm6BLHSM0y6UpRSOWvuvqAuI6z1LJ7OW9i9tMrJNELdQQ b9B+uy2YNb65W6EB/zmmxqBwOoWItAGGV2aeQZlbnTTvk/XbUCbjlPJYFh13fkKfZJ4XzO8iT/mD AhHbNOUUcwvSS80qryMWJFE3egylEYNgtBxfOneSaAwtTnr7RU2FZmxGJwzoQUBM8NAVCCh9CTsO aBMXFkIqN6ibH2Dz8YOPovdVOCmfjJ4U1PzBsiXey8cZv4NOhQ74VEyKeDh48X6DFHCRugDsTMfp UQEAMvXI0z63o6Uylmhf3j5rF79vPFHKiUA3Bg5l9CEmEOILLu/YreZxdcPgu1iL5E5I/iv3OPbC sR9sz6pVYbhI6+aC1FWQUrIGlW7AgDA63AvfQcONDhKJuTSpErpsUAKb7qYpll6/r6d85lkOZvHt tzDuRNpm0usuco71c9pqDUMCCL0HPsJOX9wLaFoTyiskJFqm9me5a0hvMSCIGKGEiFMEXOBdnqxR Wov9IlNfQOaCcjoRRye8kVVQLKIMPQJT4nuFSmUYi4OPZDSjCzl5xPlawCJ09KNr7ERGK/4Ct8md 0wRR3St6ieGlP3WJ9Wx+u1nWYUxYMEWsibMrdjlAENeTNVcn1OL5neUmuP+rehbnQqint5hHCDG0 mCsoUV5yHMSdoy/Q3oe5nAmimmlEZ3jZhxyONwA19ob3p/rPpPLtrSES0HQo8eYDjbON9nQDRX+f N4h/mZ+X1J5M0ENAtcC4mtIEd1wAuj9NoAAEKXRgvP79kHXf+oOnYPnLxwlV5HQRZhds8Rmuzz40 BXP9hYZDpcDX5BlIYyUkjSBQlY99ysNXAhNpzEMYq5RNPemn/9w0+a+kyGEc34Aogs8nWk5O2jG0 UPs+FyvkEInUuAD6B6ocBmymhXX8JA5FjkModK6HvUgg7KC37pnTuXsd80sBxgBg6BxSNzu1q483 eQB3dUg4GG/JGUlt+w+1eh5tIXTxMWPjYDsT50P1iS2QS4sqQymBn3PSIHZONhtsJqJIjnpb/mDz LbxEE0ccvGAtenYKlObioH+Bxfhn7KeGiJOWVJmEcE3QdCTUDdf9zyACke0rTL/uARMDwTE+G4ev ggA6/A+X+x1NjrjIuFKKJDo9h6YfZ92jumIVHo6onQJyMWm2JNI/csLealW+ROU4g+B1rwyoyzyN MQmZnRjKq6QMbgdv5vl3X++w8VTlax5LmGXxcvKGzJPHWsAw0gtEgbMsCtm8cXzUQWUMSjxxCoCP KhJ/qv4UlMnfU8UBLYYfXwvMaJ/9kQR9fVeEP5xkSAybtVjAptyuRo3mcn+D6Opew0wYrnGysyZE c2ZQh/e0X0zIhLCrE+POdPhHEChAIR+nOynZttg/GVDGcKzFb8Dk3w9bFkj76BIotAbO65hZYBqv Os17ivMH1yZWoIKwnZRw8gVL0NjEAu8n8Ir2Rjm+JfXiQtXjBVvLG1Txn4eunHnpNZvVROX/W7ql 5VWcdCiZEF33vtTES5VAiACbM0TrfouvpRp5d34mdxrpzz1AziSo0bquG7CFLORmVuSeF/8/W47q 30jnhUat4YmciVwFbTTcX1hkkWlJTwrkt9IR24tFNUMBVbqFbwXqgnmX0aaHkThhUpF9+hvmvhjA LlHeqyHTCjArJ5GPf8ZGgDNzkqAvLSksna5XrK07wuvw0uDb2u3c9ZF0F/NfVlGSTNgscXcNpNte J9EbFJMWfTHI1xGWc+oxai699eiHfnEvypE7U+KhAWbiPKPwyvdjyoVjOR6Vw3jEdGieDOSse/a4 1WpV+fNPpSPMYIInUIXWq4NxYPAjrXVLW4LP12/EKP3FtWGJR3OVvHGNE6f450jvTshTBEJcvgT8 wGOL8Nr6Z+y9yA6t5mf+yspBVbvAU+PmM/B012Icc/4d45sDoyCnRUXnxqZrEwLmZ9X6kMfkSH4S xetLYGgRjRlsYAnaj6xRY9S5GOIiJiu50OtLqHhvG9QO84gfTVqrV++PEEZxBmss7FbY2aXNRx+M WObheZwCsS4mDkYu/mUDbKA0b+fLhFgNw7xt5AMkFogL4qq2qpXPkqu6YNMfcdRwKe/z0eUCqXxG rcRSSe7bj+cPxBms5UwEnyv65aF9uEJeQF0f7t1n9DGcTcyFZf8Xv1xWHKBKy1izcnqn3VNFq25Y PW8vuT4Vx/SySuFYo9ReYMOlAjk0EUo0Q+eMu+l/6o3q8L8/S6d7FvyuSkzpDKSoM7AzJdB75dDT enZlDplZvdpQASX9MgJbU72rdzVFsyBcgGfkZ6/aYl6D6R2SPQ4l7TJfYqSt5OGzyHhVGkWn9WdH klsMY/W7DAwWhuamkCAIu9MoU+YAN8/3im4A09xnQN0zzu7WYpPjzsXWwW9ebPZyOMGMoPTzTsuC c2i622ub8KOr6hsD8PfshZamiYLMjzFemFYxlJiJV3mAdmNxrZaOIL07F3sYFaH2qS2FPGSDTOba Ln1zOw+aICIwbuapSZko8nqe/pVbTPEXvGqHNGL+AnUss1JYWwnhEWWw6ZDJ6mZbF8VlXTODUNxY IaiyAyGsqIz6bPUwmm8WQgCO8d+o/v84Oi6EN/vtKPTJ56JyHhjoinff1F5zc0/CO1kMYYaEpDXG H76NqzscUH90ip2+UgZ7/QtSXvRKVklHNvUl0OrFm04uOx419tMKh2Dq0Apf64AsCReZBgFgqQ70 PVYGIjOOL6u9I1OXK7nGJ0SJ8ayRjz8knuD/SusNMbkEeONoFKB6m5Chca27kYRMTMHk0sLUHE88 S81IXrQG0+BVOho52P9P2+MTUmI7e82jQPn5feac2mVcvx8+YQAiBvLV2DXsvoc7VbCYGDZeGQ7W EzShAXPymIeOzq796PSGgj/TBCtRFKndYIMeUF674iRFsuJ+WOJBrdbwOgCDlFH3qgVFMeicPA13 feBTbKWCrergtCGQUZ5MXLlO0Fg1DkRZY3jfKBZ4q7IYISnTX91XlKsWgTmKJ1tHbRtsVAaQnZpN YH6a3t0yHVrW2gbdAkeX1mVMVATa23RUm0ZgrrKb3POnL5KWUVoy69d/a1/tl8C8xfSkHISNrhbI FKGQUo7KiHwr583CrlttQylDeRo1IsjwhZh/TiNaQ9xa2lzeHoPDVdjGq4qzLRkLZhjXzcuXJQ4d TrKfOR0bXW9E5v/6XwKJ06qwIa5Far6pbqnUhFbE5Nndi7C1Btb0w6NenQ9SpCgy65V8w8ZLElS1 9TCLMI6O1FIX3hXQka2gKExmPzE6qUvHFsm1vhDY1h6TN32vri65D58/qwLc12gqmJh61+pEpDfF esK60YhAnEzny3je3MS97r8od19lpl1aMVaPwwR4LtEzJMxw7DKo/bd73LQdzQ+T769P/Dve2U5r 4ovVwEr3MTfca3sZFKmZBgLVMPOCj6O4W7wEY738p7EB5XQIUYaIKWY/MjK1f5zAfqytrOI2bfen fb8XZay1pvVwUi3Izk+4cxZZVLFPvrZcQw5QDB2bB0GNOU/khSYAiNNSM9rkE/c5+xhP2Zsn1XEz Wj2/0wca08m25tYFOyTh5GVjpji9lzhxindWusH8VvJpjTCi0PUhXizeIrV/+yBiplGLZ+7dhoSp JVx2NTaOiweI3SbZf7QvdD5I1j6YERlBDp134mgXdBd6NPPPBXUhqWLClU/1pQgLAVi8Sngu/bA9 CRP88WYmJ/xqMqXOzaQLitsP1KnJ6gCXMPASBkdJ4PkvAt9oZ/E0tUbgOpvRFGHUPPTCZAlD8n7n HhHbSTTigVmhN/dgz6W7jr58vV7jY6hIBTrgpqIZMvqrggrOZ8bsqoPyCjj3LH12WE5ppYckmNj8 ug4BP+/tA8JHnUb/19O/GDMGOMFSzslDpYLbbacB5cinujobIJEvxq2uZZGy6q5/s0RTION/X598 FfY3qZBQZEQoX0rW2MPkf1Q7/LwN+R/rUW0/jkaEryKom2/qXuIG9BDwjF82hIki5OeqBEkd24xO Jc6e5sUNPN8VmLtpBB4+ENq4yrgIsLMZkvdC6YWN/+seYFLvNJxyCME/Syu7bQyY9VO/SKJuIUfC zx610pb9mwdclWzUVuq3/X4Mjs+3kbjkKKimuaCG68ILQq0WXN9oa44laWw+rkPkL6m6Ln1nslMR miGsRwzaTh+VZPzWDaO/LYDEWGw06Bzn97IMLBk2VryQQ/vJqOMvoYgPOevjoO80x6LFpjiNKefG 7eig5Inw6fvLl9xPfGR9NgaV4CM1pbbRJF++73g9fODrRqsPhcQkBcrs4s0MZYXJR5MqH9meF/Uy Nl+dS8JEmbnBmtyPk/tmNO0e2YTE7bi/FzDzisoAWOd2O7RCEvplrSMKgh7KZcqAseT9/P7wfaz1 vm6OMb72JUpRVrXB7b/u6o7QnrYVLIbaaSnN0+1g97VRTRW6fkLcmsbDl5GX7MrwF1WluSlGm1Ic fD+1YAL1xasRUHZtmy1dNTU0/02vfKJB5NQ+mmS0ir9P4WbXn9glBZFS6Cjnt1htvOV5Z3Ws9vQS 4iE1sMcroVdTA2OSWRd8AZ56fXXEg3W05mt34QT+HEAPoZ5QMzK3JuRwv+yftLRrFPinIJWIFY3G K2f0++fkc61tiuzLd/P9t3md0ZWMzof9hT4tQdRaf/HyQwgvl9HtCTvUaVYeBXtsAWSNRxRfK3AL tzfiqt/a62dMgCZtJDNtrMmZu+4e2jZBP8hd5saNySr05+rduV+4i66JFFawcpqtwb8rYi3DoZ6J pQVln7a3rQkD1vkpgfP0Fz69q+9aOJ00Q+BXLDkX1f0sBcESDxzgEhlLO6nCZXEh0YJJk8JdqIUw isdzhu9jPxyStOG+aU/SF1ocWWxwaVLlqx95D38DGZ4A0l12cSQmhuaMGQB+R06gC7VqGpsA7XDx q8HRqdE/TgyzbPLpotdsVMpduJCLtTmWO9KyWA+GQz7bXwOl8vZadbXaOtHec+xm314oWygLfJ9+ +7UbXQ4q32HPtjT0+wg9CpltqMTiCLrWcIiu9H856PT1kdFmm8Vi4WAlozRqYn1SG7S7aVXjI1RM pe+YQuFD+jwkw/LNJfRi2ED5Ol5QxPhSmKQZ1fB14WXHKnRuVte75qfq6Vo4cvkzzDuR2A3V5nnS DcH/fG+i5VF11pv5zY9W4dVVyO8fwTNyt/B9b6e/UmRN3K1wRi9JozFPzSwD/sUfJkEcqSTNU5ir UNykqkiVMQfwe3mZyKf42N+3E5pPxVlJem8/h8LXg/qFYJFgVu9FZTJcbJWRms9iZWWG++iEZT8J IKQhRbP8m0FTq3/2ZCLJzl7fabk7jB1G3g1K6tlxVF3OJMN5KUAuUVagdUFI95f80mU3URLW9KuO LVaU0l8LeVxGWobUKO/1Up0Hauy+ktqEdFztW3y2+how1AHMs0vGyNV1rOF7jkBHp4F4I+b8/4Az zZW7xcJJoyfFkNnEF6+O8s3I3A8UjaD0fzz18NO85FcBRsd8xAFgc96nl1n0YpOW2hOg4uBod1fF r4CSm34zOq69lWo7OpaRU8vPE5oLvU2LVOXAf9BoRDLecLiSGV1X3w45EOSYaaSw1nB2Yi0dG08C h4j5iNrAt8qsZhOPkyCYoJK3HzcrGFXSRhPlWWWgGewMJHjE6S1pjEjc1lIqQof/YMCbEYRXzqtF AC/hTk18yJlUYJyctY30Qfw1awLE65v9rTLO8vqva9IbDeoKhvPRT9vNFlRDtKyIa5BXpeltqw3d +/bDE1ftihtW4w18eGPOZ8OI7KpsgTypXso4bm/yogalviDUSwVY4gR3MjHvL1pUn2/2mxHgwF69 uIHbzLWk0fgT39nnWMOue9yovDFkLo5KQ0dh1RyVa52RLQBeaJimOt35hRl7o2MlNJQtArcD0bDR jnr96raYApt43hXIYLtJIusvx4nknzG7yT3A11elMmCUhcLu1hkGKw5kG/r/hqiWlJwntjMq5Ft0 BQfITVrxnc/kpVvpRGcmDyGCRe5WKMOwu5KeIUBJzzKq/1am0A/tHgFhhwaHHR0Z4j7WYA8CvzXm acYhtBTwJ9y+VWv04UZvFpcQyWjenmJYQi9Vo5vqu8YpIDBbxe6OwfRGwj0cDyfmvzJxvNGxXhNS VBhb4YVomxCP28AzMJjflG6NEUYY6qcJ1nD82DdfhNOrTZVY30Ai6/SLhRMLzLfPnmJLPzHNZiCZ xm2GS0jizuIA8f4/Ed49QWgFKbUA5/RAdbRMJuiIFo7MW301U+TOx4SWxcgGlPf/Rs5908GmjUjm MBtZTb/qJKF8RhsIA1NER4VhP0sQTwWujq43dmimhM7wbLQ3r+VGcrrnhCl24SeBzpbHP6TCxLKL Nwh/7b8w3MZHcKmXhBKk9gjyoAUvYlvSy/ffNRGzGRscKjCpT17OGfwUpGuqXQL7zmCPtmLBunlk 1mYg1DMvX9Kc3Es6R445+veKbyj1nd8uvTYZLoBvahr3fz1JV52hhSOPKpFbUcH4IY0EtB6M68xq KDxeeYLv1Je9hP1gfku+DrMPcz/YZiMrnqozdwctSI6aKh3HOTFfGmS2Fwg3siMP/vvdL4sZb3dV lkXjdZCmXWLvDktrN3bsxIVHGCxswjnvalGMdVNySfvKRLf2TRq9lq+3QNc1vQkEwvfMMuhBDhif +rpjrIpAgOtgEXISIzOcKIdCrAoN4t+a0KQ6rcF26mYoOldlRWZj2fO2QGA3YbeXNQl4vuX0DEBo U38C7v6SdB4RXjiuRrA+MLJkRvA4VGGn2QN5Jtqs0+6pgHHtVhVJlQWe1Z8CpsBBDMIedxbUMQxX 8txWUa9QYsOc2kI9uqLlUS0DJ7tU1nsEpj3zG+BCPBTM6Fy85gTVpca4ECW617ufF5qGiKSmaG0M PobFswdAgdox/+zpT7js6f8Slqr2vfu47BE07NFQdK+oqZBSBAK5254o7AZopGU9jVZeqPV9MWDy N7GUwRcDSJgufMeA6q8sRLeRMeAX+TXEe7xc/fhCKvjay86Ztr+HeeuCD0QrWR4phtdvvvJfhACj tAN+nPer8r0T3p89xTsMDMLDjBRiPFZ8NDaThCwq4rtdIsNeZmq77zuBgQfcsGspe7Oooh3xG8Xf Rsdm4zOqFzErFB0R5mL5NFPG5wMj7SgUzemTzpmV9YcALjkf7kHBBZyi4YNVsfd10S+Q7VF7DOgZ FRgYVExlBoXlHMezMZPsLwU1mvh98/jxmTgarma7zlF5/LCmnzuZSV7qlMz0QQzex0Y1bSpfF5vk /9cY6mi5xtshYTRpP/HKJcbufTrQvv2GQXJXc6TAK6vPIMVJCWimVnwrQxWWelTtQSC9duAESzNb oMPoU8iil9RSxNXHTd3Q9SWqzPo+sd5ggpNsBwUpM2KaqyHSe9WNa324Z9z06ghTsfkWxRYrtg7T npe2km+9Dc0SOfUDMtrSbIDYj123wY6QDnWm9yybdQqj+32MfiwyUxuWamkhYPCct6NBrTQRONWV /AbaDYW7b/eeS1Nxdp8F+JVW+hpt0VD+hvKbwHf0KW2RtjmJ8uEkr2CfjpCT1G5p6V6AzgLhAbFu qt/KtslzP2E8/7xoLZ/+0FtCL/SgMbflrACcErSE/ioF5n+O7BhZt8pHJbit4AI8mhMGsch0QDYt k3PzIFsWoMG4Dlknovd9mpz9rG8GDwNf8fCITomoiMrYh4tQDyAZK2l1ziBCKqJDga3ylYF1+EbC 7iky6ecGljGYMD6PbBkMzmK1P27+8t5cZAWE8Q7rz9mFoeE9qkgSOCvVsPNerz5+zgls5Lbdvwcv sca5y6reVIcSA3HCPBbaitqgL5EB6D8s8PMKzth1vyriBgH3eSqYqeyjwtegxLeEdHujfC7emYeA K4+LDZzOBg3q0PCAPDGQR3zcsS1M5hLh0TdNCOkKL1JctbnY6wOL68KHwfBwV1GzpB8CrDKJysfV cIlTV7FDhpKn/tE6J4yxnh33UdUE/V2RtO2tY3rWkek9myeJP7sd0flSHwYeJzAJFn6gHGBiUHsp pm3G6TZNUAOj+YkJgdlou45PnBAfa4q2vDZCZUlKaY5zx4OHu+bO/w5rtdUWR/9ued7aIQCcx0AW 3jK5PCQu7+cgAgLSgC/X6rT7ATi49rOI2ocWM5fOdlFcqjTabV7AoST8RiuMtheHAIohXBAlm8dB z9CE0rFt3b42i9rIgoQyLoVZk9Q7NprVwPGiHONmoBEtRQK6xYVy+J+anyrWfvqVLvulMsMUXDf/ GEVAKHVTN4tzLrPCsD5CTr5OfC9ALRN4dZ7W/lu1d0i+D+LkGs/PpMAlfbHSjXHoBOMXaSCCuDzu 5AJEuCEruoXRUzRoRa+cfb9xCdA9ubN4vuq249RuiB8n8nr2I+fJTO8hWAY0ud2/9jqFWYvUqAlP evoHlXjyDNFDM70bKldt3ZPa+Q5yVhtblawNTMRCpIh8gmjSqDCLuJfYzQKm2g4lN/sV0VT5U93v +xD/oLOqFaInXqT7Y4aYcOaf/7L+NcN1jWgXtdRHvM+4c4lgG354dX1w6ExDKxKR3DxbgHSQR6je KxJyHPQyT1nD+N7DyelsjC+3cygp2QhOe198VY4nmQfDzMqjjZf3GsbJkZTDbn5+fJ/3MjHRJFp3 P+2kVjFf5ZpYBCJFR6uqbKPIVu93TTrCx/6CuGmLY4ZL18nd8czCXZT29gEsn8l9I1l2zdPi6C9/ wB8d6C3IpmvX0GGpre5/oW89YzjYLt/HXo9rcFUrYxG3I4TbOCUpg4COJ5Eid3aWYSRRDwL8LxqS xNZgcNJtuUW8Q7k+8faNYf31cpnW2RdAJcPYB4674dkK1h8n3kMygVuz90OwBa35JJneO2nUAp1k TPMLKr5LGxTvn7IWeZkj/BIrNMdKcMqmNIMF5SQeFJUjvYB5RizlvFeVwvwZR1sIxF4i1xT7vYUE MTUjzyW3rsitY39QvhqxOqxH16naMk1kuQLABIxERnv6yoPQNKLwMLYRiYRNBg5BQ5FKCpO3fJto Nj7swIlNT/7asjVHjLTpQFQVrUBzo0uEdPDy6A6MqxFTaT9xaS/d8z/KD61VZ7qmVEnUVippqveS tOCgVr8qYz7sKjqqYrKyeuhP83SpyHbelm7IGl5xO93msQSKNmWrJ49IrdHvyRtUK6Y7px7IuWgA W6FfCvTInvj/Gj03xRmLVRnhUkYszjcsx2Kow1nnoLdW1zwUF4mDer0psUU66ZyiAicPH1nFyRSx T0eGo9AlvgHiZerozA6XiOEEiYnlfwzfcKq2yL2pYUY6C1Ptvgr9MeYpcT9TDToS/nEeR/moOGUl 0xXpJV6BTHquifFuDdY5bg9nCI6GhvXxgsF/qMgnJfXLevKP0vAXc3Xnvn5Ndy10HPYPyRPxUIB4 QrZucr4kWrQDAPI2YHeEivyySvjPaGJkebWurBrNEXKOo5qwP7WUd83JkH9i8vmU7PiOP35kTdX3 PGNl+NU/Iz7CLA/DN99iqCJDY4Lx5CwpgOTjgxCFWl2UeTiNejaXm8c4SRXehXDn5oDC9PB50jXH a0WNacSFn3GCJyr5j1rGbGKzc6iI/kjlzuj7Xg+xWggneVyc1c6t3nLn3DwONYckqDHMxapRu9zW hrJghvAAcC+wQqtag7SCIKQfoSbOj1IwqaGiG3iW11IkBxzCOc9cThIElK224oSUlK4/IDJ9JOdP mlbJSox+RFd6N3TA18ibO4tCVYdYp5UKtCj5+062ZXJRRD3WLxW+VmXRAxFwf9yowNWjD2dBn5W6 o7AD5GdFJpAFxneFecsHLm8SV4avwA6Ctncgt4kdCmn6nvyL4tbVcAMPe/RQuWBk4hmr4zR92wPX kZ60eMDBqIgszOET9U2EjTCWCdFwssCeHssdoK/PLWs5oV8OTAe88j7zIldQEWDIs7VdKiePGO9Y 3/3RrUI3hevfGByfg0RIWl3N98yfSPZhnK/vEHzjJZjzEttjHRmoK1W1QAdA1ptHt9sacfc/4Pdb bqcLsUhi8RJ0rwaXVfa0Vx7XNokYL5GzKFn4cUDVE6SxlK43kqAG8gQUgLpcHH8iyHB3HPtNvnvQ HCqNFdXIQvnjdNP1WeiAybD5jqZ+AuBbmsSuSrVpqK3KoWV96bvwR0N09oJDsvOhDLImo2hIU6j1 g9I91iHMYVVlyZlDbGbALkV1Lg2R8exjPn8DkXdBql2o4ZQQ448kgmLCfnjW4+F/uqxazzARoslb EI4/uwmBmKJ5hTxSjR3dOM/CT+J8J3zyGCW01gRzoE3sfhacvNk+8Kf2DUin8gYNfMXcZ5Ornqzr /hJ79OBBiplAQP3pcUN/7J1ZmrMHD4W/2VFIxSpDkun9vgx6VX5Jivf5e93BsqA4IfxvmKC/bkKN n3EFDVyVsMpQX0d5Vo/+fnADPjlJ3kB8mQujPQhg/pgmmxIA9wWph8d8lZVB+HkTM722DM//+qDs gyPswB97s+NTMkZwMxec/+tw9/qrtuNJly+MWKcF6t9rBAZO8OnItqd/svbrjmKrhRyvF08bHdMW ZIuOgBTrfbDZWQbxpssfsjPxaMj+3+prYiTrR1RSaZmNk4Umkk8rR4RDby6aqOEg9yJkBcmR8seP P7rRbZR14M3SyQ/vCIozKFWREc101kloXO8hAywdOtZaKf1aZFB8PcjRWgAClYdkq7jssIRL19S8 quKw+wGYQVGVfSIHjOCa/oF0yvjMt/JMMhOayqpYlCgdpXUUsoNrkebqF2Hh9jd5Ct0ezfy9p6p0 kEoackUTTOjxLwxn98DCSJlw//d5sCETdEh2k9LIGEORfEJrlL9MymO+jBTLR4q6bj06/2r9P12o dJmNJwj3AJeh0QMhWQX+kqXNFY5fCmwhg+/zef+wSI5Ylaf9nLizJscrg/bkqyIznaFphs9ZZyQP H9e/mm217liKMYoW9H07wC77E6XaHtuE8U3gV7iQI5i4BAZjhnzDjLjDa+JdjNJ36NSPUimJOgxL +ooW0LpWo/cgefFOM/QdcF2vVmUGDOQmZO8PJjvZN3aYRIMbORqAbA0S460HlijE4Vc15hsU6KWv e9DWDqSVIkXaItVNc1jMR4D6MVWGt0DbmSuYCpE+4EaqowXmhuF9pJ70mFNy8AUIqFiDHWjNCfYE 2ZMZkV+MEQcMm8dGUHEl1ozJ4D0RkNFesZ/Wo6K+dkHstm0g1U/ScYIFaGsLmy64Wv11l7LL5Aoo dtt63XE/G+Hac9GT362GAf9lmSJ+GloxuDiAXwOuqKfyLlOYFTCmS2muXQuu3jiWwCtwrfPAs1pP /am5qWQUWozPzaA+mgKHfV2ObkTxwO3X2voBMm7h8JrK767a9TUeh1u9TgwVc2AnW6UpYBzpRaG7 ZcYXL4lgjCo22k10uTx2CZNw0f+vkzDw75Bp1D5OtdzVuC2cahpwlIZr+z3UhwbdE1hlAgwNP3FB iQ2O7vJyxf4Fvn52zRs1qCET0opUhF72Gtn4X0OFN/qlWZRa23lmX1XQbhpm+KaLixN2nWfGCmi0 2/iWOtWK9kOxH7RL5zrJbP+TnBystYCa2nEJG6eVEpsDW2/x0IFqsoaQO3dililygXTH/GxFAuiv iJVzxdquCY80ZtAFZevnbugrZIj+PdfgR12bb8mJULOeUkTHcnkMqoW6JTp3HYtjLgpVqPd9+dKo FYfxc2WUHjeTtlAopEgd4Vu/QXzEcOHb5wgXLvdCYb8siPcsqZxMVWSVWi7p5ux7gBET0dDFLRM7 OAbvufeyaQzgkLnWV/MoBokFfqd6p7hZsSMZeUKrIZE8iNbiAedO9Vf1u3rg3xyTrXlFsknrkMvr I3/ofzWjhADHwTRnulpT7mPsfxii4RqEY1GmN+DDAOg2toINm++Kyt70+jXYL2PjtYiHe+PO8RV7 dIK6cOi9PmAyUbAPco+t4AyPvKjd3JmotDHiNKelF6sNqn1x6bcw/CwzFfrLFhGkLzVbg5eTJI8d j3ZszfiMzIe9aFD2NyHWMk0xu2K70fOmihs/h6+/tbfaASiPsviGos6wua+xYBLflpWPtWgGCVAW 0I9oWYW7xOMyVMQhVst1pOp/f7GUD2zgO+XOeAAMFXpNJ795Hotl1IUhlQM6julD1pf7H7JJM12m z1tO/twisFRCk7BVbNzaZzRjHy7vqtE/of4Bih7o/+38yu2IbNNqpNQj8AuHYvaxdRJTYN1v8dHZ m6n0KCwraqob9vCOZ0GfogftbwKp5gG7PxBCMGrhC6PiUSyxI7akBrRU+0/2PJRtgdDsQk5jXOo3 jqYZprF2oOoUnQXGC8sROccKygaKn0CSRfeTWWwWj7r/cYQlgG2Pl+l5XERHAnfjS8MGnCvXVYWX R23BGpIp98pBpFRKmOuW7cvwQhwz2guFqdxMxTsShK9zL6wd0xtyza7da2oyEXXanu/oT5czpvpi DrY/ni5JeUP7jd7yPKAYIjsZiy84Xk7TB01OIrW/9AqI2ZJ9nIUw2D/JacsW18Mt2MJrl80jt7X+ 99VGoZMhtz4CWVg5BElpFOeocOzAGRDf/PWsOL5bH1Dejr5i394kdjuTDE0HZFOa7xEk5hPMjQwF ixecxafDWdy8LMm6GX5BqWiBy2zT0odFPWDuxxz1otVtxv1gtMZ1uGuCubzN55rlxgpdRRb+dVOM u44meHiIJlnO6icFOQ0M/bIzuNHQ+ISSosTQPlWWf/Ta2Y6hCYcs1jDWVh7vcpam4duZKtQZ98bR JjL0NTaqy6iZInfQmy/C6xCowRN0TtgIzuHyii8s232BCdYjW6OUZ0CCbBUHksvLBkp+X752/bb1 lQmLh4B52sLmj0/47BzoIi5x5UsiZg65VIZ3c0EgquD/sRgmjwM9ZiB03pciYFlUoJHRmheLYmkd jgV6A3iIypv2CEc9REJQkfVgw3xIzTbSiTDv8lfD4PiSGvBxCrSLRqMJaJvIl0u/ra8ZiZ24lGua MuStZio5bQPPHNMDxsF2JJGAyA5BffVPHQYZ9KJ4GYTj+yNAheRsN5NZfu1IAlpe8s2V4u5cO79N os2pHw7jRACG4FDftNK/S41An7LPBEv50jJ4WLWqag6Up7KIn0ZiKV0gtue1ugFpeNIOkTP2lV7E yLXujxXfOF0y/XUtqA8QB4dUKkoN0Ve33KZYzAmLv3RVhyEkjRiHXb6vf5brJyne23bWJNCY1ijk gw3QdM9BpxPuSEvCixlygPXCmOWuFRiHRlwZuyNUYEbhtYJUowtDZ7DQSbQUFLu2w/LDa0v2B97e rD25NpORwidxDgE1IZT8x1ufrqNJssDH3Vlzoqkfm0mpixJecT/XmGBxv7F6bk3CyJIvSkqa2CAp a3o6TEbsIWT73iDlo2MvDUue4M7f/GUmsrCMcTyfS3JHxgna665RihAsjO4dMRhLsgkIU3Fk1owt I8tZ+Zrnry8ny6GLPT/9+FHDPganoTbXM62YNpp205Rns1G9/nBITWDumlPwzts+P0HVn/YmGl1P 4g1HlE9KvGYbbKsrET0r07vtG+HK6HvwYuMdgtWnNQBy8U4u0AdCD9hAxgNWyOUqxCyfuVz+vllJ eICFK4E3v64Mx1ociw3StJD1ETKweoEaqFoaeudGDi0hPI1l/OQqGT1vplt9itOUY9OOVNNIBmg1 jYOn1bLUdsl3V3xPKFTugwbBkv4jNdxTt6TKDYtnOhYKU4UacS2TYR1w9TK07mktL7F3lIOQZmv+ s6/ScCcv3Kd98ix7h23xSaiCqERT/0GUQKsZ7TjZWswCuq8QpAtTzWNuihdGo9kapN+VVHlBYbl+ xWzkLj5V5SkUjv0Lo8gGbCn4FpxCv/wdrXGx+drPAWnjciMjwndr/ybDSMLlsqLljwWBQshKVLPB YbJaP4ERKt0E0BvEx4bm5gMrdtFjH8pkGcZyRYoC5z2+bJ/wgqivEcWyR+57LEHKDmSw4IiARJWs SLC4A2DrngvTwzRbLUWybjtDhNZlf5qlOCqpD6OPGGXb8H1gEoB1tY5mJ8LdRSqTg9M288tA/87a aptQyo5VhHfDNriooIDc9lZ7ieapHVyVPgqRGnSbrc19xtUe029PTsQ1RB0hNKCDyrwX6W+oAdqC jbp0vLaCUrI5H7qWok0gmaKJKPtAJwWZdBbnFb86BfmtQRMANhebU36aAqfieuNFn+mEOSALosL8 ZCFTZM3EAoOU9l7Mw03WRtl01DuIkngfHM67kK+0A/5if0HzrJwjYt20yl/RmxpqulorGLK+6fMd ln7XXRjGDRZvO6KJyKAJs40YMWBB8pciBLI0/uvhbGMRO9fJwMvs1pWaXKI+xbKBbUgPixK487c/ evVDORYFP4Mc5emiQufDyzX5vQTu6TYejKb5bRzHx+FcSpqMpgB9IS0HdqPshDHdZSgdkWY0cpbi +NvkMV43Ai4dDX5UuSDqbnMFRn7W+ifAAriXINiU0cJjPAkabgLBTQ/232Q/rBod1gRXDPzyXBZc AtAYus9iPw4fuZof/Hp/SCd9VLVr9xr9HpfOS5UiM6kqsedmzy6lkPO7fxbsj6/EopTlvLJuAAsR 5rWahhkfIaENdd5wUCkxaV8POHvf7c5fLIMXcmd2MtR0reYNWN/m1l+uBTHmae/9qz/5BxRFz4Y1 dfmU6WnA3Fhu9PO3bOx21jaf2CEJr2c8JpE8D+MVXJp0/yT9QygCZeKU+cRkfqszWp0BtAq/DqzY dYL1c2Y4BQMOC7/ObIqlS5baG6vYlvEJNt15hifYCnhrfFlt1a7LqhyqaS4+CTD4soNpmcN/TXfR vQ+s+qD3+aRVkyvJue8UB8MOkZOF7i/arJ2zzJx3L6n3a5Z1/oDKeLD9v+tR5r7+DsL2lc5nmlIa Q0vKhGbH04LXlUPibSPFYdCWtBgM7odXAFR9MwRYKcvQ12NIqAhWlvDPqIAYvNO2fitJiE0DZQOR Xi5d2pgFJPaG9s7Vd/z/k7+p1CZhgChCnMt0WqqHbtDajG06M1fUfAstBzjO9KV2AxjIrBJCyJB3 3ef4yk2HbHJW99GrsqFpDKtMEc97wMepyP4uGhhhsBEL+NWiLoPPkFupKVdJHNC63K32iqXLY+l5 mHFB186jDr0hsDMpI+sgUJtApcwaXM3q9CSaUFDJ8OZPJpV9uHt7EtzQmVEar/dOR4LPw18tYn7I ZJi9G6CMB1cJfiz1keAdYpjKveEyj/TVaRQJtgMYQGRkp77txB7oSSTfrO+2Iw7hJra+MwPNntXw 9vy0vAexxd4CxZ7vWDoy/FR0VFZWYL5g85uh8auU6+0V+qP2g9am1L4iFJ1wa90I6iza/M0L5lg8 15IrRrM+pRVwGaVnQn0aQqQYO2Y1T+qcnj/pQd4iHyM2jjLNB+ZzouGUAZuOu1f5Ybams36JvwIt eJObQj5w63AguweldXXyzogX4g8Qbb2zLaD9pPPOyx2BMNcYWb5hClJPpXuRQdLzeeuvQkgs/wcn 7JFG9aVSjdUkn4QlWlBNUAy+WXCihtHm8e/q3f4lr8X7uFqyfPHmuQ8f5ysu2+fwSB7A2Zk3Wu0j /VCNGtiCQDQ7mNx0XhJh5Zwsyfagmw6LDX25njbB5/+dpFN59L7d8N7Wtw5feH/vZtqw6N/E0kNm aDOIb3XnRV4LreskvgE2NeR14Xs1qjzw7qEwtmVDUX5xIMYeuJH0zwmBeAvN/Ujt97p6TNH0HF1A 8StSHoiYt0w9h9Un6+5P3FcLLgJDAII5ATNJBytlUzYTiILTCD9/R+U= `protect end_protected

mit

c3bfafd09468012eed81ca01e0e48093

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

77e4ea1acbfd7794a2e6714011d6ec53

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_hdl_node_logic.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block uS9Fi4wEl+hlOoAxATWz7JOEkR0NrTOAPXB71RDz/0sJ9oBkdyJcZqzmiJBSpJVLGXrHypKErbng NIq2yEIKicsHE2U2q0TwmOX5SeBUf5ATfJiLQmZtyrgyJ/TKwJ5Nrg3HL+15E0oFzqZEKRQD0RV0 gUht+SMMiNU2xM6RPT7pKCsVb5W4nxZuUNAOyuABEDGRH8YW/kscyF5trBuA48XfiXtVpzBwqK6v PeJ+bU10he4Sno6k9Dn4FGHEKjKtWs1EQPCyJM25dDSrh8kM7MRJepMfF7YseaGlTZntu/uKxJDR ZL3LeAxQZMrU6BodVmaZalC+X5WBYD/UwSiWkQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15792) `protect data_block j+MxfXo8KN7sW1YIoz7mWvuk8U7o1Pizkub/93qfAiZ2Edtv6EQg6jDaOJcBIYJMZggUHdz1ehRV w0/WfLExxrWt8FsWBt9XaQvb++1FNhKNvmFfqdb5SJ/BrJTbFs4UoKenC7CYGFwQx2tUmqbbLkUw 5KEhmhtuzU5klYBQAZKTafp1RjNL/jWb5muneWOzqFLJ3nyDG5KliHLt++5vFHCwW44YIYvPf+0b 3oxzq5/hdLCuuvX6tVa05wK9FxQf2/3rX5HyU+xHpHXB44zo/DLirti8ui1Bos/+YBrtyi9P0olV FNgHuIAmvHV65Wgsx1+Msd4Tnys0kJsg4LseuA/iqHx39TY0BCrEjVhuBp9VT+z8VGMhW8HUx2Wq o4+eB9beeWTvjQBkIEkrP8lF5FwxljV8k0R7XuXG0tpCEMFakRHiaBzbKCR4eVg9Wr8d9J11/N87 0gIEonGYFz2rXyRJE37guon0Q4OleepmLvP+Ln1uq0vG/26PGOhapt8y0iTc9BUlXsHi7eBbMhQh wysoe62efMNDkdMSbJ1kBgR26ME81wlOJpueMKAOlsa2S71bQWPEz0FDnekuS2X3Yb7pXKZRaKRl 2wMpCVa5ZD6JLPJf7bnEe98f6r67fXBjNRpbVQ0cgePi25j49YCk/qgTsVFMD37MHN1v4IFtt7/l CDOML6mOc7Bhxal7jE9iYKxyjKdT98kpJmzfKjaNQuJ6Psf2fMBJu0+TQDy/9HKh3xR2X0Co5JtS qq05tOU1RRyALfoYOO2052wKTbiV3W3xV1Q3wc6TemwO1w1iI1TxsiJmDfphQwZyhfl4lsaL84O0 AkbHSXvAJkNQ4bmNXWJIrD3zy4KPezZVtgd03sguigCgOVLWwAlAxVkGOkwd86UswxSu+7GInxix a6q1VIoFUL3RFmalwZ8neV3At9lbBWTnpMCAD+bb3AUfnN/aV08ek9qD4ZdvPY9NUCpBaR87lkXp Oe/SNdUJ/zQ9kX091I9joOa1+JMgPQWGZGClfuEEDqP+hDIBpUGCbD38owpFpc5+Vd6sAO3nUkgb zdc+UGdVSNJY27C6RdZOAtSiTRr/TvP/kgzXjl3KntTnJoJVHazCTUZZq6FLwHXr2B6NhUMoaOvg heqYKnZRwaFt75sO1e0t3fOxIJxS6fh80BowyHzdplK05I3TEFY1w+Rg+eK/MTm/IgTNy+v19owQ mX/lIhRYXZQJ49P+M/8y9Q0q3aZWS2JVxguNPWjnagOvjO4bQV1BWMhkl+KanswNR3Bg4RVWmf3Y Yl2t3wXSIxsN0sq+BOrL8CzlcOCty8di9vsamD7ITNDN/Qiga1OurEBk3Bv8ltYYINsC7jSwIix+ bRui0bfd7m6dF0BzZQPz/k7usMkZKShavPjmqftsHzvlzJKsN6jP7tIdHg5Sl/piuySPreelikuL bEibhu0cPaV1BpSnSe9LMVCF2D7It0X6KVjqvEt76vIGNHacpfB8ivynaf7NMxKp9eoviDyaJu73 hrXJYI/sx+/5qFdSUiA6xxL1jedWpbKib+4duUYgHXwRE1+NKI2IsanX1Q6ioqYNMTwDHWZWpR31 ikeUIR1CJpSIR0vAqBSYQoqBiuQN2w4XXzx+6b8nTzgQL+ngGA6VNLYdhtG22SbrDtDPnGwRuY4V hA/Yzv229IxfCSXwTZE5fYZEdEW2PyxNvt20vY2dposrP4Hn2R2SzitywBZ8DNQGX09+Qp+fonie fJYMA9wUDfRstSZdK9pNKxoKFk078UfdY1pc/rLBA9EsKD4Br1OZFW9a/p87fKMqLoQDI0niXJNw 5Dl1U3XftRSKxGRlzRlrB3ClfLDPz7mtKouZ//6XiALyjoMTFSxzw81Je9wY2yixvAlcWh003HBL CISDjEOKwooV75bSd1HxDpIzGDXDk0p9qobbtMXc0TvTkXOSrNPW6uK5WjAJpjh83Mg+W6QtnJzI Cb1SGrgwejbbi7y90yr/borQagxAd96bcN7GTN1reE4lk+Qk+YoQYaHwiwtsyTbmaipDTNCQHC/5 /pq13ugrrsi5xs+REUb6g3+1NQhJ0zl0uHjxN5obttexcNBZ9MkWPOk7frEUJgnbae9jJXbsrFQA o77FeUSX3uxhH75Gm4gLZueJtXN5SuaZ5s9cak1EE4RIbEe+JS/2VzokO1NvMzXJHZ2cgtZYvLRA vQqp3xbK2wlJyV/5zVgnRou2f64H0wfx27e9xlyBn9YF4jfpENZRrb0eoNN8JpEUw9HRXMgtbfZB w5Ar78P/zsRzuwBQ90x9vee2Y5UAxanAQGbuSm7c5W2GNNaKn9yyRxjGl5Fwt0ZPC8ZjeeluE9Ir b+RGcIzYRogoNZ6zDaX30izyzy9F944Tve3CxoStCkVVJEpi3BvvQJ9L+UN2xNDK3ctoX3bTyrzB Ap4VR0Thphm1xlxJxrzpLXBFo4FRCw7L0LB2tSaTxQt17R1912Jj7wLZGZ5Eb1cz4P4e/TxLSfK4 AwIZNi0rRGi05UjsNITlx0PBTi4ae9yoN9aagMj6lKStm64g42M1TiEnyjE3Vnh2eGdY1KHoOqF7 fcyJwKKQnW0atPcjrRfQW51VaSu/yGG13SzIVcp7fckfbyF/B8tQTgmXVPYQEnEV1kylvXLlg+iH DQU0P8rx9/N4fQcq52BgLdytQl5KT0ij0LjMAZed8C2xWIIXCosAoOXL1+YCtHlCoT9XbFnG8PHf +/jz2gmpFfz3+t8j2mFkajk6H/r8xeKiBUImXCH1Zi0wQ6egmdOyJ2AwLIBAydXbgf5EiScu497+ flZte8wgTxHxYzlsLHkfHx3nzzMd3I8F8cNl7kaIP7kAxYpbjmbzxtrHq3Xd8N3MZMeF+VIlXoNp HpxX8crFhTlyPtxuPIFOQ0RLNpX9hiN66HtiWus38sqGKKWb0adGXw6Xyp9nR2AkEOLc1DmCotfZ u0T048JU6mJ5spBlEHVHd4p7NPB0MzNYmnbp/SRVoGjXZMnyc2WSPT69NydRqR2EClzZ9gbxlrZ3 Q80/nT9FdR1vGA1tTelfaRL/vySt+EBGg/0iZ3WGVhGa0k8O3b4rWd2blHVckaKsoQpkWpUWCqSe CHii3JI4hOkxZ6nXRe9/a/ufJfwml99F7YshLxhgqTFgly9kF8aZpxQpzSI/JvrokCSxit+WW1gX i7tO4rY7MMgNG10CtgeKrQ5Dj0ZwwfHcf+RMWO17x/bKBaJCxlpAWtne/wVuNbWM0ANqndmJDUn7 XoXeyLFvZPbOBQfviiPwD/2U0aKpnX77FgEdTMEMTEBDTDZTKuhGvyGg/Di9hBtGrcAnizlr5S6e aOwSBxm8D/tkmNfze5MjXaQ58l13jysFXjfmoUfWbbYHDC9mvlsU4vT9djTNzU0AsVJn0xkeLh+q roQM2m2BHX4McTCd2MweYoQovrXhNKIKB/1fUHkLXidxWVvKBBDZUfTqlW0//hYchICSIRZmfA9z uCWsf10qxRCZ/j638TwJ54W7QOP+pMPans6haF9l5uTUP4jrnRqiQzrye9MVuDywXj7tsVqXwpNr h8+J6F2Jw1dFTEqJleWHjV4wpCkzic1SirOdrggqxOKgQweww2jWujsdId4jQn2bshtVGtLRYWJM OM2rLrIG2D+ucWyQr7rS3qy6aMc1v0Xa96MNRxbUwBpyP9IvBGca+mqwH9lowtIW7FWFpKhAJT/W vlDpPYKdxr62nGbWsT1nAiHIbdnuLIlS1R1rHqleDlgLwCEIBh9co4trck6ZkIeUZ9KO49l07U6c 8AWUXa7ZTml9O92GSbxCNKpuW+/ulg0RLc03tcUFexgCLehvSpP9H2Cd02AXKLpMyhwVZNbq/I9P Doc2n5Kp1EoW2l0HtxLWWKeAZn/v6eSJK+AV/fRTST+zdaQhXt+2feTbis+o/deJhJMDkYjw5yB1 Nm+LYYOrz3pOSooaWA91iEuh0YV26OSjT6ou8QWqEhTFAOxiElV2zCLIUDS0TFkekr0NTZVLF0kY sr3DXCSEh1kE0h6z2vQrhhkb1rhLvE7DReVOrV+IpGArTWa8tk4zPRjcgzpzolsmxyDebM4dezrv PVpSWRY1STlrl9jvjnJiSkD6bz4Y+K+DxH483PtkzPmSW2u/k5y50Wp+xDpW+pKk/Ap5eVhYmyLj u3znKqZsY7Yvl9MfkzUg/ruh9Z02qgmEDyW7fVfOpM196RB4gF/c6jdXtKAMBb0D+B5D48PkbCUj tEA/kSP9SvFtQxCalF+7qLVpbhtjnotNC3SqOiOZDc3TYZ7e4kpQtM5GmdE6qFyPJd7NCGUGRm/u 7ezDlRZ2XaT8gG5jjljNUI/Lmh10yMpYBmW3QqCin65HnWq+w88KMEYbPx5mKNoLoNZUnyazaUhZ fIPq/Ha9+6aZklrrmyBhi6vjuIeT40jqrc0d0TBLTrzJXEVXFsPMfx2ZReFQDqfllq/BX9IdDcjQ aboLA0uFTqEUiTfTwK1Y2kixdvpAr02It/OJxcSKT5OfJAWGadtK777uCL6+I15KzTSsBq9uNLVf 1XdWD9ibAouslawkw6ZqEkP+FHvM/KlxvJsRTUHNT5BfLO6L1GiE8VSAAGPV7LhX3SnugIxYyXxk jmqRXTRSxSkMks0+1keXxKIeytyoeN+9J9l2wvLraZXor8fEr9ITbSH+d0NOgi7z4TE2hpxClxhD mHtjMvNWFILYEOT7O2oZk3SZcoXn0VM0GWBf8qIt8708h9BrV2NNHPjGU2zeBOQXhqk9QzoCgpM2 D9+FQqnuTcLtYD3/AmsGnQfvXS/IIhC5WwkatrQJx3grR5XNPLyAsTTCQdhEuZTy//lmQZbBRKle r3bcFeBJEp1kdWMAhCMxOOeK1WjEg9hBh8YzlJ+UjBHNLHD8FyI+FLHUOsN46DOW/GrwEGyFaXIH EVDVfbFSUnVEMyKPUXOCw5xRsL/4w2RwaMNtK9j1iRXmj4IYIP2KJFV4e9p7SxUwc6Ng6ISq+BmB fUm9wFHqPkQm6R+cVQ6pgBS2Y8Xaa9a4CzLKqfisr7T55R70vu+V4sYBSQMBMTZB50ZxKjix1BzM l4Sj1Uq6W2arDgd5wXrL4czTCrCWE77iHZMHk2QqvtWF2Nnua8zXBrTSvFLPqlsi8md48JY7g7kE 8X9RgiunaN/vghNwUWK//AgbETYWDSonNcpHUPKi8k+3K1Gdt73DwX7ouV7K75prc/ttWu++tAhH ax0AflkL5WAa84Vba4fe3CTVjaVduRwJD/dH7e5xNh+wsYJ0NMJmqSk09GpH+D2z9rcaIiqR1VXN LXNHRaRcNy/DG5EU7R9sco38I6+BM6zVv4B99HOP9QGKp3Gkcw0UMtzpDYt97BjOFH83m0AzbNne flT5srXN4o6nFf3wLeizlgzKbhxp6DPyDuExWymQlD8kTdO+VP5KPN9a4v8JO2IUOxRSYh0rolPz JxzRFqg/nT8Sgs5mRWTIRB7yu5fQ8BUvZy1smEoBjkCRp04xsDV3ij4LRuyBQFxJiXE5/Ehdy1xd NE/Lyx6C/LmMwB/eGyq1+GP1hyQ4xnJRIxI7BYAN1qTDBAx1/MLvzxticH06x7JpzCPTqLZYoEZa R4rwXaBjVoCdHGzl96rOeK0vhTazcB5JiB0LjtMojEZrDDuEnE2/URVgq0GGZ1ztj6PefqoMaz4P x2nQSx7ZfLScJ7GefD0qmNawcmn2EpAJuYNVQbBK1rH+ZkOZJxq/pwIhLPEK7xQa/5cTrJhh3ayv PY6B2B7is4GFpHtrDl5eenn0ZIWD1BPD4LPgY8KVYLu+kqwUJVqR+5/rR5fTxDRMNowSQElGG6// ff8HbTBVt7grCPHrOaFdTGWM91kPbB7puFtkQEATVhy+8jwITdeiUseOMZ+j+ymmuQRnN5AoslyL vpplYWitJoSV7603q/PCqXJ+ud/eMUxWHDzPobEseBFjJ3JMp3+X/5UYE3mTI5EH0pyISWDnO4nz L2R0pd0xpsYQbTXiQAhpyAa2MQ0CdgHE45xTv9mjjBPXB5QreNEyCoKobXOq6bub+zgJKVpY12/Y +sK2NnG0SJFnKHrF8vsbkQ7yjpHAsXdcD/ATzH0m7fcOXoB1Qg9U6XFtFMQjyKlLc36XWTWwXKM/ UlvsWXnBQX1kWX10bMvb7G0gPnVcPGp9YnsxGn/4k9A0qaZZpnqHNvYpthG4FN1mZwVEcldp6gyg 0WKRim7Tu9ZAhTT0jwrRLncoqFm45iP+oHR1jcNqAyNq5IeVBb3JSHXuXTeIEEF9iTXm4W5IZN7Y z+DJvhl05qS5yPoSV4m1FBOJ7k/2MGcvyfjKqfmVOOLOmks+TY3Y0oBkK/T+Q1cY4qz5cGSkRFK3 YjSJwRY5kJnOEOvDO29v78JHgdWDtqbi8HMtSrvc7iW5+9ltpU0WIOflx7k4VMrnAcvoSIqOPkh1 IC4bqJ/Q5Sgd8UoCLrRxaUpKHy+uTmFNSTOgZ6HNrStwcpgC/fXM0FejnwJ3ym6CA3G+Vai0meui oQE3/wnRIgIsTe+L+GasmkXRUQxVdNiOzYENL0BW41ADiYiVPrzax+TT/SP5K3Pgc6l4Vft/CJmh 1bUzngIooldmnWfssSoL65S06EJx0nOMtl1dqFypWFIDhxpWNSbAifnuELaFr6d9QFjQELjW5c5j mft5q520uAgs3k8+IOCfvgeUiodwYrSMnoVlEfRA4aj0AVp++7f/YDGfSu2cu8BvcFtYPNyeqFTv qqJqy62/HHpSx8MH+L/RFxxPmV4/9Kvm6S8yiI8YPq/1r6rLncKTGxvw33Y878SGEwDB4BWgYMPk z9VK5rHTMY9JVQl29TktgaIRb3rMibimicRkPeFmtyeCVXQP46GtehgSVyijRMMk57v/mkZQkwSf eCrx50lDIPXRTjBK5xo80cOcEe4XJZCa+O+mfypfuxmg4SQXuWu6W6/ZSdllB/Xf6S9PnW7DEF5K kvYyrdr/SozTg9rl2eQY6QcpUiX4P9JaVFSqQRUQzPkOSnbrYYSScdnSouerRfw7dBZZLg3ZbupX PERsO6YWHwHcuKdJNhUJWs0J/TCZB7AOglbTEwbnkhvCpybgTHvJBXyeEKFm2BWRx5uv533H/D7R r6H0sOm11fJv1lvmGKzsUkFMeieG8uCCeaCj5BdoOOUeEpNuTukGdEUCvBG4H06cpyXxY1NyEkDU VEgLECpm6rGz5UUCBVXwW57vZ80WjBKVINTIJKb9rFQTM8bgKzgRlsGzvxZBgCb2ds5YKTkBdlt/ jkly48/CRv+CjB3p47TLwzpUZEb88Cz9dBK2MS6581yhzlIHd2OGrhMkAC3jRbFdkPu69RJ7JEGt EUVKSFAqZ9rYEeXLH++KOJd/SZx8wB47HQs6EUyD6EH37olUFeqaHy9sIW4F/s77US8S85Riy2lJ m5KF4BlkKSQobzWoAHLv08WSafH70vRVH3cb/LReNV2skP/HETKE+iTaQw2GNYBdU1lYRxTiCfU1 CSi2rPV7Uf3TYuFWG73vfzfRAeTlJ9/+zlchznUWqRbLPYItTRlLzH6MTns/JaaoX6RF+9RW5IsL 17y38nwruiinCqo855rUGbpFBvJzyZVdQvmpVtQIjy73I0TJATa9eWTT48lMjLH3tddmijOT+Mx5 ejuv+EgPCXep1AFfMRzi0/gfh8acihR9Rt5znqG1pk+MA/XLb/SId9ZuJkgk2Oopo3U0FS8RG8og 35IZk65hI00f3fWltHlQyWatjKJAXPkmGM9SoxHiEgBaW81GkAXdvLLTiwmX9pesk+X8BQA2bLLS t0zRqwdKOyih3pG2j5hb533KnO7kIDFY11Hd09In9D7nIaHA9qcmqCBX2E/ZFis4l5y4qyvJQnfi XMx5lVK1bdh0KwSGGGZWNwrNZOVvqH4869+HJYMplKcIcdO7EVB+27pqMfpGWj88MTxu8bJ5sOv/ P7ufZbX/7TcknWZve57E+B1QIBB4JdYrTIRP/6iwhdq8ku8k1JqEewxX5TeomQ6T/wzC3kVdHTac BQYDZWprtSjyVOdUDEgkeOu2+2G9Wq6s9GHufTAR1pxiumuo2VZ0i1U9ynF8aInRy0JDlQ3+9Inl 2sgM9mEfga80mHMRjkzxyK/ygdNtrJMEXkpUA8rC3XGr3cMFtuc4JjLKA/JrJe8xtsaUB2qe51nw R75S8IextZ8ufMaxrP+CX/B4ncRJkj0wxRZgdHE0mpgNPPm9RRH0X5PKOFIqP/7Xwf99aFIpynQ1 9e++2s411Mt/ZqomudNrJN95fxLFmMUPxLDh6jgWPAh5f5byuUgoh7xTrjnb6Imwos+dhGlkIgPI Cx5/A47he0UYnY2g029IC4KWBcppUMQjl+ryLcLt9x0q5OMXzdRNGlDevlI35NY28khS+tZ3EDFd jVjo9LJT20IoSK3/T655/wIQOvXpUts0wIuAWyxRGrzin95Rzf9ZnDg0UVYUtw9T4V9DvScYp+Rv YFQbkFjJq7ZeDx8OMp49PKN9YSzind/6RKzqWMb+r9/nD2wGyyMRhwnn5Hdlwnji9ICzIcD+l8Ck AgAIkV3AmumeS13Z2ujAVrl/Y5Z9abvNQ6vwa8Ge8racv+MipDLg+tpAUFyJiPGZdae2WzmesGVd MUgkq6qkclvVD8dRjaGmyQrT18ZTRqkqAZgz/6XlwjLuU+cAtvKjkdeuAHk3hgF4aJFFhs1B5Ler GKoW9CSA1nwtJDuFNeyNbM98rhe8xxBb8o71chxGoRGuA0UrTXqwVNi0qy6XNf/qP+k87bWLVhf3 x0LrEMaYDY6UmzsHCle2VwqoqK8OxNnwFz4ozack/+lhJL8UbRb0yq5CPxhmZxUKcjQW+w8YmA59 +yCG8nvUWqsCn+QTnGVtoIHbgKqK+c+FEh782CfIQNEBypS1PpthtcIpUtE7/qNBeprRa8cd0GI0 +j3WVoPgfJatU529eKLmEpPkpIglbZdVuSrikOOOTDDW8/AH1iOCaOGRIEeElRLb3SnSgWl8vtKq 5GVoh7oCFSuRKC2BLjd8Tt8kkIF2m/0S9YjqfJ0yY2By0RSknljkA0Gwfd6NwbFg9rXqLJMUh4u9 i53bJxyUGEAtdzJ/IOmiIouTYjrraG3Cob/fVm4bSbXum3FLhtYRpAbnkZye4WTV+8ccRSOds/7B oOAIHZiWZrawkruv9ezXNFSvhgElk25h0PFO1loD71qy4fPXn5FmQ2oxEqXvFyzh1dMpM5kGCc/r CPq4nF2XWMpQEqKCUVQWiOdhT5pPGBoVVPsw9N+UiQW9gnPGv17ZTdE5pqVvb8xypJ8lgyMToB1M Xln2LugkvTRI628MKgXMlnX01lVcHkNUmVIEfxj8bO/dHiYgiZw0AkR8+4Nw72bJX5bgXhmWw1cU 1PDkwxel3sdwCVNuVmQarjjlxkFvnNcJRAIGFrQ1FQaCANA3VM7OWqMCk8c+upW8FmYNKnrSCEb3 XnO0N+2i6vP1ygewWytWajtljWDfn3/iiB7yOoVjjJmaUZ3kOi9ESELyMo/+qMLg7MWD9bIYg2XE QsVkKt7uaze6K+E9qOKu5PkhHTUO7m2jDjt2AEOZU49T4S0q4AHzT2bCyczwPod8+clTWS6gNzdM j/E1FFPrIvjx/jwXyla1kJTs9BZE8NGw3fXE6myEGEo0kTFhIksYlLQRqMjN/g6o+ta2E01ZlxJc 83MfbIZu74pBIfeqjscBROCN9l8a0CWtSFcAbvBkWaNDjyn5d8tNehygeIcgIu4dZxDOlUAU3Fg+ dXLP9lyd/NRmYlAThQa5mbnHIazow53oRfg6usJHmIyAwWGFi554Be+sgebKaeLnr/lRI8RcxPbK +6W45oTsrRSPopZ0/UzeMJ+kckHvNItMhyEZ+dfHc/CSY/YMl8ufhS80nqwYyNCoirp9asDIo5z5 p4Ik8m0D0tasIcPaiT826crezDs6o9LZyhDyP72rbuj6deKds+CWE3u+CUJnSOrumpXeSR8BIKnq 4HTM3Zi2zsHK4eo9fCNxfRNa+6kBgLlliviOHXgxhplQNBB3pgeuxhkH4OMnfnQTW3OS2S1hS3Wu zjd+vnF2AMzT4IOxjDHCB2RnrEVicz67qnvJJG4clELPJOha3NJcNbzLWQwdkav5/Zh4AHA1nCWz 38tN01k9tjNS1lhdGFnBdWmTIpPbl9r15y9PDtDqDimQ3OYNA+jBLjbp73GCsi8tmWNQ5TiBsuyr jesQjeq3wPJQfTuBwACAWtXkXnls9jJP+p8r5yS8sjDj+QmKr3wKTT8t2INqTCGu8hAjkECWVLRl QsxiySVaEZ75hU5a+rkk/zhSkeClum8TFoeNcUE6zHlEapoGDGfD2YzfDs5ngXfR5PyL3A3wSREF o3CA50KEMDmG4riy0sWnO5PD1Qmvmc0UuUHj3cyhWsKKi+GWH6YQQa97zbLADvicvTE6A3OoWu9M 1lGrHLZSqf3SsldRfXqxzbIMy/SZcvcHX6cjoM2y3wooHoGg0nAB0j/A86g3RFU7LQ1C3owBCIyl Ur8OD2KLH+TVSrmhXEx5G/uVjmxm3zNNwVcc5A/rlWEsXjFZgOcvkX5O+J1pu/nAcSLhicbhIzuw wlthM7U7cO55Eckt37USoKcRw08pxFCo8+YFCf38HJnPYVPxRmFX6KD6Trn+lGYcTo1rnpCamBFr NJ+FGHNsYQY5C48wIbj1AQ4/EsikcgxylSINRsZQ0fEYcnBrZTAOxaFjoR0AH+yBzi9k53CzGFm6 /tIHZSyf5TZ5lnkIu1NKws/NHChWwTUnUFaCf/vgfJKzdYYGJWkAK16ikVoHha5DMhjUiL/A1wno vS5aBXc9rtDk0j+XfkiZOAxN2odibHgPcU82ru8BAPIWPZmcJPqq6oclYALTNpfzO2G5VXY98Hmh Iv7pkBlwCWPZOoLaN5+Cv143x6ep3efEQ16op1wgjxEfFtFSSccp8JWbZDgJd3svkw4b5UIVglGJ 19LiNPS7GOdQo66sF3bJSo529I46TTMTe0zp29Mk/yDrfWtu3AKorUox9SEbtK8sWCEn5KEAveV0 KrGmg14itb7e6ldANjwJowgJmHdKn2alHfi0eiA+1HjG7ywLMVZBZ7ddGojwh49NWMtbj06JRbUu v6e2BRoPs+W5BcDO/bLF5v+/ncACr4T7AvknpeYBiMFHQrjAK8Q0zEY1WMecz2F+5UrrqpcPueL6 /IlspN7CxzRFIRBqrmEruEIE3Xgl8d5bQhD4dOyPCghNX++JNg/JIZef9Gtq74QA6YPb7CzusEzb TLyc6gwQmpXtJaUy6i6lOL8/wc+k5DZs7q7EG6bG7Z4dvjRnlZWm/1XQ0jrpBnYfBsZt8Dc6tvRK fKxPK75xcY6p8yPLML19vcJy5vdE7LgpAoskF+wlf/QeTWPpZ7DOZb8F6e1W+vk2QizbhV/SgpfC EiXqMlodn7JhUkScPHBrNaQV+Nck1kNTtO6brxzVYfMjXGJ4SQms5c+A38MNrRKAkJ19PSy9cX/7 E/9+BIhkMu7pjD4aa5t4exuKFbc/ILJHz5PgfyaHaM9tOdQgA5O6U0YKGwqEN8O9GlE8qTBNTeBK /CzddmDx5Yci5k/TQGDTZINsvXfGETCfEBHqJw63jp73Avgzcg1X1Ko+W5K7qK97SBBnLS0ywEVP Mvpqyh+lt+5XphwoGyT5+tyBAooEBtctp392jkJugdDUL/8tR1i6NN/eV48heqfYvuWt8Qx1NaMh oHtOKWdNU0TpebGe3sLyR0tg5a4ZB7JVEmbSwf94aEzAYdxGGMFS09aHh2wwMSZZFyhFVMBLU/W7 RoQQpYDW/YdZ9eBsTWAlCZTdpu61oQrTYOUaq8IDGt1941qdncNFvUnUPZb2wg530A7kDcZG43Gg BFpDLg/LIYUK3hRnPezRwxJSIHEC8VoLOFFRc59pN7gyN1Yewzn5Z2aOewnaNXNrBu3G6yepvQff hn1BMeBYxJCxIqBAr5Yzcq0flxxxyCR9/PXfvqfBo/dqgQujciN159I+uz0PibMO/mfRkGLGOur2 Nq3BdlDiZw3SSiVQtbAN3JuvT58anmKsN0J88E1NJZB3Gv2m1G7mZrdNhxyXUIf6PTfnqecsWhUE P4JdtNFe+8cnZ9CNKXRifoyatyTkTES8KEonv8PsP8WEiCNOZXLuVuKHgDStiDuQjSIMScTx7A8Z FgBBJqbC3vB+gweExRoZHMN7B8w3WP9wgmotlX1hwCuVx9UJBI7eD2jOjqNlsm3OVRL3K2DaKbxE D6L+U4uqnhu9+L91KYFDmTCRDswByd8+mSXIQkEgNilSZevqIQKp3a8Mk+MW0LxNqC7pazUdFEZ/ bVP0w36X1c/hlAKpOppmjaIk4h5ZJqAhHimxYx9Qdt0w8cQvRLOwJf92PpUrqJ4fCnd0wj1xRbXH ++SCrQKmFtHdWfCtlPrWgUeVWhiFWXtsKzsM+nthazL7k7PUGVMVOeXke4fNbWBSm1/WBXa7+Odd 0uEOJ9mCTBAcGN55NdhbCgbLSJeoClOGKY9lc0/RimVd6VZpYzyZfJ1v/tUbjxArQx6D2IEcOJYc R+kIqVAUsVbQ2LfliAd20c//iqceJNQL+qHOQ7jcQ6Txoa7azcsxT0TaKQQ8NZ9ujrbkhzRykIlo alnmdfWCd022U6I1VuPNOmjVJQmanUHvQNXncDsooNY/SjMCfuQYs+fcZRyjMAlKbuG9Q0XXO0pB mm5Vr1GdPEp7sjIRGGq18NHAk4/Frws5BkNbjZgeMv9KUUHWDYotCr+NyEf0nu0Tqb+P25uRRkVv H/d9lEZwu7UM+Dn2HOBTqcjES9jzn4VQ/KBezGA7cDisWhtKTlKHkhirrI/nVjSYsXrrt/OavSaN eutm0ghInhfoLnkJ5yb6RzuJmY21jKKhdnAE7Zmk1Gz4M0oy+lf/3P+KBGxNTU7RVykbkUoF+oRG 7yiwqXaj4JU+cKNpjm/TulGkDt07yYFCGnMnsle4ZDaroEqg3dAtGejwUkk0nbFFNMRZn8x/t6+2 sKUjlflAQeaFKEdZo0ZPU+4953jrOwznnJp6o/lMU8mN/hyulYS6DdxAtmCu5TSG+UVNkN9NXBVG ASxGw1D0ay/j5WJl0BX0d23ntHH06At+jqISAwjsGdzcMa9TQVDdPSjg626SOx8Z/69b+hnKps+h H6wJ3Dl/mU9wWE4MBjGyxEUazf4mHyDbPK22AM0sv+AuF7XuRJqwg8RE6qVtH6ZF3MsSR+eIGFlJ XBhh5PBh8Gva9WPG7K5eFQb51WZc4R5kTmU6vrpTpFXS/dbhB6PkGX+29O2SwxviEd6mdNDfCTcA D/dK9itVAYiw7T5Ah741slBmz8X4T1JO1VCTxNA+tBt1oscU30xmozb3KnAOXQ9M08dWVpT1uhT2 QFmvDIUuRPfWW46GmvjErSaSx/cpK8ha2JlAu6MObZ16sKpu+kyGNcciCS0xAgD7DsTM3Zdkt5M7 vs5WT7Jtp7e0EbyXWsLDWwtx2sA2A3Koai+3BwDh4p98j/E0W3ULNHLJ++V0snOU3afk47XkojXv 5I4buLa7o990HlpclzHl6oYMPtK8M9nFd+TBKqhEzVgNPJvaJ5g2lR9bXeoFUaFisP50XrfXbl7e Uppzc2qyVFUh8Vxa3GVvUxtAIhoGwPpVLD5voXMSpOQzbKT6zSo+wh9Jb854lB1NvAwEB77w8hyX pCKxReIroS7wa05z8hR/FBxvsJdLWpAtJ2mc0Dd83cm7+r271u1/I1Bd5Z2OhuyfKdsDKmyOZqpG SZWNqTCeioLU24yUTqxuonU7BDQXNQ5f0jswRCTbgkAkCp/rZp6Id4QQP7ZxKQ6X0gpnEi1nJe9X 4WSjw97iCfySLosH+7k5Wp6wfPq8nHAjwivvZwh/pnsye0qK4c1+ZAXBZn9MD+Vx+gCsYB9DU211 X22rdJxmHUHWK6fvD3SRTDqFhusinj7K0zHaqM6MtIfQurpMoRpyCY9vhNpVC5v+FugozAgzdMot D04pYHPBBR8P3DnUlOtc8iOIUoBnmoKUNVPhX53piFiuKTwTvlnbq6Md8++r3mlusi3qMHkCfjEq 64ysycdcTd0Zf+g/XMWgaOd3p62YLSG5Rg1+WgbgXjFDmQjBfBxubZS4Ua8OiZxuoHV947R+HAqn kMPfFDDaMveubfiXcIPyMylH/IbMnaTyLsWie0q+SW9KFdQc5j5NCRxz45Uippf/T3YdmSY6gWkG TH9jprmk/K3Dr+0vI9Ot8VA2BycSDk/n9EPsrFGqIHvPXnQ/HBpbAlGaqvbwJzB/dZSmi2xIkQ/f 4+aV9t1zqXbEf8SJkNZp/w7dh7N1jWKJsVc8DAskyS3pDzhS2jt/NKRpPpmIQbC+Le2+M8IZzC64 E/bHzv/VS8mOq8RZJvx1p8GT3gz1Y7o2sszKTKG7QW/VRZMuenlBmTwcf1tTRvL6KB3mvY+LWe2U yUJzy6I3/6OrmulXrdyzP9lQnFz4ObZ/753SquOUIakfA9OTvulq5XrdFvFcJJhf4ZOsL3aNwQdY C1+8d1nm8l/S8N24SjldPg7SiyvDalpZ6tLdC5+BS5ZZxghq0nLGIfKUuMucZ1w0Mhorv6Wf0oZi IW/NImY6tw7jOFyHSAnAeKeUBR4pXjOjZUwLxPw/2bVrtLyqaLCSbz2xX+2i6weCNkOlUro7yxkD 3WY9Vgu3jUd/cKPdiCRH8sCTf+sG4YJgB0Sw/4o9GbQQZyBDRofLlohmPg6xuuo8KQfF6cAhpEqj 4ZLhtES2lXa8hNUWWNWSaGMkSS3UElUVAmlyRLbSXXlUCEJDb9IbmC8DO0jrL/+Jy9N25FPMc1kV HcZoUTc5dZaYX5G1bu7ATMKIKMVANQHpZzqcAI8vtq7bwZ5SW7qPAHcvdvQVF5KGZXzz2rJEqPKN 5XkHf64Sj0XCAAxlFpf/fW//dA34TMJLmosj20DJbOebkovfzF10KziQC7lYJRyCvxktLH3dBeqL mVRPv6lxp9dHkNE13bMB8pelqAkZjPtWycqDGXcx0JaeZsRp58eBIGFwl2e4FNSJ/0stluJCFA5z /QgAgMaP6txdTaGts0S3uEt2doI36DAz6kMcH1oIQILAoncwd03YiZ+L8/GnXFXwmF2+A27llWG5 mFZzQiUFLO5013fUqb4KKl2tgriLHKx0gcrWLuH9YPqLgobGoMPH3dCch/OHixMO+IFArAA8PTtV K7PDgAiBVJ77/fuIWIZBnb7ohaRdB8uy9vXpNFyrWcdPJ/7iG+8j4JqLPQ7uE3fN6AV61WFK8eAq J8xNgzx+6OWEYdSM+lJXoyJuC5LgDOb3tzh3K4qJgh49rcVUwAhCKwM2wRX6e6JU7oanEO+lvMi2 gXRSm5FmFo8DCzuN0vJJYRAAFlYBWViMrTC0ZbCY7TfjQ9jri50MadOsyoY9OeVMBCYT1rbU5jiC 0Do/vK8S8O4/CISi7p1rMR0CUw5LI3SsfkjG9EhdRZWwDhPI8zZuER59wCM0irBaTzhMBnpIe4BS BfGVNqMYMhbCRoPcw01mrTHF/W7rP68dux3A5LRmFffVduOQ4qBG5IenAmfhtKbTQlNZjJt+wsrl Y0wtU8YG+FtHAcexdXcp2tPt1HfHzPbSRiXPGqFn+A2L8nZkVR6t/4ahQ74QJMFrVl726fuaa5Z3 NzpkjSsRd2sJz022nEznQCQrjn8Lq9wx1XEs682tv6OYSZ7t1qeDDtIcKvzbbL1Oocb9brW1Yf1q eMdWLrdYX5SHSEPxFCrGpLNQznTT6etsW0ymP2ixp4p5AmveVmgSlH8NNJjJG/RG5JXtry5az+We 2vgjGVuJ/Cl1U63X/X9yZaZdbYTwYlBNNb/oFwAAWI9IC40fRmkQIqYHfKKTG5qdWS8iDDkIjli1 6Ar7Use/i74xeCjGs4jcsn8yA0L3wAejFKNjuxtDWN+UzjjfhD8X8HYOzD/yGg4znsf5AkxQC2LD f8ZjWryOR5aBNiuaqHkTOlIolcAdY+StnmYv26EQ0137NVtOFxZ8AUDXPi/axrVRXIx9bb0UBLEp fCFmunKjDesD/EioXxMrwrZT29nAZQx/zrhx5Ujxb3G//816ET7NlOxo+oG0a4fQV5MVyMal/ca8 NcLZgLDvblsjX8Fe3vfr7tlalUkxXVD0Dg7KXlWJnLNQIsioHjWH6BiFyJiRO4EfN5KHUSnHVk2u JZp2e9XIj/QJK1BUCp7d0d/8UUpsy0CI9QVJRW4aJ2QkcD0SwY352dNcqy/NZB61DQEybOBO6M5y Vq/xakFoR6xJ4BWJMO5f6k4JOxTy38vwE/gI6T46Id1l2tTL/rstlmQBZjIK5ycKQ7Oj5gZ/vJBz l9XSL80DN/Qom/BX1awAxySefouaXb082BHUbZiusrjy2eW5IRrSiLr/5VgKeAPTLb0FrbRIKIQ5 owKx0eUazkCfZyuwoxgr2nCN9fQYIFzp3DqG/wmsp+HA5+Iq6NYYIZ5NxMi8dZSmzOWt75awS4hr NRhNJK014ys0FnvcYnflQlJd2ZcdvIwIZQbbg2Y6lNooPzqo3IEhj4o16Pz+doFuR1qCRFW1up0p sRSw2RtYLNttxzQppWZ0SIOARJaAvgNwOPAju0qbR8xycqiXeuGwCx6uPtkcV4l0rAE24IG5SnkJ RS3LDeLkySAy+csaVrMj6ZvYq1eODylVICl8nSu9w9Ang4D6wG8vDqWHi3kycCh+Z/gd5otbFcRv VSH9lfLg2eATWyUYjgnNnJ81a4ZIrn3cdL5m0BCR2lqKiFATlu4SM+MSBP/Lqb5YIPzyNP/bqD68 RgnrVPeqfW0OfJvGb4pHsaKVR6KGERJm6tGzcM7XrG6KC+rEPmDI5hi9k6/KeYF6u8C3N686haAO 2eX+XikUJaCL2GifoYADwU4zOkTHauuDZy0M9/shOqDE58TDMPYxKPwlVkK9yYJjX0F58C1qJWQI d4nnpZH9UGI5Ix0s1eSC2L2PSp5C0GLQC58k/8yeI81iHMQr/uG+xzGFa04d5uQjGPlFzXstXROo CsfrIz21XM6yZy0Sqqk4QsRM0WC5pGBudwt2ZpUTsJjt4uVWWC1tDo8qm/khOyJXCr5x65U/VYra xFpi5PoxHoY4WT5oazrWcc3GuC6zVS3XW6sM3XYYOne+ElW+NPURgjI+dLutZzjGtz8a2wT7Lu5E rdfCLJuYN7b471oPQBuRvLdXLpQH/up7z7p7URTRWWNztH+Uk8DtE3Mc4jFtpkZVFBf63Rf7AZV3 mxqeM5U7QbZJqSglj5J2oItEMUrooERHfvK9T93+UXaLwdB3JrrLkTQlrcBRbBsi4k9H+vDegMiU qZZzT/4LCheqbEfidD4saheMZhCPak+Ao31as3qIh5OJKKaS4W7NFNuk3eHjSUHsPap4KB76ymRz Okg7EROlZC0c7BR8Rj0ogTUyaIt0xS8EwouqetirGKetnZFDisgayhPEyo6NKM6+lf+m2rIrGWhV P1rlpRguEjZ0R+94JZdx+mY5eJo3qFCEWMuT1vcOnDBYjg6dYGRfkVvVzzCpJ93yWoivBXPqcQCe 2pAVd/GxfakoTSLo+OdeEgaAYebFy7v1HTqvjJEmJop+3REWtsBR9KqxhOXq2wiHjHfewqpzOA0L /js2ZmIw0vyemHT1OAaN3KiPnSdwnIIUm8OAyfTt+VD/9EuSrsCmapY/HEb8G3uqTSjcLqljDqcD HkIesgLbHINqQs5aLcI93ysXFy+MZvn4PFv6A9JHpbjDfIUA0Ylk8OqA3CIc6/DgOjEQGKxDRejk zw+sYGxcPviUHIcPG6B9u50VCd313jqrpHMLlh3FTmgq0qfmOA2YryX4h8rOl6YnKumsrD+/5qV/ 9Uj1Gsjwk8wcxLE40bZC7JE4ZOmx3e6rcIeiLX78CsDoyrtBbWVKoP2zx+Sh8BEHwXbHUN0gGPmq IiHolBwebsMHf7wxhNWOoGI95f5VX1jR9svHG5mxv00DhrwNrSRus8LOZ8eTqMiNJ4FZv8Ab70o/ sOT945CxD2nV9SNimRwQy0nGZ9QjwBgjRZb4BGzcnS2QQP7uG8mz9V5BEAHg5eyd9eTcVOEkAt8v xNnP3RtLcnCC2rrqKYi/oZ/bT3GIiTHSCj5t2jeLsRPt4+KjBE54gLYa2WoYtmrlEa1+6BbfN5fh efAHYfwjgTmMntTZJGOrsH0ryxBUaah9dMERqCi+naYbQ0KKy4VRRIve9J/vziupKd3Ix7QDkym0 HtfMvry07zct+MnJl3Y5gfIoPg2L89Il43rBdMhYFMAGRNQ8mWJY6c4g4jW3KtQTJvZuQM9zJQ/m wN75MeWTabi5ho0sD1RvaXBuoCkGPtW1K7DXNmYVh5zmY1RoPSUvX8VHn7SwvCC79pzlKTtZulWZ q3HW2J9OK2zcyIP/nLzSPw7WwuTy69OM+Q0Ec7zBmxaDONP/YQB0gXQikUxTjkEfRX+BQZ3Q+xH7 klkP4bBhn9IkY3NysRu1IMsFAwKWZUwNWKXF53Y0bco2ezClvN/tSl74N+o/4uHr9RBcDWoFWvnx zC2XAloMeUKMOQpOA3I7QGkgUxv0uGQDd14HTqgEb4iI8aDfRq6tYhwkcsAzmk3HJxM6isQHOigB 9IjENcivX/bcf1zAgQhFtFYcw+nJaeEDGc4OoJyqqr6CY3ul5GI59XTkhomwBjyBSIiTDESGupyC CkZdpHF229+QeCfLZdOmbHxrnBY78DnSYp6GCXv65tXAX+tjzhWNew8jH7tkciOUZUJSC8YRuTs/ Ljy8Uvw01gyYmqgKjm6zkg3LDAPLFEuGTeei4odj/IYJdjKL6Do2DmIUpzEXSKGoIWwcN5PnrNeF XvCuzY56FyjtcsIYe7Bbf65X5EAJQYS0hbfMNYGE09W4PLewWhpct3AJcahTGKyUENckscJfz4KQ LPzvNXi2k7WIjZLoJHz2th2g6ZzNRgGoD3zsIauBzONB3ZrfJWByKS8m+MxslXlXeIL0b1JjL3ro t4OI5QAu9HGsisqztIYcr1CGz5DtwJKp7yHbpyf9j4jfWYkH6pXMhAuugGxlMQDjb+tpSa4As7Q9 act3tBexrfyFtWnh7tfxRhGckwi9BlMVNMMPHBGZew5yj7+5IfrSuVjHCLTTNwr93XUoEdVTY3Cp wsKl9OsyuMUCQImqfJUevV9DQix4+OWIFBO+dVQgJDuCxL6JQMpDl9tYcShk6AiKfSBCK4EFdPjz iNQ+XmZHKUY4DG7KCYengI14+/jPdzXg+LSVNHDZQ4O0toaO3ngxKaCTcHs/OPIJZyItIxUHhxFD TSfdAtQtYVz54ClMlnXoE0j3JaN2F+nCy/t5RVr+SJFfoxK3SWxOzbgrWmK35JpGv0tMWel/oZTy NyVTQBMVfHYToQqmH58mqgcsMpisQac0KxI5ZRzaLS+5eftIDcXp/ZS3zaZtQLk+ek/IYkYbH5S6 rZvZ0FOyLfAPyImWvecLE/ynAZVe9HZXgy0vRnj0zBghxDp9HMZhT1A1B/BqoGOWvVkqm7qqo++Z WyqwdNq+ueqT5UrJD9vcP98oBBM2fcWbMxFXw4rCeieZK0p/epTyjWmkfW4xljLGYAUtBRxHibsf q4wLGACbFmeGzeSMbuCGWQKOCqgq7YJxcJR+xP4t76Xg91XQN/mxqhO/pcJT+bxvAjZZb5f3XGfH VUTCyI0mUGMhYp2SILNiLZUMjAq/fzSYMrnOANpg7YCc+Y63gseyRkXrVeSRbz0a2c69j8wlED7L 9o5YvHvIRNgWtLqAE8TjAX+4qnnB4cCipHSkelssEsTRlopkoJBENpYDOnvdtx8MLPYNvyirG47T 22NxBEyGihcjSjB2x1vxvUZ7AfP148Z/8ZoucfFddnCZNhbRF8rNgymYITE9GrNPCM4y36nrFYR8 pRd4NCecYtvnzDe0+ZkoYE5oH9IVIicBxoWyBmLgHhfeMMP48Qoo8BwJVZ/lnvqTK8LzN3+hnbGV yBydbVqK9c182Cj17hnqDFQBbn5+V6BDhw8a5YrEW5h8CZK+ILNURsCgjIOvsjJEUBXzdK+C6iYS zPiUnTiSXvKwuaTHrRAAIcNgv81hoTDXEd0R7o4stIX3IgoJmTsGBQqL1qdRRT8pwRtp6XdvIC/9 8rDqknwF7X4z60cGelgYSyCckDDKueEHvtLtjpQZ1NqibxG8ZxkpSr38Rze/aJZh46bgyNSpwHiB mgFAOyU2eptm5OGmZA5vian3LWEbwvynaa1ONXkD56ucCpp/+mYoOdxnH0n+0qWsirXGF88bxYg8 cjkqDOKVf0QfpxBkCqReo5tib593+zytTyB9vEyDLUV1C5NyT9YaoJUHQhE44U4KCn+rCWDaN3L2 nPlQO9ySQdEQnS+EhOBPRnPxOSJCCzyVeSZ0CAn/bsLZX7z6Ys2KnVskfWL8iesTw06BOTBZVuEu OiH+FehdqBxaJtQCQclCBkvzhgbbwQn3lG4ZjvekqjgmdfSE9iGMHVqP9ZvBlyAD7WUC6tieMAWK pZlnGcfqwmWBewei1NgEoXyIb9dCSfUDffUuyZnZQHnWJmXBpZ37Yh/FCmqXlG+nXTEzsi5LxKDP fS7bOj2+IB2KTPbvT76dAj2Jpv0cG55C0fU9JZVndf9a/99sCJcdzAgHdkY4d70hh02PSJjvIzyC VG8UXp78sl+GMIddr0DV3T+rCpJx7a5Ltm/xal3xKTUWci1ioHoMMpQhu9aWA4TuWxgGpwPxzAUj AuH6kKUuEdWX6GawuKU+DgpdTmWSPKbP7rfZZ2EmzLisjmAdhblXoyddLXg1U8dZL2gpFVcIk/Gk Stf0ubOLhlZ0wAul2jIbH/u/myOd7/tLUriCXqaWHjzxF9a0/Jb0DMXmBQLZYCL9aTmN054aCZ1a fmjji4HFL4/wijjIWH244nZmLlyiKYjsvNBskf+cbCkmVyjG4Pt3+tg3Rw0Hc6xTthsE1XAdstJs aqIG `protect end_protected

gpl-2.0

8c8260ccc600dcb0c8ff1ba07af389cc

preusser/q27

src/vhdl/PoC/uart/uart_tx.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- =========================================================================== -- Module: -- -- Authors: Thomas B. Preusser -- -- Description: UART (RS232) Transmitter: 1 Start + 8 Data + 1 Stop -- ------------ -- -- License: -- =========================================================================== -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- =========================================================================== library IEEE; use IEEE.std_logic_1164.all; entity uart_tx is port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Bit Clock and TX Line bclk : in std_logic; -- bit clock, one strobe each bit length tx : out std_logic; -- Byte Stream Input di : in std_logic_vector(7 downto 0); put : in std_logic; ful : out std_logic ); end entity; library IEEE; use IEEE.numeric_std.all; architecture rtl of uart_tx is -- Buf Cnt -- Idle "---------1" "0----" -- Start "hgfedcba01" -10 -- Send "1111hgfedc" -10 -> -1 -- Done "1111111111" 0 signal Buf : std_logic_vector(9 downto 0) := (0 => '1', others => '-'); signal Cnt : signed(4 downto 0) := "0----"; begin process(clk) begin if rising_edge(clk) then if rst = '1' then Buf <= (0 => '1', others => '-'); Cnt <= "0----"; else if Cnt(Cnt'left) = '0' then -- Idle if put = '1' then -- Start Transmission Buf <= di & "01"; Cnt <= to_signed(-10, Cnt'length); else Buf <= (0 => '1', others => '-'); Cnt <= "0----"; end if; else -- Transmitting if bclk = '1' then Buf <= '1' & Buf(Buf'left downto 1); Cnt <= Cnt + 1; end if; end if; end if; end if; end process; tx <= Buf(0); ful <= Cnt(Cnt'left); end;

agpl-3.0

d2a233b602d02800fb8d68d34facc42a

wltr/cern-fgclite

critical_fpga/src/rtl/cf/sram.vhd

------------------------------------------------------------------------------- --! @file sram.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-19 --! @brief External SRAM communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.sram_pkg.all; --! @brief Entity declaration of sram --! @details --! This component handles the interface with the external SRAM. entity sram is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Command and status --! @{ --! ADC log index adc_log_idx_o : out std_ulogic_vector(15 downto 0); --! DIM log index dim_log_idx_o : out std_ulogic_vector(15 downto 0); --! ADC log freeze adc_freeze_i : in std_ulogic; --! DIM log freeze dim_freeze_i : in std_ulogic; --! Millisecond strobe indicating start of cycle ms_0_strobe_i : in std_ulogic; --! @} --! @name ADC and DIM data --! @{ --! ADC VS data adc_vs_i : in std_ulogic_vector(23 downto 0); --! ADC VS data enable adc_vs_en_i : in std_ulogic; --! ADC IA data adc_ia_i : in std_ulogic_vector(23 downto 0); --! ADC IA data enable adc_ia_en_i : in std_ulogic; --! ADC IB data adc_ib_i : in std_ulogic_vector(23 downto 0); --! ADC IB data enable adc_ib_en_i : in std_ulogic; --! DIM data dim_i : in std_ulogic_vector(19 downto 0); --! DIM data enable dim_en_i : in std_ulogic; --! @} --! @name Read interface --! @{ --! Memory index idx_i : in std_ulogic_vector(14 downto 0); --! Memory index type idx_type_i : in std_ulogic_vector(2 downto 0); --! ADC Address adc_addr_i : in std_ulogic_vector(4 downto 0); --! ADC Read enable adc_rd_en_i : in std_ulogic; --! ADC Data output adc_data_o : out std_ulogic_vector(23 downto 0); --! ADC Data output enable adc_data_en_o : out std_ulogic; --! ADC Done flag adc_done_i : in std_ulogic; --! DIM Address dim_addr_i : in std_ulogic_vector(4 downto 0); --! DIM Read enable dim_rd_en_i : in std_ulogic; --! DIM Data output dim_data_o : out std_ulogic_vector(15 downto 0); --! DIM Data output enable dim_data_en_o : out std_ulogic; --! DIM Done flag dim_done_i : in std_ulogic; --! @} --! @name External SRAM interface --! @{ --! Inputs sram_i : in sram_in_t; --! Outputs sram_o : out sram_out_t); --! @} end entity sram; --! RTL implementation of sram architecture rtl of sram is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ constant adc_vs_base_addr_c : unsigned(2 downto 0) := "000"; constant adc_ia_base_addr_c : unsigned(2 downto 0) := "001"; constant adc_ib_base_addr_c : unsigned(2 downto 0) := "010"; constant dim_base_addr_c : unsigned(18 downto 0) := "0110000000000000000"; type state_t is (RD_CHECK, RD_ADC_IA, WR_ADC_IA_0, WR_ADC_IA_1, RD_ADC_IB, WR_ADC_IB_0, WR_ADC_IB_1, RD_ADC_VS, WR_ADC_VS_0, WR_ADC_VS_1, RD_DIM, WR_DIM, FETCH_REQ, FETCH_ADC_0, STORE_ADC_0, FETCH_ADC_1, STORE_ADC_1, FETCH_DIM, STORE_DIM); type reg_t is record state : state_t; adc_idx : unsigned(14 downto 0); dim_idx : unsigned(10 downto 0); adc_rd_req : std_ulogic; dim_rd_req : std_ulogic; adc_data : std_ulogic_vector(23 downto 0); adc_data_en : std_ulogic; dim_data : std_ulogic_vector(15 downto 0); dim_data_en : std_ulogic; end record; constant init_c : reg_t := ( state => RD_CHECK, adc_idx => (others => '0'), dim_idx => (others => '0'), adc_rd_req => '0', dim_rd_req => '0', adc_data => (others => '0'), adc_data_en => '0', dim_data => (others => '0'), dim_data_en => '0'); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal next_reg: reg_t; signal tmr_addr : std_ulogic_vector(18 downto 0); signal tmr_rd_en : std_ulogic; signal tmr_wr_en : std_ulogic; signal tmr_data_in : std_ulogic_vector(15 downto 0); signal tmr_data_out : std_ulogic_vector(15 downto 0); signal tmr_data_en : std_ulogic; signal tmr_done : std_ulogic; signal tmr_busy : std_ulogic; signal sram_addr : std_ulogic_vector(19 downto 0); signal sram_rd_en : std_ulogic; signal sram_wr_en : std_ulogic; signal sram_data_in : std_ulogic_vector(15 downto 0); signal sram_data_out : std_ulogic_vector(15 downto 0); signal sram_data_en : std_ulogic; signal sram_busy : std_ulogic; signal sram_done : std_ulogic; signal dim_fifo_rd_en : std_ulogic; signal dim_fifo_data : std_ulogic_vector(19 downto 0); signal dim_fifo_data_en : std_ulogic; signal dim_fifo_empty : std_ulogic; signal dim_fifo_wr_busy : std_ulogic; signal adc_vs_fifo_rd_en : std_ulogic; signal adc_vs_fifo_data : std_ulogic_vector(23 downto 0); signal adc_vs_fifo_data_en : std_ulogic; signal adc_vs_fifo_empty : std_ulogic; signal adc_vs_fifo_wr_busy : std_ulogic; signal adc_ia_fifo_rd_en : std_ulogic; signal adc_ia_fifo_data : std_ulogic_vector(23 downto 0); signal adc_ia_fifo_data_en : std_ulogic; signal adc_ia_fifo_empty : std_ulogic; signal adc_ia_fifo_wr_busy : std_ulogic; signal adc_ib_fifo_rd_en : std_ulogic; signal adc_ib_fifo_data : std_ulogic_vector(23 downto 0); signal adc_ib_fifo_data_en : std_ulogic; signal adc_ib_fifo_empty : std_ulogic; signal adc_ib_fifo_wr_busy : std_ulogic; signal adc_req_base_addr : unsigned(2 downto 0); --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- adc_log_idx_o <= '0' & std_ulogic_vector(reg.adc_idx); dim_log_idx_o <= "00000" & std_ulogic_vector(reg.dim_idx); adc_data_o <= reg.adc_data; adc_data_en_o <= reg.adc_data_en; dim_data_o <= reg.dim_data; dim_data_en_o <= reg.dim_data_en; --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- with idx_type_i select adc_req_base_addr <= adc_vs_base_addr_c when "010", adc_ia_base_addr_c when "011", adc_ib_base_addr_c when "100", (others => '0') when others; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! DIM FIFO dim_fifo_inst : entity work.fifo_tmr generic map ( depth_g => 32, width_g => 20) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_en_i => dim_en_i, data_i => dim_i, done_o => open, full_o => open, wr_busy_o => dim_fifo_wr_busy, rd_en_i => dim_fifo_rd_en, data_o => dim_fifo_data, data_en_o => dim_fifo_data_en, empty_o => dim_fifo_empty, rd_busy_o => open); --! ADC VS FIFO adc_vs_fifo_inst : entity work.fifo_tmr generic map ( depth_g => 20, width_g => 24) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_en_i => adc_vs_en_i, data_i => adc_vs_i, done_o => open, full_o => open, wr_busy_o => adc_vs_fifo_wr_busy, rd_en_i => adc_vs_fifo_rd_en, data_o => adc_vs_fifo_data, data_en_o => adc_vs_fifo_data_en, empty_o => adc_vs_fifo_empty, rd_busy_o => open); --! ADC IA FIFO adc_ia_fifo_inst : entity work.fifo_tmr generic map ( depth_g => 20, width_g => 24) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_en_i => adc_ia_en_i, data_i => adc_ia_i, done_o => open, full_o => open, wr_busy_o => adc_ia_fifo_wr_busy, rd_en_i => adc_ia_fifo_rd_en, data_o => adc_ia_fifo_data, data_en_o => adc_ia_fifo_data_en, empty_o => adc_ia_fifo_empty, rd_busy_o => open); --! ADC IB FIFO adc_ib_fifo_inst : entity work.fifo_tmr generic map ( depth_g => 20, width_g => 24) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_en_i => adc_ib_en_i, data_i => adc_ib_i, done_o => open, full_o => open, wr_busy_o => adc_ib_fifo_wr_busy, rd_en_i => adc_ib_fifo_rd_en, data_o => adc_ib_fifo_data, data_en_o => adc_ib_fifo_data_en, empty_o => adc_ib_fifo_empty, rd_busy_o => open); --! External SRAM data triplicator tmr_inst : entity work.mem_data_triplicator generic map ( depth_g => 2**sram_addr'length, width_g => 16) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, addr_i => tmr_addr, rd_en_i => tmr_rd_en, wr_en_i => tmr_wr_en, data_i => tmr_data_in, data_o => tmr_data_out, data_en_o => tmr_data_en, busy_o => tmr_busy, done_o => tmr_done, voted_o => open, mem_addr_o => sram_addr, mem_rd_en_o => sram_rd_en, mem_wr_en_o => sram_wr_en, mem_data_o => sram_data_in, mem_data_i => sram_data_out, mem_data_en_i => sram_data_en, mem_busy_i => sram_busy, mem_done_i => sram_done); --! External SRAM interface sram_if_inst : entity work.sram_interface generic map ( addr_width_g => 20, data_width_g => 16, read_delay_g => 8, write_delay_g => 4) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, addr_i => sram_addr, rd_en_i => sram_rd_en, wr_en_i => sram_wr_en, data_i => sram_data_in, data_o => sram_data_out, data_en_o => sram_data_en, busy_o => sram_busy, done_o => sram_done, sram_addr_o => sram_o.addr, sram_data_i => sram_i.data, sram_data_o => sram_o.data, sram_cs1_n_o => sram_o.cs1_n, sram_cs2_o => sram_o.cs2, sram_we_n_o => sram_o.we_n, sram_oe_n_o => sram_o.oe_n, sram_le_n_o => sram_o.le_n, sram_ue_n_o => sram_o.ue_n, sram_byte_n_o => sram_o.byte_n); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= init_c; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else reg <= next_reg; end if; end if; end process regs; --------------------------------------------------------------------------- -- Combinatorics --------------------------------------------------------------------------- comb : process (reg, idx_i, tmr_busy, tmr_done, tmr_data_out, tmr_data_en, adc_ia_fifo_empty, adc_ia_fifo_data_en, adc_ia_fifo_data, adc_ib_fifo_empty, adc_ib_fifo_data_en, adc_ib_fifo_data, adc_vs_fifo_empty, adc_vs_fifo_data_en, adc_vs_fifo_data, dim_fifo_empty, dim_fifo_data_en, dim_fifo_data, adc_rd_en_i, dim_rd_en_i, adc_addr_i, dim_addr_i, adc_req_base_addr, adc_done_i, dim_done_i, adc_freeze_i, dim_freeze_i, dim_fifo_wr_busy, adc_vs_fifo_wr_busy, adc_ia_fifo_wr_busy, adc_ib_fifo_wr_busy, ms_0_strobe_i) is begin -- comb -- Defaults next_reg <= reg; next_reg.adc_data_en <= '0'; next_reg.dim_data_en <= '0'; adc_vs_fifo_rd_en <= '0'; adc_ia_fifo_rd_en <= '0'; adc_ib_fifo_rd_en <= '0'; dim_fifo_rd_en <= '0'; tmr_rd_en <= '0'; tmr_wr_en <= '0'; tmr_data_in <= (others => '0'); tmr_addr <= (others => '0'); if adc_rd_en_i = '1' then next_reg.adc_rd_req <= '1'; end if; if dim_rd_en_i = '1' then next_reg.dim_rd_req <= '1'; end if; if ms_0_strobe_i = '1' and dim_freeze_i = '0' then next_reg.dim_idx <= reg.dim_idx + 1; end if; case reg.state is when RD_CHECK => if adc_freeze_i = '0' and adc_ia_fifo_empty = '0' and adc_ib_fifo_empty = '0' and adc_vs_fifo_empty = '0' then next_reg.adc_idx <= reg.adc_idx + 1; next_reg.state <= RD_ADC_IA; else next_reg.state <= RD_DIM; end if; when RD_ADC_IA => if tmr_busy = '0' and adc_ia_fifo_wr_busy = '0' then adc_ia_fifo_rd_en <= '1'; next_reg.state <= WR_ADC_IA_0; end if; when WR_ADC_IA_0 => if adc_ia_fifo_data_en = '1' then tmr_wr_en <= '1'; tmr_data_in <= adc_ia_fifo_data(15 downto 0); tmr_addr <= std_ulogic_vector(adc_ia_base_addr_c & reg.adc_idx & '0'); next_reg.state <= WR_ADC_IA_1; end if; when WR_ADC_IA_1 => if tmr_busy = '0' then tmr_wr_en <= '1'; tmr_data_in <= (31 downto 24 => adc_ia_fifo_data(adc_ia_fifo_data'high)) & adc_ia_fifo_data(23 downto 16); tmr_addr <= std_ulogic_vector(adc_ia_base_addr_c & reg.adc_idx & '1'); next_reg.state <= RD_ADC_IB; end if; when RD_ADC_IB => if tmr_busy = '0' and adc_ib_fifo_wr_busy = '0' then adc_ib_fifo_rd_en <= '1'; next_reg.state <= WR_ADC_IB_0; end if; when WR_ADC_IB_0 => if adc_ib_fifo_data_en = '1' then tmr_wr_en <= '1'; tmr_data_in <= adc_ib_fifo_data(15 downto 0); tmr_addr <= std_ulogic_vector(adc_ib_base_addr_c & reg.adc_idx & '0'); next_reg.state <= WR_ADC_IB_1; end if; when WR_ADC_IB_1 => if tmr_busy = '0' then tmr_wr_en <= '1'; tmr_data_in <= (31 downto 24 => adc_ib_fifo_data(adc_ib_fifo_data'high)) & adc_ib_fifo_data(23 downto 16); tmr_addr <= std_ulogic_vector(adc_ib_base_addr_c & reg.adc_idx & '1'); next_reg.state <= RD_ADC_VS; end if; when RD_ADC_VS => if tmr_busy = '0' and adc_vs_fifo_wr_busy = '0' then adc_vs_fifo_rd_en <= '1'; next_reg.state <= WR_ADC_VS_0; end if; when WR_ADC_VS_0 => if adc_vs_fifo_data_en = '1' then tmr_wr_en <= '1'; tmr_data_in <= adc_vs_fifo_data(15 downto 0); tmr_addr <= std_ulogic_vector(adc_vs_base_addr_c & reg.adc_idx & '0'); next_reg.state <= WR_ADC_VS_1; end if; when WR_ADC_VS_1 => if tmr_busy = '0' then tmr_wr_en <= '1'; tmr_data_in <= (31 downto 24 => adc_vs_fifo_data(adc_vs_fifo_data'high)) & adc_vs_fifo_data(23 downto 16); tmr_addr <= std_ulogic_vector(adc_vs_base_addr_c & reg.adc_idx & '1'); next_reg.state <= RD_DIM; end if; when RD_DIM => if tmr_busy = '0' and dim_fifo_wr_busy = '0' then if dim_fifo_empty = '0' and dim_freeze_i = '0' then dim_fifo_rd_en <= '1'; next_reg.state <= WR_DIM; else next_reg.state <= FETCH_REQ; end if; end if; when WR_DIM => if dim_fifo_data_en = '1' then tmr_wr_en <= '1'; tmr_data_in <= dim_fifo_data(15 downto 0); tmr_addr <= std_ulogic_vector(dim_base_addr_c + (unsigned(dim_fifo_data(19 downto 16)) & reg.dim_idx & unsigned(dim_fifo_data(13 downto 12)))); next_reg.state <= FETCH_REQ; end if; when FETCH_REQ => if reg.adc_rd_req = '1' then next_reg.state <= FETCH_ADC_0; elsif reg.dim_rd_req = '1' then next_reg.state <= FETCH_DIM; else next_reg.state <= RD_CHECK; end if; when FETCH_ADC_0 => if tmr_busy = '0' then tmr_rd_en <= '1'; tmr_addr <= std_ulogic_vector(adc_req_base_addr & (unsigned(idx_i) + unsigned(adc_addr_i)) & '0'); next_reg.state <= STORE_ADC_0; end if; when STORE_ADC_0 => if tmr_data_en = '1' then next_reg.adc_data(15 downto 0) <= tmr_data_out; next_reg.state <= FETCH_ADC_1; end if; when FETCH_ADC_1 => if tmr_busy = '0' then tmr_rd_en <= '1'; tmr_addr <= std_ulogic_vector(adc_req_base_addr & (unsigned(idx_i) + unsigned(adc_addr_i)) & '1'); next_reg.state <= STORE_ADC_1; end if; when STORE_ADC_1 => if tmr_data_en = '1' then next_reg.adc_data(23 downto 16) <= tmr_data_out(7 downto 0); next_reg.adc_data_en <= '1'; end if; if adc_rd_en_i = '1' then next_reg.state <= FETCH_ADC_0; elsif adc_done_i = '1' then next_reg.state <= RD_CHECK; next_reg.adc_rd_req <= '0'; end if; when FETCH_DIM => if tmr_busy = '0' then tmr_rd_en <= '1'; tmr_addr <= std_ulogic_vector((dim_base_addr_c(18 downto 2) + unsigned(idx_i) + unsigned(dim_addr_i(4 downto 2)))) & dim_addr_i(1 downto 0); next_reg.state <= STORE_DIM; end if; when STORE_DIM => if tmr_data_en = '1' then next_reg.dim_data <= tmr_data_out; next_reg.dim_data_en <= '1'; end if; if dim_rd_en_i = '1' then next_reg.state <= FETCH_DIM; elsif dim_done_i = '1' then next_reg.state <= RD_CHECK; next_reg.dim_rd_req <= '0'; end if; end case; end process comb; end architecture rtl;

mit

87c66b48a37a7cf786c4a6f3236bb55e

malkadi/FGPU

RTL/floating_point/uitofp.vhd

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.1 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY uitofp IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END uitofp; ARCHITECTURE uitofp_arch OF uitofp IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF uitofp_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_1_2 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER; C_FIXED_DATA_UNSIGNED : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_1_2; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_1_2 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 1, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 0, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 0, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 0, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 5, C_OPTIMIZATION => 1, C_MULT_USAGE => 0, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 0, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 0, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1, C_FIXED_DATA_UNSIGNED => 1 ) PORT MAP ( aclk => aclk, aclken => '1', aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => '0', s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END uitofp_arch;

gpl-3.0

0544ef946024f027aed5e25cfe6a8d04

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_priority_decoder.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block uS9Fi4wEl+hlOoAxATWz7JOEkR0NrTOAPXB71RDz/0sJ9oBkdyJcZqzmiJBSpJVLGXrHypKErbng NIq2yEIKicsHE2U2q0TwmOX5SeBUf5ATfJiLQmZtyrgyJ/TKwJ5Nrg3HL+15E0oFzqZEKRQD0RV0 gUht+SMMiNU2xM6RPT7pKCsVb5W4nxZuUNAOyuABEDGRH8YW/kscyF5trBuA48XfiXtVpzBwqK6v PeJ+bU10he4Sno6k9Dn4FGHEKjKtWs1EQPCyJM25dDSrh8kM7MRJepMfF7YseaGlTZntu/uKxJDR ZL3LeAxQZMrU6BodVmaZalC+X5WBYD/UwSiWkQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5872) `protect data_block IQQzY8hMnjpN1vpICzvLVd6bph9UPHseU133rbCKFWvWDaMw7E2vs4wYfT/doafWormh/KMi8bb4 4kasjjx5bkYTxgTVctlgXQRl4/TWVzv2jZKZbyjhjH/GMQIJn+9Crq2v/SAVxJKJXPmNCSpKza8i YzkoYVP9Ckcch1QTVkNDpwSv16d0OPvSJum1UeA/NJvX42My+xtlflF3gKlNVkibjUAzAg3l6C+r OR3MECq8nwr+wLE9uRPgVAhyzAX1bJXMJVVEis35F1BJD/jZ6nBwKIV2Jrt43TdGuj4AQoxsbMJL EBfOb9GXwj+hYpuK4Hn6v8u8XEHPqbx0U52DZK/uom9+ycj9RGCGBJB/EhsL+ruHwCwkjrPxjZRn /SNDInl34u0zbVzHANzBNJWAEDveitfzPjU5y0x7RTii0W0J4X8ZHaldZLYUHZWMCgCsNfZnB9l0 dZqdSIpBFWAhM/2vJM3Th68fzBRTx+rCO9xLjZldkVHKxIOPyUDcla8lfuK5HFN214o3Sn65+LwC 9P9F5xJCSsGbacuybcL5eaAu47ezJnnlB+BrAyJEFmBJHlJwJqCRs+mdRQ2ff1IdHoJUyRiMKaYt W9VtzGe+CT3rcCTGmILjGcDRnhdbDf/Wz4NrhfZEbVQSOY051ZqTi70AITIZUOe96d0ROyl6i4Hf uqLVicttjSsJzcDS3PgNj/NRCoXL5jfx7SN+DxOF6BFLA2iVc9Vuu6NNDOXXH5wblPQWdycIYq+B lPF45mK6BXsm+ffR1NY/uyvUqHWzKAS9r1slCt9qT82uvTL9M6gOQWQxSRQJ+hmig7+uNuhBbD5e c48IcPd8VbWVmPqhpZTbbcBx7Fwy7gEAc8FFyf4MA6fz39JrGG2ulfNukg6ZUVLSTI+HIqIdQO2E pnWPgShSpoCfL0eXC6bqawBHoJ4mdUdQB4EoKPyHT7jbOf9D6CBsU+1yytPe9lk69bYZu75F8BkH FfpTZM5scBgHP0oNa3LBwY4IfCRHIPgeOxokiewBoVYUyMVfVesBj5EksaFPkbptIHfHgOUCraFj B3YVlcbIuwH8XqdbMMi6T9AuUwqHoSQOLDQoQRvBsMhGODREVRm6teoDsOCDdfJk1CIOPSWjaanN qOSLakzmtR48dYJFvDRDHo5RkTlxHAaytUx/d7ed533PtDT8UaB2k09jB8HSfVztTMkI310NyQlb UeJDNfQ2c4MIgF+MmBzwXOrJ9s+WsP7JiTArMZjDw7zIvk0dW49JZfyM4lQlpFg+iWduBPkplmQd /ZPtgNE3XW/fBXaaVHiyFMpwbDI2Jz8AxEd1qthRMLUUX1dkIB5OpPETXVIdfu6Jc0wcWZSTWeEV G2Y2VWlLZDlSZ/SNob4+bFK4HU89MdUYHAm0hJl7NPLG/m1U36l7esgG0qDPyA7nkidnvyPifFA3 RbnRqBKpBQ7sDamqD1jW7fNKQ2GoZ77YCVEVoTtQ21FQH/+WXGvPjexv7/B6BRX9B4dTRTyFmAAz iqa+UzWPKXRi9+eVWOmHz3oYlykUPeYFu2ov05mSvAqZxtwgwnMwTILGE4p/Wm+fzlyv11VfPw9E mAAE2/F3DSrJC52ClGOSNUosyT6ydXdrA4+REkhAfNvKuJxJNe+pJhAb8ATFBhElpIROKIcwIwYl Oq+PEO0+uhfGuB2ntjzFcFGg6RzRZY4nKJJzW0xuf7UU19GOTxY5FDOpc9nGjZWsKb4PbUxFjh/3 eprjJwHE9ZQs2indikicztqzXPvaxO9z/82ndRfmDD7j4RmA7GfdgJvm69niX9/Y+mbRrtHyXqQf ewSIDBa4RARDXe+Sx4kYM5ckxC5WyXfs+KD9OdeZvOZCPv4rsd3pjg8ZPKc0HsB9sLjWHHzLUsMG TFbfZT4aYgLtVS/0RxqdrLJs/r1KEF7eWRiCqOMvrVkIkzlOcfv3htAHyrj7UZQ8oiI1yNzQcMTB kq0z1+trMvu81hyl8vgP1VQiSuBdy18QLwrMbwQf9uklI54WX7v/vitNK3tjEdt+pg88e7OnbZ3e CpPYPOgehYE3wGGBKLubXqDfnBPJE+LF6ybb/3qH9Xb9nojUlivsjn84t58UcMLeagq0ZL+qtm+A NYCKmEFOuhxnsjGyhTOsAxeHQfYqY+XI/3T9TOL8Ze4wm87PX8vp4bVDEcY9NnGZUwhcy9DlO1S9 DU7mFh+m5QpQyOgKm2Of8vuT3aCGAwMF1RNcNpQdSFhx4NGHfwU4KyKwfRxV+CJXEYsFRr81zQuu x2d/L9ukPWa5axjXNlZmy4vF+PkEWTxjx5f0PZz3N1aWL8DGKxG++BSFQJIci2ikbrkmPzX/e19H sg0oANoE0KMcz77oajNJKoW1EZM4FnRpVmSjc7aJdXB5q4v9rXeVxDuWhd6mDJsV3kFtEBhNFX+Y 9TDHIMzF0Cp0/WlaBCuwthvEgMkuSLZVMzr1wpAuZnzw4ZOM7jsTF49ErM7NrChKJfpVcGbEH25C b3GKIv2c7C6CFsT4j91qTdkYKowFI2g2w5dJcWQZ5u6V/a9Xjdv72qRZORjcCN9rTOKlg5fsOF+y zOKHuBenuNnDlRipLijq4LT1VgV1z7dL9FZZ4zeiRXYJSkkjyU32uF1p9sbeCUbQHysl0m8ioEYJ IRzpQoqmleZ1nUY/q1gHbKyJOE8k4YgXJqLzB58LJxlFd5B2oWAbBKKR1GCnCua+NoPW5NN+U28u LuBwCTHJP12xcRI19ul6fOnvYy7kcl8zw7a5po030eutOg9HfC0G+1v3QaHHNUAigZObBi9qiNWP i39NeAyEww7TGgLsBmwcK5f1+GKw1alAa62rncF/68ny+SJwOXcsohJIkFSl4lIapdTfCaQK9+jN /GveFHG2W9zf4SG5T/bfJbq71/5EMAZdqu0EyYOaq4QJZLxHwXqVfQpXWAgwj4Y+NStEnZGEKE7s mKplcZehd82PLEirGWuErpfNa56j2GQIs7Auf8iFZ2Z/d1898pgYypNlFN0G7dxZqPrIPXdw2b6r 8mg8pZJH5di8TMSqFSDCN0AZPmNPiib/1lf6jtYsg6scZZ6BWtskGebcGK4Sd2C1vceH1iYLRi+6 6v4vjYVvWHPdD0ivLar0ufJhq4X94EKYpSAggIqQGblSDru2f7PPMvGx7+Csdv8BA1mZQ6s+iAEG V4sOqKSIsAAXlOhj2XkYWHP1CCrqJ0wj14swaQitv9FBZGLB9y6GXrpkIrWuSPoj7Pp/vyTmMxWP OcrBS0Mc9zkxMSzmocCabUz4Rgpr2boZymr+xj6lWiKnXz9Pe1c83+15ssC4BVZaE+wjfpLpDcKr 5LxBhSIRaJH5UlNmkEPuYy16MRQ/CuwXhxwu744RhIDa6tODmbPOaatvxdVqwuuqqi7hMwZ+fUJz 1Md1cWTyyhGKVu0a/R+ftrDfrTnrn3g2Ery1+5Vr3Z4Jwax7obkPT0gUd/ITGn7Tr9uSbY+KVV9B LCduNRWF9RfyItw2wYU79VH9H6nS/KRsBkYl+sdwbkPqxczVNuk6O3E8/ol+kb7Ns1K5JcPnOWKn QWCsGAdz9Tl/dKBALWZ1aVfq/D17MdxuJfGOVHIU1okZLidFdx8PzbZeIR1T5tKH1NPRiUvxIMxL 3GuP3tGU+of0MEqHfi6ut7iNViJruEKxwU/61DbF5VT+CE9ntw4gvdUtGsGME/vs2vATU1sHd/GH BuwZ68siwM63ahIXnX5YJjNKpOFzdyCe3tTUKnBeh1sC5tTqlFoHwlbxTMkHY2baZGQtSwhVL5Ir ZynANe1zJuDSMjLLVHb82vgiLFjezwhgVOSgRyma2lVSHoTraTNPUpeaXUEtjkMWLUAYBttxMFaM 1K+vFtp8bCFrper+pcsB0V9vtrPlXknoCYNstHTWFtSLGcZ7ohNhr45XZwkbuBrwVp27KsMKRDlb W6XwKbL2bRc0rIsI555JQ+SO52NcCQAAn8UswtPGEcj+rYgeiZlUi7e6Crbts2L4uZepMe0X7OjF 1Er67NYNzkvCUencn+EwkMz/K+NtaRTC4DZKQXutDmnEWpxT2a50QthSDMLupz9MF4kkhKvkHbco 9VBpn/mw0eBT7sfZYVn0/Gx+alC38s9A/KQIcVcx9TUqD55xz8P6qOpq3RYmyQfoM5gWCFUG/Rwg cu6wWERCRQqg5cPqQy2VP2TL2xa5/728C5YWcI2vFgPWjC29W2wgO3+VuRQqIDS8T6CcyXSGc5R5 qzjV1IIP7XYIijAJrCVdd7q8fEq2iwnxd98lM3xJxeyt/qgFCjWpwaV/MaI1GXbLLzjnOLYjjfih 2Apl1dosTf4nG9jXGHCovc3ycgI7dkMPICym12pwNB0NxVd7WjFbqrd+BjlSQFerqWNQMIyIMFsH r8vfF2wDoRC8I63YMSJLpCmyJ1pCPy+93XQbWw9YHSQSgJ59OjgEW05k/+NyklLgveyCO2fgGlsL CioepZ4ipVFVljqLegGHxngfGAidE350YdAboFBjZ2au7jCksOVMwN+pW5ZHIEhizxucmLTaWBJb MXK/u85vYNJ2h4DbZh3db+KSnTad19EOJ+Pex2Y+wci3i+TUehzMGyd94rDpFnxm6aLb4akmpZwX qhicpOrpIQRxErbCRc3LzO0VPETuzAkyLqGelDqHP2N9aSwQweP3lRgaZ0xEGb/vHAwLTjLSCTD2 O++26XbeFTNcj+pAw/8uwlhZgFbvn6JfdtjTHfHItKrwb6G8KAagCZRfLQjdTeaJ0VO4dAbg7vi6 4wKHv0CsAO3if7ZzQGlA1RpZzF087vhDe03nGLpF4OkFXjf84R1hEH8PIT46u2I5m+7cZm5i2hQL XRXp2LCNL8I+7xxHZO/u0ZUViNbzGYG6b2n5KXCiYwt3MM7u7ZYaRYYKMEDMuR4izR9oknTA8shQ Gr6Qnvy6X6d0TKcNnWnfD7bsk1PBOHRsXfpGMiMPVzxFyp7IrYfyJEa8rGvALWcMzK6+bFY0fkOo lB9IqQVAYDropW2ZlMs7r7UtgZ/P1VepKqzS7LoP/mhu7mqkmFYW7q5XsAkGy704ayzg1NNrC6cM 8sGz80VeqlkJ/f6a/i2neq4hyc5gidr2fghm1dZ02IRnDpHL1ZN/0AMkxpKB3fWQK/v+H0Q61miL FO9gxYTqON3rLwJ2LUVwYNTcMsiq+XyeyYSCiCD3CTRVEuh770sZJXqpHoh9LSPZQTZUHOBnmktG P8eqTcgfz84++OsqOnkuW6ZxzLcSoPZVNeXS/Cgs48xuxvDuKv338g9Lpb649Pp1WXwpwl1uU1w9 Aml1QefOZoI2rZwly9yPFOkndo7Vab2mG30LNkoZfNZUIistwujtnQVSgHcAWJgNPKrkMfR6h9DS mlDxBQrsdQZ7EpbWFE6bhSGs4fIGwI20gJGi7PXv4Poc9zbcnwx0wVizPWL4sxzi/Q4QjCiVpcya O9UC5BaT2u6/rokVARMsdFqmkcZ0hdnFDIqikdeSBurfbb8pygBs/ZrodZnW6azi+hfrF5pHSuAl kCt11SZc4nCfQj/M+89lNZvKwY8NjH6F58W2X6wolg4Dh+g4s/EY3tmSMJkDl6RrBU3c36c+g1M+ 5VFjhQ1ku2ihgs8zTbhFnV9Ein5DlQFUP5lEkZMiySVifRPa7uMUyOO7bFLKif4/oKhiyR49q2Ht KLIHHiyGYf2tzaqYnXJLpWkyRjibDDOs4G21T3EfoZ75/pWfaRNhZI0bfxz6qLGwk4j0yX9++yVl jRoaBesfiTYm9AMbM7XJKwM+8QDxvb9wvlOwoXNdTHUoskWEVrBE7oKu+0GcztF/lM/zPNce0Ei0 hNm2FQo0q7Bk+dJeTGyxk9NOu8eWzv8YDNKc1ZCA1Nbw8i3rgmR8D2AY+O+AuT6QM4CyKdO/NfrV EPY1JdJVdf1wjMSlTWyZyAZvS8prbKuykA4P/q9PVkHaaIyz04LgEtjNPK1x/IhDzEGvJbNNOaqB DIaj/l0SzdgcE1iKI2Iti6ZiTwpyaXOheNcYLvgbDnPp4pKNp725XWQ1X2qazgBtzoQvLEC0briQ W8cNzur+UtyASvoe9duwk5mKWBCpMVcPHuYWWAtIcUlkJf8ZknY2dDzM40t5jciyjaC9abTcbUJm uENHmRFN1r1RfvyQUegKs1UM4Z3qXxXJOoEg5l+XA/+P10QQ5pEJlIBvjMBmeQELweDglScbIKNH LKpL7YcNyqhoEkYEhTeQHI3fd+csDyDRYnZjQFNjU2qwnn8HCTqwvOohJsluOx3LgPl7DNzobaWU UG2CrfS1t7fdTkcSHoumwLL/utu8kF9dlojqTJHOlew8jm/u88YqmTpUDxOoq1BE/Y5NaOYJXEnF ac5IRJE35y15vOLVhJfLquGTvBKDk6kcuDPAXBw+OTzPNjnv1KwgXFzz3RmBtNwDQO9v/q/b+4bE giUT3qxinAh3rpTwSnDsAIxHNcZLJgdW8qjIgiw+6E+sSkxbBtTVnhixX+XXJoiHIo/fD8aWQTb/ +xMr8xvUTTWQN2WiU4S5eG+MW5cb/6JP6jenBiRj05t+we5IvgByxornREf7sXZv1esXk0yQ0r2a Aa+DEa3eRkH+eYWiPxWfEHx9Fo4cANm7hmTY9HGMTBi3xJxlabPnUpJ1On+MCLNE+U/v31pZ9sS1 6+AM7xggPYtvSMaMA9XduoL/AjtmSv52upB6BEY0dRK2VYXfg8rSCovR0RKX/LS16m6f7g9KcHbF agrcL8reFKRxkBx3TTMBZ9D5UlUNzsndoULKBln1OKNAJXZl8JrRveAjyYrH/a7AcKp/0u0QaIV6 mQ/8+CaWWXTOtv1+v1EYS3jlL5tLmV+N4Wlp+m847Ukpq5qrmqROv2tba7AF4FlsUMzP+VbgNasF HcrvZxQoP7oSmZhfesK74wxZotBiRZ3HqMfGj62jaOec7zHRUHED7ULVzu1X/1Lr3ugzhSegP6Hu 8ZH4cpN+afZNbZKXL5wYqAE+VBcvt2EsgGh7mv7NGW5qVLBSZ6KdH82Jy3kZN52ph2VWkiISWf7u Ygi2reZiKBk2h4REpRLwUH6Ge+HAloSQCn5tpKwBe9C+bw7Rpe/Hts8xQsQ6J4sHXJaf7SUVaLzS PvquKgJ2YY9gjAlGLq+q62aZFwMl37w/QoRrHklfeU8idvjhMleN+ITKcSRT5fu5Qto4JR+HlVv6 RSiR7gLPSPcIiHX2MORYY0TTqKlo1KBjbJzl/bcP8JDvMbJY1sANi3vtF4aPAT2KZQ6BLaJt/5Tn OdES/YAL+1eUaZZmneZxL0qv5aWDMilYMSTPrbzQOMKOLP11d24rmCw+uoWj63RZQ42tDYhXOVPW /PdsRkIAdrWwyo2/LFAmNWwvdEuLfiKXpUXRE7WLnL17MRB1CwZO1cOoE6bWIaoYdLikyfomSM3p UPJXN1vD9sPPvMuIrNr6iInrCopAnH60n50Hx2A4vKJxQtESiyuN0LlYEnJoOGUcmzrQ10tBNaYW +pFs4adaXN83X4FdhEduhGICvogLkJgAFDzZShUN93AEb9jW8yT3gpVCR0HYk5pFL1IxwN/TgWoj dB1dHkYI1QyQXDqaLv2UMBtPKpf2WyJUUIZBFGCcidtFDJ1Fxnm90qf9R+mYSl1pJUiy2ENDg957 qk4zlHAmzLgbuQoJLWXyZGGm+U5Q1iUPYa/LpYL58RhJjpDhEqG0+iaL+rsYW0degApjakzdM4vw YmDZwdbUGvAQQ4flSb+2cCO3/uBYWmSIvlX5Rj5poMhM49dl80Iq0Iv+m+OHeKgcnt8RCwVetUfr 0Q== `protect end_protected

gpl-2.0

3846a774fb524106e9a9f484ca7fbef0

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_prod_bytes_retriever.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_prod_bytes_retriever | -- | --------------------------------------------------------------------------------------------------- -- File wf_prod_bytes_retriever.vhd | -- | -- Description After an ID_DAT frame requesting for a variable to be produced, the unit provides | -- to the wf_tx_serializer unit one by one, all the bytes of data needed for the | -- RP_DAT frame (apart from the FSS, FCS and FES bytes). The coordination of the | -- retrieval is done through the wf_engine_control and the signal byte_index_i. | -- | -- General structure of a produced RP_DAT frame: | -- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ | -- |____FSS____|_CTRL_||__PDU__|_LGTH_|_...User-Data..._|_nstat_|__MPS__||____FCS____|__FES__| | -- | -- Data provided by the this unit: | -- ______ _______ ______ _________________ _______ _______ | -- |_CTRL_||__PDU__|_LGTH_|_...User-Data..._|_nstat_|__MPS__|| | -- | -- If the variable to be produced is the | -- o presence : The unit retreives the bytes from the WF_PACKAGE. | -- No MPS & no nanoFIP status are associated with this variable. | -- ______ _______ ______ ______ ______ ______ ______ ______ | -- |_CTRL_||__PDU__|__05__|__80__|__03__|__00__|__F0__|__00__|| | -- | -- | -- o identification: The unit retreives the Constructor & Model bytes from the | -- wf_model_constr_decoder, & all the rest from the WF_PACKAGE. | -- No MPS & no nanoFIP status are associated with this variable. | -- ______ _______ ______ ______ ______ ______ ______ _______ ______ ______ ______ | -- |_CTRL_||__PDU__|__08__|__01__|__00__|__00__|_cons_|__mod__|__00__|__00__|__00__|| | -- | -- | -- o var_3 : If the operation is in stand-alone mode, the unit retreives | -- the user-data bytes from the "nanoFIP User Interface, NON- | -- WISHBONE" bus DAT_I. | -- If it is in memory mode,it retreives them from the Produced RAM -- The MPS and the nanoFIP status bytes are retrieved from the | -- wf_status_bytes_gen. | -- The LGTH byte is retrieved from the wf_prod_data_lgth_calc. | -- The rest of the bytes (CTRL & PDU) come from the WF_PACKAGE. | -- ______ _______ ______ ________________________________________ _______ _______ | -- |_CTRL_||__PDU__|_LGTH_|_____________..User-Data..______________|_nstat_|__MPS__|| | -- | -- | -- o var_5 : Regardless of the operational mode or the P3_LGTH, the unit | -- sends 1 user-data byte coming from the wf_jtag_controller. | -- The nanoFIP status is always sent regardless of the NOSTAT | -- input. The MPS, LGTH, CTRL, PDU_TYPE bytes are retrived in | -- the same way as for a var_3. | -- | -- ______ _______ ______ ________ _______ _______ | -- |_CTRL_||__PDU__|_LGTH_|_jc_tdo_|_nstat_|__MPS__|| | -- | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 04/01/2011 | -- Version v0.05 | -- Depends on wf_reset_unit | -- wf_wb_controller | -- wf_engine_control | -- wf_prod_permit | -- wf_status_bytes_gen | -- wf_model_constr_dec | -- wf_jtag_controller | ---------------- | -- Last changes | -- 06/2010 v0.02 EG subs_i is not sent in the RP_DAT frames | -- signal s_wb_we includes the wb_stb_r_edge_p_i | -- cleaner structure | -- 06/2010 v0.03 EG signal s_mem_byte was not in sensitivity list in v0.01! by adding it | -- changes were essential in the timing of the tx (wf_osc, wf_tx, | -- wf_engine_control and the configuration of the memory needed changes) | -- 11/2010 v0.04 EG for simplification, new unit Slone_Data_Sampler created | -- 4/1/2011 v0.05 EG unit renamed from wf_prod_bytes_to_tx to wf_prod_bytes_retriever; | -- input byte_being_sent_p_i added, so that the reseting of status bytes | -- does not pass from the engine; clening-up+commenting | -- 2/2011 v0.051 EG wf_prod_bytes_from_dati unit removed. | -- 6/2011 v0.051 EG added jc var treatment. | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_prod_bytes_retriever --================================================================================================= entity wf_prod_bytes_retriever is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock nostat_i : in std_logic; -- if negated, nFIP status is sent slone_i : in std_logic; -- stand-alone mode -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- nanoFIP User Interface, WISHBONE Slave wb_clk_i : in std_logic; -- WISHBONE clock wb_adr_i : in std_logic_vector (8 downto 0); -- WISHBONE address to memory wb_data_i : in std_logic_vector (7 downto 0); -- WISHBONE data bus -- Signal from the wf_wb_controller wb_ack_prod_p_i : in std_logic; -- WISHBONE acknowledge -- latching moment of wb_data_i -- nanoFIP User Interface, NON WISHBONE slone_data_i : in std_logic_vector (15 downto 0); -- input data bus for slone mode -- Signals from the wf_engine_control unit byte_index_i : in std_logic_vector (7 downto 0); --index of the byte to be retrieved byte_being_sent_p_i : in std_logic; -- pulse on the beginning of the -- delivery of a new byte data_lgth_i : in std_logic_vector (7 downto 0); -- # bytes of the Conrol&Data fields -- of the RP_DAT frame; includes: -- 1 byte RP_DAT.CTRL, -- 1 byte RP_DAT.Data.PDU_type, -- 1 byte RP_DAT.Data.LGTH -- several bytes of RP_DAT.Data, and -- if applicable 1 byte RP_DAT.Data.MPS_status & -- 1 byte RP_DAT.Data.nanoFIP_status var_i : in t_var; --variable type that is being treated -- Signals from the wf_prod_permit var3_rdy_i : in std_logic; -- nanoFIP output VAR3_RDY -- Signals from the wf_status_bytes_gen mps_status_byte_i : in std_logic_vector (7 downto 0); -- MPS status byte nFIP_status_byte_i : in std_logic_vector (7 downto 0); -- nanoFIP status byte -- Signals from the wf_model_constr_dec unit constr_id_dec_i : in std_logic_vector (7 downto 0); -- decoded constructor id settings model_id_dec_i : in std_logic_vector (7 downto 0); -- decoded model id settings -- Signals from the wf_jtag_controller unit jc_tdo_byte_i : in std_logic_vector (7 downto 0); -- sampled JC_TDO -- OUTPUTS -- Signal to the wf_status_bytes_gen rst_status_bytes_p_o : out std_logic; -- reset for the nanoFIP&MPS status -- status bytes.It is activated after -- the delivery of the last one (MPS) -- Signal to the wf_tx_serializer byte_o : out std_logic_vector (7 downto 0));-- output byte to be serialized end entity wf_prod_bytes_retriever; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_prod_bytes_retriever is -- addressing the memory signal s_base_addr, s_mem_addr_offset : unsigned (8 downto 0); signal s_mem_addr_A : std_logic_vector (8 downto 0); -- index of byte to be sent signal s_byte_index_d1 : std_logic_vector (7 downto 0); signal s_byte_index_d_aux : integer range 0 to 15; -- data bytes signal s_mem_byte, s_slone_byte : std_logic_vector (7 downto 0); signal s_slone_bytes : std_logic_vector (15 downto 0); -- Length byte signal s_lgth_byte : std_logic_vector (7 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Memory mode Produced RAM -- -- Storage (by the user) & retrieval (by the unit) of produced bytes -- --------------------------------------------------------------------------------------------------- -- Instantiation of a 512 x 8 Produced Dual Port RAM. -- Port A is used by the nanoFIP for the readings from the Produced RAM; -- Port B is connected to the WISHBONE interface for the writings from the user. -- Note: only 124 bytes are used. Produced_Bytes_From_RAM: wf_dualram_512x8_clka_rd_clkb_wr port map( clk_porta_i => uclk_i, -- 40 MHz clock addr_porta_i => s_mem_addr_A, -- address of byte to be read from memory clk_portb_i => wb_clk_i, -- WISHBONE clock addr_portb_i => wb_adr_i, -- address of byte to be written data_portb_i => wb_data_i, -- byte to be written write_en_portb_i => wb_ack_prod_p_i, -- WISHBONE write enable ----------------------------------------- data_porta_o => s_mem_byte); -- output byte read ----------------------------------------- --------------------------------------------------------------------------------------------------- -- Slone mode DAT_I bus Sampling -- -- retrieval of the two bytes to be produced -- --------------------------------------------------------------------------------------------------- -- Sampling of the input data bus DAT_I(15:0) for the operation in stand-alone mode. -- The sampling takes place on the 1st clock cycle after the VAR3_RDY has been de-asserted. Sample_DAT_I_bus: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_slone_bytes <= (others=>'0'); else if var3_rdy_i = '1' then -- data latching s_slone_bytes <= slone_data_i; end if; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- s_slone_byte <= s_slone_bytes(7 downto 0) when byte_index_i = c_1st_DATA_BYTE_INDEX else s_slone_bytes(15 downto 8); --------------------------------------------------------------------------------------------------- -- Bytes Generation -- --------------------------------------------------------------------------------------------------- -- Combinatorial process Bytes_Generation: Generation of bytes for the CTRL and Data fields of an -- RP_DAT frame: If the variable requested in the ID_DAT is of "produced" type (identification/ -- presence/ var3/ var5) the process prepares accordingly, one by one, bytes of data to be sent. -- The pointer "s_byte_index_d1" (or "s_byte_index_d_aux") indicates which byte of the frame is to be sent. -- Some of the bytes are defined in the WF_PACKAGE, -- the rest come either from the memory (if slone = 0) or from the the input bus DAT_I (if slone = 1), -- or from the wf_status_bytes_gen or the wf_model_constr_decoder units. -- The output byte "byte_o" is sent to the wf_tx_serializer unit for manchester encoding and serialization. Bytes_Generation: process (var_i, s_byte_index_d1, data_lgth_i, constr_id_dec_i, model_id_dec_i, nFIP_status_byte_i, mps_status_byte_i, s_slone_byte, s_byte_index_d_aux, s_mem_byte, nostat_i, byte_being_sent_p_i, s_lgth_byte, slone_i, jc_tdo_byte_i) begin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- generation of bytes according to the type of produced var: case var_i is -- case: presence variable -- all the bytes for the RP_DAT.CTRL and RP_DAT.Data fields are predefined -- in the c_VARS_ARRAY matrix. when var_presence => byte_o <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).byte_array(s_byte_index_d_aux); s_base_addr <= (others => '0'); rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- case: identification variable -- The Constructor and Model bytes of the identification variable arrive from the -- wf_model_constr_decoder, wereas all the rest are predefined in the c_VARS_ARRAY matrix. when var_identif => if s_byte_index_d1 = c_CONSTR_BYTE_INDEX then byte_o <= constr_id_dec_i; elsif s_byte_index_d1 = c_MODEL_BYTE_INDEX then byte_o <= model_id_dec_i; else byte_o <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).byte_array(s_byte_index_d_aux); end if; s_base_addr <= (others => '0'); rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- case: variable 3 -- For a var_3 there is a separation according to the operational mode (stand-alone or memory) -- In general, few of the bytes are predefined in the c_VARS_ARRAY matrix, whereas the rest come -- either from the memory/ DAT_I bus or from wf_status_bytes_generator unit. when var_3 => --------------------------------------------------------------------------------------------- -- In memory mode: if slone_i = '0' then -- retrieval of base address info for the memory from the WF_PACKAGE s_base_addr <= c_VARS_ARRAY(c_VAR_3_INDEX).base_addr; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The first (CTRL) and second (PDU_TYPE) bytes to be sent -- are predefined in the c_VARS_ARRAY matrix of the WF_PACKAGE if unsigned(s_byte_index_d1) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_d_aux); rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The &c_LGTH_BYTE_INDEX byte is the Length elsif s_byte_index_d1 = c_LGTH_BYTE_INDEX then byte_o <= s_lgth_byte; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- If the nostat_i is negated, the one but last byte is the nanoFIP status byte elsif (unsigned(s_byte_index_d1) = (unsigned(data_lgth_i)-1 )) and nostat_i = '0' then byte_o <= nFIP_status_byte_i; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The last byte is the MPS status elsif s_byte_index_d1 = (data_lgth_i) then byte_o <= mps_status_byte_i; rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes; -- the reset arrives after the delivery -- of the MPS byte to the wf_tx_serializer -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The rest of the bytes come from the memory else byte_o <= s_mem_byte; rst_status_bytes_p_o <= '0'; end if; --------------------------------------------------------------------------------------------- -- In stand-alone mode: else s_base_addr <= (others => '0'); -- no memory access needed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The first (CTRL) and second (PDU_TYPE) bytes to be sent -- are predefined in the c_VARS_ARRAY matrix of the WF_PACKAGE if unsigned(s_byte_index_d1) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_d_aux); rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The &c_LGTH_BYTE_INDEX byte is the Length elsif s_byte_index_d1 = c_LGTH_BYTE_INDEX then byte_o <= s_lgth_byte; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- If the nostat_i is negated, the one but last byte is the nanoFIP status byte elsif unsigned(s_byte_index_d1) = (unsigned(data_lgth_i)-1 ) and nostat_i = '0' then byte_o <= nFIP_status_byte_i; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The last byte is the MPS status elsif s_byte_index_d1 = data_lgth_i then byte_o <= mps_status_byte_i; rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes. -- The reset arrives after having sent the -- MPS byte to the wf_tx_serializer. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The rest of the bytes come from the input bus DAT_I(15:0) else byte_o <= s_slone_byte; rst_status_bytes_p_o <= '0'; end if; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- case: jtag produced variable var_5 -- For a var_5 the 1 user-data byte comes from the wf_jtag_controller unit. -- The nanoFIP status byte comes from the wf_status_bytes_gen and it is always sent, regardless -- of the NOSTAT input. The MPS byte is also coming from the wf_status_bytes_gen. -- The rest of the bytes come from the WF_PACKAGE. when var_5 => s_base_addr <= (others => '0'); -- no memory access needed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The &c_LGTH_BYTE_INDEX byte is the Length if s_byte_index_d1 = c_LGTH_BYTE_INDEX then byte_o <= s_lgth_byte; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The first and only data byte comes from the JATG_controller elsif s_byte_index_d1 = c_1st_DATA_BYTE_INDEX then byte_o <= jc_tdo_byte_i; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The one but last byte is the nanoFIP status byte elsif unsigned(s_byte_index_d1) = (unsigned(data_lgth_i)-1 ) then byte_o <= nFIP_status_byte_i; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The last byte is the MPS status elsif s_byte_index_d1 = data_lgth_i then byte_o <= mps_status_byte_i; rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes. -- The reset arrives after having sent the -- MPS byte to the wf_tx_serializer. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The rest of the bytes (the very first one, CTRL, and the second one, PDU_TYPE) are -- predefined in the c_VARS_ARRAY matrix of the WF_PACKAGE else byte_o <= c_VARS_ARRAY(c_VAR_5_INDEX).byte_array(s_byte_index_d_aux); rst_status_bytes_p_o <= '0'; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when others => rst_status_bytes_p_o <= '0'; byte_o <= (others => '0'); s_base_addr <= (others => '0'); end case; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Synchronous process Delay_byte_index_i: in the combinatorial process Bytes_Generation, -- according to the value of the signal s_byte_index_d1, a byte is retrieved either from the memory, -- or from the WF_PACKAGE or from the wf_status_bytes_gen or wf_model_constr_decoder units. -- Since the memory needs one clock cycle to output its data (as opposed to the other units that -- have them ready) the signal s_byte_index_d1 has to be a delayed version of the byte_index_i -- (byte_index_i is the signal used as address for the mem; s_byte_index_d1 is the delayed one -- used for the other units). Delay_byte_index_i: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_byte_index_d1 <= (others => '0'); else s_byte_index_d1 <= byte_index_i; -- index of byte to be sent end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Auxiliary signals -- --------------------------------------------------------------------------------------------------- s_mem_addr_A <= std_logic_vector (s_base_addr + s_mem_addr_offset - 1); -- address of the byte to be read from memory: base_address(from WF_PACKAGE) + byte_index_i - 1 -- (the -1 is because the byte_index_i counts also the CTRL byte, that is not part of the -- memory; for example when byte_index_i is 3 which means that the CTRL, PDU_TYPE and LGTH -- bytes have preceded and a byte from the memory is now requested, the byte from the memory cell -- 2 (00000010) has to be retrieved). s_mem_addr_offset <= (resize((unsigned(byte_index_i)), s_mem_addr_offset'length)); s_byte_index_d_aux <= (to_integer(unsigned(s_byte_index_d1(3 downto 0)))); -- index of byte to be sent(range restricted) -- used to retreive bytes from the matrix -- c_VARS_ARRAY.byte_array, with a predefined -- width of 15 bytes s_lgth_byte <= std_logic_vector (resize((unsigned(data_lgth_i)-2),byte_o'length)); -- represents the RP_DAT.Data.LGTH byte -- it includes the # bytes of user-data -- (P3_LGTH) plus 1 byte of MPS_status -- plus 1 byte of nanoFIP_status, if -- applicable. It does not include the -- CTRL byte and itself. end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

b0c8e6135dc9132f43f75d89e0e51f64

Kinxil/VHDL_Projects

Mandelbrot/increment.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.CONSTANTS.all; use work.CONFIG_MANDELBROT.all; use WORK.FUNCTIONS.ALL; use IEEE.NUMERIC_STD.ALL; entity increment is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; start : in STD_LOGIC; x_start : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); y_start : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); step : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); y : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x2 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x3 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x4 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x5 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x6 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x7 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x8 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); stop : out std_logic); end increment; architecture Behavioral of increment is signal xs, ys : signed(XY_RANGE-1 downto 0); signal xcount : integer range 0 to XRES-1:=0; signal ycount : integer range 0 to YRES-1:=0; begin process(clock, reset,start,x_start,y_start,step) begin if reset='1' then xcount<=0; ycount<=0; xs<= signed(x_start); ys<= signed(y_start); stop<='0'; elsif rising_edge(clock) then if(start='1') then if xcount >= XRES-8 then if ycount >= YRES-1 then xcount <= 0; ycount <= 0; xs<=signed(x_start); ys<=signed(y_start); stop<='1'; else xcount <= 0; ycount <= ycount+1; ys<=ys+signed(step); xs<=signed(x_start); stop<='0'; end if; else stop<='0'; xs<=xs+(signed(step) sll 3); xcount<=xcount+8; end if; end if; end if; end process; x<=std_logic_vector(xs); y<=std_logic_vector(ys); x2 <= std_logic_vector(xs + signed(step)); x3 <= std_logic_vector(xs + mult(signed(step),X"20000000",FIXED)); x4 <= std_logic_vector(xs + mult(signed(step),X"30000000",FIXED)); x5 <= std_logic_vector(xs + mult(signed(step),X"40000000",FIXED)); x6 <= std_logic_vector(xs + mult(signed(step),X"50000000",FIXED)); x7 <= std_logic_vector(xs + mult(signed(step),X"60000000",FIXED)); x8 <= std_logic_vector(xs + mult(signed(step),X"70000000",FIXED)); end Behavioral;

gpl-3.0

68b614bce376683209dcf4cf755249c7

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_cons_bytes_processor.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_cons_bytes_processor | -- | --------------------------------------------------------------------------------------------------- -- File wf_cons_bytes_processor.vhd | -- | -- Description The unit is consuming the RP_DAT data bytes that are arriving from the | -- wf_fd_receiver, according to the following: | -- | -- o If the variable identifier of the preceded ID_DAT was: | -- | -- var_1 or var_2 | -- - If the operation is in memory mode : the unit is registering the | -- application-data bytes along with the PDU_TYPE, LGTH and MPS bytes in the | -- Consumed or Broadcast Consumed memories | -- - If the operation is in stand-alone mode: the unit is transferring the 2 appli-| -- cation-data bytes to the "nanoFIP User Interface, NON_WISHBONE" data bus DAT_O| -- | -- o var_rst | -- the two application-data bytes are identified and sent to the wf_reset_unit. | -- | -- o var_5 | -- regardless of the operational mode (memory or slone) the unit is registering | -- the application-data bytes along with the PDU_TYPE, LGTH and MPS bytes in the | -- JC_consumed memory. | -- | -- Note: The validity of the consumed bytes (stored in the memories or transfered | -- to DATO or transfered to the wf_reset_unit) is indicated by the "nanoFIP User | -- Interface, NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY or the nanoFIP internal | -- signals rst_nFIP_and_FD_p/ assert_RSTON_p/ start_jc_i, which are treated in | -- the wf_cons_outcome unit and are assessed after the end of the reception of a | -- complete frame. | -- | -- Reminder: | -- | -- Consumed RP_DAT frame structure : | -- ___________ ______ _______ ________ __________________ _______ ___________ _______ | -- |____FSS____|_CTRL_||__PDU__|__LGTH__|__..ApplicData..__|__MPS__||____FCS____|__FES__| | -- | -- |--------&LGTH bytes-------| | -- |--------write to Consumed memories---------| | -- |-----to DAT_O-----| | -- |---to Reset Unit--| | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 15/12/2010 | -- Version v0.03 | -- Depends on wf_reset_unit | -- wf_fd_receiver | -- wf_engine_control | ---------------- | -- Last changes | -- 11/09/2009 v0.01 EB First version | -- 09/2010 v0.02 EG Treatment of reset variable added; Bytes_Transfer_To_DATO unit | -- creation for simplification; Signals renamed; | -- CTRL, PDU_TYPE, LGTH bytes registered; | -- Code cleaned-up & commented. | -- 15/12/2010 v0.03 EG Unit renamed from wf_cons_bytes_from_rx to wf_cons_bytes_processor | -- byte_ready_p comes from the rx_deserializer (no need to pass from | -- the engine) Code cleaned-up & commented (more!) | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------- | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_cons_bytes_processor --================================================================================================= entity wf_cons_bytes_processor is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock slone_i : in std_logic; -- stand-alone mode (active high) -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- nanoFIP User Interface, WISHBONE Slave wb_clk_i : in std_logic; -- WISHBONE clock wb_adr_i : in std_logic_vector (8 downto 0); -- WISHBONE address to memory -- Signals from the wf_fd_receiver unit byte_i : in std_logic_vector (7 downto 0); -- input byte byte_ready_p_i : in std_logic; -- indication of a new input byte -- Signals from the wf_engine_control unit byte_index_i : in std_logic_vector (7 downto 0); -- index of a byte inside the frame; -- starting from 0, it counts all the -- bytes after the FSS&before the FES var_i : in t_var; -- variable type that is being treated -- Signals from the wf_jtag_controller unit jc_mem_adr_rd_i : in std_logic_vector (8 downto 0); -- address of byte to be read and -- transferred to the wf_jtag _controller -- OUTPUTS -- nanoFIP User Interface, WISHBONE Slave output -- MODIFIED was (15 downto 0) data_o : out std_logic_vector (7 downto 0); -- data out bus -- Signals to the wf_jtag_controller unit jc_mem_data_o : out std_logic_vector (7 downto 0); -- byte to be transferred to the wf_jtag _controller -- Signals to the wf_cons_outcome unit cons_ctrl_byte_o : out std_logic_vector (7 downto 0); -- received RP_DAT CTRL byte cons_lgth_byte_o : out std_logic_vector (7 downto 0); -- received RP_DAT LGTH byte cons_pdu_byte_o : out std_logic_vector (7 downto 0); -- received RP_DAT PDY_TYPE byte cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0); -- received var_rst RP_DAT, 1st data byte cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0)); -- received var_rst RP_DAT, 2nd data byte end entity wf_cons_bytes_processor; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_cons_bytes_processor is -- addressing the memory signal s_base_adr : unsigned (8 downto 0); signal s_adr : std_logic_vector (8 downto 0); -- bus/ memories write enable signal s_slone_wr_en_p : std_logic_vector (1 downto 0); signal s_mem_wr_en_p : std_logic; signal s_jc_mem_wr_en_p : std_logic; -- data bytes signal s_slone_data_out : std_logic_vector (15 downto 0); signal s_mem_data_out : std_logic_vector (7 downto 0); -- Length byte signal s_cons_lgth_byte : std_logic_vector (7 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Memory mode Consumed & Consumed Broadcast RAM -- -- Storage (by the unit) & retrieval (by the user) of consumed bytes -- --------------------------------------------------------------------------------------------------- -- Instantiation of a 512 x 8 Dual Port RAM, for both the consumed and consumed broadcast vars -- Port A is connected to the WISHBONE interface for the readings from the user -- Port B is used by the nanoFIP for the writings into the memory Consumption_RAM : wf_dualram_512x8_clka_rd_clkb_wr port map( clk_porta_i => wb_clk_i, -- WISHBONE clock addr_porta_i => wb_adr_i, -- address of byte to be read clk_portb_i => uclk_i, -- 40 MHz clock addr_portb_i => s_adr, -- address of byte to be written data_portb_i => byte_i, -- byte to be written write_en_portb_i => s_mem_wr_en_p, -- write enable -------------------------------------------- data_porta_o => s_mem_data_out); -- output byte read -------------------------------------------- --------------------------------------------------------------------------------------------------- -- JTAG Consumed RAM -- -- Storage (by this unit) & retrieval (by the JTAG_controller unit) of consumed bytes -- --------------------------------------------------------------------------------------------------- -- Instantiation of a 512 x 8 Dual Port RAM for the storage of var_4 variables. -- nanoFIP's user clock uclk is connected to both ports of the memory; the writing of the -- consumed data and the reading of them (by the wf_jtag_controller) take place internally. -- Note: only 127 bytes are used. Consumption_JTAG_RAM : wf_dualram_512x8_clka_rd_clkb_wr port map( clk_porta_i => uclk_i, -- user clock addr_porta_i => jc_mem_adr_rd_i, -- address of byte to be read clk_portb_i => uclk_i, -- 40 MHz clock addr_portb_i => s_adr, -- address of byte to be written data_portb_i => byte_i, -- byte to be written write_en_portb_i => s_jc_mem_wr_en_p, -- write enable -------------------------------------------- data_porta_o => jc_mem_data_o); -- output byte read -------------------------------------------- --------------------------------------------------------------------------------------------------- -- Slone mode Storage of consumed bytes to DATO -- --------------------------------------------------------------------------------------------------- -- Synchronous process Data_Transfer_To_Dat_o: In stand-alone mode, according to the signal -- s_slone_wr_en_p, the first or second byte of the "User Interface, NON WISHBONE" bus DAT_O -- takes the byte byte_i. Data_Transfer_To_Dat_o: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then -- bus initialization s_slone_data_out <= (others => '0'); else if s_slone_wr_en_p(0) = '1' then -- the 1st byte is transfered in the lsb of the bus s_slone_data_out(7 downto 0) <= byte_i; -- it stays there until a new cons. var arrives -- (or until a reset!) end if; if s_slone_wr_en_p(1) = '1' then -- the 2nd byte is transfered in the msb of the bus s_slone_data_out(15 downto 8) <= byte_i; -- it stays there until a new cons. var arrives -- (or until a reset!) end if; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- In stand-alone mode the 16 bits DAT_O fills up with the s_slone_data_out. -- In memory mode,the lsb of DAT_O contains the output of the reading of the consumed memory -- MODIFIED -- data_o <= s_slone_data_out when slone_i = '1' else "00000000" & s_mem_data_out; data_o <= s_mem_data_out; --------------------------------------------------------------------------------------------------- -- Bytes Processing -- --------------------------------------------------------------------------------------------------- -- Combinatorial process Bytes_Processing: Data bytes are consumed according to the -- variable type (var_1, var_2, var_rst, var_4) they belong to. -- In memory and in stand-alone mode, bytes are consumed even if any of the CTRL, PDU_TYPE, -- LGTH, CRC or FES bytes of the consumed RP_DAT frame are incorrect. -- It is the VAR_RDY signal that signals the user for the validity of the consumed data. -- The treatment of a var_1 or a var_2 in memory mode is identical to the treatment of a var_5; -- it is only the addresses of the memories that differ. The incoming bytes (byte_i) after the CTRL -- byte and before the CRC bytes, are written in the memory one by one as they arrive, on the -- moments indicated by the byte_ready_p_i pulses. -- To distinguish the CTRL and the CRC bytes from the rest, the signals byte_index_i and LGTH -- (s_cons_lgth_byte) are used: -- o the CTRL byte arrives when byte_index_i = 0 -- o the CRC bytes arrive &LGTH bytes after the LGTH byte. -- Note: the byte_index_i signal coming from the wf_engine_control is counting each byte after the -- FSS and before the FES. -- the LGTH byte (s_cons_lgth_byte) is received when byte_index_i is equal to 3 and -- indicates the amount of bytes in the frame after the CTRL, PDU_TYPE and itself and -- before the CRC. -- In stand-alone mode, in total two bytes of data have to be transferred to the DAT_O bus. The -- process manages the signal slone_write_byte_p which indicates on which one of the bytes of the -- bus (msb: 15 downto 8 or lsb: 7 downto 0) the new incoming byte has to be written. -- In memory and in stand-alone mode, if the consumed variable is the var_rst the process latches -- the first and second data bytes. s_adr <= std_logic_vector (unsigned(byte_index_i)+s_base_adr - 1); -- memory address of -- the byte to be written -- (-1 bc the CTRL -- byte is not written) Bytes_Processing: process (var_i,byte_index_i,slone_i, byte_i, byte_ready_p_i,s_cons_lgth_byte) begin case var_i is -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when var_1 => cons_var_rst_byte_1_o <= (others => '0'); cons_var_rst_byte_2_o <= (others => '0'); s_jc_mem_wr_en_p <= '0'; s_base_adr <= c_VARS_ARRAY(c_VAR_1_INDEX).base_addr;-- base address -- from WF_PACKAGE -- -- -- -- -- -- -- -- -- -- -- -- -- in memory mode if slone_i = '0' then s_slone_wr_en_p <= (others => '0'); if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then -- memory limits if byte_index_i > c_LGTH_BYTE_INDEX then -- after the reception -- of the LGTH byte if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2 then -- less or eq s_mem_wr_en_p <= byte_ready_p_i; -- &LGTH amount of -- bytes are written --(to avoid writing CRC!) else s_mem_wr_en_p <= '0'; end if; else -- before the reception s_mem_wr_en_p <= byte_ready_p_i; -- of the LGTH byte end if; -- all the bytes (after -- CTRL) are written else s_mem_wr_en_p <= '0'; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- in stand-alone mode else -- slone_i = '1' then s_mem_wr_en_p <= '0'; if byte_index_i = c_1st_DATA_BYTE_INDEX then -- 1st byte to be transferred s_slone_wr_en_p <= '0'& byte_ready_p_i; elsif byte_index_i = c_2nd_DATA_BYTE_INDEX then -- 2nd byte to be transferred s_slone_wr_en_p <= byte_ready_p_i & '0'; else s_slone_wr_en_p <= (others=>'0'); end if; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when var_2 => -- same treatment as var 1 on a different memory location (base_addr) cons_var_rst_byte_1_o <= (others => '0'); cons_var_rst_byte_2_o <= (others => '0'); s_jc_mem_wr_en_p <= '0'; s_base_adr <= c_VARS_ARRAY(c_VAR_2_INDEX).base_addr; -- -- -- -- -- -- -- -- -- -- -- -- -- in memory mode if slone_i = '0' then s_slone_wr_en_p <= (others => '0'); if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then if byte_index_i > c_LGTH_BYTE_INDEX then if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2 then s_mem_wr_en_p <= byte_ready_p_i; else s_mem_wr_en_p <= '0'; end if; else s_mem_wr_en_p <= byte_ready_p_i; end if; else s_mem_wr_en_p <= '0'; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- stand-alone mode does not treat consumed broadcast vars else s_mem_wr_en_p <= '0'; s_slone_wr_en_p <= (others => '0'); end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when var_rst => s_mem_wr_en_p <= '0'; -- no writing in memory or DAT_O for the var_rst s_jc_mem_wr_en_p <= '0'; s_slone_wr_en_p <= (others => '0'); s_base_adr <= (others => '0'); if (byte_ready_p_i = '1') and (byte_index_i = c_1st_DATA_BYTE_INDEX) then -- 1st byte cons_var_rst_byte_1_o <= byte_i; cons_var_rst_byte_2_o <= (others => '0'); elsif (byte_ready_p_i='1') and (byte_index_i = c_2nd_DATA_BYTE_INDEX) then -- 2nd byte cons_var_rst_byte_2_o <= byte_i; cons_var_rst_byte_1_o <= (others => '0'); else cons_var_rst_byte_1_o <= (others => '0'); cons_var_rst_byte_2_o <= (others => '0'); end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when var_4 => cons_var_rst_byte_1_o <= (others => '0'); cons_var_rst_byte_2_o <= (others => '0'); s_slone_wr_en_p <= (others => '0'); s_mem_wr_en_p <= '0'; s_base_adr <= c_VARS_ARRAY(c_VAR_4_INDEX).base_addr;-- base address -- from WF_PACKAGE -- -- -- -- -- -- -- -- -- -- -- -- if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then -- memory limits if byte_index_i > c_LGTH_BYTE_INDEX then -- after the reception -- of the LGTH byte if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2 then -- less or eq s_jc_mem_wr_en_p <= byte_ready_p_i; -- &LGTH amount of -- bytes are written --(to avoid writing CRC!) else s_jc_mem_wr_en_p <= '0'; end if; else -- before the reception s_jc_mem_wr_en_p <= byte_ready_p_i; -- of the LGTH byte end if; -- all the bytes (after -- CTRL) are written else s_jc_mem_wr_en_p <= '0'; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when others => s_base_adr <= (others => '0'); s_mem_wr_en_p <= '0'; s_jc_mem_wr_en_p <= '0'; s_slone_wr_en_p <= (others => '0'); cons_var_rst_byte_1_o <= (others => '0'); cons_var_rst_byte_2_o <= (others => '0'); end case; end process; --------------------------------------------------------------------------------------------------- -- CTRL, PDU_TYPE, LGTH bytes -- --------------------------------------------------------------------------------------------------- -- Synchronous process Register_CTRL_PDU_LGTH_bytes: Storage of the CTRL, PDU_TYPE -- and LGTH bytes of an incoming RP_DAT frame. The bytes are sent to the wf_cons_outcome -- unit that validates them and accordingly activates the: -- VAR1_RDY, for a var_1, -- VAR2_RDY, for a var_2, -- assert_rston_p & rst_nfip_and_fd_p, for a var_rst, -- jc_start_p, for a var_4. Register_CTRL_PDU_LGTH_bytes: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then cons_ctrl_byte_o <= (others => '0'); cons_pdu_byte_o <= (others => '0'); s_cons_lgth_byte <= (others => '0'); else if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) or (var_i = var_4)then -- only for consumed vars if (byte_index_i = c_CTRL_BYTE_INDEX) and (byte_ready_p_i='1') then cons_ctrl_byte_o <= byte_i; elsif (byte_index_i = c_PDU_BYTE_INDEX) and (byte_ready_p_i ='1') then cons_pdu_byte_o <= byte_i; elsif (byte_index_i = c_LGTH_BYTE_INDEX) and (byte_ready_p_i ='1') then s_cons_lgth_byte <= byte_i; end if; else cons_ctrl_byte_o <= (others => '0'); cons_pdu_byte_o <= (others => '0'); s_cons_lgth_byte <= (others => '0'); end if; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- cons_lgth_byte_o <= s_cons_lgth_byte; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

104b5b6f84715b4488b2605f04c83f54

mohamed/fsl_perf_counter

hw/perf_counter_v1_00_a/hdl/vhdl/perf_counter.vhd

-- Performance Counter for MicroBlaze -- Author: Mohamed A. Bamakhrama <m.a.m.bamakhrama@liacs.leidenuniv.nl> -- Copyrights (c) 2010 by Universiteit Leiden library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity perf_counter is generic ( C_NUM_OF_COUNTERS : integer := 4; C_LOG2_NUM_OF_COUNTERS : integer := 2; C_EXT_RESET_HIGH : integer := 1 ); port ( FSL_Clk : in std_logic; FSL_Rst : in std_logic; FSL_S_Clk : out std_logic; FSL_S_Read : out std_logic; FSL_S_Data : in std_logic_vector(0 to 31); FSL_S_Control : in std_logic; FSL_S_Exists : in std_logic; FSL_M_Clk : out std_logic; FSL_M_Write : out std_logic; FSL_M_Data : out std_logic_vector(0 to 31); FSL_M_Control : out std_logic; FSL_M_Full : in std_logic ); end perf_counter; architecture rtl of perf_counter is constant MSB_OP : integer := 31; constant LSB_OP : integer := 29; constant MSB_ID : integer := 28; constant LSB_ID : integer := 28-C_LOG2_NUM_OF_COUNTERS+1; constant RST_ALL : std_logic_vector(0 to 2) := "000"; constant RST_ID : std_logic_vector(0 to 2) := "001"; constant START_ID : std_logic_vector(0 to 2) := "010"; constant STOP_ID : std_logic_vector(0 to 2) := "011"; constant READ_ID : std_logic_vector(0 to 2) := "100"; -- 64-bit counter @ 100MHz = > 5800 years -- This eliminates the need for handling overflows type counter_t is array(1 to C_NUM_OF_COUNTERS) of std_logic_vector(0 to 63); signal counter : counter_t; type op_t is (idle, running, reset, rd); type op_array_t is array(1 to C_NUM_OF_COUNTERS) of op_t; signal op_r : op_array_t; signal op_i : op_array_t; subtype id_int_t is integer range 0 to C_NUM_OF_COUNTERS; signal rd_id_r : id_int_t; signal rd_id_i : id_int_t; signal rst : std_logic; begin rst <= FSL_Rst when (C_EXT_RESET_HIGH = 1) else not FSL_Rst; FSL_M_Control <= '0'; FSL_M_Clk <= FSL_Clk; FSL_S_Clk <= FSL_Clk; registers: process(FSL_Clk) begin if rising_edge(FSL_Clk) then if (rst = '1') then counter <= (others => (others => '0')); op_r <= (others => idle); rd_id_r <= 0; else op_r <= op_i; rd_id_r <= rd_id_i; for i in 1 to C_NUM_OF_COUNTERS loop case (op_i(i)) is when idle => counter(i) <= counter(i); when running => counter(i) <= std_logic_vector(unsigned(counter(i))+1); when reset => counter(i) <= (others => '0'); when rd => counter(i) <= counter(i); when others => null; end case; end loop; end if; end if; end process; fsm: process(FSL_S_Exists, FSL_S_Data, op_r, counter, rd_id_r) variable id : integer; begin -- Default assignments id := 0; op_i <= op_r; FSL_M_Data <= (others => '0'); FSL_M_Write <= '0'; FSL_S_Read <= '0'; rd_id_i <= 0; if (FSL_S_Exists = '1' and rd_id_r = 0) then id := to_integer(unsigned(FSL_S_Data(LSB_ID to MSB_ID))) + 1; case(FSL_S_Data(LSB_OP to MSB_OP)) is when RST_ALL => op_i <= (others => reset); FSL_S_Read <= '1'; when RST_ID => op_i(id) <= reset; FSL_S_Read <= '1'; when STOP_ID => op_i(id) <= idle; FSL_S_Read <= '1'; when START_ID => op_i(id) <= running; FSL_S_Read <= '1'; when READ_ID => op_i(id) <= rd; rd_id_i <= id; FSL_S_Read <= '1'; FSL_M_Data <= counter(id)(32 to 63); FSL_M_Write <= '1'; when others => null; end case; end if; if (rd_id_r /= 0) then op_i(rd_id_r) <= running; FSL_S_Read <= '0'; FSL_M_Data <= counter(rd_id_r)(0 to 31); FSL_M_Write <= '1'; rd_id_i <= 0; end if; end process; end architecture rtl;

bsd-3-clause

78d91e86c78a873fbc4cb59fbb0be137

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_synth_comp.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block D575Q3xzVw3eZG00s9c7sTS1nwf1O3yzcrHJcCZiylmtgvASqnNHPH6QTSxf5raWmi10OO80dMLi oDdeojVJcg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fhjpSstv2K3O7nDXVXfjxLfz3Snm75KElX7P3hjbm3ceZnWw4hqwaZ8+440m9azViR9+9UkL6/Ei 8Ru3VvvcNLRA5ez7Zj6fm5NkfabZa+cbmITovUQLKJrymKIweE4lsZomw/EcNPQlbmj6F72txFLf vcn19xtkfPpy1MVI+Q4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XQS4jH+WvuToq3BjT6h3uGnSEz97jhe1O+1vCP2k3SMEht7H/Vw1R7VXyq5mzg2fqzqIbeOkpiT1 0Nak34fIG+CpIg/hSeL6upnFy+i+zTq/1eF6JqN6wtCv7x7sG3rW8LPuoogEv+1Z+tkYDh090gBG YT6TW7htTpvPBTMpslNNFxOh3sgMWFD0OS0BhCmllLCF24fFLhD04bhN6vXWv9PiC3BrF1qzTJnW mhSccyXPH6r5IcdytK4VL76eU6HOBDy4ebjc48csOU3AsPH43jRjAXoS33nqGOEXR/LOEhwee0ng CUfQLCiygbZhEokUuHQ+eUdEUatdniDjIEa9Vg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block w92+OTk9wJGfWYXiYHSx2Y1uOJzbMuNSZu374tT7qA4u26sOdfvvAMht0kxIminKM+88uoFTZlyw W3rsP1Ms9JLzBn1jfIUPco+olaBQTIqZ1iJQKVHr3ZjW260HMpjG3Pg4nA0klTNTwG9N/0lr/pRm A/mcqpvySU5QjJTQfxM= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Ioiui/sDYRe9YCrQvF0xSIw19D5Xz/FTZVAiJPJgdO67ScUnzFX7p33fm9S5pzSQ086VEmeckcph UVIMaS/+5ENdW9GIZuPqcfyMqKK3/NP+xjrYlWf42QIOOUdMw/8fbi/hRwwo86KvDjQNe23KeQWa cxPege0F40MWKA9yybDyXMHvQqAax2+BEe/6+C1Z0oHaeSARxIsxkED7916E0UJpRX5sA63KETsw 5l6Xy80HEAeCJg9YET2RpyaAm/0TsJA9NYQgexnWWfWeDzPXrNdL0ndJ0+Qw7PDff4scPI7ORaj9 wkYxeghoEUIihSw3bjVpKYxLHEuXLCSlFJ2ggw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11888) `protect data_block phjJ8oIofYE4kvmLI7PfAwDoDn8y7ek5nRQ9n2aHSCqeEASgrctP93tqjGbkdgQP/MpjHXXisPzI JNEevPzMaZS1e3DtuYpsHt6yWoj78gt0Xt5AHAC5Vz3kiIlTy2j8Hq8JP0rq0Vds/uUysPrvsCuB iqmrgpqOwF2P+7EIqJzwkKNY3SvUG46Kxcwg+F1cpmXfJZNtlI+1FM701lQ3v2Qs2lCJSoAGwaHI X/Mcp68pjTyFa/a1IUxdSnfJOqbHKyZpupYtN59PFn3TmFHQQxDwyZ+MhwPaKz500R/AVi0kjLhf 2+WG6EeZundjL0ZW8/WauXr0eHJbf2M827mgHgbqlnI8VViV3daJoUjs5sJAwP6+2v5R+mbyHz16 a3tp6B0kAdspA/NTPrsTGRz5Rt5SyIrC2K/tvhuclPs3zsaxbQl92bi6pH+hzYprfqtLYPzvAfaI dcbIaUMu1i2/NtyhxLn1wgHDylcGxOUu3QfpOZAp/RuRgUOqBzTUl9+wn2at73vnNUmzAeIh6VNi sDlcGVwszU/6qPBZhA6uTE3sczAAFh6Uy4sSzL+xmfoeq7NyIn8Fgvxk80UM4h7utKiAE3lo2X4w Ez3t0XwdwtrxmPM4citzFiWKsyn8f3mxvYJvbNTH5oXPiEqUN2P73E6jnWYuORcVWrhYWkyTv4dJ MdRP/eubSQoxMaanGkaGnnG3jPMPux1R4JkGPFbjd2FSWet57vnQ5A8KF5sojxmqS8KpQ+3Ff48l 0vnH3gpJWz0j/gLFPjCt5mOn3HGkiyoQ1n3D5mSRHwvOhvI0V25vlr9ZT82sSZEPieGcnZ+tDNNk Fn4PmPoADORNnNnLEDE/92GrG/ToE0CVT4fkg3kV/4GQyQF1CioiIPSg1FsH5NimQytlydl6hPda bkGBUnrI0KYuSPIc2ipSw6o82JrkLNZpowGhKDKeBL1wr9EcXQqFKk6L/ir/oPKnfhaky9Vc8THt lhhFC5jssOJZe3qTR81425AzUmhyV5hqKDyjnwVlcC+jbqEi96QkYFBTOVZX+BcyIxAJjb7W5bmF n21bdSy3Oj7i2z5AzoRpE3xN/ayMjXx2eoKcnGr7bgY+r/dk16FlZaCFMibDYlfaM7exFh5Weysd SoazYTZWWxHtF8NjeUS4uqXzyHjI+ev2P65BS5pjvHAgwr9kYpaKgeQBnrsH9A5UjZsoxc/86wOI E0LrpHE/j1vQouzZLnZSSm5mIP+iV489yZ1cXO5Meq4VxhqOGMe/dLCJcr4pO4mIjt2tlBbhYaKM +BftlNTM/ejXa01FMF2aHHN6pQk4P7tTDJl2deEgMCl9e7EMzYFyymhlPIDWUzdm7ZTcxxDkLYSt tY5arM48tnjVtxJkomSlgCvC1BIEtIuuRcEzrdSpHrUom/RnUtUVvRWS4NyDKyKGKHCumjmyTwri 1hmaTcj7tFj2G1ivuRkaGMLd/oyvtWPwY2Mum0MoCff+nntP+19VqCTWHOnf6iGqhls4OdUf/Pwe 6TBOeCR+yIyOFB8LGQUuR5NmnSYNUbW1/Jyh/9rdKRi8iF3Pekn6sGE7yO0b2byDtrkiVe1plnrq ULMbb1WWaQ7tKB6sizmIn2seIpsXBv493i8eQSBBSYGTMmAeSekA3Ggo5iAoMu5BTLi+Y/8VtkLl 02Eus19DtJ7H9zVE0z9fyJVVBUNZ5NBUWjEoMUm0uLqAwYxDSKwnAAEIboF7htoAQOMzFDcO4VE5 FGYn+77a9++N9TY5CKWnpbUoeAhXHzpjwD7gFFg3E83QNuj4XzT7ubQT1M+PBTjA2SWVQ8cyh7VH C5ptqyTmJPImcQKwSz4h1AQxx50nvsh4nEjPYfD0Ugd5EFXT0ZqSd/D34z9IblS59Mnin+ZQleYg atS9/qMbGsSm0rnhrijCB+6DJ7vcm0RC/sD46v5b++Yhf6i00upjbZT0o1vWq7TzfDihIR4eZMv7 MWo06QrG72TQU4ueqPEJa46MsT35eUyaJD5/94HYmi2VbcEzm/I5IquDkQo9K9111F2GrgmHbPrL ujE3bMNesnlNvMLO3A65ba7xeoc5JtO2rgF1trNsL6WZ6fKAAhGmFdWELVrf+mvwvIJG9GsMnH8n aivMSsRfNn8uBvaX9hMdLj3xpOnGPgen1T+ajY/H4J7dLVUuiYY42CI+r4Emq/pl3dJXD0Z4DFcj sYCoqWX9Qdz22X38DwHbEURfX9XMIYNQTQ+IItnVS2KgNU9qrVwwaxum/jP1smEWItsqYVgq3BzR ZTy5+qSnHSsAT/4ebYP2V2HWkVNsUZuA6mSg0xL6nb5qf9yIYOzTA0LXJEir4YYl0t/sd3wcbLzU 2Lq4rZEmCQjBBJ6L/geBLtRAdbQi1pg9LAt25DuW9kd/V3bE4hQyfByK7rBMO/x5UDjl4OgQeKej Vs9LDqwRsBfNWYCAKhUnhaIyS4SyUpsWzv/IFdyu2kF7vh6j2CfX5qtmT/Ne/2R5X0hGSU4D/QiP DZ9HbWPl3M9BWKKYDtadu19At70ahupPCIpw1wkqB/b6l4GXN3/HW6m1lc+OX6P86e5cOkBzU2co sU8BWHuVRvZJ0aILwUAuPJIUa8c30mFpq/P1QHHeuNlRuyueiIabN8UMxE8u7P8rg3oP1GFeC8fq rujpXKj3sc/7WJrtJKhKA33YjXcAqp2LhLMKFg2kEre3iUPLtKYztJcJJCWABxgblmTUYA5/ZkdS 6GapjuZ+z4XlgAK9/mcKuiZp2sRR+oWDDpE+R4g8alHIhaq0AYwuq5LYvH4Q+5xkehxyubtrexVn HBWMlpMapsqdDE2EFnDD8XfPcsf2OV2sfdGFkqJ0cOz5ChV57ZRLR0wVSmLVJolTlYSIEpv0bhG9 n297Cxei89Gm0mV6t9cVa1TO0IFjOpttLmS0AgZWyfj2SnpimtyOF45VmS29Te1dqV50HdfvAN77 NEmTeLzvfezpdC+kRoW1SDSL+sN5RGF35D1vqQwqx6n2B0TNHIuyHXNusYuUghhyl45OVlwwpw0G L/UYSL9fIoTBeHviCQRv9awe5BEVTXEhdiabxOJruqs9OmOJxbgXzWXoDbem0VZ35zogrJIBgcPK bxsRCznEICOox8kCQiki17fHfj66bk4+Lsh4re2LpnMW5McO+OcBp5qQqOkRM50ktWfmqMFtM0Rj n+9R1m55TreZ1inO7VoHmr5k8PXr07XHtmE+BZDOXe3n0oygP7OvQpB0LWqg/Qa0717Ccr7xDcoN Gqjy6JQv5o3hsoZou44Cm3z/YCq4KwcNUazwyB3s4Uyiqn3aPu9tWHOT8/qwYkPcf/PrHQNoUkWA 4/iB8UujcMnfQzF9GrDsR7y2iZKbcyMbYVeVqT64ic6Qn7RMhMXaYLOMZvz1KlErrqC/Pw+K446f uqJZINQ8qme97aNzcnGihRAz/C9Zn9YcleYEXK7/bgG0jGuzjvMRly5bvRUmdazrNOSHSLw6RwfV wPngbTjRgr+sENR8u+dtAX2tikRNHok3BVa9WeVpvHnamqPVlHJebc+Z5OvBb3WEbp8iPwbRr03V /vfsnfP7loIgIcTarrTTCF01cwBWavx7em5ln/5TEpWCC1EceGU2FHbq6uXc3CYRGgg9CZkilUlF p75lH56Wd9kgxUIJ3m6U0Mo3bhqP06xhdhMMPH2m80zz0jjec6LOZ5IFh9hA79uSMyQgDV18ICGv qyjYactLk0vgWmgnf/kUOcVR2sc7Gc9vuSg2KlxPtZp/2PZ5kytbkeqPgkTpRrRldGD+tdWnoZ6M 6JPiLpOAKY3cuyXnvarhfTgCqCcT0EMLT7aJtvbnIevVFirwX5hyk+QxWXMI8qtqDoPh+Wj5XtR/ yg3ECHMVVNNo9Xd4/lqqv5PMEJyA55o12P/eF9RoJ/6XAr5huQT9xqX/i+A50mpJ3RKcoj169EOI Bu8ehgJbGKR31N0IIXkZjPQhhWL/1Tupgc7iED2iptYCfcpFA2OKa4yC6wKFz+GbEMNYwWpcy0uC +AM2UBakRiFGcE1nj1iMOGQcHmjnK0e/2r/HA2kDHIheatc4sbjqKY0gc4BXELeMg+Oh1rWGmaXT vLzl5j7l2FSZh9XuicVwDACXA/ysR5OREXvvDtms6r4c4V+0fvQQDtlHCb6wUYRfbWmOla1tvB0h T2vCVoU1xKEsaZr0IQsB8SL5GGX2QVYCJ49t5nn8Osw04xr3ri0C0dwR0vxIDQMzAdf4J0hdqPZz DvEbGLov8q09uYuZKKvVTTBLUu0Awg/sHHKoGWKUFkXOYxKxW1y3QyN/J72COu9xveuzM0pVRDGj cOdbwnziJ8nLMj7q9hOzm8pGoUlmW8ykOQBPLcnYdljxXq0GL9bJFdANK6jRuizqKGLUm9MlHnvg 1G1USqlqqLleqXDQcLg3FwdXp99U6aCJfqPwdYWZbYZJ9xNlE5FXKDvdJ0we8D3WkMYMVF5hvzxN 7jZgt/2gPPKi2CeWF7r41JSlhDtUcud/A1n8XIITyLZYqM0if/ZNypmuGTBx5SgI5wnaiiqhklbb Upz3Q2J5K1XPMXHRNG3EesyIF/cVA7jaS7NgW8LbwvVvDJmXaMJptTqDp7uTS+ZDmWHO/LNfetek +OJmt7i2iaQ4sW5PilEdYyx7XZocl2g2ouje1Dep0+oPyvu+5fjWGoE2Zv4Jmns9kJecOAqL/Vql 0Qh5WkCf4GMfvpL9m9/2yp9UPNvQbzK6rWDw7JgJzwK0umaH8/Q8SXqnVtnIM+bbX6kJNpAnUxuv meA4tIfYQ5Hwq5ZmWttzKs+yOP97AvDn4r430rALtzKGD6sLHpzqqZnAXDGUKDVNEBP6UJVvbct8 vfAHVy+V+3vfP4/DeoluTFQWuoQAaQaJD/VjN2gc+ZBkgj5Hgo2V5gvirPHVpBD4qmq+js3ccMrD sTH+EK+/QUr3ePTem+zF34Mx3/aYqOnWd9jM1V/oRipulbPk8BS/gkF4b8RYCtIXftQsuyJF9Jfc 4AcYIQNazfd2OCeQVVm+5urcVS6h4lniGSHwEb/paqFQks8yKvKbQqolQYlIALSEweet/H5bFUsc f+oL56dAzF8iTl14l650j2yGp8q2sW2tuV9ts0jnsCqCAn16zZZAROmmC1dFMyvBYC/Euym5s9e4 BSDFNSIQHEaX8v9hJaz2jB1jALpBHxsYW5LHPs3cD6pGIbOuuJGdWtm5EKn431FY8hFygypByUyA CJWaElT40My6FJVP3517Vqo/n19N25UOHD7qlCKcK9bxgs4cJ2vKFf0PbM/hPOJ+slv15UoGH81J k3hpKNYG2NRDny6KwTjxYQgiYA9v9OpZR5joQOViadZzUqDiM+k/uHLOv+uQ3d8PEhKpyqW9Ytjp PJ1jHobncXZcduJFifupeBKui9zSsAePrJMcU6cHZ8CGZzprwXDAYVo9GtPLIUoIIPLLUkXFS+JS Fet3VtaVaWcERYOmzLfGrchecR8zRHiSIZnGabyxjwmyDtlrQ1LpWnap3DKG1ydwSxsEb0wgz8Oi ORSOmGx4+Zt8zc+c33UN8PhLm7ySVwGCZRt/ktrj2QNhW4IOgfdRCvAFltrJbL5s0CYC5RWJBYFv XTf51axCBFsKbrvpEUcaS77k5sRIoHSox93xVuhAm8A6SZ1WwubuRydLNLjPg5po1VgFkf3i3SId s41Pmb/3czZNxEaoSb0Yj3LCZm8Ybm3fQjKxy1A25Al0cvp8UQVdvxu4TxzgxaoIcXzr4MilQMJm aPSpgHjP4IVYzTA3QfXrH7VmphiNBYQqo7tMKerDAoDwfRdPVzXUTwW30xWNNTkx36EwlINCcYw4 5X85QuapqH59DdZqNXEC7s9Ktv8WvoS6A0ewtAOX0CZJgx240eMTuisSYPD7u0MFfP0W74hvgiC/ Fx29I0QTFHcLdxkKQUfvBDVVKOQRwhibOWMakRu+R1T0gxtyBbOeDO5RnSfGbuDkwRS3WkyAh3yz 1vw3zO/YKO1sNSpmFXKTxKFTKAw2o23GXxDn4OBspl+XPSyDGuPqvgSzurReY8dhMZ58EFtmMBVi O+IDgtxOFpxKWn/qzAYUylk1sLq+WkqwjMPPp4lO8WMzYkViONEo0RMMenjy8u40Nm0mhfHmdQFY bkmWUeJSPhjKTPlFs+cXf72czenuVl1B5EZv9UwfyJGrGcLvI3iEFUjxZIt55zwHyNoxE4SKN4WB yLfVa1r79eD+ZBk+VVmpcL6UKw2+aVGUgQpwH6CDtVqf53twV1sz2Jk120WR4TNSpLkT/8Ql8dlZ 70EEForNhHQ/oEKa75YAQ/nwjF6a+F7uOwjIXmP5wUB5KFNWuJclsUfDaZDONml/qw5mi18/rCyR XkTQWJYeGaAZCNnjYTQcWKqdbwbaJnxU/KsOWAdyQ+6Eqfzcq1+B3CKOXl7QaYWmWaq0ae/qOFPC 76YwklwK4t5UdplKvuux0nfipLVV81amLq48LQ7yULSIzscw0mRNps797oVIsJzLD+rsMe35nSKv XmuZd+kKcjSBEClwbwMKHWBGmRhTxuGmbD2rez23amayuqyk7o1l3dUHSo2ngpzAuLzYIfMxi6G4 F0YCKScaDHIPrdBm2zoMQ0o8kKpsawpbWrNqXXBOkiuiSl1IiwePLkCsYlZFZmCzr2zY6ErLwdAg Wm6ULn2HqOhLyyZmtXxuOvxB1jQvf/fEPJs9mi6yZgIRTezewY85sKYtSrzu76IrqstR3wB6CVqz rt6eiDIFGtBdp6il3NkX+O3tkX4NsxrSansfbzYuadwOtdzb8s9ixUC8wj4pXfyUu9RnX89MdAsL 4zx9xkqbRlilqSoEr9F+UCow8mgFf5AaXzC8mGAzULZhjJvvuTs0T2dXwuRfiqbm9e5Vg7vL9bIy 3iyUbP3dKX9SouFY5kQ8I0ZwtI3seIxwYt2H5yZwxeJIp6N5h9kn06c8L8262CFj3UQS4p4n20EG Z6gQFiK/v2EE0zaIqAFQYw5e8If++u685xp+SKAkwYw8vCflioe266HMDwTZLAX+eXcFyBDBoOy5 FJ3QoI7lZ7Q9AT1sXjsW06FpgGEjnLJy1Y2xuq6xzah6qs1SRFXHVsnnTMiq0i8FDTTNyxdoXLBh 4hjC2DFzTOyeRUYsx5DkBpBAQ5GfJ4+8YbZoba4B9jhVQ+Kb1qbvzi1B/gpK/ZwvSqtRQRVQDKQU msrgFZm2G53oF1vxdXwNcSZzAZuRF9X2Oxh2RpF5HaZ4Z2+gG58/GW6aHVfy8REd2B4AxbZN4Rai HH8b802rrGOuz35Fbaq2bRdrdGOgfdsA2nx4cZOmvS+rNiB0VM/y0GxEMGM0cW/SPtRABmhv6NDZ gaQtVPgTmLyshB/eWratAyewYNzxTpX75O4Fwq+vsGxMRO06cZ59zhX4cZZ2SLppQUahtF0OhfRd 0FTjuKeTGs3DpkDepIGMvqQTE6gUd6fCVLdt1/0SYm5r9jckc3qZNWEloarXsL+RTiNKWAz9rV+y ZAdRtGQh+J3vaxc7tHn5KxGZm01LWcuCL8ZFq/Vdokd8XCY2afxTh8ALaMlorW1YBhb6L4AfUvDa 3CqplMC4VCWBldBEHOUSv/7O9Vyzu8eaEkzfM7C7L6dlVp9Zg/3aUei89g118SXeS8a+SfopZ3tG pcfeALjbEyKMgLPX+4+Z5KGTDmrxpCt5f0I0qJW6yyRsLER01vi7nYYAYzkZ+pUnSvnyUzTZnd5h A2KiawAdgx0d6ygJrQZQ6fz/87e0grGC7iinYE7K3vyOFC/FddeSNYqF4ORakEve9f6SzXOymnR3 8WY6M1hGTvef2QRhwCiptjRwtV9EJV4B+M9suA8oT7lzvTSkujTpPJ7l0lQyWxDDGs5eb79DNkdG EvKAMsU2GE9gdg65dexWyrYEog4WqX1OEy1rEw8vQwT0QePW96+zngWF+B+B8uTZmbAaNCvblV2P LNrfz/URJQRC5lLeNukqZUQmtYOqQzt+9wobSrsU3jQ59obkHJ7UCO7OQbq6oOtAcjKG0v8Lcufa bKVRJOXsn5/Myt92VWncybasUxkT8Rbkd9ajvxgiZrkOc7IsgiP8KJaKJ8ZX4PHTtRxzbDIEUZPB WmZRBorosmA3yA2cepxev+kXo/+pI6+eNuq6e0QtQghK17YWOmF5RMAq7dNreRsxri6c1VYPm7uy xN2s6RNvRhJushAXvokxZh8eyklbm9Lf0YYcyXgV+8/AGMyJPLuFBnHNZxVefhgAhnvaVgx4N2MO boSzG3SfnHcEiok+a9l1oEbH+plB4d9krTISYngM/X/b+kdQC47wUhXTZFJf9v5iaaLhEye4uWlP ga4NXDjT5ZOWQ+d2bGALXPz+D1jJs6X9JEWph22eaBQTVpNKWhG5VTyCEoyfMtqQl3pW59gcP9qX 2TFBc/ZIW10uq2J3qLcKHcfxuNqx1ubd2IfV3qPSBiAt0kdB5l4Qntc6o0qRymSfCZw76Ew61A04 KKJdLP2rAXW5Z8QU6/I95GSpN4eR+fZpvUBHRWcMu9qVw2Dop4FmfYMike+pDJ2T0zAj3Tjba01d ET+qE8B/VN/Sn1QRkbsbkkkjcUHsG444poPuZWPPn93Ny9ThKS6nJOHskA08PiuYzeWqiXTQN9ln QTI8r+XYgFhIsKKN7GV1YpEttU5DPjOF9QZGoUzn3EsDiAaZym+JiMxCupxkMTI8edpdmQFIOYTc WHSTvKYj7Zq9d8ENqnC4tnD8brzWJJbTXm/LRYe3KIMFtBOPrSVDSShdgWk5XBY5RpesSpZO6gT1 buZJnORw+0AwjCjnMBJ1b4i8sWRxbKWl84moboy7BQ28cl52qE5fWBHmy914xr3/M+kS8TE/k3t6 e927pa8AMevg7VO1RJjG79x5CXmWtu4A85JsKW5ulnAhhSjxUuFVQvxI6T7QitZVtD98ZRDXCHqV d8osFzV443Swjla7QSXPfYtipGoarVK1LUFcabJWPkAHXY4QvAEmB/UPliBAAmKedAbq0hIeLUCQ Nmj8LxzZuWxL6qXcXjLHOTLs1wFNumDC5sraPKX2BVC5Ly+V7DCYulxZ4YlApSmQoXPkrXZLNShO RLjRxOx340wx0NY2En2qMUkPXpNBxmPhXrfOdS74jtv8MB/dAi+b6IsYW3ukxDQmYhY4nSwRjZNS oc9no/ig5u+NvVcBtQwYYYvagodQRpeAOXzsPqNF+NpQCzF5x14JwgyNz+ZP8iokNteEoifOzx53 VBV5vJevvpUaBntQgNjy7avAFMjAjdKofgU6zn0dYjZMuig72V2jK8z78I6ebLRU0X54oB/9ElTE o+2fjv4mOsQvHWhbrg6Ej35tMn/u56KL4d03AbunzEHsXn+m1bApo9UtTBPO/bZtnVJqcBRukMUs lr8JeWKdn4OKHFX04EAEeMjwLzr+zmrZxDypULV0+ts5KUxybuSB5pQn7j1ZCc2pQKIAJ/yCyQvU ZWP1x0wn1jSUJD22LaWxUIroTuHFr/TLjf+0VbclAYnJRbeHsHoLWUmSjTmP8YozmJye+ka5qJ5u uoTxwo0MPf/QiJq6rmDc/7ZMUo//fiaSUj4LPl3I+vqtH+MWhnFM4msSWhDBVZTR5vi+Uxz84iIB vso4LZabgF1SKSk4wUaxaAnQPOTxafa80HoJ9BnnDkhDHlc1eXGjvSpVdKXJowPBzGU59HvCLAw7 H7hYqFdBc5nCiNwZBCPHb/ugULeB4WAYJixXsg57cskK/0x7QF8tsxPkGHBW1mrR/konpTxvHnJm 6iAOew0fPYUvE0XzXOsgqgDXtXLqcE3wa0mVt2+bQsSsOjFk7hqjacoAPpG8EO7rLXYO/51U/9mX AOJ5vgSMRGmSxH0kPTT4Au29Ppzso4xU/Lu6y7sX3pEp9e72CA81E7L/YDfoyJs5c2sAaRf34fZS sKn2zDWqHiEbbHDyy8ZtELwMdQb3N61e1hncS27TbMiAQr0UdppTzdJoAsLyLTtbq0B3Lru5N6yb eN7iKi92vHCVmVK5TkyEQQC5LXjgfoA3bDFDxSpGS398KYziW+BS9fV0dFtLDyrIXvc924zqrnAU YsRY3O4H0rvhqUJOqHJ9dMLrw1FH2Iek5YejW6aGJg42W9MDg/3xKGLCELr/USSERemO8nZrKMUZ RNuNa+N9BvFKDS2f0cDE+Vl3QSy9P96LkEGR6pYFHs/UpOYUAaZ7ZE9TbHRRg7E6IcRYToGZEnTU uX7VgFyoIimoHk9sRobYkY2Q6tqre6ibhZCPw/UIg0DVNuaDcDe4qr1K9EQHXNLD2ehPHfJgFn9Y 2HfnFEML9ZmjRyBDr6vIHY45MhCdtzNP4Tj1JCg6XlYK6C/GicisU1WzAcI8L962uyzSgnwclDeV ZeRUYv+agaps1wbP01wVLJf2BB7NLee5dj1jZEXgM8pZnZS/hR5PPw9LAbC1ALGI6fkL/qWco55/ G3R8IFpyA6smwX8xu4kv7shHYUvVAGrQ9LHvrhdrH3JqKR4gDYDkc5C4jDa3qYCgQMOhzOC7OG2A ES4PycxMGK8v/mV91R7lVJv7aZRjgUTLkHLxN8DQiVC56KfE+OfTkxPtdh2PrQirUqHd4LUm5vt8 LDJSt5XyJq/RoRVG65TDv9cDE8fexdOu/i2XjGp9f5pemi273gAmqK2Fladk43OJygpHDMOJHUUj NNXGPr2PonDyx2VVxQE6tdLt+8F9cWhv7l4IlZNEL9OI0kSBHhIO7bjjWHVClI6Qt5mCvfPQjhQp WE7Y06NYiL6a0OVvGMl4XYOPUoHXMXw3NdJC4wf7yZgW0mvVFkYdx3iq4U+2oSa71dhxUd0fpQOf FM1yMYKBlztNPdyWLiGJjvABkAjtcbAz/Muf+5+BIoBUlDxxmpUjMUudMYEEtYlRKyyY3CNKlS7Y cIoqV/DMFZODUKg9jmApVCLJLPemgHcqB+DIXzKDeJ+KnpZlRvwA2nwMiJttzP//tTzhhReyb6Mq N9GpwJSy22ElO2SMiiBK1BmDT1WFEoRSQVUcvyEt8gjHM5wyWE+mRGBH9fha9eYCnHuHJZUYPSw4 h09Zd0RNDoYt1cExxYTwzB1vJC40ULIiqzb6r7iMLlsy9ZrG8/sQLmaQluF9GMWslpJ7cAIcEBUX PLfriw7GPmg6ZGqscj/qnuZCJA8HpbvjrvowEziDpJ20CdkRJ7cMIiJ3DMra7P0F3ejr8tV22yzX uqvgELV3O2t7NsT63MG9fkZQag11vNFtFYBRbyX/buaunp0udIJCgb2lRzTBGJa+VQspFv0MWVOn EzG3LxWULbNn5ZPvaEm4E9gJGSAswNZTz0OXB/JM/bh38aCk1mE63wZqkR2J1aHkmrdLUYpZAHCY xC/QFjpYSz/r/b7GQCJPoRot90Knqf+Bb9fSeDCOqNF+j3z7CZ8Bs3qOtiDHBWBoM3I6CUViK6W2 kI5lLBjUGjcDZVLLQdrXni57Ie96/nIObD6+MDLUH5u3h4Znm7ChuemUmprprUc1WZlWFvgPK0wL vEas8T9sYbPAYKQgD3P4b58ZgeQfuE6t/Hut95gEgJ/4BfuOUUR4RIZwSP6vUV+nAOBZt2T2HPw3 CrZAN59GnqOEKS0xVZNLd7spkuuLC/n4gQEj0M0uFTnw5/CiUauMmVrgnMFRjk3Q/yu64lkWTY5R 5yhe7+8el3cC9rHZhDMijC90lXofovynYCXDTDGAT4EPJIgvfLAzYFuuW6YSNlhcoSAH2M0tZjrE 78GGGXCHfYW8MSsPH+dadBEoVsVK0WdGvz/awkpvCOuR1vZAldcSJjAWUcpQjAUvaBR/f5VHTkHJ 4oikSdEzjQedHMHPyfn/+E7FuggcR7aagf/Y0+ETB8VboD3gr1E7QZqwx2UOTJ/qc/MsYxlkHnc2 WR5uw0PEWRYyLFoAiZic9k8Mg4Nnp9cwwoDELfw34TmLN2X8t2T4vgfeMQqhnifrqnETns/UNEWC +uEjd4lVJ888yxy4q8kr3u+v3n30HbsZ7RGb/1lOeEIGLVfX9V2pMWhDilx5mrG/NrHsbR3JMihN gPWVJ5JmeA208NeAaENvZPhNfJ6+LUj0xCfhiDekzbVLriUbQM0gOudCOz4IlESy56izgmVTcOwr KLjEOLqQ2tTVsgp6FshGR3vBkfHvIQoHcKAW0pyGSD+0lzhlOPP4M/KHdq0RkmMAEBlBPmiJycWI t4QA5uto5ZFvdlgmxcKobaRAPIgHoKySrlzJ8RtvDpXSEEpDRX6Rqpmh5TSSrKYnTqRA05V0xqOE GRfaiwrPqbIBcCxurvnHcbf6NGjIfBExmW+/7mxZTKghpCYoDp8rRCc24wzlNbl8fMDyAODUABBw Luq54L972/S5cnxie6kCmSOprvG+HW3oRiUW25SjdP3fzfuSNX9wKMRBP6NRwBRo3FB+0dF7hvVH mvhagFA7f4PT/dElBgm3IZkDlo6Dsok5ObHSoTukzxM3YEJPAAM7RkMT9FYXksPfWjaGGGwWXJe/ mYwFlRcbnnnnJAYj5D5CNQcps13vQddqoMQcsZrhHX0/JFKbxPrvjShNzFEmGkcydqEGpWs3fd5w IEbZWXcZs8B5MhQEd3VGlfYl/y00Tymlc/MJmomgjrCo0lD2Vb1ZCkTZMZcrr/0mL452MPUVuXwB vDnCSEQuXOrLZKvJvs31ADnUTTMV18QPKSBvqTonNZ2aQXt4CAg1g4G0A4ldJAz33ELJED9mtP+U Wc0GLMnUSg7Yp4gykdIzBPc6tdLbrWttk1oEPP/mWO+XaE4Vc4x0aOxJWBx3okkV8IwFxT9WpZUx UwJLmWTAxLeLoUkD7I6qk+mBcmV5jOOovMrd3v/tKXiFBMPLnBIwglN+lYHVWHbaTaXQstaHd/KN 3ghn9v/iCaEXYrb2wd6IkIDMYfcuBT1DgZjwAA/wQJz4dYlInJaq3wu6UxDIT4aXf+6pv00YGgO/ ag+StagAT5nfLwbdBr82ck5CE/c+lGKgHjRXDpwOwDdEy1V33m5U0WxC2oqjSORUZraamb45/p01 BCEIvILVtrYodVOQjbTX/8JTLNa2gqlP0g39uoT2dbdjqJdPpGHI5CUeLEz+rmmRwz8j82j5Bnyv FM22UEgC4H62cBNCbd3pnlDgmrHN+PGkV5QaU9gChc2jtl3dyMqkfIRYAPgipBChNnELJVhlqIBJ ewsJQ2ywvcmDl43i0TTs7rwSF4315t3FpZlmNPW/ikkMhkMFi4rBR8MprUoiMFcI7b69ab0vOqsH e0BlFpj+8yh7AVW5hgXVpGhKFSIm7ddHhU8btxM1r9CsAtvd+ajqrs5CvoPdKypE6qsrJadPblns x+mq6hXvwP7t2qp615oykVJgANoNp2hL9bhTGQ9D8QBrNENDR9gdyYMxka6VE4WWTbPFubiQ8+Yv lTBzBI1yALHbS7M+2CPxVJCg7HPvrT76CHInSkM5IZGmV01t57iqSe4tvL/BxHWILZ0PJAEp0xG9 is3sqxntEpPTXQOLAIEPddrzdWo7PbkkM84TY0t5bxiE2eT0MjPl1Ha/SfJTIdI9Fjhn9WZFp4pw J/V1c5VsKXqqc3DOxsx72SiXOweZgKfkSsquOwQnEHC/IK24Vdosou8/i6dd8e6uDP4oe3DwdQWn jTw76jAyLJ8denAigRgxF2yKMgBMBt5w1Uh8wWuAN1l9QU1dcdQGr5TDGEI0vGye0lFyUJsVxSCR UUP8g8MwhSyznuq4vKjk3K3jTkNOzNtKpkZAs0CmSEZ5pYHeOKiaNnOtqD5x1yjhiWXLXQdJ/pSK EDsFVeUc3jBWElKPF20T9sZl7AJF0Oz1GBj9u/Gv0/wynco0GXWWu1/vebo7IqqLUOW9lwSgdgnp eLoopjAKlUUtmXLyEQF7cFOwP4pU6cLO2HvjqxB/+JRmaFX2AemWkepFKSpoCrDFG1etfgHWIyiW vxsgsltFkn8qJS40lioVSFn7pvLlSKt8Npw2Rt358nc21kGkbzXQhUWXUOVczlj17Ie6Xu3VxXNo ZZdmseQk9SayuhLKDLtCAth5whYJahj9qJSArBXF0xjZpRDgFo00lM05aT6WMqggbIOsMaO7jZZu Zq1dNC2MbCijqVLOpTRWWdZ8JxMF7b5bkPZu/ohj6bXOGm4V++NoqW72pdVqNL0yuwcNplQ2HwrJ kFQxewwUJOwgtf586/VqosUKDUb56XwBzqDR4/OudZYbA1WSe+NYsjd6TF+JjR/Ntw5rHIQtozcH pwz0TOcxXGh9tLTMvsyD7rDJSHL4Cse3Ih+9AIKb9PpqeCDhPMyVAeh9y6fmDFjAPeKjAAWAbkPP 2ugPoiiAMhEiY/HNoyGr9O+dD8/+3ksxHpHaQ8CRctypLaTRUJDF+f6BWUHRZuOgVcHETbeOYefj DtMJltZ95d69ch623AB/1ca+H+xhheqIAgiz46zdUNNn8+6T9BBD80rVbjmhHOlo3I+q4OYXcq/S UG3gnDlSB6Qwe4Sdvd5r/Ri215I1yf7Mbe5C3aLhR+zrxckd+E+W6PP4b+LlT4IUTmu4DpTs0N4J yJPr6nAfXilHJ6UwCNI0TJ2tNYINvt6Q0ko9iWRGdPKNhf+7rWJetAAQWhx7yXn37yJcBhqKyUtb 2mLUqnOtJ/HU1hy8buzKLdigi+Hwwml1SS+ApHFy4ihCtRTxl9DHGx+floTuqrv5l9NOkPCtulEq fed+AEYauUGw5Hq4rQnb1h/A3zBD5xdbgYsrj+l10LCM5aC8UQ3XmpP3pNEg5z5wNQ5q776JGPX+ H6Ma5Zi4dy0eYnekGVft8AO4s6KDzi5DKglIGUVWwWCbk7Uz7G3wNKYP7p2nW9XwtJ0zjleGHNnQ pPtVQWNcLfGfRLiXKgFjcgK5R7vf1c0P93RTdGOyiU8FDgN7f+CppemHcGF6zY5UzUKwXgs0sU3w hGVpy5DJMn3uFvtINpypFn7Xlh9WBI14As5qO6a73rj4o1u5JRvvgfxbeItSe7c+5zjWVpFpTePU KX3ljr0vsDybqo8fV0IsKQg6NYhHfgOQduMef6yW+U14sAelzex52gfZYK5EHVjObDuxUFPgGPQg 3SLbEbw9UcpMmNKvNba71DDXGzal5cGEY73QCYEICc2GF0yFufCXeioZv3Th7jM3iXn2Cp7NmuVx WMmlWMhHLFBmE8Qd4D81pnrfoPH15cPRCbBQr94rq1km1+mED9acc+CVbyU04VPXWhMshptLmKcA 97mLeh/ZqUiO2H8mv6yFfXWQOj99i+OitljIiUO0BfbcblKJ+wCNWBXN1s6mVpELUi4/AtQL9MlS b59/huZI9GMLuv7K2v1WCaCyQGz21n6GfLyR+0WOHmR2L2eUOvLAL/IUu27IMe7V6m8a3JQNKyuW vks6clssaC9VNiP6f6otWuGysEbOimXNyymcVVyY59oWyeUI3bPAfV3zJq7DKGEYymHIgRZDbTv2 to1ycEmBnDHSHlvkgbWi7CkidXL7eqg6cbMu359hTECbxdZwVR5aQbuToMxnCCW/9qD1QmoR+Vqt lUYZpeEXTe7lXpVdGmYy4w6RWDndZXXEzxdFs4aoJK0Az0ERPYrIXpuXROQ/c4+WT1oBcbxwqJj5 kJcn7c4FaQqGXmo67PlS6cxwN0qKlizjF8gi5FKH3Ian3Br7o1f8rJQADZ9Kbmmb1VU9CgBodtC2 cbC4qAetWec42eiUHeI/5XlrGthzRenxI1OFjc3aYm0b38cpflfT+fdXZSlfXOSEFKIBgrcdUTkR A93xh78E0d+xlCkDz9mIKVLVJ2Iaj1C89cwdcXAgl3s= `protect end_protected

mit

e88561b78a58f204ef9a592fccfa4cdb

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_cons_outcome.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_cons_outcome | -- | --------------------------------------------------------------------------------------------------- -- File wf_cons_outcome.vhd | -- | -- Description The unit starts by validating a consumed RP_DAT frame with respect to the | -- correctness of: | -- o the CTRL, PDU_TYPE and LGTH bytes; these bytes are received from the | -- wf_consumption unit | -- o the CRC, FSS & FES bytes; the rx_fss_crc_fes_ok_p_i pulse, received from the | -- wf_fd_receiver unit, groups these checks | -- | -- Then, according to the consumed variable that has been received (var_1, var_2, | -- var_rst, var_4) it generates the signals: | -- o "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY and VAR2_RDY | -- o "nanoFIP User Interface, NON_WISHBONE" output signal r_tler_o, also used by | -- the wf_status_bytes_generator unit (nanoFIP status byte, bit 4) | -- o rst_nFIP_and_FD_p and assert_RSTON_p, that are inputs to the wf_reset_unit | -- o jc_start_p that triggers the start-up of thr wf_jtag_controller unit | -- | -- | -- Reminder: | -- | -- Consumed RP_DAT frame structure : | -- ___________ ______ _______ ______ _________________________ _______ ___________ _______ | -- |____FSS____|_CTRL_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__| | -- | -- |-----------&LGTH bytes-----------| | -- |---------- >0 and <128 ----------| | -- |--------------------------&byte_index_i bytes--------------------------------| | -- | -- The LGTH byte is considered correct if it is coherent with the actual number of | -- bytes received in the frame and also respects the frame limits. | -- | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 06/2011 | -- Version v0.06 | -- Depends on wf_reset_unit | -- wf_engine_control | -- wf_fd_receiver | -- wf_consumption | ---------------- | -- Last changes | -- 10/2010 v0.01 EG First version | -- 11/2010 v0.02 EG Treatment of reset vars added to the unit | -- Correction on var1_rdy, var2_rdy for slone | -- 12/2010 v0.03 EG Finally no broadcast in slone, cleanning-up+commenting | -- 01/2011 v0.04 EG Unit wf_var_rdy_generator separated in wf_cons_outcome | -- (for var1_rdy,var2_rdy+var_rst outcome) & wf_prod_permit (for var3) | -- 02/2011 v0.05 EG Added here functionality of wf_cons_frame_validator | -- Bug on var1_rdy, var2_rdy generation corrected (the s_varX_received | -- was always set to 1!) | -- Added check of CTRL byte for rtler | -- Added cons_bytes_excess_i for tracking of too long RP_DATs | -- 06/2011 v0.06 EG added var_4 treatment | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_cons_outcome --================================================================================================= entity wf_cons_outcome is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock slone_i : in std_logic; -- stand-alone mode -- nanoFIP WorldFIP Settings subs_i : in std_logic_vector (7 downto 0); -- subscriber number coding -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- Signal from the wf_fd_receiver unit rx_fss_crc_fes_ok_p_i : in std_logic; -- indication of a frame with correct FSS, FES & CRC; -- pulse upon FES detection rx_crc_wrong_p_i : in std_logic; -- indication of a frame with a wrong CRC; -- pulse upon FES detection -- Signals from the wf_consumption unit cons_ctrl_byte_i : in std_logic_vector (7 downto 0); -- received RP_DAT CTRL byte cons_lgth_byte_i : in std_logic_vector (7 downto 0); -- received RP_DAT LGTH byte cons_pdu_byte_i : in std_logic_vector (7 downto 0); -- received RP_DAT PDU_TYPE byte cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0); -- received var_rst RP_DAT, 1st data-byte cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0); -- received var_rst RP_DAT, 2nd data-byte -- Signals from the wf_engine_control unit cons_bytes_excess_i : in std_logic; -- RP_DAT frame with > 133 bytes byte_index_i : in std_logic_vector (7 downto 0); -- index of byte being received var_i : in t_var; -- variable type that is being treated -- OUTPUTS -- nanoFIP User Interface, NON-WISHBONE outputs var1_rdy_o : out std_logic; -- signals new data is received and can safely be read var2_rdy_o : out std_logic; -- signals new data is received and can safely be read -- Signal to the wf_jtag_controller unit jc_start_p_o : out std_logic; -- pulse upon the end of a new valid var_4 -- Signal to the wf_status_bytes_gen unit nfip_status_r_tler_p_o : out std_logic; -- received PDU_TYPE or LGTH error -- nanoFIP status byte bit 4 -- Signals to the wf_reset_unit assert_rston_p_o : out std_logic; -- indicates that a var_rst with its 2nd data-byte -- containing the station's address has been -- correctly received rst_nfip_and_fd_p_o : out std_logic);-- indicates that a var_rst with its 1st data-byte -- containing the station's address has been -- correctly received end entity wf_cons_outcome; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_cons_outcome is signal s_cons_frame_ok_p : std_logic; signal s_rst_nfip_and_fd, s_assert_rston : std_logic; --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Consumed RP_DAT frame Validation -- --------------------------------------------------------------------------------------------------- -- Sequential process Frame_Validation: validation of a consumed RP_DAT frame, with -- respect to the CTRL, PDU_TYPE and LGTH bytes as well as to the CRC, FSS & FES. -- The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that -- arrive at the beginning of a frame, have been registered and keep their values until the end -- of it. The signal rx_fss_crc_fes_ok_p_i, is a pulse at the end of the FES that combines -- the checks of the FSS, CRC & FES. -- To check the correctness of the the RP_DAT.Data.LGTH byte, we compare it to the value of the -- bytes counter byte_index_i, when the FES is detected (pulse rx_fss_crc_fes_ok_p_i). -- Note: Upon FES detection the counter byte_index_i should be equal to &cons_lgth_byte_i + 5. -- This is because the byte_index_i also counts the: CTRL, PDU_TYPE, LGTH, the 2 CRC and -- the FES bytes (and counting starts from 0!). Frame_Validation: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_cons_frame_ok_p <= '0'; else -- only consumed RP_DATs if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) or (var_i = var_4) then if (rx_fss_crc_fes_ok_p_i = '1') and -- FSS CRC FES check ((cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_CTRL_BYTE) or -- CTRL byte check (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_MSG_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ1_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ2_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ1_MSG_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ2_MSG_CTRL_BYTE)) and (cons_pdu_byte_i = c_PDU_TYPE_BYTE) and -- PDU_TYPE byte check (unsigned(byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5)) then -- LGTH byte check s_cons_frame_ok_p <= '1'; else s_cons_frame_ok_p <= '0'; end if; end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- r_tler generation -- --------------------------------------------------------------------------------------------------- -- Gneration of the of the "nanoFIP User Interface, NON_WISHBONE" output signal r_tler_o which -- indicates a received CTRL or PDU_TYPE byte error or a LGTH byte incoherency. -- Note: The end of a frame is marked by either the signal rx_fss_crc_fes_ok_p_i or by the -- rx_crc_wrong_p_i. nFIP_statusbyte_bit4: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then nfip_status_r_tler_p_o <= '0'; else -- only consumed RP_DATs if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) or (var_i = var_4) then if (cons_bytes_excess_i = '1') or -- excess of bytes (without FES detection) (((rx_fss_crc_fes_ok_p_i = '1') or (rx_crc_wrong_p_i = '1')) and -- upon FES detection checking of CTRL, PDU_TUPE, LGTH ((not ((cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_CTRL_BYTE) or -- CTRL byte check (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_MSG_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ1_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ2_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ1_MSG_CTRL_BYTE)or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ2_MSG_CTRL_BYTE)))or (cons_pdu_byte_i /= c_PDU_TYPE_BYTE) or -- PDU_TYPE byte check (unsigned(byte_index_i ) /= (unsigned(cons_lgth_byte_i) + 5)))) then -- LGTH byte check nfip_status_r_tler_p_o <= '1'; else nfip_status_r_tler_p_o <= '0'; end if; end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- VAR_RDY_Generation -- --------------------------------------------------------------------------------------------------- -- Synchronous process VAR_RDY_Generation: -- Memory Mode: -- Since the three memories (consumed, consumed broadcast, produced) are independent, when a -- produced var is being sent, the user can read form the consumed memories; similarly, when a -- consumed var is being received the user can read from the consumed broadcast memory. -- VAR1_RDY (for consumed vars) : signals that the user can safely read from the -- consumed memory. The signal is asserted only after the reception of a correct var_1 RP_DAT -- frame. It is de-asserted after the reception of a correct var_1 ID_DAT frame. -- VAR2_RDY (for broadcast consumed vars): signals that the user can safely read from the -- consumed broadcast memory. The signal is asserted only after the reception of a correct -- consumed broadcast var_2 RP_DAT frame. It is de-asserted after the reception of a correct -- var_2 ID_DAT frame. -- Stand-alone Mode: -- Similarly, in stand-alone mode, the DAT_I and DAT_O buses for the produced and the consumed -- bytes are independent. Stand-alone mode though does not treat the consumed broadcast variable. -- VAR1_RDY (for consumed vars) : signals that the user can safely retrieve data from -- the DAT_O bus. The signal is asserted only after the reception of a correct var_1 RP_DAT frame. -- It is de-asserted after the reception of a correct var_1 ID_DAT frame (same as in memory mode). -- VAR2_RDY (for broadcast consumed vars): stays always deasserted. -- Note: A correct consumed RP_DAT frame is signaled by the s_cons_frame_ok_p, which arrives upon -- FES detection. A correct ID_DAT frame along with the variable it contained is signaled by the -- var_i. The signal var_i gets its value (var_1, var_2, var_rst) after the reception of a correct -- ID_DAT and of a correct RP_DAT FSS; var_i retains its value until the FES detection (or the -- detection of an excess of bytes) of the RP_DAT frame. An example follows: -- frames : ___[ID_DAT,var_1]__[......RP_DAT......]______________[ID_DAT,var_1]___[.....RP_DAT.. -- cons_frame_ok_p : ______________________________________|-|___________________________________________ -- var_i : var_whatever > < var_1 > < var_whatever > < var_1 -- VAR1_RDY : ______________________________________|--------------------------------|____________ VAR_RDY_Generation: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then var1_rdy_o <= '0'; var2_rdy_o <= '0'; else -- VAR1_RDY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- if (var_i = var_1) and (s_cons_frame_ok_p = '1') then -- only if the received var_1 RP_DAT frame is correct var1_rdy_o <= '1'; -- the nanoFIP signals the user to retreive data -- note: the signal var1_rdy_o remains asserted -- until the beginning of a new var_1 elsif (var_i = var_1) then var1_rdy_o <= '0'; -- while consuming a var_1, VAR1_RDY is '0' end if; -- VAR2_RDY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- if (var_i = var_2) and (s_cons_frame_ok_p = '1') and (slone_i = '0') then -- only in memory mode and if the received var_2 var2_rdy_o <= '1'; -- RP_DAT is correct the nanoFIP signals the user -- to retreive data -- note: the signal var2_rdy_o remains asserted -- until the beginning of a new var_2 elsif (var_i = var_2) then var2_rdy_o <= '0'; -- while consuming a var_2, VAR2_RDY is '0' end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- var_rst: Reset Signals Generation -- --------------------------------------------------------------------------------------------------- -- Generation of the signals rst_nfip_and_fd : signals that the 1st byte of a consumed -- var_rst contains the station address -- and assert_rston : signals that the 2nd byte of a consumed -- var_rst contains the station address Cons_Reset_Signals: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_rst_nfip_and_fd <= '0'; s_assert_rston <= '0'; else if var_i = var_rst then if (byte_index_i = c_1st_DATA_BYTE_INDEX) and (cons_var_rst_byte_1_i = subs_i) then s_rst_nfip_and_fd <= '1'; -- rst_nFIP_and_FD_o stays asserted until end if; -- the end of the var_rst RP_DAT frame if (byte_index_i = c_2nd_DATA_BYTE_INDEX) and (cons_var_rst_byte_2_i = subs_i) then s_assert_rston <= '1'; -- assert_RSTON_o stays asserted until end if; -- the end of the var_rst RP_DAT frame else s_rst_nfip_and_fd <= '0'; s_assert_rston <= '0'; end if; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- rst_nfip_and_fd_p_o <= '1' when s_rst_nfip_and_fd = '1' and s_cons_frame_ok_p = '1' else '0'; assert_rston_p_o <= '1' when s_assert_rston = '1' and s_cons_frame_ok_p = '1' else '0'; --------------------------------------------------------------------------------------------------- -- var_4: JTAG_contoller startup signal -- --------------------------------------------------------------------------------------------------- -- Generation of the signal jc_start_p_o that is a 1 uclk-long pulse after the reception of a -- valid JTAG consumed RP_DAT frame (var_4). The pulse triggers the startup of the wf_jtag_controller -- state machine. jc_start_p_generation: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then jc_start_p_o <= '0'; else if (var_i = var_4) and (s_cons_frame_ok_p = '1') then jc_start_p_o <= '1'; else jc_start_p_o <= '0'; end if; end if; end if; end process; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

4ed6b51e0ed781dc73b3a101a9eb2b3b

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sim_1/tb_env_pkg.m.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block uS9Fi4wEl+hlOoAxATWz7JOEkR0NrTOAPXB71RDz/0sJ9oBkdyJcZqzmiJBSpJVLGXrHypKErbng NIq2yEIKicsHE2U2q0TwmOX5SeBUf5ATfJiLQmZtyrgyJ/TKwJ5Nrg3HL+15E0oFzqZEKRQD0RV0 gUht+SMMiNU2xM6RPT7pKCsVb5W4nxZuUNAOyuABEDGRH8YW/kscyF5trBuA48XfiXtVpzBwqK6v PeJ+bU10he4Sno6k9Dn4FGHEKjKtWs1EQPCyJM25dDSrh8kM7MRJepMfF7YseaGlTZntu/uKxJDR ZL3LeAxQZMrU6BodVmaZalC+X5WBYD/UwSiWkQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19360) `protect data_block JctJrCQKbBQUufCK6XJX4eip1KZ+VeEW0nMlgZLGHJTHke2W3Niai7w7l3VHE6WICMh4hbNoPbW/ DYubtJOhPPDyu1WYcjojm3WR/o1DydHyJLuQ/G4vIhJAlOiy9GKMAdbWLZ7dQPpRz/w7bNBa8+BQ 96DrTUuWkmnwifp5K+FXEjVs1vrXjk8j5HeUYUEYQWHlrsnEgBzkTY5UTeCa1PTiVe/olLwSsfNc 7u8vs+JPueYOa99iToEoOZ/TcvEsjifK+9U1Pj6JLl5gn/GGvAsjRXmNKyAbXHD/1oeZ9UVTUIcM L38Iv4x9jwi4lkWFhfcE2Qy25t0E51ivAIVarU36nurnr8Uxg9wjdaaxLD7jOqWcdzJtTF8d1xS8 ZC7CqyOWlf3tzg6HXbu707H8PI/kE0bVD9WzIJB/Yo5fChUyJDrz6mmTulel6V6ZsZYA94NiV1D2 1rvhE//QHaccJUWioknWKELqaWDfA3TZqHvTG6b+if2l6GtM+KUDLKs/smqKDDal6mNTlswUzzYB XRd/bl/255AatsEyVEYoSkaVnlom2nS9Zbv8/CMFkVa/0o70+pNga6eVTDPXDZGziR/xUAWZx2fg vxrpICMPHvhjSzF3hoGPY+RLXcaX02mP79EDJq83Nfp5LeMf+2MddyhY5M7XZsxQsfDzqf/9rsdP jBewQ6bq2ayvEqcwdBbCPAG3IaaDHlcDAsadrWEtpbNHFcKI5Kfi+Mq6B1BPzGoxUV8EpL24kE2U dGvXRQLcYSCiJGfCAb+UUFwPQRMdTodKFRGHkn7ZtYEw0jD952RBVphNOBWMaPSLjoQdtvENf+wI 5w8ewYNiPxb5S2Arqrv1aIoreEV3ouz8LdGbXeqBUA57Ej6BG7gPvk++4RzmAcGE2MG8xeUKl0qy MDok8VbJ2HpTB4SBCI6HrHEo869KHPvuz7kPmz8mkBPcxuxmofl+lvmBlUnRgLHbnFUGOf/VBsPK Gb0acMSiphDk/tE4SGwAJ5Nv3PuEX+BTSD/fJRQX08CVeeXuYjDhsQfGwm+N2YzSXqswC75oJvQ4 A7I7vzLmqvzjBYQOm9jtF9Q1c74Yti4Y1bddEmwg8TQxBfbmDUjwLmDz74EmKWuUE7Qz79msTH47 izcXIyntWavLwEO26yblCQuwnB8guX19puPx3Ob010uqnVibF7M0Ew6MJntUdN/8D7yNshbC0G5p vSAEkD9DJUPCWRAoRS0Jae0VEtMB1L9zmlRUouPJ82wOHBLuPEWO9GDVV8GO7jxG7yaOcK8cnVB/ bAWMlC0r9ADXvmuVMksqjKp8PX6QHO0tOIeVh5OF5UhQcyrZbwyfGXz4Xi+tAEcxNV5gQ/ZbfDqK GXuxa8UzaFN1s7wyJDraZhz8nDoWhgv+0ueyuiMWOc1F6mvJpLislmyKLv9MpDgtg7if8fgmZ3A/ 4U9C+ozf+pdMlFFHUTTANxrFrNQXilr5rXSQxiT1hr5SIAM4BxdPR1y8ZjsgT2613xtpPXi8FrHa Vgwt+o0obBlRBZ+/4D+LXlM1bPaUiDOGeYeibgvMUgBjAHH1nyS4IXC/h+DuZXS2VVt+RK8ztD7A WVwNV6+YmGIu4Rej1DO4/wAMJD5p3w1YevnNj+4boibh3TdfiTkH9BBILr+yWXV0o5MhV9cxqjRh XJnmEZisTJZjZ4DSV5y5rB9YZsEY0R2fx0lKjAvTZinYjrnZGCQuNxzgL0qLqQBdrvPigi7wRVdf TibmXV/OF/jRzYO+kkcAU76j6GOD6YCP+nyuwZ1b5r85YmWBiGflJfd+mSIu9FcOO/sxHkcUtaRp eBsPD6Pe1AtimO+4VWeOv41shrwUZzdyxsKL9UmeGthXyflpP+kxdqhRwEGwzrbc4Ce3lmRpH84i Mz3YhwMCRxr63ihY4hcxw0OVhfShPzslUy1vH4SClXrrUC0/WMbw3ETvIWTDxcy2E3FKxU0LOsja /2FexjjY0EiHo5z8PzMirRKSeiBRSTD/qt9UUq88KrnmIHg4gwDowyG1esSRuSPMPCE2nz223coR ayF2McCF5LjG/Jthj2chLBpRdotsDYDYXXozTSCcYFMTDhOIv0Rp/hQ7nyV2BKb9nJxcox19IPoU y7u19SmH42Sij/Q9+xyW2wG2pnRvctHb6wqfe7ZWRKwjTt0SpEDEbbfzYWJ88475iKXiWDF7qpRz BFs7xZsX94eJgnE44LYRkbRNHxJSje/s2ZJ6sqoOHCHqFL7Dw4WxQZB2YTuFQo5WxgdAmqPKwd2G fHNw8V+akuS0KyGZAiuPEkjFtSLxVziOGj6SfGD3p7r2bwGt1sq2lnp9HR4i1dVTYvihR8tI2/BY Riwslx8+dRjXYbLBols0AxGnlx5Hv5lucKY6ohKh7TLDXeE0Quw1QZ1hc4MOXb/q8fRrnzDp03WH GKQ7paAniwWqE/vkGB7TXDyfL+RX3DnNzYNgmudvbJGEGvLkUegmYjwyaPAlNfBg3sHIhCqSuNbM +GxtTJ4nPZUKCCuwpCg0so7jQoVhZaGgbVJNtEKHCzZrDDEQ+Wcm/u979UvRLHLeF6/v28hfF3Bx QZkoITmmn83+32W/zsGhxmj3FDzK7/noiA9j62NWAS9nB3DNjocLPnIKltG13vj51dOIv8ZJyNp5 vswVXOyqw5SINkn9MDEFVvv0ZwDAF3h4zB9GGk5GJnk29qpHPwpfjdW/rRffTBMSmHgosZ6cm9Lv 3M4nvhH4xQ6iQqt7a3LmXs9BGHvQWQD9BEjCRvOwJD7rJO02mw391k14qGqvvnBslnrXqGQCHARh SOlzp4Swt+jis5i1fhIBCpu+4LwU9ePxT+/g+hVbENmM33iLQ0/7yoVyWEgSZ4D2s6z3cXQ/wYUF NH0koPd8fl5x4uNEudfRt0BaEtaIZZlqBK/t/7qYa/LXK2jdtVfw/uRR3icL1bhcEQU5Smb2V756 kQJ8Vo+Lg3TTOm4RL2Nxa1qaU6Fypq4zOUZs+LcEJhpMVxoZuVf5W1OPWUlIbq+AmN3acC91aUUB mGq7G5Uma4vcidNv6Vt6B7RsVW94piWOazhXKQls8UYUM1fNaxG9zzOG8p+7XcqixzFJudheybeY v+Qfzbxzb/nnCpFExDfA+l69V6K/uG95gbQGQAc5//Rqr/nKqYvlSRJPbBMoNfiwYuAeknNW3Rif 825b7MJYj7hIDQKx0Ag2kAfXCrIZTfGubZctIpiYeaLTYYasTgI/vHEPQCMTL4W2O06nbdM5uPmD LlPQwNt+RFYjextlc2uGIMp/7uOzcuxdSGWZw2gibPyEVQxnK74NyWvmhWRRZZ0/5Ejf7WsWebaa DPLUQD9LomWYt6qalhXgnCJtMRWfvQTPpBptxBhDrSRlP4rM9JNuyGTjF5UU9/XyCyfb6iDpwsbT G9oRKULvTjd48IP9IlZ25iJJZulwSDIU2o5lOKNwMEEGJhcy5bFQKIHqBqAO01bqLZWOIZH7wJ83 iM/RVGB/zKNlmxG25f/n5QNrSu/mu8VaqNZwup23afiJzLMBd/XMj33gxlHPAApqfKxbHduZThHx Rbzvn5bvJp7h19aA+ZeeZgO+rSOyTC8CgTHcmvzNMYS1hBZCuWDjqDpU9XfoPEG4Jq7Y71YAgTTg CtSktTXRYtp6z+OpqeWu0ofER65OMhBSHtbNKV5ogknJnEZaB3ULfw1U28VZWZwyE1Xnugarm+Xd 3CkErFeWlnUlNHJgaaQsARFz9EQ9KPdRzY6Mqrf7DNwCHbSpxq+JbCW3PRPlj9VWqg9IipHcY1wW IHPDMkyuMqfAbLIXGQ+l6Lm2w+oQlPYzR2wbyVCZcS3XepXXRTg0/tbFIvxfRaWaIoibJRUMFjqD TFHcKi1LG46+ptIEQjQg+cZTXYXaKwElxSBjkL5x+uqNAYIzZvXxz7xiBI/5iRvM/KAjAQIr+/sa QrQsnWTd/TxNYSVTjpXsG1vYstoKoJsT3KEfGfIHttysR6u2f1VJbGxfCILiww0AUn3RwF4d2dJ+ +vEeqXsaJVWuXIy1krSePi8e9eouh2fqCK91OCnGcc3mzxedDFVwDZLbBMcUuOIC4vOtSYVIDqfj qVUgukEM6FTlZIR5bOyIxyGlVuFrWW90prWK7Lefe28eiFGv/cWb7hfulXHOyZA29T3/aa68bR5F 6hEHWzRHU5jH94J/BLZH+xEzztOvDGOOdfTI7564lADAlSWU8AqvudSnEyvhTVTVPtEaYTnBvf38 4hJpAZ8Su4H0XouVBrNQwCAGZ+1s4P0DNasTYqDUFXvnANG4CF8iKn5t/iXXI1aA4ckICe+WtSPw 4y2cJF0GfV54+sMGwQkuldAH5kvJagFmqXJZO41M3TMmWFHOldbrbMxgnd36k48/xEtGRtFC4/Fe nyNJ6qh95w1qgS92+Hziktf0tDZAgF+InZtS11dsBiXPtjYjGH2yO8G+loVVtaJD26yODeLg9pxM jMGrdZW9AMk0IacJiksdd1cW/E7NY5Lroh9LLDxitYzl5A1JRxOnZBO59sw+ACyF9Y1Qhw3QNJfA rKjY9A85vpKm4+Fyzaj0cM0tjflM3wxNeNYrW201BjufXAInxq7B8mw872QybWTVr/1aGeGLQ1Cr cKV4aa25i3FrgVEJFoQIEi3yS2qxMIRGSfcLmPYUj/0C47d2afaPYuMwrGMXg3+ac3H6Ffp6RUL5 EAl2lwbz5+e9Rqu83sCcu1Z94Km3QvypBZ5v0knGPSoCO71eFr0N7Auli5JY9geBO5ChwuwXafqG kUEPC9vIqKmQfrBAuUI3cJ2VP5SbsUgdz9rQMCMKW8n+R9et9RIOjy3/jRtOQ+Dm9zJ8P9wpFU8h s7UC6H2kF8ZGO1pBJ9uOW949Ih9VPr3bytAUlI/nzQnlLZd28X2i4XUkCaYH+PHXmDkhkVX7RykE Yke8oGXRr9SRX6ak7zu0QcVafSBuCgWK/LkyeqY9LbY6RBn6IYnaukbBM78/egFixqqcd138KMpg r7gERyRLTp7oQizTKqxwoyCTCw3TS2oomrKzxT8DbpWXT6Rx44PgHY6eRC3OQr3rg5mztl0rHGiz /A4pHYWtGLJYOdYaeb1s824SK5k3mf20jplP6kOKDZqHi7mdMu2iPuLjevQbhojv+ud0Fu3NoiLv YUhnx+eGS6T1GXfu7ANS4+Bgk37mGoDLu+XDats4FrwciZe0bba2pvxPfp/+38RY+mGQmgOkOtuF pYSn1oFbPS2I8S6yiXYdALslluKMrWPivHoZKWDnz0hsks2A7xwJjl+C8d3fvLf3/nPYJQYcbS6h eATLKPodT1XN7u4gagORFRBVt2Pz7NIm6TWOgszynCxT4VT0ZvYcPaosS7aI5k4XZpR6oZAkeEUt Uu4PnjZN+MrKuPh940NcCTNa5Bb1YTsx/uISbCtILWqObBBuobCBq39RS7aALnvk+UPqEBKyr+w7 GaNzqmIAnlu4poR9fZrz/9ryMBZWkyW3o2MRI1hamOFObGs4emAq0OFCGW0ja6JyrZXTc/wD1g6J CyGeTpyfQUOhm2aourMUREu+7dzNbwiaJRv92eZm7Xg/VWx68XhskKZvCUxErFhvMW0i6ZJ74tCV pjprr4s4pD3nTkk7WZERFW411npL2OF+xqgF/+6AAA/Ews6n6YdEkcY6T7Wi97jpFRV+EaUCb/Ef Ae6fk8aRSDBo6Hqd4X/A2w44qsBeRkFGMWn9ned1DLHMkTrCtGazbM0vFmIgNX4XhTR3BOQsAZbe IN1W62OLbg9sslCpHNEDfUH0sNOJi44s3HgDDwuQVYjQ9Aqc2iPI+ZB0ZybB1B6qj1+f9+ua9ULM 9JOOFmuX9vuJO36lrj8DgFI0gou71PJ0d83mkJvHHztrXeF7M8jZwy4WgvNCYEcMU050Ymk117I5 TSrpaAadHTVPDJJgPrYXEA0O9C8trUYl1zh43LLExa1QlAa45Cnr2ydJ7IStDS1bBAI/7Wo/VrfJ /XiZlf1RkuGNHeGhGfNtoH1KMhnsgHgj1McLni3REXI71TKmtWTMRNvaxHAQnrZs2Dj27Bb3OlDe 46y1cn5C+1q7fxqBaWM8wH2Va1XB6i+YVseWPOy3NjYrufSz1V+B0CJ9b84H1sRafA6xpW3TEt6N yuTlFXCSnfTRzhD22Cw+iTrcBDxnGaGcF87ECpufM1gjEzLSZPQGkD9FLf618vUnv4ALsMMI5hkb bDNFf729WoFJq4sJMSsPQ4df24JFPKS+UxdNIf3DmbAHWZVjOkO0IXu178QxQOUwKPIP67fOD6u1 dI6txc7TCvYmF3arYq5EYW8yfgVZvkYFDIcQaVxzds6Axer9cC8xBfzlBSmV9eLqtTDCUGY9stZS 4UJ+t9jbqUeSPY90voh2/7patOLrjDwG84G7dIUOnZyDbuvLhezkOZEifZ1gNn/f1bxMI8Xb1wEO O9eBgwTSs+6YntUQLIICz7A1Nlp5xDcSKKx5+6z1c21jM3+zmpOb+67/44ofInDyiaVSqscrXtXo 7SagdjbZMngDP4Q6/3+irY9pSdgaL+8hxiQ0Zia8aIvoLbScFALSBY9l9MAP61LFFc3QXMq+G76u avIhfB6x24ibTY8Kp2Nr/e9y5KyN/R/HsoEpaxHAQaa+oDIaMGm8Ab1aMNG8vox1x3CY2Cvy/M6n D/m8jOCOBWp8j94iZAMddby9FMXuvEcL0Gr573xwxeoDXMM3+7s7N088pT5S6faitOV5PCaP3w/5 QwsWTCXJVy6JKIapg5WYxgGWGN9Qej6wu2xa92G2stI2cGSlTM+QnPj0QWttU8zsh7FmzLOUykc5 JV0JyZZTFzQv+Cyp/LsUd7mBown12B8NH933jhR2uJ2g3F15kZFHaN+KbwnuYF3kjcOrxProKzPB T7qGLH5B9GkfUPF3MQN/N5LdLgLUmwKtgPamUd+E5uYcK+GuU/2u6VPv+RSe/UWbGT5gUxh7Kgmu bCCvPZOaICy9ugvbbkm9nNmD3F+Vsv9aP9qbnCpwmBjjtxJnmkb9czBZ6oK/HM2leteYRKM2mcXw 3fPEEMgY2f7iA81hmEOYefgRXZBcqPfFI7Ao5WAfAJQlXg2KrbCoByP5qkZctPd3RGru68fW4TuD /40rwBZC4YcNDhC6MrvQE885Z3/oPAmcrUOwtNh2h5fCJqRMdQ9IOCiUhyfmkKB5jH81t7M09RC5 TX5HGzCawsNXxhkv8imy8u6mYg+0TL/sWs/2JF2ECukfwBBWrKJ5/uxFPNR+WK4WUd5xlN/VKoP0 sYDI0z4wb1bgeziewDzyeAjPTY8e9/rhQJMfHKj2/n2KfxOmJ1UuItQ+EEYNiqEB9ukwk0pxRtRL Z4nHUW4qwXpeEsDz7C19Hz7zxXZ3ruU/HPHopVjXwq9EomrohwPYfd7Nmd9kiImLWguBn1D3ln5Z MFpbpqDYoLK8LzUKmFkk3hJ8YLW5t50mXSASMBRbZxansWylv34RaWO1V/SKRCjdDLQkAx/+f5aI 4qO+kpMY4Q7SnJTEWK+NupOWMGRe1YpemktDAxtqRRE65tkzDTSEdCNffLhDtbbxXJc7S6oIl3zu poiMbs6eLzziCC+uxXusl2E63pUu9UJTcPxrT2MyhUjLAKeChCvfWyVgoGibticl+YnMpjaJaYCf 08TcSVpDg7QZKXlQL9wiVraX38JEzIskJSxrcBL2NMsspcuODZqbJ+pY0774gWUqc07IrP44MK7j QkeXoo3bC4BWuZWIWR7yWGkpAlUL/EXoOIOvn/Hg6NuF27Lt4pNrO6LHiFsXdBQjdt4051UZm9yq ptT1yPZelQoPUONP9TN6CkBk4UUPnE29+JJSZItw1xx1r6VtAiC5MOjaRJ5M8+X7DIizzq+Rkihh kL17HH58enzOW9eiKw7RxYydzZ8TPGBlOXVBg8rJE51/5bvZ65cOr7jhXi0y6b4em2+o8JW5HdZh WSwjIgoBImRnn7NDoE+CitheWMC1AW6VI7QquEnrEq9EpFNwkpwworGH3XM6NvGS3sWniyfdG0Pj iNV3pFTNfBo5jH87atyYhSHrhpvL7WRN2k6mkgFHT2cua437O9efkCjwa6sizMsYozQkM8J3SkeD 4FAd75SHzhOf9juLbEn4jPBvaWtD/DVWD77BfXjvgUo8dMqoPkdCBPQm2adiWkuSku+MpJ4EGQDk ogVwcbRu3ENNM9clkmErC8oh98OZJ1hxZZI/SzjQGhkZ+D7aYjus1tufvwX7F5JFqi1aMYFBXF8S nM3VJtuQvsvz9jfNTUYUmHj3C2gsjoXwowFtcWPejJCteZ+a89mxMBclLSoKy1gOys80ZqraOAsj vt0noBVyvkWXy5Qdu16Z9aaPcyD7bdvCtJ6Wb1GNpZw1KfdRaeQwRfTid0L0KS482MWKVLE0jI7V OsVTsVo+B4cL5suOLMwRxMz/W7XO1PWeIpAbxidbVApwwEZyraIIDlyGpAYV8Pb1oFQSWbAhEJz3 /J6bk3K0z0EmgiXW7OXhqnk+DroBrwHaqJtUrxB3QA6jpP3E0+e1y4w3dp7iAIaxtmiRR3rzOa+5 CVDjrRWF4KGGahACtMPS748DiHMg7fnW3znmJYiKsuEQWwvnq4mB9R30AcJQnfZTFd0vPwpbMrWV erQq6rXsrPT/tLvaf12Sy3ubxPyFTjDQc0Bi1eOho1vCHPWDs/UC5xoC+cwSLQ2ASc3B1ZCJaslk OIHGaSMIj7Vido34oWtNITNYbHbbLo19KVK0YklUJRcJuIiT5KWM2olFT41Wisc9dNd3f4YFvUac DUEqkR7Tn1z1uYndB6R0eU6QftWbD+H//JZgTAjLtj2OdjAiZCswck/Cl2viYE0hbZMBnJ8WMd0I F7NGxcmTfoSozDIPD9t3iTjn5LZsXNrkD4tXAcoLXAFdgkPLrtehwhCVXAjZaKgogPUQE6Qf+Mih D7cruH/ry/dfb/C3oBt7ag7O49KFTOyzHFguJZYGyXlCD4DS42OegRGG+rgOD9YNQ/Lpsi2Auk2V PL5ZS/pkm/uMvp4XZZLPYPhODvTDPi+jbXJGNXLFgXihG8h+xdeR9Xg4XpzbvyuSXDZXXMr2riAk fGsngMAwAYPx0Pe9f+dMmYhLYp15nNab3nI9qEWRn/+UGwYWmqhXFjO8WldScvl5W8Bd2At/AK+b can+DvOiPMurtdaud66UhSuoekRqPlTfDXQCtVuxZp2rMoNiRN3QMh81eh8h1aEHN08DteNoy9Zm g1mz3VtOhXMJGEdo1S4pM08Og45Xuv3wyt8c7DBky/4DKnCSc+ddXkPEoCfO96srCqG7P5QOvw7n rYXmeI9Xtyqrr+AeaQoKfoKB+soapcjIvF2sk1tsfoU9ok03H+t+LbGOKvE8xVDsY/gBKKudve48 XmgsVzTNqXVfloVkGeg6GSNfzFri/ADQbyZ2rdyIxKf5ygrR7RolIkfS6eaNZUjXF7c3sB5PTVYj MxmBPl1Esmt4axPUFIi9IH1EylO9s126PHFM+VW9RxIOPe+VnT2faib/wFaj6uaOdqKI74G+ABTN sutq3byyJxoikSQ09ymFzgCS/roF6A0GRf0VOA8SWrao7OfBEvPrHHojgN35izGOVg08HTVm+Fwp QE9umJdK/t4NDO1r2906PUtdqf0/IV2KcxXGdOPgwVI9iQkhX044+OPCgTbupaoGorlEI6iiuHDV BN5j6ggSlslUe0qvpMw7Fc2pxOGNfLrHc0tX9+Qju8hwFN4k99yu+Iuy7U7DI7kE8uyrz6QQWIr7 kpeYT3YnkDMvD8qaozhXdpVtmI8FVo1KnVkZ37LTOgQU/65MYFwnjrPrDDR0xPANEx5n0zjyY6Uc JotODrp2R2x0iR3+1iQ33cw8ICVqGsEVUanbhz3bFSl4uQRLOGnchY8hcKRgEgC93YPXtolYEdeg lFugnSGGfwm9Yoys/h259nTXhAVfHejT1was3cW/l65E9xLi7wVMz/s+LCc1QYOTurh8G1hKPpfU B+a9hABYZ6ZVSkAm31+kbPA5hk4ZKRJkzs81jxsALtSLO4XjpS/nSTG2j0kKxSUbykvrOCLCuWxE vEZNysL6BngKTELJxMHCMsjix+ushklfiRqbunMyVu72shu8KVC/1z3s7OHVALvOCmeHi6odZeuW i0dqdp33NdUhxKggopPzgsk/8gCmtEmNP0iWR6Mebh9alQTDhJjjrHPaQgk25eNEn4YsUkCNuuZ4 ghlP4ytVqXKUGjVI0QfeQOkSAoOz5yVpzvv0y7kPbYX6ZMzoMuvJ/coS9GR8uPWGHjfak38R3kPf otwn7MQLvO6Uu/kEafLAwhalaGsYKJUgUBg/zOr57R5trJO9UwB4jb6Ogu5RQM1PDVObjndOQGFK Ky7sKwc8qwKwj3QIX3xUulqXns8UN4KHAm4fyQhHteEnFwyy1DFrCjUvnYV2tqYk/qrnIN0Pleu2 mV9l3eLr+Dmn++4DFPUvu9uT36rwSs0MBn+paY6aLn+X7E4wHUPpRhh6ydah72Fbp7vJb4xRJq6p yaVpZp9p2Ib+kJtzbxT4D2M6BoE9235THKAWdVxkkT74piANF1VbuDZXoxNH3lN6Wa3BvEtgr18D FlJhalDQ7XK7OSsbBDYCBYwVDbWXEIyuYX/AgkvrlstXOYYROLinpkv57vO5vJSusA86QSHscgLt ac+hl+AMaaY0YuIuQ6FV5CzaB8bivzWmvVWzaiKUKTlpS5nZVDAS8o+LTMrMGMJ4z0lSgnsmj/II VXMqx+q40/S7JItdlNKaQhy3wb7u841oSH2jjRwN8GJCfApB05/hFzh1yWIUTR4qxg+LOr/aV4l3 6zGZrsaiVXLxbEANAobOT8ExT/sv5Bf6d7ATZJuqIHhTDqknnCmTte7/BwmkQkPtIKLZsg2IDhHF XqXKT0d6rHCXER95BhrniMvLBjb2w6oLUyR6rIiIW2V3A9TBOUHFg03TAAOAecJXcKLR2OP8Rd2U xxB0WLjh9N4aMMStrsZn4tKLcC9wJvk1IPU3C5E+ogHfAum1RHom0bQITv64R2lSPFKvbEL9aumu 4Bg5pCQ03xJu2UMOJ4l2yW6O9Gi2ac8WqyDPKBiyy/k+JI+cauEBWL6kmL8wZzo00HwIyK8SwYyY I+IV6ubfpGSpY+SXwvodRPAAgvipB+Cu7Eeah1JlttAeYBV7Vg0bz+9bOgMEPS6gUkcR+D4/J/Dn aUj+3IovAlUD0MInsCkN5rcrmc2SlKmXgE5kkNJrVgcnCHpZKKRgQYxYzAXzKxbH2yoL8lI7XaYD +DHFINho66s7UV8oB46vnaOT4QxHFWeZQ/XKlJC1LVaCvghMJmSuEFLPuxbc1A0hue0sCKVtyRK8 6MgomYzKKIrvAYuo/dSTTLahHS6SZcQSwaI/XgPatDdQUIu/B3rw82SDoqiRa08ZleaEHD1Zsipc /VN2/BOAjIDJtafOJKIH6Hg88LFZTm+7D4DXUkd0J92WrupotgJXqLvfmrra2fy6aO7Fa8f6IcaG QLuO2z49t7aW8urBS4eECMigf+ZHMAvxM2QQ15cDYJj1VMMvVm8IlO2KQIXGWVkronr6foH9YM40 CQ5HqB1a5muFBbIi+ubMgQfcYNIkPaXEj1WXeN9C83+wViRFefnTKlrDhW9hVndQJJlTdNs1vwRH wvK882DtcheWTpO4ZDIN2ED/mUcFDeG0fwDPyjAVpOAxy8YSlodVN7r4+2eZv1UmVFGFBjO+Sytg /UA0OUbHDpx4Kx2KSo+hn4jrbNT1ylSJA3QFN5MHM29fF/6ffDeLscwobY7uuyF01KrWf3aj1CUn OykJXRk18Ltn7iCENIAAnLPFkDagBJ1RDUos4ObvLreivgxr80S5e1U3/dO+ge0cj0X9IYGNpwkj dPLNTjGr9Eas9V9vqu1o8z1RARwyxih5+Zj0hjY1pDdkneLgGDdbG0ljSv2P4EA4+QfLA9vlLSLY H1fG3/Vj31ef37evPOpEDLTBIXog+Wh6Fzviaw82JQVSKBLLWIcQXdpXO/ANBtSUPeUhAzaZxOO+ mvbtB0EeywoyfzW33bSJO124fHz42MMcxHqcD0keax3K9QsxYrOhxHSJMQHCfZ32Je+LeGMqLr7J cwu0ZpdQVOMa/YjvQHZ3AZ5eElfYCWAxZB6UIzguvI4vtpGomXBf+l16DifxViyfRsV3pCHghWcH v9KW4qK5LhY18L1n3PvamXs5C2YAzm3R5l490HLXSV0rPvrzdsnTA4GvtzIQFCCXsris+vbz0fy9 PyuN7iu0pmfOOrpjc3DIySnAqKbDPKxsopqmBNGifFd999ZMkh1wkYNhs3m1IlK1g9Dfas5JNc/M //ycQ1fGtrXL/Co0wkdhoFD6CXG0ZEqT0qNGv+7h8Nndw1niGsTp+5pExz/LmAEEM+iJl4oXHSr2 UWGBB+LKvURi39Im9+GfAEOaI4WLfyjF67Yeut/CajdFNRYPNGbD73rIu/nhhuSuMxE9yrC1aV96 6WflphKfOweWi9crwULURc1GFlixmxsoO16tOJHe5O+OcWa0u3WRKOKGotjBSddoCCweGWYMUFZE s7k19+DIqDnYsiIxwih2Qd8Kqp+HdkhqFsOuCg8BWCR7qclzhXPs9ERhnzFIndM6ZV6f95fz6d3a 9ZTVQirbWb6C/sAcYWff5l6r5CPILWv2WUuvYajMLkMBgDguwV7CLPRbkysR1IlGq6mttDSEX/dx ERO/MIHn+fTmjz4ltOnFEcY8D9BPIMxtdUkLnqhWfQiVGCf1cTeK6x3uxk/rAMD3e6lJu3iSTSXY uzbor9U8Za1GxKASCqlfBpORUMSW6rMRY2N1f8ZnfnLx/ZV6C8IdFLC+L4JY7cAPRAJ/QpfhsmCU xifKY8unYIdLh8yomNmJSwOqEaP2mBfi++2TmPB1tJa6mCwahpT2Fcup5sD0RhFuO/tk2pSi/X7Z qDJJRZPHiYPdCTWOOkBXepatNQ+nEdV/dyw6nMMiwZ48qXVEhFD+YngUZpYGYNaXyiAVOeAm9ekA MfVOd1k5YPgc4jB8nRj0qru1lweBA5pn5G65of3QcGjeH+KCs/OXwfeD6pD20IQFfNOXUSIJtDlD XkKIkWZ7hnoUqKv1LwBO69wmmppUZMGW8gxrNQ5Fb2ewb7z6hSMhEXSurUtzbR87fG3Cz7y/MmNa tZLjGUL6X/zBqCy7vnCEhJ+19EjsA2JG0DdzZ/0JbMp/FDXHJMmkLkYbcN4OsWDBHjikSW2Paxxs uwOsYstEYCPkwItpQvd/0ZPWwWuXSyisD9ByhuBGsXXVXyasa036Nzh4CjEGlPVMTiQakXOEgJDb BZzK6dCJuYHckuJhm2DF1/awK+wdCFxvQE4An/bQmDEgXMGRdJU8Q6JFR4AsEMvgLj3Wev4iff+m M7kUqLJs09UtfIO0pxDQcCBKkosVj1zR0Bcw3mnwoBh+mJSMJVYZ6YmCpXG/AfBs3w/c05M/1EOt 9oSa65dLJoaLzJI1GoeM18JxCtu6C1QhXesAtJcpEx+OuJOPuzBJmXrc/PgwmEv6Kl+2jzb6Hgcz O7Ylo5kQwuqApEaENd8u7ntds+5yJ4b7BmUN+r1GXR4jmKzkchpSC/bn62QzF/eh+jyL0zZXdSPF pMtLsNvXWElgyLxdoCk4BCcd26Q1dMN4FK3rUF1KR5yutXq/Kuhxre3WaxLwiymHyJtYSMcI19MO MkJ6soMbEg5Z2nooGvynKNGrNCgdEVcw7MGNnPNIBk9La3kAeqyswzDGqSLhWtw8KIJrtK5bm/Ee QYWoLyex2F0ygq+uGfJUZbgqJQhOeMav1dBek6opFsAjNFLVeuRGzAO4SzXTku7/TjlnXELBG2uL VSsqD4JCQzwG+MjlaHUd9rsxk9klOKNOgd7EFwIP/ihR0xQYQ5kt1CFxj7vtz95KXYzAlsMoLOdi Nj63hkAfVIZm4GPDFjoGA2466qWE8njZPJCHK3OizR9VuCKy3u76K1prHGDaS9spHqNavYMu5PJQ VmTPhA2eW/rha2WWTVXbu3KMw4fOtdAWtJrYeGmWMRK3mlbk1NgQF2CesmQBfp6Nx6c1xCNTUm/F mQHyOHOiRymBimqbcbT5w4qS0xxs/rW7Tqw3tdMQ+aa2/C2sSUQfq+A/0dWnsqc2wuKG+y48fffr L/h8vSu4EZ9K+whERFnfP+c5olo0vF7WQclZtSwOFynezK56xxQR7B6WoloZUX2SsQ3JnDDI3m7p E1lw8zOqKnifIPwn0C/ME96AcwR/hQBP1cnfGRCZf/9v1JQOJmnB2QcQCdA9Ttt/rXwW/i4hFOwG ZfMLx+7roQqaq0il7b8c+hsAObURZ2kns5FKfJpET45ux+KqH6U6duw3oSPgKHEnFXDbLMcUoJE3 KgL0bnwpvMg2Evq4TIiF3uD8Bmywq+bOr9aTSPRSePKcgFmEz67Clr1trHnxzpAmg1f9vmOxZdN0 c+FEXVeyfO+H694u+6/P03Ht5iG4uSL6mKJjfJxlFXzogWQSqKAradJIJU3+ydEmqvUrRfjJdktQ kHgJU4Bxg/i7GQRzby6aCiPz/tqWij21W/Lm8IoOf+A1MKpcPZEWtvf22z6iz3WREL7q4v/3CQSu 2uKwyYlRhxrfLtGuucqk6aOS+LF5ZEzHNxbOWyE1ZpxYUEStDR6ZuokkmFay+kA3qgiTEXx6dqxo CKXccIORW3tot/r+G2JofBGPhRDo2jWFg8eNjoXpmV8pXmerpv6v2OLQSJQb/3+IzpwgoZJQPo2G IhybuYve6bb20ViWslip9OdpIuORKz+turPkWZZ64RmxCaCpXmawUVG/rbMrz2rWPQl4nboyoQ6H V4FkxP2CrKQMNtc/QQRG76NeBPq9a9y2/esq/GZwizNdrjJQFuCxsTCu4P8bSOWauEQyBTqhPlmc 1SYqyGF+SyyAW7vxDx3Y07pOqMaGlWU55LWpVdgPon8cmD0MzlcISQVhLlFU8PaP0vWyZl+t+Ywv GtMBytXliR05/nQv7sKNr5MEgRgMHDU/0yzE+2K7NYMex3IOE4qiBkCSuGm/OLGKnRJPXbbUKFFm 1JBBx+4QO/IT6jiSB5dxt9EGPlz517/5PvSPNCGwfdjykpmXPseEpslH0Qbby7wkkr5/aH9m/gOp c+PWOOo//3TKW87iVa4eDpmLzRtDMiNkhOE2ZA8vtiUG/VUDVEZMWDCRPtEPGq9u2XnjpvKncGpE dJgzwDbKZBrrHk0blFB7ps9WwM2vx9sBITpiRN1Lgqzi21jWoCaNwapqFVqAcsa/ytfsPWwrFhC8 B5sudu6yQQ9mUDQvi3/Z45sYZWfAi1Z1c8ARV6nDFpyS6Z6tReO81iVe1e/XebyLPO21GQtHgCbA 6OnZ+kvxH0sM5iSqb2OFqEUWKUIIMLQ/ygVFzq5Fun6sMO6aJAlkKggpHiu3FjtBYb0KFRfPhMw0 r+jJcdXXB4kEZ/QRjnvEVvaaUWGYBlBP+FtnjN08QG6o8tZwb8+kgztE6ADgSAmUYBuDdliYw6vA N6ANZ9wp8q3AfVb8U9UgpY99/IcAOL0yxleCE2q1+10wYT2+vqsip3/Gn75pQxsLA/yqEfBxzD50 EjClHKYgNvb2CKO+wJlMLbuTOBVLvSGhJKNYevX4q/LnL/cYKIwXbX3SW097W+0ffR2maf+mbxpT s9NC+fEkV2HaUvZb+4ALwQ+EoOmL7r+6+10jWU27J391XoxXHITaJJB6bIcctY+Yc3kBR1Uplu0X MXvkR75yPI0ElE8cekq+sf6e9Jn3CQxcAEDVMPjiaMhER0SOLg9te3ZYDKhvrfhmXUUm4+3qR1qm ZdsnDCMfu/xIL2WEZ3aanwM5UlseNzBB+sfhZPqlijqTRsLreB6jO4EFss8wCPAzdvASevKK7yug SZ4qoF72GzE+gO24JGX+LKzqgTRWKHRMZ2wI8rK3amopt5+Ja9GnF2q/nVIM6VgtUXjb/Sr9ZhQx hZZbWmffPd5CQfM7SNPi2co1FsGD9650noAq3qc4curnPBDEjKksF7Rf7nfzppm6mb4XivLXLvcC h5RegGyX1r/OBHitkFIY5gidSuy4SfuA3rv1wSmEYex5LIi/uu1EJJsD3Q+D4LtrZxQzrpQWpvsc YXaua//nFvF1AXVRf4UtXQcW30eOntNhdsjyqFOGzkIYXYsOlONauQGV8zA4CDWx07P4e5BibRnj JbHEOOH9u0luzA0bn1gD6s+sKZ3REb9oeYPQrE2KdurNNqV/SfGPsTJsHz+lhbY8YG25P6hflEGH dK2yxGHEr4d6KMr20Flf8IW2MDxPJ55y9SDr6pt3Q3yVrxzKfJwwx3W5Vu79SvzfRK2D4ohHeueS C+YVnhKXk4vNBMd2BZ+WG9V5g5wglYlfjD9wR/Yut46GFG0z68LQM4jQjHxw2raa/ZALmua20xI6 z/JD18u58TOQfgFdh01F6W5AWUtS2OHyUF74hiid8xmC6TfivpUtowa8BEp6Oqn8ecyHrBCGTfk1 Uc8mW7RRNIXxsB5iSoZy25qpD3lXYKoNcgAQtnbwPQMa3X86Ptq96HvxQzr97SeBIJWRk9Qq8j1S 1wCBXsFKLp7OzVzNCuMmKecw4o9hlLS2DJ6nWoJjpEde18GpuU7MkXpGydjz+uAaqAK1ypZ1r0xt skwkjqHdVTdgMQNz6qJftmYvQa0PHYwXzBwgdyr6Rt6oN57vFqp+LaqXDuqlrZ5Qb2aaAg+trbvJ KyKi7VrzL1B48dpY9rP8yNRlYuy068tS5Vaw5f5Csuzl5siMczY0s8YkVEMhkFtqawJw/VQn5ZhD kXQEkf75/5o6XLkLWydJSDk+GyTxqcL+OVPGKtpKA6mTxsrXXzQhJwiwe6zB1NKYVsw3cNHQVE/M p+MrNowxmB+1jlnVZ2oHjteZDbSOdaP+qDwQmB4hQmOxNqquMH2LnaZ4iDf/bUc48KjPAQrEFrS0 sAcpBW8d1aCTykBO79ZWeu4wKlKQzOPI4aazvDlowjKpzaw7cHmUtlBFfx3nWxUhKkd0rJhe0EWP 74hxxOFz7D5HKi93PNZucaP3K23U3l7IoJYWzzj+Ffoc8beprkH1DfJUtif501kaf4NfraY9493p s87D2/ahYLgu61hjebBv612bGSuU8AM+dYR8uXCOBUXEs5Zs5XugviI5wUMDHFxuq9PLAXKsMa23 JWuXKNOWh2uJYkN3Yr92QG/9M2pduR7n3bMlPgO7TU9J3cUffU7glnTxVzUXsW4SCK/m6ZrPUJlb W55qN6m8wd7DQZQ4vaKb28DTJo+wL8zJoUFCKPSmLzAgaz/pJ8sILxnbe/eK/wBSapONKube2RSW 9NcOUDhAUuF4HhbOGdjKTvYdnOfklwUi+wDEl86knFgXqt/L33SJQqPLxF6ASd9DDX62AFU/XYYm wCqM8l4LrXMD4S8ApYtr8YKQHpPuSkd3JZaY7tlQHHnRuLvfK8rsmRsP9O0FhE9uGyvwVNArgRNB b+olJ5KrY/Xi/NVwH3DRjtaBs1sPMmmi9v2+o0wO79Io0fRyxlH2611riZzk6ukL0Dajj69Tdkr4 c7oLvyjTjgmGbvkoQ8h1cvnzazXifqusVrdg4xaLxvWpx9ThAN/W+pKPstpo6u052cE6Wh8ne+/f VuyrEOxNphOcij1Ri4113pX8bVS8arkMqMK0JZfr5/buM4O/6i3TiCIbU88q+6/mgEsiI+W0cXD+ fffdnK9ogOt9YC+gWilqMHb3fwEzbvQV5e3bnsLzNrSr+svXa9EVFjTjS0Jn3ZaPUEtkYl64FKc4 2rqbdt6CI3U72hdF9UZofKKJp17E0zTKMZ4NY5y6VU6LUsdCKIuNZysHsyKYyCEs8W9lo3ejyoYB wb+rFUusDveeaerZH/jBT1aSw9gZCdvAAb4vYbHp8fW519G4BrtCMP/GEaWBhrLjF4Kr9Yeo7qnT 6uUGrJivimJ+5NjXu/bRTzAYtHEFOeZub1sxEL80nPqRjIcGUnoMhJhY5bOsFXuNMNhZzfETwC13 Zrv9Qnd4pFQ5abJzEn9z8idKO6i0Jz6IfisEWcb/x4Au5tLiCoaQz+JU4bVGgBHvRrZj/d1NPpar duAZCE0uDYsj+VM58YPIRJxShN+cvOx2/jFr49SXKaqOn+hEnICeInObuE+VHmfb5gXPjGFO9ASy LWNXahwIVAyU1M9NhZCkzN6v/ujzLZXHjLor0J2u6Lb9o6wyRekswTeWMRMWqUc/Gnp4YYvjPLij 7BxH9N/6kOospbnqIbCTMP21ZI8ncpWpJ3Zkzn51eQJx9YtXQ5FqTHQW3b9VBVpKDEkiQKzcKsjz CULxExo5qV1D7Rznqdi9qmts6TlzptFKqhRqhX1+B6Tmp+o3uRaXe4ItRQlGwOGIOR5zefMAgW/U uKztvEfPiffKe2PqkyMMoIO3CwQJgv/+UJ2wb6iPmiVux8Ydkz76v7LIy4GhQz8uIgn2W7TTajrj +fm8j38n87ptytoI4F2DN06rzjnc2V6HHGExc2d+5tIqNEhcPe8oV4IiJQ8kDUNh8ixbpZ0mEnI0 6TsdiQIYphOn9gQBc3T2C7W6XOq9NlBpAgMSsdBs+RXfskNeK8kWwJh7KOtFprEMz3/ocaaG5fsl V8quhYCd3VtTQff/895LtO0qrwkjaznOUMOufaCXHOwBTO8bs+P0Rsn4vEXIsmUj4/NeOggQcbsr b+xqTApx2xP4gyLXgkHx4Obo5I/znZxgeJr31Ue181JpQ2pgf3l1UhP1C+j6mZow16ltnrnS08Xt bGzmCd8+d4Yj/zWwvWP7dkDHFMecL9l7m82iTZcF2fba0VQ+27Cd00NFeOEJ3/5rJCvMTZeDPgt4 CiwQUe2wGzFjd6RtvFDFZ79OXKvZG2kATwFLBJ9xsnCGQEIsyMR9F8BA9hpdxPV8lxk5NbCFCNSo 3WR+SS/1p+WpAubmph6OppGywNNcn63PIp6weXGEFVPCPn1/0H5jOEIMuPd+3LjU+wAD4Lu2nP2Y bjaGfwwu8vlQS97YQ2VXdsztCKRqQLsTf3k2KkO3E5MZUjskyH6UghZ8cyNYSyclNDXhs4EVbSHy XlwZQbyvmwdiKLpeCHz7y8dsfUi5mf27Og13fNVCvggXb2344rfFRoLMG6ujWzCFNpKJFb3q+N9w 8q+WODynBXkpcogSC3uih8+Te+MFctmWdCTv0lpguMHufzSR4CQi7+B+pskniAX38iblp3+ZirOa WWqdNDaDUcRwJYKfKSMoIyk7EksYSjqHcwtnebDZbeBPTv31u1AzmZRgxbKjWsqiTg4hFlks2J2I G9/ahFSTvMxpsDUcOcuCil5cpme3NkFocST1IGGsnuPJblaTrdeZ/R1em6/gnviQOzZf3ZTIfH/D 8VlNuNXLu9uAMo57SSi8kNuUjmEwHwtoj8bDGXxwGh75YwYnGX+WayP8HGjg8GnijT9KwH84qHAq OrnRVK32e5orVvDqNdc1amryMnZjCYued0fpWgDoGthMgmylTsRSqCTgbf+4kt9GImCWOK1UFTKc FcvONtNuwYLSJviFDdDXurINxMlVgJbNGjbymdYEA2HoQb98bRmrNeb+TW0iflSm2QshKJmZIIFB cCd4zI4lm1zECZAaDHKDkkFoI6USNojkSNU4dpjKR0bUfOvq5Z6ahaBSfvfqTQo1OGwiizHs9rkW GrAnv6VMa4t5HOUBOFG6bt1SMouUa5WNq+ExxgCdXSclQK+1DDQzWxO4yPomnrVy5Pu1Hkdq2nQr GEKdN/rpRJykc06oXdseJsDHJJTdxr1LIr+8/v6U/cpyfJqwJzYr1PO+iLngIezPcwTC/wCruobU VnUcOojkgp+LI/DKkpgRmS/XTqPFSxpKnnPwHX/dWt5AtlMQncQFuHIxcOWkmOqJeYnE9dFbQZF4 XrX4gWx0fk6lGr05m0JA6SyQDSWE4mzjnY667MU9VOrnfna/SYcx4Lv0KBMkWcqr41uvymrWu889 2CvtK5bhxSZFFRHaKn5sQ6TLhJ5z8ylx3rrQhHpzYy0iUowDkF+KOC74esoisvTbFi+ssXSoeslo sILEAk7WcHMa9cUp51+DrtOwYPz4olsN3Jt4Cj06v3IfyxxR05E57Kxu0HZepS8bLVrsNKSkYlaC uCNwFxdx1G2JEsnvuAX//CchLNIpYTmYmBTQj5oPTDJt2vBZ7kEGRxuUHpu5A+YxEu0wTzjl4mLm XazNBo63gpTWPcSLW6TGWb7dpCvvXEDWzJ+SOSrfiAurNBdIlOk4GB/B3gTnxrqaWho6zQxJoN0X UJFmnsndVv2zT0r7W+fCLDKmH/akFoK8wNmEV1V5lLis6NueeA8vkfWyN+X6kdFuVH2JZrvsd2fc PlnTX4UY2hXdcj6qzfaSsOOPkRVkg1PhX/t4G3Ju7+IQN5DyNauSifgK/MbBnctp7RUG9UH/rMbv Ng45Qjv2JZkViXli3exp88XxBeYkGqEpbP74WsKNbr1JUPVYdWRqwaPkCIpI45byG3OtT++P6A+A R6dPfmdfNMaNhqV7h9qKYrb/HvgL+dohI09HxNeXGKhlpbH4plfY5lkuMWLZ145spoQeCHdbOy3D ZaEFXbadLr7Aeo6995xRUlJzNvUiYgn2nBaVH6cyZOLu3yBpZqRBGXy5zp6W0GXXC4rm/anlihz4 A1c/czyLv74+OTz8fuaiCPfFMSvbmSJBdeUCQ+FXIP+lnDThN94Mg0jrR6cCDnSLDtYGUpN7Azia XCs0ZaNDoXirs2wxGKJIXYM9iQ1hLnmj4fZEk6b+Mqar19Ai60K7OQpSaBgkUpP/fYdFGECXSwGN WdEkDDNzPG88SQGyY8FHGXJZC6EfWH8fCmabEadu0Dvjsb0zATJCrIGMMhtsOfx3kKKZ08toIKcJ MDn0PTSeIoLFXcoJqFwkIEm7qbXUYUDTFIkIgr1nveMetub3saEBUh7GQw0FNwGzHHvPXEZV1AKL DZ8lPI63Nf8epoguxCy8rbVuph07jybtELgbrHvPrcvZHZXbLsODHKtmFULe3Euzsk5xhd7Nf5x3 to/xmC8h2N/Eh9tSUfMMGAOM8qPZDhQVGPToh9UVOMztshbaKXPBIfpAy46Iw2qfPfzXTA69oVXU xxF6FjaGtDPjrerx9O5gu+wQCiaIPJeqYy77VvU5Bxi8uCax8LjEqnsZyUyDp6VeK8awE4ZHVPsr LleAZymxZExex0r33chAyWb+uqpXQ/Kob4h5oTwtXv+t/GEhoqPimGTPF082s6p+sFeV/sngqCgA V3H+/WgKbQga6YwVkfFJKHtpwNr/PXrFTR09qjTlSl3/dY4yR7btv5pmomYI5uJUWGFvgjJeMUWU fbuQxK9J9gWJZDziS7UOjb9PzHiJsadjCxS0tet2jt5jZg+0o92kfmbtyY0D54FWnovTHYaa2cJc YsVb0dGMSezXgyntJm1ahJULC0J+wqgEmKTCu4NVeM/95RGnvTs1hOlRYqYKpiBQEM8nMcP3eqWZ ETdGGA24j2fA2KOtQDIj22ArQ7QdPEFCzyR/vYRkrrjUSxaH6Im2UOfFlZYKgn9jqHuqXpjMmeSk 3d18kHOiAkEYtbsD7GXs7jwnJmVrhfSZcHlB/eoUBcWZ6egH1Wg3Pcrp9bpLC0ZnMrvAbAvtm3Ma knMyYmmut6sG2lrkpyDbJvcIhIV8yTGiKpMKUVfQqkKGseW2pUEG5n8S8tkzqLdSFhJUDCcZzBLA nMijCRZHTVtqwoBUAFcHQCGBuDZc93uo0w8v6bO9+rRz6hMGHBytuq5xiccIXYkKJdHjpKlp+Nbw 4A0WEtoZWJuiaEfal+2I9ObV2K/SeKJNGzeylUlnjeM47YTfHozD12iGcaFh0oYM3wGlnf3B6CZK Hp4IZE5OheGBR/AtMw4xMBcVAq9U03S/C4NeoQUZ54eK2E71yOgPZtYnDOGjFYtkAK7pGeqHVJwP NxV/k2Efu0b3UoMMSHqRm4tt/nijCNITd6lDFSLX6DOEwmGAb8IrmTxhZqnCDMSXkLcSdhqYVWIV rvD80AOTQvnzyWCdAWpU9UmqX0XprX62sgCfrQ1O/I1X+9djvx6QK96gv2xgNx4mQAjXhEdcKPR5 MC3d9Eo58VQMKyqL8XC+buTj0Nl7pYtPoPKoPg/xfs3K+N+0lXJf4t/w+zcy4UbHoSbVCtLaOURQ RLEXwv7Y0cu99Soci7YhlPhN2HQzs1rnIeNo9ltc2d9xlF6HU7AIiV2zAGpJWlP8tkf0rMCTVtYL 46pHuyOu69kNvYKIQbLc5IGr9eyqfMAlAS284o/rIfSuR3gxA07Cvtu7Gdt2X+tFo9ulqajfk2wc N0QvtBePlskJ3WW+XhBZYt4cNtChBcZP/5UfzgsW2/pRRV0UDOs3X1P7GfYLnwghrZr44w7Z8+eX 4vigyUz069a1g6iTuSiz+LtzDqlWqe0Ra/xIpQu5bjrOJjs6kG7Zie4YOI+NCHbo94Z2TwoTphC0 lbxmd/yNNoNpIqwkysHR7ZSz/oceVjBbDQaknDL0QD9Q9+1O7vCGpRxAkRq5l3P64C37JZ9pBdej ck6XfTYkQ25/aj3AhitazQqvhs2pJRknapjuy87N+bFRMX9Q8y3IYGc2niv7oY+1j8hxxLvbq7ac B8PgOf3XRE3z+7TerD83jOymBlZ1/umQuCKWKvZ7ltNjuADx11DvCngQUfxe2Axg1VhMIzdf3cd2 JeJoDY/iy6KflsX5JJpBUm2vVPGIRt5pcPjVWmrfMwyr0ylTqKlRyPuHOBvrAAa8XV2dAMnAqqft Z+qZFK7EPu1HzJGVLbMRNJZr/w37MqHfGOSu+GegF0sE2W9Iw0Dpx25hBH5eeFB6RMXmYExEZs6q 6j1FzFZVu/eceWcclDaizuVhLVU7qrQqtaIxXCrD5dK+PZRBaipVjenQOVfhanvOFivlXnqJRyLF foFIITnhlVEOv7sGswV3gq2ld/B5UwAZ9w3MiYcGmpWZ3qlfR4L9XhkGovVtXKXJ+PdfAjXFT09m V7UHyMjggbov3ioP+aP414UBE0grB2IlYJLZjX3V/0jTG8OozWwg7TaQUqcygHjeMXo9n8s3lssv zgc2xTbmgm3A5+awUAwYz3zeSeNT3FDqIWt9BAHsDDM1pearCzG2LH17sKck2QMzWyWeeoKDxnQp 7pNRiFPKeiSNQ9xL5jWHTxdS2YY2S5pjJ+O55vbYpHr04p2I71+wkQMCtFrlQRwjJMJldIts3Bm+ 8qY6AjYO+HW+VwWXFXLYWXxbEGOnct+4vVDD6LavOb36+DhgGQwaOXCI9eHNqI35DZ9Ig3uadddP SUxdfgx/V23CqGweAkK/J5dafx4+x0X3iBNyQpXRATArnIJN3Ase+gKW8lN2Udo7GaVk4SbXLpBT Xu/o5iAgQ8hCe3WQluFPvMGCGnG4W4NKkusyElPWQpoF25hc4oY19a6OoQ/0HAXI1Rg0OJ0dYQuB Co0y0Id4VBxrEfcLXrpwqvnPYyZOKFkLfmBXthCs2zYOMwek5EtmfvhHGDg/MVupxStwhJoSb6hX b8Fn8u0kzrIYdmKlD7fpG3YXWrml1qK0R6fMyt7Ln04g1eT2CjLZ65CTBin7DWEHoZn7SIL0TvNL ML3QgFYyIgNMRdeZdY7BowOHi4sPznOMdGsj9morOYMcPUqRYHUmcw9fUFfYgfwOZXq+fiBqaB/h mfcS8jEFqOFQbImh3VrlloE7cpqJ1ky6e757BfmPUxOvsb971c3eVJwT8qGkdl7tFewXMRxMDw40 gHJ0V+uvU5gJGjZ62HqJw9cZli+IDiTStwF4WHxCTvi0HYVC5XY0xhQhTsT+qaavI+eRqHR4hte1 yyDtA93xlDaCGE8qWQxgHqvL1U8U/Tw6hvtRyx/Rr4JP1XnemC2X2ImMQsyEnupjVJp/+scVjtt2 To37cntzMxqxh+TPuzOht5Olt5BEWGwASJ0qe5wuHvy1GV57OgzGcUR43sJNUScNkRj0VTdmvSgR BzmMh4XF4dc1R1fILN2v+lOVf+8yYVKPh4i5ik2hEYnAXBjSbMZvexp3+QDLHhVLBPcAgj0glbKD GPxLmxFGz8x2wlIoueHdjQtMA0WEU7dVmsYmPmfias0xc+TDS3TFuqE1V+1xDY0HaDaYg2jFwQD0 pjPGVsXKOka3E+1sq/EbBFwNC5ffQCGVmzE7K7sO3p1eiVt8XSWOdWl3WYn8i0a374eFWU9N/QwX fuY6pTBAks5EifdNiHUqXhQ8QfpMRFqJd0xYTH1TkMZWGDR1YXdHfTRr//fnFxAoOS5hRnlLXsdS /cyOulD8GoAYYzxnwwNFA/Qv/GZ1FoMXAa5hNce4YvukUTJdULp31dfuH1NPvO8ShX1s8wHKAeFX 6/Djuc4j0PtWbErAxq3Pit0y+mwL4WqEtnEO25k3OS7/qKYuIjpY1gCOlVRo0ownVDNw1Ov+XmHr pn59RK1vOd1Elnof3JRrX+ZAqvtfaNSZA9omtxTGfCThXpW9tsegZyIYC4JWOEhLP7t4lOdRzED7 q4a/Fflesk1s5Lar73HDZzxxX2JeXtb10r5c/2wJ54i42eXUCIqicGhzBBtu8SFM9zvUptL+51gG yZ7EyMHaJLbJ/wTvB5bEcLVzAl04rsdKJjpbHVdx2zaRRhUruS+2HWkOprW3X906TlmJA4m6Nj6N HLGIWI4LVz/n+t/Vz7TTjNA2Q5UdRAfA19InWtWpPeNEEwn/MSOOMtUWnU+Or6gCmSA6RfKJwA/U x1e81BTslDd2hOb+M9K5PbIl6yMocxYROMSerAyVfiI6gZPvkdkPD6wEhjhdDACrDvepD355IPTO Pw0wsfFzzNhqJRy3nznd9TetKbkX6GAlUrpPTl7NvV10IHWR72a6Ccgrzuo6/WwZ5x8G71fXgVU8 5j0US5PljUrhLKz5jFxc+Ub+1OPrUWfS/e0ICKUV7DSlcNevCSVQSlownyLd52QGEPfWnQE+XHMY TY+x6Gt2nf68e/t6c4MWHu+S3DTs/AoBL5HfiVWv9McN7LGuPVC9x+fmm8ZPRtqqs8tPJVvz4gPo je/q6lFPd4DGsJKrj1uKQpb8qYUOcW5BUWZs3D8hsOH5s0eKv1Q59Fbto4j1T/dM3doPJSaTengX vF23MzEEXeS2CZmQ5PvvFfQq7dP3cO2JvJTjWrrgvxKZ8Zftsnw+PCS+QWyjHF2zOpOF8yNdRcza 7x3y0rmXKqR5Z0DHF7V4zkwNVIOVZT/H9g0yU0r79MAJR2jM/vceE4nXKZ94h5x9qy4CMP7Gougd 9DflFcknhDpvXGROUgV05/J3UA/5y1gp7R8u+LY18YpF/++f9UA3S87Jcj9iBh/YLgDs08Vkngbp fLtuvAG98iVp2kRsRVThCvFW4yZatzFVtSvuxt3NQuOR6UgWDPrUCxTglUZ1/Kqpgiuxw9kExWMy ZZv29PbACeIgLR+VqUI2Oe5df7xjCRkqZo+2hrn34oKImlbBfaSw+Q35SfgbJOzAkljRMcK+aqkA I1SVUCEB4fkYdvMV9lxDwswKxPR8Hp7atDdHeDHroBbOGevSZd6WcEUjpm86DCMnz28NGNz/qquS rg0X7mA7t5Z31B2vQ8gBXXjANTU99cXvUmvUZCCFfHOiefsG8gL+m9mGDhEkkJbKdOB4t3WJMuyK ANOG5ewO8/sl+zfbqgYw+h0277s7I56dWZz5yQZn2Gi1SyswDA== `protect end_protected

gpl-2.0

c3eb5e6b0de6789748fd3cd54c5da3a9

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

264cc81566214296c5884c525f152652

preusser/q27

src/vhdl/PoC/sync/sync.pkg.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Package: VHDL package for component declarations, types and -- functions associated to the PoC.misc.sync namespace -- -- Description: -- ------------------------------------ -- For detailed documentation see below. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.utils.all; use PoC.physical.all; package sync is component sync_Bits is generic ( BITS : POSITIVE := 1; -- number of bit to be synchronized INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits ); port ( Clock : in STD_LOGIC; -- <Clock> output clock domain Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @async: input bits Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- @Clock: output bits ); end component; component sync_Bits_Altera is generic ( BITS : POSITIVE := 1; -- number of bit to be synchronized INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits ); port ( Clock : in STD_LOGIC; -- Clock to be synchronized to Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data ); end component; component sync_Bits_Xilinx is generic ( BITS : POSITIVE := 1; -- number of bit to be synchronized INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits ); port ( Clock : in STD_LOGIC; -- Clock to be synchronized to Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data ); end component; component sync_Reset is port ( Clock : in STD_LOGIC; -- <Clock> output clock domain Input : in STD_LOGIC; -- @async: reset input Output : out STD_LOGIC -- @Clock: reset output ); end component; component sync_Reset_Altera is port ( Clock : in STD_LOGIC; -- Clock to be synchronized to Input : in STD_LOGIC; -- Data to be synchronized Output : out STD_LOGIC -- synchronised data ); end component; component sync_Reset_Xilinx is port ( Clock : in STD_LOGIC; -- Clock to be synchronized to Input : in STD_LOGIC; -- high active asynchronous reset Output : out STD_LOGIC -- "Synchronised" reset signal ); end component; end package;

agpl-3.0

f2bfc7d6a1a5c1ffd832869f5fed53f6

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- nanoFIP | -- | --------------------------------------------------------------------------------------------------- -- File : nanofip.vhd | -- | -- Description: nanoFIP is an FPGA component acting as a client node/ agent in the communication | -- over WorldFIP fieldbus. nanoFIP is designed to be radiation tolerant by using different | -- Single Event Upset mitigation techniques such as Triple Module Redundancy, fail-safe state | -- machines and several reset possibilities. The nanoFIP design is to be implemented in an Actel | -- ProASIC3 Flash family FPGA (130nm CMOS technology) that offers an inherent resistance to | -- radiation: it is immune to Single Event Latchups for the LHC environment, it has high tolerance| -- to Total Ionizing Dose effects (>300 Gy) and its configuration memory is not disturbed by SEUs.| -- nanoFIP is used in conjunction with a FIELDRIVE chip and FIELDTR insulating transformer, | -- both available from the company ALSTOM. | -- | -- __________________________________________________________________ | -- | | | -- | Field devices, Radioactive environment | Radiation free zone | -- | _____________ _____________ _____________ | _______________ | -- | | | | | | | | | | | -- | | user logic | | user logic | | user logic | | | | | -- | |_____________| |_____________| |_____________| | | | | -- | ______|______ ______|______ ______|______ | | | | -- | | | | | | | | | BUS ARBITRER | | -- | | nanoFIP | | nanoFIP | . . . | nanoFIP | | | | | -- | |_____________| |_____________| |_____________| | | | | -- | _____|_____ _____|_____ _____|_____ | | | | -- | |_FIELDRIVE_| |_FIELDRIVE_| |_FIELDRIVE_| | | | | -- | _____|_____ _____|_____ _____|_____ | | | | -- | |__FIELDTR__| |__FIELDTR__| |__FIELDTR__| | |_______________| | -- | | | | | | | -- |________|_____________________|________________________|__________| | | -- | | | | | -- _______^_____________________^________________________^________________________^____________ | -- 0____________________________________WorldFIP FIELDBUS______________________________________O | -- | -- Figure 1: Fieldbus layout | -- | -- In the WorldFIP protocol, the access to the bus is controlled by a central Bus Arbitrer (BA) | -- that grants bus access to the different agents following the sequence in a pre-configured | -- table. The BA is broadcasting ID_DAT frames to all the agents connected to the same network | -- segment requesting for a particular variable. Figure 2 shows the structure of an ID_DAT frame: | -- ___________ ______ _______ ______ ___________ _______ | -- |____FSS____|_CTRL_||__Var__|_SUBS_||____FCS____|__FES__| | -- | -- Figure 2: ID_DAT frame structure | -- | -- nanoFIP agents can handle the following set of variables: | -- o ID_DAT Var_Subs = 14_xy: for the presence variable | -- o ID_DAT Var_Subs = 10_xy: for the identification variable | -- o ID_DAT Var_Subs = 05_xy: for the consumed variable of any length up to 124 bytes | -- o ID_DAT Var_Subs = aa_xy: for the JTAG consumed variable of any length up to 124 bytes | -- o ID_DAT Var_Subs = 91_..: for the broadcast consumed variable of any length up to 124 bytes | -- o ID_DAT Var_Subs = 06_xy: for the produced variable of a user-settable length (P3_LGTH) | -- o ID_DAT Var_Subs = ab_xy: for the JTAG produced variable of a predefined length of 1 byte | -- o ID_DAT Var_Subs = E0_..: for the broadcast consumed reset variable | -- | -- After a 14_xy, a 10_xy, a 06_xy or a ab_xy ID_DAT, if nanoFIP's address (SUBS) is xy, nanoFIP | -- will respond with an RP_DAT frame, containing the variable requested. Figure 3 shows the | -- structure of a RP_DAT frame: | -- ___________ ______ ____________________ ___________ _______ | -- |____FSS____|_CTRL_||_____...Data..._____||____FCS____|__FES__| | -- | -- Figure 3: RP_DAT frame structure | -- | -- After a 05_xy or an aa_xy ID_DAT, if nanoFIP's address (SUBS) is xy, | -- or after a broadcast ID_DAT 91..h or E0..h, nanoFIP will receive/ "consume" the next incoming | -- RP_DAT frame. | -- | -- Regarding the interface with the user logic, nanoFIP provides: | -- o data transfer over an integrated memory accessible with an 8-bit WISHBONE System-On-Chip | -- interconnection | -- o possibility of stand-alone mode with a 16 bits input bus and 16 bits output bus, without | -- the need to transfer data to or from the memory | -- o separate data valid outputs for the consumed (05_xy), broadcast consumed (91_..) and | -- produced (06_xy) variables | -- o JTAG master controller interfacing with the Test Access Port of the user logic FPGA | -- | -- nanoFIP provides several reset possibilities: | -- o External reset input pin, RSTIN, activated by the user logic | -- o External reset input pin, RST_I, activated by the user, that resets only the WISHBONE logic | -- o Addressed reset by the reset broadcast consumed variable (E0..h), | -- validated by station address as data | -- o External Power On Reset input pin, RSTPON | -- | -- nanoFIP also provides resets to the user and to the FIELDRIVE: | -- o Reset output available to external logic (RSTON) by the reset broadcast consumed variable | -- (E0..h), validated by station address as data | -- o FIELDRIVE reset output (FD_RSTN) by the reset broadcast consumed variable (E0..h), | -- validated by station address as data | -- | -- nanoFIP's main building blocks are (Figure 4): | -- o wf_reset_unit : for the treatment of the reset input signals & the generation | -- of the reset outputs | -- | -- o wf_fd_receiver : for the deserialization of the FIELDRIVE input and the formation | -- of ID_DAT or consumed RP_DAT bytes of data | -- | -- o wf_consumption : for the processing, storage & validation of consumed RP_DAT frames | -- | -- o wf_fd_transmitter : for the serialization of produced RP_DAT frames | -- | -- o wf_production : for the retrieval of bytes for produced RP_DAT frames | -- | -- o wf_engine_control : for the processing of the ID_DAT frames and the coordination of the | -- wf_consumption, wf_fd_receiver, wf_production & wf_fd_transmitter units| -- | -- o wf_model_constr_dec: for the decoding of the WorldFIP settings M_ID and C_ID and the | -- generation of the S_ID | -- | -- o wf_wb_controller : for the handling of the "User Interface WISHBONE Slave" control | -- signals | -- | -- o wf_jtag_controller : for driving and monitoring the user logic TAP upon reception of JTAG | -- variables (aa_xy and ab_xy). | -- | -- _____________ ____________________________________________________ | -- | | | wf_WB_controller | | -- | wf_reset | |____________________________________________________| | -- | _unit | _____________ _____________ | -- | | | | ______________ | | | -- |_____________| | | | | | | | -- | wf_ | | | | wf_ | | -- _____________ | consumption | | | | production | | -- | | | | | | | | | -- | wf_JTAG | | | | | | | | -- | _controller | |_____________| | wf_ | |_____________| | -- | | _____________ |engine_control| _____________ | -- |_____________| | | | | | | | -- | | | | | | | -- _____________ | | | | | | | -- | | | wf_FD_ | | | | wf_FD_ | | -- | wf_model_ | | receiver | | | | transmitter | | -- | constr_dec | | | | | | | | -- | | | | | | | | | -- |_____________| |_____________| |______________| |_____________| | -- | -- Figure 4: nanoFIP block diagram | -- | -- The design is based on the nanoFIP functional specification document, available at: | -- http://www.ohwr.org/projects/cern-fip/documents | -- Complete information about this project at: http://www.ohwr.org/projects/cern-fip | -- | -- | -- Authors Erik Van der Bij (Erik.Van.der.Bij@cern.ch) | -- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 10/2011 | -- Version v0.06 | -- Depends on wf_reset_unit | -- wf_model_constr_dec | -- wf_fd_receiver | -- wf_fd_transmitter | -- wf_consumption | -- wf_production | -- wf_engine_control | -- wf_wb_controller | -- wf_jtag_controller | ---------------- | -- Last changes | -- 30/06/2009 v0.010 EB First version | -- 06/07/2009 v0.011 EB Dummy blocks | -- 07/07/2009 v0.011 EB Comments | -- 15/09/2009 v0.v2 PA | -- 09/12/2010 v0.v3 EG Logic removed (new unit inputs_synchronizer added) | -- 7/01/2011 v0.04 EG major restructuring; only 7 units on top level | -- 20/01/2011 v0.05 EG new unit wf_wb_controller(removes the or gate from top level) | -- 06/2011 v0.06 EG jtag_controller unit added | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for nanoFIP --================================================================================================= entity nanofip is port( -- MODIFIED nanofip_rst_o : out std_logic; --INPUTS -- WorldFIP settings c_id_i : in std_logic_vector (3 downto 0); -- Constructor identification settings m_id_i : in std_logic_vector (3 downto 0); -- Model identification settings p3_lgth_i : in std_logic_vector (2 downto 0); -- Produced variable data length rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate subs_i : in std_logic_vector (7 downto 0); -- Subscriber number coding (station address) -- FIELDRIVE fd_rxcdn_i : in std_logic; -- Reception activity detection, active low fd_rxd_i : in std_logic; -- Receiver data fd_txer_i : in std_logic; -- Transmitter error fd_wdgn_i : in std_logic; -- Watchdog on transmitter -- User Interface, General signals nostat_i : in std_logic; -- No nanoFIP status with produced data rstin_i : in std_logic; -- Initialization control, active low -- Resets nanoFIP & the FIELDRIVE rstpon_i : in std_logic; -- Power On Reset, active low slone_i : in std_logic; -- Stand-alone mode uclk_i : in std_logic; -- 40 MHz clock -- User Interface, NON-WISHBONE var1_acc_i : in std_logic; -- Signals that the user logic is accessing var 1 var2_acc_i : in std_logic; -- Signals that the user logic is accessing var 2 var3_acc_i : in std_logic; -- Signals that the user logic is accessing var 3 -- User Interface, WISHBONE Slave wclk_i : in std_logic; -- WISHBONE clock; may be independent of uclk adr_i : in std_logic_vector (9 downto 0); -- WISHBONE address cyc_i : in std_logic; -- WISHBONE cycle dat_i : in std_logic_vector (15 downto 0);-- DAT_I(7 downto 0) : WISHBONE data in, memory mode -- DAT_I(15 downto 0): data in, stand-alone mode rst_i : in std_logic; -- WISHBONE reset -- Does not reset other internal logic stb_i : in std_logic; -- WISHBONE strobe we_i : in std_logic; -- WISHBONE write enable -- User Interface, JTAG Controller jc_tdo_i : in std_logic; -- JTAG Test Data Out; input from the target TAP -- OUTPUTS -- WorldFIP settings -- MODIFIED --s_id_o : out std_logic_vector (1 downto 0);-- Identification selection -- FIELDRIVE fd_rstn_o : out std_logic; -- Initialization control, active low fd_txck_o : out std_logic; -- Line driver half bit clock fd_txd_o : out std_logic; -- Transmitter data fd_txena_o : out std_logic; -- Transmitter enable -- User Interface, General signals rston_o : out std_logic; -- Reset output, active low -- User Interface, NON-WISHBONE r_fcser_o : out std_logic; -- nanoFIP status byte, bit 5 r_tler_o : out std_logic; -- nanoFIP status byte, bit 4 u_cacer_o : out std_logic; -- nanoFIP status byte, bit 2 u_pacer_o : out std_logic; -- nanoFIP status byte, bit 3 var1_rdy_o : out std_logic; -- Signals new data received & can safely be read var2_rdy_o : out std_logic; -- Signals new data received & can safely be read var3_rdy_o : out std_logic; -- Signals that the var 3 can safely be written -- User Interface, WISHBONE Slave -- MODIFIED was (15 downto 0) dat_o : out std_logic_vector (7 downto 0);-- DAT_O(7 downto 0) : WISHBONE data out, memory mode -- DAT_O(15 downto 0): data out, stand-alone mode ack_o : out std_logic; -- WISHBONE acknowledge -- User Interface, JTAG Controller jc_tms_o : out std_logic; -- Drives the JTAG Test Mode Select of the target TAP jc_tdi_o : out std_logic; -- Drives the JTAG Test Data In of the target TAP jc_tck_o : out std_logic); -- Drives the JTAG Test Clock of the target TAP end entity nanofip; --================================================================================================= -- architecture declaration --================================================================================================= architecture struc of nanofip is -- wf_reset_unit outputs signal s_nfip_intern_rst, s_wb_rst : std_logic; -- wf_consumption outputs signal s_var1_rdy, s_var2_rdy, s_var3_rdy : std_logic; signal s_assert_RSTON_p, s_reset_nFIP_and_FD_p : std_logic; signal s_nfip_status_r_tler : std_logic; signal s_jc_start_p : std_logic; signal s_jc_mem_data : std_logic_vector (7 downto 0); -- wf_fd_receiver outputs signal s_rx_fss_received_p, s_rx_fss_crc_fes_ok_p : std_logic; signal s_rx_crc_wrong_p, s_rx_byte_ready_p : std_logic; signal s_rx_byte : std_logic_vector (7 downto 0); -- wf_production outputs signal s_byte_to_tx : std_logic_vector (7 downto 0); -- wf_fd_transmitter outputs signal s_tx_last_byte_p, s_tx_completed_p : std_logic; -- wf_engine_control outputs signal s_tx_start_p, s_tx_request_byte_p : std_logic; signal s_byte_request_accepted_p, s_cons_bytes_excess, s_rx_rst : std_logic; signal s_var : t_var; signal s_prod_data_lgth, s_prod_byte_index, s_cons_byte_index : std_logic_vector (7 downto 0); -- wf_model_constr_dec outputs signal s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0); -- wf_wb_controller outputs signal s_wb_ack_prod : std_logic; -- wf_model_constr_dec outputs signal s_jc_mem_adr_rd : std_logic_vector (8 downto 0); signal s_jc_tdo_byte : std_logic_vector (7 downto 0); --================================================================================================= -- architecture declaration --================================================================================================= begin -- MODIFIED nanofip_rst_o <= s_nfip_intern_rst; --------------------------------------------------------------------------------------------------- -- wf_reset_unit -- --------------------------------------------------------------------------------------------------- reset_unit : wf_reset_unit port map( uclk_i => uclk_i, wb_clk_i => wclk_i, rstin_a_i => rstin_i, rstpon_a_i => rstpon_i, rate_i => rate_i, rst_i => rst_i, rst_nFIP_and_FD_p_i => s_reset_nFIP_and_FD_p, assert_RSTON_p_i => s_assert_RSTON_p, ------------------------------------------------------------- nFIP_rst_o => s_nfip_intern_rst, wb_rst_o => s_wb_rst, rston_o => rston_o, fd_rstn_o => fd_rstn_o); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_consumption -- --------------------------------------------------------------------------------------------------- Consumption: wf_consumption port map( uclk_i => uclk_i, slone_i => slone_i, nfip_rst_i => s_nfip_intern_rst, subs_i => subs_i, rx_byte_i => s_rx_byte, rx_byte_ready_p_i => s_rx_byte_ready_p, rx_fss_crc_fes_ok_p_i => s_rx_fss_crc_fes_ok_p, rx_crc_wrong_p_i => s_rx_crc_wrong_p, wb_clk_i => wclk_i, wb_adr_i => adr_i (8 downto 0), cons_bytes_excess_i => s_cons_bytes_excess, var_i => s_var, byte_index_i => s_cons_byte_index, jc_mem_adr_rd_i => s_jc_mem_adr_rd, ------------------------------------------------------------- var1_rdy_o => s_var1_rdy, var2_rdy_o => s_var2_rdy, jc_start_p_o => s_jc_start_p, data_o => dat_o, nfip_status_r_tler_p_o => s_nfip_status_r_tler, assert_rston_p_o => s_assert_RSTON_p, rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p, jc_mem_data_o => s_jc_mem_data); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_fd_receiver -- --------------------------------------------------------------------------------------------------- FIELDRIVE_Receiver: wf_fd_receiver port map( uclk_i => uclk_i, rate_i => rate_i, fd_rxd_a_i => fd_rxd_i, nfip_rst_i => s_nfip_intern_rst, rx_rst_i => s_rx_rst, ------------------------------------------------------------- rx_byte_o => s_rx_byte, rx_byte_ready_p_o => s_rx_byte_ready_p, rx_fss_crc_fes_ok_p_o => s_rx_fss_crc_fes_ok_p, rx_fss_received_p_o => s_rx_fss_received_p, rx_crc_wrong_p_o => s_rx_crc_wrong_p); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_production -- --------------------------------------------------------------------------------------------------- Production: wf_production port map( uclk_i => uclk_i, slone_i => slone_i, nostat_i => nostat_i, nfip_rst_i => s_nfip_intern_rst, wb_clk_i => wclk_i, wb_data_i => dat_i(7 downto 0), wb_adr_i => adr_i(8 downto 0), wb_ack_prod_p_i => s_wb_ack_prod, slone_data_i => dat_i, var1_acc_a_i => var1_acc_i, var2_acc_a_i => var2_acc_i, var3_acc_a_i => var3_acc_i, fd_txer_a_i => fd_txer_i, fd_wdgn_a_i => fd_wdgn_i, var_i => s_var, data_lgth_i => s_prod_data_lgth, byte_index_i => s_prod_byte_index, byte_request_accept_p_i => s_byte_request_accepted_p, nfip_status_r_tler_p_i => s_nfip_status_r_tler, nfip_status_r_fcser_p_i => s_rx_crc_wrong_p, var1_rdy_i => s_var1_rdy, var2_rdy_i => s_var2_rdy, model_id_dec_i => s_model_id_dec, constr_id_dec_i => s_constr_id_dec, jc_tdo_byte_i => s_jc_tdo_byte, ------------------------------------------------------------- byte_o => s_byte_to_tx, u_cacer_o => u_cacer_o, u_pacer_o => u_pacer_o, r_tler_o => r_tler_o, r_fcser_o => r_fcser_o, var3_rdy_o => s_var3_rdy); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_fd_transmitter -- --------------------------------------------------------------------------------------------------- FIELDRIVE_Transmitter: wf_fd_transmitter port map( uclk_i => uclk_i, rate_i => rate_i, nfip_rst_i => s_nfip_intern_rst, tx_byte_i => s_byte_to_tx, tx_byte_request_accept_p_i => s_byte_request_accepted_p, tx_last_data_byte_p_i => s_tx_last_byte_p, tx_start_p_i => s_tx_start_p, ------------------------------------------------------------- tx_byte_request_p_o => s_tx_request_byte_p, tx_completed_p_o => s_tx_completed_p, tx_data_o => fd_txd_o, tx_enable_o => fd_txena_o, tx_clk_o => fd_txck_o); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_jtag_controller -- --------------------------------------------------------------------------------------------------- JTAG_controller: wf_jtag_controller port map( uclk_i => uclk_i, nfip_rst_i => s_nfip_intern_rst, jc_mem_data_i => s_jc_mem_data, jc_start_p_i => s_jc_start_p, jc_tdo_i => jc_tdo_i, ----------------------------------------------------------------- jc_tms_o => jc_tms_o, jc_tdi_o => jc_tdi_o, jc_tck_o => jc_tck_o, jc_tdo_byte_o => s_jc_tdo_byte, jc_mem_adr_rd_o => s_jc_mem_adr_rd); ----------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_engine_control -- --------------------------------------------------------------------------------------------------- engine_control : wf_engine_control port map( uclk_i => uclk_i, nfip_rst_i => s_nfip_intern_rst, tx_byte_request_p_i => s_tx_request_byte_p, tx_completed_p_i => s_tx_completed_p, rx_fss_received_p_i => s_rx_fss_received_p, rx_byte_i => s_rx_byte, rx_byte_ready_p_i => s_rx_byte_ready_p, rx_fss_crc_fes_ok_p_i => s_rx_fss_crc_fes_ok_p, rx_crc_wrong_p_i => s_rx_crc_wrong_p, rate_i => rate_i, subs_i => subs_i, p3_lgth_i => p3_lgth_i, slone_i => slone_i, nostat_i => nostat_i, ------------------------------------------------------------- var_o => s_var, tx_start_p_o => s_tx_start_p, tx_byte_request_accept_p_o => s_byte_request_accepted_p, tx_last_data_byte_p_o => s_tx_last_byte_p, prod_byte_index_o => s_prod_byte_index, cons_byte_index_o => s_cons_byte_index, prod_data_lgth_o => s_prod_data_lgth, cons_bytes_excess_o => s_cons_bytes_excess, rx_rst_o => s_rx_rst); ------------------------------------------------------------- var1_rdy_o <= s_var1_rdy; var2_rdy_o <= s_var2_rdy; var3_rdy_o <= s_var3_rdy; --------------------------------------------------------------------------------------------------- -- wf_model_constr_decoder -- --------------------------------------------------------------------------------------------------- model_constr_decoder : wf_model_constr_decoder port map( uclk_i => uclk_i, nfip_rst_i => s_nfip_intern_rst, model_id_i => m_id_i, constr_id_i => c_id_i, ------------------------------------------------------------- -- MODIFIED -- s_id_o => s_id_o, model_id_dec_o => s_model_id_dec, constr_id_dec_o => s_constr_id_dec); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_wb_controller -- --------------------------------------------------------------------------------------------------- WISHBONE_controller: wf_wb_controller port map( wb_clk_i => wclk_i, wb_rst_i => s_wb_rst, wb_stb_i => stb_i, wb_cyc_i => cyc_i, wb_we_i => we_i, wb_adr_id_i => adr_i (9 downto 7), ------------------------------------------------------------- wb_ack_prod_p_o => s_wb_ack_prod, wb_ack_p_o => ack_o); ------------------------------------------------------------- end architecture struc; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

f78aa49b1a702ae1a65e807ed14c50f3

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_Atomic_SubInteger_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant ATOMIC_IMPLEMENT : natural := 1; constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

f18ebb962378d48230bb5b050002cbf2

preusser/q27

src/vhdl/PoC/common/my_project.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Project specific configuration. -- -- Description: -- ------------------------------------ -- This is a template file. -- -- TODO -- -- USAGE: -- 1) Copy this file into your project's source directory and rename it to -- "my_project.vhdl". -- 2) Add file to library "poc" in your synthesis tool. -- 3) Change setup appropriately. -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library PoC; package my_project is constant MY_PROJECT_DIR : string := "/non/existent"; constant MY_OPERATING_SYSTEM : string := "LINUX"; end; package body my_project is end;

agpl-3.0

20f5ec1f300a07bdc3aaf961bba27534

preusser/q27

src/vhdl/PoC/uart/uart.pkg.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- =========================================================================== -- Package: UART (RS232) Components -- -- Authors: Martin Zabel -- Thomas B. Preusser -- -- License: -- =========================================================================== -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- =========================================================================== library IEEE; use IEEE.std_logic_1164.all; package uart is component uart_bclk generic ( CLK_FREQ : positive; BAUDRATE : positive ); port ( clk : in std_logic; rst : in std_logic; bclk : out std_logic; bclk_x8 : out std_logic ); end component; component uart_rx is generic ( SYNC_DEPTH : natural := 2 -- use zero for already clock-synchronous rx ); port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Bit Clock and RX Line bclk_x8 : in std_logic; -- bit clock, eight strobes per bit length rx : in std_logic; -- Byte Stream Output do : out std_logic_vector(7 downto 0); stb : out std_logic ); end component; component uart_tx is port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Bit Clock and TX Line bclk : in std_logic; -- bit clock, one strobe each bit length tx : out std_logic; -- Byte Stream Input di : in std_logic_vector(7 downto 0); put : in std_logic; ful : out std_logic ); end component; end uart; package body uart is end uart;

agpl-3.0

57816f5421cc2deeb63dcd9a023a4f7e

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sim_1/tb_stim_reader.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block uS9Fi4wEl+hlOoAxATWz7JOEkR0NrTOAPXB71RDz/0sJ9oBkdyJcZqzmiJBSpJVLGXrHypKErbng NIq2yEIKicsHE2U2q0TwmOX5SeBUf5ATfJiLQmZtyrgyJ/TKwJ5Nrg3HL+15E0oFzqZEKRQD0RV0 gUht+SMMiNU2xM6RPT7pKCsVb5W4nxZuUNAOyuABEDGRH8YW/kscyF5trBuA48XfiXtVpzBwqK6v PeJ+bU10he4Sno6k9Dn4FGHEKjKtWs1EQPCyJM25dDSrh8kM7MRJepMfF7YseaGlTZntu/uKxJDR ZL3LeAxQZMrU6BodVmaZalC+X5WBYD/UwSiWkQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4736) `protect data_block 7VA8mzdPPZYOJeyTQqqWw6ROfVWnyt6qvtwNX9ZhrxOFRzs9VptzDCYpuvOsdXNKmLDGXRp7YUkF AuhjeFhEKjoy3cV4afIh7l6tF73hWSXpcgpvltm/P/Taxdzb0dQIFN3TxHvbjnj4qgMk2Gib23t1 esnKiL4/M3rabvXj8tSteb0yFT8QfFA5hhjKEmMObgbyv/pb0p3VCgMC8WC/tDGyvUTk3rCaixuv U5qNJWyxVKhPT+fku+U3YPgdD2rDWJ1rtVuH6fYdhDb1CRtGIiSpszjZfwNX5T/Xb7DpfemRmZQU 0uXgqFJII77cfYKiQK5Oa7gZ7EN3or6WtecdcfYWCtMXUoBNX3ESpSoC2q3BD4+NpqgfAbgnO5mD FKc+nil1SFQ5lpnCnX3PeU3rPFmqWyI/IaV2TbTPfeQ2N5FR1Ma79qx73e76hj6Y81OD6onWN12L zAnApg/lyXqZE+QR4gK2MAWLo8z4MJFFlEG5Lmw1YcQlqLjJcU/EV9dhv9erBsTs0B5fIPtnIiUZ MBQiF+B+QsFptzODqLKKhbnn5x7lescUZe5AH+hR1nsX2YI4d1c9BHILUFAy15J8xF+XsiTYVPNm 9/degi4w1m00gDmbHqL8iRDOKpRBrDgu/Sl4TF0hFYBbSQ5optFY3dPc/sHHZV/isS1CRwiaLTHv RMN7g42YwRXhOGMfnGeeFYdhIunlzfMhyskbSxr9Vh4PE6sstuaehjUt3tQyTBP1nuoI4dLeBvqo 2k9MsjjMPxrnNsIzrPSqeUFILG+PKmcW9O8NLmRJuv3QDXN2Kr/VDN/jNiVs+hWgjOh4r9Dp1P95 L2V1TxkEOOYmRpTUXAjXSD192laGoe8S7OxywlUrVASRrtvIF8mxdSe7zjEVfJL600IrM3yQdHBS hGFqNnh2zXKwzeQq4qCQnkYSoVgq41poNT3yAvjUXURKevlD6u1useTNsOs5ZiwxBGdb/O9SATkR n19XB+7L5oOvuOF/+BY82Y2FsvbTou6Y95RD0c2tKEuwnpO7OW2hmVMgBOZuo25EFgKTlbsmVQGO IUn7kkQ86i0pGk+ehsgwxdAYM0b/B0I1TgdHziNLkTr0lf4Ivq0CRzC4T/zPRtUDttjUPiXRh9To f2DGn2/VPgG/9HpH1iEMsvU7841hD1Y/7alDVF71O5fn9SAPIj5nFAdY8haMbvdiHnHvd1OheTDP njO1g7rCSH1bTAKWgB79uEpWz1puIqFLyXg22P1/nSOMmPOYAniFGYwMZDfu/PpP+c2Du1zYawIU N4EWU8UF1dvx/Po7z9XdRmCuoGZZaIMh2yhr4ZDqhLoY0P8J4EU5/2J5t7oKe++S9erZeO6RlEC4 yn8V5AiH9AERDfhsS7BRnWRx0LOiidNXHH0Oinj9d8Cu1vvIu1yPyVcUbyH0xUuKgL76GTsZMb1+ nhB0c9JknLcvyrIILHaHnL1mYJ5KS2gZIbyGnnqpTAtlJEEO6Ob8CUszr7Yao/JqrHs919Ek999x J1M0/exDN1wmS8zYtVih1L8o/rH+ISN/hxKUi+jczWWUTZ4llmO+UUDjGGmRe1S5jz0TwQNtaY9L lpkWC7c7KzXNr1C/bGKY4jCAyZ1jLbAEpIsf7i67Lf1MgfHEGuy49QpdhnWtjpCRYGj9NqHtBa1u acRthkSjx+Zq3YoXSqsWd5BZUi/VgXvRKRI9YXSeP8hWvM9C8uU7JftG7GwpBbCtKXhkBnYcEkJU aiGjyL+tOxlEFkMKI/Ylh37WhXI6oGehaABnBuQo4m/T/t6MsbCBT5r7CcgGrulQNQOk/ouok4hr Gf6qyOZVZc6+eD4JKnnA5qqH5jfx0HRgmeiwcPv6SHvfpmaCQMtuVLQQ47Zub0PdABLSNWUmhajr wyE30qMR1BKqYiXljFiyE/h+ooYarnysF9nzgYRX2UtPtJ8RzOse0lbLV2Bn5oinBOMtbTDylrmS N5NgN5xnACQbkYAmtzRflMyJQRRR3gZtfb8/lPiXZaUwsipeOyAaaGuI85lGEoRnXnnghi4OopMW rElpvLjfzTzzJ6zPM23mGl/Zlwf54HPIQwk2x7TkNcbziSWhSL/UIjIu0vuLH53sElDOJ9uuXwXA IfjlDo1OOH4FK6fMdeWK9B1Nz1/1zUcHVJSfH9TQzhzl3kT85iN2k69nG0BKGOlGFjSxUVcW1sFl N1o4jSeRaRNXHSy5FjD9ASU1UrPVGg63HB0c5ZAID1p/DAGHupSQ0gLwKlGShkq6Tx5PROk9Wqa4 xeO/M4GYsDc0ZmKNPIsK1lZly/TqZA02kIsmx0oZgg3veTPZcqlMCOPKbj6s1LbLdCek4uFLfPzZ cTsD7dtWEMdlQBwaVcze5lk2F9SMgwNLwQQuBJn/YS1fIIjCWa4GzaSm0JiQENfdi+QabONT9Edz uUCKQQ+cQp00Oe5ph5KbaaAIQuVR7JIGtbDisW9Z+r3/cb9OqDLuMFuaPOr46mlSRUZe7i3sSxH6 e8Vhm96kaGKUVeeZn7NMR+aurJWxV/ea1pDbjVgnVE55T+injBurjwt9dmqtAmu+d3+jSxJrZSHC qM8GygFtn23wjicpP97IloecIKb5cfiX2M0nhLFcLG/arvurOhRwwhtYscFNNMs+izawjZE89I+E vPYWHL3hsfH/R9cx5f3wluqulhppHpds/+8d16kQVpWirWfJk9NxBC72XTsGfLxp7Q5/WJanIqQ4 MkkgcGIKDT1U/g8a/9X2kc82qHNrdXrIf6NhaSu+pKnEFeV0DJe2lp7F2lzy1u+f5G01at4W3HV9 mYy9NQY7DDmZxkte4y8JZgKzPLwiBQru25Z54fV8AVuBrKDo8UwGUsPDmP/AQi8NBfceB4dH4sNC OtGqY1tT3UaUFVHqnRYUtXOFkQ0hRN2qbznm9h8pOkmkH3YLcIpbvu4/+5CiLkHtjdyIYwTXNexr IS0ZTw4+gQu2Vi5KHpmm2Wg/3co1wccBadur4lnRyIo36hmpQeEMtZWpDVS5R7SqSfSbll/8fGpV aPeZsk6aXCOTL92/RWTquVLtvR9cRA31UYBscvgzwI18pl++bACDjyIYoV8m0Q8DHHL9DmWaKYXT M/JWxC7RkAn520YhaATZavJqcL0ZuVlRn9G9IAF1drIGDSuSLcNlr090bhtCzVIQIRDCPPUeDuG2 /cyXomWXSU3GVyu/rbGqBZ+YKE00bosy/UKY+GlcDjRv2ywyzZEFJFM1HU9gtGaJXG7nrQ7UEfYr Za+p5LYGtcCWvCFN1Ouvl4XlwRrqrMSDogU2GW+RWWY+i8L9pZvMqSY3SKkBahJbGebVfrQsGKzn U0tkR0ItPQZ9q3MxwLMu4ModFE7u2dtIzuIWZSPy502xPnf/tmutb6t5lyXRi3vN1ewBIOPh1OF2 iZsxCEy0ZYuBx5QipJHqJiDTM5phS2yC9NtrCVkO2Kncpc+Pp+qpwK4kfFZZ82/w6s7KsjI2oeyH btWvYIxB6gK/0Q8QTVtG35mc/1yjqGqEowOptjY1uJ2LXY/KcobGozTfiv86HrMRoRvHKc6r3wCr 4Vk6cEpYWCLwgVcmj8kJw0WMQc/4qkW57WnY1Nt++YiHKIMcm7IBsWlz9n1XdtomODIesmLTUEDq nqeQojZkOnThyOKF8FQis6ikZwM9cpYQbR4+xpLvKyEp0cpbrRMcHtbdRzOkDk/9NJJ8TN3N5kj9 VPsHnIGI9pSDuT3ZEEAkc+9XVu5OPpcyx6XJZWEwoyTMU7gcYxrmUy0ZlNI+hbPt3mmNfPk/pwwU 4wBenqfpoEvxcf9/dvqcQPCCiO75xGtK5q1WCp/ZiaulpSIquSep6NqMc4ir1wRSjrDn237pc/d2 8UwoAe+886nfguxZzSrklOSYXUjhuTM6nei0kkWLu+5iqEzDsRr8eEjEECvt9OuozNhXtO1F+mR/ tsexZAgorHJQaQhfEDbe7/Php4vPYZPKOGfqILEsuWJk9ZPBosWcJkbDGsoKpfZcsm3TywqqWCA6 nbwbyLuOjJsASmBj7i4R2m4/x3QMLU4RnQJXUlYOCK2beQCHZsJum24x3SupFykRfoifXndaclUw xvxmm+4S/uUdKLYAShYa93PRRIvgkNIb5tF+JVc8DsrVReqFnxr4sTdHG0YI1iMzJ52QUThuqGCS JGi2cM6YTqpUJFc7JjTA9HHL+8/T+sZ7fTj+BSxirwGu4FoNpByDETuPDMaPsi1ZOb2mCkoozhY7 jps+qzd6BcJ9hcO/yk4fMF4t8z/5sHAyspTUIDX8v1twp1BDsqv+PT5SNip7lZ0nIMmNFS2YSS8A fTDcu796yL8OxgL1lz+oKWdYh2zdC6P+DA1ECQeY4GjGCqzxyos/oomZQjw2avIFtz3ZNjD1r0BX nJRIa+gqJ+UBXbZNbYpBL9HHv4p3ypHqFmgdDop2+wC6pA3K12uvRxLmoHZ+lHdSmalPykiecviE m5IcgEoPKVAqlxFJ8C9WIBWe/8sJUVCHdRLGlZ9sWJNpG2aJOj+1jmz46auAR+GC2W0zRco6CmBt YQIqzXNVpefOGSPjQb7JM1FXgDW0I+EYM/sEa2EcKVvre520chjDg57/917EoMnEG4bEXu8107Nn zBdtpVQxrruuqdzwI+v4v74PQ8+Tx4Pu3shVGXVazbRUkoItfK7zQDKBrTQrjCOQbVHdJHxBWEar hY9iHD4Z9W8zUlYe/g6Iz2qswz11AdabohxUGvZDw8HM0kyHM4Mt4RQ36v4gUQU8pv35pKYOd3du eN58tiAXi8fe11MHZvVQ03y4jSzdy0ST1mx+v2yKsNY9QMpiP5ElQYi9EyiuPqZmzqOe5/UCYitc 1vkhXhfpSkeM2NeSArqw0mQBk3qJkZs19QRJrYRBqCuxo79WuZUH0sFR76oqd+GdjOpJmj6PoU7E mD1ZJc5/hOmkOpz/W4AMuzBp9XwtiKmlKtshfnkHt7MoxqwclIA8ISsDLRoYVxqTpqUHDnYy5MuQ if7nj7Wk991yZqBCEkvM5alhsR7ObRurrsAjpYy+8VTh5r7e104qV4bp9PjKioeHFkJS3aeR3Zhy 8pjsy34QWGNaGBjm6yZVE7b8yBq6toWYg3vStz0NEtf88daNa+6NaRwwsA0zBQ2O7lmGNpSJgOXI YVSJjO1VGH66jBaX8r6tJl2IkXoioVEwwWx6ebVktQdaN8GdtDbkScq5dqIGlZb8BC4wfO8paZ8x BWFFaUzVZQZgjO+nOucPwH1SAFpZfuqcAXylAVcfKnnNBvGmop1KWvQw19vZ1iLdrTWQChBwjZrc PPMcel5gv0QSaE/45cpbrGZ3Enfsdcbvo8Aa5bexR2tk94Bm9hrjxZzMZqxjzrpaVSISEq635WIk ZSEN5sqeM2ICJlRKTRBwXG3LOdrTFRpDd0KyjI11W5sOnZ4eKQeoiJgPc5WH741CBFCrVwJeV5Cz ajSnxzqojDoIHbZRqP6NnYsRZ92mtRLHCvxJBT0akDdr6k4j7hFg/jjGqc4ESgQdGw4HD/hBOj2i 7BrSKwP/v7PYkeqx1587qLHeJmDauhqI3Y7kdtGy+yILBO5owumCGJzYYJ0qnZtfOIJ4GKJAw0T/ WQq+jHY6wFF33ZtnOD2C4h49OHw/kekdpD/z0s2+50VF5WttnUzmFUq7CX9fvCBCB5ObhrYhoXEo W+Cfxj7RVcCG8p17jQR91sp1ykf5BXuyq/HJPb4IdMCJ4P0VE87xR1lTBAfEGQ5rAc3RHDigLXIM cMf3mtucwEFu7TkSRAw4gLTrf0L5rQlEZPw7UtDe2XRu/my5VI6FtfGU/psUbJC3dAq3W+Y7i4U6 W6pkr51RQdfPnKUxLowLG41s/BAmrOgTyK9uX/18p0wJFoWNicFef/SI0/Rv+p7cv5Im+x/AxvXV U8QHPIZOpa0ExpDo5rmmd3Y1DHgaUpghZYA5UguEssp3hlJTQMC2qHXB08r6KA3tUXyiWX1Gr1Xd UjWeGgmGYUv4CnpeTvXivlkLNzLS+8DnCT3UajGBo1AMxB5OOATc3sXqEvgjp/BXMRUkkfAu8sC1 3MeYMVN1aDQ5wbt71a2UvofOgMVUbfLEUnAc1psKEcC2RtyShIBuOreWfWBb4x3gaXPMdfxyFcCM dDDzjOalay/5sq5GCDKwEPBXGHweavNNvSW3WaXAUggw12r09RTuHvti9lfQLxHK9+QFGBRu1nLz a0CNAYqvxmNFOYTp+OkuqmTAW+pw9klK+LWzXr0Nk27tAiXe2M9OsS9c31UL+EpQh/Qw7j69VvWX 23/zt/k= `protect end_protected

gpl-2.0

f53f43da34b40bbc7de17c9716638a81

preusser/q27

src/vhdl/top/xilinx/kc705_queens_uart.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity kc705_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 250; COUNT_CYCLES : boolean := false; CLK_FREQ : FREQ := 200 MHz; CLK_DIVA : positive := 9; CLK_MULA : positive := 64; CLK_DIVB : positive := 5; BAUDRATE : positive := 115200; SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte ); port ( clk_p : in std_logic; clk_n : in std_logic; rx : in std_logic; tx : out std_logic; rts : in std_logic; cts : out std_logic; -- Fan Control FanControl_PWM : out std_logic ); end kc705_queens_uart; library IEEE; use IEEE.numeric_std.all; library UNISIM; use UNISIM.vcomponents.all; library PoC; architecture rtl of kc705_queens_uart is -- Global Control constant CLK_COMP_FREQ : FREQ := CLK_FREQ / CLK_DIVA * CLK_MULA / CLK_DIVB; constant CLK_SLOW_FREQ : FREQ := CLK_FREQ / CLK_DIVA * CLK_MULA / 100; signal clk200 : std_logic; -- 200 MHz Input Clock signal clk_comp : std_logic; -- Computation Clock signal clk_slow : std_logic; -- Slow Interface Clock signal rst : std_logic; begin ----------------------------------------------------------------------------- -- Generate Global Controls blkGlobal: block is signal clkfb : std_logic; -- Feedback Clock signal clk_compu : std_logic; -- Unbuffered Synthesized Clock signal clk_slowu : std_logic; -- Unbuffered Synthesized Clock begin clk_in : IBUFGDS port map( O => clk200, I => clk_p, IB => clk_n ); pll : PLLE2_BASE generic map ( CLKIN1_PERIOD => to_real(to_time(CLK_FREQ), 1 ns), DIVCLK_DIVIDE => CLK_DIVA, CLKFBOUT_MULT => CLK_MULA, CLKOUT0_DIVIDE => CLK_DIVB, CLKOUT1_DIVIDE => 100, STARTUP_WAIT => "true" ) port map ( CLKIN1 => clk200, CLKFBIN => clkfb, RST => '0', CLKOUT0 => clk_compu, CLKOUT1 => clk_slowu, CLKOUT2 => open, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, CLKFBOUT => clkfb, LOCKED => open, PWRDWN => '0' ); comp_buf : BUFG port map ( I => clk_compu, O => clk_comp ); slow_buf : BUFH port map ( I => clk_slowu, O => clk_slow ); -- No Reset rst <= '0'; end block blkGlobal; ----------------------------------------------------------------------------- -- Fan Control fan : entity PoC.io_FanControl generic map ( CLOCK_FREQ => CLK_SLOW_FREQ ) port map ( Clock => clk_slow, Reset => '0', Fan_PWM => FanControl_PWM, TachoFrequency => open ); ---------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_uart generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES, CLK_FREQ => integer(to_real(CLK_COMP_FREQ, 1 Hz)), BAUDRATE => BAUDRATE, SENTINEL => SENTINEL ) port map ( clk => clk_comp, rst => rst, rx => rx, tx => tx, avail => open ); cts <= rts; end rtl;

agpl-3.0

52cedee3da5d12d74f387ffd321e0930

malkadi/FGPU

RTL/FGPU_tb.vhd

-- libraries --------------------------------------------------------------------------------- {{{ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.math_real.all; library work; use work.all; use work.FGPU_definitions.all; use work.FGPU_simulation_pkg.all; ------------------------------------------------------------------------------------------------- }}} ENTITY FGPU_tb IS END FGPU_tb; ARCHITECTURE behavior OF FGPU_tb IS signal target_offset_addr : natural := 0; --2**(N+L+M-1+2); constant MAX_NDRANGE_SIZE : natural := 64*1024; -- constants and functions {{{ CONSTANT clk_period : time := 5000 ps; CONSTANT C_MAXI_ID_WIDTH : natural := 6; CONSTANT S_DATA_W : integer := 32; CONSTANT N_WF_WG_ADDR : natural := 0; CONSTANT WG_SIZE_DX_ADDR : integer := 7; CONSTANT N_WG_D0_ADDR : integer := 8; CONSTANT N_WG_D1_ADDR : integer := 9; CONSTANT SIZE_D0_ADDR : natural := 1; CONSTANT SIZE_D1_ADDR : natural := 2; CONSTANT SIZE_D2_ADDR : natural := 3; CONSTANT WG_SIZE_ADDR : natural := 11; CONSTANT PARAM_ADDR : natural := 16; CONSTANT N_WF_WG_POS : natural := 28; CONSTANT WG_SIZE_D0_POS : natural := 0; CONSTANT WG_SIZE_D1_POS : natural := 10; CONSTANT WG_SIZE_D2_POS : natural := 20; CONSTANT N_DIM_POS : natural := 30; CONSTANT N_WF_WG_W : natural := 4; CONSTANT WG_SIZE_POS : natural := 0; --}}} -- general signals {{{ signal start_debug : std_logic := '0'; signal clk : std_logic := '0'; signal nrst : std_logic := '0'; signal gmem_addr : unsigned(GMEM_ADDR_W-1 downto 0) := (others => '0'); signal gmem_wrData : std_logic_vector(GMEM_DATA_W-1 downto 0) := (others => '0'); signal gmem_we : std_logic := '0'; signal gmem_re : std_logic := '0'; signal new_kernel, finished_kernel : std_logic := '0'; signal written_count : integer := 0; signal gmem_rdData : std_logic_vector(GMEM_DATA_W-1 downto 0); signal gmem_wr_ack, gmem_rd_ack : std_logic := '0'; signal size : natural := 1024; signal size_0, size_1, size_2 : integer := MAX_NDRANGE_SIZE; signal problemSize_sig : natural := 16; -- }}} -- axi slave signals {{{ signal s0_awaddr : std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0) := (others=>'0'); signal s0_awprot : std_logic_vector(2 downto 0) := (others=>'0'); signal s0_awvalid : std_logic := '0'; signal s0_awready : std_logic := '0'; signal s0_wdata : std_logic_vector(S_DATA_W-1 downto 0) := (others=>'0'); signal s0_wstrb : std_logic_vector((S_DATA_W/8)-1 downto 0) := (others=>'0'); signal s0_wvalid : std_logic := '0'; signal s0_wready : std_logic := '0'; signal s0_bresp : std_logic_vector(1 downto 0) := (others=>'0'); signal s0_bvalid : std_logic := '0'; signal s0_bready : std_logic := '0'; signal s0_araddr : std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0) := (others=>'0'); signal s0_arprot : std_logic_vector(2 downto 0) := (others=>'0'); signal s0_arvalid : std_logic := '0'; signal s0_arready : std_logic := '0'; signal s0_rdata : std_logic_vector(S_DATA_W-1 downto 0) := (others=>'0'); signal s0_rresp : std_logic_vector(1 downto 0) := (others=>'0'); signal s0_rvalid : std_logic := '0'; signal s0_rready : std_logic := '0'; -- }}} -- axi master signals {{{ -- interface 0 {{{ -- ar channel signal m0_araddr : std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); signal m0_arlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m0_arsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m0_arburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m0_arvalid : std_logic := '0'; signal m0_arready : std_logic := '0'; signal m0_arid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel signal m0_rdata : std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); signal m0_rresp : std_logic_vector(1 downto 0):= (others=>'0'); signal m0_rlast : std_logic := '0'; signal m0_rvalid : std_logic := '0'; signal m0_rready : std_logic := '0'; signal m0_rid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- aw channel signal m0_awaddr : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal m0_awvalid : std_logic := '0'; signal m0_awready : std_logic := '0'; signal m0_awlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m0_awsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m0_awburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m0_awid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel signal m0_wdata : std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); signal m0_wstrb : std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); signal m0_wlast : std_logic := '0'; signal m0_wvalid : std_logic := '0'; signal m0_wready : std_logic := '0'; -- b channel signal m0_bvalid : std_logic := '0'; signal m0_bready : std_logic := '0'; signal m0_bid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); --}}} -- interface 1 {{{ -- ar channel signal m1_araddr : std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); signal m1_arlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m1_arsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m1_arburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m1_arvalid : std_logic := '0'; signal m1_arready : std_logic := '0'; signal m1_arid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel signal m1_rdata : std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); signal m1_rresp : std_logic_vector(1 downto 0):= (others=>'0'); signal m1_rlast : std_logic := '0'; signal m1_rvalid : std_logic := '0'; signal m1_rready : std_logic := '0'; signal m1_rid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- aw channel signal m1_awaddr : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal m1_awvalid : std_logic := '0'; signal m1_awready : std_logic := '0'; signal m1_awlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m1_awsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m1_awburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m1_awid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel signal m1_wdata : std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); signal m1_wstrb : std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); signal m1_wlast : std_logic := '0'; signal m1_wvalid : std_logic := '0'; signal m1_wready : std_logic := '0'; -- b channel signal m1_bvalid : std_logic := '0'; signal m1_bready : std_logic := '0'; signal m1_bid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); --}}} -- interface 2 {{{ -- ar channel signal m2_araddr : std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); signal m2_arlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m2_arsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m2_arburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m2_arvalid : std_logic := '0'; signal m2_arready : std_logic := '0'; signal m2_arid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel signal m2_rdata : std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); signal m2_rresp : std_logic_vector(1 downto 0):= (others=>'0'); signal m2_rlast : std_logic := '0'; signal m2_rvalid : std_logic := '0'; signal m2_rready : std_logic := '0'; signal m2_rid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- aw channel signal m2_awaddr : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal m2_awvalid : std_logic := '0'; signal m2_awready : std_logic := '0'; signal m2_awlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m2_awsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m2_awburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m2_awid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel signal m2_wdata : std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); signal m2_wstrb : std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); signal m2_wlast : std_logic := '0'; signal m2_wvalid : std_logic := '0'; signal m2_wready : std_logic := '0'; -- b channel signal m2_bvalid : std_logic := '0'; signal m2_bready : std_logic := '0'; signal m2_bid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); --}}} -- interface 3 {{{ -- ar channel signal m3_araddr : std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); signal m3_arlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m3_arsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m3_arburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m3_arvalid : std_logic := '0'; signal m3_arready : std_logic := '0'; signal m3_arid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel signal m3_rdata : std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); signal m3_rresp : std_logic_vector(1 downto 0):= (others=>'0'); signal m3_rlast : std_logic := '0'; signal m3_rvalid : std_logic := '0'; signal m3_rready : std_logic := '0'; signal m3_rid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- aw channel signal m3_awaddr : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal m3_awvalid : std_logic := '0'; signal m3_awready : std_logic := '0'; signal m3_awlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m3_awsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m3_awburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m3_awid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel signal m3_wdata : std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); signal m3_wstrb : std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); signal m3_wlast : std_logic := '0'; signal m3_wvalid : std_logic := '0'; signal m3_wready : std_logic := '0'; -- b channel signal m3_bvalid : std_logic := '0'; signal m3_bready : std_logic := '0'; signal m3_bid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); --}}} --}}} -- observation signals ----------------------------------------------------------------------------------{{{ signal cycles_total : nat_array(N_CU-1 downto 0) := (others=>0); signal cycles_busy : nat_array(N_CU-1 downto 0) := (others=>0); signal executing : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); ---------------------------------------------------------------------------------------------------------}}} BEGIN -- instantiate the Unit Under Test (UUT) {{{ uut: entity FGPU port map ( clk => clk, -- slave axi {{{ s0_awaddr => s0_awaddr, s0_awprot => s0_awprot, s0_awvalid => s0_awvalid, s0_awready => s0_awready, s0_wdata => s0_wdata, s0_wstrb => s0_wstrb, s0_wvalid => s0_wvalid, s0_wready => s0_wready, s0_bresp => s0_bresp, s0_bvalid => s0_bvalid, s0_bready => s0_bready, s0_araddr => s0_araddr, s0_arprot => s0_arprot, s0_arvalid => s0_arvalid, s0_arready => s0_arready, s0_rdata => s0_rdata, s0_rresp => s0_rresp, s0_rvalid => s0_rvalid, s0_rready => s0_rready, -- }}} -- axi master 0 {{{ -- ar channel m0_araddr => m0_araddr, m0_arlen => m0_arlen, m0_arsize => m0_arsize, m0_arburst => m0_arburst, m0_arvalid => m0_arvalid, m0_arready => m0_arready, m0_arid => m0_arid, -- r channel m0_rdata => m0_rdata, m0_rresp => m0_rresp, m0_rlast => m0_rlast, m0_rvalid => m0_rvalid, m0_rready => m0_rready, m0_rid => m0_rid, -- aw channel m0_awvalid => m0_awvalid, m0_awaddr => m0_awaddr, m0_awready => m0_awready, m0_awlen => m0_awlen, m0_awsize => m0_awsize, m0_awburst => m0_awburst, m0_awid => m0_awid, -- w channel m0_wdata => m0_wdata, m0_wstrb => m0_wstrb, m0_wlast => m0_wlast, m0_wvalid => m0_wvalid, m0_wready => m0_wready, -- bchannel m0_bvalid => m0_bvalid, m0_bready => m0_bready, m0_bid => m0_bid, -- }}} -- axi master 1 {{{ -- ar channel m1_araddr => m1_araddr, m1_arlen => m1_arlen, m1_arsize => m1_arsize, m1_arburst => m1_arburst, m1_arvalid => m1_arvalid, m1_arready => m1_arready, m1_arid => m1_arid, -- r channel m1_rdata => m1_rdata, m1_rresp => m1_rresp, m1_rlast => m1_rlast, m1_rvalid => m1_rvalid, m1_rready => m1_rready, m1_rid => m1_rid, -- aw channel m1_awvalid => m1_awvalid, m1_awaddr => m1_awaddr, m1_awready => m1_awready, m1_awlen => m1_awlen, m1_awsize => m1_awsize, m1_awburst => m1_awburst, m1_awid => m1_awid, -- w channel m1_wdata => m1_wdata, m1_wstrb => m1_wstrb, m1_wlast => m1_wlast, m1_wvalid => m1_wvalid, m1_wready => m1_wready, -- bchannel m1_bvalid => m1_bvalid, m1_bready => m1_bready, m1_bid => m1_bid, -- }}} -- axi master 2 {{{ -- ar channel m2_araddr => m2_araddr, m2_arlen => m2_arlen, m2_arsize => m2_arsize, m2_arburst => m2_arburst, m2_arvalid => m2_arvalid, m2_arready => m2_arready, m2_arid => m2_arid, -- r channel m2_rdata => m2_rdata, m2_rresp => m2_rresp, m2_rlast => m2_rlast, m2_rvalid => m2_rvalid, m2_rready => m2_rready, m2_rid => m2_rid, -- aw channel m2_awvalid => m2_awvalid, m2_awaddr => m2_awaddr, m2_awready => m2_awready, m2_awlen => m2_awlen, m2_awsize => m2_awsize, m2_awburst => m2_awburst, m2_awid => m2_awid, -- w channel m2_wdata => m2_wdata, m2_wstrb => m2_wstrb, m2_wlast => m2_wlast, m2_wvalid => m2_wvalid, m2_wready => m2_wready, -- bchannel m2_bvalid => m2_bvalid, m2_bready => m2_bready, m2_bid => m2_bid, -- }}} -- axi master 3 {{{ -- ar channel m3_araddr => m3_araddr, m3_arlen => m3_arlen, m3_arsize => m3_arsize, m3_arburst => m3_arburst, m3_arvalid => m3_arvalid, m3_arready => m3_arready, m3_arid => m3_arid, -- r channel m3_rdata => m3_rdata, m3_rresp => m3_rresp, m3_rlast => m3_rlast, m3_rvalid => m3_rvalid, m3_rready => m3_rready, m3_rid => m3_rid, -- aw channel m3_awvalid => m3_awvalid, m3_awaddr => m3_awaddr, m3_awready => m3_awready, m3_awlen => m3_awlen, m3_awsize => m3_awsize, m3_awburst => m3_awburst, m3_awid => m3_awid, -- w channel m3_wdata => m3_wdata, m3_wstrb => m3_wstrb, m3_wlast => m3_wlast, m3_wvalid => m3_wvalid, m3_wready => m3_wready, -- bchannel m3_bvalid => m3_bvalid, m3_bready => m3_bready, m3_bid => m3_bid, -- }}} nrst => nrst -- loc_mem_rdAddr_dummy => loc_mem_rdAddr_dummy ); --}}} -- instantiate globel memory & cram{{{ gmem_inst: entity global_mem generic map( MAX_NDRANGE_SIZE => MAX_NDRANGE_SIZE ) port map ( new_kernel => new_kernel, finished_kernel => finished_kernel, size_0 => size_0, size_1 => size_1, problemSize => problemSize_sig, target_offset_addr => target_offset_addr, -- AXI Slave Interface mx_arlen_awlen => m0_arlen, -- interface 0{{{ -- ar channel m0_araddr => m0_araddr, m0_arvalid => m0_arvalid, m0_arready => m0_arready, m0_arid => m0_arid, -- r channel m0_rdata => m0_rdata, m0_rlast => m0_rlast, m0_rvalid => m0_rvalid, m0_rready => m0_rready, m0_rid => m0_rid, -- aw channel m0_awvalid => m0_awvalid, m0_awaddr => m0_awaddr, m0_awready => m0_awready, m0_awid => m0_awid, -- w channel m0_wdata => m0_wdata, m0_wstrb => m0_wstrb, m0_wlast => m0_wlast, m0_wvalid => m0_wvalid, m0_wready => m0_wready, -- b channel m0_bready => m0_bready, m0_bvalid => m0_bvalid, m0_bid => m0_bid, --}}} -- interface 1 {{{ -- ar channel m1_araddr => m1_araddr, m1_arvalid => m1_arvalid, m1_arready => m1_arready, m1_arid => m1_arid, -- r channel m1_rdata => m1_rdata, m1_rlast => m1_rlast, m1_rvalid => m1_rvalid, m1_rready => m1_rready, m1_rid => m1_rid, -- aw channel m1_awvalid => m1_awvalid, m1_awaddr => m1_awaddr, m1_awready => m1_awready, m1_awid => m1_awid, -- w channel m1_wdata => m1_wdata, m1_wstrb => m1_wstrb, m1_wlast => m1_wlast, m1_wvalid => m1_wvalid, m1_wready => m1_wready, -- b channel m1_bready => m1_bready, m1_bvalid => m1_bvalid, m1_bid => m1_bid, --}}} -- interface 2 {{{ -- ar channel m2_araddr => m2_araddr, m2_arvalid => m2_arvalid, m2_arready => m2_arready, m2_arid => m2_arid, -- r channel m2_rdata => m2_rdata, m2_rlast => m2_rlast, m2_rvalid => m2_rvalid, m2_rready => m2_rready, m2_rid => m2_rid, -- aw channel m2_awvalid => m2_awvalid, m2_awaddr => m2_awaddr, m2_awready => m2_awready, m2_awid => m2_awid, -- w channel m2_wdata => m2_wdata, m2_wstrb => m2_wstrb, m2_wlast => m2_wlast, m2_wvalid => m2_wvalid, m2_wready => m2_wready, -- b channel m2_bready => m2_bready, m2_bvalid => m2_bvalid, m2_bid => m2_bid, --}}} -- interface 3 {{{ -- ar channel m3_araddr => m3_araddr, m3_arvalid => m3_arvalid, m3_arready => m3_arready, m3_arid => m3_arid, -- r channel m3_rdata => m3_rdata, m3_rlast => m3_rlast, m3_rvalid => m3_rvalid, m3_rready => m3_rready, m3_rid => m3_rid, -- aw channel m3_awvalid => m3_awvalid, m3_awaddr => m3_awaddr, m3_awready => m3_awready, m3_awid => m3_awid, -- w channel m3_wdata => m3_wdata, m3_wstrb => m3_wstrb, m3_wlast => m3_wlast, m3_wvalid => m3_wvalid, m3_wready => m3_wready, -- b channel m3_bready => m3_bready, m3_bvalid => m3_bvalid, m3_bid => m3_bid, --}}} clk => clk, nrst => nrst ); --}}} -- clock process definitions {{{ clk_process :process begin clk <= '0'; wait for clk_period; clk <= not clk; wait for clk_period; end process; --}}} -- stimuls process {{{ process -- variables {{{ variable tmp_integer : integer := 0; variable nStages, stageIndx, passIndx : integer := 0; variable wg_size : integer := 100; variable size_d0, size_d1, size_d2 : integer := MAX_NDRANGE_SIZE; variable wg_size_d0, wg_size_d1, wg_size_d2 : natural := 1; variable nDim : natural := 1; variable reduce_factor_sum : natural := 4; variable minReduceSize : natural := 8; variable problemSize : natural := 16; variable swap_base_target : boolean := false; --}}} -- procedures {{{ procedure swap_base_target_params is --{{{ variable tmp1, tmp2 : std_logic_vector(DATA_W-1 downto 0); begin s0_araddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_araddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_araddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+0,5)); s0_araddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; tmp1 := s0_rdata; s0_araddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_araddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_araddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+1,5)); s0_araddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; tmp2 := s0_rdata; s0_wdata <= tmp2; wait until rising_edge(clk); s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+0,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; s0_awvalid <= '0'; s0_wvalid <= '0'; wait until rising_edge(clk); s0_wdata <= tmp1; s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+1,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure write_param(factor: in integer; paramIndx: in integer) is --{{{ begin s0_wdata <= std_logic_vector(to_unsigned(factor, DATA_W)); wait until rising_edge(clk); s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+paramIndx,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure replace_target_addr is --{{{ variable target_param : natural := 0; begin case kernel_name is when floydwarshall => target_param := 0; when copy | bitonic | add_float | parallelSelection | sum_atomic | fft_hard | sobel | median | max_half_atomic => target_param := 1; when fadd | mat_mul | fir | xcorr | mul_float | fir_char4 => target_param := 2; when others => report "undefined kernel index" severity failure; end case; s0_araddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_araddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_araddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+target_param,5)); s0_araddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; s0_wdata <= std_logic_vector(unsigned(s0_rdata) + to_unsigned(target_offset_addr, DATA_W)); wait until rising_edge(clk); s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+target_param,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure write_WG_size_dx_sch_ram(nDim, wg_size_d0, wg_size_d1, wg_size_d2: in natural) is --{{{ begin s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 5) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(WG_SIZE_DX_ADDR,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_wdata(WG_SIZE_D0_POS+WG_SIZE_W downto WG_SIZE_D0_POS) <= std_logic_vector(to_unsigned(wg_size_d0, WG_SIZE_W+1)); s0_wdata(WG_SIZE_D1_POS+WG_SIZE_W downto WG_SIZE_D1_POS) <= std_logic_vector(to_unsigned(wg_size_d1, WG_SIZE_W+1)); s0_wdata(WG_SIZE_D2_POS+WG_SIZE_W downto WG_SIZE_D2_POS) <= std_logic_vector(to_unsigned(wg_size_d2, WG_SIZE_W+1)); s0_wdata(N_DIM_POS+1 downto N_DIM_POS) <= std_logic_vector(to_unsigned(nDim-1, 2)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure update_WG_size_sch_ram (val: in integer) is --{{{ begin s0_araddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_araddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_araddr(4 downto 0) <= std_logic_vector(to_unsigned(WG_SIZE_ADDR,5)); s0_araddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; s0_wdata <= s0_rdata; wait until rising_edge(clk); s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(WG_SIZE_ADDR,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_wdata(WG_SIZE_POS+WG_SIZE_W downto WG_SIZE_POS) <= std_logic_vector(to_unsigned(val, WG_SIZE_W+1)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure update_nWF_WG_sch_ram (val: in integer) is --{{{ begin s0_araddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_araddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_araddr(4 downto 0) <= std_logic_vector(to_unsigned(N_WF_WG_ADDR,5)); s0_araddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; s0_wdata <= s0_rdata; wait until rising_edge(clk); s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(N_WF_WG_ADDR,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_wdata(N_WF_WG_POS+N_WF_WG_W-1 downto N_WF_WG_POS) <= std_logic_vector(to_unsigned(val, N_WF_WG_W)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure write_cram ( addr: in integer; val: in integer) is -- {{{ begin s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "01"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 0) <= std_logic_vector(to_unsigned(addr,INTERFCE_W_ADDR_W-2)); s0_wdata <= std_logic_vector(to_unsigned(val, DATA_W)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure write_sch_ram ( addr: in integer; val: in integer) is -- {{{ begin s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 5) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(addr,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_wdata <= std_logic_vector(to_unsigned(val, DATA_W)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure clear_write_cache is --{{{ begin s0_awaddr <= std_logic_vector(to_unsigned(RcleanCache_addr, INTERFCE_W_ADDR_W)); s0_wdata <= X"0000_0000"; s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure set_write_cache is --{{{ begin s0_awaddr <= std_logic_vector(to_unsigned(RcleanCache_addr, INTERFCE_W_ADDR_W)); s0_wdata <= X"0000_0000"; s0_wdata(get_kernel_index(kernel_name)) <= '1'; s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure set_initialize is --{{{ begin s0_awaddr <= std_logic_vector(to_unsigned(RInitiate_addr, INTERFCE_W_ADDR_W)); s0_wdata <= X"0000_0000"; s0_wdata(get_kernel_index(kernel_name)) <= '1'; s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure clear_initialize is --{{{ begin s0_awaddr <= std_logic_vector(to_unsigned(RInitiate_addr, INTERFCE_W_ADDR_W)); s0_wdata <= X"0000_0000"; s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure start_kernel(initialize_gmem : in integer) is --{{{ begin s0_awaddr <= std_logic_vector(to_unsigned(Rstart_addr, INTERFCE_W_ADDR_W)); s0_wdata <= X"0000_0000"; s0_wdata(get_kernel_index(kernel_name)) <= '1'; s0_awvalid <= '1'; s0_wvalid <= '1'; if initialize_gmem /= 0 then new_kernel <= '1'; end if; size <= size_d0*size_d1*size_d2; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; new_kernel <= '0'; end procedure; --}}} procedure read_status0_reg( res: out std_logic_vector(DATA_W-1 downto 0)) is --{{{ begin s0_araddr <= std_logic_vector(to_unsigned(Rstat_addr, INTERFCE_W_ADDR_W)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; res := s0_rdata; wait until rising_edge(clk); end procedure; --}}} procedure wait_to_finish is --{{{ variable tmp : std_logic_vector(DATA_W-1 downto 0); begin read_status0_reg(tmp); while to_integer(unsigned(tmp)) = 0 loop read_status0_reg(tmp); end loop; finished_kernel <= '1'; wait until rising_edge(clk); finished_kernel <= '0'; -- wait for 20*clk_period; -- the finish flag is set when the last axi_write is issued. Some extra cycles are still needed end procedure; --}}} procedure download_code is --{{{ begin case kernel_name is when copy => --copy case COMP_TYPE is when 0 => -- byte write_cram(9, 16#71000462#); write_cram(10, 16#21000C64#); write_cram(11, 16#28001042#); write_cram(13, 16#79001062#); when 1 => --half write_cram(9, 16#72000462#); write_cram(10, 16#21001064#); write_cram(11, 16#28001042#); write_cram(13, 16#7A001062#); when others => -- word write_cram(9, 16#74000462#); write_cram(10, 16#00000000#); write_cram(11, 16#00000000#); write_cram(13, 16#7C001062#); end case; when others => end case; end procedure; --}}} -- }}} begin report "Kernel Nr. "& integer'image(get_kernel_index(kernel_name)); wait for clk_period; nrst <= '1'; wait for 2*clk_period; s0_rready <= '1'; case kernel_name is when mat_mul | median | floydwarshall | sobel => nDim := 2; when others => nDim := 1; end case; replace_target_addr; download_code; set_initialize; size_d2 := 1; for i in 1 to 64 loop -- wait for 2*clk_period; case kernel_name is when mat_mul | floydwarshall | median=> wg_size_d0 := 8; wg_size_d1 := 8; wg_size := wg_size_d0 * wg_size_d1; size_d0 := wg_size_d0*i; size_d1 := wg_size_d1*i; when sobel => wg_size_d0 := 4; wg_size_d1 := 4; problemSize := 16; size_d0 := 4; size_d1 := 4; wg_size := wg_size_d0 * wg_size_d1; when bitonic | fft_hard => wg_size_d0 := 64; size_d0 := 1024*i; -- size_d0 := wg_size_d0*2**(i-1); problemSize := size_d0*2; wg_size := wg_size_d0; when others => wg_size_d0 := 64; -- size_d0 := (i+8)*1024; size_d0 := 64*i; -- size_d0 := 128*2**(i-1); -- size_d0 := wg_size_d0*i; size_d1 := 1; wg_size_d1 := 1; wg_size := wg_size_d0; problemSize := REDUCE_FACTOR*size_d0; end case; problemSize_sig <= problemSize; assert wg_size <= WF_SIZE*8 severity failure; case kernel_name is when fft_hard => -- {{{ -- clear_write_cache; set_write_cache; set_initialize; nStages := 0; tmp_integer := 1; while tmp_integer < problemSize loop tmp_integer := tmp_integer * 2; nStages := nStages + 1; end loop; stageIndx := 0; report "problemSize = " & integer'image(problemSize) & ", nStages = " & integer'image(nStages); while stageIndx /= nStages loop report "stageIndx = " & integer'image(stageIndx); if (wg_size mod WF_SIZE ) = 0 then update_nWF_WG_sch_ram(wg_size/WF_SIZE-1); else update_nWF_WG_sch_ram(wg_size/WF_SIZE); end if; write_sch_ram(SIZE_D0_ADDR, size_d0); write_WG_size_dx_sch_ram(nDim, wg_size_d0, wg_size_d1, wg_size_d2); update_WG_size_sch_ram(wg_size); write_sch_ram(N_WG_D0_ADDR, max(size_d0/wg_size_d0-1, 0)); write_param(stageIndx, 1); size_0 <= size_d0; if stageIndx = 0 then start_kernel(1); else start_kernel(0); end if; stageIndx := stageIndx + 1; if stageIndx = nStages then set_write_cache; -- report "cache write set"; end if; wait_to_finish; clear_initialize; -- if stageIndx = 1 then -- start_debug <= '1'; -- end if; end loop; -- }}} when bitonic => -- {{{ -- clear_write_cache; set_write_cache; set_initialize; nStages := 0; tmp_integer := 1; while tmp_integer < problemSize loop tmp_integer := tmp_integer * 2; nStages := nStages + 1; end loop; stageIndx := 0; passIndx := 0; report "problemSize = " & integer'image(problemSize) & ", nStages = " & integer'image(nStages); write_param(0, 3); -- direction is decreasing while stageIndx /= nStages loop -- report "stageIndx = " & integer'image(stageIndx) & ", passIndx = " & integer'image(passIndx); if (wg_size mod WF_SIZE ) = 0 then update_nWF_WG_sch_ram(wg_size/WF_SIZE-1); else update_nWF_WG_sch_ram(wg_size/WF_SIZE); end if; write_sch_ram(SIZE_D0_ADDR, size_d0); write_WG_size_dx_sch_ram(nDim, wg_size_d0, wg_size_d1, wg_size_d2); update_WG_size_sch_ram(wg_size); write_sch_ram(N_WG_D0_ADDR, max(size_d0/wg_size_d0-1, 0)); write_param(stageIndx, 1); write_param(passIndx, 2); size_0 <= size_d0; if passIndx = 0 and stageIndx = 0 then start_kernel(1); else start_kernel(0); end if; if passIndx < stageIndx then passIndx := passIndx + 1; else passIndx := 0; stageIndx := stageIndx + 1; if stageIndx = nStages then set_write_cache; -- report "cache write set"; end if; end if; wait_to_finish; clear_initialize; if stageIndx = 1 and passIndx = 1 then start_debug <= '1'; end if; wait for 50*clk_period; end loop; -- wait for 100*clk_period; -- assert false severity failure; if kernel_name = bitonic then report "bitonic_kernel finished"; else report "bitonic_kernel_float finished"; end if; -- }}} when others => -- {{{ if (wg_size mod WF_SIZE ) = 0 then update_nWF_WG_sch_ram(wg_size/WF_SIZE-1); else update_nWF_WG_sch_ram(wg_size/WF_SIZE); end if; -- write_sch_ram(WG_SIZE_DX_ADDR, wg_size); write_sch_ram(SIZE_D0_ADDR, size_d0); write_sch_ram(SIZE_D1_ADDR, size_d1); write_sch_ram(SIZE_D2_ADDR, size_d2); write_WG_size_dx_sch_ram(nDim, wg_size_d0, wg_size_d1, wg_size_d2); update_WG_size_sch_ram(wg_size); write_sch_ram(N_WG_D0_ADDR, max(size_d0/wg_size_d0-1, 0)); write_sch_ram(N_WG_D1_ADDR, max(size_d1/wg_size_d1-1, 0)); if kernel_name = max_half_atomic or kernel_name = sum_atomic then write_param(REDUCE_FACTOR, 3); end if; size_0 <= size_d0; size_1 <= size_d1; set_write_cache; start_kernel(1); -- clear_initialize; wait_to_finish; -- }}} end case; end loop; report "END of simulation" severity failure; wait; end process; -- }}} -- observing the CVs load ------------------------------------------------------------------------------{{{ CV_load: if STAT_LOAD = 1 generate begin busy_calculation: for i in 0 to N_CU-1 generate begin process(clk) alias start_CUs is <<signal .FGPU_tb.uut.start_CUs : std_logic >>; alias wf_active is <<signal .FGPU_tb.uut.wf_active : wf_active_array >>; begin if rising_edge(clk) then if <<signal .FGPU_tb.uut.compute_units_i(i).compute_unit_inst.instr: std_logic_vector >> /= (0 to DATA_W-1 => '0') then cycles_busy(i) <= cycles_busy(i) + 1; end if; if start_CUs = '1' then cycles_busy(i) <= 0; end if; if wf_active(i) /= (0 to N_WF_CU-1=>'0') then executing(i) <= '1'; end if; if wf_active(i) = (0 to N_WF_CU-1=>'0') then executing(i) <= '0'; end if; if start_CUs = '1' then cycles_total(i) <= 0; end if; if executing(i) = '1' then cycles_total(i) <= cycles_total(i) + 1; end if; end if; end process; end generate; process(clk) alias start_CUs is <<signal .FGPU_tb.uut.start_CUs : std_logic >>; alias finish_exec is << signal .FGPU_tb.uut.finish_exec : std_logic >>; variable load_ratio : real_array(N_CU-1 downto 0); variable statistics_printed : std_logic := '0'; variable load_average : real; variable std : real; variable n_active_CUs: natural; begin if rising_edge(clk) then if start_CUs = '1' then statistics_printed := '0'; end if; if finish_exec = '1' and statistics_printed = '0' then statistics_printed := '1'; load_average := 0.0; std := 0.0; n_active_CUs := 0; for i in 0 to N_CU-1 loop if cycles_total(i) /= 0 then n_active_CUs := n_active_CUs + 1; load_ratio(i) := real((cycles_busy(i) * 100)) / real(cycles_total(i)); load_average := load_average + load_ratio(i); std := std + real(load_ratio(i)*load_ratio(i)); -- report "Average load on CU " & integer'image(i) & " is " & integer'image(integer(round(load_ratio(i)))) & "%"; end if; end loop; load_average := load_average / real(n_active_CUs); std := sqrt(std/real(n_active_CUs) - load_average*load_average); report "Average CU load is " & integer'image(integer(round(load_average))) & "% width stnadard deviation of " & integer'image(integer(round(std))) & "%"; end if; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- }}} END;

gpl-3.0

47b49f676b165af269e6e7064c11677b

malkadi/FGPU

RTL/rd_cache_fifo.vhd

-- libraries --------------------------------------------------------------------------------------------{{{ library ieee; use ieee.std_logic_1164.all; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity rd_cache_fifo is -- {{{ -- cu_mem_cntrl <- port A (myram) port B -> cache generic( SIZEA : integer := 1024; ADDRWIDTHA : integer := 10; SIZEB : integer := 256; ADDRWIDTHB : integer := 8 ); port( clk : in std_logic; push : in std_logic; cache_rdData : in std_logic_vector(DATA_W*CACHE_N_BANKS - 1 downto 0); cache_rdAddr : in unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); rdData : out std_logic_vector(DATA_W*RD_CACHE_N_WORDS - 1 downto 0); rdAddr : out unsigned(GMEM_WORD_ADDR_W-RD_CACHE_N_WORDS_W-1 downto 0) := (others=>'0'); nempty : out std_logic := '0'; nrst : in std_logic ); end entity; -- }}} architecture behavioral of rd_cache_fifo is function log2(val : INTEGER) return natural is -- {{{ variable res : natural; begin for i in 0 to 31 loop if (val <= (2 ** i)) then res := i; exit; end if; end loop; return res; end function Log2; -- }}} -- signals {{{ constant minWIDTH : integer := DATA_W*RD_CACHE_N_WORDS; constant maxSIZE : integer := SIZEA; constant RATIO : integer := CACHE_N_BANKS*DATA_W/minWIDTH; -- An asymmetric RAM is modeled in a similar way as a symmetric RAM, with an -- array of array object. Its aspect ratio corresponds to the port with the -- lower data width (larger depth) type ramType is array (natural range <>) of std_logic_vector(minWIDTH - 1 downto 0); -- cu_mem_cntrl <- port A (myram) port B -> cache signal data_fifo : ramType(0 to maxSIZE-1) := (others=>(others=>'0')); type addr_fifo_type is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-RD_CACHE_N_WORDS_W-1 downto 0); signal addr_fifo : addr_fifo_type(0 to maxSIZE-1) := (others=>(others=>'0')); signal data_fifo_rdData_n : std_logic_vector(DATA_W*RD_CACHE_N_WORDS-1 downto 0) := (others => '0'); signal data_fifo_rdData : std_logic_vector(DATA_W*RD_CACHE_N_WORDS-1 downto 0) := (others => '0'); signal addr_fifo_rdData_n : unsigned(GMEM_WORD_ADDR_W-RD_CACHE_N_WORDS_W-1 downto 0) := (others=>'0'); signal addr_fifo_rdData : unsigned(GMEM_WORD_ADDR_W-RD_CACHE_N_WORDS_W-1 downto 0) := (others=>'0'); signal addrA : unsigned(ADDRWIDTHA - 1 downto 0) := (others=>'0'); signal addrB : unsigned(ADDRWIDTHB - 1 downto 0) := (others=>'0'); signal enB, enA : std_logic := '0'; signal nempty_p0 : std_logic := '0'; -- }}} begin enB <= '1'; enA <= '1'; -- addr fifo -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then if enA = '1' then addr_fifo_rdData_n <= addr_fifo(to_integer(addrA)); end if; addr_fifo_rdData <= addr_fifo_rdData_n; end if; end process; rdAddr <= addr_fifo_rdData; process(clk) begin if rising_edge(clk) then for i in 0 to RATIO - 1 loop if enB = '1' then if push = '1' then addr_fifo(to_integer(addrB & to_unsigned(i, log2(RATIO)))) <= cache_rdAddr & to_unsigned(i, log2(RATIO)); end if; end if; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- data fifo -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then if enA = '1' then data_fifo_rdData_n <= data_fifo(to_integer(addrA)); end if; data_fifo_rdData <= data_fifo_rdData_n; end if; end process; rdData <= data_fifo_rdData; process(clk) begin if rising_edge(clk) then for i in 0 to RATIO - 1 loop if enB = '1' then if push = '1' then data_fifo(to_integer(addrB & to_unsigned(i, log2(RATIO)))) <= cache_rdData((i + 1) * minWIDTH - 1 downto i * minWIDTH); end if; end if; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} process(clk) begin if rising_edge(clk) then if addrA(addrA'high downto addrA'high-ADDRWIDTHB+1) /= addrB then nempty_p0 <= '1'; else nempty_p0 <= '0'; end if; nempty <= nempty_p0; if nrst = '0' then addrB <= (others=>'0'); addrA <= (others=>'0'); else if enB = '1' and push = '1' then addrB <= addrB + 1; end if; if addrA(addrA'high downto addrA'high-ADDRWIDTHB+1) /= addrB then addrA <= addrA + 1; end if; end if; end if; end process; end architecture;

gpl-3.0

5f674a0ef96d20cb5b4eb13c9a586ff1

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_4AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 2; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

a3968fbf9ed5a1eb58ed6c06ef906c37

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_tx_serializer.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_tx_serializer | -- | --------------------------------------------------------------------------------------------------- -- File wf_tx_serializer.vhd | -- | -- Description The unit is generating the nanoFIP FIELDRIVE outputs FD_TXD and FD_TXENA. | -- It is retreiving bytes of data from: | -- o the wf_production (from the CTRL byte until the MPS) | -- o WF_PACKAGE (FSS and FES bytes) | -- o and the wf_crc (FCS bytes). | -- | -- It encodes the bytes to the Manchester 2 (manch.)scheme and outputs one by one the| -- encoded bits on the moments indicated by the wf_tx_osc unit. | -- | -- Reminder of the Produced RP_DAT frame structure : | -- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ | -- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| | -- | -- |------------- Bytes from the wf_production -------------| | -- | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 07/2011 | -- Version v0.05 | -- Depends on wf_engine_control | -- wf_production | -- wf_tx_osc | -- wf_reset_unit | ---------------- | -- Last changes | -- v0.02 2009 PAS Entity Ports added, start of architecture content | -- v0.03 07/2010 EG timing changes; tx_sched_p_buff_i got 1 more bit | -- briefly byte_index_i needed to arrive 1 clock tick earlier | -- renamed from tx to tx_serializer; | -- STOP_TRANSMISSION state added for the synch of txena | -- v0.04 01/2011 EG SYNC_TO_TXCK state added to start always with the bits 1,2,3 of the | -- clock buffer available(tx_start_p_i may arrive at any time) | -- tx_completed_p_o signal added | -- v0.05 07/2011 EG bits_to_txd unit removed | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_tx_serializer --================================================================================================= entity wf_tx_serializer is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- Signals from the wf_production byte_i : in std_logic_vector (7 downto 0); -- byte to be delivered -- Signals from the wf_engine_control unit tx_start_p_i : in std_logic; -- indication for the start of the production byte_request_accept_p_i : in std_logic; -- indication that a byte is ready to be delivered last_byte_p_i : in std_logic; -- indication of the last data byte -- (CRC, FES not included) -- Signal from the wf_tx_osc tx_sched_p_buff_i : in std_logic_vector (c_TX_SCHED_BUFF_LGTH-1 downto 0); -- pulses for the transmission synchronization -- OUTPUTS -- Signal to the wf_engine_control unit tx_byte_request_p_o : out std_logic; -- request for a new byte tx_completed_p_o : out std_logic; -- pulse upon the end of transmission -- Signal to the wf_tx_osc unit tx_osc_rst_p_o : out std_logic; -- oscillator reset after a transmission error -- nanoFIP FIELDRIVE outputs tx_data_o : out std_logic; -- transmitter serial data tx_enable_o : out std_logic);-- transmitter enable end entity wf_tx_serializer; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_tx_serializer is -- FSM type tx_st_t is (IDLE, SYNC_TO_TXCK, SEND_FSS, SEND_DATA_BYTE, SEND_CRC_BYTES, SEND_FES, STOP_TRANSMISSION); signal tx_st, nx_tx_st : tx_st_t; signal s_prepare_to_produce, s_sending_fss, s_sending_data : std_logic; signal s_sending_crc, s_sending_fes, s_stop_transmission : std_logic; -- bits counter signal s_bit_index_decr_p,s_bit_index_load, s_bit_index_is_zero : std_logic; signal s_bit_index, s_bit_index_top : unsigned (4 downto 0); -- transmitter output signal s_txd : std_logic; -- byte to be transmitted signal s_data_byte : std_logic_vector (7 downto 0); signal s_data_byte_manch : std_logic_vector (15 downto 0); -- CRC calculations signal s_start_crc_p, s_data_bit_to_crc_p : std_logic; signal s_crc_bytes : std_logic_vector (15 downto 0); signal s_crc_bytes_manch : std_logic_vector (31 downto 0); -- independent timeout counter signal s_session_timedout : std_logic; --================================================================================================= -- architecture begin --================================================================================================= begin -- The signal tx_sched_p_buff_i is used for the scheduling of the state transitions of the machine -- as well as of the actions on the output signals. -- The following drawing shows the transitions of the signal tx_sched_p_buff_i with respect to -- the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit clock). -- FD_TXCK : _________|-------...---------|________...________|-------...---------|____ -- tx_sched_p_buff(3): |0|0|0|1 |0|0|0|1 -- tx_sched_p_buff(2): |0|0|1|0 |0|0|1|0 -- tx_sched_p_buff(1): |0|1|0|0 |0|1|0|0 -- tx_sched_p_buff(0): |1|0|0|0 |1|0|0|0 ---------------------- -- new byte request : ^ -- new byte ready : . . ^ -- 1st bit of new . . . . . . . . . . . . . . . . . .^ -- byte delivery : -- bit counter : [ 15 . . .][ 14 -- A new bit is delivered after the assertion of tx_sched_p_buff (1). -- The counter Outgoing_Bits_Index that keeps the index of a bit being delivered is updated after -- the delivery of the bit, after the tx_sched_p_buff (3) assertion. The counter is ahead of the -- bit being sent. -- In the sending_bytes state, where the unit is expecting data bytes from the wf_production, -- the unit delivers a request for a new byte after the tx_sched_p_buff (0) assertion, -- and when the Outgoing_Bits_Index counter is empty (which means that the last bit of a previous -- byte is now being delivered). -- The wf_engine_control responds to the request by sending a new address to the wf_production -- for the retrieval of a byte from the memory or the stand-alone bus. -- The byte becomes available at the byte_request_accept_p_i pulse, 2 cycles after the request, -- and starts being transmitted at the tx_sched_p_buff (1) of the next FD_TXCK cycle. -- The wf_engine_control is the one keeping track of the amount of bytes delivered and asserts -- the last_byte_p_i signal accordingly; after the arrival of this signal the serializer's FSM -- proceeds with the transmission of the CRC and the FES bytes and then goes back to IDLE. -- To add a robust layer of protection to the FSM, we have implemented a counter, dependent only -- on the system clock, that from any state can bring the FSM back to IDLE. At any bit rate the -- transmission of the longest RP_DAT should not last more than 35ms. Hence, we have generated a -- 21 bits (c_SESSION_TIMEOUT_C_LGTH) counter that will reset the machine if more than 52ms -- (complete 21 bit counter) have passed since it has left this IDLE state. --------------------------------------------------------------------------------------------------- -- Serializer's FSM -- --------------------------------------------------------------------------------------------------- -- Serializer's state machine: the state machine is divided in three parts (a clocked -- process to store the current state, a combinatorial process to manage state transitions and -- finally a combinatorial process to manage the output signals), which are the 3 processes that -- follow. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Synchronous process Serializer_FSM_Sync: Serializer_FSM_Sync: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' or s_session_timedout = '1' then tx_st <= IDLE; else tx_st <= nx_tx_st; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Combinatorial process Serializer_FSM_Comb_State_Transitions Serializer_FSM_Comb_State_Transitions: process (tx_st, tx_start_p_i, last_byte_p_i, s_bit_index_is_zero, tx_sched_p_buff_i) begin case tx_st is when IDLE => if tx_start_p_i = '1' then -- trigger from wf_engine_control nx_tx_st <= SYNC_TO_TXCK; else nx_tx_st <= IDLE; end if; when SYNC_TO_TXCK => -- synch to the free running FD_TXTCK if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-4) = '1' then nx_tx_st <= SEND_FSS; else nx_tx_st <= SYNC_TO_TXCK; end if; when SEND_FSS => -- delivery of 2 FSS bytes if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1) = '1') then nx_tx_st <= SEND_DATA_BYTE; else nx_tx_st <= SEND_FSS; end if; when SEND_DATA_BYTE => -- delivery of several data bytes -- until the last_byte_p_i notification if last_byte_p_i = '1' then nx_tx_st <= SEND_CRC_BYTES; else nx_tx_st <= SEND_DATA_BYTE; end if; when SEND_CRC_BYTES => -- delivery of 2 CRC bytes if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1') then nx_tx_st <= SEND_FES; -- state change early enough (tx_sched_p_buff_i(2)) -- for the Outgoing_Bits_Index, that is loaded on -- tx_sched_p_buff_i(3), to get the 31 as top value else nx_tx_st <= SEND_CRC_BYTES; end if; when SEND_FES => -- delivery of 1 FES byte if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1') then nx_tx_st <= STOP_TRANSMISSION; -- state change early enough (tx_sched_p_buff_i(2)) -- for the Outgoing_Bits_Index that is loaded on -- tx_sched_p_buff_i(3) to get the 15 as top value else nx_tx_st <= SEND_FES; end if; when STOP_TRANSMISSION => -- end of transmission synchronous to the FD_TXCK if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1' then nx_tx_st <= IDLE; else nx_tx_st <= STOP_TRANSMISSION; end if; when OTHERS => nx_tx_st <= IDLE; end case; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Combinatorial process Serializer_FSM_Comb_Output_Signals Serializer_FSM_Comb_Output_Signals: process ( tx_st ) begin case tx_st is when IDLE | SYNC_TO_TXCK => --------------------------------- s_prepare_to_produce <= '1'; --------------------------------- s_sending_fss <= '0'; s_sending_data <= '0'; s_sending_crc <= '0'; s_sending_fes <= '0'; s_stop_transmission <= '0'; when SEND_FSS => s_prepare_to_produce <= '0'; --------------------------------- s_sending_fss <= '1'; --------------------------------- s_sending_data <= '0'; s_sending_crc <= '0'; s_sending_fes <= '0'; s_stop_transmission <= '0'; when SEND_DATA_BYTE => s_prepare_to_produce <= '0'; s_sending_fss <= '0'; --------------------------------- s_sending_data <= '1'; --------------------------------- s_sending_crc <= '0'; s_sending_fes <= '0'; s_stop_transmission <= '0'; when SEND_CRC_BYTES => s_prepare_to_produce <= '0'; s_sending_fss <= '0'; s_sending_data <= '0'; --------------------------------- s_sending_crc <= '1'; --------------------------------- s_sending_fes <= '0'; s_stop_transmission <= '0'; when SEND_FES => s_prepare_to_produce <= '0'; s_sending_fss <= '0'; s_sending_data <= '0'; s_sending_crc <= '0'; --------------------------------- s_sending_fes <= '1'; --------------------------------- s_stop_transmission <= '0'; when STOP_TRANSMISSION => s_prepare_to_produce <= '0'; s_sending_fss <= '0'; s_sending_data <= '0'; s_sending_crc <= '0'; s_sending_fes <= '0'; --------------------------------- s_stop_transmission <= '1'; --------------------------------- when OTHERS => --------------------------------- s_prepare_to_produce <= '1'; --------------------------------- s_sending_fss <= '0'; s_sending_data <= '0'; s_sending_crc <= '0'; s_sending_fes <= '0'; s_stop_transmission <= '0'; end case; end process; --------------------------------------------------------------------------------------------------- -- Input Byte Retrieval -- --------------------------------------------------------------------------------------------------- Input_Byte_Retrieval: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_data_byte <= (others => '0'); else if byte_request_accept_p_i = '1' then s_data_byte <= byte_i; end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Manchester Encoding -- --------------------------------------------------------------------------------------------------- s_data_byte_manch <= f_manch_encoder (s_data_byte); s_crc_bytes_manch <= f_manch_encoder (s_crc_bytes); --------------------------------------------------------------------------------------------------- -- CRC calculation -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instantiation of the CRC unit crc_generation: wf_crc port map( uclk_i => uclk_i, nfip_rst_i => nfip_rst_i, start_crc_p_i => s_start_crc_p, data_bit_ready_p_i => s_data_bit_to_crc_p, data_bit_i => s_txd, crc_ok_p_o => open, ------------------------------------------------- crc_o => s_crc_bytes); ------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- concurrent signals assignement for the crc_generator inputs s_start_crc_p <= s_sending_fss and s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1); -- the CRC calculation starts when at the end of th e FSS (beginning of data bytes delivery) s_data_bit_to_crc_p <= s_sending_data and s_bit_index(0) and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1); -- only the 1st part of a manchester encoded bit goes to the CRC calculator --------------------------------------------------------------------------------------------------- -- Bits counter -- --------------------------------------------------------------------------------------------------- -- Managment of the pointer that indicates which bit of a manchester encoded byte is to be -- delivered. According to the state of the FSM, a byte may be a FSS one, or a data byte or a -- CRC or a FES byte. Outgoing_Bits_Index: wf_decr_counter generic map(g_counter_lgth => 5) port map( uclk_i => uclk_i, counter_rst_i => nfip_rst_i, counter_top_i => s_bit_index_top, counter_load_i => s_bit_index_load, counter_decr_i => s_bit_index_decr_p, ----------------------------------------------- counter_o => s_bit_index, counter_is_zero_o => s_bit_index_is_zero); ----------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- s_bit_index_top <= to_unsigned (15, s_bit_index'length) when s_sending_fss = '1' or s_sending_data = '1' else to_unsigned (s_crc_bytes_manch'length-1, s_bit_index'length) when s_sending_crc = '1' else to_unsigned (c_FES'length - 1, s_bit_index'length) when s_sending_fes = '1' else to_unsigned (c_FSS'length - 1, s_bit_index'length); s_bit_index_load <= (s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1)) when (s_sending_fss = '1' or s_sending_data = '1' or s_sending_crc = '1' or s_sending_fes = '1') else '1' when s_prepare_to_produce ='1' else '0'; s_bit_index_decr_p <= tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1) when (s_sending_fss = '1' or s_sending_data = '1' or s_sending_crc = '1' or s_sending_fes = '1') else '0'; --------------------------------------------------------------------------------------------------- -- Bits delivery -- --------------------------------------------------------------------------------------------------- -- Synchronous process Bits_Delivery: handling of nanoFIP output signal FD_TXD by -- placing bits of data according to the state of wf_tx_serializer's state machine and to the -- counter s_bit_index. The delivery takes place upon a tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3) -- pulse. Bits_Delivery: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_txd <= '0'; else if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3) = '1' then if s_sending_fss = '1' then s_txd <= c_FSS (to_integer (s_bit_index)); -- FSS: 2 bytes long (no need to resize) elsif s_sending_data = '1' then s_txd <= s_data_byte_manch (to_integer (resize(s_bit_index, 4))); -- 1 data-byte at a time elsif s_sending_crc = '1' then s_txd <= s_crc_bytes_manch (to_integer (s_bit_index)); -- CRC: 2 bytes long elsif s_sending_fes = '1' then s_txd <= c_FES(to_integer (resize(s_bit_index,4))); -- FES: 1 byte else s_txd <= '0'; end if; end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- TXENA generation -- --------------------------------------------------------------------------------------------------- -- Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the -- same moment as the first bit of the FSS starts being delivered and stays asserted until the -- end of the delivery of the last FES bit. FD_TXENA_Generator: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then tx_enable_o <= '0'; else if ((s_sending_fss = '1') or (s_sending_data = '1') or (s_sending_crc = '1') or (s_sending_fes = '1') or (s_stop_transmission = '1')) then -- tx sending bits if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3) = '1' then -- in order to synchronise the tx_enable_o <= '1'; -- activation of tx_enable with the -- the delivery of the 1st FSS bit end if; -- FD_TXD (FSS) :________|-----|___________|-------- -- tx_sched_p_buff(1):______|-|___|-|___|-|___|-|___|-|__ -- sending_FSS :___|------------------------------- -- FD_TXENA :________|-------------------------- else tx_enable_o <= '0'; end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Independent Timeout Counter -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instantiation of a wf_decr_counter relying only on the system clock as an additional -- way to go back to IDLE state, in case any other logic is being stuck. Session_Timeout_Counter: wf_decr_counter generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH) port map( uclk_i => uclk_i, counter_rst_i => nfip_rst_i, counter_top_i => (others => '1'), counter_load_i => s_prepare_to_produce, counter_decr_i => '1', -- on each uclk tick counter_o => open, --------------------------------------------------- counter_is_zero_o => s_session_timedout); --------------------------------------------------- --------------------------------------------------------------------------------------------------- -- Outputs -- --------------------------------------------------------------------------------------------------- tx_data_o <= s_txd; tx_osc_rst_p_o <= s_session_timedout; tx_completed_p_o <= s_stop_transmission and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2); tx_byte_request_p_o <= s_sending_data and s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-4); -- request for a new byte from the wf_prod_bytes_retriever unit (passing from wf_engine_control) end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

314e98af7d6ad5b29661ea69d7e9ca8b

alvieboy/iotpanel

cpld/tb.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:05:08 03/28/2015 -- Design Name: -- Module Name: /home/alvieboy/otpanel/cpld/tb.vhd -- Project Name: cpld -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: top -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; library work; use work.all; ENTITY tb IS END tb; ARCHITECTURE behavior OF tb IS -- Component Declaration for the Unit Under Test (UUT) --Inputs signal clk : std_logic := '0'; signal cs : std_logic := '0'; signal di : std_logic := '0'; --signal idtr : std_logic := '0'; signal gpio13 : std_logic := '0'; signal gpio14 : std_logic := '0'; signal esptx : std_logic := '0'; --BiDirs signal gpio2 : std_logic; signal gpio0 : std_logic; signal gpio5 : std_logic; signal gpio4 : std_logic; signal gpio16 : std_logic; signal gpio12 : std_logic; signal usr : std_logic_vector(6 downto 3); --Outputs signal rgb : std_logic_vector(5 downto 0); signal col : std_logic_vector(3 downto 0); signal stb : std_logic; signal clko : std_logic; signal espreset : std_logic; signal espen : std_logic; signal esprx : std_logic; --signal espchpd : std_logic; signal oe : std_logic; signal panelen : std_logic; -- Clock period definitions constant clk_period : time := 10 ns; -- constant clko_period : time := 10 ns; alias idtr:std_logic is usr(4); BEGIN usr(4) <= '1'; gpio16 <= '0'; -- Instantiate the Unit Under Test (UUT) uut: entity work.iotpanel PORT MAP ( clk => clk, cs => cs, --di => di, rgb => rgb, col => col, stb => stb, clko => clko, --idtr => idtr, gpio13 => gpio13, gpio14 => gpio14, espreset => espreset, espen => espen, esptx => esptx, esprx => esprx, gpio2 => gpio2, gpio0 => gpio0, gpio5 => gpio5, gpio4 => gpio4, --espchpd => espchpd, gpio16 => gpio16, gpio12 => di,--gpio12, oe => oe, panelen => panelen, usr => usr, iusr => 'X' ); -- Stimulus process stim_proc: process procedure transfer(data: in std_logic_vector; deassert: in boolean) is variable w,i: natural; variable d: std_logic_vector(data'high downto data'low); begin w := data'length; d := data; wait for clk_period/2; cs <= '0'; wait for clk_period/2; l1: for i in 0 to w-1 loop -- Setup data. di <= d(data'high); wait for clk_period/2; clk <= '1'; wait for clk_period/2; clk <= '0'; d := d(data'high-1 downto 0) & 'X'; end loop; wait for clk_period/2; if (deassert) then cs<='1'; end if; end procedure; begin -- hold reset state for 100 ns. cs <= '1'; wait for 100 ns; transfer("11" & "010"&"010"&'X', false); transfer("11" & "111"&"111"&'X', false); transfer("11" & "000"&"000"&'X', false); transfer("10" & "XXX"&"XXX"&'X', true); transfer("00" & "0001111", true); wait for 100 ns; wait; end process; END;

lgpl-3.0

def52c9beeba57b6de6a552f123e81de

malkadi/FGPU

RTL/regFile.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity regFile is port( rs_addr, rt_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 2. rd_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 2. re : in std_logic; -- level 2. rs : out std_logic_vector(DATA_W-1 downto 0):= (others=>'0'); -- level 7. rt : out std_logic_vector(DATA_W-1 downto 0):= (others=>'0'); -- level 6. rd : out std_logic_vector(DATA_W-1 downto 0):= (others=>'0'); -- level 8. we : in std_logic; -- level 18. wrAddr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 18. wrData : in std_logic_vector(DATA_W-1 downto 0); -- level 18. clk : in std_logic ); end entity; architecture Behavioral of regFile is -- signals definitions {{{ signal regFile_rdAddr : unsigned(REG_FILE_BLOCK_W-1 downto 0) := (others=>'0'); signal regFile_rdAddr_n : unsigned(REG_FILE_BLOCK_W-1 downto 0) := (others=>'0'); signal regFile_outData : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal regFile_outData_n : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal clk_stable_int : std_logic; signal regFile512: SLV32_ARRAY(0 to REG_FILE_BLOCK_SIZE-1) := (others => (others => '0')); type read_state_type is (prepare_rt_addr, read_rs, read_rt, read_rd); signal state, state_n : read_state_type := prepare_rt_addr; type read_state_vec_type is array (natural range<>) of read_state_type; signal state_vec : read_state_vec_type(5 downto 0) := (others=>prepare_rt_addr); signal rs_n, rt_n, rd_n : std_logic_vector(DATA_W-1 downto 0):= (others=>'0'); signal we_d0 : std_logic := '0'; signal wrAddr_clk2x : unsigned(REG_FILE_BLOCK_W-1 downto 0) := (others=>'0'); signal wrData_d0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal wrAddr_d0 : unsigned(REG_FILE_BLOCK_W-1 downto 0) := (others=>'0'); -- }}} begin process(state, re, rs_addr, rt_addr, rd_addr) begin state_n <= state; case state is when prepare_rt_addr => if re = '1' then -- level 2. state_n <= read_rt; end if; regFile_rdAddr_n <= rt_addr; when read_rt => -- level 3. regFile_rdAddr_n <= rs_addr; state_n <= read_rs; when read_rs => -- level 4. regFile_rdAddr_n <= rd_addr; state_n <= read_rd; when read_rd => -- level 5 regFile_rdAddr_n <= rd_addr; state_n <= prepare_rt_addr; end case; end process; process(clk) begin if rising_edge(clk) then state <= state_n; -- @ 3. reset not necesary since the FSM will go always to the first state and waits until re = '1' state_vec(state_vec'high-1 downto 0) <= state_vec(state_vec'high downto 1); -- @ 5.->8. state_vec(state_vec'high) <= state; -- @ 4. we_d0 <= we; -- @ 19. wrData_d0 <= wrData; -- @ 19. wrAddr_d0 <= wrAddr; -- @ 19. case state_vec(state_vec'high-1) is -- level 5. when prepare_rt_addr => when read_rt => rt <= regFile_outData; -- @ 6. when read_rs => rs <= regFile_outData; -- @ 7. when read_rd => rd <= regFile_outData; -- @ 8. end case; end if; end process; regFile_Instance: process (clk) begin if (clk'event and clk = '1') then regFile_rdAddr <= regFile_rdAddr_n; -- rt @ 3., rs @ 4., rd @ 5. if we_d0 = '1' then -- level 19. regFile512(to_integer(wrAddr_d0)) <= wrData_d0; -- @ 20. end if; regFile_outData_n <= regFile512(to_integer(regFile_rdAddr)); -- rt @ 4., rs @ 5., rd @ 6. regFile_outData <= regFile_outData_n; -- rt @ 5., rs @ 6., rd @ 7. end if; end process; end Behavioral;

gpl-3.0

a9abb0d367aa8a57baee23c71960a10f

preusser/q27

src/vhdl/PoC/common/utils.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Common functions and types -- -- Description: -- ------------------------------------- -- For detailed documentation see below. -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.math_real.all; library PoC; use PoC.my_config.all; package utils is -- PoC settings -- ========================================================================== constant POC_VERBOSE : boolean := MY_VERBOSE; -- Environment -- ========================================================================== -- Distinguishes simulation from synthesis constant SIMULATION : boolean; -- deferred constant declaration -- Type declarations -- ========================================================================== --+ Vectors of primitive standard types +++++++++++++++++++++++++++++++++++++ type T_BOOLVEC is array(natural range <>) of boolean; type T_INTVEC is array(natural range <>) of integer; type T_NATVEC is array(natural range <>) of natural; type T_POSVEC is array(natural range <>) of positive; type T_REALVEC is array(natural range <>) of REAL; --+ Integer subranges sometimes useful for speeding up simulation ++++++++++ subtype T_INT_8 is integer range -128 to 127; subtype T_INT_16 is integer range -32768 to 32767; subtype T_UINT_8 is integer range 0 to 255; subtype T_UINT_16 is integer range 0 to 65535; --+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Intellectual Property (IP) type type T_IPSTYLE is (IPSTYLE_HARD, IPSTYLE_SOFT); -- Bit Order type T_BIT_ORDER is (LSB_FIRST, MSB_FIRST); -- Byte Order (Endian) type T_BYTE_ORDER is (LITTLE_ENDIAN, BIG_ENDIAN); -- rounding style type T_ROUNDING_STYLE is (ROUND_TO_NEAREST, ROUND_TO_ZERO, ROUND_TO_INF, ROUND_UP, ROUND_DOWN); -- define a new unrelated type T_BCD for arithmetic -- QUESTION: extract to an own BCD package? -- => overloaded operators for +/-/=/... and conversion functions type T_BCD is array(3 downto 0) of std_logic; type T_BCD_VECTOR is array(natural range <>) of T_BCD; constant C_BCD_MINUS : T_BCD := "1010"; constant C_BCD_OFF : T_BCD := "1011"; subtype byte is std_logic_vector(7 downto 0); type byte_vector is array(natural range<>) of byte; -- Function declarations -- ========================================================================== --+ Division ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Calculates: ceil(a / b) function div_ceil(a : natural; b : positive) return natural; --+ Power +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- is input a power of 2? function is_pow2(int : natural) return boolean; -- round to next power of 2 function ceil_pow2(int : natural) return positive; -- round to previous power of 2 function floor_pow2(int : natural) return natural; --+ Logarithm ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Calculates: ceil(ld(arg)) function log2ceil(arg : positive) return natural; -- Calculates: max(1, ceil(ld(arg))) function log2ceilnz(arg : positive) return positive; -- Calculates: ceil(lg(arg)) function log10ceil(arg : positive) return natural; -- Calculates: max(1, ceil(lg(arg))) function log10ceilnz(arg : positive) return positive; --+ if-then-else (ite) +++++++++++++++++++++++++++++++++++++++++++++++++++++ function ite(cond : boolean; value1 : boolean; value2 : boolean) return boolean; function ite(cond : boolean; value1 : integer; value2 : integer) return integer; function ite(cond : boolean; value1 : REAL; value2 : REAL) return REAL; function ite(cond : boolean; value1 : std_logic; value2 : std_logic) return std_logic; function ite(cond : boolean; value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector; function ite(cond : boolean; value1 : bit_vector; value2 : bit_vector) return bit_vector; function ite(cond : boolean; value1 : unsigned; value2 : unsigned) return unsigned; function ite(cond : boolean; value1 : character; value2 : character) return character; function ite(cond : boolean; value1 : string; value2 : string) return string; -- conditional increment / decrement function inc_if(cond : boolean; value : integer; increment : integer := 1) return integer; function dec_if(cond : boolean; value : integer; decrement : integer := 1) return integer; --+ Max / Min / Sum ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ function imin(arg1 : integer; arg2 : integer) return integer; -- Calculates: min(arg1, arg2) for integers alias rmin is IEEE.math_real.realmin[real, real return real]; -- function rmin(arg1 : real; arg2 : real) return real; -- Calculates: min(arg1, arg2) for reals function imin(vec : T_INTVEC) return integer; -- Calculates: min(vec) for a integer vector function imin(vec : T_NATVEC) return natural; -- Calculates: min(vec) for a natural vector function imin(vec : T_POSVEC) return positive; -- Calculates: min(vec) for a positive vector function rmin(vec : T_REALVEC) return real; -- Calculates: min(vec) of real vector function imax(arg1 : integer; arg2 : integer) return integer; -- Calculates: max(arg1, arg2) for integers alias rmax is IEEE.math_real.realmax[real, real return real]; -- function rmax(arg1 : real; arg2 : real) return real; -- Calculates: max(arg1, arg2) for reals function imax(vec : T_INTVEC) return integer; -- Calculates: max(vec) for a integer vector function imax(vec : T_NATVEC) return natural; -- Calculates: max(vec) for a natural vector function imax(vec : T_POSVEC) return positive; -- Calculates: max(vec) for a positive vector function rmax(vec : T_REALVEC) return real; -- Calculates: max(vec) of real vector function isum(vec : T_NATVEC) return natural; -- Calculates: sum(vec) for a natural vector function isum(vec : T_POSVEC) return natural; -- Calculates: sum(vec) for a positive vector function isum(vec : T_INTVEC) return integer; -- Calculates: sum(vec) of integer vector function rsum(vec : T_REALVEC) return real; -- Calculates: sum(vec) of real vector --+ Conversions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- to integer: to_int function to_int(bool : boolean; zero : integer := 0; one : integer := 1) return integer; function to_int(sl : std_logic; zero : integer := 0; one : integer := 1) return integer; -- to std_logic: to_sl function to_sl(Value : boolean) return std_logic; function to_sl(Value : character) return std_logic; -- to std_logic_vector: to_slv function to_slv(Value : natural; Size : positive) return std_logic_vector; -- short for std_logic_vector(to_unsigned(Value, Size)) function to_BCD(Digit : integer) return T_BCD; function to_BCD(Digit : character) return T_BCD; function to_BCD(Digit : unsigned) return T_BCD; function to_BCD(Digit : std_logic_vector) return T_BCD; function to_BCD_Vector(Value : integer; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR; function to_BCD_Vector(Value : string; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR; -- TODO: comment function to_index(slv : unsigned; max : natural := 0) return integer; function to_index(slv : std_logic_vector; max : natural := 0) return integer; -- is_* function is_sl(c : character) return boolean; --+ Basic Vector Utilities +++++++++++++++++++++++++++++++++++++++++++++++++ -- Aggregate functions function slv_or (vec : std_logic_vector) return std_logic; function slv_nor (vec : std_logic_vector) return std_logic; function slv_and (vec : std_logic_vector) return std_logic; function slv_nand(vec : std_logic_vector) return std_logic; function slv_xor (vec : std_logic_vector) return std_logic; -- NO slv_xnor! This operation would not be well-defined as -- not xor(vec) /= vec_{n-1} xnor ... xnor vec_1 xnor vec_0 iff n is odd. -- Reverses the elements of the passed Vector. -- -- @synthesis supported -- function reverse(vec : std_logic_vector) return std_logic_vector; function reverse(vec : bit_vector) return bit_vector; function reverse(vec : unsigned) return unsigned; -- scale a value into a range [Minimum, Maximum] function scale(Value : integer; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; function scale(Value : REAL; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL; -- Resizes the vector to the specified length. The adjustment is make on -- on the 'high end of the vector. The 'low index remains as in the argument. -- If the result vector is larger, the extension uses the provided fill value -- (default: '0'). -- Use the resize functions of the numeric_std package for value-preserving -- resizes of the signed and unsigned data types. -- -- @synthesis supported -- function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector; function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector; -- Shift the index range of a vector by the specified offset. function move(vec : std_logic_vector; ofs : integer) return std_logic_vector; -- Shift the index range of a vector making vec'low = 0. function movez(vec : std_logic_vector) return std_logic_vector; function ascend(vec : std_logic_vector) return std_logic_vector; function descend(vec : std_logic_vector) return std_logic_vector; -- Least-Significant Set Bit (lssb): -- Computes a vector of the same length as the argument with -- at most one bit set at the rightmost '1' found in arg. -- -- @synthesis supported -- function lssb(arg : std_logic_vector) return std_logic_vector; function lssb(arg : bit_vector) return bit_vector; -- Returns the index of the least-significant set bit. -- -- @synthesis supported -- function lssb_idx(arg : std_logic_vector) return integer; function lssb_idx(arg : bit_vector) return integer; -- Most-Significant Set Bit (mssb): computes a vector of the same length -- with at most one bit set at the leftmost '1' found in arg. function mssb(arg : std_logic_vector) return std_logic_vector; function mssb(arg : bit_vector) return bit_vector; function mssb_idx(arg : std_logic_vector) return integer; function mssb_idx(arg : bit_vector) return integer; -- Swap sub vectors in vector (endian reversal) function swap(slv : std_logic_vector; Size : positive) return std_logic_vector; -- generate bit masks function genmask_high(Bits : natural; MaskLength : positive) return std_logic_vector; function genmask_low(Bits : natural; MaskLength : positive) return std_logic_vector; function genmask_alternate(len : positive; lsb : std_logic := '0') return std_logic_vector; --+ Encodings ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- One-Hot-Code to Binary-Code. -- If a non-negative value empty_val is specified, its unsigned -- representation will be returned upon an all-zero input. As a consequence -- of specifying this value, no simulation warnings will be issued upon empty -- inputs. Alleged 1-hot-encoded inputs with more than one bit asserted -- will always raise a simulation warning. function onehot2bin(onehot : std_logic_vector; empty_val : integer := -1) return unsigned; -- Converts Gray-Code into Binary-Code. -- -- @synthesis supported -- function gray2bin (gray_val : std_logic_vector) return std_logic_vector; -- Binary-Code to One-Hot-Code function bin2onehot(value : std_logic_vector) return std_logic_vector; -- Binary-Code to Gray-Code function bin2gray(value : std_logic_vector) return std_logic_vector; end package; package body utils is -- Environment -- ========================================================================== function is_simulation return boolean is variable ret : boolean; begin ret := false; -- WORKAROUND: for Xilinx ISE -- Version: all versions with enabled 'use_new_parser' option -- Issue: Is_X('X') does not evaluate to FALSE in synthesis -- Solution: Use '--synthesis translate_on/off' pragmas --synthesis translate_off if Is_X('X') then ret := true; end if; --synthesis translate_on return ret; end function; -- deferred constant assignment constant SIMULATION : boolean := is_simulation; -- Divisions: div_* -- =========================================================================== -- integer division; always round-up function div_ceil(a : natural; b : positive) return natural is -- calculates: ceil(a / b) begin return (a + (b - 1)) / b; end function; -- Power functions: *_pow2 -- ========================================================================== -- return TRUE, if input is a power of 2 function is_pow2(int : natural) return boolean is begin return ceil_pow2(int) = int; end function; -- round to next power of 2 function ceil_pow2(int : natural) return positive is begin return 2 ** log2ceil(int); end function; -- round to previous power of 2 function floor_pow2(int : natural) return natural is variable temp : unsigned(30 downto 0); begin temp := to_unsigned(int, 31); for i in temp'range loop if (temp(i) = '1') then return 2 ** i; end if; end loop; return 0; end function; -- Logarithms: log*ceil* -- ========================================================================== -- return log2; always rounded up function log2ceil(arg : positive) return natural is variable tmp : positive; variable log : natural; begin if arg = 1 then return 0; end if; tmp := 1; log := 0; while arg > tmp loop tmp := tmp * 2; log := log + 1; end loop; return log; end function; -- return log2; always rounded up; the return value is >= 1 function log2ceilnz(arg : positive) return positive is begin return imax(1, log2ceil(arg)); end function; -- return log10; always rounded up function log10ceil(arg : positive) return natural is variable tmp : positive; variable log : natural; begin if arg = 1 then return 0; end if; tmp := 1; log := 0; while arg > tmp loop tmp := tmp * 10; log := log + 1; end loop; return log; end function; -- return log2; always rounded up; the return value is >= 1 function log10ceilnz(arg : positive) return positive is begin return imax(1, log10ceil(arg)); end function; -- if-then-else (ite) -- ========================================================================== function ite(cond : boolean; value1 : boolean; value2 : boolean) return boolean is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : integer; value2 : integer) return integer is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : REAL; value2 : REAL) return REAL is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : std_logic; value2 : std_logic) return std_logic is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : bit_vector; value2 : bit_vector) return bit_vector is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : unsigned; value2 : unsigned) return unsigned is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : character; value2 : character) return character is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : string; value2 : string) return string is begin if cond then return value1; else return value2; end if; end function; -- conditional increment / decrement -- =========================================================================== -- return the by increment incremented Value if cond is true else passthrough Value function inc_if(cond : boolean; Value : integer; increment : integer := 1) return integer is begin if cond then return Value + increment; else return Value; end if; end function; -- return the by decrement decremented Value if cond is true else passthrough Value function dec_if(cond : boolean; Value : integer; decrement : integer := 1) return integer is begin if cond then return Value - decrement; else return Value; end if; end function; -- *min / *max / *sum -- =========================================================================== function imin(arg1 : integer; arg2 : integer) return integer is begin if arg1 < arg2 then return arg1; end if; return arg2; end function; -- function rmin(arg1 : real; arg2 : real) return real is -- begin -- if arg1 < arg2 then return arg1; end if; -- return arg2; -- end function; function imin(vec : T_INTVEC) return integer is variable Result : integer; begin Result := integer'high; for i in vec'range loop if (vec(i) < Result) then Result := vec(i); end if; end loop; return Result; end function; function imin(vec : T_NATVEC) return natural is variable Result : natural; begin Result := natural'high; for i in vec'range loop if (vec(i) < Result) then Result := vec(i); end if; end loop; return Result; end function; function imin(vec : T_POSVEC) return positive is variable Result : positive; begin Result := positive'high; for i in vec'range loop if (vec(i) < Result) then Result := vec(i); end if; end loop; return Result; end function; function rmin(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := REAL'high; for i in vec'range loop if vec(i) < Result then Result := vec(i); end if; end loop; return Result; end function; function imax(arg1 : integer; arg2 : integer) return integer is begin if arg1 > arg2 then return arg1; end if; return arg2; end function; -- function rmax(arg1 : real; arg2 : real) return real is -- begin -- if arg1 > arg2 then return arg1; end if; -- return arg2; -- end function; function imax(vec : T_INTVEC) return integer is variable Result : integer; begin Result := integer'low; for i in vec'range loop if (vec(i) > Result) then Result := vec(i); end if; end loop; return Result; end function; function imax(vec : T_NATVEC) return natural is variable Result : natural; begin Result := natural'low; for i in vec'range loop if (vec(i) > Result) then Result := vec(i); end if; end loop; return Result; end function; function imax(vec : T_POSVEC) return positive is variable Result : positive; begin Result := positive'low; for i in vec'range loop if (vec(i) > Result) then Result := vec(i); end if; end loop; return Result; end function; function rmax(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := REAL'low; for i in vec'range loop if vec(i) > Result then Result := vec(i); end if; end loop; return Result; end function; function isum(vec : T_INTVEC) return integer is variable Result : integer; begin Result := 0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; function isum(vec : T_NATVEC) return natural is variable Result : natural; begin Result := 0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; function isum(vec : T_POSVEC) return natural is variable Result : natural; begin Result := 0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; function rsum(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := 0.0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; -- Vector aggregate functions: slv_* -- ========================================================================== function slv_or(vec : std_logic_vector) return std_logic is variable Result : std_logic; begin Result := '0'; for i in vec'range loop Result := Result or vec(i); end loop; return Result; end function; function slv_nor(vec : std_logic_vector) return std_logic is begin return not slv_or(vec); end function; function slv_and(vec : std_logic_vector) return std_logic is variable Result : std_logic; begin Result := '1'; for i in vec'range loop Result := Result and vec(i); end loop; return Result; end function; function slv_nand(vec : std_logic_vector) return std_logic is begin return not slv_and(vec); end function; function slv_xor(vec : std_logic_vector) return std_logic is variable res : std_logic; begin res := '0'; for i in vec'range loop res := res xor vec(i); end loop; return res; end function; -- =========================================================================== -- Type conversion -- =========================================================================== -- Convert to integer: to_int function to_int(bool : boolean; zero : integer := 0; one : integer := 1) return integer is begin return ite(bool, one, zero); end function; function to_int(sl : std_logic; zero : integer := 0; one : integer := 1) return integer is begin if (sl = '1') then return one; end if; return zero; end function; -- Convert to bit: to_sl -- =========================================================================== function to_sl(Value : boolean) return std_logic is begin return ite(Value, '1', '0'); end function; function to_sl(Value : character) return std_logic is begin case Value is when 'U' => return 'U'; when '0' => return '0'; when '1' => return '1'; when 'Z' => return 'Z'; when 'W' => return 'W'; when 'L' => return 'L'; when 'H' => return 'H'; when '-' => return '-'; when others => return 'X'; end case; end function; -- Convert to vector: to_slv -- =========================================================================== -- short for std_logic_vector(to_unsigned(Value, Size)) -- the return value is guaranteed to have the range (Size-1 downto 0) function to_slv(Value : natural; Size : positive) return std_logic_vector is constant res : std_logic_vector(Size-1 downto 0) := std_logic_vector(to_unsigned(Value, Size)); begin return res; end function; -- Convert to T_BCD or T_BCD_VECTOR: to_BCD* -- =========================================================================== function to_BCD(Digit : integer) return T_BCD is begin return T_BCD(to_unsigned(Digit, T_BCD'length)); end function; function to_BCD(Digit : character) return T_BCD is begin return T_BCD(to_unsigned((character'pos(Digit) - CHARACTER'pos('0')), T_BCD'length)); end function; function to_BCD(Digit : unsigned) return T_BCD is begin return T_BCD(Digit); end function; function to_BCD(Digit : std_logic_vector) return T_BCD is begin return T_BCD(Digit); end function; function to_BCD_Vector(Value : integer; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is begin return to_BCD_Vector(integer'image(Value), Size, Fill); end function; function to_BCD_Vector(Value : string; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is variable Result : T_BCD_VECTOR(Size - 1 downto 0); begin Result := (others => Fill); for i in Value'range loop Result(Value'length - (i - Value'low) - 1) := to_BCD(Value(i)); end loop; return Result; end function; -- bound array indices for simulation, to prevent out of range errors function to_index(slv : unsigned; max : natural := 0) return integer is variable res : integer; begin if (slv'length = 0) then return 0; end if; res := to_integer(slv); if SIMULATION and max > 0 then res := imin(res, max); end if; return res; end function; -- bound array indices for simulation, to prevent out of range errors function to_index(slv : std_logic_vector; max : natural := 0) return integer is begin return to_index(unsigned(slv), max); end function; -- is_* -- =========================================================================== function is_sl(c : character) return boolean is begin case c is when 'U'|'X'|'0'|'1'|'Z'|'W'|'L'|'H'|'-' => return true; when others => return false; end case; end function; -- Reverse vector elements function reverse(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'range); begin for i in vec'low to vec'high loop res(vec'low + (vec'high-i)) := vec(i); end loop; return res; end function; function reverse(vec : bit_vector) return bit_vector is variable res : bit_vector(vec'range); begin res := to_bitvector(reverse(to_stdlogicvector(vec))); return res; end function; function reverse(vec : unsigned) return unsigned is begin return unsigned(reverse(std_logic_vector(vec))); end function; -- Swap sub vectors in vector -- ========================================================================== function swap(slv : std_logic_vector; Size : positive) return std_logic_vector is constant SegmentCount : natural := slv'length / Size; variable FromH : natural; variable FromL : natural; variable ToH : natural; variable ToL : natural; variable Result : std_logic_vector(slv'length - 1 downto 0); begin for i in 0 to SegmentCount - 1 loop FromH := ((i + 1) * Size) - 1; FromL := i * Size; ToH := ((SegmentCount - i) * Size) - 1; ToL := (SegmentCount - i - 1) * Size; Result(ToH downto ToL) := slv(FromH downto FromL); end loop; return Result; end function; -- generate bit masks -- ========================================================================== function genmask_high(Bits : natural; MaskLength : positive) return std_logic_vector is begin if (Bits = 0) then return (MaskLength - 1 downto 0 => '0'); else return (MaskLength - 1 downto MaskLength - Bits + 1 => '1') & (MaskLength - Bits downto 0 => '0'); end if; end function; function genmask_low(Bits : natural; MaskLength : positive) return std_logic_vector is begin if (Bits = 0) then return (MaskLength - 1 downto 0 => '0'); else return (MaskLength - 1 downto Bits => '0') & (Bits - 1 downto 0 => '1'); end if; end function; function genmask_alternate(len : positive; lsb : std_logic := '0') return std_logic_vector is variable curr : std_logic; variable res : std_logic_vector(len-1 downto 0); begin curr := lsb; for i in res'reverse_range loop res(i) := curr; curr := not curr; end loop; return res; end function; -- binary encoding conversion functions -- ========================================================================== -- One-Hot-Code to Binary-Code function onehot2bin(onehot : std_logic_vector; empty_val : integer := -1) return unsigned is variable res : unsigned(log2ceilnz(imax(onehot'high, empty_val)+1)-1 downto 0); variable chk : natural; begin -- Note: empty_val = 0 takes the regular path to reduce on synthesized hardware if empty_val > 0 and onehot = (onehot'range => '0') then res := to_unsigned(empty_val, res'length); else res := (others => '0'); chk := 0; for i in onehot'range loop if onehot(i) = '1' then res := res or to_unsigned(i, res'length); chk := chk + 1; end if; end loop; if SIMULATION and chk /= 1 and (chk > 1 or empty_val < 0) then report "Broken 1-Hot-Code with "&integer'image(chk)&" bits set." severity warning; res := (others => 'X'); -- computed result is implementation-dependant end if; end if; return res; end function; -- Gray-Code to Binary-Code function gray2bin(gray_val : std_logic_vector) return std_logic_vector is variable tmp : std_logic_vector(gray_val'length downto 0); variable res : std_logic_vector(gray_val'range); begin tmp := '0' & gray_val; for i in tmp'left-1 downto 0 loop tmp(i) := tmp(i+1) xor tmp(i); end loop; res := tmp(tmp'left-1 downto 0); return res; end function; -- Binary-Code to One-Hot-Code function bin2onehot(Value : std_logic_vector) return std_logic_vector is variable result : std_logic_vector(2**Value'length - 1 downto 0); begin result := (others => '0'); result(to_index(Value, 0)) := '1'; return result; end function; -- Binary-Code to Gray-Code function bin2gray(Value : std_logic_vector) return std_logic_vector is variable tmp : std_logic_vector(Value'length downto 0); variable res : std_logic_vector(Value'range); begin tmp := ('0' & Value) xor (Value & '0'); res := tmp(Value'length downto 1); return res; end function; -- bit searching / bit indices -- ========================================================================== -- Least-Significant Set Bit (lssb): computes a vector of the same length with at most one bit set at the rightmost '1' found in arg. function lssb(arg : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(arg'range); begin res := arg and std_logic_vector(unsigned(not arg)+1); return res; end function; function lssb(arg : bit_vector) return bit_vector is variable res : bit_vector(arg'range); begin res := to_bitvector(lssb(to_stdlogicvector(arg))); return res; end function; -- Most-Significant Set Bit (mssb): computes a vector of the same length with at most one bit set at the leftmost '1' found in arg. function mssb(arg : std_logic_vector) return std_logic_vector is begin return reverse(lssb(reverse(arg))); end function; function mssb(arg : bit_vector) return bit_vector is begin return reverse(lssb(reverse(arg))); end function; -- Index of lssb function lssb_idx(arg : std_logic_vector) return integer is begin return to_integer(onehot2bin(lssb(arg))); end function; function lssb_idx(arg : bit_vector) return integer is variable slv : std_logic_vector(arg'range); begin slv := to_stdlogicvector(arg); return lssb_idx(slv); end function; -- Index of mssb function mssb_idx(arg : std_logic_vector) return integer is begin return to_integer(onehot2bin(mssb(arg))); end function; function mssb_idx(arg : bit_vector) return integer is variable slv : std_logic_vector(arg'range); begin slv := to_stdlogicvector(arg); return mssb_idx(slv); end function; -- scale a value into a given range function scale(Value : integer; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin return scale(real(Value), Minimum, Maximum, RoundingStyle); end function; function scale(Value : REAL; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is variable Result : REAL; begin if (Maximum < Minimum) then return integer'low; else Result := real(Value) * ((real(Maximum) + 0.5) - (real(Minimum) - 0.5)) + (real(Minimum) - 0.5); case RoundingStyle is when ROUND_TO_NEAREST => return integer(round(Result)); when ROUND_TO_ZERO => report "scale: unsupported RoundingStyle." severity FAILURE; when ROUND_TO_INF => report "scale: unsupported RoundingStyle." severity FAILURE; when ROUND_UP => return integer(ceil(Result)); when ROUND_DOWN => return integer(floor(Result)); when others => report "scale: unsupported RoundingStyle." severity FAILURE; end case; end if; end function; function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL is begin if (Maximum < Minimum) then return REAL'low; else return Value * (Maximum - Minimum) + Minimum; end if; end function; function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector is constant high2b : natural := vec'low+length-1; constant highcp : natural := imin(vec'high, high2b); variable res_up : bit_vector(vec'low to high2b); variable res_dn : bit_vector(high2b downto vec'low); begin if vec'ascending then res_up := (others => fill); res_up(vec'low to highcp) := vec(vec'low to highcp); return res_up; else res_dn := (others => fill); res_dn(highcp downto vec'low) := vec(highcp downto vec'low); return res_dn; end if; end function; function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is constant high2b : natural := vec'low+length-1; constant highcp : natural := imin(vec'high, high2b); variable res_up : std_logic_vector(vec'low to high2b); variable res_dn : std_logic_vector(high2b downto vec'low); begin if vec'ascending then res_up := (others => fill); res_up(vec'low to highcp) := vec(vec'low to highcp); return res_up; else res_dn := (others => fill); res_dn(highcp downto vec'low) := vec(highcp downto vec'low); return res_dn; end if; end function; -- Move vector boundaries -- ========================================================================== function move(vec : std_logic_vector; ofs : integer) return std_logic_vector is variable res_up : std_logic_vector(vec'low +ofs to vec'high+ofs); variable res_dn : std_logic_vector(vec'high+ofs downto vec'low +ofs); begin if vec'ascending then res_up := vec; return res_up; else res_dn := vec; return res_dn; end if; end function; function movez(vec : std_logic_vector) return std_logic_vector is begin return move(vec, -vec'low); end function; function ascend(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'low to vec'high); begin res := vec; return res; end function; function descend(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'high downto vec'low); begin res := vec; return res; end function; end package body;

agpl-3.0

d6343845153176d97c82783bbc1968ad

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_rx_osc.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_rx_osc | -- | --------------------------------------------------------------------------------------------------- -- File wf_rx_osc.vhd | -- | -- Description Generation of the clock signals needed for the FIELDRIVE reception | -- | -- Even if the bit rate of the communication is known, jitter is expected to affect | -- the arriving time of the incoming signal. The main idea of the unit is to | -- recalculate the expected arrival time of the next incoming bit, based on the | -- arrival of the previous one, so that drifts are not accumulated. The clock | -- recovery is based on the Manchester 2 coding which ensures that there is one edge | -- (transition) for each bit. | -- | -- In this unit, we refer to | -- o a significant edge: for the edge of a manch. encoded bit (bit 0:_|-, bit 1: -|_)| -- o a transition : for the moment in between two adjacent bits, that may or | -- may not result in an edge (eg. a 0 followed by a 0 will give an edge _|-|_|-, | -- but a 0 followed by a 1 will not _|--|_ ). | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 14/02/2011 | -- Version v0.04 | -- Depends on wf_reset_unit | -- wf_deglitcher | -- wf_rx_deserializer | ------------------ | -- Last changes | -- 08/2009 v0.01 PS Entity Ports added, start of architecture content | -- 07/2010 v0.02 EG rx counter changed from 20 bits signed, to 11 bits unsigned; | -- rx clk generation depends on edge detection;code cleanedup+commented | -- rst_rx_osc signal clearified | -- 12/2010 v0.03 EG code cleaned-up | -- 01/2011 v0.031 EG rxd_edge_i became fd_rxd_edge_p_i; small correctiond on comments | -- 02/2011 v0.04 EG 2 units wf_rx_osc and wf_tx_osc; process replaced by wf_incr_counter | -- check for code violations removed completely | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_rx_osc --================================================================================================= entity wf_rx_osc is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- Signal from the wf_deglitcher unit fd_rxd_edge_p_i : in std_logic; -- indication of an edge on fd_rxd -- Signal from wf_rx_deserializer unit rx_osc_rst_i : in std_logic; -- resets the clock recovery procedure -- OUTPUTS -- Signals to the wf_rx_deserializer rx_manch_clk_p_o : out std_logic; -- signal with uclk-wide pulses -- o on a significant edge -- o between adjacent bits -- ____|-|___|-|___|-|___ rx_bit_clk_p_o : out std_logic; -- signal with uclk-wide pulses -- o between adjacent bits -- __________|-|_________ rx_signif_edge_window_o : out std_logic; -- time window where a significant edge is expected rx_adjac_bits_window_o : out std_logic); -- time window where a transition between adjacent -- bits is expected end entity wf_rx_osc; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_rx_osc is -- reception period counter signal s_period_c, s_period, s_margin : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0); signal s_half_period : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0); signal s_period_c_reinit, s_period_c_is_full : std_logic; -- windows formed, based on the counter signal s_adjac_bits_window, s_signif_edge_window : std_logic; -- fd_rxd signal combined with the windows signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic; -- clocks signal s_bit_clk, s_bit_clk_d1, s_manch_clk, s_manch_clk_d1 : std_logic; --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Generation of windows where edges/ transitions are expected -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- # uclk ticks for a bit period, defined by the WorldFIP bit rate s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i))); s_half_period <= s_period srl 1; -- 1/2 s_period s_margin <= s_period srl 3; -- margin for jitter defined as 1/8 of the period -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instantiation of a wf_incr_counter unit : the rx_counter starts counting after the -- release of the reset signal rx_osc_rst_i. This takes place after a falling edge on the -- filtered FD_RXD; this edge should be representing the 1st Manchester 2 (manch.) encoded bit '1' -- of the PREamble. Starting from this edge, other falling or rising significant edges, are -- expected around one period (s_period) later. A time window around the expected arrival time is -- set and its length is defined as 1/4th of the period (1/8th before and 1/8th after the expected -- time). When the actual edge arrives, the counter is reset. -- If that first falling edge of FD_RXD is finally proven not to belong to a valid PRE the counter -- is reinitialialized through the rx_osc_rst_i signal from the wf_rx_deserializer. rx_periods_count: wf_incr_counter generic map(g_counter_lgth => c_PERIODS_COUNTER_LGTH) port map( uclk_i => uclk_i, counter_reinit_i => s_period_c_reinit, counter_incr_i => '1', counter_is_full_o => open, ------------------------------------------ counter_o => s_period_c); ------------------------------------------ s_period_c_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- counter reinitialized: if nfip_rst_i is active or -- if rx_osc_rst_i is active or -- if an edge is detected in the expected window or -- if it fills up s_period_c_reinit <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i) or s_period_c_is_full; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Concurrent signal assignments: creation of the windows where -- "significant edges" and "adjacent bits transitions" are expected on the input signal. -- o s_signif_edge_window: extends s_margin uclk ticks before and s_margin uclk ticks after -- the completion of a period, where significant edges are expected. -- o s_adjac_bits_window : extends s_margin uclk ticks before and s_margin uclk ticks after -- the middle of a period, where transitions between adjacent bits are expected. s_signif_edge_window <= '1' when ((s_period_c < s_margin) or (s_period_c > s_period-1 - s_margin-1)) else '0'; s_adjac_bits_window <= '1' when ((s_period_c >= s_half_period-s_margin-1) and (s_period_c < s_half_period+s_margin)) else '0'; --------------------------------------------------------------------------------------------------- -- Clocks Generation -- --------------------------------------------------------------------------------------------------- -- Synchronous process rx_clks: the process rx_clk is following the edges that appear on the fd_rxd -- and constructs two clock signals: rx_manch_clk & rx_bit_clk. -- The signal rx_manch_clk: is inverted on each significant edge, as well as between adjacent bits -- The signal rx_bit_clk : is inverted only between adjacent bits -- The significant edges are normally expected inside the signif_edge_window. In the cases of a -- code violation (V+ or V-) no edge will arrive in this window. In this situation rx_manch_clk -- is inverted right after the end of the signif_edge_window. -- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive -- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window. rx_clks: process (uclk_i) begin if rising_edge (uclk_i) then if (nfip_rst_i = '1') then s_manch_clk <= '0'; s_bit_clk <= '0'; s_bit_clk_d1 <= '0'; s_manch_clk_d1 <= '0'; s_signif_edge_found <= '0'; s_adjac_bits_edge_found <= '0'; else -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- regarding significant edges: -- looking for a significant edge inside the corresponding window if (s_signif_edge_window='1') and (fd_rxd_edge_p_i='1') and (s_signif_edge_found='0') then s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk s_signif_edge_found <= '1'; -- indication that the edge was found s_adjac_bits_edge_found <= '0'; -- if a significant edge is not found where expected (code violation), the rx_manch_clk -- is inverted right after the end of the signif_edge_window. elsif (s_signif_edge_found = '0') and (s_period_c = s_margin) then s_manch_clk <= not s_manch_clk; s_adjac_bits_edge_found <= '0'; -- re-initialization before the -- next cycle -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- regarding edges between adjacent bits: -- looking for an edge inside the corresponding window elsif (s_adjac_bits_window = '1') and (fd_rxd_edge_p_i = '1') then s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk s_bit_clk <= not s_bit_clk; -- inversion of rx_bit_clk s_adjac_bits_edge_found <= '1'; -- indication that an edge was found s_signif_edge_found <= '0'; -- re-initialization before next cycle -- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right -- after the end of it elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_margin) then s_manch_clk <= not s_manch_clk; s_bit_clk <= not s_bit_clk; s_signif_edge_found <= '0'; -- re-initialization before next cycle end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- s_manch_clk_d1 <= s_manch_clk; -- s_manch_clk : ____|-----|_____|-----|____ -- s_manch_clk_d1 : ______|-----|_____|-----|__ -- rx_manch_clk_p_o : ____|-|___|-|___|-|___|-|__ s_bit_clk_d1 <= s_bit_clk; -- s_bit_clk : ____|-----------|__________ -- s_bit_clk_d1 : ______|-----------|________ -- rx_bit_clk_p_o : ____|-|_________|-|________ end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Concurrent signal assignments -- --------------------------------------------------------------------------------------------------- rx_manch_clk_p_o <= s_manch_clk_d1 xor s_manch_clk; -- a 1 uclk-wide pulse, after -- o a significant edge and -- o a new bit -- ___|-|___|-|___|-|___ rx_bit_clk_p_o <= s_bit_clk xor s_bit_clk_d1; -- a 1 uclk-wide pulse, after -- o a new bit -- _________|-|_________ rx_signif_edge_window_o <= s_signif_edge_window; rx_adjac_bits_window_o <= s_adjac_bits_window; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

da53ba137eb1edc68950129e732e1514

wltr/cern-fgclite

critical_fpga/src/rtl/cf/field_bus_timing.vhd

------------------------------------------------------------------------------- --! @file field_bus_timing.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-09 --! @brief Field-bus timing synchronization. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.cf_pkg.all; --! @brief Entity declaration of field_bus_timing --! @details --! Synchronize internal timing to COMMAND 0 of field-bus transmission. entity field_bus_timing is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Timing signals --! @{ --! Cycle synchronization marker cmd_0_i : in std_ulogic; --! Millisecond strobe ms_strobe_o : out std_ulogic; --! Millisecond period (nominally 40000 * 25 ns clock cycles) ms_period_i : in std_ulogic_vector(15 downto 0); --! Millisecond number (0-19) ms_number_o : out std_ulogic_vector(0 to 19); --! Field-bus cycle period in 25 ns clock cycles (nominally 800000) cycle_period_o : out std_ulogic_vector(19 downto 0)); --! @} end entity field_bus_timing; --! RTL implementation of field_bus_timing architecture rtl of field_bus_timing is --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal ms_period : std_ulogic_vector(15 downto 0); signal ms_number : unsigned(15 downto 0); signal ms_strobe_dlyd : std_ulogic; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal ms_strobe : std_ulogic; signal cmd_0 : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- ms_number_o(00) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 00) else '0'; ms_number_o(01) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 01) else '0'; ms_number_o(02) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 02) else '0'; ms_number_o(03) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 03) else '0'; ms_number_o(04) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 04) else '0'; ms_number_o(05) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 05) else '0'; ms_number_o(06) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 06) else '0'; ms_number_o(07) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 07) else '0'; ms_number_o(08) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 08) else '0'; ms_number_o(09) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 09) else '0'; ms_number_o(10) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 10) else '0'; ms_number_o(11) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 11) else '0'; ms_number_o(12) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 12) else '0'; ms_number_o(13) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 13) else '0'; ms_number_o(14) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 14) else '0'; ms_number_o(15) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 15) else '0'; ms_number_o(16) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 16) else '0'; ms_number_o(17) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 17) else '0'; ms_number_o(18) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 18) else '0'; ms_number_o(19) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 19) else '0'; ms_strobe_o <= ms_strobe_dlyd; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! Detect rising edges on COMMAND 0 input signal edge_detector_inst : entity work.edge_detector port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, en_i => '1', ack_i => '0', sig_i => cmd_0_i, edge_o => cmd_0); --! Millisecond strobe generator strobe_gen_inst : entity work.strobe_generator generic map ( init_value_g => 0, bit_width_g => 16) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, en_i => '1', period_i => ms_period, pre_i => cmd_0, pre_value_i => cmd_0_pre_value_c, strobe_o => ms_strobe); --! Field-bus cycle period counter stop_watch_inst : entity work.stop_watch generic map ( bit_width_g => 20) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, en_i => '1', sample_i => cmd_0, value_o => cycle_period_o); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin ms_period <= ms_period_c; ms_number <= to_unsigned(0, ms_number'length); ms_strobe_dlyd <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else ms_strobe_dlyd <= ms_strobe; if cmd_0 = '1' then ms_number <= to_unsigned(0, ms_number'length); elsif ms_strobe = '1' then if to_integer(ms_number) < 19 then ms_number <= ms_number + 1; else ms_number <= to_unsigned(0, ms_number'length); end if; end if; if ms_strobe = '1' and to_integer(ms_number) = 2 then ms_period <= ms_period_i; end if; end if; end if; end process regs; end architecture rtl;

mit

2e57f1b959100bcbf7baccd0fa7b1490

touilleMan/scrips

instmemory.vhd

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:21:35 05/08/2012 -- Design Name: -- Module Name: instmemory - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity instmemory is Port ( Address : in STD_LOGIC_VECTOR (31 downto 0); Instruction : out STD_LOGIC_VECTOR (31 downto 0)); end instmemory; architecture Behavioral of instmemory is begin process (Address) begin case Address is -- Main program when "00000000000000000000000000000000"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000000000100"=>Instruction<="00000000000000000011100000100101"; when "00000000000000000000000000001000"=>Instruction<="00000000000000000011000000100101"; when "00000000000000000000000000001100"=>Instruction<="00000000000000000010100000100101"; when "00000000000000000000000000010000"=>Instruction<="00000000000000000010000000100101"; when "00000000000000000000000000010100"=>Instruction<="00000000000000000001100000100101"; when "00000000000000000000000000011000"=>Instruction<="00000000000000000001000000100101"; when "00000000000000000000000000011100"=>Instruction<="00000000000000000000100000100101"; when "00000000000000000000000000100000"=>Instruction<="10101100000000000000000000010000"; when "00000000000000000000000000100100"=>Instruction<="10101100000000000000000000110001"; when "00000000000000000000000000101000"=>Instruction<="10101100000000000000000000110010"; when "00000000000000000000000000101100"=>Instruction<="10101100000000000000000000110011"; when "00000000000000000000000000110000"=>Instruction<="00110100000001000000000000000011"; when "00000000000000000000000000110100"=>Instruction<="00001000000000000000000000101111"; when "00000000000000000000000000111000"=>Instruction<="00110100000000010000000000011001"; when "00000000000000000000000000111100"=>Instruction<="00010000000000010000000000001001"; when "00000000000000000000000001000000"=>Instruction<="00100000001000011111111111111111"; when "00000000000000000000000001000100"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001001000"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001001100"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001010000"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001010100"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001011000"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001011100"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001100000"=>Instruction<="00001000000000000000000000001111"; when "00000000000000000000000001100100"=>Instruction<="00010000000000110000000000000100"; when "00000000000000000000000001101000"=>Instruction<="00100000011000111111111111111111"; when "00000000000000000000000001101100"=>Instruction<="00110100000000010000000000000001"; when "00000000000000000000000001110000"=>Instruction<="10101100000000010000000000110001"; when "00000000000000000000000001110100"=>Instruction<="00001000000000000000000000001110"; when "00000000000000000000000001111000"=>Instruction<="10101100000000000000000000110001"; when "00000000000000000000000001111100"=>Instruction<="00010000100000001111111111111111"; when "00000000000000000000000010000000"=>Instruction<="10001100000000010000000000110100"; when "00000000000000000000000010000100"=>Instruction<="00110000001000010000000000111111"; when "00000000000000000000000010001000"=>Instruction<="00010000001000000000000000011000"; when "00000000000000000000000010001100"=>Instruction<="00100000100001001111111111111111"; when "00000000000000000000000010010000"=>Instruction<="00110100000000010000000000000011"; when "00000000000000000000000010010100"=>Instruction<="00010000001001000000000000001001"; when "00000000000000000000000010011000"=>Instruction<="00110100000000010000000000000010"; when "00000000000000000000000010011100"=>Instruction<="00010000001001000000000000001010"; when "00000000000000000000000010100000"=>Instruction<="00110100000000010000000000000001"; when "00000000000000000000000010100100"=>Instruction<="00010000001001000000000000001011"; when "00000000000000000000000010101000"=>Instruction<="00001000000000000000000000111000"; when "00000000000000000000000010101100"=>Instruction<="00110100000000010000000000000001"; when "00000000000000000000000010110000"=>Instruction<="10101100000000010000000000110001"; when "00000000000000000000000010110100"=>Instruction<="00110100000000110110000110101000"; when "00000000000000000000000010111000"=>Instruction<="00001000000000000000000000001110"; when "00000000000000000000000010111100"=>Instruction<="00110100000000010000000001001111"; when "00000000000000000000000011000000"=>Instruction<="10101100000000010000000000110010"; when "00000000000000000000000011000100"=>Instruction<="00001000000000000000000000101011"; when "00000000000000000000000011001000"=>Instruction<="00110100000000010000000001011011"; when "00000000000000000000000011001100"=>Instruction<="10101100000000010000000000110010"; when "00000000000000000000000011010000"=>Instruction<="00001000000000000000000000101011"; when "00000000000000000000000011010100"=>Instruction<="00110100000000010000000000000110"; when "00000000000000000000000011011000"=>Instruction<="10101100000000010000000000110010"; when "00000000000000000000000011011100"=>Instruction<="00001000000000000000000000101011"; when "00000000000000000000000011100000"=>Instruction<="00110100000000010000000000111111"; when "00000000000000000000000011100100"=>Instruction<="10101100000000010000000000110010"; when "00000000000000000000000011101000"=>Instruction<="00001000000000000000000000101011"; when "00000000000000000000000011101100"=>Instruction<="10001100000001010000000000110000"; when "00000000000000000000000011110000"=>Instruction<="00110000101000010000000000000001"; when "00000000000000000000000011110100"=>Instruction<="00010000001000000000000000000011"; when "00000000000000000000000011111000"=>Instruction<="00110100000000010000000000000111"; when "00000000000000000000000011111100"=>Instruction<="10101100000000010000000000110011"; when "00000000000000000000000100000000"=>Instruction<="00001000000000000000000001000010"; when "00000000000000000000000100000100"=>Instruction<="10101100000000000000000000110011"; when "00000000000000000000000100001000"=>Instruction<="00010000110000000000000000000010"; when "00000000000000000000000100001100"=>Instruction<="00100000110001101111111111111111"; when "00000000000000000000000100010000"=>Instruction<="00001000000000000000000000001110"; when "00000000000000000000000100010100"=>Instruction<="00110000101000010000000000000010"; when "00000000000000000000000100011000"=>Instruction<="00010000001000000000000000000001"; when "00000000000000000000000100011100"=>Instruction<="00001000000000000000000001100000"; when "00000000000000000000000100100000"=>Instruction<="00110000101000010000000000000100"; when "00000000000000000000000100100100"=>Instruction<="00010000001000000000000000000001"; when "00000000000000000000000100101000"=>Instruction<="00001000000000000000000001001110"; when "00000000000000000000000100101100"=>Instruction<="00110100000001100000000010100111"; when "00000000000000000000000100110000"=>Instruction<="10101100000001110000000000010000"; when "00000000000000000000000100110100"=>Instruction<="00001000000000000000000000001110"; when "00000000000000000000000100111000"=>Instruction<="00110000111000010000000000001111"; when "00000000000000000000000100111100"=>Instruction<="00110100000000100000000000000001"; when "00000000000000000000000101000000"=>Instruction<="00010000001000100000000000000110"; when "00000000000000000000000101000100"=>Instruction<="00110100000000100000000000000010"; when "00000000000000000000000101001000"=>Instruction<="00010000001000100000000000000110"; when "00000000000000000000000101001100"=>Instruction<="00110100000000100000000000000100"; when "00000000000000000000000101010000"=>Instruction<="00010000001000100000000000000110"; when "00000000000000000000000101010100"=>Instruction<="00110100000000010000000000000001"; when "00000000000000000000000101011000"=>Instruction<="00010000000000000000000000000110"; when "00000000000000000000000101011100"=>Instruction<="00110100000000010000000000000010"; when "00000000000000000000000101100000"=>Instruction<="00010000000000000000000000000100"; when "00000000000000000000000101100100"=>Instruction<="00110100000000010000000000000100"; when "00000000000000000000000101101000"=>Instruction<="00010000000000000000000000000010"; when "00000000000000000000000101101100"=>Instruction<="00110100000000010000000000001000"; when "00000000000000000000000101110000"=>Instruction<="00010000000000000000000000000000"; when "00000000000000000000000101110100"=>Instruction<="00110000111001111111111111110000"; when "00000000000000000000000101111000"=>Instruction<="00000000111000010011100000100101"; when "00000000000000000000000101111100"=>Instruction<="00010000000000001111111111101011"; when "00000000000000000000000110000000"=>Instruction<="00110000111000010000000011110000"; when "00000000000000000000000110000100"=>Instruction<="00110100000000100000000000010000"; when "00000000000000000000000110001000"=>Instruction<="00010000001000100000000000001100"; when "00000000000000000000000110001100"=>Instruction<="00110100000000100000000000100000"; when "00000000000000000000000110010000"=>Instruction<="00010000001000100000000000000100"; when "00000000000000000000000110010100"=>Instruction<="00110100000000100000000001000000"; when "00000000000000000000000110011000"=>Instruction<="00010000001000100000000000000100"; when "00000000000000000000000110011100"=>Instruction<="00110100000000100000000010000000"; when "00000000000000000000000110100000"=>Instruction<="00010000001000100000000000000100"; when "00000000000000000000000110100100"=>Instruction<="00110100000000010000000000010000"; when "00000000000000000000000110101000"=>Instruction<="00010000000000000000000000000110"; when "00000000000000000000000110101100"=>Instruction<="00110100000000010000000000100000"; when "00000000000000000000000110110000"=>Instruction<="00010000000000000000000000000100"; when "00000000000000000000000110110100"=>Instruction<="00110100000000010000000001000000"; when "00000000000000000000000110111000"=>Instruction<="00010000000000000000000000000010"; when "00000000000000000000000110111100"=>Instruction<="00110100000000010000000010000000"; when "00000000000000000000000111000000"=>Instruction<="00010000000000000000000000000000"; when "00000000000000000000000111000100"=>Instruction<="00110000111001111111111100001111"; when "00000000000000000000000111001000"=>Instruction<="00000000111000010011100000100101"; when "00000000000000000000000111001100"=>Instruction<="00010000000000001111111111010100"; when others => Instruction <= "00000000000000000000000000000000"; End case; end process; end Behavioral;

mit

5548f7e21e4b841379d1d51520335d4f

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_mux.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block O+CNhRO2jpNpLYirT91PosAB0GPlv1fr/fRbZpGSAEpjuuZ2iwl3NN/1tsB2X5Ealflo+PrKhmBU Oor0p+/BTQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block aiZwqO5NkeR+mb9Httn86aLRz4MWEyJzTbe0FkOj6GK19Bz/s5xpJv4wBKYU7utf5uZuqMMFrb6E eLJAKrGr3w3WJeUG6sP0GBICaQjhBwcV7z+710jDBzD0CPhX+eXctHa8nj6rw2MzNdZEes3iUcjl XuHsaZ8Xz5ziVqOOZQE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block pZPxVP0hQ3SMQnu1fK8WaXVHpfFEIM5tYr/Y1RmRks9V3O7tes2uXtza43kvkW3muI0HZLKLK8Rt oSzxXc6w8RsuVss6KdcSSo/JnU5VoSXZaNebzlkCnsZmGxxXKsJrI4p4PUfqFku1a1yVLfe/81UF so3TnGqTRCpNB+qyUteEI0/F2pv5CCCiEhp0HXrPgBQiNnhuiqwtSI8bhdHCgneHHNCsAtc/Qs6/ sqjlnQlasTAfFlxDbdDpJBS9ZstkkKPZaOpNVZDA/6neHasYflU4l5JTm8GPD9i3YCTt9dC2aKJZ OdYmlxjpdLQJwsIoCPz5eU57+2LFIv4+kPeBkA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block dJ/NZQjE3OboqP9Rqsm7/5f1i0MCfkoXRNyrRm9j1ZciwBFzS9PI+ez9XHOJovcsYJg1Mxkqmi+Y /z4AdIKcEJdxK1y/rTa++CApP0w1Vqpihd1Be3hePYAoogRXJb+X1DCalPfiuerbiJkTxya3G2LQ AqjUEZFOd+gKErhwatY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tvVguDJS/GcQxQ858BERkpxg1AI6D29mwx09m+VZOIP13wzF31i2SbuNBD8Z4VXoVOXHA3n5T1pZ xECH8beGxuqj7heqq8TM9ZMJYrS9dt+/ZNKdyhs1IY/L8UW3384FFbiw+Nd9uT+5BSh5+fu6sgLR b/SgmXa4iR+uZOfTNurxlAa1R6LBUxRcpzAB1sSKkkiKDRJxq470s1oXJq5mydPqC87Fn4g1LKtm 0eyhEmMfJ80172lcR77+vFKY0qy0vfMMLlFwVNdy6MLLn1H4zj4QSRCe23UHb9XBFSQjHnDCKGv9 BDnvo7cIydzHEOe7CA9KLcAmNmeygGDrouh4Ow== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 70192) `protect data_block bgxx8cjvpggnSfsCqsnwkxRG7tqrjByreIqnWIr+zXwtL1kcLGcVcGUUiUzSM4JqgHslBTgGQntn e88e+3AUZJgdEl3A/ryz72gMHZ0Dn/EmsuKpJW++Dlbu4oO6DPNlfYaEJf/+aZCHk4ucNMLjZUM6 qFHuGsBmMKIK3pcX7/I0gqPDzShwSvQFb2hfB+LDyOhZCQHkzK0NR5RWenlH2Pv2FQ1NYMrRiN4f Hzqg+V8A1CbW+XkmS76jKwjviOK3ETID6jRVe7J5XfdrCtSKUmtrrgle9tPaaKK0nN400RdqLePQ ZivKtg4zfa71pj5uTKPxHs7OAbTFZzR81CpsBewjIdz+yo4TslTNstxyK4UtI5aRNS9Cczj1/vUo LJeQppDicoX4yMZZzIUZXXy9ghavcNZfIAj3SxpS7ncrWhT6PXfAZ8qQB/6cfRWoG5e1rXscHXDu PiH9ZHrvHdAnW1ZyNIN0n2Ti0AKwpekZsCgaAG6scsFjiCNPKEsF3HipktCaR6yZO50Xb+ZBGYME K8DSN9FvRKMWwBPxmY38o4Bf8WxkjF4r1mb9DH398Ntxk7p2dUYpu3DIfg2IgyGdOPtY88Y7VfT1 fY6UuG5LbiLxU7TY+ciWhvRLkfUwKe6YXbkCnMf1gVaFAi1biksb62NyL4U360l0ZKd3B9enNqDn kxWwa62rtv/eSbL3uRGCvmpSJmReiYyFO+twWF4wtxT4k8l7/KhdfOkAPkXM+0KQ47+rqBMSrVY9 gB32lfwuxkiqqeQyigqI3C5xq9E7JgJC/RMDJusmYRpOnyLruKF5/7D2PFVtx2RwZkr9EmPIetjn 4B+w8tIZ5seB7erxM0baLymEFgUdrGU1FkLP8dIHHEXu0w2VoYyJTOlIt+feR3dWQmvCRVFoiN35 qVQff0JqQunBVmR/Z9K6DNyof+Ue/8VoRSKmll8ZQKy15+dKKPGkHhJCzHm9MRr9vuCC8eeIcOgB io9vzAf76SPjdp2qBZ+R/kry/Pbmp1huD9POaSVrgnvTLFj9aH4x++REgzcWZmqOkkVEs6FtkPB/ Z0mAX8bDK8Nz+G/FbYPMzd7UMTp5oUN/U6TLT/tmbDC8zr/8KET+/1zxdpszsKm0SCnlcmR+aGqx voWyMcmZRe1ojxzmSyTr5AoPA5Vh/PwGFuL+Di9JugvjJzIWX7TiH+UrCHUwmMXqJwub+jS2wW+0 jtPcDdju0uF/vKNIaK4w5BW3BQkLjsDd6sbMkVW5SSTyOdEH2q766x+Ks/KhhYnKewjqrqHeXiIN f+HEAk0nFGEMWuj4pymfZC6jPV+tfaracMXYv8ocT7cUMQbvxfD9CvHEBcEmoDrdZ8nvQ6NNDWgz 2pUR1IEiqkQqTcHHvkr6LPXmBdEf/35mA/FDTXuJ8QT1uJCBcy+HbhYluLgb5ZmxCgGPAF8nAv0H gWRR0Ttsitut5XZY9Kaqb7aeUP1gl84zm9vuE16dh5jXWDrJleDxpir69Y1M067/R6mnUIiWMiky XHUv4vJ7tQ7DyQwG5YT7ggK/IQuoTfEMNm3g4bx9oASqIcd4Q/086vYNRhIg0gKXFnXpjHjER+EM fss9s+DmV/Pkt5JyF4nbxnda2gysaDyL1mjAtDrIG95FphpHiptSfsLK9+ZdI4rwPDjyhuJRDhXC IO7Mzw1W+Zh8MUWjNgNtC995G1wYWR0+oJc/jvKAdx7GDpuc+08h8F/OI8nDjm5qf8LZYB9/klAr Sp8JJfpwYw3jNbAGRWOTirfYVAHDoaKXmZMZ8WZfj5BmymZJ4QrOJT4cbyzV9FAU56POReyNjf8D lc1G+O8on+4HzjHMFArs6FL6QtUM5KmH4/2eQWITjGIhdMMZgJRRXdpT42eccPY3Sjc43WdrqV53 UQEyWRDwkrrinEAWAHtMVH+7p/BwX0JBInSikHaHH5GwtFQrEeN7gGMOjA86V0wawTkFDDlql6U1 uHTrm9qerS4OuwKik53Wt5ap0MYMemdgC/e+2w5UzwMI9hHwMFLX0LE3wEN1nekhoZcX2B/UE05B dKlA3zJwUjYikW+6+JG+5KKd+nlwey22iKAb3NfYXQ9959CVWsz3H+sGobsBKyaNZmPCQiI84t0k QVL+CdWIl87kz8Z72fGZwTmPwc/9XlEbPDpCqE1YqCrn3HGcBHmgOsJ5rBg4XOYJ748MIyBJ1S/5 gRFjnj8uP1oeGS7nHlaPggygPj2QWGsBGJEMKVtg5pmcD6vl4jQVTdVo7kTO1BlZjpikpj/sMwVr v1OU+7AB+sftAmSHZiW9ULz1lmx2rVeopPM8DsOKgdXHgzG9Kw5z0nGrWRIp3gQKFSbRyq6zTFAU 6PuvuKSIiULxnOsKWHE3fHZ5TgxjQn1uoABKGIK3Y7/4CikvHA4xIZDfuswqZExsxzAo70u1x6ga PdE7VzcisE56HO4E0xVP0urFjfPaK4h2X0NcJGJZzclSK3wvIcSjDb1RIUCbG2/abPSFwqPIEZr0 o+CxyC3T+OqHhq/XHiIHJrgIqtGA/jKUJ2W6rCnsGGZzMElB4N5p/R4hCsoI2+hblh0be78Lv//O iIvnblF2XR+ktZBTPlZuDHJLe81tPdWZrDl1msdsLtQfnfKRFP6X3zzof8iSB1e5RXISPJLLTtZG bteVhZzL3EXYkYGkaHZZOnn1mN2fFjsqTKEVDhuNE5u7yIJkpAM0V6yRfTFBfLm9JiRD8WDCiEhv C5vd9mBipRdQXTfgTEftieGi+zIcEWA252HaSjaPkitOpZGfIWFnQl0vQX6cAq6k7eNUJh+LtswG FsUkDjSLqazjPR7EmtwEkckNsMWgR72eia3q3/SRLqvovPPCdvGuroj6E6LewxgnA8LYOGFAl5zt Cmg5Tpd/YDDAK57wL9dt948CH1cMd4pQQOXqzWqisHkSYwc5tYRW9SNM0JzlfIimvXemxzhaqDIb QQrG24x6fiqthQ+k7tC+L3eTKW2or8addBz0//yHa3iujWnVJ+SYmCnAZSDpg08i/WkyXPkN8WzM KwGPG+PTSSOKsG1v0p1RrcS/CYTLQWZ2qnc/ueGJ12rdMoeFTptS/VBksqRHrj3JHuS9FYGvy1/a 03O7lyC1WjZpqwwI3np5EG+opWodpyizLZ0//39PgkQUWNcFiH6IKSn64PFqDGwHN4Hj7fqphqud oPzuLI50TzZ2+woQqL+NgxKzM+TyA9C3iYkC4k41IDQbNKs5K4u8e7bnDzXvnnFZQPmNTq/0duaW PZvYrVILmJkg7fqQpqNL+Dn4Jkc937cqfTvEg3o7Ek6t1RO5uclLu7RcQmPrxrlCiT6YAMA04UN+ yc4KDcsE/dDiAg1jf3gixobugSGj42x/ahcW4Vx8hHA8CVrmtXNkUw6qQ8j6cLPMbrdvY206w0Se v5xV8TpSGhTB3Dlp5OKn9VjdN5yCu24nvHLKZk1y7cA2O1YHsTCtuXtz7ptaQkoEaFdGYKQnZNrr oHykX1hLgEptJj1j7JP76aK4ApvofV8maaezQI3cRCnsKM/2GLkrDwOCekmEGMdycQfF7EWY43t8 B6FwtFdAUF1N1Xw+zuk0yp0zlLQNLu7TE3jhleCEF1xvdBUn2ACkHxAnaJchwJnaP/XhShFt+woC y1BiMqAK8tXmXd7Ip8vLcTn/horxR6sMw1jSytHQWYOZ7pcXtGM6VsjTQsR0NpTJSN+FV5lpN76Y 2BhG63hGnXdJCDgqIisccnpy37IBt7U2VIo1f0OvDhjUhITNTkHJo3kfl/MZwmJA3CakLlnLXXG2 zEYlme992FVw7TqIshnsS6ma/Ps3zk+2xqU+Pab8v1Q/0aEPx8PtoCDNH/wyuhys7cpMFDoOKK0p zkPnPWxCElLx/j8jqgrJCfUIzbnpbpvLjOI8/hOn/DEgk/W1q+UHfBd6m6h+GZEupV4tsE3uLmtP YfSurZBcmbXVD7BG1OUBt7O8jEpEJdpK+xrGUoZh8OzY/UXz4zI3pKWXLdQ6mjfjNUGxFByNEf5i Yb2YTdjt/GFHrEJxv4QycsDRBsatLkXXZXI80e0UZAr6bV4XXmmlCExLRKTYUIKi7G50oedwEOQd cGZUZRUBG/mpsiyadiMqEFoF8NTsy+UimkRbz1RbddROm3vM7Rv9WEy38+HZcAi7OhA1j20Uvgba gJMjBHop9HFUhNQ2odGBkT3sg6WM6fvb6E80/MUfGGRzs71rOAJOxFOsMFinoDPZMdNBE82lV8TS JkPLVt0kHpC0aLU3H+ugMGN40zPyvb3ZkMdi6OuMFyio7PXQV42puZxnXH/N3MpNPCfvVOBud6Fq VyNIIVjqopeVS4tb1ByZI2MHOOqUpnzVrLQeFZ7vpX7R+UHXJP3ZM4XzJqELW2OlJ0hPf/3Mjr+V 79wyALoDdGFTTtgib/gTgHFkSNcROCIQ+Jb5AuBZhKQ1eewBM4MbaTCWo+JnYRiVDP6BZB0gbzZD 05VvxktYwAHk5oFJjEKnpOvh0jIHYigavzIgrVVqFZ4YPSUcEA4OODkzlxJ31luhAm27+yDT7812 N4wobZupXJgCAtsw+TVYBO6mqer8c48lHgCSiJzA78aDGE1+iesUSMEVcP6oKUZRarSAsEsOGrtY 3pLhQ6fjSNrJ45A3hpmwHdSvbu4u5mRPJcsiEJGi40XkdcG+lJh+etO5tiRSg3TXmnpCWRttvHSi 7L9+ov+py7khPCqHZJ5nerochH4nXEEPvOxWdlvUuUW4WbzKK5C6/5VsAYGqlVSNcRLxobn7ILPm EfNWtLT7A0Se/kP7WyiR//khYSj9Qryp8Ok13ZxZisTrUBylS9Exne2n6svFLQA5YPLjafoVKm01 /7J8n10i3ZS693S+RD0qeB+xwKIhsx8vcXEGHXPJajHnOQ/qtZUU2RCzA9eSAMPIWwzm+736/edA Q585qaYoxTPWumnRFkrECUXIGkbZ1NHVyDlHLlzDNjGorzRJeH1qPwEAkHfnru0lpG3OJeTSrmp3 kcAaBSHcbJ0qhqodsRrMaBi98QGLFduIKQ2STZ1yuUiPFdmYcL8phhBYcKw3IUvl3NWIixEG7J0y QIgZfe8TOnQvPAEcXjdf/r2e2gQ+Jd8A3nk0Ja/fQbCkTXBpKnx+VtJ7A3iZ9FpvqAfuS5ahFFW6 oWiTL6xu3i+H53EvKJ1F7ROidO0618VkBfpalR5oa2IsaEFfN4N/SzHuqe/RXiswDQ2qCJJo0csG u9Kve39wYhBzvqHd7ffq5HjHY8xTXcEIpq+Sz/e4+IpZ5M2epXh3ktzHoxxYPUkUigOLphep8rSE lkk36q0L6maQ8g8tBTxsbDpXU2Obs3SWl31zdsktJ1B/T3ZNAy2Nwq1cA8/qPAyrurXX/1Qa8Oih ZoUuBoY0t66phGNX+i5YFuGS46wupElBz9e7pK4XkjVUOv0LRHfV7I59Wno6k8Hogymaw63URQaq FN8Me2Aa3n3ZwxZfd8dLLhOEYXOy6iz0ZzpQYkQ0xZUN672MBS1DCMzrlvnF19cptgL8pLVpyD2J smY3xVrfeXsUJKSK8VRGha9gpmRPIkyxCiyf2i0KraLkqTnLkNIjD1dqDjQTdFeuAm91XzvWqjz8 50vjvt6U9r7zcsWM2Yz9eoBD/6IRIwTC72gtaKZKAHVrwB0PdwNThJURaIw1GpycqBhELu5UsCbI pvB4u9maTF4AeIw4vnqBssJmlB7XyxDiHkteH5axIPFx66pQ42J8aYdPEp12qkOgJtiKbzJ6SytU YmxzSTaF4D5/tZmBrhkS7sfXoLbdkmswATaTFcA09zRp4KS4vgl2F7ilCNbEnaUydachnMxdy1wk 6uaR6mn+/LWTHTavOVe//kr9poc55UqgAGI7R4eH6DNTiypTwxF5ursAIN0OZAyiXkqcFDOdtX/g 6RfII+Vf3I0HhOiEeUu3i+yz3iAxnU+rMx216HqtWUsg1if4g0VqGgXy4c3gZZf8X6l0/nvxGNir NeFR++xjTH7V5R8ibq4SP5Yhniv362U5MpqqpCW3qEM4KTXnN6jxBMnwM4aIBQ1qTG5GfeAEyzM3 5XwaAs/hd3D0HGQgEk4Pd7h+40ALdbCxMOY3ip7EzPG7uLfyvmv0y26BYpPvYLrH2NJIMZqKU0pp vn1VFAPMg38c/5+m7wOIU60B29yCKSpyXpp+reWvlCY/0efAQemeXmRr5ky8M+ZHgtW0Is/Ai3o8 /F9/azDfbrgUYmprCQ8eYdfgH0BEccLLJ7VdH8nsWhxiW3zIXxo0NAbemneBK3M19GTV5qUCcU90 cGyyvdcZlmT/Uy1aSlJAoaAqn6Tmx9A7BpXl4JfEPjKGyDRQRF1+cNxeOEBjo1QbmdFcRk/hDsSs l9o0QCN0t4FKjmBgF+0laTHRmyWBHtdOpxsO3yBDPXWl7N2eA/lqasf4AWdQ9k0dJ7yeUrYRArZF XmfdCfdUcl7BmImHtcOFIjzjHP+FKL9FUwyiGylHAg+3L9MAyfZNIWrPbt3/JfdMhGvo1dFfQv6l vTy31a7xiVFQhN56VocZuSaVmtZS0w/npnqrPqlt2rq77O3KdkgExcXLjBT2k7tYoUqQYRpfBn5G OOYviYiNcE6LNC/YBcOzDZ5A5pmws6TIUmciDNSGQaSoNiMp71mrHQgGfwrU1MaJMymUxsvznswg HoniP4vGpLmMbaLn/eIQ3I+pDSUDukzthrI5tU2Z95aWCvjfq39UtnXVk5WWES3cgJ2Ouk2TAat9 ZQd7IOi2wdD4ckKYymW7+5QLfW0Qh7TxG0rFZwAGHnBzrKaL812k6P485wiqZZEQFh5by6OTS9je iPqVPN/uK9ldtxg9Y9WZqSNLy2fdsFCJL7Qua0f4Y1vukiYsnyUSMwVPWJSommSLjh5IV3K7bDam b8ZMRnStBrwTojZoA/muHsMVbfvXf1P58xvDlZt0IJ81HCHWFOtFf6RINmvXvUNbdwobqBtHxkQv 6hUVkVvL3reUCF75Qxb1LoKHCd2E9Cx5Ann2OGxjqMFsPgajojx5psbw8gW/hCEvnT9ZmdRg2jTD LgVJCLbQj30meacnLclbB2X8u4QWSaVdlbKBM1Jxn8Zul29y8UAWIih68Jf4VrR66NcP7YrJcVPC WqBWtvs0ycMTKcqXwxia7L6u1n5amSnRZCU/7nydCptOInJ44eBV+Rau3oxnqy2yVIyYht2kxMx1 17AaBqdaTUtRYjPZ0bss7s6juByTWPvhvIf67ZK5SMRmlnX4kkYWUK9PkxbXtKTjNBMuid0wBQm9 9FUFYi0/DcJGxGt7Gidt075dl36eWCudkgn3jIMsjLiqIsqXBAXLU4pJHo9+pAKlirmRDV1Z4+7Z zjPnyTBPjEKjxgvOJywnqK1GoiPzCIK0U/nkFI21eYSzj7eIJwEvO7kBRrDqzngzBnSp3sAeHtJb cptDlKTt5ewEVLdPn6pfBNQVbSMXT6O1FnEj4CFaneZWv0vFLSDupsfL98SeSSBvUtotMWj2692x QbhzDSsd4pFbUWloziQYrcrOmKCVSnO05AQ9bNxJObx2Et0oxNrt4gRG7b2SLYeZT06oxw9DsrrW o3GvxgeSSh5wGWSgG6dcjzODhYNVYq36UvTm+ilJPTAsZb/cTLu0Bc9lmtURb+w5ssoJtKKjTrd5 /mJy6Kv/JZuyhd6LxHqIRs+OjoQN2uLv0oMM9HRL13gN4hU1CO1QRaMnfz7Gx4w1/SS7RpenEx+N D2MIohg4JxZClVpW2iZa4CEIdFnLe+mKoeAx3a/EgxCVMISPQFrTJ3C5scW+bnsEmVuc1DQtAv9t PL2v3Y+69SeA2HFDDtpxl+s8GyLcsBhX6YXv01fqKBYfY/lx/eVh/bgJEMlMs7PBlMco4dAhcXOE BxuZoaImKsqei9g3jfv8tL6mHS3g9aobGevLI1NTVChRbaZUZBksf15v2mP6/bSw1xVAHKFR1IXM BJrlFgK2bLnL1fMwiu3xAEtlDJShXNa0aPbwGChG6tMPPSx/bLEPUzSHqgUBDdjhW8eujE8424nG J3iwerV1pWalER+5U0bsFRHUPm3/Wsz8DbM+xFH5ErdZxZoLVX7Ja5OmRKkrB7RwiWuEoMKBFlOI GJi0ZciJYkUjvJ2ww6SUSThNk0Bp6iRua5SyRDFBzNIx8jmZHacW9EmTFYuvA8SznKBnHeOim3DS wY3fdUmvaDguIAFKmk1s+ifmPxn0C3sybsgQzwBmhIvA3me4/bNpCGipwONqna6EnX0WgI700kSh X37gY6UYKQAVpAXbtN6tjLWpM7flPrGscJZvvBUed8tqk3/olUjUje5X68BStpTzNVkTBcJJxuIN UANWmwjtBU7P0BbeQ6R+wbWnX3AAAF0qR6Zds/nb9bq51YAgbBFODuZxEA1EBbdYugUsPgZ1h2Ad D6p1fP4swdvHRWLJMrBug0NpotbH5FIQ+P7MuXOvN5OKaTgf57s8Rg2XXLJhLxfgNMInNewZwoLS 4jJDOr+BbMBY8R60YZt9J7zcezkFDQSTzkxlbwFqinJ5T8Mps9wmqqsLOdqvPs3giYAuMQZbDgaz eXEVPrgIwstCZ4bET038+u7lcd3gFo5AEzyGhNAtqmmVxmgjINuWHLgghJGO9OsiA2Y4pDlD56G3 Y+RE1GOAxcLvHCpH0TEHsUIp+mFeg0XtGeWAXdgMSm/MRyYRdauX9m8VLdFOmSxu5iA470D8hWss n1k4fTqhzkVIPLqeaq2YHKUE2pIqMEjO2y7ZLG2PLCxTvrZhma+gfW6Ix90Jw4hy67e7uqF6regS BYcafCI06RHbOyqw+zYd8BnRNkY7zpR+wdgbophbXDGZlASFlBd6W4Y0d+Sf4i84xRRwN8Z6r6vy 9L06aBDfyP99YftZC1cw0hi7sAv1oo+4Yj7oqzJE0rZN93MP59O3XO3C7+uEiCd6olVLp2ZtKttN D2S5fDQ33mLgrn5wWeCZQSWoK55rPjud+UL3yF6+dXHgH+zmt+50DwvApqsEjL93ZjNe2g3rEcRS tfH+XGrfJdGoTpk6EqcrRPxHd/AGJJZ5pe+WMOuoTmvucvYavywxtkryFF/jpjdkthBhSUhzx62K IkufQAv0dzPUZB7LxpkB8yU7x1zLNWynK9t3LtGCG+jZeVq/6K10QM/yLwUInM+2ZAEPxt5pV+aI KJZ8+w78KS9DKpUz2pGYTcBKsZUrdtGKNRncsB+DvwAM8elBPoPdfDVEfRwV4XPCfVL+cgmJyrrR Z+rb9pExqro96hKRv0G0Xz+so27NnahsP+/3GvRNEEPswcqY7dBCQ9ZbZLtt3RWOgeb24RKgb9Yq 7clf7BkJHnPyht1azNsDs4XvOpeWHFhSquVa5c0+uLVqC9pbmctxoKv1Fz9NgsUuzPHiZLul5ETX Z8LKdBfaOuCN9iVp1jfA99z7ahVy6Q93LLhQm3gqu+89WSl8yz9T2cTWjEFSGHDuwXzlSZPCKztn l7R/7w6Zd3qCTB11cfdU23itXeYhmTO+ZkOVBFQNXEBPKIKhRXzGOwr66mUMQObAdyvlJZMrVbC0 /jXX9RAll9KruK9OQpEt18EQ8JbxNBh7UA4jzNUTEQihVWJHHbqiuS9SH8x2f/jwNItod14NMzcT mYaMMEjkI8yFIDTUSNyB471gGNyc2EFIZZMntKyicVQZhwBWYcjKZht87U6TJXMlyt33KMbgVwNf pXXGpmPGWExTn1on2lexPVWGfNmH2SXQMa8/jLyz22/RrV3psC9HbzbsnmVdaXpBxYrQrNwGnSRJ KkTYiiRp5g2SPOHEx725azUXiaPbTTJdj9gN/wwZip3mBDOQ5t93a/wCYeTpjXaoTc7nmDWPSRy7 0lafrT61erCiZcJYY80bij5fZZI/ZymQ5bUKuqnrtuXdKStBUZjZSTPVkxVqisJ88T7TXgJ5ltI4 YlQjmaq2wZpZ/kwdRPT7xksLPAZxedAGMqhwLprT64BR/oKHQALOUQewxF1NQEWrK9BXDEC6+GZ1 CqT80R6W5i2l2sw7mxmF4rFLe0OvoPulFZJgoxLVjLy1r/WPDUlSItYy7YwthTLGu1/74btqlcJA rNH4wq5inrs8ee9Gngs6Uu7paCq9lBzPaKepoFh6poV6fIGNmm+nkhpsEtFUirvgw9MNM5yIBKKn vJ37o3AAEntOP9B47qsa2c2oBYfIqSezSJ35NnjrkDX2ZF3yBssobQxSvGcErQjqR0wLBboBzNvj 71/vpZwWCcg3QoNpJ0cGS1xYbKGy3ZiOCGLPHtMK+qO2TntCtXYjQ6wnMOhrh8dBXSAvZCMNmpjD 1Sh8Ee9Etmdk3B9oRcX8cmp++e6hRBe9wd3kDnJLd1WIadZxqSHptmLetS21dgP6UBlg2oZUaiUh WysUe3H0CxgTBVcY8uXJEfcRVPWq/aHTvx1YLyjvwMph9S60YC5svTXTK4Zy1uGEw1q57dziTh9e JM29M3o1o0i7+90VJvC9cYZ4bQ8SPQ6c72lhFECuWdxxwebNn/LE6uO05liMnCrxixeDcrwwt6RF y8A/DaMtSS6xTZYKoZxts4jeLgXW35K2+UrZwonDts/R9MO0c9nDo7ALaIMKntx3S/fVucGgImld yOKMh4RgRmoBFDlJ7VXNdK/f8mD7IQqJQVjposYRjWpbCrjKfEfMpEoPh5hiEAzr3JoDHf+fHCGy WKsLNtvHW6yuchSNfU8sJqnDnDzECosBmaLlWQA7aG1EfQ3LmtcCSI5u6nBTk0rOlbpb6SlGy3QH M/fKwkzA/lpjVoWhhXSqL5Q/7YStTY5cEpxJNm2+jItbQHVMqFRK3x9B7RnlS2RLGZYIs/8iE/p1 MarIiJSBFjPUHUyKdbCtulXe21Hr2vDLfU6QZY2jw5ZtSMgYUxUIsJ5Ad6ldp1jmqtt+pSOtmVKL UwOomaJlPZIXG2C27LgtbdpUV0svjyVlJK4Wr6yJO+DNuJVAQZ+xFdWZeVlPUqAxbiaaVOs4sHHy sbhsZ+6pPbG27qK0wBarnEtzFpsjui2HY0hYiKouZivspo0gNLBvHe1aCRM18wbVrqYeUv38RJ4i TLtorZU75zPW/y48aN75rRGL+z8h44ms3D9LYs+aCrwXyxKdCEbQX5o8ynaf9oPnBKsgud9+pW86 cqraAjhXp33zgbcIoxPTRS+r9KOWiydpnuEZRXDeAJv92rmT2YuNwEPYR3L69uD9udNXJWTKygoM 52DVzhC99xxar8pNVfWnPKJr30rj7ARtA+xXhJomEF0CkBn/LOMb6DGqrobbRxQSn2v1FvTwQSld Tlm0zmeiR2e0yhcOPRuxAUdk/FoXQVEJsFO0/USYNJkWQn8mmrAwjWXWEsmU7V9Gq43NSPCsdQ/z zOvJ77dHU+aRHzpx6hah5v0PKmtbIjGZYXUV+UiClYG2Ujc1r2p2Px4AafxuY7UHsvwg1WnsZWqt 0Y2oQh7YeR4RUpNjgKuDiHbNKGw1QoAhwbNjLwzuXM6DVbtJVveBMse9I0Lvlkp0OKUnhz0Io9aD lca9LiwbHui7+7zWVAy0NR0k41QXmImS2tykhzyj8kHCZr6DseIKFthJCCzjulsYiCAA7J1gv7Ll uyarR2PwJofSVw0B2hynhPYUDTtx87iPthn4isiuuqA9WD0hNWyVvnatmO5V4+o1Yx1MDFk2wEz8 WXazplOzw/PsUsfs5IODP7drFveR9SeNGuxLes/IjdUPgCH1Wl9WgL+m6OmoWwVcs5AeUlpwrOOT 2EqhW+klPPlFjWfqBxrD6TOA66z772QeHUWPz4e7m/NI/s201BMDp2VBU/RNwFGWw+X7wS4ysoUO Yilb1rWfBlxdPMyXEaPS+fxUrFmDycNraZ+gVqNS2Jtj6oHD4aXiiYL/ctc1GS4AVRVlrWrAw9jf CcbK7rjlH0GJcadrL6NXp/nB04rQa11wOm+/eiCM3Dmj7igj4CLDI1oyuFBGultkK5jVUKnsR5m5 4HzMYOSCP0D+1mIHVEuMk+Kxc0/z1PK8rXuXxMovxLdNAGuwdfN65bwFEvZY4pMJIuw/6s72jwri JZ7e5+WKisJJukOvMK2WgA8uA328lm2EIhuNWn2TqIm5nIT7ESBcr5ofFoDew4QVwaEDpBRvG/Wv XLc2nQdtJhd7C8XH35sGPjXGOgYXqUfr02r8KVDf9NhlGpbV9N2dxZWPPAHFWRlFiX5fSlgLx/bD FdhMD8bjsbZcK/IPt0k6Q2mPZINx2uWdGPOA7HN1LYAUE81Inb3ytrHpAQjIs6SM1J0xN2K0I1yF JTLWAroHL5kVyIg97qQ+ycEUcG/jY78ydiCZeFyEQZJiecHRbQ2BzkHFQN0izfiXwCJbyhrw/buQ 99qYFWk/13VT7FjzmRMdA2KHU8nu5CJunbylmmey6QSWL7QEK5ZtqDkl4sxGEHUTGkeuezFhkIo8 ELuIPERR49ayM2+JNn1bgVFgfXcRP7KT5wRnezKpHSG2oySIF1fJHp0K9o8SpVlIy31lr5Rc1LOk Yre1TVBnytrJckTxoAJ9XLBq1CJbHie86IOtLpxrMFrLQQZe93MKGA90DBWuX1kfriyqAfVT7ZnE HoV3iuZ3Y8J+3A8uiEOOw1OiMeyU10HYG1cKxglbddjmDCjYlw0bA4WUyG49OIUYTs8zWCYeUpa3 zIHhniH+xARgPnNwBFlobef6hw/FrS2nN32nW0wKvLvSklM0HUKFsxhIRHbp3LM0O4J+f3EXzRTa JMC5f2thH8/lSReVP4hVp9uFLNPCPzeajhYizXcNscqfk2V80qyHhagBlsE1Yce1MxKvDAlYrcLC A6Kvo6vLnMAHrrnko+tzDknMd3pULNrD56aemstMaMEZomIguUIyGCdwRUFd0CxQcrkqIsbsErs/ AHNIYn4lV+TZg7bzN1FfOQwvNX3jddiMmKjIqheghGlZZAsXSTVt0VMltnU20OKK5clpHNBmHMhv ygRQ9R+yOuMBaoVErQfLoHeeGu8YkO0tftSEt0me9iBpsYSbL+kZ3B6OdUpBBNuqGAjj/+LJ41v6 M9bzC6f7VUQ9o1c9uKWlRpOw3ZxDtDi1/9f4x8WaHGMhs3OMjlu6xCO+eUWGSiaW6MA0F56WKXZc +Kt8USO+ghGRYecgpD2Rl2HFUiQooYrbh/n2YskLnYqSEnTGrrkmmCTZma2gwYaxyPjVzY5NZAPv ZA6NAF7iFeKtM1aoDpSjDK5d5zjmzfTW4yDjZvDtFZYpISSm9G6NLB+sUAR2jkWVJ92I0CVKDsog pGWfS3rs2GzvhHQ57+VxYVXNcGuTgHv/+F7oL+aPmFIbDMhgfaPmkxIjBUYHOhSx3l7IRMYOH+rt u3eIwOZIfLpMYQrfFZ+H8i8t0HUNLgCmLxT0WQ2H4jn8c03km5MggBE03MRtMhnzyKiYjOv5pP3y +NvAh/HOF+NdyiJMM/GcWHE5lerlWn4YYmnifSjMMrA9ZYT5C9xsz5hCiYkCe1CtwraNVegvOI1C /O5z3bFoPnciM874ZxMRj2leSrPfPiasNuOgmsrVtt6BUV1gzDu3aEeRbhUXurdlw7DhHZ/y6ldT 6JSUg1OEx5Lk8AQTIMbkl0vcj/Rjvl2dj6y7rPhIgFgdXTtbsAeBcvbTpxbM6ACHPSkpuYz30W4v CTUpEp1j9iXE5OdusAXdgmSz925S7QLTtn4m9AcmBn7nccgu3bjF0Ya0ppjDHyJPDW9xNG5e65++ Fdrm6Xg/yyxvdYJOjvQpHKBFasa1hgr/E+JGXPECyQA44EVwTE9KZqrUaBDpDySwksA2Rx/zOj5Q CQbFaoFXm9EmMCERNhsYl/h9by2XWg0hH6uFib+nH9pCYucT7QjPKLnUqMel4Hog18De5+jMTMcr odYlRrGkB8aYAJNun4zSkMZNYftmxN5CaXLCByhHLllzMgpfJEloA6aXy3Ai5MTmRsN9fju1vl1/ uNiW6z/YTf1MuNiYLCGc7Bt/ZN3SwAW/Sd9ubNA2upfUZxk2zagbYzIED5mO/f29K1YLVpwLQxjT Sv7OfQkDBhHRfb9Aiy7Vos9hEGwsglJWyW9o54qLT90mJhTUJMZbQcA2uBlVG+JGqg4Evr8ZYllN NMr7lcedCyMMWq5BAcDfto+Z8E2KXe75ucMGB4x4e1YFnAruQJyQ/uCqOFysEk8z0fzXR7gfkLIv 2L7h20D3vdto8Pm1SjWOQKJzj8OIR4zVXNfD15KvjAg0SDJwAXZNPyE9tpgek16ktepHz2e3Zvn6 dW3xbcyKfZeiwYmAvmamtqOycqVONClSQ0u+e6EQ0K4XT+mJg1bBvwqv8g6/UyzW9usaWj+5dWpF 2smKpFvw8hRaZ7Ix9CVCz64uSHkAd81DcAAV/XdALGh5KIyxUbjWQQYD4InQYhKD5PyXR+DMpjzE 6UrkBpOlq3Ntx+Xx3ffYem0y5PevV7J0DBRWg09f+01f1ftnbuGh7cmNqF0We/HYILFotWUd4TNt /KKHpYCF1KH8djKiDxn1SPjlqee0ZeUkiNYPYHaN6EbA4YkEXeLH3UHGjliABS7iZ6oEfDSRctul HtMP7OQvRFZbNcu/9TArQq7zQdUBEgk98/2MfCmkPKL5KdrGZ8Vuvj4ecRe14p5IMwgaKN9uNk15 lVreazni++bXkM8ZNGzxqrSHFOZMzVWw6NVvEoUfiCbAdphNYkdYx81/ZX3BorW5ZTmIflVXRb1M Kn1kyTIE4J0Apz/CkBgUs+n0H/LYatjx4I6cbsx6z+P3XEByrFvKVPyS0ohe4YlI7ojdPEE7zEIn n3A8gI+mTW3Uw2q2394PUw5xqP+Q1DqSJxDpZfHAK2T8ypehYM5NadSJbNVRXyCzw+7Q89o7QYFz M7h1svqV7QYVD1PiLHOJhcCXON0aqxifvpBUaSwBNNyL4jMZOxQPdP8yIeFjUeYWVsgycAJM7ucy hgOCboKZSKoEOotihB34Z0FgEHHEiKFKYrxCE7MCJa/G1gOL+aWx6vKSPwSxRmwfPfF4DjAebqKU FxK7AsdxX+7aMOZhgqh5sL9GAupjnQaZyT6CIg1wIvAM9fN0SpUkCrV/ImkP5MVciOWnWCnfySqD q/OddapmFbFVLkZZTXS7FkBC9DLz4TLJTXnFI5ojPio8RDmUwpcBBCK8BTzDUoAPvS03C1D5YJQk N9WbRpOFmS3Z8rUzt86fx+YAaujOXkQzKDPMNmNbY/GZ8hzlmSoc2DZhrEgO5MVo4Wo/6RoDFDIC 5mY5TzTt1XMQgxxEvfM/lp2f5MiB6O/grpvJwnF5ZVO0mpHED89x2IcchLtxQ0nw9/3FhK6+ej/f UF3SG8OCYffFsNKajPvo70GeraGPKfDvzMXcw6Tq0mc6eEYoXUfJe/tRL9pGJBYIqaTPfI2L9zpV lqH/r5p2A33IXwUY+Q+1iz3BTH1Y9Y+l55fOL8bpbD6IljBZQgKub4zGSegGA6Q/XobouKoLRwRS fADXA3MVctBNxVYW2MlmDD78I3QJcqGSU/9ATMSN/XneTDjEtj2HrGW0KbGdESUrzfKsLVa502qq WbOH+oO2b22OaU0QJGXTIl3R8b3MdJkLmRbIiLPSsEsPbLLeng8xadr44R0IAJz77jyajZyP4JXr y/28swEkTiMN0R1ZLE/LlLjg1DrPzFt6WAIGd07+tQslt0GQSxhrMETkpPloE3IA82zqFJcys/52 1wvLev2u/Dn02o+KnXKryU8ToZX96wuJM481EUovPLQ0yHBUpLzGigBDbzqlVAN76x6o7yl1hjRk QoVSawrTG7uIF8ASOqrR2nwba+Ozay/oQTRGwdB0bEMgYXr93uVIGgatUN7FELJoZ4T9LpvUvCAW kNrIrL24H2iNxsoyIGfnDXMyibQTczUGNugxY0PFgnAOVsxC3CfKb4hCmzmZ2EFUU+BlrzENGxcg ZtiD9u9EOyrKhSby78dJjrxkI7F2EPcDx264xftN1Iv0F5LiY5LXALHYsCmieuoSRfF4a12nDdQ+ oV/SagLj+1Lcfn31HAURorK+lzTwK8/6gzk4I7dFRlMw26v20ePKf1ZjV8VH/LF4QK2vTPJ5+bjl asy/u02pFw9sj3TA8IFv7LFSmw1zKl7Tz7x20dH+YSPDbWR6crmtIQ0MJw20B4oXcdpGSL2uOqt6 3pKe1j5goqL64skdIpjdzWpy4HFnFtioAejIp3TwZQaa9Nqgu8aD5R6R3R7dVdL3gbEzOvFMO9eI ko6p+FKqbd4ZXrP1LwBSQXweB+dA4jEEsiAW6Qjth9XJHT1HLdM0R/fvSsl12DI+VvxU+EBXOpQ2 lVDuzOP8N80en7ilaOLPDKrUilp0/nCgz6UqWYVypYNqJHXZhCV3A/XNrL2eYS7SxV7t8ljwzVCO tEPItpGMiYbWEVMJY/nAzxthg/GNdzdPXluj62BpUHkIkaFMbAPyLvifMLtSRmdKeS2Sqhyd6myP BT2Z0hpWAOoiBP90GdftYKqdcjCJNYW0Gv4MVPGiSQlOiZneXAn3xsRaW6oieUHiQiDGHfk/rbLi n6ab/keesNvepmN8ZHYHZPNN7eeUAcgsDykVdDfXabsWlRkHZmj+9w6qYk+CerWivNDwr2qlvglM Jsh23wI5hULVrJcCcaRFpUEk12sdCep4SsL32rXjRtupZBAZSTkd/v8kbgGV9WtTgK4zex2JXU3i mFVzSXg7Z3N0fc/zUQ3jc4ZVVEHqYrwE4kU2ThbnqXr1Hqgn5APwu8psOUWFODgEU8I3rbcj/0f/ C4Z8PWbAkZDDEvKjp7Dg88Sae3SVdCTiNPm2VnMWcDn8ihnfFDFoWlQsuQdooA+JNonIL935zvdq 4RUsixXVAgJHXT8njNy//M7oThSLSV1Fw5Doff1mdpeY2EBJnUlhnyfT2HbRBlXL8EJ9a1fCDv2T y9inJxktUYBwM8xxMfKdFp5nkXHK6BoatOF4vMJ4pBy7CjS//XeWaoQkNWivbJzkQuWbMAvmFSLK fv0pqlQp7/MtKghnMpMnIt8A1eSuqwAk62jzbHhzJEGW9vhrZsOSWKz1S9oaJXnrSZJezBLaXa1n xf56IyF/4wQ//KsbuZstu0gQXzkqW48LNhPr/iiasFh1OaAot33Xog7BJlia7Pq8nuZ7mGOuXsOg r/qOJSGYP0tJMiDILQeBra7cdN8tdh9gk4Vlojzd+LsFX9uHnNV81UvLckeZuWFO0DIk+LVHDg1K VjGNC4TKq6m1/J6cG4uuIcKedjwjMWhNGAdlqV7DvRpaPLecuADMJfKOEpjL/KdU4IScPc/SSXwA O+gOYR9YN1i0vZF3k6xRUbE6MS6+rwJ76ps4e8+QHQuIyQorFnkmesc+K6rGEkrbI94EwVks5wGW e+oItvjMdIlnf+OQ30pIMn/XRkya3DOQ2gct3caFSuT0GgCkSYVj+jyGhklGDoGx+bTsrwSJ+yVD yOjYXunsByg9G1wUvxk3wUChXYmXgSI1ClSXKgdV8R2A7mpgNefhE+6yJ1Qoy5TMGtM6YGsZ9P8Q BJ34XGAItdGpNocfIK70UP5GV5fQN80IqJmWXUKj2CPZcVeeYtcUl5a87UQ0eMHxLbnkeaOIMJDb Ul8N/w07LhNOw5VNBIwqzwdoeN26pMw6A+CL+Cq/dlteZW181CXmGl3egoXi3VoXiEu3PG+LMjWQ 1o0WFo32VmTXUMzRORMBqOfL/31kBMdXoe5iVGkpeLKEZf+vEKuUKHRrEpOaUlRd0UXSp4dGo/iA zHCfYxT7GoLGftiTk1QH+iJubg84lc6wqT9UF5JwHq4zUEpVf1ljbfxbFBwj+q/1ZMrHTDxeEC78 e2ccAXqsNswuSUP/rGJ8d0qTKdvcFB+S3EHKDdoSPnbUvowrfs73fV5ts3ZW1RAFmk2w9I4YfqqW HvZ9TS62eGw5D1ohzaVhqUoQkEiisrBQcK2ElkrQiuKHpd4ugh1DKnzVmoWRLpjKAB4cEg6Im82J VBtug4Tq1iv7uNYP2NSR+gHpAIrN/APeESEuhCCJ0rwzAAh0AigKw0Bh276y0eJb1wvpCgnkrBz7 HrCZ7Ap1tw7QMesx5UvToNWwg7aUAEDjKK1MOzIEp4zLiaIwe0J0DabHSRIAb+xNMF5H4/hercui AtPIqE7yu92YqWZVkocZ2670NA53z/iG9Qhw5JvoXiOJf/hNyIKIMoefvPBroZvWMOX0hAadaSF9 Lj1rPH8eS8j+slVknyGEMaAqCPKsjMK47tgq5F2Hmbw4FpAtJNjR18GWSbqLRZci83++puvJg52+ qnDXyf7lW2nszvgFmCl7UkAhE6qMLzXz0k5xrKLvPlzxAtEjYKkA+lukgcD7nj0jP15bGa05hpYi KVWTbHNuW1yMla4G/Ls1bfkuGMltni8keprrmAEH96++Spc6CYQKtOucQFE731//8Q8oc6yut9TT hYm4KckahdDjyd+0QVyuSWo3MB3auPZ5ILYTafLLVE5wA0QSKVgYiKJM6hmVU8pnmFsAZkI5Obqh uTCaY3pZ2105i36ZKu5BI5tG4VOZfqKDDshsZRVDeKlZV4Vv8ZeGrPZUQE/muvWfxvcXgcjZdrdm k8qhR3wjXt94dllipMos/Cj4AsF36gxYjlxYPAWF0N8JPTk2r8n/0lsWuRDqdPwbpuP/P0OP1M7m SpkyGxmtsTw/yIkc2N747vt2me+A1MwjgGPSjHbg3W7Tvqq0f98Ld+oguZZ2IbKVawMtQf86XEAt i0LY2w9IQu/dXQnRG6jokmxlhvd5fwjgOTRxLTmfUNevCe2tApFULb87oYzLyR5ZBg0BcyWRr9V7 4wR7RDs705fwua8VqNSKl6en3wyd8lgWtf40gOVgsuP7WwuMgV+lr0+vRw8Kw/CXXOqET8S/PccY xvAqQ69rRT2W8i74xDwQlqLS3Cx0Ozc2qbt9UfM8KbmmxN2aoyLWJISUJE33XOLh6+oA82jPYQEu 0m65jnrorgtqXd21QIWnAQZ9q6JVDmALUCdwouDSVpx01Td2A6HBFpvI71nkPXaWirF00SMy3iRI T0/kjDZbjYLRgaLDLUB5o3zhr5GqWbMbAKyNOjpzvNQe0ZGgpONmK5btweP4Jt+9L+cYiDPREcrK NwIK+bJXSPJBaayOzLxX+U8A/Itlxv+5rmRRfGTBCwRDsGKyl7eBqhB0xg1YliXdKo0E5lIBIfuE SCLy440cjdl3VWa59+DyrbwHTbPE9UH3X8KemhIyrmJVvBy4qoP1kuSZ0jxL6pWT+Bkkva806v5g +NxVxp3VC7fmFQlLqE4S2J33DNRGhNuRlBoqZ0jHLEFwtr3zcuuS56HZzey9TzKD8Kg6zyim/IiV q2paDRz4b7oxx8ybuG9F81SaP/GhqQL1AflC0EWnQsIz2ttIrm/64u2lQvgdS3jG4IdYfvlA7/yK OvgNETrf2AsgY88pUAd+OHn3L5PbPVe1BdxSXkJdZyOhcG6cYZ1XhOrWegME1CJ3tZijYdVhoXcf qtPI3sU/LhCSN4Op28Gkx+FnUXzYusHwjpHPcITTley5HWvpuDfGnRnuPRlY1Bmyf+2EC/JbKlks HNcFojiBAulrzXAaYn8A/LKMci3EAmfJU9rsuiJf0KI+nBBw0L8R1iYbua49Xzr9tCAGbukwL9mZ fGLHmxxS53gONS/GxAkzenQWisp+72oaSescnY8SzaapEtDTTrszfn+9jsvBsRoj0ZioOivi2zEF 96qAkXUCBZs65R+jjO/SYwfnycsGj+GzSm6H3Sx097qVlozahT1jmBSP80zyhLz05lzvT+FDWuoA 9C67+eVz9WtXAFHaMzsivgp5PkVjUHFM7HMOOyMmMB1R+k4B36Jo/oO2KZuK+XpGShnJPso98j81 OLy7oI4rLnvokzGAGyImUjC881XC2m7x2kXjj35fJ5FlgQF28K1prgIE6CgOUKaMsTKrk6SN6VSO lXMu8h/NzOmwx69GiUcmIFULEQmIONKnHNBQF1P5iYJVXuhcByWV7aK3tw8RpeWu7hWt1XwLnV4P 4rdGcujoolFB79un5ZvYQdzPcLW8SeDblw13pKrHW42FS8+TVAdNBGdumoP7UmFvgYPwO4L43687 OmFmiR+N1O3otkxgnl0gk6oKFek1lf6ILy9myjVko66HnjQH3ejMLQzrXwhUj8M72LGrxpNwQQnO WfsOBArEL9o59Zb5gkKJT30D/eJ+XH+/6KlULYiTLab76v70c4AHJQimJyl3oELY2oNcs3E5tSwp NaJka+NmtuXbEcvwA40amN0A7FHM1d4NdFJGvJBk1T1b2QysP5A6rmOxw01Nw5DZ/GKCE7iVioTY fntwkJSJmsk3y+xeUVulKj0qVQb+K1Qfu0O/o4MyB0EFnWy515Y4BIJ6l6sPdCwUq2A8FBJP1RFC yBoYPVf3ar0sqCKbeMvuqfCwSnAjdtuCHLulfyFGai72N9LP36ZqPqsbWDxx1TlB4ZZarTQfyL5H 64s+uQBcnKgA13LHYz5a5hG1CSlbbWeBLZ1caSNcjgxNt6ujwzlFdiRgSQG1c9QxwlAuAX5blUuj K3kyiGqzG2+UVN91AQgwDuUT4oifb3dP+4/0fHMX5+FAzsuELeRR82W5rSYYkmG7eATK4iZjiZP3 1v6HS55CT0lhxrh/yEjpkw6xh8bfJR68lPgDd71o4myoy9eZw73DzsQUhI2WaDJ2J+N5EyhxWcO/ QI3H8Xrcb8w8Ff7nI5ylnIzecgwLlMrzvIA7q1jUWcqrhgkml5vH8ctuFM/w/gbz/l8QFvN1K8BL tBZSPyDYG9enpZiiHPerm+YLBXyEfskPyAc6U1v4AaTsjYB0BcoBY3JWWcLxrmvXnlaPIHUpd9SB gu36lboKIcJhZmvNKKo4QvztSQpkx8y8vjuM/hRL83TLyjBYoQQBXlJlya/RScQwPMzSX8dVU+xk ZDJGeuRM1OpzUhDgHgcB2qp+YnY9ukx9jR7L7WGmOs1D6L9ehR8M4R4zv80WPruZ7Nwgo7lqMgTP b3DkR0jSyNRTQ0L37l9azKPGVUPFKQp5OmlZv6v2S12rA8smi2dyj8H6/+QaPP7DjuMgCOkNbHs5 36A5V8tEbLPYi6ve08v06bXXIKFPSoqJ6wa220Jb9yjt+6/eMEL2tzsXTnTmN0HEyR+OCw7DEg2V MhhSrXVzoi/yxAhTVBO4HOXAqQK4Ir8gWf3O8RuGzHR5HutCMMtx7p1WeO0nHniMrw+VhkU2qBKH 9k5jljPTasQRS8i5gGV6OqS7qfn5IFb0GtxWrwx80Ac+ZZVUDk5ug7cxtRik7kxWm4qmponSLDLq iFVxGx95Y775oc1S7MOpKorkQhRqlw0QI62BuZNT1/2lP7kVon7bTVx9ryXVkbw+l0TPSmVItkjs BDct/2XGNpxAmO3Nz9Mxy9Y5R3wCTclFl4F7jU+2WDOKmvhrKRjB09asJvPo2RYP5+IvktkDpV/+ mZgNytqgSYojnHSz9FcNL32+lvQRBo3gB2nxIDQE7oIpEY6SyP5vxo3p/CDqdwLTPZg/iDok+aLm 8o5ukAb3GxQuD1cR5kecS1Mryd6YTZZpKfK1kQ3zFIEFY5ARd7QZ2P1jGCydQNSrVfdoaE8RnN2K h3pAD3MOsTagyeV46g5TFJFBp+jJnqIoh4oFjhTd/84ChyW/LsOa/NKNBm9x3TPz+WZvG2xtpP+s Igx2pUyIGX96F2KM2ZAO/tKqe7aj8jIwNUQRnfcuwqLQJS76yYvez7mPB4YhKbdOmnjPw+pZOrn/ P4IZEMw+IctNR0hFXKwB660z9F4O3GUnsWPBsun3LVS8cvO4RjnhAEoSyYeiHMLCSHORDVSuWJt6 /74qeFps4zS5V8K7Zj/Tp7jhO30rrM65QKkaJYXafn3ncwZ1im0z9RB0LKuEWXOQB+e3waqLnjv0 rFwokCvfllcQJVASdkxvw62mSWHQqMt5ovqeyGWmLSNr8gZZ6crGDM9y/LwozI8f6mtrACTMJAKn VXlXlBkQYri6hiAMFVm+NwXU66y6Krnae00gRtt9BRlzmZqiGShF8eP2DU916D26VC5UpPYwqOXU lMqkEabmSKNDoTl7U5Ulx5FZoy8oLF4LvTKMMGfpmxEJqHMJrpfOi9SvRUKoBFBa9JJvF2RKa+rV 0OYU3tI2vyQb1H93/pwWjmtparhSD35zM6rgN3l0+pWsnHMI2CxhzoPj1r8jeqKM88KSngEjEJ0+ hmSAyClMfvKUTJBSIiJJCoPLfO0R4LRerWVBMCrZUEOo08Vn8sfuRr5D77IXzgidvTGCVeO/1OzO kgZNQ64PmGafCkFieylSAjICbOOaRtVSRutIdUeqAUNcEHNH1DxKnWQhGbyQroYiLVffyoSdLcmz 0RqB8IZ94BRT5N0jKt+RTA7xSzCFgAISsHd/AHxJiH+rLI9Sgxp1vIGXBxGvztCZ+r1fnqyf/YiH SqyllrZs8TUdrRqvzUoBJ/FuneLT4dK9B5DAWRke+tHWYIGApp0C9z62ki5Ae//OrQ2RAaplwqKB WtRIhkcwmM/O+iEWYX+a9rhcxNIku1gDuW4MuK8n7EK+/G3YgZETbRT1faENOVF8K+H+Ij7lDDkw bJffxU2XwU+5DzrAOdK1/WXgeKc0/wJFWw125CxxM5byhY55jNs4TkcmYQePaVPvY9W5CzB1GnV+ PG+BxfP95z6OY3dkUGAkmOGC8mU1dmiUiSqZACQnUOzgLm1XywabuyoMnBAErxPdUaXrjOBPogEi deUwZyULhQjI53fmarQKcdNUNchaxcwYcgMprMMc1o+vUXVRJgg0M5On0ASH7cFlp/sRnZIpy8k7 JcofFGJgJbZ2QWqAMMZsLGvEWbGW9nBMJN3wb5Fd9vqbgSfyp51CTO7rNVIatsPOXDJ/CIzPKTi8 umB9Ntd4+tJqRbXAWZdVeYsk7cpbZekCJe+qGfLEC6acfCQ4v6jIQjst/O/RvZaydqTd+P7AGsnD NwmqiLkmJuKD7XExJhZ+0cy20IbTSsawyryGr/+07ViiPv368/B+r8JpSx1q//FuCZdzyxtHSKQ/ cPZYeKhe+aebZip5j1i7XJ/zUVxeViE0Fi7JqGfkoBrOpprZjpQHN4/yidZY5dFMtEM03moaEj2w sxK/bEqGbAzfQyY3JDgv3iGTpsbIvIgJd0CQuXNvw1YfnlO1/lvSYttJfrscM9ZFD/7F2RCQ+0NR JJUFT7VCTaigujQx4aDvDitz8NDZjk4/iW3qD42euPZqkhSNyWV15DF5slr/IikMYuC06gN90+y3 cFZIJ7d8fbIL72j7R7oRnhb1lTSuYp3UlJGGy6E4hrlQAWBHOx0f6nmIp/lgcSpj5yQM42hUiidd LJEYB36ihFd+4x7O6yZtxrmjkf6a4cjZpWGZOFOacewmA9URt+Iuek2g5vcvuUacVfXWk6os/fRz 9D8bTVMXwpXtwNsHwwvJBUZWbMPSLVN84e2vLyEwwmWhRiA3U77ufvarKoti0y3mmUEYjzmNGc7F T+MMjcaIRBmk2mlEc4RkImaKs4CF63pEO7KRq3Jh+FTW/Z1pgFaDmkVM18T1IM0R5iup/Sm66WHb FRT2pY3VobBuZwJwFXhUoCxppxL6AXmE6CA9qPl7fgYFwmGA0WI10z5Jd4heHsWWjA1VeWEApeBV L91ztz9nHu8ONjCXN50Na1Ur4AUB0GhjRM1f7rS6DXPS00pyW6g4MISHvTs2LeIzruiqww/+6jwe aeqN9Du4bCBeIPPbK+w1eP7ktVApLbN79qDAFSaHb/Ja/iikLOwMQ588SuobiP9BBKXAyGZmlxJ7 DRr9uldgiZr3ck/l+dOL6J6bCozFXAgjyk3UodUyXM9Oy9NnkcfFn3NqFvCM4qRjpSz0Q5dy+9tf eFHJ3ejcAMLMOk6nyfeyfgzo57ClWqbE/R7kqEuqBXmDje0WF74dp+aqgICiliPqezZOTi9S2skW unRiQSFdg0QyfBsy74AZlbmjEkMFwBj8Dss548pwfZrt9HwddCziSIr/YaASDQs2Ty2zJOwrKgjZ NYQkZuX5e+2GI4B1pWQ8dvb+j4s7CgIPxjXZPAGA/yNgvVdhr/phR2jYkMBQxj95GcU9i7hNZRRk ojoNudNlcwJ5mu//5tJtdjMQcr941+yUTdv4Lrty5yYHEyufGF3sdo6cImQFj5ctradIjO4GHrgr cO/Kz5u9Wpa0p/0ojZQaRTIsZ81GTh314Rm0hXTyaZBdiThkDlguk38zF3ujrcmzO9BnNs0N0xRN grNr92QtmcdFyWkEOCAhvnHv/WevZGXk7Pb2Bpe4fdAamdJ3V0StOnNxbbsQjc7QtrmY/SefrKX2 K+bqAUCEDsD9sGT1fqjFo8szHVxKpm98klo6gQHomfSYPVYuWMbaCH4D8RSa6P1CKwKkiJ7Tp5Wx I+19vPnL19BnNrFzL2GOm02QXQ/xH5+hWG2jAleDDjN5owXsATnj4soQxhX82wgsW7+vbybMZGV7 RkedBwglV6QanEvMIk6KUK3oRsq4+zaC40nOV7B1+CCHIcDR3O7eQWI4IzGFSVycXFTHulm5WzBQ BoIdmgpcWCdtlXQKNFs7kCARqc5VRPLQhxmRCp6hUNAgqwfFC4VAIBz7XxGMhsCTaKqYi2uCEPoc o7SSLwRT86jkl2YTI900kEcSt384SzL4U7OD8BXIsmNCmK2ZajbjBzRWRPJ37fEgSY19mEVXvDH+ B71qajp1ZGR2u663KlIK69DreGNjrMSfkvHCYdwN1K4Ch/J1Ye9ltjNBGjmuCShCc0/zvLRh7deY oTN+sDzzhiRtk3fUBNZSIlnr8LXWaV8P7Gvt8jpgJqiUNWGZlSHxJUaeYnuiNrpRmQh0u6yi0+7O 44uZpXfGer0MmFhhoQ1BE0N+gNlqlyK3e/bIIA96iyWKkvot44FKmJKpiaPaijZMyUrbeE1FRMEb rt3TL8jCCMKSC+hn4DaEq80xe/plROdQ/EJMUzMTkKtusL+IaxZz1o5t9317T9TPZ4BSmSy1T/SQ H9DMQEYNNP7Z68azgaCDLZiJEZ+ietTYM9Ai+BKnEXvUP/ae08OhKci5g0XWZt93LfHpfnkr6UQt pEGvJCBR5tTgbMLl/1vFYa6XevTmwfrJX4IfPUNRFdL5NY73V75at058KUcgFRbhmaovW1izKePk QGx9lhGFvVvger6POIYe7S9c6JRuAYeswgBHfogHKxHMGKMhcF1JtPwQzTf/NMc+MmA6Z5HXLRB/ 1kZpiNSSXD8ZaPUN55xgtWFLe/t8808oQBqq3Vc51sJe9WvtL0NjfbWplgs6JNkyAtbsHuRWKWTq 6X6wlTYmH6w/Z+vVZEaT/uDMm/cjQzwiXpeVw2/15bT7Gu3EoMg62IEdBvfy3GDFKvCWcON2SQKr up3mQaX+pdssSfZkSUhNgQIIt87h0Ze9O2HXkL6I9qE6jz9lpRvML29wcSH8l8/GSxtJCQiSWCEQ NWuRa8B9rNSvD3uzO3Qm339HX4098cEUvtoDsURbVgA1m5SnF5PZwkkeLLjyYd66u/UhJM6/uh7k WQHUlpJERt2Nr3P0Ea51pkBFN4EiY1RxHxx797ER7oJbgLqbFt/BNRJyF4+SW/VfpSbvi7/9JAVL ipW9EbOuFT4R5V0EHdRd4sjq5mRCnhZO+7qkldHFRm8fRyuQhFEHU6E6xBUJStCDFBlPVOKfQIj4 uTtqfPKjwfC1tUAoT7PKvaeVz5yA6/xWV775hhGONd4PdqkBu95oWBfqmqdkHX48N829MPwEPNTz 35PgkGGWYdf06C4vtR+3ti6NijklueYDlTIYcO0m46QKGgvC0UA/FpI46F8CnplQtb59rvL/R98K mDvXwJ+NN8In0grrmU7YsUvuLKI5RIqby1MB+DDotBPvKRSGfk1xdlUworQQDqAgSv4LmVeNd+9x Xh8cP4ZVTlIjnEeHWt+wKbdxGUfzyCWFJLoy65CID5xuxITbYQiuNFfnMzgxkeyb6fXAwtUNiGCy MASkcY6ahhnU2YmsJR1rlSBPEPMQexWT3u7pfTziPW4JKT+TAbHEATH3+XbNaOGyJ6R6JsFsvvgP UP5d5TviSW+b6VSgrF5s/WwYSdP2lBiL74KgAOBv1SrfkHhLKCxtgqsp5wTa64Bg6hvkaFz4V0F4 3kXs33SGPJNaIed/YehbZq1/58l01NXtjB+0+70td+Os39+FLGOqMG8wadCuybKd0dyuvy7qyN7j /bD4ZGKwm+9ESM4IPsv/CTTJBTRv4BpJ+EHlFr0FiX1tG/js27e+9UTKH/c6ZBFCK9dVvRw079VV cYDQrWWnVm0StH/RQjP0fBd8hVkuqSFjZwC1Fw2gvoaGFJVvQj8FseloGOmS3/ppOxhPdLreSLi9 Zj22lo2p/k+Hf72IYSW78KNabqG4QjHMIafzPu4QNAVZHl9P1wD/H6aFfUmeCU0flGlrCH5hPvn5 h6SBPFAS/c8tuY/Qiyi80odCSje0fBiuKN9pmqRji4J9xzbrpb7wIEeKHZxioBsXes2kgTkuHeB3 KdIcgZkS5tC2jF4zT41v3BVdiNljzOBuytgbR0h6TKRtXR1GICvvRdi5XR2cbeBCkvn7UZiXuwPo RavgG57viz587NMtg5KhwBnkjU3V2JOvo1uBCxSot4LdvWj7+23k8IB1j/GEeum4PyQRi2lfjNhM frYDqh39BW388csZA0+pAh5ZzE2FS1T4NShgNeOK9o/zbPOlsR7H+2Etp8BAJExoM8qB7GJTNhX4 6WHzHr2CF1lpBEuWrBPT1RW841di59Rk8pmly8zHwfNXIuFFwGXR+yYzOs8im4MGygRR+D5eS7Gz CK9Tz42b/6JUfXB8X2+0rImnP1oYrGGJDeeTyrlcUHQyaH643lrQUeuij3uCeKlf7gv68luzfcEA caaJsVBCYbqS22bT89iqWLOPzYQsoeIGR+QJ8idSXQasC+q3lsvRh/zwQTrgmtNV/yPsGHmm2Y9l QCwHnx4xpjmRxDoS3QeagCuzlFCPrcLJdAKWe64uazJ6/VQOhymWq6ncJ4wY+5KWHQTNNV/bJhG1 oafaS20qmNPpc+EUYheAkwUl5GODaRwzIW2P3hIWdGcsciw6kfY8LwQHwMqYkAcwBjj3v+0rLxPA 7ttGQZkjaLqm9v3FOBSZjohK/TOJYDtlPRYSkhYXZzbOU46C8dmmV+dYR1AzHUiIX/Dzb3lu8sKO Oygh3RhSR+RARjTx/i2WlRJJyo4nI8yMn8y30bERUZg6+TORg7Nh4MM59a7xWaPzV1jUnqhxWHDh pP2dKdp6RrZRXzFE7Grf5dB6ttuKtT/ouzdoxmA+08WskAI2XGTnaxx3Fx6jaViYInPgJXcBYeiD Z4GqOBEykThu0PNgko1q1OVgI00iQCneF2g957JWbv35uZkPIw91SD38PVzBOKPmvKUIzYLGaTtw a4/NjoJbugRnUJOvasMZFkW+gNbafV45gmDC1eI7wMEDkft3oewh5QWYwmiRWP+N6XM9OAZbFu7B QS9d7e4XLdGbx/rB1c1BXFh+cOwzMauvzRLQBoGKBfGZ0STjCKfjYJlxnZYx7EooSZLL9wuEl/Ge N/Vg225jSKQMqhhEGn+RkcRsbAImiBRNuauGch5+j/1YV+s1y3tDhaEwtmm+3n0UV06BTAsubW3R Ofqc6RgMAxBs6WQDgx4fZ2VwrEaREFIAmHfKjTs/XrU1+PrpuzPO3GYLiomEWCbDiOCZGTQ/Y1qA 5YL0hT+GofJs93zC9DVDNvlNUbIZebUVb+Nrk6ZS+kdAXEUEgP87ZO4xJW+m2OWnSrlAjGP6l+Mo sIC4zqm2XcWQej2cC/jbAwrEhDgR8MM7nd8MPETtR4/1oEcDIvxidk1fQ8CmSENxvD7VLW02ggOo Z3QWF/rAbwQ2xQsa8kD1xxvyOzVCWdUkJxbQ4wS7JZnanCN+M6bYjczlSBlYdMrmS9BsSg58LVHz 91PR4DMNyBGfoUhjuvLhwhRgrWXh+b6SaPMCqWGip/NGo1kl4asD34AJ1WqCd1YSul8T97SaCQ16 XudC/b/cPMBMLhnh3O0AenW8gNAHruhrTwOJvvL+Xb3pUA3rjBi0+69k4Zq5sx045+UC3qQPNv8N ABpp6ndAS7xrIXtAyISnFzqE5t8wz3GbteT5e09URSF7yW27f6h4M2yHsnRfHNIEnZdA7ZKWKfjZ uTI6iOwX9JW3Y8j6eq9qSYUZxUeuBrxIIloePQxzM+j51r5Iag+ZhGJ/XvQuW1RI+JvzogIyEZgB TOQhHm0lBcaFQHOiDt9lHII8w0p7vwkjFbrq1GGfVyqb8o64FUVTpUk/HlU8+YjZmdcvYciPAhd3 Za067H/B85NZmTwOKjJFe67VhuKFwJI8FXxUiv2FCs/hbpJ8sN9LEKhc4kYgBMVz8WYf8XjtTsdh D4pKDsrYSahE/On5cn/d+6v/vz8QqNRMUUhWcTA0NCcn2S9xQXOf5fRZK2zjeCTEYeHDvT/supZT uSUCo7RXobKYCsFgZytrk5D9C8IOWSl8K55Xao91niufIAIqA0bY8vnweDByjdSYNlRiiFtq+cwc JtZt06Ujihyqh7jmNZoaAyY27HCBzpRN9KbG0c6z7ooKEL1YhrHkNQQouQ8VfYAj5bAkrCxbTt7S iNum5XHH7U8XbAN/U06C5HQtYGpoQmDqcfnHWXnIQiXvI42t4feepT9P6vxCcU1ctwzHkFPflt8n sicsumL4/w5mjLRsSByusAG+2B8V3KrH8GQZ60iDAPjjBQMWRz+GaGcgtP+moM3MggRLkm26pSmQ 4sUBQWPzGLQ7IiJEsXj/u5dmCsi9JCXl5xKqYHrznjQGc3BUdpbZGW0TzP5kKQElo2O4yDwNa9C6 21MakoI3a7kIP+oHxWG0XW24P9/0GO5e7JQ3q6r+L37f6AjrfOO9J3w7yKxAGd7F6SvbpAdrjR8B H17TN4EedDTB/ozKoAanRN2FGqbA3LKu7O1FGvfaTq2oftcGhPJ3K0YHAsDc7M5C84495nfk0SaV ZbTghg4Al4w8EImgwk/9+HTiD0GrDgMyEsmyo17nqDh1xMz7h2+F1LkEwKXhiKbw/Pl+xXAhx3E6 tBUID4woC2vzos/Bna4FJJROYEOn+u7+HoDD8ZL6CYTusW/lL+8nwa0frjK13cu0haMrDYdbjHBQ Fdy9SE7fsR6u+Jc57XsiWuqTdmj9YCHLA0WrOfavQ3aimf1EJMAKmuWns4Qbe5HdFw2iL3dQ/b3/ Zg3IqawRjym7RKhG+cysJUDObK7BkY7dsSM1OvIEaU5A6wv69aitgNC6Gw3RuReHAx/1pTY/IBdV 32fztLSNM/m3vMAeBj30MRzrMAJnPqicVDPjE74LQmmsk4RuLz/sbLU7slDzOgHn/71LG7NUazt0 j/PT3vJlnjwfYHxaLTmOYbYvfkErmcUUNjN2GJVAClFp6oflbR1L1JXQPEgsa4gXEcWUvWFlCBZ/ SaiBBqyE1S/xE7m4kr2hqnu/x91i7+36gf0Pc9gwKlTUiq4Db9f69BNMMzY8PvvqJ5sIZ4v8jq2I G/pMqfQOcrifw+gagdEB3wgTuADteE8LmDVoX8QSXgsmwm6TVkx3EAT5KQkHuzrEhZ5rwZb9NI8k pycG/xzxlDMNxagro3W993/GAkFvVbu6VFigokR2uf5CIRKgapvTcXG6/mkMdiIvnHgogmKEMQiy 6jr5w8UqJTOpPsn15iqsQ6mRuqAEmzxk13W6Bh5gXcGCX7yVduUdmLIqI1MVCQbejybGCdDjVZo3 d9iFRmDNSV0vECJ1SlMTBRtJc5N8DXaTYMisBR98+n3lrKbv7boTksXWtAVJ+DdVLMGYwt331LvG LVuymGtQZKco1RVL/jR+PuzzwJmYb22L8CTV0sgKureFQTSR0DYI6m9e1zd3/+mde0XH8JrUuHh8 x21WJb4qNU0ix183cSWtKX2Y7HaHboXZY4C83xLP3UzbMSLM3WwNNJczGQjS2LZZqejpyN9o2anR QEIG/xNSQDjtDMR3MJsL7aprG+XlnWJZJ+GHx/g4oO6nEHWxW1BaTK7BWjFZb681BmjrjggXcMR9 JO/5JLxeNyH/zWM3ZU+6JgtM0czkwSvr+g8hUXFe9UldI8jHcP1kD6r4HbCklO50GmXbOfrX3fZG j1rhNI+I0NlSZ2drCC1VVAykNIKJiY1jF4hi4iFbcm35MNz2dBV9772TDcNi5OiNiXsJf6U2kkkX BDGX1FQMjV/Ck3SjJIwGrhX1bOPIDSzfswy5EPc5+AMh7Ga+9qJmF5n3nZ6THUNQ+neWCBgVskbM eZwDYXO3Ff64US41zK6BirZY2lsyN2Xnb5CFYMfN4GHr5hYJyANqyS5L4S9Opf9C8fUG5vsKl3l4 D8RwfIdNOVu/DwY70/sG8O6yVaQNVvsu4zTO902vMSm/JeEJdm/DUcAU1rn2U1wBWPGQ+MEDETe/ RP3YMIDZBDQKZKzmCJr76OaVXbg75DiAyNIbgyY0IC0iOKtvbBLNTEl4Vf/mPqGl7xaO7Ws5z6bR FNnfuR/Vhfx8gxvuzjUSIekNFDXfmuKR+uW/kQOTEwoisTOJiryurss4fW/yNgwR5nh3oNFY3END MHCCztFT055ildmjRSP6lv2SzouS3zexWnEVKX6RvCIBGmLroTJjPGNuDJAb0uhokseM+EsDNv1u YeKQwHB99DYRVmAG1b/pf9fBmbM5jSisyW/pqplLGav21JDlDoNocL+shQUBAUT5BLidM3wwHRPV iG44Nq+9lGp1DA3OYAxnU87jhFty9BEacLXqq6GXQHHvn9Xf2m4hSZquuWjNsVDMAhAOvKRQL+id odiyAOCGVNXVGF5/GUB8xNWYwN1OpkgPp4hGHDZhkPNbuwIkJl5C4YTMV3QdoplYOSdjOpw2Asuh BrXs8YTgldV6Sc4YkYZWUYcuL7QsaNRjSvveKGNVWGKAF40ACnbZU6XdubkzDLFMO3wYA/Tp2LbD jAr43q67Rxi4gKU1LBv8QbmtR9z23MCqgmBVVNf8s/XBhrdUBvGhMkrmIMn0l5hi1MkEWTI1rW7q 2e/6WUPP69wY4ekhtgBXrmee5UFs8G0fmRLSX1aMkiS4JdZ3Uw76H+s78M2S0OneLAlsAeiqswAw SR7rj8HrBOK24m6QNe9y8zNYW/kLTdA6Ph1Ly2iktsWrQ9HcJocVkUiDV9/8G/oAOmFO3ftqNoAo 8yBPmCb7ytFlAla3oA0kEUgTdXVWVeogfQL7AHVyI7uUEOu/3OomuSyBnxd07IdViJxio1nLK+ZU LGeINZZKjUElTUhMxLr1qMnVF/p8o6yDi9vLx23ZRLoRHnYXO2m0b4sFlnrf4Jq0y1dL69QC2DjZ nBi2Cg6n6WqiOZfdQ71B44Jdnh9lpr0zKSvTTktgUKG/GYSG+hQEqliX4wW8OhnxmVcwZjhFcwvf dgj1XxwINMFehvLpypyEaQUbL1EWHmikwxjptwSgkXMDXhNtpZ32Wbd6QtLuaAIvWM2VQ1YLlwzI 74Fc2xARS672vr68A0o9j1Dg1+pq3B1U3bjCA92qlYqqUPb34XiKv0Ij6INsPkIIOMzxjvLBqDv2 I41ir8b1YNndTdscoloGoihznrJPL/rYJ282XzLSJY2eoNMH2J7wPEXZwviPVO+rRrHgXvc1WDSd Kvq9WWeU77O8P1NfR8cLOh5sJDEDbl/nzRj5NC4CVI+JHJHcHD3IY9UU4muM16Pg/cq6lbe76pue y2qxeV0LnEcgd8+puvrWtaxGBZQXnrs61BFazjsC+XTrFOE15X2pk7DQK4pEnyobB8tMCMhhOt+U 3ViIVdxK92SO+H6EaF31bUFdDDov9Y47uHg+OPM6YBWuHZgyr8H1vQrhoBWi2hS9WQrc8OQ65u9R kRMV5rTFDYjmtYjLsM12biZA17myFO9ZcG/hKkamBy4JDm8p2lUrzWl34DOFrpdVT9zFYs1KiREn QMZ2rCls+kSQJtcTISKR1+zl1xlRruziATyxOHWv4fdBd+Z0feech87Nk9JQgGXpGHgMVW6UhjNY 1vUme9NxgRU8FzvKQtpRiC/UUHOJYXUQYUPXzZPE5fhz1p0wDHmDJa/RSQ0Ka3ZG6JHak3YslIW+ oRkGzHg2rbPxIKpBtb6KngRTcesNvbTO4T1SUZ4UqVy3XoW9GW6sKDCzPJibF6WPEyBVnPybQ1IP MYVtYacb2FT+znCzx8UYsLnffdQC5CE4LtRzWAXyXuCDe8tP70u7emJeV8FpX6FlaOznH4XlOe/9 5oLzTtCM+jC2ERxtrPHOhJN9VI3Vohkuv29fvdePPfeJOzP0Mk9guS/KWqXWRP2bcD0UztHIdgH1 2txqst5ebkgs1bSyWmzgBj+5k3QxMzPxGI7RhQlso2/rLzclaYwai+8uxed67pvjNdJ3wwQ/Vt1Y ZAZE++yTNeoDDJtuaO+1pOzWgvnwvfpfFL/2Y3D57TjJTA3BCDH8dVmBWyuOu+Lqu/NqAQ3j5eex Lcdtwn/DLYc+tGaYm8BzBd+pHt9CqglSIAVYQNIly9kqdjxx70VUuhYGx4yWnvWs0pHJ7A/FYcTK AzjxKTRYNDqXeDSLtTeOvwq4Ur5SVjBdjfudra8FeflQ2Vb1ksMA4Kjwr1BAULXgA68D/p8srh9N rLKgKZG363OQmBsGFzw5nRCq0xRZERH+YvrFx2Qz1tI4aoxsvlV51gyJG/nOgLcsiCjOt32VoMUs LQsucS4tCXnaVD32VWpKOecBMqpCNaBmvglE7z/FKxCE07cCTYQZYuCrvInlObrGVVv2hmdcqCl+ 8b/P+9le5fSza5vy6yUdHRaLq7mNdBuYu9yHSJCo9NFwCRWKhnPYnnsLvyGvOkE0nehGuewM+6Rn 2wHQkjxiY6tc4lXUuXucjH01FQ3q0Njl6OpWdMNVjTWXLeol1xRnJSP3iXz+T4mRrw08/Cq/wwPd EAa/IVFrlmldYoSsmizM8upT3hdTFdtz2s6nTWZAuOJzmMLASh5sHo3p0RwzM/Gg2Nou58FIf0al CLz9+ccciXeumyfWj2sehA0kI2D6PpW0PS37Iz+HFEAxes2oKmvp+DxBuAX9k6AT6jXWULv+PxMQ uz+967XhkAZaI425cusFDu6EK1+BJWExitQJOiLerRaNDvCjXlYzpd3BxMjaiCkCaMdUBhVU3Ucu SGGgHXxFwTtFIZrpgN9ixUb0AKQPxH7Huoxw6iqZSBIoChTNknCZaH8YCSeYA6cMsHUnGdhZu/9r D9P0po2WX2ClBmxKG38s3Ct0KTGPfPUM2gotqEC5nKZEb+J3+5h6moHHcWVJxeaEN5UbHIieD0KX vPeu2rj5VOP7UDbzfCo4q9CYRbSZVyCGvPdA2/C2Yo0Vpq55VPyrWRzaMwdD2J3YxtZUVhBGjPJY aMkOfjtDfJsGyrEOhDgzMArBVzmHMp2bQPmrzRf/7WpRmIalW3e1nwYWOC/djVuB3KihWraDfV3+ zL3F5PKWNs6xkJbEvjVCsY13zv8JsTAtbqKCpi5MbQsaZwAn3cOx/JCUeBN49KPW8CZDh8iAnvoL m+K2agFF1uYvH3dJIT5ia4+HiUBRy/P1Hhx4kzy1BXQxQAJc/+nZKVbSxY9SZEgMZbJt90fkU+lG hj4eRRusnZhXmtM5xPDLcSNyojRQM3QUMSXxwg1fdpWMf4Q/l5aCs3Wxbui+DbldtrGFlmAlbzeB Q4HWA/WLT1VJNO4kNXDlC0tuBUSjX9K54gl1uisMXrN2AxUEPcw+7d/tDKSBwaFnpgLU4VWrHRMm /k8H89t82je5L4m+oSMTT3M6ItvknDpJrvKd36pU9CgiJOexUecJ9GHqodOrwuu3cl5GxlkovuAb Hth08DLNJJW28RavLym165th61V8TsanRiNhMMrMlKENlUXx1Zht44T5iORcGI9S5biBvO+ttdIL DGu5Imiqf+d+Li1su+U7WcvzS53m1oHgVIw8ZY52uMrtSo7Dkn4JwNVYGldALDfYVmCPwi7R2Moy G5/jb/pXwkf2ERe23YTQ7gyfiQis+F/tmfsUBl4glhqa9A9iUjICtEm5dBTrHz8x7W3HqThpWCB1 LGV124yzX5ybOn2PPNyzFhwnFWUE8wztVdydR1VHGVZa9mUOA569noTUPyf8k6XSF4wZlCFNh5QK eV4OjOgygfxoVAJ25eJwOY2RgGiZPv99I633oDaHp65+Z5LuFjMyAizPKpoM2D+QQ9etzQuob2Ds uT2GP7t0zyeB9Fmz3buRaasfzXi8aWVBMY3C/E8JAfqIjHDbQfEPCYQIjXGx2odranGfCkzkC9rP 3lrHnivEi/msUuy6nIJjTJm/MtkRbX8yT8eAC8/MHuuIsHRjr+xW0/+1cvl/7222dU79T68YRuT/ sX4KOz8AIb4FaPWSuNfpA43ipZj+rO5F+0S3G8XreZVWG526s4DPn1GS1WeIV2G9v+qZ4cH1XKa4 CpmH/Nkc1xrvtWYVT1Uw4g1EoAsNoS/mB3oHwGNbFMiaSWL01ukurXmjSJHG2vcNsix0LCoisDze HKV5qv+RxpG117ir2WlnCHQNbssImRj9xksBHHvWTxLdCphHtyYvZasCiMSHjqeztjnpc0Yd67cE KyfHUvK/5gTUHsWlAXbzMnr0T2iy/k+lsmuYELPOWOcWedWqQ25FM9/sWXZjLsHXGPAhpfJt5/gc 3TOj6DrH/6gAOx0PJSUPBUzG97jVmDdWWCfGj1/+Sc8Iz8CPc/O4BWl7VSPfAwD4nxgEN5ltBP8j PIhkzxku8RTkJ/Fi7QF3z7pgSSx0PW/zmwoR9DpOPtH/W2mJUnsCUIKGuWhYeqlChzb89jIu1ZiI zO24nweR2dqBgDxT32a3PghmL5w9pv2CXQI4V2Zmpn7FziIPrrkS8ujb7gsmVngr7416zMX2r/pR 6fw1Nw+/ipKEEAboGWvaMlflH9LfoaGTmsvA9dnNSFF/SZJl2boiX8g5VuaaLeQ+ovYz8dMTx0g9 SDmkySyUEzxnMVQafPKUsUJQBxicbsfpRuJxZ664fQyFF7HrTFxobi2bqlFLq3NbhxCw6vIWsfFO kv67c2IMUYKf5LOmQiOVy/yinGLs6YhQ1mGDtZr1mV47cUowQYON+u8RBDPUqV5R7SrCCOfXFTWy 6iEneIlEm+YPbN0hiNsL40ID5BTte7LzwOE9LWIY7IQIVzGxmHv5IIKyCluBG/146wgkTTZ5V842 CvRqvyg+ZwnVlYbMhQ6EX3y1+474f2TokvG6aeHKAek7/j4DNsCXG1nHSIlSOxCAbvPbpLLck8K1 iAZ4C/hC4VBfoEAhTl3LD0f+5eQK8/+OAWKvDjw8bDgXkl3KURZdr800ph+iwqNpoYUVfH9QOs6R 6VLLJirOQto45Axm3C/H8mIgfEne5GHymvwaJeKi78cfBv0OaqIoKAtp62lYLEQwvNB+k57GDWkl ef81H4YkEHSD3ofDGYzDw9dXcjyMrN81bCjLERRRZUiitlrHboXz+m04NX74bRgYv2Y73NNcNGeI F2zt/lh/4dppsLmh0KAN7ESm4nlNiSDjJ53cy3xUQhXlLkeREch5CZKCe41Q2ZFRKAtQTg2FMOg/ 62SYU9Rosi05/z6s7YHZKfwxtQoqAALDBNB11CTqBwDkMfyKIkiHXhkwVo5uGotyias1gAw4Bkfo r0E3KtDVQa82wcLxAWIi24MazILSvQwO7moLYpL8OSL1GNM6qAVgj0B3sZq5Mbxg943TJ/pTgqYi vyHn8Zsxa27UNZIx544Q8CiQz7SJOudZB3rxwHK7X9EIgnVJED//zizYek2YvYt6TBuZUk5BhZD9 z2N0XfWIWSauFpkqn20t3q5xQhsZ0KXKCoj7fIN4/rwPxqVUc0dd5IJSZQfxelMsd/1TnbxFWt/1 ZIfjmbI4wwyd4rbtRpuWJpfu5NnUle7WhLCTz2IW+uZotFw3i5JDA5fDvj3Q3mU0uaZlkvOdMoR9 cbtzFu7kSByjbCztYJCn2/HO7XbtZYk79+wT4/4dIDsgU8z/BB7KiT2J01m3fdqvuMAhaeYocDGE EZyirbMtBxk9kD0Mt3CmGva5KDlPk51/bx/CHPhZcb9rCW6VghSQig59S/ovJH8e2PC1kk33Ocr3 yXQR6q466sH/8MbBhgxQmtnBUgcvqOJU1GgggA8MKyNL72Vt6/bz55umQPpVUafja7u4SSiMAQ3i vj2aCc8L1mnFE+uoa2aTXuZvZa3Wl87Kj6Ar7GT6rRlV434hL43Mizc1ibnUGXwI08VvJ1PUjxlS qlzxJqszsRVHX/+GB64yxcDxtIFI57ZliHX7nvXl9VrtslTZ/y0waavZlVHnFrlEt7INwJZFNmzt VixScIgHmTNsRF/gJ2E7OjotOYP8aLBiSUNSGzGNVa7PncdzYzu+NY71lszeDBiDGLaRSW7xpCXd k0RLqQ943wrge7HomDy3oeUELFtkpWq/fQeYXc70h0MZayLWyNLsSqzLlyJimQrWDwDw051vR0MW u5p1bTv1fHAByT7PTaVYFgoD8a6mbpfdPT0o3n+8VbrkTHhBV/YXnQbzR/q8cYI6DtYSQjP9nJzf KkoVmNuR2rZqyVdBHILFSXxAbHf8SH9sxuy/b+D4CCFJNc0R2msXmIYU/At+HjovhU4Ma2eBU6Dr uoOiOrDOWeNg8gQ5wFcPvXxseuuylWgTfZtwNmmMy5O8RGqX/vCYdAnBsckiQce/RLutTKwuVe/z DfywPxk6n+VzBKLBMBD+gIb6KFpWGb7xyIlAPTak3OHnteEoHWIcnGmfhTmpJROs9Y/j4NY0152G zg3kXBNhzWCAaWfDc9W6DaUKoNMFm0MicLkRdgMEx2Jcqa5hljLVy9/mNhCgLBAU9zYYoZfiKfT/ +lx6y+RQFQmDfUJfTBKzosESZ47mjIqTeZO/xECBujVvt6NFYOKqPay3Oo2dcrEBGK8uxRk0wdMt hpqVX3tQwS+SeDrQJas7mIks8nRf4zsfeheSWkQjp6GukHsbfTD9/YEK25/60MvnL6Bwbtza1sau 1FrvZROUHKvblekb7XI6IScbUQ/d7k1cjToDzlpXZibSRkQCLvn7m+77yPJ2skWXlnNqljA2YzwT iPQGsb69MEwSH780I0SksYRdmuc5az9fgUG/gjU1beYrypxXLcRjDVSvBUEhUdpjVo2fyk99jBR+ Zoo3AGqCcMRA1tebPftwPgvQ159Y9bcEapiDTFX7MjKQKFDX4R218QWI3zxDauIDEWtIpt05Ex63 +tAAGetu9TXRSlGZrnMvqHWN0hEXq+Rjx/jt/fcVVDBT1qMaeBEnRqZ7GGs2+bZqPqJRB6S6P6Wr Gj1za+VioWAlpjKe11ZGR0xwGnDvv6UUGnrASJPi0+S327kGKnlPJ72Nvp3V8WEgHbsjnIpYMQhw QsZRTmYhxFXf+/vGqscU0cpw0idvtQLMxOiKxlOIVeFLDGBIGZui8U195nRyx42/Ox+b7LdlFKZY DZnoXXEz6VnoLW5Jj4TW6b5X+kH3UdCDkH4mOrOXhgjiND7EVyXWhz88tjsWYRbzz7TvfCh2usW4 FHctiDb6rmzgKtAsfNDt3Q1VzmXBN7wRcb/obgBfy1kR7sS/pjgjK1IAIMnGdU7n4rhu2C2ZNpRk V59IuOOAlljFTNlSqZPPQ1NJbTKSVT/KFqtu3nYuC6EV2bM1+EQZBDxCYJlckfiJl9FtYGDO1NN1 QK/1/AJnQMAsyBu+49wBGRQSStMnYKTC3tsLTLUk8WsF5OG2hLGznXKH2bR9ksDUV0vhD+pDRJX0 c25wxO8iKkHf1qtReRpoAH1PXkKe7O1RqKPy1jCv8JkIcAZKCKGuuVGHNnXrCru4zWeQ44Kxy7CL QVep/bss0vtlAb/nZXcm3iTI4E+vPDAWIasmP8GWnbd9JtwvYxlASK+/6Mw31Qo7QvbMh+quDI0s 1sCKk46H2OKQ2puskLlt/Qk4QXS6NkvKS129bku0t1oiyciWmXi+jJPtu3z2Jh2vjGFx8ZQu/w9U ow9s0Y2ayq9nx52tQMK1Fxo8D7P9Hmstk1vMCsJ0zPb/cIHH8twMdci5uJF1i0pcufQ3iIzV8vpK 2D0T75i1E/XK50AicFbuA5ogoLFD3pvltqMJDuYCieV9vSglW6FJSGw4O9Gkixev2WL7LE+6Twyy giozh8JmyU8BiZiJzrnSJTIDlrMZPMxihj8auP0UpC2V2qazlJ9bVfQ/7X7Eh1bKVhKVzdr1Ixfo nfKA02VNqpNoks6u5BiISJhHqNXAxZYSm1JkpbBJxyfF8t2Jb7KoXnJqtU7bciHqqHV6DgEZIAL/ atcFL0ptqJd1FHSj71WtS2sVk4ucNbz527ZQm83P9yf8RT8RAkL/ygcxsUslHyvT/Ksx8tGx8GyG //0sjJKuTMipIo4o6UnHIz6yzq78szUvmW7wMM9Rw8vyjmiPJEdoZnNruw5ZNKRZbLKtLluC0xZf RYvo9g5t6OZO4pHeAezJX/c4rgzsvruoVAzJbq171hL+d2nH37T21QuACvSUS7Jtqpgp3N7X98MQ GPsE0JUpnhcgeGjvFdZbUk9972RqPq7VaybZosjWdSmvo5mGR1eV190YaUkwx56JXAt+ePWv0zV7 LY6Y1oWLJjZIOyDUuliF1WIg4a3pZxkZ1JQ48OcYtv5+hZFlqsYI+/PJlXNHoXvA3apRq3PQFJFg OsrRiZXUDlQodaLhw8Lklfk9/Sp1vcmtI2qvyz8PTyhio8dRFxQ4ndDMtVqlfTgDgTGhqSUDLH5H LRyZ+ZardJJ2cHqmQBzeAnT7EXI0JIjHoMji3Rs0DgY6e46TPoEaGbmDo9mk7gT8cy3lplpQbY0y nCmT3JaHWA80yaAwyrElFLmlqZEH74X/M39QQxlKNDQR1b0Zu9NivNTPRNSPakpW9ONIoHT7mYbI D2EIpkfllfcRpBJfztbj2Ct4swe3ERbyogKyUi9I1iHDcCRKRKL0uaSFPjvaILxrsqWeV8W/IN1T ubkZemYo+wOSe/Y+YNm52b5vEdONgcz3sD2+kwcKnMOogWKxgiMmngwSuI6gg0+Vv/XxENc3gmas 4L33p7Itgjyq04UoJCjeJQLYzio6GootBaR+JP8x5jf6fjhVWb24Du6YMyFio/J+gsdJzbHkI/8O TYHUQEdAVPPIRM3IPb1DkER7Zz+yCXOou5sVSRfLDyQiXQLsHC7qll64nw55OsxxzPMwGUJWgoLV KY6k4fAu/zKuij/6lCRc3Of8CCbYIlQRkisGWtmYjWppDxCiJZGvmG1OStF3oorO2SA2RcDHVWvU WRh8TaGwRXRatGy1zBailp15HNtZA3CnvFegPpGbaFtmIsh6Dx8S0JUKm//p33JDV4kCoGiO0a3c 0vEIpZ/xrcJHesN7OKG+faPQspiwx0vNKYE4agY3q7vG0Y2CnfEktgFpBwNIqLkKiFf6vUborU+T 4e/aDm15pWJx12iB7s4n75mFzqlfFvdwijWRLG3KX/35hKo6JjWsT2Lqav9CxGXkQeSEVkDnvUXD ge/OTejrWns8hL3INXDzsV4XBcdcokox/MYsHXjQExnkN+VqHy1JhkB7qdHNAvwgIy+OTgyOlm8B SW2eMD75VBOdKl1xusbrGdaYlAlVAPpJVnQQ4+zN7xsle5vxt0PL7MIqO/XxdPY3iN7V+Zy94cB6 PfGZ9wITqlZdm5DJxRNA9E7Tv3KNCELMgqC2PUg4FUUZAYajGH4kbTxVBXpHyoJdndhkheV3xwR7 cnb/rQQUH7bOE1TU/Re918aMn1VGfbLi07KA+h01OLWbjgsGpVf9W/fk2O4n/l5Q0hN92mTr/ddB sNJ8rU315f+zRDVqwRsPcMftgGfPXD8J3dR0oXPgc4wJ5BdCPHs6Vzd6HunFHmSsl79is4KSG4mW QmfEbACdS7Gi6Fza2/p/jm+m7VbDCtaIKqN1bp/7+nxne9JwAmgCAyntT9fjqJ9NmJ0TB3G9jqT1 80ocsW+pQ5DkWkI88wa8nD3LV1Awdq5RdBcWO/k5bNNwAQjLJjUGk27Y5In+nI/WdlMNNKaqXQV4 7waks2Pdk5Vgi3l+eiNJ0h9cRZauDG506lnD0iJA0oe9h9UBYoSq+X7G51LBwqtAKOI/ohdqpUo2 h47oGetGaOa8RWibEOHoW4yFo4yUZSZSafGLLoshtOyDyo6oZWHU8a4akzwxhZN1Hg14k8tZfoq0 eL4gVXzHjcusx+q04eYR9m4VDfFfjlTZ1tkbTkM2Zk52lCbB5ZASwM3jPkb+fuJn4kFPxarrYiX4 Y1DI8DbbzpYsju5Rm5ISkmn9IpDF9mRH1mcHvVUAi9RG4QPIKx1BMBfrH0ZXtUJvpCrDFpO16Y6H wDPSW604vTS6j+2OmkHaJK+uQ1UJzionalmNRw1+7p3q55N4LRuYIVnO5I17v2sr4Ca9BQqw9FZY n7pj4uDxZtOEcurJg9YqL/F/x0JAMr/OcJ5cO8WkpyLMR7BCKizDaJQh2RfVDMJIdl4Rr0tsyJQC VD0mXP9FpH/nIiYqenOiqlh7d0xCILyTj4b1a8m8FKM396r2aKVeaD6/fnWELQOLPh3g+cbwiHVk WjUXqFB/8SLl6il1J7GfGAKV2BwnGpKozTf9Irlxr9XBu94f9bJ9uSBU0dfPf1erKIvRcVfZJ52S /Q/yPk+0MyFqbOGEMq+MghsVbEyamlbVN/rXdySnt/j58oyZ9e+ctBtikVHuun+KK/EnQZIuIDou v/0aT4QcRsDeuwmhtnfG+tzpq/gzHREp8DOe1eAS0uk3irzFaIC2lo8ao6lvTMnf20FDy6CKgxDE 7foOgaauNvHHIQyszPttFM0JTZr9IKQQm1FdJQ9VhipRkaaFlY+OTf29xQhiQOKF2TDtt4A9Wcyc K5rui72Uh15SR+e2esiPM04Yle9B4WC5BgYxp5oNLOosFLidsj3U8rkf2lQByzNtfSensWpjxsbN BaX2n3M9rdmnSDWtbahCPB5z6LTQfnIsck3lT7IZxeM7D0jsKxDXSiLF0lLMFdn/6vSkT++rEEEO RhFmBI//llx+Po42O1u5Ei+jf0XJE4952NnQTySOGQnoVIpVd9Mdyn19pXqMunw6OgkwxhEMDboH nfzg1/8c6NBdW1CMgBnNM1o2+wU93rQmhc+T/e13KNLfBhV94knzqrc2Tw4n+aKf8GoVRngrA07b BfLUfkac/+YfVJT7OKVY6XPs0QdzhJR/h1t090+G2HGVCQRJuvXsU9EO6kUvP66ymF19mZjGG20z ubV0rLDybCEMkSR8z+5mVwGh069DWfv4MUfxrKb9TKlkdd+LqOzZElWNwyUeK8JryjgTQm2av+EZ d3Ez12gEc3gzsEHUdbu/qNViakzIyLSVwAQo3FGkgXj/krI9p1HRl+Zrow0F+w27cUdb0rWyRP+G JlpZU9HGLQZpyMIs7OdQdWJvaK6aAyfRnGR8cCuaK8EXTe7mxQ5v7ib104ZFdWmmbV6kddfFyu8j 8uvBN2Tnc8WSR3LrMXqgFWb2/vo4O5l6K0OzzgiKwCntzmlqnQ2MMggwbRoI1pGmXu3R4VTikSUp hRz3D73Gzth+DtHa6xyQL5Y9Y/pcbs3qFZpHKHGNPUsvYMfiCO8gvTz5i3SWs6hYntG7UYfnntOe Onihigt08tdA1ddwNfCXMpGbeIOTB7ap8UPiz0pKmi3X2fKRmxcV4wf+hiDk2kgot8Cl2QPpYsT1 z+jMSh/Qr/yMhM8FEbrwfzE7GtqaeD2j5wXMEB8MvrV+skt+RMMgBwZ1YXvjKwCUxsPmc9F5/D9z CdkzyjYZ081LIIzBZia2k7wTDNv441olyAbXXkaIxd2pRE4Ezr+Ms9mLfSiDey9BnYtdW8bY2P/1 ijZRB5pr5Uk2HshhJKQPjkfiEViw8CSpO0zAaBNV15SObxiPwkyUxn2mtfG9FzJIdFyjGpmPPp+q dPDFaEe/ayec9BNbM6bPs3iHIfXbjearJ7jHtoDVa+CUZywdSN93yiiOThsqLy3ZRmpj96bSMkwY xXLygGOBdFALBy+q7rTYgjXDKRj8W5bVk4yCinJ5mYKUoeA3j8b97h8d+u6xoKp0x7/yi7Snhpvu 7SE70v4IkIpkKnUOp9pyH5TbiWDR9juVaYBgtLxxyFLLgqiu12AtfuxwDXhM+676JXK/VgbMfbXU 92kXJb3Oa6UdddHwaR77NIRIf6synca//G+3fDVlWaymLHg4IGJ7FRJexNSymJYkFIkDyyQbSDQV ornJdV7xcJNqrgfYiv6Zh3iQ2SzBNiEuLq3DiAburQ4GfZ4WNep9O1MkfSRc2EzhGBCMuEbu6Ugw 8AbwC7CpUwCwFu7yLmaUxdDiOrWdXJRskyO8/A3UMyE5mTKdL6HhDR86zmwB5NoLtHU60G2Nhv2/ 9f15A70taVp7jxOzXGA9CxwubeDPEtUMAvuyJ5PRdPbioIcIcU0uyrjdhvlONKvrCguD2UCWWwVg Wl1BzvlRy9BOIh54lnzDgD2Ga+LzYJuPHgDrDE+obJFkI9KRspaZaRnuNv53TykF3U2TLR5ojW5P mobv46wQ8jTdAm5HvJlt8VdBjzgPVr4fPGAv3IobA/RWaEIz+ZBm8laiGaQaCz6ULREkdqLwxzx9 TEw5QhXWOsw9SR6qh3Qr2r86QGKe2OBPS9VU3K/ovfP4oE2ga44rKk7lh13G3gmavweDUCuk6d8f oMohdqzOaNzA9ypCi9AcyqFJkjgIcPrSnE2UX9LTmDPgwYGIbksiEDfh/xQOYrrYcNGKe30F5ZFx SAwPQIfK4CZnLuxAUbO6rQIzzKQodAuBqgJXBBfFh4kXJkIE+vgKhXb9jmWWU5EgoXrqT+QMU8jf EaxgWnXydZhfwJC93zPyatQ4F8WaaKvSopFholwqmGSkt4+Pcl36RGMKARt5z8eBwn25TzvRXJ7Z 0vZIOUshWjeNLMnJ1bHEimSUfGQEBaZWqFL2z5h3h+S6B9qLKhWAYAniOw+ZjiFItCAise3S7MoN ibN7Zw2egYQe7vUKElZBAdJdsGAsZfBtcrVdLp5Zyz/aTG25znrELVPUFplk0qWqFUe87oRuxss8 OeRgQsBDShZ+69cmeRnOa4rQFIOe+IHZzCyWWdF9UF8JzgyDIt9AYox+4QvRsYXI8RO1Sp+O2UEx 2f1jNKD0tSklhQUuCUMLjxsP+K02YxaA2dA6WzG98ICFkUZU0zF5e3NElw32pODV86HBCVEVM32T +1NpfSsz/uP+wsI5960rXOUx0B338U5qRrrJFd8nJfiKI1TzAs+tgcvF7J2ulp3pmG1lRu9LFHfT jIv5FfNX24UoLcG0cnbz/eR6rUBQNdtdBF9eiDtq43KZfJisIjkO35J7/M7BESdNDkkcixJRTI6t Kpyi9K661ocaByAJ9istxbsf7U2QOPDdlhjKPK47qgGm3HN8VSELFTR1+aBrazanDZcXrdrL2Ucb fhfV2rjAwjmMyfBbQFvw34JethEImi1bF/2WYJU47NFPcXPVSbGsBLT1XowaCc8hutVN9l4sc6UF qmIKdoro6CuN2PokDNW27YY9BUZudKKIWSrX8ZEtUDujpeoccyHGvpoXfUI4yVk+LeJH5HmPPMSI rECxynaIPgK3/77H5mXhUMJMHOsNGGM25aXEHevUzYq/r/cLQ86i0y0eK8Ev1lNl26fc+eupXNS0 WQKPZUquhEMta06jVTk7Wdm3Q9KYVixYvM/Xk8V08KbJKC3qI4j06Mpn6YbeSuUoovSwxHZlEPit mSJGJHOL841vX7XQSX4FnIgsWaammmZnll7cPF8cnh67+gdk/NZRmU/ze1nO0Z746S6SlMtJBCBU FgDBMxS+al3VEkNfVPL+i2/717AnwnUKxoZ0EPQctymFodAVoGx98aM/MhTFmZ8VDTFkFyPIcr5I ATF0Z/tnDam79eWAGvaGqlNDTk9yBkHBMreY6dvO5wZdPmaqJFe+bQi1h6w5xCmEeA5MIl25Zfyv u9JNZ50Dlm5LaJ9543VntPU3pXAUepKC5EWWJS9L5GwqC19/oH7/1pNfh9nsJOgAoICzyDFAE8cU BCaMjqskmNTuHJvrhq+fI9TWqwhDVUeiQVfra37KZX/+f0V4cSpopC5Ds685ENvk2d8zteQDyuX6 7szZa1orPdObqAkvEUgsa9RpzSmcVCpAnWP/HHfLx1BW62ECCVi6DK5GyQlai+FXNVkn1Qj/qhKx LDNN4kKjDmZKdn7q98CfIS8KB9LusKAX522nqiZj0Y6G9utPa1Hw/qeCUT73cbXpz8oWCRJcFNKu 47pdQYA7w6daIEau+l90nSA7fSyn0zZHT7/36KwRJjM/ZzEpPp1niGq/ZPpIH5ETqFQX6sG4naDC TTF47uK6fr2P0HxNu7/UOdoyqlzibWOaZDD+SWgdavDbqT+OH91I1h7eLB/Of8kksI6snnXVSGcD pgohu5RReLr/hTISiCfNmWhPpinOpapGSJ2TKG3L4fBppxIAoktS8ojSIg54iXBdINP7AOQL6FVK /mkpHBLrikf1Tl+ksX/SDF+GC25u51LgbHWcb9/luKMSHdMeVd8eqLhV/3Db4XT/j4uFQw3gWgid OPswUqSXOUYHVYVcBv4FUqBoGCMFOu9JY2FdoY/HWg0vDxQ0t/QWlrebDUYFltnDfoJuREVtYpmm nbBv/RP3c45MBVevUJlVENd9h9oKdGoQ24rUcKYqRXRFZFrPKlgihn+Btw4RDpR3RnF/vtj40w4O oDxkOkP451conbq1G/1yK7J+2AkWQTnsouVoKIdjwndGsPx9a5TOvEt43A7vZ9Az3djehXZ3BQmW o1cKlHhlRTQsygw4c4QsO5Iwglopt3NcHlOt9mSBJhRJjQw9t7hGIVe583Yd7nWzdimeJZakwEdz O0H0ploYIDr5BRvaoVfDqFvioDHOjEYLGUFFSMJlOKeqPTdB5A7nlEgx8Z2viSHzCRWXw8LlKpMQ 9u+0ETkx7n/etrmto6sHbTtLTnw115OlAuMfOOWJG2YGfewFpv4ccEcAbl4T1Wpcl7yoMEoh6rHt WAf/bkSagX7K5v3vlTYqeCB/1cflFHmYwoCGuvLNxQffj7F30oEZoS4F31Is9DZeNqN/cl32DDfc oEK0QCGzOQlXQukITX4woYX4c5Gd21xjxhdpjCDmw5is237b4byTBdRq+sKEXkEnN556fwAflPZz ivPCfCSIrcHtG0KiScHlqRcfPN5ppkr2y6OHRjcPqLigZKxNOqGYkslBybUZNRl8+1Wj95XWTHzc gPGvJ0RmWtiFoLCVVM1i0Skw4QUqm2ofgWziBRMZR+n1XfGYdBos/HscQYDPFTwIlhNbbFRWpkQF qbB/zrBXX/77ZmjexDmwqS2DBnX6kgat+FM6I4dLgAmq8SKRiBNE967VFfsRa8YhAYQtPpB9z/2D luBQdac3o2DwF+5CppU1i6zwYG5bhH47A7xCSLCFzZ4TOwjbxA5z++uU/+j4r+KqINC7ydknDryj +JMJ+wLNxJjFyqU7tMOXsOqzj9vry0A9pxQ9Vszmr70RisW1uZk1urpOFj3BK2QyVIhxjbfDDVs+ EtkVioAoZaWVnhXjM4uaS7noARhgX6lke7sy+VQm9QmvKD9omfij96fQHyCrVGnH/RAiebpq2QX9 EyRlsDfXrO+rX+vH0FJCo4/vm8jywWuXphxCikPsyHJzXJEVKeFhcTeRp8yUuSaDxukHebntj0a2 WIrG8VMzxOXwCEvqqqUxWoQoebZWTv3CRHx+RlAIRwQ/RKF7LbhHGf/71dSBM9v5PzrDYyWekCn5 wQUXpEQkj/ujGOiqy3Aqx03VPBJ8MnW7+a70YSyPb94upcIPPXok1rg8JQL9t/Km0YeKn1gnbgSZ jt/Z122eLiSJ0j2As6kL7HEJxCRY1ouUm/dDcNtcAsEHBDaFQqB1tDY+dSt2NanTidZmQ1Q6JDx4 G0ybVBhPkNvX26HP0stQaDHTygcVgpZmlmWPmymkItqowGuphAqlOxSe7TpZqqhayGCHLp1oEjgb cmZnlwThBlcBWIbUb2gnW7Hu8zHH1wY6hDt03CYCgCrMbI/9rWEyy+vfTjFNzJPPaJBZiQ8ERKEr ErZoIIpnXS+aIFFdOhC+bteh0IVJSnbBd6lHDO3UjOhhif5ayuqPtuxehr+hSigWi5KCo7I0TvQK L51kUSF60rpjLaxA0/Uzh2IboRIpEExUaEmHLv5bgtVtuT6Axwed1kRhl5UBTEhYu2qgBgepHz27 0IHP8aVHOy6moNJQ0OB8CaEUrEGYSlfUV91q71MExX+jZqzjXokCia8B/0FgU3zjke8r0WHKpGOP qgtJWVQoYujyvS0CbE58H7KzoRxGtXHSvfceXcubjvFwCHMthHWAE1qu4b0PDo8dTKgotGadMQ3j YSrsb4srUqsZ60NqMOIB4pg5WS8Q7rVcYRvcH1+JAFWRKeFvabWhmt2U6+/Ten2Q13XnjdeKUj57 oTZ9zqlmJLivjPIW4Lz4hxZA+Jii8UhNyeuVZ/y9P4Q4Sd5ESgpe0Nr8VXUV8pr7XgGfNzYlju1b 0YF4Xg35fAfcXdhbCBvGybyzjijjdZepMkWQlPKQzdHvUNr2c7Easpl6ImlNOwmpJ9bF4YlO17/7 xtgM81erBHNBWHtUzqcRZ0hlSFEw0V2VHQyxHgy8exHvQ/kiUeCuOyZfQcVFDxSinwBiaLOpasRN 2PCa985sbgrDQgEV6vlK1J1g1ZbS7o4lVzzU6SccgfAqfufGB2v8AvRYyVuDoFIP+JF9d7lwNyRh V8yTOYjzjQ/CtGjy1YTwlgdwxFyVXaxpJUxkcXprhffiQ9co2idWPhBcDuuAdfT70PP2r2VJkbEO JW3qMMKoD32GcdEpTg/lYz8G87PEaMaD7t3B8OQFleRKEut/0VmOzGzxLTqtzs+iipwY3CJqrD6S hhNtkOqLD4O39z30xF3W2m+czFLTiNmn0pr8hW/4H53GnnZGyVo/5+CnMcS5UoMtPYtbCw4Db5AX V9cg8PCVB3jfaTnJFfJwDfa9SShETIlDUCEmQkZkFTX7d8cq3m8QMNUEbXcGdSSdJBeHir1CyPvF a/Sp+p5u/vllT5tn+F1q2dYPA9y/PgwOENg2MaqZYbMCnz4Hf2AGjl62zyVbJ7AXZrVNEwPFaPMT ySOFr7wMjKq9ibhcroXfGn28zdKlVbPlcqsurAngWN7yup9zIuVACN5qgzZUwZS6EJg9LuVgr9M4 TKRqBV9KvvnwGckBsMDycFIJMyduYTIJeQN3virpi6Zym/+QVxYfLxtlTqP3tnBG8MPcVMbHqEij ifeDXnNMT9LzIhYqnxRlyHBDKtGIIr5543tZFrn08AjY9wxSQydzLLsGm+JDhTPAn4NYrRm7ehkO w1M0TlxbczwSahf7gLxC67+NBKD/3aNO+KLAlnFC3iX2q0rPM5AegVEJFKljpZ1UG5owInUiQBKU wjIgDf5jo1xNFgrK+J+FBCBLoRsAMI17WWVl75oDr7XJ7HE2gJ9SeTwAlDRdMvH8VpYBrz02qXUF fGbRmh4Hk4mITNpaF7byg4Lgy6z6tJC+cZP/Ovj7xQZOuoNOX1WRQu0b8tJkvfKhc5WiBsVbvwzt XPn9WL+zGj124SpDafXMcWZw8icTryRquWnCSvoBV6ioq35GWXMUSP32ov6l7oyobUnL8RDAEEF2 lUhLzDQtDFtp6rLvZO0O+1VJgVO0vODAyEJvgK2jjm0vrPXYMIWNCdrZ/kXWLp/4pOunVaYxqT6t kWy1hmG3GQXVa3os+einWERK2G6vq645Q6jUhrmQiBno2Vtu+Gt73hF1zE73iv3POng3/Ob5/6Wr jjzpcQAelmOBoJ4N3AA1HSxzoS3HvNPJGIH4UxRB8YMDQQTCf5BGGe2duL5zMSyHVHjvoHrutxOJ 8CGGMuEEC4g7T/c4Pa/4jIDamVr067+zmWXpIJ56cStDPgPttdJHR3pMO2dtj+7aMebILCVRvqkD qUWC83D3RMGTNKOXVlqykJr/mA3qOZmpi5u8uoWPdrnblJvW/Q1HfOzhCdQVK22x62IZZewR2pWL WZDc3RZ0UMKzv6PbhzEjo50/3YPlKQQztjRfHlo+XTUC5pcKIIuRFR8QRDFHvKzq/PPOoZ+T99IR T2swJnxKSw6nfx+79vo4utDijJn9W/7eRvdErfiGZIoEld7oD4z/ESvkPgzP75qykRg+KgHKHUtK Yis8RH0tqkWGuseluH62QDlLAfzfm/cZ8MQthQleh4HG85+krZ4KZmmpznqOuGw4i1AxFBtfPu9g rANAKaAsiq69cnu3byVAkJz2cd2EbQO7pDQt9OQRf2eKMnAS8JRt/Feq09xYzNhR5qZaLvMLNiFd QJ5hckhR7DRbP0TjzdRRJ1ls2gM5uQAqrq6s0ojpl1G5l3VChguHcjG+3j5bm2x2/k8rHfDBpKVK v774QxA11m8SEzooRfQdvJWlDgMeQ7x22sF9SmjxWTXwhBuc0WXa4wTDzRxZzgTIs5wupYDtKXqr 1DUFaCWE4rQq3MA2zuWw9HYWhcYOr/kg/vGZLm1ookmLnPwkstcVqHjnIz7nKtBrSLPsLrMynvH1 9Ue+dz+XHltfV+XmHPpfH1Cw89eXRnd4QU9Ijvkr/JofHlGSMbuLVrAj8GfNFs/bdQ1eW/b0OUnO EqoXtoaqcSSlLRpY6xCnd/+1CNfkr850r6hmm+EaSbRwyxtd9UWQLwj1fs/JnP5QDNKGyiToE0+R 5+gaXeHqq2e/hLfpNJverzx4XTcG0OS72j3w04HrDuArQz9O6KBiJmX8oIkBRfgAGzqyKBwI9YRH F+L/xUGD1jsJo/skt6NhzyR045ajHvAFRkUKOGQs4kYgzV81wxeq2zuWTguMbu7/XxRUil3ikTXs zpHNCyytg/IOZd8Jalt5CmJKgt224Ovxn1RR2fMZYzRYEusqymYmGf7s497WD9b63vFvhJtMEtgN 6Nvsw7Ui2lggJVSTb2N2AKVzb66iCjCKrGOoARw8ehv9yvMsKgRvtsu73mUvy7KS9SJbdbfTG6+E KsKll2aMt7CDDQCF1+9SRu6gLcH+jB3hKRbRoOocxTICUilp1OBZbeO8H41i7yUUTUvxmFlXgP99 TaGrfNDe+N4XnDULG+DGc3/bSr94ZoUM8mp+JphEYMf+29Z28Jo1Z00IquTCC4pLDmpc/rOj6v/t Bondq9Fzp8s1KAZ7f2HPF70mi5bDix+yeKQnUxhJTRKHhJyA9bHeBTcHMAU2C0WPgcmapehXkF7E SmBGufpnIxl3Gm32nBRgiykfyO92fXkwihyQmc8Clg4UdVo7RhwoKNYS7exMAvc5r5OWObkWUO5i 3F4GhKS4W20FpUk/Pdm7fpMOpNI+m95wAQs0yv1DnN8ZKTm4GMZEql+e/8EIQVLAONBin69f0Xpz WupXa18iDdQZggJezp3aurIEuiGb9IVtOSLtaX7muQnYADVM92pC3YogYf39JAPQcU700tRHkrC1 TXbDuTl60eUY4CN3FsAy3I81g594zMfMRx0RATAQhzFHUr2cBRQzRSzIzfcDrhtdb2EAUZHuX876 kSYWhtDK2pq9fuI2w0HR1xcPEKgSCd/ibIhzIfMpkzngAQYj4L4kTikLbkWYyJw1oye2DAlNuDUN 6SR9+UhhLAXzc7bflXDJmejJ3ulFnmHxUcJqapIiafBTPKpBVdlzJSEdEZckY2Swyg4u4y6Ge5OX kdTRI6yhWa78DDpQ6qebYnxQLRiPnhTFkmBdYRHd1xnWDvHcnZ8THYGKLld1mImQD3Z8dK1hyH0w +q8v97XzNOzPGgfXYNEQ2Y3W6UL7DgsQXPEppkUI5oKXI8VmkSsM+tJxxfTIBCYo7FXkEtUXd8jg zHWFNOCJDRoiLLi77dttf+jZHfzd9i8cqIPdLCvSfzpBqItkF3hc+Ngkqya/VfZ507iGOtuRNNef /3bMycvHx1SqW84yi0Guub/Srk77WTfjEzM8Dgb3Y6yDng49p1MfJR/1Se9WLW/cxSAXyE7JH5iD iqGBYGmr+0vcxwdx+rL+XEwQVe2neOw9sDfOH7kKrLbKRM59lzSCEOZKNKx3CHgGBAVLxtDuaO2h YoZNc/QPtmFWrzIFQ5kLMzFMctbYy6XMeUHEiqXDKLxbhJllOwgV1u3fUiNUAFSjoh4WBtYvIHH1 l4He62fDJUK61/Ptce8Ks9LoD3oTNSIUPpZXSwFKOdc4nnR1JLql/X/sET6QrgRmCbNyqARkAIOa wUjGd+Tp4XuKbXnCKpQzU2j3gJI003uolmCdzZYHuIQL0ZNBRVjY1Oay8lV8EndUM8QLrdQ7yC4t AOyYzeGh61LFI/JZ5762JFI4r3kZJviIf86BBKbExAR6I0xlI/Lt3+gyk3v0jMrH2q2DYnqQFkvp eRo4FfuVDiyOug4y5d2FYmCy1z7x+BHQwM5XaNl070dPKlFibFDkmg+/mm28mTjr375hCTnXXIL5 rvCIBYGlG7V1xPQgdlJnrOLDAvTrXcLvlGlE9cwil3qs++VQ0P6d2UTc7BSiLe7Df8ZQ9POxZxPH /d+hwsqsOxKWnZL5XHA+pOpMKR7ZDL89X20qhXfv6khaXHoFgXSswSOSWIysF56gkSU2pw9D8iym AgkPTx2ChqhPx/uWQyBdAVEy8ecAXWxBefhM62Toozse1yFmRsp+9DbD/jeGyU7c0cVNcP+oYv/y yQBP3lhkoBXpWXmVtcfroSZ4vH0yhtmveUBLoUpfMSHV2uJFZky2EZVN6TruAehwHa9s9Vu4WG8X GTlqLkVeRAnFA0XeZe4MJgyTqRCXYMIrE+pUCDu3/kWlH8wzfATC52Rc5tyjK+dNEiQIqP9SLdr/ 7kVmpFFxoyL99f8H0khu6yIgNWN9I6AskTOHqN/PR9oQUSVbu0qK4w2Z1m/3hoRGjJpsOD4jBWXh 8N59SKAfnXZRS87swR3+yt6IKF8wxDkfS1L3jaZ8DshUsG6ICo7bUcpcz7iHRj/90jlU+x6AjASv 199VPUJAhPM/Veog5hPl90KuH8K66LkT/9smqMcsBiYhz89DlvzjwYEWLfQ1Nrfm/GwZB4gbsu0V iq2NuBAo60196RNWuC6WTpto5n3Trhs3xI5VirLKH4KKATB8jvEPVwDHAJ2y16/1tX8zOZUDANqm zshFoswJOCfOdvZc1qFZUy4lfS7/FUcHy9obyGy4A97XE3YzO6jA12U730PpjQ5RUiHpBRyXkI30 LH96Loe0oSm5UdsAn/4h7Rm3KUsu61q+9zL+WFXeDSQvzVHkUGQrIEEm35asUq2WVwTD95FfdXBi kk55KLH+Puim3ZjGEIGxyVK9G/NPnEbXyEiKZ9K3s1gMPaoKxdXIkzEKoTdsXPPv7A6hXiBWBvWh QL1leHet7wMg9599plbN4rDW2Bis2a+zWE2Nqcxmf80Ny8MBvcD83NYGwh1NlEsmwpvIqW2O395t FupphO+2XNRkwYN81TvDswcVY2qI+eRzZSF9piJr4PGcBVtNq+1ZLzJM8FmcL67P6ccmsOZ6rlf9 gYCrMg+nR7pzla4ZTLbLpRRIPNW6vAF2Zwo9RLoDPRgIdNggTEcC7nIH6feTkyLeuRsxDfmG9rJm 0shK9j/J7ReGQfAnfs4zSQrYidkRItrNlN+aJtienya1L/BogrsFOG5p9CY1rqWyYG4ex8WMZBt2 l3DZS6JtSw5hlOkjnT6q2YwNLWj+c9UYM+lyHZ+MSgw+qD0m62yQuzzm6Ek7GejcR3lHphx18ai/ LbxFL+oVdLpkCOeg7BPxU4RE9hwbZDf0w3RfqzdEuGBgjwfnKvZkdV9mF40IN7OrciO2PWYzhBKD GFX26cgdZzz61plz0wtlCjP1YLIv0O7GQ0eTfzZoRudMMJTmsUtgB630Ijr1C7oPO6Isl0+iHxSd qPlYuMJinuQ60dv9WJvk6DNrF7pSWfhxg7awKyVLIcgRMKhPYcnXGWOtbqtmcIS7YrZf4bZVzl/c uXyk/pSg4R0QvKF9ILwv3GBMV1ntGbBd4xvPk2On7Z4HdlUQX1Bat4dpxgbH0vlz3LN/T5mBLiNv uhTm4nl0AYLjM3/F1H+mLsSdxFrzhlCgMcmVmMGScu+GYrDyU0rGrUXrV813X0sRy4woJ46HbEnG OgDpiFoJkXotzPtWttnv2GqgPMaG7GrjQ3W3XmKd2v5jCJAk8KUM5n9Xn7K0hRUp0+N7fLYkAhvz 8vcaCTu98ChebKM95kotbwNKjSgX0YsYI4DiGdEJMBsYZEWjcdkK/i7ywZLdW/+J/z2UidXVVPWs aI/t/uQngwQfAJGfI0bf3hrithq3FPavzw0+nyDRtVP+d9RBHMiK9qZsNgnTdkwEkAJ2X1TQ/H5O 2U2Y4AFtutm61xHuN5Y8JJRgxf6msQ+KpSE7UupZlyWUaY3dzoXkJLRwdXbBOGvOCzDj5vfGUL/h IGN3lPPxLmuEDf2RRhspcQad3i+ISVSzOZ1kzZmMY0Eq/r4eEFJHdfZtcUOP6zpn/oSfatWVsHHD MdUiYrn/4vnuGJ2EdYhiRny7aFApCtQEBYip+/JDAgduNhtFhtKfCQ0CV0dh0Kex3rT+gzCeUSRr HO6UaZnfd5PkhlMDNQ0o7JtEd6EaboYSv3yCK9gvdqvmptQBMdMU8NMRgvKSaqB29PS9vu8Cj3M4 mCp++M0Tg2/CZLFHkcdMYyuKAwq2Qn0zWnGAD9bV+CdV9pCJvBu4SfsafPmaTLbUB/CnOHYb2E4C zk6I7/y+qytRjybfOeV582D9G9w1B8D1xYK23JphJ1+B5U7dGdP3E8A1pydDqyQnUQkhbtE/cb47 EfdHFU9Yp89QYkV4imkVukSdFNFTf2ds5hVlfDGIS57S4YfOWxe7+Ma7HyHvcHhfJKBrE3BxqZIG XYQfBNHZaYCGQwZbOpr72sQXNXgVcKDCA6zgbn24SWbHT81sV0yuNITDIohpzFkUFIGqVHpFpfBG wrGAzD1PUkV7zk7tdJuUyCl5iF3UqAPphO0Py7fOQRdQgDZNHNvFEPLBV6102BN/CovQ2+2cgrUn 22U7Qp834B6t0YNizPyCIqkhQpNUj4IlcmhrK2ATWilyFY/x1vdgP9JI2kIOsmZbwoGkX27ZIYxX HoDhlEYgdNYqNjSKBiVgJMHrolzHsZsKgFI8/hRS8fAsLdNAoTHu1YLyjOhqNbBY/xrkn+tPX4yv eM4hWzbm5UCA56vcy1CCsrC0IK5+vDBAY5s0RXM5k3kxKyrjLz1QJ5jzYZTKfoHCWQRj0F1dDwR0 W2QvAtt64kNgpyGR7NtHwb5Kac1JYzvOKkle+HJsTaTDxD/jIMEmZxIm9PRZbv5UN8hlSLZqQQkW i4ul07lkDpB1jlvM5rm4roTMqedfAZKeh2cmqFx9ZoXKiF3RPAGxOu++Ogf7o9fmoweA1sNRnG2R dcRPtskkiPD+OUlgZoMfUHINz5dWHihamAW77ZzdNfIvdnapsowA/A7KGdfnes8YWDMNo0SMeu6f DzkEgJtpi12iW8/0CyUnyeGeDCt3uetKLTcPox9e1+A9ty9moqzf9pLXjMkM2NzxqbNvAVYPv+hw dQEh6wzLpgypSNx1cKH1onOg5JJC1aQTaWuy1KRYjn6lhU+VPT7J+2fIeYTqFr4W3cxLxh+q7+rx p/DIdp+kMKaPRFN5P6tYmqT+8W38K0KbnhzCqH1mhzeeqTFj4WvTAsF291J91J6sP9+Hq3fmFj17 w0duEFbOaTUmypF84grFtNWoZtdZUAYNJLtOcz0Ar/adWFMVzYWbs7DvCT5z4ryi4qXmzCaw1yuI d4fMe87iOu8ZNn/tusmc6bEzMMBG1W8+hY2yZ9bxoIrgq/AdBuqBl6epIu7K5KQcBJQSIzJ5zOti AhikK3vN3gIqgDxAWz2AGlCg+4Qj8YkjnTJbBo+N5a4DF/9OYmSDMNVf/GfGMuGDbesvHIR+KILN 3/LiY69DHR/IetCcl6qsLtoSyZe87Ydl6tngqROGBqCDJbMdpvGjywF43B5WZoFRlYIYxe49b2zQ uHX7k9RapA2zvwmMbI+WA1kbHQA7sKtoVdBnHAME5wrtiBxeeO1xi/zgBw+W81d/2Z+jNpsO908z 3JpZvcb9dg1uzvAqK11iEhHhak8R+RLuv46D96lExJIdUm2qaILHOhAXXWhKwtSRE3jmo6Xsnx6z T4CSt98CnOaPUNYr3TMXJVSqWmlZl9pGTsfYYA8tJYIXgG++fXXwLtf43ga36zYXrkv+uKZV4p+t r/idlXKf5kKzr2bLgWjPKdnLF/5cHrTP3Mjfs2ybSPgDxUYzmuflf7wKVhgAp8ZfqX+GqrAYFfTM nE/zsUc/FO4M/Q+Epzfnv3RGpgeWvIrD5evyR2g47pavgltxgMLhR+tshuJWT5bzT6U1hnBtVZlt iqOyuojoqWZ35tAbUouWFB1f0bnr8tfZjejcppqZW03LsAnNRm8+P64rHXLJsUnqyTEsBHb8OZDe fUdofMoOWCoQBzzflCxC5+MInnqLg7UgHrXdvZt3bOjHeZRuWyCRGyBp7nms5Y7FCqnTh7Jt2sew Zoyx8fEplTyaOcKz5p4lsXNCup4DbwNrUuXk+IZkCVQwaRSRwHodcAacls79w1+z8xdKyEnPvr3f b+xmd0Vskay7jzzA96//V9KvH7BnHK9+oCAfVGZK00jE+t4NyDkLoqvPsSzsx099/f1ZoQq87FNq 540VK11uhkr8MzY9vDvl81+QuEJ4x5BibYRduqbYsvwBQ5Hx4FVEZLJJTIBoJL/qEiqjAGVLbo51 ZOoxdqmu6u06Oy34QPT8Uz1V8qafWgd93haqQBx1osMtElB4A4SK9AxWvPdMuYvgJfuGGgAMaM2U v/TnNjgqXjE7VYo3CCIIOLvQixKcImBWmDvP6Rr5778GRRuaollmkT6dj6EMpvCAaUI9Idcw3gRx vFC1QJFvFUqRzeYjid0qmNcTW/eiRH8g6htZwUyWnHSTAbpDfv2a3KNwsoPEnC72UuORE8U1laYG eBV42hLdSFPHMZwCOzmdmadrm5bz06LLFbDr96upoQnveQtw0MKvwDizgEj5bmH1YQHsskjxhR8A w3vHD1F9fkO4R9xHbGflRViM90b75Xes0osQz53n8jh95XXQJljK2DB7HALt9SMM87uLxN2ZNsFB qPKI9abKnFTEltkxvQCvaaf5j25mSOhtm8bqkES+DvcDwj4yLYp0o6nkTcFAdzOdolaFMDnpqYy/ /Xez98rGay+QkP9UZTEkJKRaHIhkCTOODqq3KnUE0CgYX/dBq6dm1zX6eVMwGVnwRPETxcY556ge WlLGiGSR3LigIcOTubsw9ZFNaKly+W+4In7ej/AjBLhNbVKe0knVT77R6cn81YK9KU5hWMW7SV2w MjDf+86P2nLQmg/EPOhBXuLlOI1dt9GiE+Y9e9W2jB/9jhX7nT2UfUZPHnXNpxsOLMy5U6FXBQsi BtnEAe1tjenKoux2eoBAuSfprCaJ9UtJwgktjgpZRSyYk560QtRGuVzMUYtOc5513LwkcMefXmsL xymOB4dqyjMZRgaW8IBmWwKX1JmVMG3+aVuYcEegf3IxcabfgpkDfGbngoNwns+GZgIvcXszsmNj dnnReOU9nwx9Vlbsa0sj9YgwFnGtgP9Zt6CB1UoEU5DIhITiJFjxz4ZIxI4RH3MRr11VhguiPxZb L1mW/p5jC+hKNyknbqMEdLzRmvwe12pGBgg3//ywfGOwnMA24laCD9sZB4iCySaueqbueySYuhOs aKdnhVEK1Vit9akPcH8qIsW88fdZAHDKoUCHYEbJdHCjKEGkpnoS7Kh1ESqHtp1YCj8xbi6KHlAr 4m5xqJHBrK6vcmwVUICEw1SUnCX5ZAPRNJ8q4BuWxuuNhNi3LFF1q0lRQpStC6pyY0W197+szrqJ /t/XqdUGEIX0xbpK3qFaeUlRx4i4bdd9ZqEwyvkMqFlgsNrRT/7kBii/eaenxKHAS074lyPdCziu 5LAST0kG4ViQgpMRnljeupfmH7ve8+5JLxelHW/AZ8LbGL/IkCAOL6xwCIwzOhg/iJTYGbeLfdbE JJwWVSCbJOC1YHd585tKHFyg29gQ0f6sJi5ygBU0dhbkPW1APs1MqIuv/av34xJwwT/w6ugkZnwW BZGuIeMeFv6ku4oI6eyYwuSGz9vufeIk2iIfrjttDyrFs18OdhjH9yZiyk45WnoOB/zO4IgZhrC2 6kgR5vD+QqEpG9Q96dJdCJsy3B9SVt7k1VYI5+ckTuJjJJB+pORa9HydBepnlSt+2qqbeMO4krjt E7JtEev0st9vWHeLs9twKzv6DL8DZCOhuzCusW+FiDaWf54G6/X7hUiUJzQQFmnrymQ0Cl5wp7W8 Fr9/pnWkmVbXjKa2bqr1ve314DmnwTNdWmAPSH5H+tDkhy759mnsMU0RkKKkEbp6E6XuIXTFSEVD SYKdbesQc1iDyd+togZj0AFdS50WORjESmNFrvuVvAlMCvqL6xNPbKmrVaRHb3+0S0H5aNypFeVs WyUx5rDrXi/u09XXAQClivUEBq6pmiaAv3Np6Ioo8c14wZYVvdP69sZsWN1IPX6YlohhQAoThroZ UvazUfSDJWa0ru6i0sl6Ip6N0I8JqUdXJbhvOBSveActz6TdothnzHKDBP4rL0Rkb1x4Gx3zDGdJ jQ6nkWa/QR/cjMI7Bda1e/Qeeg+EDAN8NYdIXV6JaBgnuWPVvcNkdGD56Pum9ZJhn6dkLHPfju7C QcH0O+hn17vxWMxxPdSX2h6sd5S/sw49EGk0ARb6E2jGmMFhnapp3SsqFgynMvUR/+3i0uan1nxg XPHiMT9WYPTd9mUvjtEZd/VQP+uHriUZZpJ0tP0oKFfwCCK+9l60R3oD+AIJo2w6fh9W2YOSSbfF Tgb2satI7tFTINRNgjNKtIHIhrPrBnrQRGB186PJIg/MlIoIMCaThXDJCM8UK+G5H0FSzI0r+RYE mf7+w/El32u+IkrSN2TUFEWu115XHqTk81+s3POqoF1kYRjVpsNKgSJT4AaqqO8Le1euXbmqOsdJ u63R8rjXzUbYIiJEl5du5nWYpn+Vr/IjA55qcITdY5stPPDgwXCYhxESxlT53lXljcg7mr/m+Gjx ZLhLRYOs6mOtBr2UASS1bar121NDjKGYX88jSvM2FoFqHI7q2NdEZKee8mi+ePsa7f2iaIX9g3+V 9UIJRiW3kBF+A+H7QWeZBgDsxp4MDXGFQIl7j13lP8Anijjz/14PEWzY+1VlJxzavBenczA9DNYP 9X/bFMpbSBzWifeJzuM8q12GyvNNKiqDwjxeb7GP8dlm034IpAVzNtN1qg+tFu1lx6S053Ue4CTq 7aSBWuPk3X3Rzo2Mq39wWwYlhGIYIKqO774NE/MHI2czu152bpc4RehI+U4OGL/IXEiY3YdWRtNe FJ6efjJDLZ0Q657RgdLMsYeHBd6gHLQQoMiFwxW0vsSRzl8VlDYxrHZqcSXkrQGiv6ZmSBVYHnsJ LaHh+ogP/op4mohlqWiDY5T3NKM6DducIG3EzRli0N/QI4G6p4Cgej8kZrrFlfVlOPGaby4V3Ihn 3HayuI9JKDLJ0d74NKGzjaHLso9oYybQ9nyz/4D2pTqHO36p8JwqUe3saVCDgdOOtmLRDs2yPDeF 0rdJ1vebhzw4gLzo6BKQl5YAPfSt2p6XFO0l4JcR/dDgsrw1CZdQ4BpIZu5N/MO3f9clsKifOz3w riVGwLomnhokCsqqeOOKt7jBYsB+SLT2IpNl1O2PS1ui68O0OsyGkVXmQV64lasqpsln7OEqXTIg VzDwLrm+hPFGV96pLSLrcLqMXTuSE8B6S4js+Cpv8siAIaCApvEiMHpVQ/lUQym/2SiXJ2kojAuz HqI8YlsmigrUYkIKCC9ZhhPyUGsjDn2T821Cgq+1t82k+qhq4PFrTmNK7ymwDl6TMOI+vb9NxfbZ GfN+hLM5eJ2zE6uXOUdR/FFzlPfhDWa/6oqL56ReqUWsxUCNNF+QDu8VByxXSxOZh3WuXraEnLCm 3g7XD7DRFFcvmwTXjCx4M6NVuuFLnYC4G3r37OjBUwl2kMh+BD/rU1cJj2DUtY/Pv9Jp21e17Tg6 ELFa6G+QOE99iBPCFbdfc5cVk+qg+ytWn5LHOpWZ4AC/O9xzauPqBW18SGUl4dFv0CBIP4xouZCg iiIVZZ2SvUQVQkNpEIZn4hGuqZEW9z5NUln6vmx2dPuOU84AQwcvFGbfmhGWW52XfKm2lwKCyz/J z9R35WSuUp37iqoEXkWi2hCT0BLcLXJAseUHiw6uscHF9XocEmjF280zByHzF7gd0dgOCWelvcGK oAsWAKwD0628E0ckYq2KzBV/wIBsLQJ3m4CiwD/WBcBU4GVM6/4jIa4IPE6Hq+7/BErbqdIlXc32 iQHo0MGlh/znAdKcQcyL97OH04mcv+gtkc+4vjesJ20K0pZGikTaxA9hqWMvM7poxYxxXWRy8aDZ qpEhGR6MFdaaPgh9F9fcNaCTyVd8MtTY8b3E6xFzUBVW1MiliQbrZaRDB09Ijzn8EWzWZ3s0od6M G7qXMskkhqXqVk/J1fU4Cp6QGtu4PNbHGOQCT333YL83pDY9UUcZZEz+8dOiKx9Y6mCgzOi3/x0s oxF2abai2yE4xZAMiN+lH8DV21CfwhpL/mCXu73mEIs+e/t52ena+ms6lPNYXt6HkgBas1udh+7j KDIf+jBUZOM0pTJmq2kx1BA6bUwlcLbdck5iyztc19Yr+An58z+fvaHwsA99X8RLT4KkRIJnkDlQ XeAGOAX5aP+HLG34DnCmJQ6gF2pitBh8Mhgpadh61T0j5sv1rgnnueXWCwkjKdFYzbu/1OC4D9CI SB8Oauq6+Ll3MPa0GPEAwLm/VvXD4KjURh6+/gcgYVv38qaRi4wDw3U7oEWz8TP6sI8GeJpmtIbW xcQhu47pFGiDMx5kJ71JJ4lk90WN4rxb5WdiuztVKnscSyzI0YKDxm1N8sbQ/3B4oxGFfDME3Qkc otaXnZuYahX66bXjO6ha4vlRMMjggnSz7KNGpsykgM3+sMQ6YpnLuJ+Q7Lks4b+w3yUFYNmcFF9H PWBR4xNDI0RNpUw2QJ4epfqz2flXdo+jH+NeZDby+qkmm7vs4BmCKxGLAwj8ssdUz6m/ZEmX9kKW Fwb61w3gsFLTfhcYg2gkXY2IC8b32oGMUeqFVvRYc88HOI2ResJhwHP7J7LvAWg/AcG+CBdDD45z 5wVAFb14G5gp3MO2PbLOX/LouItyYw6gGIpCKM9xHIlZl45mxdzqFXrY8qU3TWOcHuwS5v6VsbjM Jxxg6/WfO8ZDo3ukWltfRoDER4zp6+gQUKUWWGaMnn5E9KQvxiTwRAJyyoBs76T3tdb4HbkLV2kI Z+Xr7nOOErbzguO6+qW0Bg2dlg++Bg62V5pFox2Wrj+uwiBjbCm9y0BeTDAe/PjqnDGqsP7t8X4T m+JsN2xAcjQ1rKORqp5tjBWv0MG4yId3uQTqH5tSMJXsny2DN28hpW3krUwvOsAfObZD6qCOL3uh 5mqF9l+l5XrXwvjmHfSUjtAuwoyVFzV6rUIa/GpyVjbqVmhD37CQ9S8+lv3PILJmKrDVGrHfQsUp TFcFXUgf9a3EAPUitfb4fQNwIi9jG7k6Te2unOcbe57xzI7bF6mf7EDNbSRetru1hThxmfqdDvEt 7CFVsCrQq1gr1F/t8XKLjz7lfp9uzz3aKNl360DKxGGp5+X0Uq1xk0zaEb2hlcb6C9dfs2Z8ppsF mPLJ1Fg6uhLSmlbuapEOPryYRn4nFFJIS6Wy0m438nIUSmBbRSXXNk0bZdlTPNE6Zrlu65QxVj5k jd7J2VbB2rLHbNtO2k9lg9EvHYMBQuxGiePEWdsRjNFxq4nXjEFhLdd5f3l8MFYSDcHn/FXqFpSk cetJQD1zpHz9Lv5QIP+zgDpdOxD2BB/rbgYFt/PLSxzKLNlDyBNtAznSMCDTfYz5fRCYTimyRO7x h3evUH4lo9csK6jFQoSPXFYkZxwcEpjHJaItmqL7WjPSoQIcnfVmNk0pt585KIi49qNlefQOYuLy uDf2oqSiwLZEm9zq3de2vfPwXdomuJbkUtzDSGE43OaCNVhb3iUnnMeYzEayNWW4KA+WrNkfaivr uto+HNbZd80c2e6r5thVPjUGEXpWZ0xLUmcZfri48ocH9YtoQNhCCZSAjtEIVLLYJzj8k9VDZE23 jo78ABx89aK3ivYy9/QuobXv2kfThMuPeMlao0bBncbKLRSCOv61rsM27J4Ig/W5s4eBndPSy3jX fr50XYMFf8TAoZO/cjFKgHHfxj3PoSI03r4U1MGtUQHAuoPXzMrl5DpAkcUNQ4BDOZx0XDA7MKx2 wq/fVyaUq8Hw4jlAqGYoX2pii84A/fDJGN0+kWYK4OnD8vLcvXzDGOnMWtilV/rZJ5sGZdkD+B6g WA7NSLPBxm0v+8ZcwJZHSmP5TQTRBdE94/owEAMmYHePU3gzsNwvJjfY1IAArn9OXeppM1Avyr/Z /YdBnqbeKdHnj0xfMWoAH7ju0H1eOuF1tvi7/hXcfL97JIUP04VioDxbp1+qPWm4cuGFJo99hfju HkK49fpq4UCIyZJNrb2GD1sUk6Izoq3bEwgWiKAHmVXJQwNv2V+NFdptaqzgWZPWdheqrNlqe1wB so+6NPlhDf0UTETR9ayfmeKcVHDzbsT0E/UIFArW4V132rdBiZp78wA1mnhjAoQddWZkjkgW0+uL vUEwBV1I24IAR2eBi4/FMkvzJB9DhY4DwaONEN5gEw4M654d0yYaV7sQSG7O9v1/DVWDpSanBegF oTT7Yg7bUBg+o74skr0DYMUT42EKAkiN/8Wnf8RB/bOR+BHKQV/pX62JUthX8/qfuCRbb/gzpX85 0YPAr9sSsBYu+6ZShglFl60zFLb+bVKs6PR++Kt6Zxu74meUrTHe33vZxXMX2rNzZj97xabwoK/n HEcY8NhnOv8R2zWAgfIvZzAB2ciKKhBnOx1D8CbRdAPtXCYlvZrcNkqBxcn1tkNdFA1DKia9Qpey Mf8FQ0TvXTquIRZXZY7TNJpRRLLA5B6vVAbiUMtMsRw6H49/Hhmlcw1izOxKTe4rqTrEbXG4j7OX mA85gOSub9iWoNXYGLA94Bhfv82B/tHkpPtB2ltTf/pENDb+9z3h/lcF15ZVghmQBegowz2K1HGE faGElXd2CyZ/IRk3n6q6U230D2LvhJsMgI1uZS4LW1Za+krmL1bvWD8hHj9bPMIqrlUlK2DFbbOA 0RRDRUF77y7kuz5EPkgDhzGX8hXTZUiDR/e7coHp6q0RAEu+pdaLajySg3Dk6/Hv2hlNFsb8O+Pp MoufpGo4SN4TGk1oafAW12EAZkWmOp0+phIGuinfDL2ILnO7rZpkSjC2KJCSkW6xdsiwI8TnYDXj SZClmWORJd6wr55LlqiePahmRDFN9JhxCgCtFxdCe8MSOB9CkNU+FT28asdhOGpEcduLCfhniyOj QNsqhSJHYzomjCd9jsKuVIZuyn+uKw0pVcukW6OLiSULuKDKgCoHfJByrucEl1GLF8iUGedEqj2B ERP7c8/vtBgkaNJ+O8roiAuRV2eLMNjGEJhC6/Br24RWwk+AIJ9z/92umMk7WY9lx9CE0vkiHdBk cqiPyA3Wy5QR8Qx39Xxg0YnPEfMGV/L3+W4c2LDf9ZibGnIUILbbhJYK2z3oDcssU3O6/FGLwOQR QiwEzf/RdPsDZ3NFMk+FFMdZI0F+0C3V1W6ay+FOqIsXCDml1etPYH8UKHfdZYP50QaqxIDHmq1Y qzReZHPFRkI4APQRjGP8k1VxBB5VQdsX09yIX4SiX2412cZ2TH1wVvJFyhOicc9bgoPD4P/Ch2WD KTjb/AvfF+0jEQZMv8oiZWjQ5lDcmEfHqS1bp3/RSoponFOHr4wbqZ/w4Av5Iq3stUADybNNPmei ZNYlFIfG/1ka2nwP0u7AxUWtqWMzsbDR0Z538/vR8vuXlv812G/olVT1GEkazHonqAMKoex4SS3Q ha6CJOAg83PgEDiyu6YWa1DKq3g54cnacENe41hEIwo5jZSAr5NFEhojkbvPpkAukBbjqLujfMT9 ROjUARIqRlJ95zbjg0AQIcCqY/tQ/6q4npQVpGBEc4Hb56MnBUcW5A7PAtjCJnE1nDGMKKiuataL xoqFR2ISK6Pk1qcTLgzPdv5H0bpmgr/0jPJLs0hqlq15USeAuUdENTwgHkdttb6I/qNrEJriCWra wupwsMfVbQnmA0PFP31yKu/WJJrrskmuwC1nuUU8AWLatkVt1vSR4AxDJEUm3sh6f9foDwBuqMTz a/+vQS7RJqGKY2z8VaWnZiqg3yyu2u620+JQLaoUqow4RBvhccZ5frGeDkXIo4eWHPVPDwv2f4qb 9LjpoI3I0aiCeSohO7WTLmYXA8VDdKYH7cYqn/tj2B77eupblel6MPZAqVmzin6+XSlBBSj23UjJ PBhdVTyXSGu8O3ErxYx1ftaEU8sVnuyR1/DR//uH2C4/UUFrZ99T1aXqXYRS5sFFrFYrnyzQ90l4 TzxbJAQokQlieaQ/gcNbNh4ttZM2+MJ9LPNICsw+vHCzD8xWWhq6Uc2ga6BLlV/jCGqsojoK0zC8 tvUoKLprENkDUnFDuEq+zm2NbCD/GaoEiUbS6VO4W8Ln5MQQWQVLfAPw5Ow4v0YoY46oGZaoHLSb Dnz76KongzQQ/LKLrJwbooMLiLUmSOn/c20lAw2Le7xj8vsyIHn9Lp4rEGy9HGaXFAmpfniJrtdB LIhg6C119++tyUHdkWKUKJ8T2m1OMWnUaFHGl+kJYPey9njjmGK0gsluFyupSmbC71wrvLNu9diX BNJUHTWCSuOYvFy35bHsGoEuXMGKlDolmKks2i9Nzs4FroqMHX8hT/xxXysP4Y5lo+Sm32lpM9db ybGKsHJZ2ccUPdE3Qy4dbtPz3cyagKEKimIMnzyc5uruAgskKNlRNmG6d7Zxb+/5QTvoGvvF8yV7 haTpLnFo5PxQbX9kzdXWm41C7brXkeCW2fBeyqIiBJoRzDodwq37kbLA5Xye0kZ8E+8uxyzloljW rapqcDXbFZ1meTifSCfS0CUkm2Nk5eztmLrdPqG5vWSUPddYBPRzwEEJ4/UffvXND/qdGZGBsmcz 4X5tFhEt12iQybVbn5LKNk7v38cK1TkOL3TfVoBxo0UrYa1czlR5q0/jCVmISN33wzAfbdsbLICr JEih8J/2qPcEovo/hN0AFA88ufAcG1/uDIPnnzCX9r4COaq/zVjnRPRVuMyAxgR6VM9TAyQS77qy TJIloymvvuS02KUVnp5ykFHRpfaWijxNhdsDlbNvLVBrph3zGIPn9QKs9nSyj4E+Qn9y+wt4L3o6 ByDCQDvj4Tcpwh9mgOkwYARtYAHA34EDtpaRSy+ORFvlxKnDmSkq4LNMxV+p6QV0U5XXx9153a5a JPBaHY4IN8mATLCWGa4V+gpkCw+oYvbhIBxY/1+g6BnSUXvkhL3cVIG2/aIIHM364PjMDISG7ItJ D8NVgRIqvlTkBbfA5euSc1+JDTDibqXsI/JVFOdVPwGkBhjWAj/n4gBSqbHr3+pbunP0gW8rGdrN u/qfRS9bFl3A8HJKqitjCPptbLbZ0X00rb2rq0YAou3uDal858nyZg9WnArAAaWI3qHoYWwBRPfw txs8knX+aZtLAF+HLFIwkAGeZUsNwfl6ptZvnlqckaoBZX+nRqwBNu5g0dU/Kxur6b8gkzO556y/ ZVLCIbk/sy9uz5emOOTi7QOvWaluw275nH9n+SEpQKO+PRvflyjJnbENk4yKZzBFzBza32K3OAnb guRTMBv3rsP/p5SJ/1xadGySnhfjJRZxg661W/QtK8bJiVAcbZcu9Ca0Tzb9z6L31VNicf4WW5Y2 pE3SV0w/JrS7jszJXA5oHZF5+xKLA2sFXbiQ7v26CiKzvLbP/265H0zUS7tx23DEb3igVkStf6pg djLLnM9dBwFxAfwULEu9CWuTCm8NangBnR40v21UkvIYSN7BokPXBKpdSBIecCcikAOhr+Gnlb7k b57UbfZvlCQ5W6o5rkrOFcZluxWOJz0nebfGP2p1WpHVZsjUtpSIqZszj8VjdfUCRpOxf8pBjgUE 7JK2ceGQmjSRT4OsnIn3zSFtvoS4HwdAvQb6NHIGXVpZHOcs0nTNRHnBZt8ALaBYPelPZBdzAR/C 0NSpGG7wflGLMUvq1Uma8xch16w39JtHqw7a4ig3m6IQaZO9KWNn8H2h9uTehQyONpSLRF/K+vuc MtyCIb8pSNTDWLD9G6Hke4CmPm35GwRkaCqIbLfLCFS+BgSv7fYPEoiR3lnCm3+CCMsl1fN4TCT0 P3kkOZWgQr/9TzipmsXOKSAgjfGgEUWbh+blJVkoKkOaiq9inHSoZR8DPpp5Mhe+pNgJSaMMaj2e p5MilX3wiUFtTuMRy7jimGN0OIb+9ByLwjLmSS3g/dxMas314efV5tCTbKBiy5K6beGJ7YgZF0MV dBY4DI7b9UvzB7eXnoQBfRZwB+GPbBrrOXuTKR94F5d96BV93wzut7NXak9hC0HARxT/dmfgV0CT Q2FjDOwbjvA6i3rosQ3aO16tRtSvAgk5H/z7MZXx4KuhIscEdWDZEQ6FPPyJvShPBA2WRFOUDAMo OypomKmgwX+Oo9ClVAmMNm3zLDGnUFBVYQKrUKBO3M7NhU0/fkGqvL5yjyT6cTFxgctMTcUp+o31 SnUsgcuux1qWS8dLd15K1+wDtLu2xJigSJIWQVAoO73QyXm4WW0ShoENqQBKDmymTn0yII5Dkful 8M8HpsHb1pfkWOoVMLCPK0Ag1Asexw5cJ63Wkh2iwm4EJbLukXkSJOGalZ9sm6UeyD1IR9TjgHAO YCmr4hS0fPmNZ9pEiV7eU0C4UFzru0YIKUK8L7b4u7XHaMhqaa77jcZ7uVjd3WhzuKYzGP8e19QG wHl9dgoR3ha/mK1t9x+uXIZA9t8a/4+gxx/nDw8pxBD8/sT4S5kOGdMwdrU89r3sk6pJyfdqdkSy BaPuc0CWPasBpAKuXw6wUuFPchBz0ULy0sv4r3a2VM6KH0WG/fOyqJNxFuIJWC9hoRcT4UEhc+0b jKBON4AARtc9xiaUZrHKvetEnD0Wb4NPhYTVP57MhTj6E7wpysFC5waU4uS7Ch6Za2cPSt2yr8he FQall0QlqVVafL8z4hqO8s9x4qRpNAWu/X5126p8X9fT0dJtQK/KzXdQIPXY/5tJ9vbKoJAWuNtw eZ0lm+E4Nkt631eDqkabOmHKyhtzWDwE9HGTySeygQGKf87HWJq3DhKZVr8aWDNjyQUoZkM+82Sz z1Q/j/nmItVdyPJ3s3p6cE1yRkq7yJlt+CgLntOci+KUjLZvw2ta4oDOrWduS7ExcjHNI9LM6Cml 7bXseN7OXtUCV/2bxbXCOvzyqezTpB688zZR6RCt97b0SX/U0EW23NaCxCs9g/6Cp3DEQgw5yB/d H4OGLC2wXsre4+/TCapHwyARfoKXV8pbN5Hjfu680CgoCZd8UOOyzbnWMgjY3RfBOPFPK0Fhyat7 IanOxNTgGPH8CYghDtQekiV8EhzT4kzPtqq0hfpN0zU+pnsDhbduMu9MjOKtABq0xf5xOvaYsoYf ggt7sYzr6wHkPo4o9SxEkD7ebQiRGBG0HoDRAkz0UOkb3lxUUO6Mz9V0Bv7Y/LV6urVPHw8kcO1B SykzS0c/mThaQOEQV18E2JSupDdMmc5ZEw/ihnIOFdlEE3uqUhYkGR7kFWVGYmsZuPJp4CXg/31Q Upirk/UPqS7Q1vCZYMg/dFPaBw+UN9+Gl+00nMQ3jE8OFb4hAjE4/t68lP3l67hyTuSV5lG9vkVD fsN2TW+I/HQt+Bb/T/QZrLNeRtt1NAMaP9Wt/PgADQnLPB7pdnBV5eORVjrJE244S9HZHU1+kJ8H nRMpm97NTURGJZamk7iXvPNmOyaXuzh8ROwOdyLATT8QTYH205FSHPJeEPqAKDgHFKpW0hBFid4n RVtXgikCCuw0Bj2mSyTy2KW2cuTJZYdupTECO/F3/9LAitiu54tl4MUMo/FmPoAsjKM98I+FnHw8 si1XyVjwvMz+MgCvN3WPFEX9SwUk2XzyJgLy/vu10znEy9YFvF4XyHd/hTrnh3f0nOD3mjZXYTfh qztu8DNZs0dMmay4K7Grl/WZXk3u4c3pD4DEPO3mRuij0ilxynY748jqKTcump5YlNgvgrGsZ0+K eP+q80/aD/EoBwO/RSUG7TECsT1Y+gjasL4cM4+cEFt/5YMiycBh4kK6sg+4MrzNQYxAJ1ojFaMy snUhBCaDYesOJja/AMrJXEAq8COKDhiiUO2MPJ8qV2n+3fLTDp7KO43JCJP84DdxQc4YUwhJNNcX w9YcLzXUvtlpEQqdG3ch4oQffNKKxITfRIRI+f0+SPyPKAA98YeUYilmtdZAOiXzwp7fL13ZcBYj DJ/VLmQMq45+lIeFQgz66l1eMcheiQ5ElgmpiJLR9waa6F73LCPoOtqM/SJMLpGzYju6wP4aDQgZ AniEPVFx+XuAZJ9IBkctigkGxn9UeF6zuIIRLbqf2eAb7VvSpRP4mgfTJSPBEcome4EQnJCIEfzP Q4j9lnDa4YTkxWzMyDbAWlBgqccuAOwPlCOy9RnXPD/zCXZx6sxvxilJCYFF4/tA0Rqr3mrjpOsn rt9TqKZVl7xK65mtG7F2dDcdbzhmhieoasGErAsMU/MR47EuHeYldDiOeqMDgrf+OtEVNXyr6lUf l4phBic7DdFKvtxzQGj0n64hblQZ4zABhfntMCtaFGrtHc4lLd6wwWVFG8LCSeWMeYsduumzgdV0 WKO5tzyDN/EPpnteXvZKfz0010y5CaGsmR5cmW0zwos6ePp1BlQGAyeHao/iXxbn3ft7bTD9NExZ w3imrrc94sNxH1pYjTG73KbjslK6r5Zwm9Xms8GwC3P4kZ40Fr7sscxBDM1zQr/+8sNUzl67YjBG xF4MctJI0MdUdljIFo1+cgWdBDVgCXtasazhs5yc/J4uyOGJRwy2tWemo7s+/yaRpgNi0H7gd7i9 8fCBdrFaZqPapgYQYFUMmfIsNGTZkp2TxdyPP2X7jMuk0cPuq8Z95dkNrd+iXAMx6aPa8C/buvlW pnhgUBP4PGurwGR8w56Pk1VDgMu+fLTOR2Syvzwr9vVxkhUrAdwBi+TCQsWipU3UesptVNlRk4UV j0TbkJE3DV6AUBUMCOl1pZKIg0hiIOrbaNnnP6rhZqR7aI+Qv7iYTZ3cg8aZr4pVqdWNCB9ur0xW RocaYDDcwriUiHuk7Yp3/MFAZUjAgvfw4Re0rq4r3dFIoN182THFgOOTHHyayhT5hX3WZx3YcfI7 nlf1fuccfi/kiHD1bVibWQAU7P7KYx5bON8Nplkh9iD2Z8Ek15beuPVXztszVZH1xzf34FdhoJAy NjfChd8w6gRpXhDObhu6e+w55QBMFq1NYVE8hgV0jyG+4o++qGq+2TiHqtVghb/KGuAZF6xTOlQZ HjrQX8l+uqww3PMDdsittCM41AcKrBAlvNwsMzRnebn7ojrEMf2hNQkmgKO3F1J3x1wRfcRfhtgr L4J0oe2eBOCnEY6bhuRNIlgg88CbsHRfaDo/lixFM8OV91km9UxWXl6u6KTJYCz4rq/N9cf+t56Y aYzzdIJmD1FpgzSoZQcN5f+IBLJUnh0dWUfeWexYlccPjKkzKlOXuN0iQuEz0EMdBtY4dblapt0/ dehAhqSNg6rTml0yYVUGE/PjOve6EFyiGwl6F7XXDjOvHn0Mlln56prd0XRFkNsZaarIXXod88WK 7dNpfnrwiD9J75kSIaD5W8U+w1azT0cnZPcSIZTgTde+Zca10SKzNVieCUdNUxlikOyFV/9a2VAw fxaH3R0aj8uguXHD2ik9P6cIESWLEHAfyBoyAwmIznBHHvkqmcV5JWL/sdEYRAMIdkQAuvWc+/LO GSJZR6rpK/OX3AGRdBKvct5WUzkIIX0QEofgOmJB1eaqWrkNnU4L1R9AzcjR+PtMz3euNqY5Q1e0 gsLxEU++HDvXp3wxbTItj+Rygqs4OmNf3T0owwZH6gGLP7DOUE8TaX/UCcI8Suk/2hIDmd2r1JE6 lt4xkkxzJ35VyMPHXGIoSjym6naxPLb45FFZ5PHQeTTADWv9GjihmSwt35tvUtcvEIS0bgQ7/Eal ag9etAyjnrsyiP88Io4NXfI26C19xZj1JxduE1fxdakXU3yrGaiXL60ADxEyQuB53Nl+TDHXrvMH 8w8TvKwJTpQPvb7nF9mvUtVyVoi/ic3ZjiOURCGsB0yCqxVzvd+Y7ECjM08Otb041ilueWL685To ooyhhFIZxfwzxWb9pu2YyBsm4/SJ9oBn1N3Lvva8xlfu2qsoXW9QEZ2C7pyWT25sBshBdRpHLD9R g9DsLWmm+kUEJWsmGUucCIWd/pku7/H/iUpFHh6Qh6VuBKv2IPEOFkaOc4hOGIRbYl6t7t4B7RGw gAkgXoTti3iSSE7s0/viv8LhLarnJ++RCdVFrUrHLhSV8pK50FUVcFFcMGs6r9vIeNGzdqch+liI KlB2toBtpKPF7XjiRb/4Ij8BvE1DlbRc2i82nppGdt9b+wRYYIUsU3C8diHCGO9rj/+a8AAveNUl raNC9FYgf7pggvJSqCDZaXcN1Daf14T5dQokO6y/eMOqmSd3dT5EiyukbwoM53NkgsM4ahhzitTA 9PoIbhhEzS/v0WYlQ7xZYV2CbOF7Vrl+gO9VvhqV1M0jFfV7NOOtLzXcex3W/dRaEaMSwWJozDSF ZZpQoPaErS+0/zrusIE+Zif3hrM3kxSvKA78u60pP0v2cSdg6F2Az53tquvRO3ALGHNF0EKM811K 9xJoSPF6y1O5VnxbrRczb7Vfhts1BbU4kwF4yciy5/ZA2kvS4GCnvAD7PuR2FZAOIYHkfEbSuRH9 x90TcMMJsbtqgRde6AfyN88Propbkf/MG1EbCssc3mkrt4XIbxiJPhaPBaOkXzYCGDf9jv4DsSis 6En9qWo5ccRIj40MmIjQhxAGPhpmNd5KhPz+UiJiu/t6PXICsI5s+UIcxMZwDNSO7UWmY4/KY333 S0PunjwVNw2NfzD2gJ8Ni/NwUkevWVq2RjxUe9F3bt3oj61ggsoVk47ZPSJVMdCKBIFXh7T57wFU kZQ1XKnjDIa+jzX/EAfb+CJ+fE5B1BmlO5qgpNLq5fGJSTnmzJKZoRBGgphAAmzeqJp/swXYs81d WbKbHOJzFHn8RGh1zoH9S6MG5bRD1VNOC9eVPuL2VHBlF9acaylFHvC+hyQ190GT3XlgoLar9QDH cIJ81x805bZ8yYCkAXD7s0ZHiRqDgQ3Ugk2OhDwyGQH6ZwP858Zo7fl3BQ9z7kPpgxYNak5rwDBa Iio9/Ht9FSzJpFdJ7fs4ao3Wttn4xF98DpAyxjlhFf5F+vN6IrMvdoI1YZTh8l77J5l2IUOt36oF Gi0hXRj4ypWdw90P2nWwZ/JBn49PiFTacJMjk8M+N/A2ZaeEvRHrJUnmYMiz42TOrV5qsPGEP2cu uvlr42KOfLbCSLgPvtpNg8wc1MQZOOD7q0U+RsxxELGMSObXG6xKHEaeqJvYQmVNHDk94gHngSUs 41rXWQnp/Bcd1m3UIBDzNsrq8rG+9OD8Lvq0HFjCrY59lZL7yTD3wqxXraI+0wKuKzZtTU6mDL2H 5jt8uhJt6xtpziwHMj4e1HAlUFJsNfz/4OR5+Yv7uTfFOi0iwmeCLQA2p3xIAJu9uLcWbRLuZMFT Zwh4e6QNMQa6GUSGaZ/q8skM8VJp/xiszQhgLh8M7ixZRc0kLw0ElPMTvVJVk2gyULnS/CMztXMs CV6Y0UfQuhje/lSIdhtyrwpv6z9pUKfxBCDGJcRNAxNBSZPemBBCc7uyoE7IXDBP7aDmM+ZWHW3T EbwtqmAmUo9JSusXAfb9YO8OegYo3d2suuL+tiNhSoH9AtiC2Tj+FJ/vWdHw3NxzrRwIFeXoV/0V vMZOvMvtgzt3ofDhy0AXK+3MDcLbpZAqUcIRnJQ1wpF6EuuP0TDLM5bEwO2WRaPNjM0Qwq0xhoDu cMZdfli9Oy4froGztUs9vOAR+yFsiVf87iqOJ8G4bAES8IiOuh667FAr9LdUF22syPROqu4+kA5J Xm+nMj09rXmbjFAOtACMu3IBFPhdYHnaqL/YQ9uK/R5NgT9zP+9MGCd1wbgPozgP1ACb/I6I/4Kj tK0z+72s+zGTy/3H06rfmUnR9ygGUZNU41TG+so5wIXUsZ2wf90WaAKnLFEfAqZ4XMH+kWdbCyYQ Nm8svfXESeTfeCoo8puq0rROoHymjFb8Mk2/fI9W66teELPOKz/MCa1dRsxaX7jJAH1OvOdJvxpm ttxwHFiPdlxS6OuF2Y6bYkDCodm45N7qWq7ZIN2oU8a4m22mhIcJjF8qLZ9ukTuoiD//M7nbLAvb JwNfF5wkUACSHL6PjK4LGKgyETa30ZN+IFP8vpxcnZzsHMyjm5rvA8+sTbEN1FV0ZShVSBL1/kxQ ahAaj6VQZD+oVErhGV9AtgZJwW7ljF8sjAFs5g7eO8s4eJQZ5rtJG38I34Yk/+toAG/UeFR5fKsA btjo70K6sJi3ha7WEWbXjzjSHfUsCGHSvR2Js3DyyWRgwx0O0OE/D/7pLD+QqVSrIl0g5veU9nnz pDPjhcio9BAuzgx1SJMOALzkwtpKeB5laOtjcqE3gKBLXQKrgIxZREj6c/setGuIL1/6UBYrap4u Gu856ZgKleRuHaof+WTJLPxGOtN707EjE0ly0n1L3Re4HU4zc0J19/1Fba9QwDPFihuczU/MB6N8 buzX1FcpDjkd/0gyHaDC4+FtNS+gzu3wdSTWMLOpUR0fKGhAzwlwJbTzc1qsbfILL0IGC0V0U+Ys sFYQUACVoLcgmHsqIO5TDIU9qBeUu/aSpiRDdjfQ/4ZhYGh0u/J91MSGjPme6IfhXyH2cUkCJeSp tPda2718j4JHI/HZHOeTv3uJuIauPIhbTp1Ic42f8BoMsJZ9fwCcK46ySuHRzPHn3L5XNzQBOscZ cMXToGERY7apo7WhynxK9Q+7oZ3c+UQrMCya9dw6wTx/o5mXzJnk+82xtP5Ew9T2ZfLpbWiMQUWv y7fspPWkfQ/PcaihFVt2f9QdZnbLimvvOsz7cuUWaRJxjUvKY4Cs+YQOG1Xgm+nK4gJBb1BBvq2u b++JDb793guL2LQJBPD1XavWJA5Eg3RrcRNy+q5IacYAzLU6LE6scziK19UPJ85Hpn66w60AZYyX h05EutJqpzb7YmnMPXYv8vdzb79eGT448pnU0vGChdR+eTuHHcoD8GDMSLEtzP/3zdoOen8gs9v2 3GRnxq1hjbAWhnPyBWdM1FmR563rHjAQFKkht0WTiapgsEGCgr+BLGQgyjY2GJWcN3KICH0OhVYn PrdM7g4ndWwua0U5c0dyd6J5DUYvNcn1SE4K+bw1yW/hGrKKU6VZypeZc2ZEn1X3eHzR3mf535W6 waRE/JIFXgPFz+lrDy/q0R0/I5ckMSZyw6FOOn5gzVITOkGMg2cVjbnvPQuXNOpbedH0lkTDZXlA GEMzC1CfOYQiamzftDrjW9Pj7HZRVI6e/BQ7m9hrRUhlc75XsKEVmhSnUe4MrJkf3IYaRise0Sqr tzCShr6v53SKks9Yzadttklbd3sIcnelAh/kqqRIGYGmTz5dDPhTSIHkQeN6fQLwunAc4A05xbDg sngQXWXEg2SX72W3UydY6z09l2x+OGSKNYAcg5cig+prpKe13MB3qAbP48Qln+ETmMh1pVxZaWaO TwRV2z7R9oIXklFry1rIJJeuxTNwanu5l1mlZLIlBR7WhsqZAr7AmiF48avO2KBs+0m0yxFNVc3L lnBbFvDvNS/xSzdAt7XLZDH2uzr3SvJBYkRIvSKP69/DMI/WgdnzlvdAAruM8HNNj7pgEt8FJ9MJ DGN0r8lXxjW1OHSexip8zfy8w/C0ZNuVwB+Ydt+epj9ygXrkxP4mF7IzP0GhJDEtZ32S2ciGzy3p 5uMuEtVr8ecx41Pxh7vsrfJPjp4+40catEF7Ym1ij0snEgN8Rh5WzB9U7LxavRw0PGpA3FbUyhu4 ayh+dpMPri0tMaNgiVGXkKK/VkzDJSdZ7UqQCBBUZ65WdYOhOntMH91zSoTl+1x3ygplUPY6dJFA s+sTxwS8VGb2kXXeSKa7eYC8wT9gaEZKV1DxiK6seRn02qDXChGLBn+IwCCTViIMbvqPsPElktbk pGp2N/LRvuKw/my1uv1TwNWCbcT+Ka7BhnRtzvfYNjgJvA/BAguWawZfurEhKI9RltkTeP1R4Xmr W3qbxrCfW2HXMpP0pj/8VLYNL4z1bSPyJmSGP//1hIfJeIKG/2++j5Fd2gcO+pMxAfkeMThkZSMI IEKtOiRJ7QnfDgjB3o6ipGl8OUMPK7jYxmK6f6HiuljQ9Fy3dOoUKDIcBUBt67d6rjCfQTT8Sr1N 1HGAqhaU3eVKJ1q8LEsQQrxXprGsFJGYgMlAFeGg7gGJ6xpTtaPRiE577uYO6y/kqKmPjBheQCvd KOQjhYtbasSLn8pMOAyCNRnXcv0ek3B4qPi2ANrpfiZ4rT+DTIpBUJl933L+POtPmkZuwTwiplJk MOsAW57vgL9MAHCN8mW++/CQ4grIyoNBMXHV2Cr4jtzmuNHFrAxffF+W/U9Dt7M+zBEWnez69xit Q8zwNAScrprCDZoJZ7DquNyWwuioerbivV4R7uu0U+7Mq6FjcLZ2o0QapBlC+ySuOrvtMihPfMFe fh3sfmGtYCsdyqKf+r9HbTcHdiMceYxNVyySofpmZjenqysOvQYnZZbJMBMscwNpt7ndfWyo7fAv 1tPIp1NbRMfHawEVdfRv26m/BLaKq+4+mV3NHB5ZwyerRtFCCxWRU+fS9+4rqqRNPeREd7B2gxYR O3ExYSOniblYiUKlf5e2IO4IX5T/xWGqq1RiJ+xM+/gWpXGQ+wChP+oLnC5mFalIh46yzH4hyU/Y VyT8FJo2ezNTkHpKZlu+rusa+XvXvsRDWiCkkj9J471q/QWbAg9CtYFs3Zt8P682qwWVPL6oYG1t SgdBVaaZusgVNXwnlN6m9ceh+QBVsnVwKCkToI2BEAAnHsxbNnJO85BXn0y0H1mgij0HOMS+H6lB bpaQ3Go3ImxqioHAajYypg68F+Mg5r+4beA4BZ1y7ivqXEnFX0ShWhtjsgo+uGXY2t01IJ0kfKTE FYCBv4Pwbai1K8CAbD6vaRShC47ZuIEZaxoAhLjU0UcYk2MHof+IfFBvUqOZ/9jmai5xwoR6cKqR MsOAexL9g4WuT7yvuwLSLVtwB1DajPwAecGkML+IVt7GEw62kR0roC/NBj4hCW1IfnZMCtb+9SkS 9XVNLqwu13kZQDiuWEb8z1BUlFL+3irJLjLxMdHFFTXW0FyP8gB4nc3IplJtKvtxS9cfxvHzZlwY O7iyTrpTT6IebXDbA9P43n/fNpOi2WmdIcnrIi/xc2rpw0F+mSC96gOZxnsZNRe0xI6efQFJZwGU hOsxaANfi5b55pbxIwy+55Ky153a/jfI5iD+qq8oMY/D2aC+tKlNuXsPMzJ0QwcISfP7odThsIV0 hDN9Ue9XRM52N1ODHZ4/U+6OtznoPQ2lAzs+/7ft9miJGk7banNCfITBt1KAh3GmWfyuCU/wJUk8 D17tygVPM370m5EmPss5DyKaYcP2447q+ZV7H5/506hzHCrg0b4RPkdYrXxPCWj5mrfV5HEa6Iuj 2jd68za849VTvVx1Ws4Cl4QT6RJAYkV4Ca+mP3jWKUEJ92sz8HvhofKQpKzHAgqwTdiFYZ/9y9nl c51M9Uz5KBluqVw3859GEbqdgI9/GzR86h0bV4iiKzuu36rYGaPoP1X/+6VObhw6vALC/BHEBbIr Zh+EKaU9bXR1gzPeuYTmSbz/5M9uGzjyf+pwXRcOUozZXTAw5DirjWlGxZN9VCE8kTADq52v3Hs9 OEM5du4Bn+VpbO9GuzfviXvcUMCgLyokLCZTTex7KokKuyATyJLvr5QyzSp+7sBm3aAQwoK1+8/y nK3KX337zzs6DxymnUuWxBwcZCt03H5qNIHtb51EdVtYbgG/fx+WZsaplb+CErqRGnlIZJeDT85x 7dmtMFHnEZ73AKnUbfIsJM7JeA9zyI27yCjtAGc20O4h3YIbxs2l2Gnjhz+dMwbmcEBM35Pg34cd Bf+1FYNcISXL5s6QJT1NcLG4+jYSXKVSWeEfa+S2C56VNxFbNBB+qDvcExmgC0dR4vrPLO+ebxNt Awp+4XY/cJyy+SZE6ANMxpqehuwZvqdpssNmK+iHP8bozIlD2ATcP9ml8IiXKWtzMUpENlK3WUog bE8GgBsE3lJbJo+c9j2g2+0e05Gr/LMTrRFjKY//taCPJDK6uW4qRPrrNG6KqeBFnAXBzeJz4e13 xCjCBc9oz/F7lDhtxW+76WPceq/P2Fdv+AqeG3nHaL8LyBYSQGdlHlEgHC+OI34uy9EN8hqv0QK+ JbOQPg17BBTxUIjDjlZM2b0JLcbOxKig8FeDlZo0RPkSijd6tN5Ka8adSe+UhB27nU4CLxk23cq3 EqsPcfdurqUZ6rmaoojKaDecSZrfdXZ9vZu2Z79HVUynt8c/nwSfAR12O5XT7hDa0fTxWUytXhN9 3li1CJaD391XsnqHuuLUrNGGn2dKGWlfx5dvP6MMZ36QS9Czfr5PPn627esfvHzwA5km9OqDlIwF iZCw/uBXFYxRUSOe/7/wUtzJxHZXnmh1WOzTHO1fdyTpa02J4znRYM2sJKcsxoob6COo5sdWP5OK JUhwLfriIMGBDomFFoiOTOk/bxdwJjknxpvjj06koau45Bai5GN36cGCG3S7FDJHCpzXru/wxly/ DFF+F36usiA7e9VhgjxIOJk9AyiZR/vSswmoeiDnTeAofLDOfL8voItFUMzPYcTEqXG9EUYpiJV2 JIRNo4ziOqnqxvHHbRJu+cHWX2bdavSTrLwkMwjwn319oGKxWDwBxYAz+U4/so9UB85tvu/QC7u4 IvieDpFHWVN+hvIX6gGkB9TMtQsZvqOj8EQZEspy0YOHrS3EdlPxj/co11Ni+Qu3mri3czoQV3MC z8sY1ApjcHgpwutKfA9INO6SWpNCdcH/b2OHKMlqxmUN9G3HEqms629AoUNKdgUp2m19W6sQb0ir m17/6UVT8Arm592jHewLIl5fD2SQ8t17fuD0xNAqpnpCdjOPbO32kdoni2q8yOn/JaAC7xfjU+2c aCf9Ro9ta2jCsIzWKs5gLotocQ4PBFhCraf6EsXMx2vmGMLl/afWaPRaEdBFrnh5s0RPvJRB+RXI OdbVKG7P/ZvIBZR/nTGFtT1z1hAbFTE3F7Z8CQaKCCdZeBEhxIcF0v8FoNsh4EtfQEGRiX2305Fi DnqXWO0Yk+lEamcwqkamOaB8juMREgmkQeCu2fMEyPHXyytdJH7uks+AbEDrt+DVhEA1wooE5L55 EqrSwGT2NboEXUmkvUn8OokHa43pJkoxHpYAA2SXk21Alq2owyZhOx1O7ZN7iv4rvb7KqhwIoMy/ 95DMEXtoNfiNaelcExp/1C+t4phUQ9JwWKmhIeW1GwtBeaD6bWTydE6T4paiSja+46rU4VId3PV7 BRT6nJHtXCU/TbKRpFR5xZoUjQxNALCCAB4yxbHzzOQS/KggVGPuGbJyNp0QolxPSGMjglHL5Op9 La7/dAmHP2PFoYmu3PtXO0k7MXAMQxjfDJx82F2o5xfXHSgrOsOoKIXuVNQaX+Gpf8Cm+edPK6ZN NZw6wva3rAgri7O4euLUdv9qO+819DHb0SfQY8bW4UYBRMTB4VyGJOSxGkSVdo3U30cJ+LbL2BqT yqyR3RaiVGcmni/eEPwW+Xb4rrB5TqJAmfA7fnet9g2+3MygQgSPo3c2SdSIIK8J+8ivExflEIPM 8n64uOG0KXnwf/V7puy6NMTocoLlf5ryjouzLDjtwk25gDF7ig2MXD9zqn68gITZDEfCvfirYnBT 9F5RNfLNWoD+ub5r3aT3YdE2aGskxCpK7PVTcBTix6rDo/YIdIbXotWxPDtj6BTac8rkhQeAiGn9 DNQX9IaQEK7F/o9lU3xPfLeXmCmrwilAOIp7lveBj3yLJC8MpS4AuA6NauTU3G2tsNBpN2krvAQU CbAW0wYUN+8iZx/U8CS4IGdvrcYQo6nSG4AzISDIvnKptDWCpc4V+tM4/1DZf8eMYkoTWslTjGoc 4fuA8OUjVsT0yZfx641meUfY2zDDHFI3agm6HCBD4oEnxwSjsoq72++AAYr1MbVLsP+umOKLN33v e+dQwv3xJL04ScPhxE74uKvY56hgwBlowPMb/UehlZMQclZDQedh366aVI1lLec6TufciTd4DGqs RZ7jw71+5Z8Lf2lBrYurSPjhKpp3HFiL9HI6DHFmQy6gIVPJsCdlEDHpq5S5tQ3ym51fTxVMF8qv snIj1GJi7JXii2s/rTomuvrNdbgzQlKVzNU5VOxT2s7Scm1PhWCfGtfrcCwoLQ+/iBJZismybh5M YhlPBPpV7rH8s7NSqoRn8Iinygf38mV0e2Yf2mZbiUC0reGajgIz4MkAURwf+Uj/4r1TI41utyjP t91AtFPDCkeXnLeTYjn/i86o6EKVxbW6PzVfw/KlV11nZXVKW+72JcPhx8aGbU84wHkI7UYxUtsf SSEoWu6Ah4FRzXr36/dBheE0jVXKRdHcvf2svce1jnEtWHfn/Mt4v+bfsHiSTDiNkx3wrS5bWkxD cEzJGRuToO4XbYC/a6xWNFWql7mnJboHCdGQftD4Q3rt8TI2BaOnyIN66tB6N8qTURqJQdjSj9nt mAuWG5YC44djNFNGSWNqv7qCVbtgmGQVhrql4/0Dy8tWe7km5woBXNj58gSdrvcOGlcfsXp8u7Dn SUl77SKfMdsf77ZmNeqgkWed/yvjo6Wng7Lr5ESk039ecKde0Jmww0011f+Shf4TQL+rlxzBK2yN kwoDEfPgNVIGvLwOH2ha88xLhWE+D5zfZf0ldI5UyJjITjcUwByM9BKMX6nkylaNw9apU0DXXOkT LiKVDBbYcAuE/OFGqmF4niDFpU0sw1elzFeRmmc0XfDBePmLc6p390fPnD8Nm17aR8fK921WOSNe VC+mmdebktUxQ/oqqFZ3J0ghES3ULK2qa2KOr9I5Dl7PwBmdmP4AWeQitcxfLuLvsOeceAJ6lR2w TsMAXavQ0D17OEyVvAwhHiMTvmFVIgFa0cMQVPW5k9IaIOBv7fBpVKnDkspEPquGCF2bDSbolHym 0r1TXyg8y5S2gjVmuI924FNdRn3H30lqFfwuscmqTSCTGQSahYgw2piW1SXJSGH5qKPfCruLedBB l5LVz32UAzmAbpYjuR0xmmExvuV5JUByieOw8NEs7zzl2/D/GbLJvHFkmJrb9DtxJm1hqW+x2Q/M ayFidEr7VnuGHhiEhwdB6NitJ5ODHa8fQyIvBIhHNrHIsn1ZtdAXEuwRuKr+SbF3IVfKhOAZkA+W UWP4VzBP+8Avem3ypK13ROvAqJz7YCkmMclfAvuGdf9Om69zajJCluImFkFVP5s6B3ZyRSLzXFgT SklETvShQkicXf6vafrlUSBRjfu0bHiRGV92Umexbvu5eoCYquMslFSEfYG4ZeSPp6E/KCEtztfb trhEpVP88BYcQuxGWhSKjWdb2/mf9nzTNzTtsWLbasQWvG6S/0Ns3s8FGIeN6P9jy2JiWrHnY6Iw em7QvGpILwvZm83h8dK9axTP9u5CsJVo2uoxgvAaiLGS5XkBaUlHa/40w6XQFaQ+UJRGTDqU1bFN IWFrz5RG5gy11Msd4N2kEZpFfX8mejTCPlPFFR/xdp3j/DIRvdQQEqNwIE7jAXR3BTNpjDzKljJg UHS3zmX3miRGT1TCIYRyZ7qxGBrGkBvbilaK/IsS22OftEs87KGjdXKxyFvtJJFaH455ZKuDoYBi wilGeTDVAO2Uef8aSt/bJ6Cx+qhkkL0cHcea4hdc9O7Aiu5Nm2jhKi4aKrKb35dZ9EOgBlb2Zqzj fzYyiwoYxZCKc/D63I5tS4OgasyUnmzzwkVCxvkv9exeT/kb+yU/d5oXO1Sjm6g9A1C6vNjZOgLg IlzFF0Ty/CWF06X2tny2cAVM7XWwrkDfYwO/E1kqxng3MI2xMi7I/YJ40oEhLwvuhSz5v9RpOb23 bczArIOqOqItMcuFAO2wmVK/6b/FYH16ueB2sWTTpMrV7xIGMFEnTuZIo0V3QKZ1mDe+Y0rP9/02 M71i5CqXpOke7WNiIKpZoIAJyIoBB1uUFIK3E3/wJwXhaXBNXCHmkvOmmvrbr58qRswP8kCr0N+a QuAs2a29zWz+m3BbOUn5xyTF4MUfaFElepEQ4hGG2Ilzs23W83hmGhp7mZorwc4bTyn8W4ScbBsO 9gwiUKCxpRXVoAxM1Ve6Z0voJ0gB8nusgaHh4Px5QWgPGORjIaKm+O8rh9DP7Vhz07S5XTWutjzu Ca2G641EAYv/wenVffG2KUAzQm44ipRjx2h0ATctWCrllZPG3q6QAUJ84wNQ914IhIsse87ij9nK kUygOe3/05HPgxk9fqTxgbw8BReL3+zVL/rcu3dnd27Ayv5a1E50rNh9shwKGtTafnOGLrkcy0IG rE1aGYP01mgbHRx2i610B56y7hXk0VRGgm9B3izzeuUhz/Y+QV6nVmn7InRR/6uvE8+PU9+GJ99Q p9aYx0sPTxIBdTADNOxdy3RjAtVXQB2lzc2phLfe3BS4INRqx44CI3/ke/2O53FneBMci34JKY32 p8FQAKhkXKI8O4qwGF3Ro6Y96mgMkL9bNT+hJ7CWgPr4qzU96p5OXu6q/QScVl4BHEVsSvMXojVI T/pj4v2MGb7BABhZDO1aRK3Oz1ZNDT4y66k6SMHDTs/ZpaSzBXTwu5jeckAc35aCPUXTNr1vI/qL v1BWdYVth1i3zbrIURTEi5zEDIZ4HSJAVZnvHWC2YiXiV+DsEZJ8TP9FjtxyXbAPZbgrJ1GVLmJF 8TYmZ6gq9jai6xzrGSRNta9jDZPNXzv9PiiMA/kNXtLgSgeAdBqb/Cz2ZwdarX033EqJeb7vjRml 1/0a65qzCouocys/zHLIagJzD3nm5vBbAk9DXpQvAd8aiV9ai8LvyJiKoGRjO37OKfPoS2ejvmN1 HX0Jfdng2Ma0e0GPJVil54nAh9iEG+y6ZnoHRqX4hth6Ms47jgXOVH0FJZNNE9yRLNnCI8qke8gX WcPjyRDvSuQ4gzAlKVCvd+vJFNa8hfhAwcgEsJBEoQGpXKVZ5xkaTuUTEI/VFWd547sKw70tSZ4M CWov6BMt40dzydbfIZzZy/HgNuPDK7XKwWAH7q2Lyp59mobXfkdCZRC2kZK3TenlumuacGvUU8Bw LdL3mTJph+JkRATz44c3wfJqTw/Lj1n7M4QkghiKaFOpEZLT+lsxbsTHJl7rrkx40irQDTEXzclm ezk87LXiPMIcqZMPRIrGNh0Sjwe+XNqj7r3oic4d3qqzePU3j9G099PJ6MrZYw3wc+l2DIMTG58k c0TAefSWnqgaJr+0ec+FYbChpjfmeew4OIdNaYx/VpTBBgVYMUgIvqGX8dgiWpL4Ut0b45ryAflh 4xPfBkhwupNNI0TOgezFehx7h8wM1cEGwXtmnae22jARpnpi7W2cJbktXd7j3fuuqqEG03C549Nd 2uceY+Wkwlz509PbsCi4Doyc0UQP9DKDrURi3FdU/YcMoHaMFibvSofFkRdGnLix+Kc1CE1UBwFH MxNslPFXM5ZtYTsqrd1Md7VuhsrOG4jhP1r6khNPh3QQfjIE6pLIIh6obk+070vsgFc9zTtvGFZm /opkDyChudMD+NHI1sUIVMDNP46yZf815A6nVKaOkkrFih/fOIPy5jb6hQGbk05ffxzuDeIlSxmj Mi1NlnWhXrdlLYkEbrYAEKb2yPZC7sQaPD8pODJQYVmuiBurmNcntdkhGrnpze5givtRE/Zhc0iA fNPzYxiAW7kJj5nYiEFYXipJ0pRO4RAEwowNrpwiySwxJ88Q0gDidTdRj1SkHoyGWHcFpVmntQKq p1vLB8iUKdUpECton04J3DmqnEN+QoEq+HShNJ7ZjbTvvZP++Ei86btXVOnf92wbbLlU/TfsAajB 7/eSoywG7Dxv7hOv+adh+D61J383pkQaXb1wH4PyuVmiumuNxfqZ7Whw027dMiLZi00YWOSIz5pK 8pE+i6DNg5Q9krxYCQNZasUOntt382azbkzmotBFnlig/oYinG3pWGbq1vptQ55eAS+9FYOxZmjM Sx1X6dPGfO34neoj3I8S/w1saRTWGkna35Ti6VmefWX7iMp1H6Ta6/3VxsWOllb45YRwegMXrQdj NF34cXoC9TItTeJldq5w0cTLNU8iqRzHdCMNLceuL7LYdGmeYSMVxG9EeSv/ySqoVLcrSwm4i+UF +Yj+QzH/SKjiHFtbwkcw4iiWifag8vTORc+LkHK0YpBq8pNTyj/MoBn8Z+X70iY57nkaPxM1m5rS r6kARW9dSE2mztMA2vgwf49ErY97nnub1PN1vWggVIPRVfg0ELWoHptfeubRxMVMG6KHzj1+9u/z itmYvbXkn+Zc9K4tL4yLYNFUmFu+KvwDIGjw1TYNQXbO/0vifOzd5+2aN3UV+bNfb9OZdqpAATCE DK9ACKtdKaT5AKtekENJyh8Ov9BKYC/4ABUrdOXi2SfDrw/65dd5zHRDoA4jSVukLDvJM6HbNIyF Mz7MjwWGY2SPUBEzr69cwhRG3CHejRVUc1McxqxbQi4K70ZlNBj6OaeI99gCdVYpTiJ5+GU5KQVZ YMPotMsnGE8L4zFiY7Y7BXHvrFazJaXvxh9YYMcwEOeEPRMzmjyop2WuwAUbH/iZHpbSPZSFEzSC GQC0vWr7r7o5CJ1ipVDIZ1WGvUu/dyBu4ovYG1+PPUb7VpB/RJhykExg7h13lx1sOZfjhpH6GbmO viqRSfCoyQkbOll4f5OHJoSdOiZho1OEcs+j8X3bpoJnEBBkJrUn4bfpbL4+XNzNv9eaKpth/u3o WwBnHVUI1DuWjre8ERPdjZo/QMy7T7LrEw3jmMQWx1JsGpzycoBCeJRzmKlOw6AdYVdjOrZVd4o+ d0RPemorfEZHG29LO4TvMw8NnZhu0wEG1g6lc286Cz68alflmaRP2qbZ8t8+3pyclWm4l+ECQhmJ Y6rVKPLfyY4u2ItXb2yjHbbwUWINAtc7J32wbo9mkSWps+8pHQMXAIrV6ZqZoYUcqkS8ku+rxMfd 4M0a4wG9Hp73my0ZMKPNXRv+vtvAD3rjMN6zA2zY6KfACncwDYl04aNQDnH4kbLWi/aMomN4bxxY 025mb9EwocwJU1eBNaVtVWuSSJ0wpsOSXb1rER6EJ4UdGIOi4gzndk2dXG+YUe9RdNFch4rDa5h/ 3RQIroToZ0hGbOD+mi3C73AMMFrztLHAt4tHmH4veAqBSCmKQcwkGPrmctkqPJVMPtLfvjI/bOa0 Y3tGsUhrk0UNdc8VTHW8fdyScNFp8DBGhOGx8ilIsiD7NjRHjJ/rVDbRC9XYeuKS8/GV25vTiQhX ZatrSKcYyOp4FgewSPmFwz7EYejHrIkdjOb8nD8yhGPAjUuDIE9CaDe4wundTZYekxTs6pSkyzyI hnPPGGpalkSnUM29ow23wUsqEYFKhEjI1KxfG2tPR5h+DppLqKZBawjsSHEnHxMsHToit454oOtE qWDKSMOiyTp5VQOFtK7YE+KtQ7sT8SnhUN6j8ocy/G7kmnNANvoWA2YORAsbTK8A2y21gdl668ee PNe/GHED78pJk82k+nouB30hZaZIoiTMHyQZ6qjQ/sl54LwQRI0XHGcwgA3anQPe9Jx1UJSy8G3t bcej8hDqbRiIHfyg51NzloBHoD1DkC+VyZPe+C2CWRtH6yt8QywlmA5a+ohBpI0EGLMTiTJIyNzR WvjOkd6qFhGBUDy2vCA8t4WGu6ZUPib0lp8U0/d18ZvnMcmSdHz783ET6ySz3is7k9Ut3JN7OvGj gKrsYElp7xVtHq/+ckDjmmlwy6dLGhRk+ioBJLfdFKNkbyMGkBddZ++Eiqq2YEWYCUvdlVzcofNI 9PMF/4IefCDxS/qXMTNFNNS/xRxsYkIK9vMipiSCd2X484tilz9N+rjDD2cvotuC6ucEnAy7ZHGQ eX9yIR5i4TgLoCnw+k8IOpgjWj1WvEipCPId3NtnUSnM75vBCQDeY7RSdmKI5zY49jDmfqbJFJE8 5bPlO86BLrjRzDe1n7SGuvbpXCxi8IPqVMcpdZG09exNeA+V+DaUEboScUBVUBluExqVOwuDnfmD gXWgyJnbVnhEnTiwiuVqoItEziOpN2qu01mMZeVsuQAV3GL6Nh/DPQqul93sotKhF0Y6nPEwklDZ o6ti5Y0A6Wvv7qQz/QTyINHcZL6b/o71grSk7bdeynAP+lTfbsy/UP+xv1Xs63BVQArtAqqUv0jI iRwqbHuKGXqv0DXKIXZIh454eX5lsZ6i6iSFRSCO1spjXLh8HkZXs3c1rkHIPohhtiAfdTyqOXh3 BdymERmssmVjh6CvGnjr4Awsb2q/epq6YkOCz4ORJ+1OHKelYz71r/k23zlWPQbEUp+9rL4Rm+Zh ske/zHm9m5B37XI9RSDLG1GUaMgXSt7oNSVfBpMNBboLyCnZX0ZDS3dk4GVjeQ27X9HQMmeOVRoI ZQUnrFf0kU5Jx50fq3em//nKS93srpiUaUXWOKSVgtCrmtb0h1H60b5M+9uVCPuJFk1qqpayFgyR 0aIOUDfj3BPzY3KejgT3wVvufRqhmFaeaeMJOlND9cWnA+DWJo0DNOgINuak7zE4L7VvZpDpcyfW 2P0+lLtSgJNUhh5dVJ0tQrTrA0ZsA2oC5sm0PPPscVsU0nCAkVqUJC9pxKS0bGny+IFYnBsqt4sQ oIcSfmwE0Tjc1eBmS3y2Ku5vJL9sT025WAKG9LLEKmbKHRpQLvMu8RlcX9z7r/8ETWGJkLRn6WaS v1LslOtXOav00lLUDHWVE0E+ZS3K4z9vjHsobOhH+vsa2pAPkRAxUr5N9mZZaH6q6LECZrsiJ6Ek Wig32F8gZyBrLbLxoe9davpVc4jABKf1NeM08aBzBnFLoz1QNHSo3b6QdzdfqxPFUiOvl+ypSnL0 SCleIrgHDqHEaM3sQqqn7LD/HVjPftTpAkF1uE8/4K30m6IQf1uZ9eiF4XSf2SOVJTFGQ+8bpm1v 4aCPSdL/Y/8DJdNEkrWAyG/A1W0Pdzv887Wghri9q+KpQ0Sunn/YEume7enfVZj0GII8qZHJqfcp hZxNOnKs2ZCaFfBuhtYe9LTUNDSNLYAsrK/fJfl9vSFNukEssL7RsSxZFEgPUehgCrnUJA6l924c F3fO0Y5Pt6m6Eujfw28I6kPHpPwAY0y/4DLBEU/l3JsUk0V9m5qwugjLFysWDfYRshZz6FVfGSL7 saA2Cfw1se5HFNnK53OpEBxNpp3/HALxHBaVyWHUNYSUxTL8qKjBTPOQ8pbabvvK24nykWjxt9V3 DHO7mNEn5vInBt9qqgB9D9bzIME8fgo5949l2Mzt+j51Zt8BQVlEfwboPZ2+RhFwqw2mCBLOdu+V vXZ0TcX4R60tIB9xOR6JlvkvoSuQttGtKo2kQkXgXF3bKoo5WAXNfSI6ITFfY3HD6qVyJ76uUysc WkNhcbPdzR5q/oxCKep1yEX4Hpi+NSgQnFNmoWrwLRBnCtFKdnbVncya0/PujQfoLcg7g8B4Avv8 kjvvHJiSmMtW19hC/rqi9aL/SmA9nhd3pQLYlek+flyIgSUNeGNBjr+M1CRb8Jf8mUZBWIPtkkhk HUYfhZhfykoQQH/r7rbuDz5hfmCfJy0fHV8Uplh1pwyk0IsEmCN8OENAzdgM6nHcHTlNlK2tmzW/ 2NaiNS7czZwZOksgPZ+5hawWuMGNNiWSYwVt3B/p3Xm1XXAsgT7yoFFhxyN125xECwoVJ1Ex9Uiz IhFUKiasH+xFXDrEskAl+0SYphZ8pU7GJFfs2Tdnti2NOAs/VFyhbP1LqVYR/2VB5HNxQRN6mXfN W3DjGGaECZaqwHE9z/W7e9FrGwhmPVjNUSx646FwDDwhHsI6H2MwurH15mf8BPyiXrz4bf46MmJ3 uvcA9WEnCZhO4UlUjIFoM0G4z9HCHlfW0D+pm+UdCL0gyXaGnex4q7ex72zugoqNi1qG/SvWiITo 71CKmSvgFUeAh5Z9tP8AzW3l2H8p+npUmijHNvVTGMm0Zbhuy15VHh3y9ImML+f9+Y66lUsqhJMJ m90S20Bi7SUJCbcWLEocxS3Peztxr/0xMk/dSA5zdA0HEHAP+/VyQszQ5+TPPDxl3lT9X10/p1I0 Ps+OWgD8ESCtf33HHQKhzouLU6lQZTHuxDPqZTgc6JBRNrI+44Vnq5gpYd9TWwloASbaoFURvOLQ GfllS5EWGgJDVgozuxZAgEW5FVAnhfOZTtRdMtUvjgsYqcVOtfuPlA+cS3hPUAMgmjgYhOz1QG8J 7DrWt7WM96dOmRauBedjp8/R+fGyoJdiil5r4Iy7v5nhF/uY2MxU6UbWFyOzC1x4+rDTLBJdZuAF FW513IMOZFP5RfxHer7ZgkWqpnerPTRxjiJSrHMNIYt+XjNVrjywVm0y8mrVyIrhUvAxb4w2w5ax owWlu56YYKJ4pZIgQy4sB46oWfKfCCCX7ihnIbDO1/aPXEbNqhmOB4za2GR6+8BgbOCcujnsYkEM XKvScMeewd3rF1yJ69kM0fvAQz0HqNl0DrqsVsQk/H/HcElZohfqiUR+WLfrWVHhbhzbnn54IBY5 f+15OLeWC1OWexE93pB1AUE18zJJTr0eXZjMJBAApSjzIh4TyvgQdW1JBhBnL7nQEm7gAleYXdHO R826puIErMqch5lxqvCExNrcyIMb18911n94WuIwysOcyPt4HcAGKtV3lrEPp2qm2L4TZTysrGr/ Pw+XNNK3Wf9WBWL2WIi4/Lu/haYd+fL+2YSpJxL/9ctwLhJH/ZLgVsjE2ZVcp6U/JqumqSHaSYcd 8WfCGEHVZ01Cc2+ghLuWKXrc6jiaeC6gdfnu4vH54UWgQ54/qkHZ7TcEAyNYqYsOkuMwxA9LbKO0 NqvP6gBWR605u0SAEmdGmI6Pzkad8c56W7+EV+ivPHRw/5SBisKh0/Vamc4sasLKEyEZ01vWLRsI daTpS08u0gDD7n2EB/oxRMJKH06KeoB4OUq8W213YcXlRVr0A5zcYtmMr3WOlYMWp7x6nY9jU4j2 0lvV9beDGTA6JX+kPihcE2WrLoXvg2owZJHAjtOD+DhLZeN/fBjUI71qDUC8Ph9c+zkQkzfNiG3r YFvllQwB43ttUH2hy6tjCi9jGFOH1o4AxxtxUOQzgr2UzetuJQCnPhczOJIJ7xZMo0r424xB37Bc QPrfwrY88T9AmMhDlCv/UVVaSsVBHUJQJyv4YFQKrCevSkWlj+zTUpw0Qj21hcTSS2Xc2GyIifOl OgbzRuX8W+Y0LWVNqOZYTdj+keB/et+y3E/jXZvaD6nxc+8IzUvhkBjYKSP3I1Scc35WrhRR7cG3 jrNnOAcOA/kq/tVSFo+QnifOWPOQHhgHSSOUWbPowWyWqjeJpBX+s9A9rn1hpuiEnshZ/biqmuo3 6R8KQ78QjTEtLmcsfAJkBToLOkomGP195K/eoQw+7yCpJdxyF42eYwc+BG/RxjdXO51Lv/0VvoVZ Eg1gga2MuEl3JPoS/BGtO4fTE5pN1mgpQHqwYjXCko+1adKXet0LF89v5daf09EFgvvWX8HG6P7+ n35mwxHY3z/cF8he/cDSfxVgCenhm+e2IfrDfNy8wW6NT+2t7EOEgjXikdsRg5NqYHWXCyl+E1zI eBnJM7ErnGfP6X3IAOf4vvPzPnMYx310m3f50lETa9VbOfaPQdKdIJnG1q4vGZ0LntQ6z0gNz6Ox FdBDEqwA4io2v31AgWhM97J/hTkulWNHqYW9JpGTcZr37To9q/3eKGAAc8B4lrPC0IBAiaO9K2F3 d5Uu2o+ei3M1zYio7lhQtZH6St6MfNnDzDYz6fRoS8rlYp75jw/x9NHNTKmE+tKXh/asYgxZnyoR lioBu90cHOsIC7xyjkkIllgjwuqGOluCu1mHhQWqgSpDEIRF5dfZGcJws4RUytkNL43WWs9MmSrD jtahEF7/NyWBCNZGc/2QI++slECpS/rJ94qOkZEzjiqGffL/S51oFEhumZr3VMayZqjIq+McJasS 2osPI7f2Cm2rfJQQokGpc5paqI9USrQFe9kgN8KbHHHy2re3gHBSXR3g+WIgXts3TBH8vBR3E1oE sOCXveldbOPCY0nW5epBr/11dRCKF54zbHuNiUCpLhsWt0zfsDG3ZC5Q/vTYBaPoJQkwGQUoBvCo i0gpASt+ltPlnTeSUqboTyZ0hYdb/E9bXsWhhlavE9w/HZ1ZJO106NUQeC5aoFgZWqLa0xqxJhYL icZhfXHBJiHh850c8FvwTY37Tcmpz5RvyA5g9q1amyZTOBXCoVeqF5dFXO93FpeTdBMGTSe9H+XT Jb0fCrT6WTwt1i9OnA2aNEpzU1OWxzf7xKz7yrAunb7orYUuhvBWT+cqEq0ySgmLJYlTKBptwLsR vXbLJhz9ZpkqoIvEGyfZ1Njn72ofURdqVHHygIPfSi3rqz2RaRvER7dLaYD/39E30irGrSVI5h2j A5NvnEnAyo3uzM9gxz6tafqbIKwWbBMDQBFXAykmaFuqu9296d8l1QB2SxYs0iUK1ypd5t8BfVyH K+eRtXa69fODTI9Gna4Dw78kl+3yl39n3dFtASg77uAebJLTTElZUx2B6DzOjg3gXYGm0xIlWh0G sfsgIGDBLv2eN+jzoVsdJbiJh+eOrxG8puywEdpTDVCv9bwpUxDATPa6c3FO5NuKLNmPWSnApR44 s6154M5nKEzpAD5F6HTS7E8pjN0SBU8Wtuxe06LtQeLXcVc04zoO+5K3qs1e1vAW2P3UOAN3ePgz po7OYC4PwBLAtftGFFYQDOWMlB/UpMYAKtr+/ScNUVbaoeln1SrT4OqtQNRSaSG4hCGY9q5OFeyM tgV93Euw0gbcoMBx4fYVSPLyFEaTnFAg+ajmR1f11gqv+o4LxdKQbzNYon6569cuKE0Yo4dqLDS8 5GvVOMFdIkiHzVh6QmPFSkPTsowI6srBRYXCRG1LB7hSUIHJTWJv3fRtuFf6a22p8tcjqGe/2+gw 9QADzXTl/yz53oJjkkOYGNPEmWAj6LT/FBNLlv/c4DY2laEoWovd5abanFgXfOWNvvoxFH2XEKTY HOx9zCP13rTPxA04ZaOVMreXsbUecqGVydcM4rXjf7uRLqYy9pKhv9sBWi075dzUU8ySjBnEI4N7 AD28krexCj8bxID7pmiOLPRzkV5N3HJ1wWXMaVR2IQflxE6uilJzYX6eB18ahllj4iS2gwJ2KBAd sB+DTsTxb7nzua/CyyiHL3Sk3G564srMjDahVPCA8pgWsozIK4rCkRuDazujucQjMNYMK2Ic/oQE 7D3DdDabeKX3bNXKfD/BL3Ia/mitOHLC11McWnjc3slaoNd1gFDzYbbUFJfngNJeLvu+WkUzU/XZ rSBpUiWW8QBVW0cZyRM92jpOPoycoUW1U4RbiEr2XYzVdfXp0s32/eSShQq1/M+RmRbj2pGPlaYV Ac2b9rCzB+DvZ6Zq9XrERS2EIDH7CDPECN5rsswTpyaXhc1w8pCxzVzcQMy8jRZjVxmsjVm+Aw+3 Nob0W4Zaqq5juEJ/O7p6FPusw7k/Wtv59FBS0vjxYJQ7XmYOIDhIh4F+cgdtIXgAXZfHxbemvS65 UwYcuNG8npWIJHl2HTha5G3ChoaqrtWu6MmRg3rGT/ah9vyxjwQs2CVZ7D20E27n+uJ/A8tQELDp +nWMuSR9LW+xHVR8mD4h6cBjLNsjZOAPD/DLeOUegstLLRVTR3ga36X8hV2Fl2vaUuaTlMksoxeH Z6LE59v3QGAsX2H/zKeKlpVCzAlBYIwjQn4ILCiVwOaCB85IQOQCfKxhKgB/VJXxDcsMaXOCQeTs Ntty1wH3SmU33dBWVNvVObWnMh5eCPYR9/jkU94zkbiRN0JsUndxJffp8X878RyMvzIFKVEd/uV3 35K5Yv+b6nM1qgUlQoGQsnCUWLLiERo+gEWjwrlbIieqmrCzla43s7YlAPlcurUFv73yczfSMLtP zWThkXK8mlr86z6NtC6OxhtunshuK0ZgwFT58EyKEYrcnxOk4Eft/o9VJePvy6kxXvn//jiDTuNB erWyYbLo8hpEe2mnBtK0dPN2CVgIXlvnIeRy5kHYfIWhtyFohpMLej+7mesp5VrXM2JyZ3lQghk7 iaW77SzMTWDk2SZbsIl+Gckf5SVP8/SSxAlVqEvcSlcDUh5fEU/ddBsqD7/a8eTPJ4QYcFI4lb+4 tznvXaUtiAiNmrouYuyjrspVtAyF6VRRu5g7C72W5D38DzdUwruT+OsBB5wdhUrWd+zICmnKzRf8 FW/rGSrYq2xsD1FYYFlf5buLcAJlov+0C1SFo2NK4PQJd5A8vcHbBKgMLAJJuBhmXhOaXol/Vsxt hgjdOBxJZd072RbZ0gJNhBHxfLad+1zH6RQTJKjklWRBggjWX34ARTpnhENjym34ifDDEeYHrRRn Qb6OJzGJSI7TllM/rBHMhfC1GEueUHiMK3Sk/lBxhLe6Bn0GkAAspDk5VHUyozHCrJMlpY2/26AT GmclKNp65U6ayUjuR5CrqWXXj6HqSuyIlE1PlFSIujdcbKcWSJAhgn3lraGh5vuSuHmAM5+L3RAA sq87uhulnUi4AcHyBOJzzeXEUbTNrvgDWisOfDkOUeaYonjBtK2uJhEO33MDkedeGS4ayqE7BGoR LpQANExyP5qj3wpYFS6y10MxixizM5bZPzITvvWXH6NAcF1qJo2bDpACbQZbUEizP9KkwI1sogOy +RTHvSlrcskRpBlfg6jacFlKRhIe5Z88xOdqJk3clBvIGO4oEfoBDoIPN0VVlgEGRrgK+COAdsv4 TZrMvLl28k6WeYTG14+sRRWVWu5Lh4bLP5CzTswsr+57qLUWTtrdmB+0ry4rw5oDcytRiIcWrFR8 W/9aGMVFdU2uZNhKhIyxy9aV8JR+chpOW4nPylPsDPg03xIslzAHwGNKD9tjOua3HtSCiZ02dKl0 56ujfv5hDTgIfwuT9nVQP3rPh7nNpkpZk7Cwo87b1jGmRAdGFtHNaNSQlESGnPeW/mfQY3FSg/3D 2o0a4ZCTjQoExCbn84oDyVLkqjHbveVBKO2oqNrqauIKXvN2v1lIMdETH5KYXs1pgYiYLvIylSFv W4ojBOb+UONdKrWFsCfnYNhmZlKQVL30pBgQau1PwTv+bv6cz6k8cX/efywPRtQ4dJh+WLHn2RuW jrDmN8O7G5IbeYXcBa1h/1ojTQyLqzNZDVfvH5mKVanc1MoBGzFIIpWLVwYbvJw7OT5xnOB4vvkB CXvAryvFaad5+DeX/3ioiy9wnLdOYO4yhf5odL7M6FDVfcIfYr1JGJDUYjyPjETrgOkwrsS+gePN E2Y2vsLeqtuRC6J1sCxu7KTyG7gv+zeeG/ADGxkIkQWxGRngBanaCJuHiP0QJ2nEqIfpmR8rkpaL Rh3BbsAPBvMbztjFmn3pN6dBRSe2RrYSpgRFUJqvj7TzcMiwE3/i+UfbWhdP5HdFJvhOjxr+mawU xd3N16KP0oOQZiL9IiV0bG5RrQm7+kzK+50J1tjfRrEd1SyWvPkLLIsIiGe40MUlZxwxuVHc2iZe 2Q871D5hBnRtZ5rFNiRkqcrP+hk+2FUK0tM1ml/JhdU7JTjStuZbxiq52mH/jccglPAQ4eOE8E0E oioUYTvHv6QEzbLCOvq+5A8C6RCALdANWTWOqQxnu20Mftz6ILQalWOT1pR4dxPKT2RFNLLOCS0y bLBoWoTNjRNocLUpQyQezVF0G6acxa228J9JQGx2X+TlHGKYMtxcr+SsHYvE9Y3Bn4OhcgeRKv3h aOFjxfoOhdN4BWH+lW4L+U+N1Tq0KVtCDyI3vnPVCxCM2wCqsQq/Try91M4nHomlOv7dQ2o5gTtp M+irjj0l0DoKtfrgkT0E85SkclpBpvnN7CuC30BzthgTBoXI8fHIVcmAFw9sgcmOzVAA6M+EPmrm 7F9jvVvTu2hqWi/9ovLm9mA7jsAXRi+XGC2meq+WfVN/mLXogN2MobXCvrLfn/2mvsyXJ/0BA4WL IcQyD51TOqfDTclcOKFsf4PE0pwZ2lxENFVb10jYB1YtErYYbcGcw9Fm1W1C1sJxoZva7ZuTriN/ mT6jS+Qt/8i7861QmEAsHqzG7Ug/3ZpuuDWOAyi8dke3tq2mVjM7TmpC5HLQD5b1Obq5GcJc+bYU BXcBvMAj53JlyanH93g/TSMX6W/qm0NSr8h3Y5AvfPOM/zHWxDc1J9OcRFURW6bxUh7njOqkx7dM +Jsx9isFmx9vOI7go/LSYwf8KPaGfZa4Y6wZzVhfCJhuhG+D7xTAOerJ/SAt0HTWwQXBpGGraGnj T2WtKIb/XtHSlUmDyQI0SZVgsDNQ/oR7HWUYi6ERTgpJqUtRVEtAYFyHvkScdKLHrPbn4JvXUiBw tdAFbWxuP+YoOUSdqOO3VCdEOiGueO04EHj8DMwHoKiz/bIQgB7Um4iWW/bk9rO5xen0JlaAMitX 3qrQ/v60X9svZ7iNXf25ilhCAw5oNonH1Nqpe22VfRBTqaqmwo2QksWJZc+3pJlYE/hS/x0gQoL1 8LoxiDm1ZkfcldsdwEQVDFLgajqD81LHvh5twEzH9u0dit6aOg4BXxWZBCXGclWWizhk1bsYe7Lz h6nsgIInrr7oaoTPBGy0vN2HpMw+a/p1FZM+BuSax1KFYqkF7zWEUUH9n3tAj4AVliusnJfI3SIa tNdza+SKakPvaALvYdjoF7teHSWUzYztKe6Ulv2YEMAeorTmRjCpYHlov9t895nIxHsX1zqRMgCZ hnDANegrudmpQROm/vivbiKPJOg7kaAQesu2fLPSFH2tz5zvP2P42vK9WSkqDCC+fez3RPTfRac0 6nNg/D9S+gFK9tH4Th80umCprWE4XGrr+xK7YFR+7ebn6f237JEeyPfwIE4V1z230BVmAY7xNndn 4r2ed2MO00HCJ6MEZXv8FNEa26gx/NTFmOqQOjlDcCBPcOLbMyWUd9uvcWVySEXYToc4WolMpUKJ dq8ckVDXZh61bBZjJqtXfEPelyNVkweT1hJrHwn7NRDbnbXbpM8YkpHEy1r44KCDuTMo64GrDdfl w/YajpJLllubl2IKLRH+mwWzUG7M0Sn+uqE/Zq/pcLclCcSJSKd/cQbVHXNnTECavVJYLL8spqMU QA7Z6lcEvAV8zFX5Q0qeMhCuLlYyCv4tLl5jHJjEhN6Ozz1C6F2XSzHi43ZXIizkyq6Cv6F5BrUM iIdyzoWefaC3eVKrQdyu7kQVwUMcUkODZCbNF4c9csyy7apY/o5N7BTvXEcDV2Uxs4ohMP7tIEXO bzDWbrFz93VG1PasBmVsj7pq+nEOpp8Pp4Tf8keA7t6cU/2X9Oo/Mre/AmiRzuBrnfJ7wV0bQAIe lgTRgi5FhAWDPWs5aW4QGtc3jbfDXINPhpL9NTWyh76c+doIctOPc1vP9fCM0/xH+/nnFP7sj7vg oxWAADyTAHmeECoKs7hT9T3uM2M65wezjfgUcujnUZCn0PR3S+F4ods0/iYBc+4kXmd8Ob60SK56 3y+Uxvm+np0OP0Q6JG687Bkm1ps8XQSLTUqDflAHgj5ya2/imJVXblSeoF1vz5kWCWXma40IQ0T5 UCKjNsrahzWcQdQtHfhcJDm7yZIBPNQesBDdrBzjCM1r1sX2JJxKuHXylOcU58CZIlrtX8uiklZM FNrl5d4zYth3q3jNWeUgsDHghlPT2yu35shMfOL30guGaZQik8qpzXP5IROOlOz5o+iKVjrysKw+ 23pV+93Y7yoq/Xf9fsB1LOjQTBYyjKViYp4a0jYdnWasafeXzmFpNQkp6z8ZtsPDthcif3qXaUx3 H2n20Icf63YNyYj4d0TJRo6rjTdtRi6Zp+jAUSNNtMc6rlk391uI0XLA3apsSBWCq+fYJ4jVP75h uSC58LGLWD20c4XeltVIUsLz/qKmdm+NvOqWELA0edlVugcCpHLJmdueCRpBwUUg9F+oQIq13LNr VHClfjNzQhyVCwUCqYtdhcDbDVrYlJKyzjbkUcGXz8om2rvJvv+AEHsJqAiXJOWcygmMd7T5mRH9 yN+uOQvp4WDy3sGuCQRsmblbx2tlwJMxpinT0b4zx3zttsL29impSRcqThy0G38xdaYl3HLJWQSh v45D6ZDS6Zd7RMRunICLJcRaM66YIGOe2VWP4rY6k7ENISwmpyDFSXOb18Eij19UaC+gCRtVPyCn M7xyAf2uk6mczSDEYSpzaLEqA/2KLc376a/4c85KO9uz4RZcUpNw+iYVAdgJ6yMvvyXIeBp1jCR+ z7HVh00ZsUUIMKWgTZwkKbPJmNEzLkrztv0biu0UW+js5tqfEs444N7CietD/Ksk2L4VLpsBYaGs fKDfRwwUO4XBWXBENC3Du8slighv2YfBlrN4UPEmnNsrdi7tFzE1rqZZmntbcXkM1Ua2D0rVrVmy QexbG5EprZXsNtiB8PME+wRDC+4q6Bhu33581H9OZXyJtVs8bktqh7NpK9JJs4E4B1TdUD70190n mqE0A2x3mx3lQ7qral9NANO51OXnFQA2eMrQVYBlyTKIVDt2SG1vJ01NeIQTUKaZoLG3qlJ/ZbJy evDX4KuDIi7K+tIivGq2PohNsTbfGCip8BhtEItu3kRVS4PR8fw8wkaSXAZbp7mUivHPik/t9EkF lekP0whr8N2mDCaba35ok0ezrSK3rKytC6Tb1caHYYmAVU7eZ2+x/iAkjIvG+awNrl4Ckx4djeYL FMsaMDNYPrKvnphz2X0vouiIV0L0/pwnAQ== `protect end_protected

mit

de326321f5036fb3e527118e09beb935

joalcava/sparcv8-monocicle

psr.vhd

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:25:06 10/20/2016 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity psr is Port( clk : in std_logic; reset : in std_logic; nzvc : in std_logic_vector(3 downto 0); ncwp : in std_logic; carry : out std_logic; cwp : out std_logic ); end psr; architecture psrArq of psr is signal PSRDATA : std_logic_vector (3 downto 0) := "0000"; begin process(clk,nzvc,ncwp,reset) begin if (reset='1') then PSRDATA<= "0000"; carry<= '0'; cwp <= '0'; else if (rising_edge(clk))then PSRDATA<= nzvc; carry<=PSRDATA(0); cwp <= ncwp; end if; end if; end process; end psrArq;

gpl-3.0

6573b5ff5afe0f63e3412da78475ecb4

joalcava/sparcv8-monocicle

MuxPC.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MuxPC is Port ( PCdisp30 : in STD_LOGIC_VECTOR(31 downto 0); PCdisp22 : in STD_LOGIC_VECTOR(31 downto 0); PC : in STD_LOGIC_VECTOR(31 downto 0); PCplus1 : in STD_LOGIC_VECTOR(31 downto 0); PCSource: in STD_LOGIC_VECTOR(1 downto 0); nPC : out STD_LOGIC_VECTOR(31 downto 0) ); end MuxPC; architecture Behavioral of MuxPC is begin process(PCdisp30,PCdisp22,PC,PCSource) begin if (PCSource="10") then nPC <= PCdisp22; elsif (PCsource="01") then nPC <= PCdisp30; elsif (PCSource="00") then nPC <= PC; else nPC <= PCplus1; end if; end process; end Behavioral;

gpl-3.0

614b946e8fe80bfaa8c517532e433bc4

preusser/q27

src/vhdl/PoC/common/physical.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel -- Thomas B. Preusser -- -- Package: This VHDL package declares new physical types and their -- conversion functions. -- -- Description: -- ------------------------------------- -- For detailed documentation see below. -- -- NAMING CONVENTION: -- t - time -- p - period -- d - delay -- f - frequency -- br - baud rate -- vec - vector -- -- ATTENTION: -- This package is not supported by Xilinx Synthese Tools prior to 14.7! -- -- It was successfully tested with: -- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7 -- - Quartus II 13.1 -- - QuestaSim 10.0d -- - GHDL 0.31 -- -- Tool chains with known issues: -- - Xilinx Vivado Synthesis 2014.4 -- -- Untested tool chains -- - Xilinx Vivado Simulator (xSim) 2014.4 -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.math_real.all; library PoC; use PoC.config.all; use PoC.utils.all; use PoC.strings.all; package physical is type FREQ is range 0 to integer'high units Hz; kHz = 1000 Hz; MHz = 1000 kHz; GHz = 1000 MHz; end units; type BAUD is range 0 to integer'high units Bd; kBd = 1000 Bd; MBd = 1000 kBd; GBd = 1000 MBd; end units; type MEMORY is range 0 to integer'high units Byte; KiB = 1024 Byte; MiB = 1024 KiB; GiB = 1024 MiB; end units; -- vector data types type T_TIMEVEC is array(natural range <>) of time; type T_FREQVEC is array(natural range <>) of FREQ; type T_BAUDVEC is array(natural range <>) of BAUD; type T_MEMVEC is array(natural range <>) of MEMORY; -- if true: TimingToCycles reports difference between expected and actual result constant C_PHYSICAL_REPORT_TIMING_DEVIATION : boolean := TRUE; -- conversion functions function to_time(f : FREQ) return time; function to_freq(p : time) return FREQ; function to_freq(br : BAUD) return FREQ; function to_baud(str : string) return BAUD; -- inter-type arithmetic function "/"(x : real; t : time) return FREQ; function "/"(x : real; f : FREQ) return time; function "*"(t : time; f : FREQ) return real; function "*"(f : FREQ; t : time) return real; -- if-then-else function ite(cond : boolean; value1 : time; value2 : time) return time; function ite(cond : boolean; value1 : FREQ; value2 : FREQ) return FREQ; function ite(cond : boolean; value1 : BAUD; value2 : BAUD) return BAUD; function ite(cond : boolean; value1 : MEMORY; value2 : MEMORY) return MEMORY; -- min/ max for 2 arguments function tmin(arg1 : time; arg2 : time) return time; -- Calculates: min(arg1, arg2) for times function fmin(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies function bmin(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second function mmin(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory function tmax(arg1 : time; arg2 : time) return time; -- Calculates: max(arg1, arg2) for times function fmax(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies function bmax(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second function mmax(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory -- min/max/sum as vector aggregation function tmin(vec : T_TIMEVEC) return time; -- Calculates: min(vec) for a time vector function fmin(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector function bmin(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector function mmin(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector function tmax(vec : T_TIMEVEC) return time; -- Calculates: max(vec) for a time vector function fmax(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector function bmax(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector function mmax(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector function tsum(vec : T_TIMEVEC) return time; -- Calculates: sum(vec) for a time vector function fsum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector function bsum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector function msum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector -- convert standard types (NATURAL, REAL) to time (TIME) function fs2Time(t_fs : integer) return time; function ps2Time(t_ps : integer) return time; function ns2Time(t_ns : integer) return time; function us2Time(t_us : integer) return time; function ms2Time(t_ms : integer) return time; function sec2Time(t_sec : integer) return time; function fs2Time(t_fs : REAL) return time; function ps2Time(t_ps : REAL) return time; function ns2Time(t_ns : REAL) return time; function us2Time(t_us : REAL) return time; function ms2Time(t_ms : REAL) return time; function sec2Time(t_sec : REAL) return time; -- convert standard types (NATURAL, REAL) to period (TIME) function Hz2Time(f_Hz : natural) return time; function kHz2Time(f_kHz : natural) return time; function MHz2Time(f_MHz : natural) return time; function GHz2Time(f_GHz : natural) return time; function Hz2Time(f_Hz : REAL) return time; function kHz2Time(f_kHz : REAL) return time; function MHz2Time(f_MHz : REAL) return time; function GHz2Time(f_GHz : REAL) return time; -- convert standard types (NATURAL, REAL) to frequency (FREQ) function Hz2Freq(f_Hz : natural) return FREQ; function kHz2Freq(f_kHz : natural) return FREQ; function MHz2Freq(f_MHz : natural) return FREQ; function GHz2Freq(f_GHz : natural) return FREQ; function Hz2Freq(f_Hz : REAL) return FREQ; function kHz2Freq(f_kHz : REAL) return FREQ; function MHz2Freq(f_MHz : REAL) return FREQ; function GHz2Freq(f_GHz : REAL) return FREQ; -- convert physical types to standard type (REAL) function to_real(t : time; scale : time) return REAL; function to_real(f : FREQ; scale : FREQ) return REAL; function to_real(br : BAUD; scale : BAUD) return REAL; function to_real(mem : MEMORY; scale : MEMORY) return REAL; -- convert physical types to standard type (INTEGER) function to_int(t : time; scale : time; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return integer; -- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period function TimingToCycles(Timing : time; Clock_Period : time; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural; function TimingToCycles(Timing : time; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural; function CyclesToDelay(Cycles : natural; Clock_Period : time) return time; function CyclesToDelay(Cycles : natural; Clock_Frequency : FREQ) return time; -- convert and format physical types to STRING function to_string(t : time; precision : natural) return string; function to_string(f : FREQ; precision : natural) return string; function to_string(br : BAUD; precision : natural) return string; function to_string(mem : MEMORY; precision : natural) return string; end package; package body physical is -- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps) function MinimalTimeResolutionInSimulation return time is begin if (1 fs > 0 sec) then return 1 fs; elsif (1 ps > 0 sec) then return 1 ps; elsif (1 ns > 0 sec) then return 1 ns; elsif (1 us > 0 sec) then return 1 us; elsif (1 ms > 0 sec) then return 1 ms; else return 1 sec; end if; end function; -- real division for physical types -- =========================================================================== function div(a : time; b : time) return REAL is constant MTRIS : time := MinimalTimeResolutionInSimulation; variable a_real : real; variable b_real : real; begin -- Quartus-II work-around if a < 1 us then a_real := real(a / MTRIS); elsif a < 1 ms then a_real := real(a / (1000 * MTRIS)) * 1000.0; elsif a < 1 sec then a_real := real(a / (1000000 * MTRIS)) * 1000000.0; else a_real := real(a / (1000000000 * MTRIS)) * 1000000000.0; end if; if b < 1 us then b_real := real(b / MTRIS); elsif b < 1 ms then b_real := real(b / (1000 * MTRIS)) * 1000.0; elsif b < 1 sec then b_real := real(b / (1000000 * MTRIS)) * 1000000.0; else b_real := real(b / (1000000000 * MTRIS)) * 1000000000.0; end if; return a_real / b_real; end function; function div(a : FREQ; b : FREQ) return REAL is begin return real(a / 1 Hz) / real(b / 1 Hz); end function; function div(a : BAUD; b : BAUD) return REAL is begin return real(a / 1 Bd) / real(b / 1 Bd); end function; function div(a : MEMORY; b : MEMORY) return REAL is begin return real(a / 1 Byte) / real(b / 1 Byte); end function; -- conversion functions -- =========================================================================== function to_time(f : FREQ) return time is variable res : time; begin res := div(1000 MHz, f) * 1 ns; if (POC_VERBOSE = TRUE) then report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note; end if; return res; end function; function to_freq(p : time) return FREQ is variable res : FREQ; begin if (p <= 1 sec) then res := div(1 sec, p) * 1 Hz; else report "to_freq: input period exceeds output frequency scale." severity failure; end if; if (POC_VERBOSE = TRUE) then report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note; end if; return res; end function; function to_freq(br : BAUD) return FREQ is variable res : FREQ; begin res := (br / 1 Bd) * 1 Hz; if (POC_VERBOSE = TRUE) then report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note; end if; return res; end function; function to_baud(str : string) return BAUD is variable pos : integer; variable int : natural; variable base : positive; variable frac : natural; variable digits : natural; begin pos := str'low; int := 0; frac := 0; digits := 0; -- read integer part for i in pos to str'high loop if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i)); elsif (str(i) = '.') then pos := -i; exit; elsif (str(i) = ' ') then pos := i; exit; else pos := 0; exit; end if; end loop; -- read fractional part if ((pos < 0) and (-pos < str'high)) then for i in -pos+1 to str'high loop if ((frac = 0) and (str(i) = '0')) then next; elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i)); elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit; else pos := 0; exit; end if; end loop; end if; -- abort if format is unknown if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if; -- parse unit pos := pos + 1; if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then return int * 1 Bd; elsif (pos + 2 = str'high) then if (str(pos to pos + 2) = "kBd") then if (frac = 0) then return (int * 1 kBd); elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd); else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd); end if; elsif (str(pos to pos + 2) = "MBd") then if (frac = 0) then return (int * 1 kBd); elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd); elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd); else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd); end if; elsif (str(pos to pos + 2) = "GBd") then if (frac = 0) then return (int * 1 kBd); elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd); elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd); elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd); else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd); end if; else report "to_baud: Unknown unit." severity FAILURE; end if; else report "to_baud: Unknown format" severity FAILURE; end if; end function; -- inter-type arithmetic -- =========================================================================== function "/"(x : real; t : time) return FREQ is begin return x*div(1 ms, t) * 1 kHz; end function; function "/"(x : real; f : FREQ) return time is begin return x*div(1 kHz, f) * 1 ms; end function; function "*"(t : time; f : FREQ) return real is begin return div(t, 1.0/f); end function; function "*"(f : FREQ; t : time) return real is begin return div(f, 1.0/t); end function; -- if-then-else -- =========================================================================== function ite(cond : boolean; value1 : time; value2 : time) return time is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : FREQ; value2 : FREQ) return FREQ is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : BAUD; value2 : BAUD) return BAUD is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : MEMORY; value2 : MEMORY) return MEMORY is begin if cond then return value1; else return value2; end if; end function; -- min/ max for 2 arguments -- =========================================================================== -- Calculates: min(arg1, arg2) for times function tmin(arg1 : time; arg2 : time) return time is begin if (arg1 < arg2) then return arg1; end if; return arg2; end function; -- Calculates: min(arg1, arg2) for frequencies function fmin(arg1 : FREQ; arg2 : FREQ) return FREQ is begin if (arg1 < arg2) then return arg1; end if; return arg2; end function; -- Calculates: min(arg1, arg2) for symbols per second function bmin(arg1 : BAUD; arg2 : BAUD) return BAUD is begin if (arg1 < arg2) then return arg1; end if; return arg2; end function; -- Calculates: min(arg1, arg2) for memory function mmin(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is begin if (arg1 < arg2) then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for times function tmax(arg1 : time; arg2 : time) return time is begin if (arg1 > arg2) then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for frequencies function fmax(arg1 : FREQ; arg2 : FREQ) return FREQ is begin if (arg1 > arg2) then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for symbols per second function bmax(arg1 : BAUD; arg2 : BAUD) return BAUD is begin if (arg1 > arg2) then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for memory function mmax(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is begin if (arg1 > arg2) then return arg1; end if; return arg2; end function; -- min/max/sum as vector aggregation -- =========================================================================== -- Calculates: min(vec) for a time vector function tmin(vec : T_TIMEVEC) return time is variable res : time := time'high; begin for i in vec'range loop if (vec(i) < res) then res := vec(i); end if; end loop; return res; end; -- Calculates: min(vec) for a frequency vector function fmin(vec : T_FREQVEC) return FREQ is variable res : FREQ := FREQ'high; begin for i in vec'range loop if (integer(FREQ'pos(vec(i))) < integer(FREQ'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: min(vec) for a baud vector function bmin(vec : T_BAUDVEC) return BAUD is variable res : BAUD := BAUD'high; begin for i in vec'range loop if (integer(BAUD'pos(vec(i))) < integer(BAUD'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: min(vec) for a memory vector function mmin(vec : T_MEMVEC) return MEMORY is variable res : MEMORY := MEMORY'high; begin for i in vec'range loop if (integer(MEMORY'pos(vec(i))) < integer(MEMORY'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: max(vec) for a time vector function tmax(vec : T_TIMEVEC) return time is variable res : time := time'low; begin for i in vec'range loop if (vec(i) > res) then res := vec(i); end if; end loop; return res; end; -- Calculates: max(vec) for a frequency vector function fmax(vec : T_FREQVEC) return FREQ is variable res : FREQ := FREQ'low; begin for i in vec'range loop if (integer(FREQ'pos(vec(i))) > integer(FREQ'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: max(vec) for a baud vector function bmax(vec : T_BAUDVEC) return BAUD is variable res : BAUD := BAUD'low; begin for i in vec'range loop if (integer(BAUD'pos(vec(i))) > integer(BAUD'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: max(vec) for a memory vector function mmax(vec : T_MEMVEC) return MEMORY is variable res : MEMORY := MEMORY'low; begin for i in vec'range loop if (integer(MEMORY'pos(vec(i))) > integer(MEMORY'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: sum(vec) for a time vector function tsum(vec : T_TIMEVEC) return time is variable res : time := 0 fs; begin for i in vec'range loop res := res + vec(i); end loop; return res; end; -- Calculates: sum(vec) for a frequency vector function fsum(vec : T_FREQVEC) return FREQ is variable res : FREQ := 0 Hz; begin for i in vec'range loop res := res + vec(i); end loop; return res; end; -- Calculates: sum(vec) for a baud vector function bsum(vec : T_BAUDVEC) return BAUD is variable res : BAUD := 0 Bd; begin for i in vec'range loop res := res + vec(i); end loop; return res; end; -- Calculates: sum(vec) for a memory vector function msum(vec : T_MEMVEC) return MEMORY is variable res : MEMORY := 0 Byte; begin for i in vec'range loop res := res + vec(i); end loop; return res; end; -- convert standard types (NATURAL, REAL) to time (TIME) -- =========================================================================== function fs2Time(t_fs : integer) return time is begin return t_fs * 1 fs; end function; function ps2Time(t_ps : integer) return time is begin return t_ps * 1 ps; end function; function ns2Time(t_ns : integer) return time is begin return t_ns * 1 ns; end function; function us2Time(t_us : integer) return time is begin return t_us * 1 us; end function; function ms2Time(t_ms : integer) return time is begin return t_ms * 1 ms; end function; function sec2Time(t_sec : integer) return time is begin return t_sec * 1 sec; end function; function fs2Time(t_fs : REAL) return time is begin return t_fs * 1 fs; end function; function ps2Time(t_ps : REAL) return time is begin return t_ps * 1 ps; end function; function ns2Time(t_ns : REAL) return time is begin return t_ns * 1 ns; end function; function us2Time(t_us : REAL) return time is begin return t_us * 1 us; end function; function ms2Time(t_ms : REAL) return time is begin return t_ms * 1 ms; end function; function sec2Time(t_sec : REAL) return time is begin return t_sec * 1 sec; end function; -- convert standard types (NATURAL, REAL) to period (TIME) -- =========================================================================== function Hz2Time(f_Hz : natural) return time is begin return 1 sec / f_Hz; end function; function kHz2Time(f_kHz : natural) return time is begin return 1 ms / f_kHz; end function; function MHz2Time(f_MHz : natural) return time is begin return 1 us / f_MHz; end function; function GHz2Time(f_GHz : natural) return time is begin return 1 ns / f_GHz; end function; function Hz2Time(f_Hz : REAL) return time is begin return 1 sec / f_Hz; end function; function kHz2Time(f_kHz : REAL) return time is begin return 1 ms / f_kHz; end function; function MHz2Time(f_MHz : REAL) return time is begin return 1 us / f_MHz; end function; function GHz2Time(f_GHz : REAL) return time is begin return 1 ns / f_GHz; end function; -- convert standard types (NATURAL, REAL) to frequency (FREQ) -- =========================================================================== function Hz2Freq(f_Hz : natural) return FREQ is begin return f_Hz * 1 Hz; end function; function kHz2Freq(f_kHz : natural) return FREQ is begin return f_kHz * 1 kHz; end function; function MHz2Freq(f_MHz : natural) return FREQ is begin return f_MHz * 1 MHz; end function; function GHz2Freq(f_GHz : natural) return FREQ is begin return f_GHz * 1 GHz; end function; function Hz2Freq(f_Hz : REAL) return FREQ is begin return f_Hz * 1 Hz; end function; function kHz2Freq(f_kHz : REAL )return FREQ is begin return f_kHz * 1 kHz; end function; function MHz2Freq(f_MHz : REAL )return FREQ is begin return f_MHz * 1 MHz; end function; function GHz2Freq(f_GHz : REAL )return FREQ is begin return f_GHz * 1 GHz; end function; -- convert physical types to standard type (REAL) -- =========================================================================== function to_real(t : time; scale : time) return REAL is begin if (scale = 1 fs) then return div(t, 1 fs); elsif (scale = 1 ps) then return div(t, 1 ps); elsif (scale = 1 ns) then return div(t, 1 ns); elsif (scale = 1 us) then return div(t, 1 us); elsif (scale = 1 ms) then return div(t, 1 ms); elsif (scale = 1 sec) then return div(t, 1 sec); else report "to_real: scale must have a value of '1 <unit>'" severity failure; end if; end; function to_real(f : FREQ; scale : FREQ) return REAL is begin if (scale = 1 Hz) then return div(f, 1 Hz); elsif (scale = 1 kHz) then return div(f, 1 kHz); elsif (scale = 1 MHz) then return div(f, 1 MHz); elsif (scale = 1 GHz) then return div(f, 1 GHz); -- elsif (scale = 1 THz) then return div(f, 1 THz); else report "to_real: scale must have a value of '1 <unit>'" severity failure; end if; end; function to_real(br : BAUD; scale : BAUD) return REAL is begin if (scale = 1 Bd) then return div(br, 1 Bd); elsif (scale = 1 kBd) then return div(br, 1 kBd); elsif (scale = 1 MBd) then return div(br, 1 MBd); elsif (scale = 1 GBd) then return div(br, 1 GBd); else report "to_real: scale must have a value of '1 <unit>'" severity failure; end if; end; function to_real(mem : MEMORY; scale : MEMORY) return REAL is begin if (scale = 1 Byte) then return div(mem, 1 Byte); elsif (scale = 1 KiB) then return div(mem, 1 KiB); elsif (scale = 1 MiB) then return div(mem, 1 MiB); elsif (scale = 1 GiB) then return div(mem, 1 GiB); else report "to_real: scale must have a value of '1 <unit>'" severity failure; end if; end; -- convert physical types to standard type (INTEGER) -- =========================================================================== function to_int(t : time; scale : time; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(t, scale))); when ROUND_DOWN => return integer(floor(to_real(t, scale))); when ROUND_TO_NEAREST => return integer(round(to_real(t, scale))); when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; end; function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(f, scale))); when ROUND_DOWN => return integer(floor(to_real(f, scale))); when ROUND_TO_NEAREST => return integer(round(to_real(f, scale))); when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; end; function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(br, scale))); when ROUND_DOWN => return integer(floor(to_real(br, scale))); when ROUND_TO_NEAREST => return integer(round(to_real(br, scale))); when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; end; function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(mem, scale))); when ROUND_DOWN => return integer(floor(to_real(mem, scale))); when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale))); when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; end; -- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period -- =========================================================================== -- @param Timing A given timing or delay, which should be archived -- @param Clock_Period The period of the circuits clock -- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN function TimingToCycles(Timing : time; Clock_Period : time; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural is variable res_real : REAL; variable res_nat : natural; variable res_time : time; variable res_dev : REAL; begin res_real := div(Timing, Clock_Period); case RoundingStyle is when ROUND_TO_NEAREST => res_nat := natural(round(res_real)); when ROUND_UP => res_nat := natural(ceil(res_real)); when ROUND_DOWN => res_nat := natural(floor(res_real)); when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure; end case; res_time := CyclesToDelay(res_nat, Clock_Period); res_dev := (div(res_time, Timing) - 1.0) * 100.0; if (POC_VERBOSE = TRUE) then report "TimingToCycles: " & CR & " Timing: " & to_string(Timing, 3) & CR & " Clock_Period: " & to_string(Clock_Period, 3) & CR & " RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR & " res_real = " & str_format(res_real, 3) & CR & " => " & integer'image(res_nat) severity note; end if; if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then report "TimingToCycles (timing deviation report): " & CR & " timing to achieve: " & to_string(Timing, 3) & CR & " calculated cycles: " & integer'image(res_nat) & " cy" & CR & " resulting timing: " & to_string(res_time, 3) & CR & " deviation: " & to_string(res_time - Timing, 3) & " (" & str_format(res_dev, 2) & "%)" severity note; end if; return res_nat; end; function TimingToCycles(Timing : time; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural is begin return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle); end function; function CyclesToDelay(Cycles : natural; Clock_Period : time) return time is begin return Clock_Period * Cycles; end function; function CyclesToDelay(Cycles : natural; Clock_Frequency : FREQ) return time is begin return CyclesToDelay(Cycles, to_time(Clock_Frequency)); end function; -- convert and format physical types to STRING function to_string(t : time; precision : natural) return string is variable tt : time; variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin tt := abs t; if (tt < 1 ps) then unit(1 to 2) := "fs"; value := to_real(tt, 1 fs); elsif (tt < 1 ns) then unit(1 to 2) := "ps"; value := to_real(tt, 1 ps); elsif (tt < 1 us) then unit(1 to 2) := "ns"; value := to_real(tt, 1 ns); elsif (tt < 1 ms) then unit(1 to 2) := "us"; value := to_real(tt, 1 us); elsif (tt < 1 sec) then unit(1 to 2) := "ms"; value := to_real(tt, 1 ms); else unit := "sec"; value := to_real(tt, 1 sec); end if; return ite(t >= 0 fs, str_format(value, precision) & " " & str_trim(unit), '-' & str_format(value, precision) & " " & str_trim(unit)); end function; function to_string(f : FREQ; precision : natural) return string is variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin if (f < 1 kHz) then unit(1 to 2) := "Hz"; value := to_real(f, 1 Hz); elsif (f < 1 MHz) then unit := "kHz"; value := to_real(f, 1 kHz); elsif (f < 1 GHz) then unit := "MHz"; value := to_real(f, 1 MHz); else unit := "GHz"; value := to_real(f, 1 GHz); end if; return str_format(value, precision) & " " & str_trim(unit); end function; function to_string(br : BAUD; precision : natural) return string is variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin if (br < 1 kBd) then unit(1 to 2) := "Bd"; value := to_real(br, 1 Bd); elsif (br < 1 MBd) then unit := "kBd"; value := to_real(br, 1 kBd); elsif (br < 1 GBd) then unit := "MBd"; value := to_real(br, 1 MBd); else unit := "GBd"; value := to_real(br, 1 GBd); end if; return str_format(value, precision) & " " & str_trim(unit); end function; function to_string(mem : MEMORY; precision : natural) return string is variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin if (mem < 1 KiB) then unit(1) := 'B'; value := to_real(mem, 1 Byte); elsif (mem < 1 MiB) then unit := "KiB"; value := to_real(mem, 1 KiB); elsif (mem < 1 GiB) then unit := "MiB"; value := to_real(mem, 1 MiB); else unit := "GiB"; value := to_real(mem, 1 GiB); end if; return str_format(value, precision) & " " & str_trim(unit); end function; end package body;

agpl-3.0

eaa7433ac8ceef262a021cf9db4b2324

preusser/q27

src/vhdl/PoC/fifo/fifo_ic_got.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- =========================================================================== -- Module: FIFO, independent clocks (ic), first-word-fall-through mode -- -- Authors: Thomas B. Preusser -- Steffen Koehler -- Martin Zabel -- -- Description: -- ------------------------------------ -- Independent clocks meens that read and write clock are unrelated. -- -- This implementation uses dedicated block RAM for storing data. -- -- First-word-fall-through (FWFT) mode is implemented, so data can be read out -- as soon as 'valid' goes high. After the data has been captured, then the -- signal 'got' must be asserted. -- -- Synchronous reset is used. Both resets may overlap. -- -- DATA_REG (=true) is a hint, that distributed memory or registers should be -- used as data storage. The actual memory type depends on the device -- architecture. See implementation for details. -- -- *STATE_*_BITS defines the granularity of the fill state indicator -- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs -- the guaranteed number of words available in the FIFO. 'estate_wr' is -- associated with the write clock domain and outputs the number of words that -- is guaranteed to be accepted by the FIFO without a capacity overflow. Note -- that both these indicators cannot replace the 'full' or 'valid' outputs as -- they may be implemented as giving pessimistic bounds that are minimally off -- the true fill state. -- -- If a fill state is not of interest, set *STATE_*_BITS = 0. -- -- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address -- comparator (subtractor) in their path. -- -- Examples: -- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full -- fstate_rd == 1 => 1/2 full (half full) -- -- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full -- fstate_rd == 1 => 1/4 full -- fstate_rd == 2 => 2/4 full -- fstate_rd == 3 => 3/4 full -- -- License: -- =========================================================================== -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================================================================================================ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library poc; USE PoC.utils.ALL; use poc.ocram.all; -- "all" required by Quartus RTL simulation entity fifo_ic_got is generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Write Interface clk_wr : in std_logic; rst_wr : in std_logic; put : in std_logic; din : in std_logic_vector(D_BITS-1 downto 0); full : out std_logic; estate_wr : out std_logic_vector(imax(ESTATE_WR_BITS-1, 0) downto 0); -- Read Interface clk_rd : in std_logic; rst_rd : in std_logic; got : in std_logic; valid : out std_logic; dout : out std_logic_vector(D_BITS-1 downto 0); fstate_rd : out std_logic_vector(imax(FSTATE_RD_BITS-1, 0) downto 0) ); end fifo_ic_got; architecture rtl of fifo_ic_got is -- Constants constant A_BITS : positive := log2ceilnz(MIN_DEPTH); constant AN : positive := A_BITS + 1; -- Registers, clk_wr domain signal IP1 : std_logic_vector(AN-1 downto 0); -- IP + 1 signal IP0 : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Write Pointer IP signal IPz : std_logic_vector(AN-1 downto 0) := (others => '0'); -- IP delayed by one clock signal OPs : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Sync stage: OP0 -> OPc signal OPc : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Copy of OP signal Ful : std_logic := '0'; -- RAM full -- Registers, clk_rd domain signal OP1 : std_logic_vector(AN-1 downto 0); -- OP + 1 signal OP0 : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Read Pointer OP signal IPs : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Sync stage: IPz -> IPc signal IPc : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Copy of IP signal Avl : std_logic := '0'; -- RAM Data available signal Vld : std_logic := '0'; -- Output Valid -- Memory Connectivity signal wa : unsigned(A_BITS-1 downto 0); signal di : std_logic_vector(D_BITS-1 downto 0); signal puti : std_logic; signal ra : unsigned(A_BITS-1 downto 0); signal do : std_logic_vector(D_BITS-1 downto 0); signal geti : std_logic; signal goti : std_logic; -- Internal Read ACK begin ----------------------------------------------------------------------------- -- Write clock domain ----------------------------------------------------------------------------- blkIP: block signal Cnt : unsigned(AN-1 downto 0) := to_unsigned(1, AN); begin process(clk_wr) begin if rising_edge(clk_wr) then if rst_wr = '1' then Cnt <= to_unsigned(1, AN); elsif puti = '1' then Cnt <= Cnt + 1; end if; end if; end process; IP1 <= std_logic_vector(Cnt(A_BITS) & (Cnt(A_BITS-1 downto 0) xor ('0' & Cnt(A_BITS-1 downto 1)))); end block blkIP; -- Update Write Pointer upon puti process(clk_wr) begin if rising_edge(clk_wr) then if rst_wr = '1' then IP0 <= (others => '0'); IPz <= (others => '0'); OPs <= (others => '0'); OPc <= (others => '0'); Ful <= '0'; else IPz <= IP0; OPs <= OP0; OPc <= OPs; if puti = '1' then IP0 <= IP1; if IP1(A_BITS-1 downto 0) = OPc(A_BITS-1 downto 0) then Ful <= '1'; else Ful <= '0'; end if; end if; if Ful = '1' then if IP0 = (not OPc(A_BITS) & OPc(A_BITS-1 downto 0)) then Ful <= '1'; else Ful <= '0'; end if; end if; end if; end if; end process; puti <= put and not Ful; full <= Ful; di <= din; wa <= unsigned(IP0(A_BITS-1 downto 0)); ----------------------------------------------------------------------------- -- Read clock domain ----------------------------------------------------------------------------- blkOP: block signal Cnt : unsigned(AN-1 downto 0) := to_unsigned(1, AN); begin process(clk_rd) begin if rising_edge(clk_rd) then if rst_rd = '1' then Cnt <= to_unsigned(1, AN); elsif geti = '1' then Cnt <= Cnt + 1; end if; end if; end process; OP1 <= std_logic_vector(Cnt(A_BITS) & (Cnt(A_BITS-1 downto 0) xor ('0' & Cnt(A_BITS-1 downto 1)))); end block blkOP; process(clk_rd) begin if rising_edge(clk_rd) then if rst_rd = '1' then OP0 <= (others => '0'); IPs <= (others => '0'); IPc <= (others => '0'); Avl <= '0'; Vld <= '0'; else IPs <= IPz; IPc <= IPs; if geti = '1' then OP0 <= OP1; if OP1(A_BITS-1 downto 0) = IPc(A_BITS-1 downto 0) then Avl <= '0'; else Avl <= '1'; end if; Vld <= '1'; elsif goti = '1' then Vld <= '0'; end if; if Avl = '0' then if OP0 = IPc then Avl <= '0'; else Avl <= '1'; end if; end if; end if; end if; end process; geti <= (not Vld or goti) and Avl; ra <= unsigned(OP0(A_BITS-1 downto 0)); ----------------------------------------------------------------------------- -- Add register to data output -- -- Not needed if DATA_REG = true, because "dout" is already feed from a -- register in that case. ----------------------------------------------------------------------------- genRegN: if DATA_REG or not OUTPUT_REG generate goti <= got; dout <= do; valid <= Vld; end generate genRegN; genRegY: if (not DATA_REG) and OUTPUT_REG generate signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); signal VldB : std_logic := '0'; begin process(clk_rd) begin if rising_edge(clk_rd) then if rst_rd = '1' then Buf <= (others => '-'); VldB <= '0'; elsif goti = '1' then Buf <= do; VldB <= Vld; end if; end if; end process; goti <= not VldB or got; dout <= Buf; valid <= VldB; end generate genRegY; ----------------------------------------------------------------------------- -- Fill State ----------------------------------------------------------------------------- -- Write Clock Domain gEstateWr: if ESTATE_WR_BITS >= 1 generate signal d : unsigned(A_BITS-1 downto 0); begin d <= unsigned(gray2bin(OPc(A_BITS-1 downto 0))) + not unsigned(gray2bin(IP0(A_BITS-1 downto 0))); estate_wr <= (others => '0') when Ful = '1' else std_logic_vector(d(d'left downto d'left-ESTATE_WR_BITS+1)); end generate gEstateWr; gNoEstateWr: if ESTATE_WR_BITS = 0 generate estate_wr <= "X"; end generate gNoEstateWr; -- Read Clock Domain gFstateRd: if FSTATE_RD_BITS >= 1 generate signal d : unsigned(A_BITS-1 downto 0); begin d <= unsigned(gray2bin(IPc(A_BITS-1 downto 0))) + not unsigned(gray2bin(OP0(A_BITS-1 downto 0))); fstate_rd <= (others => '0') when Avl = '0' else std_logic_vector(d(d'left downto d'left-FSTATE_RD_BITS+1)); end generate gFstateRd; gNoFstateRd: if FSTATE_RD_BITS = 0 generate fstate_rd <= "X"; end generate gNoFstateRd; ----------------------------------------------------------------------------- -- Memory Instantiation ----------------------------------------------------------------------------- gLarge: if not DATA_REG generate ram : ocram_sdp generic map ( A_BITS => A_BITS, D_BITS => D_BITS ) port map ( wclk => clk_wr, rclk => clk_rd, wce => '1', rce => geti, we => puti, ra => ra, wa => wa, d => di, q => do ); end generate gLarge; gSmall: if DATA_REG generate -- Memory modelled as Array type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0); signal regfile : regfile_t; attribute ram_style : string; -- XST specific attribute ram_style of regfile : signal is "distributed"; -- Altera Quartus II: Allow automatic RAM type selection. -- For small RAMs, registers are used on Cyclone devices and the M512 type -- is used on Stratix devices. Pass-through logic is not required as -- reads do not occur on write addresses. -- Warning about undefined read-during-write behaviour can be ignored. attribute ramstyle : string; attribute ramstyle of regfile : signal is "no_rw_check"; begin -- Memory State process(clk_wr) begin if rising_edge(clk_wr) then --synthesis translate_off if SIMULATION AND (rst_wr = '1') then regfile <= (others => (others => '-')); else --synthesis translate_on if puti = '1' then regfile(to_integer(wa)) <= di; end if; --synthesis translate_off end if; --synthesis translate_on end if; end process; -- Memory Output process (clk_rd) begin -- process if rising_edge(clk_rd) then if SIMULATION and (rst_rd = '1') then do <= (others => 'U'); elsif geti = '1' then if Is_X(std_logic_vector(ra)) then do <= (others => 'X'); else do <= regfile(to_integer(ra)); end if; end if; end if; end process; end generate gSmall; end rtl;

agpl-3.0

759f4bb0d0f783d9dbb77939f797dd2d

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_max.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

cc60bc6fd7d36b1f70a787aa465677dd

berickson1/DE2-Adafruit-ZFM-20

Quartus/FingerprintSensorExample.vhd

-- ZFM-20 Fingerprint Sensor Example -- Top level system file library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.vital_primitives.all; use work.DE2_CONSTANTS.all; entity FingerprintSensorExample is port ( -- Reset and Clock KEY : in std_logic_vector (0 downto 0); CLOCK_50 : in std_logic; CLOCK_27 : in std_logic; -- Off Chip GPIO_1 : inout std_logic_vector(35 downto 0); -- SDRAM On Board DRAM_ADDR : out DE2_SDRAM_ADDR_BUS; DRAM_BA_0 : out std_logic; DRAM_BA_1 : out std_logic; DRAM_CAS_N : out std_logic; DRAM_CKE : out std_logic; DRAM_CLK : out std_logic; DRAM_CS_N : out std_logic; DRAM_DQ : inout DE2_SDRAM_DATA_BUS; DRAM_LDQM : out std_logic; DRAM_UDQM : out std_logic; DRAM_RAS_N : out std_logic; DRAM_WE_N : out std_logic; -- SRAM On Board SRAM_ADDR : out DE2_SRAM_ADDR_BUS; SRAM_DQ : inout DE2_SRAM_DATA_BUS; SRAM_WE_N : out std_logic; SRAM_OE_N : out std_logic; SRAM_UB_N : out std_logic; SRAM_LB_N : out std_logic; SRAM_CE_N : out std_logic; -- Flash memory FL_ADDR : out std_logic_vector (21 downto 0); FL_CE_N : out std_logic_vector (0 downto 0); FL_OE_N : out std_logic_vector (0 downto 0); FL_DQ : inout std_logic_vector (7 downto 0); FL_RST_N : out std_logic_vector (0 downto 0); FL_WE_N : out std_logic_vector (0 downto 0) ); end FingerprintSensorExample; architecture structure of FingerprintSensorExample is component nios_system is port ( clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n -- export altpll_0_c0_clk : out std_logic; -- clk serial_external_connection_rxd : in std_logic := 'X'; -- rxd serial_external_connection_txd : out std_logic; -- txd sdram_0_wire_addr : out std_logic_vector(11 downto 0); -- addr sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba sdram_0_wire_cas_n : out std_logic; -- cas_n sdram_0_wire_cke : out std_logic; -- cke sdram_0_wire_cs_n : out std_logic; -- cs_n sdram_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm sdram_0_wire_ras_n : out std_logic; -- ras_n sdram_0_wire_we_n : out std_logic; -- we_n tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0) -- generic_tristate_controller_0_tcm_address_out ); end component nios_system; -- signals to match provided IP core to specific SDRAM chip of our system signal BA : std_logic_vector (1 downto 0); signal DQM : std_logic_vector (1 downto 0); begin DRAM_BA_1 <= BA(1); DRAM_BA_0 <= BA(0); DRAM_UDQM <= DQM(1); DRAM_LDQM <= DQM(0); FL_RST_N <= "1"; u0 : component nios_system port map ( reset_reset_n => KEY(0), -- reset.reset_n altpll_0_c0_clk => DRAM_CLK, -- altpll_0_c0.clk serial_external_connection_rxd => GPIO_1(26), -- GREEN serial_external_connection.rxd serial_external_connection_txd => GPIO_1(28), -- WHITE .txd sdram_0_wire_addr => DRAM_ADDR, -- sdram_0_wire.addr sdram_0_wire_ba => BA, -- .ba sdram_0_wire_cas_n => DRAM_CAS_N, -- .cas_n sdram_0_wire_cke => DRAM_CKE, -- .cke sdram_0_wire_cs_n => DRAM_CS_N, -- .cs_n sdram_0_wire_dq => DRAM_DQ, -- .dq sdram_0_wire_dqm => DQM, -- .dqm sdram_0_wire_ras_n => DRAM_RAS_N, -- .ras_n sdram_0_wire_we_n => DRAM_WE_N, -- .we_n clk_clk => CLOCK_50, -- clk.clk tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out => FL_OE_N, -- tristate_conduit_bridge_0_out.generic_tristate_controller_0_tcm_read_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out => FL_DQ, -- .generic_tristate_controller_0_tcm_data_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out => FL_CE_N, -- .generic_tristate_controller_0_tcm_chipselect_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out => FL_WE_N, -- .generic_tristate_controller_0_tcm_write_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out => FL_ADDR -- .generic_tristate_controller_0_tcm_address_out ); end structure; library ieee; --DE2 Constants use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.vital_primitives.all; package DE2_CONSTANTS is subtype DE2_LCD_DATA_BUS is std_logic_vector(7 downto 0); subtype DE2_LED_GREEN is std_logic_vector(7 downto 0); subtype DE2_SRAM_ADDR_BUS is std_logic_vector(17 downto 0); subtype DE2_SRAM_DATA_BUS is std_logic_vector(15 downto 0); subtype DE2_SDRAM_ADDR_BUS is std_logic_vector(11 downto 0); subtype DE2_SDRAM_DATA_BUS is std_logic_vector(15 downto 0); end DE2_CONSTANTS;

gpl-2.0

ae6082d7cb2be1e7469caacfbd3c5070

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_max.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 1; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

b24c8695fe201313b2233ccfe679a25f

malkadi/FGPU

RTL/CV.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity CV is -- {{{ port( -- CU Scheduler signals instr : in std_logic_vector(DATA_W-1 downto 0); -- level 0. wf_indx, wf_indx_in_wg : in natural range 0 to N_WF_CU-1; -- level 0. phase : in unsigned(PHASE_W-1 downto 0); -- level 0. alu_en_divStack : in std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 2. -- RTM signals rdAddr_alu_en : out unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0'); -- level 2. rdData_alu_en : in std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 4. rtm_rdAddr : out unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); -- level 13. rtm_rdData : in unsigned(RTM_DATA_W-1 downto 0); -- level 15. -- gmem signals gmem_re, gmem_we : out std_logic := '0'; -- level 17. mem_op_type : out std_logic_vector(2 downto 0) := (others=>'0'); --level 17. mem_addr : out GMEM_ADDR_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- level 17. mem_rd_addr : out unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); -- level 17. mem_wrData : out SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); --level 17. alu_en : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 17. alu_en_pri_enc : out integer range 0 to CV_SIZE-1 := 0; -- level 17. lmem_rqst, lmem_we : out std_logic := '0'; -- level 17. gmem_atomic : out std_logic := '0'; -- level 17. --branch wf_is_branching : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); -- level 18. alu_branch : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 18. mem_regFile_wrAddr : in unsigned(REG_FILE_W-1 downto 0); -- stage -1 (stable for 3 clock cycles) mem_regFile_we : in std_logic_vector(CV_SIZE-1 downto 0); -- stage 0 (stable for 2 clock cycles) (level 20. for loads from lmem) mem_regFile_wrData : in SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- stage 0 (stabel for 2 clock cycles) lmem_regFile_we_p0 : in std_logic := '0'; -- level 19. clk : in std_logic ); attribute max_fanout of wf_indx : signal is 10; end CV; -- }}} architecture Behavioral of CV is -- signals definitions -------------------------------------------------------------------------------------- {{{ ----------------- RTM & Initial ALU enable type rtm_rdAddr_vec_type is array (natural range <>) of unsigned(RTM_ADDR_W-1 downto 0); signal rtm_rdAddr_vec : rtm_rdAddr_vec_type(9 downto 0) := (others=>(others=>'0')); signal rdData_alu_en_vec : alu_en_vec_type(MAX_FPU_DELAY+6 downto 0) := (others=>(others=>'0')); signal rtm_rdData_d0 : unsigned(RTM_DATA_W-1 downto 0); signal alu_en_divStack_vec : alu_en_vec_type(2 downto 0) := (others=>(others=>'0')); signal rdAddr_alu_en_p0 : unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0'); ----------------- global use signal phase_d0, phase_d1 : unsigned( PHASE_W-1 downto 0) := (others=>'0'); signal op_arith_shift, op_arith_shift_n : op_arith_shift_type := op_add; ------------------ decoding signal family : std_logic_vector(FAMILY_W-1 downto 0) := (others=>'0'); signal code : std_logic_vector(CODE_W-1 downto 0) := (others=>'0'); signal inst_rd_addr, inst_rs_addr : std_logic_vector(WI_REG_ADDR_W-1 downto 0) := (others=>'0'); signal inst_rt_addr : std_logic_vector(WI_REG_ADDR_W-1 downto 0) := (others=>'0'); type dim_vec_type is array (natural range <>) of std_logic_vector(1 downto 0); signal dim_vec : dim_vec_type(1 downto 0) := (others=>(others=>'0')); signal dim : std_logic_vector(1 downto 0) := (others=>'0'); type params_vec_type is array (natural range <>) of std_logic_vector(N_PARAMS_W-1 downto 0); signal params_vec : params_vec_type(1 downto 0) := (others=>(others=>'0')); signal params : std_logic_vector(N_PARAMS_W-1 downto 0) := (others=>'0'); type family_vec_type is array(natural range <>) of std_logic_vector(FAMILY_W-1 downto 0); signal family_vec : family_vec_type(MAX_FPU_DELAY+10 downto 0) := (others=>(others=>'0')); signal family_vec_at_16 : std_logic_vector(FAMILY_W-1 downto 0) := (others=>'0'); -- this signal is extracted out of family_vec to dcrease the fanout @family_vec(..@16) attribute max_fanout of family_vec_at_16: signal is 40; signal branch_on_zero : std_logic := '0'; signal branch_on_not_zero : std_logic := '0'; signal wf_is_branching_p0 : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal code_vec : code_vec_type(15 downto 0) := (others=>(others=>'0')); type immediate_vec_type is array(natural range <>) of std_logic_vector(IMM_W-1 downto 0); signal immediate_vec : immediate_vec_type(5 downto 0) := (others=>(others=>'0')); type wf_indx_array is array (natural range <>) of natural range 0 to N_WF_CU-1; signal wf_indx_vec : wf_indx_array(15 downto 0) := (others=>0); signal wf_indx_in_wg_vec : wf_indx_array(1 downto 0) := (others=>0); ------------------ register file signal rs_addr, rt_addr, rd_addr : unsigned(REG_FILE_BLOCK_W-1 downto 0) := (others=>'0'); type op_arith_shift_vec_type is array(natural range <>) of op_arith_shift_type; signal op_arith_shift_vec : op_arith_shift_vec_type(4 downto 0) := (others => op_add); signal op_logical_v : std_logic := '0'; signal regBlock_re : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0'); -- attribute max_fanout of regBlock_re : signal is 10; signal regBlocK_re_n : std_logic := '0'; signal reg_we_alu, reg_we_alu_n : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal reg_we_float : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal res_alu : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); type rd_out_vec_type is array (natural range <>) of slv32_array(CV_SIZE-1 downto 0); signal rd_out_vec : rd_out_vec_type(6 downto 0) := (others=>(others=>(others=>'0'))); ------------------ global memory signal gmem_re_p0, gmem_we_p0 : std_logic := '0'; signal gmem_ato_p0 : std_logic := '0'; -------------------------------------------------------------------------------------}}} -- write back into regFiles {{{ type regBlock_we_vec_type is array(natural range <>) of std_logic_vector(N_REG_BLOCKS-1 downto 0); signal regBlock_we : regBlock_we_vec_type(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal regBlock_we_alu : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0'); attribute max_fanout of regBlock_we_alu : signal is 50; signal regBlock_we_mem : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0'); signal wrAddr_regFile_vec : reg_addr_array(MAX_FPU_DELAY+12 downto 0) := (others=>(others=>'0')); signal regBlock_wrAddr : reg_file_block_array(N_REG_BLOCKS-1 downto 0) := (others=>(others=>'0')); signal wrData_alu : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); type regBlock_wrData_type is array(natural range <>) of slv32_array(N_REG_BLOCKS-1 downto 0); signal regBlock_wrData : regBlock_wrData_type(CV_SIZE-1 downto 0) := (others=>(others=>(others=>'0'))); signal rtm_rdData_nlid_vec : std_logic_vector(3 downto 0) := (others=>'0'); signal res_low : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal res_alu_clk2x_d0 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal res_high : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal reg_we_mov_vec : alu_en_vec_type(6 downto 0) := (others=>(others=>'0')); signal mem_regFile_wrAddr_d0 : unsigned(REG_FILE_W-1 downto 0); signal lmem_regFile_we : std_logic := '0'; -- }}} -- floating point {{{ signal float_a, float_b : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal res_float : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal res_float_d0 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal res_float_d1 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal regBlock_we_float_vec : regBlock_we_vec_type(MAX_FPU_DELAY-7 downto 0) := (others=>(others=>'0')); signal regBlock_we_float : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0'); attribute max_fanout of regBlock_we_float : signal is 50; -- }}} begin -- internal signals and asserts -------------------------------------------------------------------------{{{ ---------------------------------------------------------------------------------------------------------}}} -- RTM contorl & ALU enable -------------------------------------------------------------------- {{{ process(clk) begin if rising_edge(clk) then -- rtm {{{ rtm_rdData_d0 <= rtm_rdData; -- @ 16. if family_vec(family_vec'high-1) = RTM_FAMILY then -- level 2. case code_vec(code_vec'high-1) is -- level 2. when LID => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '0'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= unsigned(dim_vec(dim_vec'high-1)); --dimension rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= to_unsigned(wf_indx_in_wg_vec(wf_indx_in_wg_vec'high-1), N_WF_CU_W); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1 downto 0) <= phase_d1; when WGOFF => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= unsigned(dim_vec(dim_vec'high-1)); --dimension rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= to_unsigned(wf_indx_vec(wf_indx_vec'high-1), N_WF_CU_W); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1 downto 0) <= (others=>'0'); when SIZE => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= (others=>'1'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1) <= '0'; rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-2 downto 0) <= unsigned(dim_vec(dim_vec'high-1)); when WGID => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= (others=>'1'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1) <= '0'; rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-2 downto 0) <= unsigned(dim_vec(dim_vec'high-1)); when WGSIZE => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= (others=>'1'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1) <= '0'; rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-2 downto 0) <= unsigned(dim_vec(dim_vec'high-1)); when LP => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; --dimension rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto N_PARAMS_W) <= (others=>'0'); -- wf_indx is zero, except its LSB, rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_PARAMS_W-1 downto 0) <= unsigned(params_vec(params_vec'high-1)); -- @ 2. when others => end case; end if; rtm_rdAddr_vec(rtm_rdAddr_vec'high-1 downto 0) <= rtm_rdAddr_vec(rtm_rdAddr_vec'high downto 1); -- @ 4.->12. rtm_rdAddr <= rtm_rdAddr_vec(0); -- @ 13. rtm_rdData_nlid_vec(rtm_rdData_nlid_vec'high-1 downto 0) <= rtm_rdData_nlid_vec(rtm_rdData_nlid_vec'high downto 1); -- @ 14.->16. rtm_rdData_nlid_vec(rtm_rdData_nlid_vec'high) <= rtm_rdAddr_vec(0)(RTM_ADDR_W-1); -- @ 13. -- }}} -- ALU enable {{{ rdAddr_alu_en_p0(PHASE_W-1 downto 0) <= phase; --@ 1. rdAddr_alu_en_p0(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= to_unsigned(wf_indx_in_wg, N_WF_CU_W); --@ 1. rdAddr_alu_en <= rdAddr_alu_en_p0; -- @ 2. alu_en_divStack_vec(alu_en_divStack_vec'high) <= alu_en_divStack; -- @ 3. alu_en_divStack_vec(alu_en_divStack_vec'high-1 downto 0) <= alu_en_divStack_vec(alu_en_divStack_vec'high downto 1); -- @ 4.->5. rdData_alu_en_vec(rdData_alu_en_vec'high) <= rdData_alu_en; -- @ 5. rdData_alu_en_vec(rdData_alu_en_vec'high-1) <= rdData_alu_en_vec(rdData_alu_en_vec'high) and not alu_en_divStack_vec(0); -- @ 6. rdData_alu_en_vec(rdData_alu_en_vec'high-2 downto 0) <= rdData_alu_en_vec(rdData_alu_en_vec'high-1 downto 1); -- @ 7.->7+MAX_FPU_DELAY+4. -- for gmem operations alu_en <= rdData_alu_en_vec(rdData_alu_en_vec'high-11); -- @ 17. alu_en_pri_enc <= 0; -- @ 17. for i in CV_SIZE-1 downto 0 loop if rdData_alu_en_vec(rdData_alu_en_vec'high-11)(i) = '1' then -- level 16. alu_en_pri_enc <= i; -- @ 17. end if; end loop; -- }}} end if; end process; ----------------------------------------------------------------------------------------------}}} -- decoding logic --------------------------------------------------------------------{{{ family <= instr(FAMILY_POS+FAMILY_W-1 downto FAMILY_POS); -- alias code <= instr(CODE_POS+CODE_W-1 downto CODE_POS); -- alias inst_rd_addr <= instr(RD_POS+WI_REG_ADDR_W-1 downto RD_POS); -- alias inst_rs_addr <= instr(RS_POS+WI_REG_ADDR_W-1 downto RS_POS); -- alias inst_rt_addr <= instr(RT_POS+WI_REG_ADDR_W-1 downto RT_POS); -- alias dim <= instr(DIM_POS+1 downto DIM_POS); params <= instr(PARAM_POS+N_PARAMS_W-1 downto PARAM_POS); process(clk) begin if rising_edge(clk) then -- pipes {{{ family_vec(family_vec'high-1 downto 0) <= family_vec(family_vec'high downto 1); -- @ 2.->2+MAX_FPU_DELAY+9. family_vec(family_vec'high) <= family; -- @ 1. family_vec_at_16 <= family_vec(family_vec'high-14); -- @ 16. dim_vec(dim_vec'high-1 downto 0) <= dim_vec(dim_vec'high downto 1); -- @ 2 dim_vec(dim_vec'high) <= dim; -- @ 1. code_vec(code_vec'high-1 downto 0) <= code_vec(code_vec'high downto 1); -- @ 2.->16. code_vec(code_vec'high) <= code; -- @ 1. params_vec(params_vec'high-1 downto 0) <= params_vec(params_vec'high downto 1); -- @ 2.->2. params_vec(params_vec'high) <= params; -- @ 1. immediate_vec(immediate_vec'high-1 downto 0) <= immediate_vec(immediate_vec'high downto 1); -- @ 2.->6. immediate_vec(immediate_vec'high)(IMM_ARITH_W-1 downto 0) <= instr(IMM_POS+IMM_ARITH_W-1 downto IMM_POS); -- @ 1. immediate_vec(immediate_vec'high)(IMM_W-1 downto IMM_ARITH_W) <= instr(RS_POS+IMM_W-IMM_ARITH_W-1 downto RS_POS); -- @ 1. wf_indx_vec(wf_indx_vec'high-1 downto 0) <= wf_indx_vec(wf_indx_vec'high downto 1); -- @ 2.->16. wf_indx_vec(wf_indx_vec'high) <= wf_indx; -- @ 1. wf_indx_in_wg_vec(wf_indx_in_wg_vec'high-1 downto 0) <= wf_indx_in_wg_vec(wf_indx_in_wg_vec'high downto 1); -- @ 2.->2. wf_indx_in_wg_vec(wf_indx_in_wg_vec'high) <= wf_indx_in_wg; -- @ 1. regBlock_re(0) <= regBlock_re_n; -- @ 1. regBlock_re(regBlock_re'high downto 1) <= regBlock_re(regBlock_re'high-1 downto 0); -- @ 2.->4. op_arith_shift <= op_arith_shift_n; -- @ 1. op_arith_shift_vec(op_arith_shift_vec'high-1 downto 0) <= op_arith_shift_vec(op_arith_shift_vec'high downto 1); -- @ 3.->6. op_arith_shift_vec(op_arith_shift_vec'high) <= op_arith_shift; -- @ 2. phase_d0 <= phase; -- @ 1. phase_d1 <= phase_d0; -- @ 2. -- }}} -- Rs, Rt & Rd addresses {{{ rs_addr(REG_FILE_BLOCK_W-1) <= phase(PHASE_W-1); -- @1. rs_addr(WI_REG_ADDR_W+N_WF_CU_W-1 downto WI_REG_ADDR_W) <= to_unsigned(wf_indx, N_WF_CU_W); -- @1. if family = ADD_FAMILY and code(3) = '1'then -- level 0. rs_addr(WI_REG_ADDR_W-1 downto 0) <= (others=>'0'); -- @1. -- for li & lui else rs_addr(WI_REG_ADDR_W-1 downto 0) <= unsigned(inst_rs_addr); -- @1. end if; rt_addr(REG_FILE_BLOCK_W-1) <= phase(PHASE_W-1); -- @1. rt_addr(WI_REG_ADDR_W+N_WF_CU_W-1 downto WI_REG_ADDR_W) <= to_unsigned(wf_indx, N_WF_CU_W); -- @1. rt_addr(WI_REG_ADDR_W-1 downto 0) <= unsigned(inst_rt_addr); -- @1. rd_addr <= wrAddr_regFile_vec(wrAddr_regFile_vec'high)(REG_FILE_BLOCK_W-1 downto 0); -- @1. -- }}} -- set operation type {{{ op_logical_v <= '0'; -- @ 14. if family_vec(family_vec'high-12) = LGK_FAMILY then -- level 13. op_logical_v <= '1'; -- @ 14. end if; -- }}} end if; end process; -- memory accesses {{{ process(clk) begin if rising_edge(clk) then -- pipes {{{ rd_out_vec(rd_out_vec'high-1 downto 0) <= rd_out_vec(rd_out_vec'high downto 1); -- @ 11.->16. -- }}} -- @ 16 {{{ gmem_re_p0 <= '0'; -- @ 16. gmem_we_p0 <= '0'; -- @ 16. if family_vec(family_vec'high-14) = GLS_FAMILY then -- level 15. if code_vec(1)(3) = '1' then -- level 15. gmem_re_p0 <= '0'; -- store @ 16. gmem_we_p0 <= '1'; else gmem_re_p0 <= '1'; -- load @ 16. gmem_we_p0 <= '0'; end if; end if; if ATOMIC_IMPLEMENT /= 0 then gmem_ato_p0 <= '0'; if family_vec(family_vec'high-14) = ATO_FAMILY then -- level 15. gmem_ato_p0 <= '1'; -- @ 16. end if; end if; -- }}} -- @ 17 {{{ gmem_we <= gmem_we_p0; -- @ 17. gmem_re <= gmem_re_p0; -- @ 17. if ATOMIC_IMPLEMENT /= 0 then gmem_atomic <= gmem_ato_p0; -- @ 17. end if; if LMEM_IMPLEMENT /= 0 then lmem_rqst <= '0'; -- @ 17. lmem_we <= '0'; -- @ 17. if family_vec(family_vec'high-15) = LSI_FAMILY then -- level 16. lmem_rqst <= '1'; -- @ 17. if code_vec(0)(3) = '1' then -- level 16. lmem_we <= '1'; -- @ 17. else lmem_we <= '0'; -- @ 17. end if; end if; end if; mem_wrData <= rd_out_vec(0); -- @ 17. mem_rd_addr <= wrAddr_regFile_vec(wrAddr_regFile_vec'high-16); -- @ 17. for i in 0 to CV_SIZE-1 loop mem_addr(i) <= unsigned(res_low(i)(GMEM_ADDR_W-1 downto 0)); -- @ 17. end loop; mem_op_type <= code_vec(0)(2 downto 0); -- @ 17. -- }}} end if; end process; -- }}} ------------------------------------------------------------------------------------------------}}} -- ALUs ----------------------------------------------------------------------------------------- {{{ ALUs: for i in 0 to CV_SIZE-1 generate begin -- the calculation begins @ level 3 in the pipeline alu_inst: entity ALU port map( rs_addr => rs_addr, --level 1. rt_addr => rt_addr, -- level 1. rd_addr => rd_addr, -- level 1. family => family_vec(family_vec'high), -- level 1. regBlock_re => regBlock_re, -- level 1. op_arith_shift => op_arith_shift_vec(0), -- level 6. code => code_vec(code_vec'high-5), -- level 6. immediate => immediate_vec(0), -- level 6. rd_out => rd_out_vec(rd_out_vec'high)(i), -- level 10. reg_we_mov => reg_we_mov_vec(reg_we_mov_vec'high)(i), -- level 10. float_a => float_a(i), -- level 9. float_b => float_b(i), -- level 9. op_logical_v => op_logical_v, -- level 14. res_low => res_low(i), -- level 16. res_high => res_high(i), -- level 16. reg_wrData => regBlock_wrData(i), -- level 18. (level 21. for loads from lmem) (level 24. for float results) reg_wrAddr => regBlock_wrAddr, -- level 18. (level 21. for loads from lmem) (level 24. for float results) reg_we => regBlock_we(i), -- level 18. (level 21. for loads from lmem) (level 24. for float results) clk => clk ); end generate; -- set register files read enables {{{ set_register_re:process(phase(0), family) -- this process executes in level 0. begin regBlock_re_n <= '0'; -- level 0. case family is -- level 0. when ADD_FAMILY | MUL_FAMILY | BRA_FAMILY | SHF_FAMILY | LGK_FAMILY | CND_FAMILY | MOV_FAMILY | LSI_FAMILY | FLT_FAMILY | GLS_FAMILY | ATO_FAMILY=> if phase(PHASE_W-2 downto 0) = (0 to PHASE_W-2=>'0') then -- phase = 0 or 4 regBlock_re_n <= '1'; end if; when others => end case; -- }}} -- set opertion type {{{ op_arith_shift_n <= op_add; -- level 0. case family is -- level 0. when ADD_FAMILY => op_arith_shift_n <= op_add; when MUL_FAMILY => op_arith_shift_n <= op_mult; when GLS_FAMILY => op_arith_shift_n <= op_lw; when LSI_FAMILY => op_arith_shift_n <= op_lmem; when ATO_FAMILY => op_arith_shift_n <= op_ato; when BRA_FAMILY => op_arith_shift_n <= op_bra; when SHF_FAMILY => op_arith_shift_n <= op_shift; when CND_FAMILY => op_arith_shift_n <= op_slt; when MOV_FAMILY => op_arith_shift_n <= op_mov; when others => end case; end process; -- }}} ---------------------------------------------------------------------------------------}}} -- floating point ---------------------------------------------------------------------------------------{{{ float_units_inst: if FLOAT_IMPLEMENT /= 0 generate float_inst: entity float_units port map( float_a => float_a, -- level 9. float_b => float_b, -- level 9. fsub => code_vec(7)(CODE_W-1), -- level 9. code => code_vec(0), -- level 16. res_float => res_float, -- level MAX_FPU_DELAY+10. (38 if fdiv, 21 if fadd) clk => clk ); process(clk) begin if rising_edge(clk) then res_float_d0 <= res_float; -- @ MAX_FPU_DELAY+11 (39 if fdiv, 22 if fadd) res_float_d1 <= res_float_d0; -- @ MAX_FPU_DELAY+12 (40 if fdiv, 23 if fadd) -- float_ce <= '0'; -- for i in 0 to N_REG_BLOCKS-1 loop -- if regBlock_re_vec(1)(i) = '1' then -- float_ce <= '1'; -- end if; -- end loop; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- branch control ---------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then -- @ 17 {{{ res_alu <= res_low; -- @ 17. branch_on_zero <= '0'; -- @ 17. branch_on_not_zero <= '0'; -- @ 17. wf_is_branching_p0 <= (others=>'0'); if family_vec(family_vec'high-15) = BRA_FAMILY then -- level 16. wf_is_branching_p0(wf_indx_vec(0)) <= '1'; -- @ 17. case code_vec(0) is -- level 16. when BEQ => branch_on_zero <= '1'; -- @ 17. when BNE => branch_on_not_zero <= '1'; -- @ 17. when others=> end case; end if; -- }}} -- @ 18 {{{ wf_is_branching <= wf_is_branching_p0; -- @ 18. alu_branch <= (others=>'0'); -- @ 18. for i in 0 to CV_SIZE-1 loop if res_alu(i) = (res_alu(i)'reverse_range=>'0') then -- level 17. if branch_on_zero = '1' then -- level 17. alu_branch(i) <= '1'; -- @ 18. end if; else if branch_on_not_zero = '1' then -- level 17. alu_branch(i) <= '1'; -- @ 18. end if; end if; end loop; -- }}} end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- write back into regFiles ----------------------------------------------------------------------------------{{{ -- register file ----------------------------------------------------------------------- -- bits 10:9 8 7:5 4:0 -- phase(1:0) phase(2) wf_indx instr_rd_addr wrAddr_regFile_vec(wrAddr_regFile_vec'high)(REG_FILE_W-1 downto REG_FILE_W-2) <= phase(1 downto 0); -- level 0. wrAddr_regFile_vec(wrAddr_regFile_vec'high)(REG_FILE_W-3) <= phase(PHASE_W-1); -- level 0. wrAddr_regFile_vec(wrAddr_regFile_vec'high)(WI_REG_ADDR_W+N_WF_CU_W-1 downto WI_REG_ADDR_W) <= to_unsigned(wf_indx, N_WF_CU_W); -- level 0. wrAddr_regFile_vec(wrAddr_regFile_vec'high)(WI_REG_ADDR_W-1 downto 0) <= unsigned(inst_rd_addr); -- level 0. write_alu_res_back: process(family_vec(family_vec'high-15), rdData_alu_en_vec(rdData_alu_en_vec'high-11), reg_we_mov_vec(0)) begin reg_we_alu_n <= (others=>'0'); -- level 16. case family_vec(family_vec'high-15) is -- level 16. when RTM_FAMILY | ADD_FAMILY | MUL_FAMILY | SHF_FAMILY | LGK_FAMILY | CND_FAMILY => reg_we_alu_n <= rdData_alu_en_vec(rdData_alu_en_vec'high-11); -- level 16. when MOV_FAMILY => reg_we_alu_n <= rdData_alu_en_vec(rdData_alu_en_vec'high-11) and reg_we_mov_vec(0); -- level 16. when others=> end case; end process; process(clk) begin if rising_edge(clk) then wrAddr_regFile_vec(wrAddr_regFile_vec'high-1 downto 0) <= wrAddr_regFile_vec(wrAddr_regFile_vec'high downto 1); -- @ 1.->MAX_FPU_DELAY+12. reg_we_mov_vec(reg_we_mov_vec'high-1 downto 0) <= reg_we_mov_vec(reg_we_mov_vec'high downto 1); -- @ 11.->16. lmem_regFile_we <= lmem_regFile_we_p0; reg_we_alu <= reg_we_alu_n; -- @ 17. reg_we_float <= (others=>'0'); -- @ 23. case MAX_FPU_DELAY is when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay if family_vec(1) = FLT_FAMILY then -- level 38. if fdiv reg_we_float <= rdData_alu_en_vec(1); -- @ 39. if fdiv end if; when others => -- fadd has the maximum delay if family_vec(0) = FLT_FAMILY then -- level 22. if fadd reg_we_float <= rdData_alu_en_vec(0); -- @ 23. if fadd end if; end case; wrData_alu <= (others=>(others=>'0')); -- @ 17. case family_vec_at_16 is -- level 16. when RTM_FAMILY => if rtm_rdData_nlid_vec(0) = '0' then -- level 16. for i in 0 to CV_SIZE-1 loop wrData_alu(i)(WG_SIZE_W-1 downto 0) <= std_logic_vector(rtm_rdData_d0((i+1)*WG_SIZE_W-1 downto i*WG_SIZE_W)); -- @ 17. end loop; else for i in 0 to CV_SIZE-1 loop wrData_alu(i) <= std_logic_vector(rtm_rdData_d0(DATA_W-1 downto 0)); -- @ 17. end loop; end if; when ADD_FAMILY | MUL_FAMILY | CND_FAMILY | MOV_FAMILY => wrData_alu <= res_low; -- @ 17. when SHF_FAMILY => if code_vec(0)(CODE_W-1) = '0' then -- level 16. wrData_alu <= res_low; -- @ 17. else wrData_alu <= res_high; end if; when LGK_FAMILY => wrData_alu <= res_low; -- @ 17. when GLS_FAMILY => when others => end case; regBlock_we_alu <= (others=>'0'); -- @ 17. regBlock_we_alu(to_integer(wrAddr_regFile_vec(wrAddr_regFile_vec'high-16)(REG_FILE_W-1 downto REG_FILE_BLOCK_W))) <= '1'; -- @ 17.+N_REG_BLOCKS*i -- regBlock_we_float {{{ regBlock_we_float_vec(regBlock_we_float_vec'high) <= regBlock_we_alu; -- @ 18.+N_REG_BLOCKS*i regBlock_we_float_vec(regBlock_we_float_vec'high-1 downto 0) <= regBlock_we_float_vec(regBlock_we_float_vec'high downto 1); -- @ 19.->19+MAX_FPU_DELAY-7-1 (39. if fdiv, 22. if fadd) case MAX_FPU_DELAY is when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay regBlock_we_float <= regBlock_we_float_vec(1); -- @ MAX_FPU_DELAY+11 (39. if fadd) when others => -- fadd has the maximum delay regBlock_we_float <= regBlock_we_float_vec(0); -- @ MAX_FPU_DELAY+12 (23. if fadd) end case; -- }}} -- the register block that will be written from global and local memory reads will be selected {{{ if LMEM_IMPLEMENT = 0 or lmem_regFile_we_p0 = '0' then -- if no read of lmem content is comming, prepare the we of the register block according to the current address sent from CU_mem_cntrl regBlock_we_mem <= (others=>'0'); -- stage 0 regBlock_we_mem(to_integer(mem_regFile_wrAddr(REG_FILE_W-1 downto REG_FILE_BLOCK_W))) <= '1'; -- (@ 22. for lmem reads) elsif lmem_regFile_we = '0' or regBlock_we_mem(N_REG_BLOCKS-1) = '1' then -- there will be a read from lmem or a half of the read data burst is over. Set the we of the first register block! regBlock_we_mem(N_REG_BLOCKS-1 downto 1) <= (others=>'0'); -- stage 0 regBlock_we_mem(0) <= '1'; else -- lmem is being read. Shift left for regBlock_we_mem! regBlock_we_mem(N_REG_BLOCKS-1 downto 1) <= regBlock_we_mem(N_REG_BLOCKS-2 downto 0); regBlock_we_mem(0) <= '0'; end if; mem_regFile_wrAddr_d0 <= mem_regFile_wrAddr; -- stage 1 -- }}} -- regBlock_wrAddr {{{ for j in 0 to N_REG_BLOCKS-1 loop if regBlock_we_alu(j) = '1' then -- level 17.+j regBlock_wrAddr(j) <= wrAddr_regFile_vec(wrAddr_regFile_vec'high-17)(REG_FILE_BLOCK_W-1 downto 0); -- @ 18.+j elsif FLOAT_IMPLEMENT /= 0 and regBlock_we_float(j) = '1' then -- level 23.+j if add, 39.+j if fdiv case MAX_FPU_DELAY is when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay regBlock_wrAddr(j) <= wrAddr_regFile_vec(1)(REG_FILE_BLOCK_W-1 downto 0); -- @ 40.+j if fdiv when others => -- fadd has the maximum delay regBlock_wrAddr(j) <= wrAddr_regFile_vec(0)(REG_FILE_BLOCK_W-1 downto 0); -- @ 24.+j if fadd end case; else regBlock_wrAddr(j) <= mem_regFile_wrAddr(REG_FILE_BLOCK_W-1 downto 0); -- stage 1. or 2. end if; end loop; -- }}} for i in 0 to CV_SIZE-1 loop for j in 0 to N_REG_BLOCKS-1 loop -- regBlock_wrData {{{ if regBlock_we_alu(j) = '1' then -- level 17. -- write by alu operations regBlock_wrData(i)(j) <= wrData_alu(i); -- @ 18. elsif FLOAT_IMPLEMENT /= 0 and regBlock_we_float(j) = '1' then -- level 23. if fadd, 39. if fdiv -- write by floating point units case MAX_FPU_DELAY is when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay regBlock_wrData(i)(j) <= res_float_d0(i); -- @ 40.+j when others => -- fadd has the maximum delay regBlock_wrData(i)(j) <= res_float_d1(i); -- @ 24.+j end case; else -- write by memory reads regBlock_wrData(i)(j) <= mem_regFile_wrData(i); -- @ 1. or 2. end if; -- }}} -- regBlock_we {{{ if regBlock_we_alu(j) = '1' then -- level 17.+j regBlock_we(i)(j) <= reg_we_alu(i); -- @ 18.+j elsif FLOAT_IMPLEMENT /= 0 and regBlock_we_float(j) = '1' then -- level 23.+j if fadd, 39.+j uf fdiv regBlock_we(i)(j) <= reg_we_float(i); -- @ 24.+j if fadd, 40.+j if fdiv elsif regBlock_we_mem(j) = '1' then -- (level 22 for lmem reads; no conflict with 17+N_REG_BLOCKS*i) regBlock_we(i)(j) <= mem_regFile_we(i); -- @ 1. or 2. (@23. for loads from lmem) else regBlock_we(i)(j) <= '0'; end if; -- }}} end loop; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} end Behavioral;

gpl-3.0

149a9f52f207b9b109053da08d7ca52b

malkadi/FGPU

HW/sources/IPs/FGPU_3.0/hdl/FGPU_v3_0.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; library xil_defaultlib; use xil_defaultlib.all; ------------------------------------------------------------------------------------------------- }}} entity FGPU_v3_0 is -- generics {{{ generic ( -- Users to add parameters here -- User parameters ends -- Do not modify the parameters beyond this line -- Parameters of Axi Slave Bus Interface S0 C_S0_DATA_WIDTH : integer := 32; C_S0_ADDR_WIDTH : integer := 16; -- Parameters of Axi Master Bus Interface M0 C_M0_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M0_BURST_LEN : integer := 8; C_M0_ID_WIDTH : integer := 6; C_M0_ADDR_WIDTH : integer := 32; C_M0_DATA_WIDTH : integer := 64; C_M0_AWUSER_WIDTH : integer := 0; C_M0_ARUSER_WIDTH : integer := 0; C_M0_WUSER_WIDTH : integer := 0; C_M0_RUSER_WIDTH : integer := 0; C_M0_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M1 C_M1_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M1_BURST_LEN : integer := 8; C_M1_ID_WIDTH : integer := 6; C_M1_ADDR_WIDTH : integer := 32; C_M1_DATA_WIDTH : integer := 64; C_M1_AWUSER_WIDTH : integer := 0; C_M1_ARUSER_WIDTH : integer := 0; C_M1_WUSER_WIDTH : integer := 0; C_M1_RUSER_WIDTH : integer := 0; C_M1_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M2 C_M2_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M2_BURST_LEN : integer := 8; C_M2_ID_WIDTH : integer := 6; C_M2_ADDR_WIDTH : integer := 32; C_M2_DATA_WIDTH : integer := 64; C_M2_AWUSER_WIDTH : integer := 0; C_M2_ARUSER_WIDTH : integer := 0; C_M2_WUSER_WIDTH : integer := 0; C_M2_RUSER_WIDTH : integer := 0; C_M2_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M3 C_M3_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M3_BURST_LEN : integer := 8; C_M3_ID_WIDTH : integer := 6; C_M3_ADDR_WIDTH : integer := 32; C_M3_DATA_WIDTH : integer := 64; C_M3_AWUSER_WIDTH : integer := 0; C_M3_ARUSER_WIDTH : integer := 0; C_M3_WUSER_WIDTH : integer := 0; C_M3_RUSER_WIDTH : integer := 0; C_M3_BUSER_WIDTH : integer := 0 ); --}}} -- ports {{{ port ( -- Users to add ports here -- User ports ends -- Do not modify the ports beyond this line -- Ports of Axi Slave Bus Interface S0 {{{ s0_aclk : in std_logic; s0_aresetn : in std_logic; s0_awaddr : in std_logic_vector(C_S0_ADDR_WIDTH-1 downto 0); s0_awprot : in std_logic_vector(2 downto 0); s0_awvalid : in std_logic; s0_awready : out std_logic; s0_wdata : in std_logic_vector(C_S0_DATA_WIDTH-1 downto 0); s0_wstrb : in std_logic_vector((C_S0_DATA_WIDTH/8)-1 downto 0); s0_wvalid : in std_logic; s0_wready : out std_logic; s0_bresp : out std_logic_vector(1 downto 0); s0_bvalid : out std_logic; s0_bready : in std_logic; s0_araddr : in std_logic_vector(C_S0_ADDR_WIDTH-1 downto 0); s0_arprot : in std_logic_vector(2 downto 0); s0_arvalid : in std_logic; s0_arready : out std_logic; s0_rdata : out std_logic_vector(C_S0_DATA_WIDTH-1 downto 0); s0_rresp : out std_logic_vector(1 downto 0); s0_rvalid : out std_logic; s0_rready : in std_logic; -- }}} -- Ports of Axi Master Bus Interface M0 {{{ m0_aclk : in std_logic; m0_aresetn : in std_logic; m0_awid : out std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_awaddr : out std_logic_vector(C_M0_ADDR_WIDTH-1 downto 0); m0_awlen : out std_logic_vector(7 downto 0); m0_awsize : out std_logic_vector(2 downto 0); m0_awburst : out std_logic_vector(1 downto 0); m0_awlock : out std_logic; m0_awcache : out std_logic_vector(3 downto 0); m0_awprot : out std_logic_vector(2 downto 0); m0_awqos : out std_logic_vector(3 downto 0); m0_awuser : out std_logic_vector(C_M0_AWUSER_WIDTH-1 downto 0); m0_awvalid : out std_logic; m0_awready : in std_logic; m0_wdata : out std_logic_vector(C_M0_DATA_WIDTH-1 downto 0); m0_wstrb : out std_logic_vector(C_M0_DATA_WIDTH/8-1 downto 0); m0_wlast : out std_logic; m0_wuser : out std_logic_vector(C_M0_WUSER_WIDTH-1 downto 0); m0_wvalid : out std_logic; m0_wready : in std_logic; m0_bid : in std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_bresp : in std_logic_vector(1 downto 0); m0_buser : in std_logic_vector(C_M0_BUSER_WIDTH-1 downto 0); m0_bvalid : in std_logic; m0_bready : out std_logic; m0_arid : out std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_araddr : out std_logic_vector(C_M0_ADDR_WIDTH-1 downto 0); m0_arlen : out std_logic_vector(7 downto 0); m0_arsize : out std_logic_vector(2 downto 0); m0_arburst : out std_logic_vector(1 downto 0); m0_arlock : out std_logic; m0_arcache : out std_logic_vector(3 downto 0); m0_arprot : out std_logic_vector(2 downto 0); m0_arqos : out std_logic_vector(3 downto 0); m0_aruser : out std_logic_vector(C_M0_ARUSER_WIDTH-1 downto 0); m0_arvalid : out std_logic; m0_arready : in std_logic; m0_rid : in std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_rdata : in std_logic_vector(C_M0_DATA_WIDTH-1 downto 0); m0_rresp : in std_logic_vector(1 downto 0); m0_rlast : in std_logic; m0_ruser : in std_logic_vector(C_M0_RUSER_WIDTH-1 downto 0); m0_rvalid : in std_logic; m0_rready : out std_logic; --}}} -- Ports of Axi Master Bus Interface M1 {{{ m1_aclk : in std_logic; m1_aresetn : in std_logic; m1_awid : out std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_awaddr : out std_logic_vector(C_M1_ADDR_WIDTH-1 downto 0); m1_awlen : out std_logic_vector(7 downto 0); m1_awsize : out std_logic_vector(2 downto 0); m1_awburst : out std_logic_vector(1 downto 0); m1_awlock : out std_logic; m1_awcache : out std_logic_vector(3 downto 0); m1_awprot : out std_logic_vector(2 downto 0); m1_awqos : out std_logic_vector(3 downto 0); m1_awuser : out std_logic_vector(C_M1_AWUSER_WIDTH-1 downto 0); m1_awvalid : out std_logic; m1_awready : in std_logic; m1_wdata : out std_logic_vector(C_M1_DATA_WIDTH-1 downto 0); m1_wstrb : out std_logic_vector(C_M1_DATA_WIDTH/8-1 downto 0); m1_wlast : out std_logic; m1_wuser : out std_logic_vector(C_M1_WUSER_WIDTH-1 downto 0); m1_wvalid : out std_logic; m1_wready : in std_logic; m1_bid : in std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_bresp : in std_logic_vector(1 downto 0); m1_buser : in std_logic_vector(C_M1_BUSER_WIDTH-1 downto 0); m1_bvalid : in std_logic; m1_bready : out std_logic; m1_arid : out std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_araddr : out std_logic_vector(C_M1_ADDR_WIDTH-1 downto 0); m1_arlen : out std_logic_vector(7 downto 0); m1_arsize : out std_logic_vector(2 downto 0); m1_arburst : out std_logic_vector(1 downto 0); m1_arlock : out std_logic; m1_arcache : out std_logic_vector(3 downto 0); m1_arprot : out std_logic_vector(2 downto 0); m1_arqos : out std_logic_vector(3 downto 0); m1_aruser : out std_logic_vector(C_M1_ARUSER_WIDTH-1 downto 0); m1_arvalid : out std_logic; m1_arready : in std_logic; m1_rid : in std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_rdata : in std_logic_vector(C_M1_DATA_WIDTH-1 downto 0); m1_rresp : in std_logic_vector(1 downto 0); m1_rlast : in std_logic; m1_ruser : in std_logic_vector(C_M1_RUSER_WIDTH-1 downto 0); m1_rvalid : in std_logic; m1_rready : out std_logic; -- }}} -- Ports of Axi Master Bus Interface M2 {{{ m2_aclk : in std_logic; m2_aresetn : in std_logic; m2_awid : out std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_awaddr : out std_logic_vector(C_M2_ADDR_WIDTH-1 downto 0); m2_awlen : out std_logic_vector(7 downto 0); m2_awsize : out std_logic_vector(2 downto 0); m2_awburst : out std_logic_vector(1 downto 0); m2_awlock : out std_logic; m2_awcache : out std_logic_vector(3 downto 0); m2_awprot : out std_logic_vector(2 downto 0); m2_awqos : out std_logic_vector(3 downto 0); m2_awuser : out std_logic_vector(C_M2_AWUSER_WIDTH-1 downto 0); m2_awvalid : out std_logic; m2_awready : in std_logic; m2_wdata : out std_logic_vector(C_M2_DATA_WIDTH-1 downto 0); m2_wstrb : out std_logic_vector(C_M2_DATA_WIDTH/8-1 downto 0); m2_wlast : out std_logic; m2_wuser : out std_logic_vector(C_M2_WUSER_WIDTH-1 downto 0); m2_wvalid : out std_logic; m2_wready : in std_logic; m2_bid : in std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_bresp : in std_logic_vector(1 downto 0); m2_buser : in std_logic_vector(C_M2_BUSER_WIDTH-1 downto 0); m2_bvalid : in std_logic; m2_bready : out std_logic; m2_arid : out std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_araddr : out std_logic_vector(C_M2_ADDR_WIDTH-1 downto 0); m2_arlen : out std_logic_vector(7 downto 0); m2_arsize : out std_logic_vector(2 downto 0); m2_arburst : out std_logic_vector(1 downto 0); m2_arlock : out std_logic; m2_arcache : out std_logic_vector(3 downto 0); m2_arprot : out std_logic_vector(2 downto 0); m2_arqos : out std_logic_vector(3 downto 0); m2_aruser : out std_logic_vector(C_M2_ARUSER_WIDTH-1 downto 0); m2_arvalid : out std_logic; m2_arready : in std_logic; m2_rid : in std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_rdata : in std_logic_vector(C_M2_DATA_WIDTH-1 downto 0); m2_rresp : in std_logic_vector(1 downto 0); m2_rlast : in std_logic; m2_ruser : in std_logic_vector(C_M2_RUSER_WIDTH-1 downto 0); m2_rvalid : in std_logic; m2_rready : out std_logic; -- }}} -- Ports of Axi Master Bus Interface M3 {{{ m3_aclk : in std_logic; m3_aresetn : in std_logic; m3_awid : out std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_awaddr : out std_logic_vector(C_M3_ADDR_WIDTH-1 downto 0); m3_awlen : out std_logic_vector(7 downto 0); m3_awsize : out std_logic_vector(2 downto 0); m3_awburst : out std_logic_vector(1 downto 0); m3_awlock : out std_logic; m3_awcache : out std_logic_vector(3 downto 0); m3_awprot : out std_logic_vector(2 downto 0); m3_awqos : out std_logic_vector(3 downto 0); m3_awuser : out std_logic_vector(C_M3_AWUSER_WIDTH-1 downto 0); m3_awvalid : out std_logic; m3_awready : in std_logic; m3_wdata : out std_logic_vector(C_M3_DATA_WIDTH-1 downto 0); m3_wstrb : out std_logic_vector(C_M3_DATA_WIDTH/8-1 downto 0); m3_wlast : out std_logic; m3_wuser : out std_logic_vector(C_M3_WUSER_WIDTH-1 downto 0); m3_wvalid : out std_logic; m3_wready : in std_logic; m3_bid : in std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_bresp : in std_logic_vector(1 downto 0); m3_buser : in std_logic_vector(C_M3_BUSER_WIDTH-1 downto 0); m3_bvalid : in std_logic; m3_bready : out std_logic; m3_arid : out std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_araddr : out std_logic_vector(C_M3_ADDR_WIDTH-1 downto 0); m3_arlen : out std_logic_vector(7 downto 0); m3_arsize : out std_logic_vector(2 downto 0); m3_arburst : out std_logic_vector(1 downto 0); m3_arlock : out std_logic; m3_arcache : out std_logic_vector(3 downto 0); m3_arprot : out std_logic_vector(2 downto 0); m3_arqos : out std_logic_vector(3 downto 0); m3_aruser : out std_logic_vector(C_M3_ARUSER_WIDTH-1 downto 0); m3_arvalid : out std_logic; m3_arready : in std_logic; m3_rid : in std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_rdata : in std_logic_vector(C_M3_DATA_WIDTH-1 downto 0); m3_rresp : in std_logic_vector(1 downto 0); m3_rlast : in std_logic; m3_ruser : in std_logic_vector(C_M3_RUSER_WIDTH-1 downto 0); m3_rvalid : in std_logic; m3_rready : out std_logic -- }}} ); --}}} end entity; architecture arch_imp of FGPU_v3_0 is signal nrst : std_logic := '0'; begin -- fixed signals ------------------------------------------------------------------------------------{{{ -- m0 {{{ m0_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m0_awcache <= "0010"; m0_awprot <= "000"; m0_awqos <= X"0"; m0_arlock <= '0'; m0_arcache <= "0010"; m0_arprot <= "000"; m0_arqos <= X"0"; -- }}} -- m1 {{{ m1_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m1_awcache <= "0010"; m1_awprot <= "000"; m1_awqos <= X"0"; m1_arlock <= '0'; m1_arcache <= "0010"; m1_arprot <= "000"; m1_arqos <= X"0"; --}}} -- m2 {{{ m2_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m2_awcache <= "0010"; m2_awprot <= "000"; m2_awqos <= X"0"; m2_arlock <= '0'; m2_arcache <= "0010"; m2_arprot <= "000"; m2_arqos <= X"0"; -- }}} -- m3 {{{ m3_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m3_awcache <= "0010"; m3_awprot <= "000"; m3_awqos <= X"0"; m3_arlock <= '0'; m3_arcache <= "0010"; m3_arprot <= "000"; m3_arqos <= X"0"; -- }}} ---------------------------------------------------------------------------------------------------------}}} process(s0_aclk) begin if rising_edge(s0_aclk) then nrst <= s0_aresetn and m0_aresetn and m1_aresetn and m2_aresetn and m3_aresetn; end if; end process; uut: entity FGPU PORT MAP ( clk => s0_aclk, -- slave axi {{{ s0_awaddr => s0_awaddr(C_S0_ADDR_WIDTH-1 downto 2), s0_awprot => s0_awprot, s0_awvalid => s0_awvalid, s0_awready => s0_awready, s0_wdata => s0_wdata, s0_wstrb => s0_wstrb, s0_wvalid => s0_wvalid, s0_wready => s0_wready, s0_bresp => s0_bresp, s0_bvalid => s0_bvalid, s0_bready => s0_bready, s0_araddr => s0_araddr(C_S0_ADDR_WIDTH-1 downto 2), s0_arprot => s0_arprot, s0_arvalid => s0_arvalid, s0_arready => s0_arready, s0_rdata => s0_rdata, s0_rresp => s0_rresp, s0_rvalid => s0_rvalid, s0_rready => s0_rready, -- }}} -- axi master 0 connections {{{ -- ar channel m0_araddr => m0_araddr, m0_arlen => m0_arlen, m0_arsize => m0_arsize, m0_arburst => m0_arburst, m0_arvalid => m0_arvalid, m0_arready => m0_arready, m0_arid => m0_arid, -- r channel m0_rdata => m0_rdata, m0_rresp => m0_rresp, m0_rlast => m0_rlast, m0_rvalid => m0_rvalid, m0_rready => m0_rready, m0_rid => m0_rid, -- aw channel m0_awvalid => m0_awvalid, m0_awaddr => m0_awaddr, m0_awready => m0_awready, m0_awlen => m0_awlen, m0_awsize => m0_awsize, m0_awburst => m0_awburst, m0_awid => m0_awid, -- w channel m0_wdata => m0_wdata, m0_wstrb => m0_wstrb, m0_wlast => m0_wlast, m0_wvalid => m0_wvalid, m0_wready => m0_wready, -- b channel m0_bvalid => m0_bvalid, m0_bready => m0_bready, m0_bid => m0_bid, -- }}} -- axi master 1 connections {{{ -- ar channel m1_araddr => m2_araddr, m1_arlen => m2_arlen, m1_arsize => m2_arsize, m1_arburst => m2_arburst, m1_arvalid => m2_arvalid, m1_arready => m2_arready, m1_arid => m2_arid, -- r channel m1_rdata => m2_rdata, m1_rresp => m2_rresp, m1_rlast => m2_rlast, m1_rvalid => m2_rvalid, m1_rready => m2_rready, m1_rid => m2_rid, -- aw channel m1_awvalid => m2_awvalid, m1_awaddr => m2_awaddr, m1_awready => m2_awready, m1_awlen => m2_awlen, m1_awsize => m2_awsize, m1_awburst => m2_awburst, m1_awid => m2_awid, -- w channel m1_wdata => m2_wdata, m1_wstrb => m2_wstrb, m1_wlast => m2_wlast, m1_wvalid => m2_wvalid, m1_wready => m2_wready, -- b channel m1_bvalid => m2_bvalid, m1_bready => m2_bready, m1_bid => m2_bid, -- }}} -- axi master 2 connections {{{ -- ar channel m2_araddr => m1_araddr, m2_arlen => m1_arlen, m2_arsize => m1_arsize, m2_arburst => m1_arburst, m2_arvalid => m1_arvalid, m2_arready => m1_arready, m2_arid => m1_arid, -- r channel m2_rdata => m1_rdata, m2_rresp => m1_rresp, m2_rlast => m1_rlast, m2_rvalid => m1_rvalid, m2_rready => m1_rready, m2_rid => m1_rid, -- aw channel m2_awvalid => m1_awvalid, m2_awaddr => m1_awaddr, m2_awready => m1_awready, m2_awlen => m1_awlen, m2_awsize => m1_awsize, m2_awburst => m1_awburst, m2_awid => m1_awid, -- w channel m2_wdata => m1_wdata, m2_wstrb => m1_wstrb, m2_wlast => m1_wlast, m2_wvalid => m1_wvalid, m2_wready => m1_wready, -- b channel m2_bvalid => m1_bvalid, m2_bready => m1_bready, m2_bid => m1_bid, -- }}} -- axi master 3 connections {{{ -- ar channel m3_araddr => m3_araddr, m3_arlen => m3_arlen, m3_arsize => m3_arsize, m3_arburst => m3_arburst, m3_arvalid => m3_arvalid, m3_arready => m3_arready, m3_arid => m3_arid, -- r channel m3_rdata => m3_rdata, m3_rresp => m3_rresp, m3_rlast => m3_rlast, m3_rvalid => m3_rvalid, m3_rready => m3_rready, m3_rid => m3_rid, -- aw channel m3_awvalid => m3_awvalid, m3_awaddr => m3_awaddr, m3_awready => m3_awready, m3_awlen => m3_awlen, m3_awsize => m3_awsize, m3_awburst => m3_awburst, m3_awid => m3_awid, -- w channel m3_wdata => m3_wdata, m3_wstrb => m3_wstrb, m3_wlast => m3_wlast, m3_wvalid => m3_wvalid, m3_wready => m3_wready, -- b channel m3_bvalid => m3_bvalid, m3_bready => m3_bready, m3_bid => m3_bid, -- }}} nrst => nrst ); end arch_imp;

gpl-3.0

12011149724dabcbd521e691716af0fe

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_LMEM_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

d1de789a7ff07a9f15c7434e52b04e83

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_user_logic_subtractor.vhd

-- File: dyplo_user_logic_stub.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic�s maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_signed.all; library dyplo_hdl_node_lib; use dyplo_hdl_node_lib.hdl_node_package.all; use dyplo_hdl_node_lib.hdl_node_user_params.all; entity dyplo_user_logic_subtractor is generic( INPUT_STREAMS : integer := 4; OUTPUT_STREAMS : integer := 4 ); port( -- Processor bus interface dab_clk : in std_logic; dab_rst : in std_logic; dab_addr : in std_logic_vector(15 DOWNTO 0); dab_sel : in std_logic; dab_wvalid : in std_logic; dab_rvalid : in std_logic; dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Streaming input interfaces cin_tdata : in cin_tdata_ul_type; cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tlevel : in cin_tlevel_ul_type; -- Streaming output interfaces cout_tdata : out cout_tdata_ul_type; cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0); cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0); -- Clock signals user_clocks : in std_logic_vector(3 downto 0) ); end dyplo_user_logic_subtractor; architecture rtl of dyplo_user_logic_subtractor is type signed_matrix_4x32 is array (0 to INPUT_STREAMS - 1) of signed(31 downto 0); signal value_to_subtract : signed_matrix_4x32; signal cin_tdata_i : signed_matrix_4x32; signal cout_tdata_i : signed_matrix_4x32; begin config_reg : process (dab_clk) variable index : integer; begin if rising_edge(dab_clk) then if (dab_rst = '1') then value_to_subtract <= (others => (others => '0')); else index := to_integer(unsigned(dab_addr(3 downto 2))); if (dab_sel = '1') and (dab_wvalid = '1') then value_to_subtract(index) <= signed(dab_wdata); end if; dab_rdata <= std_logic_vector(value_to_subtract(index)); end if; end if; end process config_reg; subtractors : for i in 0 to 3 generate type sm_calc_states is (S_FETCH, S_CALC, S_SEND, S_FINISH); signal sm_calc : sm_calc_states; signal tdata : signed(31 downto 0); begin calc_data : process (dab_clk) begin if rising_edge(dab_clk) then if (dab_rst = '1') then cout_tdata_i(i) <= (others => '0'); cout_tvalid(i) <= '0'; cin_tready(i) <= '0'; sm_calc <= S_FETCH; tdata <= (others => '0'); else case sm_calc is when S_FETCH => if (cin_tvalid(i) = '1') and (conv_integer(cin_tlevel(i)) /= 0) then cin_tready(i) <= '1'; tdata <= to_signed(conv_integer(cin_tdata(i)),32); sm_calc <= S_CALC; end if; when S_CALC => cin_tready(i) <= '0'; cout_tdata_i(i) <= tdata - value_to_subtract(i); cout_tvalid(i) <= '1'; sm_calc <= S_SEND; when S_SEND => if (cout_tready(i) = '1') then cout_tvalid(i) <= '0'; sm_calc <= S_FINISH; end if; when S_FINISH => sm_calc <= S_FETCH; end case; end if; end if; end process calc_data; end generate subtractors; cout_tdata(0) <= std_logic_vector(cout_tdata_i(0)); cout_tdata(1) <= std_logic_vector(cout_tdata_i(1)); cout_tdata(2) <= std_logic_vector(cout_tdata_i(2)); cout_tdata(3) <= std_logic_vector(cout_tdata_i(3)); end rtl;

gpl-2.0

da5d5018bcb1b096876f16026fd5adf5

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_fdiv_fsqrt_8_2_2_2.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

b8122fbdc6d8aa7067a187ce6ea09c9d

kennethlyn/fpga-image-example

hdl_nodes/adder_2_to_1/adder_2_to_1.srcs/sources_1/dyplo_hdl_node_user_params.vhd

-- File: dyplo_hdl_node_user_params.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic�s maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package hdl_node_user_params is constant c_vendor_id : integer range 0 to 255 := 1; constant c_product_id : integer range 0 to 255 := 4; constant c_version_id : integer range 0 to 255 := 1; constant c_revision_id : integer range 0 to 255 := 1; constant c_input_streams : integer range 0 to 4 := 2; constant c_hdl_in_fifo_depth : integer range 7 to 12 := 8; -- specify power of 2. FIFO size = 2^x. 7 = 128, 12 = 4096 constant c_hdl_in_fifo_type : string := "DISTRIBUTED"; constant c_output_streams : integer range 0 to 4 := 1; end hdl_node_user_params;

gpl-2.0

7c5846f03cee67c83993e271c339d561

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_fadd_fslt_max.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

bb5dee530315fea9c16824c204ee177c

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_SubInteger_6ALUs.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

a213b4286eae0df5cd0131bbf343d847

joalcava/sparcv8-monocicle

Test_Instructionmemory.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Test_instructionMemory IS END Test_instructionMemory; ARCHITECTURE behavior OF Test_instructionMemory IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT instructionMemory PORT( address : IN std_logic_vector(3 downto 0); reset : IN std_logic; clkFPGA : IN std_logic; outInstruction : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs signal address : std_logic_vector(3 downto 0) := (others => '0'); signal reset : std_logic := '0'; signal clkFPGA : std_logic := '0'; --Outputs signal outInstruction : std_logic_vector(31 downto 0); -- Clock period definitions constant clkFPGA_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: instructionMemory PORT MAP ( address => address, reset => reset, clkFPGA => clkFPGA, outInstruction => outInstruction ); -- Clock process definitions clkFPGA_process :process begin clkFPGA <= '0'; wait for clkFPGA_period/2; clkFPGA <= '1'; wait for clkFPGA_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. reset<='1'; address <= "0000"; wait for 100 ns; reset<='0'; address <= "1110"; wait; end process; END;

gpl-3.0

f5a70dde47e3dc4583011188a4233d48

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_min.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

06161b0c3fa62827ca1649af44fcd31e

preusser/q27

src/vhdl/queens/xilinx/arbit_forward.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity arbit_forward is generic ( N : positive -- Length of Token Chain ); port ( tin : in std_logic; -- Fed Token have : in std_logic_vector(0 to N-1); -- Token Owner pass : in std_logic_vector(0 to N-1); -- Token Passers grnt : out std_logic_vector(0 to N-1); -- Token Output tout : out std_logic -- Unused Token ); end arbit_forward; library UNISIM; use UNISIM.vcomponents.all; architecture rtl_xilinx of arbit_forward is -- Intermediate Token Signals signal q : std_logic_vector(0 to N); begin -- First MUXCY only with switching LUT q(0) <= have(0) or (tin and pass(0)); MUXCY_inst : MUXCY port map ( O => q(1), CI => '1', DI => '0', S => q(0) ); grnt(0) <= tin and not q(1); genChain : for i in 1 to N-1 generate MUXCY_inst : MUXCY port map ( O => q(i+1), CI => q(i), DI => have(i), S => pass(i) ); grnt(i) <= q(i) and not q(i+1); end generate; tout <= q(N); end rtl_xilinx;

agpl-3.0

673ee4085a197963589cb4ef20dc87bd

wltr/cern-fgclite

critical_fpga/src/rtl/cf/pf.vhd

------------------------------------------------------------------------------- --! @file pf.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2015-01-19 --! @brief Power FPGA communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --! @brief Entity declaration of pf --! @details --! This component handles the Power FPGA communication and takes action in --! case field-bus communication is broken. entity pf is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name PF interface --! @{ --! Send power cycle request to PF pf_req_n_o : out std_ulogic; --! Enable power down on PF pf_pwr_dwn_en_o : out std_ulogic; --! Power down signal from PF pf_pwr_dwn_i : in std_ulogic; --! @} --! @name Internal interface --! @{ --! Start of cycle ms_0_strobe_i : in std_ulogic; --! Millisecond strobe ms_9_strobe_i : in std_ulogic; --! Millisecond strobe ms_11_strobe_i : in std_ulogic; --! Voltage reference input v_ref_i : in std_ulogic_vector(15 downto 0); --! Voltage reference output v_ref_o : out std_ulogic_vector(15 downto 0); --! Voltage reference output enable v_ref_en_o : out std_ulogic; --! Flag indicating voltage reference override v_ref_override_o : out std_ulogic; --! Backplane type backplane_i : in std_ulogic_vector(7 downto 0); --! Flags indicating which commands have been received command_received_i : in std_ulogic_vector(3 downto 0)); --! @} end entity pf; --! RTL implementation of pf architecture rtl of pf is --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal pf_req_n : std_ulogic; signal pf_pwr_dwn_en : std_ulogic; signal pwr_cyc_chk : std_ulogic_vector(1 downto 0); signal v_ref : unsigned(15 downto 0); signal v_ref_en : std_ulogic; signal v_ref_ovr : std_ulogic; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal rmp_dwn_strb_rst : std_ulogic; signal rmp_dwn_strb_en : std_ulogic; signal rmp_dwn_strb : std_ulogic; signal pf_pwr_dwn_redge : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- pf_req_n_o <= pf_req_n; pf_pwr_dwn_en_o <= pf_pwr_dwn_en; v_ref_o <= std_ulogic_vector(v_ref); v_ref_en_o <= v_ref_en; v_ref_override_o <= v_ref_ovr; --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- rmp_dwn_strb_rst <= not rmp_dwn_strb_en; rmp_dwn_strb_en <= v_ref_ovr; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- strobe_inst : entity work.lfsr_strobe_generator generic map ( period_g => 3051, -- 3051 * 25 ns = 76.275 us preset_value_g => 0) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, en_i => rmp_dwn_strb_en, pre_i => rmp_dwn_strb_rst, strobe_o => rmp_dwn_strb); pwr_dwn_edge_inst : entity work.edge_detector port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, en_i => '1', ack_i => '1', sig_i => pf_pwr_dwn_i, edge_o => pf_pwr_dwn_redge); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin pf_req_n <= '1'; pf_pwr_dwn_en <= '0'; pwr_cyc_chk <= "00"; v_ref <= to_unsigned(0, v_ref'length); v_ref_en <= '0'; v_ref_ovr <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else if ms_0_strobe_i = '1' then if command_received_i = "0000" then pwr_cyc_chk <= pwr_cyc_chk(0) & '1'; else pwr_cyc_chk <= "00"; pf_pwr_dwn_en <= '1'; end if; end if; if ms_9_strobe_i = '1' and pwr_cyc_chk(1) = '1' then pf_req_n <= '0'; elsif ms_11_strobe_i = '1' then if pf_req_n = '0' then pf_pwr_dwn_en <= '0'; end if; pf_req_n <= '1'; end if; if pf_pwr_dwn_redge = '1' and pwr_cyc_chk(1) = '1' then v_ref <= unsigned(v_ref_i); v_ref_ovr <= '1'; end if; v_ref_en <= '0'; if v_ref_ovr = '1' and rmp_dwn_strb = '1' then if to_integer(v_ref) > 0 then v_ref <= v_ref - 1; v_ref_en <= '1'; end if; end if; -- Don't do anything when backplane type is x00 if backplane_i = x"00" then reset; end if; end if; end if; end process regs; end architecture rtl;

mit

3eb20a1952d3c950c8a4974770184b44

wltr/cern-fgclite

nanofip_fpga/src/rtl/var2_rx.vhd

------------------------------------------------------------------------------- --! @file var2_rx.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2013-10-24 --! @brief NanoFIP VAR2 data receiver. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; --! @brief Entity declaration of var2_rx --! @details --! Whenever VAR2 data is received from the NanoFIP field-bus, this component --! ensures correct handling of the address space within the NanoFIP core. --! Each FGClite receives 4 bytes of data according to its station ID. entity var2_rx is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name FGClite interface --! @{ --! The FGClite station ID station_id_i : in std_ulogic_vector(4 downto 0); --! Signal reception of FGClite command 0 cmd_0_o : out std_ulogic; --! @} --! @name Receiver interface --! @{ --! Data is ready to be received rx_rdy_i : in std_ulogic; --! Read address rx_addr_o : out std_ulogic_vector(6 downto 0); --! Read enable rx_en_o : out std_ulogic; --! Read data input rx_data_i : in std_ulogic_vector(7 downto 0); --! Read data input enable rx_data_en_i : in std_ulogic; --! @} --! @name VAR2 interface --! @{ --! Received data for serial transmission tx_data_o : out std_ulogic_vector(39 downto 0); --! Received data enable tx_data_en_o : out std_ulogic; --! Transmitter busy tx_bsy_i : in std_ulogic; --! @} --! @name Error flags --! @{ --! Read-write collision err_rw_coll_i : in std_ulogic; --! Interface busy err_bsy_i : in std_ulogic; --! VAR not ready err_not_rdy_i : in std_ulogic; --! Wishbone bus acknowledge timeout err_timeout_i : in std_ulogic); --! @} end entity var2_rx; --! RTL implementation of var2_rx architecture rtl of var2_rx is --------------------------------------------------------------------------- -- Types and Constants --------------------------------------------------------------------------- --! Base address for data payload constant base_addr_c : natural := 2; --! Number of payload bytes for VAR2 constant num_data_c : positive := 4; --! Data array type data_t is array (0 to num_data_c - 1) of std_ulogic_vector(7 downto 0); --! FSM states type state_t is (IDLE, REQ_CMD, STORE_CMD, REQ_DATA, STORE_DATA, SEND, INIT); --! FSM registers type reg_t is record state : state_t; wb_addr : unsigned(6 downto 0); wb_en : std_ulogic; num : unsigned(integer(ceil(log2(real(num_data_c)))) - 1 downto 0); cmd : std_ulogic_vector(7 downto 0); data : data_t; data_en : std_ulogic; cmd_0 : std_ulogic; end record reg_t; --! FSM initial state constant init_c : reg_t := ( state => IDLE, wb_addr => to_unsigned(base_addr_c, 7), wb_en => '0', num => (others => '0'), cmd => (others => '0'), data => (others => (others => '0')), data_en => '0', cmd_0 => '0'); --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal next_reg : reg_t; signal wb_if_err : std_ulogic; signal data_addr : unsigned(6 downto 0); --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- rx_addr_o <= std_ulogic_vector(reg.wb_addr); rx_en_o <= reg.wb_en; tx_data_o <= reg.cmd & reg.data(3) & reg.data(2) & reg.data(1) & reg.data(0); tx_data_en_o <= reg.data_en; cmd_0_o <= reg.cmd_0; --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- -- Combine errors into one signal wb_if_err <= err_rw_coll_i or err_not_rdy_i or err_timeout_i or err_bsy_i; -- Calculate memory address based on station ID data_addr <= resize(base_addr_c + (unsigned(station_id_i) * num_data_c), data_addr'length); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= init_c; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else reg <= next_reg; end if; end if; end process regs; --------------------------------------------------------------------------- -- Combinatorics --------------------------------------------------------------------------- comb : process (reg, rx_rdy_i, rx_data_i, rx_data_en_i, wb_if_err, data_addr, tx_bsy_i) is begin -- process comb -- Defaults next_reg <= reg; next_reg.wb_en <= '0'; next_reg.data_en <= '0'; case reg.state is when IDLE => if rx_rdy_i = '1' then next_reg.state <= REQ_CMD; end if; when REQ_CMD => next_reg.wb_addr <= to_unsigned(base_addr_c, reg.wb_addr'length); next_reg.wb_en <= '1'; next_reg.state <= STORE_CMD; when STORE_CMD => if rx_data_en_i = '1' then next_reg.cmd <= rx_data_i; if rx_data_i = x"00" then next_reg.cmd_0 <= '1'; end if; next_reg.state <= REQ_DATA; end if; when REQ_DATA => next_reg.wb_addr <= data_addr + reg.num; next_reg.wb_en <= '1'; next_reg.state <= STORE_DATA; when STORE_DATA => if rx_data_en_i = '1' then next_reg.data(to_integer(reg.num)) <= rx_data_i; if to_integer(reg.num) < num_data_c - 1 then next_reg.num <= reg.num + 1; next_reg.state <= REQ_DATA; else next_reg.state <= SEND; end if; end if; when SEND => if tx_bsy_i = '0' then next_reg.data_en <= '1'; next_reg.state <= INIT; end if; when INIT => next_reg <= init_c; end case; -- Reset on error if wb_if_err = '1' then next_reg <= init_c; end if; end process comb; end architecture rtl;

mit

329f43ef331bfff61c668d1d823eaad9

preusser/q27

src/vhdl/queens/enframe.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity enframe is generic ( SENTINEL : std_logic_vector(7 downto 0) -- Start Byte ); port ( clk : in std_logic; rst : in std_logic; idat : in std_logic_vector(7 downto 0); ieof : in std_logic; ivld : in std_logic; igot : out std_logic; tx_ful : in std_logic; tx_put : out std_logic; tx_dat : out std_logic_vector(7 downto 0) ); end enframe; library IEEE; use IEEE.numeric_std.all; architecture rtl of enframe is -- CRC Table for 0x1D5 (CRC-8) type tFCS is array(0 to 255) of std_logic_vector(7 downto 0); constant FCS : tFCS := ( x"00", x"D5", x"7F", x"AA", x"FE", x"2B", x"81", x"54", x"29", x"FC", x"56", x"83", x"D7", x"02", x"A8", x"7D", x"52", x"87", x"2D", x"F8", x"AC", x"79", x"D3", x"06", x"7B", x"AE", x"04", x"D1", x"85", x"50", x"FA", x"2F", x"A4", x"71", x"DB", x"0E", x"5A", x"8F", x"25", x"F0", x"8D", x"58", x"F2", x"27", x"73", x"A6", x"0C", x"D9", x"F6", x"23", x"89", x"5C", x"08", x"DD", x"77", x"A2", x"DF", x"0A", x"A0", x"75", x"21", x"F4", x"5E", x"8B", x"9D", x"48", x"E2", x"37", x"63", x"B6", x"1C", x"C9", x"B4", x"61", x"CB", x"1E", x"4A", x"9F", x"35", x"E0", x"CF", x"1A", x"B0", x"65", x"31", x"E4", x"4E", x"9B", x"E6", x"33", x"99", x"4C", x"18", x"CD", x"67", x"B2", x"39", x"EC", x"46", x"93", x"C7", x"12", x"B8", x"6D", x"10", x"C5", x"6F", x"BA", x"EE", x"3B", x"91", x"44", x"6B", x"BE", x"14", x"C1", x"95", x"40", x"EA", x"3F", x"42", x"97", x"3D", x"E8", x"BC", x"69", x"C3", x"16", x"EF", x"3A", x"90", x"45", x"11", x"C4", x"6E", x"BB", x"C6", x"13", x"B9", x"6C", x"38", x"ED", x"47", x"92", x"BD", x"68", x"C2", x"17", x"43", x"96", x"3C", x"E9", x"94", x"41", x"EB", x"3E", x"6A", x"BF", x"15", x"C0", x"4B", x"9E", x"34", x"E1", x"B5", x"60", x"CA", x"1F", x"62", x"B7", x"1D", x"C8", x"9C", x"49", x"E3", x"36", x"19", x"CC", x"66", x"B3", x"E7", x"32", x"98", x"4D", x"30", x"E5", x"4F", x"9A", x"CE", x"1B", x"B1", x"64", x"72", x"A7", x"0D", x"D8", x"8C", x"59", x"F3", x"26", x"5B", x"8E", x"24", x"F1", x"A5", x"70", x"DA", x"0F", x"20", x"F5", x"5F", x"8A", x"DE", x"0B", x"A1", x"74", x"09", x"DC", x"76", x"A3", x"F7", x"22", x"88", x"5D", x"D6", x"03", x"A9", x"7C", x"28", x"FD", x"57", x"82", x"FF", x"2A", x"80", x"55", x"01", x"D4", x"7E", x"AB", x"84", x"51", x"FB", x"2E", x"7A", x"AF", x"05", x"D0", x"AD", x"78", x"D2", x"07", x"53", x"86", x"2C", x"F9" ); -- State Machine type tState is (Idle, Transmit, WriteCRC); signal State : tState := Idle; signal NextState : tState; signal CRC : std_logic_vector(7 downto 0) := (others => '-'); signal InitCRC : std_logic; signal UpdateCRC : std_logic; begin -- State process(clk) begin if rising_edge(clk) then if rst = '1' then State <= Idle; CRC <= (others => '-'); else State <= NextState; if InitCRC = '1' then CRC <= FCS(255); elsif UpdateCRC = '1' then CRC <= FCS(to_integer(unsigned(CRC xor idat))); end if; end if; end if; end process; process(State, tx_ful, ivld, ieof, idat, CRC) begin NextState <= State; InitCRC <= '0'; UpdateCRC <= '0'; tx_dat <= (others => '-'); tx_put <= '0'; igot <= '0'; if tx_ful = '0' then case State is when Idle => if ivld = '1' then InitCRC <= '1'; tx_dat <= SENTINEL; tx_put <= '1'; NextState <= Transmit; end if; when Transmit => if ivld = '1' then UpdateCRC <= '1'; tx_dat <= idat; tx_put <= '1'; igot <= '1'; if ieof = '1' then NextState <= WriteCRC; end if; end if; when WriteCRC => tx_dat <= CRC; tx_put <= '1'; NextState <= Idle; end case; end if; end process; end rtl;

agpl-3.0

67d3ce827b42b83fbc672cfa30bb22e8

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_fsqrt_uitofp_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 3; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

8c3129e1083bf6af66588a8383503204

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_2Banks.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 1; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 1; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

dd77b113e04153da1854d10cc990b66b

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block WehuouTPPDZGrXRUMpMRdt7q1oelAHGjB47h15Zm3uCzRX/C7e4hjTSNtYAqRPnxnMGuytQhCta7 hIBv8KlybQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block HZvnlYU3mMOjvCRkuHEOcrAkBFUBRdXRhlMlWDL/vscHLzWEjckJbOi6NuP/WMQBJsmKtKI84K5c CD3cfbNCLaFx8ExeLJCNQBB2EctErlSUqJnKl4bOB6E+G5lMdvRUOmojRYPXKo8DG3xt10MDC2sr 3CZttSSAGOX+dkJl2oc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Bv/8FzaE8Ktpnfx8CL1R4Bao4u5TAbEUx1z5oXcCV6FPxgIoNHNzRd+sbueBJ8Uoe170xKccP5Tp KAtrK+36KPWl2py8rh5pRNU2lIuolTKw/XJZXlqmEHqC3/J6ygP2GRRr4h5twjcjpe5IZ+1cuNVE 619kCO2wPFtaMjLgrRwybo5nX7X/tjihSwBiXCbRHedjyL9XuMV1lgkHY89Dd6V7Cjm6adpETOwK M9JwzUtY/J4dkqQzOQULrslekYLjqnWy5ASwL3kke3j2/pHtktRtS3YE7DfGWMeXxPP23yVL7BLt IOK34dVRcpGTIFvkBRENVtDFLiix1Z85oCyPJA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block u/fGsPEo7c2kpt/Ag3bFYiBIjW47p24yMNKHftRSfNd6DBoxgDXis69adYak+S7aQRrSwrKjXKlF xpfe5CvmunXboRNXIbOKOnSHRRjXJOPQjLD71fqfV5NJvuZv9jkZ8Ezq8OZPWf2VZm/NNemJYyCP mm2oVer5TmXVfOsTZ10= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block i2UmAAB8R8ARRaZJLFRGpDkMbb72o+J42AKpMWLZexJf0AG3BrWLOrSjAw9Zq6sRmO4bGU6a0XPM ARsFTgSrT4PUvRftPqPDt3e+2jL6q7EXGo86e4xlsWMY5HWpZlF9zQpZqF4dT3x+ljv19ieap054 4eBXHC9L3USUDerZyG+s8uGNqa4QMAj2wewsfGo5fZ6cS+GLDCP9ilw2OxueHOelvTBOnCOO/5Pc ndJ34iuwYAJaNXUg0UCLnlQrGJa81z7KM4VxKu8EkIT9fQj3fUnYMwu8TSByGLb/lv6ZnX2057u8 Mw62BQ4PSDE05fJjG3KMx1absQHlHnKs7hqKdA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008) `protect data_block jqzd0xptB8OH4pBur1yGTPvBCTSxzET1zY3Tx0gh+0n8w+3b1BF++GHl4CqT5jiyo/5C6pmdxCOp 2zPgYR77xyPzJJCI21wpkeMOaZ8AOhNh52rrhu7uc2ZhpLRgltQ3QeWe+LY0voc4Y2thWUmIca0n yOyKzDBAXqdA1o6vn4jdtM15ypHGq7PdceWZHSlL434uNY3QBNKTq3dfLOft3EXe3X3/L5pED9rX qovEgf0VINDHJ8B0RkEwpZ5S6r8nYx27bcvjQqEtHTzDn4QG+4bsrt4V5CL2zo1nOuk2f/RDGjtC s2Cxn45Ltga8Rgcqt3R81il4zqg4zCLw7g3W/4J1cpcBQvJ9wJx4Vx8SUyFQh6Ea+0HwezFf821n 1hk3lX1S/raDMk9v8Ku+Nj9YGAPUvZeUf0dz+S5MVnk9+HW2/nPaSWkL6Kgm/vY12JjwLKYG3XeO 3GVbYECjzfEkrHqk7FvgqaIst+dcQFEG1EcmN/Q4toYwI3O/MP3jg6SJ4G83IVTOFuo2JrCYq0q+ WLWFco9BVztJSHQ6hSF3jNfimseVKfxKClu2Uac6xAl8QceGBg3LhQ5RI0LOPG2HprbjpjGtNYJy Z0Ag+yJeWsUKSaN33U3+0J/d7SPDhk/rLBzKlMBG0wTTlUYKUEokod67TAkFWDL8zuL73zxe+Qcd jtwjlpSSntRLDh0u+1fTMOajjdR8XhJd/sDStJiQLt4ckq2H+JsXAEKeCKzt3ag2yyPTkv9Hv64+ nDlZJTs5LnPDnGa8b9z4gMF7xyirfJokGad0+f7hew4EHFMgxHEx7I/iWgtAbjtHHcGFDfDmPYax 9uvbW60+ITQkfPyPDKYtGIJieiOhbRtjBJBUt/pl+VR7+57WGVGhzjLPcMfekljKptYZnpFloaBf 5jddi4uJQdvq4Q7I7UljQhEnfR4LvEJAi+5uEQpX3nIUhE8mTpRHUn4z7TDN7T4UGhGa43d7g2lC pbKSJMWaF72w+iFM1oY9J0ZbtFJFNqednM5L9TVOtvESGdKv+4/kFqvJMWmPqbPIpKcz72Ob7JXP dCzxk7m0gU9m0OeX4L4dhEpdDrtT3nB0oFxuR1F2FGNIB33cLlrr1v+WI4ManrhxrU551UXIKUJN TLsm24Dyxha4IOWD9PYrZ9QOmfFN6OPBMHI8JZQmAkiDWmUTbUOlNuRdbz3Lq1G+nXboV8JXQlL3 msIPVxLW/T3Ju9uGHwzPRYY9zZPpwhxaqEILheHVtuDt61OjkqWnUH5psCFqPIOqnos1n8b3t7hB lc1VKeEVtGHzE+KzG9WYxtdyFGcPtgpSCMypKV416cXd+8wgc09eHKUR1Bb2cZEPUGE0ynuBgebe B+DBxk8cNkUDi1RTwm/b53UBCXdrI21CM3CJ8mUkgW5kTGAlKMb3IOUQ6sb3NROHpKLNE4p6BGwm BJCeEsHSL3IzTLBfxE8C2JFCntlHSfp46MicikooENQch8MgFL0RqIpkkcWdR+y9mFsJC/WPg7v3 R+weCUbP1H4Bb5hLTkL/XjZ2LeDvQ25fx9Y/B0aIowfOwMi3Vnh7AyqFqd6bZc43DaKfMYuOudgl MrMngeDtJlF1rN4QmcTA60cfdEbySqBIFJpYPQTWMwI+Hw9+/wdb6BgDX/1AHjNXLURpTzVHzzxr 1sdn6q15VZnvsSBw/e+V7+gQn1uIEXP/Y7lmuZ66hW0fcqGkSq6xNyRtmT6IOjP5ZbhQQvUhVZDy 4SNC2xrNBFBVbq96gMDGUUTQ/GHwffg+Lf/sqt0HnqeX4GOrnFrr5Te+j8VmRMOMnDn3UynBg2f1 XOGEUYd98fB5qUv+BFHuatWxb1r3Dd+2riG8/uFl/wuQ35KzpcC747VuidR0fsTJUGWIXkVzl4Ns rcBRi/DurPI2BTz4sSlJ+A3htYMQCLZhYeBdX7rTnvkQI78O8tBZBRcONS8n6umZFEPSD5ZSUXQm ZG5X5rdhT9YUb6DvjLyD++m0JRypAI4ceDQOi1e6vcK8+BxornsJxP2lbMrJvieXOKUveD9aFD/5 u96sahf4c3ix+QF3UIEJOsL+Jc581lKLa4djgJNNGTYJLuaX8BugvMpgqBYLqgspd5WOBzJGENiT xqpqlgRT8e23TkvpQdS5D3arx8VmjKRrzX9uyPj2cMeT0cwQlcZyB7SRiKp+qx2MWyylY9umhG73 cv+O87kxvhbnZXII5F3EaFjy3Wu80e9LcLNxZcaKyGJfLnoWrMfnDYH46kPWa+/NCFDQRMxnQ9cG GMFdRP1S26/aQn0nwW6SbIdv7qJUB/vO/7UkncWe31l71I+UKkPpB8Sh3+awJuSTXaDqGeA3Zdxu iehDpWax0YfYR6k0qP73Bl4z08L1B1yUGeZ+ODzpZzl5OI3mTiPMB7qLPXvRs/VVYPKcKgeg6ZKT 0DD07ueZ7JHFLS1xoy4NHhNBvkf176wcCQ+R4BA8QuAeBYyON564wYj7nb6zjIuFIgeLVF06wf9/ ot0MjmxVcjmUocx79sTedqs0crINCXrRcW2n996RcsA6Rk8wkRM7L0qezc0eTydw5y7m2bn2qKTV clqa2Hxr5jG5hUzrce8BXb5vsMHuV6W6XM0B04Fbmx9C/5a1op51ChFZx8fq1zACD0SIePiY5UCY wYX7aL5K5vmOIPgfvgP9z5VrtfYNRWWrReHQ2ovRnHtp09xUz4Q6Yr3FvFj3F7Mkku9It2aXxXFE xx3/7kULe8H/XUw3p05mLP9PkUk1eh3CZXCqsRyzKKHfhOHF0wdc5cq+A7d9/eTUqfMIt9EeqJk0 GhLWjFp+xAtv8P+1T+4TLZuehq1ejYYIAXV7J0Yg1HeEPTbdvWglxcq5WjaG+P03v1fjOdi2bma8 D/M395mjjQQ+JeNAxQYzOerwA0bh0J9x1KViC2mJKCuMgBgZ8v/RWIwV5F8sqVNYeNgFUcsaDJ6t sS8prh2QuqD07rRtTOTR7a3R4AzmZ4T+fEvh58KovCq11rEky2zAwFdOMZwlDqBQcrOoth5/vSpm YccVFX7iXRpFG5Gp+wPrzVTnTUUtU1ghT9ZFneK14f0DJT2yPwM7jSm4M7kSmyVVFA12nMHTE52l v3lW+c+9H1Ty2uZflv/HkWCOi0mzk4wLpwtSw4B2j653n76nZF8AYEC1UnYX0FuYRoFiD/t8B2ms 2d3epptU7ix7jaNjIkbOyyToOwv59c8hW0/tDCmcEfFedMq7DybgMRVciTdUJzNHyxlLrhnZM3Pu sXpIsGePJnJKybXHE7cdIbaL15dOTB+l8ZAmaaetYpKneD+7/4zh/63YhzxlEiQLapqvAGHwlB3p WI83eMoXS4FP4w/bqSDTBcoQjQxjA/eYPOyh4FRAiBbW2O77oLkIaljR8fFFqSRWdGbDjFMQJV2z R7r9IFdqdI7Q9+QU+rkb3F0UNGlzPwq8EYbY3jNkl5RJfPUSVReCoVpaBjzgLaajZYKLXMVXQEvp RlIbErgS3Wgvzvj1ztjdgCOqUJkUPab2WVAdDEFUDCUTdAPQId1bkgS3YzBVVndJFL4ZnxsDtxzC xWLXis4JbVBaDdyEuPcG8EQ0HE/yTj3f88DAwNIcBWEGYP3/stZ9LStcG20yP3ROtDJeNaO93vEk UmSG3t8DtjhJ9l/+gCfhJPZUFdIhX5dJUN96YhNVS6M2/R+ideAEn5Kc2Wa9GtDK0nwO+tELPxrp EFAOoBXEUFh+fK2VZgITz8fx+n+BywHbpFW3YRlLx40jNKzFfweoRsnwSiMT1H1lqdTPoR8pTuPh 0cPKHL/FsHHqoRCO/Zb0QpnNG29vDEa88ydXsKMjmyP3D7tpQA2zvQ78W2DpVNpOLX5yIr9ZzeGb E2sEPto9uOjndSo9jH9D1nHTibdhin7lgI3hlzHCVzTXZbADGxoUF5cVBUCA18I9FLbd/NzzEkEP cWGfa44t4YDeWNblnPB5is5bT7+Ti4I++fIypq5MXBsbF1aFOUYqUjiD6Bx4XLtr+p0dVZcv86ZA rDqSXv6ZOPG5nyA+iNtstIJAuPVSQNzW8/rO8iwYemxwinWWUy2/s9VK1fw2OFSqb/uEvvdi1cYu IP81k7fRkiiBIQa/jETKmjR2mupEjL5Z56jjXiPmXy7Lpk5ux5KmpJqX/7/ndztFQ9A5ZyX9ZvpU uConxsvN1RnPTOT8wLhi5fchG5uZSNczDGXy9MJ6FK9LJ283ZMA4+C6pzld8+lojQaT91nVtaj3p Uc7csU8UH9hP5uFAtCU9NINE172Na4F0wmDzZvV7xCOGeY0zaLhiNj1yj02Eu93rFuk+XdID01HT SrKv8Wk/Vzk4v0Ai68dXMmKqzXjJQXY2ic8yMjss/pzsFvxL+ntv3yyF6WtXVP1FU88U1OBCJCv+ kP9hKKFyCdyEVMe4EvcW+nDV+aDfHXizVPW0MXeOzYHyFHPYJ+sMwNoEEMmb/41E/YkJa5YG30mi zfVIf2CWoRT7yJ6UdXU7c3HApXm41Ti4bt15+SzF4Zx/JLBvpqhowEbKcc9nOKPFpDaih1Tbv5Gw rt+kAvloKbMTxX/5rNqwXIMVlg5+eD/PszYa0BcuhZErYF51IMat6IxUQu3WN8be6DARWo36RWDj J0wRE8Xa1qaKNKfIBJAeFY6sTN6M1p3Iz3+mKEOXPJmkqJTXmAEihR4sDetVdaaEJjKtqNsSoG84 T5gXGnu6mCX7Mt2ZrrF2TGKZUXZUrGldjpHaz5hyI4UfqK/QseXtfhCBx3AxnpL9t9mrvvNBDHp9 qKBMWYQLoHjEVYlFLg0CMQQHqG+DDcv3qQnBsV/WoYeMDlS/p8ZZXB9EsRLVD0TxG1YFkS+D9b35 thu6sHqDv/OuHYXWLnPlDNkfXQr2hpbB20GpZXRuWsHRD2OD6dqP4HvnBP5vQ1XuExITO5DJekLl oiPQv0aveBK6JBwSCHWGIc3wd9g/hqxUMwZBDjjBfMvwycGqIbEWdVKaYFAhSRhQhSmLwd37J9eT q3avefoxnxZ443LyN/+jRl+rBUPS2e9cPZUCUWZVA7f/g/sj1FGrLbA2BnhceeeS64eVxF5ryIEN 7Y/2Pt46E4TJOVhc5+/OFDyqFQWpGAto6aB2AnNzLDvsKgwv+C/bpNglKt7rHnipO1DJeXwJjz/5 FwrjVql6pcwIgjeqdhmV4vXSKD5HWCvV04HtIR4cKFInF/fjVmmbd6QDpMCbEcp0loKngeZyn6XC BihZvXnFh/g2tA/N0/gExkaCMf/guQcWe1sUL3adYdUGUyJ/yJaMoGh0E7lsziGXOHw1sut8q3Ef I5vdt1jiLv9GHI+BS6WNAZWvE1URY6DkZ3xzTPhkcmOF3C+O++P9VzR2sz5mNRnuUY/hORkEpmpk N0MDt3+h6wWssTzcipMDGLlRAwrbZyxwY0qfPoE+3FndTJ4SJ6p4JPjY2T0Mj6v56yGbpEda3HI3 fMG1LuLbp8zNCjk2EtuGLJDAMNEeXiRZkG9mRDldFEM3saxM2uh8wfxspIw+ggbNlJioapmbYZCo yV+ZMZxd/TSJnmWVPqYrEnoPzrSYYITk28CbELZYn9d8/YMUpJAvauv9eu3rh09camNlV4sbKPG1 z5NvHuVLRqBLdwptuZwLeIpPcNp7AoedoL+7orSqwi9VF4Am0jSpbGR7/6FthB9Fvb2/Hwt2PxX+ fXfHt8/t6j4pXzDiEluMGaoLWR7cOGB6O7wGpEKztLfO80MslykcwqonsEx1TjbHUYLvUhAsqv9f wOM55+TEC1PJ7VmBwqc8VRnv8p2lzVZVT6PcVOmCwuQxWxvC+vpRQw0pEFxpazfH3j3Ae2I3LZpd ZjGOlb3g7C8JroTtzm5BMB1T7XES9NSLf5/74IKwhBpipNRup4oSXFQO8varPZh5arnu557Ume9W F3ocbAB9g3JyZkLt2Co6GO6jB6FPP807G3t2OUkotfHze3OX087KSWPK1BOuxBAnncsX3poKJlIU XsUbBRXZWja+FrorR4ZL0eEdSUAyNoGdojQp+i4DJFtC72e9Fgm8C5QdMkaYK1d6SZy1uveAw+QA hQWeTj89AwiCWIKgr+NnsXATKEq8ojvwMfv3fV0DHtd53eGSb9JDmtuMtsPsQHMwrevYSWmXlO27 6hV+9aN4zCNHVJ4gI9AFXEUfeNTpWZfgQ3VNbAg1gm1kFVYM8aHiGqBLXmzJQBFzk6MoXK6BQwxc fcDs46G0KWKyyVAfY2174sEP6L7l/rU2P/CTFnecM0bS0FxbR2OX3t/dOASCa/ghP/U1GPjPXo2G pZamIlCErSWSElXMjYJxPBseYKmLJY/CoyasruqUOQQ4rjgoMNQ7RlsWoOZAwgj5CVV8lz25s47o VaYL0c9OXMrabtNlaRaOK72CAZ78J9SkmWMa0ETeKBz5ZK/7RmMg1N5XnCKiJvPsIVmc0iGAq86l cUXBOtYVvJAIlltiUcOaX3x965YZ6fJJ7ai0TyCj3DapH1o55s+CNHvsKcYHPgMIwEoDwWIMzWJI WJ1yrV1u/dYz5spK008joOEFNFk3KzVPfF1Zo1qJj7vHlBpKnetiXhgFHltNmDKXDKZPWgvccD35 p1S2QQC1NGlN8u56b5GRMnTYgzr2sbxZ2caslLle8Qj5JEfTT2cY+wsWNrlRySwb9wkIxdDfccUS UipCDLJ6KdiqMAJ2F/1UUZGI4z8vEPOFOHWqQaQUvZV0UHDu1LGkuGisGA0Oiza6VjFNs++b53qN Mz8YnzIBvyEJyy8TmDo7cp2y5uVOpVeHoxiTHZrMilRQTWsuURCdIb4e38ku+q5XxGnxlI/HQL5F jOJ5VpMipDKuWtUXzP0HgKz7RxvC3EbQOqc/FXTgQfiIPymJO8SAWyOn4Kq7MKHBTr6V8VyFPrD4 fGwh86oURip3w1cZ7isRY5oGR+wtw4aUx6HEkgPjc8cloN3lo+CHLOWyRk287s6Qdbp2lMjI3Kra lsm7x+S4sS86qs3ahBM2TUf6eI/r2DLSgyl3ozE2jI2VwuucYohGTIPYRgqJb36K9Z4AbYY/Usjd KFbeKXvKJs5QWK50McdvhOGb1Q06nq7zjLsnUV2axxIYGIQgw54SXxJ6/oXqnFvKRGmwbL7CVLzf 8/5Dt71GgVIOyBS12eWvsYZDaR0vbmunGN3LATh3u0NlY0i4TP+TNXlmFzNyHP2+SV7LbG0crcWc tWETjrMHbezxqNag3LIULtofqZdEW91khfmkiPWw2towjltnwTySj8zJ++qCXU+lNO5amyAWD+qt o5UH8/S1CcCuauhtlH7+DE7jRl22UDYdc5Q2053XNK4kTGXfJc3B8sl8idkQZMb+ekNjQi33XG1+ ELtREyEgAhgzJXXLYLkqRe53w1ko6wD3QyNwLlowJ4oj/2zZcVzaOR4VQQSJkmW61ZRUKQ6vHho7 UiW00RVjOO5HbH7HBIbYC1VttT6+C3uy/K+7Hnpl3tS89TLv9cI6qtjO0qCpkQxuIG7APICm1KGx FQBwAhe6lLpDcFfj3JqxuLwmkAYlCLeTgqD4b4+Ckb1RqpA3PI2I+mKS0Aklh+NRhighETxDkQCh r0wCVql2/H0Jl/tyjuOwrDvGgyY1f0R8KJOB5a8LHMBRGEMi41Qh2NKL8IJqUChJOCNpIua40tRu EYAbCj48FK6+OxIUCjPN2gxlwfZnnLndFLBpoZYr9j3sZwxS8DaJQD5r4GLuJdDWD3hbWO7+cgDC O5Yc85pwIldD5ogqjMA2bvU5gAvsM+SxoB71lgcIAACUqhmbv5fn6LUH2mLszrALxw2YqlpBy08G lEktXTDiZQcKh51K7kc2UYU2IjLVtmhSTldvsoALhnT7UatsMhzzQpA0Vg0A/+lhnhT711oPmygG +on+RnbTL8d1HonEnW0zW46GUk84JM4dO3f2RgF5Fox4nqdLuGIDXJZzJSTRd6dMTPhyrPMSwgGy b1knAardLEHQmpN8S29Fu0RtDUtN993283peIUJt3GKmI4oZ2HqTSkANoL0jd2AenI+RQF59xGbW LjSqwZBP/x+KeWVQKdoNUpemilVZzNcJTNZFW2S7de0PurmxkdCuu9+7V0wD88tvH+gnhrxCv9Ln hrX59f0tRsMwR4G88mdVy6X34ORqX+1xGDk3F1oa2tdc6fcONDQOiwhyorSDsm0zvIhFSlnZ5bv+ cFdr+lrlmb208aiEfHovfBtCbOop3kZE3RF7HIWz07gjHW3YIrJjFv/aujxS+1bFO6/Uf+GD4foJ tdIQuPRJM1fLQawZJ622dNLSBBtDRmIgUQRAY98mblHhqEgjS/roEyrp9HwrIg5m67X2VLOZ11qE 9O7FT7impllQ+iHz7Io3QNHr0EQgXbvUyZAy5cD3Gmu7oBh8u5MWS7u9Q3ZRgZE0BAY8iLM85Pp0 VSCVZQFrpUmOv20HFV/oFFYhHxJnF3v02fEWbalX2mQGrPX+XLlgdPtcxMKqecNTg6r7HlmOGZ/M GQ8KFTbftUscmC6C8a7PXc32i4oQJSDHMIYINkaq+aetasxUB4RU1HuOn4Vip5II9refjZPGGdLU 92svGL55K+zrTm6vPDiO+wQTipymoJ64vSJYhOJH8p3kl94lGGWhfcDO/x+yg9W3y+ZPckHC30nr ulXsFc2uPp/AedRrAx5dt79odY3LD+AjgCJYrujdsGdwP9OTfiIItbUqLGtk4aYXjshK2D+Q3Fs5 O11Kl6LKfS3ufSF34WbvAPY5CbfiGZpecCQWcEUBaYaaLOcB7hj5FBwVoDRbggBLYhvuFTZ7i4My LB81Tge4REVfhxA815wQn1LVepidqbi2n3n2l/7fND86Xo+47QD/VYdBkVFzb1mLnTYOHyJWdVbf fNJurLnApMigYc4K3RM5QHSlcNRYTa+b11yXsezs6l1mugYQtBbqfUCBeTlVlTx82SueGMES3ZrC GL3Xtfa05WlEmACbnEYRFZhJHKutF+LQOg6jYLbCPnMFzcmNgSPodKd+aHVX9UvcSfxdU8tDF9pp 3xdZDSHe6DLXOfA3Tm0Mtam7BTr4OOE7V5BdCE7pc6fTCFLBo7md4IuuvuoLux8FnmWrNWC+Lq0d pKq7m8Y/8ybAW2X8HiIMnaCYre+hA4oVeDR98c83ioZr7YpqnUJ1cR7tFT+ta8YrFtFKL3w/cc4k vY+HW0RoLFTUa5HJunlw+52QVw9R7Kv3nmpUOF6FXZa/4hJbxJYFQBy0VoBq9guTb3ohfHWeCOSc hgWhiw4sI/XmuLsVD5PCio9/hM3bDxc5umlKruI8OBehKg2wsOtFUB61gC/mI8M+FfZ+hlbf72Ue 9PAfvj6w0xnBjowV6gZsCXq9sTgzadAoLHW6Layn+9Vkc+Hc3G8CEUi+8MhySL87ni2AIa0A0Ofj HDmBQ9lfKwYH/JecLU1GopdqSSQRGnQB32oE16PWuL3RlGyrHPIhDBmJ2grc2rb2cVX3EmmlHfMT 4dcE/XxczYEzRZ0BaZUtuk9IUobRt9MCQ6ov0fvuc58iLqe5XR6J9J85Aq/DXTO9cuQDizSlX7uk 7kok0pfnWX8T9gy+XwdGSDM8ycz0vWlSmguV3JODTT7osQzU+aDDShubAeuSNd412jgXPTF5JGO8 gXmHwQEbtKiqg6ELwBlEzWRc3dskwMpTa9KIYLV/XWhqlzLzygoCsulxQWKT37wCKnbNRERF1e+9 YTXT5Jl/UwqcS6fG8MwtzqJXB7WVED/W8vD7kk2wOgzaUDuzCwtV+w4Kqlc/FdNx2jnOnxvewamV ObG2yJvv1YGC+nQ0LCcQ1Sylibm2gHf+bTClJ4pui8KOOsQ4dPWKloqLXA4sG9H1Hn/2X5vTZiGX IB1m+P+dWTL0fUUz/zdz7oYe0tUz64P+Z203AXpngP7eGcf1PCojJLmfRfgqEEqSzLQB/9DENd4z U9CxwpjRq1+/S4zd7u/E+y+IhkQ5RJQKAU/UGKh5hYHJxIASoCWTeoO9HIBlln863YUivjRY0aTN 2dDxqabIKSXWsBqm4grwtW5zm1K46Burm5aUAFj6rpGLgqOiz9sh5bZDuAcXE3Ktdq22cBzUZo6t nzRiD+oUaF7Opg3Mid4ZVEkLt85din8+f13ED3ogE9THta+E79fOvhjXdiAVmarj5QBY91ywBn8M CbEigMeJMsQWJilj9RNrfuWo2+4mXQMenu91rcvhRUgJsafqAzD2mIVMTRkFWEWjbZrVK5v0r1e3 J1SixDSFX9fYLZz1BqkMesuqKMxqtfiUbPX8ceHpMt0S41Fd2+Ef8lcK2S8d37LolewZBLitKxY1 SnJ/nl7ibX3IJDbnTVgLt7XJINdlwCmoG1vwqLHB8/imbySYxvnXbPX756/gtEY+MN7G220Hs/10 Dp05HZ+vQRs5zqMH8KKV4FGI8/tWPBYqUqK7n7EVUzR5PWgAUugG+d0kl+Ktiu8cFCnwRjad0Gwj 5Nx2cF88bP+NVcAEEIeHqEG86W3mTbk9Y7H4rdWGC9ghofp7bqmyBfaPME12HRdQhd/hcHXKkWMM asmUYPkvPm05b+xL8abHZyZ77xC8ml+QfvxG7NZqjWcpTiZnAxbKe9MS9wkU8RK1t8ozE97u9xO2 FAfZNMiYRcC6ocVexNcbl6XSmyKiTVl15Gp8hntv3+49W3Hs18FCAQ5WAb+Ou7qk1m+ZurVDZjWO 7l/Y2HDpMbk3Zf+9HmY1GIZJMaeuUh41jNjhqsiyULeAGk7b9bJKBS3+/Ynr/+y79ajDJ/IpvNzW Cn84MNpUiZaltQMFz/CpHQz928xfKOQUNu4+MhkkGijwaYnyISNkVuPjG2f16/5exfuCPgn8WH9i i1hRxuNy04Ko6SUE25kj6br6S1nk17ddCmGQo32tY8XWpWlN8F7OOUblu8WFm9tN+YQV+DmxpNIj Kfib/ibSVWbV1kYghBkeLLRAB/BhlFG4hF6J/0HnyrEuAe+mWbaKklBozTZJqDct1IYpjLS5sfsZ jmvOcU/q4fKsSIw5zFyJl0ZKQnndNLJiPG7JAjhU4+fIqXvQqRxjUQi7Qf99PQiTr+tIeoIVqXg/ MA0Pec/gw5iZM+PoIX+SDpx0+yoyIIbEbEzMuJSzmIqXn5Lq+0VQemTEmHSB/otJeYMb0hWtyW5P IPxGEmIpP7mryhZ67mxRbv5SCDMaXTODvguZTXAd34QKb79hy8ZdPSeMZjKzvTnH/B4c7d5scGYG h0PUvNv9frKKV31X/OJ6xxCNvkT8aZzJiwv/Eop6sT/usxGA3MgPZNHSV1OAeg1/0gcbmbMgT+rH 5UISUAiTt5wW55ezsg/K8Ka3H5xYEVeBcGSvn1api8D2yqOuavtLLINjCps6TEcPpZl9Fd2+q6YG 0RSp64uQQE0QJNdNiWd7nyxcUmizYsT67ywtUTivyv0IcTijMyq0TVTnE7xE+td3Y2aBNSEAadyr K38SS3uFaVXB8my9yil6t/H5Noxml8O8IUjwMQ4rO+FRYe0ugnCTx/KrJOCWIoJeyOpgZMkmSgWG Nllm5Ew22NKQEaxVZuxgn2jjkdjGV5ycFQw+jVMaI6BRQG1j1SO5g2vgtWYr7IvxbE/h29PYy4JO UtWIYJidBTMlP3CH8tresXAX4ffKO2gAd/AY4lo0CKLUJMJN8uBmTDQyeCWAN/onz0/lP40XNGZc HxUWM8CRqJWlqCM0lEsoXWktwC7b+A/9FJqT1BVNb3uzaYoBT4Z553qahFvV1tKie/hdKp8uvCYq jpZRpT0JrOirlwS9jxF/T5H0sYjtDSlM0TrdwWKlkTi9JD9bkelPvniceRKDsUBcZm+5qWE6jND8 ca98JHSw8LkN0YEAiXZYdFXOjyKu5KymfXAiabm4mKi0tFh1f0YexKs42iwd4aYROQJpB+RdLWUI LtfHbCC76EZ5iwWWULIx1SAxTD5LscrIu0onFXhvY1Pwi4Na5UA/vavy1Og4SK/806FQOQzITJOB GUdQKNolKEgPkewezM8W1hDdKuAlf9jcwPqP9VS8wqbo6Ma+7HaKvik6GIeGyMLc0EW4/pSeoJEp ynLuVJRhfjBUktxdWilTVByUyM3hpACmqfvZUYUnDWLfhBy6OVtw/nsaT/TRu41T908SnNrKAAcL BPqyar+jXWUzQr7eSpQZHWaL3yi7LDmsZjxyYVByBWBNHppEJAcAHXfrEEz/QZ1A2wm8Z2G1g/d8 0tVTAGFYmO7tfdiUu3WkFK9eJjMNwOpuq/OzMsNvahs/fy1ZQQuCMq5OIpDjE3juxU6Qz52WNgDB lEZduwZo3WHS3ZvTiS3hJpjMZgwT4HicbIgMod53SR226Hpt1wnkb7hhrnGTzhqiRMmDViymPXcu 3AQWacxImyDmuFHJEjTLfzK0F3Tz5td8qF+IkDIwTtCTbNMOgnfw0mhIIHmS2qeEj9gP+oO9Jy4V /6Q93nXFfJps6z9Isb4TYIOZIp3CwdpBbJw3HjTqOZOOeudEXLksEAPA+v1IG3h91xUPYKFJikZo LGy+t78Ng+7PX38bmXZGECk855rhivLliifJV7UlhBd/pJyOwiQdlSTwvsxGTKSiyaJgSnprIfrs SSkuDdIUee0I3tw8N8mJpQa2fgHwEauoAzGQ3nQ9BMI10AcjXEEvoOWd+1vvRC2YrLDFMPxpDpRb lksqg3kMrmUOHVdbGb9H1Cbz+o93nkK2Drlc7JZMaCnuNuUzI7qt2IyxTwuCdpMR3hBsn6K2MrZr iSQ648DZ4vS7JbQFBwYzMvGBjCgRpfhK2TxPgfQ/N9H9JTh0SPmGIWPzu+oDKjvt2DPi2fqp1QDM XonpV6jSKIEVkFfkSWL8QPxOV8QlbANnpqB+w4UzG7b2INhitYAirq/YRqo6/b6K9Xxb/eufTdPv uwFWKv7ZZgN7fFwB5xj5vx9jUnxc0KC5T2jUh2L7I+UHy5OUn9BXSvE5NgrlUuhLZdeM9/lfXiNc aym9+ppo0pZSdGFZCtg7T0N4VzZ4aRDQhkiuLfKTe7+VyfP6DcRaeEjZsLKgD5ECGx6qwU9DN8a4 pS6qHMX4pOSyHtB1OfGQilsgLfVjTcXwI+9cDRrOmxZlj1MRyvsWzLcgPP/TTYS3JK1QL4eCtSLB GCBTDjcZEQ8yfkVHRrKJ9T/vrnVvevvxfdXHNLIbVTHs+TXNZPa9xWaS6UnKTvGLt/fKl8EfGuNF EtnCazB64wlj5sstBE0PVHYvbU5ftL5GYiasETCducQeA59IBBM45qVyxQmJK3cxHsJ17IiW41OU 4Ri9umIz6I0Oy7GmtGQuISEdj2dOVTv7LCHELDa+6KWzjAnVhTZj8FaWcwlNGGWh112Tu9v9i487 LEK/dmagg6Esyc7Mw9AGrb0gv9XfajyZQsagHNIVDLlfswk8+13DM+Ke258Lhq1VKxZNKhsDijqs y23IXch6Knj5e/bJ4ejz8SrPVZ4WieCZHK4i28Lr81MlgHkPyPJeTsS1aAyGA0uLZvu+OH4cHGrS pyHAfLWs/QzzbL25UMSFwstZ0YSRaz0e9iaETHYJ9Da4UvBqGLXfl5xFbJHTGuDXgf95FyS9JmkM vPjklRWjTtIgcNX6lLlSt4L8J+Dfh8LVlX+auVayydDWpUs4iRqbyeAgLaXwL/aKvPBt9SN15+mo 97ZPRXN6aEHAODgxoMzME6oarouyp9E7q7MnYdrraDttApNYDH7hlhL/J4wOnVe7RUI6AcmMjkWT /pOheUo45NcD/NK0BypM63Av6u0DkhTd32G58mYGfeyZV3cfA1c/N6t0PSALwA9UORLGnEXt0nKD yxV0Iz2M3vA9Eu0e5goN89nJnIu5pKAJ/fEryIkk7xLPrwjJHXDJt04QGGRX96xzjxl44m7FKmeV E7n81CpMV4kfCiR9DE69ZcSZ7Aq4/CqndTsonOJXKUFhUdYMOPN+tFqAuY/b91TpdLMsYyIcMEdj 6kKtdF22Os+D6pzP4Z2MUKpAzZKmFwZYtC5BX0tpNf3HoQMtmRSkci60/a3d2SPQQs/hA5mYi8Ca LmrPoAFtJyzzW1Nt+mOXFFUuxF6NO78XviLsiIF41d6FpysOa8Epow8rzmcdBRRbZU1rwxhqL7ue SFL2+RofDTaa54zoSdgyundLR1lTcNno57zLTzYL7HJKj0MfDMIXND8pfG11Jbk5BlxoLPsRx1vZ HghuhucPrmKC1RnaGiSUC06DLO8Qj4mC1qtfktY2lVNb7jNnyCM3BnSO/ciAGa6NIcKk6XyZ8h4B CV2BrbGHwMjuYNOlyBMR9uaHL5eKh6OTpSYJsD/Kx+XprxmScqt4z7SpoYgY4H2rWpvbF93frDxa xeWk0+ZDqx7rNGpWIKxqsB7ZGDpY7VWyffcz+xOpVig7tHZW0KaiPYpBO8+ahzS7jBCCz2fpwzUk 1paRxXStCzDkisfW3h/DweuZeE4LjhcN45NH4vgT7W4YGIQ4AduszZJgc91w2kkxHXPFIvQ+mryy ZZqnIn+8O/HLz8dBZ5XV6F+oA5Ctj/gvxQmX7pYmfdzXZBdVZzLHiUOAD4QIR2O6ldP736op6K+t Bgpv83PlbaiKI6KCrmO/j/SA9/gLnjLfqcLVAAP3mdd01jB81WFXw9fnj1k4P3IK+2xWwB5WXdI8 FHzRwg+KgicT73pm1jN2Hl8SZ5Pu1us+EK1bI8XMetiXL5YvoBuDA0IX89V5TcOP/jm8MB716oY7 owYR53V82ZhuD/BtsGTGwfJZNBJqkMErPAiZJBKuGQhCNIPDACNwq+Qrno3lkncRUPtPfTuC35Ko d22QrPLD94Sn6mQ+jQsLyUh+xVOBdZI655tPLvCG3V06uAXivZ7Fu5ostI1H5fIErJqNFRPfMgln YsJOxu5q4S79EJQuPb0FmkJdrhsLdBwSPKI0LRXppDFQqkRPhySAnygJk756XBCEnNQ3wzrTmeju serKZ5m31CJmFq6e6+dPLuD71yii1Vl5yQ+R5FChQVwlVTZ7Eo+hacMk35N/4ZI3uF8InCarIDAo fI9yv3YbJbHLSELy6jwIDX9I80FlA85JfSj228uQDxTZcC5XCFveQMWDpnJVnM5JaB6ATVS6K9zy Dg09MRKxRZMZoyDIEBhQYb/tJV3XrxqCZpGceSCfqMTy08TBFCkbYw7pBoZIsQaXJm98zP4Ji3dJ 22YYHssMXtv/n8ylkkVtgH77m8aqyElvLfW2vVhetFFFsPEHi5ZWklzaFICXboY62ZuI/PHwreAe Yl6dsGbB/igNwDzqn3FbsXH3XL1q3toZ93HwQ8BclS0RYwDExP3DRqKbqBxhjgntviSfrqkU6u9W ZGxyaCLzOUoL7SzbxngevdsjiXAlpNKoLJqRSiVhd1V73/jKUrxtamKJdSr+4Mz9tKBpTiItZIcv rfJsHtedAyUpzFBYqyx0V1+pmpMP9jrhzpGv7afr5YPK+lpxPphrThNdbMHilBieLw01PTm3tyhL IZPHNmXAMJCPO36zHmQwBtDsj0aNbfHyQZu1iDlOVI1NGOQHVO/czhRkyqbVWsy8mqdXEvxIwcy6 RmF9xWmmCF7FPUN65es+N9aNotf1dd+IZ3VYbHMPTmD+GhEqBjstsWQXBnOoKbl1HJ22mhltjYdP 6Eh4CbAyfR1/H+/piEq72e+8un53XG896k8X2glWxxnSPxpO9HybX2PEb54bPvaRXKa2sduVXrhq zF5xRGwJ6qmWz9/aAVLbdUiy2KQNFq+0LATHIyzAsGe4e/gfxYGJc22GlQG8f0mEZ+4NGX9xCCpq t/aaM95BdZUf9G6akRjnvaXOTsadQUopGWaIrsiZqPZliJ1UA9RytzXQNT71Mv9IB2iIblK8+P5j iUr9Tt5x+X26U9fDk+z4Sw4RhyJ51UMhAu4Jizo8JnI4+/gomeVCaexbsNLUtj0c/g19h0wVKgXB Nc/oIPlJt8wfc/qg+5TYp5SsFYMh8Mc3ZoWIglSr3fegVlKBR3tHHjKerOnePK2wi6ZHYy4BXPPw fowPV8VqiGaKomR+yzqVxu2rrPjAGot8cFf6Mb9A643aCxPdlxY1tuVe73R1Z1yHaE+8eAb2DxS6 Ud6Ao39F5wqEMRXeBwm3bWliIwm5U988gNYt9EVmK5f0kJkGQ8so0UZly7ZhuDbYldng9BevfuGT TcVXEFYwy4Gco6fHqLJvjF9fsXnAwhsZDI5+EFcRnN8ezWs8mdt2v+PgEtpo3MFj5IXyGpoZ5XR9 YUQcwRwxakooyXuCawZcU+ZDbn6w4NUtC8BAHxXXh147uT1yFwoJv39fX5wKwQHPYExFd5gqTsHe tejs5xoEZUzHFBmDUbxQK10s/NjEJWuU95ikreXUWXiKxJHEaRt0diLLVz8c2jwaSQFL45CKnRbc yC3wRkE7lhbizZClqkzdBnJy+KLi/lrUJkWaDLUpAXtneN0eYeiuTgrQ+U8AnV/r4+gHIku3jqZg wUgqqlq7V+UdDHGPqr7wsu9Kov9j73YBq1WBga4rOmr/gZxPxuEVw7ggryP8XeJ0dnprb+CZpOXB qbvyRD0c9Mo1JCjGdwSfBPzNxfw1M1MjeP3jUQ9ybVpmQAeQzQaL66sLOHninDGRRmYNHDIsirRK psiin6vhknrGFAE6CNNMOjaz0lqM5Wlr3EyHHoYmSTWgh+g7OhAoJDm9U36TuQbn2YjKp4DNm4Cs aEy8z1rEU6FNFqHTOm4fAwWtnpRIYA2k1lCfDpxvekxwYgdIg1YeiiFSUJ7L2Lrafy3rb4+xI0+p NamTKqlWvCDle2RA7HVSZr2YdFA8t/iZba8UsAZbAP1+NZKH/wrWaRTLx70vSTfNExxqsHTXxkje b6RIqn/kIkFm3C+TgZfmCo0cy4xNLWyHR3EJGyyv+u4hkyrd13xYUw/Sj3iaQNUn8RWheoNFzGWJ 4Tv7/YRAuHaPT1c9diqU386GSyM2/gXyX979ZhbUFv0fWSXc3+Xuyut595nF5V+uVMzIeGhJHTcS wF3rgNR2AVqHy+ZkatQB6+GIZ8O18xttXqbdA8x7aXIsaMzcr3xkHsVkomQ3GgDwElYrA4hCVnKC /qXYmET8nTPgjFk/g+/XGVYtLBKC2/v+y3U5zWCCfy86YVWbxFQ4YUFLprjr+ak2XRnfhY2NbY5h ellcbmcVF0JMZ5dcmiUT5NSWG8oVw5PDF/wcVO9S4SNF3orO6U78JksfYHtuI1oVvdSGLrffi/ij OwcnExg42X5YsBExhBUGSe/AYaNR461RGLuXauvFwRlXgZG8hQQBQBrqInytLBBHD9mBC1ve+TcE 4bNb1gO/SKIQj2hS `protect end_protected

mit

cb4b3e159a7400c2dd5ca33d7a1c0994

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_LMEM_2_CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

e62a978e767ad8d7a521a9fa3ae71371

malkadi/FGPU

RTL/RTM.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity RTM is -- ports {{{ port( clk : in std_logic; rtm_rdAddr : in unsigned(RTM_ADDR_W-1 downto 0); -- level 13. rtm_rdData : out unsigned(RTM_DATA_W-1 downto 0) := (others=> '0'); -- level 15. rtm_wrData_cv : in unsigned(DATA_W-1 downto 0) := (others => '0'); rtm_wrAddr_cv : in unsigned(N_WF_CU_W+2-1 downto 0) := (others => '0'); rtm_we_cv : in std_logic := '0'; rtm_wrAddr_wg : in unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); rtm_wrData_wg : in unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); -- from _wg_dispatcher rtm_we_wg : in std_logic; WGsDispatched : in std_logic; start_CUs : in std_logic; nrst : in std_logic ); -- }}} end RTM; architecture Behavioral of RTM is -- signals definitions {{{ signal rtm : rtm_ram_type(0 to RTM_SIZE-1) := (others => (others => '0')); signal rtm_wrData, rtm_wrData_n : unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); signal rtm_rdData_n : unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); signal rtm_wrAddr, rtm_wrAddr_n : unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); signal rtm_we, rtm_we_n : std_logic := '0'; type st_rtm_write_type is (wg_dispatcher, cv_Dispatcher); signal st_rtm_write : st_rtm_write_type := wg_dispatcher; signal st_rtm_write_n : st_rtm_write_type := wg_dispatcher; -- }}} begin -- Local Memory -------------------------------------------------------------------------------------------{{{ ---------------------------------------------------------------------------------------------------------}}} -- RTM ram ------------------------------------------------------------------------------------ {{{ process(clk) begin if rising_edge(clk) then if rtm_we = '1' then rtm(to_integer(rtm_wrAddr)) <= rtm_wrData; end if; rtm_rdData_n <= rtm(to_integer(rtm_rdAddr)); -- @ 14. rtm_rdData <= rtm_rdData_n; -- @ 15. end if; end process; process(clk) begin if rising_edge(clk) then rtm_wrData <= rtm_wrData_n; rtm_wrAddr <= rtm_wrAddr_n; if nrst = '0' then st_rtm_write <= wg_dispatcher; rtm_we <= '0'; else st_rtm_write <= st_rtm_write_n; rtm_we <= rtm_we_n; end if; end if; end process; process(st_rtm_write, start_CUs, WGsDispatched, rtm_wrAddr_cv, rtm_wrAddr_wg, rtm_wrData_cv, rtm_wrData_wg, rtm_we_cv, rtm_we_wg, rtm_wrData, rtm_wrAddr, rtm_we) begin st_rtm_write_n <= st_rtm_write; rtm_wrAddr_n <= rtm_wrAddr; rtm_wrData_n <= rtm_wrData; rtm_we_n <= rtm_we; case st_rtm_write is when wg_dispatcher => if start_CUs = '1' then st_rtm_write_n <= cv_Dispatcher; end if; rtm_wrAddr_n <= rtm_wrAddr_wg; rtm_wrData_n <= rtm_wrData_wg; rtm_we_n <= rtm_we_wg; when cv_Dispatcher => if WGsDispatched = '1' then st_rtm_write_n <= wg_dispatcher; end if; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto PHASE_W) <= rtm_wrAddr_cv; rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= rtm_wrData_cv; rtm_we_n <= rtm_we_cv; end case; end process; ---------------------------------------------------------------------------------------------------------}}} end Behavioral;

gpl-3.0

f2c9550fe2bae5d2270ff44660f3ff33

malkadi/FGPU

RTL/FGPU.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ------------------------------------------------------------------------------------------------- }}} entity FGPU is -- Generics & ports {{{ port( clk : in std_logic; -- Contorl Interface - AXI LITE SLAVE {{{ s0_awaddr : in std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0); s0_awprot : in std_logic_vector(2 downto 0); s0_awvalid : in std_logic; s0_awready : out std_logic := '0'; s0_wdata : in std_logic_vector(DATA_W-1 downto 0); s0_wstrb : in std_logic_vector((DATA_W/8)-1 downto 0); s0_wvalid : in std_logic; s0_wready : out std_logic := '0'; s0_bresp : out std_logic_vector(1 downto 0) := (others=>'0'); s0_bvalid : out std_logic := '0'; s0_bready : in std_logic; s0_araddr : in std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0); s0_arprot : in std_logic_vector(2 downto 0); s0_arvalid : in std_logic; s0_arready : out std_logic := '0'; s0_rdata : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); s0_rresp : out std_logic_vector(1 downto 0) := (others=>'0'); s0_rvalid : out std_logic := '0'; s0_rready : in std_logic; -- }}} -- AXI MASTER 0 {{{ -- ar channel m0_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); m0_arlen : out std_logic_vector(7 downto 0):= (others=>'0'); m0_arsize : out std_logic_vector(2 downto 0):= (others=>'0'); m0_arburst : out std_logic_vector(1 downto 0):= (others=>'0'); m0_arvalid : out std_logic := '0'; m0_arready : in std_logic; m0_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel m0_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); m0_rresp : in std_logic_vector(1 downto 0):= (others=>'0'); m0_rlast : in std_logic; m0_rvalid : in std_logic; m0_rready : out std_logic := '0'; m0_rid : in std_logic_vector(ID_WIDTH-1 downto 0); -- aw channel m0_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); m0_awvalid : out std_logic := '0'; m0_awready : in std_logic; m0_awlen : out std_logic_vector(7 downto 0):= (others=>'0'); m0_awsize : out std_logic_vector(2 downto 0):= (others=>'0'); m0_awburst : out std_logic_vector(1 downto 0):= (others=>'0'); m0_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel m0_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); m0_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); m0_wlast : out std_logic := '0'; m0_wvalid : out std_logic := '0'; m0_wready : in std_logic; -- b channel m0_bvalid : in std_logic; m0_bready : out std_logic := '0'; m0_bid : in std_logic_vector(ID_WIDTH-1 downto 0); -- }}}} -- AXI MASTER 1 {{{ -- ar channel m1_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); m1_arlen : out std_logic_vector(7 downto 0):= (others=>'0'); m1_arsize : out std_logic_vector(2 downto 0):= (others=>'0'); m1_arburst : out std_logic_vector(1 downto 0):= (others=>'0'); m1_arvalid : out std_logic := '0'; m1_arready : in std_logic; m1_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel m1_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); m1_rresp : in std_logic_vector(1 downto 0):= (others=>'0'); m1_rlast : in std_logic; m1_rvalid : in std_logic; m1_rready : out std_logic := '0'; m1_rid : in std_logic_vector(ID_WIDTH-1 downto 0); -- -- aw channel m1_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); m1_awvalid : out std_logic := '0'; m1_awready : in std_logic; m1_awlen : out std_logic_vector(7 downto 0):= (others=>'0'); m1_awsize : out std_logic_vector(2 downto 0):= (others=>'0'); m1_awburst : out std_logic_vector(1 downto 0):= (others=>'0'); m1_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel m1_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); m1_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); m1_wlast : out std_logic := '0'; m1_wvalid : out std_logic := '0'; m1_wready : in std_logic; -- b channel m1_bvalid : in std_logic; m1_bready : out std_logic := '0'; m1_bid : in std_logic_vector(ID_WIDTH-1 downto 0); -- }}}} -- AXI MASTER 2 {{{ -- ar channel m2_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); m2_arlen : out std_logic_vector(7 downto 0):= (others=>'0'); m2_arsize : out std_logic_vector(2 downto 0):= (others=>'0'); m2_arburst : out std_logic_vector(1 downto 0):= (others=>'0'); m2_arvalid : out std_logic := '0'; m2_arready : in std_logic; m2_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel m2_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); m2_rresp : in std_logic_vector(1 downto 0):= (others=>'0'); m2_rlast : in std_logic; m2_rvalid : in std_logic; m2_rready : out std_logic := '0'; m2_rid : in std_logic_vector(ID_WIDTH-1 downto 0); -- -- aw channel m2_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); m2_awvalid : out std_logic := '0'; m2_awready : in std_logic; m2_awlen : out std_logic_vector(7 downto 0):= (others=>'0'); m2_awsize : out std_logic_vector(2 downto 0):= (others=>'0'); m2_awburst : out std_logic_vector(1 downto 0):= (others=>'0'); m2_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel m2_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); m2_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); m2_wlast : out std_logic := '0'; m2_wvalid : out std_logic := '0'; m2_wready : in std_logic; -- b channel m2_bvalid : in std_logic; m2_bready : out std_logic := '0'; m2_bid : in std_logic_vector(ID_WIDTH-1 downto 0); -- }}}} -- AXI MASTER 3 {{{ -- ar channel m3_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); m3_arlen : out std_logic_vector(7 downto 0):= (others=>'0'); m3_arsize : out std_logic_vector(2 downto 0):= (others=>'0'); m3_arburst : out std_logic_vector(1 downto 0):= (others=>'0'); m3_arvalid : out std_logic := '0'; m3_arready : in std_logic; m3_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel m3_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); m3_rresp : in std_logic_vector(1 downto 0):= (others=>'0'); m3_rlast : in std_logic; m3_rvalid : in std_logic; m3_rready : out std_logic := '0'; m3_rid : in std_logic_vector(ID_WIDTH-1 downto 0); -- -- aw channel m3_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); m3_awvalid : out std_logic := '0'; m3_awready : in std_logic; m3_awlen : out std_logic_vector(7 downto 0):= (others=>'0'); m3_awsize : out std_logic_vector(2 downto 0):= (others=>'0'); m3_awburst : out std_logic_vector(1 downto 0):= (others=>'0'); m3_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel m3_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); m3_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); m3_wlast : out std_logic := '0'; m3_wvalid : out std_logic := '0'; m3_wready : in std_logic; -- b channel m3_bvalid : in std_logic; m3_bready : out std_logic := '0'; m3_bid : in std_logic_vector(ID_WIDTH-1 downto 0); -- }}}} nrst : in std_logic ); -- ports }}} end FGPU; architecture Behavioral of FGPU is -- internal signals definitions {{{ signal s0_awready_i, s0_bvalid_i : std_logic := '0'; signal s0_wready_i, s0_arready_i : std_logic := '0'; signal nrst_CUs : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal nrst_gmem_cntrl : std_logic := '0'; signal nrst_wgDispatcher : std_logic := '0'; -- }}} -- slave axi interface {{{ signal mainProc_we : std_logic := '0'; signal mainProc_wrAddr : std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0) := (others=>'0'); signal mainProc_rdAddr : unsigned(INTERFCE_W_ADDR_W-1 downto 0) := (others=>'0'); signal s0_rvalid_vec : std_logic_vector(3 downto 0) := (others=>'0'); signal s0_wdata_d0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- }}} -- general signals definitions {{{ signal KRNL_SCHEDULER_RAM : KRNL_SCHEDULER_RAM_type := init_krnl_ram("krnl_ram.mif"); -- signal cram_b1 : CRAM_type := init_CRAM("cram_LUdecomposition.mif", 930); signal cram_b1 : CRAM_type := init_CRAM("cram.mif", 3000); signal KRNL_SCH_we : std_logic := '0'; signal krnl_sch_rdData : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal krnl_sch_rdData_n : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal krnl_sch_rdAddr : unsigned(KRNL_SCH_ADDR_W-1 downto 0) := (others => '0'); signal krnl_sch_rdAddr_WGD : std_logic_vector(KRNL_SCH_ADDR_W-1 downto 0) := (others => '0'); signal CRAM_we : std_logic := '0'; -- signal cram_rdData, cram_rdData_n : SLV32_ARRAY(CRAM_BLOCKS-1 downto 0) := (others=>(others=>'0')); -- signal cram_rdAddr, cram_rdAddr_d0 : CRAM_ADDR_ARRAY(CRAM_BLOCKS-1 downto 0) := (others=>(others=>'0')); signal cram_rdData, cram_rdData_n : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal cram_rdData_vec : slv32_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal cram_rdAddr, cram_rdAddr_d0 : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal cram_rdAddr_d0_vec : cram_addr_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal status_reg : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal regFile_we, regFile_we_d0 : std_logic := '0'; signal Rstat : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others => '0'); signal Rstart : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others => '0'); signal RcleanCache : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others=>'0'); signal RInitiate : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others=>'0'); type WG_dispatcher_state_type is (idle, st1_dispatch); signal st_wg_disp, st_wg_disp_n : WG_dispatcher_state_type := idle; signal new_krnl_indx : integer range 0 to NEW_KRNL_MAX_INDX-1 := 0; signal new_krnl_field : std_logic_vector(NEW_KRNL_DESC_W-1 downto 0) := (others =>'0'); signal start_kernel, clean_cache : std_logic := '0'; signal start_CUs, initialize_d0 : std_logic := '0'; -- informs all CUs to start working after initialization phase of the WG_dispatcher is finished signal start_CUs_vec : std_logic_vector(max(N_CU-1, 0) downto 0) := (others=>'0'); -- to improve timing signal finish_exec : std_logic := '0'; -- high when execution of a kernel is done signal WGsDispatched : std_logic := '0'; -- high when WG_Dispatcher has schedules all WGs signal finish_exec_d0 : std_logic := '0'; signal finish_krnl_indx : integer range 0 to NEW_KRNL_MAX_INDX-1 := 0; signal wg_req : std_logic_vector(N_CU-1 downto 0) := (others => '0'); signal wg_ack : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); type wg_req_vec_type is array(natural range <>) of std_logic_vector(N_CU-1 downto 0); signal wg_req_vec : wg_req_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal wg_ack_vec : wg_req_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal CU_cram_rqst : std_logic_vector(N_CU-1 downto 0) := (others => '0'); signal sch_rqst_n_WFs_m1 : unsigned(N_WF_CU_W-1 downto 0) := (others=>'0'); type sch_rqst_n_WFs_m1_vec_type is array (natural range <>) of unsigned(N_WF_CU_W-1 downto 0); signal sch_rqst_n_WFs_m1_vec : sch_rqst_n_WFs_m1_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal cram_served_CUs : std_logic := '0'; -- one-bit-toggle to serve different CUs when fetching instructions signal CU_cram_rdAddr : CRAM_ADDR_ARRay(N_CU-1 downto 0) := (others =>(others=>'0')); signal start_addr : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); -- the address of the first instruction to be fetched signal start_addr_vec : cram_addr_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); -- just to improve timing signal rdData_alu_en : alu_en_vec_type(N_CU-1 downto 0) := (others=>(others=>'0')); signal rdAddr_alu_en : alu_en_rdAddr_type(N_CU-1 downto 0) := (others=>(others=>'0')); signal rtm_wrAddr_wg : unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); type rtm_addr_vec_type is array (natural range<>) of unsigned(RTM_ADDR_W-1 downto 0); signal rtm_wrAddr_wg_vec : rtm_addr_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal rtm_wrData_wg : unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); signal rtm_wrData_wg_vec : rtm_ram_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal rtm_we_wg : std_logic := '0'; signal rtm_we_wg_vec : std_logic_vector(max(N_CU-1, 0) downto 0) := (others=>'0'); signal wg_info : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal wg_info_vec : slv32_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); -- }}} -- global memory ---------------------------------------------------- {{{ -- cache signals function distribute_cache_rd_ports_on_CUs (n_cus: integer) return nat_array is -- {{{ variable res: nat_array(n_cus-1 downto 0) := (others=>0); -- res(0) will have the maximum distance to the global memory controller begin for i in 0 to n_cus-1 loop res(i) := n_cus/2*(i mod 2) + (i/2); end loop; return res; end; -- }}} constant cache_rd_port_to_CU : nat_array(N_CU-1 downto 0) := distribute_cache_rd_ports_on_CUs(N_CU); type cache_rdData_vec_type is array(natural range <>) of std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0); signal cache_rdData_vec : cache_rdData_vec_type(N_CU downto 0) := (others=>(others=>'0')); signal atomic_rdData_vec : slv32_array(N_CU downto 0) := (others=>(others=>'0')); type rdData_v_vec_type is array(natural range <>) of std_logic_vector(N_CU-1 downto 0); signal atomic_rdData_v_vec : rdData_v_vec_type(N_CU downto 0) := (others=>(others=>'0')); type atomic_sgntr_vec_type is array(natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); signal atomic_sgntr_vec : atomic_sgntr_vec_type(N_CU downto 0) := (others=>(others=>'0')); signal cache_rdAddr_vec : GMEM_ADDR_ARRAY_NO_BANK(N_CU downto 0) := (others=>(others=>'0')); signal cache_rdAck_vec : rdData_v_vec_type(N_CU downto 0) := (others=>(others=>'0')); signal cache_rdData_out : std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0) := (others=>'0'); signal cache_rdAddr_out : unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0) := (others=>'0'); signal cache_rdAck_out : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal atomic_rdData : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal atomic_rdData_v : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal atomic_sgntr : std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); signal cu_gmem_valid, cu_gmem_ready : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal cu_gmem_we : be_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_gmem_rnw, cu_gmem_atomic : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal cu_gmem_atomic_sgntr : atomic_sgntr_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_rqst_addr : GMEM_WORD_ADDR_ARRAY(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_gmem_wrData : SLV32_ARRAY(N_CU-1 downto 0) := (others=>(others=>'0')); signal wf_active : wf_active_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal CU_gmem_idle : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal CUs_gmem_idle : std_logic := '0'; signal axi_araddr : GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_arvalid, axi_arready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_rdata : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_rlast : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_rvalid, axi_rready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_awaddr : GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_awvalid, axi_awready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_wdata : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_wstrb : gmem_be_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_wlast : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_wvalid, axi_wready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_bvalid, axi_bready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_arid, axi_rid : id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_awid, axi_bid : id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); --}}} begin -- asserts -------------------------------------------------------------------------------------------{{{ assert KRNL_SCH_ADDR_W <= CRAM_ADDR_W severity failure; --Code RAM is the biggest block assert CRAM_ADDR_W <= INTERFCE_W_ADDR_W-2 severity failure; --there should be two bits to choose among: HW_sch_RAM, CRAM and the register file assert DATA_W >= GMEM_ADDR_W report "the width bus between a gmem_ctrl_CV and gmem_ctrl is GMEM_DATA_W" severity failure; assert CV_SIZE = 8 or CV_SIZE = 4 severity failure; assert 2**N_CU_STATIONS_W >= N_STATIONS_ALU*CV_SIZE report "increase N_STATIONS_W" severity failure; assert N_TAG_MANAGERS_W > 0 report "There should be at least two tag managers" severity failure; assert DATA_W = 32; -- assert CRAM_BLOCKS = 1 or CRAM_BLOCKS = 2; -- assert N_AXI = 1 or N_AXI = 2; -- assert N_AXI = 1 or N_AXI = 2; ---------------------------------------------------------------------------------------------------------}}} -- interal signals assignments --------------------------------------------------------------------------{{{ s0_awready <= s0_awready_i; s0_bvalid <= s0_bvalid_i; s0_wready <= s0_wready_i; s0_arready <= s0_arready_i; ---------------------------------------------------------------------------------------------------------}}} -- slave axi interface ----------------------------------------------------------------------------------{{{ -- aw & w channels process(clk) begin if rising_edge(clk) then if nrst = '0' then s0_awready_i <= '0'; s0_wready_i <= '0'; mainProc_we <= '0'; mainProc_wrAddr <= (others=>'0'); else if s0_awready_i = '0' and s0_awvalid = '1' and s0_wvalid = '1' then s0_awready_i <= '1'; mainProc_wrAddr <= s0_awaddr; s0_wready_i <= '1'; mainProc_we <= '1'; else s0_awready_i <= '0'; s0_wready_i <= '0'; mainProc_we <= '0'; end if; end if; end if; end process; -- b channel process(clk) begin if rising_edge(clk) then if nrst = '0' then s0_bvalid_i <= '0'; else if s0_awready_i = '1' and s0_awvalid = '1' and s0_wready_i = '1' and s0_wvalid = '1' and s0_bvalid_i = '0' then s0_bvalid_i <= '1'; elsif s0_bready = '1' and s0_bvalid_i = '1' then s0_bvalid_i <= '0'; end if; end if; end if; end process; -- ar channel process(clk) begin if rising_edge(clk) then -- if nrst = '0' then -- s_arready_i <= '0'; -- mainProc_rdAddr <= (others=>'0'); -- else if s0_arready_i = '0' and s0_arvalid = '1' then s0_arready_i <= '1'; mainProc_rdAddr <= unsigned(s0_araddr); else s0_arready_i <= '0'; end if; -- end if; end if; end process; -- r channel process(clk) begin if rising_edge(clk) then if nrst = '0' then s0_rvalid_vec <= (others=>'0'); s0_rvalid <= '0'; else s0_rvalid_vec(s0_rvalid_vec'high-1 downto 0) <= s0_rvalid_vec(s0_rvalid_vec'high downto 1); if s0_arready_i = '1' and s0_arvalid = '1' and s0_rvalid_vec(s0_rvalid_vec'high) = '0' then s0_rvalid_vec(s0_rvalid_vec'high) <= '1'; else s0_rvalid_vec(s0_rvalid_vec'high) <= '0'; end if; if s0_rvalid_vec(1) = '1' then s0_rvalid <= '1'; end if; if s0_rvalid_vec(0) = '1' then if s0_rready = '1' then s0_rvalid <= '0'; else s0_rvalid_vec(0) <= '1'; end if; end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then if mainProc_rdAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "00" then -- HW_scheduler_ram s0_rdata <= krnl_sch_rdData; elsif mainProc_rdAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "01" then -- Code_ram s0_rdata <= cram_rdData; -- s0_rdata <= cram_rdData(0); else -- "10", register file case mainProc_rdAddr(1 downto 0) is when "00" => s0_rdata(NEW_KRNL_MAX_INDX-1 downto 0) <= Rstat(NEW_KRNL_MAX_INDX-1 downto 0); when "10" => s0_rdata(NEW_KRNL_MAX_INDX-1 downto 0) <= RcleanCache(NEW_KRNL_MAX_INDX-1 downto 0); when others => s0_rdata(NEW_KRNL_MAX_INDX-1 downto 0) <= RInitiate(NEW_KRNL_MAX_INDX-1 downto 0); end case; s0_rdata(DATA_W-1 downto NEW_KRNL_MAX_INDX) <= (others=>'0'); end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- fixed signals --------------------------------------------------------------------------------- {{{ s0_bresp <= "00"; s0_rresp <= "00"; ------------------------------------------------------------------------------------------------- }}} -- HW Scheduler RAM ----------------------------------------------------------------------------- {{{ Krnl_Scheduler: process (clk) begin if rising_edge(clk) then krnl_sch_rdData_n <= KRNL_SCHEDULER_RAM(to_integer(krnl_sch_rdAddr)); krnl_sch_rdData <= krnl_sch_rdData_n; if KRNL_SCH_we = '1' then KRNL_SCHEDULER_RAM(to_integer(unsigned(mainProc_wrAddr(KRNL_SCH_ADDR_W-1 downto 0)))) <= s0_wdata_d0; end if; end if; end process; krnl_sch_rdAddr <= mainProc_rdAddr(KRNL_SCH_ADDR_W-1 downto 0) when st_wg_disp = idle else unsigned(krnl_sch_rdAddr_WGD); KRNL_SCH_we <= '1' when mainProc_wrAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "00" and mainProc_we = '1' else '0'; ------------------------------------------------------------------------------------------------- }}} -- Code RAM -------------------------------------------------------------------------------------- {{{ CRAM_inst: process (clk) begin if rising_edge(clk) then nrst_wgDispatcher <= nrst; cram_rdData_n <= cram_b1(to_integer(cram_rdAddr)); -- cram_rdData_n <= cram_b1(to_integer(cram_rdAddr(0))); -- cram_rdData_n(0) <= cram_b1(to_integer(cram_rdAddr(0))); if CRAM_we = '1' then cram_b1(to_integer(unsigned(mainProc_wrAddr(CRAM_ADDR_W-1 downto 0)))) <= s0_wdata_d0; end if; -- if CRAM_BLOCKS > 1 then -- cram_rdData_n(CRAM_BLOCKS-1) <= cram_b2(to_integer(cram_rdAddr(CRAM_BLOCKS-1))); -- if CRAM_we = '1' then -- cram_b2(to_integer(unsigned(mainProc_wrAddr(CRAM_ADDR_W-1 downto 0)))) <= s0_wdata_d0; -- end if; -- end if; cram_rdData <= cram_rdData_n; end if; end process; CRAM_we <= '1' when mainProc_wrAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "01" and mainProc_we = '1' else '0'; process(clk) begin if rising_edge(clk) then cram_rdAddr_d0 <= cram_rdAddr; cram_rdAddr <= mainProc_rdAddr(CRAM_ADDR_W-1 downto 0); -- cram_rdAddr(0) <= mainProc_rdAddr(CRAM_ADDR_W-1 downto 0); cram_served_CUs <= not cram_served_CUs; if cram_served_CUs = '0' then for i in 0 to max(N_CU/2-1,0) loop if CU_cram_rqst(i) = '1' then cram_rdAddr <= CU_cram_rdAddr(i); -- cram_rdAddr(i mod CRAM_BLOCKS) <= CU_cram_rdAddr(i); end if; end loop; else for i in N_CU/2 to N_CU-1 loop if CU_cram_rqst(i) = '1' then cram_rdAddr <= CU_cram_rdAddr(i); -- cram_rdAddr(i mod CRAM_BLOCKS) <= CU_cram_rdAddr(i); end if; end loop; end if; end if; end process; ------------------------------------------------------------------------------------------------- }}} -- WG dispatcher -------------------------------------------------------------------------------------- {{{ WG_dispatcher_inst: entity WG_dispatcher port map( krnl_indx => new_krnl_indx, start => start_kernel, initialize_d0 => initialize_d0, krnl_sch_rdAddr => krnl_sch_rdAddr_WGD, krnl_sch_rdData => krnl_sch_rdData, finish_krnl_indx => finish_krnl_indx, -- to CUs start_exec => start_CUs, req => wg_req, ack => wg_ack, rtm_wrAddr => rtm_wrAddr_wg, rtm_wrData => rtm_wrData_wg, rtm_we => rtm_we_wg, sch_rqst_n_WFs_m1 => sch_rqst_n_WFs_m1, finish => WGsDispatched, start_addr => start_addr, rdData_alu_en => rdData_alu_en, wg_info => wg_info, -- from CUs wf_active => wf_active, rdAddr_alu_en => rdAddr_alu_en, clk => clk, nrst => nrst_wgDispatcher ); ------------------------------------------------------------------------------------------------- }}} -- compute units -------------------------------------------------------------------------------------- {{{ compute_units_i: for i in 0 to N_CU-1 generate begin compute_unit_inst: entity compute_unit port map( clk => clk, wf_active => wf_active(i), WGsDispatched => WGsDispatched, nrst => nrst_CUs(i), cram_rdAddr => CU_cram_rdAddr(i), cram_rdData => cram_rdData_vec(i), -- cram_rdData => cram_rdData(i mod CRAM_BLOCKS), cram_rqst => CU_cram_rqst(i), cram_rdAddr_conf => cram_rdAddr_d0_vec(i), -- cram_rdAddr_conf => cram_rdAddr_d0(i mod CRAM_BLOCKS), start_addr => start_addr_vec(i), start_CUs => start_CUs_vec(i), sch_rqst_n_wfs_m1 => sch_rqst_n_WFs_m1_vec(i), sch_rqst => wg_req_vec(i)(i), sch_ack => wg_ack(i), wg_info => unsigned(wg_info_vec(i)), rtm_wrAddr_wg => rtm_wrAddr_wg_vec(i), rtm_wrData_wg => rtm_wrData_wg_vec(i), rtm_we_wg => rtm_we_wg_vec(i), rdData_alu_en => rdData_alu_en(i), rdAddr_alu_en => rdAddr_alu_en(i), gmem_valid => cu_gmem_valid(i), gmem_we => cu_gmem_we(i), gmem_rnw => cu_gmem_rnw(i), gmem_atomic => cu_gmem_atomic(i), gmem_atomic_sgntr => cu_gmem_atomic_sgntr(i), gmem_rqst_addr => cu_rqst_addr(i), gmem_ready => cu_gmem_ready(i), gmem_wrData => cu_gmem_wrData(i), --cache read data cache_rdAddr => cache_rdAddr_vec(cache_rd_port_to_CU(i)), cache_rdAck => cache_rdAck_vec(cache_rd_port_to_CU(i))(i), cache_rdData => cache_rdData_vec(cache_rd_port_to_CU(i)), atomic_rdData => atomic_rdData_vec(cache_rd_port_to_CU(i)), atomic_rdData_v => atomic_rdData_v_vec(cache_rd_port_to_CU(i))(i), atomic_sgntr => atomic_sgntr_vec(cache_rd_port_to_CU(i)), gmem_cntrl_idle => CU_gmem_idle(i) -- loc_mem_rdAddr_dummy => loc_mem_rdAddr_dummy(DATA_W*(i+1)-1 downto i*DATA_W) ); end generate; process(clk) begin if rising_edge(clk) then cache_rdAck_vec(cache_rdAck_vec'high) <= cache_rdAck_out; cache_rdAck_vec(cache_rdAck_vec'high-1 downto 0) <= cache_rdAck_vec(cache_rdAck_vec'high downto 1); cache_rdAddr_vec(cache_rdAddr_vec'high) <= cache_rdAddr_out; cache_rdAddr_vec(cache_rdAddr_vec'high-1 downto 0) <= cache_rdAddr_vec(cache_rdAddr_vec'high downto 1); cache_rdData_vec(cache_rdData_vec'high) <= cache_rdData_out; cache_rdData_vec(cache_rdData_vec'high-1 downto 0) <= cache_rdData_vec(cache_rdData_vec'high downto 1); atomic_rdData_vec(atomic_rdData_vec'high) <= atomic_rdData; atomic_rdData_vec(atomic_rdData_vec'high-1 downto 0) <= atomic_rdData_vec(atomic_rdData_vec'high downto 1); atomic_rdData_v_vec(atomic_rdData_v_vec'high) <= atomic_rdData_v; atomic_rdData_v_vec(atomic_rdData_vec'high -1 downto 0) <= atomic_rdData_v_vec(atomic_rdData_v_vec'high downto 1); atomic_sgntr_vec(atomic_sgntr_vec'high) <= atomic_sgntr; atomic_sgntr_vec(atomic_sgntr_vec'high-1 downto 0) <= atomic_sgntr_vec(atomic_sgntr_vec'high downto 1); start_addr_vec(start_addr_vec'high) <= start_addr; start_addr_vec(start_addr_vec'high-1 downto 0) <= start_addr_vec(start_addr_vec'high downto 1); start_CUs_vec(start_CUs_vec'high) <= start_CUs; wg_req_vec(wg_req_vec'high) <= wg_req; wg_info_vec(wg_info_vec'high) <= std_logic_vector(wg_info); rtm_we_wg_vec(rtm_we_wg_vec'high) <= rtm_we_wg; sch_rqst_n_WFs_m1_vec(sch_rqst_n_WFs_m1_vec'high) <= sch_rqst_n_WFs_m1; rtm_wrData_wg_vec(rtm_wrData_wg_vec'high) <= rtm_wrData_wg; rtm_wrAddr_wg_vec(rtm_wrAddr_wg_vec'high) <= rtm_wrAddr_wg; cram_rdData_vec(cram_rdData_vec'high) <= cram_rdData; cram_rdAddr_d0_vec(cram_rdAddr_d0_vec'high) <= cram_rdAddr_d0; if N_CU > 1 then start_CUs_vec(start_CUs_vec'high-1 downto 0) <= start_CUs_vec(start_CUs_vec'high downto 1); wg_req_vec(wg_req_vec'high-1 downto 0) <= wg_req_vec(wg_req_vec'high downto 1); -- wg_ack_vec(wg_ack_vec'high-1 downto 0) <= wg_ack_vec(wg_ack_vec'high downto 1); wg_info_vec(wg_info_vec'high-1 downto 0) <= wg_info_vec(wg_info_vec'high downto 1); rtm_wrAddr_wg_vec(rtm_wrAddr_wg_vec'high-1 downto 0) <= rtm_wrAddr_wg_vec(rtm_wrAddr_wg_vec'high downto 1); rtm_wrData_wg_vec(rtm_wrData_wg_vec'high-1 downto 0) <= rtm_wrData_wg_vec(rtm_wrData_wg_vec'high downto 1); rtm_we_wg_vec(rtm_we_wg_vec'high-1 downto 0) <= rtm_we_wg_vec(rtm_we_wg_vec'high downto 1); sch_rqst_n_WFs_m1_vec(sch_rqst_n_WFs_m1_vec'high-1 downto 0) <= sch_rqst_n_WFs_m1_vec(sch_rqst_n_WFs_m1_vec'high downto 1); cram_rdData_vec(cram_rdData_vec'high-1 downto 0) <= cram_rdData_vec(cram_rdData_vec'high downto 1); cram_rdAddr_d0_vec(cram_rdAddr_d0_vec'high-1 downto 0) <= cram_rdAddr_d0_vec(cram_rdAddr_d0_vec'high downto 1); end if; for i in 0 to N_CU-1 loop nrst_CUs(i) <= nrst; end loop; end if; end process; process(clk) begin if rising_edge(clk) then if to_integer(unsigned(CU_gmem_idle)) = 2**N_CU-1 then CUs_gmem_idle <= '1'; else CUs_gmem_idle <= '0'; end if; end if; end process; ------------------------------------------------------------------------------------------------- }}} -- global memory controller----------------------------------------------------------------------------------- {{{ gmem_controller_inst: entity gmem_cntrl port map( clk => clk, cu_valid => cu_gmem_valid, cu_ready => cu_gmem_ready, cu_we => cu_gmem_we, cu_rnw => cu_gmem_rnw, cu_atomic => cu_gmem_atomic, cu_atomic_sgntr => cu_gmem_atomic_sgntr, cu_rqst_addr => cu_rqst_addr, cu_wrData => cu_gmem_wrData, WGsDispatched => WGsDispatched, finish_exec => finish_exec, start_kernel => start_kernel, clean_cache => clean_cache, CUs_gmem_idle => CUs_gmem_idle, -- read data from cache rdAck => cache_rdAck_out, rdAddr => cache_rdAddr_out, rdData => cache_rdData_out, atomic_rdData => atomic_rdData, atomic_rdData_v => atomic_rdData_v, atomic_sgntr => atomic_sgntr, -- read axi bus {{{ -- ar channel axi_araddr => axi_araddr, axi_arvalid => axi_arvalid, axi_arready => axi_arready, axi_arid => axi_arid, -- r channel axi_rdata => axi_rdata, axi_rlast => axi_rlast, axi_rvalid => axi_rvalid, axi_rready => axi_rready, axi_rid => axi_rid, -- aw channel axi_awaddr => axi_awaddr, axi_awvalid => axi_awvalid, axi_awready => axi_awready, axi_awid => axi_awid, -- w channel axi_wdata => axi_wdata, axi_wstrb => axi_wstrb, axi_wlast => axi_wlast, axi_wvalid => axi_wvalid, axi_wready => axi_wready, -- b channel axi_bvalid => axi_bvalid, axi_bready => axi_bready, axi_bid => axi_bid, --}}} nrst => nrst_gmem_cntrl ); -- fixed signals assignments {{{ m0_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m0_arlen'length)); m1_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m1_arlen'length)); m2_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m2_arlen'length)); m3_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m3_arlen'length)); m0_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m1_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m2_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m3_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m0_arburst <= "01"; --INCR burst type m1_arburst <= "01"; --INCR burst type m2_arburst <= "01"; --INCR burst type m3_arburst <= "01"; --INCR burst type m0_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m0_awlen'length)); m1_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m1_awlen'length)); m2_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m2_awlen'length)); m3_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m3_awlen'length)); m0_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m1_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m2_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m3_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m0_awburst <= "01"; --INCR burst type m1_awburst <= "01"; --INCR burst type m2_awburst <= "01"; --INCR burst type m3_awburst <= "01"; --INCR burst type --}}} -- ar & r assignments {{{ m0_araddr <= std_logic_vector(axi_araddr(0)); m0_arvalid <= axi_arvalid(0); axi_arready(0) <= m0_arready; axi_rdata(0) <= m0_rdata; axi_rlast(0) <= m0_rlast; axi_rvalid(0) <= m0_rvalid; axi_rid(0) <= m0_rid; axi_bid(0) <= m0_bid; m0_awid <= axi_awid(0); m0_rready <= axi_rready(0); m0_arid <= axi_arid(0); AXI_READ_1: if N_AXI > 1 generate m1_araddr <= std_logic_vector(axi_araddr(1)); m1_arvalid <= axi_arvalid(1); axi_arready(1) <= m1_arready; axi_rdata(1) <= m1_rdata; axi_rlast(1) <= m1_rlast; axi_rvalid(1) <= m1_rvalid; axi_rid(1) <= m1_rid; axi_bid(1) <= m1_bid; m1_awid <= axi_awid(1); m1_rready <= axi_rready(1); m1_arid <= axi_arid(1); end generate; AXI_READ_2: if N_AXI > 2 generate m2_araddr <= std_logic_vector(axi_araddr(2)); m2_arvalid <= axi_arvalid(2); axi_arready(2) <= m2_arready; axi_rdata(2) <= m2_rdata; axi_rlast(2) <= m2_rlast; axi_rvalid(2) <= m2_rvalid; axi_rid(2) <= m2_rid; axi_bid(2) <= m2_bid; m2_awid <= axi_awid(2); m2_rready <= axi_rready(2); m2_arid <= axi_arid(2); end generate; AXI_READ_3: if N_AXI > 3 generate m3_araddr <= std_logic_vector(axi_araddr(3)); m3_arvalid <= axi_arvalid(3); axi_arready(3) <= m3_arready; axi_rdata(3) <= m3_rdata; axi_rlast(3) <= m3_rlast; axi_rvalid(3) <= m3_rvalid; axi_rid(3) <= m3_rid; axi_bid(3) <= m3_bid; m3_awid <= axi_awid(3); m3_rready <= axi_rready(3); m3_arid <= axi_arid(3); end generate; -- }}} -- aw, w & b assignments {{{ m0_awaddr <= std_logic_vector(axi_awaddr(0)); m0_awvalid <= axi_awvalid(0); axi_awready(0) <= m0_awready; m0_wdata <= axi_wdata(0); m0_wstrb <= axi_wstrb(0); m0_wlast <= axi_wlast(0); m0_wvalid <= axi_wvalid(0); axi_wready(0) <= m0_wready; axi_bvalid(0) <= m0_bvalid; m0_bready <= axi_bready(0); AXI_WRITE_1: if N_AXI > 1 generate m1_awaddr <= std_logic_vector(axi_awaddr(1)); m1_awvalid <= axi_awvalid(1); axi_awready(1) <= m1_awready; m1_wdata <= axi_wdata(1); m1_wstrb <= axi_wstrb(1); m1_wlast <= axi_wlast(1); m1_wvalid <= axi_wvalid(1); axi_wready(1) <= m1_wready; axi_bvalid(1) <= m1_bvalid; m1_bready <= axi_bready(1); end generate; AXI_WRITE_2: if N_AXI > 2 generate m2_awaddr <= std_logic_vector(axi_awaddr(2)); m2_awvalid <= axi_awvalid(2); axi_awready(2) <= m2_awready; m2_wdata <= axi_wdata(2); m2_wstrb <= axi_wstrb(2); m2_wlast <= axi_wlast(2); m2_wvalid <= axi_wvalid(2); axi_wready(2) <= m2_wready; axi_bvalid(2) <= m2_bvalid; m2_bready <= axi_bready(2); end generate; AXI_WRITE_3: if N_AXI > 3 generate m3_awaddr <= std_logic_vector(axi_awaddr(3)); m3_awvalid <= axi_awvalid(3); axi_awready(3) <= m3_awready; m3_wdata <= axi_wdata(3); m3_wstrb <= axi_wstrb(3); m3_wlast <= axi_wlast(3); m3_wvalid <= axi_wvalid(3); axi_wready(3) <= m3_wready; axi_bvalid(3) <= m3_bvalid; m3_bready <= axi_bready(3); end generate; -- }}} ------------------------------------------------------------------------------------------------- }}} -- WG dispatcher FSM -------------------------------------------------------------------------------------- {{{ regFile_we <= '1' when mainProc_wrAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "10" and mainProc_we = '1' else '0'; regs_trans: process(clk) begin if rising_edge(clk) then nrst_gmem_cntrl <= nrst; if start_kernel = '1' then clean_cache <= RcleanCache(new_krnl_indx); initialize_d0 <= RInitiate(new_krnl_indx); end if; s0_wdata_d0 <= s0_wdata; finish_exec_d0 <= finish_exec; if nrst = '0' then st_wg_disp <= idle; Rstat <= (others =>'0'); RcleanCache <= (others=>'0'); Rstart <= (others =>'0'); RInitiate <= (others=>'0'); else st_wg_disp <= st_wg_disp_n; -- regFile_we_d0 <= regFile_we; if start_kernel = '1' then Rstart(new_krnl_indx) <= '0'; elsif regFile_we = '1' and to_integer(unsigned(mainProc_wrAddr(N_REG_W-1 downto 0))) = Rstart_regFile_addr then Rstart <= s0_wdata_d0(NEW_KRNL_MAX_INDX-1 downto 0); end if; if regFile_we = '1' and to_integer(unsigned(mainProc_wrAddr(N_REG_W-1 downto 0))) = RcleanCache_regFile_addr then RcleanCache <= s0_wdata_d0(NEW_KRNL_MAX_INDX-1 downto 0); end if; if regFile_we = '1' and to_integer(unsigned(mainProc_wrAddr(N_REG_W-1 downto 0))) = RInitiate_regFile_addr then RInitiate <= s0_wdata_d0(NEW_KRNL_MAX_INDX-1 downto 0); end if; if start_kernel = '1' then Rstat(new_krnl_indx) <= '0'; elsif finish_exec = '1' and finish_exec_d0 = '0' then Rstat(finish_krnl_indx) <= '1'; end if; end if; end if; end process; process(Rstart) begin new_krnl_indx <= 0; for i in NEW_KRNL_MAX_INDX-1 downto 0 loop if Rstart(i) = '1' then new_krnl_indx <= i; end if; end loop; end process; start_kernel <= '1' when st_wg_disp_n = st1_dispatch and st_wg_disp = idle else '0'; process(st_wg_disp, finish_exec, Rstart) begin st_wg_disp_n <= st_wg_disp; case(st_wg_disp) is when idle => if to_integer(unsigned(Rstart)) /= 0 then --new kernel to start st_wg_disp_n <= st1_dispatch; end if; when st1_dispatch => if finish_exec = '1' then -- kernel is dispatched st_wg_disp_n <= idle; end if; end case; end process; ------------------------------------------------------------------------------------------------- }}} end Behavioral;

gpl-3.0

ef7e609a8088bf1fb519b87a94320587

wltr/cern-fgclite

nanofip_fpga/src/rtl/rx_var_select.vhd

------------------------------------------------------------------------------- --! @file rx_var_select.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-04-03 --! @brief Toggle between VAR1 and VAR2 when receiving data. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; --! @brief Entity declaration of rx_var_select --! @details --! Multiplexer control for data reception. When VAR1 or VAR2 are received, --! the Wishbone interface will be connected to the corresponding receiver. entity rx_var_select is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Ready signals --! @{ --! VAR1 is ready var1_rdy_i : in std_ulogic; --! VAR2 is ready var2_rdy_i : in std_ulogic; --! @} --! @name Multiplexer control --! @{ --! Select receiver, 0 = VAR1, 1 = VAR2, VAR2 is default var_select_o : out std_ulogic); --! @} end entity rx_var_select; --! RTL implementation of rx_var_select architecture rtl of rx_var_select is --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal var_select : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- var_select_o <= var_select; --------------------------------------------------------------------------- -- Registering --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin var_select <= '1'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; elsif var1_rdy_i = '1' then var_select <= '0'; elsif var2_rdy_i = '1' then var_select <= '1'; end if; end if; end process regs; end architecture rtl;

mit

c919e7cd2801be8a9107dc999b420b00

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_decr_counter.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_decr_counter | -- | --------------------------------------------------------------------------------------------------- -- File wf_decr_counter.vhd | -- Description Decreasing counter with synchronous reset, load enable and decrease enable | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 10/2010 | -- Version v0.01 | -- Depends on - | ---------------- | -- Last changes | -- 10/2010 EG v0.01 first version | -- 10/2011 EG v0.01b nfip_rst_i renamed to counter_rst_i; counter_top renamed to | -- counter_top_i; initial value after reset is all '1'; | -- counter_decr_p_i renamed to counter_decr_i | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_decr_counter --================================================================================================= entity wf_decr_counter is generic(g_counter_lgth : natural := 4); -- default length port( -- INPUTS -- nanoFIP User Interface general signal uclk_i : in std_logic; -- 40 MHz clock -- Signal from the wf_reset_unit counter_rst_i : in std_logic; -- resets counter to all '1' -- Signals from any unit counter_decr_i : in std_logic; -- decrement enable counter_load_i : in std_logic; -- load enable; loads counter to counter_top_i counter_top_i : in unsigned (g_counter_lgth-1 downto 0); -- load value -- OUTPUTS -- Signal to any unit counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter counter_is_zero_o : out std_logic); -- empty counter indication end entity wf_decr_counter; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_decr_counter is signal s_counter : unsigned (g_counter_lgth-1 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Synchronous process Decr_Counter Decr_Counter: process (uclk_i) begin if rising_edge (uclk_i) then if counter_rst_i = '1' then s_counter <= (others => '1'); else if counter_load_i = '1' then s_counter <= counter_top_i; elsif counter_decr_i = '1' then s_counter <= s_counter - 1; end if; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- counter_o <= s_counter; counter_is_zero_o <= '1' when s_counter = to_unsigned(0, s_counter'length) else '0'; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

b4a4873134df7108f8f0c602de50448a

Ttl/fsm_uart

examples/echo.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity echo is Port ( rx : in STD_LOGIC; tx : out STD_LOGIC; clk : in STD_LOGIC); end echo; architecture Behavioral of echo is -- Implementation parameters constant CLK_FREQ : integer := 32; constant SER_FREQ : integer := 115200; constant PARITY : boolean := true; -- UART signals signal uart_tx_req, uart_tx_end, uart_rx_ready : std_logic; signal uart_rx_tx_data : std_logic_vector(7 downto 0); -- FSM states type statetype is (s_rx, s_tx); signal state, next_state : statetype := s_rx; -- Transmission delay, wait for 2^10=1024 clock cycles before responding -- to make sure that receiver catches the beginning signal tx_delay, tx_delay_next : std_logic_vector(10 downto 0); component uart is generic ( CLK_FREQ : integer := CLK_FREQ; -- Main frequency (MHz) SER_FREQ : integer := SER_FREQ; -- Baud rate (bps) PARITY_BIT : boolean := PARITY -- RS232 parity bit ); port ( -- Control clk : in std_logic; -- Main clock rst : in std_logic; -- Main reset -- External Interface rx : in std_logic; -- RS232 received serial data tx : out std_logic; -- RS232 transmitted serial data -- uPC Interface tx_req : in std_logic; -- Request SEND of data tx_end : out std_logic; -- Data SENDED tx_data : in std_logic_vector(7 downto 0); -- Data to transmit rx_ready : out std_logic; -- Received data ready to uPC read rx_data : out std_logic_vector(7 downto 0) -- Received data ); end component; begin u1 : uart generic map( CLK_FREQ => CLK_FREQ, -- Main frequency (MHz) SER_FREQ => SER_FREQ, -- Baud rate (bps) PARITY_BIT => PARITY -- RS232 parity bit ) port map( -- Control clk => clk, rst => '0', -- External Interface rx => rx, tx => tx, -- uPC Interface tx_req => uart_tx_req, tx_end => uart_tx_end, tx_data => uart_rx_tx_data, rx_ready => uart_rx_ready, rx_data => uart_rx_tx_data ); process(clk) begin if rising_edge(clk) then state <= next_state; tx_delay <= tx_delay_next; end if; end process; process(state, uart_rx_ready, uart_tx_end, tx_delay) begin uart_tx_req <= '0'; tx_delay_next <= (others => '0'); case state is when s_rx => next_state <= s_rx; -- Received data if uart_rx_ready = '1' then -- Echo it back next_state <= s_tx; end if; when s_tx => next_state <= s_tx; if tx_delay(10) = '1' then -- Start TX uart_tx_req <= '1'; -- Hold tx_req --tx_delay_next <= tx_delay; else tx_delay_next <= std_logic_vector(unsigned(tx_delay) + 1); end if; -- Transmission done if uart_tx_end = '1' then next_state <= s_rx; end if; end case; end process; end Behavioral;

lgpl-3.0

196fa2685f245abdcc8d848eafbb05ab

wltr/cern-fgclite

critical_fpga/src/rtl/cf/fetch_page/fetch_page_dim.vhd

------------------------------------------------------------------------------- --! @file fetch_page_dim.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-19 --! @brief Prepare DIM page for NanoFIP communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --! @brief Entity declaration of fetch_page_dim --! @details --! This component prepares the DIM page for the NanoFIP response. entity fetch_page_dim is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Commands --! @{ --! Start flag start_i : in std_ulogic; --! Done flag done_o : out std_ulogic; --! Memory index idx_i : in std_ulogic_vector(14 downto 0); --! @} --! @name Memory page interface --! @{ --! Address page_addr_o : out std_ulogic_vector(5 downto 0); --! Write enable page_wr_en_o : out std_ulogic; --! Data output page_data_o : out std_ulogic_vector(7 downto 0); --! Done flag page_done_i : in std_ulogic; --! @} --! @name DIM data --! @{ --! Address dim_addr_o : out std_ulogic_vector(6 downto 0); --! Read enable dim_rd_en_o : out std_ulogic; --! Data input dim_data_i : in std_ulogic_vector(15 downto 0); --! Data input enable dim_data_en_i : in std_ulogic); --! @} end entity fetch_page_dim; --! RTL implementation of fetch_page_dim architecture rtl of fetch_page_dim is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type state_t is (IDLE, WRITE_LOW, WRITE_HIGH, DONE); type reg_t is record state : state_t; addr : unsigned(5 downto 0); data : std_ulogic_vector(7 downto 0); wr_en : std_ulogic; rd_en : std_ulogic; done : std_ulogic; end record; constant init_c : reg_t := ( state => IDLE, addr => (others => '0'), data => (others => '0'), wr_en => '0', rd_en => '0', done => '0'); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal next_reg : reg_t; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- page_addr_o <= std_ulogic_vector(reg.addr); page_wr_en_o <= reg.wr_en; page_data_o <= reg.data; dim_addr_o <= idx_i(1 downto 0) & std_ulogic_vector(reg.addr(5 downto 1)); dim_rd_en_o <= reg.rd_en; done_o <= reg.done; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= init_c; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else reg <= next_reg; end if; end if; end process regs; --------------------------------------------------------------------------- -- Combinatorics --------------------------------------------------------------------------- comb : process (reg, start_i, page_done_i, dim_data_i, dim_data_en_i) is begin -- comb -- Defaults next_reg <= reg; next_reg.rd_en <= '0'; next_reg.wr_en <= '0'; next_reg.done <= '0'; case reg.state is when IDLE => if start_i = '1' then next_reg.rd_en <= '1'; next_reg.state <= WRITE_LOW; end if; when WRITE_LOW => if dim_data_en_i = '1' then next_reg.data <= dim_data_i(7 downto 0); next_reg.wr_en <= '1'; end if; if page_done_i = '1' then next_reg.addr <= reg.addr + 1; next_reg.state <= WRITE_HIGH; end if; when WRITE_HIGH => next_reg.data <= dim_data_i(15 downto 8); next_reg.wr_en <= '1'; next_reg.state <= DONE; when DONE => if page_done_i = '1' then if to_integer(reg.addr) < 63 then next_reg.addr <= reg.addr + 1; next_reg.rd_en <= '1'; next_reg.state <= WRITE_LOW; else next_reg <= init_c; next_reg.done <= '1'; end if; end if; end case; end process comb; end architecture rtl;

mit

c1d4169b153eb1365b1098a0828f3bfa

malkadi/FGPU

RTL/WG_dispatcher.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity WG_dispatcher is -- ports {{{ port( clk, nrst : in std_logic; start : in std_logic; initialize_d0 : in std_logic; start_exec : out std_logic := '0'; krnl_indx : in integer range 0 to NEW_KRNL_MAX_INDX-1; krnl_sch_rdAddr : out std_logic_vector(KRNL_SCH_ADDR_W-1 downto 0) := (others => '0'); krnl_sch_rdData : in std_logic_vector(DATA_W-1 downto 0) := (others => '0'); finish : out std_logic := '0'; finish_krnl_indx : out integer range 0 to NEW_KRNL_MAX_INDX-1 := 0; -- index of kernel whose execution just finished start_addr : out unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); -- cds interface req : out std_logic_vector(N_CU-1 downto 0) := (others => '0'); ack : in std_logic_vector(N_CU-1 downto 0) := (others => '0'); sch_rqst_n_WFs_m1 : out unsigned(N_WF_CU_W-1 downto 0) := (others=>'0'); wf_active : in wf_active_array(N_CU-1 downto 0) := (others=>(others=>'0')); wg_info : out unsigned(DATA_W-1 downto 0) := (others=>'0'); rdData_alu_en : out alu_en_vec_type(N_CU-1 downto 0) := (others=>(others=>'0')); rdAddr_alu_en : in alu_en_rdAddr_type(N_CU-1 downto 0) := (others=>(others=>'0')); rtm_wrAddr : out unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); rtm_wrData : out unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); rtm_we : out std_logic := '0' ); -- }}} end WG_dispatcher; architecture Behavioral of WG_dispatcher is -- internal signals {{{ signal start_exec_i : std_logic := '0'; signal finish_i : std_logic := '0'; signal sch_rqst_n_WFs_m1_i : unsigned(N_WF_CU_W-1 downto 0) := (others=>'0'); -- }}} -- signals definitions {{{ signal schedulingInProgress : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal schedulingInProgress_n : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal nDim : integer range 0 to 2 := 0; type WG_st_sch_type is (idle, read_delay, prepare, seekCV, allocateWFs, checkAgain, wait_wf_active, wait_finish); signal st_sch, st_sch_n : WG_st_sch_type := idle; signal st_prepare, st_prepare_d0 : unsigned(NEW_KRNL_DESC_W-1 downto 0) := (others => '0'); signal st_prepare_n : unsigned(NEW_KRNL_DESC_W-1 downto 0) := (others => '0'); signal params : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal params_wrAddr : unsigned(N_PARAMS_W-1 downto 0) := (others=>'0'); signal params_written, params_written_n : std_logic := '0'; signal krnl_infos_we : std_logic := '0'; signal id0_offset : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id1_offset : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id2_offset : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id0_size : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id1_size : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id2_size : unsigned(DATA_W-1 downto 0) := (others => '0'); signal wg_size : unsigned(WG_SIZE_W downto 0) := (others=>'0'); signal wg_size_d0 : integer range 0 to WG_MAX_SIZE := 0; signal wg_size_d1 : integer range 0 to WG_MAX_SIZE := 0; signal wg_size_d2 : integer range 0 to WG_MAX_SIZE := 0; signal start_prepare : std_logic := '0'; signal prepare_params_n, prepare_params : std_logic := '0'; signal krnl_indx_ltchd : integer range 0 to NEW_KRNL_MAX_INDX-1 := 0; signal addr_first_inst : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal n_wg_d0_m1 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal n_wg_d1_m1 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal n_wg_d2_m1 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal prepare_fin : std_logic := '0'; signal nDisp_wg_d0 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d1 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d2 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d1_ov : std_logic := '0'; signal nDisp_wg_d0_ov : std_logic := '0'; signal id0,id1,id2 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nParams : integer range 0 to N_PARAMS := 0; -- next signals signal prepare_fin_n, prepare_fin_d0 : std_logic := '0'; signal start_loc_indcs : std_logic := '0'; signal start_prepare_n : std_logic := '0'; signal nDisp_wg_d0_n : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d1_n : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d2_n : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id0_n,id1_n,id2_n : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d0_ov_n : std_logic := '0'; signal nDisp_wg_d1_ov_n : std_logic := '0'; signal req_n : std_logic_vector(N_CU-1 downto 0) := (others => '0'); signal wg_info_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal alu_en_rdy : std_logic := '0'; signal start_d0 : std_logic := '0'; -- }}} -- RTM signals{{{ signal rtm_we_n : std_logic := '0'; signal rtm_wrAddr_n : unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); signal rtm_wrData_n : unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); --}}} -- scheduling signals {{{ signal alloc_CV_indx : integer range 0 to N_CU := 0; signal cd_indx, cd_indx_d0, cd_indx_d1 : unsigned(max(N_CU_W, 1)-1 downto 0) := (others=>'0'); signal wf_active_slctd : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal n_inactive_wfs : integer range 0 to N_WF_CU := 0; --}}} -- loc indices signals {{{ signal loc_indcs_fin : std_logic := '0'; signal loc_indcs_wrAddr : unsigned(RTM_ADDR_W-2 downto 0) := (others => '0'); signal loc_indcs_wrData : unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); signal loc_indcs_we : std_logic := '0'; type loc_indcs_wr_state_type is ( write_size0, write_size1, write_size2, write_wg_size_d0, write_wg_size_d1, write_wg_size_d2, write_n_wgs_d0, write_n_wgs_d1, write_n_wgs_d2, write_params, write_loc_indcs, write_d0, write_d1, write_d2); signal loc_indcs_wr_state : loc_indcs_wr_state_type := write_size0; signal loc_indcs_wr_state_n : loc_indcs_wr_state_type := write_size0; -- }}} begin -- internal signals assignments --------------------------------------------------------------------{{{ assert(RTM_DATA_W >= DATA_W) severity failure; start_exec <= start_exec_i; sch_rqst_n_WFs_m1 <= sch_rqst_n_WFs_m1_i; ---------------------------------------------------------------------------------------------------------}}} -- others {{{ finish_krnl_indx <= krnl_indx_ltchd; start_addr <= addr_first_inst; --}}} -- local indices generator ------------------------------------------------------------------------------------ {{{ loc_indcs_gen: entity loc_indcs_generator port map( clk => clk, start => start_loc_indcs, finish => loc_indcs_fin, clear_finish => start_exec_i, n_wf_wg_m1 => sch_rqst_n_WFs_m1_i, wg_size_d0 => wg_size_d0, wg_size_d1 => wg_size_d1, wg_size_d2 => wg_size_d2, wrAddr => loc_indcs_wrAddr, we => loc_indcs_we, wrData => loc_indcs_wrData, nrst => nrst ); start_exec_i <= (loc_indcs_fin and alu_en_rdy) or params_written; process(clk) begin if rising_edge(clk) then finish <= finish_i; rtm_we <= rtm_we_n; rtm_wrAddr <= rtm_wrAddr_n; rtm_wrData <= rtm_wrData_n; wg_info <= wg_info_n; start_d0 <= start; params_written <= params_written_n; if nrst = '0' then loc_indcs_wr_state <= write_size0; else loc_indcs_wr_state <= loc_indcs_wr_state_n; end if; end if; end process; process(loc_indcs_wr_state, req_n, id0, id1, id2, start_exec_i, loc_indcs_we, loc_indcs_wrAddr, loc_indcs_wrData, krnl_infos_we, params_wrAddr, params, prepare_fin_d0, finish_i, wg_size_d0, wg_size_d1, wg_size_d2, id0_size, id1_size, id2_size, n_wg_d0_m1, n_wg_d1_m1, n_wg_d2_m1, initialize_d0, start_d0) begin loc_indcs_wr_state_n <= loc_indcs_wr_state; rtm_we_n <= loc_indcs_we; rtm_wrAddr_n(RTM_ADDR_W-2 downto 0) <= loc_indcs_wrAddr; rtm_wrAddr_n(RTM_ADDR_W-1) <= '0'; rtm_wrData_n <= loc_indcs_wrData; wg_info_n <= id0; params_written_n <= '0'; case loc_indcs_wr_state is when write_size0 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= id0_size; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_size1; end if; if start_d0 = '1' and initialize_d0 = '0' then loc_indcs_wr_state_n <= write_params; end if; when write_size1 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (0=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= id1_size; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_size2; end if; when write_size2 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (1=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= id2_size; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_wg_size_d0; end if; when write_wg_size_d0 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0'); rtm_wrData_n(DATA_W-1 downto WG_SIZE_W+1) <= (others=>'0'); rtm_wrData_n(WG_SIZE_W downto 0) <= to_unsigned(wg_size_d0, WG_SIZE_W+1); if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_n_wgs_d0; end if; when write_n_wgs_d0 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= n_wg_d0_m1; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_n_wgs_d1; end if; when write_n_wgs_d1 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (0=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= n_wg_d1_m1; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_n_wgs_d2; end if; when write_n_wgs_d2 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (1=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= n_wg_d2_m1; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_wg_size_d1; end if; when write_wg_size_d1 => rtm_we_n <= '1'; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (0=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto WG_SIZE_W+1) <= (others=>'0'); rtm_wrData_n(WG_SIZE_W downto 0) <= to_unsigned(wg_size_d1, WG_SIZE_W+1); loc_indcs_wr_state_n <= write_wg_size_d2; when write_wg_size_d2 => rtm_we_n <= '1'; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (1=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto WG_SIZE_W+1) <= (others=>'0'); rtm_wrData_n(WG_SIZE_W downto 0) <= to_unsigned(wg_size_d2, WG_SIZE_W+1); loc_indcs_wr_state_n <= write_params; when write_params => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(RTM_ADDR_W-4 downto N_PARAMS_W) <= (others=>'0'); rtm_wrAddr_n(N_PARAMS_W-1 downto 0) <= params_wrAddr; rtm_wrData_n(DATA_W-1 downto 0) <= params; if prepare_fin_d0 = '1' then if initialize_d0 = '0' then loc_indcs_wr_state_n <= write_d0; params_written_n <= '1'; else loc_indcs_wr_state_n <= write_loc_indcs; end if; end if; when write_loc_indcs => if start_exec_i = '1' then loc_indcs_wr_state_n <= write_d0; end if; rtm_wrData_n <= loc_indcs_wrData; when write_d0 => -- rtm_we has not to be set during write_dx because it is done in the CU_schceduler. -- in case that a WG consists of multiple WFs, the WG's offsets need to written multiple times. wg_info_n <= id0; if to_integer(unsigned(req_n)) /= 0 then loc_indcs_wr_state_n <= write_d1; end if; if finish_i = '1' then loc_indcs_wr_state_n <= write_size0; end if; when write_d1 => wg_info_n <= id1; loc_indcs_wr_state_n <= write_d2; when write_d2 => wg_info_n <= id2; loc_indcs_wr_state_n <= write_d0; end case; end process; ---------------------------------------------------------------------------------------------------------------}}} -- WG scheduler FSM ------------------------------------------------------------------------------------{{{ process(st_sch, start, alloc_CV_indx, start_exec_i, nDisp_wg_d0_ov, nDisp_wg_d1_ov, nDisp_wg_d0, nDisp_wg_d1, nDisp_wg_d2, id0, id1, id2, id0_offset, id1_offset, id2_offset, n_wg_d0_m1, n_wg_d1_m1, n_wg_d2_m1, wg_size_d0, wg_size_d1, wg_size_d2, wf_active, schedulingInProgress, initialize_d0) --, alloc_CV_indx_ltchd) begin st_sch_n <= st_sch; start_prepare_n <= '0'; id0_n <= id0; id1_n <= id1; id2_n <= id2; nDisp_wg_d0_n <= nDisp_wg_d0; nDisp_wg_d1_n <= nDisp_wg_d1; nDisp_wg_d2_n <= nDisp_wg_d2; nDisp_wg_d0_ov_n <= nDisp_wg_d0_ov; nDisp_wg_d1_ov_n <= nDisp_wg_d1_ov; req_n <= (others=>'0'); finish_i <= '0'; prepare_params_n <= '0'; schedulingInProgress_n <= schedulingInProgress; -- rtm_we_dx <= (others=>'0'); case st_sch is when idle => if start = '1' then st_sch_n <= read_delay; end if; when read_delay => st_sch_n <= prepare; start_prepare_n <= '1'; if initialize_d0 = '0' then prepare_params_n <= '1'; end if; when prepare => if start_exec_i = '1' then st_sch_n <= seekCV; id0_n <= id0_offset; id1_n <= id1_offset; id2_n <= id2_offset; end if; when seekCV => if alloc_CV_indx /= N_CU then st_sch_n <= allocateWFs; req_n(alloc_CV_indx) <= '1'; schedulingInProgress_n(alloc_CV_indx) <= '1'; -- rtm_we_dx(alloc_CV_indx) <= '1'; if nDisp_wg_d0 = n_wg_d0_m1 then nDisp_wg_d0_ov_n <= '1'; else nDisp_wg_d0_ov_n <= '0'; end if; end if; when allocateWFs => st_sch_n <= checkAgain; -- rtm_we_dx(alloc_CV_indx_ltchd) <= '1'; nDisp_wg_d1_ov_n <= '0'; if nDisp_wg_d0_ov = '1' and nDisp_wg_d1 = n_wg_d1_m1 then nDisp_wg_d1_ov_n <= '1'; end if; when checkAgain => st_sch_n <= seekCV; -- rtm_we_dx(alloc_CV_indx_ltchd) <= '1'; if nDisp_wg_d0_ov = '1' then nDisp_wg_d0_n <= (others => '0'); id0_n <= id0_offset; nDisp_wg_d1_n <= nDisp_wg_d1 + 1; id1_n <= id1 + WG_size_d1; else nDisp_wg_d0_n <= nDisp_wg_d0 + 1; id0_n <= id0 + wg_size_d0; end if; if nDisp_wg_d1_ov = '1' then nDisp_wg_d1_n <= (others => '0'); id1_n <= id1_offset; nDisp_wg_d2_n <= nDisp_wg_d2 + 1; id2_n <= id2 + WG_size_d2; if nDisp_wg_d2 = n_wg_d2_m1 then st_sch_n <= wait_wf_active; end if; end if; when wait_wf_active => if schedulingInProgress = (schedulingInProgress'reverse_range=>'0') then st_sch_n <= wait_finish; end if; when wait_finish => finish_i <= '1'; st_sch_n <= idle; for i in 0 to N_CU-1 loop if to_integer(unsigned(wf_active(i))) /= 0 then st_sch_n <= wait_finish; finish_i <= '0'; end if; end loop; end case; end process; process(clk) variable tmp : integer range 0 to N_WF_CU := 0; begin if rising_edge(clk) then if nrst = '0' or finish_i = '1' then nDisp_wg_d0 <= (others => '0'); nDisp_wg_d1 <= (others => '0'); nDisp_wg_d2 <= (others => '0'); nDisp_wg_d0_ov <= '0'; nDisp_wg_d1_ov <= '0'; req <= (others=>'0'); cd_indx <= (others=>'0'); wf_active_slctd <= (others=>'0'); cd_indx_d0 <= (others=>'0'); n_inactive_wfs <= 0; cd_indx_d1 <= (others=>'0'); alloc_CV_indx <= 0; schedulingInProgress <= (others=>'0'); else nDisp_wg_d0 <= nDisp_wg_d0_n; nDisp_wg_d1 <= nDisp_wg_d1_n; nDisp_wg_d2 <= nDisp_wg_d2_n; nDisp_wg_d0_ov <= nDisp_wg_d0_ov_n; nDisp_wg_d1_ov <= nDisp_wg_d1_ov_n; req <= req_n; schedulingInProgress <= schedulingInProgress_n; for i in 0 to N_CU-1 loop if ack(i) = '1' then schedulingInProgress(i) <= '0'; end if; end loop; -- stage 0 if N_CU_W > 0 then cd_indx <= cd_indx+1; end if; -- stage 1 wf_active_slctd <= wf_active(to_integer(cd_indx)); cd_indx_d0 <= cd_indx; -- stage 2 tmp := 0; for i in 0 to N_WF_CU-1 loop if wf_active_slctd(i) = '0' then tmp := tmp + 1; end if; end loop; n_inactive_wfs <= tmp; cd_indx_d1 <= cd_indx_d0; -- stage 3 alloc_CV_indx <= N_CU; if n_inactive_wfs > to_integer(sch_rqst_n_WFs_m1_i) and schedulingInProgress(to_integer(cd_indx_d1)) = '0' then alloc_CV_indx <= to_integer(cd_indx_d1); end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then id0 <= id0_n; id1 <= id1_n; id2 <= id2_n; prepare_params <= prepare_params_n; if start = '1' and st_sch = idle then krnl_indx_ltchd <= krnl_indx; end if; if nrst = '0' then st_sch <= idle; start_prepare <= '0'; else st_sch <= st_sch_n; start_prepare <= start_prepare_n; end if; end if; end process; ------------------------------------------------------------------------------------------------}}} -- prepare FSM -------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then prepare_fin <= prepare_fin_n; prepare_fin_d0 <= prepare_fin; start_loc_indcs <= prepare_fin and initialize_d0; krnl_infos_we <= '0'; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WF then addr_first_inst <= unsigned(krnl_sch_rdData(ADDR_FIRST_INST_OFFSET+CRAM_ADDR_W-1 downto ADDR_FIRST_INST_OFFSET)); -- addr_last_inst <= to_integer(unsigned(krnl_sch_rdData(ADDR_LAST_INST_OFFSET+CRAM_ADDR_W-1 downto ADDR_LAST_INST_OFFSET))); sch_rqst_n_WFs_m1_i <= unsigned(krnl_sch_rdData(N_WF_OFFSET+N_WF_CU_W-1 downto N_WF_OFFSET)); end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID0_SIZE then id0_size <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); krnl_infos_we <= '1'; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID1_SIZE then id1_size <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); krnl_infos_we <= '1'; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID2_SIZE then id2_size <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); krnl_infos_we <= '1'; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID0_OFFSET then id0_offset <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID1_OFFSET then id1_offset <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID2_OFFSET then id2_offset <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_WG_SIZE then krnl_infos_we <= '1'; wg_size_d0 <= to_integer(unsigned(krnl_sch_rdData(WG_SIZE_0_OFFSET+WG_SIZE_W downto WG_SIZE_0_OFFSET))); --WG_SIZE_W+1 bits are assigned if to_integer(unsigned(krnl_sch_rdData(N_DIM_OFFSET+1 downto N_DIM_OFFSET))) /=0 then -- compare with nDim wg_size_d1 <= to_integer(unsigned(krnl_sch_rdData(WG_SIZE_1_OFFSET+WG_SIZE_W downto WG_SIZE_1_OFFSET))); else wg_size_d1 <= 1; end if; if to_integer(unsigned(krnl_sch_rdData(N_DIM_OFFSET+1 downto N_DIM_OFFSET))) = 2 then -- compare with nDim wg_size_d2 <= to_integer(unsigned(krnl_sch_rdData(WG_SIZE_2_OFFSET+WG_SIZE_W downto WG_SIZE_2_OFFSET))); else wg_size_d2 <= 1; end if; nDim <= to_integer(unsigned(krnl_sch_rdData(N_DIM_OFFSET+1 downto N_DIM_OFFSET))); end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WG_0 then n_wg_d0_m1 <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); krnl_infos_we <= '1'; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WG_1 then krnl_infos_we <= '1'; if nDim /= 0 then n_wg_d1_m1 <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); else n_wg_d1_m1 <= (others => '0'); end if; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WG_2 then krnl_infos_we <= '1'; if nDim = 2 then n_wg_d2_m1 <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); else n_wg_d2_m1 <= (others => '0'); end if; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_PARAMS then nParams <= to_integer(unsigned(krnl_sch_rdData(N_PARAMS_OFFSET+N_PARAMS_W-1 downto N_PARAMS_OFFSET))); wg_size <= unsigned(krnl_sch_rdData(WG_SIZE_OFFSET+WG_SIZE_W downto WG_SIZE_OFFSET)); end if; if to_integer(st_prepare_d0) >= PARAMS_OFFSET then params <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); krnl_infos_we <= '1'; params_wrAddr <= st_prepare_d0(N_PARAMS_W-1 downto 0); end if; if nrst = '0' then st_prepare <= (others=>'0'); st_prepare_d0 <= (others=>'0'); else st_prepare <= st_prepare_n; st_prepare_d0 <= st_prepare; end if; end if; end process; process(st_prepare, start_prepare, nParams, prepare_params) begin st_prepare_n <= st_prepare; prepare_fin_n <= '0'; case to_integer(st_prepare) is when 0 => if start_prepare = '1' then if prepare_params = '0' then st_prepare_n <= st_prepare + 1; else st_prepare_n <= (st_prepare_n'high => '1', others=>'0'); end if; end if; when others => st_prepare_n <= st_prepare + 1; if st_prepare = (2**(NEW_KRNL_DESC_W-1))+nParams-1 then prepare_fin_n <= '1'; st_prepare_n <= (others=>'0'); else end if; end case; end process; krnl_sch_rdAddr(KRNL_SCH_ADDR_W-1 downto NEW_KRNL_DESC_W) <= std_logic_vector(to_unsigned(krnl_indx_ltchd, NEW_KRNL_INDX_W)); krnl_sch_rdAddr(NEW_KRNL_DESC_W-1 downto 0) <= std_logic_vector(st_prepare_n); --------------------------------------------------------------------------------------------------}}} -- init alu enable -------------------------------------------------------------------------------------------{{{ init_alu_enable: entity init_alu_en_ram generic map( N_RD_PORTS => N_CU )port map( start => start_loc_indcs, finish => alu_en_rdy, clear_finish => start_exec_i, wg_size => wg_size, sch_rqst_n_WFs_m1 => sch_rqst_n_WFs_m1_i, rdData_alu_en => rdData_alu_en, rdAddr_alu_en => rdAddr_alu_en, clk => clk, nrst => nrst ); ---------------------------------------------------------------------------------------------------------}}} end Behavioral;

gpl-3.0

8858900db7eafa4961077cb21ff0d974

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_6Stations_8Banks_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

4ab1f143beae153f51c54734d96fec51

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_all.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 1; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

aa6adf91dd558d6bdf0af8fd71850cd6

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_float_8ALUs.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data por0s constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

619fe0c8d0adb2f77b0b38bfa3c0ea4e

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_area_estimation.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

366dac64cc17c8bf3e3149d6c1f02107

preusser/q27

src/vhdl/PoC/common/vectors.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Common functions and types -- -- Description: -- ------------------------------------- -- For detailed documentation see below. -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.strings.all; package vectors is -- ========================================================================== -- Type declarations -- ========================================================================== -- STD_LOGIC_VECTORs subtype T_SLV_2 is std_logic_vector(1 downto 0); subtype T_SLV_3 is std_logic_vector(2 downto 0); subtype T_SLV_4 is std_logic_vector(3 downto 0); subtype T_SLV_8 is std_logic_vector(7 downto 0); subtype T_SLV_12 is std_logic_vector(11 downto 0); subtype T_SLV_16 is std_logic_vector(15 downto 0); subtype T_SLV_24 is std_logic_vector(23 downto 0); subtype T_SLV_32 is std_logic_vector(31 downto 0); subtype T_SLV_48 is std_logic_vector(47 downto 0); subtype T_SLV_64 is std_logic_vector(63 downto 0); subtype T_SLV_96 is std_logic_vector(95 downto 0); subtype T_SLV_128 is std_logic_vector(127 downto 0); subtype T_SLV_256 is std_logic_vector(255 downto 0); subtype T_SLV_512 is std_logic_vector(511 downto 0); -- STD_LOGIC_VECTOR_VECTORs -- type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR; -- VHDL 2008 syntax - not yet supported by Xilinx type T_SLVV_2 is array(natural range <>) of T_SLV_2; type T_SLVV_3 is array(natural range <>) of T_SLV_3; type T_SLVV_4 is array(natural range <>) of T_SLV_4; type T_SLVV_8 is array(natural range <>) of T_SLV_8; type T_SLVV_12 is array(natural range <>) of T_SLV_12; type T_SLVV_16 is array(natural range <>) of T_SLV_16; type T_SLVV_24 is array(natural range <>) of T_SLV_24; type T_SLVV_32 is array(natural range <>) of T_SLV_32; type T_SLVV_48 is array(natural range <>) of T_SLV_48; type T_SLVV_64 is array(natural range <>) of T_SLV_64; type T_SLVV_128 is array(natural range <>) of T_SLV_128; type T_SLVV_256 is array(natural range <>) of T_SLV_256; type T_SLVV_512 is array(natural range <>) of T_SLV_512; -- STD_LOGIC_MATRIXs type T_SLM is array(natural range <>, natural range <>) of std_logic; -- ATTENTION: -- 1. you MUST initialize your matrix signal with 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) -- Example: signal myMatrix : T_SLM(3 downto 0, 7 downto 0) := (others => (others => 'Z')); -- 2. Xilinx iSIM bug: DON'T use myMatrix'range(n) for n >= 2 -- myMatrix'range(2) returns always myMatrix'range(1); see work-around notes below -- -- USAGE NOTES: -- dimension 1 => rows - e.g. Words -- dimension 2 => columns - e.g. Bits/Bytes in a word -- -- WORKAROUND: for Xilinx ISE/iSim -- Version: 14.2 -- Issue: myMatrix'range(n) for n >= 2 returns always myMatrix'range(1) -- ========================================================================== -- Function declarations -- ========================================================================== -- slicing boundary calulations function low (lenvec : T_POSVEC; index : natural) return natural; function high(lenvec : T_POSVEC; index : natural) return natural; -- Assign procedures: assign_* procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural); -- assign vector to complete row procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; Position : natural); -- assign short vector to row starting at position procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; High : natural; Low : natural); -- assign short vector to row in range high:low procedure assign_col(signal slm : out T_SLM; slv : std_logic_vector; constant ColIndex : natural); -- assign vector to complete column -- ATTENTION: see T_SLM definition for further details and work-arounds -- Matrix to matrix conversion: slm_slice* function slm_slice(slm : T_SLM; RowIndex : natural; ColIndex : natural; Height : natural; Width : natural) return T_SLM; -- get submatrix in boundingbox RowIndex,ColIndex,Height,Width function slm_slice_rows(slm : T_SLM; High : natural; Low : natural) return T_SLM; -- get submatrix / all rows in RowIndex range high:low function slm_slice_cols(slm : T_SLM; High : natural; Low : natural) return T_SLM; -- get submatrix / all columns in ColIndex range high:low -- Boolean Operators function "not" (a : t_slm) return t_slm; function "and" (a, b : t_slm) return t_slm; function "or" (a, b : t_slm) return t_slm; function "xor" (a, b : t_slm) return t_slm; function "nand"(a, b : t_slm) return t_slm; function "nor" (a, b : t_slm) return t_slm; function "xnor"(a, b : t_slm) return t_slm; -- Matrix concatenation: slm_merge_* function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM; function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM; -- Matrix to vector conversion: get_* function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector; -- get a matrix column function get_row(slm : T_SLM; RowIndex : natural) return std_logic_vector; -- get a matrix row function get_row(slm : T_SLM; RowIndex : natural; Length : positive) return std_logic_vector; -- get a matrix row of defined length [length - 1 downto 0] function get_row(slm : T_SLM; RowIndex : natural; High : natural; Low : natural) return std_logic_vector; -- get a sub vector of a matrix row at high:low -- Convert to vector: to_slv function to_slv(slvv : T_SLVV_2) return std_logic_vector; -- convert vector-vector to flatten vector function to_slv(slvv : T_SLVV_4) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_8) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_12) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_16) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_24) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_32) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_64) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_128) return std_logic_vector; -- ... function to_slv(slm : T_SLM) return std_logic_vector; -- convert matrix to flatten vector -- Convert flat vector to avector-vector: to_slvv_* function to_slvv_4(slv : std_logic_vector) return T_SLVV_4; -- function to_slvv_8(slv : std_logic_vector) return T_SLVV_8; -- function to_slvv_12(slv : std_logic_vector) return T_SLVV_12; -- function to_slvv_16(slv : std_logic_vector) return T_SLVV_16; -- function to_slvv_32(slv : std_logic_vector) return T_SLVV_32; -- function to_slvv_64(slv : std_logic_vector) return T_SLVV_64; -- function to_slvv_128(slv : std_logic_vector) return T_SLVV_128; -- function to_slvv_256(slv : std_logic_vector) return T_SLVV_256; -- function to_slvv_512(slv : std_logic_vector) return T_SLVV_512; -- -- Convert matrix to avector-vector: to_slvv_* function to_slvv_4(slm : T_SLM) return T_SLVV_4; -- function to_slvv_8(slm : T_SLM) return T_SLVV_8; -- function to_slvv_12(slm : T_SLM) return T_SLVV_12; -- function to_slvv_16(slm : T_SLM) return T_SLVV_16; -- function to_slvv_32(slm : T_SLM) return T_SLVV_32; -- function to_slvv_64(slm : T_SLM) return T_SLVV_64; -- function to_slvv_128(slm : T_SLM) return T_SLVV_128; -- function to_slvv_256(slm : T_SLM) return T_SLVV_256; -- function to_slvv_512(slm : T_SLM) return T_SLVV_512; -- -- Convert vector-vector to matrix: to_slm function to_slm(slv : std_logic_vector; ROWS : positive; COLS : positive) return T_SLM; -- create matrix from vector function to_slm(slvv : T_SLVV_4) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_8) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_12) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_16) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_32) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_48) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_64) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_128) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_256) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_512) return T_SLM; -- create matrix from vector-vector -- Change vector direction function dir(slvv : T_SLVV_8) return T_SLVV_8; -- Reverse vector elements function rev(slvv : T_SLVV_4) return T_SLVV_4; function rev(slvv : T_SLVV_8) return T_SLVV_8; function rev(slvv : T_SLVV_12) return T_SLVV_12; function rev(slvv : T_SLVV_16) return T_SLVV_16; function rev(slvv : T_SLVV_32) return T_SLVV_32; function rev(slvv : T_SLVV_64) return T_SLVV_64; function rev(slvv : T_SLVV_128) return T_SLVV_128; function rev(slvv : T_SLVV_256) return T_SLVV_256; function rev(slvv : T_SLVV_512) return T_SLVV_512; -- TODO: function resize(slm : T_SLM; size : positive) return T_SLM; -- to_string function to_string(slvv : T_SLVV_8; sep : character := ':') return string; function to_string(slm : T_SLM; groups : positive := 4; format : character := 'b') return string; end package vectors; package body vectors is -- slicing boundary calulations -- ========================================================================== function low(lenvec : T_POSVEC; index : natural) return natural is variable pos : natural := 0; begin for i in lenvec'low to index - 1 loop pos := pos + lenvec(i); end loop; return pos; end function; function high(lenvec : T_POSVEC; index : natural) return natural is variable pos : natural := 0; begin for i in lenvec'low to index loop pos := pos + lenvec(i); end loop; return pos - 1; end function; -- Assign procedures: assign_* -- ========================================================================== procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural) is variable temp : std_logic_vector(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration begin temp := slv; for i in temp'range loop slm(RowIndex, i) <= temp(i); end loop; end procedure; procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; Position : natural) is variable temp : std_logic_vector(Position + slv'length - 1 downto Position); begin temp := slv; for i in temp'range loop slm(RowIndex, i) <= temp(i); end loop; end procedure; procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; High : natural; Low : natural) is variable temp : std_logic_vector(High downto Low); begin temp := slv; for i in temp'range loop slm(RowIndex, i) <= temp(i); end loop; end procedure; procedure assign_col(signal slm : out T_SLM; slv : std_logic_vector; constant ColIndex : natural) is variable temp : std_logic_vector(slm'range(1)); begin temp := slv; for i in temp'range loop slm(i, ColIndex) <= temp(i); end loop; end procedure; -- Matrix to matrix conversion: slm_slice* -- ========================================================================== function slm_slice(slm : T_SLM; RowIndex : natural; ColIndex : natural; Height : natural; Width : natural) return T_SLM is variable Result : T_SLM(Height - 1 downto 0, Width - 1 downto 0) := (others => (others => '0')); begin for i in 0 to Height - 1 loop for j in 0 to Width - 1 loop Result(i, j) := slm(RowIndex + i, ColIndex + j); end loop; end loop; return Result; end function; function slm_slice_rows(slm : T_SLM; High : natural; Low : natural) return T_SLM is variable Result : T_SLM(High - Low downto 0, slm'length(2) - 1 downto 0) := (others => (others => '0')); begin for i in 0 to High - Low loop for j in 0 to slm'length(2) - 1 loop Result(i, j) := slm(Low + i, slm'low(2) + j); end loop; end loop; return Result; end function; function slm_slice_cols(slm : T_SLM; High : natural; Low : natural) return T_SLM is variable Result : T_SLM(slm'length(1) - 1 downto 0, High - Low downto 0) := (others => (others => '0')); begin for i in 0 to slm'length(1) - 1 loop for j in 0 to High - Low loop Result(i, j) := slm(slm'low(1) + i, Low + j); end loop; end loop; return Result; end function; -- Boolean Operators function "not"(a : t_slm) return t_slm is variable res : t_slm(a'range(1), a'range(2)); begin for i in res'range(1) loop for j in res'range(2) loop res(i, j) := not a(i, j); end loop; end loop; return res; end function; function "and"(a, b : t_slm) return t_slm is variable bb, res : t_slm(a'range(1), a'range(2)); begin bb := b; for i in res'range(1) loop for j in res'range(2) loop res(i, j) := a(i, j) and bb(i, j); end loop; end loop; return res; end function; function "or"(a, b : t_slm) return t_slm is variable bb, res : t_slm(a'range(1), a'range(2)); begin bb := b; for i in res'range(1) loop for j in res'range(2) loop res(i, j) := a(i, j) or bb(i, j); end loop; end loop; return res; end function; function "xor"(a, b : t_slm) return t_slm is variable bb, res : t_slm(a'range(1), a'range(2)); begin bb := b; for i in res'range(1) loop for j in res'range(2) loop res(i, j) := a(i, j) xor bb(i, j); end loop; end loop; return res; end function; function "nand"(a, b : t_slm) return t_slm is begin return not(a and b); end function; function "nor"(a, b : t_slm) return t_slm is begin return not(a or b); end function; function "xnor"(a, b : t_slm) return t_slm is begin return not(a xor b); end function; -- Matrix concatenation: slm_merge_* function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is constant ROWS : positive := slm1'length(1) + slm2'length(1); constant COLUMNS : positive := slm1'length(2); variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0); begin for i in slm1'range(1) loop for j in slm1'low(2) to slm1'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration slm(i, j) := slm1(i, j); end loop; end loop; for i in slm2'range(1) loop for j in slm2'low(2) to slm2'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration slm(slm1'length(1) + i, j) := slm2(i, j); end loop; end loop; return slm; end function; function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is constant ROWS : positive := slm1'length(1); constant COLUMNS : positive := slm1'length(2) + slm2'length(2); variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0); begin for i in slm1'range(1) loop for j in slm1'low(2) to slm1'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration slm(i, j) := slm1(i, j); end loop; for j in slm2'low(2) to slm2'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration slm(i, slm1'length(2) + j) := slm2(i, j); end loop; end loop; return slm; end function; -- Matrix to vector conversion: get_* -- ========================================================================== -- get a matrix column function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector is variable slv : std_logic_vector(slm'range(1)); begin for i in slm'range(1) loop slv(i) := slm(i, ColIndex); end loop; return slv; end function; -- get a matrix row function get_row(slm : T_SLM; RowIndex : natural) return std_logic_vector is variable slv : std_logic_vector(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration begin for i in slv'range loop slv(i) := slm(RowIndex, i); end loop; return slv; end function; -- get a matrix row of defined length [length - 1 downto 0] function get_row(slm : T_SLM; RowIndex : natural; Length : positive) return std_logic_vector is begin return get_row(slm, RowIndex, (Length - 1), 0); end function; -- get a sub vector of a matrix row at high:low function get_row(slm : T_SLM; RowIndex : natural; High : natural; Low : natural) return std_logic_vector is variable slv : std_logic_vector(High downto Low); begin for i in slv'range loop slv(i) := slm(RowIndex, i); end loop; return slv; end function; -- Convert to vector: to_slv -- ========================================================================== -- convert vector-vector to flatten vector function to_slv(slvv : T_SLVV_2) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 2) - 1 downto 0); begin for i in slvv'range loop slv((i * 2) + 1 downto (i * 2)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_4) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 4) - 1 downto 0); begin for i in slvv'range loop slv((i * 4) + 3 downto (i * 4)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_8) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 8) - 1 downto 0); begin for i in slvv'range loop slv((i * 8) + 7 downto (i * 8)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_12) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 12) - 1 downto 0); begin for i in slvv'range loop slv((i * 12) + 11 downto (i * 12)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_16) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 16) - 1 downto 0); begin for i in slvv'range loop slv((i * 16) + 15 downto (i * 16)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_24) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 24) - 1 downto 0); begin for i in slvv'range loop slv((i * 24) + 23 downto (i * 24)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_32) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 32) - 1 downto 0); begin for i in slvv'range loop slv((i * 32) + 31 downto (i * 32)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_64) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 64) - 1 downto 0); begin for i in slvv'range loop slv((i * 64) + 63 downto (i * 64)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_128) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 128) - 1 downto 0); begin for i in slvv'range loop slv((i * 128) + 127 downto (i * 128)) := slvv(i); end loop; return slv; end function; -- convert matrix to flatten vector function to_slv(slm : T_SLM) return std_logic_vector is variable slv : std_logic_vector((slm'length(1) * slm'length(2)) - 1 downto 0); begin for i in slm'range(1) loop for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration slv((i * slm'length(2)) + j) := slm(i, j); end loop; end loop; return slv; end function; -- Convert flat vector to a vector-vector: to_slvv_* -- ========================================================================== -- create vector-vector from vector (4 bit) function to_slvv_4(slv : std_logic_vector) return T_SLVV_4 is variable Result : T_SLVV_4((slv'length / 4) - 1 downto 0); begin if ((slv'length mod 4) /= 0) then report "to_slvv_4: width mismatch - slv'length is no multiple of 4 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 4) + 3 downto (i * 4)); end loop; return Result; end function; -- create vector-vector from vector (8 bit) function to_slvv_8(slv : std_logic_vector) return T_SLVV_8 is variable Result : T_SLVV_8((slv'length / 8) - 1 downto 0); begin if ((slv'length mod 8) /= 0) then report "to_slvv_8: width mismatch - slv'length is no multiple of 8 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 8) + 7 downto (i * 8)); end loop; return Result; end function; -- create vector-vector from vector (12 bit) function to_slvv_12(slv : std_logic_vector) return T_SLVV_12 is variable Result : T_SLVV_12((slv'length / 12) - 1 downto 0); begin if ((slv'length mod 12) /= 0) then report "to_slvv_12: width mismatch - slv'length is no multiple of 12 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 12) + 11 downto (i * 12)); end loop; return Result; end function; -- create vector-vector from vector (16 bit) function to_slvv_16(slv : std_logic_vector) return T_SLVV_16 is variable Result : T_SLVV_16((slv'length / 16) - 1 downto 0); begin if ((slv'length mod 16) /= 0) then report "to_slvv_16: width mismatch - slv'length is no multiple of 16 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 16) + 15 downto (i * 16)); end loop; return Result; end function; -- create vector-vector from vector (32 bit) function to_slvv_32(slv : std_logic_vector) return T_SLVV_32 is variable Result : T_SLVV_32((slv'length / 32) - 1 downto 0); begin if ((slv'length mod 32) /= 0) then report "to_slvv_32: width mismatch - slv'length is no multiple of 32 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 32) + 31 downto (i * 32)); end loop; return Result; end function; -- create vector-vector from vector (64 bit) function to_slvv_64(slv : std_logic_vector) return T_SLVV_64 is variable Result : T_SLVV_64((slv'length / 64) - 1 downto 0); begin if ((slv'length mod 64) /= 0) then report "to_slvv_64: width mismatch - slv'length is no multiple of 64 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 64) + 63 downto (i * 64)); end loop; return Result; end function; -- create vector-vector from vector (128 bit) function to_slvv_128(slv : std_logic_vector) return T_SLVV_128 is variable Result : T_SLVV_128((slv'length / 128) - 1 downto 0); begin if ((slv'length mod 128) /= 0) then report "to_slvv_128: width mismatch - slv'length is no multiple of 128 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 128) + 127 downto (i * 128)); end loop; return Result; end function; -- create vector-vector from vector (256 bit) function to_slvv_256(slv : std_logic_vector) return T_SLVV_256 is variable Result : T_SLVV_256((slv'length / 256) - 1 downto 0); begin if ((slv'length mod 256) /= 0) then report "to_slvv_256: width mismatch - slv'length is no multiple of 256 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 256) + 255 downto (i * 256)); end loop; return Result; end function; -- create vector-vector from vector (512 bit) function to_slvv_512(slv : std_logic_vector) return T_SLVV_512 is variable Result : T_SLVV_512((slv'length / 512) - 1 downto 0); begin if ((slv'length mod 512) /= 0) then report "to_slvv_512: width mismatch - slv'length is no multiple of 512 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 512) + 511 downto (i * 512)); end loop; return Result; end function; -- Convert matrix to avector-vector: to_slvv_* -- ========================================================================== -- create vector-vector from matrix (4 bit) function to_slvv_4(slm : T_SLM) return T_SLVV_4 is variable Result : T_SLVV_4(slm'range(1)); begin if (slm'length(2) /= 4) then report "to_slvv_4: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (8 bit) function to_slvv_8(slm : T_SLM) return T_SLVV_8 is variable Result : T_SLVV_8(slm'range(1)); begin if (slm'length(2) /= 8) then report "to_slvv_8: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (12 bit) function to_slvv_12(slm : T_SLM) return T_SLVV_12 is variable Result : T_SLVV_12(slm'range(1)); begin if (slm'length(2) /= 12) then report "to_slvv_12: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (16 bit) function to_slvv_16(slm : T_SLM) return T_SLVV_16 is variable Result : T_SLVV_16(slm'range(1)); begin if (slm'length(2) /= 16) then report "to_slvv_16: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (32 bit) function to_slvv_32(slm : T_SLM) return T_SLVV_32 is variable Result : T_SLVV_32(slm'range(1)); begin if (slm'length(2) /= 32) then report "to_slvv_32: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (64 bit) function to_slvv_64(slm : T_SLM) return T_SLVV_64 is variable Result : T_SLVV_64(slm'range(1)); begin if (slm'length(2) /= 64) then report "to_slvv_64: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (128 bit) function to_slvv_128(slm : T_SLM) return T_SLVV_128 is variable Result : T_SLVV_128(slm'range(1)); begin if (slm'length(2) /= 128) then report "to_slvv_128: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (256 bit) function to_slvv_256(slm : T_SLM) return T_SLVV_256 is variable Result : T_SLVV_256(slm'range); begin if (slm'length(2) /= 256) then report "to_slvv_256: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (512 bit) function to_slvv_512(slm : T_SLM) return T_SLVV_512 is variable Result : T_SLVV_512(slm'range(1)); begin if (slm'length(2) /= 512) then report "to_slvv_512: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- Convert vector-vector to matrix: to_slm -- ========================================================================== -- create matrix from vector function to_slm(slv : std_logic_vector; ROWS : positive; COLS : positive) return T_SLM is variable slm : T_SLM(ROWS - 1 downto 0, COLS - 1 downto 0); begin for i in 0 to ROWS - 1 loop for j in 0 to COLS - 1 loop slm(i, j) := slv((i * COLS) + j); end loop; end loop; return slm; end function; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_4) return T_SLM is variable slm : T_SLM(slvv'range, 3 downto 0); begin for i in slvv'range loop for j in T_SLV_4'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_8) return T_SLM is -- variable test : STD_LOGIC_VECTOR(T_SLV_8'range); -- variable slm : T_SLM(slvv'range, test'range); -- BUG: iSIM 14.5 cascaded 'range accesses let iSIM break down -- variable slm : T_SLM(slvv'range, T_SLV_8'range); -- BUG: iSIM 14.5 allocates 9 bits in dimension 2 variable slm : T_SLM(slvv'range, 7 downto 0); -- WORKAROUND: use constant range begin -- report "slvv: slvv.length=" & INTEGER'image(slvv'length) & " slm.dim0.length=" & INTEGER'image(slm'length(1)) & " slm.dim1.length=" & INTEGER'image(slm'length(2)) severity NOTE; -- report "T_SLV_8: .length=" & INTEGER'image(T_SLV_8'length) & " .high=" & INTEGER'image(T_SLV_8'high) & " .low=" & INTEGER'image(T_SLV_8'low) severity NOTE; -- report "test: test.length=" & INTEGER'image(test'length) & " .high=" & INTEGER'image(test'high) & " .low=" & INTEGER'image(test'low) severity NOTE; for i in slvv'range loop for j in T_SLV_8'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_12) return T_SLM is variable slm : T_SLM(slvv'range, 11 downto 0); begin for i in slvv'range loop for j in T_SLV_12'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_16) return T_SLM is variable slm : T_SLM(slvv'range, 15 downto 0); begin for i in slvv'range loop for j in T_SLV_16'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_32) return T_SLM is variable slm : T_SLM(slvv'range, 31 downto 0); begin for i in slvv'range loop for j in T_SLV_32'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_48) return T_SLM is variable slm : T_SLM(slvv'range, 47 downto 0); begin for i in slvv'range loop for j in T_SLV_48'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_64) return T_SLM is variable slm : T_SLM(slvv'range, 63 downto 0); begin for i in slvv'range loop for j in T_SLV_64'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_128) return T_SLM is variable slm : T_SLM(slvv'range, 127 downto 0); begin for i in slvv'range loop for j in T_SLV_128'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_256) return T_SLM is variable slm : T_SLM(slvv'range, 255 downto 0); begin for i in slvv'range loop for j in T_SLV_256'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_512) return T_SLM is variable slm : T_SLM(slvv'range, 511 downto 0); begin for i in slvv'range loop for j in T_SLV_512'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; -- Change vector direction -- ========================================================================== function dir(slvv : T_SLVV_8) return T_SLVV_8 is variable Result : T_SLVV_8(slvv'reverse_range); begin Result := slvv; return Result; end function; -- Reverse vector elements function rev(slvv : T_SLVV_4) return T_SLVV_4 is variable Result : T_SLVV_4(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_8) return T_SLVV_8 is variable Result : T_SLVV_8(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_12) return T_SLVV_12 is variable Result : T_SLVV_12(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_16) return T_SLVV_16 is variable Result : T_SLVV_16(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_32) return T_SLVV_32 is variable Result : T_SLVV_32(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_64) return T_SLVV_64 is variable Result : T_SLVV_64(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_128) return T_SLVV_128 is variable Result : T_SLVV_128(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_256) return T_SLVV_256 is variable Result : T_SLVV_256(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_512) return T_SLVV_512 is variable Result : T_SLVV_512(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; -- Resize functions -- ========================================================================== -- Resizes the vector to the specified length. Input vectors larger than the specified size are truncated from the left side. Smaller input -- vectors are extended on the left by the provided fill value (default: '0'). Use the resize functions of the numeric_std package for -- value-preserving resizes of the signed and unsigned data types. function resize(slm : T_SLM; size : positive) return T_SLM is variable Result : T_SLM(size - 1 downto 0, slm'high(2) downto slm'low(2)) := (others => (others => '0')); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration begin for i in slm'range(1) loop for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration Result(i, j) := slm(i, j); end loop; end loop; return Result; end function; function to_string(slvv : T_SLVV_8; sep : character := ':') return string is constant hex_len : positive := ite((sep = C_POC_NUL), (slvv'length * 2), (slvv'length * 3) - 1); variable Result : string(1 to hex_len) := (others => sep); variable pos : positive := 1; begin for i in slvv'range loop Result(pos to pos + 1) := to_string(slvv(i), 'h'); pos := pos + ite((sep = C_POC_NUL), 2, 3); end loop; return Result; end function; function to_string_bin(slm : T_SLM; groups : positive := 4; format : character := 'h') return string is variable PerLineOverheader : positive := div_ceil(slm'length(2), groups); variable Result : string(1 to (slm'length(1) * (slm'length(2) + PerLineOverheader)) + 10); variable Writer : positive; variable GroupCounter : natural; begin Result := (others => C_POC_NUL); Result(1) := LF; Writer := 2; GroupCounter := 0; for i in slm'low(1) to slm'high(1) loop for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration Result(Writer) := to_char(slm(i, j)); Writer := Writer + 1; GroupCounter := GroupCounter + 1; if (GroupCounter = groups) then Result(Writer) := ' '; Writer := Writer + 1; GroupCounter := 0; end if; end loop; Result(Writer - 1) := LF; GroupCounter := 0; end loop; return str_trim(Result); end function; function to_string(slm : T_SLM; groups : positive := 4; format : character := 'b') return string is begin if (format = 'b') then return to_string_bin(slm, groups); else return "Format not supported."; end if; end function; end package body;

agpl-3.0

4ca7955c9b7ef61bdc167fb4f2439ad3

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

ab1de88cfdb6373168238a28fc11e4bf

preusser/q27

src/vhdl/PoC/sync/sync_Bits.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Patrick Lehmann -- -- Module: Synchronizes a flag signal across clock-domain boundaries -- -- Description: -- ------------------------------------ -- This module synchronizes multiple flag bits from clock-domain 'Clock1' to -- clock-domain 'Clock'. The clock-domain boundary crossing is done by two -- synchronizer D-FFs. All bits are independent from each other. If a known -- vendor like Altera or Xilinx are recognized, a vendor specific -- implementation is chosen. -- -- ATTENTION: -- Use this synchronizer only for long time stable signals (flags). -- -- CONSTRAINTS: -- General: -- Please add constraints for meta stability to all '_meta' signals and -- timing ignore constraints to all '_async' signals. -- -- Xilinx: -- In case of a Xilinx device, this module will instantiate the optimized -- module PoC.xil.SyncBits. Please attend to the notes of xil_SyncBits.vhdl. -- -- Altera sdc file: -- TODO -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; library PoC; use PoC.config.all; use PoC.utils.all; use PoC.sync.all; entity sync_Bits is generic ( BITS : POSITIVE := 1; -- number of bit to be synchronized INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits ); port ( Clock : in STD_LOGIC; -- <Clock> output clock domain Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @async: input bits Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- @Clock: output bits ); end entity; architecture rtl of sync_Bits is constant INIT_I : STD_LOGIC_VECTOR := resize(descend(INIT), BITS); begin genGeneric : if ((VENDOR /= VENDOR_ALTERA) and (VENDOR /= VENDOR_XILINX)) generate attribute ASYNC_REG : STRING; attribute SHREG_EXTRACT : STRING; begin gen : for i in 0 to BITS - 1 generate signal Data_async : STD_LOGIC; signal Data_meta : STD_LOGIC := INIT_I(i); signal Data_sync : STD_LOGIC := INIT_I(i); -- Mark register DataSync_async's input as asynchronous and ignore timings (TIG) attribute ASYNC_REG of Data_meta : signal is "TRUE"; -- Prevent XST from translating two FFs into SRL plus FF attribute SHREG_EXTRACT of Data_meta : signal is "NO"; attribute SHREG_EXTRACT of Data_sync : signal is "NO"; begin Data_async <= Input(i); process(Clock) begin if rising_edge(Clock) then Data_meta <= Data_async; Data_sync <= Data_meta; end if; end process; Output(i) <= Data_sync; end generate; end generate; -- use dedicated and optimized 2 D-FF synchronizer for Altera FPGAs genAltera : if (VENDOR = VENDOR_ALTERA) generate sync : sync_Bits_Altera generic map ( BITS => BITS, INIT => INIT_I ) port map ( Clock => Clock, Input => Input, Output => Output ); end generate; -- use dedicated and optimized 2 D-FF synchronizer for Xilinx FPGAs genXilinx : if (VENDOR = VENDOR_XILINX) generate sync : sync_Bits_Xilinx generic map ( BITS => BITS, INIT => INIT_I ) port map ( Clock => Clock, Input => Input, Output => Output ); end generate; end architecture;

agpl-3.0

2d365783d680ac209a6590014cb4f072

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_6Stations_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

33c740904e4551277df08a5557debe9e

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fslt.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

d00b1d3c4b3182b8db9315be37840808

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

d3ce749ccb0c9e7343442d10cb4eca40

malkadi/FGPU

RTL/lmem.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity lmem is --{{{ port ( clk : in std_logic; rqst, we : in std_logic; -- stage 0 alu_en : in std_logic_vector(CV_SIZE-1 downto 0); wrData : in SLV32_ARRAY(CV_SIZE-1 downto 0); rdData : out SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- stage 2 rdData_v : out std_logic := '0'; -- stage 2 rdData_rd_addr : out unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); rdData_alu_en : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); sp : in unsigned(LMEM_ADDR_W-N_WF_CU_W-PHASE_W-1 downto 0); rd_addr : in unsigned(REG_FILE_W-1 downto 0); nrst : in std_logic ); end lmem; --}}} architecture basic of lmem is type lmemory_type is array (0 to 2**LMEM_ADDR_W-1) of std_logic_vector(CV_SIZE*DATA_W-1 downto 0); signal lmemory : lmemory_type := (others=>(others=>'0')); signal lmemory_addr : unsigned(LMEM_ADDR_W-1 downto 0) := (others=>'0'); signal phase : unsigned(PHASE_W-1 downto 0) := (others=>'0'); signal rdData_n : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal alu_en_vec : alu_en_vec_type(1 downto 0) := (others=>(others=>'0')); signal rd_addr_vec : reg_addr_array(1 downto 0) := (others=>(others=>'0')); signal rdData_v_p0 : std_logic := '0'; begin -- lmemory ----------------------------------------------------------------------------------------------{{{ lmemory_addr(LMEM_ADDR_W-1 downto LMEM_ADDR_W-PHASE_W) <= phase; lmemory_addr(LMEM_ADDR_W-PHASE_W-1 downto LMEM_ADDR_W-PHASE_W-N_WF_CU_W) <= rd_addr(WI_REG_ADDR_W+N_WF_CU_W-1 downto WI_REG_ADDR_W); lmemory_addr(LMEM_ADDR_W-N_WF_CU_W-PHASE_W-1 downto 0) <= sp; process(clk) begin if rising_edge(clk) then for i in 0 to CV_SIZE-1 loop rdData_n(i) <= lmemory(to_integer(lmemory_addr))((i+1)*DATA_W-1 downto i*DATA_W); -- @ 1 end loop; rdData <= rdData_n; -- @ 2 if we = '1' then for i in 0 to CV_SIZE-1 loop if alu_en(i) = '1' then lmemory(to_integer(lmemory_addr))((i+1)*DATA_W-1 downto i*DATA_W) <= wrData(i); end if; end loop; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- control ----------------------------------------------------------------------------------------------{{{ rdData_alu_en <= alu_en_vec(0); rdData_rd_addr <= rd_addr_vec(0); process(clk) begin if rising_edge(clk) then alu_en_vec(alu_en_vec'high) <= alu_en; alu_en_vec(alu_en_vec'high-1 downto 0) <= alu_en_vec(alu_en_vec'high downto 1); rd_addr_vec(rd_addr_vec'high) <= rd_addr; rd_addr_vec(rd_addr_vec'high-1 downto 0) <= rd_addr_vec(rd_addr_vec'high downto 1); rdData_v <= rdData_v_p0; if nrst = '0' then phase <= (others=>'0'); rdData_v_p0 <= '0'; else if rqst = '1' then phase <= phase + 1; end if; if phase = (phase'reverse_range=>'0') then rdData_v_p0 <= '0'; end if; if rqst = '1' and we = '0' then if phase = (phase'reverse_range=>'0') then rdData_v_p0 <= '1'; end if; end if; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} end architecture;

gpl-3.0

c004bd8e9f0943b1588e5681d125109a

Kinxil/VHDL_Projects

Mandelbrot/Zoom.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library WORK; use WORK.CONSTANTS.ALL; use WORK.FUNCTIONS.ALL; entity Zoom is Port ( bleft : in STD_LOGIC; bright : in STD_LOGIC; bup : in STD_LOGIC; bdwn : in STD_LOGIC; bctr : in STD_LOGIC; clock : in STD_LOGIC; reset : in STD_LOGIC; ce_param : in std_logic; x_start : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0); y_start : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0); step : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0)); end Zoom; architecture Behavioral of Zoom is signal s_xstart, s_ystart, s_step : signed(XY_RANGE-1 downto 0); begin process(clock, ce_param, reset, bup, bdwn, bleft, bright, bctr) begin if reset = '1' then s_xstart <= x"E0000000"; s_ystart <= x"F0000000"; s_step <= x"00111111"; --Mandelbrot -2 1 x -1 1 sur 640x480 elsif ((rising_edge(clock)) and (ce_param='1')) then -- TODO : Centrer le zoom if bctr = '1' then if bup = '1' then s_xstart <= s_xstart + (mult(s_step srl 2,x"28000000",FIXED) sll 8); s_ystart <= s_ystart + (mult(s_step srl 2,x"1E000000",FIXED) sll 8); s_step <= s_step srl 1; --Zoom x2> réduction du step elsif bdwn = '1' then s_xstart <= s_xstart + not (mult(s_step srl 1,x"28000000",FIXED) sll 8) + 1; s_ystart <= s_ystart + not (mult(s_step srl 1,x"1E000000",FIXED) sll 8) +1; s_step <= s_step sll 1; --Dezoom x0.5> augmentation du step end if; elsif bup = '1' then s_ystart <= s_ystart + (s_step sll 7); elsif bdwn = '1' then s_ystart <= s_ystart - (s_step sll 7); end if; if bleft = '1' then s_xstart <= s_xstart + (s_step sll 7); elsif bright = '1' then s_xstart <= s_xstart - (s_step sll 7); end if; end if; end process; x_start <= STD_LOGIC_VECTOR(s_xstart); y_start <= STD_LOGIC_VECTOR(s_ystart); step <= STD_LOGIC_VECTOR(s_step); end Behavioral;

gpl-3.0

dc0c9a87dd2fc2d236f92db6dd961ac1

preusser/q27

src/vhdl/queens/queens_slice.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> -- Benedikt Reuter <breutr@gmail.com> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity queens_slice is generic ( N : positive; -- size of field L : natural -- number of preplaced outer rings ); port ( -- Global Clock clk : in std_logic; rst : in std_logic; -- Inputs (strobed) start : in std_logic; -- Strobe for Start BH_l : in std_logic_vector(0 to N-2*L-1); -- Blocking for leftmost Column BU_l : in std_logic_vector(0 to 2*N-4*L-2); BD_l : in std_logic_vector(0 to 2*N-4*L-2); BV_l : in std_logic_vector(0 to N-2*L-1); -- Output Strobes sol : out std_logic; done : out std_logic ); end queens_slice; library IEEE; use IEEE.numeric_std.all; architecture rtl of queens_slice is --------------------------------------------------------------------------- -- Matrix to iterate through -- These types are plain ugly but the multidiemsional tMatrix(<>, <>) -- is not slicable. Thus, these types are still better than lots of -- generate loops working through the columns. subtype tColumn is std_logic_vector(L to N-L-1); type tField is array(L to N-L-1) of tColumn; -- Placed Queen Matrix signal QN : tField := (others => (others => '-')); component arbit_forward generic ( N : positive -- Length of Token Chain ); port ( tin : in std_logic; -- Fed Token have : in std_logic_vector(0 to N-1); -- Token Owner pass : in std_logic_vector(0 to N-1); -- Token Passers grnt : out std_logic_vector(0 to N-1); -- Token Output tout : out std_logic -- Unused Token ); end component; -- Blocking Signals signal BH : std_logic_vector(L to N-L-1) := (others => '-'); -- Window: L to N-L-1 signal BV : std_logic_vector(L to N-L-1) := (others => '-'); -- Window: L -- put rotates left signal BU : std_logic_vector(2*L to 2*N-2*L-2) := (others => '-'); -- Window: N-1 to 2*N-2*L-2 -- put rotates right signal BD : std_logic_vector(2*L to 2*N-2*L-2) := (others => '-'); -- Window: 2*L to N-1 -- put rotates left signal s : std_logic_vector(L to N-L-1); signal put : std_logic; begin assert false report LF& "Queens@TUD Solver Slice [N="&integer'image(N)&", L="&integer'image(L)&']' &LF& "Copyright (C) 2015-2016 Thomas B. Preusser <thomas.preusser@utexas.edu> " &LF& " Benedikt Reuter <breutr@gmail.com>" &LF& "This design is free software, and you are welcome to redistribute it " &LF& "under the conditions of the GPL version 3. " &LF& "It comes with ABSOLUTELY NO WARRANTY. " &LF& "For details see the notice in the file COPYING."&LF severity note; ---------------------------------------------------------------------------- -- Queen Matrix process(clk) begin if rising_edge(clk) then if put = '1' then QN(L to N-L-2) <= QN(L+1 to N-L-1); else QN(L to N-L-2) <= tColumn'(tColumn'range => '-') & QN(L to N-L-3); end if; end if; end process; ---------------------------------------------------------------------------- -- Blocking Signals process(clk) variable b : std_logic_vector(2*L to 2*N-2*L-2); begin if rising_edge(clk) then -- Initialization if start = '1' then BH <= BH_l; BV <= BV_l; BU <= BU_l; BD <= BD_l; else -- In Progress if put = '1' then -- Add placed Queen BH <= BH or s; BV <= BV(BV'left+1 to BV'right) & BV(BV'left); b := BU(BU'left to N-2) & (BU(N-1 to BU'right) or s); BU <= b(b'right) & b(b'left to b'right-1); b := (BD(BD'left to N-1) or s) & BD(N to BD'right); BD <= b(b'left+1 to b'right) & b(b'left); else -- Clear Queen BH <= BH and not QN(N-L-2); BV <= BV(BV'right) & BV(BV'left to BV'right-1); b := BU(BU'left+1 to BU'right) & BU(BU'left); BU <= b(b'left to N-2) & (b(N-1 to b'right) and not QN(N-L-2)); b := BD(BD'right) & BD(BD'left to BD'right-1); BD <= (b(b'left to N-1) and not QN(N-L-2)) & b(N to b'right); end if; end if; end if; end process; ---------------------------------------------------------------------------- -- Placement Calculation blkPlace : block -- State signal CS : std_logic_vector(L to N-L-1) := (others => '0'); -- Column Front Selector signal Ins : std_logic := '-'; -- Direction signal H : std_logic_vector(L to N-L-1) := (others => '-'); -- Last Placement in active Col -- Combined Blocking signal pass : std_logic_vector(L to N-L-1); signal tout : std_logic; begin -- Combine Blocking Signals pass <= BH or BD(2*L to N-1) or BU(N-1 to 2*N-2*L-2) when BV(L) = '0' else (others => '1'); col : arbit_forward generic map ( N => N-2*L ) port map ( tin => Ins, have => H, pass => pass, grnt => s, tout => tout ); QN(N-L-1) <= s; -- Column Front Selector, a shift-based counter with: process(clk) begin if rising_edge(clk) then if rst = '1' then CS <= (others => '0'); elsif start = '1' then CS <= (others => '0'); CS(CS'left) <= '1'; else if put = '1' then CS <= '0' & CS(CS'left to CS'right-1); else CS <= CS(CS'left+1 to CS'right) & '0'; end if; end if; end if; end process; -- Direction Control process(clk) begin if rising_edge(clk) then if start = '1' then H <= (others => '0'); Ins <= not BV_l(BV_l'left); elsif put = '1' then H <= (others => '0'); Ins <= not BV(L+1); else H <= QN(N-L-2); Ins <= BV(BV'right); end if; end if; end process; -- Control put <= (not tout) and not CS(CS'right); -- Outputs process(clk) begin if rising_edge(clk) then if rst = '1' or start = '1' then sol <= '0'; done <= '0'; else sol <= (not tout) and CS(CS'right); done <= tout and CS(CS'left); end if; end if; end process; end block blkPlace; end rtl;

agpl-3.0

e35d2161ae65d392f842e670c457abb7

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_synth.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block KWVujtFtbw2d3/xo1vIOEwFbjfeUp9+LiAOLaVI0YOyvz7SGsiVFnnecIKH6LMaBGbmqJwypQ3ho hUJUXG7oeg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QlSlzBPpn2RO2nmaEL2fz9rmzwO0yDVwrWv7lQUEYRWypJ9MhVr2icMJgfDllwNeh752IVAvHfu5 1DqlBXy4RN268XSRRvWwZVkyCibbFrBD5gLLVrX5/LhrGH+VbBo3ca57Td+b4JmoTIHzjewhBFK0 07J2/uAi3nDn9hQG7m8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block N7Vl1+JEpjWDLeSFRqDioddAogxF8TeXLnQrr3ffCBlkfrbnKyHo7n3nYMT2CgAK8qjLViq2bi2J p2Ij/AJ6t8JZNKepVq2fhxo2eyzU4tE8SKNtPqOv3j1aWUpmq73uRDewpv1Kj9/r4yP3csQXBgGY Kys/i9LiLIRFFKop/08nhTTOlpmBAZb/BtKhq/5vSxOfdoPrBlwwgIKJwDkwPcbqqAbXWTMY6ehf FN0S7KEWvq2TDeG32O5bZ0YTZLnPzHfhxUE0wowVvXdiseZJ8+IClAJDnB3owq4wSI578oyeVM5l KvRfHaQ6BXgMwvxtSljoo5nAn0WWi6EQ9ltr0Q== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block MW2/vR6BjDsekINPI5JlK8VQ7uMy/SHABv/a7DoboW9d+p0rjHCd3jqdFCM5SxCubk6+yTiKguoa Uq1nTIoCk/woIauS11brot4t4RHEbRy9y9YHezmtfj4zNhhgG06oD1Aorh9hd6WPLO6Zjv78l4J8 xdOFfGo1BX+v8lRHR/4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Veh9j/fHCHllxA/7Gidu4fcWHIjPSuh9FU1gLxrdqbqnlm+XRejKfn/4II23RCKOsSIS1d+0WSYj ri+KeWpPFqaqUOO9i5czzE11qA5yj5gHDHUNLEzcM7zIpsWScmCS6ooFs903juqZhsj0oSXMyOnZ uYp0qvJpCW7jmnYslViTxUzx45pthSCUKDYh/pnaixQawrLhBt8UPZqjT5Tt+xeT0Pqk/yFGGOR6 Q6ukLXnJrLWIjiU/L5u8dpOlRI54s67W9yybpkjvdflfYeJEbD9g2lQH8Ucaoi2vCP6s6HfEAxmH zWTY83kMqOBkoaWsNbb57zUbvuA0CtVgk+ofQA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 54480) `protect data_block vI9ld8C5//5rn2fEm/i5aO+X7vrUw5qpZ7WZBorxZKd68tmzGZ+BYfVlzi6fcOxlshp60nZWSfGN NqqNKC0StO6OZxlEUOdySTYALv/4Mblb4273p8Ps3bNZE5Izljfx0+iLCBsFWq7hvWxrwnvJrkVs 2dA37u7Jje4ff76HLaUg3EAzLXYpUwYCLoVLyER++FvFdiqOBdRU7FhU9EwcE8zHh81Of/z1+SVl P1kS945+AJ1xsqxBCm2kdySB1+Bp0zbp7054/3ywqN2xWqYdvsSm3KJk0Gp4en8TUAz0l/tQgbd8 CQNq5UIT0PHWswc5hjIC6SCYSGsKwMxMr5nysOZW3gESXDmlW/dJm8bZPqc3ELF/0QBeNcDzaCdg Fg7qv4hQ8HkPGxB5pWavvctBrN6UiwNENp5d8XBGxgJl5aP+NBJUEsCfbfgbvbHvOFl+5N3lZ24j 5aQHw96IxsL6pNRafswYmtNa0gRKtXvwSo1Wth5K5UT3oRDcVa5KpjqkRykdjr3H9SkU9z1hleoP UILKlugoA//fWHiiBrz3m7yZhPyaIN0dl8hk+pTOzEKI2DBA2m9necPE2S+YMSJMs88UE1/8uDNX Qd8X2DPrE/Rm2xXevEqx4SKwdL3FPC2WLVUYt2vzS7eFFndXVMPhZJ7wVFYDRnbQMwjC4gvyZtGb Pcw1Q3+KXwAToYHAP9DWAEXOCNQK0o4x8DIhl1pIXnj2g+RCZqQXtXzGeqY18tCwPW9E/VnEtpUN 9ydNEQCwkj226767976JtfmPtbnPvf0Jd11eU+4N/kBMtssqdZSBt8ZTTN/0CydCcIh/X+n+7Mme moiAWSSWwNHMcCkgmYYuQtjJ56C/2Kjv9JAPQBaF4MDLnnv875yG6OVTYmuhO+Mn76DXjPa3LzUQ 5N2PMOhPscHR0BKdOZLf8Fug+5g3XycxbfharS6XcHe48gg1/1s1I5fuoLvO/9E0kniaLZuu2VAX n7LwC+p35n3WFHOIn2pinq+peeE+vBODA0D22AMWciB2riej9kbkiVu/OfzVk38BQ9iu3xjhXdNO TibZ0AvWhwLVeQO/wwN3fh4lGgfRtTaXbE4Wfmel/iYP8lQoS/a8+BX8uPTgraIfGx/TZ+UxotBH 1OvUflNe7HRKi7Ffz2YDbXuyioBreuvDpDyvG4g7/07+8/ne6wf8ptEIAXmPz9mxUZwgLgFWRZoO IUz0jy7KK291CXwLoCRs6UoyvZ6OzsBR7RdpPXcIbfenpJsROTd41R1xtSJ8EiGbHAKLvQAmjme8 Hi25PHgLtsHhRws+Wl8gGG6V7rK5bwee+8g0sPC2sgFaLVk+JTfGGiHTKwMwASiAygyJ59OgTTaf haOjVNpsFhEQ7hlpg8BOn/HR42ykHNuZPPL1Cymv3xSFw4gcho9V0SlVGq63TKv9NQ3MMCWDSUr0 ZND4pCP2B8kvnbz/uNIY14r3gPt43XKVqAMngSE/z6iayY2VNJDCIEJF7037rH8wexIVEOAaxHIz pdGouL4/2DimOu/QtAkM9e6K5CUHrZrk8RcNNKgDJveBWpi3xPdjjVqXPj1gVBKnm8ObuhyHPwea p7492PlCRxGAwUZzBH6piFELT1mcUJ4/KBQRDdz5XYlCj4AZNSXGdT/y+BDp2y+NLRyj3c8g2Vco SORKZyqQbjaA5RdFywp3iL7L9O7/wOlDl4ys43jygyFHU5tiLYK3EnPqTHssS7v/d7B3ZzrDaNqy bidoTAvJ+FICea7LO2IRcI8u7uANQuDg3bjVYtU8O+BUkC2tYvHfmqUP5cwCZHP5pACsMzKPoAIL 4WVQfIGnxggmgyNs9AVE6ywOEXjtmU5fhiIUBATbC1yPRtZAIei/HahRQxGt8M8F98TLntMp9r5O hv9NanKg9MUY0UzSIiPqYG39Gid5Wzm+FNrPwbUfYnCk4fwdco/DxPZFvcv0wLCJacMeWcwazfXX zZvJ3cQ1bEMbapjsWZP302+p2vwfsyCr3MyjkgFYHze4P71a5Ezkfksh0yDcq/yCU80p7q+bHmzJ Dhau6sVW4Rgim+DgfdIYoJjHZMI8K/pwJgRrMGuRUgWYibWpPt+cJjVdM101VtZBqsuppPV5JYq2 nNsplelmTWT09Y0XO1Rd6v6ZiO6kPKPSQZvRKoj4bcNTx/s0RdXq72uIvoJDAwTuvYTi9zggorV/ 44UlvY4qxu4HMEIZJXuhUBM5YRUAL7TzIBnTO07cN37M36lpQVg+k124v1rklt2G/zvZ4iy6je1l dLXpwE7MgFOfNJu6PHsON5Oto98N+aXhCvKSprNB/4Axmgisino7axRn3CDDHR8dTufBUTeeDJse g6toGl3TQfNJFevIHJELsk/Sbs0CeLkgcRN5TE+WsUG/Gnuf2Y7iSmKgisT0OJgQzUEuMTOiFbrX vBTTYrNZXEMDBj4yjVCub03w53JJFkxNmgvpFhrIhM6au9LRiovyezdzMCvdILr7WskQ4M9YFZU1 XiHgu4MPY1vX//ftStF07F2Z5AJBCovYVM7B/rkPS3/jenCKi7ACTYl5ATdSZskAWbpdusYICnMX SrSR4a7xzg0OBmD6lkEZ5sorKq3S+BZX9/L0qgZbtah6QPHISmLZB3NRtRxZ+2lVEPT9LBneZSYj cCmwQY6jVjcpLA4plMDXya/A1ptHOPCF17aYfIT6YQoSpwHP0ulfaujuxzzOaYu7ofGUnTy0qYTj +064HAODTWGtMWCORZ2wFmg3sKhaJarDjBDF1/o4y5DgS733ISEJZzSnIrXHdVVBT6byTbWOTBWU AMuYhoj5FN7yEjmDTha+qhK4QKkW2BBJv+HIP5uMuABNGWjaKp9Pziuu3w2ym5T+IIj65lNuFX+S z/RVmlycblju8+XC7ytMY6y02yZRgJWx8/UlmpYJWohglSMAD30nhOqeH8s103qAL7WaFA41WmT6 BWvO7tHOet8WvW7f+Q+jAFCr3o2pyS82AgifToaj9BPIIkE8vHA2eYr0mkunxDpOkKF/FdpDW8LN L8JTdt1MkbfoUQq3T6j7iamxTsZ/QGiPflOyRqWOh7IvA4KEiEg9encs6SbDyJXQL17s1dUMYZuL HGG/FZCNhgwkqdlJ+XqwJk2yfCBPz10UH/+KKYVJ9RZy+lR/KSxcSCENnuS/4BdBZf4SMzW4EWqf 0XLmtfD3ZvLpzsGApICDtt0SjUrJE7ON+CIN40iXJ3MN+WE8OCe2nB65wtTIEO8GwzV1KpUzRndB 0cbcLAWGbkDrdoxREhp3LXRfctfMWYY2H4E2XESXsqfOJjALf2/wjbXHGaxjXLfszw2dQUWMdqTs 2FF94JJtflK6gjVP9bZCc5SYcIuVBIk2KzDvvPFgp1vQXchH3CbPyg5yYq4ScpnCvCOKF13vSjSt x4L8BsU7D5QUoSOd7qj75E5rXw6AFwEg9hynypjVtY4oqqgoh7dCjOFA+jmj8DeQoAakBTyBL1/b a+5j83qgNansGzyfsm688mCh/tOaAos+jNXQ6rgmZkY7AaZlJNaaExZSaQsQdz+1bBm1qbvUHUgC 0z6VhUzyjIMPnvyPaL1wmikhxFEJv6meq2h+3Z/7+WYrE8HwlXPyDmJjQIqpnadVLB06ZjYqHPse SWr53IOI1f8bORiReI6KJs5tfpB5mj07S1BKabXlQ+W/SM7UPmq3SVhjXhO2Vtyaf/pzrS/1z+Y8 xJp/Xvw9noxfjXvW1XtwmBW1NeJDwI+BfrTjwMH0c0JO5cQ2+t1XaI2A4+XbtZ4VZlNZWhuJOQLm vq2guavVB0ZsIGQswn/5ReSvpiJFhDlQqzkl49D4hIHUSGTMU/o6teyqnQt00RjFAQkYWYpjY330 QjdYq9uQFOJHVKPQrnkE+KM74OY2gm1j0dj4zRw2CKHYy7nn6GkTPiKOPwHAse53P3FYxvtrGPZs VrD82q89LdG+ISUJn/EF321g1IXUkC6jeOfdd04/L4U/RepDDrkND8YJF6BQl3RbKOLHqb8U8vvy j4d9z4fH8Z+n6ZFoEtnGb1DTLj+UaIgjmhOpyFX53sNJ8C/QAKE0T1gNb32jIBtQBoViBd+NUnrY CnJPChYRnw3XEGB637248TDYc9Mdyvjv4kBslCnYQLN8wYAKZ2KzpJXFZxj1+0p3PIKaR1wTH+9B YXMjk7GzfN4/FMhLX/ovnAWMzPd+c+CxvhmuuSl0Un+wRZnghsJltQJ8gLBFj6luftkPtywXS0M/ OJKooNiZOWcv2JMliAViw6qRO+oWuYBYigqOxVE3/A2M8wtKzwouYexVmUA7gJRRSzaqJaqkL8IH ggEjrRspBhfEJtkF+AqChmhfP8HNnEabPjEVboqT4lTK+ccsXsDnPUg28mul6Rej7PB0y//L6l9+ UeeVr9Y0ncqHyCBNOfwHetvYuNKwr4gNIJmOVEzdX36lVCnMo+2PTXMXAjIcDSbT9YQr+Md1n+LM AcLGtGisDOLeSIN6KVmMBYx+/DqGAW3LkoQ2nFyYAmb3vp0PxptmjH8lYQhwtdESatg/ucL3Fbm4 QnxmuFLE1klsnVwd676SyoP89Lu/sxcf+CqBBYsoFJUWMtwFsX39cIUZUxg0dzFdb7ZuC68rf9kk Adt3iMpxyy8r4U3TBM4E7XEJHfWRiBxP9vtM+1DETX/+yhG1GbO/R9PBrm5uUj2YvEalLCBfxIew bitP7OGk2pgoxB6OiFbSdSzaWc+UcXo9kSXYmCJ47ckh+dxaIutrcXHUAORhXVfaE92IhQJiuzlE IpHvYyS9tNnM1/MmnJbgNao+MQIHKaoAMN3U2f6WU7tc7/KO+lLCPhsU65ctAm3q+RPbS1DK5pgp 0JxPLTDuSBSpPwfrAMUL0zYwT5A842SuVZjgZUQR35Vii6aN4NgkWJrojDhaznVyUr8Xlh2S7vkH oEtRZsZDdC68jzPu2shn9GGHjqpMh03VSNjlLKjO3dlZ9XT56V+PWf8klx3pTQXPShyINf1fAgJb SaAQBcyKWJ9fmi0nsXdGPRGBNRXz0ChAdXhZAkrlPTFtZ3VLVZM25rZ9PGzPIQJXAEybyq9byOxs OwsEn2ovrzXnd1j4iJTTx475OFH5dNj8anVTdP0N5wLMHxmkqrsPAqxspvU5dGlOGoSEMFLld9Vz yTTL3C5CtzVFZ8/BY1ljr6+a/e3pndmiRc/UXzokonCqJ1CHRonrLNIw52JglZ7Ps+C55ZysbAZs dqoOyUEREuBXOkcbNOeWnPdgP+LQ19qFnxgG63bGLdWYr/YWHC3KEcHZzuRZwSubTqoftpdDozqP jHFtn/QdkElaRbgd2KwGNusPuRg3S47LarILSzI3IKQ96HJKQrB1dSZn2k7w4SivCTcrBOSriFUw ANzSaIcfx08nf7YZQjqxSAeE9UYMENHvGRKVJ/yIF2cdAshDtX86yQvv28AhfHDP1Eh9WMLzYi0L CZhA8v3SvYb/mo0u+nTZZJPgS4AvEOfBp/g4OIp9ApHj0d/E5xl9H7qTnnY2TrBt0xdhdf9ChaA2 Fgv+cTs4cYfhiqk5uyGdpU7lOP4eQYByrZUpcWmRrZhfY4OlecPgp9TF54cPl2iZk/6dk1bGkUyg pc1wiEw1ENDIFPNNrPCh5jjEFZx11gN+yln4laIsJondT8uHPrsZhOmGlqO9bz6D/somWLvAJAIq YKq6uoPTUpJy5OTWK6ofcN+wpx0v/0NR6vBwKgFBW+/f6boyh7OMXJrYkJHZdmh+gjm99FgUXGtz ONBM15feJJ3FLCCkfpGnyIODQ9XO7O6BcreilFAKzhCTel8VnzczowNUlts+mBFtDT0Z65U+WWtT J02LHWUGm3xfGW1hrP3pInIwCx+XPDlxPwnw3nSedUuKBdofz01PaSH5bIev8jeF5ejAGxRlX7ht HAUC/zH3hVNJUvMFtfsePAxmw0jajpGC6zPa3Uxjvo3XD6CT5FL/BvFTKbt/r10NK4hq/2TFrOqv 8bNPOqIwC8bbJcwZ/9nB3fxC5RRblIJSoGNUqpn10VDwKv/U5uAZcBwIWVUfnwvz8Yje1i6M2cfA muFTSEeMdevHxFvetXk4hTvUvdjWUjPwPkd6w1V36Z1EhFvPygdh87exAeekZmLVBaForVvbDMKA YZdRnTcN5/PSIpMBLFx40W5xm9S+AndxibO8dCr2H/n3VxpLGHoY5kxkKf42zLFcMRp617zieglT wNM8tnq+qeGsiyhcjV+OJn+ws2xAjvXYzxdxrqK3eBqnewx/upSQVlugOJc5DP/LC4d+x1Oxj51S Ctem84WdqBkxCzkYqvozey/e1Au+Zr+zOJCg9D/EF/zdVaxPVOeaLfzYyaABMgFEEzu5fZi8a8WI 8OI/XmYSqGL7beYuCdGKopxOBNg/Qw+FvtDmupYukKV3z94CfUPaCgzi4eahZSg4Bht6VcgPPYyI XCGpCBEeJ1it6HO2jahCvXTI50vPghZzhR0ymoK2+2leEe+V/eLoONx2dr5YDasFt+E45Tr5NaJh OoASBfOe5eEmEjCeOmyFMUtmKryEhP3MPomhtPZ7fh7XkoUJkNBOfpLKqRbemXIGKoe4FPf8YF6e wXUiG1i3PUDg6SPKXK6wIxO4JDiKlazLPcZxBkZoYV1P6qiOTlpVyNk5XG8WxAadIBnBsiAlTCq2 Z/miyvmBJm6YbHF9aXkCfW6PuxJ2NxYUbtapeoiwv/jWUuf/EhO2OAgPJHwix4XAEV1JZ5qzLrIv XlhNQdw/g062LcmNdCwA/GPZj0uEHbkpVoQTbJyW/0t8OEsXusWEoLM6vNPMBUTjbedzqY8n3AC3 IvRTH+4uz6N+eSC32njz3pro2LSMdH8Apruj+ytDEcxwfcAbF0ospkNUy2mo6UsCY5Wm0t65FgCO 6cPxJzMlVpP6YURoF3JMMs593u2YXBkCMag1reeSwKJXJlfGTuyauCVvB3o4L4IKn7J4OXFl7UGd 7oSZo6AfMclsCZT0anCpXhS2uNV/7Li/2qw9uA3sugDNpDqtsjH+fSPCK+wYrm6MWM65zi2CvcCv FZi+wAOAl3QXwNLLfUaE3mMYdFx2pLUPC8trG5S+4EXFZjAqgWERBwWvcymZGt+1XOudWd9WWitW x5ArjPCgV9IewCWVk4HLFVNC3Jh+pZ+R/Za5jMsvGf3ZMTEpY63wDBFvHAdQHPxwGSb+O4BIDDDX N7iR8TsLxjdReIpZ2yngHkGUpn5o6HT4uQF13lyczJpfsKow0S7C1qved2tkRoL4qE3NYlohruCp 71g9oL3YqjtKh61D4iO32emAk0M7F1kyjbzNAG+FMFuPA626xu21bUWboJ+K9V/BcKlWNCx98uHe XX1ve0BiNw2ShlDSq9a1xRdtR2bdus0A+V6FiT+gZzgBQ+pwTO9lcg93c7jdFsOElilHmrS0pdqe hVKzvaGk/GJ55E10Jin9515BFBgZHrN5uD0YEBTZNGId5Ab/OT1XlCBXxIWkoQpdAKuUDXnrsoF0 KMpv38TOWXSN6JhXQ0ka1khyVmSQHpDNBwCyITHA8eBQEX+njK23NaoPXRUOC1Y4KB4sXBb5olLO 8JJ0+x/XnVJCsq60oOkkb1zNkHEVyQntAW1iAKFIX3HG2R01DTeyFJ3ZqDdRTIyiytL+VQTHf39P DRl9ybX1h010HPIFX2dzexTb+Ri4RCRYP5wkyRZRU32QlaW/iZIWjxKncY6svox6YIO2uqxkP0Vp WA8xZ7Z4F4D8CAl/3P1Z6mzsIaD6l6oPbw2fpBK97vnBJdEd7R2RLKP6eDiIGGcbpapPlqO2ciVk 00tEavx1+S7o7WVghqK0wk1hLulw1H8FbVEoIlSNUoNhDjcwdSUwvuAiurZUS+c/Fy0PNdWZso7N Is+dQx0/AgF/UJlNXbJi+i7bb1nKvpTvLpd0kNpxJhmX1jdD+g6Oc2DEeUfnkqftVd8sfytRaR5y 2RszC/2rNsDBE/bvenOykQFjRjJdbWKrRCSvS0dIUnK1KR6TlpHnV9G/eljnnD4+bC08R94H33NN KCF7a7iZ0PVh30pyQIYkQ1DWe0/xbb7hOlTB5TGeN+ym35I1RvqOYJp3zYisvv+ZiDxlRcyDTfeg IvkuRX34A2ywB9/XmRJwcmpkBWN2UXfqt5cFmZELlKAzhtsP+KsCbxC41Mc0540u+tPSWTpZdcax iv4IOd9viv7fmMKXwr6zw0Ach+6mQmNAMyHtAYfZgzr+czqY1J4DVSqG+uDWKYs2wvS4mBRw9KzF 7QqIdftvddL5+rDsKyeSJsuW93cMVpiHiH0EQoImE12rLdD0hKmt9sgnhEDUc0EWm9w36k9/GS0F k0NOqYmg3VGHFOlPgQzp8bIqZM3LawV/Dbr9I5Qw1K3oow4g/cvJa0SIkDebTxR8Cr94errVMKJJ dHdR2c80hqLqN2kEFHsn033bKRTvIS74D1n84TtlbUvp0q19stXCALTVY8BuqOw7Sr+OBfEvcI9e gQW1lzxhqAMN186gra/crXHczvMccs3PM597RKWTm2rRT6TfG5jzaZfdANCww0F5ynec9/ALLVDd Tuhl+7LLgNByF2xA2ViZtW4Omk9NcQx0CDlOLZI65U/Td0jmtF70Mg90roEzNjsIrWLS4lkkFYob db4tlN3KD4GyRF6/xWGBn/D7XnCJSVDGvNDLfUaFYrhbh67RYv5UblVfWSIxH7EOvNsyB0gyFack L2undMZxI90oj5Em0NjqfQgfB1N1k3A8rrnG6sfm6QKoJ/4C0/EVB2V76BDTo5XSNuGKjCF2pVZv v7O5dFdG5uCoOv5N7rlEvgyxrBtAnz/hXgs6yVRHnzJv2Z0HFzH2jvcTw/Mxu5du6GBN4UKluVUP fzechnl3JMcIFfEQ9QqWfLH1lWhtKFmiaGBFjA/l3V4kz3OPey6TT3WXbZXjouuQtRRKtVeoXpsV I+ZCo5U4cA/pwgUVOPtwSyigvZHJcL1/6SepyDuAKw2FMynpBF8j+oFWtRpFGYvkCU25TUcbs/c5 X2VrW5LhxwqMNGxmVM4AMh+T7PYsQgHUHdVwOuau3hqyVfZsTcHU/fwqRtruqcNuQLINztfzJZjv zNZ1lu3vG5pXAgv2vKqrXzFpUOw3nZq948ZUkgUKANQigSL5rxxAaWgwDCGXs+Jj+LSwaIW1dMuw 6Mvq180QX8ixRDmkmxujK59VnnRns9W3RvPbRR5U5VeIKScnyO5XEMY+tPWB6Gy9AMCbWFJ4qcX2 QB/0N2rS7tPtdkBMoFScxXLLrqALk7EteSL/wTQOONro8XaeLvtLnbq95lb4KLwkN6mHKAeJOLDR Frd4K98s16rvevV3/REL6mz28pUQBFQDWMgLTKrFmITlSBNyMBRVETjXKVT8x/dnE7tRATozmvBH UmSImM7oKCbgpziMNedTnI8LzmaPjXS4xsXYhEBgwwYIs2rclADUU3TVDt96rZ0pdVCInZN15nWp DJc7/HCWbDHTixBDAAgzL/Q3BnY/oRHqXU8KBGWhbWUHni+BxKpEd8qobd757xEUpO3hF7vanaXy 5JAfpbwVSxi+8wnT/1/bHYPzq7v/opQ9wWcrsiE/yOtM15e2VSZG4PpZaCjl8dGtZFek+rApxkkP XokRNdZtKS8g4HRgRixEC6pLOx8grDsmgFtamMhhjOT6GIyP5sT3VAlnu6Zm7r6YB4O0sNx6TlNL hziwiNyZN87bdyHlHwwkMeg7jOlatI9UOcziP9ETLibIdqDGtWYg7oQd5Bb4brLfgF/cXpyPgoO3 p8x9+XuBn1XUPcVqH6ymnqaryfO7nWx6Ie3gUSLGOdlt+RNzE/BQugIdg6r5rLbHqFRGL3fsuHrL Yltnd2hHV3Klq75cvlqWewPEHlcRU0KfXSEF+CIu5YD6M/lRu5esGO+OMhPOhjYC+YRXcK2nsvIM ojR1ji2pPsk+sCh/KPgSnc3hnIETRlY8fUlyeHFHk6FSt+jOBQeKV+1iLVCkEk0VYsFarzBoN1H7 20u8mOisqehOD06CuhMD63fr5biJlPjOqhwVHsC3hhOeXhjrZGlFuewoF5PFbz/5iwK5+kqRcNfM VRb8OxOqDdiWLwlS+AQN6klG7LCAleqDsB2HXKMfw5DRWWls4NP1hHs8EBJYJJ0o0chgaJqMFtYO pE8Y58pXp0DMHgn9ptT+NU9OiARiueqzPvB2xu+bUPajX67D+hAwLf+aOI/y99gTpFmkenKMzbLo J+l4SipIhFEwDIVRe+PNPEFYqx/gwHkcRrvpYWF9yN5ZgI2G1L75qcwrqytrLSTdm7KgbradZ9Cx b2nTmDzgwA9Ymwc+oNNbCUWezFpSdTWGOQYAz/RVl01Czda3IAW/injJ1+x3IUfks5iFe+Rp/SNP LLzvXbz32HhlhJnyTXSoA8WSWpSccpGSgQzRdAG1WhEZnwE+vLQJrV4onU9m38H/EQP43YEFHzCM V/cGgmIbdfZqW4EYHEEf7NbkCh4lJ2Bqnq6prXdKaF3fs1mRgf91jtMrcLvReE1siOmBXFuRMwal 7XsMQW+cwl2XAGJdXIBnpxKAJpIO+Voho9vjKQHgPJHH/dPem98maDuJHou0qcqY4LraToyZKSuM Ggg+gdg9yThJGae2xfU9Z95XwiPN7N66kNUSkcjf3TKADz2nRRo45PcCsdNXTiD4mpsEkNpNKf23 mcLyEp1qhQWH4m/wl5fROpO4lpfLl8vYbUIA69nQdzHGOthS2u1YrCMFnu/Y7AWul5TUKfb0cvbu +arzldFVPUmWjxIkAeixwn0nGANfbWxBy43XgMDuaFlWrB6agAfVeahB/RCAuOx1bIvneomn8avc c/0BacOWMEpNz43ozKyPC/m9dH0a4CykspOXl3YS38pu/cVVs+MrnqCzv1QkQ5ZN25fVftiPPJ// qGOL/UKYhzWqc605q0hSkIW8w2myXg9lmLzo4owQSitaWQwNZOkckHOpFj51bfgYIWr8hLaM4P8e h685s3UfnmXVghYSFYIZqIGC0APqoTEPwCcOFzBVX52FH0y5ViNy9aUm/q3aaSzKmrz8goh1HC9u QFsPljv0vVX080h3y1kTsDyfFd0PQNqvdfHudRsmeKal4/ymLe115P/QzPnRchTQVh0zw0oBPKAO 9JM1RFJWSHhEbwci5ze2woU01Tut/UtyyXjoAMEdJsEko/sPF70Iy5CB7REQB8R3XMxOzVLCpwaL 7ptoaOjhFu42eCXsjeg3hiq6GS5MU7PCbe2RerCajMj2IxDuoz2Erxe6aR4RmTkICBIAVj1sqeVa 0RpWEMy5jw6ABjcjNkZvvKVxR1X6F52Iv8Dkp+qmlU3HKm5uOA7wyW0Y/453/dy/4gMYSQWmcXRu SwtVlaPaOih9Ntupzr600GIxnltrZsDKg14skP8YHb/Yl+zsDF7hQDqfW1j0jHdK/lw9pHUS07Hh mxtIcgxt1hOwsslTV9i94ve0DsQMug43NNvkapDyYhhs5ErJuuf7TNg9vze5nYuHgBJJbQYgcRAs ZlAZxxy3Qg/4tDYm6T75n3cZpf2OiwGE7rQNs24QIKlEKwUf4WR3J75YyOFfqgRXOV89jsI19F8Q +/egbgABrzJvq/yZzY9I+OGA/y25Sft8tfM5g6E2a9MhrOtjsBN8OKpgyJZ5Z41aYflwZbgL1mPD jmi+mq4kNL4YQmMwDJOZOAuRrH0tin3/mxaV2AwFl9zg2Wc1qzlsiWD69m8aWKEn5xdG8oiA7U31 KJtKL+LpXbkN10spppFxQeZt4T3GQhURpQPxkfueaFo1YN6QNabZE1FNnX7L/ibzesHiTpflwzDT 174BKV6wjbvsF1PthE3LycMu5uGjAg5zwi6vXUosjZBLYzC+qr0TjScj88cXJyAsqw90miuJffm6 W25NiiLWAknwHcP5zlBiEB8W46V/31PBomVIgKdS7+6mkT05Z2dhSzn5SBaPap0DNkHR/CoKOISS QPv2tRg6IisPMxfn/CF7anPRNlo5JDWy35TZxbVMTkXdhoa66G1fr4u4bxKHiGecGU7CRjl794vH zLfP/zMVJyo4olC94xnTw9T1m/xahYzLfuZ/Gh8ht2naYE1cdLmNQWkV6Cr4ecyTRwAkeZ2qK998 tAcpWc0pyNibiKCieRxzmgBjpsEZTxpX9IDtA/PwPsrCtRi/NnUuCZHYxubJcFIrCqw8FYFBIoQX LW/b0ahvDkrp+hGpnHmMQYCOJPIGJFVFQRj5zYGfYGUrFnoiz786SHhoI3L5GX98TA+GAUTBr5kC mrJbNrFTPNKngBs9LZQoebksfvz+uSEVvfA8Wn3qDWZL0O+PyiaNLfV2jeVOEOnPuU9fUDqh+sNI oy+ZDx3k5TMaIbF7Qtwyk3ailnRX7t8bd9mmNf7RG4Rb+nBj2DNKbPoCjSYLZtPQ/7+hgSKcRU2W ekNmoivMjeh80j1Eyxfry/7plXAXMfhwKKVhnYEZqGkv6I/xbngWvuvlnSj4Wg8wQtlq4FROX/QP DfC1g1JNHfOxk+BWxVTfXTI2OOyex1CdGjrComdV/TfIgjSZ/BNnRCB4NAdHTzrstU00sCtmdhK+ jTrSFnzNu82EaS12lV9tcND8vvkZ/ckjvGr8jAh32TsIOJZ+S0pEiillrT4ZMKwecNhqw9dG5mpk ZRaGDHXp6DR5H9He4lYm6qrqoa+vQSyI5RaarTdlO9xp2xNoNbNOKujlrdcbYxoBIbk/tkFylQvS jRtkikPcG57RLPpC5V60cWyscZHyGLu13j1JlpQ8kJEU4T+EJreo8Vo5Mueug8WhJ5MwoC3PTaO+ ortJwaU9EsWPydZmugnFB+W6kLMifQ6lPIbE3Pz3RK5Ky76rmODbQU7lhjCHGKJttAA6mOHezaJv m5TYLDLWZUbxjn1L3zwmUdV9TKRi1OgiJZyQkB0d1FQ0hdXHcvhozazCCYwZxyjLsJROZ8BaVeP2 56XFdTG4WtKk9DZ857yien9BgdUQxmWl5tfbkn5tJmSVmn4ttIWpOVrL/uTBedD3ZlJPsfuuMlNN rTvqN4e3Bs7cmSmLCMLuLA3uFl+456ZBPbHHfZ8tRIyvQlt86QkeP7NtZyi+zp3AcnODvCbSIXJU B9beDWtpAEHSegzEzsoKfv7BQDgLZP1O/xaVdyjzPADDQ5KMsyU8JLCDFz+l1PjJ5MtowNxUZTbU 6TnSD9fbMrqH3vl1xVsIcPfGbPraZ79Ru1DwF0dvAoVpc87eAiA8lWD2hvU3U9Giqg1gtswM5VZ1 DZjMbjRVsprauB+2XVxfCGc8KCOaijBm58sIur+eLEAIssxSyjmBF8Ck2AyykuLoy70m6WUrBLqH HA4DFRf0H9hFLd76YPIZAdKg4IjLJNt0DiqpvVd5dCHaTa8gN/H2C4y0ACGO9da86WfMZ0hv2AAq ALUe3HbGlf0GeSAbN1iJo1N60hGfiGEl3ZQCHzb2FYbT2vOc4ceJGwasWDtHM7H91oE46MGWqCdA KjniIqjZ9aoQ5Je8/yBvj5L0eqq+TiXv6eEJF/Vw6U1X+irhPobe+KySI5C+US8sAitEQxxhhidn ydor4OWmW+4OK96GShcIdatoPS7N/3xPUhnvn0jFAJMJNZvJBtf5GN+TOWHual95NkyI4yulHCTi KeMNJoJTERtrBmO9GI/c3Ml2RE7Z8l9R0NgYJ9wab02cYCJtT68GybKwNe2/DjGNTJuhXK/R303R 5J/7CNsA4tZ5cEh4Fcg3CEf1vl403+f5ga6wn4UH9J+XP0/D6WIPHGyJkBI5cb6f04UNHzfgTe9x ue25xZJFhWJ3oGmo4vE29e2awJYJx5p3DKExJURDzvzTQIqfrPlc/vVUoxm0j4NtZL15X7Jz6yJM skLDDtb1rIeMDwtpp7PVliXwnFKYHgAIJqyfSpqKr3XpguHU8vmqZs1JtEbURHkjcVY27vpFR7NH +JWm3i/RcBhJk7l45CRyeno6HW3Fa0LRDIGmyh5rPlNcqwN5YWLCtM46X/mjcLr1f8cEyrxshjod 8WaXxHidXoh+VNWja3XrPBAsIAXpdnC+1oWEhsuRlFn82cskG5zEM5g/QTyLB8svQ0G4mzXSyA7b Ln2PWkz5iIGOudw5quuSzicjD/Ao3S6KZEhpZz4r/ShoyV6GxkNzh38c1EnxUUZWIwm1WzU9LE1M Qs1eeMQFFWLw/aaGYmZQgrBS3HM4kttZHLG54TKSTEaEYmbrhaRGaSvL4GbhxDTNTDVyI33ssv5a QNPOW7gJTryuUnJN/G1TnQh3IBzgDXX7xb7BvQkDKi95ySxtjfHjznmeiHtP2fMSg6vYzn5ZnUmT +Bvcaepp6jhSZ39ZnoqX4YbW+Qqw4sPlhFXrz+3Y6+UHaUpjug2c4X7KFpNsY3x9BYHEGx/EKFWU iQMfEm8d+0qFEa/3P03H2n7KFRVVmBtSIZBa7E93KedizL9rLR7w1pcbYz8AZUKBtFKlSXtFtIlL MKrUyQW62CQp7x52OmuoIgqeuM+JELTBpqZYdJEHaGLaA9+N1pLl2ophRaTp6a5irJdc2+PxrqsC rCYRcG9+FK/x7QTaYOSEo8kgAA2dFuEvtGmUXvpfoExR1MYS4KQo00VAEbuJQrZdgfzux1NNIzRw s00f+sw/wOGyZC1BjXsVNmef+cd2KwngTbFow52BUtjR2P5OTdvfthUsyMA6rOIRhL6Seq9VkV65 alL4/fOe16sSDCvVyqGjPMTJt9CYHJSuQC/+RC27rpYq6umy0WmKDmYW8InQJt+Tm/ihwinYaJps hSgbFRXPuLvYTJp2dlfgTUzXxPYgE49sfuYHOJNOFz+iX3tnUc1S1Wht0KH4t4sqNrrRElUwkmNO x2sXPGKPv1BCvqQEqTsFNr5SnByRFSuZw2ppO+20S+6POIWFN0vv5ihqckWInWHpgwznmqEhyUmg sP28voDG6OmV59iF8UDAbVg3ztE0ABWlP+UyZ/DhuqKroQ6WqGM+0YZw9BnFmZgHDHr0+9EhHX2y 8GL/kJZHL1jzgIUuvJyUS1dKgU3ft2OMMeQeMecMZu+0HIZSc7ikLoU3kQOQmNfmVLaZGsDF7umK tIFOC161oZTALZNIjJGxwd1lVm5i6Jkdi8AYm68WNaFfwWLXYLm/DTlT/dtEtAch0SqIoLTlpbQp DEE3GZaxRy6zZ8eEErnOQKOFN/lgDo71rySyh+ZIM29pGRaId8j/PZ/Dm6pVrAUG1RxNQihhDxG6 1kcVtRK17YaNjcR5Ps76SMH5xuS9aB7eZd8+21mXtcMZ/EbuKUi4D/j8q0C1xLnse4ROBsO6rNy5 orw/RbfKr+x4w0AE11Yp4oXHGHBKLfDlVXNJ6C8VM9vAgjU10azElNAXKBRyS6HwrCqxdrrAKvKK EujT8rxjiK977qudW+lXvmkc8RzRP2nWqFuQ3a+qWz7bDWg6VeD53quimdxbqMZKESBGEnnjHDzk EVp3aLSfh/lujHMn1vzcJYsS9ONGLzRHgPQutAuDMIH7y09q5NhF041mhOMVhBvxZvZ2Qo1lX7u6 Jmp30glQ0sMjywqRccpFbW2v2C+MVPK4dtGvi5XnyS/QfJ7wLpIr4ToPc2RZlApFP3JBAN+/jAAV IoZ3Gmmk9XZf9HE2iyDLYimvGLf/2KqPj2HLFyOQ6HGpF/aOzQUTdWa+l+Q/NIA58KBBIKx7Oglv 2eiltMYRnEGi+kS+gr+hdckrul9rO2go9Y6tBVeJ/dU0rmNibxYQM6OPtKSFZMAAaZBSwKuzcP7u cvR8JcQvjNVxyQLNGjEuhVjOrQIhaKS65KUlWhL6hk0UqpTV5qvrIggnK3XCEj9Lij6hR2o+L68I eouamSF4w3h2xHoGvPDYskiMesEEfhFuUfN+4pxP1l/BFBX8F1p/xI9zMI8j18vcwo/OtibCZCal rFOfACjfN03lGCcEadALmDXsO3An72fzEE2XOfEAtlY15u2l2axp2V896n8nSjQxQXtQM/2fZi+C 4ZA6NDN15FqEjqoiFv6uvuXNAEvH6y3v2Q+WWgcYfhcpNRwPQDVnVlxFpGgi3KSMvSAAjqZiKl4l D2iLy8idoaPkwdL0jzR9PGtTwkvlKxp4juNRk9yXWS0+WYsv4BDBEgYhwKQ73Du+VjmigymOeDfG T15zrsOW0/pgmEdF+cUcRbaBQexomBnOtNUGD3LVX+liFhKPfsP6YWGHjokWxOtaiT7Lg6EnMZMI g1oyIf0HUFZd095Pkj5NaOjO9jVhhm8+HptLuXRqL2as8MHDl2szpDbKYU8OhOAEeNJD3+LZw0o/ sEJPJ6gY3j/IGA8Cvsgbno7lGkfTR03gDdJP/T3mnAvBxuefQhohCHH0tsY0pE5QHq4WBUxGw7CY YDPi5ZXN5ounXTBJfdCaO2fDR61p1gZKbXwteVZlitVqpeEaN9UjJ7IcLddDANCG6MYPkNvqiUsd XNEko7A6XJbK0p36lqqk1PsRLKHvWUgMBTmZ384UZjUgbaU0JGpnraPNbgWxFQutBoS3Wl02sZfE KJLBjwU1t7m0pmM06NRfoiyFy5jHg3bha+Ox7ECW6PvcLUM69H4K1WFgOJSdAPMCLD/u61amMZel jJ7coJOJzEdRjAlIAJ6OE8Vve0gXkmWgDWJK4nnME0PorBNKjSiddv1xTLxTN60z8vf6SsLIWNYV NWyeT8igtJjzrJdolYapRnTDREp/m+tBYJAISKuep3lYuBmH7gIO47K6dDs0jHF9D26OSkjUediy CIXrr0kIWRQu1oix+0Bjo0YAdqz4n7ixhTnkDX//o7iTYaLqBlURe3q2hh+esn8fcnzdLa6qCDKN xOOBTIfr+cWaNcX8kkuExWYI7f7rp1bnUtnSGneFzvP+nQu8camNpKns+hE3Oi7Hlxx/Tj5JWFNH qDogCX6Igz/+mKjGq7KxPaAkHBxieTasBM5DXZcda6RnZvYBxJM/ZeT8GtfxXIvMKZoBO2dlzMMX +UcXA4sGlHXrsfB//dwzkPZr3UokCjRL8oIBjhAXUh94W8IfGxvaYjAfLlX/TRXBwTHjL8Cuzpqz CExmqxZNLm/InYTs6ka6suNVfffp0TpEHVkO6tM0EMjB9raDy1US0eketn38ZZa8cWsejGMU2VbX 1fqzC/qYdQ8VK0zWtxrRcRD1F+E6T6WWP5uTyu0pZgrUs6i3A8Zn86qIynTAX76kVKOSdWiYtEbQ ZIHdY+MuDVzFDlzagAkHllk2BmSAdTgj66ZaIzXH0wMwxVJ5p+HCB3z07kBa35KSHABBM2vFzWdG 2Wr5CQr2G5r36EA8O+0D/B8lL925W7v/twLMeDeRxqVWkPRbN0M1dvuuQyfuGjEeRSrkK5BLOyCh Bptf/4RhB7u0Xu7LR2jQXA4bQ1ves0YI4QxEZ+jBeoLk4v2XWrMFjRiEynmKK8wCkZ+thmLAQNYo iBethJZdhVKly8UGZUCAlhPH37I+wdTb7ZAPjYlz8r9i0II0X2W7LwguNAxV9o6xVo+plQ+bkbbU uSjtJUAXnGXENcCVUQyczjSNLD310j/DPQ/l3OBkcEoL943+PP2jYEMLCiGObysu4HackZY+6KLK +t+KZx/H+helUY5C8CS2tCcZ7ALKXsAxion49Vmwsfp0Y1wzL4C6YIgrd3KOAm0K9yO8ed5wAbtz l0KQB6C9dh3i/oSSa2aU0OcZ7DxZosZwIwQ+cdKNNeaRIysxujWQeUCwk39k/A9GGyJi9tgjKUrr 0tmL9I+TX7dU14Lt8mJ07oCXVI7+OGz9mwChhEKNhXeOTAYsQ1vSp7JJiU7SVZJqkSvzJjQtUSh/ G194W6T/6exlan6dGGn7Rq1p+dltKw+7zDRI9l2W/OFsZqdVLoKwk7//2jMSuQan3QGrnFWM5Nxu qoWGnTdlLtwwt1oaAkrxOGn/QmtSlu7gvfKoEptOxefWDmHKXCOVfeiuP+kKwq1SmUeuy61JDaVd dh2orZbjRhDPb/vD+izg9++H8jiU1k8bAVOR4/n57nkrQlZ1e46fGbyTHafvDkKftPiHyw+XjvbK iKuTS5oppdPh35l4SloLQGzTSceZk7Uecu+U7vZKVuzb6CTaL9R4IWNjVgcVoaKvRP1Tlp+z4TIv 7vVnYS1fqEgD84ar+/vixa6eXU+FtCHbgJDxB+GYkTVvuh1RnRvLvH7YwaUH8g5QiyfungPmvj+N MOReiuYIwgyIKHHFGku9AzOc+MZJIt+1R3hypZUeWs2Sg8poeMV7o/Bh2gdS3rwNzvF5Vodszmfn t1ro1FtBEW3KgDMbyyk2lgBwByytcNBu4uiL8zHgntj64WojTK7B9+klIpD//j+FVMPTIGw3ygJY KNF+5hhz9mGCnfJjjnoonjyR0KSz5f18fL2L0NSCU0iFyVtQJYK/BdO7A0MkGe5cCXYYj9ceHMHh a81+llHQpobgwcPtwOdjpP4keri2yJDQXTqqsn+fJ5aUPOQZiJg13wQvTZAe62K/A+kUl/UASgyz Gsq2CpsvQVrC0dtlNzndx5z+CAofbi/ms9hTbHPklhmUizh2k93KdTlN33EC7dx7dz9wI13+gF8p asoalC5oKdzFZaHmDfjo8WGr0+Ep+aMmbJrFE/2ixxavR5SUyujJENRfWtoAyX7dfX4gdEx3JtnA lK20cQ+xgb4o1WmLqvEGWahCFr0CMkIjhMo5rbWKDwvXUdFaa/Op8WDrxD2efZOOWnEvqWBUPenI RrdgOVLK1yvAuOd+QI0N4xeeML8Uc9EV2QVOn+nJwBNaOknU7MitAczHwPPZ9tQSTSfk0SA5AsqU GPcsp3yWoLn6rl8EdbIoFXQChHS/xDJ+fVr5snWq1wmV72bUN0Llft2LuI5aB7/PZF7+i5COcbJT b2mrUYzAqOmavkOBnTbxNElufggzPGqu54D0nAt5aCJeXb12SntCWa/9hIAEa4T9D+4wnm8QY8aU VZoL7TdHxU5gITZsOoYKxtevMvt2XWTk0F2AzsbCxr2iP9gGGJpcQFB67cHL+pEEkcYaoVI5uyeP fRHnKovQ2J+RKiUDpM3ondD2diDkb8hcwWb97tTZS15KDuj3yA0JHxcnObVsGK8Vx+3tzQLUfUDF 4Mz02h5VOVPGUL0CqF0PPDq0DatXEnWKyaKex8LNWDe2wpqN2Y+elk00+yhebz4tKOeO+7/G7FhS KDP9DeKc9bmQy7strZDzyDHHY9JYDBy2gZeT6Y0NO9nIs///MAdIk2+nTfhEE0CFNzbD/khyuN2n iAlnzUOMgn9imAcnRcoCy0Mqmlv5L6bIcjaIlXr1kXIDx1GG8vWniqTohgOsL/77kGxX6cUXeOr/ N3C5qt3xAzP9UMAnmLIJz5k5Isk6V5Qk0e/SW5i8qT0SSes9FayyzZg/T2xe9ulHInQBIEB84wOp xQAJ7rWe/l6+KNUF6mmbUMOevpNBzC5HIasWxAduo8ySPYpAvLhG07ko/oSubXxWsn4z0vHytt6P mry+ucg5kP1xikLGfgAahmImH03AU5i+49sD5OFket8tHKzJ1tgUpSzECnz3Yme1OxEzOV06i7sj /DMQYy+mjhpEE5jl5ngHrfziabwE6mCSVkmW0BgJJBs7tYFwlim75EsJQXqfs4RW4O5bSah/R7PE yOKlsl2o8I1h/5w7ZqHjkzICgtODP/OJUWQHurPAjrywL0luWfTihn+IyxVXD6YyxU8LewosDlaI rs/COf7VdFCAfjyKNM5KikhDsCWB/a1UtiNwYttpXVksNkz87zShvD+SnN0KH29Xygj9PUW+kllH wZdegMdfiKYicmM7vMMvJ2ZobmVLuhI9rKXWdQqlZwUA7f6aLy+X3M6jZSVp8yiN/bK6OfqEnn2+ peZnM3zAPERT6jN2UyK50Kf46jXBRagpur2OWiTYDMzZ9j4UHhFRdbWpYrsuij0wiPepK6lxOWuS Pm2v6MDYeauKowghd8yOO7CAk5JdhOHUYmGNihBR5q3V1xm48UBToDmZkbCwZankVL6vPzByJsOf eMyqADf1j8kAupY4eaeJgRARyuaZI8b7MpzGu2Z5VZaEh/91Zuzizbljp9vqe9YX55hkGBUjDgyd nmlyS4droGYfMJGZAWbUC4fL/rWoFC7MxYZ1oxvuFHwG59TQIxEbKHSrnLR8bnnoAZm1MMiwFc6a Dfi/TDi5CWaO9NlfVeeNDijjQrZ9q4JwIC2JJqzziOILvNpRvgw0rAM0p1CABuO32que9CUU3qIL XZ31kDQsHvJJDmnL8n2CnFNGnwr1SE+VYR2LdSVry2jQ8F5DPFkjjbiNMBpYmWRbSFkEyLrNuKaG tYt/b4oQ1OwSCLA/Zu3kBHkGtsggw2bRjGPbDpfFKTFFkA/caY1JzVWLVGopJOSDpFHMydMOcBfW MP00cDLio6f91PQ9ejXpmvUxGjJn4UPzsoghM8XDQs5emtCwRtKEj7hGLiUfY3bWcv+y+72QoXo6 z1FoKX71+xR0vclW5/6VHj0svDIfIeEYNeta4Ai6OoYCPVI70wpTkW2nffgMHp+7WFzE7RsdHKUM 80JIeVjLqrSEXIvxy5LuQ32yFSlgUT9xeQKpuJADY30z7LQpaXCzxUJi97RDiNXq5eH9vetTRh7B hiOGn0SGsKHmIf8zAhdspJVoPcza+6gu8MlGB7rMGpR2fO2oqbzixE+/N5IVk4mJeATMrhV3lQCC yMqsm146Wd5kXWOFe3XDsmUBf199atF2pjS9hBNzHUfABXXDoH0/mAn2/LZJKoq3JvoRPetYr4jH mvhCL+0Bypo3cW/d1g4dNecCXTBdR6f+Q2eemNiW2XhmgSYJlqys7BsQnSyHdBLHt9DvigZYGeAB 5zsfzFQrv7ojw9m90GEbc64ZJqME2anq7dmFT/0DytdejTpWuSbiOjcfEQL0hKCK0EOg2B5jxU7l pgeyXJsu2d0PqjWZzkl0c8aNlcZyG463sBd5/PM+7qMs2ZwUShXB8rnBvoGm6eWMkGh97nJbkfR0 0m1ekUPyRBLxyJ6YJmPFlB3psu7E4UuM9OKS13N8zlHCbPCpI7Fx8EVpGQaV59tjZYSlCC4gHVTA ld5vjRXwtt1G7kwHFLQ3WxVZX3gbBPPknwklz5bNj55tWb2sk6VsbPoqionY3j3/2WdPY9CgBvwM CCw8IseDFzpLK8yCNbVP5RuUy0kbn+gpFUleARnY8iAabnSPtUkjQUOR59FkxFqZO8YzElmy7Q/n tsDI2/bSofuG0vLsLETTsOsktHswzQ7BWpaQ1nzKchCv0AXQLjJ0GXTvllXdOUAy5aLilaKunOJd HMA0X3bbLiOgfHEftsne1ventc2dhPQv6X+90Fw5nINd33RH8eNiSWrMgGsjh4feFYP3ZblnJHff o6R9UyJaUVvxbdHScYQCapHgualQxYxnlAGtg+lSss/rAZclJTSvRoQIaqYWeiKR38x9Cf5RNcaw 3E7WG7UWUgjznxzEcy/+1gitWRXGU90lXmNP4y4uJKum6SWnEjbeX5uyDF6P1leu4niGjd7vEcdv /rufQoMD71XChORcTQO0m4k4KgyAZx/I7yxH/dc4/eI3yJjVGOhGqlsM5fN15ItbwUcvMaVZbA2f TdA1P2NwBRJ3Bn4OkfyfuSsiUg9cCk8EI1cE9ii/giQwUwMIFvg+R4a/O/LMr9Ykn7ACDrMIXeop aZgLBaGv1q40q2CMkWOAtneOwCMK+32PffZM7JA5+zigh3WXVG/VwzxgqGwhv/WhZpsPCFzZjAS2 aO1IcrTB7sQqLAyIQHv3pv4DVQsUjUzOlyLuoKnkOVlJ8iRqIjpNZI/j9nlf59t4QY2LQTfkdQ18 hSDE1VWTXSvjHdZz+NRQ+qYvXvSQooP9oYSuvO2615u62mSVrB5RotFteoclbMow09JqXUbADsZa 2N6z/6izQpzcp5i4LKzE6mYNb3vgSTKb0/i/VUrBIb43tQS5PIBroyDKfulf0BUHaMeEpDQyZc57 ikTkILtX7i9CtCjGBrmSOODF4xZObBaAozGAseKCuidaNqHo/KxydhNtAojR8U1tcALwyMlZollH 7w41seoFmsIO3kCxQj5kb7YXEdFNMcwFnzkN4DeOw64QMuWZxZ7hvA4p/E/I0xYNLS5faLdnEBSJ 3/IGHrh3SqeN4hM2A5mQgAkBHh24qlv0nUYKyZ2/OWfJ4VNzT2v3C7jbeS0fVDMLx9n+4Pu0crdX VwM/4hDJ/VKZNCTjcsarYgGx2ovfdKZE+ixLZmxof2wnJKJ6jKOGLrT81ONtBrzYjyC/S/RfVnKb Xkf7Xk7aVFUOSrKDCkUqAYkhDfVPflsFfjep1Uq5vWoVXMm7zKHJ4jZ2bw9PN7CAzkJ+W8QlLr37 4Tyz7wsO7kePpxk5o5FKHTaXDDP6LGq7Ym17LgQN8VQWhxt7O1I5i1/I82sF0IMVjmjPyVDAOllC C7ZoFp4uo6PGehB48Bq5E2cfsggMMHtYBJvyh8usPsjYhVK9aaSN/e1bXYCPUVIucOA8jFCumvFm g2MgPO/tWxwvbKxyIwFpgjEiiAGSuSzseooUwBUoVeN1xFct2c0Qkr6riM0exP8yAbQSmpONnRGE i0z/qJfRJu8YMtqrN9HGhpHOzK0MLEtBd1g/5Y56w3TO1riwIovg2GeyshrVFIrOrpjyAcS7M81Z dukFvmhEHDLvnW5hfBFI2bdOf/VPiUVQT2n51I6vH9/PLVYQrdFQdaa48zlToWdWxZw6HTKGmTcW sR+/9eqXUYguicxE1XpQK9rR+324IDEgICPJO2o0BYRU1yHTevMq2C6nmNW32hFnNnafLK/YU8T1 aUJWYhqAR7p8Dx9c7UDs2sebdHP2GVtfWezal44Q9gOVAprtX1Eu7krrunoKhKMufQl2WuK9iDHu HreXQrrrIM/m0JJmsoKBC7J4t03BVNVkznYhA7JubrD+4Ug1v4qMVPL1ohjVhoj9OXkHT3942uGr FHKdQeEOQCp58HUZexyD3iqYLVbT9Dq7SZ6xismUegMjJlBLxRk/Nz7zx5uj5gqMkwwDzHJoigRb JPLrgl7JhxlgZEzYoN0u4F8DidpE+m0uYFMmAd9zwUAh0rCYIV1kIqgO/6cdLySrUQ+vHnTGRGHf lHbvWxyWNmjGUfDzpi5DSOB/HjzxLHdKrcC1EwL8CE5373lqgiewDqmTXQB312Z0PJj4/iQNDgod arwtET/5LvQOQQTpA0R2bJtrWz3KdR7rcAOu5Kww0ygsdECiYDojUGM/6FjJ5OQiIP+CK44rZOii 0qCqN83As4B9jjjmw5gk1d4dOOctjJM0arqbjg7QDuqywrmnfRzEY54+rWZcKbKDMV/tLCMQqmAy u1cRAo042OV9RO0B/3NkGGgBRBYHgRZKvhPWJ3SwT9SsRIjnILtX8uIBcpkRdgyf8k0wBMCm5Q1F 6YDfriYNe0ZF1NwL2CrgiwkT2EgSa3DJlRS4xCnS8DmVbMjYRh6M+S+quJeTRMm5HLicu8hRfcxh hCm5G+geC6exim3OBbhmO4gnBjNpHJmpztfL0gOHJs3QVCZ5IeJsYrSF0wA93lti8Sf5W1CATxFs pm/08bsBJmtsA+N8kFNm5I7WBzUfESn62Rd1ZgfM5LueOrNE8+qyXGWB9jCbFaBcVL1E8enkpYQ8 VaRc4jgb9thoN9CX7EhurgvV4aWDeoxMuVVwGDg/RsP2zwMoU3oJCr5r0/i1R0ihg1W9QyVXD0s9 pxH1SlEI3IEWTxpV1MffQQjLEwt+dv0y7kpfzJsOE4mOxMScTNphMUyyoIm2we18P8Fstw3pfMae ncar9XOn+R0zcDbkF4x3UAI1BPXpEXIvLyWyK8v248RWDC15c1Z7ftSrxm+envItzo187mX8jhct 3prvzGZo8ZAi88HJciTkSJFGzZ+8ojD89IMxcwOCcCziguHnzF0Tn9mMuyavQAQj8pelHjxib4+n RIPEH9se3RgtqYHAUFD0pawsUsNYnY7t0cqdaivH6wR0elGCvBxkwfWBy08QyW6xu338ej+f58Zj QJPPiQ1+KoFj2vVHGmKP54cFXVRG0dIhEn4ihaWJ1YYexd5nJU7cmpLCqIOv2NlqKgKfigZmu3eo BF8zEM+q7rJAAaXmgOrCJzNRZZdUoUKHOFrYa+pTJfXpJMOsyJNd92Xfui7IuMX0VzQKu7rOAI/0 ARnnwsDDfx6OqIMSwnre0zCnsq4GGCHEVPy+yuje9+ECiAV9gCMmd//t3/iiLuUxgUjOaz4a4clD wLkgwtSF6H67raOP65I09X/44uGprhbfrrYdcKnBKYNvCYdZbYC7TfPjZJ0YTYd/8zs7lrdw0M+b Vbe5Ltz7WOC8h3kMpVR91oCrOBCUFXmvayBqRpMwylo3uUS3mnUUbICFywyCCmUcSwJbrxaByozL 1k1NTpGIgINIABdTmZFYOwOTOMrRHElqMdOxTccX25OAKs3CV2h8FfmpmU9EGkWEy7I73gfjSw1/ h9gAc+3N0M82fCzA1/g/ORcJn0JTVfFcf1KamWh7ppRKEHrndQ/YbcY/hZPgfk7ajlfBdNgxbg1g Dtdd+uO9TVasNSC7O/WtYxI2HSdLZVWtFZaJ8JFz0tE1LO8WvnU/RBEXpeP/3AC3VzDVfhPIOmVs oeY11QoITFYv+BGfKyZsPMoARdwADgY3d6nyTui/s1t74exN6kK82rzDXIF9dNodyS7dXZLTKRTH 3HdP0wSLfK1NVBIaOafGFPRmqYts7KLqNFBLzI2JXzEp1pp5H54XswTW0lUAMWf/9me2VOJcSpcI AvJVmZe2x5B1392R0NmT5fen5ty4PQU/DThRy0YKyMVS3aNmWPBp8bazBXeZq+hpgmkAyrtEg7K4 WWzG/MPZRxTx3CKwNjAmynY+JMce7UtcQRa92i5fFCex+UJf+MdRtRKNMnKCthgi2q1AQ14HI8MZ obNwQsW2TifnfKfEEJZZ1LL/D7J1+fgmZXsSe6PqdiNZde5QDthd0nS8UsvauEdKnEh3S7gBjJQ1 HnGIIOzLEejcjv3d+fbqeIlLX1rKjpnIbY5EfqQRQnbNmVSYSE2Wec8pd7PmsEk+a+GLozy2kIC0 CDOM1lICPaKmzVIvWSQoa4W00OSSK4Me5CZ4eB2ZiZ52TqcontKPlwwEqhH4yR7enlV/9tV6ow+x syoPduvIaetWpKlzRipgnH11WvhPjJhqFVJekbwzdm6YHrNly+uJSdFXBs3gOpWEMeWWke/lzUxN 0p2tjbRj1U69EpGWrviZgl2gKTBUHcFebGxcVVQNtRP+w35H3A3Wz1xdrt7J4t+zdZgrTYr4cBX+ HhO32GH/jVGV5jQFtiga2KbaEBPStvK4OcrrL/WLj7LD1yr0hwghd9wSzx0RaCGEfH03dG/ogdFu iDoj9dprPpYabhotuA9TiqEGWB6B/qCOPbeveMMP1CUstMfnRgnvbqW8vsygnesvIMWr4exZxVSJ +ANBTv6+dZV2A4sqQNyERZiKvyXZtUm1leMRk7JXFAV6GKn+32seobu7nH4lHKuMpu+QBZnwvqQo MCmqKnwEz3GXUIKykbk/GuAgjebN7BOWVLc1rDawDKvKeaDKVYEXzp7ykDMLliKqZRUKRdvcbt8I NUFITVgXo78iQQnVHyfHAIVaxdvDH/O2dxRcA5D+1+KwJWfBJGAt2L4EUQHfDVPl8BnKv5MFcENc dgymWgrJU6wh3uqavz0jFJ1nsqSBukY8mtefi4G9yYa9cJbsOASiPCnyybbT/Vb57Yzzp+YpGk/w NqYZn9Xwv7CBWKXqnZ2R+uXMRRxHKdwljPhX1D+jGAyi5nhOqOHp8BCfzULYdWUkW1nM1uKnpoyu DABGrVF53UyOE4AktLNhBGcDJq/sXmY3syh9rpdjH3alpD8pYCbeivwoeeu+vyozPziBO/xkHj2a nztgWHEwWOoLNU5bpTJnwn1eMY55S7xPSTxS0MLCSE47NvHsWHbbjBWiUVQRCYixCyGRs9nns+RN SrA4XJJH3ekIpPy99ZdQELonRNLywBVS68NIh5zX0Qe1cB1nzQqJWrQQC+GAI9f8fhqTUPNj05Zg mED5edStiDN4rcun9YMpn/iBxYU8c1jN+kzDOU10p8ppvFEud4mGkUFKO/t2pJgIqHtw38XeIB0T ZtBKbqdZQcvPY33Jc7aSdgakuYDmxrp06A+s5TthiE2TgqLbJotHg5EoDCyUG5ijpTnS/uox5zRS ewwANXcsmzYd5NuNXEurgttDbXDLsxbco/VyFRPCqPtiTxQ1GvaPkkTWGsfbPkcdU6jxZ0WMbpcS MKYVOOHFn1wRHDX+QEGXbroQ/MiVxCyGMa1enpR4C/Xn3UcqR5SXIE3mgrcYKGlxnqoNuGPMGRxc dWNj7FO7WWY0IC3y+vjZ3fAnkUI2A09WJU2s/6FbmUuyZMQu+2KwDn5/80lZLXN5OTgBdFFZttER bYKl76EyZ4Z2YT2UcwSaCBaaFfSS4fQz8puKUZygITEnecj37gFUZrS4T5BIVs8e9SexyVFMKByH FUyWG27O/8aQyXeTCrkYl5EZW7djeNbvAD7iOPbX9gBND5Bhdya345o34rxqp4tCEDzxysBvxFqO KhNfePbBCwI0rKFG+/M2ZV638odYmmFS9Ktxuyo0zbA5KS/ce8lp2bjHNy33xo5Wk7JmYXyziKa1 Izl02G9WpksLMYDvKYt3DBDOyx5XkCIkC30qO6ovT5On/4A7TL//jrBVwi14YKlbF3ObLyaVdrgx tdRn/x+17PYqRnn1jSMGlURLCL0zZd1rHaaaY4BiQ0u/T9JURGbdjrCKc+9bqv0E/StdRfPGNPKp m58xzGmX/PKvM24Vd6go4PF50o/EILnWmlvYcQSyiEi7L1Wf2rbfSlhwczwASbfTNpXG4kAJkIE1 dhkTE3lwXLrEQI4DZu0Vu8Vn3Khc6ey/PRQ5b3oNAfh9JztBbd/51yY8KBooo63DY5T+gpml9uxW KZn/QVCG0I/op1yw5vequjT9l3KMVRjH2zo2LQGfpmfrtOrXWIWrEcNcvLG9OWYOCLNpiCKSj02r JuvPU0D04y7r0pZXTSjfY6W3Fajsxht+RhEWswwxV1PJhtLvABXG7/TyhNxDjNfnFENQaIi7m2yT kVRRgcOlcHpzcAmcTv4PFqvVX0gK2IpSmoWXzO7DV6N3X7U3gQszyOh3tb43uPQkUs7TkYoR3EHe zednj4T0Zy1H+Fu6q4gdprDR6LaA93yu1wFHvLyNtkbCKFJvQCWYdkLyxFu1nMXiDYagIxbkBmho AqtA7GcLrz+9mcTfipt/IAyN928bu3APNXNDYKk0oBfDXg0B/Wr9aLrdm69VMbPKEx9YyI2XDMkn zOXq6+RUuBDJLHL517jrL74IBrFefg3L5LDIsAC/5xFZm/7/YuiGvthf/ue6FYyY2T3OR493ztLX +p9D663/6styePxo0lwONP0vdaGhdedCqvb8AIFyw4iMq/bbQWgCPNyXsBAVb5zp1wRiVb5eEQsr zcrx3pXwrl0f4HNg1I+8okx6w7lSZ9G1Z8wNALU0r5sRU5lpyFYdkLxa2/++BI3V2h+OWcNBq6D4 pbmLOClsfSVjQL1/ckTeseuMU4JLR94SPfvkuNdJK/WKf1RCcblLdc7Ssty12COc3dYCtSr+P/1i 4HAbUmVddj5QAfdO1/kQNwAp0qEslxIGfDXO11t/eqowiHFWHMI+9q56h3aa8VW46H6guLEOaB7P B8MMURtDWnwNrBsjd7voK2/+1eUhtRWMLc3YsfTfkAbf7rTPebEaJNmzUFsrD0txaDsgBwA1VDKQ NpdhBIaJhQGImMD+OQpPVGRzRlolDirph5FU5LwzgsOLN4KW16b+yFVALuhGsTVtUlovrwFU26KU wx5swugSpchQ+dfZ9veiEPJSt1C5vwQ6DCcYjZ9JgqgR7ulj34tGD+gKYapzJMEQKC1ISrzjlLI0 c2gryJYYLRJFjZ7qIwy1y+WluXX7xjfffN71ijDU5CljzQ+9+8t+pJhrYK0Wht4WaoIkPkMA/rU+ pldZhxrf5F2OB150AwsyfOmzUzAJgoqfSc+/+dST41y3abFIsj1SQj8F2cNTP0/L4mRp43hQHAsm aLNiuejqMIsG0pwzXIr6N42pw5yt2fXZQjvcurY+W/RaQ/vlAZRQsCjQAJIXh6Kd4n5Ha+1F5fAT LHuN2BziGGCy4ZX0YFgXCKvUuoR45YYgrZZ9NK+eAA2pOG3myKv6j6DgEp0AsaiNXUR5DQWZRand RDDHM8+xXLFL20amf/Y3kE3ZtudNpARp0F5oW95GCFS1seXki4JlYYWBl3z/4GXT9GeTxChWbdxU asTSxhtSqfCrbZJEcjaYbW0WY6gEVAfbuPWhnoZGAV3u2ymefoLEo6FhUQo4rrOSBFsMt0W9ZVF2 fJ62SqKxkm35Cx84tsJT/XfKaV5xMtakIAF+eDDr0/4O9xpLlKlrwkXgmF1w4IjBZKGc/pyfueGX XklgPcuH5wEtTl3JHPENCKXUR0MoxEjpSjNFwvwXLg63jLYl3cLbFBVaGKoDy8vmmQQn3TDEoN+M cXnfWRuJ18p2oHKNkyyC8rdyXUr0cBnHc6WrXYCRYx0CAVsc82kldhoyvImZ2TnC3nmKcu3u+ows OWh/Ikf7y+kOf+jbt5OtN+w2dNv203Zp1LDaHkI5wvt5ljO7sAS3ggNVjb+RC0Y81Vk6Za5DSB6E opjXuYada4rBiPv6Sh0JfCeaz89yKvSXmr+2GH6tbay7u10MJ4XCcYzTHTUvAuil+VmkNRZonj44 jJedd4r1esD7y5T0BVv8ocuamBpWesOmwNkhgCU0eW17GMH1lclh1dTk2XWioqopFIfLG/S+tORw MifXk2yGeCe4SKqsxnNDgGECsMFiIR6a3hRNeG9uM4WwPzruMYNVpDlBLud0Kihgv/QMzFMIvPZB Qj5d0xpOUCZ1nMLX0XHr8mGuegDY0DBJ4uv8ZHIENOBX/MyXgNcdlJ8xO2UPBnrOqo3vjvz9zHEM pKBnLgF2Urk2Fj5h3AMmoTVCpt+TdArraIK2vyERX/R1/R2KYLgXvTznmnTzJsvCAjPqgDgjKgdg 8Mq6O/nSUnX4EfHqEXGdVcJYcQmK+qa+gvMC91obp3scYYtcFwI7MZkTB90IZxUqfeRYA8eq6749 uC4xDc3XiBuqF2UH7RWyGYmB5wdjhjLn6aRPNB5cEqT7lye21YFnEuWomfMSPEkqcKIfWjLiDh7I hXWmS1AP6PaihBm/6pO8RkSpPTFRYY+LAZT3fp7/xhCebrvmztM9xey09/MxidYnvqy5D6saUSeo i274ovdUEohyeohMybvBCUopu8yqtjCAPEsBlLERrdDUn+uPck9NfPRIhAdw6iTHp45u8MCrdWfK 8CteQQBJ7Y6KSQ98FurmsssVDEFC1VvSSKpASgFK3b8c1JFwVRJoRFfYKCpFeF8hxnonVIT486a6 oa+6w9x31WqPLBrxn8u2pHT0Zkn95wB9UqIjqwz3VGOZ4hmGe+RL6uUXPztnWDpSBg/FpFWDXYrf d2AgqD6rh77eVLhQMkWy29dc0fuqctU5om35EhpDdnVuDALMJQ4eRoQHZPERVMv6q8F62Bli2z20 05h6NLZRfE2nlqxun5PBpGuPvVdtdmRXcUpPCPg3oFo+9NWSXetEfZNOZVcuMUSBjno471EPKuEl KUkSef2SptDCCrKz+4wTW3ezmltlgNnIb4cCyG23lpZhhkzfQufPtJqgCQL/mgy25p3xf5vfKhfd 2vnRzpnpYixP/Lg4N8w90EBokgGqiWUvOFHTEHFeRNsgDfIJjy6w9vg4EJ7Kcb4eJSWp+VBrgmvo inbL/gj+mtwIoH1Vt6B1WBFaDxPs9Q3d16AEbXL2uqws1YyUblXbh+3gFTm4GZo4RpV7qoblga8y /Y1YVuB6ZOZF2O1aXdx5OkrfG1KDWUVP/xTEdxuIXm2P7E+uaWxI8E/XMYEuzf4kp105NgR+azMe 4lJWlm7FvRwZ5S7m32/0PxJZMgJRup311jx9LR3hYuRjF3OrkSobBjW3rvHXz3L5QtuqDTsacyPa 3louKGZvtbHJxfEMeMivHfW39/Ie7QEEr74hkqYL01vAn2q7ewMe4IFSh+dzfa+RIE5k6ygbiLBg vsr/oTONa6IIlSBEtrSGtNRBklyD+k+giaaQ9QLFACjmW5PonMSe6B0pZFHeO7D+am7ZzGkzPnNv wL9ZrUyQRS2cvvn48/Ljxu+eK04lslen0GbDoVSG6Un6dVNAlPB9L+Z3wTCCYYpiUIqAOwZs89F7 WoAFaub0qIppQGa6d3wKxbroDe7DXz5//kPnr8VjvYmfEqxP3wTmbZurn60AMUr4VflB83gDj9/s DgTcK883cIlh5eD8zU44N8NfQWh5y9tl8fTSbdIa7+ym1jM9rtMawXBJwsW4rJvKblWAwxIEmGA8 LwS2Za5jfin94gkPFPek9fEHIZu9HChuBWIa+6EtEykkNCKtdKG0kYyNh5Tm+fZUN99cT0DSVkxh +voiXRsOjIysy7L+6Arn3NTqRvkfyTYAiyULAH2+ajjDceY3r/vfcCtCEiZJ5tef8LJZF98yRXEp SI7H0aXkv474Qgx1b/7aUeQytJchEDA3sFzuHEJlfWojaDeNfnYYJqj66/OzM1F8iBUWNR01gpxT jPzFyz5zqYRnJQS6Pmt27MA2/Qj8enhgO9hVYNTtm3YfBp72AWPMcps/aPth03cokfZUkXs9wWL7 04ouOUPP4bJ3kCLgBWiberuOTh4vAGM3Gpxy1D12hSO6fQoSCDRE4LCQkp7P6VCpO5PQolsAINCl pLA+7/RRJnR5INNEfOpozm+uBbjUiWqdIj70RtNyb1haO/1lw0CK8GxtIEVCVlOXklJjJOdiVF9S NTn1Z4O0XWxciRQCdId4NXJgcEutGv1mBWrtoE0FJGWhCEPDyMFvgFrO+XAmUi0jSyLXnfk+3+z1 0tPBODHSjFGA6NRys9zBtgyzONCL44QboFcAwkQKybgn+cOxNQsIJJY4lr59DUgTY3C4XPGyoe1u MIvsB4WOSPNAvlO10+4YLnd1lL1WoGqXq9cSAnP6HkdAK2+SzaYoQQlU5PnL/D/FJOzqfrsk7typ jujE5NcO0HsSLFPsVdy+EhCbCM73wXXfUUrTe9ax6gfjBhqhUvoG1Erb6/mJNDPPKGzvXC78upeI DkO2YZuBXL8UuUWmzOoBARiviK711jy3z3xQKmGG506jc9yw14l9eojjstKlSf5vHUQN+07qR2vZ qym78JOkudOwUh36kyHzDGV3A58BBsqerK1sf6q0UQiSmYQ+qrSWijJmrto9y1UzxB9oteAerIAp ckuIzJw+kAoXX2Y80Rw5z6/QG1+7dE4VCYKZIY8iCKx4tj6+GDtLYxV9b1A7Y76y/1cagaMbFHMl hEl3tgOZRawrT2ZQdXFnEr5wJqFgOgpUqAtBSRIzO2hGO5HLZb8cF5GbuECuo1dlEPgSdsFXFQTN 3vWy0f7tRHUFqhrq5UwvdXPZ4kdjT0/pqhCoaW5a1cHKAjdSCHeg3+xbiaoMNs8cen+HIc+5m+dQ d1J+LxGBi+NfwsqPwjLU6wCT8jucY/fMDQ91RRXWTryY1n9/XGhUwGigUb5RlqiQtbfdZ0iUyOZh qlfR8G+GnWyFANBpljMiPKUtjn+v9vBGcIsVH64y0lRWHedyu7K5GlfN8xTOP75J3789YK8yo3Uk JhoSntA/UotezGx3XcsW9GJvm1CtHJVJeLUrzWaJh4OrxQbK1aS9fq/sk33tc2jolwptff3ndEVp JmfmDDzW/PnVPh5PpJl+Xodogvyymz3raMnR9Dvwz8FMolMPwJG51ouTxNJDomjKExrqj5FV84g+ WmOuTs2hekIoWu63QXwh8uGx+gtkDEZJT2RKJEloIy0zOdxy4buO1uTyb0r0yXYh/rooxdW3uUBS vVSqWiiKF5tkpWeWziaDxIqY8heD4jsTcK11WDRxBOmrvo6U5RmmpyOUD4VJMWWTLiEUNSsC5DLa mlHdDLVYq0kJidYpWddfil+15NUPX1PupYITnIjMdkRbypi16eQx6qQT0w5Zt62wWlSyQ5WWJgJC jIp9ID+krexqZBwbEp/+zNlV0DADTh8xtQekYTKobcLUbXKrvRDTry0gTxfd3SwnJlPMKJmCUlDc fQKi/DNseQP17teqDojOuqivbMNVQKesx7Wj4TZqYZbm6ppnHMrUDMvsIfmtcDlTn+DAIKxR5lN2 kTHmIk63dcNDIDlRj//BwtcQQAhpXZ2VLzARY1weipLhyX0oVTsmrlwA2Q4cEe6nCZxIuwEfzKnl 7FCqwF5VQFKN13hnQtQH1wqR/h+BCscgSA5kOFsGyNLb3cFXn7kLHpPmNuVV7iFya4g7eQBJ46PS d2mL6rtB7P+Ap7d1IKqjgRER/sI9++dpQeh35FdFWRg44zieBb6nbMXg44HvVRGgTeWyoRX29Ynf HPGHbPwxG8aq0u5MpyYVI+B1yMtej88QmvrGmF171UrufpKpbTmLZvXyGrbWMgJskHxP0/y9d8CD I/d4z4nA1AucTNNcu5An3qdFnOCvivETDUDza2NPRy00hBy/NT9GXhuKzA/7m9ZKhgQFMElfk4RC smr6MS7J8HBG0bfDDgy2b4gMgfY73h7PCV++dLgIYM7sFUVes1loqUcBpyJT3F/2/NmNjaZ8Y/BB I1xInxbaLXRWcfEcd3M5qRJLlV9D2l+CkDg8vZ7K5lInKiXpdxdRioceIPeH3LztAAcU6fNtpnsg pFpWsduLNpPtqKX8XM95KRU5/QjKAoK8lHcvJFAEelb6cUUx4mt0/8pOAF0149/klEQ8P6hEXCCy DCz2MN65BRFyghgKRf57Y2xNnsTnDDzXX7e3YV6tUhu/Z2zjV7IiotF3/tc6E6Bi0rX8xcSk+rgX dzegwkSj/ipyCBIelrqWgSe2Zhw0Rk5oZhQGplZlQXJ++RoRqjTEZl2mHUP82ilQkgMMQOhj/2iL 6qiXLO1TA7x1lZEKnrGwXuTczE3I6sHuto04K7iGXBe7s6u/fIgcAc/NAQ9n00TtFjIbQ6nMsnao Se1shxbbwTRfYfo8RYDrMY9GObrymGoA55OvGkLwKYP99ME8ZEg4D741g8I+YkIXGYxiIluM8pyy BHY18Fe2Uf8zKkDtB6uf22WqxnzhYYezxnfkSx/ewVbx8mgCtcoQkXW8r4V118flU4po/S3bVq+g xfu2TSCsSDlY/CMr32aPbQsGMatL2RKR4W/Uz60CWfyy+vldqNJ30JySNydasuTZHLQd1bQY2c3y ZyIHmHWUyyFYMPUJdui5hPo300jMBmoVlgnE592/oXd92C+4VCVIUw2j3uvPK47qx/zNIg9Jr3RW 0CAfH1HfkYAN+XSoFsuBCoGIRNc7yx6UVDgg9sqrY5kH6CIIt7pRaQlG2NMn2RSIfj0jeAQHHkov BCPCbW4b0o1u/qZ671dbAejnCw4rcwjw9mHNk+KKJ3aopHQFmNnNYaeyVsxVCakcwhdfzfQXXNtQ xXTnH0SjkrLediXtd3QqBJxPuM35X3uFBM56cB8vg7JQEoGFr0Wi6TSy5lNziwnzkv8VMowgBtt7 Og7IXpUSEJPAPVEh7+x1ArUIc2AaOCmUi1pRz6QQHnVPdlELWYzxbRD9Da/LD+7CEJAIDiP9Zx0i eCf1iChHFSV5XmG3SB4VNKf5aErC3LXjqkyQK+p9y8zmHDFvFkE8nI7DPyNesXNt6Rnd0PbHRFr2 BjFADUdvkF4QekUvN8boUCmOh2qRo0G9YdJ1WtNBrDh79370haKhDIuBkL24eelbeX+UvdpBAH6S XniwQVwII8LkuGbMyvAQMEJO5jvQ4fFvY5ziiiwvO+n4z0xEF9pWC4ppSOe0ymoA3VkG/XKo6oIv 6kmJSfWVvTqsVs3IMsKcXfhyozmMpwsYVLFU5bcqyv54E7Fh3lOpwrchqj3Qm8DKySkSYoGHfsdo 4+mSr0MHBjyvBx0eP6tIaWBuQIx4cJWs729S5rzUvekzHaaSbE83QjArPtwZVwpfA1ZRBw+fXRYk uH62c065wpZ3+x4ORD6smKEJCLzIRYpfhgK8qUCADpGxYP1Qw9wz/XgFkrKB/j3u9ag1Gb7q3qjU rz5AeVn57LrtwnDcw3hVvGq4iXYHSOecpwl/dVb5UvN6J8YtpUznA7s6VCGkNM/6CPhxJuKNTzeL 7E1KWeXKGFLSCFZZKKh/7lODyvf0fba03m45CF583tF4F+XD1dokbo8+3NQEpZgvVn6H3jsQFlFK HiU+/YZTzLwqxtgc1A4oDYv4pjRGe+q3H0YbaeWkbQQQrLhKfYO0EntmEYtXJAxWE2BlVclFp1Uk r/77SK4hriyRCgoXJbV85iYRZUnV4A1V1zajhBojgiGQsU+JxF9NYN1XeOnd5OvRUXf4A10fIvJ+ izEK8V6LHRMAe6U+2Euz6okQBJlHAHg5YFgxCKfihdJkyBB8Cs+E/zzV0m7F9HAK8WvTw5/jzlEA 69lwtIkQZ0cBmx/hjDDSZUkaAujoA3OdJFvCzMSUpGiYLDfSsdRvwUateebCV46L3lUoc0cd/GT9 dh4aOrCH1/nJGGy/xXvBqEsGQwLS7kshV4Ek8i4IqFvlqbDacgu8db76XF1rXvPTJ82YRsDmrI4D zjDnKi2sSsgNYATQKOf0gA6LNXIXIe1wce5XJy+tgfBIf4ZOyFQe8S92goaRR0ote91J+m8yXegA h81szZrBsesWGKyFwkZWoHYmJqFLyxH8OmVB41OWcfx3CZCvqZkQys1eJUmLUuxniWzPYPophHQE ZPnD95DyIbZLiPRkLd/SHYoObxpNe1ql1QgKK6wTbHQJHqOLeH7whDUfUwvxdUnYyxAfiW/4V32F 8Aan7uLGfqpuns0G+tHwUkIGKPWwVTr/igI3v2gs/qu/DIlScIuvkiXdtEAfEdrOsmrr43Dm5RHN aQCC/PunJQ2XdjQOlAMk5ysZK4kM0+eIZgLJpP4xdi/XjLI3c7qUk8M3XRbInPyB1DWUB56iT1eb D+bArSZ3uWzV2JjSh+BydOgDxskpGi6kNuuSyDPaRswy4W8Hokhy+mSMSoTOAj8sSSOrmW8f21aw tBv7WRxXM61P9eOzcyw+JQydo1+EFsZ1K2DOa6w0c65QFi+R4tQpx46ketkUYDQJqcRUQ2GrhazI SMVsIS3uB12RmwNDfKLzMAieZ8B9v/0xh+K+V6A7Y+2l3J7h7RQKeEizlUc+KlMKEIZvDNmiMT1T Zh4Hq01rHIaasYfTMkK/R1oVMB3gVcOYlRPW0kNqKIm+XSrn97lOlFEifA//KZ1/2fpOMq6wF4jT +biIR8Fec4vZ7jlO+ft2YiBpwhbXbgJEdMD2OsS4n76Ta802FWRHAJGkAU1wlG3YLdGUJ8f7OM9e LafN5nxlZGaJrSZ02dov1NHjl5TQcQO1OWv8EmC4zP1rPBDCP04ftZnTBaKvv2uBsJClicM0WQtH 7UMsYMURfsOf0dQtM7N8zNH4YvI9lyYa7iE7LS/zytERMfXb7pnwTH05efNU3n9UM54BuSMDnucf AFREiaUIMK0exFIa8d4ntaPp2xMYtePWvWtz9n7F824BXqCqyBSjUgCSGFDeoF7o2gkAxAPr1YIG hTcsP5iz1FLtTHWNB/APlzPygjuKO9O9xkb/13bNzUXS412xqAMCDZAMhxVuFgzh20XCENmrx5o6 6mGPLOPGIb2xj8kahXyA4KZvBlvgKS59bVOy6EM9SkDdpoaPyCh2ovHkETFMiBj7E5vfHhUMC4Cl plLnaNoNKNb4675zpnbudlqGLRBG5qpbC3r8ksf4r6NI7eqcsV+ppmz+G/uvKPXQsb50nbwcvIvO n9ZpmJdV49gPjvy9hQ3iVH8l/e6hwWlGYb5pvu9E1VNoz6r9xTOHbB7FLIjNKec2aPxfLeeCplj9 er/FrxWri6WAJGVlc5AY9O0plXzWRn+jxUazNnAEzFBFKG6BRkWgmeA8qDbwpcqvb/1KMmQKz8Ri 0npGBvx4s9oosjj9jVCK14+KOvlogieLHYeDlUcSJrJnbjuDrj4DYiRnFp1gFaLR35WDTU9+783l A+XXorF7wKd1UdbP8TbcFNzD920wCXiffX8yHHtmIQgThxlILC/NxyeWhJN+U1IV9pQRwvd1S/EW NgxMlEjS91AFsIhHnHmRfzgwWtPJbp+ygTNKB+/HDzNeAfKJdVlaXVSC92XhBrDU6gSSk7ZrhNVl k28yfmGYLOMttGp5lxwIYQKD+kIxmIqujSV9zpl8hULnVFX+Z7LkzaizY7fzrFf97KZLIFa4NZU0 mQjXyvh85YK67g72Eo5/yaRu48kNmD70xPqLGPfSdWXMiyXkgdz34f70dkUoDWKQ9fR4d5wdwvuO q2h3BlqzwaUf7QBkLKDtrZIO48g9UWkVdAgMjyN+SbTPDJWPzuLf+zaGSZJs70eDlNl9vouWgTfG 0kFh3/CHLY6jVXAwokpt6zRR1TYlLgC7PsxESAJN6eiwdj4xe2kPy4K5Q4p0HgN/pXJNAnoWMFA5 oKrOpySpofaUpmBPE6vlwexTUgEU1fGWj5hIJqEcWVtb9P7XzODU0A1FO+eeNncOieZYM0kSz5kS SwdAhaNdxnY/6PKdhoDzB3rR/TXzeh0AHG6px08wnqPou/x3T1h5jREQghjXkyXmL07oM/zw9cps pJQD84B/En22keGejupkCFlonUWxfI9gvbnBhz4Rt3DKEIZZDzKn8SRKMqa9LxsYme2wKrJTJw4n wQ7fpwBDyjbk0x7wEp70tT50EfmRb3l4/9h+OMjNzyd/LlBB1BwXWPZYwZkUh6XNrMmLbq1WUu9p nTP3mMLr/hXKSZxpFjMRsXklHtx4Uz9HjhcGSuV0tZ7sp7FXXxZyx9Mq3GBO3GO0w4mfS62OAren R7/sPbp9odK7IcCGk34Yp67taFn4+BtEPyXDP9H0upiku7kTPFlGsbPx4F3DCT76j9J/wTT5UaZn LSuN3j+/SCGa20rvSUQ+BRvb70zh7wY07wrmofYhV2xFzjl9hbmMoe/Vjf1+s6tvLVyZ7FpsNKMO rfWFLgope1OS0lLoAuWtaonrkJq7DxTT4nPhaweC+fiSydTgB6iBhLhw/Ue0hwp7aws1gatlmyhv X+EO9QPrHmulwzTM3HDTT7MohXJkzCiDeCPDhjTZ9Ily0AgMdWOzJm7/uzJDjtUGe2gW51yLpiR6 6eQbQ/my18GPuiXyq7lccyhQEEPZU1o8T5FeBTfyFNwAH9zpLRLRF/m/nRE2O2dc+U23lgO0YCUh blIYQw70RJZ3DDWKTciF76V4X/1/7xXFWlYTSUwtQvfW6snllU+WZ1UW0TNF8XT0o/eUK/IGc5p9 68M+eYY/O5dGnpP0+gCABZpS0TZq7EFrBZS8h/Ec2bwBZKnqUd6uc42W83VHBajrEQdV2uS+CNEn z47nbVQPztSlu4EaHOXOAhZX7gSoMH4x3gANtsnaAZdLLEbmg4BmBiMj+nX7jYHYvw/RW2+S+Or4 Ueqzp7l/IByuynWva70dyXD+2Vf+PFBtC7NQV9ebzvEVo74Orw/5RL9p+fC+vqy2IdPgVdXW/ErM tEVz2VuVfOEIRR3e0Qt2k3bHSt0mZbigTrCp9vP/nVBIAfzNcihZ1IcR2sJay6244/NwU/xxsmZg U7YCcJkmREZjS+QARHgrk1gDQb/f7JrzMYR1TLkhC62mmWqIKYPjJx68LoA/GzCLpXFvIqc6UIgc cprNEEPMJ2ZlwuF/jW779YwYaJTKdAoEKo+njtyl3jDpiBe6vBJfZEfDYWHdZWDsXiCPVzv8yLJe GEJRiywyJnrx3d2xBAe4KyajtADK0MOiydVEbH94bzYT0hva/SratH45r3Z5wGzrROktjWceCH3h kwIwnZI82oLg/lglqBjbdXZzeMxDBtiWEWRemUTJmXc7u1vfSWXjTfWQNMtWQvu/yFKkZIGkPCnz 0bLLM3bQek/I1nAsImaz12pF2CZxFhzthuopGYtKnkbMACZs3IRbPVaE8l+P6RjjDmiWqjpw+/+W 96rBDj+gjbRzxcRc/IhVOPyl063f1/jrf0MeCV9d5346T5Nr7zyvOENXMPJQPZBXLFDKB4b5YdId P+5olqAqDNFDIvJ1ApvhjQ7jgMdAVbF5Swo1T4OjZeIlRVgH61HCS+8m0U5nCxkuUC88tTLh98Ik QPtudxFoN1wye2auZH2U74VlHbQfh5vS7+/8zxDH1h8xoOR0lmlVGshAkC2hbOfjcITj8HlLA62a PpMd/WmAZnievQ5goP4g9XHFOkwP8ppl+HeWUHj4WbA4rQqlkwDIKv3hDUnlSaEDa6nrR6FDJkko gBZqE1mNDw6SiBvCaRYR430u0JFYt87xRXS9VYVC02e7is5wYLNqss1fRA72xiTZhxrVupcXDQRC d+HlQNmlQY5Qy26Y9PFbM2kKGXEBln8rNU0A+ypWp2eDULM2WDsRzRATry5KbHfwM6kbU5xZRb0c BbSgUekuDZe0AHruwbcItWY5/H7zmsa+3DDK2nczcvv8LWfKht2j/6RQbIyH8pivgtKuFfpXMKBQ JIxW/MFpNmjIAngYp5jfYo04z4KGdzkRI4/P/MROil0behwri+zeDPVCqYHWmDI2Ap0w/qDS0K57 llMCT0W5aJp2OivMGLHYGRXLQt2q+WvgkW5CVe9PBalPrbgb8+Q32VkadCLtga9fwuXG/Aves95Q ViZ7OYbJAzSA9LyndtV/QRmzOpkWZ/xxIYDXZ+ixg6E45yKGPwG1OdRxbzi2r2sr9hAuYn2L8zz9 KFjMjaIEtmjhRxXAGzXnmT69tMpoum3KX233cFRhJ/30iUTbg5A3Sg+1/9ERqZvHPZAC5WkLjWIf oBUMkq9JP/CxIOBVcgVFq3YopsEkfjtzT4sDASxjthLXJcl+vohyerOjGoIlMfSWLWYjSCfSbNUu +fFgdG6RBoyB3nUSjGGYwy6I39CRMlqv9oovJO39O9St0qcyDXWkgfKAmSg3dMFZEQfagNyyuvhw SXeQVYUqak8EuUSG89qYQNuRkDxvDLZZoe9jd2hu3Hux5LaJmFfLqwke4uzcvfRxlujMvsoirwTk Bmadr86QTLnqbFrzaC6M2bjg9ZpkJdGH2863mSnD3JzmfVVmc8L62vBaoo3A0wWYSJszVoEySh4M Bp6NJJ4W9bMND/GihjuLtO7o06O9NqcoqG3DlLcqzUPEY53ZT62GkSIN35f9tJIclu+7uMWDoeQ/ gVFI8ybDlkiojAnX3LltcZcNeAc19Qlc/wQzKcXm7pBVEv6Zpr8p2oScx6PcjeIQy9wX+55x5843 cH+zRjr2rXVo/uuilvPb57LVR0SjqZih6myYecL48v0HlBSMlz9x1Sd3s6mDBgXWg/HU4DqPGQvN nKO+b4p36hbgs5izTH+hV7CTh90RhUtmSTskf27wi2rTofYaTm5Z5C4KCNJqx3Sf6GimdmcwVNdt sOoFOdVVWQLhJw0QR5ojIpKIYOEsD2fMp/rO9yJMMJ8nB1Za6nfOa1VaRLxJ/W1FFZAuOmX5SV8g vn9YcboanKUO5Zl2LLskZlKSveWSK5eL605N8zdVq/u8Nsj70Qw5WTE40tvvo9JwJ6VDPLOOOeBA +4c7D2EmBS8SGIc4kmJZP7TQA7MfmnttVqrhR9NWYazssvIerttI7nMBkRCEU9rISu37w26Is6YO xp8EpGA8hndFDJsj7Qs0o7kgjpvR/7C241XZRNGn3D9UizX7F72kIOk5x7RcA9aVtBYA38oaNsWr MshAShShxpPvRkwLQO4RjiK7A3Qlbdsu+f/578l1ZlOtSX5/adGgxQpjN1ZihfJUlkRR0nhlX5mQ nC4DV/rJi3SNYjgSZxY/d5aQnTpDydGDwWQNBjDR9TJIEIWLbFB/yncC4ygFZ0RF2HEbe+s+z/sU fw9oPDik2yRTx2fmWxNkpfYw2PAb1iW/fLLOip+Cz4TKwE8BPCMwLNso18L4K4xmD81MtpIl/ahV ELFdYWqsQ0VSagiBwZWuP0G/3PgQ/MwMJA2h5vhpChE7bTro2QwBpBprZsXylfRqyKLXM9pznv7W wQgOVXyoaPLDzvlfrwdH4F7hjaH0AMIKnYOM8jR9LP9c8ZYY2+Hdocepu45miyNtlbIXwUvLb3b8 c5CCxB2OZrIoeVwXIKyLiLzl6abudnAlPv33IPj5YLptnioMAvGLZGHnD7d0VhNYqq4Yffg/zpb2 cyBk2w76UsY+fjlgNimXMwN/C3iZWCAHRiwxN1KMGkHCkQGVhwh2bMVtnOLVSlVO+IXG0qlFNn7I z8F/VGVjBMUA1dDQTBSorGYlbjdBPNxVnkdSCDPi3PYfInmPFeKSUoyGmL9mQU8P/4kXctEW29HG tovroketmiCTDJFv2S6jFWtFBuUeW68FBUg4WCbDE5oeJ3cnM9rUOkbpNSpT1SLSRodzNcvHMWQb 9egPXF7SCYlQHaJmLqp72JjCE4Un9CIce/aNV1JFzG2VbmZxEF5bjeBk6Vi071lViRH5Q1AEHXGr ytTSNr11LEuqP9JlFSOIOJid/zEOY9HYz8XA4Zzbn/p1ru5s/ZhkQ11mR3YM6pXJZv992GQ9cErQ YDc2FAZsGMCMMni5UJAfXvpZbtAJX83j8fza0y0JM9Ry2372j3CMlU+KpyBC59u8i9Jvtkh5viqK D+zXSgslgTbmgBPJyH+9QJUbC8OVqW+hrhoLDw0b4YSgE62S8DDanFMZe9ZdtSEq2TIoHQhGLa90 6/hqS2g5s5qlo+agNuqYuKS2dWRcCkm2/a/8vTfPH+hzPmDLaeR65fMjdQGhqLpJbRaHU6KrSkSB wn4QqbxfwF+Dj+NwKle5EK+fAgwsByxTRZikXtvdYJXCvdrxdSa9JIOZV6VGc7ry0pYf+ak5x0UK nOuTFpj6dJSmMUxZKuXWhEvHmZkF+ZmxczRSBBij8Qr21c8zXKc6dDYZNg2Lba5RJ3HBNdkgmquW D2xx6OK7ctKv/pcn719xvRiN0Y0s4d/rZ6XyqamGsjfySwHBjsX5vpzyqV2MvKGSO1lz6VNwIHX8 8kE74jDID66Zp1AHe6GDdhClLyV0jpZzOKT+Bl3V6OOAyilO2fP+BUwI6iECkfOm8pXHDPN5B33B Sej7FOCaK8dlvaEtJqL43ah6nH6BOzJY0pK0KPQ0ujLDJatoxcXIh59kZr7Ba6L5iOoXI/BcRGX1 VCILCMPXsEgRgJgxqOcyvraLHtSiO4x1IyvUnw08MV7ufBAuqfmyWLNUym2cZJTzfENwpy6Yo/Of OxyWs52HAp9d9aYX5qEEx/sh03TIqkYXSPSBYk6+IepcHR2b3C4QF4iqvV4MmG7/z4pLba8eQXrx 2eE1Yj9A2XcdcRgLfNLSOIkRj8KzvkLJ1+e+rIDZ2Z+EcELU7g/uKj5wwHxOqU7q38KuleNAqXWo Ur8bFC7e2y8YfLl1izYJbE4pMZOtd6dLjtyfdyAn55zAH79rizUKUqRZTq6jLpfo5MHHHykeLbYB 9FhFMwWOUOBpWGzUTxj1OkDJQrtOMdYpGRxnCBw/2m8vyBl4XwkrsBQ4naWkKPYyv2ROxJLR2D6M Tvbv/DEZNyz4Cf3JMZinKHFaS7CS1zr88DEq9SlX1ljRBd9xSnKuRLCZ1a9YMeDs06zd6AxcD7B4 arrgzDTHQ4hP0qQ+GEhNsf21FBGXsqUkY/cFyLhXJEQ9yaRHv47m88x72AkiItGTohpwkTEIHtMW d7hv2nP2A20g/U5EgjuO2MdKrETA8YAv8Zspzp329618+eYLQtzt2Uo9hyv4c6y7IapP1j5hmO+M 8AkIT1NwnzRbfV1k+GF/lVG5g+UmfcatMOPl39UNvryZPZOlPOa6tU6WBaviH04Qf7O8pEKMrR5e R+U9FEP18U3VtogzGP3g9ojIAznmQ4UwLB/uNcWQV8V7a/5UZN3bDYjeBlzd2sAlyM0izbKOMK7F 6HRe56iOHmT3eYA7yV08SwkwE1c8IgZFaaNEK3wwN1pZt0cQlXTR4F3KT74tAV8H82P3vbBDC+WW dk9dJzRa6+YJE2W/vgVgZi0Kg4ft/AvQMkz4WpqC92QMPqnwi2NV3tP53LnH9nREINaZC3+eueaf gl/DR7MPeMchuvjD7XumAwWCmzdHjFhXpkCR7K5qiBicGFJSCl+YhB2AWGAOUMSldcIJCL1QbtYX W9OzAlxPPd6+jjncbbQPf7ocSgPzTaHzJwhhAwBKuqdvm/BHAY0DIaDM3B53tOiBop7Ln1UABWy8 SYrryitRHp9H28EYyFoEiLqhnUd9ZdcRc3DutSiYjv/glsqmcuPALP0KpuPnBmrxOOtSV1vLEgUK 4Cx0lPHdz6vI0xhY4rSrw4+/9ga+3KvY76HVXX9KNDiS3pzABM5BsNqNS3oRZ3FhZzo2p6TRp8kR MoSFqj58dnmGhkbZ+EVbJileZ5D5C3fWEIdA6ZmwBQaaiFdwQ3uunS4KG4WPZGgTGF9ewaA7reiD 7pVfjf4Rq6QUYt+xywDCsjFuq710Rlg3jEKgW/+I06Tn852kuvRHzmXvV5GDqtNhRrkerh2ZojMt fXoSUVH91ZEqG5aFTUhx04ax0hlg/gMGEcz6J0244Fub4DFw4yenOfhQ6it/Cp7Wawfm0MiPH0aJ EcUFHPjhyk7MhnnW3BDVYpca86wapQw5jNoQhYczQjF9j2HajVyeGGCqk26s+VKsMaVS3dLWwA0S XiHG6o7/gMQh9eehZPwU8YfR1D6qz3EXiGzCPnQtlQu+U5V3fO8SlviZHmeuEXp3xYrtQxPYPMnx 3RZjoNyar22OEQ8S0+KixY8SrvxckIsbilWf1gZZaJo20gPCQyFetjsoi6f7wZXtKBR4AfbHkyGY jN2qdhUJjv76lhcD4P4tdLUFAOsYI/AKbB0xib4dJ2H4+5VqFzgOKNYdDoY/VJjn8A8Ht6v0/rZb cnoNpwarcqhXDIkNWmRJeoYR1PAVdMUYi9mrQtxZdiQ4P84/lvPpiKwAX5VuZjtRJdkbtFBJnElp RnNwN1R0mhmZwmt1RxfKK3v7Or+/yd3kwI8QzZutoCCJA3hN00jLNKHuvmtFYj1vOKnZS5/gINtv VbhHL8LTM5RN4j+D7aVsWFsNNoFjjM69Yecbg5C0htvx3+iKqp/2VbzTK4j+wTpc819x1HPu+LWX +XGkpGLxU5OI5cmpAFS6gnw2SgqnrwdN0VkO3ngX/0OFbMGnBBTKQbdlYUYwE+BCyIy58c0T/vdB 40VxC9c+6edMGKunyiQ/HX5MzPT3KlMe3d1sRpJlM/R7ReCYA/HgmOCQnaZddVqsSx1OFmJoE9nn TGhe/GL/R4tfyVqLT6DG2LB+K7AeZ/vs54zV4nm+Mbt87oa2nv2MAYtfrHgBX+6Mq3ptitPQ2CPw J0+jr7ASL55N9XCbypkxtbbpPbTjFe1qBYeIdQZ6Z9+RIohmwXiKEMBX3uHApR7AQrK/gWolOJ5J cZtbaCxtcOwksDSpxLDLLc2iTkT3kJB479+h5mJS/pSfs4ebbe+TowjKRbaVU8nEe0foA6NCJUWD XDKIg0t/+YcL2DvfmPfXVFmQlSqEfQlEFpdOtJQTcZ5gwMmpk7M43vBL6NVlYqKm8dbolmnUD1cf L9Axp8oDp27GoYhmEB1uh8Fggm9pJ5/8Su/RpJvQ+Xxy/9105dWOaRLQszOXWZMO7O+bkH9unnJC jbD9n/tXncbvC9HJxOTny+sEu47MaT3HYv5tyb9vkgnHCAv2MR9eRGYjH6tYHfzHWdEJIuVFRsn0 kxZfZqbOmIn6lmcGBDQcCBBZPRJaB1Ot12ezSc+pdPzjZPBV+JxtgoPnThzyvJCEjZWCvAoXWGFN De7y+xJ0XwDOwM+rmCQZADX8cnmLgLyVYYUKTR4vjQWwDKxW0HAXyZWLJUsEGd+nkACSIXXpKFR6 sGZDUUCKl9yd7cY+zwYunmv0lpG0/mr18pxyrHRZ3vgbS5QpNLa6D4TwY4osqniWHdrGva1hiymZ WS3oOM+CHld3z+LNIVFFcu+elBVRzZPIRVgKw49mr+8rdMu1TtbqCWGrFAg/fGJ41n72UT2vHyMD tK33K+CRpXCrzyzXvEuhV0uedlP7iCr4gsGEe1j9nX/IKYaXEiTeCvVSjN7gsoRFq5fmozviLe1x +bV7EZn3MhJ0Yim8mh05DtcHFAljfoejV7Tm/xlXmDFPK1tbOvNVNHI58vABn6LL5CO0w0kvg945 rvNcv9BvyguAXSaZrCahhBBlR2a4y45bMZngkBkcvxGSzvuE34xTk2QZtiG/oRhMyRFYaUZvMwPb 1ghR2JuAoarQ0Ilt7hanocVTYmY43h9VwP5a0w4o64eYrdpEcwe5EbOCwktS7sAK+KpO3CiR6sGN HlEWnkUkPVsUcUK2Ged4jnQMyxtL04s/ke8x5q+HfDsOmSvPMME8pa9pVBHHZ3cAPGPeiH0og/hj zpTvpzT0Kq2L9AdTU8TSRABEA4aGAUbdHRz1WwMyz9Wa//Pm+CIAUwkPpc8EggdAV+/i6Iv4JPM0 Czt7243Al/BMg1BWXMlhcJIWWW53nF6N6hWCZf99LMShhHruSDS0GbKkBjibJDvUUT9WCEI8xf5t 3ymNlBNmPiokCWUBSgLuSgnR8lR/xSLgqHOHB310nsN7CqVMtdHRQirmS+fY7Yt4UooFPjZMXZqH A6VPREahg8DZjCpQjB3DOE3Je9CbYkxCRx8Ht2gl1FeBeHMfg6kOid2MXhbqzQ8l202pr5hj8vC0 FKDWW3MrxoeSdLeLlxSxVOOtVIP4LNQ2rUSLPWJQA9YzwLiwuV2aM4DlkHZoBZ/RWne7wI8EkOFk I/JRBN0kqlJXwcO4hXhPfBY2fpP4MNWj4ONyPLZtupdDGj9Wu7HMgzv2RR4NHtNPFeivdpUMIsyS Id3Y9vKchABW0NsVzALpdl2AoUQAWZofx5P7EYs4FdkjXNwaSosW2f3YfqgCt/KsnPJIsY0EbvQ7 tTQMZm6oiCv5O9zJD34YHAg7AR64ikMmftGBBrqs7dAqbfWmo5h5EyyVpSUHDPX6uKIf5efmia8D R3nwZk2C84HG0uthV5t7wrOpWNSE8OiTxKs0tMj/2H015hLSh+KR/upT2pjlJc8wnK87vtEk/uqT FVsMq0xUYOmzoRLZ5guty2KePKpoj/fL+a7gjTBtUGeUQ0RzQABVVa5cbqxtRSifyq1j+qHnfTC9 +otsULQaaipPpdbeE8EsLfnLdYWY07AyiBqswlf3R74BOPk5KaPaT2dF3RwNlgAshfl0QvpCXY/Q n9Q3x4uJbxUuJIsgTn0g2QtUCGsan/EvKPpNXUuqrWRtjoz/o3kMR08lm/iqFrDxNnv8BB86QkOE 7rH9g0g42Mi5vX0gPiznmwFtAtLthw5/daDg1iU1oMDDUUkvfC/3FYrL0YjvjU7am4/1tmu96B3z 2OUZ2pjHg2jswQ9oyowS/3WI64xcivem4t/fmNpnlMCB0G+oRyec9ZIhLgg76aZJM8+cQTyBoXau PR4NvMSjxWZDLhwzl35GG4YMTfOmOEuONWIV85jLEUOXjyaGj4RCeZnFv9mAMDc6vjf010hc2uog RJ58xj/hmz9dE4spqDuUs7QBrRJMkympEnGmovhjbbQdcaFSBIOpdf7g/HUD7GoiceeKPqxnYrhK 1khYvkC/JmicIFICFggqwg98KniPiwH8VBuBrZosYXBezcwlTSsHjEqg0GmQGLjon7h5ecD+PQv7 G3jp+E7McoswRndLgWwYCPVhtL6Sn1BNWcDTklaKXBHB8+3/o7qtR9y86lBmzE2Enu9i1Qj5uMhH PSPdsXyT0PWYVebwGP/1chVGIY35cTkYMhcbgPMop+ggGpVZhlFV0MaQUJPuwf6Hh4KXJOiTQine r8d7pCV3Im4vrrUjhPhZmwBoaEINxToMw+OYzAjt5ZWRlurCrTAoMcY++UlD3Ic2L4tYEL4c3NL2 vKTjVJ8H8g7rGRuImz7PEt9BxfbmVuHt6LPEX7p0Fvc3a3/ZxuWmRujWm+GRarQKN3J1/3Z6D/Vh ThqxhwCA/pWoWeSTRWAgG7z1vm87s8ixZuGMFLhMiL5mmY5a5Euc9snoh5F+2hBAPd0RWVAwQLRz e0Q1QqA3YGo6tu5QFvOgw+tMjZzfMA59NEtFiQQiljl4PxryYHy6VaszL0b7EfRvEEywQAYE9B6l XH0kHFuz0cmC9CWgN9Ql972FWHhWmUvebebIUMz5xz8mhhl9wPkTAdksUNpSQn1O0m++SE9ktcnW gwXWPUngiNpXGr1Oe/z4aDT4a2Co4nG487I9kA1o1PXljnlNFkQWvC+NFC/jjgp9v74KxjAiSI9W mJEHu4GlJyZZprgXUK1Jw0wlmUe6bxudn6Gv6OivSq4YAN+vXXwXUKT5jrInIMqu1KisTM2fCB/E 89RkL8A1Sq/78NHYnjFim+48lMy42EO0J6Zm1IZpTDBX0aulMjB+dtIB9Nh7uJANK4ipdUmHTLdx Fo8fNHQSShi8xWja79zcXXsB2h1ij4Ye2xTziMaPVNxeKE3+Q9Sm74PvkZM93kK3fnXvCuSPTOgN a746dnkv+qon2lRrsR6VS0nfdoB6nVmx8/V2Ab+AYxt9BhAWf+NssyqeV1z2s5exvoy5kjOZ+zAt pZ4WovhI99kA94u4Tc1RFEcezVoV810/s9L2uiDAJEl+RqhAEMfhtczvUQMV8PNHKvG1V+Rz9AZn g2zlkWxkMWy+Z4oC1hTvEmmYhD1texz2R+He7ypAkZf1jiRnBcFt+EEMYxUv+ASE9IGgF1yZlG9e pM/YTtgq96+a7C7O8EQ16qaPkJFGuihQ6Lgluphlvmdk5aqM8PLKXJDyKnAadMooivaqekaIlRbZ 5orxp7k58MU4gGKwwPTSM4z/SNYxfo2FRCyYJsZVhFYDpVitglHg7KCRMBT/db/9SggZYJ5ZPOK9 yxFZFtoVx5oqiyPGEAnJC34bbArCaJOSnjgh4M6ivZ+tMdS3hiDPLGkRGnYSfyT60lC4cAoGX9Vu E6LKyOpKTaDyBkj9mppeVMJAYHSNC3+5TctNusE4tqJZUUizRVrRui6HBHgfuqeL3QzpS5AuEzDU bs+SpO3i8kvAlQlLrMqg8v1Hw0sEn59UpxLyCweIJauwkXqUZREAc2v0/m2p1c1uQlUijBN5DJdB r/mLR7jolb7JHRKZqKNk8igh/1OCIyPeYS878w/RPFUFL63atGJzOPGgdBLv3i1ykbqgseLIi/UJ xjCq4mH0mB2e+zakVQDfvsShzMBrn9MaDY++dvbXmxMIbnFOto35AmMPzEM7YgRlaYWdGXerET0G s6hes9nCCg4QNgpIt1WhJrce9et3H8llwXQhP7HaPVbTqZ+DayVCegEMEPrPcb3n07XtHHP9kd5S X+0P6+h28PWjLlGGAPM723Zp1lu3ZaDvo4yF29886fI3K6EgREIJGrgNgMOiKPh2MIQs4Nks9NTc Pd2s9pqrx1ZA+4d7SqP3jABPiDxslFcozxSFBdK/dxG5Ib6bB5/2yyHh+ghgUvzUbX6saZ/f6rqF EgF/87l8a+hGeNpmo0aAAhB9fgra01PnMBVcBkF3nNI2sQeWsLyr8zKGWe0427s48nxXEfEgUXOU R/ES4/u6GqfFemmjtloa1PEBqQqeCi8Np71/CEsgxys2E+gLqpSO7H2GuWIc9Vug2uzvcJypYrEE CZL27o3/K17TS15Ys6XQWZ4hcinQEl+eIQBke1Aa7pKD0o/IsYsy3ClI4NlkRTKKmr0gRBSz7pF9 5C/x1JW616LXQrjRUrgWG2mGu+xBeYusyTWrJId0NcQvqSmp7PP96ZzvwC6ORGjFywZdhkwGY25P SbP3Bk5/6QxuhbK6iQCwRXL/S/OHakbfIQbgNz2OnD5ZieEtjjFkBksVJkQZRBwcnHuvEAfQM0FE D2+e0YEIuuXUKsDAGvQhwKsCPVIG2OOW0SIwODzoh1hrogL5JGb89/HyXejndEVCqGLaijfQtlWE Qz2LHb4WdwmMNB72BM4ClpwPo5H7PO4X6ZyB361vchoFniPm5/cXencgUEm8/6u17Z7hmRD222UG xvIh5Ukub69DuAp+v3+ydZmlrnI6akzNfo4FAC7l89pqgdID3SF/59mJYI7xtjXLmFUVdIXGuyKb a4ZrZL6zSYMVSZz6Yx8vS6Kl3zixoHGxsySzrvyN/w8JQm6v/PYe+SB2swYW2yAzp/KblpDkvGrd TOVk4pIyi+y2f/zhUB7DLeySvuLqS0d8GK6cbaUTvR0Nxs0FkYbB3gSIm9lJUEsc4wijEaTgHaJx bgwdrjbmlDkFwGAl547lrynamRqPceDi2dK0BzRRRA9NrotK43AKj6KmHSAMMYOuVDivlZlTCMP5 E/HEbdOdkfyvktsT8MzvKtTLCeYtbiHnQ6D75tUozqhmsyZXG2w78scd7daJ/HT9DdgXIM/FX914 5Gspy1Ok+7TwwIbBJtgO7xYC/8J7wZJfHIfoFQUdd0FVQkCo40P3B7eXExINLpS4vZhdt6CDI27Z 5J6BMbvlHxzQJkAfRfakSwJ3QsL21x72UoT+co/VuiScZ69YDwf/rpjjIG6h/28YELMdt1AWiHnl S5o1uR93IniZL4wHN3zv/1Bh07ujdKuZJh1dtAnx9qnq/HVbo3bBfw9Ckztc00L/pCuaGUpmqaDl QRUWLM8byH914zII9zCC14UOg4IdUGgoL6wR0+MJQTqkYUt/XnLNt69gi9InZq1QWryrmDdeH/Nq ZlVZmJeobXTxGLvHWNao67sOjLbUf7QGIqSdQMvGlWwtD/8u+1d3QwUl2h5VGghhs6DKfADCQGnE aRo9qiuYU7OmBFijalWLNi4LRzynaeNvQ7CYh3U1ortKhbZX/aHjiMx2W1uRr9U5Q8ebOwViCLWL Ol/ccUq/S+wbPLK97GpWJhTSpsjV1dSBcxH4aywxLjlQTB+srbD4i0G5IIrv9teor0BJ8EzclDiE aoucL875R69XZ0PifV52743Og5Sbr5UgxktSBt0dUjKeYdlofpga77EO9oQYveq3YjNvWY3Qf6RI 2YYlrG4ldKFTd+iqmx9vjmWup4cTDfQ8dOQF1nSiSmdH7GViCRMVfTItKN2x+U5ccsKp9jwqAG2Q 4I91GDMRk/lraE4aBgarTZouDYCcQlL0LgU5cuO5Eac+3OcqWYN392Md29gYcdiUdHZTbOaO95IZ vRuLMf39I4LvUZzeqIppPj1hP+O3i5qHlDzZFSZbAiC4LZciekfNBaDQxoxDeWmuIUTez8nvWKUd pHD/x1ZTIKAsv72cNvCYuMmBtZrdckS8C6L/eZJm2A4lX8J5NCl+U6HjPlM7XnELTzug9GzaUlsC 3HprpwyJNEhmEN7azmXOWX0dcgAgZf27LsjbXnZY71dfnQzq+bLI3IxhaCSpeKh71RylvhIvAklX KSb/bQQwxevG27a0IXwpwdV7C+BoxQI1R07rxXMDyrnuE4X+UgiF6pRMMXRr0GGND3vZhGpu5q1E IFm7itDfaoE/A58Sxm3E0OY5JnHr4kaoILVgS011gGBk8wy0P1wfajqeDVRsJB8fulgcgirvcfTP NPJ7cWW5iv/hcMHJBeHvF52iVtmjmqE4+DzRdlsjGPTfNB3WMAOZlTLIOd7W1Mf/qel2xRe6QswZ kfS6kAOECzrrFsi5okBTcIhrjGcOgrbqxq1sNFEFdbppjO2RPjXx06J3eoWn/mknUNP43ZMxt1+G /6u841LbDk8+aAQ1gCwT6wHQ4PBD5L9ZhmALJLcflOKzga8YkPjiFXKFzzQMJWXNu0QpsfWYfs74 avSx4KnL7A5LHVboCQmlW1NaoPOOZhQzC1KhRJyXdML+JrXRYjcz2/18+OAnq5CrqwPMcPj2t3Ob aFMc9y6d/nrVsFAv9VlC1qUfBatRZ9n2FxqLZ/0UGpkj3hV6hnFsTndJ8tPQE97uEfwMv/F3StTU 4YiNfQl1d2+QyfoPhgXV+LC+PijLslpyF1rmoLWp4NEyzPf6H5hRWZY4hFelf49QS4vGMya6nAS4 81v6iKKRXMydmiiYLexMoBtmMyvs+rVsVtb5A8JOZuGwTHc4y7EFrOHnuirSxSNisdFJdPKa8Xr3 GsRObpGFt5DcLg1YBAdQZYlzzieH//eB5C5s+66oITYe4nS9ZY9kDTUKXR5VOLvVwqM4K2Cq2g5y wdZ3TUps/jAHBfJoi+g0xA8b0XZgHlyaTBhb2hbvQlQqAPDM34VgZFJ4xoOlXZ2qwQM/JNN2gVYQ fCDEx/XWv4BHyATOFY7FA/LVRS+KK/L9GVJ7mR46fICdXPz4CkVlXjKEuoz2O6tnqNSLSe8gZUTy JMSAP+8pvxBAOKMyKT5eVckzWYrsEGsY8MYqm0L1OFBhxt+o5awLkQSHPCSAa0E0CvmSFSt5DuH/ XbMoHRacWlI7grmImJBBv0qfz0dkW8oPkEoqD9wV5rVJImNjtU4FEfwRTrEepxazbFwD7M0a+L8o y1Lh5r+ioppal2GC38NGmNlgTIHMyeWE/HIsk1T/VIAZl5jCtXVSBtjOH0EoqXESZY4g9pxAL1yO fLf0Gx5Ds+924RqugGBDAjBrDI1Ezi9onAeLGvl+u2hA1q/y0Lvr7cdth10dSBkZaNSlM8Sf1TRp WgGslAb0KqguSlZWyZnP5YX40v9wWRMIP07KVGuAPuI1CJF8qZLJmsew8hB6Cs0JeqG52w3X120x CAAhjAQcpwgSS5d1mizRS08pMQvdTfDelyMSnEtwZJwz7oUgDWFNk028JUVNQemUI6HAIijEwtKU ZNlO0lJ2IB3qqWl3uZHKURELD3cyEExTxVxsBmy012RsYPjPt06G9D0uV98o/7agVxSdndz4FDGY +C3Nt10IIee18MOkjJJN9S3FcO1XMO6qB+m5hGY1YZutcqv6QxHQ29M3RU9AO4K/8dhjg45XmMlQ XX34dACnCjk9EAGj4oBYxrPDXQ9uw2EGF0tjA0uNayN7nGuG/ETnK/s8RcEoFEhPddq2x6HQ6IQI euOE/Iu8913ErMGfUmTjd40h4B+u2YQZqQPq+ymhTfSx+xZjTankFoiHxNe5akO6SxPUIMuv2e7G CdNgMfEnVlGyurNrdzI6YBFql0nabRQBBAfxfRaAbayT0i0pesuIidu1u1Fgq6mpTRor66SKfaNT sHGm5dDahKIZg+NL4hCcy/ENP8QaaMO8iG+ZEN6LXFTBASSfwt5ClmQxlSdDj5EIyrwlRkztbUoX DSdAsS04sYCEABRlAPfKCIwWjFrxskVgNpHYeaeTnnTMufb+DGBNrxd5qjbmuOF+8N8sa7a31tWC Kdiw8qOnH/Uz/NFKPGZd7tYNMVszVYQn+JPXD01/eJbAsLjWAP16jH0ntKuxw2DopiG2gNVeQuK/ 2V3FSXF3DDCz0fTXAg5TFPjndrJfp92N/I/KbgwEYUIGK0hcmW6gxFGcLUWmSV70ua8ytdEyKGxg Qe9hOO4Cy83lznZ4pIHzRZWdZV98thAVMbp1yTwCpBb2mw6xtn2rOZdY+x5YMeCoG46bD0drs+wa qUw74RnGdin4hZ2QxWIcW/8gXTJLv++QWkTzOkswGf5kQZtAh7hqHfwVIYLUNwf/Pc8vP7fJ98b+ 6KWFhCAlxEpuB9D8EXVDoGGXYOfsfSHLkDyjU3KgUHc9AKAkvu000UIhs3XsdnpTmJ4FSuVTQVRJ VwsTkW9MgF1JnV+J1OBB4e6T/l2EwTAU+WA50SYOYobq8/Pd0jiNbZ4MtsYFgbWAlLjCfFDNiD0m E3avrFKm+JSQi0cu/mbLW4TIuwZpQXbkmNhjUrZTfLMhsrELFwJIVUt3rdXKiGdzxF+YScQvUpuw O7FBDhpHbFOeq5aZejHt7iORwC75EoqCg+8pZJyC8a5Actbnp9YX8iXx4U3L9CuciPdaZDVnMjJx V3YE8n1ct37AK2YxkzlGOjXF8YfO+7cIn4F0iH1HBGdQLaRbaslQ6r48ZmLGnZj90/1xuiM6hgho ShnxF+Fkitt5Wp1nqWdccuzS/aMBDd7aCA6RLknJzOnxwL50N8A8eT1qxG0kmEEN48kaGIL7SFly 4KW4/dEaSiF+ucUka0+6Kr9llNY/lv8A03x+UD+ngVmSe2hukV1pkDoHjqwbWqNdi2ibYH9DmF6G ISziRjs4L7m9JIHW1Zx8nCmPTHYX8JoMKTnbOBpcWG0xqbX7eemjJtRMOs9Mvz416V46ZNvVAXfh fuP552qDNtGwAdohbrFp2hZQ/UPR3NHC1Nsf2laiFVATMWjubuXTx692/W1kfsrfIeT4Z/KLlmox qgbSySkmZuC9cAn1RtX/khyXIgk/k50PWS2GyDF8vq3USb9NF3OVS/CAY+de02ojU2Gsll2hwXcN yVntXZPTzwtTgb4Rzkr6NVl4xGFA3FQQO7hrBkKXdG5J2O6UOKlWbYTiLUE2qYByLd3HhzdDINDa ZPXdazQfLjKGwjA8BSE7Vu3ds4WE8JCa434zJ+7U7pDfoqn8be3eKfu6rDmqZz3e0oAdUzfE0LtJ bWnl9prd4nMeyKHy/YN4FRxbFaCQdV2FDoV1GCJI5lZIGwZdLormKmcmlInUt74ynHvpO77gMJIt lJk3TxvHuvnDSaD64OXtXCNxVVFSgRN5SEKyb8dxEG1wT/3BZvgDqX10KLAG3XFe1VryFC+So5yu X1KrDQkEidSFMwWpVqzAka8oQ4XqBGSPPp/YehD9qSUyXAvfvv1RKUGDDnmS7GIgAPJkpwW0iMbW Wdc6dHytDaUWmUIDZYG2fbb4arPVE2on1ddgE+JHJjlVn7Ct8DqQ9SQIwTtLiMvMEsVs0BTHNnsF J/KIqMrr6XqL5ryocXZcgMNUKTEFBfohGz6eqMM7Erqz0IJYKCTiDpISXMwu7gNGmO3ItVmM7rRk 9UpfjO4iQNKgG7jfQ8c34CSrnjd51k9s1a3iKAn1kXdiML9BQzIVH2eBv21Lg6hf0ZZLaPcr2oHg A4HHuPGzwtuDwx0kurkL4hKSDxup0GM6hAKoyi0fnaoO0znSc7p3JS+Dz6AWb2beLrG6yPNbTNmP MuQZGft/QzIA2RucS1OVx5Qmp61PaGMKLe5SsRyP4xuC/XTCdu+g360flQWy1iuLyqCqc6JpVFJl Q07GHFWYakux8KODE6OaWDjHw3eJjEk38fbd9SBEwDEoGLT1gTELjd/s0Kw0MzldON+IB3i2XB0a tinlwYoJPZevp71hR4QOCelXUscL6Kc7ZMXgJwAR0Qdi6Ky+nSpZwotJhRFO5xACqBoNG12TFZMT 1rj1gdeDL5Q/dTzbJwESngXKamgARYxFAIqr9rZV+y4aImw/MNmW/phgnrEVqSPIk0mbljJPIGJb UBeWfW/hNue68IZ0BIqm4mr9wGId8hQjXEG9ucheMwGl5YXk6i/Agz36m3U6Zx2pId4dFoHCDhKb Nqd5u1N4PhM2DhLe3LIoLIkENNy7I6rDwI2M+7rOj+TllWb0kuUQ1tyVGjH7mIvXV4yhCsVXxLiz dc3go7f0j6rFDVASmja4LyoO5/EE7aUPEaw5RqTOLu3N8PUdR1TRcakOkUbP0Ix+tSd5k3bXcDo1 A/NPN4oVdGU5BuDQi3LFzPpvr6I6OSCgGSQNJ8kPUq4+K6EIvcicRbRrxYRVK51XYb5G0K6qrQH+ pZKqdaipg/3o8vBmnFBPEOctbEQcP0SGs3xJiSznmlF5nhtGYTVSCKxmqvtHHUJh1f3GBIo7IjZT NtViQ97/AeDu9J/Vmg2uZNrGyQL8FtZxtDSpRUXno/tlf0tfMhW1VGdITlzgbiTsybVv4UiFywKY 73sTD8OyB2HKEdMJ2scAd2v2eQMFS3E+B9G8/x28B1kOBSlSdz02wwsJd07ZIGPUiLGGC4hMgpSJ pNbN/9zz7Ujpp15YY9DJxR83zJqg9Gd4s1qfuqcKMRZXuaHDRA6Nv+f3wH1Yebqf3rXE1DyWH5S9 eHeUghvHmScfwPVRhJgnh2BWi0A/Youv6JYDCdTqQJ4iexE2kQSs/GikLAP9RT6WEofQ+iBS2KGJ ZEZz/PiI9Vd71xkAvxkVsYxc0dC+71VpQ6xKxwB3YICMuMfDjXok9H3+TadyXRTX9rOSrxacw6IE xBhJ621djO0Zsl5r8Bx3wVCo73XCsYl21QzY+wrCEwoNyQYtzTUJ71nV7E5xp5sEYzak7PxeNRd7 9MavoDr6rI03iIFyRXXyG9nHCGkkh4npsAf+gDEqtxZq5fTz3fpB8mC19k61m/0zp8hFN1wo0Hsw 1y1+z58PBL8UEi+pNus/eE8LL2KRDa3Uk1ZmAWXFm1mHpJlOr+OPwRjgx2L0lkG5OG0YYTUzp+hc zQWW7UqCqZwBjB4ao1fA3+nNktE+leBEdH/V5EAetKpSY8kaRnAq8A0KiCxlLFafml+l01jp/0S/ 4XjQwSSXSFf1RPqjluCjnA/T98xRYRXFB6o0Lx/YVkxow4+PTJ5Dtd6xF7PyV+2pG+6qV5FSj+fx JVVHVXO0HaZLG5KLkD7RSaRefj7Nb+LEDnzs9rmYD4jUVvac6sKQZoDVvyqM1FfX/uMEFqls3sXC NMvJN6vLTQ36CVOA7xKkw1pLYDguvU6tgI4s4yqX5MBz4hHS7s9tEaibtW3zLhUyutftKwu0YhtO 4UYgovoG5H+4Tdby3WY6IkCv1+DMeyBsOm1s51eiYmvMe4sB/En1dRQ0itO2/9sIxL0ddNmWDs7V gKosCBYpaTlw4W67ti2Mkk004KlT6VtxeTdFZk+oLfgoN3nNVHF9k7YA6FLdPZdlcpxfs5oo9bCt LZkYXBJchD1hBEH+qFTu4VzVyM/xEuLzhih2zqKt5EatYs3hQSXZ9GixawKH38fCkBCJXq1oM84Z JjKZfriMydnVvO03Rl/Iv4GVDZWGlI6Ieici6a+rHcpmOSTDt2FNJY2xbtnWYgpaiXjafNwtIgnE kEIMJcE81NWHVhLxIcCkUha3lcKvJU90+itqnjdMmERBPaz5UJIhVqcypsETf92ugCjcLOdp7Lov wL3svZ+2LH1zmFX627ixai5P3GOus0rHew06deDvORaP1ihKBjEmBA60+yIwcSraMVaYi6Ej3IiZ Nf1vceObJ9VXtoishbftA398Sta4jUvZHkjDj22eNYFLnMaW/aCjCgI6kkQpx6jlbM413RtQZ6h7 L2eds0z9donZ8pFmRFSmysxlh0CALrvoUZ3sXmnIFtik0tE/6exCWmZdSlTjBqaQX9Zq+CpuJuPy +ZoQTJmkhFq1phKHr9YNaYLYvX+OmlPkk0tEIRyhu78AmR8tLPwISJjvwm1TWjasDy5gPD8X7VeN iUf0zGxgfXNoOtLNnk2dxroPBumODNnILEJEUwR6NvwNQ/iDaaORUUCocPo3DznM1+uV6C4GMVlL F0+q5GTgr1mbKuMof3nHtR2TEUdlikPv/KzVu3t+MWerozLoKl6J1EDDneaBObXSleP6NVZNvZ7Z vaSYxuxC/7l2i/SdO7TtWERS2bkQNho00lNBH6GqhYHgFiHMHkAmL5uF9Moyqrub+V2o0sU5Ariv gIXXpM07rdE5BtuJKI+32BRD94CVkV8BD67t6MtAXuTsH3z6zgisWwrK9N8TvvZ8zI5jPxNMdCUt pUTm1ICqaQu0FHFyiL/GjMHG6wiVu0si4EYubyihiuEFM3TAaxcBt/P5bAbo0t65hvWTAIBwVRJE lDIIa02R4XZw3zGdJ81hQ1tt/olpiTU1TnyhPv4nDGmcWbn9JsG4TdGdxTHmZRVm/2fhI5z2XJ+e guVs//GEyQfj59G4ve/b+OHWgSifS7xkXtNjGSNcWH5HkheYcslJN6eNIW2vAUZd05vm92SuhfS7 pwtQE07s76/Rb+r52nrv5pQc4AvWgJT+g/R1G+dbYKdtEj8tgOWQK8VHf99rJeUaiGsmxaHgbzCx y/bk5Gymrf892xLzak5LSdkDijIVnuehwXQnry9zHFtrAoB6ati6atusCD87C1IdjgcxJ+dQ2kh3 NVL+dwGhlRGkR4fu0iq/ekt3rjpmNJbyw0oMb1tfIrCw9cLdSgGNUsLRZfFvEIasRqQ23Gts0CKT KsMI3YkeujuxAczFReyYRJRUJi3/Sqi3+W9x5Ilm8nua98IGTb+Zsig1OaIGK8cFyBCkWI52p2tj nP9W+go8iwM2vqelLKVJ+GBOLLA1vfa8fzUuGTSKodWIMac9//wM11imb+Qwm4Rlz0miwbYqtNf+ lF7vRxQYRTCOdS4JlatHmXfklEYzAluq1FE+93lPUYxzjMy/AhEUHs/oRW3uUEK92Ktb20orQ2rs sPTADKW0p8MDKVlzR7PdNJt5VPUtIhDSpBTISA9SADj26mwH2gglGOt5aype8tEYFjuNFAxzCGts ZMk9Fiz3FKbtEkK52/XV8rEKM8xD+ds3eKLp8SBYpZwsDq2lqQ2y4M0TjN8yECBOSHKmoJXTcPJj DqKsL/YFKuBzhYQ+J/mVWfCEBABlo2mXwnuuNjBBFtis80pg0zMB5/65GXhE9JXjPCGoNwvDCnjr zFfSkcZAkl6lQEF3pKJ1Pi3CzI/7CFzcMbmSxMFp90PvvAKnoGc6xki5p3yG2iNXw3aJmqNLsB2I OQd9PH30Cg5MnaX31LgSSBlPIb9dP+7WNGSBw0sJs7rfjBVFVDHBtaMkxZyC3N13RW/F73aogosm dTg8YwTmvDddvK2GS6ms3x6xrIb4P37u1tvG/JanQyCGJHNhQcSynmjMAITo+RU+bMJY3TU+fDBY gQSoSCcYipGScYKVrUD4RPNYvqgeWqOkof/BabCUyuiexU7rWALsAFuZ2ueCb1fkj9Q52GM37PpD XkDx6wUprdW/Etex+cdeDa/fC7WuR5wUjHZI9Go0C9sn9FEzDLEMhnDkxsTKHalSa6B2HkYWD7OV Gb/kJF+ZuQwFMdDPovfhmOYjGK4heo0U9Q3nXmWnt1PMe8lYGceubfVnBjFerVcJ8fNI62X5qMbW ACiXFh/6LFT5a+xtHrssPCi0O3Kyrc2jNXQdbut/EfTdaBwwqgsc5iN1Wk6peG7y8U4e8yaV3wHu rm8umyyhK3r54AM7XdWBftMroOEiX8ZVbU7qWe69x2rBBRl+A13DBjAFGAC2L9hn6PTrsAilTCg+ OB0AidUevjcRgoOmjN8V4Zjj9T5ODh5CtFWVYw7+nq6kUC2ryR1D3VwQRoPlW7tU9t8bGQ+kIG1e mnx4R3ikALqwrt1PQUWxNxpUq+84Xd/BKQLPtooxDzBs634LyreKMiFhp7Q60ThiqmL1oO48jAoJ Q8SS1ucAmJFn1G+KCxe18dXRw5LhiaAnH4/EHry7gTYrp+nZ0PQJi2I58q0YvyPusl2hisyO69bd Rsu/eoIsvz/Aqat3kMhQUPREiCfqogfhWBZRJciWxkx/Jgfn6/7aoKLVAilvcg3Kf03CZZbp7uKx PNGlWQj42g3/hSEh8GURQ4Zjbswof6MlymQEDGAwY5nuuQpkr9AZa2vSV0jJGabgd+M8jhhQTvYC KyFRZJbkPw6WUbAY1syNHUHNoY17JE+lPxso+wfbUnZ3jXEAkd1NQMzq7a/HFbvwaf5R9QW5svYq MmgPx9dEYX4rSvL5UVgo4PVrna3sZqc9nTkgyCOZuytAkfrXU22MSEmAe4SzQSNci4Rx1k1dYP/z 00l5JbHc7Hg3y4P9uXbSZ7LsmzflG7Eos2pCRUrhwporOw17et+SZB9X4/0A9irXL1kqcOxqtVvo irzD8eyYtBUyB0IAXxZiwNE4pRX2LPDwLOV7fHWChETJwuM/LkVsCxipMCcv9masOE4658k3zq2z sECEOEFSR+PKBsaQFWh3oMnPGgIAZZ+V5QdHOCLoh7XNprF1BF6pOGjEONPT3SbKbZMTku3Y+6xx wnL3trPLtlH5S1eO69WhxJ4PP81bTRbjMMuYuDByXgSZ1yyYaisNc+j2JGpHwtRQWjfY0UdQbuFb qDOnrAduipQ0MoVbeF5kKX7v8muN+A3+GEVLCfuoV5L1kLPL5IMAW5oEppbL9GtcaN93+6tu8Z6c eZ4uv/xqanpG2UkgAAILbzHP/jS7v4WgF6ub3Bh4DLO37LJIXS7+HorxL1p6I9wPsZSXDwdNjj1M Bn2DahuZ176IVgsFakrwZ5zcLwpSUsnkgUU+MdqsrDqS3janSV/VPQJLyeLCMmsXjFDxH7V9z2CL qR+DgNEjJdx05tg0exWAuMLsYWp+3baGLjSx1Ng2etVEBExn0wmhBpOEAPKcciOwgOGGFwkDogv4 t6gwk4GCjfs25f/aPo6UIXNYyG7nOKqg1tWWDYLPJrHU/Q69/z4awEOht+4B18ZdhZidgTPo5HX1 hRHj48nWm6O0HmyPfFSv76UGCbseRExUvTksPTbGmoiDEaIsNjUxtNwCdk2yHieo7uKHXohxuO0s X0Qcn1SpK1nQvzVuloOJj0syJ38Wh/AXRvJoGU3yyT44CIXag1ESymFBLkyjFZwM2DXUWmoP2ou2 dogDvj8PHDWCsj6Kism+l1HXKEHfTzHK46naNDsbuw2QnUz4UQ35zgtf9HqNs65PWOuaLt8bSbCX h/Tcb7jZNHsARxUyodQY9ATk66nfZq7I9ll7O5ZWTZHqb18LE/VG4SwTMK0plV4c9HfGJnNHw8k/ BdNjRoGTlV2nq45ZYnvPwio8I5dAePncfuLBMEeSHIudn1XEbjMDdPVmjgyuW2I60BQRAx/nCK3p /YygKvzbpzuXJmGXbOMmK5MTiFWv/mJLmpEGGu2JHVmAkJWPR+irDB9WpK3C+Ck2ovUj0aZQH1g4 BBZ+hmD3isbh23jSAMxDx5JY71WjdihpQSJLnsKuifTBp3iYQ2J3Tpbpad6EXG7AyJP8jDU1VgmM LcP340fA6CKx64kPm/iJcICSxqff/nXXuo8WVPOGL3aXozHE4GqJryeD6SqdVyv1oEhlBbWTyItK CO72IAOaLuvvlE5YvudX2VzOF+GO8jAfdpHCPeqgpNhWJFEZGKZt9AnFHR4Lr826V0bqIKFgXdFv VA9ke3oTTdjWZeTC59/Z0pJ1t9xB7wp/pDxCEqToSydhhyMKsCx1Iv/+pGCz9048n6cOFn4Hv5Ud PrvRaX3x184dRwAiJAiEpy+6Albo0hl5jSLvPK9QBWncTN+u/E/K+VNHpv27iihxyVtOBMqlMBKz abmm40p3NLQPyFGLQwr2EoyOzuS63hpER+aQTx7cprbrDIJVIudRx5Qv2lXpo1tsin+6kjaui/o6 z+ohhBpKCIY5MCdebmkQc83pjs4x8SwbnEEEuQED6kT14fP3MBbhxnn43yRoBGbKrfgqkaMXCzg+ 0a11QXgLviLyHpUqhXJwU6uCpGvws0UEtnBAbjuubEsBIHUDK56pK0oEXGht6h7HE98luWMrdje2 m2pyaDDJAc+ZwYoSm8uhAX2SU8zqwtmP5o3hr7wi3PJ7hP7fzy9om/pSWaQ01MEeEL2d5xeYkZq3 nk/1//pqleolNZmMIuTY73cMnzPJWvBpMesLJ7kiZcSPrUIg2t8EGx9ae3xV6VD2Feyf9kFed2Io D+Tbqvpar+Rk+HNfyIgpR+BpUBhiF/tcOKoMmQLQn/guO0W74G95W5OnDqwCsQnKMBSIjvU0iG4S UWCe696fHUapGdCOJYOhfcEYRhVVzaAxhxFwmo8u+0DzkFp1cr0xiEoTFwXbilx/DMdldraoGu/s 2dI6M9DYbseebUIIbf0JcuTnHcX7xnsEkh+Wio5docDp67la0z49hbOlqdkgCSEbWcGbrWx/J+fE Wh1+M6cuMz3xGVL+0DGmyePlEhr4NahdVKk7EJ6AUVYEKc0TOJe38wqg+gOCH3jydZMxH3SkLMRb ZnVGUYNKBj8g3BJ3VZ/RxaI+eHqJCmvhxGbMl9YlpY2URecwkr0GHQN8hIpAEyDxcGZ7/4sVneIX 8tLtRol5VWJJuu/asRKrIwyqXrwnZ9r2U1hQeghf8+Vrxqzo+WUit8gTwsHDhWfeYrVMYCqkdE6o XarEOA0e1TG5/D4eyOapIa5sP2LRWa7sqvwkWoiJBRib5jhcPs4AldD8ux94/C6Y6o4jPK4b90Om +BMd4VfuNtfrBcpqW+hudT7Cecmh+BP8YPQY0CXGovaeImj2le6dc3nMJdncH9B/3BNlbPP8186s Nruske8h/8p9mGRZUYDdVZU8852asfniFRRugLxGQD688SLdNCKxEdcb00uGeaSOH89X9bkFUM64 D4YpusWVGFVySDeDqUyRhA8CjVaXjt/FWgyy7si0ZakX7dsUMy7+z30BaCVc8DrHF+UsI6K0DxsH oemZvJkRPypWZ8YEvviBQI6Binu6ANV0JM0smOVYaStPl1aQ3YSriVPybu2bKXzGitN94IKLHcK/ qYnpCNhZ8txgDQSa0nUjmUageyzRf9TipYpRwKuwFp0XF4gLiC8gkP15kTkJUjgeT3ltR6nz3XzT MBJP0bMSU4KATAtbmQbO1rYOLSk3C03yfAWEM4o/wZdKcOpsWwEwx5sAH37870ufa2CZUps40Ire iWwlxCwfDatLzOvSilqw47urjC5Jni0MUo0yLavcJNrefNmSkdDlzsokbXfdFGBaTwcFA+XpbSAX Y1EyAY4Op1cOJgg00am5lgUdiia3XGluG+Wsrf/ec8ARCGz7RzEsKNbqWAD8XAmqwoTc0q8y8Afd xdEFyBKhCykgT+wXEQYQGh5yO6XK7pWxLV7BcbZ0EbYuVDpj3wwy/Q2uPe7FlVuzO6wYW2cwARPU rP5GRWUIRgmLnEmTCMEUyH/zDdcb1R8CbvS/Und2r4z7rhfCm0B1hAga0ovmO2YsJh6OtCJDruKE 003RKAWrsyuL8RmJDIhamWKX5QxNSQaazmkPGaXTxpIpFQi7xBdXrxLNFTVwl3kFT9u1gG+f5cln N+T5Ct7i1DfMTGlwIYP9asJS4R+aEwJFTJwU1YnAWP3ogOFbKnpJEEiYLVmUn/icIr5K8rJTd6xo ErEixTxoQqihlEQ3Z5QFfZ9jcnsTvwcaXly/TtGS42ROiZUnJfN7YrLd0I5UpwpWLHUe3TAkEHGM LA48C84v2yDwg/T4gOOrAw14uGLiR0SjfYYYFSYBO5AAWNF0LgUq/pP9xeQaEmjr45JCmzd23Zwu F9CEvosUYoiON5y0Rj6D/aDAFJZU+Rm7jFLeWz7s9Hs59Bi7RIClIgA+9exGRp8hzUhpwQS9EEaf p4SphfMOncpsM6Z2bdf6G2YpvZfTlQPbuAw47d82XDNTAYYOTRrYIBh81P7OgGh5xqrT3Y53Y85f atuKziaXubk460T4inw6ZB53UvjfXUqFa/WY92Ukmf7/Y2YWFOrHCEBE4RjwysyS+hwQdJ8swtCj IWXWSHi83hQmSL0C9rbuvZJXUfx1BWNMabs/k7Ef/iHUGxzrC5zCX6FcQUoxeZzgqDQFSbbYEt7/ XoutnslJOzPAGV2zpOKF6pVBPzZTKeAo5sEl7sP7GW6XMNiGBSQ0ZTwYwLGjVGevckYdxGEGjSgo i5GpW2jx1Isu1XC0sK9vo+vWehQ6yT26VVC1gxucl8LE0a31HhTcca63DRWjGSxtLGEdR1MQjLX/ bXt6LCh/YWz3LzGAQdeob5r1yGe2V5wRr4UAXEa2QyK7Pt8sg8GbvtWbMoKukTZqfBsjWbvB5Ye2 T20exxDJZmAPH/gSrxlz0uUpGFknWxcbdUK0qdyq8URohDB+9z8V9WvZaXjBAXMA6CLTY6cdSVpM w65N8QBl+poaBWMgxBw4TKyzCgnhpDBSO1JBL2gxS7bUcqIZc32PZ/Zk5WS2quCs0kR+J94P1Me7 11rWLrhWBjcHr9yUK7UDXYDeT/HQW5m5pYNzodZKzR0BaAgZYoPCymJofoX3OOfQ57ltAiDGGAQu Wx98bneqllw2n3rJ9+5U4jV1DsdvPJvevt9dXQS0cdDweptoqiT/c102/DGYK0YKo6XfqBkWORbQ cEOrD9S32Z6iJc/qx64akN0MrDbSbw1ImjJvjrM9XdvSvKMrUSVNoHuWMLmI5APFoFmCDVPCbsmX 9TsLQ6odrBjlKv2zZFIag1W7ZfR7UZt3i/wPRU+gzEeCATZfzAfuaclXC7Z9dQaMTfEnX/4+CFsx awE4ln+kU2zwiULYNDrn63tKJM+ChRC0jq+L/aFs/ghXKzEt+O+OVhBn12i2GuZbmel3G+NmvU+0 q+oF2pou3fgzcOse2ogv1SoU64PMszM5JkuBeySEbzJHmWY1VBVdnf3so5pXDLbRs9gn5hI9jb55 ZjjkxOc0P7EjuyWpdo2MZz28asONioU93kyfU3T782xuQP52Ya94lDoVs+ZAYIuh2Y50pzttFRvD oX4qJB2xUtI+lKBJJ8Jswobw7tHWn/g8YIEV9xP8wFQ1RUj9ZBjpXbfZB7nzdv2Tqy82+9U4r7KE zPp4ahbKhvtTEzaJHCcVuy5aDz9Hao2rT0lb1xsrN1EtoPkYtK3AAHY2IFwao2WQDCKuSnvWPXN0 S4HwGx4CrO1PxMH3QFRCetn8P4kmmYRRREdRuUsWfHElt+5qSOfrcXzu8/8raYttxj0/BIZ93iIP UgOHRsTkLHPWsmb8nMkyIcTcezANk3Uu24FaqFtbkE+Zz07W41UC+bMYcbQWbaSQzL9VsL437a8P 6gVvwEfmgCPEN/8+OK5dSwDJ4D4GpTnIOw6aeoCB+IROlL4sFrtwSbK4DP+w+atrcx3EXSWYQIMj CAURZSAV6wNgUArY+MHredW91vPS8K2R4kCTqMFx8emjZvke1aXGLvH/XoMDtL9e6GhfcQMylPwe 3ueKDK6DtMFIdwPaKwxKx08cYAFhQHaW48LdD/pzr9WitCBRfyh9Tmv6bRvoy0S54tbh1gyBfdxK a14rrsJlDNHLVrm6MPFZlxeJmchApKNsuPTkM1q2W3LiG9BwtVrDKlvG9+1dEA+F/E7zNOCVUXLZ MbB70xS3/HZVhwE+/Lr4GCCFDEO8S4b9ZtQSR3x/m04RRuDW8ZBj1kL18T2fDuwpZXB8MaL5ToNv qpI3cDvsAobD7f8fUfWPQqdwqTS1atGHmfTaxo/y8+A5izVkTQlSPYdAUdXynosrdYBLZk7wpHap kRAWqlNh9XQw3QpEgCBIaiFs48ktxA/lT1ckxgv2a+zvdvHrOKaN3B1UR3zOeNTCQ74l8MMn27Kw RPoFN1wsttIjP+Oieou0rwqGENO+P/DLPQKaUeDBMbBNjk50+oB9u/jkSBvgtvfCF7eWS6IdEZYb 9LHTmT8mu2KZbtoTRrMyQ0sVZ0AL8tlBkczzvjgmeNR/onQ601xv13mrbMWAHgf/QLI+LWE3dW2N HLZuRWZfMpMvMFWox2EmL6vxzYoqz1vaPtEWeR+7Pr0r5xFg+NP6jY5zrSDeNuD5FWSwd/N1IY1Y m9LcPUOGEcaoIcL4sudy81M98T01prMKtGuVv2m5J4KCEfZn+ZJdQLc9KTasyq2VMj3HbV4QS0oK w8ZNXgWdRpos+fwO6yzvmjpofSRNQf3jBLLk77Z+8RiU/u3wjHZw91Fc3jWsX1s4j0aMN+s0NK0N J1RKOuT7f6QWAl0Ss6Cm8gzoC46nHt9Lb87fzU0j+2UehDiXnKE9UY21rOtq9jINXDg6WeOH2db0 IRZ+VDR8efC1twuiTZkoQZahjKry8VR8Kiv6sh0InoRBt8HVeJ0xLf2oEl5m1pd2Vu8ApC9A61Q6 Ovn2/ek/OUSZiJjoVSY4nPGDakOARIZlTQ38O5gUGfBg/RExza3R+szPvbtqsUxShl/HOE2e90TZ ooc/J7voPCzrNUF3SiVvR9Dnn/wduK0Mr7Cl2kZ1qTWUjgpzSbQJsxON9WMGgsfiFRbwuffO96/v bLjsSJdVdIDOgDUED3paQFIg72azzQfG41bCDJJyPUFnOSxMdjUSWUHSDVTyAvRcuqXCYTowF8+K 7qvM1Ec4caZmGyNx2fz52s56ZyZGci6gIw7vMvZyqDXWblNVd9YRZb8BSwR3GBLubJhdxzlRh/41 QrH7pN0BUiUREHQ9ZRPcRq7oTi4UOzGf+lvL9/9Nqw0JSNCX4rdk/5zy9xzXS7as7rA9O0VuAJkH rDBLGohawTJfJb75FLQ/CXEgy138/+OcefCNNZpGOBVe43dCM0VfKHS8YMXPEBPN9eU7jVbOztWc ClzxM4Du53D9V+UXiReM/CXK9/l3NdrMntNJ7t7maV7dqr6qZSOTNxMsY/Jxn6w670sFipvLX0A1 8InDhgn5GlgjIVrH1U/qVwGRjB/oh9uTCmi1LIETL8Mjz2K5oYAgVi1mIHwYEDsMNYD5hX/qr3Ba ocOh+SNxek7fVRTFGUlYbeo/uLnUGUzITq1sZKnZByZ8xf1mhHvn+M/1hSKwQmjG5BdDgSTbwga5 9cgbUjYmUIFHe+cXEXUbgTFXnUK1BpJBUaD41dJOEp2jjPuT1FQ/5NR5jeSAl9h7vXcqiVSVBUGi /9GESFX/uamGQwP3E+4HUkuveE52v4AIrr35RpWIBtEo+CS2mLnzuDkXDeJ1cYSlUU+Ht1tOJphF qQtqUqFxFhNPb/x7TR29xj59WBQDdvxv+fQAAZ3JDXjjCE6FV6U5qHbqRxh7yX0lLQTKm2/aZT8H 5PVREqzmWEzkWuVXIk2IvXy/xSRRvqjIljlkCne5ThOb3onEXYZtXWrT56UOMppcvqTl8YMRO9WV dX15geg4rWfEEF54/aWsvhdB/HZXbn6eyOqUJB7/h1Q1C62Wumdtu2k2VEzTqjgu77M83NCI4C0K ztuV21TzvaWcT4dDDIUBQbZSh3AxdygVm0kVyVCmTcP/GSwdUSU8Up/GlRlTlktj/ogqBBL+IY5S ZtgLPs76WfS5vfZETH1BQSsxhnEU18ZyeYKf1xNwq9C7N9NsxgqbE5fPc70LsgNfMu9F8QrD3LMe IBwPyN1MUC0nrN6x9z32OqhNHaRo1gPBtuQbOft1zHOQ+05a/Q87uwgvf9fwPA7axuLRkukZgsgk PMoe0J/08GD/N5kl53E6xnqNnuBpUP8P2FA8VddOcly3VZOZqimcdI5EjK2MiAzvvlnSKYKW9+iO 2ycQXcoaFqovHlCvgZGHpGWzbn5kAcCWgtGeSgfW0lJbpBv4u1SORfNOJNWLxpRD7Uef1I6yDUYo 0rcy/VMJn9kqaEm+k2/tXsdiCFTDFQA5tQ1j3+3BhX7+Kfw1goykdE7XJo7oEQk+GKBvojfHY/Y3 ESfaq6nWHEYvPI5/VKAcl22crRA/EkLqXKNV0jghovq1tw9EQemFYGlsYY8+7HGLwtcunjBh7CfH i+Dd+iJlw1VHLVXxCWOHhWHPDKJAGWM0ayUEPC7MSDvHtI+yJC0PZyRrzsUvIDviNjoW8biRJ1GX /O6R2rPTzoRzREqtkjhb9LLUWikLtz3Yvx5v8Jkf4JW/AVwVWXsVcDrH/DLBby74mAnZ3t6xpX4z aKzYXGkbM5sR9iuJu1EA85gGXdqgLj7b+Rl0daT3wXFiRrpxZCJfHvUA/a8UPzsbvSOkV91LuiBe 7A9ZNQDdbAGeWI5D5GVLbG+WJhzCh0jm0A+y9SJWdeWyaSRRHA1sN8lZqLxsqI+iDYrqytk6/J6X ln4NqEARGNzGDNAKF2EiOusLL52ecdwCKwdvNEOX+D2fSK6Xq1rLWHclAQUQLkjmXqWufCeyw6gB NtLVcce7aFIS+89NJZ1QClldfLuB1ekES1hIuVlv8vvNN3c0NkYzlaRVvZXqEMEVO60T9u03CPR4 tx/aPo75VkB5GnP6t1b5W5RIqUvrW8ZbcR7pCbT7+z4ndnGsUXtOh2W/np+icmwC6dff5xunMQbe Wt6la+yT7i1qfxd1LJmxB1g1CRtJmK6P3qBlH52W+83B1YAqlWxGawPlgygwQY8k+NK8tRUELFQf kc2XTq3oadQncTz5wj3kZw5lvoK+/9PpaD+hYFNYNO3NaI02jFf7EI/s1Z6WGZn8+RHc3C/Qr4Zc DoO335LRzm+3iWX69bZA4oR0cF2c+KEu0D9NWWgmv657gCl6eOVrBA98xla9xGxxAdJJUtIhhm3m LIT2j8QL4D/ouqIiNfUaDIXBggC/75As50vLIxQmXcuwZSdjM39jbR4MXEciJGCf9jZ29+p0LwcX h2UhNXriuu39t6PbZEBJkEyLokgTobFmOnZlCAzsZZVCURVLCi0VTdkatLbd5n4ChJzlwB7x4kmx r0Tmhc6xI76xAQIhHJ3uLyBexHKz+a1ohdCwGxTcY709O3KYgcpc/EvRr8qgRD8TzD4JCrxY+rRG dvE4MWimgoLipcGOYhh4CC/yDGuYyj3h0KLVJ/CfRUMTFco5iuyuxQCpbyC7kF5T2pcs1fdN+hD2 oZxyqIlI+Hy9VMtLi82p3FUyrFOQwT9qCHPsv3m91oJ/9AmAagv9sTLvo/58NlvqvbtIxoZvvHTA 8MQElYmz9hwNAz1KetXiDfLQ7Z62TQbljECXYoFyQAgVR3gSKh7gnVBGZK+3+/kjcuRb32iXBvt3 qx4jX6pj2JB9WAGUs6tvZJ1bDInWPbCwAgxkWe0mHWftk+Xd+J25pnynwyao3+0YvghWmB1XTdTR d5shQKrq0Qm+skVZe5vzZyYcSKUeecvhj8IiPNyTxmPGeBRokLbzmDi+vJP2DkyM+AEwPk7X0H8g dnXjj0SsFUmid5NgO9cVv7yfxPe4f/kpyoz+4Vczlgf3S1hWLbYKbv3hCqGyVKRnhATA32yt/I7D 1zTFxKTsPMnbjqd5jZe6TmsC+wfyhMdIAKXpDLAI/5X10b7ZSS+POvsI9YOD/31iUAx+PvqF6PM1 H5DVbrgbzQL21xk6wfWcQCwPSgfqa0SBYJJgCbexOEktgK1aXmIiH5HP8YTX24OsyEfB290m0mGt MK0By0s+PyRdgAD1PBdalUd3e2OP2yD8yKULU4UN/kvLqlP90HRfsbJf6EHKZtLYDwO40CYrjLU9 +5oWkad06/rAha4OVtFzuAr2ashRagZ3W5QeHUzAxk+U0f/y7+ZhPSnPT/YIbVR3qNavwv575iIA +bQNQ6p5RtDrX5poRxT8JJJhYNoKyYcvpq0+4D/FmK/+o1zkICaxubX++5QOb+QOe6x3fNy0S2sV mtfBf3DPUraQln2jeAjsYq0fkP/9s+Ft6rFE1ihTw1BS5xfmqjnFKDMy1apve3jA5nMwy83YkTC9 of0cKsMpVrjdXfizG0yhEQv2T4XpRq/Qyu2r7Etl5OcacAcIdfPMj2U+CRqREXBupWvGX4MUTBBw Xlk5qMnUM48930RqYoOLe+TvG26hmrJXrjH2EwvdujyHNu3GFrNnCqXtRi+zuqriFrncAX+DF656 JhVxBGPzCBiIYM0ZlEyjBzxxin7p3AsZSMOQMe30p8Zh+UH58gPU/yzpbJ+l1R1pTNMCzVSzDSZX pLd0NaCytI3kkpVT1rI0rAz46Vp/5p+HqNSRL3HGjGBED3sQDxHm8IXG9L6G9FBmPx/iqxiuuWq7 go/aMPXUxGMtw5VDsOoBac2+4shHSZQwVRMB4GSxRzCLLFnH0UJ7REnpEHuxcD/qYInhzOqpHL9b 3d9cP40NkwsmGKxr3KILZMGz9GPoqFawe/c1zNr9IVZITUVv+2Do2K3dF8xw9E2plmDsIWCxpuuD Xivo24PCf6h8ipYJfPxZV9ZbKvN8K3km2M1QizqsmswmBds0s9tRk2TCAdcYtHDO6LjAlvQrPmke XPK4wE+WsEigWzAGbA2+7R4FVLfGq8TmBoZ9tcDsRx5ztXudoepW86Oo5SuEeQjg6sfKmwbPvbjW V12x34CDO08u9wJOlebqI2VW2iiWZhqz8dMP8eVCAogfNRH9YHv3qlP46Svs3la58XY6x+Rd3EFM pbfX4NtXxQTiDZoramOyEnn/JN9DspmwcxmIWu/4i0nLvAY2crTqfs/8zNyvoLdFPdI6i+ZzgI+c 68bOK79qx1RHzsqqTuSfqEHXAVuMX4OS8IuxqgDbOnQ8o0dfbc5/7lrTj90tL6/lG/VuiZgcvls7 CJ9aFJTh6V84QToLdvuadGiz1AMhrInv1ESQbpb0kvaur8XB5wYcHf6BIELy3V43/pS/PwceqbTd swORIp/zdcOqimkMB+xZctWZTQz01z2Ogm49fQTnd/bIFzJm6iH+hyjh2AwFqI9vu/zqh8ozAzEQ CadZQ1oe4RBZlKkIFYltIRxCszv1qDUakRBXM1sDYFRvrxYxB+hbNN/EK64H6SICMtcVu4vB6LjH 4EsxoL+ubLv+kyqgDEsscHxebNpaF0PdF5VNh3AYD+OR1fnHpyLp0yWYqpTFROEAf2pXxkoSpuK9 DMsMHiv5g7rfw+KIRc0yrvy0AXynrH/FhUssvztx4KAbT7vQAScgc41YK1nBwF3Rd+Kj4uCO7gx6 RjTQ6+IpU0dThhGYojYinFsU/FHbGjK0/2PMT8KdOThCqwk54HBfAnXL51H+UfWXi1jXOprewbQN LEA0bIUV0sdeZyJsAumxYJ+chuCevD3S+zIqdxR7Sm2x/9M5pO32+hBJ9qk5MBF8L7e+tjLYcWlA rZePqXC90w/albgBNwJIj2p9cyy5S9hnxP0lbFR98/6ZjYzudLXCrvKC8XMmT5YM0XsIDJriFxty RcEL9wSLgCRHURKic5sBst0c1hk1cEe+K/8B9mgORqjue61EcYFRjhlQ9A3BOB2BMKZku3hSb1s0 90iQ/XPaYRo4g0syhliU82ZR8n+vsDkAWVEvYi8l+g73IqyiVCqojfPuNFSaR+BHt4KWJP3z82IQ 8RrGFmNmDikD4e74sdVfSU20rGCks3a5jXC69U4bDbKR7k5xUIEzW4TWF8thzv3mySe0bZAzZHiN BlZtKOz0H1wdd1mLWWm350tWpTZwUl5EOA906oszWQRGrwl3FIpDFLWFRG9Ne/QmE/a0Dj36D2J9 XLtiTK6OHWRkuCeVNDmlDC1r/6bcktPglgMq3RBc2x65sHURD8JSm1y3S/TaeVbYoicpIKl94k+i d8pN/1yW/AsZbzWWxRWC5YNOedxSmG8YgOoukETY6J2CTHdp+jv8245w7SdlnOZQHUerICL4orwm U5WJdY1mDVXzNHK6pUmkHxBzNhF1b8Sj/jZ4AF+7EwF/7SsfPM6eK6hIpBYGWheCO/MHPaTTtj4I g/qRJepS11QcQUYJBEKlUC+Mb12E3hD3gFQN3JVowrZOksukjgITpwdAHls9KItj4OTE2c+KK1+0 fHOOQJ7uUINRQpg647UFOc3AJleZVp0HyWx4OJ/AYxv0cDaLCOoDb0E/vLAUvD2MXvHZoVC2cTLZ yTlMZlWRpKrOJpA1Y1X7gcTIwGV2Q0AEGk0CBJKNGnJXRSyQFUXSzWRdWN0UeavhE7exl+rZVZhG XsJN8iQqTS+jUqHIGzlHgJHMIaCL47Uo3dt3xueHcK5CRbEeaeKpu0vvMk0wIeiFa1DAerI/+6xM UMy6PTOqPLqSC/mlAxzcsQIGGs+8jRaCRNxwxPPKnpLavU+65dZV5bucVV2SVdPh/DxFAoZeH1ws MZRbJINK8ot8aXUZPekM6ayFlz7P4B29HykPZTQsP8HSq4kmzFP/55NdqIhO2tPUlewasjUCsbXs CWytywKQFbYPDTwjg/VUsoSAg/dDFKIMzZydJn2a1d38LGR9z1HXd69rPS+PlyB59i0yfEBfHbhm Rx0NXYzNDQJ7kmr0zAdi3KdrG/PYp4kFTRSloOlk7BeSHtgZ08ezdcIOxxuAVu7ONdPNAhLMj+Tr 5TO4PBaeCmRIMUfU1UjTKVy9wp3IzBhXlQabbZVKf573ujd8XOgK4HoGl2J4r/i0X0GajX1xuvIa qI7gFSGf49gHJhBYcq489Fs6qOBe5mcmNYvU8u80Fo+DoDyQyCvOd9UYSWlAl31FEZFkG3wOjMov LycpQo3mfULLm3zaVlIUFf2k/XIuYMn21bW8BDn3MRT4VYu6ckqHZUla9AnePI/fE8PLK1KHskiN DA/gxyqE/UMFHYXujTb4J5BJTzImyTq4GcsUedVeg2fRoQr9EllJ1pdQabwwvIff1OkCRd/7wSl3 id1dUPdPsevGQ46cslvF9r8ON8dhJ20i/q4aB2pbNxHunqU7pELKVuMIjEXK6C4bROEBDrX+FPyU 6ur2ZBMEv/cfMlyZs/5nZ7PjzosDfWKxFitDFQh+1FQE5nSopOTCvjagL7En81FIUBsKHG5vh3sq DnQ49BcUfMfCIr5XUeT/1d6AjiVIX5w72ueTCO6M8m7svM2VZCmWTbxk8brWYBxIfjOQMIG0Cfxo 1mw/lY43nWeU9rvq3gWrGwESp2zu2zUiCaDV5Pc+hBgrjMmnz4qZaZTAhcbqU4Et1xZW31wL4Hyk vVN3dUg49TbfmXqUTU6R7wSfNkTOInsRdTbS2kU5zLXFd+mwree/ePT0iXwh6oAN4qARZdb67178 gZ+KOxVCR+vcmMOYrd2BtifDvwZiicWHEWGOt806tR3b3fXIDONott5IW2pgkECXnhTvJIBwOX5A 1vHzG0nbHOSBWDQl1hBIykWQqBLyJpFmNMF+eNVHv/JPgIaiNL4Ango7LsTa6dwWYHTftHl30w72 oqGYQVJEiRVZXMLSUyL6tkiLTjI87XRIlcR2d1B8Pl83GuOlKp5GE2nQQUoWkZ6gIV/VdG4ZqDVx dI7DdW9EcKl49ARLt/UtYzRJPnG3KRcsvP2ekQnn5WSa3mZBpqgP0BhdBXmh7LFGDHe+FLWFyM+p ue0qTISq0jCANWQ+aULm3rvRnhS35fo3ZmInZ3pmEmz06ql+LPq8VWZAZ3anUM1xDmmpiz2tl0qo rUn+hx9CA04BNoF3sCbLZ9OXr1cvg2+cGTLwqxnS6HrZxsswgbtpHbUnwXbdVQU65ugP/TMwhI4M XGPNQtCPq7K3DrrTo9/eD0lZ6g6B4gFRJkHnl5s4hgQJtunofhblvkHXs81AAmtxT2lMGyKhFsF4 3ojtRG1lNhSxF1ohkDRgMHoI3XgdsMdeOKR+Qr+mX5+qDhbvG2OBIN3X8Cpe5pGnXKFuD/TvFnyi 81Y1bqeEBKxULOtTgQ9MooDUa5trTAkf9Id9reXsIzsw38TdeyWemPp3+b2DSOrnWxjVu57nYZXQ 1YBxU+rkYcv2cw0JPxfAk9UHuDYpNZGEl65gtO6OhGw7Siweyq/P4kbHWNo0BwvSMqUOmWblKk/Z qrMGtFoAAhNXR4U8WniMBl43UPShgcc4I2HZG+Z9kih+yoxwExbecX6179o/ygFahhhmgp/Qh/fr H95pAljMcQowNykGsWFxHV+hZ0p8j6fScO3NchsLpPKFueZb6u1hlZfzR50C7kXJBFvZdP8em98v /AfwJnUTDhPMymOCFA1jUvoOr5egxkaS4vAXbOFib0BEaqwgavhLYACTlYnqIRW5TihZOTukDsXc toKRVhwuqA335yOsaW4QS3wNsfgBovhMzpEFKDi2Tw6Xi/MMqv39KS+YxPFFLaqGo2VU39aawnKE xJSZl6zlVC4gw61F6Ij1hEKkwQhfeIV5RxfDN8waXmVxuCtXfLMvMF4TtAunLEPd9WZW7Vk/v5AG DWy7iE6Ex2umVg4id4H+XeRXm94lrN7PF6cLu4yzep5Sk8exsGXrMaUkGnhTwSDdTavlMOuBLAc/ gX2AQZ0r46EwNoJ017pjy06Qih5ZImh7t51+Ivu0eSS6h56BRnFMGItHIMOxvbLsfPumeAy8+8fy jEgZ2J7w3hMok5H1Yalgld5n8aidqY209+hSIh0XPS9owRhTHiwrsibRe0U9gfP3BSVNu5aflKon cPyvSTaMbVOSojxHhZm3fNrEhxHhC57rdKtphJM79kJNjMNjSX0RWdDOEOiSYDEqQwZq25ld4Hkc 154LWaTMbKPcFyn8dNtUPESbfPj6fTyD5s+gBh1bN5w/ZpnQc8GTV1BqvpDdZ/dfs/WeuxRUdCSO +qhdG9nWGyyrVom/zGKoASUkKbMXRSt7ekooX0DNDf5dOUW0VynT8vEeoS6Yf3sutC4BM72aKgD0 fnginE817SxWbxzs2yVYjRgg2N1fGHbvny4I2vOymWO/dASTA+a8VvzYIi+ifeoJi8pz47LaKWSc U8KnqVGtFMddKJS7xVxV+zRB49iD5Arsz6MUdjSvJc8qW+FcKbGUVX8fb/HeXnPQXOcKhEu9tDJy 97RqLEAhUAmyJRWIpS38/naxPYc8J2nlzIcG3aMmiTpr/MZXBhWWtl1DD1zn `protect end_protected

mit

b7e3262438dd4d5fe57171dd1b318d5e

malkadi/FGPU

RTL/axi_controllers.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; use ieee.std_logic_textio.all; use std.textio.all; ---------------------------------------------------------------------------------------------------------}}} entity axi_controllers is port( -- {{{ -- to tag controller ---- axi read control axi_rdAddr : in gmem_addr_array_no_bank(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); wr_fifo_go : in std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); wr_fifo_free : out std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); --free ports have to respond to go ports immediately (in one clock cycle) ---- axi write controls axi_wrAddr : in gmem_addr_array_no_bank(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_writer_go : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_writer_free : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_writer_id : in std_logic_vector(N_TAG_MANAGERS_W-1 downto 0) := (others=>'0'); axi_writer_ack : out std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- high for just one clock cycle -- to cache controller wr_fifo_cache_rqst : out std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); rd_fifo_cache_rqst : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); wr_fifo_cache_ack : in std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); rd_fifo_cache_ack : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); wr_fifo_rqst_addr : out cache_addr_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); rd_fifo_rqst_addr : out cache_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); wr_fifo_dout : out cache_word_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); cache_dob : in std_logic_vector(DATA_W*2**N-1 downto 0) := (others=>'0'); rd_fifo_din_v : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); ---- be signals fifo_be_din : in std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); -- axi signals {{{ --Read address channel axi_araddr : out GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_arvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_arready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_arid : out id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- Read data channel axi_rdata : in gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_rlast : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rvalid : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rready : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rid : in id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- write address channel axi_awaddr : out GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_awvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_awready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_awid : out id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- write data channel axi_wdata : out gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_wstrb : out gmem_be_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_wlast : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_wvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_wready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); -- write response channel axi_bvalid : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_bready : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_bid : in id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); --}}} clk, nrst : std_logic ); -- }}} end entity; architecture basic of axi_controllers is -- internal signals {{{ signal axi_arvalid_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_rready_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_awvalid_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_free_i : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_araddr_i : GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_arid_i : id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_cache_rqst_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_rqst_addr_i : cache_addr_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_rqst_addr_i : cache_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_wvalid_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); -- }}} -- functions & constants {{{ function distribute_fifos_on_axis (n_fifos: integer; n_axis: integer) return nat_array is variable res: nat_array(n_fifos-1 downto 0) := (others=>0); variable axi_indx: integer range 0 to n_axis-1 := 0; begin for i in 0 to n_fifos-1 loop res(i) := axi_indx; if axi_indx /= n_axis-1 then axi_indx := axi_indx + 1; else axi_indx := 0; end if; end loop; return res; end; function axi_wr_fifos_indcs(n_axis: natural; n_fifos_axi: natural) return nat_2d_array is variable res: nat_2d_array(n_axis-1 downto 0, n_fifos_axi-1 downto 0) := (others=>(others=>0)); begin for i in 0 to n_axis-1 loop for j in 0 to n_fifos_axi-1 loop res(i,j) := i+j*n_axis; end loop; end loop; return res; end function; function find_fifo_indx (n_fifos: integer; n_axis: integer) return nat_array is variable res: nat_array(n_fifos-1 downto 0) := (others=>0); begin for i in 0 to n_fifos-1 loop res(i) := i / n_axis ; end loop; return res; end; constant c_wr_fifo_axi_indx : nat_array(N_WR_FIFOS-1 downto 0) := distribute_fifos_on_axis(N_WR_FIFOS, N_AXI); -- fifo -> axi constant c_axi_wr_fifos : nat_2d_array(N_AXI-1 downto 0, N_WR_FIFOS_AXI-1 downto 0) := axi_wr_fifos_indcs(N_AXI, N_WR_FIFOS_AXI); -- axi -> fifo constant c_wr_fifo_indx : nat_array(N_WR_FIFOS-1 downto 0) := find_fifo_indx(N_WR_FIFOS, N_AXI); -- 0 <= fifo indx < N_WR_FIFOS_AXI-1 -- }}} -- axi interfaces {{{ type st_addr_channel is (idle, active); type st_addr_channel_array is array(natural range <>) of st_addr_channel; signal st_ar, st_ar_n : st_addr_channel_array(N_AXI-1 downto 0) := (others=>idle); signal axi_arvalid_n, axi_rready_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_free_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_araddr_n : GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_set_araddr_ack : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_set_araddr_ack_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_arid_n : id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_writer_free_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); -- }}} -- a fifo can write (wr_fifo) the cache or can read (rd_fifo) from the cache -- write fifos (read axi channels) {{{ type st_wr_fifo_type is (idle, send_address, get_data, wait_empty, wait_for_writing_cache, wait2); type st_wr_fifo_array is array (natural range <>) of st_wr_fifo_type; signal st_wr_fifo, st_wr_fifo_n : st_wr_fifo_array(N_WR_FIFOS-1 downto 0) := (others=>idle); signal wr_fifo_rqst_addr_n : cache_addr_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_push, wr_fifo_push_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal wr_fifo_set_araddr : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal wr_fifo_set_araddr_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); type wr_fifo_narrow_port_addr_vec is array (natural range <>) of unsigned(BURST_W-1 downto 0); type fifo_wide_port_addr_vec is array (natural range <>) of unsigned(BURST_WORDS_W-CACHE_N_BANKS_W-1 downto 0); signal wr_fifo_wrAddr : wr_fifo_narrow_port_addr_vec(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_wrAddr_n : wr_fifo_narrow_port_addr_vec(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_rdAddr : fifo_wide_port_addr_vec(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_rdAddr_n : fifo_wide_port_addr_vec(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_full, wr_fifo_full_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); type wr_fifo_vec is array(natural range <>) of gmem_word_array(2**BURST_W-1 downto 0); signal wr_fifo : wr_fifo_vec(N_WR_FIFOS-1 downto 0) := (others=>(others=>(others=>'0'))); signal axi_rdata_d0 : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_rdata_wr_fifo : gmem_word_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); attribute max_fanout of wr_fifo_rdAddr : signal is 60; -- }}} -- read fifos (write axi channels) {{{ type rd_fifo_vec is array(natural range <>) of gmem_word_array(2**RD_FIFO_W-1 downto 0); signal rd_fifo : rd_fifo_vec(N_AXI-1 downto 0) := (others=>(others=>(others=>'0'))); signal rd_fifo_cache_rqst_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal rd_fifo_rqst_addr_n : cache_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal fifo_cache_rqst_rd_data : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_pop, rd_fifo_slice_filled: std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_written : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); type st_rd_fifo_fill_type is (idle, fill_fifo, wait_w_channel); type st_rd_fifo_fill_array is array (natural range <>) of st_rd_fifo_fill_type; signal st_rd_fifo_data : st_rd_fifo_fill_array(N_AXI-1 downto 0) := (others=>idle); signal st_rd_fifo_data_n : st_rd_fifo_fill_array(N_AXI-1 downto 0) := (others=>idle); type rd_fifo_wrAddr_array is array (natural range <>) of unsigned(RD_FIFO_N_BURSTS_W+BURST_WORDS_W-CACHE_N_BANKS_W-1 downto 0); signal rd_fifo_wrAddr : rd_fifo_wrAddr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_wrAddr_n : rd_fifo_wrAddr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); attribute max_fanout of rd_fifo_wrAddr : signal is 60; type rd_fifo_rdAddr_array is array (natural range <>) of unsigned(RD_FIFO_N_BURSTS_W+BURST_WORDS_W-GMEM_N_BANK_W-1 downto 0); signal rd_fifo_rdAddr, rd_fifo_rdAddr_n : rd_fifo_rdAddr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_nempty, rd_fifo_nempty_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); type rd_fifo_n_filled_array is array (natural range <>) of unsigned(RD_FIFO_W-1 downto 0); signal rd_fifo_n_filled : rd_fifo_n_filled_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_n_filled_n : rd_fifo_n_filled_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_n_filled_on_ack : rd_fifo_n_filled_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_n_filled_on_ack_n : rd_fifo_n_filled_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal cache_dob_latched : std_logic_vector(DATA_W*2**N-1 downto 0) := (others=>'0'); signal axi_wlast_p0 : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal rd_fifo_din_v_d0 : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal cache_dob_d0 : std_logic_vector(DATA_W*2**N-1 downto 0) := (others=>'0'); signal fifo_be_din_d0 : std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); -- be fifos type fifo_be_vec is array(natural range <>) of gmem_be_array(2**RD_FIFO_W-1 downto 0); signal fifo_be : fifo_be_vec(N_AXI-1 downto 0) := (others=>(others=>(others=>'0'))); type awaddr_fifo_type is array(natural range <>) of gmem_addr_array(2**RD_FIFO_N_BURSTS_W-1 downto 0); signal awaddr_fifo : awaddr_fifo_type(N_AXI-1 downto 0) := (others=>(others=>(others=>'0'))); type tmanager_indx_array is array(natural range <>) of std_logic_vector(N_TAG_MANAGERS_W-1 downto 0); type awid_fifo_type is array(natural range <>) of tmanager_indx_array(2**RD_FIFO_N_BURSTS_W-1 downto 0); signal awid_fifo : awid_fifo_type(N_AXI-1 downto 0) := (others=>(others=>(others=>'0'))); type awaddr_fifo_addr_vec is array(natural range <>) of unsigned(RD_FIFO_N_BURSTS_W-1 downto 0); signal awaddr_fifo_wrAddr : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0')); signal awaddr_fifo_wrAddr_n : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0')); signal awaddr_fifo_rdAddr : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0')); signal awaddr_fifo_rdAddr_n : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0')); signal awaddr_fifo_pop_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal awaddr_fifo_pop : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal awaddr_fifo_full_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal awaddr_fifo_full : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal awaddr_fifo_nempty_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal awaddr_fifo_nempty : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_wdata_n : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_wstrb_n : gmem_be_array(N_AXI-1 downto 0) := (others=>(others=>'0')); --}}} begin -- internal & fixed signals assignments -------------------------------------------------------------------------{{{ axi_arvalid <= axi_arvalid_i; axi_wvalid <= axi_wvalid_i; axi_rready <= axi_rready_i; axi_awvalid <= axi_awvalid_i; axi_bready <= (others=>'1'); wr_fifo_free <= wr_fifo_free_i; rd_fifo_cache_rqst <= rd_fifo_cache_rqst_i; wr_fifo_rqst_addr <= wr_fifo_rqst_addr_i; rd_fifo_rqst_addr <= rd_fifo_rqst_addr_i; axi_araddr <= axi_araddr_i; axi_arid <= axi_arid_i; assert N_TAG_MANAGERS_W <= ID_WIDTH report "Width of AWID channel is not enough for sending the tag manager id" severity failure; ---------------------------------------------------------------------------------------------------------}}} -- axi fifos wr (to cache) ----------------------------------------------------------------------------------------{{{ wr_fifo_cache_rqst <= wr_fifo_full; wr_fifos: for i in 0 to N_WR_FIFOS-1 generate begin process(clk) begin if rising_edge(clk) then if wr_fifo_push(i) = '1' then wr_fifo(i)(to_integer(wr_fifo_wrAddr(i))) <= axi_rdata_wr_fifo(i); -- wr_fifo(i)(to_integer(wr_fifo_wrAddr(i))) <= axi_rdata_d0(c_wr_fifo_axi_indx(i)); end if; wr_fifo_push(i) <= wr_fifo_push_n(i); wr_fifo_free_i(i) <= wr_fifo_free_n(i); if nrst = '0' then st_wr_fifo(i) <= idle; wr_fifo_set_araddr(i) <= '0'; wr_fifo_rqst_addr_i(i) <= (others=>'0'); else st_wr_fifo(i) <= st_wr_fifo_n(i); wr_fifo_set_araddr(i) <= wr_fifo_set_araddr_n(i); wr_fifo_rqst_addr_i(i) <= wr_fifo_rqst_addr_n(i); end if; end if; end process; process(st_wr_fifo(i), wr_fifo_set_araddr(i), wr_fifo_free_i(i), wr_fifo_go(i), axi_rdAddr(i), axi_set_araddr_ack(i), wr_fifo_rqst_addr_i(i), axi_rvalid(c_wr_fifo_axi_indx(i)), wr_fifo_cache_ack(i), axi_rlast(c_wr_fifo_axi_indx(i)), axi_rid(c_wr_fifo_axi_indx(i)), wr_fifo_rdAddr(i)) begin st_wr_fifo_n(i) <= st_wr_fifo(i); wr_fifo_set_araddr_n(i) <= wr_fifo_set_araddr(i); wr_fifo_free_n(i) <= wr_fifo_free_i(i); wr_fifo_rqst_addr_n(i) <= wr_fifo_rqst_addr_i(i); if wr_fifo_cache_ack(i) = '1' or wr_fifo_rdAddr(i) /= (wr_fifo_rdAddr(i)'reverse_range => '0') then wr_fifo_rqst_addr_n(i) <= wr_fifo_rqst_addr_i(i) + 1; end if; wr_fifo_push_n(i) <= '0'; case st_wr_fifo(i) is when idle => wr_fifo_free_n(i) <= '1'; if wr_fifo_go(i) = '1' then wr_fifo_free_n(i) <= '0'; wr_fifo_set_araddr_n(i) <= '1'; st_wr_fifo_n(i) <= send_address; wr_fifo_rqst_addr_n(i) <= axi_rdAddr(i)(M+L-1 downto 0); -- this signal has priority on wr_fifo_cache_ack when setting wr_fifo_rqst_addr_n end if; when send_address => if axi_set_araddr_ack(i) = '1' then st_wr_fifo_n(i) <= get_data; wr_fifo_set_araddr_n(i) <= '0'; end if; when get_data => if axi_rvalid(c_wr_fifo_axi_indx(i)) = '1' and to_integer(unsigned(axi_rid(c_wr_fifo_axi_indx(i)))) = c_wr_fifo_indx(i) then wr_fifo_push_n(i) <= '1'; if axi_rlast(c_wr_fifo_axi_indx(i)) = '1' then st_wr_fifo_n(i) <= wait_empty; end if; end if; when wait_empty => -- if wr_fifo_cache_ack(i) = '1' then if wr_fifo_rdAddr(i) = (wr_fifo_rdAddr(i)'reverse_range => '1') then -- st_wr_fifo_n(i) <= wait_for_writing_cache; st_wr_fifo_n(i) <= idle; wr_fifo_free_n(i) <= '1'; end if; when wait_for_writing_cache => -- st_wr_fifo_n(i) <= wait2; st_wr_fifo_n(i) <= idle; wr_fifo_free_n(i) <= '1'; when wait2 => wr_fifo_free_n(i) <= '1'; st_wr_fifo_n(i) <= idle; end case; end process; wr_fifo_out: process(wr_fifo(i), wr_fifo_rdAddr(i)) variable indx: unsigned(BURST_W-1 downto 0) := (others=>'0'); begin for j in 0 to CACHE_N_BANKS/GMEM_N_BANK-1 loop if CACHE_N_BANKS_W > GMEM_N_BANK_W then indx(max(CACHE_N_BANKS_W-GMEM_N_BANK_W-1, 0) downto 0) := to_unsigned(j, CACHE_N_BANKS_W-GMEM_N_BANK_W); end if; indx(indx'high downto CACHE_N_BANKS_W-GMEM_N_BANK_W) := wr_fifo_rdAddr(i); wr_fifo_dout(i)((j+1)*GMEM_DATA_W-1 downto j*GMEM_DATA_W) <= wr_fifo(i)(to_integer(indx)); end loop; end process; process(wr_fifo_rdAddr(i), wr_fifo_cache_ack(i), wr_fifo_push(i), wr_fifo_wrAddr(i), wr_fifo_full(i)) begin wr_fifo_rdAddr_n(i) <= wr_fifo_rdAddr(i); wr_fifo_wrAddr_n(i) <= wr_fifo_wrAddr(i); wr_fifo_full_n(i) <= wr_fifo_full(i); if wr_fifo_cache_ack(i) = '1' or wr_fifo_rdAddr(i) /= (wr_fifo_rdAddr(i)'reverse_range => '0') then wr_fifo_rdAddr_n(i) <= wr_fifo_rdAddr(i) + 1; end if; if wr_fifo_push(i) = '1' then wr_fifo_wrAddr_n(i) <= wr_fifo_wrAddr(i) + 1; end if; if wr_fifo_push(i) = '1' and wr_fifo_wrAddr(i) = (wr_fifo_wrAddr(i)'reverse_range => '1') then wr_fifo_full_n(i) <= '1'; elsif wr_fifo_cache_ack(i) = '1' then wr_fifo_full_n(i) <= '0'; end if; end process; process(clk) begin if rising_edge(clk) then if nrst = '0' then wr_fifo_wrAddr(i) <= (others=>'0'); wr_fifo_rdAddr(i) <= (others=>'0'); wr_fifo_full(i) <= '0'; else wr_fifo_rdAddr(i) <= wr_fifo_rdAddr_n(i); wr_fifo_wrAddr(i) <= wr_fifo_wrAddr_n(i); wr_fifo_full(i) <= wr_fifo_full_n(i); end if; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- axi read channels ------------------------------------------------------------------------------------------- {{{ axi_trans_read: process(clk) begin if rising_edge(clk) then axi_set_araddr_ack <= axi_set_araddr_ack_n; cache_dob_d0 <= cache_dob; axi_arid_i <= axi_arid_n; rd_fifo_din_v_d0 <= rd_fifo_din_v; fifo_be_din_d0 <= fifo_be_din; if nrst = '0' then axi_arvalid_i <= (others=>'0'); axi_rready_i <= (others=>'0'); axi_araddr_i <= (others=>(others=>'0')); st_ar <= (others=>idle); else -- read signals axi_arvalid_i <= axi_arvalid_n; axi_rready_i <= axi_rready_n; axi_araddr_i <= axi_araddr_n; st_ar <= st_ar_n; end if; end if; end process; process(st_ar, wr_fifo_set_araddr, axi_arvalid_i, axi_arready, axi_araddr_i, axi_arid_i, axi_rdAddr) begin for i in 0 to N_AXI-1 loop st_ar_n(i) <= st_ar(i); axi_arvalid_n(i) <= axi_arvalid_i(i); axi_araddr_n(i) <= axi_araddr_i(i); axi_araddr_n(i)(2+N-1 downto 0) <= (others=>'0'); axi_arid_n(i) <= axi_arid_i(i); for j in 0 to N_WR_FIFOS_AXI-1 loop axi_set_araddr_ack_n(c_axi_wr_fifos(i, j)) <= '0'; end loop; case st_ar(i) is when idle => for j in 0 to N_WR_FIFOS_AXI-1 loop if wr_fifo_set_araddr(c_axi_wr_fifos(i, j)) = '1' then st_ar_n(i) <= active; axi_arvalid_n(i) <= '1'; axi_araddr_n(i)(GMEM_ADDR_W-1 downto 2+N) <= axi_rdAddr(c_axi_wr_fifos(i, j)); axi_set_araddr_ack_n(c_axi_wr_fifos(i, j)) <= '1'; axi_arid_n(i) <= std_logic_vector(to_unsigned(j, ID_WIDTH)); exit; end if; end loop; when active => if axi_arready(i) = '1' then axi_arvalid_n(i) <= '0'; st_ar_n(i) <= idle; end if; end case; axi_rready_n(i) <= '1'; end loop; end process; ---------------------------------------------------------------------------------------------------------}}} -- axi fifos rd (from cache) ------------------------------------------------------------------------------------{{{ fifos_rd: for i in 0 to N_AXI-1 generate begin fifor_rd_fill: process(clk) variable indx: unsigned(BURST_W+RD_FIFO_N_BURSTS_W-1 downto 0) := (others=>'0'); begin if rising_edge(clk) then if axi_written(i) = '1' or rd_fifo_slice_filled(i) = '0' then axi_wdata(i) <= rd_fifo(i)(to_integer(rd_fifo_rdAddr(i))); axi_wstrb(i) <= fifo_be(i)(to_integer(rd_fifo_rdAddr(i))); axi_wvalid_i(i) <= rd_fifo_nempty(i); axi_wlast(i) <= axi_wlast_p0(i); end if; if rd_fifo_din_v_d0(i) = '1' then for j in 0 to CACHE_N_BANKS/GMEM_N_BANK-1 loop if CACHE_N_BANKS_W > GMEM_N_BANK_W then indx(max(CACHE_N_BANKS_W-GMEM_N_BANK_W-1,0) downto 0) := to_unsigned(j, CACHE_N_BANKS_W-GMEM_N_BANK_W); end if; indx(indx'high downto CACHE_N_BANKS_W-GMEM_N_BANK_W) := rd_fifo_wrAddr(i); rd_fifo(i)(to_integer(indx)) <= cache_dob_d0((j+1)*GMEM_DATA_W-1 downto j*GMEM_DATA_W); fifo_be(i)(to_integer(indx)) <= fifo_be_din_d0((j+1)*GMEM_DATA_W/8-1 downto j*GMEM_DATA_W/8); end loop; end if; end if; end process; rd_fifo_trans: process(clk) variable tmp: std_logic_vector(BURST_W-1 downto 0) := (others=>'0'); begin if rising_edge(clk) then rd_fifo_rqst_addr_i(i) <= rd_fifo_rqst_addr_n(i); axi_writer_free(i) <= axi_writer_free_n(i); rd_fifo_nempty(i) <= rd_fifo_nempty_n(i); axi_writer_ack <= (others=>'0'); for i in 0 to N_TAG_MANAGERS-1 loop if axi_bvalid(c_wr_fifo_axi_indx(i)) = '1' then axi_writer_ack(to_integer(unsigned(axi_bid(c_wr_fifo_axi_indx(i))))) <= '1'; end if; end loop; -- for i in 0 to N_AXI-1 loop -- if axi_bvalid(i) = '1' then -- axi_writer_ack(to_integer(unsigned(axi_bid(i)))) <= '1'; -- end if; -- end loop; if nrst = '0' then st_rd_fifo_data(i) <= idle; rd_fifo_cache_rqst_i(i) <= '0'; rd_fifo_rdAddr(i) <= (others=>'0'); rd_fifo_wrAddr(i) <= (others=>'0'); rd_fifo_n_filled(i) <= (others=>'0'); rd_fifo_n_filled_on_ack(i) <= (others=>'0'); axi_wlast_p0(i) <= '0'; rd_fifo_slice_filled(i) <= '0'; else st_rd_fifo_data(i) <= st_rd_fifo_data_n(i); rd_fifo_cache_rqst_i(i) <= rd_fifo_cache_rqst_n(i); rd_fifo_rdAddr(i) <= rd_fifo_rdAddr_n(i); rd_fifo_wrAddr(i) <= rd_fifo_wrAddr_n(i); rd_fifo_n_filled(i) <= rd_fifo_n_filled_n(i); rd_fifo_n_filled_on_ack(i) <= rd_fifo_n_filled_on_ack_n(i); if axi_written(i) = '1' or rd_fifo_slice_filled(i) = '0' then axi_wlast_p0(i) <= '0'; if rd_fifo_rdAddr(i)(BURST_W-1 downto 1) = (1 to BURST_W-1 =>'1') and rd_fifo_rdAddr(i)(0) = '0' and rd_fifo_pop(i) = '1' then axi_wlast_p0(i) <= '1'; end if; end if; -- if axi_wready(i) = '1' and rd_fifo_nempty(i) = '1' then -- axi_wlast_p0(i) <= '0'; -- end if; if axi_written(i) = '1' and rd_fifo_nempty(i) = '0' then rd_fifo_slice_filled(i) <= '0'; end if; if rd_fifo_slice_filled(i) = '0' and rd_fifo_nempty(i) = '1' then rd_fifo_slice_filled(i) <= '1'; end if; end if; end if; end process; rd_fifo_proc: process(rd_fifo_wrAddr(i), rd_fifo_rdAddr(i), rd_fifo_pop(i), rd_fifo_din_v_d0(i), rd_fifo_n_filled(i), rd_fifo_n_filled_on_ack(i), rd_fifo_cache_ack(i)) begin rd_fifo_rdAddr_n(i) <= rd_fifo_rdAddr(i); rd_fifo_wrAddr_n(i) <= rd_fifo_wrAddr(i); if rd_fifo_pop(i) = '1' then rd_fifo_rdAddr_n(i) <= rd_fifo_rdAddr(i) + 1; end if; if rd_fifo_din_v_d0(i) = '1' then rd_fifo_wrAddr_n(i) <= rd_fifo_wrAddr(i) + 1; end if; if rd_fifo_pop(i) = '0' and rd_fifo_din_v_d0(i) = '0' then rd_fifo_n_filled_n(i) <= rd_fifo_n_filled(i); elsif rd_fifo_pop(i) = '1' and rd_fifo_din_v_d0(i) = '0' then rd_fifo_n_filled_n(i) <= rd_fifo_n_filled(i) - 1; elsif rd_fifo_pop(i) = '1' and rd_fifo_din_v_d0(i) = '1' then rd_fifo_n_filled_n(i) <= rd_fifo_n_filled(i) - 1 + CACHE_N_BANKS/GMEM_N_BANK; else rd_fifo_n_filled_n(i) <= rd_fifo_n_filled(i) + CACHE_N_BANKS/GMEM_N_BANK; end if; -- consider the rd_fifo_cache_ack as the push signal for not overfilling the fifo if rd_fifo_pop(i) = '0' and rd_fifo_cache_ack(i) = '0' then rd_fifo_n_filled_on_ack_n(i) <= rd_fifo_n_filled_on_ack(i); elsif rd_fifo_pop(i) = '1' and rd_fifo_cache_ack(i) = '0' then rd_fifo_n_filled_on_ack_n(i) <= rd_fifo_n_filled_on_ack(i) - 1; elsif rd_fifo_pop(i) = '1' and rd_fifo_cache_ack(i) = '1' then rd_fifo_n_filled_on_ack_n(i) <= rd_fifo_n_filled_on_ack(i) - 1 + (2**BURST_WORDS_W)/GMEM_N_BANK; else rd_fifo_n_filled_on_ack_n(i) <= rd_fifo_n_filled_on_ack(i) + 2**(BURST_WORDS_W)/GMEM_N_BANK; end if; end process; rd_fifo_nempty_n(i) <= '0' when rd_fifo_n_filled_n(i) = (rd_fifo_n_filled_n(i)'reverse_range=>'0') else '1'; axi_written(i) <= axi_wready(i) and axi_wvalid_i(i); rd_fifo_pop(i) <= rd_fifo_nempty(i) and (axi_written(i) or (not rd_fifo_slice_filled(i))); process(st_rd_fifo_data(i), axi_writer_go(i), rd_fifo_rqst_addr_i(i), rd_fifo_cache_ack(i), axi_wrAddr(i)(M+L-1 downto 0), rd_fifo_cache_rqst_i(i), awaddr_fifo_full(i), rd_fifo_n_filled_on_ack_n(i)) --, axi_awvalid_i(i), axi_awready(i)) begin st_rd_fifo_data_n(i) <= st_rd_fifo_data(i); rd_fifo_rqst_addr_n(i) <= rd_fifo_rqst_addr_i(i); rd_fifo_cache_rqst_n(i) <= rd_fifo_cache_rqst_i(i); axi_writer_free_n(i) <= not awaddr_fifo_full(i); case st_rd_fifo_data(i) is when idle => if axi_writer_go(i) = '1' then st_rd_fifo_data_n(i) <= fill_fifo; rd_fifo_rqst_addr_n(i) <= axi_wrAddr(i)(M+L-1 downto 0); rd_fifo_cache_rqst_n(i) <= '1'; axi_writer_free_n(i) <= '0'; end if; when fill_fifo => axi_writer_free_n(i) <= '0'; if rd_fifo_cache_ack(i) = '1' then rd_fifo_cache_rqst_n(i) <= '0'; if rd_fifo_n_filled_on_ack_n(i)(rd_fifo_n_filled_on_ack_n(i)'high downto BURST_W) /= (0 to rd_fifo_n_filled_on_ack_n(i)'high-BURST_W =>'1') then axi_writer_free_n(i) <= not awaddr_fifo_full(i); st_rd_fifo_data_n(i) <= idle; else st_rd_fifo_data_n(i) <= wait_w_channel; end if; end if; when wait_w_channel => axi_writer_free_n(i) <= '0'; if rd_fifo_n_filled_on_ack_n(i)(rd_fifo_n_filled_on_ack_n(i)'high downto BURST_W) /= (0 to rd_fifo_n_filled_on_ack_n(i)'high-BURST_W =>'1') then axi_writer_free_n(i) <= not awaddr_fifo_full(i); st_rd_fifo_data_n(i) <= idle; end if; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- awaddr fifo -------------------------------------------------------------------------------------------{{{ awaddr_fifos: for i in 0 to N_AXI-1 generate begin awaddr_fifo_trans: process(clk) begin if rising_edge(clk) then if axi_writer_go(i) = '1' then awaddr_fifo(i)(to_integer(awaddr_fifo_wrAddr(i)))(GMEM_ADDR_W-1 downto 2+N) <= axi_wrAddr(i); awaddr_fifo(i)(to_integer(awaddr_fifo_wrAddr(i)))(2+N-1 downto 0) <= (others=>'0'); awid_fifo(i)(to_integer(awaddr_fifo_wrAddr(i))) <= axi_writer_id; end if; for i in 0 to N_WR_FIFOS-1 loop axi_rdata_wr_fifo(i) <= axi_rdata(c_wr_fifo_axi_indx(i)); end loop; -- axi_rdata_d0(i) <= axi_rdata(i); if nrst = '0' then awaddr_fifo_wrAddr(i) <= (others=>'0'); awaddr_fifo_rdAddr(i) <= (others=>'0'); awaddr_fifo_full(i) <= '0'; awaddr_fifo_nempty(i) <= '0'; else awaddr_fifo_nempty(i) <= awaddr_fifo_nempty_n(i); awaddr_fifo_full(i) <= awaddr_fifo_full_n(i); awaddr_fifo_wrAddr(i) <= awaddr_fifo_wrAddr_n(i); awaddr_fifo_rdAddr(i) <= awaddr_fifo_rdAddr_n(i); end if; end if; end process; axi_awaddr(i) <= awaddr_fifo(i)(to_integer(awaddr_fifo_rdAddr(i))); axi_awid(i)(N_TAG_MANAGERS_W-1 downto 0) <= awid_fifo(i)(to_integer(awaddr_fifo_rdAddr(i))); axi_awid(i)(ID_WIDTH-1 downto N_TAG_MANAGERS_W) <= (others=>'0'); awaddr_fifo_proc: process(awaddr_fifo_wrAddr(i), axi_writer_go(i), awaddr_fifo_rdAddr(i), axi_awready(i), axi_awvalid_i(i)) begin awaddr_fifo_wrAddr_n(i) <= awaddr_fifo_wrAddr(i); awaddr_fifo_rdAddr_n(i) <= awaddr_fifo_rdAddr(i); if axi_writer_go(i) = '1' then awaddr_fifo_wrAddr_n(i) <= awaddr_fifo_wrAddr(i) + 1; end if; if axi_awvalid_i(i) = '1' and axi_awready(i) = '1' then awaddr_fifo_rdAddr_n(i) <= awaddr_fifo_rdAddr(i) + 1; end if; end process; axi_awvalid_i(i) <= awaddr_fifo_nempty(i); awaddr_fifo_proc1: process(axi_writer_go(i), awaddr_fifo_full(i), awaddr_fifo_nempty(i), awaddr_fifo_wrAddr(i), awaddr_fifo_wrAddr_n(i), awaddr_fifo_rdAddr(i), awaddr_fifo_rdAddr_n(i), axi_awvalid_i(i), axi_awready(i)) begin awaddr_fifo_full_n(i) <= awaddr_fifo_full(i); awaddr_fifo_nempty_n(i) <= awaddr_fifo_nempty(i); if axi_writer_go(i) = '1' and (axi_awvalid_i(i) = '0' or axi_awready(i) = '0') and awaddr_fifo_wrAddr_n(i) = awaddr_fifo_rdAddr(i) then awaddr_fifo_full_n(i) <= '1'; elsif axi_writer_go(i) = '0' and axi_awvalid_i(i) = '1' and axi_awready(i) = '1' then awaddr_fifo_full_n(i) <= '0'; end if; if axi_writer_go(i) = '1' and (axi_awvalid_i(i) = '0' or axi_awready(i) = '0') then awaddr_fifo_nempty_n(i) <= '1'; elsif axi_writer_go(i) = '0' and axi_awvalid_i(i) = '1' and axi_awready(i) = '1' and awaddr_fifo_wrAddr(i) = awaddr_fifo_rdAddr_n(i) then awaddr_fifo_nempty_n(i) <= '0'; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------------}}} end architecture;

gpl-3.0

87178071a3abe437755af29f3d192830

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/VOICE_ROM_INIT_funcsim.vhdl

-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014 -- Date : Wed Sep 10 03:37:56 2014 -- Host : Dtysky running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- d:/spira_heaven/0-myworks/ld3320_axi/ld3320_axi_1.0/src/VOICE_ROM_INIT/VOICE_ROM_INIT_funcsim.vhdl -- Design : VOICE_ROM_INIT -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT_blk_mem_gen_prim_wrapper is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper"; end VOICE_ROM_INIT_blk_mem_gen_prim_wrapper; architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_prim_wrapper is signal \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "SDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 36, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 0, WRITE_WIDTH_B => 36 ) port map ( ADDRARDADDR(13) => '0', ADDRARDADDR(12) => '0', ADDRARDADDR(11) => '0', ADDRARDADDR(10 downto 5) => addrb(5 downto 0), ADDRARDADDR(4) => '0', ADDRARDADDR(3) => '0', ADDRARDADDR(2) => '0', ADDRARDADDR(1) => '0', ADDRARDADDR(0) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10 downto 5) => addra(5 downto 0), ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CLKARDCLK => clkb, CLKBWRCLK => clka, DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11 downto 8) => dina(7 downto 4), DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3 downto 0) => dina(3 downto 0), DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11 downto 8) => dina(15 downto 12), DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3 downto 0) => dina(11 downto 8), DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(15) => \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(14) => \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(13) => \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(12) => \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(11 downto 8) => doutb(7 downto 4), DOADO(7) => \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(6) => \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(5) => \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(4) => \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(3 downto 0) => doutb(3 downto 0), DOBDO(15) => \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(14) => \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(13) => \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(12) => \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(11 downto 8) => doutb(15 downto 12), DOBDO(7) => \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(6) => \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(5) => \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(4) => \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(3 downto 0) => doutb(11 downto 8), DOPADOP(1) => \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOPADOP(0) => \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOPBDOP(1) => \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOPBDOP(0) => \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, ENARDEN => '1', ENBWREN => wea(0), REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => '0', WEA(0) => '0', WEBWE(3) => '1', WEBWE(2) => '1', WEBWE(1) => '1', WEBWE(0) => '1' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT_blk_mem_gen_prim_width is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end VOICE_ROM_INIT_blk_mem_gen_prim_width; architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_prim_width is begin \prim_noinit.ram\: entity work.VOICE_ROM_INIT_blk_mem_gen_prim_wrapper port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT_blk_mem_gen_generic_cstr is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end VOICE_ROM_INIT_blk_mem_gen_generic_cstr; architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.VOICE_ROM_INIT_blk_mem_gen_prim_width port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT_blk_mem_gen_top is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_top : entity is "blk_mem_gen_top"; end VOICE_ROM_INIT_blk_mem_gen_top; architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_top is begin \valid.cstr\: entity work.VOICE_ROM_INIT_blk_mem_gen_generic_cstr port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT_blk_mem_gen_v8_2_synth is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth"; end VOICE_ROM_INIT_blk_mem_gen_v8_2_synth; architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_v8_2_synth is begin \gnativebmg.native_blk_mem_gen\: entity work.VOICE_ROM_INIT_blk_mem_gen_top port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 15 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 5 downto 0 ); sleep : in STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 5 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2"; attribute C_FAMILY : string; attribute C_FAMILY of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "zynq"; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "zynq"; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "./"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "NONE"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 4; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 9; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "no_coe_file_loaded"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "VOICE_ROM_INIT.mem"; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "CE"; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64; attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 6; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "CE"; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_INITB_VAL : string; attribute C_INITB_VAL of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 6; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "ALL"; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "1"; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 3.01735 mW"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "yes"; end \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\; architecture STRUCTURE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; douta(15) <= \<const0>\; douta(14) <= \<const0>\; douta(13) <= \<const0>\; douta(12) <= \<const0>\; douta(11) <= \<const0>\; douta(10) <= \<const0>\; douta(9) <= \<const0>\; douta(8) <= \<const0>\; douta(7) <= \<const0>\; douta(6) <= \<const0>\; douta(5) <= \<const0>\; douta(4) <= \<const0>\; douta(3) <= \<const0>\; douta(2) <= \<const0>\; douta(1) <= \<const0>\; douta(0) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.VOICE_ROM_INIT_blk_mem_gen_v8_2_synth port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT is port ( clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of VOICE_ROM_INIT : entity is true; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of VOICE_ROM_INIT : entity is "yes"; attribute x_core_info : string; attribute x_core_info of VOICE_ROM_INIT : entity is "blk_mem_gen_v8_2,Vivado 2014.2"; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of VOICE_ROM_INIT : entity is "VOICE_ROM_INIT,blk_mem_gen_v8_2,{}"; attribute core_generation_info : string; attribute core_generation_info of VOICE_ROM_INIT : entity is "VOICE_ROM_INIT,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=VOICE_ROM_INIT.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=64,C_READ_DEPTH_A=64,C_ADDRA_WIDTH=6,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=64,C_READ_DEPTH_B=64,C_ADDRB_WIDTH=6,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.01735 mW}"; end VOICE_ROM_INIT; architecture STRUCTURE of VOICE_ROM_INIT is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 6; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 6; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "0"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.01735 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 0; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "VOICE_ROM_INIT.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 0; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 1; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 64; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 64; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 16; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 16; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 64; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 64; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 16; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 16; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.\VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dbiterr => NLW_U0_dbiterr_UNCONNECTED, dina(15 downto 0) => dina(15 downto 0), dinb(15) => '0', dinb(14) => '0', dinb(13) => '0', dinb(12) => '0', dinb(11) => '0', dinb(10) => '0', dinb(9) => '0', dinb(8) => '0', dinb(7) => '0', dinb(6) => '0', dinb(5) => '0', dinb(4) => '0', dinb(3) => '0', dinb(2) => '0', dinb(1) => '0', dinb(0) => '0', douta(15 downto 0) => NLW_U0_douta_UNCONNECTED(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), eccpipece => '0', ena => '0', enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(5 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(5 downto 0), regcea => '0', regceb => '0', rsta => '0', rstb => '0', s_aclk => '0', s_aresetn => '0', s_axi_araddr(31) => '0', s_axi_araddr(30) => '0', s_axi_araddr(29) => '0', s_axi_araddr(28) => '0', s_axi_araddr(27) => '0', s_axi_araddr(26) => '0', s_axi_araddr(25) => '0', s_axi_araddr(24) => '0', s_axi_araddr(23) => '0', s_axi_araddr(22) => '0', s_axi_araddr(21) => '0', s_axi_araddr(20) => '0', s_axi_araddr(19) => '0', s_axi_araddr(18) => '0', s_axi_araddr(17) => '0', s_axi_araddr(16) => '0', s_axi_araddr(15) => '0', s_axi_araddr(14) => '0', s_axi_araddr(13) => '0', s_axi_araddr(12) => '0', s_axi_araddr(11) => '0', s_axi_araddr(10) => '0', s_axi_araddr(9) => '0', s_axi_araddr(8) => '0', s_axi_araddr(7) => '0', s_axi_araddr(6) => '0', s_axi_araddr(5) => '0', s_axi_araddr(4) => '0', s_axi_araddr(3) => '0', s_axi_araddr(2) => '0', s_axi_araddr(1) => '0', s_axi_araddr(0) => '0', s_axi_arburst(1) => '0', s_axi_arburst(0) => '0', s_axi_arid(3) => '0', s_axi_arid(2) => '0', s_axi_arid(1) => '0', s_axi_arid(0) => '0', s_axi_arlen(7) => '0', s_axi_arlen(6) => '0', s_axi_arlen(5) => '0', s_axi_arlen(4) => '0', s_axi_arlen(3) => '0', s_axi_arlen(2) => '0', s_axi_arlen(1) => '0', s_axi_arlen(0) => '0', s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2) => '0', s_axi_arsize(1) => '0', s_axi_arsize(0) => '0', s_axi_arvalid => '0', s_axi_awaddr(31) => '0', s_axi_awaddr(30) => '0', s_axi_awaddr(29) => '0', s_axi_awaddr(28) => '0', s_axi_awaddr(27) => '0', s_axi_awaddr(26) => '0', s_axi_awaddr(25) => '0', s_axi_awaddr(24) => '0', s_axi_awaddr(23) => '0', s_axi_awaddr(22) => '0', s_axi_awaddr(21) => '0', s_axi_awaddr(20) => '0', s_axi_awaddr(19) => '0', s_axi_awaddr(18) => '0', s_axi_awaddr(17) => '0', s_axi_awaddr(16) => '0', s_axi_awaddr(15) => '0', s_axi_awaddr(14) => '0', s_axi_awaddr(13) => '0', s_axi_awaddr(12) => '0', s_axi_awaddr(11) => '0', s_axi_awaddr(10) => '0', s_axi_awaddr(9) => '0', s_axi_awaddr(8) => '0', s_axi_awaddr(7) => '0', s_axi_awaddr(6) => '0', s_axi_awaddr(5) => '0', s_axi_awaddr(4) => '0', s_axi_awaddr(3) => '0', s_axi_awaddr(2) => '0', s_axi_awaddr(1) => '0', s_axi_awaddr(0) => '0', s_axi_awburst(1) => '0', s_axi_awburst(0) => '0', s_axi_awid(3) => '0', s_axi_awid(2) => '0', s_axi_awid(1) => '0', s_axi_awid(0) => '0', s_axi_awlen(7) => '0', s_axi_awlen(6) => '0', s_axi_awlen(5) => '0', s_axi_awlen(4) => '0', s_axi_awlen(3) => '0', s_axi_awlen(2) => '0', s_axi_awlen(1) => '0', s_axi_awlen(0) => '0', s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2) => '0', s_axi_awsize(1) => '0', s_axi_awsize(0) => '0', s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(5 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(5 downto 0), s_axi_rdata(15 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(15 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(15) => '0', s_axi_wdata(14) => '0', s_axi_wdata(13) => '0', s_axi_wdata(12) => '0', s_axi_wdata(11) => '0', s_axi_wdata(10) => '0', s_axi_wdata(9) => '0', s_axi_wdata(8) => '0', s_axi_wdata(7) => '0', s_axi_wdata(6) => '0', s_axi_wdata(5) => '0', s_axi_wdata(4) => '0', s_axi_wdata(3) => '0', s_axi_wdata(2) => '0', s_axi_wdata(1) => '0', s_axi_wdata(0) => '0', s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;

mit

19781ae9dd3483a4f1d470bc0e8cdbb1

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fslt_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

038e33b4409c1faf505e6e9437baf45a

preusser/q27

src/vhdl/queens/queens_uart.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity queens_uart is generic ( -- Problem Size N : positive; L : positive; -- Design Spec SOLVERS : positive; COUNT_CYCLES : boolean; -- Communication Parameters CLK_FREQ : positive; BAUDRATE : positive; SENTINEL : std_logic_vector(7 downto 0) ); port ( -- Global Control clk : in std_logic; rst : in std_logic; -- UART Interface rx : in std_logic; tx : out std_logic; -- Activity avail : out std_logic ); end queens_uart; library IEEE; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.fifo.all; use PoC.uart.all; architecture rtl of queens_uart is -- Bit Length of Pre-Placement constant PRE_BITS : positive := 4*L*log2ceil(N)-1; constant PRE_BYTES : positive := (PRE_BITS+7)/8; -- UART-to-Unframe Interface signal rx_dat : std_logic_vector(7 downto 0); signal rx_stb : std_logic; -- Unframe-to-Chain Interface signal piful : std_logic; signal pidat : byte; signal pieof : std_logic; signal piput : std_logic; -- Chain-to-Enframe Interface signal sovld : std_logic; signal sodat : byte; signal soeof : std_logic; signal sogot : std_logic; -- Enframe-to-UART Interface signal tx_dat : std_logic_vector(7 downto 0); signal tx_ful : std_logic; signal tx_put : std_logic; begin ----------------------------------------------------------------------------- -- UART -> Byte Interface blkUART: block signal bclk_x8 : std_logic; signal bclk_x1 : std_logic; begin -- Bit Clock Generation bclk_gen_x8: entity PoC.arith_counter_free generic map ( DIVIDER => CLK_FREQ/(8*BAUDRATE) ) port map ( clk => clk, rst => '0', inc => '1', stb => bclk_x8 ); bclk_gen_x1: entity PoC.arith_counter_free generic map ( DIVIDER => 8 ) port map ( clk => clk, rst => '0', inc => bclk_x8, stb => bclk_x1 ); -- Receive Bytes uart_rx_2 : uart_rx port map ( clk => clk, rst => rst, bclk_x8 => bclk_x8, rx => rx, stb => rx_stb, do => rx_dat ); -- Transmit Byte uart_tx_1 : uart_tx port map ( clk => clk, rst => rst, bclk => bclk_x1, put => tx_put, di => tx_dat, ful => tx_ful, tx => tx ); end block blkUART; blkUnframe: block -- Input Glue FIFO -> Unframe signal glue_vld : std_logic; signal glue_dat : std_logic_vector(7 downto 0); signal glue_got : std_logic; -- Unframe -> Input Buffer signal odat : std_logic_vector(7 downto 0); signal oeof : std_logic; signal oful : std_logic; signal oput : std_logic; signal ocommit : std_logic; signal orollback : std_logic; signal pvld : std_logic; begin glue: fifo_glue generic map ( D_BITS => 8 ) port map ( clk => clk, rst => rst, put => rx_stb, di => rx_dat, ful => open, vld => glue_vld, do => glue_dat, got => glue_got ); unframe_i: entity work.unframe generic map ( SENTINEL => SENTINEL, PAY_LEN => PRE_BYTES ) port map ( clk => clk, rst => rst, rx_dat => glue_dat, rx_vld => glue_vld, rx_got => glue_got, odat => odat, oeof => oeof, oful => oful, oput => oput, ocommit => ocommit, orollback => orollback ); buf: fifo_cc_got_tempput generic map ( MIN_DEPTH => 5*(SOLVERS+5), D_BITS => 9 ) port map ( clk => clk, rst => rst, put => oput, din(8) => oeof, din(7 downto 0) => odat, full => oful, commit => ocommit, rollback => orollback, got => piput, dout(8) => pieof, dout(7 downto 0) => pidat, valid => pvld ); piput <= pvld and not piful; avail <= pvld; end block blkUnframe; chain: entity work.queens_chain generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES ) port map ( clk => clk, rst => rst, piful => piful, pidat => pidat, pieof => pieof, piput => piput, poful => '1', podat => open, poeof => open, poput => open, sivld => '0', sidat => (others => '-'), sieof => '-', sigot => open, sovld => sovld, sodat => sodat, soeof => soeof, sogot => sogot ); blkEnframe: block signal sful : std_logic; signal ogot : std_logic; signal oeof : std_logic; signal odat : byte; signal ovld : std_logic; begin sogot <= sovld and not sful; buf: fifo_cc_got generic map ( MIN_DEPTH => 5*(SOLVERS+5), D_BITS => 9, STATE_REG => true ) port map ( clk => clk, rst => rst, put => sogot, din(8) => soeof, din(7 downto 0) => sodat, full => sful, got => ogot, dout(8) => oeof, dout(7 downto 0) => odat, valid => ovld ); enframe_i: entity work.enframe generic map ( SENTINEL => SENTINEL ) port map ( clk => clk, rst => rst, ivld => ovld, idat => odat, ieof => oeof, igot => ogot, tx_ful => tx_ful, tx_put => tx_put, tx_dat => tx_dat ); end block blkEnframe; end rtl;

agpl-3.0

72e5d8e2d553987d631dc72cd036b5e1

malkadi/FGPU

RTL/gmem_cntrl.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; use ieee.std_logic_textio.all; use std.textio.all; ---------------------------------------------------------------------------------------------------------}}} entity gmem_cntrl is -- {{{ port( clk : in std_logic; start_kernel : in std_logic; clean_cache : in std_logic; WGsDispatched : in std_logic; CUs_gmem_idle : in std_logic; finish_exec : out std_logic := '0'; cu_valid : in std_logic_vector(N_CU-1 downto 0); cu_ready : out std_logic_vector(N_CU-1 downto 0) := (others=>'0'); cu_we : in be_array(N_CU-1 downto 0); cu_rnw, cu_atomic : in std_logic_vector(N_CU-1 downto 0); cu_atomic_sgntr : in atomic_sgntr_array(N_CU-1 downto 0); cu_rqst_addr : in GMEM_WORD_ADDR_ARRAY(N_CU-1 downto 0); cu_wrData : in SLV32_ARRAY(N_CU-1 downto 0); rdAck : out std_logic_vector(N_CU-1 downto 0) := (others=>'0'); rdAddr : out unsigned(GMEM_WORD_ADDR_W-1-CACHE_N_BANKS_W downto 0) := (others=>'0'); rdData : out std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0) := (others => '0'); atomic_rdData : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); atomic_rdData_v : out std_logic_vector(N_CU-1 downto 0) := (others=>'0'); atomic_sgntr : out std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); -- AXI Interface signals {{{ --Read address channel axi_araddr : out GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_arvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_arready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_arid : out id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- Read data channel axi_rdata : in gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_rlast : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rvalid : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rready : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rid : in id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- write address channel axi_awaddr : out GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_awvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_awready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_awid : out id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- write data channel axi_wdata : out gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_wstrb : out gmem_be_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_wlast : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_wvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_wready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); -- write response channel axi_bvalid : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_bready : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_bid : in id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- }}} nrst : in std_logic ); end gmem_cntrl; --}}} architecture Behavioral of gmem_cntrl is -- internal signals {{{ signal cu_ready_i : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal axi_wvalid_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal rdData_i : std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0) := (others => '0'); signal finish_exec_i : std_logic := '0'; -- }}} -- axi signals {{{ signal axi_rdAddr : gmem_addr_array_no_bank(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_go : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); -- attribute mark_debug of wr_fifo_go : signal is "true"; signal axi_writer_go : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_free : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_writer_free : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_wrAddr : gmem_addr_array_no_bank(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_writer_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal axi_writer_id : std_logic_vector(N_TAG_MANAGERS_W-1 downto 0) := (others=>'0'); -- attribute mark_debug of axi_writer_id : signal is "true"; --}}} -- doc part (obselete) -------------------------------------------------------------------------------{{{ -- rmem = request mem -- rmem_blk = request memory block. There are GMEM_N_BANKS of rmem_block -- mir_blk = request memory mirror of a block. -- -- byte count : |7 6 5 |4 |3 2 1 0 | -- |_____|______________________|____|____|________________________________| | -- | cnt | TAG | we | re | Data to write | | -- _ _ |_____|______________________|____|____|________________________________| _ | -- | | | | TAG |____|____|________________________________| | | -- | rqst | | |¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|____|____|________________________________| rqst line | 2^L | -- | entry | | | XXX |____|____|________________________________| | | -- | |_ |_____|______________________|____|____|________________________________| _| | * 2^N rmem_block -- 2^M | | | | | | | | -- | | | | | | | | -- : : : : : : : : -- : : : : : : : : -- | | | | | | | | -- |_ |_____|______________________|____|____|________________________________| | -- -- 2^N = GMEM_N_BANKS (default=2^1) -- 2^M = number of rqst entries (default=2^5) -- 2^N = number of rqst lines/entry = burst length (default=2^4) -- TAG should be identical in all instances of request memory blocks -- cnt is the number of set bits either in re or we. It's limited in bit width and needs to sturated while incrementing. ------------------------------------------------------------------------------------------------}}} -- functions ------------------------------------------------------------------ {{{ function distribute_rcvs_on_CUs (n_rcvs: integer; n_cus: integer) return nat_array is variable res: nat_array(n_rcvs-1 downto 0) := (others=>0); begin for i in 0 to n_rcvs-1 loop for k in 0 to n_cus-1 loop if i < (k+1)*(n_rcvs/n_cus) and i >= k*(n_rcvs/n_cus) then res(i) := k; exit; end if; end loop; end loop; return res; end; function distribute_rcvs_on_gmem_banks (n_rcvs: natural; n_banks: natural) return nat_array is variable res: nat_array(n_rcvs-1 downto 0) := (others=>0); begin for i in 0 to n_rcvs-1 loop for k in 0 to n_banks-1 loop for j in 0 to (n_rcvs/n_banks)-1 loop if i = k + j*n_banks then res(i) := k; exit; end if; end loop; end loop; end loop; return res; end function distribute_rcvs_on_gmem_banks; -------------------------------------------------------------------------------------}}} -- Constants & types -------------------------------------------------------------------------------{{{ CONSTANT c_rcv_cu_indx : nat_array(N_RECEIVERS-1 downto 0) := distribute_rcvs_on_CUs(N_RECEIVERS, N_CU); CONSTANT c_rcv_bank_indx : nat_array(N_RECEIVERS-1 downto 0) := distribute_rcvs_on_gmem_banks(N_RECEIVERS, N_RD_PORTS); type cache_bank is array(natural range <>) of unsigned(DATA_W-1 downto 0); type cache_type is array(natural range <>) of cache_bank(2**(L+M)-1 downto 0); ------------------------------------------------------------------------------------------------}}} -- CUs' interface{{{ signal cu_ready_n : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal cuIndx_msb : std_logic := '0'; signal cu_atomic_ack_p0 : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); -- }}} -- receivers signals {{{ type st_rcv_type is ( get_addr, get_read_tag_ticket, wait_read_tag, check_tag_rd, check_tag_wr, alloc_tag, clean, request_write_addr, request_write_data, write_cache, read_cache, requesting_atomic); type st_rcv_array is array (N_RECEIVERS-1 downto 0) of st_rcv_type; signal st_rcv, st_rcv_n : st_rcv_array := (others=>get_addr); signal rcv_idle, rcv_idle_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_all_idle : std_logic := '0'; signal rcv_gmem_addr, rcv_gmem_addr_n : gmem_word_addr_array(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); signal rcv_gmem_data, rcv_gmem_data_n : SLV32_ARRAY(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); signal rcv_rnw, rcv_rnw_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_atomic, rcv_atomic_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_be, rcv_be_n : be_array(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); signal rcv_atomic_sgntr : atomic_sgntr_array(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); signal rcv_atomic_sgntr_n : atomic_sgntr_array(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); signal rcv_go, rcv_go_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_must_read : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_read_tag, rcv_read_tag_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_atomic_rqst : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_atomic_rqst_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_atomic_ack : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_atomic_performed : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal atomic_sgntr_p0 : std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); alias rcv_atomic_type : be_array(N_RECEIVERS-1 downto 0) is rcv_be; signal rcv_read_tag_ack : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_alloc_tag, rcv_alloc_tag_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal cu_rqst_addr_d0 : gmem_word_addr_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_wrData_d0 : SLV32_ARRAY(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_rnw_d0, cu_atomic_d0 : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal cu_we_d0 : be_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_atomic_sgntr_d0 : atomic_sgntr_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal rcv_tag_written, rcv_tag_updated : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_page_validated : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_perform_read : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_perform_read_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_request_write_addr : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_request_write_addr_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); attribute max_fanout of rcv_request_write_addr : signal is 50; signal rcv_request_write_data : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_request_write_data_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_tag_compared : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_wait_1st_cycle : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_wait_1st_cycle_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); -- }}} -- tag signals {{{ signal rdData_tag : tag_array(N_RD_PORTS-1 downto 0) := (others=>(others=>'0')); signal rdData_tag_v : std_logic_vector(N_RD_PORTS-1 downto 0) := (others=>'0'); signal rdData_page_v, rdData_page_v_d0 : std_logic_vector(N_RD_PORTS-1 downto 0) := (others=>'0'); -- }}} -- cache signals {{{ signal cache_mem : cache_type(2**N-1 downto 0) := (others=>(others=>(others=>'0'))); signal cache_wea, cache_wea_n : std_logic_vector((2**N)*DATA_W/8-1 downto 0) := (others=>'0'); signal cache_we, cache_we_n : std_logic := '0'; signal cache_addra, cache_addra_n : unsigned(M+L-1 downto 0) := (others=>'0'); signal cache_read_v, cache_read_v_p0 : std_logic := '0'; signal rcv_rd_done, rcv_rd_done_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); attribute max_fanout of cache_read_v : signal is 100; signal cache_read_v_p0_n : std_logic := '0'; signal cache_read_v_d0 : std_logic := '0'; signal cache_last_rdAddr : unsigned(M+L-1 downto 0) := (others=>'0'); -- }}} -- responder signals {{{ signal rcv_to_read, rcv_to_read_n : integer range 0 to N_RECEIVERS-1 := 0; signal rdAddr_p0, rdAddr_p1 : unsigned(GMEM_WORD_ADDR_W-N-1 downto 0) := (others=>'0'); signal cache_wrData : std_logic_vector((2**N)*DATA_W-1 downto 0) := (others=>'0'); constant c_n_priority_classes_w : natural := 2; type rcv_priority_vec is array (natural range <>) of unsigned(RCV_PRIORITY_W-1 downto 0); signal rcv_priority, rcv_priority_n : rcv_priority_vec(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); constant c_served_vec_len : natural := 2; -- max(CACHE_N_BANKS-1, 2); type served_vec is array (natural range <>) of std_logic_vector(c_served_vec_len-1 downto 0); signal cu_served : served_vec(N_CU-1 downto 0) := (others=>(others=>'0')); signal write_phase : unsigned(WRITE_PHASE_W-1 downto 0) := (others=>'0'); attribute max_fanout of write_phase : signal is 8; signal cu_served_n : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); type rcv_to_read_priority_vec is array (natural range <>) of integer range 0 to N_RECEIVERS-1; signal rcv_to_read_pri : rcv_to_read_priority_vec(2**c_n_priority_classes_w-1 downto 0) := (others=>0); signal rcv_to_read_pri_n : rcv_to_read_priority_vec(2**c_n_priority_classes_w-1 downto 0) := (others=>0); signal rcv_to_write_pri : rcv_to_read_priority_vec(2**c_n_priority_classes_w-1 downto 0) := (others=>0); signal rcv_to_write_pri_n : rcv_to_read_priority_vec(2**c_n_priority_classes_w-1 downto 0) := (others=>0); signal rcv_to_read_pri_v_n : std_logic_vector(2**c_n_priority_classes_w-1 downto 0) := (others=>'0'); signal rcv_to_read_pri_v : std_logic_vector(2**c_n_priority_classes_w-1 downto 0) := (others=>'0'); signal rcv_to_write_pri_v_n : std_logic_vector(2**c_n_priority_classes_w-1 downto 0) := (others=>'0'); signal rcv_to_write_pri_v : std_logic_vector(2**c_n_priority_classes_w-1 downto 0) := (others=>'0'); --}}} -- write pipeline {{{ signal rcv_to_write, rcv_to_write_n : natural range 0 to N_RECEIVERS-1 := 0; attribute max_fanout of rcv_to_write : signal is 60; signal rcv_write_in_pipeline : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_write_in_pipeline_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal write_addr : cache_addr_array(3 downto 0) := (others=>(others=>'0')); signal rcv_will_write, rcv_will_write_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_will_write_d0 : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal write_word : std_logic_vector(DATA_W*2**N-1 downto 0) := (others=>'0'); type write_word_rcv_indx_type is array (natural range <>) of integer range 0 to N_RECEIVERS-1; signal write_word_rcv_indx : write_word_rcv_indx_type(DATA_W/8*2**N-1 downto 0) := (others=>0); signal write_word_rcv_indx_n : write_word_rcv_indx_type(DATA_W/8*2**N-1 downto 0) := (others=>0); signal write_be_p0 : std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); signal write_be_p0_n : std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); signal stall_write_pipe : std_logic := '0'; signal write_v : std_logic_vector(3 downto 0) := (others=>'0'); signal write_v_n : std_logic := '0'; signal write_be : std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); signal write_pipe_wrTag : tag_addr_array(4 downto 0) := (others=>(others=>'0')); signal write_pipe_wrTag_valid : std_logic_vector(4 downto 0) := (others=>'0'); signal write_addr_match : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal write_addr_match_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); --}}} -- fifos {{{ signal wr_fifo_cache_rqst : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal rd_fifo_cache_rqst : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_cache_ack : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal rd_fifo_cache_ack : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_rqst_addr : cache_addr_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_rqst_addr : cache_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_dout : cache_word_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal cache_dob : std_logic_vector(DATA_W*2**N-1 downto 0) := (others=>'0'); signal rd_fifo_din_v : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal fifo_be_din : std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); --}}} -- atomics -------------------------------------------------------------------------------------------{{{ signal flush_ack, flush_ack_n : std_logic := '0'; signal flush_done : std_logic := '0'; signal flush_rcv_index : integer range 0 to N_RECEIVERS-1 := 0; signal flush_rcv_index_n : integer range 0 to N_RECEIVERS-1 := 0; signal flush_v : std_logic := '0'; signal flush_gmem_addr : unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); signal flush_data : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal atomic_can_finish : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} begin -- internal & fixed signals assignments -------------------------------------------------------------------------{{{ cu_ready <= cu_ready_i; axi_wvalid <= axi_wvalid_i; rdData <= rdData_i; finish_exec <= finish_exec_i; ---------------------------------------------------------------------------------------------------------}}} -- error handling ------------------------------------------------------------------------------------------- {{{ assert GMEM_WORD_ADDR_W-BRMEM_ADDR_W-CACHE_N_BANKS_W <= 24; assert CACHE_N_BANKS_W > 0 and CACHE_N_BANKS_W <= 3; assert (N_RECEIVERS/2**N)*2**N = N_RECEIVERS; assert N_AXI = 1 or N_AXI = 2 or N_AXI = 4; assert BURST_WORDS_W >= CACHE_N_BANKS_W; ---------------------------------------------------------------------------------------------------------------}}} -- cache -------------------------------------------------------------------------------------------{{{ cache_inst: entity cache port map( clk => clk, nrst => nrst, ena => '1', wea => cache_wea, addra => cache_addra, dia => cache_wrData, doa => rdData_i, enb => '1', enb_be => '1', wr_fifo_rqst_addr => wr_fifo_rqst_addr, rd_fifo_rqst_addr => rd_fifo_rqst_addr, wr_fifo_dout => wr_fifo_dout, dob => cache_dob, rd_fifo_din_v => rd_fifo_din_v, be_rdData => fifo_be_din, ticket_rqst_wr => wr_fifo_cache_rqst, ticket_rqst_rd => rd_fifo_cache_rqst, ticket_ack_wr_fifo=> wr_fifo_cache_ack, ticket_ack_rd_fifo=> rd_fifo_cache_ack ); ---------------------------------------------------------------------------------------------------------}}} -- write pipeline -------------------------------------------------------------------------------------- {{{ process(clk) begin if rising_edge(clk) then write_phase <= write_phase + 1; rcv_to_write_pri <= rcv_to_write_pri_n; rcv_to_write_pri_v <= rcv_to_write_pri_v_n; if stall_write_pipe = '0' or write_v(2) = '0' or write_v(1) = '0' or write_v(0) = '0'then --stage 0 rcv_to_write <= rcv_to_write_n; write_v(0) <= write_v_n; rcv_write_in_pipeline <= rcv_write_in_pipeline_n; end if; if stall_write_pipe = '0' or write_v(2) = '0' or write_v(1) = '0' then --stage 1 write_addr(1) <= write_addr(0); write_v(1) <= write_v(0); write_addr_match <= write_addr_match_n; end if; if stall_write_pipe = '0' or write_v(2) = '0' then -- stage 2 rcv_will_write <= rcv_will_write_n; write_word_rcv_indx <= write_word_rcv_indx_n; write_be_p0 <= write_be_p0_n; write_addr(2) <= write_addr(1); write_v(2) <= write_v(1); end if; -- write_be <= (others=>'0'); if stall_write_pipe = '0' then -- stage 3 rcv_will_write_d0 <= rcv_will_write; write_addr(3) <= write_addr(2); write_be <= (others=>'0'); write_v(3) <= write_v(2); write_be <= write_be_p0; if SUB_INTEGER_IMPLEMENT /= 0 then for k in 0 to DATA_W/8-1 loop for j in 0 to 2**N-1 loop write_word(j*DATA_W+(k+1)*8-1 downto j*DATA_W+k*8) <= rcv_gmem_data(write_word_rcv_indx(j*DATA_W/8+k))(8*(k+1)-1 downto 8*k); end loop; end loop; else for j in 0 to 2**N-1 loop write_word((j+1)*DATA_W-1 downto j*DATA_W) <= rcv_gmem_data(write_word_rcv_indx(j)); end loop; end if; end if; end if; end process; process(rcv_priority, rcv_request_write_addr, write_phase) variable indx : unsigned(N_RECEIVERS_W-1 downto 0) := (others=>'0'); begin indx(N_RECEIVERS_W-1 downto N_RECEIVERS_W-WRITE_PHASE_W) := write_phase; for j in 0 to 2**c_n_priority_classes_w-1 loop rcv_to_write_pri_n(j) <= 0; rcv_to_write_pri_v_n(j) <= '0'; for i in 0 to N_RECEIVERS/2**WRITE_PHASE_W-1 loop indx(N_RECEIVERS_W-WRITE_PHASE_W-1 downto 0) := to_unsigned(i, N_RECEIVERS_W-WRITE_PHASE_W); if rcv_request_write_addr(to_integer(indx)) = '1' and to_integer(rcv_priority(to_integer(indx))(RCV_PRIORITY_W-1 downto RCV_PRIORITY_W-c_n_priority_classes_w)) = j then rcv_to_write_pri_n(j) <= to_integer(indx); rcv_to_write_pri_v_n(j) <= '1'; end if; end loop; end loop; end process; process(rcv_gmem_addr, rcv_to_write, write_v, rcv_request_write_data, rcv_to_write_pri_v, rcv_to_write_pri, rcv_be, write_addr_match, rcv_request_write_addr) variable rcv_indx : unsigned(N_RECEIVERS_W-1 downto 0) := (others=>'0'); begin rcv_to_write_n <= rcv_to_write; write_v_n <= '0'; rcv_write_in_pipeline_n <= (others=>'0'); -- stage 0: define the rcv indx to write for j in 2**c_n_priority_classes_w-1 downto 0 loop if rcv_to_write_pri_v(j) = '1' and rcv_request_write_addr(rcv_to_write_pri(j)) = '1' then rcv_to_write_n <= rcv_to_write_pri(j); write_v_n <= '1'; rcv_write_in_pipeline_n(rcv_to_write_pri(j)) <= '1'; exit; end if; end loop; -- stage 1: define the address to be written write_addr(0) <= rcv_gmem_addr(rcv_to_write)(M+L+N-1 downto N); write_addr_match_n <= (others=>'0'); for i in 0 to N_RECEIVERS-1 loop if rcv_gmem_addr(i)(M+L+N-1 downto N) = rcv_gmem_addr(rcv_to_write)(M+L+N-1 downto N) and rcv_request_write_data(i) = '1' then write_addr_match_n(i) <= '1'; end if; end loop; -- stage 2: define which receivers will write rcv_will_write_n <= (others=>'0'); write_word_rcv_indx_n <= (others=>0); write_be_p0_n <= (others=>'0'); if write_v(1) = '1' then if SUB_INTEGER_IMPLEMENT /= 0 then for k in 0 to DATA_W/8-1 loop for j in 0 to 2**N-1 loop for i in 0 to N_RECEIVERS-1 loop if write_addr_match(i) = '1' and to_integer(rcv_gmem_addr(i)(N-1 downto 0)) = j and rcv_be(i)(k) = '1' and rcv_request_write_data(i) = '1' then -- if rcv_gmem_addr(i)(M+L+N-1 downto N) = write_addr(1) and rcv_request_write_data(i) = '1' and -- to_integer(rcv_gmem_addr(i)(N-1 downto 0)) = j and rcv_be(i)(k) = '1' then rcv_will_write_n(i) <= '1'; write_word_rcv_indx_n(j*DATA_W/8+k) <= i; write_be_p0_n(j*DATA_W/8+k) <= '1'; -- exit; end if; end loop; end loop; end loop; else for j in 0 to 2**N-1 loop for i in 0 to N_RECEIVERS-1 loop if write_addr_match(i) = '1' and to_integer(rcv_gmem_addr(i)(N-1 downto 0)) = j and rcv_be(i)(0) = '1' and rcv_request_write_data(i) = '1' then rcv_will_write_n(i) <= '1'; write_word_rcv_indx_n(j) <= i; write_be_p0_n((j+1)*DATA_W/8-1 downto j*DATA_W/8) <= (others=>'1'); end if; end loop; end loop; end if; end if; -- stage 3: form the data word to be written end process; --------------------------------------------------------------------------------------------------------- }}} -- responder -------------------------------------------------------------------------------------------{{{ -- TODO: the effeciency of this should be studied on the real hardware read_priority_pipe_true: if ENABLE_READ_PRIORIRY_PIPE generate process(rcv_priority, rcv_perform_read, rcv_to_read_pri, cu_served) begin for j in 0 to 2**c_n_priority_classes_w-1 loop rcv_to_read_pri_n(j) <= rcv_to_read_pri(j); rcv_to_read_pri_v_n(j) <= '0'; for i in N_RECEIVERS-1 downto 0 loop if rcv_perform_read(i) = '1' and to_integer(rcv_priority(i)(RCV_PRIORITY_W-1 downto RCV_PRIORITY_W-c_n_priority_classes_w)) = j and cu_served(c_rcv_cu_indx(i)) = (c_served_vec_len-1 downto 0 => '0') then rcv_to_read_pri_n(j) <= i; rcv_to_read_pri_v_n(j) <= '1'; end if; end loop; end loop; end process; process(rcv_to_read_pri_v, rcv_to_read_pri, rcv_to_read, rcv_perform_read) begin rcv_to_read_n <= rcv_to_read; cache_read_v_p0_n <= '0'; cu_served_n <= (others=>'0'); for j in 2**c_n_priority_classes_w-1 downto 0 loop if rcv_to_read_pri_v(j) = '1' and rcv_perform_read(rcv_to_read_pri(j)) = '1' then rcv_to_read_n <= rcv_to_read_pri(j); cache_read_v_p0_n <= '1'; cu_served_n(c_rcv_cu_indx(rcv_to_read_pri(j))) <= '1'; exit; end if; end loop; end process; end generate; read_priority_pipe_false: if not ENABLE_READ_PRIORIRY_PIPE generate process(rcv_priority, rcv_perform_read, rcv_to_read_pri, cu_served) begin for j in 0 to 2**c_n_priority_classes_w-1 loop rcv_to_read_pri_n(j) <= rcv_to_read_pri(j); rcv_to_read_pri_v_n(j) <= '0'; for i in N_RECEIVERS-1 downto 0 loop if rcv_perform_read(i) = '1' and to_integer(rcv_priority(i)(RCV_PRIORITY_W-1 downto RCV_PRIORITY_W-c_n_priority_classes_w)) = j and cu_served(c_rcv_cu_indx(i)) = (0 to c_served_vec_len-1 => '0') then rcv_to_read_pri_n(j) <= i; rcv_to_read_pri_v_n(j) <= '1'; end if; end loop; end loop; end process; process(rcv_to_read_pri_v_n, rcv_to_read_pri_n, rcv_to_read) begin rcv_to_read_n <= rcv_to_read; cache_read_v_p0_n <= '0'; cu_served_n <= (others=>'0'); for j in 2**c_n_priority_classes_w-1 downto 0 loop if rcv_to_read_pri_v_n(j) = '1' then rcv_to_read_n <= rcv_to_read_pri_n(j); cache_read_v_p0_n <= '1'; cu_served_n(c_rcv_cu_indx(rcv_to_read_pri_n(j))) <= '1'; exit; end if; end loop; end process; end generate; process(clk) variable rcv_indx : unsigned(N_RECEIVERS_W-1 downto 0) := (others=>'0'); begin if rising_edge(clk) then for i in 0 to N_CU-1 loop cu_served(i)(c_served_vec_len-2 downto 0) <= cu_served(i)(c_served_vec_len-1 downto 1); cu_served(i)(c_served_vec_len-1) <= cu_served_n(i); -- cu_served(i)(c_served_vec_len-1) <= '0'; end loop; rcv_to_read_pri_v <= rcv_to_read_pri_v_n; cache_read_v_p0 <= '0'; cache_wea <= cache_wea_n; cache_we <= cache_we_n; -- assert cache_we = '0' or cache_addra /= X"23" severity failure; --stage 0 (read) --stage 1 (read) cache_addra <= cache_addra_n; rdAddr_p1 <= rcv_gmem_addr(rcv_to_read)(GMEM_WORD_ADDR_W-1 downto N); -- stage 1(write) cache_wrData <= write_word; --stage 2 rdAddr_p0 <= rdAddr_p1; rcv_rd_done <= rcv_rd_done_n; --stage 3 rdAddr <= rdAddr_p0; rdAck <= (others=>'0'); for i in 0 to N_RECEIVERS-1 loop if rcv_rd_done(i) = '1' then rdAck(c_rcv_cu_indx(i)) <= '1'; end if; end loop; if nrst = '0' then cache_read_v <= '0'; cache_read_v_d0 <= '0'; rcv_to_read <= 0; rcv_to_read_pri <= (others=>0); else --stage 0 (read) rcv_to_read_pri <= rcv_to_read_pri_n; rcv_to_read <= rcv_to_read_n; cache_read_v_p0 <= cache_read_v_p0_n; --stage 1 (read) cache_read_v <= cache_read_v_p0; -- stage 1(write) --stage 2 cache_read_v_d0 <= cache_read_v; end if; end if; end process; -- process(rcv_gmem_addr, rcv_to_read, cache_read_v_p0, write_addr(3), write_v(3), cache_addra) -- begin -- cache_addra_n <= cache_addra; -- if cache_read_v_p0 = '1' then -- cache_addra_n <= rcv_gmem_addr(rcv_to_read)(L+M+N-1 downto N); -- elsif write_v(3) = '1' then -- cache_addra_n <= write_addr(3); -- end if; -- end process; process(rcv_gmem_addr, rcv_to_read, cache_read_v_p0, write_addr(3)) begin if cache_read_v_p0 = '1' then cache_addra_n <= rcv_gmem_addr(rcv_to_read)(L+M+N-1 downto N); else cache_addra_n <= write_addr(3); end if; end process; process(write_v(3), cache_read_v_p0, write_be) begin if write_v(3) = '0' or cache_read_v_p0 = '0' then stall_write_pipe <= '0'; else stall_write_pipe <= '1'; end if; cache_wea_n <= (others=>'0'); cache_we_n <= '0'; if write_v(3) = '1' and cache_read_v_p0 = '0' then cache_wea_n <= write_be; cache_we_n <= '1'; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- axi controllers --------------------------------------------------------------------------------------{{{ axi_cntrl: entity axi_controllers port map( clk => clk, axi_rdAddr => axi_rdAddr, axi_wrAddr => axi_wrAddr, wr_fifo_go => wr_fifo_go, axi_writer_go => axi_writer_go, axi_writer_ack => axi_writer_ack, axi_writer_id => axi_writer_id, wr_fifo_free => wr_fifo_free, axi_writer_free => axi_writer_free, wr_fifo_cache_rqst=> wr_fifo_cache_rqst, rd_fifo_cache_rqst=> rd_fifo_cache_rqst, wr_fifo_cache_ack => wr_fifo_cache_ack, rd_fifo_cache_ack => rd_fifo_cache_ack, wr_fifo_rqst_addr => wr_fifo_rqst_addr, rd_fifo_rqst_addr => rd_fifo_rqst_addr, wr_fifo_dout => wr_fifo_dout, cache_dob => cache_dob, rd_fifo_din_v => rd_fifo_din_v, fifo_be_din => fifo_be_din, axi_araddr => axi_araddr, axi_arvalid => axi_arvalid, axi_arready => axi_arready, axi_arid => axi_arid, axi_rdata => axi_rdata, axi_rlast => axi_rlast, axi_rvalid => axi_rvalid, axi_rready => axi_rready, axi_rid => axi_rid, axi_awaddr => axi_awaddr, axi_awvalid => axi_awvalid, axi_awready => axi_awready, axi_awid => axi_awid, axi_wdata => axi_wdata, axi_wstrb => axi_wstrb, axi_wlast => axi_wlast, axi_wvalid => axi_wvalid_i, axi_wready => axi_wready, axi_bvalid => axi_bvalid, axi_bready => axi_bready, axi_bid => axi_bid, nrst => nrst ); ---------------------------------------------------------------------------------------------------------}}} -- tags mem ------------------------------------------------------------------------------------------- {{{ process(write_addr, write_v, cache_addra, cache_we) begin for i in 0 to 3 loop write_pipe_wrTag(i) <= write_addr(i)(M+L-1 downto L); write_pipe_wrTag_valid(i) <= write_v(i); end loop; write_pipe_wrTag(4) <= cache_addra(M+L-1 downto L); write_pipe_wrTag_valid(4) <= cache_we; end process; tags_controller: entity gmem_cntrl_tag port map( clk => clk, wr_fifo_go => wr_fifo_go, axi_writer_go => axi_writer_go, axi_writer_ack => axi_writer_ack, axi_writer_id => axi_writer_id, wr_fifo_free => wr_fifo_free, axi_writer_free => axi_writer_free, axi_rd_fifo_filled=> rd_fifo_cache_ack, axi_rdAddr => axi_rdAddr, axi_wrAddr => axi_wrAddr, wr_fifo_cache_ack => wr_fifo_cache_ack, axi_wvalid => axi_wvalid_i, --receivers signals rcv_alloc_tag => rcv_alloc_tag, rcv_rnw => rcv_rnw, rcv_gmem_addr => rcv_gmem_addr, rcv_read_tag => rcv_read_tag, rcv_read_tag_ack => rcv_read_tag_ack, rdData_page_v => rdData_page_v, rdData_tag_v => rdData_tag_v, rdData_tag => rdData_tag, rcv_tag_written => rcv_tag_written, rcv_tag_updated => rcv_tag_updated, rcv_page_validated=> rcv_page_validated, -- it is a one-cycle message cache_we => cache_we, cache_addra => cache_addra, cache_wea => cache_wea, --finish WGsDispatched => WGsDispatched, CUs_gmem_idle => CUs_gmem_idle, rcv_all_idle => rcv_all_idle, rcv_idle => rcv_idle, finish_exec => finish_exec_i, start_kernel => start_kernel, clean_cache => clean_cache, atomic_can_finish => atomic_can_finish, -- write pipeline write_pipe_active => write_pipe_wrTag_valid, write_pipe_wrTag => write_pipe_wrTag, nrst => nrst ); ---------------------------------------------------------------------------------------------------------}}} -- atomics ----------------------------------------------------------------------------------------------{{{ atomics_if: if ATOMIC_IMPLEMENT /=0 generate atomics_inst: entity gmem_atomics port map( clk => clk, rcv_atomic_rqst => rcv_atomic_rqst, rcv_atomic_ack => rcv_atomic_ack, rcv_atomic_type => rcv_atomic_type, rcv_gmem_addr => rcv_gmem_addr, rcv_must_read => rcv_must_read, rcv_gmem_data => rcv_gmem_data, gmem_rdAddr_p0 => rdAddr_p0, gmem_rdData => rdData_i, gmem_rdData_v_p0 => cache_read_v_d0, rcv_retire => rcv_atomic_performed, atomic_rdData => atomic_rdData, flush_ack => flush_ack, flush_done => flush_done, flush_v => flush_v, flush_gmem_addr => flush_gmem_addr, flush_data => flush_data, finish => finish_exec_i, atomic_can_finish => atomic_can_finish, WGsDispatched => WGsDispatched, nrst => nrst ); end generate; ---------------------------------------------------------------------------------------------------------}}} -- receivers -------------------------------------------------------------------------------------------{{{ receivers_trans: process(clk) -- {{{ begin if rising_edge(clk) then rcv_gmem_addr <= rcv_gmem_addr_n; rcv_gmem_data <= rcv_gmem_data_n; rcv_be <= rcv_be_n; rcv_rnw <= rcv_rnw_n; cu_rnw_d0 <= cu_rnw; cu_we_d0 <= cu_we; cu_rqst_addr_d0 <= cu_rqst_addr; cu_wrData_d0 <= cu_wrData; if ATOMIC_IMPLEMENT /= 0 then rcv_atomic_sgntr <= rcv_atomic_sgntr_n; rcv_atomic <= rcv_atomic_n; cu_atomic_d0 <= cu_atomic; cu_atomic_sgntr_d0 <= cu_atomic_sgntr; cu_atomic_ack_p0 <= (others=>'0'); if flush_ack = '1' then cu_atomic_d0(0) <= '0'; cu_rqst_addr_d0(0) <= flush_gmem_addr; cu_wrData_d0(0) <= flush_data; cu_we_d0(0) <= (others=>'1'); cu_rnw_d0(0) <= '0'; end if; for i in 0 to N_RECEIVERS-1 loop if rcv_atomic_performed(i) = '1' then cu_atomic_ack_p0(c_rcv_cu_indx(i)) <= '1'; end if; end loop; atomic_rdData_v <= cu_atomic_ack_p0; for i in 0 to N_RECEIVERS-1 loop if rcv_atomic_performed(i) = '1' then atomic_sgntr_p0 <= rcv_atomic_sgntr(i); end if; end loop; atomic_sgntr <= atomic_sgntr_p0; end if; if rcv_idle = (rcv_idle'reverse_range => '1') then rcv_all_idle <= '1'; else rcv_all_idle <= '0'; end if; rcv_priority <= rcv_priority_n; rcv_go <= rcv_go_n; for i in 0 to N_RECEIVERS-1 loop if rdData_tag(c_rcv_bank_indx(i)) = rcv_gmem_addr(i)(GMEM_WORD_ADDR_W-1 downto L+M+N) and rdData_tag_v(c_rcv_bank_indx(i)) = '1' then rcv_tag_compared(i) <= '1'; else rcv_tag_compared(i) <= '0'; end if; end loop; rdData_page_v_d0 <= rdData_page_v; rcv_wait_1st_cycle <= rcv_wait_1st_cycle_n; rcv_request_write_data <= rcv_request_write_data_n; if nrst = '0' then st_rcv <= (others=>get_addr); rcv_idle <= (others=>'0'); rcv_read_tag <= (others=>'0'); if ATOMIC_IMPLEMENT /= 0 then rcv_atomic_rqst <= (others=>'0'); end if; rcv_alloc_tag <= (others=>'0'); rcv_perform_read <= (others=>'0'); rcv_request_write_addr <= (others=>'0'); else st_rcv <= st_rcv_n; rcv_idle <= rcv_idle_n; rcv_read_tag <= rcv_read_tag_n; if ATOMIC_IMPLEMENT /= 0 then rcv_atomic_rqst <= rcv_atomic_rqst_n; end if; rcv_alloc_tag <= rcv_alloc_tag_n; rcv_perform_read <= rcv_perform_read_n; rcv_request_write_addr <= rcv_request_write_addr_n; end if; end if; end process; -- }}} rcv_comb: for i in 0 to N_RECEIVERS-1 generate begin rcv_com: process (st_rcv(i), rcv_gmem_addr(i), cu_rqst_addr_d0(c_rcv_cu_indx(i)), rcv_read_tag(i), rcv_be(i), rcv_rnw(i), rcv_idle(i), -- {{{ rcv_write_in_pipeline(i), cu_we_d0(c_rcv_cu_indx(i)), rcv_tag_compared(i), rcv_go(i), rcv_read_tag_ack(i), rcv_atomic_sgntr(i), rcv_alloc_tag(i), rdData_page_v_d0(c_rcv_bank_indx(i)), rcv_atomic_rqst(i), cu_rnw_d0(c_rcv_cu_indx(i)), cu_wrData_d0(c_rcv_cu_indx(i)), rcv_tag_written(i), rcv_tag_updated(i), rcv_request_write_addr(i), rcv_request_write_data(i), rcv_perform_read(i), cache_addra, cache_read_v, rcv_page_validated(i), cache_we, rcv_will_write(i), rcv_gmem_data(i), rcv_priority(i), rcv_atomic_ack(i), rcv_will_write_d0(i), rcv_wait_1st_cycle(i), cu_atomic_d0(c_rcv_cu_indx(i)), rcv_atomic(i), rcv_must_read(i), rcv_atomic_performed(i), cu_atomic_sgntr_d0(c_rcv_cu_indx(i))) variable li : line; -- }}} begin -- assignments {{{ st_rcv_n(i) <= st_rcv(i); rcv_gmem_addr_n(i) <= rcv_gmem_addr(i); rcv_gmem_data_n(i) <= rcv_gmem_data(i); rcv_read_tag_n(i) <= rcv_read_tag(i); if ATOMIC_IMPLEMENT /= 0 then rcv_atomic_rqst_n(i) <= rcv_atomic_rqst(i); end if; rcv_rnw_n(i) <= rcv_rnw(i); rcv_atomic_n(i) <= rcv_atomic(i); rcv_perform_read_n(i) <= rcv_perform_read(i); rcv_request_write_addr_n(i) <= rcv_request_write_addr(i); rcv_request_write_data_n(i) <= rcv_request_write_data(i); rcv_wait_1st_cycle_n(i) <= rcv_wait_1st_cycle(i); rcv_alloc_tag_n(i) <= rcv_alloc_tag(i); rcv_be_n(i) <= rcv_be(i); rcv_atomic_sgntr_n(i) <= rcv_atomic_sgntr(i); rcv_idle_n(i) <= rcv_idle(i); rcv_priority_n(i) <= rcv_priority(i); rcv_rd_done_n(i) <= '0'; --}}} case st_rcv(i) is when get_addr => -- {{{ -- rcv_be_n(i) <= (others=>'0'); rcv_idle_n(i) <= '1'; rcv_wait_1st_cycle_n(i) <= '0'; rcv_request_write_data_n(i) <= '0'; rcv_priority_n(i) <= (others=>'0'); rcv_rnw_n(i) <= cu_rnw_d0(c_rcv_cu_indx(i)); if rcv_go(i) = '1' then rcv_gmem_addr_n(i) <= unsigned(cu_rqst_addr_d0(c_rcv_cu_indx(i))); rcv_be_n(i) <= cu_we_d0(c_rcv_cu_indx(i)); rcv_atomic_sgntr_n(i) <= cu_atomic_sgntr_d0(c_rcv_cu_indx(i)); rcv_gmem_data_n(i) <= cu_wrData_d0(c_rcv_cu_indx(i)); rcv_atomic_n(i) <= cu_atomic_d0(c_rcv_cu_indx(i)); -- assert to_integer(unsigned(cu_rqst_addr_d0(c_rcv_cu_indx(i)))) = 792 or cu_rnw_d0(c_rcv_cu_indx(i)) = '1' severity failure; if cu_atomic_d0(c_rcv_cu_indx(i)) = '0' then st_rcv_n(i) <= get_read_tag_ticket; rcv_read_tag_n(i) <= '1'; else st_rcv_n(i) <= requesting_atomic; if ATOMIC_IMPLEMENT /= 0 then rcv_atomic_rqst_n(i) <= '1'; end if; end if; rcv_idle_n(i) <= '0'; end if; -- }}} when requesting_atomic => -- {{{ if ATOMIC_IMPLEMENT /= 0 then rcv_priority_n(i) <= rcv_priority(i) + 1; if rcv_priority(i) = (rcv_priority(i)'reverse_range=>'1') then rcv_atomic_rqst_n(i) <= '1'; end if; if rcv_atomic_ack(i) = '1' then rcv_atomic_rqst_n(i) <= '0'; end if; if rcv_must_read(i) = '1' then -- rcv_must_read & rcv_atomic_performed cann't be at 1 simultaneously rcv_atomic_rqst_n(i) <= '0'; rcv_rnw_n(i) <= '1'; st_rcv_n(i) <= get_read_tag_ticket; rcv_read_tag_n(i) <= '1'; end if; if rcv_atomic_performed(i) = '1' then rcv_atomic_rqst_n(i) <= '0'; st_rcv_n(i) <= get_addr; end if; end if; -- }}} when get_read_tag_ticket => -- rdAddr of tag mem is being selected {{{ if rcv_read_tag_ack(i) = '1' then st_rcv_n(i) <= wait_read_tag; rcv_read_tag_n(i) <= '0'; end if; -- }}} when wait_read_tag => --address is fixed and tag mem is being read {{{ rcv_wait_1st_cycle_n(i) <= '1'; if rcv_tag_written(i) = '1' then if rcv_rnw(i) = '1' then st_rcv_n(i) <= clean; rcv_alloc_tag_n(i) <= '1'; else if rcv_rnw(i) = '1' then st_rcv_n(i) <= read_cache; rcv_perform_read_n(i) <= '1'; else st_rcv_n(i) <= request_write_addr; rcv_request_write_addr_n(i) <= '1'; rcv_request_write_data_n(i) <= '1'; end if; end if; elsif rcv_tag_updated(i) = '1' then st_rcv_n(i) <= alloc_tag; rcv_alloc_tag_n(i) <= '1'; else if rcv_wait_1st_cycle(i) = '1' then if rcv_rnw(i) = '1' then st_rcv_n(i) <= check_tag_rd; else st_rcv_n(i) <= check_tag_wr; end if; end if; end if; --}}} when check_tag_rd => -- rdData of tag mem are ready {{{ if rcv_tag_updated(i) = '1' or (rcv_tag_written(i) = '0' and rcv_tag_compared(i) = '0') then st_rcv_n(i) <= alloc_tag; rcv_alloc_tag_n(i) <= '1'; elsif rcv_tag_compared(i) = '1' and rdData_page_v_d0(c_rcv_bank_indx(i)) = '1' then st_rcv_n(i) <= read_cache; rcv_perform_read_n(i) <= '1'; elsif rcv_page_validated(i) = '0' then --if rcv_rnw(i) = '1' and ( rcv_tag_written(i) = '1' or (rcv_tag_compared(i) = '1' and rdData_page_v_d0(c_rcv_bank_indx(i)) = '0' ) ) the st_rcv_n(i) <= clean; rcv_alloc_tag_n(i) <= '1'; else st_rcv_n(i) <= read_cache; rcv_perform_read_n(i) <= '1'; end if; -- }}} when check_tag_wr => -- rdData of tag mem are ready {{{ if rcv_tag_updated(i) = '1' or (rcv_tag_written(i) = '0' and rcv_tag_compared(i) = '0') then st_rcv_n(i) <= alloc_tag; rcv_alloc_tag_n(i) <= '1'; elsif rcv_tag_written(i) = '1' or rcv_tag_compared(i) = '1' then st_rcv_n(i) <= request_write_addr; rcv_request_write_addr_n(i) <= '1'; rcv_request_write_data_n(i) <= '1'; else st_rcv_n(i) <= clean; rcv_alloc_tag_n(i) <= '1'; end if; --}}} when alloc_tag => -- {{{ if rcv_tag_written(i) = '1' then if rcv_rnw(i) = '1' then st_rcv_n(i) <= clean; else st_rcv_n(i) <= request_write_addr; rcv_request_write_addr_n(i) <= '1'; rcv_request_write_data_n(i) <= '1'; rcv_alloc_tag_n(i) <= '0'; end if; end if; --}}} when clean => --{{{ if rcv_tag_updated(i) = '1' then st_rcv_n(i) <= alloc_tag; elsif rcv_page_validated(i) = '1' then rcv_alloc_tag_n(i) <= '0'; if rcv_rnw(i) = '1' then st_rcv_n(i) <= read_cache; rcv_perform_read_n(i) <= '1'; else st_rcv_n(i) <= request_write_addr; rcv_request_write_addr_n(i) <= '1'; rcv_request_write_data_n(i) <= '1'; end if; end if; -- }}} when read_cache => -- {{{ if rcv_tag_updated(i) = '1' then st_rcv_n(i) <= alloc_tag; rcv_alloc_tag_n(i) <= '1'; rcv_perform_read_n(i) <= '0'; elsif (cache_addra = rcv_gmem_addr(i)(L+M+N-1 downto N)) and cache_read_v = '1' then rcv_perform_read_n(i) <= '0'; if ATOMIC_IMPLEMENT /= 0 and rcv_atomic(i) = '1' then rcv_atomic_rqst_n(i) <= '1'; st_rcv_n(i) <= requesting_atomic; else st_rcv_n(i) <= get_addr; rcv_idle_n(i) <= '1'; rcv_rd_done_n(i) <= '1'; end if; end if; if rcv_priority(i) /= (rcv_priority(i)'reverse_range=>'1') then rcv_priority_n(i) <= rcv_priority(i) + 1; end if; -- }}} when request_write_addr => -- {{{ if rcv_tag_updated(i) = '1' then st_rcv_n(i) <= alloc_tag; rcv_alloc_tag_n(i) <= '1'; rcv_request_write_addr_n(i) <= '0'; rcv_request_write_data_n(i) <= '0'; elsif rcv_will_write(i) = '1' then rcv_request_write_addr_n(i) <= '0'; rcv_request_write_data_n(i) <= '0'; st_rcv_n(i) <= write_cache; elsif rcv_write_in_pipeline(i) = '1' then rcv_request_write_addr_n(i) <= '0'; st_rcv_n(i) <= request_write_data; end if; if rcv_priority(i) /= (rcv_priority(i)'reverse_range=>'1') then rcv_priority_n(i) <= rcv_priority(i) + 1; end if; -- }}} when request_write_data => -- {{{ if rcv_will_write(i) = '1' then st_rcv_n(i) <= write_cache; rcv_request_write_data_n(i) <= '0'; end if; -- }}} when write_cache=> -- {{{ -- assert std_logic_vector(rcv_gmem_addr(i)(15 downto 0)) = rcv_gmem_data(i)(15 downto 0); if cache_we = '1' and rcv_will_write_d0(i) = '0' then st_rcv_n(i) <= get_addr; rcv_idle_n(i) <= '1'; end if; -- }}} end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- interface to CUs ----------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then cu_ready_i <= cu_ready_n; cuIndx_msb <= not cuIndx_msb; if ATOMIC_IMPLEMENT /= 0 then flush_ack <= flush_ack_n; flush_rcv_index <= flush_rcv_index_n; flush_done <= rcv_idle(flush_rcv_index); end if; end if; end process; process(cu_valid, cu_ready_i, rcv_idle, cuIndx_msb, rcv_idle_n, flush_v, flush_ack, flush_rcv_index) variable rcvIndx: unsigned(N_RECEIVERS_W-1 downto 0) := (others=>'0'); begin rcv_go_n <= (others=>'0'); -- setting ready signal for CU0 cu_ready_n(0) <= '0'; flush_ack_n <= '0'; if ATOMIC_IMPLEMENT /= 0 then flush_rcv_index_n <= flush_rcv_index; end if; for j in N_RECEIVERS_CU/2-1 downto 0 loop rcvIndx(N_RECEIVERS_W-1 downto N_RECEIVERS_W-max(N_CU_W, 1)) := to_unsigned(0, max(1, N_CU_W)); rcvIndx(N_RECEIVERS_CU_W-1) := not cuIndx_msb; rcvIndx(N_RECEIVERS_CU_W-2 downto 0) := to_unsigned(j, N_RECEIVERS_CU_W-1); if rcv_idle_n(to_integer(rcvIndx)) = '1' then if ATOMIC_IMPLEMENT /= 0 and flush_v = '1' and flush_ack = '0' then flush_ack_n <= '1'; cu_ready_n(0) <= '0'; else flush_ack_n <= '0'; cu_ready_n(0) <= '1'; end if; end if; end loop; -- starting receviers for CU0 if (cu_valid(0) = '1' and cu_ready_i(0) = '1') or (ATOMIC_IMPLEMENT /= 0 and flush_v = '1' and flush_ack = '1' ) then for j in N_RECEIVERS_CU/2-1 downto 0 loop rcvIndx(N_RECEIVERS_W-1 downto N_RECEIVERS_W-max(1,N_CU_W)) := to_unsigned(0, max(1, N_CU_W)); rcvIndx(N_RECEIVERS_CU_W-1) := cuIndx_msb; rcvIndx(N_RECEIVERS_CU_W-2 downto 0) := to_unsigned(j, N_RECEIVERS_CU_W-1); if rcv_idle(to_integer(rcvIndx)) = '1' then rcv_go_n(to_integer(rcvIndx)) <= '1'; flush_rcv_index_n <= to_integer(rcvIndx); exit; end if; end loop; end if; -- other receivers if N_CU > 1 then for i in 1 to max(N_CU-1,1) loop -- starting receviers if cu_valid(i) = '1' and cu_ready_i(i) = '1' then for j in N_RECEIVERS_CU/2-1 downto 0 loop rcvIndx(N_RECEIVERS_W-1 downto N_RECEIVERS_W-max(1,N_CU_W)) := to_unsigned(i, max(1, N_CU_W)); rcvIndx(N_RECEIVERS_CU_W-1) := cuIndx_msb; rcvIndx(N_RECEIVERS_CU_W-2 downto 0) := to_unsigned(j, N_RECEIVERS_CU_W-1); if rcv_idle(to_integer(rcvIndx)) = '1' then rcv_go_n(to_integer(rcvIndx)) <= '1'; exit; end if; end loop; end if; -- setting ready signal cu_ready_n(i) <= '0'; for j in N_RECEIVERS_CU/2-1 downto 0 loop rcvIndx(N_RECEIVERS_W-1 downto N_RECEIVERS_W-max(N_CU_W, 1)) := to_unsigned(i, max(1, N_CU_W)); rcvIndx(N_RECEIVERS_CU_W-1) := not cuIndx_msb; rcvIndx(N_RECEIVERS_CU_W-2 downto 0) := to_unsigned(j, N_RECEIVERS_CU_W-1); if rcv_idle_n(to_integer(rcvIndx)) = '1' then cu_ready_n(c_rcv_cu_indx(to_integer(rcvIndx))) <= '1'; end if; end loop; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} end Behavioral;

gpl-3.0

c73c7819336b346f5269cc9c0c1e7f25

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_4_CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 2; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

4583efed39b90b089d2a0fed0ed4e53b

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_8Stations_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

ed68248997189b34ae774a791a7d9c95

viccuad/fpga-thingies

tron/ps2KeyboardInterface.vhd

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY ps2KeyboardInterface IS PORT ( clk: IN std_logic; rst: IN std_logic; ps2Clk: IN std_logic; ps2Data: IN std_logic; data: OUT std_logic_vector (7 DOWNTO 0); newData: OUT std_logic; newDataAck: IN std_logic ); END ps2KeyboardInterface; ARCHITECTURE ps2KeyboardInterfaceArch OF ps2KeyboardInterface IS SIGNAL ldData, validData, lastBitRcv, ps2ClkSync, ps2ClkFallingEdge: std_logic; SIGNAL ps2DataRegOut: std_logic_vector(10 DOWNTO 0); SIGNAL goodParity: std_logic; BEGIN synchronizer: PROCESS (rst, clk) VARIABLE aux1: std_logic; BEGIN IF (rst='0') THEN aux1 := '1'; ps2ClkSync <= '1'; ELSIF (clk'EVENT AND clk='1') THEN ps2ClkSync <= aux1; aux1 := ps2Clk; END IF; END PROCESS synchronizer; edgeDetector: PROCESS (rst, clk) VARIABLE aux1, aux2: std_logic; BEGIN ps2ClkFallingEdge <= (NOT aux1) AND aux2; IF (rst='0') THEN aux1 := '1'; aux2 := '1'; ELSIF (clk'EVENT AND clk='1') THEN aux2 := aux1; aux1 := ps2ClkSync; END IF; END PROCESS edgeDetector; ps2DataReg: PROCESS (rst, clk) BEGIN IF (rst='0') THEN ps2DataRegOut <= (OTHERS =>'1'); ELSIF (clk'EVENT AND clk='1') THEN IF (lastBitRcv='1') THEN ps2DataRegOut <= (OTHERS=>'1'); ELSIF (ps2ClkFallingEdge='1') THEN ps2DataRegOut <= ps2Data & ps2DataRegOut(10 downto 1); END IF; END IF; END PROCESS ps2DataReg; oddParityCheker: goodParity <= ((ps2DataRegOut(9) XOR ps2DataRegOut(8)) XOR (ps2DataRegOut(7) XOR ps2DataRegOut(6))) XOR ((ps2DataRegOut(5) XOR ps2DataRegOut(4)) XOR (ps2DataRegOut(3) XOR ps2DataRegOut(2))) XOR ps2DataRegOut(1); lastBitRcv <= NOT ps2DataRegOut(0); validData <= lastBitRcv AND goodParity; dataReg: PROCESS (rst, clk) BEGIN IF (rst='0') THEN data <= (OTHERS=>'0'); ELSIF (clk'EVENT AND clk='1') THEN IF (ldData='1') THEN data <= ps2DataRegOut(8 downto 1); END IF; END IF; END PROCESS dataReg; controller: PROCESS (validData, rst, clk) TYPE states IS (waitingData, waitingNewDataAck); VARIABLE state: states; BEGIN ldData <= '0'; newData <= '0'; CASE state IS WHEN waitingData => IF (validData='1') THEN ldData <= '1'; END IF; WHEN waitingNewDataAck => newData <= '1'; WHEN OTHERS => NULL; END CASE; IF (rst='0') THEN state := waitingData; ELSIF (clk'EVENT AND clk='1') THEN CASE state IS WHEN waitingData => IF (validData='1') THEN state := waitingNewDataAck; END IF; WHEN waitingNewDataAck => IF (newDataAck='1') THEN state := waitingData; END IF; WHEN OTHERS => NULL; END CASE; END IF; END PROCESS controller; END ps2KeyboardInterfaceArch;

gpl-3.0

78f8e9af873e7cfed535c7ee26d5b447

viccuad/fpga-thingies

monophonic_keyb/keyboard.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity keyboard is port( clk: IN std_logic; rst: IN std_logic; ps2Clk: IN std_logic; ps2Data: IN std_logic; segs : out STD_LOGIC_VECTOR (6 downto 0); altavoz: OUT std_logic ); end keyboard; architecture Behavioral of keyboard is component ps2KeyboardInterface port ( clk: IN std_logic; rst: IN std_logic; ps2Clk: IN std_logic; ps2Data: IN std_logic; data: OUT std_logic_vector (7 DOWNTO 0); newData: OUT std_logic; newDataAck: IN std_logic ); end component; type fsm_estados is (esperando, pulsada, despulsarPosible); signal estado: fsm_estados; signal scancode: std_logic_vector (7 downto 0); signal newData: std_logic; signal newDataAck: std_logic; signal letra: std_logic_vector (7 downto 0); signal in_semiperiodo: std_logic_vector (17 downto 0); signal out_semiperiodo: std_logic_vector (17 downto 0); signal cuentacont: std_logic_vector (17 downto 0); signal onda: std_logic; signal silencio: std_logic; signal clSemiper: std_logic; signal clLetra: std_logic; signal ldLetra: std_logic; signal ldNewNote: std_logic; signal st : std_logic_vector (2 downto 0); begin interfaz_ps2: ps2KeyboardInterface port map ( rst => rst, clk => clk, ps2Clk => ps2Clk, ps2Data => ps2Data, data => scancode, newData => newData, newDataAck => newDataAck ); --tabla memoria para convertir codigo de teclas al semiperiodo de la nota memoria_notas: process(letra) begin case letra is when "00011100" => in_semiperiodo <= "010111010101001101"; --A(1C): do when "00011101" => in_semiperiodo <= "010110000001001011"; --W(1D): do# when "00011011" => in_semiperiodo <= "010100110010000000"; --S(1B): re when "00100100" => in_semiperiodo <= "010011100111101000"; --E(24): re# when "00100011" => in_semiperiodo <= "010010100001001001"; --D(23): mi when "00101011" => in_semiperiodo <= "010001011110101000"; --F(2B): fa when "00101100" => in_semiperiodo <= "010000011111101111"; --T(2C): fa# when "00110100" => in_semiperiodo <= "001111100100011111"; --G(34): sol when "00110101" => in_semiperiodo <= "001110101100001000"; --Y(35): sol# when "00110011" => in_semiperiodo <= "001101110111110010"; --H(33): la when "00111100" => in_semiperiodo <= "001101000101111001"; --U(3C): la# when "00111011" => in_semiperiodo <= "001100010110111001"; --J(3b): si when "01000010" => in_semiperiodo <= "001011101010011101"; --K(42): do when "00000000" => in_semiperiodo <= "000000000000000000"; -- silencio when others => in_semiperiodo <= "000000000000000000"; -- silencio end case; end process memoria_notas; --maquina de estados----------------------------------------------------- controladorEstados: process (clk, rst, newData, scancode) begin if(rst = '0') then estado <= esperando; elsif (clk'event and clk = '1') then estado <= esperando; -- estado por defecto, puede ser sobreescrito luego case estado is when esperando => if (newData = '1') then estado <= pulsada; else estado <= esperando; end if; when pulsada => if (newData = '1' and scancode /= "11110000") then --11110000: F0 estado <= pulsada; elsif (newData = '1' and scancode = "11110000") then --11110000: F0 estado <= despulsarPosible; else estado <= pulsada; end if; when despulsarPosible => if (newData = '1' and scancode = letra) then estado <= esperando; elsif (newData = '1' and scancode /= letra) then estado <= pulsada; else estado <= despulsarPosible; end if; end case; end if; end process; generadorSalidaMealy: process (newDataAck, scancode, estado, newData, letra) begin --inicializamos: newDataAck <= '0'; clLetra <= '0'; ldletra <= '0'; case estado is when esperando => if (newData = '1') then ldletra <= '1'; ldNewNote <= '1'; newDataAck <= '1'; end if; when pulsada => if (newData = '1') then --esto contiene las 2 posibles transiciones newDataAck <= '1'; ldletra <= '0'; end if; when despulsarPosible => if (newData = '1') then if (scancode = letra) then clLetra <= '1'; newDataAck <= '1'; ldNewNote <= '1'; else newDataAck <= '1'; end if; end if; when others => newDataAck <= '0'; end case; end process; generadorSalidaMoore: process (estado) --genera st begin case estado is when esperando => st <= "000"; when pulsada => st <= "001"; when despulsarPosible => st <= "010"; end case; end process; conversor7seg: process(st) begin case st is -- gfedcba when "000" => segs <= "0111111"; -- cerrado: Locked when "001" => segs <= "0000110"; when "010" => segs <= "1011011"; when "011" => segs <= "1001111"; when others => segs <= "1111001"; -- error end case; end process; ----------------------------------------------------------------------------- oscilador18bits: process(clk,rst,clSemiper) begin if(rst = '0')then cuentacont <= (others => '0'); onda <= '0'; --reset biestable T elsif(clk'event and clk = '1') then if (clSemiper = '1') then cuentacont <= (others => '0'); onda <= not onda; else cuentacont <= cuentacont + 1; end if; end if; end process oscilador18bits; generadorSonido: process(clk,rst,out_semiperiodo,cuentacont,letra,onda,silencio) begin if(rst = '0')then -- registro SemiPer out_semiperiodo <= (others => '0'); elsif(clk'event and clk = '1' and ldNewNote = '1') then out_semiperiodo <= in_semiperiodo; end if; if (out_semiperiodo = cuentaCont) then -- comparador del oscilador clSemiper <= '1'; else clSemiper <= '0'; end if; if (letra = "00000000") then -- puerta NOR para generar silencio silencio <= '1'; else silencio <= '0'; end if; altavoz <= onda or silencio; -- puerta OR para generar onda del sonido end process generadorSonido; registroLetra: process(rst,clk,ldLetra,clLetra) begin if(rst = '0')then letra <= (others => '0'); elsif(clk'event and clk = '1' ) then if (clLetra = '1') then letra <= (others => '0'); elsif (ldLetra = '1') then letra <= scancode; end if; end if; end process registroLetra; end Behavioral;

gpl-3.0

3633647b11a440478f2fc2cd4612c004

preusser/q27

src/vhdl/PoC/fifo/fifo.pkg.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler -- Martin Zabel -- Patrick Lehmann -- -- Package: VHDL package for component declarations, types and functions -- associated to the PoC.fifo namespace -- -- Description: -- ------------------------------------ -- For detailed documentation see below. -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library poc; use PoC.utils.all; package fifo is -- Minimal FIFO with single clock to decouple enable domains. component fifo_glue generic ( D_BITS : positive -- Data Width ); port ( -- Control clk : in std_logic; -- Clock rst : in std_logic; -- Synchronous Reset -- Input put : in std_logic; -- Put Value di : in std_logic_vector(D_BITS - 1 downto 0); -- Data Input ful : out std_logic; -- Full -- Output vld : out std_logic; -- Data Available do : out std_logic_vector(D_BITS - 1 downto 0); -- Data Output got : in std_logic -- Data Consumed ); end component; -- Minimal Local-Link-FIFO with single clock and first-word-fall-through mode. component fifo_ll_glue generic ( D_BITS : positive; FRAME_USER_BITS : natural; REGISTER_PATH : boolean ); port ( clk : in std_logic; reset : in std_logic; -- in port sof_in : in std_logic; data_in : in std_logic_vector(D_BITS downto 1); frame_data_in : in std_logic_vector(imax(1, FRAME_USER_BITS) downto 1); eof_in : in std_logic; src_rdy_in : in std_logic; dst_rdy_in : out std_logic; -- out port sof_out : out std_logic; data_out : out std_logic_vector(D_BITS downto 1); frame_data_out : out std_logic_vector(imax(1, FRAME_USER_BITS) downto 1); eof_out : out std_logic; src_rdy_out : out std_logic; dst_rdy_out : in std_logic ); end component; -- Simple FIFO backed by a shift register. component fifo_shift generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive -- Minimum FIFO Size in Words ); port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Writing Interface put : in std_logic; -- Write Request din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data ful : out std_logic; -- Capacity Exhausted -- Reading Interface got : in std_logic; -- Read Done Strobe dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data vld : out std_logic -- Data Valid ); end component; -- Full-fledged FIFO with single clock domain using on-chip RAM. component fifo_cc_got generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers STATE_REG : boolean := false; -- Registered Full/Empty Indicators OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Global Reset and Clock rst, clk : in std_logic; -- Writing Interface put : in std_logic; -- Write Request din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data full : out std_logic; estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0); -- Reading Interface got : in std_logic; -- Read Completed dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data valid : out std_logic; fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0) ); end component; component fifo_dc_got_sm generic ( D_BITS : positive; MIN_DEPTH : positive); port ( clk_wr : in std_logic; rst_wr : in std_logic; put : in std_logic; din : in std_logic_vector(D_BITS - 1 downto 0); full : out std_logic; clk_rd : in std_logic; rst_rd : in std_logic; got : in std_logic; valid : out std_logic; dout : out std_logic_vector(D_BITS - 1 downto 0)); end component; component fifo_ic_got generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Write Interface clk_wr : in std_logic; rst_wr : in std_logic; put : in std_logic; din : in std_logic_vector(D_BITS - 1 downto 0); full : out std_logic; estate_wr : out std_logic_vector(imax(ESTATE_WR_BITS - 1, 0) downto 0); -- Read Interface clk_rd : in std_logic; rst_rd : in std_logic; got : in std_logic; valid : out std_logic; dout : out std_logic_vector(D_BITS - 1 downto 0); fstate_rd : out std_logic_vector(imax(FSTATE_RD_BITS - 1, 0) downto 0) ); end component; component fifo_cc_got_tempput generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers STATE_REG : boolean := false; -- Registered Full/Empty Indicators OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Global Reset and Clock rst, clk : in std_logic; -- Writing Interface put : in std_logic; -- Write Request din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data full : out std_logic; estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0); commit : in std_logic; rollback : in std_logic; -- Reading Interface got : in std_logic; -- Read Completed dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data valid : out std_logic; fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0) ); end component; component fifo_cc_got_tempgot is generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers STATE_REG : boolean := false; -- Registered Full/Empty Indicators OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Global Reset and Clock rst, clk : in std_logic; -- Writing Interface put : in std_logic; -- Write Request din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data full : out std_logic; estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0); -- Reading Interface got : in std_logic; -- Read Completed dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data valid : out std_logic; fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0); commit : in std_logic; rollback : in std_logic ); end component; end fifo; package body fifo is end fifo;

agpl-3.0

071b4b9fde2537657c6babb8da0bb25c

jcowgill/cs-dacs-robot

Common/AsyncRxTest.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY AsyncRxTest IS END AsyncRxTest; ARCHITECTURE behavioral OF AsyncRxTest IS COMPONENT AsyncRx PORT ( Q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); UPDATE : OUT STD_LOGIC; RX : IN STD_LOGIC; CLK : IN STD_LOGIC; CLR : IN STD_LOGIC); END COMPONENT; SIGNAL Q : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL UPDATE : STD_LOGIC; SIGNAL RX : STD_LOGIC; SIGNAL CLK : STD_LOGIC; SIGNAL CLR : STD_LOGIC; BEGIN UUT: AsyncRx PORT MAP( Q => Q, UPDATE => UPDATE, RX => RX, CLK => CLK, CLR => CLR ); clk_process : PROCESS BEGIN -- Clock signal (4 MHz) CLK <= '0'; WAIT FOR 125ns; CLK <= '1'; WAIT FOR 125ns; END PROCESS; tb_process : PROCESS BEGIN -- Reset CLR <= '1'; WAIT FOR 1000ns; CLR <= '0'; -- Send some crap over WAIT FOR 2000ns; RX <= '1'; WAIT FOR 1us; RX <= '0'; WAIT FOR 4us; RX <= '1'; WAIT FOR 4us; RX <= '0'; WAIT FOR 4us; RX <= '0'; WAIT FOR 4us; RX <= '0'; WAIT FOR 4us; RX <= '1'; WAIT FOR 4us; RX <= '1'; WAIT; END PROCESS; END;

apache-2.0

fdf560b394e966f402265b1010dc3ea2

wltr/cern-fgclite

critical_fpga/src/rtl/cf/xf.vhd

------------------------------------------------------------------------------- --! @file xf.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-08 --! @brief Auxiliary FPGA communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.xf_pkg.all; use work.nf_pkg.all; --! @brief Entity declaration of xf --! @details --! This component handles the NanoFIP communication and provides a --! synchronization mechanism with the field-bus cycle. entity xf is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Auxiliary FPGA interface --! @{ --! Inputs xf_i : in xf_in_t; --! Outputs xf_o : out xf_out_t; --! @} --! @name Internal interface --! @{ --! Millisecond strobe indicating start of cycle ms_0_strobe_i : in std_ulogic; --! Millisecond strobe indicating start of second millisecond ms_1_strobe_i : in std_ulogic; --! Commands command_i : in nf_command_t; --! @} --! @name Auxiliary FPGA data --! @{ --! DIM analogue data dim_o : out std_ulogic_vector(19 downto 0); --! DIM analogue data enable dim_en_o : out std_ulogic; --! DIM trigger number dim_trig_num_o : out std_ulogic_vector(3 downto 0); --! DIM latched trigger dim_trig_lat_o : out std_ulogic; --! DIM unlatched trigger dim_trig_unl_o : out std_ulogic; --! Backplane type backplane_type_o : out std_ulogic_vector(7 downto 0); --! Backplane type enable backplane_type_en_o : out std_ulogic; --! XF and PF versions version_xfpf_o : out std_ulogic_vector(7 downto 0); --! XF and PF versions enable version_xfpf_en_o : out std_ulogic; --! Single-event upset (SEU) count seu_count_o : out std_ulogic_vector(7 downto 0); --! Single-event upset (SEU) count enable seu_count_en_o : out std_ulogic; --! 1-wire scan busy ow_scan_busy_o : out std_ulogic; --! @} --! @name DIM data --! @{ --! Address dim_addr_i : in std_ulogic_vector(6 downto 0); --! Read enable dim_rd_en_i : in std_ulogic; --! Data output dim_data_o : out std_ulogic_vector(15 downto 0); --! Data output enable dim_data_en_o : out std_ulogic; --! @} --! @name One-wire data --! @{ --! Address ow_addr_i : in std_ulogic_vector(5 downto 0); --! Read enable ow_rd_en_i : in std_ulogic; --! Data output ow_data_o : out std_ulogic_vector(79 downto 0); --! Data output enable ow_data_en_o : out std_ulogic); --! @} end entity xf; --! RTL implementation of xf architecture rtl of xf is --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal ow_scan_busy : std_ulogic; signal dim_trigger : std_ulogic; signal dim_reset : std_ulogic; signal ow_scan : std_ulogic; signal ow_bus_select : std_ulogic_vector(2 downto 0); --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal xf_rx_data_0 : std_ulogic_vector(41 downto 0); signal xf_rx_data_en_0 : std_ulogic; signal xf_rx_error_0 : std_ulogic; signal xf_rx_data_1 : std_ulogic_vector(83 downto 0); signal xf_rx_data_en_1 : std_ulogic; signal xf_rx_error_1 : std_ulogic; signal dim_addr : std_ulogic_vector(6 downto 0); signal ow_addr : std_ulogic_vector(5 downto 0); --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- xf_o.dim_trig <= dim_trigger; xf_o.dim_rst <= dim_reset; xf_o.ow_trig <= ow_scan; xf_o.ow_bus_select <= ow_bus_select; backplane_type_o <= "00" & xf_rx_data_0(13 downto 8); backplane_type_en_o <= xf_rx_data_en_0; version_xfpf_o <= xf_rx_data_0(7 downto 0); version_xfpf_en_o <= xf_rx_data_en_0; seu_count_o <= xf_rx_data_0(21 downto 14); seu_count_en_o <= xf_rx_data_en_0 when dim_addr = "0000000" else '0'; ow_scan_busy_o <= ow_scan_busy; dim_o <= xf_rx_data_0(41 downto 22); dim_en_o <= xf_rx_data_en_0 and xf_rx_data_0(36); -- only save analogue values dim_trig_num_o <= xf_rx_data_0(41 downto 38); dim_trig_lat_o <= xf_rx_data_en_0 when (xf_rx_data_0(37) = '1' and xf_rx_data_0(36 downto 34) = "010") else '0'; dim_trig_unl_o <= xf_rx_data_en_0 when (xf_rx_data_0(37) = '1' and xf_rx_data_0(36) = '1') else '0'; --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- dim_addr <= xf_rx_data_0(41 downto 38) & xf_rx_data_0(36 downto 34); ow_addr <= "00" & xf_rx_data_1(83 downto 80); --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! 1st 3-wire serial receiver from XF xf_rx_inst_0 : entity work.serial_3wire_rx generic map ( data_width_g => 42) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, rx_frame_i => xf_i.rx_frame(0), rx_bit_en_i => xf_i.rx_bit_en(0), rx_i => xf_i.rx(0), data_o => xf_rx_data_0, data_en_o => xf_rx_data_en_0, error_o => xf_rx_error_0); --! 2nd 3-wire serial receiver from XF xf_rx_inst_1 : entity work.serial_3wire_rx generic map ( data_width_g => 84) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, rx_frame_i => xf_i.rx_frame(1), rx_bit_en_i => xf_i.rx_bit_en(1), rx_i => xf_i.rx(1), data_o => xf_rx_data_1, data_en_o => xf_rx_data_en_1, error_o => xf_rx_error_1); --! DIM pages dim_page_inst : entity work.two_port_ram_tmr generic map ( depth_g => 128, width_g => 16) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_addr_i => dim_addr, wr_en_i => xf_rx_data_en_0, wr_data_i => xf_rx_data_0(37 downto 22), wr_done_o => open, wr_busy_o => open, rd_addr_i => dim_addr_i, rd_en_i => dim_rd_en_i, rd_data_o => dim_data_o, rd_data_en_o => dim_data_en_o, rd_busy_o => open); --! One-wire pages ow_page_inst : entity work.two_port_ram_tmr generic map ( depth_g => 64, width_g => 80) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_addr_i => ow_addr, wr_en_i => xf_rx_data_en_1, wr_data_i => xf_rx_data_1(79 downto 0), wr_done_o => open, wr_busy_o => open, rd_addr_i => ow_addr_i, rd_en_i => ow_rd_en_i, rd_data_o => ow_data_o, rd_data_en_o => ow_data_en_o, rd_busy_o => open); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin dim_trigger <= '0'; ow_scan_busy <= '0'; dim_reset <= '0'; ow_scan <= '0'; ow_bus_select <= (others => '0'); end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else if ms_0_strobe_i = '1' then dim_reset <= command_i.dim_reset; ow_scan <= command_i.ow_scan; ow_bus_select <= command_i.ow_bus_select; end if; if ms_0_strobe_i = '1' then dim_trigger <= '1'; elsif ms_1_strobe_i = '1' then dim_trigger <= '0'; end if; if command_i.ow_scan = '1' then ow_scan_busy <= '1'; elsif xf_rx_data_en_1 = '1' then ow_scan_busy <= '0'; end if; end if; end if; end process regs; end architecture rtl;

mit

ed4dac5ab55122f4d30ba064ffdb0c9b

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_regs_fwd.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RzJL2iY+lsIKJHAms45sQoVX5/BWGrwOSRVd1oSzKijFLXWuK4Ya4nlDxl1+AQQ7gYBsfbcplmqd TtZbmWFQqQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OlMuqjxAV7Z3Pb2A7dAymKGjbZIPS4tMmQPeuNSTg2p1m82+/S9aL7l1+hYB/dkn6GMD/BNomE0p VKMF6LRxozjB/qH3C4OdCZzAvo9s3pzmlTXPw8TjqdtApRK97I+7JVMOZFy327uwr4h2WDQi+iL0 keaHOsIv65PyFgZQQLw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZjqpAwCPVFyEp/SV7jKXnTsZE/+P4teJSObrKmr4OJEO1DKZyppaHotd2+wP4PB8yFBFhBAFfht O63C5xWNxC+SHDV+pJSRNnssPF5GwaEU/F+mT53vJcyjDW68jgKXCX7l6oSYuLEKB7ljzclB54M5 uyBME51et4n3X2xdvwAj2RgWJ3b9guRh955hmePMA/FBTUd3QBpSqb/b/AhGbauWyNo8tMwwHXft 5UoMS0UNCQW10w7uG11oV9SW+lF0Zb4S5J0MvikysDH28u6OHcTukXeKtxGs8sqcjqrhfvvCW0ft 7t/iCN2fMVz7cGVrDtTFN5gjZ7V7jZoRCqz2aw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block TpLA+fh2xo6W6z3HuI8JP/p8Q3+l0Rvt0I3KNxXbJvgSRjhOerFRv/fBX0zqjRmQ3tHmmRltgCeG FT6/0H+Wcgz5NCZuOrb0dlnXSh48ramTPR8MYtvqrqhB4bwVEuGx4Q3E6cud54JmuSktfkEnD+hy v4NJFKNIQ4QQ1OZJ0pw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block dVq52ILv85JnlOR/qZTJAZCxpdASwT1GsamY9XCBV+29Ybz0aPwql+DHP7X0BAQSJuM3Cb+4Qolk GG/D/TBK7MYrCBp/orV9K+ye0+Y0Ex4lt7rj8WdMRX96ISFTHSR00+9QVZ6+oenckGSrpRG6LyNC FsWkzhyazQ9FM5j1//Stt8YEW3AqmuKeW3UTEO60CCak+21UFR/xheu9db/O/wY2UKn8XcQwVY3T AAdvDhJmtb/skZzNpHCjAkwfWRzkYqg+YwlRHNFCmsq5vqsJ2nzmhI95IKKtSURvwhvDWJMubmM7 o2Wy7eB0wxBKTmgEVKDDvL4pMr7NK/1Pa6Oswg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328) `protect data_block FmtYf5Y5ir/EfoVVtyaQBoFKG1Gh2hH+OVsExr37nhDtC0943v5XBTk9T4c9EW0WqmxQLX6fUADK hIeF8XdZ6pTvU0uWKVPxTQeUCVLH8DW485dGPDDTc3OdxYMYtNz/EKtOmGVpU9Vb3ThntwWjotJ1 kgLMrdfEYwjP/lc2N2FjicVFCTImS8qy6DAvJZPaTOcx3Kl8Dv9D1U0u/gBFG3Sr5E1TWdxGFZvq 1ryVqeCcqiggbriuDa9rZaJUjsoTQ996vx7ak8OC/RRGQi1Tj3VNUd38fbRcyn6U7UY3UgRyTF/z 8qbnj6KmqVofdcFt15sc0nXvBssX5eVq31JSZWX00w4GeQAbrHsJH5E4GEfUrb/Rr1pflUCFRBhl aQCy1OKfhfvYzz6xt+DOnzDDb6HYgzrST3+zbSmmXdYbTde4cNkcwpWE8MWvjoba8blTq/ZRShst 7xptH35QbIgMdDL65jkg28ZmpcFZHlOsIlgge5uwcLX2rjft7rpi511K6moYGphaesxa/LMMToP0 zmciyoFVbOV+FcFtxUgWuFQXAr6+BJjiO4P6W7t3AxO9wkK+hAHLbBv49wyqv/ai/BN/E5ETNzwh k8mXY3uM+CzScbmW8Vc5+q3pLVP/bb9l82270LjsAC/OzuNp40ruB9YBWYvb5QAyWJkwGMsVXRnE Q2/rYffZ8y81enSjNtKsqHkoqmvSlCpAU8iYRqCIFKxqbxDCAJoaY7b8l1T3QuoXtyuUavxh1ikF SlHvgs2715ncNeJeV+crAjNiD1KBTHC5zfFpqHkr2tJ+y+4OUosIMvg9emDV2RErjQmkrtuP24kL iiOvpkbyWoWIk8b+zeoi50qGZu9aF4WBEO7o9gbhhNx9V8reTM+OfxPy9l0kWVq244Zr0BZyAxF2 SjNOSZ+dDy9vUiyjLX4ekjBZKdA5n9HgtXQQsuRErgOsqDd4LJY47CYRl+psv6Bw97hJXoGLvqle lz3/v1PINTSH0d87dCrqzCdpvuffnRcm7gT2PjnHAXQ/aFwlMyOT5clUFWOtFR5+JskRuGN0TlLf +A9qMU11N9kUq+PYI1kVqqNz/fqp+3MKhKKwXFMt6HmsiD5bbSuFSLhwrCS1uUE9Gi71oLg5cdH1 3lWEzRGWgetKUJzTIsygO2ftCWmYHg8LVWGOT0cvnsaGFgij/vTab34NCEshh4o/WdPzyJ02mR5l Foob0Ukue12d08FXyp6jOhu3n95jHCLs93kOiBi7F/A3hpAVrztTQpx4secKyaajAYt4Rt7k3hws oKC906124ivpe12uSVLEYIbIYWyV03cnAQWx8OHKqpxiyS7tA1OLAXM5WpLUbJJUmUd+g3cpZsn0 2x/PN6gJuu6/wQCfgDzK77hqrlw69ScAJOi2ccz3xwmZfqnhxW9Za2tMskO/jV/itSq2Dh11N3Hl LI0aQbSektUe99Q4n8koMeT9BW32tvB6peKbkAOUrahEme8Z/16IxqFwZm3HprJW9B8ALNjMCDuB 5+z8F06QaFGs2PmnomAQw+zyGc5H78r/q4WsRn9Zf1QlKsryd4M7reGHnNxMbEtbhlAqVUrpMuCL r1STIjsZom/gQ+iKrzP8PkoAnbi7bPHSWIMsaIKLm7Jq/IgssNAohVMFDQxb0cLaiZuZK6i72Lg9 hFXEHXl4n3J3S1B8U8mE/LqXICp5YA5BZEDXpjhG4yEkPdoVFEOmFPXk+sHKjoj+zXyoyqCQnt0f M7OlY7Fu59ZK+UGHk13+TuMVsTIhD3GE3mRjKbcqW7MC/J3q4N9nkR4XWtkfmLwTzyYCUV8fUDcJ 5uFXBVSfACMS1E4BdLUdZCytZVLsMPcuuPIt0kQ088KmYkqiA01DNC5XPHFANa2Oh4lWFjz/sW/v 0Kk3nYQO67NgMZJOSFtjahnm4He+t/LAmi+vBJUvl5NWqXd5vJlLdJebEQCCd90oxlh9UsxepdB2 g6F0ifwsq8iUERpr2n0h5OGY79lhX1RGg8WH3TNE3gsdCZZZkrFnwMRigN/g6yW47ZA9RfcdPPqA FPwsemRCXuTdEor1FUBQpE7n8Ax/tP8vrmPf8WSZHi9a0PoR0/zCXKtiFdP4jh+8tmArhyKVTVqt 0wu5EjErZq42aUxnPpw20EiUxjqTKgj2NpWbjINlUnHsjG4KZF7648jsBLBScwHq1B8NvNcEmGOT BWkoBsqFETjj5eoATAydZkOokYxZGfg13bV9SaQsfr41Zh2Et2YfXsviBf9bRCZfGQQDKQWyeYFN 2bG2UqYPok623awwyWJVhmqfsa7b9GOXC8VqqNLCbV44rbsLKN3lxj5O7SaRvSgBtKVsYPJ7venM RKljm75RK78OjTTYbiI/qNWKGbmXcG+1+WV5i5uuxzMjuwqagyBvUI1mQN6enESQBgH8BpGGVvvk UKBET8mbybguMfTyLYtLBVxFkhyUIr2w82bRJMh0X7Y/XNDMHVyeyJmn3d5stPqSUVSHg+0sqJwp rKxaBFTM6NsV4yZhoZzpeO1xQhvuzjrKJLu6s8uQ6vPobUjTEgFGauR2U8A8RKMObOh0zR3/EEaC Hzq5ooxLyGOAZhLJ3jJKxNEAGDpnZFkxTNDdJfdg5S5xhOFMS2ON6jrA0vTW5Mu/jJj1yX90aaUt gEfy0geeODjOPqiXGN+OBQiLMx7SEKNRvIsSfV4aDE/beRH1j4pna8DfU3KGxHoe/j32NH9hbLQZ o7GkZt/FXDLoTiprbIlphtOvF2jAj0N9Nnwhiv3mJXUjCqpDTDGRHweawkhQ9toOshVV11HxWCu+ NPYHGWvawcGICgNGDicFk2qi/3tbU3tXFbz9Pk7lsmXBJQHBEe55ZNVsK1ByojHFh5YNGUTUAkrg ZUafqgKN/AWG2MH0d2RJt2mJ4f7lCPsNIW5feXd8LulIxNTy2FE+aTGi8JKUgphLyljaNaMwaTOy JWhXZJkmL+NhJ9QRguGKcdPYJBDlpmjfqWK+0Kk4FObhCAtPGXAVYHZNhqEu/sKJItES+cgsRO1s Qlb4utypJWMCwiT3A0zzDMWQyF++za721V3R/G0zEWM/mRE7ROGnQt8WwPDVb03oDC/SYxa9UM+e zbDlRdGum6mPl5KzVCcopnfFI0vPMuRr5rQ3/5LBeu5Fq7S+SgXak2P9EiVmL+qkf4fgn4Dw9Jf1 h2na+c5u5PevlGQrGBP6IAozmGmndTkCTRBqM1gTsOumOBff0Lhw4OdLaofSH6PyQ8rozrKKMSsc 8K1dhzKNM+EYBz0cFsRkyhasI5V5F7DPCsLLkX2U1/pWZy0Sz1ky8vFrTlBMHheBtLsVUA9UDUfS 29RzH5hL1xVNDusthfvPOFjxU2wAcNcmIHhkwDHkOFEzq4v90OpxtS1xRI/u1Gb4E7T5ltaZ7F0E woRlkGwtS6vcpfwCGDaXwJzDxONq3++DA8p6JADn9nmz0coP+ovEpRvm159IxGJl+SRbkck3EtbX +2JhwVAuJiBekw1WrobhFD7Ed7VYYfcR4YD0qoAj4mrgrLXs9k3pU8aDkzrCRzJn90qds5gWCxcC 5kkhMdHiq3cKC/qOtd81c3Cr48xHNaZc7xS1Bcq1dNp7lbmd8gNYlkHlElliAlFIIg4Mtm5iUfSE UHWFG3P/Cp3RinEuirgTvCWwpYil32TgVspQa4J0IFpO9M/g4BSXr/Qh3e89qE6y7T6eZdWjr5Zm eeH8agP7fHzZIuMD02FCLgKPUhcj3EGrr1lBpE7fjFvQvwOysqEFge1dQexFDYYkrXSPJ8jcBiNk o4TUNY4l1C71sGv46mi9jPHxsw4pLdyOCpVPdLEYG3Rz01JbrPkpoj7/halo+ypzbqFSBetXEPP2 yfb1l4vNhWkV9WeDeVTNFZ4Kh8iJbqEFt2DST0y+qn1m67bfQjx4/1wpPcJJZIBoDIRsi/j821gA FTHiJVgsS2lSIJhL6yYlKPAOvQTMSOm6WlItLRUxcYmu9h/Wazzhcog2ZtQWZirBt5yhUFamqnge ZdgYilBTlfVB+vuNlvGG6NNRdXq9d68k7aNc24uUBJYkTn8T2XILhw2rGlKtQ2p5Br0uoJibQiH1 fNYAfgQC/DS+zu9lNGkTd9h9ItTQ+ktHuFY7P5fbaWHcrT2ALCV2Rzl/efHSKGTOJBs8Bm0ucf2y lzru+TApISmKPazPpKBk4mwuNenVwxr0zQ7Je1VNELpUE2oYWT1/3DqllOjsofgr1EXANuyjF4F+ t9VqbNUfS4KAHRp9ajmAieiScldmqjYWkPYNXs2gk3vUeaShTcCK1hx0mY6TAHasu7Io91DU7dlA 1V89DuEE2hgvHd/CKDIqIzgFzYLQULqsF6RzVucZhEuCdz9KiaNumyHgMKzBjWiOplKt901MRwad V3sMg2iKkaQT7PLXAfWCDeVvc+ScqzoTFpM5qSQCt1CAjHZLxgsWhClhsL3cc7KNVHobLWfmCljG lgNI+cvUjlcfhpL7/BFr6Gfd4/e4TBAoSjpNzeT5KIKCGhHCv2WIcNBkPYEUnL9l54uF5mh7OQ6l nCuh+Yyc4ryX12KsNT4vJaXFfu4zPKIGGCENTIShyDBaKmilqcL1NoJvmlvQVnRYyKvjdQ/lhQAH whm6SKEcbTviYyE/B9eJQFUy9CcQAyvGuT55jz6m+e/XK6OOCxERiKFAXDYys1AAJE8DK90nmhU1 5bAzbDpgXfYxcO4qLBTtM3NNoyHCk8E5Bh1yW4CWSA6qprPR19fxFz5EsSPF8a6NxueuIMD85fxb 2YdXxzGy5/XgZ68EQJVFBixF9k3/VmsR4Prz+oF6fq5CARpLy9qTlbH5SMyqU0uqLhN/Sle5oRUU sxcJRI65ooFrPWDfmXbZvNMWN83Q/a17yd+WAWGP4RrYAoWRp1MEnlvM8qOmASdO1gL1PsUS4fXN 6dHyGuvQuZRVJHoGSPcgYmrpi6A5Hzyrt0o1NS5a2RHOiisCPSqDxRfhnXab5z7Njk3WTbz8dVoI TPXo4CNeUI9zkdY/crW0yxMWDmqTQfq60yIFXBxfDDIhIYJ5S4e7mFutDUvhavi3uBtCn1BOGsYz aGrF/cbCkK+btou6bIKD+46+3rfaFV21qDrEm3SaMoSduhv3OJMJURBpYf5PRabuPhYbr0oK09QH eJZQgxk9dPK6g63/SsmU4/hWuhad3Q1FCoCKVgrsbEsLRTEbnh6licPbeox32jUIZUQzcODi6Qtn IqUrLcMkGcBx52P9aODiEwGN0XuazZTbKm5O6N1QwNZZsA+pLVKClyfSJWcy8Beaxu1P/i0eDDbv LzEE9lSqTGsdcCsVt/AndvnMpv66ODsQMyReZ26ca3InmKRIVQfOfV+Ivkdiu9RBiiZFXdWej2yF YYsOHl6KIG06LPzG5yLIZS+aXV6ozjAaEsCFbhmWwbDJLHlWFogUgRX+ZZwT1lj3AAF1g3EruI5E LmYPyC7fNWCl5xWcChd8yMD5WRHEmPRHOaTxP2yjs10ns8j6CtSUaVKirppdJE2URc5t/GwHUgAA 9q2/jTsUWWMUzMglRFqs6mBjdB8vGeOWs6zXC/iviBP+4gBfh8fXaTPbS7VcoQLQ20iVXD6p4Gn/ mxbR2pMz9H6WAODNtNU3+dl/pIDi0FBEP4+UZCdcuxTQXqB4y3cs84K2FI26TR8U0eC24t6Rko8v q18bPFa/1tb35niO13qyqKuC7+7uxNrI7A9rnm0FAV4EN5bofn6GEzJJ1V1jPsVvahCiW69MOryo eT11H2D3you1jcvko/rZBL3IjHQd1RBSQCg2x1B8/qiiRozsjPOkNyNZsZ6rfwl9EQGTRKcH4yX7 PkmqlnJLRwwfWjJWAGJdiFOfVKNsnl53C/FHPrIbw+QOuxwg1v/UdwloSi2NxBBi9GvQgLU1QBYv lmcF37qy7v46J37oN8csyCpiGelSepBTp+NcvRSzq+kW5QwobHxFFl/lb2e9caYutsTe+Vr7JDYU HKCFTOQrl7EpXFnPiAWi7N3X9BY9WSr1jPDi/8pdrzdHgSGfZVS96Ilv5jV4PVNR7nm7dHIxz+Nx ZhqLbshRwbjIDkeQKKlaxbCKPf3MFSDxFKuyhnLU51y2BFu9tGvULKq14rrI6ib5VpgyS02m3NWk oqaMFlfLlnAP07voPpxlrN2JXXREhHZw4pSCeWW7O1oMQCSX1qvDToWmKGkkWEGO6OxYnYhlTmFx ZnsNCsa4dPj51yYGxJL3Nj0gScRslFzUz0PwXUEGEgc0/osEiGH2+zougUOQ8UGmxEgaQI8sW5Ee O39id+j73aMSCVHYUaCwtze9xRAn2HOGF4zdqZyH//p0sZMbPpCrTqRbb1MfAk2grYWktv3N/ZsD TMat2QtLeayGcT5ZThfpYbaya+CgCTffLmmL2Ruw/AtpykybO4oATggSYeIghobkYemubtJNViWX AlSrEXjMQDQYH6/tie73lw4itsjqr/a8W2fZSz0MaWBK6R9nUvVJjBIKP3+l/A82qPkYFhSt+f88 u/ZQy/0T12BNIB2Xowx3M/GGbzjmWM9H9rnYqN3cs7/rbA6Ausq82bH1HJQQ0mKNOWofm3hLuJaC 7TcjUjTxzGUiih8i1E2yEnBodqOP8Tyrh2GO0U5/tcEBrmf9Zwqw1/A5ilfMmqYCQCEowrUD+2md jLgiCr9owt0PjczDVo/SKqSIr7+TlrhrC1ZhvKCBprZIE4xuFUHmgHJsm5xcVEyOXiXMQVqTZ4Fz dV/O0Lq/QmQpjd7fr9ZIRcxvGiGI8H8UpDElYTONm8J/nzp9qj8F4koIUk+d1Par6yOZ5UdXccp+ nbqnD0grPy5EpZdKaVhqbNi95zSwm07vpsxMvr+pTgoDItK3sqO6ODnoC1zm2hneA9T9CgBTzbs/ ddi+DOxTP3HoshCQ9UITyFnrfAyr4zkAdQ8pIw5qxUIGRZhM3dP58hTgsqdA1vTAMSm5T4GdmOYq wXUtLyk8JlOqxn3kGcLrllt4RI22HrLnwySwt7m9/X5wF9GX9AY4UZKTjGemaLz9CqcXYjT9H8Sm BvEpbkI/seDibjltuP+x6QJFa0APlyj3NKA7 `protect end_protected

mit

5628c9748a9da4787e3742e4396f7da9

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_SubInteger_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

ed8c1617dc984620f833ba689baadd3b

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_2_CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

ab8ce06cae016799d6e4c0ae204ff97f

joalcava/sparcv8-monocicle

Test_PC.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Test_PC IS END Test_PC; ARCHITECTURE behavior OF Test_PC IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT pc PORT( clk : IN std_logic; rst : IN std_logic; address : IN std_logic_vector(31 downto 0); sig : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal address : std_logic_vector(31 downto 0) := (others => '0'); --Outputs signal sig : std_logic_vector(31 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: pc PORT MAP ( clk => clk, rst => rst, address => address, sig => sig ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. address <= x"FFFFFFFF"; wait for 200 ns; rst <= '1'; wait for 100 ns; rst <= '0'; wait for 50 ns; address <= x"11111111"; -- insert stimulus here wait; end process; END;

gpl-3.0

b5db93745d1cf7d9eef425a3489fd2b2

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_Atomic.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant ATOMIC_IMPLEMENT : natural := 1; constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

f34c83881c698be50b33d8048d3d1d53

malkadi/FGPU

RTL/FGPU_definitions.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is -- Begin of Configurable FGPU Parameters ----------------------------------------------------------------{{{ constant N_CU_W : natural := 0; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; -- Bitwidth of # of words the global read bus cache -> CUs constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; -- Bitwidth of the fifo buffer for the data read out of the cache. A fifo is implemented in each CU. constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst (only 5 is tested intensively, 4 & 6 should work but needs testing) constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; -- Implements a priority pipeline for the stations of the global memory controller which prioritizes waiting stations when more time is elapsed constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV (only 3 was tested, i.e. 8 PEs/CU) -- Floating-point hardware support: constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; -- End of Configurable FGPU Parameters ------------------------------------------------------------------}}} constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; -- one fifo to store data read out of global memory for each tag manager (now, only 0 makes sense) constant GMEM_N_BANK_W : natural := 1; -- Bitwidth of the number of words of a single AXI data interface, i.e. the global memory bus constant ID_WIDTH : natural := 6; -- Bitwidth of the read & write id channels of AXI4 constant PHASE_W : natural := 3; -- # of clock cycles when executing the same instruction on the a CV (only 3 is tested) constant CV_SIZE : natural := 2**CV_W; -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

7bf93125aeb39845261492008274a30d