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malkadi/FGPU | RTL/floating_point/fadd_fsub.vhd | 1 | 10,878 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY fadd_fsub IS
PORT (
aclk : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END fadd_fsub;
ARCHITECTURE fadd_fsub_arch OF fadd_fsub IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fadd_fsub_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 11,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 1,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => s_axis_operation_tvalid,
s_axis_operation_tdata => s_axis_operation_tdata,
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END fadd_fsub_arch;
| gpl-3.0 | 7ec009ef245c034a20100e54443ff73c | 0.63348 | 3.231729 | false | false | false | false |
preusser/q27 | src/vhdl/queens/expand_blocking.vhdl | 1 | 3,953 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
entity expand_blocking is
generic(
N : positive;
L : positive
);
port(
pre : in std_logic_vector(4*L*log2ceil(N)-2 downto 0);
bh : out std_logic_vector(L to N-L-1);
bv : out std_logic_vector(L to N-L-1);
bu : out std_logic_vector(0 to 2*N-4*L-2);
bd : out std_logic_vector(0 to 2*N-4*L-2)
);
end entity;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of expand_blocking is
constant M : positive := log2ceil(N);
-- Decoded Placement
-- Frame Indices: 0 - west, 1 - north, 2 - east, 3 - south
subtype tRow is std_logic_vector(0 to N-1);
type tEdge is array(0 to L-1) of tRow;
type tFrame is array(0 to 3) of tEdge;
-- Normalized Pre-Placement with full first Coordinate West(0)
signal pp : std_logic_vector(0 to 4*L*log2ceil(N)-1);
signal frame : tFrame;
begin
-- Normalize the Pre-Placement
pp <= '0' & pre;
-- Placement Decoder
genFrame: for i in tFrame'range generate
genEdge: for j in tEdge'range generate
genAlias: for k in 0 to L-1 generate
frame(i)(j)(k) <= frame((i+3) mod 4)(k)(N-1-j);
end generate genAlias;
genCells: for k in L to N-1 generate
constant BASE : natural := (i*L+j)*M;
begin
frame(i)(j)(k) <= 'X' when Is_X(pp(BASE to BASE+M-1)) else
'1' when to_integer(unsigned(pp(BASE to BASE+M-1))) = k else
'0';
end generate genCells;
end generate genEdge;
end generate genFrame;
-- compute combined blocking
process(frame)
variable h, v, u, d : std_logic;
begin
-- Horizontal and Vertical
for i in L to N-L-1 loop
h := '0';
v := '0';
for j in 0 to L-1 loop
h := h or frame(0)(j)(i) or frame(2)(j)(N-1-i);
v := v or frame(1)(j)(i) or frame(3)(j)(N-1-i);
end loop;
bh(i) <= h;
bv(i) <= v;
end loop;
-- Up and Down: 0 .. N-2L-1
for i in 0 to N-2*L-1 loop
u := '0';
d := '0';
for j in 0 to L-1 loop
u := u or frame(2)(j)(N-1-2*L-i+j) or frame(3)(j)(2*L+i-j);
d := d or frame(0)(j)(2*L+i-j) or frame(3)(j)(N-1-2*L-i+j);
end loop;
bu(i) <= u;
bd(i) <= d;
end loop;
-- Up and Down: 0 .. N-2L-1
for i in N-2*L to 2*N-4*L-2 loop
u := '0';
d := '0';
for j in 0 to L-1 loop
u := u or frame(0)(j)((i-(N-1-2*L))+j) or frame(1)(j)(2*N-2*L-2-i-j);
d := d or frame(1)(j)((i-(N-1-2*L))+j) or frame(2)(j)(2*N-2*L-2-i-j);
end loop;
bu(i) <= u;
bd(i) <= d;
end loop;
end process;
end rtl;
| agpl-3.0 | 9434a74a3feb897e0162ed5e5f98ea5c | 0.555527 | 3.134814 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_fsqrt_uitofp_max.vhd | 1 | 23,658 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data por0s
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 8;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FSQRT_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | e1bda023edb0999061fc00a0a8ffbe7d | 0.56818 | 3.721567 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_wb_controller.vhd | 1 | 10,257 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_wb_controller |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_wb_controller.vhd |
-- |
-- Description The unit generates the "User Interface WISHBONE" signal ACK, nanoFIP's answer to |
-- the user's STBs. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 21/01/2011 |
-- Version v0.01 |
-- Depends on wf_production |
---------------- |
-- Last changes |
-- 21/01/2011 v0.011 EG changed registering |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_wb_controller
--=================================================================================================
entity wf_wb_controller is port(
-- INPUTS
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; -- WISHBONE clock
wb_rst_i : in std_logic; -- WISHBONE reset
wb_stb_i : in std_logic; -- WISHBONE strobe
wb_cyc_i : in std_logic; -- WISHBONE cycle
wb_we_i : in std_logic; -- WISHBONE write enable
wb_adr_id_i : in std_logic_vector (2 downto 0); -- 3 first bits of WISHBONE address
-- OUTPUTS
-- Signal from the wf_production_unit
wb_ack_prod_p_o : out std_logic; -- response to a write cycle
-- latching moment of wb_dat_i
-- nanoFIP User Interface, WISHBONE Slave output
wb_ack_p_o : out std_logic); -- WISHBONE acknowledge
end entity wf_wb_controller;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_wb_controller is
signal s_wb_ack_write_p, s_wb_ack_read_p, s_wb_stb_r_edge_p : std_logic;
signal s_wb_we_synch, s_wb_cyc_synch : std_logic_vector (2 downto 0);
signal s_wb_stb_synch : std_logic_vector (3 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Input Synchronizers --
---------------------------------------------------------------------------------------------------
-- Synchronization of the WISHBONE control signals: stb, cyc, we.
WISHBONE_inputs_synchronization: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
s_wb_stb_synch <= (others => '0');
s_wb_cyc_synch <= (others => '0');
s_wb_we_synch <= (others => '0');
else
s_wb_stb_synch <= s_wb_stb_synch (2 downto 0) & wb_stb_i;
s_wb_cyc_synch <= s_wb_cyc_synch (1 downto 0) & wb_cyc_i;
s_wb_we_synch <= s_wb_we_synch (1 downto 0) & wb_we_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_wb_stb_r_edge_p <= (not s_wb_stb_synch(3)) and s_wb_stb_synch(2);
---------------------------------------------------------------------------------------------------
-- ACK outputs Generation --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Generation of the wb_ack_write_p signal (acknowledgement from WISHBONE Slave of the write cycle,
-- as a response to the master's storbe). The 1 wb_clk-wide pulse is generated if the wb_cyc and
-- wb_we are asserted and the WISHBONE input address corresponds to an address in the Produced
-- memory block.
s_wb_ack_write_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_we_synch (2) = '1') and
(s_wb_cyc_synch(2) = '1') and
(wb_adr_id_i = "010")) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Generation of the wb_ack_read_p signal (acknowledgement from WISHBONE Slave of the read cycle,
-- as a response to the master's strobe). The 1 wb_clk-wide pulse is generated if the wb_cyc is
-- asserted, the wb_we is deasserted and the WISHBONE input address corresponds to an address in
-- the Consumed memory block.
s_wb_ack_read_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_cyc_synch(2) = '1') and
(s_wb_we_synch(2) = '0') and
(wb_adr_id_i(2 downto 1) = "00")) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Output registrers
WB_ACK_Output_Reg: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then
wb_ack_p_o <= '0';
wb_ack_prod_p_o <= '0';
else
wb_ack_p_o <= s_wb_ack_read_p or s_wb_ack_write_p;
wb_ack_prod_p_o <= s_wb_ack_write_p;
end if;
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit | df4b226c34c50bceba6de3762129dacc | 0.303695 | 5.421247 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_decoder.vhd | 2 | 24,873 | `protect begin_protected
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
`protect data_block
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`protect end_protected
| mit | b88805ba380927fd850c88de23296379 | 0.943593 | 1.869026 | false | false | false | false |
joalcava/sparcv8-monocicle | control_unit.vhd | 1 | 12,657 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity control_unit is
Port (
op : in STD_LOGIC_VECTOR (1 downto 0);
op2 : in STD_LOGIC_VECTOR (2 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
cond: in STD_LOGIC_VECTOR (3 downto 0);
Aluop: out STD_LOGIC_VECTOR (5 downto 0);
wrenDM: out STD_LOGIC;
RFSource: out STD_LOGIC_VECTOR(1 downto 0);
PCSource: out STD_LOGIC_VECTOR(1 downto 0);
RFdest: out STD_LOGIC;
write_enable : out STD_LOGIC);
end control_unit;
architecture arq_UnidadControl of control_unit is
begin
process(op,op2,op3,icc,cond)
begin
if(op = "01") then --CALL
PCSource<= "01";--PC + disp30
write_enable <= '1';--Permitimos guardar datos en RF (Valor actual de PC)
RFSource<= "10";--Elegimos PC
RFdest<='1';--Se debe elegir el O7 en el RF
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
if(op= "00") then
if(op2= "010") then
case cond is
when "1000" => --Branch Always
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
when "1001" => --Branch on Not Equal
if(not(icc(2)) = '1') then --not z
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when "0001" => --Branch on Equal
if(icc(2) = '1') then
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when "1010" => --Branch on Greater
if((not(icc(2) or (icc(3) xor icc(1)))) = '1') then --not(Z or (N xor V))
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when "0010" => --Branch on Less or Equal
if((icc(2) or (icc(3) xor icc(1))) = '1') then --Z or (N xor V)
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when "1011" => -- Branch on Greater or Equal
if((not(icc(3) xor icc(1))) = '1') then --not (N xor V)
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when "0011" => --Branch on Less
if((icc(3) xor icc(1)) = '1') then -- (N xor V)
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when others =>
PCSource<= "11";--PC + PCaddress
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end case;
elsif(op2 = "100") then --NOP
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF (Valor actual de PC)
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
elsif(op = "10")then
case op3 is
when "000000" => -- ADD
Aluop <= "000000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010000" => --ADDcc
Aluop <= "001000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "001000" => --ADDX
Aluop <= "001010";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "011000" => --ADDXcc
Aluop <= "001011";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000100" => -- SUB
Aluop <= "000001";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010100" => -- SUBcc
Aluop <= "001001";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "001100" => -- SUBX
Aluop <= "001100";
write_enable <= '1';
RFSource<= "00";
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "011100" => -- SUBXcc
Aluop <= "001101";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000001" => -- AND
Aluop <= "000011";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010001" => -- ANDcc
Aluop <= "001111";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000101" => --ANDN
Aluop <= "000110";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
when "010101" => --ANDNcc
Aluop <= "010001";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000010" => -- OR
Aluop <= "000010";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010010" => -- ORcc
Aluop <= "001110";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000110" => --ORN
Aluop <= "000101";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010110" => --ORNcc
Aluop <= "010010";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000011" => -- XOR
Aluop <= "000100";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010011" => -- XORcc
Aluop <= "010000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000111" => -- XNOR
Aluop <= "000111";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010111" => -- XNORcc
Aluop <= "010011";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "111100" => -- SAVE
Aluop <= "000000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "111101" => -- RESTORE
Aluop <= "000000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "111000" => --JMPL
Aluop <= "000000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "10";
PCSource<= "00";--PC calculada
RFdest<='0';--Se debe elegir el nrd en el RF
when "100101" => --SLL
Aluop <= "010100";
write_enable <= '0';
wrenDM <= '0';
RFSource<= "10";
PCSource<= "00";
RFdest<='0';
when "100110" => --SRL
Aluop <= "010101";
write_enable <= '0';
wrenDM <= '0';
RFSource<= "10";
PCSource<= "00";
RFdest<='0';
when others => --En otros casos desconocidos
Aluop <= "111111";
write_enable <= '0';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
end case;
elsif(OP = "11") then
case op3 is
when "000100" => --SW
Aluop <= "000000";
write_enable <= '0';
wrenDM <= '1';--Habilitamos la escritura en el DM
RFSource <= "00";
PCSource <= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000000" => --LW
Aluop <= "000000";
write_enable <= '1';--Habilitamos la escritura en el RF
wrenDM <= '0';--Si no habilitamos la escritura, es porque vamos a leer
RFSource <= "01";
PCSource <= "11";--Se salta a PC + 1
RFdest <='0';--Se debe elegir el nrd en el RF
when others =>
Aluop <= "000000";
write_enable <= '0';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
end case;
end if;
end if;
end process;
end arq_UnidadControl;
| gpl-3.0 | f4536f822ec50b8eadf707bf992ac871 | 0.547523 | 3.460087 | false | false | false | false |
chrreisinger/OpenVC | document/Masterarbeit/src/astTransformation2To.vhd | 1 | 152 | case expression is
when choiceList1 => target := expr1;
when choiceList2 => target := expr2;
...
when choiceListN => target := exprN;
end case;
| gpl-3.0 | 8fe3cbeb3b6149de8030514f5269c77b | 0.664474 | 3.534884 | false | false | false | false |
kennethlyn/fpga-image-example | hdl_nodes/adder_2_to_1/adder_2_to_1.srcs/sources_1/dyplo_user_logic_adder_2_to_1.vhd | 1 | 4,369 | -- File: dyplo_user_logic_adder_2_to_1.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
--
-- Disclaimer
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Topic Embedded Products B.V., and to the maximum
-- extend permitted by applicable law:
--
-- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no
-- warranty, express or implied, with respect to the capability of Dyplo. All
-- warranties of any type, express or implied, including the warranties of
-- merchantability, fitness for a particular purpose and non-infringement of
-- third party rights are expressly disclaimed.
--
-- 2. Topic�s maximum total liability shall be limited to general money
-- damages in an amount not to exceed the total amount paid for in the year
-- in which the damages have occurred. Under no circumstances including
-- negligence shall Topic be liable for direct, indirect, incidental, special,
-- consequential or punitive damages, or for loss of profits, revenue, or data,
-- that are directly or indirectly related to the use of, or the inability to
-- access and use Dyplo and related services, whether in an action in contract,
-- tort, product liability, strict liability, statute or otherwise even if
-- Topic has been advised of the possibility of those damages.
--
-- This copyright notice and disclaimer must be retained as part of this file at all times.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library dyplo_hdl_node_lib;
use dyplo_hdl_node_lib.hdl_node_package.all;
use dyplo_hdl_node_lib.hdl_node_user_params.all;
entity dyplo_user_logic_adder_2_to_1 is
generic(
INPUT_STREAMS : integer := 4;
OUTPUT_STREAMS : integer := 4
);
port(
-- Processor bus interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(15 DOWNTO 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Streaming input interfaces
cin_tdata : in cin_tdata_ul_type;
cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tlevel : in cin_tlevel_ul_type;
-- Streaming output interfaces
cout_tdata : out cout_tdata_ul_type;
cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
end dyplo_user_logic_adder_2_to_1;
architecture rtl of dyplo_user_logic_adder_2_to_1 is
type sm_calc_type is (RECEIVE, SEND);
signal sm_calc : sm_calc_type;
begin
process(dab_clk)
begin
if(rising_edge(dab_clk)) then
if(dab_rst = '1') then
cout_tdata <= (others => (others => '0'));
cout_tvalid <= (others => '0');
cin_tready <= (others => '0');
sm_calc <= RECEIVE;
else
case(sm_calc) is
when RECEIVE =>
if(cin_tvalid(0) = '1' and cin_tvalid(1) = '1') then
cin_tready(1 downto 0) <= "11";
cout_tdata(0) <= cin_tdata(0) + cin_tdata(1);
cout_tvalid(0) <= '1';
sm_calc <= SEND;
end if;
when SEND =>
cin_tready(1 downto 0) <= "00";
if(cout_tready(0) = '1') then
cout_tvalid(0) <= '0';
sm_calc <= RECEIVE;
end if;
end case;
end if;
end if;
end process;
end rtl;
| gpl-2.0 | c928851de6da0b24291434f98a6e8d74 | 0.612474 | 3.686391 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | d62f3309561709e3f7ab9f0e089e1052 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fslt_2AXI_2CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 1;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 1ebb6504a9727d5ed52dcfdeb3b66410 | 0.567707 | 3.729005 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip_wb_if.vhd | 1 | 11,200 | -------------------------------------------------------------------------------
--! @file nanofip_wb_if.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2013-10-24
--! @brief NanoFIP Wishbone bus interface.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--! @brief Entity declaration of nanofip_wb_if
--! @details
--! This component provides an interface for the NanoFIP Wishbone bus and
--! performs error detection for read and write cycles.
entity nanofip_wb_if is
generic (
--! Number of clock cycles before watchdog times out
watchdog_max_g : positive := 32);
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name NanoFIP packet control signals
--! @{
--! VAR1_RDY from NanoFIP
var1_rdy_i : in std_ulogic;
--! VAR1_ACC to NanoFIP
var1_acc_o : out std_ulogic;
--! VAR2_RDY from NanoFIP
var2_rdy_i : in std_ulogic;
--! VAR2_ACC to NanoFIP
var2_acc_o : out std_ulogic;
--! VAR3_RDY from NanoFIP
var3_rdy_i : in std_ulogic;
--! VAR3_ACC to NanoFIP
var3_acc_o : out std_ulogic;
--! @}
--! @name NanoFIP Wishbone bus
--! @{
--! Clock
wb_clk_o : out std_ulogic;
--! Reset (active-high)
wb_rst_o : out std_ulogic;
--! Address
wb_addr_o : out std_ulogic_vector(9 downto 0);
--! Data input
wb_data_i : in std_ulogic_vector(7 downto 0);
--! Data output
wb_data_o : out std_ulogic_vector(7 downto 0);
--! Write enable
wb_we_o : out std_ulogic;
--! Strobe
wb_stb_o : out std_ulogic;
--! Cycle
wb_cyc_o : out std_ulogic;
--! Acknowledge
wb_ack_i : in std_ulogic;
--! @}
--! @name Receiver interface
--! @{
--! Signal that a VAR1 has been received
rx_var1_rdy_o : out std_ulogic;
--! Signal that a VAR2 has been received
rx_var2_rdy_o : out std_ulogic;
--! Select which VAR to access, 0 = VAR1, 1 = VAR2
rx_var_sel_i : in std_ulogic;
--! Read address
rx_addr_i : in std_ulogic_vector(6 downto 0);
--! Read enable
rx_en_i : in std_ulogic;
--! Read data output
rx_data_o : out std_ulogic_vector(7 downto 0);
--! Read data output enable
rx_data_en_o : out std_ulogic;
--! @}
--! @name Transmitter interface
--! @{
--! Indicate if VAR3 can be written
tx_rdy_o : out std_ulogic;
--! Write address
tx_addr_i : in std_ulogic_vector(6 downto 0);
--! Write enable
tx_en_i : in std_ulogic;
--! Write data input
tx_data_i : in std_ulogic_vector(7 downto 0);
--! Signal end of write operation
tx_done_o : out std_ulogic;
--! @}
--! @name Error flags
--! @{
--! Read-write collision
err_rw_coll_o : out std_ulogic;
--! Interface busy
err_bsy_o : out std_ulogic;
--! VAR not ready
err_not_rdy_o : out std_ulogic;
--! Wishbone bus acknowledge timeout
err_timeout_o : out std_ulogic);
--! @}
end entity nanofip_wb_if;
--! RTL implementation of nanofip_wb_if
architecture rtl of nanofip_wb_if is
---------------------------------------------------------------------------
-- Types and Constants
---------------------------------------------------------------------------
--! Most significant address bits for VAR1 and VAR2
constant var1_var2_addr_msbs_c : std_ulogic_vector(1 downto 0) := "00";
--! Most significant address bits for VAR3
constant var3_addr_msbs_c : std_ulogic_vector(2 downto 0) := "010";
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal var1_acc : std_ulogic;
signal var2_acc : std_ulogic;
signal var3_acc : std_ulogic;
signal addr : std_ulogic_vector(9 downto 0);
signal we : std_ulogic;
signal stb_cyc : std_ulogic;
signal rx_data : std_ulogic_vector(7 downto 0);
signal rx_data_en : std_ulogic;
signal tx_rdy : std_ulogic;
signal tx_data : std_ulogic_vector(7 downto 0);
signal tx_done : std_ulogic;
signal err_rw_coll : std_ulogic;
signal err_bsy : std_ulogic;
signal err_not_rdy : std_ulogic;
signal err_timeout : std_ulogic;
signal watchdog : unsigned(integer(ceil(log2(real(watchdog_max_g)))) - 1 downto 0);
--! @}
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
signal var1_rdy : std_ulogic;
signal var2_rdy : std_ulogic;
signal rx_not_rdy : std_ulogic;
signal tx_not_rdy : std_ulogic;
signal rx_en : std_ulogic;
signal tx_en : std_ulogic;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
var1_acc_o <= var1_acc;
var2_acc_o <= var2_acc;
var3_acc_o <= var3_acc;
wb_clk_o <= clk_i;
wb_rst_o <= rst_syn_i;
wb_addr_o <= addr;
wb_data_o <= tx_data;
wb_we_o <= we;
wb_stb_o <= stb_cyc;
wb_cyc_o <= stb_cyc;
rx_var1_rdy_o <= var1_rdy;
rx_var2_rdy_o <= var2_rdy;
rx_data_o <= rx_data;
rx_data_en_o <= rx_data_en;
tx_rdy_o <= tx_rdy;
tx_done_o <= tx_done;
err_rw_coll_o <= err_rw_coll;
err_bsy_o <= err_bsy;
err_not_rdy_o <= err_not_rdy;
err_timeout_o <= err_timeout;
---------------------------------------------------------------------------
-- Signal Assignments
---------------------------------------------------------------------------
-- Check for errors when variable is read
rx_not_rdy <= rx_en_i and (not var1_rdy_i) when rx_var_sel_i = '0' else
rx_en_i and (not var2_rdy_i) when rx_var_sel_i = '1' else
'0';
-- Check for errors when variable is written
tx_not_rdy <= tx_en_i and (not var3_rdy_i);
-- Check if variable to be read is ready
rx_en <= rx_en_i and var1_rdy_i and (not tx_en_i) when rx_var_sel_i = '0' else
rx_en_i and var2_rdy_i and (not tx_en_i) when rx_var_sel_i = '1' else
'0';
-- Check if variable to be written is ready
tx_en <= tx_en_i and var3_rdy_i and (not rx_en_i);
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! Detect rising edge of VAR1_RDY flag
var1_edge_detect_inst : entity work.edge_detector
generic map (
init_value_g => '0',
edge_type_g => 0,
hold_flag_g => false)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => '1',
ack_i => '1',
sig_i => var1_rdy_i,
edge_o => var1_rdy);
--! Detect rising edge of VAR2_RDY flag
var2_edge_detect_inst : entity work.edge_detector
generic map (
init_value_g => '0',
edge_type_g => 0,
hold_flag_g => false)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => '1',
ack_i => '1',
sig_i => var2_rdy_i,
edge_o => var2_rdy);
---------------------------------------------------------------------------
-- Registering
---------------------------------------------------------------------------
intf : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
var1_acc <= '0';
var2_acc <= '0';
var3_acc <= '0';
addr <= (others => '0');
we <= '0';
stb_cyc <= '0';
rx_data <= (others => '0');
rx_data_en <= '0';
tx_rdy <= '0';
tx_data <= (others => '0');
tx_done <= '0';
err_rw_coll <= '0';
err_bsy <= '0';
err_not_rdy <= '0';
err_timeout <= '0';
watchdog <= to_unsigned(0, watchdog'length);
end procedure reset;
begin -- process intf
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
-- Default values for enable flags
rx_data_en <= '0';
tx_done <= '0';
-- Signal if VAR3 can be written
tx_rdy <= var3_rdy_i and (not stb_cyc);
-- Detect read-write collision
err_rw_coll <= rx_en_i and tx_en_i;
-- Detect access attempts during running cycle
err_bsy <= stb_cyc and (rx_en_i or tx_en_i);
-- Detect access attempt when NanoFIP is not ready
err_not_rdy <= rx_not_rdy or tx_not_rdy;
-- Default value for timeout error
err_timeout <= '0';
if stb_cyc = '0' then
-- Wishbone cycle is idle
if rx_en = '1' then
-- Read operation
addr <= var1_var2_addr_msbs_c & rx_var_sel_i & rx_addr_i;
we <= '0';
stb_cyc <= '1';
var1_acc <= not rx_var_sel_i;
var2_acc <= rx_var_sel_i;
elsif tx_en = '1' then
-- Write operation
addr <= var3_addr_msbs_c & tx_addr_i;
tx_data <= tx_data_i;
we <= '1';
stb_cyc <= '1';
var3_acc <= '1';
end if;
else
-- Wishbone cycle is running
-- Increment watchdog
watchdog <= watchdog + 1;
if wb_ack_i = '1' then
-- Received acknowledge
if we = '0' then
-- Save data after a read cycle
rx_data <= wb_data_i;
rx_data_en <= '1';
else
-- Signal success after a write cycle
tx_done <= '1';
end if;
-- Stop cycle
stb_cyc <= '0';
we <= '0';
var1_acc <= '0';
var2_acc <= '0';
var3_acc <= '0';
watchdog <= to_unsigned(0, watchdog'length);
elsif to_integer(watchdog) = watchdog_max_g - 1 then
-- Watchdog timed out
err_timeout <= '1';
stb_cyc <= '0';
we <= '0';
var1_acc <= '0';
var2_acc <= '0';
var3_acc <= '0';
watchdog <= to_unsigned(0, watchdog'length);
end if;
end if;
end if;
end if;
end process intf;
end architecture rtl;
| mit | 38faa933baeb8ff9a4fd6d58477da5b7 | 0.455714 | 3.682999 | false | false | false | false |
malkadi/FGPU | RTL/floating_point/fslt.vhd | 1 | 10,483 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY fslt IS
PORT (
aclk : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END fslt;
ARCHITECTURE fslt_arch OF fslt IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fslt_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 1,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 1,
C_RESULT_FRACTION_WIDTH => 0,
C_COMPARE_OPERATION => 1,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 8,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END fslt_arch;
| gpl-3.0 | d36c93ea028ffd7a627de4728c6a6ce0 | 0.628064 | 3.228519 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_dualram_512x8_clka_rd_clkb_wr.vhd | 1 | 8,330 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_dualram_512x8_clka_rd_clkb_wr |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_dualram_512x8_clka_rd_clkb_wr.vhd |
-- |
-- Description The unit adds a layer over the dual port 512x8 memory, by disabling writing from |
-- one side and reading from the other. Finally from port A only reading is possible |
-- and from port B only writing. |
-- Commented in the unit is the memory triplication. Precision RadTol makes the |
-- triplication automatically; in Synplify the comments have to be removed. With the |
-- triplication each incoming byte is written at the same position in the three |
-- memories, whereas each outgoing one is the outcome of a majority voter. |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 10/12/2010 |
-- Version v0.02 |
-- Depends on dualram_512x8.vhd |
---------------- |
-- Last changes |
-- 12/2010 v0.02 EG code cleaned-up+commented |
-- 11/2011 v0.03 EG removed generics! addr+data lgth already defined at the |
-- dualram_512x8 |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_dualram_512x8_clka_rd_clkb_wr
--=================================================================================================
entity wf_dualram_512x8_clka_rd_clkb_wr is port(
-- INPUTS
-- Inputs concerning port A
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (8 downto 0);
-- Inputs concerning port B
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (8 downto 0);
data_portb_i : in std_logic_vector (7 downto 0);
write_en_portb_i : in std_logic;
-- OUTPUT
-- Output concerning port A
data_porta_o : out std_logic_vector (7 downto 0));
end wf_dualram_512x8_clka_rd_clkb_wr;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture syn of wf_dualram_512x8_clka_rd_clkb_wr is
signal s_one, s_rwB : std_logic;
signal s_zeros : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_one <= '1';
s_zeros <= (others => '0');
s_rwB <= not write_en_portb_i;
---------------------------------------------------------------------------------------------------
-- Port A used for reading only, port B for writing only.
-- for triplication: G_memory_triplication: for I in 0 to 2 generate
DualRam : dualram_512x8
port map(
DINA => s_zeros,
ADDRA => addr_porta_i,
RWA => s_one,
CLKA => clk_porta_i,
DINB => data_portb_i,
ADDRB => addr_portb_i,
RWB => s_rwB,
CLKB => clk_portb_i,
RESETn => s_one,
DOUTA => data_porta_o, -- for triplication: s_data_o_A_array(I)
DOUTB => open);
-- end generate;
---------------------------------------------------------------------------------------------------
-- for triplication: Combinatorial Majority_Voter
-- for triplication: Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
-- (s_data_o_A_array(1) and s_data_o_A_array(2)) or
-- (s_data_o_A_array(2) and s_data_o_A_array(0));
end syn;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit | 5d2fb7d10873c84b587dd4891eb0f7d1 | 0.307923 | 6.452363 | false | false | false | false |
preusser/q27 | src/vhdl/top/xilinx/vc707_queens_uart.vhdl | 1 | 4,883 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity vc707_queens_uart is
generic (
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 360;
COUNT_CYCLES : boolean := false;
CLK_FREQ : FREQ := 200 MHz;
CLK_DIVA : positive := 5; -- Choose so that CLK_FREQ/CLK_DIVA*CLK_MULA
CLK_MULA : positive := 31; -- is smaller than but close to 1800 MHz
CLK_DIVB : positive := 5;
BAUDRATE : positive := 115200;
SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte
);
port (
clk_p : in std_logic;
clk_n : in std_logic;
rx : in std_logic;
tx : out std_logic;
rts_n : in std_logic;
cts_n : out std_logic;
-- Fan Control
VC707_FanControl_PWM : out std_logic
);
end vc707_queens_uart;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library PoC;
architecture rtl of vc707_queens_uart is
-- Global Control
constant CLK_COMP_FREQ : FREQ := CLK_FREQ * CLK_MULA / CLK_DIVA / CLK_DIVB;
constant CLK_SLOW_FREQ : FREQ := CLK_FREQ * CLK_MULA / CLK_DIVA / 100;
signal clk200 : std_logic; -- 200 MHz Input Clock
signal clk_comp : std_logic; -- Computation Clock
signal clk_slow : std_logic; -- Slow Interface Clock
signal rst : std_logic;
begin
-----------------------------------------------------------------------------
-- Generate Global Controls
blkGlobal: block is
signal clkfb : std_logic; -- Feedback Clock
signal clk_compu : std_logic; -- Unbuffered Synthesized Clock
signal clk_slowu : std_logic; -- Unbuffered Synthesized Clock
begin
clk_in : IBUFGDS
port map(
O => clk200,
I => clk_p,
IB => clk_n
);
pll : PLLE2_BASE
generic map (
CLKIN1_PERIOD => to_real(to_time(CLK_FREQ), 1 ns),
DIVCLK_DIVIDE => CLK_DIVA,
CLKFBOUT_MULT => CLK_MULA,
CLKOUT0_DIVIDE => CLK_DIVB,
CLKOUT1_DIVIDE => 100,
STARTUP_WAIT => "true"
)
port map (
CLKIN1 => clk200,
CLKFBIN => clkfb,
RST => '0',
CLKOUT0 => clk_compu,
CLKOUT1 => clk_slowu,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKFBOUT => clkfb,
LOCKED => open,
PWRDWN => '0'
);
comp_buf : BUFG
port map (
I => clk_compu,
O => clk_comp
);
slow_buf : BUFH
port map (
I => clk_slowu,
O => clk_slow
);
-- No Reset
rst <= '0';
end block blkGlobal;
-----------------------------------------------------------------------------
-- Fan Control
fan : entity PoC.io_FanControl
generic map (
CLOCK_FREQ => CLK_SLOW_FREQ
)
port map (
Clock => clk_slow,
Reset => '0',
Fan_PWM => VC707_FanControl_PWM,
TachoFrequency => open
);
----------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_uart
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES,
CLK_FREQ => integer(to_real(CLK_COMP_FREQ, 1 Hz)),
BAUDRATE => BAUDRATE,
SENTINEL => SENTINEL
)
port map (
clk => clk_comp,
rst => rst,
rx => rx,
tx => tx,
avail => open
);
cts_n <= rts_n;
end rtl;
| agpl-3.0 | 74d86dd246ac751df86bfc31394b746f | 0.518329 | 4.032205 | false | false | false | false |
preusser/q27 | src/vhdl/top/altera/de4_queens_uart.vhdl | 1 | 7,770 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Modifications to this work must be clearly identified and must leave
-- the original copyright statement and contact information intact. This
-- license notice may not be removed.
--
-- This design is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity de4_queens_uart is
generic (
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 125;
COUNT_CYCLES : boolean := false;
CLK_FREQ : FREQ := 50 MHz;
CLK_MUL : positive := 5;
CLK_DIV : positive := 1;
BAUDRATE : positive := 115200;
SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte
);
port (
osc_50_bank2 : in std_logic;
cpu_reset_n : in std_logic;
uart_rxd : in std_logic;
uart_txd : out std_logic;
uart_rts : in std_logic;
uart_cts : out std_logic;
fan_ctrl : out std_logic
);
end de4_queens_uart;
library IEEE;
use IEEE.numeric_std.all;
library altera_mf;
use altera_mf.all;
architecture rtl of DE4_queens_uart is
-- Altera PLL Component
component altpll
generic (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
port (
clk : out std_logic_vector (9 downto 0);
inclk : in std_logic_vector (1 downto 0)
);
end component;
-- Global Control
constant CLK_PLL_FREQ : FREQ := CLK_FREQ * CLK_MUL / CLK_DIV;
signal pll_clkout : std_logic_vector(9 DOWNTO 0);
signal pll_clkin : std_logic_vector(1 DOWNTO 0);
signal rst : std_logic;
signal pwm_counter : unsigned(21 downto 0) := (others => '0');
begin
-- PWM generator (cooling fan)
process(osc_50_bank2) begin
if rising_edge(osc_50_bank2) then
pwm_counter <= pwm_counter + 1;
end if;
end process;
-- Solver clock PLL
pll: altpll generic map (
bandwidth_type => "AUTO",
clk0_divide_by => CLK_DIV,
clk0_duty_cycle => 50,
clk0_multiply_by => CLK_MUL,
clk0_phase_shift => "0",
inclk0_input_frequency => integer(to_real(to_time(CLK_FREQ), 1 ps)),
intended_device_family => "Stratix IV",
lpm_hint => "CBX_MODULE_PREFIX=solver_pll",
lpm_type => "altpll",
operation_mode => "NO_COMPENSATION",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
using_fbmimicbidir_port => "OFF",
width_clock => 10
) port map (
inclk => pll_clkin,
clk => pll_clkout
);
----------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_uart
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES,
CLK_FREQ => integer(to_real(CLK_PLL_FREQ, 1 Hz)),
BAUDRATE => BAUDRATE,
SENTINEL => SENTINEL
)
port map (
clk => pll_clkout(0),
rst => rst,
rx => uart_rxd,
tx => uart_txd,
snap => open,
avail => open
);
pll_clkin <= "0" & osc_50_bank2;
rst <= not cpu_reset_n;
uart_cts <= uart_rts;
fan_ctrl <= pwm_counter(21);
end rtl;
| agpl-3.0 | 1a25e0be42f283be32c13901c1a5beba | 0.550193 | 3.808824 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_8Stations_2AXI_2CACHE_W.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 8;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 1;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | eddcf87c5bf2c73c01f99df57f32bf8a | 0.567707 | 3.729005 | false | false | false | false |
dtysky/LD3320_AXI | hdl/LD3320_AXI_v1_0_S00_AXI.vhd | 1 | 22,043 | ----¼Ä´æÆ÷0£ºÖ¸Áî----
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----¼Ä´æÆ÷2£º³õʼ»¯RAMдÈëÓÃ----
----¼Ä´æÆ÷3£º·µ»ØRAMдÈë״̬----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity LD3320_AXI_v1_0_S00_AXI is
generic (
-- Users to add parameters here
constant Cmd_Start:std_logic_vector(31 downto 0):=x"00000001";
constant Cmd_Rqu:std_logic_vector(31 downto 0):=x"00000002";
constant Re_Success:std_logic_vector(7 downto 0):=x"01";
constant Re_Fail:std_logic_vector(7 downto 0):=x"02";
constant Re_Wait:std_logic_vector(7 downto 0):=x"03";
constant Ram_Init:std_logic_vector(7 downto 0):=x"01";
constant Ram_List:std_logic_vector(7 downto 0):=x"02";
constant Ram_Stop:std_logic_vector(7 downto 0):=x"03";
constant Ram_Re_Yes:std_logic_vector(7 downto 0):=x"01";
constant Ram_Re_No:std_logic_vector(7 downto 0):=x"02";
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
inclk,inclk_n:in std_logic;
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_logic:='0';
data_voice:inout std_logic_vector(7 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end LD3320_AXI_v1_0_S00_AXI;
architecture arch_imp of LD3320_AXI_v1_0_S00_AXI is
component VOICE is
port
(
start:in std_logic;
inclk,inclk_n:in std_logic;
init_clk:in std_logic;
init_wea:in std_logic_vector(0 downto 0);
init_addr:in std_logic_vector(5 downto 0);
init_din:in std_logic_vector(15 downto 0);
list_clk:in std_logic;
list_wea:in std_logic_vector(0 downto 0);
list_addr:in std_logic_vector(7 downto 0);
list_din:in std_logic_vector(7 downto 0);
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_logic:='0';
data_voice:inout std_logic_vector(7 downto 0);
voice_result:out std_logic_vector(7 downto 0):=x"00";
reco_rqu:in std_logic:='0';
reco_fin:out std_logic:='0';
voice_state:out std_logic_vector(7 downto 0):=x"00";
voice_ram:out std_logic_vector(15 downto 0):=x"0000"
);
end component;
signal inclk_s,inclk_n_s:std_logic;
signal voice_start:std_logic:='0';
signal voice_result:std_logic_vector(7 downto 0);
signal voice_rqu:std_logic;
signal voice_fin:std_logic;
signal init_clk:std_logic;
signal init_wea:std_logic_vector(0 downto 0);
signal init_addr:std_logic_vector(5 downto 0);
signal init_din:std_logic_vector(15 downto 0);
signal list_clk:std_logic;
signal list_wea:std_logic_vector(0 downto 0);
signal list_addr:std_logic_vector(7 downto 0);
signal list_din:std_logic_vector(7 downto 0);
signal voice_state:std_logic_vector(7 downto 0):=x"00";
signal voice_ram:std_logic_vector(15 downto 0):=x"0000";
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg0_last :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2_last :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
inclk_s<=inclk;
inclk_n_s<=inclk_n;
list_clk<=inclk_n_s;
init_clk<=inclk_n_s;
VOICEX:VOICE
port map
(
start=>voice_start,
inclk=>inclk_s,
inclk_n=>inclk_n_s,
clk_voice=>clk_voice,
n_wr=>n_wr,
n_cs=>n_cs,
n_rd=>n_rd,
n_rst=>n_rst,
n_int=>n_int,
add_en=>add_en,
data_voice=>data_voice,
init_clk=>init_clk,
init_wea=>init_wea,
init_addr=>init_addr,
init_din=>init_din,
list_clk=>list_clk,
list_wea=>list_wea,
list_addr=>list_addr,
list_din=>list_din,
voice_result=>voice_result,
reco_rqu=>voice_rqu,
reco_fin=>voice_fin,
voice_state=>voice_state,
voice_ram=>voice_ram
);
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg2 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg2 <= slv_reg2;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if S_AXI_ARESETN = '0' then
reg_data_out <= (others => '1');
else
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end if;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
ram_wr:process(inclk_s)
variable con_wr:integer range 0 to 3:=0;
begin
if rising_edge(inclk_s) then
slv_reg2_last<=slv_reg2;
if slv_reg2 /= slv_reg2_last then
case slv_reg2(31 downto 24) is
when Ram_Init=>
init_wea<="1";
init_addr<=slv_reg2(21 downto 16);
init_din<=slv_reg2(15 downto 0);
con_wr:=0;
when Ram_List=>
list_wea<="1";
list_addr<=slv_reg2(23 downto 16);
list_din<=slv_reg2(7 downto 0);
con_wr:=0;
when Ram_Stop=>
init_wea<="0";
list_wea<="0";
con_wr:=0;
when others=>
init_wea<=init_wea;
init_addr<=init_addr;
init_din<=init_din;
list_wea<=list_wea;
list_addr<=list_addr;
list_din<=list_din;
end case;
else
case slv_reg2(31 downto 24) is
when Ram_Init=>
if con_wr=3 then
init_wea<="0";
slv_reg3<=slv_reg2;
slv_reg3(31 downto 24)<=Ram_Re_Yes;
else
con_wr:=con_wr+1;
slv_reg3<=slv_reg2;
slv_reg3(31 downto 24)<=Ram_Re_No;
end if;
when Ram_List=>
if con_wr=3 then
list_wea<="0";
slv_reg3<=slv_reg2;
slv_reg3(31 downto 24)<=Ram_Re_Yes;
else
con_wr:=con_wr+1;
slv_reg3<=slv_reg2;
slv_reg3(31 downto 24)<=Ram_Re_No;
end if;
when others=>
init_wea<=init_wea;
init_addr<=init_addr;
init_din<=init_din;
list_wea<=list_wea;
list_addr<=list_addr;
list_din<=list_din;
slv_reg3<=slv_reg2;
slv_reg3(31 downto 24)<=x"ff";
end case;
end if;
end if;
end process;
Cmd:process(inclk_s)
begin
if rising_edge(inclk_s) then
slv_reg0_last<=slv_reg0;
if slv_reg0 /= slv_reg0_last then
slv_reg1(15 downto 8)<=Re_Wait;
case slv_reg0 is
when Cmd_Start=>
voice_start<='1';
when Cmd_Rqu=>
voice_Rqu<='1';
when others=>
voice_start<=voice_start;
voice_Rqu<=voice_Rqu;
end case;
else
slv_reg1(7 downto 0)<=voice_result;
slv_reg1(31 downto 24)<=voice_ram(15 downto 8);
slv_reg1(23 downto 16)<=voice_state;
case voice_fin is
when '1'=>
voice_Rqu<='0';
case voice_result is
when x"FD"=>
slv_reg1(15 downto 8)<=Re_Fail;
when others=>
slv_reg1(15 downto 8)<=Re_Success;
end case;
when others=>
voice_Rqu<=voice_Rqu;
end case;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
| mit | 5baddb4fad8637eff41f8b3f27dc11d3 | 0.560132 | 3.547313 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_Atomic_4AXI.vhd | 1 | 23,372 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant N_AXI_W : natural := 2;
-- Bitwidth of # of AXI data ports
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant ATOMIC_IMPLEMENT : natural := 1;
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant FADD_DELAY : integer := 11;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | f09b2cd98ff16f70d7da5c6ea5507656 | 0.568971 | 3.706899 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_fdiv_fsqrt_8_2_1_2.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 8;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 1;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 3627509d0bd967cc382ce61ce5639691 | 0.567707 | 3.729005 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_input_block.vhd | 2 | 45,404 | `protect begin_protected
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| mit | efae6c5ba1d408afe64c700def490413 | 0.94941 | 1.844042 | false | false | false | false |
Kinxil/VHDL_Projects | Mandelbrot/FSM.vhd | 1 | 1,499 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
use IEEE.NUMERIC_STD.ALL;
entity FSM is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
b_done : in STD_LOGIC_VECTOR (7 downto 0);
stop : in std_logic;
doneVGA : in std_logic;
start : out STD_LOGIC;
startVGA : out STD_LOGIC);
end FSM;
architecture Behavioral of FSM is
type type_etat is (init, inc,finish,writing,calcul);
Signal etat_present, etat_futur : type_etat;
begin
process(clock,reset)
begin
if reset='1' then
etat_present<=init;
elsif rising_edge(clock) then
etat_present<=etat_futur;
end if;
end process;
process(etat_present, doneVGA, stop, b_done)
begin
case etat_present is
when init=> etat_futur<=inc;
when calcul=>
if stop='1' then
etat_futur<=finish;
elsif b_done=X"FF" then --all iterators are done
etat_futur<=writing;
else
etat_futur<=calcul;
end if;
when writing=>
if doneVGA='1' then --all results have been written on VGA
etat_futur<=inc;
else
etat_futur<=writing;
end if;
when inc=> etat_futur<=calcul;
when finish=>etat_futur<=init;
end case;
end process;
process(etat_present)
begin
case etat_present is
when init=> start<='0';
startVGA<='0';
when calcul=> start<='0';
startVGA<='0';
when writing=> start<='0';
startVGA<='1';
when inc=> start<='1';
startVGA<='0';
when finish=>start<='0';
startVGA<='0';
end case;
end process;
end Behavioral; | gpl-3.0 | bb10861bfc299df2885b59921e14337d | 0.662442 | 2.980119 | false | false | false | false |
viccuad/fpga-thingies | pong/pong.vhd | 1 | 20,826 | -- Hecho para ser visto con tab size = 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pong is
port (
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
clk: IN std_logic;
reset: IN std_logic; --reset activo a baja!
segs: OUT std_logic_vector (6 downto 0);
altavoz: OUT std_logic;
hSync: OUT std_logic;
Vsync: OUT std_logic;
R: OUT std_logic_vector (2 downto 0); -- alconversor D/A
G: OUT std_logic_vector (2 downto 0); -- alconversor D/A
B: OUT std_logic_vector (2 downto 0); -- alconversor D/A
outTeclaQ: OUT std_logic
);
end pong;
architecture Behavioral of pong is
component ps2KeyboardInterface
port ( clk: IN std_logic;
rst: IN std_logic;
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
data: OUT std_logic_vector (7 DOWNTO 0);
newData: OUT std_logic;
newDataAck: IN std_logic
);
end component;
type fsmEstados is (pulsadas, despulsadas);
signal estado: fsmEstados;
--señales PS2
signal newData, newDataAck: std_logic;
signal scancode: std_logic_vector (7 downto 0);
--señales VGA
signal senialHSync, senialVSync: std_logic;
signal finPixelCont: std_logic;
signal cuentaPixelCont: std_logic_vector (10 downto 0);
signal cuentaLineCont: std_logic_vector (9 downto 0);
signal comp1, comp2, comp3, comp4, comp5, comp6: std_logic;
signal Rcampo: std_logic_vector (2 downto 0);
signal Gcampo: std_logic_vector (2 downto 0);
signal Bcampo: std_logic_vector (2 downto 0);
signal Rpalas: std_logic_vector (2 downto 0);
signal Gpalas: std_logic_vector (2 downto 0);
signal Bpalas: std_logic_vector (2 downto 0);
signal Rpelota: std_logic_vector (2 downto 0);
signal Gpelota: std_logic_vector (2 downto 0);
signal Bpelota: std_logic_vector (2 downto 0);
--señales control
signal pixelPalaIzq: std_logic_vector (6 downto 0); --102 pixeles (1100110)
signal pixelPalaDer: std_logic_vector (6 downto 0); --102 pixeles
signal pixelPelotaVer: std_logic_vector (6 downto 0); --102 pixeles
signal pixelPelotaHor: std_logic_vector (7 downto 0); --153 pixeles (10011001)
signal arribaPalaIzq: std_logic;
signal abajoPalaIzq: std_logic;
signal arribaPalaDer: std_logic;
signal abajoPalaDer: std_logic;
signal horizontalPelota: std_logic; -- 1 = derecha , 0 = izquieda
signal verticalPelota: std_logic; -- 1 = abajo , 0 = arriba
signal moverPelota: std_logic;
signal cuenta1dec: STD_LOGIC_VECTOR(22 downto 0); --contador1decima
signal finCuenta1Dec: STD_LOGIC;
--señales teclas
signal teclaQ: std_logic;
signal clTeclaQ: std_logic;
signal ldTeclaQ: std_logic;
signal teclaA: std_logic;
signal clTeclaA: std_logic;
signal ldTeclaA: std_logic;
signal teclaP: std_logic;
signal clTeclaP: std_logic;
signal ldTeclaP: std_logic;
signal teclaL: std_logic;
signal clTeclaL: std_logic;
signal ldTeclaL: std_logic;
signal teclaSPC: std_logic;
signal clTeclaSPC: std_logic;
signal ldTeclaSPC: std_logic;
--señales sonido
signal ldScancode: std_logic;
signal buzz,onda,silencio: std_logic;
signal cuentaOscilador: std_logic_vector(17 downto 0);
signal clOscilador: std_logic;
--señales depuracion
signal st : std_logic_vector (2 downto 0);
begin
interfazPS2: ps2KeyboardInterface port map (
rst => reset,
clk => clk,
ps2Clk => ps2Clk,
ps2Data => ps2Data,
data => scancode,
newData => newData,
newDataAck => newDataAck
);
hSync <= senialHSync;
vSync <= senialVSync;
pantalla: process(clk, reset,cuentaPixelCont,cuentaLineCont,Rcampo,Rpelota,
Rpalas,Gcampo,Gpelota,Gpalas,Bcampo,Bpelota,Bpalas)
begin
--cont mod 1589 (pixelCont para sincronismo horizontal)
if (cuentaPixelCont = "11000110100") then
finPixelCont <= '1';
else
finPixelCont <= '0';
end if;
if(reset = '0')then
cuentaPixelCont <= (others => '0');
finPixelCont <= '0';
elsif(clk'event and clk = '1') then
if (cuentaPixelCont /= "11000110100") then --1588
cuentaPixelCont <= cuentaPixelCont + '1';
elsif (cuentaPixelCont = "11000110100") then
cuentaPixelCont <= (others => '0');
end if;
end if;
--cont mod 528 (lineCont para sincronismo vertical)
if(reset = '0')then
cuentaLineCont <= (others => '0');
elsif(clk'event and clk = '1') then
if (finPixelCont = '1' and cuentaLineCont /= "1000001111") then --527
cuentaLineCont <= cuentaLineCont + '1';
elsif (finPixelCont = '1' and cuentaLineCont = "1000001111") then
cuentaLineCont <= (others => '0');
end if;
end if;
--comparaciones
if (cuentaPixelCont > 1257) then comp1 <= '1'; else comp1 <= '0'; end if;
if (cuentaPixelCont > 1304) then comp2 <= '1'; else comp2 <= '0'; end if;
if (cuentaPixelCont <= 1493) then comp3 <= '1'; else comp3 <= '0'; end if;
if (cuentaLineCont > 479) then comp4 <= '1'; else comp4 <= '0'; end if;
if (cuentaLineCont > 493) then comp5 <= '1'; else comp5 <= '0'; end if;
if (cuentaLineCont <= 495) then comp6 <= '1'; else comp6 <= '0'; end if;
senialHSync <= comp2 nand comp3;
senialVSync <= comp5 nand comp6;
if (senialHSync = '0' or senialVSync = '0') then --no pinta
R <= "000";
G <= "000";
B <= "000";
else
R(2) <= ( (not (comp1 or comp4)) and (Rcampo(2) or Rpalas(2) or Rpelota(2)) );
R(1) <= ( (not (comp1 or comp4)) and (Rcampo(1) or Rpalas(1) or Rpelota(1)) );
R(0) <= ( (not (comp1 or comp4)) and (Rcampo(0) or Rpalas(0) or Rpelota(0)) );
G(2) <= ( (not (comp1 or comp4)) and (Gcampo(2) or Gpalas(2) or Gpelota(2)) );
G(1) <= ( (not (comp1 or comp4)) and (Gcampo(1) or Gpalas(1) or Gpelota(1)) );
G(0) <= ( (not (comp1 or comp4)) and (Gcampo(0) or Gpalas(0) or Gpelota(0)) );
B(2) <= ( (not (comp1 or comp4)) and (Bcampo(2) or Bpalas(2) or Bpelota(2)) );
B(1) <= ( (not (comp1 or comp4)) and (Bcampo(1) or Bpalas(1) or Bpelota(1)) );
B(0) <= ( (not (comp1 or comp4)) and (Bcampo(0) or Bpalas(0) or Bpelota(0)) );
end if;
-- --para pintar un damero y probar la generación de hSync y vSync:
-- R(2) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- R(1) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- R(0) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- G(2) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- G(1) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- G(0) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- B(2) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- B(1) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
-- B(0) <= ( (not (comp1 or comp4)) and (cuentaPixelCont(6) xor cuentaLineCont(5)) );
end process;
--########################## PINTAR JUEGO ###############################--
-- vertical: 479 limite de pixeles visibles
-- 120 pixeles -> 479 x= (479*1)/120 = 3.99 = aprox 4
-- 1 pixeles -> x
-- horizontal: 1257 limite de pixeles visibles
-- 153 pixeles -> 1257 x= (1257*1)/153 = 8.21 = aprox 8
-- 1 pixeles -> x
pintarCampo: process(cuentaLineCont,cuentaPixelCont)
begin
-- inicializacion
Rcampo <= "000";
Gcampo <= "000";
Bcampo <= "000";
--linea continua superior
if (cuentaLineCont(9 downto 2) = 8) then
Rcampo <= "111";
Gcampo <= "111";
Bcampo <= "111";
end if;
--red
if (cuentaPixelCont(10 downto 3) = 76) then --mitad del campo,pintar la red
if ( (cuentaLineCont(9 downto 2) > 8 and cuentaLineCont(9 downto 2) <= 16) or
(cuentaLineCont(9 downto 2) > 23 and cuentaLineCont(9 downto 2) <= 31) or
(cuentaLineCont(9 downto 2) > 39 and cuentaLineCont(9 downto 2) <= 47) or
(cuentaLineCont(9 downto 2) > 55 and cuentaLineCont(9 downto 2) <= 63) or
(cuentaLineCont(9 downto 2) > 71 and cuentaLineCont(9 downto 2) <= 79) or
(cuentaLineCont(9 downto 2) > 87 and cuentaLineCont(9 downto 2) <= 95) or
(cuentaLineCont(9 downto 2) > 103 and cuentaLineCont(9 downto 2) <= 111)
) then
Rcampo <= "111";
Gcampo <= "111";
Bcampo <= "111";
end if;
end if;
--linea continua inferior
if (cuentaLineCont(9 downto 2) = 112) then
Rcampo <= "111";
Gcampo <= "111";
Bcampo <= "111";
end if;
end process pintarCampo;
pintarPalas: process(cuentaLineCont,cuentaPixelCont,pixelPalaIzq,pixelPalaDer)
begin
-- inicializacion
Rpalas <= "000";
Gpalas <= "000";
Bpalas <= "000";
--pala izquierda
if (cuentaLineCont(9 downto 2) > 8 and cuentaLineCont(9 downto 2) < 112) then --dentro del campo:
if (cuentaPixelCont(10 downto 3) = 8) then --linea de la pala
if (cuentaLineCont(9 downto 2) >= pixelPalaIzq and
cuentaLineCont(9 downto 2) <= pixelPalaIzq+16) then--la pala en si (longitud pala= 16)
Rpalas <= "111";
Gpalas <= "111";
Bpalas <= "111";
end if;
end if;
end if;
--pala derecha
if (cuentaLineCont(9 downto 2) > 8 and cuentaLineCont(9 downto 2) < 112) then --dentro del campo:
if (cuentaPixelCont(10 downto 3) = 145) then --linea de la pala
if (cuentaLineCont(9 downto 2) >= pixelPalaDer and
cuentaLineCont(9 downto 2) <= pixelPalaDer+16) then --la pala en si (longitud pala= 16)
Rpalas <= "111";
Gpalas <= "111";
Bpalas <= "111";
end if;
end if;
end if;
end process pintarPalas;
pintarPelota: process(cuentaLineCont,cuentaPixelCont,pixelPelotaVer,pixelPelotaHor)
begin
-- inicializacion
Rpelota <= "000";
Gpelota <= "000";
Bpelota <= "000";
--pelota
if (cuentaLineCont(9 downto 2) > 8 and
cuentaLineCont(9 downto 2) < 112) then --dentro del campo:
if (cuentaLineCont(9 downto 2) = pixelPelotaVer and
cuentaPixelCont(10 downto 3) = pixelPelotaHor) then --la pelota en si
Rpelota <= "000";--Rpelota <= "111";
Gpelota <= "111";
Bpelota <= "000";--Bpelota <= "111";
end if;
end if;
end process pintarPelota;
--#########################################################################--
contadorMediaDecima: process(reset,clk,cuenta1dec) --contador mod 5.000.000 (de 0 a 4.999.999)
begin
if (cuenta1dec = "10011000100101100111111") then
finCuenta1Dec <= '1';
else
finCuenta1Dec <= '0';
end if;
if(reset = '0')then
cuenta1dec <= (others => '0');
finCuenta1Dec <= '0';
elsif(clk'event and clk = '1') then
if (cuenta1dec /= "10011000100101100111111") then
cuenta1dec <= cuenta1dec + 1;
elsif (cuenta1dec = "10011000100101100111111") then
cuenta1dec <= (others => '0');
end if;
end if;
end process contadorMediaDecima;
palas: process(clk,reset,arribaPalaIzq,abajoPalaIzq,pixelPalaIzq,arribaPalaDer,
abajoPalaDer,pixelPalaDer)
begin
--pala izq: cont mod 102 y pala der: cont mod 102
if(reset = '0')then
pixelPalaIzq <= "0110100"; --en medio: (120/2)-8 = 52
pixelPalaDer <= "0110100"; --en medio: (120/2)-8 = 52
elsif(clk'event and clk = '1') then
if (finCuenta1Dec = '1') then
--pala izq
if (arribaPalaIzq = '1' and (pixelPalaIzq > 9) and (pixelPalaIzq /= 9)) then --si orden=arriba and (todavia puede subir)
pixelPalaIzq <= pixelPalaIzq - '1';
end if;
if (abajoPalaIzq = '1' and (pixelPalaIzq < (111 -16)) and (pixelPalaIzq /= 111-16)) then --si orden=abajo and (todavia puede bajar)
pixelPalaIzq <= pixelPalaIzq + '1';
end if;
--pala der
if (arribaPalaDer = '1' and (pixelPalaDer > 9) and (pixelPalaDer /= 9)) then --si orden=arriba and (todavia puede subir)
pixelPalaDer <= pixelPalaDer - '1';
end if;
if (abajoPalaDer = '1' and (pixelPalaDer < (111 -16)) and (pixelPalaDer /= 111-16)) then --si orden=abajo and (todavia puede bajar)
pixelPalaDer <= pixelPalaDer + '1';
end if;
end if;
if (teclaSPC = '1') then
pixelPalaIzq <= "0110100"; --en medio: (120/2)-8 = 52
pixelPalaDer <= "0110100"; --en medio: (120/2)-8 = 52
end if;
end if;
end process palas;
pelota: process(clk,reset,verticalPelota,horizontalPelota,pixelPelotaHor,pixelPelotaVer)
begin
--vertical: cont mod 102 y horizontal: cont mod 153
if (reset = '0')then
pixelPelotaVer <= "0111001"; --en medio: (120/2) = aprox 57
pixelPelotaHor <= "01000110"; --en medio: (153/2) = aprox 76. la ponemos a la izq, en 70
elsif (clk'event and clk = '1') then
if(finCuenta1Dec = '1' and moverPelota = '1') then
--contador vertical
if (verticalPelota = '0') then
pixelPelotaVer <= pixelPelotaVer - '1'; --va hacia arriba
else
pixelPelotaVer <= pixelPelotaVer + '1'; --va hacia abajo
end if;
--contador horizontal
if (horizontalPelota = '0') then
pixelPelotaHor <= pixelPelotaHor - '1'; --va hacia izquierda
else
pixelPelotaHor <= pixelPelotaHor + '1'; --va hacia derecha
end if;
end if;
if (teclaSPC = '1') then
pixelPelotaVer <= "0111001"; --en medio: (120/2) = aprox 57
pixelPelotaHor <= "01000110"; --en medio: (153/2) = aprox 76. la ponemos a la izq, en 70
end if;
end if;
--controlador de movimiento
if (reset = '0')then
moverPelota <= '1';
horizontalPelota <= '1';
verticalPelota <= '1';
buzz <= '0';
elsif (clk'event and clk = '1') then
if (finCuenta1Dec='1') then --chequeo de colision
buzz <= '0';
--pala izquierda
if (pixelPelotaHor = 10) then --esta enfrente de la pala
if (pixelPelotaVer >= pixelPalaIzq and pixelPelotaVer <= pixelPalaIzq+16 ) then --choca con la pala
horizontalPelota <= '1';
buzz <= '1';
end if;
end if;
--pala derecha
if (pixelPelotaHor = 143) then --esta enfrente de la pala
if (pixelPelotaVer >= pixelPalaDer and pixelPelotaVer <= pixelPalaDer+16 ) then --choca con la pala
horizontalPelota <= '0';
buzz <= '1';
end if;
end if;
--campo arriba
if (pixelPelotaVer = 10) then --esta enfrente de la barrera =10
verticalPelota <= '1';
buzz <= '1';
end if;
--campo abajo
if (pixelPelotaVer = 110) then --esta enfrente de la barrera =110
verticalPelota <= '0';
buzz <= '1';
end if;
--fuera
if (pixelPelotaHor = 1 or pixelPelotaHor = 155) then
moverPelota <= '0';
buzz <= '1';
end if;
if (teclaSPC = '1') then
moverPelota <= '1';
horizontalPelota <= '1';
verticalPelota <= '1';
buzz <= '0';
end if;
end if;
end if;
end process pelota;
--maquina de estados con registros de flags-------------------------------------------------
controladorEstados: process (clk, reset, newData, scancode)
begin
if(reset = '0') then
estado <= pulsadas;
elsif (clk'event and clk = '1') then
estado <= pulsadas; -- estado por defecto, puede ser sobreescrito luego
case estado is
when pulsadas =>
estado <= pulsadas;
if (newData = '1' and scancode = "11110000") then --11110000: F0
estado <= despulsadas;
end if;
when despulsadas =>
estado <= despulsadas;
if (newData = '1') then
estado <= pulsadas;
end if;
end case;
end if;
end process;
generadorSalidaMealy: process (newDataAck, scancode, estado, newData)
begin
newDataAck <= '0';
clTeclaQ <= '0';
clTeclaA <= '0';
clTeclaP <= '0';
clTeclaL <= '0';
clTeclaSPC <= '0';
ldTeclaQ <= '0';
ldTeclaA <= '0';
ldTeclaP <= '0';
ldTeclaL <= '0';
ldTeclaSPC <= '0';
case estado is
when pulsadas =>
if (newData = '1') then --11110000: F0
case scancode is --registros de flags:
when "00010101" => ldTeclaQ <= '1'; clTeclaQ <= '0'; --Q=15
when "00011100" => ldTeclaA <= '1'; clTeclaA <= '0'; --A=1C
when "01001101" => ldTeclaP <= '1'; clTeclaP <= '0'; --P=4D
when "01001011" => ldTeclaL <= '1'; clTeclaL <= '0'; --L=4B
when "00101001" => ldTeclaSPC <= '1'; clTeclaSPC <= '0'; --SPC=29
when others => null;
end case;
newDataAck <= '1';
end if;
when despulsadas =>
if (newData = '1') then
case scancode is --registros de flags:
when "00010101" => ldTeclaQ <= '0'; clTeclaQ <= '1'; --Q=15
when "00011100" => ldTeclaA <= '0'; clTeclaA <= '1'; --A=1C
when "01001101" => ldTeclaP <= '0'; clTeclaP <= '1'; --P=4D
when "01001011" => ldTeclaL <= '0'; clTeclaL <= '1'; --L=4B
when "00101001" => ldTeclaSPC <= '0'; clTeclaSPC <= '1'; --SPC=29
when others => null;
end case;
newDataAck <= '1';
end if;
when others => null;
end case;
end process;
generadorSalidaMoore: process (estado) --genera st
begin
case estado is
when pulsadas =>
st <= "000";
when despulsadas =>
st <= "001";
end case;
end process;
conversor7seg: process(st)
begin
case st is
-- gfedcba
when "000" => segs <= "0111111"; -- cerrado: Locked
when "001" => segs <= "0000110";
when OTHERS => segs <= "1111001"; -- error
end case;
end process;
-----------------------------------------------------------------------------
outteclaQ <= teclaQ;
arribaPalaIzq <= teclaQ and not teclaA;
abajoPalaIzq <= teclaA;
arribaPalaDer <= teclaP and not teclaL;
abajoPalaDer <= teclaL;
biestableDTeclaQ: process(reset,clk,ldTeclaQ,clTeclaQ)
begin
if(reset = '0')then
teclaQ <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaQ = '1') then
teclaQ <= '0';
elsif (ldTeclaQ = '1') then
teclaQ <= '1';
end if;
end if;
end process biestableDTeclaQ;
biestableDTeclaA: process(reset,clk,ldTeclaA,clTeclaA)
begin
if(reset = '0')then
teclaA <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaA = '1') then
teclaA <= '0';
elsif (ldTeclaA = '1') then
teclaA <= '1';
end if;
end if;
end process biestableDTeclaA;
biestableDTeclaP: process(reset,clk,ldTeclaP,clTeclaP)
begin
if(reset = '0')then
teclaP <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaP = '1') then
teclaP <= '0';
elsif (ldTeclaP = '1') then
teclaP <= '1';
end if;
end if;
end process biestableDTeclaP;
biestableDTeclaL: process(reset,clk,ldTeclaL,clTeclaL)
begin
if(reset = '0')then
teclaL <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaL = '1') then
teclaL <= '0';
elsif (ldTeclaL = '1') then
teclaL <= '1';
end if;
end if;
end process biestableDTeclaL;
biestableDTeclaSPC: process(reset,clk,ldTeclaSPC,clTeclaSPC)
begin
if(reset = '0')then
teclaSPC <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaSPC = '1') then
teclaSPC <= '0';
elsif (ldTeclaSPC = '1') then
teclaSPC <= '1';
end if;
end if;
end process biestableDTeclaSPC;
----- GENERACIÓN DE SONIDO --------------------------------------------------
oscilador18bits: process(clk,reset,clOscilador)
begin
if(reset = '0')then
cuentaOscilador <= (others => '0');
onda <= '0'; --reset biestable T
elsif(clk'event and clk = '1') then
if (clOscilador = '1') then
cuentaOscilador <= (others => '0');
onda <= not onda;
else
cuentaOscilador <= cuentaOscilador + 1;
end if;
end if;
end process oscilador18bits;
generadorSonido: process(clk,reset,cuentaOscilador,buzz,onda,silencio)
begin
if (cuentaOscilador = "010111010101001101") then -- comparador del oscilador
clOscilador <= '1';
else
clOscilador <= '0';
end if;
if (buzz = '0') then -- puerta NOR para generar silencio
silencio <= '1';
else
silencio <= '0';
end if;
altavoz <= onda or silencio; -- puerta OR para generar onda del sonido
end process generadorSonido;
----- FIN GENERACIÓN DE SONIDO ----------------------------------------------
end Behavioral;
| gpl-3.0 | 65ac3377d7517cc461ead1ff558ae001 | 0.586286 | 3.240896 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/field_bus_serial.vhd | 1 | 6,801 | -------------------------------------------------------------------------------
--! @file field_bus_serial.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-12-01
--! @brief Field-bus serial interface.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.nf_pkg.all;
--! @brief Entity declaration of field_bus_serial
--! @details
--! Provide a serial interface over NanoFIP.
entity field_bus_serial is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Gateway communication
--! @{
--! Start of field-bus cycle
start_i : in std_ulogic;
--! Commands
command_i : in nf_command_t;
--! Serial data
data_o : out std_ulogic_vector(7 downto 0);
--! Serial data number
data_num_o : out std_ulogic_vector(3 downto 0);
--! Serial data enable
data_en_o : out std_ulogic;
--! @}
--! @name Serial communication
--! @{
--! Serial receiver
rx_i : in std_ulogic;
--! Serial transmitter
tx_o : out std_ulogic);
--! @}
end entity field_bus_serial;
--! RTL implementation of field_bus_serial
architecture rtl of field_bus_serial is
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal data_num : unsigned(3 downto 0);
--! @}
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
signal cmd_fifo_rd_en : std_ulogic;
signal cmd_fifo_data : std_ulogic_vector(31 downto 0);
signal cmd_fifo_data_en : std_ulogic;
signal cmd_fifo_empty : std_ulogic;
signal cmd_fifo_wr_busy : std_ulogic;
signal cmd_fifo_rd_busy : std_ulogic;
signal stat_fifo_rd_en : std_ulogic;
signal stat_fifo_empty : std_ulogic;
signal stat_fifo_data_en : std_ulogic;
signal tx_data : std_ulogic_vector(7 downto 0);
signal tx_data_en : std_ulogic;
signal tx_done : std_ulogic;
signal rx_data : std_ulogic_vector(7 downto 0);
signal rx_data_en : std_ulogic;
signal array_tx_busy : std_ulogic;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
data_num_o <= std_ulogic_vector(data_num);
data_en_o <= stat_fifo_data_en;
---------------------------------------------------------------------------
-- Signal Assignments
---------------------------------------------------------------------------
cmd_fifo_rd_en <= (not command_i.serial_data_en) and (not cmd_fifo_wr_busy) and (not cmd_fifo_rd_busy) and (not cmd_fifo_empty) and (not array_tx_busy);
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! Command FIFO
cmd_fifo_inst : entity work.fifo_tmr
generic map (
depth_g => 8,
width_g => 32)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_en_i => command_i.serial_data_en,
data_i => command_i.serial_data,
done_o => open,
full_o => open,
wr_busy_o => cmd_fifo_wr_busy,
rd_en_i => cmd_fifo_rd_en,
data_o => cmd_fifo_data,
data_en_o => cmd_fifo_data_en,
empty_o => cmd_fifo_empty,
rd_busy_o => cmd_fifo_rd_busy);
--! Status FIFO
stat_fifo_inst : entity work.fifo_tmr
generic map (
depth_g => 256,
width_g => 8)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_en_i => rx_data_en,
data_i => rx_data,
done_o => open,
full_o => open,
wr_busy_o => open,
rd_en_i => stat_fifo_rd_en,
data_o => data_o,
data_en_o => stat_fifo_data_en,
empty_o => stat_fifo_empty,
rd_busy_o => open);
--! Array transmitter
array_tx_inst : entity work.array_tx
generic map (
data_count_g => 4,
data_width_g => 8)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
data_i => cmd_fifo_data,
data_en_i => cmd_fifo_data_en,
busy_o => array_tx_busy,
done_o => open,
tx_data_o => tx_data,
tx_data_en_o => tx_data_en,
tx_done_i => tx_done);
--! Serial transmitter
uart_tx_inst : entity work.uart_tx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 4166)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
data_i => tx_data,
data_en_i => tx_data_en,
busy_o => open,
done_o => tx_done,
tx_o => tx_o);
--! Serial receiver
uart_rx_inst : entity work.uart_rx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 4166)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
rx_i => rx_i,
data_o => rx_data,
data_en_o => rx_data_en,
error_o => open);
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
data_num <= to_unsigned(0, data_num'length);
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
stat_fifo_rd_en <= '0';
if start_i = '1' then
data_num <= to_unsigned(0, data_num'length);
stat_fifo_rd_en <= not stat_fifo_empty;
end if;
if stat_fifo_data_en = '1' and to_integer(data_num) < 6 then
data_num <= data_num + 1;
stat_fifo_rd_en <= not stat_fifo_empty;
end if;
end if;
end if;
end process regs;
end architecture rtl;
| mit | 25d6aefb74cdc3119877fec30f2ae061 | 0.449493 | 3.587025 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fslt_2AXI.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 071a7c9dbdbc46c2d5bc5c59e6ca1aa2 | 0.567707 | 3.729005 | false | false | false | false |
jcowgill/cs-dacs-robot | Common/DataChangeDetectorTest.vhd | 1 | 1,530 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DataChangeDetectorTest IS
END DataChangeDetectorTest;
ARCHITECTURE behavioral OF DataChangeDetectorTest IS
COMPONENT DataChangeDetector
PORT ( SEND : OUT STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR (5 DOWNTO 0));
END COMPONENT;
SIGNAL SEND : STD_LOGIC;
SIGNAL CLR : STD_LOGIC;
SIGNAL CLK : STD_LOGIC;
SIGNAL DATA : STD_LOGIC_VECTOR (5 DOWNTO 0);
BEGIN
UUT: DataChangeDetector PORT MAP(
SEND => SEND,
CLR => CLR,
CLK => CLK,
DATA => DATA
);
clk_process : PROCESS
BEGIN
-- Clock signal (4 MHz)
CLK <= '0';
WAIT FOR 125ns;
CLK <= '1';
WAIT FOR 125ns;
END PROCESS;
tb_process : PROCESS
BEGIN
-- Reset
CLR <= '1';
WAIT FOR 1000ns;
CLR <= '0';
-- Send some data down
DATA <= "000000"; WAIT FOR 1000ns;
DATA <= "000001"; WAIT FOR 1000ns;
DATA <= "000010"; WAIT FOR 1000ns;
DATA <= "000011"; WAIT FOR 1000ns;
DATA <= "000100"; WAIT FOR 1000ns;
DATA <= "000101"; WAIT FOR 1000ns;
DATA <= "000110"; WAIT FOR 1000ns;
DATA <= "000111"; WAIT FOR 1000ns;
DATA <= "000000"; WAIT FOR 500ns;
DATA <= "000001"; WAIT FOR 1000ns;
DATA <= "000000"; WAIT FOR 1000ns;
WAIT;
END PROCESS;
END;
| apache-2.0 | f2a9183925634b6d3417ff887a0db875 | 0.538562 | 3.787129 | false | false | false | false |
joalcava/sparcv8-monocicle | psr_modifier.vhd | 1 | 1,430 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity psr_modifier is
Port( crs1 : in std_logic;
ope2 : in std_logic;
alur : in STD_LOGIC_VECTOR(31 downto 0);
aluop : in std_logic_vector(5 downto 0);
nzvc : out std_logic_vector(3 downto 0)
);
end psr_modifier;
architecture psr_modArq of psr_modifier is
begin
process(crs1, ope2, alur, aluop)
begin
-- ADDcc y ADDxcc
if (aluop = "001000" or aluop = "01011") then
nzvc(3) <= alur(31);
if (alur = x"00000000") then nzvc(2) <= '1'; else nzvc(2) <= '0'; end if;
nzvc(1) <= (crs1 and ope2 and (not alur(31))) or ((not crs1) and (not ope2) and alur(31));
nzvc(0) <= (crs1 and ope2) or ((not alur(31)) and (crs1 or ope2));
-- SUBcc y SUBxcc
else
if (aluop = "001001" or aluop = "001101")then
nzvc(3) <= alur(31);
if (alur = x"00000000") then nzvc(2) <= '1'; else nzvc(2) <= '0'; end if;
nzvc(1) <= (crs1 and (not ope2) and (not alur(31))) or ((not crs1) and ope2 and alur(31));
nzvc(0) <= ((not crs1) and ope2) or (alur(31) and ((not crs1) or ope2));
--ANDcc, ANDNcc, ORcc, ORNcc, XORcc, XNORcc
else
if (aluop = "001111" or aluop = "010001" or aluop = "001110" or aluop = "010010" or aluop = "010000" or aluop = "010011")then
nzvc(3) <= alur(31);
if (alur = x"00000000") then nzvc(2) <= '1'; else nzvc(2) <= '0'; end if;
nzvc(1) <= '0';
nzvc(0) <= '1';
end if;
end if;
end if;
end process;
end psr_modArq;
| gpl-3.0 | 3a1659abfc29cdaf00a9990e686157a7 | 0.598601 | 2.609489 | false | false | false | false |
preusser/q27 | src/vhdl/queens/queens_chain.vhdl | 1 | 7,997 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity queens_chain is
generic (
-- Problem Size
N : positive;
L : positive;
-- Design Spec
SOLVERS : positive;
COUNT_CYCLES : boolean
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Problem Chain
piful : out std_logic;
pidat : in std_logic_vector(7 downto 0);
pieof : in std_logic;
piput : in std_logic;
poful : in std_logic := '1'; -- Open-end as default
podat : out std_logic_vector(7 downto 0);
poeof : out std_logic;
poput : out std_logic;
-- Solution Chain
sivld : in std_logic := '0';
sidat : in std_logic_vector(7 downto 0) := (others => '-');
sieof : in std_logic := '-';
sigot : out std_logic;
sovld : out std_logic;
sodat : out std_logic_vector(7 downto 0);
soeof : out std_logic;
sogot : in std_logic
);
end queens_chain;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.fifo.all;
architecture rtl of queens_chain is
-- Bit Length of Pre-Placement
constant PRE_BITS : positive := 4*L*log2ceil(N)-1;
constant PRE_BYTES : positive := (PRE_BITS+7)/8;
-- Inter-Stage Input Distribution
signal pful : std_logic_vector(0 to SOLVERS);
signal pdat : byte_vector(0 to SOLVERS);
signal peof : std_logic_vector(0 to SOLVERS);
signal pput : std_logic_vector(0 to SOLVERS);
-- Inter-Stage Result Stream
signal svld : std_logic_vector(0 to SOLVERS);
signal sdat : byte_vector(0 to SOLVERS);
signal seof : std_logic_vector(0 to SOLVERS);
signal sgot : std_logic_vector(0 to SOLVERS);
begin
-- Connect Subproblem Chain
piful <= pful(0);
pdat(0) <= pidat;
peof(0) <= pieof;
pput(0) <= piput;
pful(SOLVERS) <= poful;
podat <= pdat(SOLVERS);
poeof <= peof(SOLVERS);
poput <= pput(SOLVERS);
-- Connect Result Chain
svld(0) <= sivld;
sdat(0) <= sidat;
seof(0) <= sieof;
sigot <= sgot(0);
sovld <= svld(SOLVERS);
sodat <= sdat(SOLVERS);
soeof <= seof(SOLVERS);
sgot(SOLVERS) <= sogot;
-- Linear Solver Chain
-- Input @index i
-- Output @index i+1
genSolvers: for i in 0 to SOLVERS-1 generate
-- Widened Tap for this Stage
signal tful : std_logic;
signal tput : std_logic;
signal tdat : std_logic_vector(8*PRE_BYTES-1 downto 0);
-- Decoded Pre-Placement
signal bh, bv : std_logic_vector(L to N-L-1);
signal bu, bd : std_logic_vector(0 to 2*N-4*L-2);
-- Solver Strobes
signal sol, done : std_logic;
-- Computation State
signal Act : std_logic := '0';
signal Vld : std_logic := '0';
-- Result Buffer
constant BUF_LEN : positive := ite(COUNT_CYCLES, 48, 0) + 8*PRE_BYTES + 52;
signal Buf : unsigned(BUF_LEN-1 downto 0) := (others => '-');
signal Cnt : unsigned(log2ceil((BUF_LEN+7)/8-1) downto 0) := (others => '-');
alias Cycles : unsigned(47 downto 0) is Buf(BUF_LEN-1 downto BUF_LEN-48);
alias Pre : unsigned(8*PRE_BYTES-1 downto 0) is Buf(8*PRE_BYTES+51 downto 52);
alias Sols13 : unsigned( 3 downto 0) is Buf(51 downto 48);
alias Sols15 : unsigned( 3 downto 0) is Buf(47 downto 44);
alias Sols : unsigned(43 downto 0) is Buf(43 downto 0);
-- Streamed Stage Result
signal rvld : std_logic;
signal rdat : byte;
signal reof : std_logic;
signal rgot : std_logic;
begin
-- Input Tap
tap: entity work.msg_tap
generic map (
D => PRE_BYTES
)
port map (
clk => clk,
rst => rst,
iful => pful(i),
idat => pdat(i),
ieof => peof(i),
iput => pput(i),
oful => pful(i+1),
odat => pdat(i+1),
oeof => peof(i+1),
oput => pput(i+1),
tful => tful,
tdat => tdat,
tput => tput
);
-- Pre-Placement Expansion
expander: entity work.expand_blocking
generic map (
N => N,
L => L
)
port map (
pre => tdat(PRE_BITS-1 downto 0),
bh => bh,
bv => bv,
bu => bu,
bd => bd
);
-- Solver Slice
slice: entity work.queens_slice
generic map (
N => N,
L => L
)
port map (
clk => clk,
rst => rst,
start => tput,
BH_l => bh,
BU_l => bu,
BD_l => bd,
BV_l => bv,
sol => sol,
done => done
);
-- Computation Control
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Act <= '0';
Vld <= '0';
Cnt <= (others => '-');
Buf <= (others => '-');
else
if tput = '1' then
-- Start
Act <= '1';
Buf <= (others => '-');
if COUNT_CYCLES then
Cycles <= (others => '0');
end if;
Pre <= unsigned(tdat);
Sols <= (others => '0');
Sols13 <= (others => '0');
Sols15 <= (others => '0');
else
-- Counting Cycles
if COUNT_CYCLES and Act = '1' and Vld = '0' then
Cycles <= Cycles + 1;
end if;
-- Counting Solutions
if sol = '1' then
Sols <= Sols + 1;
Sols13 <= Sols13 - ("11" & (1 downto 0 => (not(Sols13(3) and Sols13(2)))));
Sols15 <= Sols15 - ("111" & (not(Sols15(3) and Sols15(2) and Sols15(1))));
end if;
-- Result Output
if done = '1' then
Vld <= '1';
Cnt <= to_unsigned((BUF_LEN+7)/8-2, Cnt'length);
end if;
if rgot = '1' then
Buf <= Buf(Buf'left-8 downto 0) & (1 to 8 => '-');
Cnt <= Cnt - 1;
if Cnt(Cnt'left) = '1' then
Act <= '0';
Vld <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
tful <= Act;
rvld <= Vld;
rdat <= byte(Buf(Buf'left downto Buf'left-7));
reof <= Cnt(Cnt'left);
-- Connect Result Stream
blkFunnel: block
-- Funnel-to-FIFO Interface
signal f2f_ful : std_logic;
signal f2f_dat : std_logic_vector(8 downto 0);
signal f2f_put : std_logic;
begin
-- Merge local Output with Result Stream
funnel: entity work.msg_funnel
generic map (
N => 2
)
port map (
clk => clk,
rst => rst,
ivld(0) => rvld,
ivld(1) => svld(i),
idat(0) => rdat,
idat(1) => sdat(i),
ieof(0) => reof,
ieof(1) => seof(i),
igot(0) => rgot,
igot(1) => sgot(i),
oful => f2f_ful,
odat => f2f_dat(7 downto 0),
oeof => f2f_dat(8),
oput => f2f_put
);
-- Stage Output through FIFO
glue : fifo_glue
generic map (
D_BITS => 9
)
port map (
clk => clk,
rst => rst,
ful => f2f_ful,
di => f2f_dat,
put => f2f_put,
vld => svld(i+1),
do(7 downto 0) => sdat(i+1),
do(8) => seof(i+1),
got => sgot(i+1)
);
end block blkFunnel;
end generate genSolvers;
end rtl;
| agpl-3.0 | 587d9d5d1f65995b7591cf5223ad1a75 | 0.552457 | 3.066334 | false | false | false | false |
malkadi/FGPU | RTL/init_alu_en_ram.vhd | 1 | 5,188 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
---------------------------------------------------------------------------------------------------------}}}
entity init_alu_en_ram is -- {{{
generic(
N_RD_PORTS : natural := 4
);
port(
start : in std_logic := '0';
finish : out std_logic := '0';
clear_finish : in std_logic;
wg_size : in unsigned(N_WF_CU_W+WF_SIZE_W downto 0);
sch_rqst_n_WFs_m1 : in unsigned(N_WF_CU_W-1 downto 0);
rdData_alu_en : out alu_en_vec_type(N_RD_PORTS-1 downto 0) := (others=>(others=>'0')); -- level 3
rdAddr_alu_en : in alu_en_rdAddr_type(N_RD_PORTS-1 downto 0) := (others=>(others=>'0')); -- level 1
clk, nrst : in std_logic
);
end entity; --}}}
architecture behavioural of init_alu_en_ram is
-- signal definitions -----------------------------------------------------------------------------------{{{
type st_alu_en_type is (idle, set_till_last_wf, check_last_wf);
signal st_alu_en, st_alu_en_n : st_alu_en_type := idle;
signal alu_en_ram : alu_en_vec_type(2**(PHASE_W+N_WF_CU_W)-1 downto 0) := (others=>(others=>'0'));
signal wrData_alu_en, wrData_alu_en_n : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
signal wrAddr_alu_en, wrAddr_alu_en_n : unsigned(PHASE_W+N_WF_CU_W downto 0) := (others=>'0');
signal we_alu_en, we_alu_en_n : std_logic := '0';
signal alu_count, alu_count_n : unsigned(WF_SIZE_W-1 downto 0) := (others=>'0');
signal finish_n, finish_i : std_logic := '0';
signal n_complete_wfs, n_complete_wfs_n : integer range 0 to 2**N_WF_CU_W := 0;
signal rdData_alu_en_n : alu_en_vec_type(N_RD_PORTS-1 downto 0) := (others=>(others=>'0'));
---------------------------------------------------------------------------------------------------------}}}
begin
finish <= finish_i;
process(clk)
begin
if rising_edge(clk) then
rdData_alu_en <= rdData_alu_en_n;
for i in 0 to N_RD_PORTS-1 loop
rdData_alu_en_n(i) <= alu_en_ram(to_integer(rdAddr_alu_en(i)));
end loop;
if we_alu_en = '1' then
alu_en_ram(to_integer(wrAddr_alu_en(PHASE_W+N_WF_CU_W-1 downto 0))) <= wrData_alu_en;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if nrst = '0' then
st_alu_en <= idle;
we_alu_en <= '0';
alu_count <= (others=>'0');
finish_i <= '0';
wrAddr_alu_en <= (others=>'0');
wrData_alu_en <= (others=>'0');
n_complete_wfs <= 0;
else
st_alu_en <= st_alu_en_n;
wrAddr_alu_en <= wrAddr_alu_en_n;
wrData_alu_en <= wrData_alu_en_n;
we_alu_en <= we_alu_en_n;
alu_count <= alu_count_n;
finish_i <= finish_n;
n_complete_wfs <= n_complete_wfs_n;
if clear_finish = '1' then
finish_i <= '0';
end if;
end if;
end if;
end process;
process(start , st_alu_en, wrData_alu_en, wrAddr_alu_en, sch_rqst_n_WFs_m1, alu_count, wg_size, finish_i, wrAddr_alu_en_n, n_complete_wfs)
begin
st_alu_en_n <= st_alu_en;
wrData_alu_en_n <= wrData_alu_en;
wrAddr_alu_en_n <= wrAddr_alu_en;
we_alu_en_n <= '0';
alu_count_n <= alu_count;
finish_n <= finish_i;
n_complete_wfs_n <= n_complete_wfs;
case st_alu_en is
when idle =>
if start = '1' then
st_alu_en_n <= set_till_last_wf;
wrAddr_alu_en_n <= (others=>'1');
alu_count_n <= (others=>'0');
finish_n <= '0';
if to_integer(wg_size(WF_SIZE_W-1 downto 0)) = 0 then
n_complete_wfs_n <= to_integer(sch_rqst_n_WFs_m1) + 1;
else
n_complete_wfs_n <= to_integer(sch_rqst_n_WFs_m1);
end if;
end if;
when set_till_last_wf =>
wrAddr_alu_en_n <= wrAddr_alu_en + 1;
if wrAddr_alu_en_n(PHASE_W+N_WF_CU_W downto PHASE_W) /= n_complete_wfs then
wrData_alu_en_n <= (others=>'1');
we_alu_en_n <= '1';
else
if to_integer(wg_size(WF_SIZE_W-1 downto 0)) = 0 then
st_alu_en_n <= idle;
finish_n <= '1';
else
st_alu_en_n <= check_last_wf;
end if;
end if;
when check_last_wf =>
wrAddr_alu_en_n(PHASE_W-1 downto 0) <= alu_count(PHASE_W+CV_W-1 downto CV_W);
if to_integer(alu_count) < wg_size(WF_SIZE_W-1 downto 0) then
wrData_alu_en_n(to_integer(alu_count(CV_W-1 downto 0))) <= '1';
else
wrData_alu_en_n(to_integer(alu_count(CV_W-1 downto 0))) <= '0';
end if;
if to_integer(alu_count(CV_W-1 downto 0)) = CV_SIZE-1 then
we_alu_en_n <= '1';
end if;
alu_count_n <= alu_count + 1;
if to_integer(alu_count) = WF_SIZE-1 then
st_alu_en_n <= idle;
finish_n <= '1';
end if;
end case;
end process;
end architecture;
| gpl-3.0 | 5b6bf8082eae014d7030b1ec5d8c2e18 | 0.495952 | 3.084423 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/io/io_FrequencyCounter.vhdl | 2 | 3,850 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
entity io_FrequencyCounter is
generic (
CLOCK_FREQ : FREQ := 100 MHz;
TIMEBASE : TIME := 1 sec;
RESOLUTION : POSITIVE := 8
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
FreqIn : in STD_LOGIC;
FreqOut : out STD_LOGIC_VECTOR(RESOLUTION - 1 downto 0)
);
end;
architecture rtl of io_FrequencyCounter is
constant TIMEBASECOUNTER_MAX : POSITIVE := TimingToCycles(TIMEBASE, CLOCK_FREQ);
constant TIMEBASECOUNTER_BITS : POSITIVE := log2ceilnz(TIMEBASECOUNTER_MAX);
constant REQUENCYCOUNTER_MAX : POSITIVE := 2**RESOLUTION;
constant FREQUENCYCOUNTER_BITS : POSITIVE := RESOLUTION;
signal TimeBaseCounter_us : UNSIGNED(TIMEBASECOUNTER_BITS - 1 downto 0) := (others => '0');
signal TimeBaseCounter_ov : STD_LOGIC;
signal FrequencyCounter_us : UNSIGNED(FREQUENCYCOUNTER_BITS downto 0) := (others => '0');
signal FrequencyCounter_ov : STD_LOGIC;
signal FreqIn_d : STD_LOGIC := '0';
signal FreqIn_re : STD_LOGIC;
signal FreqOut_d : STD_LOGIC_VECTOR(RESOLUTION - 1 downto 0) := (others => '0');
begin
FreqIn_d <= FreqIn when rising_edge(Clock);
FreqIn_re <= not FreqIn_d and FreqIn;
-- timebase counter
process(Clock)
begin
if rising_edge(clock) then
if ((Reset or TimeBaseCounter_ov) = '1') then
TimeBaseCounter_us <= (others => '0');
else
TimeBaseCounter_us <= TimeBaseCounter_us + 1;
end if;
end if;
end process;
TimeBaseCounter_ov <= to_sl(TimeBaseCounter_us = TIMEBASECOUNTER_MAX);
-- frequency counter
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or TimeBaseCounter_ov) = '1') then
FrequencyCounter_us <= (others => '0');
elsif (FrequencyCounter_ov = '0') and (FreqIn_re = '1') then
FrequencyCounter_us <= FrequencyCounter_us + 1;
end if;
end if;
end process;
FrequencyCounter_ov <= FrequencyCounter_us(FrequencyCounter_us'high);
-- hold counter value until next TimeBaseCounter event
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
FreqOut_d <= (others => '0');
elsif (TimeBaseCounter_ov = '1') then
if (FrequencyCounter_ov = '1') then
FreqOut_d <= (others => '1');
else
FreqOut_d <= std_logic_vector(FrequencyCounter_us(FreqOut_d'range));
end if;
end if;
end if;
end process;
FreqOut <= FreqOut_d;
end;
| agpl-3.0 | 222fd6b56733a25893e70a366ba89194 | 0.604416 | 3.588071 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_fsqrt_2AXI.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 69957a8946f24f03a2334b7e3b6d6f85 | 0.567707 | 3.729005 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/var1_rx.vhd | 1 | 4,233 | -------------------------------------------------------------------------------
--! @file var1_rx.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2013-10-24
--! @brief NanoFIP VAR1 receiver controlling JTAG TRST.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! @brief Entity declaration of var1_rx
--! @details
--! NanoFIP VAR1 packets are controlling the JTAG TRST output. The first byte
--! either sets TRST high or low.
--!
--! 0xDB sets TRST to '1'
--! 0xA5 sets TRST to '0'
entity var1_rx is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Receiver interface
--! @{
--! Data is ready to be received
rx_rdy_i : in std_ulogic;
--! Read address
rx_addr_o : out std_ulogic_vector(6 downto 0);
--! Read enable
rx_en_o : out std_ulogic;
--! Read data input
rx_data_i : in std_ulogic_vector(7 downto 0);
--! Read data input enable
rx_data_en_i : in std_ulogic;
--! @}
--! @name VAR1 interface
--! @{
--! JTAG TRST
jtag_trst_o : out std_ulogic;
--! @}
--! @name Error flags
--! @{
--! Read-write collision
err_rw_coll_i : in std_ulogic;
--! Interface busy
err_bsy_i : in std_ulogic;
--! VAR not ready
err_not_rdy_i : in std_ulogic;
--! Wishbone bus acknowledge timeout
err_timeout_i : in std_ulogic);
--! @}
end entity var1_rx;
--! RTL implementation of var1_rx
architecture rtl of var1_rx is
---------------------------------------------------------------------------
-- Types and Constants
---------------------------------------------------------------------------
--! Base address for data payload
constant base_addr_c : natural := 2;
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal en : std_ulogic;
signal trst : std_ulogic;
--! @}
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
signal wb_if_err : std_ulogic;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
rx_addr_o <= std_ulogic_vector(to_unsigned(base_addr_c, rx_addr_o'length));
rx_en_o <= en;
jtag_trst_o <= trst;
---------------------------------------------------------------------------
-- Signal Assignments
---------------------------------------------------------------------------
-- Combine errors into one signal
wb_if_err <= err_rw_coll_i or err_not_rdy_i or err_timeout_i or err_bsy_i;
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
en <= '0';
trst <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
en <= rx_rdy_i;
if rx_data_en_i = '1' then
if rx_data_i = "11011011" then -- 0xDB
trst <= '1';
elsif rx_data_i = "10100101" then -- 0xA5
trst <= '0';
end if;
end if;
-- Reset on error
if wb_if_err = '1' then
reset;
end if;
end if;
end if;
end process regs;
end architecture rtl;
| mit | 15120a2c3fb8739d088a5d8820e57f19 | 0.395228 | 4.53212 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_rx_deserializer.vhd | 1 | 34,328 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_rx_deserializer |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_rx_deserializer.vhd |
-- |
-- Description De-serialization of the deglitched "nanoFIP FIELDRIVE" input signal FD_RXD and |
-- construction of bytes of data to be provided to: |
-- o the wf_engine_control unit, for the contents of ID_DAT frames |
-- o the wf_consumption unit, for the contents of consumed RP_DAT frames. |
-- The unit is also responsible for the identification of the FSS and FES fields of |
-- ID_DAT and RP_DAT frames and the verification of their CRC. |
-- At the end of a frame (FES detection) either the fss_crc_fes_ok_p_o pulse |
-- is assserted, indicating a frame with with correct FSS, CRC and FES |
-- or the pulse crc_wrong_p_o is asserted indicating an error on the CRC. |
-- If a FES is not detected after the reception of more than 8 bytes for an ID_DAT |
-- or more than 133 bytes for a RP_DAT the unit is reset by the wf_engine_control. |
-- The unit also remains reset during data production. |
-- |
-- Remark: We refer to |
-- o a significant edge : for the edge of a manch. encoded bit |
-- (bit 0: _|-, bit 1: -|_). |
-- |
-- o a transition : for the moment in between two adjacent bits, that|
-- may or may not result in an edge (eg. a 0 followed by a 0 will give an edge: |
-- _|-|_|-, but a 0 followed by a 1 will not: _|--|_ ). |
-- |
-- o the sampling of a manch. bit: for the moments when a manch. encoded bit should |
-- be sampled, before and after a significant edge. |
-- |
-- o the sampling of a bit : for the sampling of only the 1st part, |
-- before the transition. |
-- |
-- Example: |
-- bits : 0 1 |
-- manch. encoded : _|- -|_ |
-- significant edge : ^ ^ |
-- transition : ^ |
-- sample_manch_bit_p: ^ ^ ^ ^ |
-- sample_bit_p : ^ ^ (this sampling will give the 0 and the 1) |
-- |
-- |
-- Reminder of the consumed RP_DAT frame structure: |
-- _______ _______ ______ _______ ______ ________________ _______ ___________ _______ |
-- |__PRE__|__FSD__|_CTRL_||__PDU__|_LGTH_|_..ApplicData.._|__MPS__||____FCS____|__FES__| |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 15/02/2011 |
-- Version v0.05 |
-- Depends on wf_reset_unit |
-- wf_rx_osc |
-- wf_rx_deglitcher |
-- wf_engine_control |
---------------- |
-- Last changes |
-- 09/2009 v0.01 PAS First version |
-- 10/2010 v0.02 EG state switch_to_deglitched added; |
-- output signal rx_osc_rst_o added; signals renamed; |
-- state machine rewritten (moore style); |
-- units wf_rx_manch_code_check and Incoming_Bits_Index created; |
-- each manch bit of FES checked (bf was just each bit, so any D5 was FES) |
-- code cleaned-up + commented. |
-- 12/2010 v0.03 EG CRC_ok pulse transfered 16 bits later to match the FES; |
-- like this we confirm that the CRC_ok_p arrived just before the FES, |
-- and any 2 bytes that could by chanche be seen as CRC, are neglected. |
-- FSM data_field_byte state: redundant code removed: |
-- "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then IDLE" |
-- code(more!)cleaned-up |
-- 01/2011 v0.04 EG changed way of detecting the FES to be able to detect a FES even if |
-- bytes with size different than 8 have preceeded. |
-- crc_wrong_p_o replaced the crc_wrong_p_o. |
-- 02/2011 v0.05 EG changed crc pulse transfer; removed switch to deglitch state |
-- s_fes_detected removed and s_byte_ready_p_d1; if bytes arrive with |
-- bits not x8, the fss_crc_fes_ok_p_o stays 0 (bc of s_byte_ready_p_d1) |
-- and the crc_wrong_p_o is asserted (bc of s_sample_manch_bit_p_d1); |
-- unit reset during production; |
-- check for code vilations completely removed! |
-- 10/2011 v0.05b EG moved session_timedout in the synchronous FSM process |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_rx_deserializer
--=================================================================================================
entity wf_rx_deserializer is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signal from the wf_engine_control unit
rx_rst_i : in std_logic; -- reset during production or
-- reset pulse when during reception a frame is rejected
-- by the engine_control (example: ID_DAT > 8 bytes,
-- RP_DAT > 133 bytes, wrong ID_DAT CTRL/ VAR/ SUBS bytes)
-- Signals from the wf_rx_deglitcher
fd_rxd_f_edge_p_i : in std_logic; -- indicates a falling edge on the deglitched FD_RXD
fd_rxd_r_edge_p_i : in std_logic; -- indicates a rising edge on the deglitched FD_RXD
fd_rxd_i : in std_logic; -- deglitched FD_RXD
-- Signals from the wf_rx_osc unit
sample_manch_bit_p_i : in std_logic; -- pulse indicating the sampling of a manch. bit
sample_bit_p_i : in std_logic; -- pulse indicating the sampling of a bit
signif_edge_window_i : in std_logic; -- time window where a significant edge is expected
adjac_bits_window_i : in std_logic; -- time window where a transition between adjacent
-- bits is expected
-- OUTPUTS
-- Signals to the wf_consumption and the wf_engine_control units
byte_o : out std_logic_vector (7 downto 0) ; -- retrieved data byte
byte_ready_p_o : out std_logic; -- pulse indicating a new retrieved data byte
fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- correct FSS, FES and CRC
-- Signal to the wf_production and the wf_engine_control units
crc_wrong_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with a
-- wrong CRC; pulse upon FES detection
-- Signal to the wf_engine_control unit
fss_received_p_o : out std_logic; -- pulse upon reception of a correct FSS (ID/RP)
-- Signal to the wf_rx_osc unit
rx_osc_rst_o : out std_logic);-- resets the clk recovery procedure
end entity wf_rx_deserializer;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_rx_deserializer is
-- FSM
type rx_st_t is (IDLE, PRE_FIELD_FIRST_F_EDGE, PRE_FIELD_R_EDGE, PRE_FIELD_F_EDGE, FSD_FIELD,
CTRL_DATA_FCS_FES_FIELDS);
signal rx_st, nx_rx_st : rx_st_t;
signal s_idle, s_receiving_pre, s_receiving_fsd, s_receiving_bytes : std_logic;
-- PRE detection
signal s_manch_r_edge_p, s_manch_f_edge_p, s_bit_r_edge_p, s_edge_out_manch_window_p : std_logic;
-- FSD, FES detection
signal s_fsd_bit, s_fsd_wrong_bit, s_fsd_last_bit, s_fes_detected : std_logic;
signal s_arriving_fes : std_logic_vector (15 downto 0);
-- bytes construction
signal s_write_bit_to_byte_p,s_byte_ready_p,s_byte_ready_p_d1,s_sample_manch_bit_p_d1: std_logic;
signal s_manch_bit_index_load_p, s_manch_bit_index_decr_p, s_manch_bit_index_is_zero : std_logic;
signal s_manch_bit_index, s_manch_bit_index_top : unsigned (3 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
-- CRC calculation
signal s_CRC_ok_p, s_CRC_ok_p_d, s_CRC_ok_p_found : std_logic;
-- independent timeout counter
signal s_session_timedout : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Deserializer's FSM --
---------------------------------------------------------------------------------------------------
-- Receiver's state machine: The state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process Deserializer_FSM_Sync: storage of the current state of the FSM
-- A robust protection, that depends only on the system clock, has been implemented:
-- knowing that at any bit rate the reception of a frame should not last more than 35ms (this
-- corresponds to the consumption of 133 bytes at 31.25 Kbps), a counter has been implemented,
-- responsible for bringing the machine back to IDLE if more than 52ms (complete 21 bit counter)
-- have passed since the machine left the IDLE state.
Deserializer_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or rx_rst_i = '1' or s_session_timedout = '1' then
rx_st <= IDLE;
else
rx_st <= nx_rx_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Deserializer_FSM_Comb_State_Transitions: Definition of the state
-- transitions of the FSM.
Deserializer_FSM_Comb_State_Transitions: process (s_bit_r_edge_p, s_edge_out_manch_window_p,
fd_rxd_f_edge_p_i, s_manch_r_edge_p, rx_st,
s_fsd_wrong_bit, s_manch_f_edge_p,
s_fsd_last_bit, s_fes_detected)
begin
case rx_st is
-- During the PRE, the wf_rx_osc is trying to synchronize to the transmitter's clock and every
-- edge detected in the FD_RXD is taken into account. At this phase, the unit uses
-- the wf_rx_osc signals: adjac_bits_window_i and signif_edge_window_i and if edges are found
-- outside those windows the unit goes back to IDLE and the wf_rx_osc is reset.
-- For the rest of the frame, the unit is just sampling the deglitched FD_RXD on the moments
-- specified by the wf_rx_osc signals: sample_manch_bit_p_i and sample_bit_p_i.
when IDLE =>
if fd_rxd_f_edge_p_i = '1' then -- falling edge detection
nx_rx_st <= PRE_FIELD_FIRST_F_EDGE;
else
nx_rx_st <= IDLE;
end if;
when PRE_FIELD_FIRST_F_EDGE =>
if s_manch_r_edge_p = '1' then -- arrival of a manch.
nx_rx_st <= PRE_FIELD_R_EDGE; -- rising edge
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= IDLE;
else
nx_rx_st <= PRE_FIELD_FIRST_F_EDGE;
end if;
when PRE_FIELD_R_EDGE =>
if s_manch_f_edge_p = '1' then -- arrival of a manch. falling edge
nx_rx_st <= PRE_FIELD_F_EDGE; -- note: several loops between
-- a rising and a falling edge are
-- expected for the PRE
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= IDLE;
else
nx_rx_st <= PRE_FIELD_R_EDGE;
end if;
when PRE_FIELD_F_EDGE =>
if s_manch_r_edge_p = '1' then -- arrival of a manch. rising edge
nx_rx_st <= PRE_FIELD_R_EDGE;
elsif s_bit_r_edge_p = '1' then -- arrival of a rising edge between
nx_rx_st <= FSD_FIELD; -- adjacent bits, signaling the
-- beginning of the 1st V+ violation
-- of the FSD
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= IDLE;
else
nx_rx_st <= PRE_FIELD_F_EDGE;
end if;
-- For the monitoring of the FSD, the unit is sampling each manch. bit of the incoming
-- FD_RXD and it is comparing it to the nominal bit of the FSD; the signal s_fsd_wrong_bit
-- is doing this comparison. If a wrong bit is received, the state machine jumps back to IDLE,
-- whereas if the complete byte is correctly received, it jumps to the CTRL_DATA_FCS_FES_FIELDS.
when FSD_FIELD =>
if s_fsd_last_bit = '1' then -- reception of the last (15th)
nx_rx_st <= CTRL_DATA_FCS_FES_FIELDS;-- FSD bit
elsif s_fsd_wrong_bit = '1' then -- wrong bit
nx_rx_st <= IDLE;
else
nx_rx_st <= FSD_FIELD;
end if;
-- The state machine stays in the CTRL_DATA_FCS_FES_FIELDS state until a FES detection (or
-- a reset rx_rst_i signal or a s_session_timeout signal). In this state bytes are "blindly"
-- being constructed and it is the wf_engine_control unit that supervises what is being received;
-- if for example an ID_DAT is being received without a FES detected after 8 bytes or an
-- RP_DAT without a FES after 133 bytes, or if the CTRL byte of an ID_DAT is wrong, the
-- engine_control will discard the current reception and reset the FSM through the rx_rst_i.
when CTRL_DATA_FCS_FES_FIELDS =>
if s_fes_detected = '1' then
nx_rx_st <= IDLE;
else
nx_rx_st <= CTRL_DATA_FCS_FES_FIELDS;
end if;
when OTHERS =>
nx_rx_st <= IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Deserializer_FSM_Comb_Output_Signals: Definition of the output
-- signals of the FSM
Deserializer_FSM_Comb_Output_Signals: process (rx_st)
begin
case rx_st is
when IDLE =>
------------------------------------
s_idle <= '1';
------------------------------------
s_receiving_pre <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
when PRE_FIELD_FIRST_F_EDGE | PRE_FIELD_R_EDGE | PRE_FIELD_F_EDGE =>
s_idle <= '0';
------------------------------------
s_receiving_pre <= '1';
------------------------------------
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
when FSD_FIELD =>
s_idle <= '0';
s_receiving_pre <= '0';
------------------------------------
s_receiving_fsd <= '1';
------------------------------------
s_receiving_bytes <= '0';
when CTRL_DATA_FCS_FES_FIELDS =>
s_idle <= '0';
s_receiving_pre <= '0';
s_receiving_fsd <= '0';
------------------------------------
s_receiving_bytes <= '1';
------------------------------------
when OTHERS =>
------------------------------------
s_idle <= '1';
------------------------------------
s_receiving_pre <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
end case;
end process;
---------------------------------------------------------------------------------------------------
-- Bytes Creation --
---------------------------------------------------------------------------------------------------
-- Synchronous process Append_Bit_To_Byte: Creation of bytes of data.
-- A new bit of the FD_RXD is appended to the output byte that is being formed when the FSM is in
-- the "CTRL_DATA_FCS_FES_FIELDS" state, on the "sample_bit_p_i" moments.
Append_Bit_To_Byte: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_byte_ready_p_d1 <= '0';
s_sample_manch_bit_p_d1 <= '0';
s_byte <= (others => '0');
else
s_byte_ready_p_d1 <= s_byte_ready_p;
s_sample_manch_bit_p_d1 <= sample_manch_bit_p_i;
if s_write_bit_to_byte_p = '1' then
s_byte <= s_byte(6 downto 0) & fd_rxd_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_write_bit_to_byte_p <= s_receiving_bytes and sample_bit_p_i;
s_byte_ready_p <= s_receiving_bytes and s_manch_bit_index_is_zero and sample_manch_bit_p_i
and (not s_fes_detected);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a counter that manages the position of an incoming FD_RXD bit inside a manch.
-- encoded byte (16 bits).
Incoming_Bits_Index: wf_decr_counter
generic map(g_counter_lgth => 4)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => s_manch_bit_index_top,
counter_load_i => s_manch_bit_index_load_p,
counter_decr_i => s_manch_bit_index_decr_p,
---------------------------------------------------
counter_o => s_manch_bit_index,
counter_is_zero_o => s_manch_bit_index_is_zero);
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_manch_bit_index_top <= to_unsigned (c_FSD'left-2, s_manch_bit_index_top'length) when s_receiving_pre = '1' else
to_unsigned (15, s_manch_bit_index_top'length) when s_receiving_bytes ='1' else
to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load_p <= '1' when (s_idle ='1') else
s_manch_bit_index_is_zero and sample_manch_bit_p_i when (s_receiving_pre = '1') or (s_receiving_bytes = '1') else --reloading for every new byte
'0';
s_manch_bit_index_decr_p <= sample_manch_bit_p_i when (s_receiving_fsd = '1') or (s_receiving_bytes = '1') else '0';
---------------------------------------------------------------------------------------------------
-- FSD detection --
---------------------------------------------------------------------------------------------------
-- FSD aux signals concurrent assignments:
s_fsd_bit <= s_receiving_fsd and c_FSD (to_integer(s_manch_bit_index));
s_fsd_last_bit <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_fsd_wrong_bit <= (s_fsd_bit xor fd_rxd_i) and sample_manch_bit_p_i;
---------------------------------------------------------------------------------------------------
-- FES detection --
---------------------------------------------------------------------------------------------------
-- Synchronous process FES_Detector: The s_arriving_fes register is storing the last 16
-- manch. encoded bits received and the s_fes_detected indicates whether they match the FES.
FES_Detector: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_receiving_bytes = '0' then
s_arriving_fes <= (others =>'0');
elsif s_receiving_bytes = '1' and sample_manch_bit_p_i = '1' then
s_arriving_fes <= s_arriving_fes (14 downto 0) & fd_rxd_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_fes_detected <= '1' when s_arriving_fes = c_FES else '0';
---------------------------------------------------------------------------------------------------
-- CRC Verification --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of the CRC calculator unit that verifies the received FCS field.
CRC_Verification : wf_crc
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_receiving_fsd,
data_bit_ready_p_i => s_write_bit_to_byte_p,
data_bit_i => fd_rxd_i,
crc_o => open,
---------------------------------------------------
crc_ok_p_o => s_CRC_ok_p);
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process that checks the position of the CRC bytes in the frame: The 1 uclk-
-- wide crc_ok_p coming from the CRC calculator is delayed for 1 complete byte. The matching of
-- this delayed pulse with the end of frame pulse (s_fes_detected), would confirm that the two
-- last bytes received before the FES were the correct CRC.
CRC_OK_pulse_delay: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or s_receiving_bytes = '0' then
s_CRC_ok_p_d <= '0';
s_CRC_ok_p_found <= '0';
else
if s_CRC_ok_p = '1' then
s_CRC_ok_p_found <= '1';
end if;
if s_byte_ready_p = '1' and s_CRC_ok_p_found = '1' then -- arrival of the next byte
s_CRC_ok_p_d <= '1'; -- (FES normally)
s_CRC_ok_p_found <= '0';
else
s_CRC_ok_p_d <= '0';
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Independent Timeout Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_decr_counter relying only on the system clock, as an additional
-- way to go back to IDLE state, in case any other logic is being stuck. The length of the counter
-- is defined using the slowest bit rate and considering reception of the upper limit of 133 bytes.
Session_Timeout_Counter: wf_decr_counter
generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => (others => '1'),
counter_load_i => s_idle,
counter_decr_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Concurrent signal assignments --
---------------------------------------------------------------------------------------------------
-- aux signals concurrent assignments :
s_manch_r_edge_p <= signif_edge_window_i and fd_rxd_r_edge_p_i;
s_manch_f_edge_p <= signif_edge_window_i and fd_rxd_f_edge_p_i;
s_bit_r_edge_p <= adjac_bits_window_i and fd_rxd_r_edge_p_i;
s_edge_out_manch_window_p <= (not signif_edge_window_i)and(fd_rxd_r_edge_p_i or fd_rxd_f_edge_p_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- output signals concurrent assignments :
byte_o <= s_byte;
byte_ready_p_o <= s_byte_ready_p_d1;
rx_osc_rst_o <= s_idle;
fss_received_p_o <= s_receiving_fsd and s_fsd_last_bit;
-- frame with correct FSS, CRC, FES (plus with number of bits multiple of 8)
fss_crc_fes_ok_p_o <= s_fes_detected and s_byte_ready_p_d1 and s_CRC_ok_p_d;
-- frame with wrong CRC; pulse upon FES detection
-- here the s_sample_manch_bit_p_d1 and not the s_byte_ready_p_d1 is used, so that frames
-- with number of bits not multiple of 8, but with correct FES, can be detected.
crc_wrong_p_o <= s_fes_detected and s_sample_manch_bit_p_d1 and (not s_CRC_ok_p_d);
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit | 8216b7090d027233d8bf4cbca5160f19 | 0.377564 | 4.730329 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/cf_pkg.vhd | 1 | 1,130 | -------------------------------------------------------------------------------
--! @file cf_pkg.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-12-01
--! @brief Critical FPGA package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--! @brief Package declaration of cf_pkg
--! @details
--! This provides types and constants for the Critical FPGA.
package cf_pkg is
---------------------------------------------------------------------------
-- Types and Constants
---------------------------------------------------------------------------
--! Critical FPGA version number
constant CF_VERSION_c : std_ulogic_vector(3 downto 0) := "0001";
--! Offset value for the first millisecond upon reception of COMMAND 0
constant cmd_0_pre_value_c : std_ulogic_vector(15 downto 0) := x"5F78"; -- 24440 * 25 ns = 611 us
--! Period for the millisecond strobe
constant ms_period_c : std_ulogic_vector(15 downto 0) := x"9C40"; -- 40000 * 25 ns = 1 ms
end package cf_pkg;
| mit | e2c687cc7cb9ca3ed8c6527d8a242884 | 0.485841 | 4.556452 | false | false | false | false |
malkadi/FGPU | RTL/floating_point/frsqrt.vhd | 1 | 10,206 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY frsqrt IS
PORT (
aclk : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END frsqrt;
ARCHITECTURE frsqrt_arch OF frsqrt IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF frsqrt_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 1,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 28,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END frsqrt_arch;
| gpl-3.0 | eed0d7f3cb76b34f4030165f109774e4 | 0.626004 | 3.250318 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_6Stations.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 6;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 19fef7ee9174447d8e0fb391a2fa1f93 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_6Stations_2AXI_2TAGM.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 6;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 664ebfccb750a5865747d71dcb1a88c8 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fdiv.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 1737168fdbac8c54c3bb02ebeb4d0f5f | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fslt_4CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 2;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 87792657787444a3f3840f3fc0bdcae7 | 0.567707 | 3.729005 | false | false | false | false |
joalcava/sparcv8-monocicle | windows_manager.vhd | 1 | 3,034 | library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.ALL;
entity windows_manager is
Port ( cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR(4 downto 0);
rs2 : in STD_LOGIC_VECTOR(4 downto 0);
rd : in STD_LOGIC_VECTOR(4 downto 0);
op : in STD_LOGIC_VECTOR(1 downto 0);
op3 : in STD_LOGIC_VECTOR(5 downto 0);
nrs1 : out STD_LOGIC_VECTOR(5 downto 0);
nrs2 : out STD_LOGIC_VECTOR(5 downto 0);
nrd : out STD_LOGIC_VECTOR(5 downto 0);
ncwp : out STD_LOGIC
);
end windows_manager;
architecture Behavioral of windows_manager is
signal rs1int,rs2int,rdint: integer range 0 to 39;
signal ncwp_signal: std_logic;
begin
process(cwp,rs1,rs2,rd,op,op3,ncwp_signal)
begin
if(op = "10") then
if(op3= "111100") then --Save (Resto)
ncwp_signal<= '0';
elsif(op3="111101") then --Restore (Sumo)
ncwp_signal<= '1';
else
ncwp_signal<=cwp;
end if;
end if;
if(rs1>="11000" and rs1<="11111") then--Formula registro de entrada (r[24] - r[31])
rs1int <= conv_integer(rs1)-(conv_integer(cwp)*16);
elsif(rs1>="10000" and rs1<="10111") then--Formula registro de local (r[16] - r[23])
rs1int <= conv_integer(rs1)+(conv_integer(cwp)*16);
elsif(rs1>="01000" and rs1<="01111") then--Formula registro de salida (r[8] - r[15])
rs1int <= conv_integer(rs1)+ (conv_integer(cwp)*16);
elsif(rs1>="00000" and rs1<="00111") then--Formula registro global (r[0] - r[7])
rs1int <= conv_integer(rs1);
end if;
if(rs2>="11000" and rs2<="11111") then--Formula registro de entrada (r[24] - r[31])
rs2int <= conv_integer(rs2)-(conv_integer(cwp)*16);
elsif(rs2>="10000" and rs2<="10111") then--Formula registro de local (r[16] - r[23])
rs2int <= conv_integer(rs2)+(conv_integer(cwp)*16);
elsif(rs2>="01000" and rs2<="01111") then--Formula registro de salida (r[8] - r[15])
rs2int <= conv_integer(rs2)+ (conv_integer(cwp)*16);
elsif(rs2>="00000" and rs2<="00111") then--Formula registro global (r[0] - r[7])
rs2int <= conv_integer(rs2);
end if;
if(rd>="11000" and rd<="11111") then--Formula registro de entrada (r[24] - r[31])
rdint <= conv_integer(rd)-(conv_integer(ncwp_signal)*16);
elsif(rd>="10000" and rd<="10111") then--Formula registro de local (r[16] - r[23])
rdint <= conv_integer(rd)+(conv_integer(ncwp_signal)*16);
elsif(rd>="01000" and rd<="01111") then--Formula registro de salida (r[8] - r[15])
rdint <= conv_integer(rd)+ (conv_integer(ncwp_signal)*16);
elsif(rd>="00000" and rd<="00111") then--Formula registro global (r[0] - r[7])
rdint <= conv_integer(rd);
end if;
end process;
nrs1 <= conv_std_logic_vector(rs1int, 6);
nrs2 <= conv_std_logic_vector(rs2int, 6);
nrd <= conv_std_logic_vector(rdint, 6);
ncwp <= ncwp_signal;
end Behavioral;
| gpl-3.0 | 1d109da7e771cd1c74ef7aded0e46bd4 | 0.605471 | 2.908917 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_LMEM_4_CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 2;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | bad7f64df357891e2bb7369fc279b515 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_2CUs_min_area.vhd | 2 | 23,421 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 1; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant FADD_DELAY : integer := 11;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 89a3edc16566820da70b6dbefdd22b1b | 0.569105 | 3.711139 | false | false | false | false |
malkadi/FGPU | RTL/DSP48E1.vhd | 1 | 1,615 | --
-- File: macc.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DSP48E1 is
generic (
SIZE_A : natural := 16;
SIZE_B : natural := 16;
SUB : boolean := false
); port (
clk, ce : in std_logic;
ain : in unsigned(SIZE_A-1 downto 0);
bin : in unsigned(SIZE_B-1 downto 0);
cin : in unsigned(SIZE_A+SIZE_B-1 downto 0); -- should be delayed 1 clock cycle after ain & bin
res : out unsigned(SIZE_A+SIZE_B-1 downto 0) := (others=>'0')-- ready after 3 clock cycles (reference is ain or bin)
);
end entity;
architecture rtl of DSP48E1 is
-- Declare intermediate values
signal a_reg : unsigned(SIZE_A-1 downto 0) := (others=>'0');
signal b_reg : unsigned(SIZE_B-1 downto 0) := (others=>'0');
signal sload_reg : std_logic := '0';
signal mult_reg : unsigned(SIZE_A+SIZE_B-1 downto 0):= (others=>'0');
signal c_reg : unsigned(SIZE_A+SIZE_B-1 downto 0) := (others=>'0');
begin
process(clk)
begin
if rising_edge(clk) then
if ce = '1' then
-- pipe 0
a_reg <= unsigned(ain);
b_reg <= unsigned(bin);
c_reg <= cin;
-- pipe 1
mult_reg <= a_reg * b_reg;
-- pipe 2
-- Store accumulation result into a register
if SUB then
res <= mult_reg - c_reg;
else
res <= mult_reg + c_reg;
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 7c6414c06caec29df218e44e173f8814 | 0.512693 | 3.473118 | false | false | false | false |
preusser/q27 | src/vhdl/top/xilinx/ml506_queens_uart.vhdl | 1 | 4,404 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ml506_queens_uart is
generic (
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 23;
COUNT_CYCLES : boolean := false;
CLK_FREQ : positive := 100000000;
CLK_MUL : positive := 20;
CLK_DIV : positive := 11;
BAUDRATE : positive := 115200;
SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte
);
port (
clkx : in std_logic;
rstx : in std_logic;
rx : in std_logic;
tx : out std_logic;
leds : out std_logic_vector(0 to 7)
);
end ml506_queens_uart;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
architecture rtl of ml506_queens_uart is
-- Global Control
signal clk : std_logic;
signal rst : std_logic;
-- Solver Status
signal avail : std_logic;
begin
-----------------------------------------------------------------------------
-- Generate Global Controls
blkGlobal: block is
signal clk_u : std_logic; -- Unbuffered Synthesized Clock
signal rst_s : std_logic_vector(1 downto 0) := (others => '0');
begin
DCM0 : DCM_BASE
generic map (
CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ),
CLKIN_DIVIDE_BY_2 => FALSE,
PHASE_SHIFT => 0,
CLKFX_MULTIPLY => CLK_MUL,
CLKFX_DIVIDE => CLK_DIV,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE", -- only using clkfx
DLL_FREQUENCY_MODE => "HIGH",
DFS_FREQUENCY_MODE => "HIGH",
DUTY_CYCLE_CORRECTION => TRUE,
STARTUP_WAIT => TRUE -- Delay until DCM LOCK
)
port map (
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => clk_u,
CLKFX180 => open,
LOCKED => open,
CLKFB => '0',
CLKIN => clkx,
RST => '0'
);
clk_buf : BUFG
port map (
I => clk_u,
O => clk
);
-- Reset Synchronization
process(clk)
begin
if rising_edge(clk) then
rst_s <= (not rstx) & rst_s(rst_s'left downto 1);
end if;
end process;
rst <= rst_s(0);
end block blkGlobal;
----------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_uart
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES,
CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)),
BAUDRATE => BAUDRATE,
SENTINEL => SENTINEL
)
port map (
clk => clk,
rst => rst,
rx => rx,
tx => tx,
avail => avail
);
----------------------------------------------------------------------------
-- Basic Status Output
leds <= std_logic_vector(to_unsigned((SOLVERS mod (2**(leds'length-1)-1))+1, leds'length-1)) & avail;
end rtl;
| agpl-3.0 | e6a3107b64f95506028b97b98abef1b6 | 0.50931 | 4.12746 | false | false | false | false |
joalcava/sparcv8-monocicle | Test_sum32b.vhd | 1 | 1,147 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Test_sum32b IS
END Test_sum32b;
ARCHITECTURE behavior OF Test_sum32b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sum32b
PORT(
Op1 : IN std_logic_vector(31 downto 0);
Op2 : IN std_logic_vector(31 downto 0);
R : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Op1 : std_logic_vector(31 downto 0) := (others => '0');
signal Op2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal R : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sum32b PORT MAP (
Op1 => Op1,
Op2 => Op2,
R => R
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Op1 <= x"00000014";
Op2 <= x"0000000A";
wait for 100 ns;
Op2 <= x"00000014";
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 96c475bf1bf6fc7a9cc38afb91f12c48 | 0.583261 | 3.562112 | false | true | false | false |
mohamed/fsl_perf_counter | hw/perf_counter_v1_00_a/hdl/vhdl/perf_counter_tb.vhd | 1 | 3,433 | -- Testbench of Performance Counter for MicroBlaze
-- Author: Mohamed A. Bamakhrama <m.a.m.bamakhrama@liacs.leidenuniv.nl>
-- Copyrights (c) 2010 by Universiteit Leiden
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity perf_counter_tb is
end perf_counter_tb;
architecture sim of perf_counter_tb is
constant clock_frequency : natural := 100_000_000;
constant clock_period : time := 1000 ms /clock_frequency;
signal clock : std_logic := '0';
signal rst : std_logic := '1'; --active high reset
signal tb_FSL_Clk : std_logic;
signal tb_FSL_Rst : std_logic;
signal tb_FSL_S_Clk : std_logic;
signal tb_FSL_S_Read : std_logic;
signal tb_FSL_S_Data : std_logic_vector(0 to 31);
signal tb_FSL_S_Control : std_logic;
signal tb_FSL_S_Exists : std_logic;
signal tb_FSL_M_Clk : std_logic;
signal tb_FSL_M_Write : std_logic;
signal tb_FSL_M_Data : std_logic_vector(0 to 31);
signal tb_FSL_M_Control : std_logic;
signal tb_FSL_M_Full : std_logic;
component perf_counter
generic
(
C_NUM_OF_COUNTERS : integer := 4;
C_LOG2_NUM_OF_COUNTERS : integer := 2;
C_EXT_RESET_HIGH : integer := 1
);
port
(
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : out std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
);
end component;
begin
clock <= not clock after clock_period/2;
tb_FSL_Clk <= clock;
tb_FSL_Rst <= rst;
dut: perf_counter
port map (
FSL_Clk => tb_FSL_Clk,
FSL_Rst => tb_FSL_Rst,
FSL_S_Clk => open,
FSL_S_Read => tb_FSL_S_Read,
FSL_S_Control => tb_FSL_S_Control,
FSL_S_Data => tb_FSL_S_Data,
FSL_S_Exists => tb_FSL_S_Exists,
FSL_M_Clk => open,
FSL_M_Write => tb_FSL_M_Write,
FSL_M_Data => tb_FSL_M_Data,
FSL_M_Control => tb_FSL_M_Control,
FSL_M_Full => tb_FSL_M_Full
);
stim: process
begin
rst <= '0';
wait for clock_period;
rst <= '1';
wait for clock_period;
rst <= '0';
tb_FSL_S_Exists <= '1';
tb_FSL_S_Data <= X"00000000";
wait for clock_period;
tb_FSL_S_Exists <= '1';
tb_FSL_S_Data <= X"00000001";
wait for clock_period;
tb_FSL_S_Exists <= '1';
tb_FSL_S_Data <= X"0000000A";
wait for clock_period;
tb_FSL_S_Exists <= '0';
tb_FSL_S_Data <= X"00000000";
wait for 10*clock_period;
tb_FSL_S_Exists <= '1';
tb_FSL_S_Data <= X"0000000B";
wait for clock_period;
tb_FSL_S_Exists <= '0';
tb_FSL_S_Data <= X"00000000";
wait for 10*clock_period;
tb_FSL_S_Exists <= '1';
tb_FSL_S_Data <= X"0000000C";
wait for clock_period;
tb_FSL_S_Exists <= '0';
tb_FSL_S_Data <= X"00000000";
wait for 10*clock_period;
assert false report "Testbench terminated successfully!" severity note;
assert false report "Simulation stopped" severity failure;
end process;
end sim;
| bsd-3-clause | 992361d659a098af85146ff17dffc90e | 0.566851 | 3.04614 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_jtag_controller.vhd | 1 | 26,343 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_jtag_controller |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_jtag_controller.vhd |
-- |
-- Description After the reception and validation of a consumed var_4 RP_DAT frame, the unit |
-- is responsible for driving the "nanoFIP, User Interface, JTAG Controller" signals |
-- JC_TCK, JC_TMS, JC_TDI and for sampling the JC_TDO input. |
-- |
-- o JC_TCK is a 5 MHz clock generated by the 40 MHz uclk; a cycle is created for |
-- every JC_TMS/ JC_TDI pair. |
-- |
-- o JC_TMS and JC_TDI are being retreived from the JC_consumed memory and are |
-- put to the corresponding outputs on each falling edge of the JC_TCK. |
-- |
-- o The first and second data bytes of the JC_consumed memory do not contain |
-- JC_TMS/ JC_TDI bits, but are used to indicate, in big endian order, the |
-- amount of JC_TMS and JC_TDI bits that have to be output. |
-- |
-- o the JC_TDO input is sampled on the rising edge of JC_TCK; only the last |
-- sampled JC_TDO bit is significant. It is registered and sent to the |
-- wf_production unit for it to be delivered in the next produced var_5 frame. |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 09/2011 |
-- Version v0.02 |
-- Depends on wf_reset_unit |
-- wf_consumption |
---------------- |
-- Last changes |
-- 07/07/2011 v0.01 EG First version |
-- 09/2011 v0.02 EG added counter for counting the outgoing TMS/TDI bits; combinatorial |
-- was too heavy; changed a bit state machine to include counter |
-- put session_timedout in the synchronous FSM process |
-- 11/2011 v0.021 EG timeout counter has different size (constant added) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_jtag_controller
--=================================================================================================
entity wf_jtag_controller is port(
-- INPUTS
-- nanoFIP User Interface, General signal
uclk_i : in std_logic; -- 40 MHz clock
-- nanoFIP User Interface, JTAG Controller signal
jc_tdo_i : in std_logic; -- JTAG TDO input
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the wf_consumption unit
jc_start_p_i : in std_logic; -- pulse upon validation of a var_4 RP_DAT frame
jc_mem_data_i : in std_logic_vector (7 downto 0); -- byte retreived from the JC_consumed memory
-- OUTPUTS
-- nanoFIP User Interface, JTAG Controller signals
jc_tms_o : out std_logic; -- JTAG TMS output
jc_tdi_o : out std_logic; -- JTAG TDI output
jc_tck_o : out std_logic; -- JTAG TCK output
-- Signal to the wf_production unit
jc_tdo_byte_o : out std_logic_vector (7 downto 0); -- byte containing the TDO sample for the next var_5
-- Signal to the wf_consumption unit
jc_mem_adr_rd_o : out std_logic_vector (8 downto 0));-- address of byte to be retreived from the JC_cons memory
end entity wf_jtag_controller;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_jtag_controller is
-- FSM
type jc_st_t is (IDLE, GET_BYTE, PLAY_BYTE, SET_ADDR);
signal jc_st, nx_jc_st : jc_st_t;
signal s_idle, s_play_byte, s_set_addr : std_logic;
signal s_not_play_byte : std_logic;
signal s_session_timedout : std_logic;
-- bytes counter
signal s_bytes_c, s_bytes_c_d1 : unsigned (6 downto 0);
-- retrieval of the number of TMS/ TDI bits that have to be delivered
signal s_frame_bits_lsb, s_frame_bits_msb : std_logic_vector (7 downto 0);
signal s_frame_bits : unsigned (15 downto 0);
-- number of TMS/ TDI bits delivered so far
signal s_bits_so_far : unsigned (15 downto 0);
-- TCK generation
signal s_tck, s_tck_c_is_full : std_logic;
signal s_tck_r_edge_p, s_tck_f_edge_p : std_logic;
signal s_tck_c, s_tck_period, s_tck_four_periods : unsigned (c_FOUR_JC_TCK_C_LGTH-1 downto 0);
signal s_tck_half_period, s_tck_quarter_period : unsigned (c_FOUR_JC_TCK_C_LGTH-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FSM --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- JTAG Controller FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- After the reception of a var_4 RP_DAT frame the FSM starts retrieving one by one bytes from
-- the JC_consumed memory. The first two bytes concatenated in big endian encoding indicate the
-- total amount of TMS/ TDI bits that have to be retrieved and output.
-- The rest of the bytes contain the TMS/ TDI bits.
-- The FSM goes back to IDLE if the counter that counts the amount the bits that have been output
-- reaches the total amount.
-- To add a robust layer of protection to the FSM, we have implemented a counter, dependent only on
-- the system clock, that from any state can bring the FSM back to IDLE. A frame with the maximum
-- number of TMS/ TDI bits needs: 122 bytes * ((4 * JC_TCK) + 2 uclk) seconds to be treated.
-- For a 5 MHz JC_TCK clock this is 103.7 us. We use a counter of c_JC_TIMEOUT_C_LGTH = 13 bits
-- which means that the FSM is reset if 204.8 us have passed since it has left the IDLE state.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process JC_FSM_Sync: storage of the current state of the FSM
JC_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or s_session_timedout = '1' then
jc_st <= IDLE;
else
jc_st <= nx_jc_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process JC_FSM_Comb_State_Transitions: Definition of the state
-- transitions of the FSM.
JC_FSM_Comb_State_Transitions: process (jc_st, s_bytes_c, s_frame_bits,s_bits_so_far, jc_start_p_i,
s_tck_c_is_full, s_tck_r_edge_p, s_tck_f_edge_p)
begin
case jc_st is
when IDLE =>
if jc_start_p_i = '1' then -- consumed var_4 frame validated
nx_jc_st <= SET_ADDR;
else
nx_jc_st <= IDLE;
end if;
when SET_ADDR =>
nx_jc_st <= GET_BYTE; -- 1 uclk cycle for the setting of the memory
-- address; byte available at the next cycle
when GET_BYTE =>
if s_bytes_c < 2 then -- 2 first bytes: amount of JC_TMS & JC_TDI bits
nx_jc_st <= SET_ADDR;
else -- the rest of the bytes have to be "played"
nx_jc_st <= PLAY_BYTE;
end if;
when PLAY_BYTE =>
if s_frame_bits <= 0 or s_frame_bits > c_MAX_FRAME_BITS then
nx_jc_st <= IDLE; -- outside expected limits
elsif s_frame_bits > s_bits_so_far then -- still available bits to go..
if s_tck_c_is_full = '1' then-- byte completed; a new one has
nx_jc_st <= SET_ADDR; -- to be retrieved
else -- byte being output
nx_jc_st <= PLAY_BYTE;
end if;
else -- last bit
if s_tck_r_edge_p = '1' or s_tck_f_edge_p = '1' then
nx_jc_st <= IDLE; -- wait until the completion of a JC_TCK cycle
else
nx_jc_st <= PLAY_BYTE;
end if;
end if;
when OTHERS =>
nx_jc_st <= IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process JC_FSM_Comb_Output_Signals: Definition of the output signals of the FSM.
JC_FSM_Comb_Output_Signals: process (jc_st)
begin
case jc_st is
when IDLE =>
-----------------------------
s_idle <= '1';
-----------------------------
s_set_addr <= '0';
s_play_byte <= '0';
when SET_ADDR =>
s_idle <= '0';
-----------------------------
s_set_addr <= '1';
-----------------------------
s_play_byte <= '0';
when GET_BYTE =>
s_idle <= '0';
s_set_addr <= '0';
s_play_byte <= '0';
when PLAY_BYTE =>
s_idle <= '0';
s_set_addr <= '0';
-----------------------------
s_play_byte <= '1';
-----------------------------
when OTHERS =>
-----------------------------
s_idle <= '1';
-----------------------------
s_set_addr <= '0';
s_play_byte <= '0';
end case;
end process;
---------------------------------------------------------------------------------------------------
-- JC_TCK generation --
---------------------------------------------------------------------------------------------------
-- Instantiation of a wf_incr_counter used for the generation of the JC_TCK output clock.
-- The counter is filled up after having counted 4 JC_TCK periods; this corresponds to the amount
-- of periods needed for outputting a full JC_TMS/ JC_TDI byte.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
JC_TCK_periods_counter: wf_incr_counter
generic map(g_counter_lgth => c_FOUR_JC_TCK_C_LGTH)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_not_play_byte,
counter_incr_i => s_play_byte,
counter_is_full_o => s_tck_c_is_full,
------------------------------------------
counter_o => s_tck_c);
------------------------------------------
s_not_play_byte <= not s_play_byte;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
JC_TCK_Construction: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_tck <= '1';
else
if s_tck_f_edge_p = '1' or s_tck_r_edge_p = '1' then
s_tck <= not s_tck;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_tck_four_periods <= (others => '1'); -- # uclk ticks for 4 JC_TCK periods i.e delivery of 1 byte
s_tck_period <= (s_tck_four_periods srl 2)+1; -- # uclk ticks for 1 JC_TCK period
s_tck_half_period <= (s_tck_four_periods srl 3)+1; -- # uclk ticks for 1/2 JC_TCK period
s_tck_quarter_period <= (s_tck_four_periods srl 4)+1; -- # uclk ticks for 1/4 JC_TCK period
-- s_tck_four_periods : >------------------------<
-- s_tck_period : >-----<
-- s_tck_half_period : >--<
-- s_tck_quarter_period: >-<
-- s_tck : -|__|--|__|--|__|--|__|-
s_tck_f_edge_p <= '1' when (s_tck_c = s_tck_quarter_period) or
(s_tck_c = (2*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (4*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (6*s_tck_half_period) +s_tck_quarter_period) else '0';
s_tck_r_edge_p <= '1' when (s_tck_c = s_tck_half_period+s_tck_quarter_period) or
(s_tck_c = (3*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (5*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (7*s_tck_half_period) +s_tck_quarter_period) else '0';
jc_tck_o <= s_tck;
---------------------------------------------------------------------------------------------------
-- Bytes counter --
---------------------------------------------------------------------------------------------------
-- Instantiation of a wf_incr_counter for the counting of the bytes that are being retreived from
-- the JC_cons memory.
JC_bytes_counter: wf_incr_counter
generic map(g_counter_lgth => 7)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_idle,
counter_incr_i => s_set_addr,
counter_is_full_o => open,
------------------------------------------
counter_o => s_bytes_c);
------------------------------------------
jc_mem_adr_rd_o <= std_logic_vector (resize((s_bytes_c + 2), jc_mem_adr_rd_o'length));
-- "+2" is bc the first 2 bytes in the memory (PDU_TYPE and LGTH) are not read
---------------------------------------------------------------------------------------------------
-- Delivered bits counter --
---------------------------------------------------------------------------------------------------
-- Creation of a counter counting the number of TMS and TDI bits that have been output.
-- The output of this counter, s_bits_so_far, could have been derived from the s_bytes_c with some
-- combinatorial logic, but then the timing performance was prohibiting.
JC_bits_counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_idle = '1' then
s_bits_so_far <= (others => '0');
elsif s_tck_f_edge_p = '1' then
s_bits_so_far <= s_bits_so_far + 2; -- 1 TMS + 1 TDI bits
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Frame bits retrieval --
---------------------------------------------------------------------------------------------------
-- Construction of the 16 bits word that indicates the amount of TMS/ TDI bits that have to be
-- played from this frame. The word is the result of the big endian concatenation of the 1st and
-- 2nd data bytes from the memory.
Bits_Number_retrieval: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_bytes_c_d1 <= (others => '0');
s_frame_bits_msb <= (others => '0');
s_frame_bits_lsb <= (others => '0');
else
s_bytes_c_d1 <= s_bytes_c;
if s_set_addr = '1' and s_bytes_c_d1 = 0 then
s_frame_bits_msb <= jc_mem_data_i;
end if;
if s_set_addr = '1' and s_bytes_c_d1 = 1 then
s_frame_bits_lsb <= jc_mem_data_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_frame_bits <= unsigned (s_frame_bits_msb) & unsigned (s_frame_bits_lsb);
---------------------------------------------------------------------------------------------------
-- TMS and TDI player --
---------------------------------------------------------------------------------------------------
-- Delivery of the jc_tms_o and jc_tdi_o bits on the falling edge of the jc_tck_o clock.
-- At the "PLAY_BYTE" state of the FSM the incoming jc_mem_data_i byte is decomposed to 4 TMS and
-- 4 TDI bits; a pair of TMS/ TDI bits is output on every TCK falling edge.
JC_TMS_TDI_player: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
jc_tms_o <= '0';
jc_tdi_o <= '0';
elsif s_tck_f_edge_p = '1' then
if s_tck_c < (s_tck_period) then -- 1st JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(7);
jc_tdi_o <= jc_mem_data_i(6);
elsif s_tck_c < (s_tck_period sll 1) then -- 2nd JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(5);
jc_tdi_o <= jc_mem_data_i(4);
elsif s_tck_c < ((s_tck_period sll 1)+s_tck_period) then -- 3rd JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(3);
jc_tdi_o <= jc_mem_data_i(2);
else
jc_tms_o <= jc_mem_data_i(1); -- 4th JC_TMS/ JC_TDI pair
jc_tdi_o <= jc_mem_data_i(0);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- TDO sampler --
---------------------------------------------------------------------------------------------------
-- Sampling of the jc_tdo_i input on the rising edge of the jc_tck_o clock. Only the last sampled
-- bit is significant and is delivered.
-- Note: on the side of the target TAP, the jc_tdo should be provided on the falling edge of jc_tck;
-- a falling jc_tck edge comes many uclk cycles before a rising one, which is nanoFIP's sampling
-- moment for jc_tdo; therefore on the rising edges, jc_tdo is not expected to be metastable.
-- That is why we have decided not to synchronize the jc_tdo input.
JC_TDO_sampling: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
jc_tdo_byte_o <= (others => '0');
elsif s_tck_r_edge_p = '1' then
jc_tdo_byte_o <= "0000000" & jc_tdo_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Independent Timeout Counter --
---------------------------------------------------------------------------------------------------
-- Instantiation of a wf_decr_counter relying only on the system clock, as an additional
-- way to go back to IDLE state, in case any other logic is being stuck. The timeout is 204.8 us.
Session_Timeout_Counter: wf_decr_counter
generic map(g_counter_lgth => c_JC_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => (others => '1'),
counter_load_i => s_idle,
counter_decr_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit | c0cd9f7557ef7195936935ee3744b6ef | 0.36932 | 4.68987 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_status_bytes_gen.vhd | 1 | 26,557 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_status_bytes_gen |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_status_bytes_gen.vhd |
-- |
-- Description Generation of the nanoFIP status and MPS status bytes. |
-- The unit is also responsible for outputting the "nanoFIP User Interface, |
-- NON_WISHBONE" signals U_CACER, U_PACER, R_TLER, R_FCSER, that correspond to |
-- nanoFIP status bits 2 to 5. |
-- |
-- The information contained in the nanoFIP status byte is coming from : |
-- o the wf_consumption unit, for the bits 4 and 5 |
-- o the "nanoFIP FIELDRIVE" inputs FD_WDGN and FD_TXER, for the bits 6 and 7 |
-- o the "nanoFIP User Interface, NON_WISHBONE" inputs (VAR_ACC) and outputs |
-- (VAR_RDY), for the bits 2 and 3. |
-- |
-- For the MPS byte, in memory mode, the refreshment and significance bits are set to|
-- 1 if the user has updated the produced variable var3 since its last transmission; |
-- the signal "nanoFIP User Interface, NON_WISHBONE" input VAR3_ACC,is used for this.|
-- In stand-alone mode the MPS status byte has the refreshment and significance set |
-- to 1. The same happens for the JTAG produced variable var_5, regardless of the |
-- mode. |
-- |
-- The MPS and the nanoFIP status byte are reset after having been sent or after a |
-- nanoFIP internal reset. |
-- |
-- Reminder: |
-- ______________________ __________ ____________________________________________ |
-- | nanoFIP STATUS BIT | NAME | CONTENTS | |
-- |______________________|__________|____________________________________________| |
-- | 0 | r1 | reserved | |
-- |______________________|__________|____________________________________________| |
-- | 1 | r2 | reserved | |
-- |______________________|__________|____________________________________________| |
-- | 2 | u_cacer | user cons var access error | |
-- |______________________|__________|____________________________________________| |
-- | 3 | u_pacer | user prod var access error | |
-- |______________________|__________|____________________________________________| |
-- | 4 | r_tler | received CTRL, PDU_TYPE or LGTH error | |
-- |______________________|__________|____________________________________________| |
-- | 5 | r_fcser | received FCS or bit number error | |
-- |______________________|__________|____________________________________________| |
-- | 6 | t_txer | transmit error (FIELDRIVE) | |
-- |______________________|__________|____________________________________________| |
-- | 7 | t_wder | watchdog error (FIELDRIVE) | |
-- |______________________|__________|____________________________________________| |
-- |
-- --------------------------------------------------------------------------- |
-- __________________ ______________ ______________ |
-- | MPS STATUS BIT | NAME | CONTENTS | |
-- |__________________|______________|______________| |
-- | 0 | refreshment | 1/0 | |
-- |__________________|______________|______________| |
-- | 1 | | 0 | |
-- |__________________|______________|______________| |
-- | 2 | significance | 1/0 | |
-- |__________________|______________|______________| |
-- | 3 | | 0 | |
-- |__________________|_____________ |______________| |
-- | 4-7 | | 000 | |
-- |__________________|_____________ |______________| |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2011 |
-- Version v0.04 |
-- Depends on wf_reset_unit |
-- wf_consumption |
-- wf_prod_bytes_retriever |
-- wf_prod_permit |
---------------- |
-- Last changes |
-- 07/07/2009 v0.01 PA First version |
-- 08/2010 v0.02 EG Internal extention of the var_rdy signals to avoid nanoFIP status |
-- errors few cycles after var_rdy deactivation |
-- 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_p_i |
-- for nanoFIP status bit 4; var_i input not needed as the signals |
-- nfip_status_r_fcser_p_i and nfip_status_r_tler_p_i check the var |
-- 06/2011 v0.04 EG all bits of nanoFIP status byte are reset upon rst_status_bytes_p_i |
-- var_i added for the jtag_var1 treatment; |
-- r_fcser, r_tler_o considered only for a cons variable (bf a wrong |
-- crc on an id-dat could give r_fcser) |
-- 11/2011 v0.042 EG the var3_acc_a_i and not the s_var3_acc_synch(3) was used for |
-- the refreshment:s |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_status_bytes_gen
--=================================================================================================
entity wf_status_bytes_gen is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz Clock
slone_i : in std_logic; -- stand-alone mode
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanaoFIP internal reset
-- nanoFIP FIELDRIVE
fd_txer_a_i : in std_logic; -- transmitter error
fd_wdgn_a_i : in std_logic; -- watchdog on transmitter
-- nanoFIP User Interface, NON-WISHBONE
var1_acc_a_i : in std_logic; -- variable 1 access
var2_acc_a_i : in std_logic; -- variable 2 access
var3_acc_a_i : in std_logic; -- variable 3 access
-- Signals from the wf_consumption unit
nfip_status_r_fcser_p_i : in std_logic; -- wrong CRC bytes received
nfip_status_r_tler_p_i : in std_logic; -- wrong PDU_TYPE, CTRL or LGTH bytes received
var1_rdy_i : in std_logic; -- variable 1 ready
var2_rdy_i : in std_logic; -- variable 2 ready
-- Signals from the wf_prod_bytes_retriever unit
rst_status_bytes_p_i : in std_logic; -- reset for both status bytes;
-- they are reset right after having been delivered
-- Signals from the wf_prod_permit unit
var3_rdy_i : in std_logic; -- variable 3 ready
-- Signal from the wf_engine_control unit
var_i : in t_var; -- variable type that is being treated
-- OUTPUTS
-- nanoFIP User Interface, NON-WISHBONE outputs
r_fcser_o : out std_logic; -- nanoFIP status byte, bit 5
r_tler_o : out std_logic; -- nanoFIP status byte, bit 4
u_cacer_o : out std_logic; -- nanoFIP status byte, bit 2
u_pacer_o : out std_logic; -- nanoFIP status byte, bit 3
-- Signal to the wf_prod_bytes_retriever
mps_status_byte_o : out std_logic_vector (7 downto 0); -- MPS status byte
nFIP_status_byte_o : out std_logic_vector (7 downto 0));-- nanoFIP status byte
end entity wf_status_bytes_gen;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_status_bytes_gen is
-- synchronizers
signal s_fd_txer_synch, s_fd_wdg_synch, s_var1_acc_synch : std_logic_vector (2 downto 0);
signal s_var2_acc_synch, s_var3_acc_synch : std_logic_vector (2 downto 0);
-- MPS refreshment/ significance bit
signal s_refreshment : std_logic;
-- nanoFIP status byte
signal s_nFIP_status_byte : std_logic_vector (7 downto 0);
-- extension of var_rdy signals
signal s_var1_rdy_c, s_var2_rdy_c, s_var3_rdy_c : unsigned (3 downto 0);
signal s_var1_rdy_c_incr,s_var1_rdy_c_reinit,s_var1_rdy_extended : std_logic;
signal s_var2_rdy_c_incr,s_var2_rdy_c_reinit,s_var2_rdy_extended : std_logic;
signal s_var3_rdy_c_incr,s_var3_rdy_c_reinit,s_var3_rdy_extended : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FD_TXER, FD_WDGN, VARx_ACC Synchronizers --
---------------------------------------------------------------------------------------------------
FIELDRIVE_inputs_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_fd_wdg_synch <= (others => '0');
s_fd_txer_synch <= (others => '0');
else
s_fd_wdg_synch <= s_fd_wdg_synch (1 downto 0) & not fd_wdgn_a_i;
s_fd_txer_synch <= s_fd_txer_synch (1 downto 0) & fd_txer_a_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
VAR_ACC_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_var1_acc_synch <= (others => '0');
s_var2_acc_synch <= (others => '0');
s_var3_acc_synch <= (others => '0');
else
s_var1_acc_synch <= s_var1_acc_synch(1 downto 0) & var1_acc_a_i;
s_var2_acc_synch <= s_var2_acc_synch(1 downto 0) & var2_acc_a_i;
s_var3_acc_synch <= s_var3_acc_synch(1 downto 0) & var3_acc_a_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- MPS status byte --
---------------------------------------------------------------------------------------------------
-- Synchronous process Refreshment_bit_Creation: Creation of the refreshment bit (used in
-- the MPS status byte). The bit is set to 1 if the user has updated the produced variable since
-- its last transmission. The process is checking if the signal VAR3_ACC has been asserted since
-- the last production of a variable.
Refreshment_bit_Creation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_refreshment <= '0';
else
if rst_status_bytes_p_i = '1' then -- bit reinitialized after a production
s_refreshment <= '0';
elsif s_var3_acc_synch(2) = '1' then -- indication that the memory has been accessed
s_refreshment <= '1';
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process MPS_byte_Generation: Creation of the MPS byte (Table 2, functional specs)
MPS_byte_Generation: process (slone_i, s_refreshment, var_i)
begin -- var_5, regardless of the mode, has signif. & refresh. set to 1
if slone_i = '1' or var_i = var_5 then -- stand-alone mode has signif. & refresh. set to 1
mps_status_byte_o (7 downto 3) <= (others => '0');
mps_status_byte_o (c_SIGNIFICANCE_INDEX) <= '1';
mps_status_byte_o (1) <= '0';
mps_status_byte_o (c_REFRESHMENT_INDEX) <= '1';
else
mps_status_byte_o (7 downto 3) <= (others => '0');
mps_status_byte_o (c_REFRESHMENT_INDEX) <= s_refreshment;
mps_status_byte_o (1) <= '0';
mps_status_byte_o (c_SIGNIFICANCE_INDEX) <= s_refreshment;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- nanoFIP status byte --
---------------------------------------------------------------------------------------------------
-- Synchronous process nFIP_status_byte_Generation: Creation of the nanoFIP status byte (Table 8,
-- functional specs)
nFIP_status_byte_Generation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_nFIP_status_byte <= (others => '0');
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- reinitialization after the transmission of a produced variable
if rst_status_bytes_p_i = '1' then
s_nFIP_status_byte <= (others => '0');
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- u_cacer
if ((s_var1_rdy_extended = '0' and s_var1_acc_synch(2) = '1') or
(s_var2_rdy_extended = '0' and s_var2_acc_synch(2) = '1')) then
-- since the last time the status
-- byte was delivered,
s_nFIP_status_byte(c_U_CACER_INDEX) <= '1'; -- the user logic accessed a cons.
-- var. when it was not ready
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- u_pacer
if (s_var3_rdy_extended = '0' and s_var3_acc_synch(2) = '1') then
-- since the last time the status
s_nFIP_status_byte(c_U_PACER_INDEX) <= '1'; -- byte was delivered,
-- the user logic accessed a prod.
-- var. when it was not ready
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_wder
if (s_fd_wdg_synch(2) = '1') then -- FIELDRIVE transmission error
s_nFIP_status_byte(c_T_WDER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_rxer
if (s_fd_txer_synch(2) = '1') then -- FIELDRIVE watchdog timer problem
s_nFIP_status_byte(c_T_TXER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler -- PDU_TYPE or LGTH error on a consumed var
if (nfip_status_r_tler_p_i = '1' and ((var_i = var_1) or (var_i = var_2) or (var_i = var_4) or (var_i = var_rst))) then
s_nFIP_status_byte(c_R_TLER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser -- CRC or bit number error on a consumed var
if (nfip_status_r_fcser_p_i = '1' and ((var_i = var_1) or (var_i = var_2) or (var_i = var_4) or (var_i = var_rst))) then
s_nFIP_status_byte(c_R_FCSER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of 3 wf_incr_counters used for the internal extension of each one of the
-- signals VAR1_RDY, VAR2_RDY, VAR3_RDY for 15 uclk cycles.
-- Enabled VAR_ACC during this period will not trigger a nanoFIP status byte error.
-- Note: actually it is the var_acc_synch(2) rather than the VAR_ACC used to check for access errors;
-- var_acc_synch(2) is 3 cycles later than VAR_ACC and therefore enabled VAR_ACC is ignored up to 12
-- uclk cycles (not 15 uclk cycles!) after the deassertion of the VAR_RDY.
Extend_VAR1_RDY: wf_incr_counter -- VAR1_RDY : __|---...---|___________________
generic map(g_counter_lgth => 4) -- s_var1_rdy_extended: __|---...------------------|____
port map( -- --> VAR_ACC here is OK! <--
uclk_i => uclk_i,
counter_reinit_i => s_var1_rdy_c_reinit,
counter_incr_i => s_var1_rdy_c_incr,
counter_is_full_o => open,
------------------------------------------
counter_o => s_var1_rdy_c);
------------------------------------------
s_var1_rdy_c_reinit <= var1_rdy_i or nfip_rst_i;
s_var1_rdy_c_incr <= '1' when s_var1_rdy_c < "1111" else '0';
s_var1_rdy_extended <= '1' when var1_rdy_i= '1' or s_var1_rdy_c_incr = '1' else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR2_RDY: wf_incr_counter
generic map(g_counter_lgth => 4)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_var2_rdy_c_reinit,
counter_incr_i => s_var2_rdy_c_incr,
counter_is_full_o => open,
------------------------------------------
counter_o => s_var2_rdy_c);
------------------------------------------
s_var2_rdy_c_reinit <= var2_rdy_i or nfip_rst_i;
s_var2_rdy_c_incr <= '1' when s_var2_rdy_c < "1111" else '0';
s_var2_rdy_extended <= '1' when var2_rdy_i= '1' or s_var2_rdy_c_incr = '1' else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR3_RDY: wf_incr_counter
generic map(g_counter_lgth => 4)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_var3_rdy_c_reinit,
counter_incr_i => s_var3_rdy_c_incr,
counter_is_full_o => open,
------------------------------------------
counter_o => s_var3_rdy_c);
------------------------------------------
s_var3_rdy_c_reinit <= var3_rdy_i or nfip_rst_i;
s_var3_rdy_c_incr <= '1' when s_var3_rdy_c < "1111" else '0';
s_var3_rdy_extended <= '1' when VAR3_RDY_i= '1' or s_var3_rdy_c_incr = '1' else '0';
---------------------------------------------------------------------------------------------------
-- Outputs --
---------------------------------------------------------------------------------------------------
nFIP_status_byte_o <= s_nFIP_status_byte;
u_cacer_o <= s_nFIP_status_byte(c_U_CACER_INDEX);
u_pacer_o <= s_nFIP_status_byte(c_U_PACER_INDEX);
r_tler_o <= s_nFIP_status_byte(c_R_TLER_INDEX);
r_fcser_o <= s_nFIP_status_byte(c_R_FCSER_INDEX);
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit | a93081e438468f7ec9c016cc0ec1a463 | 0.327898 | 4.646081 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_package.vhd | 1 | 53,662 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- WF_PACKAGE |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_package.vhd |
-- |
-- Description Definitions of constants, types, entities, functions |
-- Author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 11/01/2011 |
-- Version v0.05 |
---------------- |
-- Last changes |
-- 8/2010 v0.01 EG byte_array of all vars cleaned_up (ex: subs_i removed) |
-- 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of |
-- std_logic_vector (9 downto 0) to simplify calculations; cleaning-up |
-- 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs |
-- added DualClkRam |
-- 2/2011 v0.04 EG function for manch_encoder; cleaning up of constants+generics |
-- added CTRL bytes for RP_DAT_MSG and RP_DAT_RQ and RP_DAT_RQ_MSG |
-- 2/2011 v0.05 EG JTAG variables added |
-- 11/2011 v0.06 EG c_SESSION_TIMEOUT_C_LGTH, c_JTAG_TIMEOUT_C_LGTH added |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
-- Package declaration for wf_package
--=================================================================================================
package wf_package is
---------------------------------------------------------------------------------------------------
-- Constant regarding the user clock --
---------------------------------------------------------------------------------------------------
constant c_QUARTZ_PERIOD : real := 25.0;
---------------------------------------------------------------------------------------------------
-- Constants regarding the JTAG controller --
---------------------------------------------------------------------------------------------------
constant c_MAX_FRAME_BITS : natural := 976; -- maximum number of TMS/ TDI bits that can be sent
-- in one frame: 122 bytes * 8 bits
constant c_FOUR_JC_TCK_C_LGTH : natural := 5; -- length of a counter counting 4 JC_TCK periods;
-- the JC_TCK frequency is defined by this constant.
-- ex: 5 MHz JC_TCK period = 200 ns = 4 uclk periods,
-- 4 JC_TCK periods = 16 uclk, hence 5 bits counter.
-- Use c_FOUR_JC_TCK_C_LGTH = 6 for a 2.5 MHz JC_TCK,
-- c_FOUR_JC_TCK_C_LGTH = 7 for 1.25 MHz etc.
-- check also the c_JC_TIMEOUT_C_LGTH in the following paragraph
---------------------------------------------------------------------------------------------------
-- Constants regarding the session timeout counters --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- To add a robust layer of protection to the FSMs of the design, counters that depend only on
-- the system clock have being implemented; when they are filled up, they can bring the FSMs back
-- to the IDLE state.
-- For the wf_rx_deserializer, at the slowest bit rate, 31.25 kbps, the reception of the longest
-- frame should not last more than:
-- 133 bytes RP_DAT = 34048 us
-- This demands for a 21 bits counter.
-- Similarly, for the wf_tx_serializer, at the slowest bit rate, 31.25 kbps, the transmission of
-- the longest frame should not last more than:
-- 133 bytes RP_DAT = 34048 us
-- This demands for a 21 bits counter.
-- For the wf_engine_control, at the slowest bit rate, 31.25 kbps, the reception of an ID_DAT frame
-- followed by the reception/ transmission of an RP_DAT should not last more than:
-- 8 bytes ID_DAT = 2048 us
-- silence time = 4096 us
-- 133 bytes RP_DAT = 34048 us
-- ------------
-- 40192 us
-- This also demands for a 21 bits counter.
-- Therefore the same length of the timeout counters can be used for the FSMs of the wf_rx_deserializer,
-- wf_tx_serializer and wf_engine_control. The FSMs will be reset if 52 ms (complete 21 bit counter)
-- have passed since they have left the IDLE state.
constant c_SESSION_TIMEOUT_C_LGTH : natural := 21;
---------------------------------------------------------------------------------------------------
-- For the wf_jtag_controller FSM this timeout depends on the frequency of the JC_TCK.
-- The time the FSM needs to handle the biggest frame (122 bytes) is:
-- 122 * ((4 * JC_TCK_period) + 2 uclk_period)
-- For a 5 MHz JC_TCK this is 103.7 us and demands for a counter of 13 bits.
-- Use c_JC_TIMEOUT_C_LGTH = 13 also for a 2.5 MHz JC_TCK,
-- c_JC_TIMEOUT_C_LGTH = 14 for 1.25 MHz etc.
constant c_JC_TIMEOUT_C_LGTH : natural := 13;
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filter --
---------------------------------------------------------------------------------------------------
constant c_DEGLITCH_THRESHOLD : natural := 4;
---------------------------------------------------------------------------------------------------
-- Constant regarding the frame structure --
---------------------------------------------------------------------------------------------------
constant c_MAX_FRAME_BYTES : natural := 130; -- maximum number of bytes in a frame after the
-- FSS (counting starts from 0!)
---------------------------------------------------------------------------------------------------
-- Constants regarding the CRC calculation --
---------------------------------------------------------------------------------------------------
constant c_CRC_POLY_LGTH : natural := 16;
constant c_CRC_GENER_POLY : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0) := "0001110111001111";
constant c_CRC_VERIF_POLY : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0) := "0001110001101011";
---------------------------------------------------------------------------------------------------
-- Constants regarding the the ID_DAT and RP_DAT frame structure --
---------------------------------------------------------------------------------------------------
constant c_VP : std_logic_vector (1 downto 0) := "11";
constant c_VN : std_logic_vector (1 downto 0) := "00";
constant c_ONE : std_logic_vector (1 downto 0) := "10";
constant c_ZERO : std_logic_vector (1 downto 0) := "01";
constant c_PRE : std_logic_vector (15 downto 0) := c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO;
constant c_FSD : std_logic_vector (15 downto 0) := c_ONE & c_VP & c_VN & c_ONE & c_ZERO & c_VN & c_VP & c_ZERO;
constant c_FES : std_logic_vector (15 downto 0) := c_ONE & c_VP & c_VN & c_VP & c_VN & c_ONE & c_ZERO & c_ONE;
constant c_FSS : std_logic_vector (31 downto 0) := c_PRE & c_FSD;
---------------------------------------------------------------------------------------------------
-- Constants regarding the CTRL and PDU_TYPE bytes of ID_DAT and RP_DAT frames --
---------------------------------------------------------------------------------------------------
constant c_ID_DAT_CTRL_BYTE : std_logic_vector (5 downto 0) := "000011";
constant c_RP_DAT_CTRL_BYTE : std_logic_vector (5 downto 0) := "000010";
constant c_RP_DAT_MSG_CTRL_BYTE : std_logic_vector (5 downto 0) := "000110";
constant c_RP_DAT_RQ1_CTRL_BYTE : std_logic_vector (5 downto 0) := "101010";
constant c_RP_DAT_RQ2_CTRL_BYTE : std_logic_vector (5 downto 0) := "001010";
constant c_RP_DAT_RQ1_MSG_CTRL_BYTE : std_logic_vector (5 downto 0) := "101110";
constant c_RP_DAT_RQ2_MSG_CTRL_BYTE : std_logic_vector (5 downto 0) := "001110";
constant c_PDU_TYPE_BYTE : std_logic_vector (7 downto 0) := "01000000";
---------------------------------------------------------------------------------------------------
-- Constants regarding the nanoFIP status bits --
---------------------------------------------------------------------------------------------------
constant c_U_CACER_INDEX : integer := 2;
constant c_U_PACER_INDEX : integer := 3;
constant c_R_TLER_INDEX : integer := 4;
constant c_R_FCSER_INDEX : integer := 5;
constant c_T_TXER_INDEX : integer := 6;
constant c_T_WDER_INDEX : integer := 7;
---------------------------------------------------------------------------------------------------
-- Constant regarding the Model & Constructor decoding --
---------------------------------------------------------------------------------------------------
constant c_RELOAD_MID_CID : natural := 8;
---------------------------------------------------------------------------------------------------
-- Constant regarding the Transmitter --
---------------------------------------------------------------------------------------------------
constant c_TX_SCHED_BUFF_LGTH : natural := 4; -- length of the buffer of pulses used for
-- the transmission synchronization
---------------------------------------------------------------------------------------------------
-- Constants regarding the MPS status bits --
---------------------------------------------------------------------------------------------------
constant c_REFRESHMENT_INDEX : integer := 0;
constant c_SIGNIFICANCE_INDEX : integer := 2;
---------------------------------------------------------------------------------------------------
-- Constants regarding the position of bytes in the frame structure --
---------------------------------------------------------------------------------------------------
constant c_CTRL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000000"; -- 0
constant c_PDU_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000001"; -- 1
constant c_LGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
constant c_1st_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000011"; -- 3
constant c_2nd_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000100"; -- 4
constant c_CONSTR_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000110"; -- 6
constant c_MODEL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000111"; -- 7
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the P3_LGTH[2:0] settings --
---------------------------------------------------------------------------------------------------
-- Construction of a table for the P3_LGTH[2:0] settings
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
constant c_P3_LGTH_TABLE : t_unsigned_array(7 downto 0) :=
(0 => "00000010", -- 2 bytes
1 => "00001000", -- 8 bytes
2 => "00010000", -- 16 bytes
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000010"); -- reserved
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the bit rate --
---------------------------------------------------------------------------------------------------
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
constant c_PERIODS_COUNTER_LGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
-- period is 32000 ns and can be measured after
-- 1280 uclk ticks. Therefore a counter of 11
-- bits is the max needed for counting
-- transmission/ reception periods.
constant c_BIT_RATE_UCLK_TICKS_31_25Kbit: unsigned :=
to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_1_Mbit: unsigned :=
to_unsigned((1000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_2_5_Mbit: unsigned :=
to_unsigned((400 /integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
-- Creation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
type t_uclk_ticks is array (Natural range <>) of unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
constant c_BIT_RATE_UCLK_TICKS : t_uclk_ticks (3 downto 0):=
(0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit),
1 => (c_BIT_RATE_UCLK_TICKS_1_Mbit),
2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit),
3 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit));
constant c_2_PERIODS_COUNTER_LGTH : natural := 12; -- length of a counter counting 2 reception/
-- transmission periods
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the turnaround and silence times --
---------------------------------------------------------------------------------------------------
-- Construction of a table with the turnaround and silence times for each bit rate.
-- The table contains the number of uclk ticks corresponding to the turnaround/ silence times.
type t_timeouts is
record
turnaround : integer;
silence : integer;
end record;
constant c_31K25_INDEX : integer := 0;
constant c_1M_INDEX : integer := 1;
constant c_2M5_INDEX : integer := 2;
constant c_RESERVE_INDEX : integer := 3;
type t_timeouts_table is array (natural range <>) of t_timeouts;
constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) :=
(c_31K25_INDEX => (turnaround => integer (480000.0 / c_QUARTZ_PERIOD),
silence => integer (4096000.0 / c_QUARTZ_PERIOD)),
c_1M_INDEX => (turnaround => integer (14000.0 / c_QUARTZ_PERIOD),
silence => integer (150000.0 / c_QUARTZ_PERIOD)),
c_2M5_INDEX => (turnaround => integer (13500.0 / c_QUARTZ_PERIOD),
silence => integer (96000.0 / c_QUARTZ_PERIOD)),
c_RESERVE_INDEX => (turnaround => integer (480000.0 /C_QUARTZ_PERIOD),
silence => integer (4096000.0 /C_QUARTZ_PERIOD)));
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the consumed & produced variables --
---------------------------------------------------------------------------------------------------
-- Construction of a table that groups main information for all the variables
type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_4, var_5, var_whatever);
type t_byte_array is array (natural range <>) of std_logic_vector (7 downto 0);
type t_var_record is record
var : t_var;
hexvalue : std_logic_vector (7 downto 0);
prod_or_cons : std_logic_vector (1 downto 0);
broadcast : std_logic;
base_addr : unsigned (8 downto 0);
array_lgth : unsigned (7 downto 0);
byte_array : t_byte_array (0 to 15);
end record;
type t_var_array is array (natural range <>) of t_var_record;
constant c_VAR_PRESENCE_INDEX : integer := 0;
constant c_VAR_IDENTIF_INDEX : integer := 1;
constant c_VAR_3_INDEX : integer := 2;
constant c_VAR_1_INDEX : integer := 3;
constant c_VAR_2_INDEX : integer := 4;
constant c_VAR_RST_INDEX : integer := 5;
constant c_VAR_4_INDEX : integer := 6;
constant c_VAR_5_INDEX : integer := 7;
constant c_VARS_ARRAY : t_var_array(0 to 7) :=
(c_VAR_PRESENCE_INDEX => (var => var_presence,
hexvalue => x"14",
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_lgth => "00000111", -- 8 bytes in total including the CTRL byte
-- (counting starts from 0;-))
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => x"50", 2 => x"05",
3 => x"80", 4 => x"03" , 5 => x"00", 6 => x"f0",
7 => x"00", others => x"ff")),
c_VAR_IDENTIF_INDEX => (var => var_identif,
hexvalue => x"10",
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_lgth => "00001010", -- 11 bytes in total including the CTRL byte
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08",
3 => x"01", 4 => x"00" , 5 => x"00", 6 => x"ff",
7 => x"ff", 8 => x"00" , 9 => x"00", 10 => x"00",
others => x"ff")),
c_VAR_3_INDEX => (var => var_3,
hexvalue => x"06",
prod_or_cons => "10",
broadcast => '0',
base_addr => "100000000",
array_lgth => "00000001", -- only the CTRL and PDU_TYPE bytes are
-- predefined
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => c_PDU_TYPE_BYTE,
others => x"ff")),
c_VAR_1_INDEX => (var => var_1,
hexvalue => x"05",
prod_or_cons => "01",
broadcast => '0',
base_addr => "000000000",
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_2_INDEX => (var => var_2,
hexvalue => x"91",
prod_or_cons => "01",
broadcast => '1',
base_addr => "010000000",
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_RST_INDEX => (var => var_rst,
hexvalue => x"e0",
prod_or_cons => "01",
broadcast => '1',
base_addr => "---------",
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_4_INDEX => (var => var_4,
hexvalue => x"aa",
prod_or_cons => "01",
broadcast => '0',
base_addr => "000000000",
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_5_INDEX => (var => var_5,
hexvalue => x"ab",
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_lgth => "00000101", -- 6 bytes in total: CTRL, PDU_TYPE, LGTH,
-- 1 byte of data, nFIP status and MPS bytes
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => c_PDU_TYPE_BYTE,
others => x"ff"))); -- only the CTRL and PDU_TYPE bytes
-- are predefined
---------------------------------------------------------------------------------------------------
-- Components Declarations: --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component wf_rx_deserializer
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
rx_rst_i : in std_logic;
signif_edge_window_i : in std_logic;
adjac_bits_window_i : in std_logic;
fd_rxd_r_edge_p_i : in std_logic;
fd_rxd_f_edge_p_i : in std_logic;
fd_rxd_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic;
-----------------------------------------------------------------
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
crc_wrong_p_o : out std_logic;
fss_crc_fes_ok_p_o : out std_logic;
fss_received_p_o : out std_logic;
rx_osc_rst_o : out std_logic);
-----------------------------------------------------------------
end component wf_rx_deserializer;
---------------------------------------------------------------------------------------------------
component wf_tx_serializer
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
tx_start_p_i : in std_logic;
byte_request_accept_p_i : in std_logic;
last_byte_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
tx_sched_p_buff_i : in std_logic_vector (c_TX_SCHED_BUFF_LGTH -1 downto 0);
-----------------------------------------------------------------
tx_byte_request_p_o : out std_logic;
tx_completed_p_o : out std_logic;
tx_osc_rst_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic);
-----------------------------------------------------------------
end component wf_tx_serializer;
---------------------------------------------------------------------------------------------------
component wf_cons_bytes_processor
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
byte_ready_p_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
byte_i : in std_logic_vector (7 downto 0);
jc_mem_adr_rd_i : in std_logic_vector (8 downto 0);
-----------------------------------------------------------------
-- MODIFIED was (15 downto 0)
data_o : out std_logic_vector (7 downto 0);
jc_mem_data_o : out std_logic_vector (7 downto 0);
cons_ctrl_byte_o : out std_logic_vector (7 downto 0);
cons_pdu_byte_o : out std_logic_vector (7 downto 0);
cons_lgth_byte_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_cons_bytes_processor;
---------------------------------------------------------------------------------------------------
component wf_consumption is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
nfip_rst_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_ok_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
cons_bytes_excess_i : in std_logic;
var_i : in t_var;
byte_index_i : in std_logic_vector (7 downto 0);
jc_mem_adr_rd_i : in std_logic_vector (8 downto 0);
-----------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
jc_start_p_o : out std_logic;
-- MODIFIED was (15 downto 0)
data_o : out std_logic_vector (7 downto 0);
nfip_status_r_tler_p_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic;
jc_mem_data_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_consumption;
---------------------------------------------------------------------------------------------------
component wf_jtag_controller is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
jc_mem_data_i : in std_logic_vector (7 downto 0);
jc_start_p_i : in std_logic;
jc_tdo_i : in std_logic;
-----------------------------------------------------------------
jc_tms_o : out std_logic;
jc_tdi_o : out std_logic;
jc_tck_o : out std_logic;
jc_tdo_byte_o : out std_logic_vector (7 downto 0);
--TP39 : out std_logic;
jc_mem_adr_rd_o : out std_logic_vector (8 downto 0));
-----------------------------------------------------------------
end component wf_jtag_controller;
---------------------------------------------------------------------------------------------------
component wf_fd_receiver is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
fd_rxd_a_i : in std_logic;
nfip_rst_i : in std_logic;
rx_rst_i : in std_logic;
-----------------------------------------------------------------
rx_byte_o : out std_logic_vector (7 downto 0);
rx_byte_ready_p_o : out std_logic;
rx_fss_crc_fes_ok_p_o : out std_logic;
rx_fss_received_p_o : out std_logic;
rx_crc_wrong_p_o : out std_logic );
-----------------------------------------------------------------
end component wf_fd_receiver;
---------------------------------------------------------------------------------------------------
component wf_rx_osc is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
fd_rxd_edge_p_i : in std_logic;
rx_osc_rst_i : in std_logic;
-----------------------------------------------------------------
rx_manch_clk_p_o : out std_logic;
rx_bit_clk_p_o : out std_logic;
rx_signif_edge_window_o : out std_logic;
rx_adjac_bits_window_o : out std_logic );
-----------------------------------------------------------------
end component wf_rx_osc;
---------------------------------------------------------------------------------------------------
component wf_production is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
nfip_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (8 downto 0);
wb_data_i : in std_logic_vector (7 downto 0);
wb_ack_prod_p_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
data_lgth_i : in std_logic_vector (7 downto 0);
byte_request_accept_p_i : in std_logic;
var_i : in t_var;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
nfip_status_r_tler_p_i : in std_logic;
constr_id_dec_i : in std_logic_vector (7 downto 0);
model_id_dec_i : in std_logic_vector (7 downto 0);
jc_tdo_byte_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
byte_o : out std_logic_vector (7 downto 0);
u_cacer_o : out std_logic;
r_fcser_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
var3_rdy_o : out std_logic);
-----------------------------------------------------------------
end component wf_production;
---------------------------------------------------------------------------------------------------
component wf_fd_transmitter is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
tx_byte_i : in std_logic_vector (7 downto 0);
tx_byte_request_accept_p_i : in std_logic;
tx_last_data_byte_p_i : in std_logic;
tx_start_p_i : in std_logic;
-----------------------------------------------------------------
tx_byte_request_p_o : out std_logic;
tx_completed_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
tx_clk_o : out std_logic);
-----------------------------------------------------------------
end component wf_fd_transmitter;
---------------------------------------------------------------------------------------------------
component wf_tx_osc is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
tx_osc_rst_p_i : in std_logic;
-----------------------------------------------------------------
tx_clk_o : out std_logic;
tx_sched_p_buff_o : out std_logic_vector (c_TX_SCHED_BUFF_LGTH -1 downto 0));
-----------------------------------------------------------------
end component wf_tx_osc;
---------------------------------------------------------------------------------------------------
component wf_prod_bytes_retriever is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
nfip_rst_i : in std_logic;
model_id_dec_i : in std_logic_vector (7 downto 0);
constr_id_dec_i : in std_logic_vector (7 downto 0);
wb_clk_i : in std_logic;
wb_data_i : in std_logic_vector (7 downto 0);
wb_adr_i : in std_logic_vector (8 downto 0);
wb_ack_prod_p_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
nFIP_status_byte_i : in std_logic_vector (7 downto 0);
mps_status_byte_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
data_lgth_i : in std_logic_vector (7 downto 0);
byte_index_i : in std_logic_vector (7 downto 0);
byte_being_sent_p_i : in std_logic;
var3_rdy_i : in std_logic;
jc_tdo_byte_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
rst_status_bytes_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_prod_bytes_retriever;
---------------------------------------------------------------------------------------------------
component wf_engine_control
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic;
nostat_i : in std_logic;
tx_byte_request_p_i : in std_logic;
tx_completed_p_i : in std_logic;
rx_fss_received_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_ok_p_i : in std_logic;
-----------------------------------------------------------------
tx_byte_request_accept_p_o : out std_logic;
tx_last_data_byte_p_o : out std_logic;
tx_start_p_o : out std_logic;
prod_byte_index_o : out std_logic_vector (7 downto 0);
cons_byte_index_o : out std_logic_vector (7 downto 0);
prod_data_lgth_o : out std_logic_vector (7 downto 0);
cons_bytes_excess_o : out std_logic;
rx_rst_o : out std_logic;
var_o : out t_var);
-----------------------------------------------------------------
end component wf_engine_control;
---------------------------------------------------------------------------------------------------
component wf_reset_unit
port (
uclk_i : in std_logic;
wb_clk_i : in std_logic;
rstin_a_i : in std_logic;
rstpon_a_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
rst_i : in std_logic;
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
-----------------------------------------------------------------
wb_rst_o : out std_logic;
nFIP_rst_o : out std_logic;
rston_o : out std_logic;
fd_rstn_o : out std_logic);
-----------------------------------------------------------------
end component wf_reset_unit;
---------------------------------------------------------------------------------------------------
component wf_dualram_512x8_clka_rd_clkb_wr
port (
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (8 downto 0);
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (8 downto 0);
data_portb_i : in std_logic_vector (7 downto 0);
write_en_portb_i : in std_logic;
-----------------------------------------------------------------
data_porta_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_dualram_512x8_clka_rd_clkb_wr;
---------------------------------------------------------------------------------------------------
component dualram_512x8 is
port (
CLKA : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
DINA : in std_logic_vector (7 downto 0);
RWA : in std_logic;
CLKB : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DINB : in std_logic_vector (7 downto 0);
RWB : in std_logic;
RESETn : in std_logic;
-----------------------------------------------------------------
DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component dualram_512x8;
---------------------------------------------------------------------------------------------------
component wf_crc
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
start_crc_p_i : in std_logic;
data_bit_i : in std_logic;
data_bit_ready_p_i : in std_logic;
-----------------------------------------------------------------
crc_ok_p_o : out std_logic;
crc_o : out std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0));
-----------------------------------------------------------------
end component wf_crc;
---------------------------------------------------------------------------------------------------
component wf_manch_encoder is
generic (g_word_lgth : natural);
port (
word_i : in std_logic_vector (g_word_lgth-1 downto 0);
-----------------------------------------------------------------
word_manch_o : out std_logic_vector ((2*g_word_lgth)-1 downto 0));
-----------------------------------------------------------------
end component wf_manch_encoder;
---------------------------------------------------------------------------------------------------
component wf_rx_deglitcher
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
fd_rxd_a_i : in std_logic;
-----------------------------------------------------------------
fd_rxd_filt_o : out std_logic;
fd_rxd_filt_edge_p_o : out std_logic;
fd_rxd_filt_f_edge_p_o : out std_logic);
-----------------------------------------------------------------
end component wf_rx_deglitcher;
---------------------------------------------------------------------------------------------------
component wf_status_bytes_gen
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_rst_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
nfip_status_r_tler_p_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
rst_status_bytes_p_i : in std_logic;
var_i : in t_var;
-----------------------------------------------------------------
u_cacer_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
nFIP_status_byte_o : out std_logic_vector (7 downto 0);
mps_status_byte_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_status_bytes_gen;
---------------------------------------------------------------------------------------------------
component wf_bits_to_txd
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
txd_bit_index_i : in unsigned (4 downto 0);
data_byte_manch_i : in std_logic_vector (15 downto 0);
crc_byte_manch_i : in std_logic_vector (31 downto 0);
sending_fss_i : in std_logic;
sending_data_i : in std_logic;
sending_crc_i : in std_logic;
sending_fes_i : in std_logic;
stop_transmission_i : in std_logic;
tx_clk_p_i : in std_logic;
-----------------------------------------------------------------
txd_o : out std_logic;
tx_enable_o : out std_logic);
-----------------------------------------------------------------
end component wf_bits_to_txd;
---------------------------------------------------------------------------------------------------
component nanofip
port (
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
m_id_i : in std_logic_vector (3 downto 0);
c_id_i : in std_logic_vector (3 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
rstin_i : in std_logic;
rstpon_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
wb_clk_i : in std_logic;
dat_i : in std_logic_vector (15 downto 0);
adr_i : in std_logic_vector (9 downto 0);
rst_i : in std_logic;
stb_i : in std_logic;
cyc_i : in std_logic;
we_i : in std_logic;
jc_tdo_i : in std_logic;
-----------------------------------------------------------------
rston_o : out std_logic;
-- MODIFIED
-- s_id_o : out std_logic_vector (1 downto 0);
fd_rstn_o : out std_logic;
fd_txena_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
u_cacer_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
ack_o : out std_logic;
dat_o : out std_logic_vector (15 downto 0);
jc_tms_o : out std_logic;
jc_tdi_o : out std_logic;
jc_tck_o : out std_logic);
-----------------------------------------------------------------
end component nanofip;
---------------------------------------------------------------------------------------------------
component wf_model_constr_decoder
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
model_id_i : in std_logic_vector (3 downto 0);
constr_id_i : in std_logic_vector (3 downto 0);
-----------------------------------------------------------------
-- MODIFIED
-- s_id_o : out std_logic_vector (1 downto 0);
model_id_dec_o : out std_logic_vector (7 downto 0);
constr_id_dec_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_model_constr_decoder;
---------------------------------------------------------------------------------------------------
component wf_decr_counter is
generic (g_counter_lgth : natural := 5);
port (
uclk_i : in std_logic;
counter_rst_i : in std_logic;
counter_top_i : in unsigned (g_counter_lgth-1 downto 0);
counter_load_i : in std_logic;
counter_decr_i : in std_logic;
-----------------------------------------------------------------
counter_o : out unsigned (g_counter_lgth-1 downto 0);
counter_is_zero_o : out std_logic);
-----------------------------------------------------------------
end component wf_decr_counter;
---------------------------------------------------------------------------------------------------
component wf_incr_counter is
generic (g_counter_lgth : natural := 8);
port (
uclk_i : in std_logic;
counter_reinit_i : in std_logic;
counter_incr_i : in std_logic;
-----------------------------------------------------------------
counter_o : out unsigned (g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic);
-----------------------------------------------------------------
end component wf_incr_counter;
---------------------------------------------------------------------------------------------------
component wf_prod_data_lgth_calc is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
var_i : in t_var;
-----------------------------------------------------------------
prod_data_lgth_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component wf_prod_data_lgth_calc;
---------------------------------------------------------------------------------------------------
component wf_cons_outcome is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_rst_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
rx_fss_crc_fes_ok_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic;
cons_bytes_excess_i : in std_logic;
var_i : in t_var;
byte_index_i : in std_logic_vector (7 downto 0);
cons_ctrl_byte_i : in std_logic_vector (7 downto 0);
cons_pdu_byte_i : in std_logic_vector (7 downto 0);
cons_lgth_byte_i : in std_logic_vector (7 downto 0);
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
jc_start_p_o : out std_logic;
nfip_status_r_tler_p_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic);
-----------------------------------------------------------------
end component wf_cons_outcome;
---------------------------------------------------------------------------------------------------
component wf_prod_permit is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
var_i : in t_var;
-----------------------------------------------------------------
var3_rdy_o : out std_logic);
-----------------------------------------------------------------
end component wf_prod_permit;
---------------------------------------------------------------------------------------------------
component wf_wb_controller is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_id_i : in std_logic_vector (2 downto 0);
-----------------------------------------------------------------
wb_ack_prod_p_o : out std_logic;
wb_ack_p_o : out std_logic);
-----------------------------------------------------------------
end component wf_wb_controller;
---------------------------------------------------------------------------------------------------
function f_manch_encoder (word_i :std_logic_vector) return std_logic_vector;
end wf_package;
--=================================================================================================
-- package body
--=================================================================================================
package body wf_package is
---------------------------------------------------------------------------------------------------
-- Function for the encoding of a word to its Manchester 2 (manch.) equivalent.
-- Each bit "1" is replaced by "10" and each bit "0" by "01".
-- The manch. encoding ensures that there is one transition for each bit.
-- o bit : "0" "1"
-- o manch. encoded : "0 1" "1 0"
-- o scheme : _|- -|_
function f_manch_encoder (word_i : std_logic_vector) return std_logic_vector is
variable word_manch_o : std_logic_vector ((2*word_i'length) -1 downto 0);
begin
for I in word_i'range loop
word_manch_o (I*2) := not word_i(I);
word_manch_o (I*2+1) := word_i(I);
end loop;
-----------------------------------------------------------------
return word_manch_o;
-----------------------------------------------------------------
end function;
end wf_package;
--=================================================================================================
-- package end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
| mit | 3015df9275956f90d4317b852b3f5e3f | 0.376784 | 4.612119 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_prod_permit.vhd | 1 | 8,163 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_prod_permit |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_prod_permit.vhd |
-- |
-- Description Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY, |
-- according to the variable (var_i) that is being treated. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/1/2011 |
-- Version v0.01 |
-- Depends on wf_engine_control |
-- wf_reset_unit |
---------------- |
-- Last changes |
-- 1/2011 v0.01 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_prod_permit
--=================================================================================================
entity wf_prod_permit is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the wf_engine_control
var_i : in t_var; -- variable type that is being treated
-- OUTPUT
-- nanoFIP User Interface, NON-WISHBONE outputs
var3_rdy_o : out std_logic); -- signals the user that data can safely be written
end entity wf_prod_permit;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_prod_permit is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process VAR3_RDY_Generation:
-- VAR3_RDY: signals that the user can safely write to the produced variable memory or to the
-- DAT_I bus. It is deasserted right after the end of the reception of a correct var_3 ID_DAT frame
-- and stays de-asserted until the end of the transmission of the corresponding RP_DAT from nanoFIP.
-- Note: A correct ID_DAT frame along with the variable it contained is signaled by the var_i.
-- For produced variables, the signal var_i gets its value after the reception of a correct ID_DAT
-- frame and retains it until the end of the transmission of the corresponding RP_DAT.
-- An example follows:
-- frames : ___[ID_DAT,var_3]__[......RP_DAT......]______________[ID_DAT,var_3]___[.....RP_DAT..
-- var_i : var_whatever > < var_3 > < var_whatever > < var_3
-- VAR3_RDY: -------------------|__________________|--------------------------------|___________
VAR_RDY_Generation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
var3_rdy_o <= '0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
case var_i is
when var_3 => -- nanoFIP is producing
---------------------
var3_rdy_o <= '0'; -- while producing, VAR3_RDY is 0
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
var3_rdy_o <= '1';
end case;
end if;
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit | 171746912d0fb0d524111465b6567e6b | 0.290579 | 6.535629 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_engine_control.vhd | 1 | 51,040 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_engine_control |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_engine_control.vhd |
-- |
-- Description The wf_engine_control is following the reception of an incoming ID_DAT frame and |
-- o identifies the variable to be treated |
-- o signals accordingly the wf_production or wf_consumption units. |
-- |
-- Reminder: |
-- |
-- ID_DAT frame structure: |
-- ___________ ______ _______ ______ ___________ _______ |
-- |____FSS____|_CTRL_||__Var__|_SUBS_||____FCS____|__FES__| |
-- |
-- |
-- Produced RP_DAT frame structure: |
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| |
-- |
-- |
-- Consumed RP_DAT frame structure: |
-- ___________ ______ _______ ______ _________________________ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__| |
-- |
-- |
-- Turnaround time: Time between the end of the reception of an ID_DAT frame |
-- requesting for a variable to be produced and the starting of the delivery of a |
-- produced RP_DAT frame. |
-- |
-- Silence time : Maximum time that nanoFIP waits for a consumed RP_DAT frame |
-- after the reception of an ID_DAT frame that indicates a variable to be consumed. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 15/01/2011 |
-- Version v0.06 |
-- Depends on wf_reset_unit |
-- wf_fd_transmitter |
-- wf_fd_receiver |
---------------- |
-- Last changes |
-- 07/2009 v0.01 EB First version |
-- 08/2010 v0.02 EG E0 added as broadcast |
-- PDU,LGTH,CTRL bytes of RP_DAT checked bf VAR1_RDY/var_2_rdy assertion; |
-- if ID_DAT>8 bytes or RP_DAT>133 (bf reception of a FES) go to IDLE; |
-- state CONSUME_WAIT_FSS, for the correct use of the silence time(time |
-- stops counting when an RP_DAT frame has started) |
-- 12/2010 v0.03 EG state machine rewritten moore style; removed check on slone mode |
-- for #bytes>4; in slone no broadcast |
-- 01/2011 v0.04 EG signals named according to their origin; signals var_rdy (1,2,3), |
-- assert_rston_p_o,rst_nfip_and_fd_p_o, nFIP status bits and |
-- rx_byte_ready_p_o removed cleaning-up+commenting |
-- 02/2011 v0.05 EG Independent timeout counter added; time counter 18 digits instead of 15|
-- ID_DAT_FRAME_OK: corrected mistake if rx_fss_crc_fes_ok_p not |
-- activated; rx reset during production (rx_rst_o); |
-- cons_bytes_excess_o added |
-- tx_completed_p_i added (bf for the engine ctrl production was finished |
-- after the delivery of the last data byte (MPS)) |
-- 07/2011 v0.06 EG RST_RX state added |
-- 10/2011 v0.06b EG moved session_timedout in the synchronous FSM process |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_engine_control
--=================================================================================================
entity wf_engine_control is port(
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
nostat_i : in std_logic; -- if negated, nFIP status is sent
slone_i : in std_logic; -- stand-alone mode
-- nanoFIP WorldFIP Settings
p3_lgth_i : in std_logic_vector (2 downto 0); -- produced var user-data length
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
subs_i : in std_logic_vector (7 downto 0); -- subscriber number coding
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the wf_fd_transmitter unit
tx_completed_p_i : in std_logic; -- pulse upon termination of a
-- produced RP_DAT transmission
tx_byte_request_p_i : in std_logic; -- used for the counting of the
-- # produced bytes
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the wf_fd_receiver unit
rx_byte_i : in std_logic_vector (7 downto 0); -- deserialized ID_DAT/ RP_DAT byte
rx_byte_ready_p_i : in std_logic; -- indication of a new byte on rx_byte_i
rx_fss_crc_fes_ok_p_i : in std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- correct FSS, FES and CRC
rx_crc_wrong_p_i : in std_logic; -- indication of a frame with a wrong CRC
-- pulse upon FES detection
rx_fss_received_p_i : in std_logic; -- pulse upon FSS detection (ID/ RP_DAT)
-------------------------------------------------------------------------------------------------
-- OUTPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the wf_fd_transmitter unit
tx_start_p_o : out std_logic; -- launches the transmitter
tx_byte_request_accept_p_o : out std_logic; -- answer to tx_byte_request_p_i
tx_last_data_byte_p_o : out std_logic; -- indication of the last data-byte
-- (CRC & FES not included)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the wf_production unit
prod_data_lgth_o : out std_logic_vector (7 downto 0); -- # bytes of the Conrol & Data
-- fields of a prod RP_DAT frame
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the wf_fd_receiver
rx_rst_o : out std_logic; -- reset during production or
-- reset pulse when during reception a frame is rejected
-- (example: ID_DAT > 8 bytes, RP_DAT > 133 bytes,
-- wrong ID_DAT CTRL, variable, subs bytes)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the wf_consumption unit
cons_bytes_excess_o : out std_logic; -- indication of a consumed RP_DAT frame with more
-- than 133 bytes
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the wf_production & wf_consumption
prod_byte_index_o : out std_logic_vector (7 downto 0); -- index of the byte being
-- produced
cons_byte_index_o : out std_logic_vector (7 downto 0); -- index of the byte being
-- consumed
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the wf_production, wf_consumption, wf_reset_unit
var_o : out t_var); -- received variable; takes a value only after a
-- valid ID_DAT frame with SUBS the station's address
end entity wf_engine_control;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_engine_control is
-- FSM
type control_st_t is (IDLE,
ID_DAT_CTRL_BYTE, ID_DAT_VAR_BYTE, ID_DAT_SUBS_BYTE, ID_DAT_FRAME_OK,
CONSUME_WAIT_FSS, CONSUME, RST_RX,
PRODUCE_WAIT_TURNAR_TIME, PRODUCE);
signal control_st, nx_control_st : control_st_t;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_id_dat_frame_ok : std_logic;
signal s_cons_wait_FSS, s_consuming, s_rst_rx_p : std_logic;
signal s_prod_wait_turnar_time, s_producing : std_logic;
-- variable identification
signal s_var_aux, s_var : t_var;
signal s_var_identified, s_broadcast_var : std_logic;
signal s_prod_or_cons : std_logic_vector (1 downto 0);
-- time counters (turnaround, silence, timeout)
signal s_time_c_top, s_turnaround_time, s_silence_time : unsigned (17 downto 0);
signal s_time_c_load, s_time_c_is_zero : std_logic;
signal s_session_timedout : std_logic;
-- received & produced byte counters
signal s_rx_bytes_c, s_prod_bytes_c : unsigned (7 downto 0);
signal s_prod_bytes_c_rst, s_prod_bytes_c_inc : std_logic;
signal s_rx_bytes_c_rst, s_rx_bytes_c_inc : std_logic;
-- transmitter controls
signal s_tx_start_prod_p, s_tx_byte_request_accept_p, s_tx_byte_request_accept_p_d1 : std_logic;
signal s_tx_byte_request_accept_p_d2, s_tx_last_data_byte_p, s_tx_last_data_byte_p_d : std_logic;
-- length of produced data
signal s_prod_data_lgth : std_logic_vector (7 downto 0);
signal s_prod_data_lgth_match : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- engine_control FSM --
---------------------------------------------------------------------------------------------------
-- Central control FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- The FSM stays in IDLE until the reception of a FSS from the wf_fd_receiver.
-- It continues by checking one by one the bytes of the frame as they arrive:
-- o if the CTRL byte corresponds to an ID_DAT,
-- o if the variable byte corresponds to a defined variable,
-- o if the subscriber byte matches the station's address, or if the variable is a broadcast
-- o and if the frame finishes with a correct CRC and FES.
-- If any of the bytes above has been different than the expected, the FSM resets the wf_fd_receiver
-- and goes back to IDLE.
-- o if the ID_DAT frame has been correct and the received variable is a produced (var_presence,
-- var_identif, var_3, var_5) the FSM stays in the "PRODUCE_WAIT_TURNAR_TIME" state until the
-- expiration of the turnaround time and then jumps to the "PRODUCE" state, waiting for the
-- wf_fd_serializer to finish the transmission; then it goes back to IDLE.
-- o if the received variable is a consumed (var_1, var_2, var_rst, var_4) the FSM stays in the
-- "CONSUME_WAIT_FSS" state until the arrival of a FSS or the expiration of the silence time.
-- After the arrival of the FSS the FSM jumps to the "CONSUME" state, where it stays until the
-- end of the reception of the consumed frame (marked by a FES).
-- Note: In the case of a var_5, it is the wf_consumption unit that signals the start-up of
-- the wf_jtag_controller which will work in parallel and independently from the
-- wf_engine_control; i.e. new frames reception can take place while the
-- wf_jtag_controller is working.
-- To add a robust layer of protection to the FSM, a counter dependent only on the system clock
-- has been implemented, that from any state can bring the FSM back to IDLE. At any bit rate the
-- reception of an ID_DAT frame followed by the reception/ transmission of an RP_DAT should not
-- last more than 41ms. Hence, we have generated a 21 bits (c_SESSION_TIMEOUT_C_LGTH)counter that
-- will reset the machine if more than 52ms (complete 21 bit counter) have passed since it has
-- left this IDLE state.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process Engine_Control_FSM_Sync: storage of the current state of the FSM
Engine_Control_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or s_session_timedout = '1' then
control_st <= IDLE;
else
control_st <= nx_control_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Engine_Control_FSM_Comb_State_Transitions: definition of the state
-- transitions of the FSM.
Engine_Control_FSM_Comb_State_Transitions: process (s_time_c_is_zero, s_prod_or_cons,subs_i,
rx_crc_wrong_p_i, rx_fss_crc_fes_ok_p_i,
s_broadcast_var, s_var_identified, rx_byte_i,
rx_byte_ready_p_i, control_st, s_rx_bytes_c,
rx_fss_received_p_i,tx_completed_p_i)
begin
case control_st is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when IDLE =>
if rx_fss_received_p_i = '1' then -- new frame FSS detected
nx_control_st <= ID_DAT_CTRL_BYTE;
else
nx_control_st <= IDLE;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when ID_DAT_CTRL_BYTE =>
if (rx_byte_ready_p_i = '1') and (rx_byte_i(5 downto 0) = c_ID_DAT_CTRL_BYTE) then
nx_control_st <= ID_DAT_VAR_BYTE; -- check of ID_DAT CTRL byte
elsif rx_byte_ready_p_i = '1' then
nx_control_st <= RST_RX; -- byte different than the expected ID_DAT CTRL
else
nx_control_st <= ID_DAT_CTRL_BYTE; -- ID_DAT CTRL byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when ID_DAT_VAR_BYTE =>
if (rx_byte_ready_p_i = '1') and (s_var_identified = '1') then
nx_control_st <= ID_DAT_SUBS_BYTE; -- check of the ID_DAT variable
elsif rx_byte_ready_p_i = '1' then
nx_control_st <= RST_RX; -- byte not corresponding to an expected variable
else
nx_control_st <= ID_DAT_VAR_BYTE; -- ID_DAT variable byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when ID_DAT_SUBS_BYTE =>
if (rx_byte_ready_p_i = '1') and ((rx_byte_i = subs_i) or (s_broadcast_var = '1')) then
nx_control_st <= ID_DAT_FRAME_OK; -- checking of the ID_DAT subscriber
-- or if it is a broadcast variable
-- note: broadcast consumed vars are only treated in
-- memory mode, but at this moment we do not do this
-- check as the var_rst which is broadcast is treated
-- also in stand-alone mode.
elsif rx_byte_ready_p_i = '1' then -- not the station's address, neither a broadcast var
nx_control_st <= RST_RX;
else
nx_control_st <= ID_DAT_SUBS_BYTE; -- ID_DAT subscriber byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when ID_DAT_FRAME_OK =>
if (rx_fss_crc_fes_ok_p_i = '1') and (s_prod_or_cons = "10") then
nx_control_st <= PRODUCE_WAIT_TURNAR_TIME; -- ID_DAT frame ok! station has to PRODUCE
elsif (rx_fss_crc_fes_ok_p_i = '1') and (s_prod_or_cons = "01") then
nx_control_st <= CONSUME_WAIT_FSS; -- ID_DAT frame ok! station has to CONSUME
elsif (s_rx_bytes_c > 2) then -- 3 bytes after the arrival of the subscriber
nx_control_st <= RST_RX; -- byte, a FES has not been detected
else
nx_control_st <= ID_DAT_FRAME_OK; -- CRC & FES bytes being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when PRODUCE_WAIT_TURNAR_TIME =>
if s_time_c_is_zero = '1' then -- turnaround time passed
nx_control_st <= PRODUCE;
else
nx_control_st <= PRODUCE_WAIT_TURNAR_TIME; -- waiting for turnaround time to pass
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when CONSUME_WAIT_FSS =>
if rx_fss_received_p_i = '1' then -- FSS of the consumed RP_DAT arrived
nx_control_st <= CONSUME;
elsif s_time_c_is_zero = '1' then -- if the FSS of the consumed RP_DAT frame doesn't
nx_control_st <= RST_RX; -- arrive before the expiration of the silence time,
-- the engine goes back to IDLE
else
nx_control_st <= CONSUME_WAIT_FSS; -- counting silence time
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when CONSUME =>
if (rx_fss_crc_fes_ok_p_i = '1') or -- the cons frame arrived to the end, as expected
(rx_crc_wrong_p_i = '1') then -- FES detected but wrong CRC or wrong # bits
nx_control_st <= IDLE;
elsif (s_rx_bytes_c > c_MAX_FRAME_BYTES) then -- no FES detected after the max number of bytes
nx_control_st <= RST_RX;
else
nx_control_st <= CONSUME; -- consuming bytes
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when PRODUCE =>
if tx_completed_p_i = '1' then -- end of production (including CRC and FES)
nx_control_st <= IDLE;
else
nx_control_st <= PRODUCE; -- producing bytes
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when RST_RX => -- the current reception has finished
-- a reset pulse is sent to the wf_receiver
nx_control_st <= IDLE; -- which will start looking for a new FSS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
nx_control_st <= IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Engine_Control_FSM_Comb_Output_Signals : definition of the output
-- signals of the FSM
Engine_Control_FSM_Comb_Output_Signals: process (control_st)
begin
case control_st is
when IDLE =>
---------------------------------
s_idle_state <= '1';
---------------------------------
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when ID_DAT_CTRL_BYTE =>
s_idle_state <= '0';
---------------------------------
s_id_dat_ctrl_byte <= '1';
---------------------------------
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when ID_DAT_VAR_BYTE =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
---------------------------------
s_id_dat_var_byte <= '1';
---------------------------------
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when ID_DAT_SUBS_BYTE =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when ID_DAT_FRAME_OK =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
---------------------------------
s_id_dat_frame_ok <= '1';
---------------------------------
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when PRODUCE_WAIT_TURNAR_TIME =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
---------------------------------
s_prod_wait_turnar_time <= '1';
---------------------------------
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when CONSUME_WAIT_FSS =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
---------------------------------
s_cons_wait_FSS <= '1';
---------------------------------
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when CONSUME =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
---------------------------------
s_consuming <= '1';
---------------------------------
s_rst_rx_p <= '0';
s_producing <= '0';
when RST_RX =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
---------------------------------
s_rst_rx_p <= '1';
---------------------------------
s_producing <= '0';
when PRODUCE =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
---------------------------------
s_producing <= '1';
---------------------------------
when others =>
---------------------------------
s_idle_state <= '1';
---------------------------------
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
end case;
end process;
---------------------------------------------------------------------------------------------------
-- Counters for the number of bytes being received or produced --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of the wf_prod_data_lgth_calc unit that calculates the amount of bytes that have
-- to be transmitted when a variable is produced; the CTRL, MPS and nanoFIP_status bytes are
-- included; The FSS, CRC and FES bytes are not included!
Produced_Data_Length_Calculator: wf_prod_data_lgth_calc
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
slone_i => slone_i,
nostat_i => nostat_i,
p3_lgth_i => p3_lgth_i,
var_i => s_var,
-------------------------------------------------------
prod_data_lgth_o => s_prod_data_lgth);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter for the counting of the number of the bytes that are
-- being produced. The counter is reset at the "PRODUCE_WAIT_TURNAR_TIME" state of the FSM and
-- counts bytes following the "tx_byte_request_p_i" pulse in the "PRODUCE" state.
Prod_Bytes_Counter: wf_incr_counter
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_prod_bytes_c_rst,
counter_incr_i => s_prod_bytes_c_inc,
counter_is_full_o => open,
-------------------------------------------------------
counter_o => s_prod_bytes_c);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- --
s_prod_bytes_c_rst <= '0' when s_producing = '1' else '1';
s_prod_bytes_c_inc <= tx_byte_request_p_i when s_producing = '1' else '0';
-- when s_prod_data_lgth bytes have been counted,the signal s_prod_data_lgth_match is activated
s_prod_data_lgth_match <= '1' when s_prod_bytes_c = unsigned (s_prod_data_lgth) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter for the counting of the number of bytes that are being
-- received. The same counter is used for the bytes of an ID_DAT frame or a consumed RP_DAT
-- frame (hence the name of the counter is s_rx_bytes_c and not s_cons_bytes_c).
-- Regarding an ID_DAT frame: the FSS, CTRL, var and SUBS bytes are being followed by the
-- Engine_Control_FSM; the counter is used for the counting of the bytes from then on and until
-- the arrival of a FES. Therefore, the counter is reset at the "ID_DAT_SUBS_BYTE" state and counts
-- bytes following the "rx_byte_ready_p_i" pulse in the "ID_DAT_FRAME_OK" state.
-- Regarding a RP_DAT frame : the counter is reset at the "CONSUME_WAIT_FSS" state and counts
-- bytes following the "rx_byte_ready_p_i" pulse in the "CONSUME" state.
Rx_Bytes_Counter: wf_incr_counter
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_rx_bytes_c_rst,
counter_incr_i => s_rx_bytes_c_inc,
counter_is_full_o => open,
-------------------------------------------------------
counter_o => s_rx_bytes_c);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- --
s_rx_bytes_c_rst <= '0' when (s_id_dat_frame_ok = '1') or (s_consuming = '1') else '1';
s_rx_bytes_c_inc <= rx_byte_ready_p_i when (s_id_dat_frame_ok = '1') or (s_consuming = '1') else '0';
---------------------------------------------------------------------------------------------------
-- Independent Timeout Counter --
---------------------------------------------------------------------------------------------------
-- Instantiation of a wf_decr_counter relying only on the system clock as an additional
-- way to go back to IDLE state, in case any other logic is being stuck.
Session_Timeout_Counter: wf_decr_counter
generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => (others => '1'),
counter_load_i => s_idle_state,
counter_decr_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Turnaround & Silence times --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- retrieval of the turnaround and silence times (in equivalent number of uclk ticks) from the
-- c_TIMEOUTS_TABLE declared in the WF_PACKAGE unit.
s_turnaround_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).turnaround),
s_turnaround_time'length);
s_silence_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).silence),
s_turnaround_time'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_decr_counter for the counting of turnaround and silence times.
-- The same counter is used in both cases. The signal s_time_c_top initializes the counter
-- to either the turnaround or the silence time. If after the correct arrival of an ID_DAT frame
-- the identified variable is a produced one the counter loads to the turnaround time, whereas if
-- it had been a consumed variable it loads to the silence. The counting takes place during the
-- states "PRODUCE_WAIT_TURNAR_TIME" and "CONSUME_WAIT_FSS" respectively.
Turnaround_and_Silence_Time_Counter: wf_decr_counter
generic map(g_counter_lgth => 18)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => s_time_c_top,
counter_load_i => s_time_c_load,
counter_decr_i => '1', -- on each uclk tick
counter_o => open,
-------------------------------------------------------
counter_is_zero_o => s_time_c_is_zero);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- --
s_time_c_top <= s_turnaround_time when (s_id_dat_frame_ok = '1' and s_prod_or_cons = "10") else s_silence_time;
s_time_c_load <= '0' when s_prod_wait_turnar_time= '1' or s_cons_wait_FSS = '1' else '1';
---------------------------------------------------------------------------------------------------
-- Identification of the variable received by an ID_DAT frame --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The following process generates the signals:
-- o internal signal s_var_aux that locks to the value of the ID_DAT.Identifier.Variable byte
-- upon its arrival
-- o output signal var_o (or s_var, used also internally by the wf_prod_data_lgth_calc) that
-- locks to the value of the ID_DAT.Identifier.Variable byte at the end of the reception of a
-- valid ID_DAT frame, if the received SUBS byte matches the station's address.
-- For a produced var this takes place at the "PRODUCE_WAIT_TURNAR_TIME" state, and
-- for a consumed at the "CONSUME" state (not in the "consume_wait_silence_time", as at this
-- state there is no knowledge that a consumed RP_DAT frame will indeed arrive!).
-- (the process is very simple but very big as we decided not to use a for loop:s)
ID_DAT_var: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_var_aux <= var_whatever;
s_var <= var_whatever;
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
else
-------------------------------------------------------------------------------------------
if (s_idle_state = '1') or (s_id_dat_ctrl_byte = '1') then -- new frame initializations
s_var_aux <= var_whatever;
s_var <= var_whatever;
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
-------------------------------------------------------------------------------------------
elsif (s_id_dat_var_byte = '1') and (rx_byte_ready_p_i = '1') then -- var byte arrived
case rx_byte_i is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue =>
s_var_aux <= var_presence;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue =>
s_var_aux <= var_identif;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue =>
s_var_aux <= var_1;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_1_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_1_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue =>
s_var_aux <= var_2;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_2_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_2_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue =>
s_var_aux <= var_3;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_3_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_3_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue =>
s_var_aux <= var_rst;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_RST_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_RST_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_4_INDEX).hexvalue =>
s_var_aux <= var_4;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_4_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_4_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_5_INDEX).hexvalue =>
s_var_aux <= var_5;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_5_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_5_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
s_var_aux <= var_whatever;
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
end case;
-------------------------------------------------------------------------------------------
elsif (s_prod_wait_turnar_time = '1') or (s_consuming = '1') then -- ID_DAT OK!
s_var <= s_var_aux;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment (used by the FSM)
s_var_identified <= '1' when rx_byte_i = c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_4_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_5_INDEX).hexvalue else '0';
---------------------------------------------------------------------------------------------------
-- Signals Registration --
---------------------------------------------------------------------------------------------------
process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
tx_last_data_byte_p_o <= '0';
s_tx_last_data_byte_p_d <= '0';
s_tx_byte_request_accept_p_d1 <= '0';
s_tx_byte_request_accept_p_d2 <= '0';
s_tx_start_prod_p <= '0';
else
s_tx_last_data_byte_p_d <= s_tx_last_data_byte_p;
tx_last_data_byte_p_o <= s_tx_last_data_byte_p_d;
s_tx_byte_request_accept_p_d1 <= s_tx_byte_request_accept_p;
s_tx_byte_request_accept_p_d2 <= s_tx_byte_request_accept_p_d1;
s_tx_start_prod_p <= (s_prod_wait_turnar_time and s_time_c_is_zero);
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_tx_byte_request_accept_p <= s_producing and (tx_byte_request_p_i or s_tx_start_prod_p);
s_tx_last_data_byte_p <= s_producing and s_prod_data_lgth_match and tx_byte_request_p_i;
---------------------------------------------------------------------------------------------------
-- Concurrent Signal Assignments --
---------------------------------------------------------------------------------------------------
-- variable received by a valid ID_DAT frame that concerns this station
var_o <= s_var;
-- number of bytes for the CTRL & Data fields of a produced RP_DAT frame
prod_data_lgth_o <= s_prod_data_lgth;
-- response to wf_tx_serializer request for a byte
tx_byte_request_accept_p_o <= s_tx_byte_request_accept_p_d2;
-- index of the byte being produced/ consumed
prod_byte_index_o <= std_logic_vector (s_prod_bytes_c);
cons_byte_index_o <= std_logic_vector (s_rx_bytes_c);
-- The wf_fd_receiver receives a 1 uclk long reset pulse if during the reception of an ID or an
-- RP_DAT the engine control FSM has to go back to IDLE.
-- This may happen if : any of the CTRL, variable, subs bytes of an ID_DAT frame are wrong or
-- an ID_DAT is lasting more than 8 bytes or
-- an RP_DAT is lasting more than 133 bytes or
-- the silence times expires
-- the engine control FSM times out
-- After this reset, the receiver will discard any frame being received and will restart looking
-- for the FSS of a new one.
-- The wf_fd_receiver also stays reset during a production session.
rx_rst_o <= '1' when (s_rst_rx_p = '1') or
(s_prod_wait_turnar_time = '1') or (s_producing = '1') else '0';
-- indication of a consumed RP_DAT frame with more than 133 bytes
cons_bytes_excess_o <= '1' when (s_consuming = '1') and (s_rx_bytes_c > c_MAX_FRAME_BYTES) else '0';
-- production starts after the expiration of the turnaround time
tx_start_p_o <= s_tx_start_prod_p;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit | d0ec95f83ffee22c24cfb67416b999de | 0.373707 | 4.170957 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_fdiv.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 3;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 7a4f5154b026da226ca924c0f85e7de6 | 0.567707 | 3.729005 | false | false | false | false |
quicky2000/falling_edge_detector | falling_edge_detector.vhd | 1 | 1,733 | --
-- This file is part of falling edge_detector
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity falling_edge_detector is
Port ( clk : in std_logic;
rst : in std_logic;
input : in STD_LOGIC;
edge : out STD_LOGIC);
end falling_edge_detector;
architecture Behavioral of falling_edge_detector is
begin
process(clk,rst)
variable previous : std_logic := '0';
begin
if rst = '1' then
previous := '0';
edge <= '0' ;
elsif rising_edge(clk) then
if previous = '1' and input = '0' then
edge <= '1';
else
edge <= '0';
end if;
previous := input;
end if;
end process;
end Behavioral;
| gpl-3.0 | f0c4f726f80e41c2ba38b11a28b15c12 | 0.673399 | 3.911964 | false | false | false | false |
malkadi/FGPU | RTL/FGPU_simulation_pkg.vhd | 1 | 2,168 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_simulation_pkg is
type kernel_type is ( copy, max_half_atomic, bitonic, fadd, median, floydwarshall, fir_char4, add_float, parallelSelection, mat_mul, fir, xcorr, sum_atomic, fft_hard, mul_float, sobel);
-- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CONSTANT kernel_name : kernel_type := fft_hard;
-- byte(0), half word(1), word(2)
CONSTANT COMP_TYPE : natural := 2;
-- slli(0), sll(1), srli(2), srl(3), srai(4), sra(5), andi(6), and(7), ori(8), or(9), xori(10), xor(11), nor(12), sllb(13), srlb(14), srab(15)
CONSTANT LOGIC_OP : natural := 15;
CONSTANT REDUCE_FACTOR : natural := 1;
function get_kernel_index (name: in kernel_type) return integer;
end FGPU_simulation_pkg;
package body FGPU_simulation_pkg is
function get_kernel_index (name: in kernel_type) return integer is
begin
case name is
when copy =>
return 0;
when max_half_atomic =>
return 1;
when bitonic =>
return 2;
when fadd =>
return 3;
when median =>
return 4;
when floydwarshall =>
return 5;
when fir_char4 =>
return 6;
when add_float =>
return 7;
when parallelSelection =>
return 8;
when mat_mul =>
return 9;
when fir =>
return 10;
when xcorr =>
return 11;
when sum_atomic =>
return 12;
when fft_hard =>
return 13;
when mul_float =>
return 14;
when sobel =>
return 15;
when others=>
assert(false) severity failure;
return 0;
end case;
end; -- function reverse_any_vector
end FGPU_simulation_pkg;
| gpl-3.0 | f1c4c40dcb820380b0d4d95ff948d883 | 0.491697 | 3.992634 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_3Stations.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 3;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 2ca95b4b9c2a074064c361ef75e70df1 | 0.567707 | 3.729005 | false | false | false | false |
preusser/q27 | src/vhdl/queens/queens_slice_tb.vhdl | 1 | 23,501 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2016
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This testbench is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
entity queens_slice_tb is
end queens_slice_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture tb of queens_slice_tb is
constant L : natural := 2; -- pre-placed rings:
-- testbench only supports 2 currently
type tTest is record
cnt : positive;
bh : positive;
bv : positive;
bu : positive;
bd : positive;
end record tTest;
type tTests is array (natural range<>) of tTest;
function selectTests(s : positive) return tTests is
constant TESTS_8 : tTests := (
( 1 , 10,12,27,41),
( 1 , 10,12,82,25),
( 1 , 10,3,25,82),
( 1 , 10,3,41,27),
( 1 , 10,6,67,78),
( 1 , 10,6,78,67),
( 1 , 11,11,114,106),
( 1 , 11,11,116,102),
( 1 , 11,11,22,103),
( 1 , 11,11,23,102),
( 1 , 11,11,39,106),
( 1 , 11,11,49,108),
( 1 , 11,11,52,103),
( 1 , 11,11,70,108),
( 1 , 11,13,102,116),
( 1 , 11,13,102,23),
( 1 , 11,13,103,22),
( 1 , 11,13,103,52),
( 1 , 11,13,106,114),
( 1 , 11,13,106,39),
( 1 , 11,13,108,49),
( 1 , 11,13,108,70),
( 1 , 11,14,87,82),
( 1 , 11,7,82,87),
( 1 , 12,10,108,41),
( 1 , 12,10,37,25),
( 1 , 12,5,25,37),
( 1 , 12,5,41,108),
( 1 , 13,11,115,22),
( 1 , 13,11,115,52),
( 1 , 13,11,27,49),
( 1 , 13,11,27,70),
( 1 , 13,11,43,114),
( 1 , 13,11,43,39),
( 1 , 13,11,51,116),
( 1 , 13,11,51,23),
( 1 , 13,13,114,43),
( 1 , 13,13,116,51),
( 1 , 13,13,22,115),
( 1 , 13,13,23,51),
( 1 , 13,13,39,43),
( 1 , 13,13,49,27),
( 1 , 13,13,52,115),
( 1 , 13,13,70,27),
( 1 , 13,14,37,117),
( 1 , 13,7,117,37),
( 1 , 14,11,117,82),
( 1 , 14,13,82,117),
( 1 , 15,15,119,99),
( 1 , 15,15,99,119),
( 1 , 2,2,25,80),
( 1 , 2,2,76,80),
( 1 , 2,4,80,25),
( 1 , 2,4,80,76),
( 1 , 3,10,74,27),
( 1 , 3,10,76,82),
( 1 , 3,5,27,74),
( 1 , 3,5,82,76),
( 1 , 4,2,5,25),
( 1 , 4,2,5,76),
( 1 , 4,4,25,5),
( 1 , 4,4,76,5),
( 1 , 5,12,74,108),
( 1 , 5,12,76,37),
( 1 , 5,3,108,74),
( 1 , 5,3,37,76),
( 1 , 5,6,57,97),
( 1 , 5,6,97,57),
( 1 , 6,10,57,67),
( 1 , 6,10,97,78),
( 1 , 6,5,67,57),
( 1 , 6,5,78,97),
( 1 , 6,9,105,20),
( 1 , 6,9,106,88),
( 1 , 6,9,13,43),
( 1 , 6,9,20,105),
( 1 , 6,9,20,75),
( 1 , 6,9,43,13),
( 1 , 6,9,75,20),
( 1 , 6,9,88,106),
( 1 , 7,11,37,87),
( 1 , 7,13,87,37),
( 1 , 9,6,105,20),
( 1 , 9,6,106,13),
( 1 , 9,6,13,106),
( 1 , 9,6,20,105),
( 1 , 9,6,20,75),
( 1 , 9,6,43,88),
( 1 , 9,6,75,20),
( 1 , 9,6,88,43)
);
constant TESTS_9 : tTests := (
( 1 , 10,12,243,133),
( 1 , 10,12,243,257),
( 1 , 10,12,257,414),
( 1 , 10,12,322,414),
( 1 , 10,17,108,325),
( 1 , 10,17,325,108),
( 1 , 10,17,365,68),
( 1 , 10,17,68,365),
( 1 , 10,20,147,41),
( 1 , 10,20,149,281),
( 1 , 10,20,275,344),
( 1 , 10,20,296,402),
( 1 , 10,20,305,338),
( 1 , 10,20,53,401),
( 1 , 10,5,281,149),
( 1 , 10,5,338,305),
( 1 , 10,5,344,275),
( 1 , 10,5,401,53),
( 1 , 10,5,402,296),
( 1 , 10,5,41,147),
( 1 , 10,6,133,243),
( 1 , 10,6,257,243),
( 1 , 10,6,414,257),
( 1 , 10,6,414,322),
( 1 , 11,13,193,247),
( 1 , 11,13,199,181),
( 1 , 11,13,203,226),
( 1 , 11,13,449,181),
( 1 , 11,13,451,118),
( 1 , 11,14,167,211),
( 1 , 11,14,211,167),
( 1 , 11,14,211,417),
( 1 , 11,14,417,211),
( 1 , 11,19,452,109),
( 1 , 11,22,118,451),
( 1 , 11,22,181,199),
( 1 , 11,22,181,449),
( 1 , 11,22,226,203),
( 1 , 11,22,247,193),
( 1 , 11,25,109,452),
( 1 , 12,10,133,414),
( 1 , 12,10,257,414),
( 1 , 12,10,414,133),
( 1 , 12,10,414,257),
( 1 , 12,17,300,305),
( 1 , 12,17,305,300),
( 1 , 12,17,306,37),
( 1 , 12,17,37,306),
( 1 , 12,18,260,437),
( 1 , 12,18,284,389),
( 1 , 12,18,388,374),
( 1 , 12,20,237,259),
( 1 , 12,5,259,237),
( 1 , 12,9,374,388),
( 1 , 12,9,389,284),
( 1 , 12,9,437,260),
( 1 , 13,11,262,247),
( 1 , 13,11,263,181),
( 1 , 13,11,391,118),
( 1 , 13,11,422,226),
( 1 , 13,11,454,181),
( 1 , 13,19,138,174),
( 1 , 13,19,214,71),
( 1 , 13,19,313,420),
( 1 , 13,19,342,353),
( 1 , 13,21,133,379),
( 1 , 13,21,203,43),
( 1 , 13,21,205,331),
( 1 , 13,21,331,205),
( 1 , 13,21,334,355),
( 1 , 13,21,355,334),
( 1 , 13,21,379,133),
( 1 , 13,21,43,203),
( 1 , 13,25,174,138),
( 1 , 13,25,353,342),
( 1 , 13,25,420,313),
( 1 , 13,25,71,214),
( 1 , 13,26,118,391),
( 1 , 13,26,181,263),
( 1 , 13,26,181,454),
( 1 , 13,26,226,422),
( 1 , 13,26,247,262),
( 1 , 13,28,171,139),
( 1 , 13,28,323,477),
( 1 , 13,28,67,491),
( 1 , 13,7,139,171),
( 1 , 13,7,477,323),
( 1 , 13,7,491,67),
( 1 , 14,11,267,211),
( 1 , 14,11,406,167),
( 1 , 14,11,406,417),
( 1 , 14,11,458,211),
( 1 , 14,19,421,404),
( 1 , 14,19,83,331),
( 1 , 14,25,331,83),
( 1 , 14,25,404,421),
( 1 , 14,26,167,406),
( 1 , 14,26,211,267),
( 1 , 14,26,211,458),
( 1 , 14,26,417,406),
( 1 , 1,4,49,73),
( 1 , 1,4,73,49),
( 1 , 15,23,455,359),
( 1 , 15,29,359,455),
( 1 , 16,4,280,292),
( 1 , 16,4,292,280),
( 1 , 17,10,108,325),
( 1 , 17,10,325,108),
( 1 , 17,10,365,68),
( 1 , 17,10,68,365),
( 1 , 17,12,105,305),
( 1 , 17,12,153,37),
( 1 , 17,12,281,300),
( 1 , 17,12,328,306),
( 1 , 17,6,300,281),
( 1 , 17,6,305,105),
( 1 , 17,6,306,328),
( 1 , 17,6,37,153),
( 1 , 18,12,113,389),
( 1 , 18,12,65,437),
( 1 , 18,12,67,374),
( 1 , 18,20,165,25),
( 1 , 18,20,165,49),
( 1 , 18,24,101,356),
( 1 , 18,24,149,88),
( 1 , 18,3,356,101),
( 1 , 18,3,88,149),
( 1 , 18,5,25,165),
( 1 , 18,5,49,165),
( 1 , 18,6,374,67),
( 1 , 18,6,389,113),
( 1 , 18,6,437,65),
( 1 , 19,11,71,109),
( 1 , 19,13,162,174),
( 1 , 19,13,213,353),
( 1 , 19,13,214,71),
( 1 , 19,13,313,420),
( 1 , 19,14,331,404),
( 1 , 19,14,404,331),
( 1 , 19,21,181,204),
( 1 , 19,21,204,181),
( 1 , 19,22,174,162),
( 1 , 19,22,353,213),
( 1 , 19,22,420,313),
( 1 , 19,22,71,214),
( 1 , 19,26,109,71),
( 1 , 20,10,281,338),
( 1 , 20,10,338,281),
( 1 , 20,10,344,401),
( 1 , 20,10,401,344),
( 1 , 20,10,402,41),
( 1 , 20,10,41,402),
( 1 , 20,12,366,259),
( 1 , 20,18,330,25),
( 1 , 20,18,330,49),
( 1 , 20,6,259,366),
( 1 , 20,9,25,330),
( 1 , 20,9,49,330),
( 1 , 21,13,229,355),
( 1 , 21,13,322,379),
( 1 , 21,13,358,331),
( 1 , 21,13,397,334),
( 1 , 21,13,421,205),
( 1 , 21,13,422,43),
( 1 , 21,13,424,203),
( 1 , 21,13,445,133),
( 1 , 21,19,102,181),
( 1 , 21,19,346,204),
( 1 , 21,22,133,445),
( 1 , 21,22,203,424),
( 1 , 21,22,205,421),
( 1 , 21,22,331,358),
( 1 , 21,22,334,397),
( 1 , 21,22,355,229),
( 1 , 21,22,379,322),
( 1 , 21,22,43,422),
( 1 , 21,25,181,102),
( 1 , 21,25,204,346),
( 1 , 22,11,142,203),
( 1 , 22,11,220,451),
( 1 , 22,11,346,199),
( 1 , 22,11,346,449),
( 1 , 22,11,478,193),
( 1 , 22,19,234,162),
( 1 , 22,19,269,213),
( 1 , 22,19,452,214),
( 1 , 22,19,75,313),
( 1 , 22,21,229,397),
( 1 , 22,21,322,445),
( 1 , 22,21,358,421),
( 1 , 22,21,397,229),
( 1 , 22,21,421,358),
( 1 , 22,21,422,424),
( 1 , 22,21,424,422),
( 1 , 22,21,445,322),
( 1 , 22,25,162,234),
( 1 , 22,25,213,269),
( 1 , 22,25,214,452),
( 1 , 22,25,313,75),
( 1 , 22,26,193,478),
( 1 , 22,26,199,346),
( 1 , 22,26,203,142),
( 1 , 22,26,449,346),
( 1 , 22,26,451,220),
( 1 , 22,28,375,389),
( 1 , 22,28,418,426),
( 1 , 22,28,431,388),
( 1 , 22,7,388,431),
( 1 , 22,7,389,375),
( 1 , 22,7,426,418),
( 1 , 23,15,455,359),
( 1 , 23,23,103,423),
( 1 , 23,23,460,423),
( 1 , 23,29,423,103),
( 1 , 23,29,423,460),
( 1 , 23,30,359,455),
( 1 , 2,4,138,42),
( 1 , 24,18,332,356),
( 1 , 24,18,338,88),
( 1 , 2,4,42,138),
( 1 , 24,9,356,332),
( 1 , 24,9,88,338),
( 1 , 25,11,364,452),
( 1 , 25,13,234,138),
( 1 , 25,13,269,342),
( 1 , 25,13,452,214),
( 1 , 25,13,75,313),
( 1 , 25,14,421,83),
( 1 , 25,14,83,421),
( 1 , 25,21,102,346),
( 1 , 25,21,346,102),
( 1 , 25,22,138,234),
( 1 , 25,22,214,452),
( 1 , 25,22,313,75),
( 1 , 25,22,342,269),
( 1 , 25,26,452,364),
( 1 , 26,13,142,422),
( 1 , 26,13,220,391),
( 1 , 26,13,346,263),
( 1 , 26,13,346,454),
( 1 , 26,13,478,262),
( 1 , 26,14,267,406),
( 1 , 26,14,406,267),
( 1 , 26,14,406,458),
( 1 , 26,14,458,406),
( 1 , 26,19,364,71),
( 1 , 26,22,262,478),
( 1 , 26,22,263,346),
( 1 , 26,22,391,220),
( 1 , 26,22,422,142),
( 1 , 26,22,454,346),
( 1 , 26,25,71,364),
( 1 , 27,27,103,103),
( 1 , 27,27,103,460),
( 1 , 27,27,108,455),
( 1 , 27,27,198,365),
( 1 , 27,27,365,198),
( 1 , 27,27,455,108),
( 1 , 27,27,460,103),
( 1 , 27,27,460,460),
( 1 , 28,13,388,491),
( 1 , 28,13,389,477),
( 1 , 28,13,426,139),
( 1 , 28,22,139,426),
( 1 , 28,22,477,389),
( 1 , 28,22,491,388),
( 1 , 29,15,461,455),
( 1 , 29,23,459,103),
( 1 , 29,23,459,460),
( 1 , 29,29,103,459),
( 1 , 29,29,460,459),
( 1 , 29,30,455,461),
( 1 , 30,23,461,455),
( 1 , 30,29,455,461),
( 1 , 3,18,52,149),
( 1 , 3,18,77,101),
( 1 , 3,9,101,77),
( 1 , 3,9,149,52),
( 1 , 4,1,280,73),
( 1 , 4,1,292,49),
( 1 , 4,16,49,292),
( 1 , 4,16,73,280),
( 1 , 4,2,162,42),
( 1 , 4,2,168,138),
( 1 , 4,8,138,168),
( 1 , 4,8,42,162),
( 1 , 5,10,147,296),
( 1 , 5,10,149,305),
( 1 , 5,10,275,53),
( 1 , 5,10,296,147),
( 1 , 5,10,305,149),
( 1 , 5,10,53,275),
( 1 , 5,12,385,237),
( 1 , 5,18,280,165),
( 1 , 5,18,304,165),
( 1 , 5,6,237,385),
( 1 , 5,9,165,280),
( 1 , 5,9,165,304),
( 1 , 6,10,243,257),
( 1 , 6,10,243,322),
( 1 , 6,10,257,243),
( 1 , 6,10,322,243),
( 1 , 6,17,105,281),
( 1 , 6,17,153,328),
( 1 , 6,17,281,105),
( 1 , 6,17,328,153),
( 1 , 6,18,221,67),
( 1 , 6,18,323,113),
( 1 , 6,18,347,65),
( 1 , 6,20,385,366),
( 1 , 6,5,366,385),
( 1 , 6,9,113,323),
( 1 , 6,9,65,347),
( 1 , 6,9,67,221),
( 1 , 7,13,375,323),
( 1 , 7,13,418,171),
( 1 , 7,13,431,67),
( 1 , 7,22,171,418),
( 1 , 7,22,323,375),
( 1 , 7,22,67,431),
( 1 , 8,4,162,168),
( 1 , 8,4,168,162),
( 1 , 9,12,221,388),
( 1 , 9,12,323,284),
( 1 , 9,12,347,260),
( 1 , 9,20,280,330),
( 1 , 9,20,304,330),
( 1 , 9,24,52,338),
( 1 , 9,24,77,332),
( 1 , 9,3,332,77),
( 1 , 9,3,338,52),
( 1 , 9,5,330,280),
( 1 , 9,5,330,304),
( 1 , 9,6,260,347),
( 1 , 9,6,284,323),
( 1 , 9,6,388,221)
);
constant TESTS_11 : tTests := (
( 1 , 18,5,4424,167 ),
( 1 , 18,5,4676,5280 ),
( 1 , 18,5,6736,1160 ),
( 2 , 18,65,4256,676 ),
( 2 , 18,65,676,4256 ),
( 1 , 18,66,4232,708 ),
( 1 , 18,66,568,2193 ),
( 1 , 18,66,660,4177 ),
( 1 , 18,66,676,4672 ),
( 2 , 20,34,2570,680 ),
( 1 , 20,34,4369,5285 ),
( 1 , 20,34,4529,5125 ),
( 1 , 20,34,4618,708 ),
( 1 , 20,34,5125,4529 ),
( 1 , 20,34,5285,4369 ),
( 2 , 20,34,680,2570 ),
( 1 , 20,3,4688,167 ),
( 1 , 20,3,4688,646 ),
( 1 , 20,34,708,4618 ),
( 1 , 97,26,6409,2404 ),
( 1 , 97,28,4882,7330 ),
( 2 , 26,81,2374,4379 ),
( 1 , 26,81,2438,4395 ),
( 1 , 26,81,2441,2439 ),
( 1 , 26,81,3336,6371 ),
( 1 , 41,84,2318,203 ),
( 2 , 41,84,2326,4427 ),
( 1 , 44,81,6371,534 ),
( 1 , 44,81,6801,3122 ),
( 2 , 44,81,6929,3154 ),
( 1 , 44,81,7218,4658 ),
( 1 , 44,81,741,1038 ),
( 1 , 65,24,2145,2340 ),
( 2 , 65,36,4256,1192 ),
( 2 , 65,36,676,161 ),
( 1 , 65,40,2097,2224 ),
( 1 , 65,40,418,4482 ),
( 1 , 66,10,1232,1569 )
);
constant TESTS_12 : tTests := (
( 2 , 75,165,787,4891 ),
( 2 , 76,196,10914,21521 ),
( 2 , 76,35,21521,10914 ),
( 2 , 77,170,10531,5661 ),
( 2 , 77,85,5661,10531 ),
( 2 , 80,12,12648,20489 ),
( 3 , 80,12,24804,18438 ),
( 2 , 80,20,26784,22660 ),
( 2 , 80,40,22660,26784 ),
( 3 , 80,48,18438,24804 ),
( 2 , 80,48,20489,12648 ),
( 2 , 82,104,13857,18701 ),
( 2 , 82,168,7316,16458 ),
( 2 , 82,21,16458,7316 ),
( 2 , 82,22,18701,13857 ),
( 2 , 82,42,22532,18074 ),
( 2 , 82,74,13872,18693 ),
( 2 , 82,74,13872,20553 ),
( 2 , 82,82,18693,13872 ),
( 2 , 82,82,20553,13872 ),
( 2 , 82,84,18074,22532 ),
( 2 , 84,11,20805,2586 ),
( 2 , 84,137,22820,10337 ),
( 2 , 84,145,10337,22820 ),
( 2 , 84,162,9377,27684 ),
( 2 , 84,208,2586,20805 ),
( 2 , 84,69,27684,9377 ),
( 2 , 84,74,22532,11441 ),
( 2 , 84,82,11441,22532 ),
( 2 , 85,108,22042,11292 ),
( 2 , 85,178,10531,23604 ),
( 2 , 85,54,11292,22042 ),
( 2 , 85,77,23604,10531 ),
( 2 , 88,100,5149,10409 ),
( 2 , 88,38,10409,5149 ),
( 2 , 90,195,20805,9778 ),
( 2 , 90,195,9778,20805 ),
( 2 , 98,104,21777,11304 ),
( 2 , 98,148,4441,25106 ),
( 2 , 98,22,11304,21777 ),
( 2 , 98,41,25106,4441 ),
( 2 , 98,44,21785,18474 ),
( 2 , 98,52,18474,21785 ),
( 1 , 99,116,19754,21529 ),
( 1 , 99,120,15379,18740 ),
( 1 , 99,120,6419,27700 ),
( 1 , 99,150,26154,17701 ),
( 1 , 99,150,27696,6449 ),
( 1 , 99,150,28977,9769 ),
( 1 , 99,156,18701,23122 ),
( 1 , 99,165,17225,18713 ),
( 1 , 99,165,18713,17225 ),
( 1 , 99,170,25393,13353 ),
( 1 , 99,172,17677,27218 ),
( 1 , 99,172,22809,19017 ),
( 1 , 99,172,23576,27233 ),
( 1 , 99,180,13105,25626 ),
( 1 , 99,180,17677,27192 ),
( 1 , 99,180,19740,25129 ),
( 1 , 99,198,17177,17993 ),
( 1 , 99,198,17177,18737 ),
( 1 , 99,204,17176,27700 ),
( 1 , 99,204,4889,11313 ),
( 1 , 99,212,11801,4401 ),
( 1 , 99,212,11824,21554 ),
( 1 , 99,212,19760,21546 ),
( 1 , 99,212,3608,20787 ),
( 1 , 99,216,22050,19021 ),
( 1 , 99,27,19021,22050 ),
( 1 , 99,30,18740,15379 ),
( 1 , 99,30,27700,6419 ),
( 1 , 99,43,20787,3608 ),
( 1 , 99,43,21546,19760 ),
( 1 , 99,43,21554,11824 ),
( 1 , 99,43,4401,11801 ),
( 1 , 99,45,25129,19740 ),
( 1 , 99,45,25626,13105 )
);
begin
case s is
when 8 => return TESTS_8;
when 9 => return TESTS_9;
when 11 => return TESTS_11;
when 12 => return TESTS_12;
when others => null;
end case;
report "Unsupported problem size "&integer'image(s)&'.'
severity failure;
end;
component queens_slice
generic (
N : positive; -- size of field
L : positive -- number of preplaced columns
);
port (
clk : IN std_logic;
rst : IN std_logic;
start : IN std_logic;
BH_l : IN std_logic_vector(0 to N-2*L-1);
BU_l : IN std_logic_vector(0 to 2*N-4*L-2);
BD_l : IN std_logic_vector(0 to 2*N-4*L-2);
BV_l : IN std_logic_vector(0 to N-2*L-1);
sol : OUT std_logic;
done : OUT std_logic
);
end component;
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
genSizes: for s in 8 to 12 generate
genFilter: if s /= 10 generate
constant TESTS : tTests := selectTests(s);
--Inputs
signal clk : std_logic;
signal rst : std_logic;
signal start : std_logic;
signal bh : std_logic_vector(0 to s-2*L-1);
signal bv : std_logic_vector(0 to s-2*L-1);
signal bu : std_logic_vector(0 to 2*s-4*L-2);
signal bd : std_logic_vector(0 to 2*s-4*L-2);
--Outputs
signal sol : std_logic;
signal done : std_logic;
-- Test Control
signal nxt : boolean;
begin
dut: queens_slice
generic map (
N => s,
L => L
)
port map (
clk => clk,
rst => rst,
start => start,
BH_l => bh,
BV_l => bv,
BU_l => bu,
BD_l => bd,
sol => sol,
done => done
);
-- Stimuli
process
procedure cycle is
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end;
begin
rst <= '1';
cycle;
rst <= '0';
start <= '0';
cycle;
for i in TESTS'range loop
bh <= std_logic_vector(to_unsigned(TESTS(i).bh, bh'length));
bv <= std_logic_vector(to_unsigned(TESTS(i).bv, bv'length));
bu <= std_logic_vector(to_unsigned(TESTS(i).bu, bu'length));
bd <= std_logic_vector(to_unsigned(TESTS(i).bd, bd'length));
start <= '1';
cycle;
bh <= (others => '-');
bv <= (others => '-');
bu <= (others => '-');
bd <= (others => '-');
start <= '0';
loop
cycle;
exit when nxt;
end loop;
end loop;
wait; -- forever
end process;
-- Checker
process
variable err : natural;
variable cnt : natural;
begin
err := 0;
for i in TESTS'range loop
nxt <= true;
wait until rising_edge(clk) and start = '1';
nxt <= false;
cnt := 0;
loop
wait until rising_edge(clk);
if sol = '1' then
cnt := cnt + 1;
end if;
exit when done = '1';
end loop;
if cnt /= TESTS(i).cnt then
report "Result mismatch in test case #"&integer'image(i)&": "&
integer'image(TESTS(i).cnt)&" -> "&integer'image(cnt)
severity error;
err := err + 1;
end if;
end loop;
if err = 0 then
report "Test [N="&integer'image(s)&", L="&integer'image(L)&"] completed successfully." severity note;
else
report "Test [N="&integer'image(s)&", L="&integer'image(L)&"] completed with "&integer'image(err)&" ERRORS." severity note;
end if;
end process;
end generate;
end generate;
end tb;
| agpl-3.0 | b87f193b6e3c5876baad3786c88c6814 | 0.380069 | 2.674824 | false | false | false | false |
malkadi/FGPU | RTL/float_units.vhd | 1 | 10,052 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
library xil_defaultlib; -- necessray for synthesis
use xil_defaultlib.all;
---------------------------------------------------------------------------------------------------------}}}
entity float_units is -- {{{
port(
float_a, float_b : in SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- level 9.
fsub : in std_logic := '0';
res_float : out SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- level 10+MAX_FPU_DELAY.
code : in std_logic_vector(CODE_W-1 downto 0); -- level 16.
clk : in std_logic
);
end entity; -- }}}
architecture Behavioral of float_units is
-- signals definitions {{{
signal ce : std_logic := '0';
signal fadd_res : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal fslt_res : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal fmul_res : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal fdiv_res : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal fsqrt_res : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal frsqrt_res : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal uitofp_res : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
type res_vec_type is array (natural range<>) of SLV32_ARRAY(CV_SIZE-1 downto 0);
signal fmul_res_vec : res_vec_type(max(MAX_FPU_DELAY-FMUL_DELAY,0) downto 0) := (others=>(others=>(others=>'0')));
signal uitofp_res_vec : res_vec_type(max(MAX_FPU_DELAY-UITOFP_DELAY, 0) downto 0) := (others=>(others=>(others=>'0')));
signal fadd_res_vec : res_vec_type(max(MAX_FPU_DELAY-FADD_DELAY, 0) downto 0) := (others=>(others=>(others=>'0')));
signal fslt_res_vec : alu_en_vec_type(MAX_FPU_DELAY-FSLT_DELAY downto 0) := (others=>(others=>'0'));
signal code_vec : code_vec_type(MAX_FPU_DELAY-8 downto 0) := (others=>(others=>'0'));
attribute max_fanout of code_vec : signal is 32;
signal fmul_valid : std_logic_vector(CV_SIZE-1 downto 0 ) := (others=>'0');
signal fdiv_valid : std_logic_vector(CV_SIZE-1 downto 0 ) := (others=>'0');
signal fsqrt_valid : std_logic_vector(CV_SIZE-1 downto 0 ) := (others=>'0');
-- Operation slave channel signals
signal operation_tdata : std_logic_vector(7 downto 0) := (others=>'0');
--}}}
begin
ce <= '1';
uitofp_res_vec(uitofp_res_vec'high) <= uitofp_res; -- level 14.
fmul_res_vec(fmul_res_vec'high) <= fmul_res; -- level 17.
fadd_res_vec(fadd_res_vec'high) <= fadd_res; -- level 20.
fstl_vec: for i in 0 to CV_SIZE-1 generate
fslt_res_vec(fslt_res_vec'high)(i) <= fslt_res(i)(0); -- level 11.
end generate;
process(clk)
begin
if rising_edge(clk) then
-- pipes {{{
if MAX_FPU_DELAY /= FSLT_DELAY then
fslt_res_vec(fslt_res_vec'high-1 downto 0) <= fslt_res_vec(fslt_res_vec'high downto 1); -- @ 11.->11+MAX_FPU_DELAY-UITOFP_DELAY-1.
end if;
if MAX_FPU_DELAY /= UITOFP_DELAY then
uitofp_res_vec(uitofp_res_vec'high-1 downto 0) <= uitofp_res_vec(uitofp_res_vec'high downto 1); -- @ 15.->15+MAX_FPU_DELAY-UITOFP_DELAY-1.
end if;
if MAX_FPU_DELAY /= FMUL_DELAY then
fmul_res_vec(fmul_res_vec'high-1 downto 0) <= fmul_res_vec(fmul_res_vec'high downto 1); -- @ 18.->18+MAX_FPU_DELAY-FMUL_DELAY-1.
end if;
if MAX_FPU_DELAY /= FADD_DELAY then
fadd_res_vec(max(fadd_res_vec'high-1, 0) downto 0) <= fadd_res_vec(fadd_res_vec'high downto min_int(MAX_FPU_DELAY-FADD_DELAY,1)); -- @ 21.->21+MAX_FPU_DELAY-FADD_DELAY-1.
-- min and max to avoid warning during simulations
end if;
code_vec(code_vec'high) <= code; -- @ 17.
code_vec(code_vec'high -1 downto 0) <= code_vec(code_vec'high downto 1); -- @ 18.->18+MAX_FPU_DELAY-8-1.
-- }}}
case code_vec(0) is -- 9+MAX_FPU_DELAY. (37)
when X"3" => -- uitofp
res_float <= uitofp_res_vec(0); -- @ 10+MAX_FPU_DELAY.
when X"1" => -- fmul
res_float <= fmul_res_vec(0); -- @ 10+MAX_FPU_DELAY.
when X"2" => -- fdiv
res_float <= fdiv_res; -- @ 10+MAX_FPU_DELAY.
when X"4" => -- fsqrt
res_float <= fsqrt_res; -- @ 10+MAX_FPU_DELAY.
when X"5" => -- frsqrt
res_float <= frsqrt_res; -- @ 10+MAX_FPU_DELAY.
when X"7" => -- fslt
res_float <= (others=>(others=>'0'));
for i in 0 to CV_SIZE-1 loop
res_float(i)(0) <= fslt_res_vec(0)(i); -- @ 10+MAX_FPU_DELAY.
end loop;
when others => -- fadd X"0" or fsub X"8"
if MAX_FPU_DELAY /= FADD_DELAY then
res_float <= fadd_res_vec(0); -- @ 10+MAX_FPU_DELAY.
else
res_float <= fadd_res;
end if;
end case;
end if;
end process;
fadd_units: for i in 0 to CV_SIZE-1 generate
begin
uitofp_if: if UITOFP_IMPLEMENT /= 0 generate -- {{{
ui_to_float : entity uitofp
port map (
-- Global signals
aclk => clk,
-- AXI4-Stream slave channel for operand A
s_axis_a_tvalid => ce,
s_axis_a_tdata => float_a(i), -- level 9.
-- AXI4-Stream master channel for output result
m_axis_result_tvalid => open,
m_axis_result_tdata => uitofp_res(i) -- level 9+5=14.
);
end generate; -- }}}
fsqrt_if: if FSQRT_IMPLEMENT /= 0 generate -- {{{
float_sqrt : entity fsqrt
port map (
-- Global signals
aclk => clk,
-- AXI4-Stream slave channel for operand A
s_axis_a_tvalid => ce,
s_axis_a_tdata => float_a(i), -- level 9.
-- AXI4-Stream master channel for output result
m_axis_result_tvalid => fsqrt_valid(i),
m_axis_result_tdata => fsqrt_res(i) -- level 9+28=37.
);
end generate; -- }}}
frsqrt_if: if FRSQRT_IMPLEMENT /= 0 generate -- {{{
float_rsqrt : entity frsqrt
port map (
-- Global signals
aclk => clk,
-- AXI4-Stream slave channel for operand A
s_axis_a_tvalid => ce,
s_axis_a_tdata => float_a(i), -- level 9.
-- AXI4-Stream master channel for output result
m_axis_result_tvalid => open,
m_axis_result_tdata => frsqrt_res(i) -- level 9+28=37.
);
end generate; -- }}}
fdiv_if: if FDIV_IMPLEMENT /= 0 generate -- {{{
float_div : entity fdiv
port map (
-- Global signals
aclk => clk,
-- AXI4-Stream slave channel for operand A
s_axis_a_tvalid => ce,
s_axis_a_tdata => float_a(i), -- level 9.
-- AXI4-Stream slave channel for operand B
s_axis_b_tvalid => ce,
s_axis_b_tdata => float_b(i), -- level 9.
-- AXI4-Stream master channel for output result
m_axis_result_tvalid => fdiv_valid(i),
m_axis_result_tdata => fdiv_res(i) -- level 9+28=37.
);
end generate; -- }}}
fmul_if: if FMUL_IMPLEMENT /= 0 generate -- {{{
float_mul : entity fmul
port map (
-- Global signals
aclk => clk,
-- AXI4-Stream slave channel for operand A
s_axis_a_tvalid => ce,
s_axis_a_tdata => float_a(i), -- level 9.
-- AXI4-Stream slave channel for operand B
s_axis_b_tvalid => ce,
s_axis_b_tdata => float_b(i), -- level 9.
-- AXI4-Stream master channel for output result
m_axis_result_tvalid => fmul_valid(i),
m_axis_result_tdata => fmul_res(i) -- level 9+8=17.
);
end generate; -- }}}
fadd_if: if FADD_IMPLEMENT /= 0 generate -- {{{
operation_tdata(0) <= fsub;
float_add_sub : entity fadd_fsub
port map (
-- Global signals
aclk => clk,
-- AXI4-Stream slave channel for operand A
s_axis_a_tvalid => ce,
s_axis_a_tdata => float_a(i), -- level 9.
-- AXI4-Stream slave channel for operand B
s_axis_b_tvalid => ce,
s_axis_b_tdata => float_b(i), -- level 9.
-- AXI4-Stream slave channel for operation control information
s_axis_operation_tvalid => ce,
s_axis_operation_tdata => operation_tdata, -- level 9
-- AXI4-Stream master channel for output result
m_axis_result_tvalid => open,
m_axis_result_tdata => fadd_res(i) -- level 9+11=20.
);
end generate; -- }}}
fslt_if: if FSLT_IMPLEMENT /= 0 generate -- {{{
float_slt : entity fslt
port map (
-- Global signals
aclk => clk,
-- AXI4-Stream slave channel for operand A
s_axis_a_tvalid => ce,
s_axis_a_tdata => float_a(i), -- level 9.
-- AXI4-Stream slave channel for operand B
s_axis_b_tvalid => ce,
s_axis_b_tdata => float_b(i), -- level 9.
-- AXI4-Stream master channel for output result
m_axis_result_tvalid => open,
m_axis_result_tdata => fslt_res(i)(7 downto 0) -- level 9+2=11.
);
end generate; -- }}}
end generate;
---------------------------------------------------------------------------------------------------------}}}
end Behavioral;
| gpl-3.0 | 897cb4864d6f300100decf3678f7d014 | 0.511142 | 3.54693 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nf_top.vhd | 1 | 15,669 | -------------------------------------------------------------------------------
--! @file nf_top.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-02-24
--! @brief FGClite NanoFIP FPGA (NF) top-level.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.nf_top_pkg.all;
--! @brief Entity declaration of nf_top
--! @details
--! The top-level component for the NanoFIP FPGA implementation.
entity nf_top is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! @}
--! @name NanoFIP core
--! @{
--! The FGClite station ID
subs_i : in std_ulogic_vector(4 downto 0);
--! Fieldrive reception activity detection
fd_rxcdn_i : in std_ulogic;
--! Fieldrive receiver data
fd_rxd_i : in std_ulogic;
--! Fieldrive transmitter error
fd_txer_i : in std_ulogic;
--! Fieldrive watchdog on transmitter
fd_wdgn_i : in std_ulogic;
--! Push-button reset
rstin_i : in std_ulogic;
--! Power-on reset
rstpon_i : inout std_logic;
--! JTAG TDO
jc_tdo_i : in std_ulogic;
--! Fieldrive reset
fd_rstn_o : out std_ulogic;
--! Fieldrive transmitter clock
fd_txck_o : out std_ulogic;
--! Fieldrive transmitter data
fd_txd_o : out std_ulogic;
--! Fieldrive transmitter enable
fd_txena_o : out std_ulogic;
--! Reset output (FGClite power cycle to PF)
rston_o : out std_ulogic;
--! NanoFIP status byte - bit 5
r_fcser_o : out std_ulogic;
--! NanoFIP status byte - bit 4
r_tler_o : out std_ulogic;
--! NanoFIP status byte - bit 2
u_cacer_o : out std_ulogic;
--! NanoFIP status byte - bit 3
u_pacer_o : out std_ulogic;
--! JTAG TMS
jc_tms_o : out std_ulogic;
--! JTAG TDI
jc_tdi_o : out std_ulogic;
--! JTAG TCK
jc_tck_o : out std_ulogic;
--! @}
--! @name NanoFIP extensions
--! @{
--! JTAG TRST
jc_trst_o : out std_ulogic;
--! CF and XF reset
cfxf_rst_n_o : out std_ulogic;
--! CMD 0 was received
cmd_0_o : out std_ulogic;
--! VAR3 (TX buffer) can be accessed
tx_rdy_o : out std_ulogic;
--! PF inhibit
pf_inh_n_o : out std_ulogic;
--! @}
--! @name 3-wire serial receiver from CF
--! @{
--! Frame
cf_rx_frame_i : in std_ulogic;
--! Bit enable
cf_rx_bit_en_i : in std_ulogic;
--! Data
cf_rx_i : in std_ulogic;
--! @}
--! @name 3-wire serial transmitter to CF
--! @{
--! Frame
cf_tx_frame_o : out std_ulogic;
--! Bit enable
cf_tx_bit_en_o : out std_ulogic;
--! Data
cf_tx_o : out std_ulogic;
--! @}
--! @name Debugging
--! @{
--! Serial receiver
debug_rx_i : in std_ulogic;
--! Serial transmitter
debug_tx_o : out std_ulogic;
--! Debugging probe
debug_probe_o : out std_ulogic);
--! @}
end entity nf_top;
--! RTL implementation of nf_top
architecture rtl of nf_top is
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
-- Safe reset generation
signal rstpon : std_ulogic;
signal nanofip_rst : std_ulogic;
signal rst : std_ulogic;
-- Input synchronization and glitch filter
signal station_id_syn : std_ulogic_vector(4 downto 0);
signal cf_rx_frame_syn : std_ulogic;
signal cf_rx_bit_en_syn : std_ulogic;
signal cf_rx_syn : std_ulogic;
signal debug_rx_syn : std_ulogic;
-- NanoFIP core
signal var1_rdy : std_ulogic;
signal var1_acc : std_ulogic;
signal var2_rdy : std_ulogic;
signal var2_acc : std_ulogic;
signal var3_rdy : std_ulogic;
signal var3_acc : std_ulogic;
signal nf_wb_rst : std_ulogic;
signal nf_wb_addr : std_ulogic_vector(9 downto 0);
signal nf_wb_data_rx : std_ulogic_vector(7 downto 0);
signal nf_wb_data_tx : std_ulogic_vector(7 downto 0);
signal nf_wb_we : std_ulogic;
signal nf_wb_stb : std_ulogic;
signal nf_wb_cyc : std_ulogic;
signal nf_wb_ack : std_ulogic;
-- NanoFIP Wishbone interface
signal wb_if_rx_var1_rdy : std_ulogic;
signal wb_if_rx_var2_rdy : std_ulogic;
signal wb_if_rx_var_sel : std_ulogic;
signal wb_if_rx_addr : std_ulogic_vector(6 downto 0);
signal wb_if_rx_en : std_ulogic;
signal wb_if_rx_data : std_ulogic_vector(7 downto 0);
signal wb_if_rx_data_en : std_ulogic;
signal wb_if_tx_addr : std_ulogic_vector(6 downto 0);
signal wb_if_tx_en : std_ulogic;
signal wb_if_tx_data : std_ulogic_vector(7 downto 0);
signal wb_if_err_rw_coll : std_ulogic;
signal wb_if_err_bsy : std_ulogic;
signal wb_if_err_not_rdy : std_ulogic;
signal wb_if_err_timeout : std_ulogic;
-- NanoFIP extensions
signal jtag_trst : std_ulogic;
signal cmd_0 : std_ulogic;
-- VAR1 receiver
signal var1_rx_addr : std_ulogic_vector(6 downto 0);
signal var1_rx_en : std_ulogic;
signal var1_rx_data : std_ulogic_vector(7 downto 0);
signal var1_rx_data_en : std_ulogic;
-- VAR2 receiver
signal var2_rx_addr : std_ulogic_vector(6 downto 0);
signal var2_rx_en : std_ulogic;
signal var2_rx_data : std_ulogic_vector(7 downto 0);
signal var2_rx_data_en : std_ulogic;
-- 3-wire serial receiver from CF
signal cf_rx_data : std_ulogic_vector(14 downto 0);
signal cf_rx_data_en : std_ulogic;
-- 3-wire serial transmitter to CF
signal cf_tx_data : std_ulogic_vector(39 downto 0);
signal cf_tx_data_en : std_ulogic;
signal cf_tx_busy : std_ulogic;
-- Debugging
signal debug_tx_data : std_ulogic_vector(7 downto 0);
signal debug_tx_data_en : std_ulogic;
signal debug_tx_done : std_ulogic;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
tx_rdy_o <= var3_rdy;
cmd_0_o <= cmd_0;
cfxf_rst_n_o <= not rst;
pf_inh_n_o <= jtag_trst;
jc_trst_o <= jtag_trst;
debug_probe_o <= cmd_0;
---------------------------------------------------------------------------
-- Signal Assignments
---------------------------------------------------------------------------
wb_if_tx_addr <= cf_rx_data(14 downto 8);
wb_if_tx_data <= cf_rx_data(7 downto 0);
wb_if_tx_en <= cf_rx_data_en;
wb_if_rx_addr <= var1_rx_addr when wb_if_rx_var_sel = '0' else var2_rx_addr;
wb_if_rx_en <= var1_rx_en when wb_if_rx_var_sel = '0' else var2_rx_en;
var1_rx_data <= wb_if_rx_data;
var1_rx_data_en <= wb_if_rx_data_en when wb_if_rx_var_sel = '0' else '0';
var2_rx_data <= wb_if_rx_data;
var2_rx_data_en <= wb_if_rx_data_en when wb_if_rx_var_sel = '1' else '0';
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! Power-on reset generation for Microsemi devices
po_reset_inst : entity work.microsemi_reset_generator
generic map (
num_delay_g => 4,
active_g => '0')
port map (
clk_i => clk_i,
rst_asy_io => rstpon_i,
rst_o => rstpon);
--! Safe reset generation for logic except NanoFIP core
nf_reset_inst : entity work.reset_generator
generic map (
num_delay_g => 16,
active_g => '1')
port map (
clk_i => clk_i,
rst_asy_i => nanofip_rst,
rst_o => rst);
--! Input synchronization and glitch filter for serial receiver
ext_inputs_inst_0 : entity work.external_inputs
generic map (
init_value_g => '0',
num_inputs_g => 4)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
sig_i(0) => cf_rx_frame_i,
sig_i(1) => cf_rx_bit_en_i,
sig_i(2) => cf_rx_i,
sig_i(3) => debug_rx_i,
sig_o(0) => cf_rx_frame_syn,
sig_o(1) => cf_rx_bit_en_syn,
sig_o(2) => cf_rx_syn,
sig_o(3) => debug_rx_syn);
--! Input synchronization and glitch filter for station ID
ext_inputs_inst_1 : entity work.external_inputs
generic map (
init_value_g => '0',
num_inputs_g => subs_i'length)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
sig_i => subs_i,
sig_o => station_id_syn);
--! NanoFIP core
nanofip_inst: entity work.nanofip
port map (
nanofip_rst_o => nanofip_rst,
c_id_i => "0001",
m_id_i => "0001",
p3_lgth_i => "101",
rate_i => "10",
subs_i(4 downto 0) => std_logic_vector(subs_i),
subs_i(7 downto 5) => "000",
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
nostat_i => '0',
rstin_i => rstin_i,
rstpon_i => rstpon,
slone_i => '0',
uclk_i => clk_i,
var1_acc_i => var1_acc,
var2_acc_i => var2_acc,
var3_acc_i => var3_acc,
wclk_i => clk_i,
adr_i => std_logic_vector(nf_wb_addr),
cyc_i => nf_wb_cyc,
dat_i(7 downto 0) => std_logic_vector(nf_wb_data_tx),
dat_i(15 downto 8) => x"00",
rst_i => nf_wb_rst,
stb_i => nf_wb_stb,
we_i => nf_wb_we,
jc_tdo_i => jc_tdo_i,
--s_id_o => open, -- UNUSED: Information is not used anywhere
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena_o,
rston_o => rston_o,
r_fcser_o => r_fcser_o,
r_tler_o => r_tler_o,
u_cacer_o => u_cacer_o,
u_pacer_o => u_pacer_o,
var1_rdy_o => var1_rdy,
var2_rdy_o => var2_rdy,
var3_rdy_o => var3_rdy,
std_ulogic_vector(dat_o) => nf_wb_data_rx,
ack_o => nf_wb_ack,
jc_tms_o => jc_tms_o,
jc_tdi_o => jc_tdi_o,
jc_tck_o => jc_tck_o);
--! NanoFIP Wishbone interface
nanofip_wb_if_inst : entity work.nanofip_wb_if
generic map (
watchdog_max_g => 32)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
var1_rdy_i => var1_rdy,
var1_acc_o => var1_acc,
var2_rdy_i => var2_rdy,
var2_acc_o => var2_acc,
var3_rdy_i => var3_rdy,
var3_acc_o => var3_acc,
wb_clk_o => open,
wb_rst_o => nf_wb_rst,
wb_addr_o => nf_wb_addr,
wb_data_i => nf_wb_data_rx,
wb_data_o => nf_wb_data_tx,
wb_we_o => nf_wb_we,
wb_stb_o => nf_wb_stb,
wb_cyc_o => nf_wb_cyc,
wb_ack_i => nf_wb_ack,
rx_var1_rdy_o => wb_if_rx_var1_rdy,
rx_var2_rdy_o => wb_if_rx_var2_rdy,
rx_var_sel_i => wb_if_rx_var_sel,
rx_addr_i => wb_if_rx_addr,
rx_en_i => wb_if_rx_en,
rx_data_o => wb_if_rx_data,
rx_data_en_o => wb_if_rx_data_en,
tx_rdy_o => open, -- UNUSED: CF knows when VAR3 is ready
tx_addr_i => wb_if_tx_addr,
tx_en_i => wb_if_tx_en,
tx_data_i => wb_if_tx_data,
tx_done_o => open, -- UNUSED: Serial receiver is slower than Wishbone interface
err_rw_coll_o => wb_if_err_rw_coll,
err_bsy_o => wb_if_err_bsy,
err_not_rdy_o => wb_if_err_not_rdy,
err_timeout_o => wb_if_err_timeout);
--! Receiver VAR select
rx_var_sel_inst : entity work.rx_var_select
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
var1_rdy_i => wb_if_rx_var1_rdy,
var2_rdy_i => wb_if_rx_var2_rdy,
var_select_o => wb_if_rx_var_sel);
--! VAR1 receiver
var1_rx_inst : entity work.var1_rx
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
rx_rdy_i => wb_if_rx_var1_rdy,
rx_addr_o => var1_rx_addr,
rx_en_o => var1_rx_en,
rx_data_i => var1_rx_data,
rx_data_en_i => var1_rx_data_en,
jtag_trst_o => jtag_trst,
err_rw_coll_i => wb_if_err_rw_coll,
err_bsy_i => wb_if_err_bsy,
err_not_rdy_i => wb_if_err_not_rdy,
err_timeout_i => wb_if_err_timeout);
--! VAR2 receiver
var2_rx_inst : entity work.var2_rx
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
station_id_i => station_id_syn,
cmd_0_o => cmd_0,
rx_rdy_i => wb_if_rx_var2_rdy,
rx_addr_o => var2_rx_addr,
rx_en_o => var2_rx_en,
rx_data_i => var2_rx_data,
rx_data_en_i => var2_rx_data_en,
tx_data_o => cf_tx_data,
tx_data_en_o => cf_tx_data_en,
tx_bsy_i => cf_tx_busy,
err_rw_coll_i => wb_if_err_rw_coll,
err_bsy_i => wb_if_err_bsy,
err_not_rdy_i => wb_if_err_not_rdy,
err_timeout_i => wb_if_err_timeout);
--! 3-wire serial receiver from CF
cf_rx_inst : entity work.serial_3wire_rx
generic map (
data_width_g => 15)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
rx_frame_i => cf_rx_frame_syn,
rx_bit_en_i => cf_rx_bit_en_syn,
rx_i => cf_rx_syn,
data_o => cf_rx_data,
data_en_o => cf_rx_data_en,
error_o => open); -- UNUSED: CF can't be notified of errors anyway
--! 3-wire serial transmitter to CF
cf_tx_inst : entity work.serial_3wire_tx
generic map (
data_width_g => 44,
num_ticks_g => 6)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
data_i(43 downto 40) => NF_VERSION_c,
data_i(39 downto 0) => cf_tx_data,
data_en_i => cf_tx_data_en,
busy_o => cf_tx_busy,
done_o => open,
tx_frame_o => cf_tx_frame_o,
tx_bit_en_o => cf_tx_bit_en_o,
tx_o => cf_tx_o);
--! Serial debugging receiver
debug_rx_inst : entity work.uart_rx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 156)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
rx_i => debug_rx_syn,
data_o => open,
data_en_o => open,
error_o => open);
--! Serial debugging transmitter
debug_tx_inst : entity work.uart_tx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 156)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
data_i => debug_tx_data,
data_en_i => debug_tx_data_en,
busy_o => open,
done_o => debug_tx_done,
tx_o => debug_tx_o);
--! Debugging packet transmitter
debug_array_tx_inst : entity work.array_tx
generic map (
data_count_g => 5,
data_width_g => 8)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
data_i => cf_tx_data,
data_en_i => cf_tx_data_en,
busy_o => open,
done_o => open,
tx_data_o => debug_tx_data,
tx_data_en_o => debug_tx_data_en,
tx_done_i => debug_tx_done);
end architecture rtl;
| mit | 81f709a3fb00f9d56e08896b4aefd883 | 0.504308 | 2.97099 | false | false | false | false |
malkadi/FGPU | RTL/mult_add_sub.vhd | 1 | 7,036 | -- libraries -------------------------------------------------------------------------------------------{{{
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.all;
---------------------------------------------------------------------------------------------------------}}}
entity mult_add_sub is -- {{{
generic (DATA_W : natural := 32);
port (
sub : in std_logic; -- level 10.
a, c : in unsigned (DATA_W-1 downto 0); -- level 10.
b : in unsigned (DATA_W downto 0); -- level 10.
sra_sign_v : in std_logic := '0'; -- level 10.
sra_sign : in unsigned (DATA_W downto 0); -- level 10.
sltu_true_p0 : out std_logic := '0'; -- level 15.
res_low_p0 : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 15.
res_high : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 16.
clk, ce : in std_logic
);
end entity; --}}}
architecture Behavioral of mult_add_sub is
-- signals definitions ----------------------------------------------------------------------------------{{{
signal c_sub, res_low_low_d0 : unsigned(DATA_W downto 0) := (others=>'0');
signal res_low_low : unsigned(DATA_W downto 0) := (others=>'0');
signal res_low_high, res_high_low : unsigned(DATA_W downto 0) := (others=>'0');
signal res_high_high : unsigned(DATA_W downto 0) := (others=>'0');
signal res_middle : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal res_middle_high : unsigned(DATA_W downto 0) := (others=>'0');
signal zeros : unsigned(DATA_W downto 0) := (others=>'0');
signal res_middle_low : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal res_low_i : std_logic_vector(DATA_W downto 0) := (others=>'0');
signal a_high_d0, a_high_d1, a_high_d2 : unsigned(DATA_W/2-1 downto 0) := (others=>'0');
signal b_high_d0, b_high_d1, b_high_d2 : unsigned(DATA_W/2 downto 0) := (others=>'0');
signal sra_sign_low : unsigned(DATA_W downto 0) := (others=>'0');
signal sra_sign_high_d0 : signed(DATA_W/2 downto 0) := (others=>'0');
signal sra_sign_set_to_ones : std_logic := '0';
signal sra_sign_high_d1 : signed(DATA_W/2 downto 0) := (others=>'0');
signal sra_sign_high_d2 : signed(DATA_W/2 downto 0) := (others=>'0');
signal sra_sign_v_d0, sra_sign_v_d1 : std_logic := '0';
signal a_low_extended : unsigned(DATA_W/2 downto 0) := (others=>'0');
signal sra_sign_d0 : unsigned(DATA_W downto 0) := (others=>'0');
attribute use_dsp48 :string;
attribute use_dsp48 of res_middle : signal is "no";
---------------------------------------------------------------------------------------------------------}}}
begin
-- DSPs -------------------------------------------------------------------------------------------------{{{
mul_add_low_low: entity DSP48E1 generic map(
SIZE_A => DATA_W/2+1,
SIZE_B => DATA_W/2,
SUB => false
) port map(
clk => clk,
ce => ce,
ain => a_low_extended, -- level 10.
bin => b(DATA_W/2-1 downto 0), -- level 10.
cin => c_sub, -- level 11.
res => res_low_low -- level 13.
);
mul_add_low_high: entity DSP48E1 generic map(
SIZE_A => DATA_W/2,
SIZE_B => DATA_W/2+1,
SUB => true
) port map(
clk => clk,
ce => ce,
ain => a(DATA_W/2-1 downto 0), -- level 10.
bin => b(DATA_W downto DATA_W/2), -- level 10.
cin => sra_sign_low, -- level 11.
res => res_low_high -- level 13.
);
mul_add_high_low: entity DSP48E1 generic map(
SIZE_A => DATA_W/2,
SIZE_B => DATA_W/2,
SUB => false
) port map(
clk => clk,
ce => ce,
ain => a(DATA_W-1 downto DATA_W/2), -- level 10.
bin => b(DATA_W/2-1 downto 0), -- level 10.
cin => zeros(DATA_W-1 downto 0),
res => res_high_low(DATA_W-1 downto 0) -- level 13.
);
mul_add_high_high: entity DSP48E1 generic map(
SIZE_A => DATA_W/2,
SIZE_B => DATA_W/2+1,
SUB => false
) port map(
clk => clk,
ce => ce,
ain => a_high_d2, -- level 13.
bin => b_high_d2, -- level 13.
cin => res_middle_high, -- level 14.
res => res_high_high -- level 16.
);
---------------------------------------------------------------------------------------------------------}}}
-- other logic ------------------------------------------------------------------------------------------{{{
res_middle_low(DATA_W-1 downto DATA_W/2) <= res_middle(DATA_W/2-1 downto 0); -- level 14.
res_middle_high(DATA_W/2-1 downto 0) <= res_middle(DATA_W-1 downto DATA_W/2); -- level 14.
res_high <= std_logic_vector(res_high_high(DATA_W-1 downto 0)); -- level 16.
res_middle_high(DATA_W downto DATA_W/2) <= unsigned(sra_sign_high_d2); -- level 14.
a_low_extended <= '0' & a(DATA_W/2-1 downto 0);
process(clk)
begin
if rising_edge(clk) then
sra_sign_low(DATA_W downto DATA_W/2) <= sra_sign(DATA_W/2 downto 0); -- @ 11.
sra_sign_d0 <= sra_sign; -- @ 11.
sra_sign_v_d0 <= sra_sign_v; -- @ 11.
sra_sign_high_d0 <= -signed(sra_sign_d0(DATA_W downto DATA_W/2)); ---@ 12.
sra_sign_v_d1 <= sra_sign_v_d0; -- @ 12.
if sra_sign_high_d0 = (sra_sign_high_d0'range => '0') and sra_sign_v_d1 = '1' then -- level 12.
sra_sign_set_to_ones <= '1'; -- @ 13.
else
sra_sign_set_to_ones <= '0'; -- @ 13.
end if;
sra_sign_high_d1 <= sra_sign_high_d0; -- @ 13.
if sra_sign_set_to_ones = '1' then -- level 13.
sra_sign_high_d2 <= (others=>'1');
else
sra_sign_high_d2 <= sra_sign_high_d1; -- @ 14.
end if;
if sub = '1' then -- level 10.
c_sub <= unsigned(-signed('0' & c)); -- @ 11.
else
c_sub <= '0' & c; -- @ 11.
end if;
a_high_d0 <= a(DATA_W-1 downto DATA_W/2); -- @ 11.
b_high_d0 <= b(DATA_W downto DATA_W/2); -- @ 11.
a_high_d1 <= a_high_d0; -- @ 12.
b_high_d1 <= b_high_d0; -- @ 12.
a_high_d2 <= a_high_d1; -- @ 13.
b_high_d2 <= b_high_d1; -- @ 13.
-- stage 0 after DSPs
res_low_low_d0 <= res_low_low; -- @ 14.
res_middle <= res_high_low(DATA_W-1 downto 0) + res_low_high(DATA_W-1 downto 0); -- @ 14.
-- stage 1 after DSP
res_low_i <= std_logic_vector(res_low_low_d0 + unsigned('0'&res_middle_low)); -- @ 15.
end if;
end process;
res_low_p0 <= res_low_i(DATA_W-1 downto 0); -- @ 15.
sltu_true_p0 <= res_low_i(DATA_W); -- @ 15.
---------------------------------------------------------------------------------------------------------}}}
end architecture;
| gpl-3.0 | 7d757a5183373bd89492cd6e7efca813 | 0.453951 | 3.258916 | false | false | false | false |
touilleMan/scrips | datamemory.vhd | 1 | 3,243 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:55:03 05/08/2012
-- Design Name:
-- Module Name: datamemory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity datamemory is
Port ( Address : in STD_LOGIC_VECTOR (31 downto 0);
WriteData : in STD_LOGIC_VECTOR (31 downto 0);
MemWrite : in STD_LOGIC;
MemRead : in STD_LOGIC;
ReadData : out STD_LOGIC_VECTOR (31 downto 0);
O_LMotor : out STD_LOGIC_VECTOR (3 downto 0);
O_RMotor : out STD_LOGIC_VECTOR (3 downto 0);
I_Sensors : in STD_LOGIC_VECTOR (6 downto 0);
O_Leds : out STD_LOGIC_VECTOR (6 downto 0);
I_Rf : in STD_LOGIC_VECTOR (2 downto 0);
O_Buzzer : out STD_LOGIC;
O_Seg : out STD_LOGIC_VECTOR (7 downto 0);
O_El_7l :out STD_LOGIC_VECTOR (2 downto 0);
I_St_7l : in STD_LOGIC_VECTOR (5 downto 0);
I_Clock : in STD_LOGIC
);
end datamemory;
architecture Behavioral of datamemory is
begin
-- Memory Map
-- 0x000
-- 0x001
-- 0x010 Set motors
-- 0x020 Set leds
-- 0x021 Get Sensors
-- 0x030 Get RF
-- 0x031 Set BUZZER
-- 0x032 Set SEG
-- 0x033 Set EL_7L
-- 0x034 Get ST_7L
read : process (I_Clock)
begin
if (I_Clock'Event and I_Clock = '1') then
if (MemRead = '1') then
case Address is
when "00000000000000000000000000100001"=>
ReadData(6 downto 0) <= I_Sensors(6 downto 0);
ReadData(31 downto 7) <= "0000000000000000000000000";
when "00000000000000000000000000110000"=>
ReadData(2 downto 0) <= I_Rf(2 downto 0);
ReadData(31 downto 3) <= "00000000000000000000000000000";
when "00000000000000000000000000110100"=>
ReadData(5 downto 0) <= I_St_7l(5 downto 0);
ReadData(31 downto 6) <= "00000000000000000000000000";
when others => ReadData <= "00000000000000000000000000000000";
end case;
end if;
end if;
end process;
write : process(I_Clock)
begin
if (I_Clock'Event and I_Clock = '1') then
if (MemWrite = '1') then
case Address is
when "00000000000000000000000000010000"=>
O_RMotor <= WriteData(3 downto 0);
O_LMotor <= WriteData(7 downto 4);
when "00000000000000000000000000100000"=>
O_Leds <= WriteData(6 downto 0);
when "00000000000000000000000000110001"=>
O_Buzzer <= WriteData(0);
when "00000000000000000000000000110010"=>
O_Seg <= WriteData(7 downto 0);
when "00000000000000000000000000110011"=>
O_El_7l <= WriteData(2 downto 0);
when others =>
end case;
end if;
end if;
end process;
end Behavioral;
| mit | 0290dfa38af998bbe2b77bb02f8dc1ed | 0.608079 | 3.784131 | false | false | false | false |
kennethlyn/fpga-image-example | hdl_nodes/adder/adder.srcs/sources_1/dyplo_hdl_node.vhd | 1 | 10,285 | -- File: dyplo_hdl_node.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
--
-- Disclaimer
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Topic Embedded Products B.V., and to the maximum
-- extend permitted by applicable law:
--
-- 1. Dyplo is furnished on an "as is", as available basis. Topic makes no
-- warranty, express or implied, with respect to the capability of Dyplo. All
-- warranties of any type, express or implied, including the warranties of
-- merchantability, fitness for a particular purpose and non-infringement of
-- third party rights are expressly disclaimed.
--
-- 2. Topic's maximum total liability shall be limited to general money
-- damages in an amount not to exceed the total amount paid for in the year
-- in which the damages have occurred. Under no circumstances including
-- negligence shall Topic be liable for direct, indirect, incidental, special,
-- consequential or punitive damages, or for loss of profits, revenue, or data,
-- that are directly or indirectly related to the use of, or the inability to
-- access and use Dyplo and related services, whether in an action in contract,
-- tort, product liability, strict liability, statute or otherwise even if
-- Topic has been advised of the possibility of those damages.
--
-- This copyright notice and disclaimer must be retained as part of this file at all times.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library dyplo_hdl_node_lib;
use dyplo_hdl_node_lib.hdl_node_package.all;
use dyplo_hdl_node_lib.hdl_node_user_params.all;
library user_logic;
use user_logic.all;
entity dyplo_hdl_node is
port(
-- Miscellaneous
node_id : in std_logic_vector(c_hdl_node_id_width - 1 downto 0);
-- DAB interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(c_hdl_dab_awidth - 1 downto 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Receive data from backplane to FIFO
b2f_tdata : in std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
b2f_tstream_id : in std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
b2f_tvalid : in std_logic;
b2f_tready : out std_logic;
-- Send data from FIFO to backplane
f2b_tdata : out std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
f2b_tstream_id : out std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
f2b_tvalid : out std_logic;
f2b_tready : in std_logic;
-- Serial fifo status info
fifo_status_sync : in std_logic;
fifo_status_flag : out std_logic;
-- fifo statuses of destination fifo's
dest_fifo_status : in std_logic_vector(3 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
attribute secure_config : string;
attribute secure_config of dyplo_hdl_node : entity is "PROTECT";
attribute secure_netlist : string;
attribute secure_netlist of dyplo_hdl_node : entity is "ENCRYPT";
attribute secure_net_editing : string;
attribute secure_net_editing of dyplo_hdl_node : entity is "PROHIBIT";
attribute secure_net_probing : string;
attribute secure_net_probing of dyplo_hdl_node : entity is "PROHIBIT";
end dyplo_hdl_node;
architecture rtl of dyplo_hdl_node is
component dyplo_user_logic_adder is
generic(
INPUT_STREAMS : integer := 4;
OUTPUT_STREAMS : integer := 4
);
port(
-- Processor bus interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(15 downto 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Streaming input interfaces
cin_tdata : in cin_tdata_ul_type;
cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tlevel : in cin_tlevel_ul_type;
-- Streaming output interfaces
cout_tdata : out cout_tdata_ul_type;
cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
end component dyplo_user_logic_adder;
signal dab_sel_ul : std_logic;
signal dab_wvalid_ul : std_logic;
signal dab_rvalid_ul : std_logic;
signal dab_rdata_ul : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
signal cin_tdata_i : cin_tdata_ul_type;
signal cin_tvalid_i : std_logic_vector(c_input_streams - 1 downto 0);
signal cin_tready_i : std_logic_vector(c_input_streams - 1 downto 0);
signal cin_tlevel_i : cin_tlevel_ul_type;
signal cout_tdata_i : cout_tdata_ul_type;
signal cout_tvalid_i : std_logic_vector(c_output_streams - 1 downto 0);
signal cout_tready_i : std_logic_vector(c_output_streams - 1 downto 0);
begin
-----------------------------------------------------------------------------
-- CONTROL MEMORY MAP FOR CPU FIFO INTERFACE --
-----------------------------------------------------------------------------
-- The available memory range for the CPU fifo control is limited to --
-- 64Kbyte/32 = 2Kbytes or 512 words. The maximum burst transfer of the --
-- AXI bus is 256 words. The actual FIFO data memory range is also limited --
-- to 64Kbytes or 16Kwords. Also, the space is divided between reading and --
-- writing. This leaves 8Kwords per direction and with a burst length of --
-- 256 words, maximum 32 input streams and 32 output streams can be --
-- supported. --
-----------------------------------------------------------------------------
-- Each fifo has the following metrics: --
-- - FIFO full and FIFO empty flag --
-- - FIFO fill level compare register and compare flag --
-- - Actual FIFO fill level indicator --
-- - Under/overflow detection flag when operating FIFO out of range --
-- --
-- Per input FIFO (from FPGA fabric to the CPU) it is required to specify --
-- the stream source. Also, a maskable interrupt should be issued per --
-- input FIFO to signal the need to empty the FIFO by the CPU. --
-----------------------------------------------------------------------------
dyplo_hdl_node_logic_i : dyplo_hdl_node_logic
generic map (
INPUT_STREAMS => c_input_streams,
OUTPUT_STREAMS => c_output_streams
)
port map(
-- Miscellaneous
node_id => node_id,
-- DAB interface
dab_clk => dab_clk,
dab_rst => dab_rst,
dab_addr => dab_addr,
dab_sel => dab_sel,
dab_wvalid => dab_wvalid,
dab_rvalid => dab_rvalid,
dab_wdata => dab_wdata,
dab_rdata => dab_rdata,
-- Receive data from backplane to FIFO
b2f_tdata => b2f_tdata,
b2f_tstream_id => b2f_tstream_id,
b2f_tvalid => b2f_tvalid,
b2f_tready => b2f_tready,
-- Send data from FIFO to backplane
f2b_tdata => f2b_tdata,
f2b_tstream_id => f2b_tstream_id,
f2b_tvalid => f2b_tvalid,
f2b_tready => f2b_tready,
-- Serial fifo status info
fifo_status_sync => fifo_status_sync,
fifo_status_flag => fifo_status_flag,
-- fifo statuses of destination fifo's
dest_fifo_status => dest_fifo_status(c_output_streams - 1 downto 0),
-- DAB interface to user logic
dab_sel_ul => dab_sel_ul,
dab_wvalid_ul => dab_wvalid_ul,
dab_rvalid_ul => dab_rvalid_ul,
dab_rdata_ul => dab_rdata_ul,
-- In streams to user logic
cin_tdata_ul => cin_tdata_i,
cin_tvalid_ul => cin_tvalid_i,
cin_tready_ul => cin_tready_i,
cin_tlevel_ul => cin_tlevel_i,
-- Out streams from user logic
cout_tdata_ul => cout_tdata_i,
cout_tvalid_ul => cout_tvalid_i,
cout_tready_ul => cout_tready_i
);
dyplo_user_logic_i : dyplo_user_logic_adder
generic map(
INPUT_STREAMS => c_input_streams,
OUTPUT_STREAMS => c_output_streams
)
port map(
-- Processor bus interface
dab_clk => dab_clk,
dab_rst => dab_rst,
dab_addr => dab_addr(15 downto 0),
dab_sel => dab_sel_ul,
dab_wvalid => dab_wvalid_ul,
dab_rvalid => dab_rvalid_ul,
dab_wdata => dab_wdata,
dab_rdata => dab_rdata_ul,
-- Streaming input interfaces
cin_tdata => cin_tdata_i,
cin_tvalid => cin_tvalid_i,
cin_tready => cin_tready_i,
cin_tlevel => cin_tlevel_i,
-- Streaming output interfaces
cout_tdata => cout_tdata_i,
cout_tvalid => cout_tvalid_i,
cout_tready => cout_tready_i,
-- Clock signals
user_clocks => user_clocks
);
end rtl;
| gpl-2.0 | f466adbcdb668a13aaddd317f728267e | 0.581834 | 3.751551 | false | false | false | false |
kennethlyn/fpga-image-example | hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_hdl_node_package.vhd | 3 | 9,725 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6592)
`protect data_block
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`protect end_protected
| gpl-2.0 | 73c64094aecb93c1c16848601dc6609a | 0.943753 | 1.875603 | false | false | false | false |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_encoder.vhd | 2 | 20,893 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13728)
`protect data_block
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`protect end_protected
| mit | a810a305547b2ebfa5a27be0aea8fe96 | 0.94132 | 1.871127 | false | false | false | false |
jpidancet/mips | rtl/cpu_writeback.vhd | 1 | 863 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity cpu_writeback is
port (regwrite : in std_logic;
memtoreg : in std_logic;
aluout : in std_logic_vector(31 downto 0);
readdata : in std_logic_vector(31 downto 0);
writereg : in std_logic_vector(4 downto 0);
writereg_n : out std_logic_vector(4 downto 0);
result_n : out std_logic_vector(31 downto 0);
regwrite_n : out std_logic);
end entity cpu_writeback;
architecture rtl of cpu_writeback is
signal result : std_logic_vector(31 downto 0);
begin
result <= readdata when memtoreg = '1' else
aluout;
writereg_n <= writereg;
result_n <= result;
regwrite_n <= regwrite;
end architecture rtl;
| isc | 84a2a20dc38c401e9ab83b4e714d6106 | 0.597914 | 3.67234 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_fdiv_fsqrt_6_1_1_2.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 6;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 1;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 348451ba02621d1014ec3196af6da8d5 | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_float_2AXI.vhd | 1 | 23,540 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 11;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FSQRT_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 0c49a9ff012230fb962e2df07288356b | 0.568734 | 3.717038 | false | false | false | false |
dtysky/LD3320_AXI | hdl/VOICE.vhd | 1 | 16,919 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity VOICE is
port
(
start:in std_logic;
inclk,inclk_n:in std_logic;
init_clk:in std_logic;
init_wea:in std_logic_vector(0 downto 0);
init_addr:in std_logic_vector(5 downto 0);
init_din:in std_logic_vector(15 downto 0);
list_clk:in std_logic;
list_wea:in std_logic_vector(0 downto 0);
list_addr:in std_logic_vector(7 downto 0);
list_din:in std_logic_vector(7 downto 0);
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_logic:='0';
data_voice:inout std_logic_vector(7 downto 0);
voice_result:out std_logic_vector(7 downto 0):=x"00";
reco_rqu:in std_logic:='0';
reco_fin:out std_logic:='0';
voice_state:out std_logic_vector(7 downto 0):=x"00";
voice_ram:out std_logic_vector(15 downto 0):=x"0000"
);
end entity;
architecture voicex of VOICE is
component VOICE_ROM_INIT is
PORT
(
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
end component;
component LIST is
PORT
(
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN std_logic_vector(7 downto 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN std_logic_vector(7 downto 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
component VOICE_DELAY is
port
(
clk:in std_logic;
start:in std_logic:='0';
total:in std_logic_vector(7 downto 0);
finish:out std_logic:='1'
);
end component;
-------------------æ¶éã?0MHz---------------------
signal clk_self,clk_out:std_logic;
-----------------------å¤ä½------------------------
signal reset:std_logic:='0';
--------------------åå§åROM----------------------
signal rom_init_addr:std_logic_vector(5 downto 0):="000000";
signal rom_init_data:std_logic_vector(15 downto 0);
signal rom_en:std_logic:='1';
---------------------å表ROM-----------------------
signal rom_list_addr:std_logic_vector(7 downto 0):=x"00";
signal rom_list_data:std_logic_vector(7 downto 0);
-----------------------延æ¶------------------------
signal delay_start,delay_finish:std_logic:='0';
signal delay_total:std_logic_vector(7 downto 0);
----------------------é
ç½®ç¶æ?----------------------
signal init_done,list_done,all_wait,all_done,all_done_last:std_logic:='0';
----------------------è¯å«ç¶æ?----------------------
signal reco_allow,reco_allow_last,reco_start:std_logic:='0';
signal reco_rqu_last:std_logic:='0';
signal n_int_last:std_logic:='1';
signal add_en_s:std_logic:='1';
begin
voice_state(1)<=start;
voice_state(0)<=reco_rqu;
clk_voice<=inclk_n;
VOICE_ROM_INITX:voice_rom_init
port map
(
clka=>init_clk,
wea=>init_wea,
addra=>init_addr,
dina=>init_din,
clkb=>clk_out,
addrb=>rom_init_addr,
doutb=>rom_init_data
);
VOICE_ROM_LIST:list
port map
(
clka=>list_clk,
wea=>list_wea,
addra=>list_addr,
dina=>list_din,
clkb=>clk_out,
addrb=>rom_list_addr,
doutb=>rom_list_data
);
VOICE_DLLAYX:voice_delay port map(clk=>clk_self,start=>delay_start,finish=>delay_finish,total=>delay_total);
clk_self<=inclk;
clk_out<=inclk_n;
add_en<=add_en_s;
rom_en<='1';
process(clk_self,reset)
variable con_reset:integer range 0 to 127:=0;
variable con_init_start:integer range 0 to 2047:=0;
variable con:integer range 0 to 5:=0;
variable con_total:integer range 0 to 26:=0;
variable con_type:integer range 0 to 31:=0;
variable con_init_fin_start:integer range 0 to 3:=0;
begin
if clk_self'event and clk_self='1' then
voice_state(7)<='1';
--------------------å¤ä½-----------------------
if con_reset=127 then
reset<='1';
end if;
if reset='1' then
con_reset:=0;
reset<='0';
reco_fin<='0';
init_done<='0';
list_done<='0';
all_wait<='0';
all_done<='0';
reco_allow<='0';
rom_init_addr<="000000";
rom_list_addr<="00000000";
con_init_start:=0;
end if;
---------------------åå§å?---------------------
if start='1' then
if con_init_start=2047 then
con_init_start:=2047;
else
con_init_start:=con_init_start+1;
con:=0;
con_type:=0;
con_total:=0;
con_init_fin_start:=0;
end if;
end if;
if con_init_start=500 then
n_rst<='0';
elsif con_init_start=1000 then
n_rst<='1';
elsif con_init_start=1500 then
n_cs<='0';
elsif con_init_start=2000 then
n_cs<='1';
delay_start<='1';
delay_total<=x"5F";
end if;
--------------------åå§å?--------------------
if con_init_start=2047 and init_done='0' and delay_finish='1' then
voice_state(6)<='1';
if con=5 then
con:=0;
elsif con=0 then
if con_total=26 then
init_done<='1';
con:=0;
con_type:=0;
con_total:=0;
else
con:=con+1;
end if;
else
con:=con+1;
end if;
-------------------------------------------------------
if con_total=0 or con_total=2 then
if con=1 then
delay_start<='0';
if con_type=0 then
add_en_s<='1';
data_voice<=x"06";
else
add_en_s<='0';
data_voice<="ZZZZZZZZ";
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if con_type=0 then
n_wr<='0';
else
n_rd<='0';
end if;
elsif con=4 then
if add_en_s='0' then
delay_total<=x"0A";
delay_start<='1';
end if;
if con_type=0 then
n_wr<='1';
else
n_rd<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
-------------------------------------------------------
else
if con=1 then
delay_start<='0';
if con_type=0 then
add_en_s<='1';
data_voice<=rom_init_data(15 downto 8);
else
add_en_s<='0';
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
n_wr<='0';
elsif con=4 then
n_wr<='1';
delay_total<=x"0A";
delay_start<='1';
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
-------------------å¾
è¯å«å表åå
?---------------
if init_done='1' and list_done='0' and delay_finish='1' then
voice_state(5)<='1';
if con=0 then
delay_start<='0';
con:=con+1;
elsif con=1 then
if con_type=0 then
add_en_s<='1';
data_voice<=x"B2";
con:=con+1;
elsif con_type=10 then
add_en_s<='0';
data_voice<="ZZZZZZZZ";
con:=con+1;
elsif con_type=1 then
if rom_list_data=x"FF" then
con_type:=20;
--list_done<='1';
delay_total<=x"5F";
delay_start<='1';
con:=0;
--con_type:=0;
else
add_en_s<='1';
data_voice<=x"C1";
con:=con+1;
con_type:=2;
end if;
elsif con_type=20 then
add_en_s<='1';
data_voice<=x"BF";
con:=con+1;
elsif con_type=21 then
add_en_s<='0';
data_voice<="ZZZZZZZZ";
con:=con+1;
elsif con_type=2 then
add_en_s<='0';
data_voice<=rom_list_data;
con:=con+1;
con_type:=12;
elsif con_type=12 then
add_en_s<='1';
data_voice<=x"C3";
con:=con+1;
con_type:=13;
elsif con_type=13 then
add_en_s<='0';
data_voice<=x"00";
con:=con+1;
con_type:=14;
elsif con_type=14 then
add_en_s<='1';
data_voice<=x"08";
con:=con+1;
con_type:=15;
elsif con_type=15 then
add_en_s<='0';
data_voice<=x"04";
con:=con+1;
con_type:=16;
elsif con_type=16 then
add_en_s<='1';
data_voice<=x"08";
con:=con+1;
con_type:=17;
elsif con_type=17 then
add_en_s<='0';
data_voice<=x"00";
con:=con+1;
con_type:=3;
elsif con_type=3 then
add_en_s<='1';
data_voice<=x"05";
con:=con+1;
con_type:=11;
rom_list_addr<=rom_list_addr+1;
elsif con_type=4 then
add_en_s<='1';
data_voice<=x"B9";
con:=con+1;
con_type:=5;
rom_list_addr<=rom_list_addr+1;
elsif con_type=5 then
add_en_s<='0';
data_voice<=rom_list_data;
con:=con+1;
con_type:=6;
elsif con_type=6 then
add_en_s<='1';
data_voice<=x"B2";
con:=con+1;
con_type:=7;
elsif con_type=7 then
add_en_s<='0';
data_voice<=x"FF";
con:=con+1;
con_type:=8;
elsif con_type=8 then
add_en_s<='1';
data_voice<=x"37";
con:=con+1;
con_type:=9;
elsif con_type=9 then
add_en_s<='0';
data_voice<=x"04";
con:=con+1;
con_type:=0;
rom_list_addr<=rom_list_addr+1;
elsif con_type=11 then
if rom_list_data=x"FF" then
con_type:=4;
con:=0;
else
add_en_s<='0';
data_voice<=rom_list_data;
rom_list_addr<=rom_list_addr+1;
con:=con+1;
end if;
end if;
elsif con=2 then
n_cs<='0';
con:=con+1;
elsif con=3 then
con:=con+1;
if con_type=10 or con_type=21 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
con:=con+1;
if add_en_s='0' and con_type/=11 then
delay_total<=x"01";
delay_start<='1';
end if;
if con_type=21 or con_type=10 then
n_rd<='1';
else
n_wr<='1';
end if;
elsif con=5 then
n_cs<='1';
con:=0;
if con_type=10 then
voice_ram(15 downto 8)<=data_voice;
voice_ram(5 downto 0)<=rom_init_addr;
if data_voice=x"21" then
con_type:=1;
else
delay_total<=x"0A";
delay_start<='1';
con_type:=0;
con_reset:=con_reset+1;
end if;
elsif con_type=0 then
con_type:=10;
elsif con_type=20 then
con_type:=21;
elsif con_type=21 then
if data_voice=x"31" then
con_type:=0;
list_done<='1';
con:=0;
con_type:=0;
else
reset<='1';
end if;
end if;
end if;
end if;
-------------------------è¯å«åå¤------------------------
reco_rqu_last<=reco_rqu;
if reco_rqu_last='0' and reco_rqu='1' then
reco_start<='1';
end if;
if list_done='1' and all_wait='0' and reco_start='1' and delay_finish='1' then
voice_state(4)<='1';
if con_init_fin_start=3 then
con_init_fin_start:=3;
else
rom_init_addr<="100000";
con_init_fin_start:=con_init_fin_start+1;
end if;
if con_init_fin_start=3 then
if con=5 then
con:=0;
elsif con=0 then
if con_total=5 then
all_wait<='1';
reco_start<='0';
con:=0;
con_type:=0;
con_total:=0;
con_reset:=0;
elsif con_total=0 then
con:=con+1;
else
con:=con+1;
end if;
else
con:=con+1;
end if;
if con=0 then
delay_start<='0';
elsif con=1 then
if con_type=0 then
add_en_s<='1';
data_voice<=rom_init_data(15 downto 8);
else
add_en_s<='0';
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
n_wr<='0';
elsif con=4 then
n_wr<='1';
if add_en_s='0' then
delay_total<=x"01";
delay_start<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
---------------------------è¯å«--------------------------
if all_wait='1' and delay_finish='1' then
voice_state(3)<='1';
if con=5 then
con:=0;
elsif con=0 then
if con_total=7 then
con_total:=0;
con_type:=0;
con:=0;
all_wait<='0';
all_done<='1';
else
con:=con+1;
end if;
else
con:=con+1;
end if;
if con=0 then
delay_start<='0';
elsif con=1 then
if con_type=0 then
add_en_s<='1';
if con_total=0 then
data_voice<=x"B2";
elsif con_total=3 then
data_voice<=x"BF";
else
data_voice<=rom_init_data(15 downto 8);
end if;
else
add_en_s<='0';
if con_total=0 or con_total=3 then
data_voice<="ZZZZZZZZ";
else
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if (con_total=0 or con_total=3) and con_type=1 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
if (con_total=0 or con_total=3) and con_type=1 then
n_rd<='1';
else
n_wr<='1';
end if;
if add_en_s='0' then
if con_total=2 then
delay_total<=x"05";
else
delay_total<=x"01";
end if;
delay_start<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_total=0 and con_type=1 then
if data_voice=x"21" then
con_total:=con_total+1;
else
con_reset:=con_reset+1;
con_total:=0;
end if;
elsif con_total=3 and con_type=1 then
if data_voice=x"31" then
con_total:=con_total+1;
else
reco_fin<='1';
data_voice<=x"FF";
reset<='1';
end if;
elsif con_type=1 then
con_total:=con_total+1;
end if;
if con_type=1 then
con_type:=0;
else
con_type:=con_type+1;
end if;
end if;
end if;
-----------------------è¯å«ç»æ---------------------
if all_done='1' and delay_finish='1' then
n_int_last<=n_int;
if n_int_last='1' and n_int='0' then
reco_allow<='1';
end if;
end if;
reco_allow_last<=reco_allow;
if reco_allow_last='1' and reco_allow='0' then
reco_fin<='0';
end if;
if reco_allow='1' then
voice_state(2)<='1';
if con=5 then
con:=0;
else
con:=con+1;
end if;
if con=0 then
if con_total=6 then
reco_allow<='0';
all_done<='0';
con:=0;
con_type:=0;
con_total:=0;
end if;
elsif con=1 then
if con_type=0 then
add_en_s<='1';
if con_total=0 then
data_voice<=x"29";
elsif con_total=1 then
data_voice<=x"02";
elsif con_total=2 then
data_voice<=x"BF";
elsif con_total=3 then
data_voice<=x"2B";
elsif con_total=4 then
data_voice<=x"BA";
elsif con_total=5 then
data_voice<=x"C5";
end if;
else
add_en_s<='0';
if con_total<2 then
data_voice<=x"00";
else
data_voice<="ZZZZZZZZ";
end if;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if con_total>1 and con_type=1 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
if con_total>1 and con_type=1 then
n_rd<='1';
else
n_wr<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
if con_total<2 then
con_total:=con_total+1;
elsif con_total=2 and data_voice=x"35" then
con_total:=con_total+1;
elsif con_total=3 and data_voice(3)='0' then
con_total:=con_total+1;
elsif con_total=4 then
if data_voice>x"00" and data_voice<x"05" then
con_total:=con_total+1;
else
voice_result<=x"FD";
reco_allow<='0';
reco_fin<='1';
all_done<='0';
con:=0;
con_type:=0;
con_total:=0;
end if;
elsif con_total=5 then
reco_fin<='1';
voice_result<=data_voice;
con_total:=con_total+1;
else
reset<='1';
end if;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
end process;
end voicex;
| mit | d3bcf5c2c46b5ab7d8ba1c18f6c97b46 | 0.493824 | 2.778617 | false | false | false | false |
Kinxil/VHDL_Projects | Mandelbrot/Iterator.vhd | 1 | 1,948 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Iterator is
Port ( go : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC;
x0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
y0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
itermax : in std_logic_vector(ITER_RANGE-1 downto 0);
iters : out STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
done : out STD_LOGIC);
end Iterator;
architecture Behavioral of Iterator is
component Calc is
Port( y0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
x0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
yi : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
xi : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
yi1 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
xi1 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0));
end component;
signal xi1 : STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
signal yi1 : STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
signal xi : STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
signal yi : STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
signal cptiters : unsigned(ITER_RANGE-1 downto 0);
signal donestate : STD_LOGIC;
begin
fCalc : Calc
port map(y0=>y0,x0=>x0,yi=>yi,xi=>xi,yi1=>yi1,xi1=>xi1);
process(clock, reset, go, itermax)
begin
if reset='1' then
donestate<='1';
xi<=(others=>'0');
yi<=(others=>'0');
cptiters<=(others=>'0');
elsif rising_edge(clock) then
if ((go='1') and (donestate='1')) then --Start iteration
donestate<='0';
cptiters<=(others=>'0');
xi<=(others=>'0');
yi<=(others=>'0');
elsif((cptiters < unsigned(itermax)) and (SIGNED(mult(xi,xi,FIXED)) + SIGNED(mult(yi,yi,FIXED)) < QUATRE)) then --Still <4
xi<=xi1; --Updating values
yi<=yi1;
cptiters <= cptiters + 1;
else --computing done
donestate <= '1';
end if;
end if;
end process;
iters<=std_logic_vector(cptiters);
done<=donestate;
end Behavioral; | gpl-3.0 | f6dbf84b8358e743e43da55c709d132e | 0.656057 | 2.847953 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fslt_2AXI_4CACHE_WORDS.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 2;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | c01b7c53c7496067714b23f3485464b9 | 0.567707 | 3.729005 | false | false | false | false |
preusser/q27 | src/vhdl/top/xilinx/ml605_queens_uart.vhdl | 1 | 4,783 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity ml605_queens_uart is
generic (
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 127;
COUNT_CYCLES : boolean := false;
CLK_FREQ : FREQ := 200 MHz;
CLK_MULA : positive := 6;
CLK_DIVA : positive := 1;
CLK_DIVB : positive := 7;
BAUDRATE : positive := 115200;
SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte
);
port (
clk_p : in std_logic;
clk_n : in std_logic;
rx : in std_logic;
tx : out std_logic;
rts_n : in std_logic;
cts_n : out std_logic;
FanControl_PWM : out std_logic
);
end ml605_queens_uart;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library PoC;
architecture rtl of ml605_queens_uart is
-- Global Control
constant CLK_COMP_FREQ : FREQ := CLK_FREQ * CLK_MULA / CLK_DIVA / CLK_DIVB;
constant CLK_SLOW_FREQ : FREQ := CLK_FREQ * CLK_MULA / CLK_DIVA / 100;
signal clk200 : std_logic; -- 200 MHz Input Clock
signal clk_comp : std_logic; -- Computation Clock
signal clk_slow : std_logic; -- Slow Interface Clock
signal rst : std_logic;
begin
-----------------------------------------------------------------------------
-- Generate Global Controls
blkGlobal: block is
signal clkfb : std_logic; -- Feedback Clock
signal clk_compu : std_logic; -- Unbuffered Synthesized Clock
signal clk_slowu : std_logic; -- Unbuffered Synthesized Clock
begin
clk_in : IBUFGDS
port map(
O => clk200,
I => clk_p,
IB => clk_n
);
pll : MMCM_BASE
generic map (
CLKIN1_PERIOD => to_real(to_time(CLK_FREQ), 1 ns),
CLKFBOUT_MULT_F => real(CLK_MULA),
DIVCLK_DIVIDE => CLK_DIVA,
CLKOUT0_DIVIDE_F => real(CLK_DIVB),
CLKOUT1_DIVIDE => 100,
STARTUP_WAIT => false
)
port map (
CLKIN1 => clk200,
CLKFBIN => clkfb,
RST => '0',
CLKOUT0 => clk_compu,
CLKOUT1 => clk_slowu,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKFBOUT => clkfb,
LOCKED => open,
PWRDWN => '0'
);
comp_buf : BUFG
port map (
I => clk_compu,
O => clk_comp
);
slow_buf : BUFH
port map (
I => clk_slowu,
O => clk_slow
);
-- No Reset
rst <= '0';
end block blkGlobal;
-----------------------------------------------------------------------------
-- Fan Control
fan : entity PoC.io_FanControl
generic map (
CLOCK_FREQ => CLK_SLOW_FREQ
)
port map (
Clock => clk_slow,
Reset => '0',
Fan_PWM => FanControl_PWM,
TachoFrequency => open
);
----------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_uart
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES,
CLK_FREQ => integer(to_real(CLK_COMP_FREQ, 1 Hz)),
BAUDRATE => BAUDRATE,
SENTINEL => SENTINEL
)
port map (
clk => clk_comp,
rst => rst,
rx => rx,
tx => tx,
avail => open
);
cts_n <= rts_n;
end rtl;
| agpl-3.0 | 736151bbfc6c3a3f06792d82f8d3da59 | 0.513694 | 4.056828 | false | false | false | false |
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`protect end_protected
| mit | 6b7006e5d5f836d44bca915626292252 | 0.951551 | 1.8373 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_2AXI.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 722173d7425ae4f9aa5feb488840fe2f | 0.567707 | 3.729005 | false | false | false | false |
malkadi/FGPU | RTL/cache.vhd | 1 | 12,075 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
---------------------------------------------------------------------------------------------------------}}}
entity cache is -- {{{
port(
-- port a
wea : in std_logic_vector(CACHE_N_BANKS*DATA_W/8-1 downto 0);
ena : in std_logic;
addra : in unsigned(M+L-1 downto 0);
dia : in std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
doa : out std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0) := (others=>'0');
-- port b
enb, enb_be : in std_logic;
wr_fifo_rqst_addr : in cache_addr_array(N_WR_FIFOS-1 downto 0);
rd_fifo_rqst_addr : in cache_addr_array(N_AXI-1 downto 0);
wr_fifo_dout : in cache_word_array(N_WR_FIFOS-1 downto 0);
rd_fifo_din_v : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
dob : out std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0) := (others=>'0');
-- ticket signals
ticket_rqst_wr : in std_logic_vector(N_WR_FIFOS-1 downto 0);
ticket_ack_wr_fifo : out std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0');
ticket_rqst_rd : in std_logic_vector(N_AXI-1 downto 0);
ticket_ack_rd_fifo : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
-- be signals
be_rdData : out std_logic_vector (DATA_W/8*2**N-1 downto 0) := (others=>'0');
clk, nrst : in std_logic
);
end cache; -- }}}
architecture Behavioral of cache is
-- internal signals definitions {{{
signal ticket_ack_wr_fifo_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0');
signal ticket_ack_rd_fifo_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal ticket_ack_wr_fifo_i : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0');
signal ticket_ack_rd_fifo_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
-- }}}
-- constants and functions {{{
CONSTANT COL_W : natural := 8;
CONSTANT N_COL : natural := 4*2**N;
--}}}
-- cache definition {{{
type cache_bank_type is array(0 to 2**(M+L)-1) of std_logic_vector(N_COL*COL_W-1 downto 0);
shared variable cache : cache_bank_type := (others=>(others=>'0'));
-- }}}
-- port b signals & ticketing system {{{
signal addrb, addrb_n : unsigned((M+L)-1 downto 0) := (others=>'0');
signal dib, doa_n, dob_n : std_logic_vector((2**N)*DATA_W-1 downto 0) := (others=>'0');
signal web : std_logic_vector((2**N)*DATA_W/8-1 downto 0) := (others=>'0');
signal rd_fifo_din_v_p0 : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal rd_fifo_din_v_p1 : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal rd_fifo_rqst_addr_inc : unsigned((M+L)-1 downto 0) := (others=>'0');
signal rd_fifo_rqst_addr_inc_n : unsigned((M+L)-1 downto 0) := (others=>'0');
signal wr_fifo_dout_d0 : cache_word_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0'));
signal ticket_ack_vec : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_wr_vec : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_rd_vec : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_vec_d0 : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_wr_vec_d0 : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_rd_vec_d0 : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_vec_n : std_logic := '0';
signal ticket_ack_wr_vec_n : std_logic := '0';
signal ticket_ack_rd_vec_n : std_logic := '0';
signal wr_fifo_ack_indx_n : integer range 0 to N_WR_FIFOS-1 := 0;
signal wr_fifo_ack_indx : integer range 0 to N_WR_FIFOS-1 := 0;
signal wr_fifo_ack_indx_d0 : integer range 0 to N_WR_FIFOS-1 := 0;
signal rd_fifo_ack_indx_n : integer range 0 to N_AXI-1 := 0;
signal rd_fifo_ack_indx : integer range 0 to N_AXI-1 := 0;
signal rd_fifo_ack_indx_d0 : integer range 0 to N_AXI-1 := 0;
signal wr_fifo_rqst_addr_d0 : cache_addr_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0'));
signal rd_fifo_rqst_addr_d0 : cache_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
-- }}}
-- be signals{{{
type be_mem_type is array(0 to 2**(M+L)-1) of std_logic_vector(2**N*DATA_W/8-1 downto 0);
shared variable be : be_mem_type := (others=>(others=>'0'));
signal be_we : std_logic := '0';
attribute max_fanout of wr_fifo_ack_indx_d0 : signal is 60;
signal be_rdData_n : std_logic_vector (DATA_W/8*2**N-1 downto 0) := (others=>'0');
---}}}
begin
-- internal signals assignments -------------------------------------------------------------------------{{{
ticket_ack_wr_fifo <= ticket_ack_wr_fifo_i;
ticket_ack_rd_fifo <= ticket_ack_rd_fifo_i;
---------------------------------------------------------------------------------------------------------}}}
-- error handling -------------------------------------------------------------------------------------------{{{
-- assert(addra(7 downto 0) /= X"B7" or addra(8) /= '0' or wea(7 downto 4) /= X"F");
---------------------------------------------------------------------------------------------------------}}}
-- be -------------------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
if ena = '1' then
-- if to_integer(addra) = 11 and wea /= (wea'range => '0') then
-- report "Address B written";
-- end if;
for j in 0 to 2**N*DATA_W/8-1 loop
if wea(j) = '1' then
be(to_integer(addra))(j) := '1';
end if;
end loop;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
be_rdData_n <= be(to_integer(addrb));
if be_we = '1' then
be(to_integer(addrb)) := (others=>'0');
end if;
if enb_be = '1' then
be_rdData <= be_rdData_n;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- cache port b control -------------------------------------------------------------------------------------------{{{
assert(ticket_ack_rd_vec = (ticket_ack_rd_vec'reverse_range=>'0') or ticket_ack_wr_vec = (ticket_ack_wr_vec'reverse_range=>'0'));
process(clk)
begin
if rising_edge(clk) then
ticket_ack_wr_fifo_i <= ticket_ack_wr_fifo_n;
ticket_ack_rd_fifo_i <= ticket_ack_rd_fifo_n;
wr_fifo_dout_d0 <= wr_fifo_dout;
ticket_ack_vec(ticket_ack_vec'high-1 downto 0) <= ticket_ack_vec(ticket_ack_vec'high downto 1);
ticket_ack_vec(ticket_ack_vec'high) <= ticket_ack_vec_n;
ticket_ack_vec_d0 <= ticket_ack_vec;
ticket_ack_wr_vec(ticket_ack_wr_vec'high-1 downto 0) <= ticket_ack_wr_vec(ticket_ack_wr_vec'high downto 1);
ticket_ack_wr_vec(ticket_ack_wr_vec'high) <= ticket_ack_wr_vec_n;
ticket_ack_wr_vec_d0 <= ticket_ack_wr_vec;
ticket_ack_rd_vec(ticket_ack_rd_vec'high-1 downto 0) <= ticket_ack_rd_vec(ticket_ack_rd_vec'high downto 1);
ticket_ack_rd_vec(ticket_ack_rd_vec'high) <= ticket_ack_rd_vec_n;
ticket_ack_rd_vec_d0 <= ticket_ack_rd_vec;
wr_fifo_ack_indx <= wr_fifo_ack_indx_n;
rd_fifo_ack_indx <= rd_fifo_ack_indx_n;
wr_fifo_ack_indx_d0 <= wr_fifo_ack_indx;
rd_fifo_ack_indx_d0 <= rd_fifo_ack_indx;
wr_fifo_rqst_addr_d0 <= wr_fifo_rqst_addr;
rd_fifo_rqst_addr_d0 <= rd_fifo_rqst_addr;
-- write path
web <= (others=>'0');
dib <= wr_fifo_dout_d0(wr_fifo_ack_indx_d0);
if ticket_ack_wr_vec_d0 /= (ticket_ack_wr_vec_d0'reverse_range => '0') then
addrb <= wr_fifo_rqst_addr_d0(wr_fifo_ack_indx_d0);
web <= (others=>'1');
end if;
-- read path
be_we <= '0';
rd_fifo_din_v_p1 <= (others=>'0');
if ticket_ack_rd_vec_d0 /= (ticket_ack_rd_vec_d0'reverse_range => '0') then
addrb <= rd_fifo_rqst_addr_inc;
rd_fifo_din_v_p1(rd_fifo_ack_indx_d0) <= '1';
be_we <= '1';
end if;
rd_fifo_din_v_p0 <= rd_fifo_din_v_p1;
rd_fifo_din_v <= rd_fifo_din_v_p0;
if nrst = '0' then
rd_fifo_rqst_addr_inc <= (others=>'0');
else
rd_fifo_rqst_addr_inc <= rd_fifo_rqst_addr_inc_n;
end if;
end if;
end process;
process(ticket_rqst_wr, ticket_rqst_rd, ticket_ack_vec, wr_fifo_ack_indx, rd_fifo_ack_indx, rd_fifo_rqst_addr_inc, rd_fifo_rqst_addr_d0, ticket_ack_rd_vec_d0)
variable wr_served: boolean := false;
begin
ticket_ack_wr_fifo_n <= (others=>'0');
ticket_ack_rd_fifo_n <= (others=>'0');
ticket_ack_vec_n <= '0';
ticket_ack_wr_vec_n <= '0';
ticket_ack_rd_vec_n <= '0';
wr_fifo_ack_indx_n <= wr_fifo_ack_indx;
rd_fifo_ack_indx_n <= rd_fifo_ack_indx;
rd_fifo_rqst_addr_inc_n <= rd_fifo_rqst_addr_inc;
if ticket_ack_rd_vec_d0(ticket_ack_rd_vec_d0'high downto 1) /= (0 to ticket_ack_rd_vec_d0'high-1 =>'0') then
rd_fifo_rqst_addr_inc_n <= rd_fifo_rqst_addr_inc + 1;
else
rd_fifo_rqst_addr_inc_n <= rd_fifo_rqst_addr_d0(rd_fifo_ack_indx);
end if;
wr_served := false;
for i in 0 to N_WR_FIFOS-1 loop
-- if ticket_rqst_wr(i) = '1' and ticket_ack_vec = (ticket_ack_vec'range=>'0') then
if ticket_rqst_wr(i) = '1' and ticket_ack_vec(ticket_ack_vec'high downto 1) = (0 to ticket_ack_vec'high-1 =>'0') then
ticket_ack_wr_fifo_n(i) <= '1';
wr_served := true;
ticket_ack_vec_n <= '1';
ticket_ack_wr_vec_n <= '1';
wr_fifo_ack_indx_n <= i;
exit;
end if;
end loop;
if wr_served = false then
for i in 0 to N_AXI-1 loop
if ticket_rqst_rd(i) = '1' and ticket_ack_vec(ticket_ack_vec'high downto 1) = (0 to ticket_ack_vec'high-1 =>'0') then
ticket_ack_rd_fifo_n(i) <= '1';
ticket_ack_vec_n <= '1';
ticket_ack_rd_vec_n <= '1';
rd_fifo_ack_indx_n <= i;
-- rd_fifo_rqst_addr_inc_n <= rd_fifo_rqst_addr(i);
exit;
end if;
end loop;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- cache mems -------------------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
doa_n <= cache(to_integer(addra));
for j in 0 to N_COL-1 loop
if wea(j) = '1' then
cache(to_integer(addra))((j+1)*COL_W-1 downto j*COL_W) := dia((j+1)*COL_W-1 downto j*COL_W);
end if;
end loop;
if ena = '1' then
doa <= doa_n;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if enb = '1' then
dob <= dob_n;
end if;
dob_n <= cache(to_integer(addrb));
-- assert(web = (web'range => '0') or dib /= (dib'range => '0')) severity failure;
for j in 0 to N_COL-1 loop
if web(j) = '1' then
cache(to_integer(addrb))((j+1)*COL_W-1 downto j*COL_W) := dib((j+1)*COL_W-1 downto j*COL_W);
end if;
end loop;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
end Behavioral;
| gpl-3.0 | 4c3b59826f32957602ea4bddb206957c | 0.504679 | 3.157688 | false | false | false | false |
joalcava/sparcv8-monocicle | Test_signExtUnit.vhd | 1 | 2,189 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:20:42 10/06/2016
-- Design Name:
-- Module Name: C:/Users/utp.CRIE/Desktop/sparcv8-monocicle/Test_signExtUnit.vhd
-- Project Name: monocicle-sparcv8
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: sign_ext_unit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_signExtUnit IS
END Test_signExtUnit;
ARCHITECTURE behavior OF Test_signExtUnit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sign_ext_unit
PORT(
entrada : IN std_logic_vector(12 downto 0);
salida : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal entrada : std_logic_vector(12 downto 0) := (others => '0');
--Outputs
signal salida : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sign_ext_unit PORT MAP (
entrada => entrada,
salida => salida
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
entrada <= "1111111111111";
wait for 100 ns;
entrada <= "0011111111111";
wait for 100 ns;
entrada <= "1010101010101";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 92c7beacd814348e5830de8493ad9e3c | 0.612152 | 4.130189 | false | true | false | false |
dtysky/LD3320_AXI | hdl/LD3320_AXI_v1_0.vhd | 1 | 4,445 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity LD3320_AXI_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
inclk,inclk_n:in std_logic;
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_logic:='0';
data_voice:inout std_logic_vector(7 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end LD3320_AXI_v1_0;
architecture arch_imp of LD3320_AXI_v1_0 is
-- component declaration
component LD3320_AXI_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
inclk,inclk_n:in std_logic;
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_logic:='0';
data_voice:inout std_logic_vector(7 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component LD3320_AXI_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
LD3320_AXI_v1_0_S00_AXI_inst : LD3320_AXI_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
inclk=>inclk,
inclk_n=>inclk_n,
clk_voice=>clk_voice,
n_wr=>n_wr,
n_cs=>n_cs,
n_rd=>n_rd,
n_rst=>n_rst,
n_int=>n_int,
add_en=>add_en,
data_voice=>data_voice,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| mit | a66e3021052302a7621f1ffb1bda129a | 0.648369 | 2.405303 | false | false | false | false |
jpidancet/mips | rtl/cpu_memory.vhd | 1 | 1,370 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity cpu_memory is
port (regwrite : in std_logic;
memtoreg : in std_logic;
memread : in std_logic;
memwrite : in std_logic;
aluout : in std_logic_vector(31 downto 0);
writedata : in std_logic_vector(31 downto 0);
writereg : in std_logic_vector(4 downto 0);
regwrite_n : out std_logic;
memtoreg_n : out std_logic;
aluout_n : out std_logic_vector(31 downto 0);
readdata_n : out std_logic_vector(31 downto 0);
writereg_n : out std_logic_vector(4 downto 0);
data_addr : out std_logic_vector(31 downto 0);
data_read : out std_logic;
data_in : in std_logic_vector(31 downto 0);
data_write : out std_logic;
data_out : out std_logic_vector(31 downto 0));
end entity cpu_memory;
architecture rtl of cpu_memory is
begin
regwrite_n <= regwrite;
memtoreg_n <= memtoreg;
aluout_n <= aluout;
writereg_n <= writereg;
data_addr <= aluout;
data_read <= memread;
data_write <= memwrite;
data_out <= writedata;
readdata_n <= data_in;
end architecture rtl;
| isc | d3e92e4ea227a35042063aa5c672ad43 | 0.552555 | 3.614776 | false | false | false | false |
dtysky/LD3320_AXI | src/LIST/LIST_funcsim.vhdl | 1 | 47,409 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014
-- Date : Wed Sep 10 03:38:08 2014
-- Host : Dtysky running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/spira_heaven/0-myworks/ld3320_axi/ld3320_axi_1.0/src/LIST/LIST_funcsim.vhdl
-- Design : LIST
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST_blk_mem_gen_prim_wrapper is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of LIST_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end LIST_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of LIST_blk_mem_gen_prim_wrapper is
signal \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_13_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_29_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12 downto 5) => addrb(7 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12 downto 5) => addra(7 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => clkb,
CLKBWRCLK => clka,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9 downto 8) => dina(3 downto 2),
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9 downto 8) => dina(7 downto 6),
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1 downto 0) => dina(5 downto 4),
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15) => \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(14) => \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(13) => \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(12) => \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(11) => \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(10) => \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(9 downto 8) => doutb(3 downto 2),
DOADO(7) => \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(6) => \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(5) => \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(4) => \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(3) => \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(2) => \n_13_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(1 downto 0) => doutb(1 downto 0),
DOBDO(15) => \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(14) => \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(13) => \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(12) => \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(11) => \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(10) => \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(9 downto 8) => doutb(7 downto 6),
DOBDO(7) => \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(6) => \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(5) => \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(4) => \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(3) => \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(2) => \n_29_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(1 downto 0) => doutb(5 downto 4),
DOPADOP(1) => \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPADOP(0) => \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(1) => \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(0) => \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
ENARDEN => '1',
ENBWREN => wea(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => '1',
WEBWE(2) => '1',
WEBWE(1) => '1',
WEBWE(0) => '1'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST_blk_mem_gen_prim_width is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of LIST_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end LIST_blk_mem_gen_prim_width;
architecture STRUCTURE of LIST_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.LIST_blk_mem_gen_prim_wrapper
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of LIST_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end LIST_blk_mem_gen_generic_cstr;
architecture STRUCTURE of LIST_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.LIST_blk_mem_gen_prim_width
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of LIST_blk_mem_gen_top : entity is "blk_mem_gen_top";
end LIST_blk_mem_gen_top;
architecture STRUCTURE of LIST_blk_mem_gen_top is
begin
\valid.cstr\: entity work.LIST_blk_mem_gen_generic_cstr
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST_blk_mem_gen_v8_2_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of LIST_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end LIST_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of LIST_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.LIST_blk_mem_gen_top
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \LIST_blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "no_coe_file_loaded";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "LIST.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 256;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 256;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 256;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 256;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "1";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 2.68455 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \LIST_blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \LIST_blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.LIST_blk_mem_gen_v8_2_synth
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of LIST : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of LIST : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of LIST : entity is "blk_mem_gen_v8_2,Vivado 2014.2";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of LIST : entity is "LIST,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of LIST : entity is "LIST,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=LIST.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.68455 mW}";
end LIST;
architecture STRUCTURE of LIST is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 8;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 8;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.68455 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "LIST.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 256;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 256;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 256;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 256;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\LIST_blk_mem_gen_v8_2__parameterized0\
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(7 downto 0) => dina(7 downto 0),
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(7 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(7 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(7 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(7 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| mit | 2481037c204c30d64a14aa84ada41625 | 0.660086 | 3.120656 | false | false | false | false |
Kinxil/VHDL_Projects | Mandelbrot/mux2.vhd | 1 | 1,563 |
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
entity muxandcpt is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
i_iters1 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters2 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters3 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters4 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters5 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters6 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters7 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters8 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
startVGA : in STD_LOGIC;
o_iters : out STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
doneVGA : out STD_LOGIC);
end muxandcpt;
architecture Behavioral of muxandcpt is
signal cpt : integer range 0 to 7;
begin
process(clock, reset, startVGA, cpt)
begin
if reset='1' then
cpt <= 0;
doneVGA <= '0';
elsif rising_edge(clock) then
if startVGA='1' then
if(cpt=7) then
cpt<=0;
doneVGA<='1';
else
cpt <= cpt + 1;
doneVGA<='0';
end if;
end if;
end if;
end process;
o_iters <= i_iters7 when (cpt = 7) else
i_iters6 when (cpt = 6) else
i_iters5 when (cpt = 5) else
i_iters4 when (cpt = 4) else
i_iters3 when (cpt = 3) else
i_iters2 when (cpt = 2) else
i_iters1 when (cpt = 1) else
i_iters8;
end Behavioral;
| gpl-3.0 | e0e8b7b6af42f4e9a464d48ce12af5bd | 0.590531 | 2.878453 | false | false | false | false |
kennethlyn/fpga-image-example | hdl_nodes/adder_2_to_1/adder_2_to_1.srcs/sources_1/dyplo_hdl_node.vhd | 1 | 10,306 | -- File: dyplo_hdl_node.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
--
-- Disclaimer
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Topic Embedded Products B.V., and to the maximum
-- extend permitted by applicable law:
--
-- 1. Dyplo is furnished on an "as is", as available basis. Topic makes no
-- warranty, express or implied, with respect to the capability of Dyplo. All
-- warranties of any type, express or implied, including the warranties of
-- merchantability, fitness for a particular purpose and non-infringement of
-- third party rights are expressly disclaimed.
--
-- 2. Topic's maximum total liability shall be limited to general money
-- damages in an amount not to exceed the total amount paid for in the year
-- in which the damages have occurred. Under no circumstances including
-- negligence shall Topic be liable for direct, indirect, incidental, special,
-- consequential or punitive damages, or for loss of profits, revenue, or data,
-- that are directly or indirectly related to the use of, or the inability to
-- access and use Dyplo and related services, whether in an action in contract,
-- tort, product liability, strict liability, statute or otherwise even if
-- Topic has been advised of the possibility of those damages.
--
-- This copyright notice and disclaimer must be retained as part of this file at all times.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library dyplo_hdl_node_lib;
use dyplo_hdl_node_lib.hdl_node_package.all;
use dyplo_hdl_node_lib.hdl_node_user_params.all;
library user_logic;
use user_logic.all;
entity dyplo_hdl_node is
port(
-- Miscellaneous
node_id : in std_logic_vector(c_hdl_node_id_width - 1 downto 0);
-- DAB interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(c_hdl_dab_awidth - 1 downto 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Receive data from backplane to FIFO
b2f_tdata : in std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
b2f_tstream_id : in std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
b2f_tvalid : in std_logic;
b2f_tready : out std_logic;
-- Send data from FIFO to backplane
f2b_tdata : out std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
f2b_tstream_id : out std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
f2b_tvalid : out std_logic;
f2b_tready : in std_logic;
-- Serial fifo status info
fifo_status_sync : in std_logic;
fifo_status_flag : out std_logic;
-- fifo statuses of destination fifo's
dest_fifo_status : in std_logic_vector(3 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
attribute secure_config : string;
attribute secure_config of dyplo_hdl_node : entity is "PROTECT";
attribute secure_netlist : string;
attribute secure_netlist of dyplo_hdl_node : entity is "ENCRYPT";
attribute secure_net_editing : string;
attribute secure_net_editing of dyplo_hdl_node : entity is "PROHIBIT";
attribute secure_net_probing : string;
attribute secure_net_probing of dyplo_hdl_node : entity is "PROHIBIT";
end dyplo_hdl_node;
architecture rtl of dyplo_hdl_node is
component dyplo_user_logic_adder_2_to_1 is
generic(
INPUT_STREAMS : integer := 4;
OUTPUT_STREAMS : integer := 4
);
port(
-- Processor bus interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(15 downto 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Streaming input interfaces
cin_tdata : in cin_tdata_ul_type;
cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tlevel : in cin_tlevel_ul_type;
-- Streaming output interfaces
cout_tdata : out cout_tdata_ul_type;
cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
end component dyplo_user_logic_adder_2_to_1;
signal dab_sel_ul : std_logic;
signal dab_wvalid_ul : std_logic;
signal dab_rvalid_ul : std_logic;
signal dab_rdata_ul : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
signal cin_tdata_i : cin_tdata_ul_type;
signal cin_tvalid_i : std_logic_vector(c_input_streams - 1 downto 0);
signal cin_tready_i : std_logic_vector(c_input_streams - 1 downto 0);
signal cin_tlevel_i : cin_tlevel_ul_type;
signal cout_tdata_i : cout_tdata_ul_type;
signal cout_tvalid_i : std_logic_vector(c_output_streams - 1 downto 0);
signal cout_tready_i : std_logic_vector(c_output_streams - 1 downto 0);
begin
-----------------------------------------------------------------------------
-- CONTROL MEMORY MAP FOR CPU FIFO INTERFACE --
-----------------------------------------------------------------------------
-- The available memory range for the CPU fifo control is limited to --
-- 64Kbyte/32 = 2Kbytes or 512 words. The maximum burst transfer of the --
-- AXI bus is 256 words. The actual FIFO data memory range is also limited --
-- to 64Kbytes or 16Kwords. Also, the space is divided between reading and --
-- writing. This leaves 8Kwords per direction and with a burst length of --
-- 256 words, maximum 32 input streams and 32 output streams can be --
-- supported. --
-----------------------------------------------------------------------------
-- Each fifo has the following metrics: --
-- - FIFO full and FIFO empty flag --
-- - FIFO fill level compare register and compare flag --
-- - Actual FIFO fill level indicator --
-- - Under/overflow detection flag when operating FIFO out of range --
-- --
-- Per input FIFO (from FPGA fabric to the CPU) it is required to specify --
-- the stream source. Also, a maskable interrupt should be issued per --
-- input FIFO to signal the need to empty the FIFO by the CPU. --
-----------------------------------------------------------------------------
dyplo_hdl_node_logic_i : dyplo_hdl_node_logic
generic map (
INPUT_STREAMS => c_input_streams,
OUTPUT_STREAMS => c_output_streams
)
port map(
-- Miscellaneous
node_id => node_id,
-- DAB interface
dab_clk => dab_clk,
dab_rst => dab_rst,
dab_addr => dab_addr,
dab_sel => dab_sel,
dab_wvalid => dab_wvalid,
dab_rvalid => dab_rvalid,
dab_wdata => dab_wdata,
dab_rdata => dab_rdata,
-- Receive data from backplane to FIFO
b2f_tdata => b2f_tdata,
b2f_tstream_id => b2f_tstream_id,
b2f_tvalid => b2f_tvalid,
b2f_tready => b2f_tready,
-- Send data from FIFO to backplane
f2b_tdata => f2b_tdata,
f2b_tstream_id => f2b_tstream_id,
f2b_tvalid => f2b_tvalid,
f2b_tready => f2b_tready,
-- Serial fifo status info
fifo_status_sync => fifo_status_sync,
fifo_status_flag => fifo_status_flag,
-- fifo statuses of destination fifo's
dest_fifo_status => dest_fifo_status(c_output_streams - 1 downto 0),
-- DAB interface to user logic
dab_sel_ul => dab_sel_ul,
dab_wvalid_ul => dab_wvalid_ul,
dab_rvalid_ul => dab_rvalid_ul,
dab_rdata_ul => dab_rdata_ul,
-- In streams to user logic
cin_tdata_ul => cin_tdata_i,
cin_tvalid_ul => cin_tvalid_i,
cin_tready_ul => cin_tready_i,
cin_tlevel_ul => cin_tlevel_i,
-- Out streams from user logic
cout_tdata_ul => cout_tdata_i,
cout_tvalid_ul => cout_tvalid_i,
cout_tready_ul => cout_tready_i
);
dyplo_user_logic_i : dyplo_user_logic_adder_2_to_1
generic map(
INPUT_STREAMS => c_input_streams,
OUTPUT_STREAMS => c_output_streams
)
port map(
-- Processor bus interface
dab_clk => dab_clk,
dab_rst => dab_rst,
dab_addr => dab_addr(15 downto 0),
dab_sel => dab_sel_ul,
dab_wvalid => dab_wvalid_ul,
dab_rvalid => dab_rvalid_ul,
dab_wdata => dab_wdata,
dab_rdata => dab_rdata_ul,
-- Streaming input interfaces
cin_tdata => cin_tdata_i,
cin_tvalid => cin_tvalid_i,
cin_tready => cin_tready_i,
cin_tlevel => cin_tlevel_i,
-- Streaming output interfaces
cout_tdata => cout_tdata_i,
cout_tvalid => cout_tvalid_i,
cout_tready => cout_tready_i,
-- Clock signals
user_clocks => user_clocks
);
end rtl;
| gpl-2.0 | 9aad261290fd4054fafd32f840bf4158 | 0.581813 | 3.734686 | false | false | false | false |
chrreisinger/OpenVC | document/Masterarbeit/src/reg4Behv.vhd | 1 | 412 | architecture behav of reg4 is
begin
storage : process is
variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
begin
wait until clk;
if en then
stored_d0 := d0;
stored_d1 := d1;
stored_d2 := d2;
stored_d3 := d3;
end if;
q0 <= stored_d0 after 5 ns;
q1 <= stored_d1 after 5 ns;
q2 <= stored_d2 after 5 ns;
q3 <= stored_d3 after 5 ns;
end process storage;
end architecture behav; | gpl-3.0 | 9d951e2b04e9bb3170364e7c604d60f2 | 0.650485 | 2.559006 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/fetch_page/fetch_page_sram_dim.vhd | 1 | 5,225 | -------------------------------------------------------------------------------
--! @file fetch_page_sram_dim.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-11-19
--! @brief Prepare SRAM page with DIM data for NanoFIP communication.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! @brief Entity declaration of fetch_page_sram_dim
--! @details
--! This component prepares the SRAM DIM log page for the NanoFIP response.
entity fetch_page_sram_dim is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Commands
--! @{
--! Start flag
start_i : in std_ulogic;
--! Done flag
done_o : out std_ulogic;
--! @}
--! @name Memory page interface
--! @{
--! Address
page_addr_o : out std_ulogic_vector(5 downto 0);
--! Write enable
page_wr_en_o : out std_ulogic;
--! Data output
page_data_o : out std_ulogic_vector(7 downto 0);
--! Done flag
page_done_i : in std_ulogic;
--! @}
--! @name External SRAM data
--! @{
-- Address
sram_addr_o : out std_ulogic_vector(4 downto 0);
--! Read request
sram_rd_en_o : out std_ulogic;
--! Data input
sram_data_i : in std_ulogic_vector(15 downto 0);
--! Data input enable
sram_data_en_i : in std_ulogic);
--! @}
end entity fetch_page_sram_dim;
--! RTL implementation of fetch_page_sram_dim
architecture rtl of fetch_page_sram_dim is
---------------------------------------------------------------------------
--! @name Types and Constants
---------------------------------------------------------------------------
--! @{
type state_t is (IDLE, WRITE_LOW, WRITE_HIGH, DONE);
type reg_t is record
state : state_t;
addr : unsigned(5 downto 0);
data : std_ulogic_vector(7 downto 0);
wr_en : std_ulogic;
rd_en : std_ulogic;
done : std_ulogic;
end record;
constant init_c : reg_t := (
state => IDLE,
addr => (others => '0'),
data => (others => '0'),
wr_en => '0',
rd_en => '0',
done => '0');
--! @}
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal reg : reg_t;
--! @}
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
signal next_reg : reg_t;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
page_addr_o <= std_ulogic_vector(reg.addr);
page_wr_en_o <= reg.wr_en;
page_data_o <= reg.data;
sram_addr_o <= std_ulogic_vector(reg.addr(5 downto 1));
sram_rd_en_o <= reg.rd_en;
done_o <= reg.done;
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= next_reg;
end if;
end if;
end process regs;
---------------------------------------------------------------------------
-- Combinatorics
---------------------------------------------------------------------------
comb : process (reg, start_i, page_done_i, sram_data_i, sram_data_en_i) is
begin -- comb
-- Defaults
next_reg <= reg;
next_reg.rd_en <= '0';
next_reg.wr_en <= '0';
next_reg.done <= '0';
case reg.state is
when IDLE =>
if start_i = '1' then
next_reg.rd_en <= '1';
next_reg.state <= WRITE_LOW;
end if;
when WRITE_LOW =>
if sram_data_en_i = '1' then
next_reg.data <= sram_data_i(7 downto 0);
next_reg.wr_en <= '1';
end if;
if page_done_i = '1' then
next_reg.addr <= reg.addr + 1;
next_reg.state <= WRITE_HIGH;
end if;
when WRITE_HIGH =>
next_reg.data <= sram_data_i(15 downto 8);
next_reg.wr_en <= '1';
next_reg.state <= DONE;
when DONE =>
if page_done_i = '1' then
if to_integer(reg.addr) < 63 then
next_reg.addr <= reg.addr + 1;
next_reg.rd_en <= '1';
next_reg.state <= WRITE_LOW;
else
next_reg <= init_c;
next_reg.done <= '1';
end if;
end if;
end case;
end process comb;
end architecture rtl;
| mit | d10177d3b84bc6382355dcb61b91ebd1 | 0.426603 | 4.009977 | false | false | false | false |
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`protect end_protected
| mit | 2db592b151e8cd320525a14dce293868 | 0.952336 | 1.833279 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fslt.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | cf6e15861d2694ab5e267c7e610e36f6 | 0.567707 | 3.729005 | false | false | false | false |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_reset_unit.vhd | 1 | 39,205 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_reset_unit |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_reset_unit.vhd |
-- |
-- Description The unit is responsible for the generation of the: |
-- |
-- o nanoFIP internal reset that resets all nanoFIP's logic, apart from WISHBONE. |
-- It is asserted: |
-- - after the assertion of the "nanoFIP User Interface General signal" RSTIN; |
-- in this case it stays active for 4 uclk cycles |
-- - after the reception of a var_rst with its 1st application-data byte |
-- containing the station's address; in this case as well it stays active for |
-- 4 uclk cycles |
-- - during the activation of the "nanoFIP User Interface General signal" RSTPON;|
-- in this case it stays active for as long as the RSTPON is active. |
-- __________ |
-- RSTIN | | \ \ |
-- ________| FSM |_______ \ \ |
-- | RSTIN | \ \ |
-- |__________| \ \ |
-- __________ | \ |
-- rst_nFIP_and_FD_p | | | | nFIP_rst |
-- ________| FSM |________ |OR | _______________ |
-- | var_rst | | | |
-- |__________| | / |
-- / / |
-- RSTPON / / |
-- __________________________ / / |
-- / / |
-- |
-- |
-- o FIELDRIVE reset: nanoFIP FIELDRIVE output FD_RSTN |
-- Same as the nanoFIP internal reset, it can be activated by the RSTIN, |
-- the var_rst or the RSTPON. |
-- Regarding the activation time, for the first two cases (RSTIN, var_rst) it stays|
-- asserted for 4 FD_TXCK cycles whereas in the case of the RSTPON, it stays active|
-- for as long as the RSTPON is active. |
-- |
-- __________ |
-- RSTIN | | \ \ |
-- ________| FSM |_______ \ \ |
-- | RSTIN | \ \ |
-- |__________| \ \ |
-- __________ | \ |
-- rst_nFIP_and_FD_p | | | | FD_RSTN |
-- ________| FSM |________ |OR | _______________ |
-- | var_rst | | | |
-- |__________| | / |
-- / / |
-- RSTPON / / |
-- __________________________ / / |
-- / / |
-- |
-- o reset to the external logic: "nanoFIP User Interface, General signal" RSTON |
-- It is asserted after the reception of a var_rst with its 2nd data byte |
-- containing the station's address. |
-- It stays active for 8 uclk cycles. |
-- _________ |
-- assert_RSTON_p | | RSTON |
-- ________| FSM |_________________________________ |
-- | var_rst | |
-- |__________| |
-- |
-- o nanoFIP internal reset for the WISHBONE logic: |
-- It is asserted after the assertion of the "nanoFIP User Interface, WISHBONE |
-- Slave" input RST_I or of the "nanoFIP User Interface General signal" RSTPON. |
-- It stays asserted for as long as the RST_I or RSTPON stay asserted. |
-- |
-- RSTPON |
-- __________________________ \ \ |
-- \ \ wb_rst |
-- RST_I |OR|____________________ |
-- __________________________ / / |
-- / / |
-- |
-- Notes: |
-- - The input signal RSTIN is considered only if it has been active for at least |
-- 4 uclk cycles; the functional specs define 8 uclks, but in reality we check for 4.|
-- - The pulses rst_nFIP_and_FD_p and assert_RSTON_p come from the wf_cons_outcome |
-- unit only after the sucessful validation of the frame structure and of the |
-- application-data bytes of the var_rst. |
-- - The RSTPON (Power On Reset generated with an RC circuit) removal is synchronized |
-- with both uclk and wb_clk. |
-- |
-- The unit implements 2 state machines: one for resets coming from RSTIN |
-- and one for resets coming from a var_rst. |
-- |
-- |
-- Authors Erik van der Bij (Erik.van.der.Bij@cern.ch) |
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 11/2011 |
-- Version v0.03 |
-- Depends on wf_consumption |
---------------- |
-- Last changes |
-- 07/2009 v0.01 EB First version |
-- 08/2010 v0.02 EG checking of bytes1 and 2 of reset var added |
-- fd_rstn_o, nfip_rst_o enabled only if rstin has been active for>4 uclk |
-- 01/2011 v0.03 EG PoR added; signals assert_rston_p_i & rst_nfip_and_fd_p_i are inputs |
-- treated in the wf_cons_outcome; 2 state machines created; clean-up |
-- PoR also for internal WISHBONE resets |
-- 02/2011 v0.031 EG state nFIP_OFF_FD_OFF added |
-- 11/2011 v0.032 EG added s_rstin_c_is_full, s_var_rst_c_is_full signals that reset FSMs |
-- corrections on # cycles nFIP_rst is activated (was 6, now 4) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_reset_unit
--=================================================================================================
entity wf_reset_unit is port(
-- INPUTS
-- nanoFIP User Interface General signals
uclk_i : in std_logic; -- 40 MHz clock
rstin_a_i : in std_logic; -- initialization control, active low
rstpon_a_i : in std_logic; -- Power On Reset, active low
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- nanoFIP User Interface WISHBONE Slave
rst_i : in std_logic; -- WISHBONE reset
wb_clk_i : in std_logic; -- WISHBONE clock
-- Signal from the wf_consumption unit
rst_nfip_and_fd_p_i : in std_logic; -- indicates that a var_rst with its 1st byte
-- containing the station's address has been
-- correctly received
assert_rston_p_i : in std_logic; -- indicates that a var_rst with its 2nd byte
-- containing the station's address has been
-- correctly received
-- OUTPUTS
-- nanoFIP internal reset, to all the units
nfip_rst_o : out std_logic; -- nanoFIP internal reset, active high
-- resets all nanoFIP logic, apart from the WISHBONE
-- Signal to the wf_wb_controller
wb_rst_o : out std_logic; -- reset of the WISHBONE logic
-- nanoFIP User Interface General signal output
rston_o : out std_logic; -- reset output, active low
-- nanoFIP FIELDRIVE output
fd_rstn_o : out std_logic); -- FIELDRIVE reset, active low
end entity wf_reset_unit;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_reset_unit is
-- RSTIN and RSTPON synchronizers
signal s_rsti_synch : std_logic_vector (2 downto 0);
signal s_wb_por_synch, s_u_por_synch : std_logic_vector (1 downto 0);
-- FSM for RSTIN
type rstin_st_t is (IDLE, RSTIN_EVAL, nFIP_ON_FD_ON, nFIP_OFF_FD_ON, nFIP_OFF_FD_OFF);
signal rstin_st, nx_rstin_st : rstin_st_t;
-- RSTIN counter
signal s_rstin_c, s_var_rst_c : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_rstin_c_reinit, s_rstin_c_is_three : std_logic;
signal s_rstin_c_is_seven, s_rstin_c_is_4txck : std_logic;
signal s_rstin_c_is_full : std_logic;
-- resets generated after a RSTIN
signal s_rstin_nfip, s_rstin_fd : std_logic;
-- FSM for var_rst
type var_rst_st_t is (VAR_RST_IDLE, VAR_RST_RSTON_ON, VAR_RST_nFIP_ON_FD_ON_RSTON_ON,
VAR_RST_nFIP_OFF_FD_ON_RSTON_ON, VAR_RST_nFIP_ON_FD_ON,
VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF);
signal var_rst_st, nx_var_rst_st : var_rst_st_t;
-- var_rst counter
signal s_var_rst_c_reinit, s_var_rst_c_is_three : std_logic;
signal s_var_rst_c_is_seven, s_var_rst_c_is_4txck : std_logic;
signal s_var_rst_c_is_full : std_logic;
-- resets generated after a var_rst
signal s_var_rst_fd, s_var_rst_nfip, s_rston : std_logic;
-- info needed to define the length of the FD_RSTN
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LGTH - 1 downto 0);
signal s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_transm_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclk ticks of a
-- transmission period
s_txck_four_periods <= resize(s_transm_period, s_txck_four_periods'length) sll 1;-- # uclk ticks
-- of 2 transm.
-- periods = 4
-- FD_TXCK periods
---------------------------------------------------------------------------------------------------
-- Input Synchronizers --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTIN synchronization with the uclk, using a set of 3 registers.
RSTIN_uclk_Synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
s_rsti_synch <= s_rsti_synch (1 downto 0) & not rstin_a_i;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTPON synchronization, with the wb_clk.
-- The second flip-flop is used to remove metastabilities.
PoR_wb_clk_Synchronizer: process (wb_clk_i, rstpon_a_i)
begin
if rstpon_a_i = '0' then
s_wb_por_synch <= (others => '1');
elsif rising_edge (wb_clk_i) then
s_wb_por_synch <= s_wb_por_synch(0) & '0';
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTPON synchronization, with the uclk.
-- The second flip-flop is used to remove metastabilities.
PoR_uclk_Synchronizer: process (uclk_i, rstpon_a_i)
begin
if rstpon_a_i = '0' then
s_u_por_synch <= (others => '1');
elsif rising_edge (uclk_i) then
s_u_por_synch <= s_u_por_synch(0) & '0';
end if;
end process;
---------------------------------------------------------------------------------------------------
-- RSTIN --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTIN FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- The FSM is following the "User Interface, General signal" RSTIN and checks whether it stays
-- active for at least 4 uclk cycles; if so, it enables the nanoFIP internal reset (s_rstin_nfip)
-- and the FIELDRIVE reset (s_rstin_fd). The nanoFIP internal reset stays active for 4 uclk cycles
-- and the FIELDRIVE for 4 FD_TXCK cycles.
-- The state machine can be reset by the Power On Reset and the variable reset.
-- Note: The same counter is used for the evaluation of the RSTIN (if it is >= 4 uclk) and for the
-- generation of the two reset signals.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process RSTIN_FSM_Sync: Storage of the current state of the FSM.
RSTIN_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por_synch(1) = '1' or rst_nfip_and_fd_p_i = '1' or s_rstin_c_is_full = '1' then
rstin_st <= IDLE;
else
rstin_st <= nx_rstin_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process RSTIN_FSM_Comb_State_Transitions: definition of the state
-- transitions of the FSM.
RSTIN_FSM_Comb_State_Transitions: process (rstin_st, s_rsti_synch(2), s_rstin_c_is_three,
s_rstin_c_is_seven, s_rstin_c_is_4txck)
begin
case rstin_st is
when IDLE =>
if s_rsti_synch(2) = '1' then -- RSTIN active
nx_rstin_st <= RSTIN_EVAL;
else
nx_rstin_st <= IDLE;
end if;
when RSTIN_EVAL =>
if s_rsti_synch(2) = '0' then -- RSTIN deactivated
nx_rstin_st <= IDLE;
else
if s_rstin_c_is_three = '1' then -- counting the uclk cycles that
nx_rstin_st <= nFIP_ON_FD_ON; -- RSTIN is active
else
nx_rstin_st <= RSTIN_EVAL;
end if;
end if;
when nFIP_ON_FD_ON =>
if s_rstin_c_is_seven = '1' then -- nanoFIP internal reset and
nx_rstin_st <= nFIP_OFF_FD_ON; -- FIELDRIVE reset active for
-- 4 uclk cycles
else
nx_rstin_st <= nFIP_ON_FD_ON;
end if;
when nFIP_OFF_FD_ON =>
-- nanoFIP internal reset deactivated
if s_rstin_c_is_4txck = '1' then -- FIELDRIVE reset continues being active
nx_rstin_st <= nFIP_OFF_FD_OFF;-- until 4 FD_TXCK cycles have passed
else
nx_rstin_st <= nFIP_OFF_FD_ON;
end if;
when nFIP_OFF_FD_OFF =>
if s_rsti_synch(2) = '1' then -- RSTIN still active
nx_rstin_st <= nFIP_OFF_FD_OFF;
else
nx_rstin_st <= IDLE;
end if;
when OTHERS =>
nx_rstin_st <= IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process RSTIN_FSM_Comb_Output_Signals: definition of the output signals of
-- the FSM. The process is handling the signals for the nanoFIP internal reset (s_rstin_nfip)
-- and the FIELDRIVE reset (s_rstin_fd), as well as the inputs of the RSTIN_free_counter.
RSTIN_FSM_Comb_Output_Signals: process (rstin_st)
begin
case rstin_st is
when IDLE =>
s_rstin_c_reinit <= '1'; -- counter initialized
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when RSTIN_EVAL =>
s_rstin_c_reinit <= '0'; -- counting until 4
-- if RSTIN is active
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when nFIP_ON_FD_ON =>
s_rstin_c_reinit <= '0'; -- free counter counting 4 uclk cycles
-------------------------------------
s_rstin_fd <= '1'; -- FIELDRIVE active
s_rstin_nfip <= '1'; -- nFIP internal active
-------------------------------------
when nFIP_OFF_FD_ON =>
s_rstin_c_reinit <= '0'; -- free counter counting until 4 FD_TXCK
s_rstin_nfip <= '0';
-------------------------------------
s_rstin_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when nFIP_OFF_FD_OFF =>
s_rstin_c_reinit <= '1'; -- no counting
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when OTHERS =>
s_rstin_c_reinit <= '1'; -- no counting
s_rstin_fd <= '0';
s_rstin_nfip <= '0';
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter: the counter counts from 0 to 4 FD_TXCK.
-- In case something goes wrong and the counter continues conting after the 4 FD_TXCK, the
-- s_rstin_c_is_full will be activated and the FSM will be reset.
RSTIN_free_counter: wf_incr_counter
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_rstin_c_reinit,
counter_incr_i => '1',
----------------------------------------
counter_is_full_o => s_rstin_c_is_full,
counter_o => s_rstin_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_rstin_c_is_three <= '1' when s_rstin_c = to_unsigned(3, s_rstin_c'length) else '0';
s_rstin_c_is_seven <= '1' when s_rstin_c = to_unsigned(7, s_rstin_c'length) else '0';
s_rstin_c_is_4txck <= '1' when s_rstin_c = s_txck_four_periods + 3 else '0';
-- +3 bc of the first 4 RSTIN evaluation cycles
---------------------------------------------------------------------------------------------------
-- var_rst --
---------------------------------------------------------------------------------------------------
-- Resets_after_a_var_rst FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- If after the reception of a var_rst the signal assert_rston_p_i is asserted, the FSM
-- asserts the "nanoFIP user Interface General signal" RSTON for 8 uclk cycles.
-- If after the reception of a var_rst the signal rst_nfip_and_fd_p_i is asserted, the FSM
-- asserts the nanoFIP internal reset (s_var_rst_nfip) for 4 uclk cycles and the
-- "nanoFIP FIELDRIVE" output (s_var_rst_fd) for 4 FD_TXCK cycles.
-- If after the reception of a var_rst both assert_rston_p_i and rst_nfip_and_fd_p_i
-- are asserted, the FSM asserts the s_var_rst_nfip for 2 uclk cycles, the RSTON for 8
-- uclk cycles and the s_var_rst_fd for 4 FD_TXCK cycles.
-- The same counter is used for all the countings!
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process Resets_after_a_var_rst_synch: Storage of the current state of the FSM
-- The state machine can be reset by the Power On Reset and the nanoFIP internal reset from RSTIN.
Resets_after_a_var_rst_synch: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por_synch(1) = '1' or s_rstin_nfip = '1' or s_var_rst_c_is_full = '1' then
var_rst_st <= VAR_RST_IDLE;
else
var_rst_st <= nx_var_rst_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Resets_after_a_var_rst_Comb_State_Transitions: definition of the
-- state transitions of the FSM.
Resets_after_a_var_rst_Comb_State_Transitions: process (var_rst_st, rst_nfip_and_fd_p_i,
assert_rston_p_i, s_var_rst_c_is_three,
s_var_rst_c_is_seven,
s_var_rst_c_is_4txck)
begin
case var_rst_st is
when VAR_RST_IDLE =>
if assert_rston_p_i = '1' and rst_nfip_and_fd_p_i = '1' then
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON_RSTON_ON;
elsif assert_rston_p_i = '1' then
nx_var_rst_st <= VAR_RST_RSTON_ON;
elsif rst_nfip_and_fd_p_i = '1' then
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON;
else
nx_var_rst_st <= VAR_RST_IDLE;
end if;
when VAR_RST_RSTON_ON => -- for 8 uclk cycles
if s_var_rst_c_is_seven = '1' then
nx_var_rst_st <= VAR_RST_IDLE;
else
nx_var_rst_st <= VAR_RST_RSTON_ON;
end if;
when VAR_RST_nFIP_ON_FD_ON_RSTON_ON => -- for 4 uclk cycles
if s_var_rst_c_is_three = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_ON;
else
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON_RSTON_ON;
end if;
when VAR_RST_nFIP_OFF_FD_ON_RSTON_ON => -- for 4 more uclk cycles
if s_var_rst_c_is_seven = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
else
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_ON;
end if;
when VAR_RST_nFIP_ON_FD_ON => -- for 4 uclk cycles
if s_var_rst_c_is_three = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
else
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON;
end if;
when VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF => -- until 4 TXCK
if s_var_rst_c_is_4txck = '1' then
nx_var_rst_st <= VAR_RST_IDLE;
else
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
end if;
when OTHERS =>
nx_var_rst_st <= VAR_RST_IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process RSTIN_FSM_Comb_Output_Signals: definition of the output signals of
-- the FSM. The process is managing the signals for the nanoFIP internal reset and the FIELDRIVE
-- reset, as well as the arguments of the counter.
rst_var_FSM_Comb_Output_Signals: process (var_rst_st)
begin
case var_rst_st is
when VAR_RST_IDLE =>
s_var_rst_c_reinit <= '1'; -- counter initialized
s_rston <= '1';
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
when VAR_RST_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 8 uclk cycles
-------------------------------------
s_rston <= '0'; -- RSTON active
-------------------------------------
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
when VAR_RST_nFIP_ON_FD_ON_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
-------------------------------------
s_rston <= '0'; -- RSTON active
s_var_rst_nfip <= '1'; -- nFIP internal active
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when VAR_RST_nFIP_OFF_FD_ON_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
s_var_rst_nfip <= '0';
-------------------------------------
s_rston <= '0'; -- RSTON active
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when VAR_RST_nFIP_ON_FD_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
s_rston <= '1';
-------------------------------------
s_var_rst_nfip <= '1'; -- nFIP internal active
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF =>
s_var_rst_c_reinit <= '0'; -- counting until 4 FD_TXCK cycles
s_rston <= '1';
s_var_rst_nfip <= '0';
-------------------------------------
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when OTHERS =>
s_var_rst_c_reinit <= '1'; -- no counting
s_rston <= '1';
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter:
-- the counter counts from 0 to 8, if only assert_RSTON_p has been activated, or
-- from 0 to 4 * FD_TXCK, if rst_nfip_and_fd_p_i has been activated.
-- In case something goes wrong and the counter continues conting after the 4 FD_TXCK, the
-- s_var_rst_c_is_full will be activated and the FSM will be reset.
free_counter: wf_incr_counter
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_var_rst_c_reinit,
counter_incr_i => '1',
----------------------------------------
counter_is_full_o => s_var_rst_c_is_full,
counter_o => s_var_rst_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_var_rst_c_is_seven <= '1' when s_var_rst_c = to_unsigned(7, s_var_rst_c'length) else '0';
s_var_rst_c_is_three <= '1' when s_var_rst_c = to_unsigned(3, s_var_rst_c'length) else '0';
s_var_rst_c_is_4txck <= '1' when s_var_rst_c = s_txck_four_periods -1 else '0';
---------------------------------------------------------------------------------------------------
-- Output Signals --
---------------------------------------------------------------------------------------------------
wb_rst_o <= rst_i or s_wb_por_synch(1);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
nfip_rst_o <= s_rstin_nfip or s_var_rst_nfip or s_u_por_synch(1);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Flip-flop with asynchronous reset to be sure that whenever nanoFIP is reset the user is not
RSTON_Buffering: process (uclk_i, s_u_por_synch(1), s_rstin_nfip, s_var_rst_nfip)
begin
if s_rstin_nfip = '1' or s_var_rst_nfip = '1' or s_u_por_synch(1) = '1' then
rston_o <= '1';
elsif rising_edge (uclk_i) then
rston_o <= s_rston;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FIELDRIVE reset
FD_RST_Buffering: process (uclk_i)
begin
if rising_edge (uclk_i) then
fd_rstn_o <= not (s_rstin_fd or s_var_rst_fd or s_u_por_synch(1));
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit | 370e3a728439d660437ac0ddef78786e | 0.33687 | 4.789859 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_no_fmul_area_estimation.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 4245c0a220d4c64585eb8f2763fe9a05 | 0.567707 | 3.729005 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/uart/uart_rx.vhdl | 3 | 3,702 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
--
-- Authors: Thomas B. Preusser
--
-- Module: uart_rx
--
-- Description: UART (RS232) Receiver: 1 Start + 8 Data + 1 Stop
-- ------------
--
-- License:
-- ===========================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity uart_rx is
generic (
SYNC_DEPTH : natural := 2 -- use zero for already clock-synchronous rx
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Bit Clock and RX Line
bclk_x8 : in std_logic; -- bit clock, eight strobes per bit length
rx : in std_logic;
-- Byte Stream Output
do : out std_logic_vector(7 downto 0);
stb : out std_logic
);
end uart_rx;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of uart_rx is
-- RX Synchronization
signal rxs : std_logic_vector(0 to SYNC_DEPTH) := (0 => 'Z', others => '1');
-- Buf Cnt Vld
-- Idle "---------0" X 0
-- Start "0111111111" 5->16 0 -- 1.5 bit length after start of start bit
-- Recv "dcba011111" 9->16 0 -- shifting left to right (LSB first)
-- Done "1hgfedcba0" X 1 -- Output Strobe
-- Data Buffer
signal Buf : std_logic_vector(9 downto 0) := (0 => '0', others => '-');
-- Bit Clock Counter: 8 ticks per bit
signal Cnt : unsigned(4 downto 0) := (others => '-');
-- Output Strobe
signal Vld : std_logic := '0';
begin
-- RX Synchronization, Synchronized Signal on rxs(SYNC_DEPTH)
rxs(0) <= rx;
genSyncFF: if SYNC_DEPTH > 0 generate
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
rxs(1 to SYNC_DEPTH) <= (others => '1');
else
rxs(1 to SYNC_DEPTH) <= rxs(0 to SYNC_DEPTH-1);
end if;
end if;
end process;
end generate genSyncFF;
-- Reception State
process(clk)
begin
if rising_edge(clk) then
Vld <= '0';
if rst = '1' then
Buf <= (0 => '0', others => '-');
Cnt <= (others => '-');
else
if Buf(0) = '0' then
-- Idle
if rxs(SYNC_DEPTH) = '0' then
-- Start Bit -> Receive Byte
Buf <= (Buf'left => '0', others => '1');
Cnt <= to_unsigned(5, Cnt'length);
else
Buf <= (0 => '0', others => '-');
Cnt <= (others => '-');
end if;
elsif bclk_x8 = '1' then
if Cnt(Cnt'left) = '1' then
Buf <= rxs(SYNC_DEPTH) & Buf(Buf'left downto 1);
Vld <= rxs(SYNC_DEPTH) and not Buf(1);
end if;
Cnt <= Cnt + (Cnt(4) & Cnt(4) & "001");
end if;
end if;
end if;
end process;
-- Outputs
do <= Buf(8 downto 1);
stb <= Vld;
end rtl;
| agpl-3.0 | 8369197e6429d95455debd1b5906d5fd | 0.540249 | 3.512334 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/ocram/ocram_sdp.vhdl | 2 | 5,084 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Thomas B. Preusser
-- Patrick Lehmann
--
-- Module: Simple dual-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating simple dual-port memory, with:
-- * dual clock, clock enable,
-- * 1 read port plus 1 write port.
--
-- The generalized behavior across Altera and Xilinx FPGAs since
-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:
--
-- The Altera M512/M4K TriMatrix memory (as found e.g. in Stratix and
-- Stratix II FPGAs) defines the minimum time after which the written data at
-- the write port can be read-out at read port again. As stated in the Stratix
-- Handbook, Volume 2, page 2-13, data is actually written with the falling
-- (instead of the rising) edge of the clock into the memory array. The write
-- itself takes the write-cycle time which is less or equal to the minimum
-- clock-period time. After this, the data can be read-out at the other port.
-- Consequently, data "d" written at the rising-edge of "wclk" at address
-- "wa" can be read-out at the read port from the same address with the
-- 2nd rising-edge of "rclk" following the falling-edge of "wclk".
-- If the rising-edge of "rclk" coincides with the falling-edge of "wclk"
-- (e.g. same clock signal), then it is counted as the 1st rising-edge of
-- "rclk" in this timing.
--
-- WARNING: The simulated behavior on RT-level is not correct.
--
-- TODO: add timing diagram
-- TODO: implement correct behavior for RT-level simulation
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ocram_sdp is
generic (
A_BITS : positive;
D_BITS : positive
);
port (
rclk : in std_logic; -- read clock
rce : in std_logic; -- read clock-enable
wclk : in std_logic; -- write clock
wce : in std_logic; -- write clock-enable
we : in std_logic; -- write enable
ra : in unsigned(A_BITS-1 downto 0); -- read address
wa : in unsigned(A_BITS-1 downto 0); -- write address
d : in std_logic_vector(D_BITS-1 downto 0); -- data in
q : out std_logic_vector(D_BITS-1 downto 0)); -- data out
end entity;
library PoC;
use PoC.config.all;
architecture rtl of ocram_sdp is
attribute ramstyle : string;
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA generate
-- RAM can be inferred correctly
-- Xilinx notes:
-- WRITE_MODE is set to WRITE_FIRST, but this also means that read data
-- is unknown on the opposite port. (As expected.)
-- Altera notes:
-- Setting attribute "ramstyle" to "no_rw_check" suppresses generation of
-- bypass logic, when 'clk1'='clk2' and 'ra' is feed from a register.
-- This is the expected behaviour.
-- With two different clocks, synthesis complains about an undefined
-- read-write behaviour, that can be ignored.
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
signal ram : ram_t;
attribute ramstyle of ram : signal is "no_rw_check";
begin
process (wclk)
begin
if rising_edge(wclk) then
if (wce and we) = '1' then
ram(to_integer(wa)) <= d;
end if;
end if;
end process;
process (rclk)
begin
if rising_edge(rclk) then
-- read data doesn't care, when reading at write address
if rce = '1' then
--synthesis translate_off
if Is_X(std_logic_vector(ra)) then
q <= (others => 'X');
else
--synthesis translate_on
q <= ram(to_integer(ra));
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end if;
end process;
end generate gInfer;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
| agpl-3.0 | fd8273abd0867a73f88a63b679ca772b | 0.626082 | 3.652299 | false | false | false | false |
malkadi/FGPU | RTL/CU.vhd | 1 | 10,854 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
---------------------------------------------------------------------------------------------------------}}}
entity compute_unit is
-- ports {{{
port(
clk : in std_logic;
cram_rdAddr : out unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0');
cram_rdAddr_conf : in unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0');
cram_rdData : in std_logic_vector(DATA_W-1 downto 0);
cram_rqst : out std_logic := '0';
start_addr : in unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0');
sch_rqst_n_wfs_m1 : in unsigned(N_WF_CU_W-1 downto 0);
wg_info : in unsigned(DATA_W-1 downto 0);
sch_rqst : in std_logic;
wf_active : out std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); -- active WFs in the CU
sch_ack : out std_logic := '0';
start_CUs : in std_logic := '0';
WGsDispatched : in std_logic := '0';
rtm_wrAddr_wg : in unsigned(RTM_ADDR_W-1 downto 0) := (others => '0');
rtm_wrData_wg : in unsigned(RTM_DATA_W-1 downto 0) := (others => '0');
rtm_we_wg : in std_logic := '0';
rdData_alu_en : in std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
rdAddr_alu_en : out unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0');
cache_rdData : in std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0) := (others=>'0');
cache_rdAck : in std_logic := '0';
cache_rdAddr : in unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0) := (others=>'0');
atomic_rdData : in std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
atomic_rdData_v : in std_logic := '0';
atomic_sgntr : in std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0');
gmem_wrData : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
gmem_valid : out std_logic := '0';
gmem_we : out std_logic_vector(DATA_W/8-1 downto 0) := (others=>'0');
gmem_rnw : out std_logic := '0';
gmem_atomic : out std_logic := '0';
gmem_atomic_sgntr : out std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0');
gmem_rqst_addr : out unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0');
gmem_ready : in std_logic := '0';
gmem_cntrl_idle : out std_logic := '0';
nrst : in std_logic
);
-- ports }}}
end compute_unit;
architecture Behavioral of compute_unit is
-- signals definitions {{{
signal nrst_scheduler : std_logic := '0';
signal nrst_mem_cntrl : std_logic := '0';
signal nrst_rtm : std_logic := '0';
signal rtm_wrAddr_cv : unsigned(N_WF_CU_W+2-1 downto 0) := (others => '0');
signal rtm_wrData_cv : unsigned(DATA_W-1 downto 0) := (others => '0');
signal rtm_we_cv : std_logic := '0';
signal rtm_rdAddr : unsigned(RTM_ADDR_W-1 downto 0) := (others => '0');
signal rtm_rdData : unsigned(RTM_DATA_W-1 downto 0) := (others => '0');
signal instr, instr_out : std_logic_vector(DATA_W-1 downto 0) := (others => '0');
signal wf_indx_in_wg, wf_indx : natural range 0 to N_WF_CU-1;
signal wf_indx_in_wg_out, wf_indx_out : natural range 0 to N_WF_CU-1;
signal phase, phase_out : unsigned(PHASE_W-1 downto 0) := (others=>'0');
signal alu_branch : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
signal wf_is_branching : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
signal alu_en_divStack : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
signal cv_gmem_re, cv_gmem_we : std_logic := '0';
signal cv_gmem_atomic : std_logic := '0';
signal cv_mem_wrData : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal cv_op_type : std_logic_vector(2 downto 0) := (others=>'0');
signal cv_lmem_rqst, cv_lmem_we : std_logic := '0';
signal cv_mem_addr : GMEM_ADDR_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal alu_en, alu_en_d0 : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
signal alu_en_pri_enc : integer range 0 to CV_SIZE-1 := 0;
signal cv_mem_rd_addr : unsigned(REG_FILE_W-1 downto 0) := (others=>'0');
signal regFile_wrAddr : unsigned(REG_FILE_W-1 downto 0) := (others=>'0');
signal regFile_wrData : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal regFile_we : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
signal regFile_we_lmem_p0 : std_logic := '0';
signal gmem_finish : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
attribute max_fanout of phase : signal is 10;
attribute max_fanout of wf_indx : signal is 10;
-- }}}
begin
-- RTM -------------------------------------------------------------------------------------- {{{
RTM_inst: entity RTM port map(
clk => clk,
rtm_rdAddr => rtm_rdAddr,
rtm_rdData => rtm_rdData,
rtm_wrData_cv => rtm_wrData_cv,
rtm_wrAddr_cv => rtm_wrAddr_cv,
rtm_we_cv => rtm_we_cv,
rtm_wrAddr_wg => rtm_wrAddr_wg,
rtm_wrData_wg => rtm_wrData_wg,
rtm_we_wg => rtm_we_wg,
WGsDispatched => WGsDispatched,
start_CUs => start_CUs,
nrst => nrst_rtm
);
------------------------------------------------------------------------------------------------}}}
-- CU WF Scheduler -----------------------------------------------------------------------------------{{{
CUS_inst: entity CU_scheduler
port map(
clk => clk,
wf_active => wf_active,
sch_ack => sch_ack,
sch_rqst => sch_rqst,
sch_rqst_n_wfs_m1 => sch_rqst_n_wfs_m1,
nrst => nrst_scheduler,
cram_rdAddr => cram_rdAddr,
cram_rdData => cram_rdData,
cram_rqst => cram_rqst,
cram_rdAddr_conf => cram_rdAddr_conf,
start_addr => start_addr,
wg_info => wg_info,
rtm_wrAddr_cv => rtm_wrAddr_cv,
rtm_wrData_cv => rtm_wrData_cv,
rtm_we_cv => rtm_we_cv,
alu_branch => alu_branch, -- level 10
wf_is_branching => wf_is_branching, -- level 10
alu_en => alu_en_d0, -- level 10
gmem_finish => gmem_finish,
instr => instr_out,
wf_indx_in_wg => wf_indx_in_wg_out,
wf_indx_in_CU => wf_indx_out,
alu_en_divStack => alu_en_divStack,
phase => phase_out
);
instr_slice_true: if INSTR_READ_SLICE generate
process(clk)
begin
if rising_edge(clk) then
nrst_scheduler <= nrst;
nrst_mem_cntrl <= nrst;
nrst_rtm <= nrst;
instr <= instr_out;
wf_indx_in_wg <= wf_indx_in_wg_out;
wf_indx <= wf_indx_out;
phase <= phase_out;
alu_en_d0 <= alu_en;
end if;
end process;
end generate;
instr_slice_false: if not INSTR_READ_SLICE generate
instr <= instr_out;
wf_indx_in_wg <= wf_indx_in_wg_out;
wf_indx <= wf_indx_out;
phase <= phase_out;
end generate;
------------------------------------------------------------------------------------------------}}}
-- CV --------------------------------------------------------------------------------------{{{
CV_inst: entity CV port map(
clk => clk,
instr => instr,
rdData_alu_en => rdData_alu_en,
rdAddr_alu_en => rdAddr_alu_en,
rtm_rdAddr => rtm_rdAddr, -- level 13.
rtm_rdData => rtm_rdData, -- level 15.
wf_indx => wf_indx,
wf_indx_in_wg => wf_indx_in_wg,
phase => phase,
alu_en => alu_en,
alu_en_pri_enc => alu_en_pri_enc,
alu_en_divStack => alu_en_divStack,
-- branch
alu_branch => alu_branch,
wf_is_branching => wf_is_branching,
gmem_re => cv_gmem_re,
gmem_atomic => cv_gmem_atomic,
gmem_we => cv_gmem_we,
mem_op_type => cv_op_type,
mem_addr => cv_mem_addr,
mem_rd_addr => cv_mem_rd_addr,
mem_wrData => cv_mem_wrData,
lmem_rqst => cv_lmem_rqst,
lmem_we => cv_lmem_we,
mem_regFile_wrAddr => regFile_wrAddr,
mem_regFile_wrData => regFile_wrData,
lmem_regFile_we_p0 => regFile_we_lmem_p0,
mem_regFile_we => regFile_we
);
------------------------------------------------------------------------------------------------}}}
-- CU mem controller -----------------------------------------------------------------{{{
CU_mem_cntrl_inst: entity CU_mem_cntrl
port map(
clk => clk,
cache_rdData => cache_rdData,
cache_rdAddr => cache_rdAddr,
cache_rdAck => cache_rdAck,
atomic_rdData => atomic_rdData,
atomic_rdData_v => atomic_rdData_v,
atomic_sgntr => atomic_sgntr,
cv_wrData => cv_mem_wrData,
cv_addr => cv_mem_addr,
cv_gmem_we => cv_gmem_we,
cv_gmem_re => cv_gmem_re,
cv_gmem_atomic => cv_gmem_atomic,
cv_lmem_rqst => cv_lmem_rqst,
cv_lmem_we => cv_lmem_we,
cv_op_type => cv_op_type,
cv_alu_en => alu_en,
cv_alu_en_pri_enc => alu_en_pri_enc,
cv_rd_addr => cv_mem_rd_addr,
gmem_wrData => gmem_wrData,
gmem_valid => gmem_valid,
gmem_ready => gmem_ready,
gmem_we => gmem_we,
gmem_atomic => gmem_atomic,
gmem_atomic_sgntr => gmem_atomic_sgntr,
gmem_rnw => gmem_rnw,
gmem_rqst_addr => gmem_rqst_addr,
regFile_wrAddr => regFile_wrAddr,
regFile_wrData => regFile_wrData,
regFile_we => regFile_we,
regFile_we_lmem_p0 => regFile_we_lmem_p0,
wf_finish => gmem_finish,
cntrl_idle => gmem_cntrl_idle,
nrst => nrst_mem_cntrl
);
------------------------------------------------------------------------------------------------}}}
end Behavioral;
| gpl-3.0 | 00f751a1729b535b0495eef1d83bb5be | 0.467662 | 3.577456 | false | false | false | false |
preusser/q27 | src/vhdl/queens/unframe.vhdl | 1 | 6,302 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity unframe is
generic (
SENTINEL : std_logic_vector(7 downto 0); -- Start Byte
PAY_LEN : positive
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dat : in std_logic_vector(7 downto 0);
rx_vld : in std_logic;
rx_got : out std_logic;
odat : out std_logic_vector(7 downto 0);
oeof : out std_logic;
oful : in std_logic;
oput : out std_logic;
ocommit : out std_logic;
orollback : out std_logic
);
end unframe;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
architecture rtl of unframe is
-- CRC Table for 0x1D5 (CRC-8)
type tFCS is array(0 to 255) of std_logic_vector(7 downto 0);
constant FCS : tFCS := (
x"00", x"D5", x"7F", x"AA", x"FE", x"2B", x"81", x"54",
x"29", x"FC", x"56", x"83", x"D7", x"02", x"A8", x"7D",
x"52", x"87", x"2D", x"F8", x"AC", x"79", x"D3", x"06",
x"7B", x"AE", x"04", x"D1", x"85", x"50", x"FA", x"2F",
x"A4", x"71", x"DB", x"0E", x"5A", x"8F", x"25", x"F0",
x"8D", x"58", x"F2", x"27", x"73", x"A6", x"0C", x"D9",
x"F6", x"23", x"89", x"5C", x"08", x"DD", x"77", x"A2",
x"DF", x"0A", x"A0", x"75", x"21", x"F4", x"5E", x"8B",
x"9D", x"48", x"E2", x"37", x"63", x"B6", x"1C", x"C9",
x"B4", x"61", x"CB", x"1E", x"4A", x"9F", x"35", x"E0",
x"CF", x"1A", x"B0", x"65", x"31", x"E4", x"4E", x"9B",
x"E6", x"33", x"99", x"4C", x"18", x"CD", x"67", x"B2",
x"39", x"EC", x"46", x"93", x"C7", x"12", x"B8", x"6D",
x"10", x"C5", x"6F", x"BA", x"EE", x"3B", x"91", x"44",
x"6B", x"BE", x"14", x"C1", x"95", x"40", x"EA", x"3F",
x"42", x"97", x"3D", x"E8", x"BC", x"69", x"C3", x"16",
x"EF", x"3A", x"90", x"45", x"11", x"C4", x"6E", x"BB",
x"C6", x"13", x"B9", x"6C", x"38", x"ED", x"47", x"92",
x"BD", x"68", x"C2", x"17", x"43", x"96", x"3C", x"E9",
x"94", x"41", x"EB", x"3E", x"6A", x"BF", x"15", x"C0",
x"4B", x"9E", x"34", x"E1", x"B5", x"60", x"CA", x"1F",
x"62", x"B7", x"1D", x"C8", x"9C", x"49", x"E3", x"36",
x"19", x"CC", x"66", x"B3", x"E7", x"32", x"98", x"4D",
x"30", x"E5", x"4F", x"9A", x"CE", x"1B", x"B1", x"64",
x"72", x"A7", x"0D", x"D8", x"8C", x"59", x"F3", x"26",
x"5B", x"8E", x"24", x"F1", x"A5", x"70", x"DA", x"0F",
x"20", x"F5", x"5F", x"8A", x"DE", x"0B", x"A1", x"74",
x"09", x"DC", x"76", x"A3", x"F7", x"22", x"88", x"5D",
x"D6", x"03", x"A9", x"7C", x"28", x"FD", x"57", x"82",
x"FF", x"2A", x"80", x"55", x"01", x"D4", x"7E", x"AB",
x"84", x"51", x"FB", x"2E", x"7A", x"AF", x"05", x"D0",
x"AD", x"78", x"D2", x"07", x"53", x"86", x"2C", x"F9"
);
-- State Machine
type tState is (Idle, Load, CheckCRC);
signal State : tState := Idle;
signal NextState : tState;
signal CRC : std_logic_vector(7 downto 0) := (others => '-');
signal Start : std_logic;
signal Append : std_logic;
signal Last : std_logic;
signal CRC_next : std_logic_vector(7 downto 0);
begin
-- State
CRC_next <= FCS(to_integer(unsigned(CRC xor rx_dat)));
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
CRC <= (others => '-');
else
State <= NextState;
if Start = '1' then
CRC <= FCS(255);
elsif Append = '1' then
CRC <= CRC_next;
end if;
end if;
end if;
end process;
process(State, rx_vld, rx_dat, oful, Last, CRC)
begin
NextState <= State;
Start <= '0';
Append <= '0';
odat <= (others => '-');
oeof <= Last;
oput <= '0';
ocommit <= '0';
orollback <= '0';
rx_got <= '0';
if rx_vld = '1' then
case State is
when Idle =>
rx_got <= '1';
if rx_dat = SENTINEL then
Start <= '1';
NextState <= Load;
end if;
when Load =>
if oful = '0' then
odat <= rx_dat;
oput <= '1';
rx_got <= '1';
Append <= '1';
if Last = '1' then
NextState <= CheckCRC;
end if;
end if;
when CheckCRC =>
rx_got <= '1';
if rx_dat = CRC then
ocommit <= '1';
else
orollback <= '1';
end if;
NextState <= Idle;
end case;
end if;
end process;
-- Payload Counter
genPayEq1: if PAY_LEN = 1 generate
Last <= '1';
end generate genPayEq1;
genPayGt1: if PAY_LEN > 1 generate
signal Cnt : unsigned(log2ceil(PAY_LEN-1) downto 0) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Cnt <= (others => '-');
else
if Start = '1' then
Cnt <= to_unsigned(PAY_LEN-2, Cnt'length);
elsif Append = '1' then
Cnt <= Cnt - 1;
end if;
end if;
end if;
end process;
Last <= Cnt(Cnt'left);
end generate genPayGt1;
end rtl;
| agpl-3.0 | d020645bb3c55768c3a13e38fc4554ba | 0.494446 | 2.71404 | false | false | false | false |
malkadi/FGPU | RTL/floating_point/fdiv.vhd | 1 | 10,489 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY fdiv IS
PORT (
aclk : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END fdiv;
ARCHITECTURE fdiv_arch OF fdiv IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fdiv_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 28,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END fdiv_arch;
| gpl-3.0 | 816237af6c7861b56478a5c51dfe4dbd | 0.628277 | 3.230366 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | d310987e1cb3d25c46786cc0c8f4944e | 0.567707 | 3.729005 | false | false | false | false |
jpidancet/mips | tests/rom.vhd | 1 | 1,395 | library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity rom is
generic (FILENAME : string;
DATA_WIDTH : integer;
ADDR_WIDTH : integer);
port (addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity rom;
architecture rtl of rom is
constant DEPTH : integer := 2**ADDR_WIDTH;
type mem_type is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
impure function init_mem(file_name : in string) return mem_type is
type file_type is file of character;
file f : file_type open read_mode is file_name;
variable ch : character;
variable m : mem_type;
begin
for i in 0 to DEPTH - 1 loop
for j in 0 to (DATA_WIDTH / 8) - 1 loop
if endfile(f) then
m(i)((((j + 1) * 8) - 1) downto (j * 8)) := "11111111";
else
read(f, ch);
m(i)((((j + 1) * 8) - 1) downto (j * 8)) :=
std_logic_vector(to_unsigned(character'pos(ch), 8));
end if;
end loop;
end loop;
return m;
end function;
constant mem : mem_type := init_mem(FILENAME);
begin
data <= mem(to_integer(unsigned(addr)));
end architecture rtl;
| isc | 61238ab1e67d0c302dba19688e49da1c | 0.549104 | 3.632813 | false | false | false | false |
malkadi/FGPU | RTL/global_mem.vhd | 1 | 71,074 | -- libraries -------------------------------------------------------------------------------------------{{{
library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all;
use ieee.numeric_std.ALL;
use ieee.math_real.all;
use ieee.math_complex.all;
library work;
use work.all;
use work.FGPU_definitions.all;
use work.FGPU_simulation_pkg.all;
use ieee.std_logic_textio.all;
use std.textio.all;
---------------------------------------------------------------------------------------------------------}}}
entity global_mem is
-- generics & ports {{{
generic(
MEM_PHY_ADDR_W : natural := 17;
ADDR_OFFSET : unsigned := X"1000_0000";
MAX_NDRANGE_SIZE : natural := 64*1024
);
port(
new_kernel : in std_logic;
finished_kernel : in std_logic;
size_0 : in natural;
size_1 : in natural;
target_offset_addr : in natural := 2**(N+L+M-1+2);
problemSize : in natural;
-- AXI Slave Interfaces
-- common signals
mx_arlen_awlen : in std_logic_vector(7 downto 0):= (others=>'0');
-- interface 0 {{{
-- ar channel
m0_araddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m0_arvalid : in std_logic := '0';
m0_arready : buffer std_logic := '0';
m0_arid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m0_rdata : out std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m0_rlast : out std_logic := '0';
m0_rvalid : buffer std_logic := '0';
m0_rready : in std_logic;
m0_rid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- aw channel
m0_awaddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m0_awvalid : in std_logic := '0';
m0_awready : buffer std_logic := '0';
m0_awid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m0_wdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m0_wstrb : in std_logic_vector(GMEM_DATA_W/8-1 downto 0):= (others=>'0');
m0_wlast : in std_logic := '0';
m0_wvalid : in std_logic := '0';
m0_wready : buffer std_logic := '0';
-- b channel
m0_bvalid : out std_logic := '0';
m0_bready : in std_logic := '0';
m0_bid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- }}}
-- interface 1 {{{
-- ar channel
m1_araddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m1_arvalid : in std_logic := '0';
m1_arready : buffer std_logic := '0';
m1_arid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m1_rdata : out std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m1_rlast : out std_logic := '0';
m1_rvalid : buffer std_logic := '0';
m1_rready : in std_logic;
m1_rid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- aw channel
m1_awaddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m1_awvalid : in std_logic := '0';
m1_awready : buffer std_logic := '0';
m1_awid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m1_wdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m1_wstrb : in std_logic_vector(GMEM_DATA_W/8-1 downto 0):= (others=>'0');
m1_wlast : in std_logic := '0';
m1_wvalid : in std_logic := '0';
m1_wready : buffer std_logic := '0';
-- b channel
m1_bvalid : out std_logic := '0';
m1_bready : in std_logic := '0';
m1_bid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- }}}
-- interface 2 {{{
-- ar channel
m2_araddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m2_arvalid : in std_logic := '0';
m2_arready : buffer std_logic := '0';
m2_arid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m2_rdata : out std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m2_rlast : out std_logic := '0';
m2_rvalid : buffer std_logic := '0';
m2_rready : in std_logic;
m2_rid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- aw channel
m2_awaddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m2_awvalid : in std_logic := '0';
m2_awready : buffer std_logic := '0';
m2_awid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m2_wdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m2_wstrb : in std_logic_vector(GMEM_DATA_W/8-1 downto 0):= (others=>'0');
m2_wlast : in std_logic := '0';
m2_wvalid : in std_logic := '0';
m2_wready : buffer std_logic := '0';
-- b channel
m2_bvalid : out std_logic := '0';
m2_bready : in std_logic := '0';
m2_bid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- }}}
-- interface 3 {{{
-- ar channel
m3_araddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m3_arvalid : in std_logic := '0';
m3_arready : buffer std_logic := '0';
m3_arid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m3_rdata : out std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m3_rlast : out std_logic := '0';
m3_rvalid : buffer std_logic := '0';
m3_rready : in std_logic;
m3_rid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- aw channel
m3_awaddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m3_awvalid : in std_logic := '0';
m3_awready : buffer std_logic := '0';
m3_awid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m3_wdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m3_wstrb : in std_logic_vector(GMEM_DATA_W/8-1 downto 0):= (others=>'0');
m3_wlast : in std_logic := '0';
m3_wvalid : in std_logic := '0';
m3_wready : buffer std_logic := '0';
-- b channel
m3_bvalid : out std_logic := '0';
m3_bready : in std_logic := '0';
m3_bid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- }}}
clk, nrst : in std_logic
);
-- }}}
end global_mem;
architecture Behavioral of global_mem is
-- constants & functions {{{
constant C_MEM_SIZE : integer := 2**MEM_PHY_ADDR_W;
CONSTANT MAX_DELAY : real := 20.0;
CONSTANT MIN_DELAY : integer := 10; -- delay = min + rand*max
CONSTANT IMPLEMENT_DELAY : boolean := false;
CONSTANT MAX_STEAM_PAUSE : real := 15.0;
CONSTANT IMPLEMENT_NO_STREAM_READ : boolean := false;
CONSTANT FILL_MODULO : natural := 49;
CONSTANT BVALID_DELAY_W : natural := 2;
type gmem_type is array (C_MEM_SIZE-1 downto 0) of std_logic_vector(GMEM_DATA_W-1 downto 0);
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is -- {{{
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end; -- }}}
function init_me_with_modulu(len: in integer; fill_modulo: in natural) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/32-1 loop
res(i)((j+1)*32-1 downto j*32) := std_logic_vector(to_unsigned((i*2+j) mod fill_modulo, 32));
end loop;
-- res(i)(31 downto 0) := std_logic_vector(to_unsigned(i, 32) );
-- res(i)(63 downto 32) := std_logic_vector(to_signed(-i, 32));
end loop;
return(res);
end; -- }}}
impure function init_mem_fft (size_0: in integer ) return gmem_type is -- {{{
variable res : gmem_type := (others=>(others=>'0'));
variable seed1, seed2 : positive := 1;
variable rand : real;
variable tmp_unsigned : unsigned(DATA_W-1 downto 0) := (others=>'0');
variable nStages, tmp_integer : integer;
variable tmp_std_logic : std_logic := '0';
variable li : line;
begin
nStages := 1;
tmp_integer := 1;
while tmp_integer < size_0 loop
tmp_integer := tmp_integer * 2;
nStages := nStages + 1;
end loop;
assert DATA_W*2 = GMEM_DATA_W;
-- write data with bit reverse
for i in 0 to 2*size_0-1 loop
tmp_unsigned := to_unsigned(i, 32);
for m in 0 to nStages/2 loop
tmp_std_logic := tmp_unsigned(nStages-1-m);
tmp_unsigned(nStages-1-m) := tmp_unsigned(m);
tmp_unsigned(m) := tmp_std_logic;
end loop;
res(to_integer(tmp_unsigned))(DATA_W-1 downto 0) := to_slv(to_float(i mod 4)); -- real part
res(to_integer(tmp_unsigned))(2*DATA_W-1 downto DATA_W) := (others=>'0'); -- imaginary part
end loop;
-- for i in 0 to 7 loop
-- write(li, to_real(to_float(res(i)(DATA_W-1 downto 0))));
-- swrite(li, " +j ");
-- write(li, to_real(to_float(res(i)(2*DATA_W-1 downto DATA_W))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
-- write twiddles
for i in 0 to 2*size_0-1 loop
-- res(C_MEM_SIZE/2 + i)(DATA_W-1 downto 0) := to_slv(to_float(cos(to_real(MATH_PI*i/to_real(size_0)))));
res(C_MEM_SIZE/4 + i)(DATA_W-1 downto 0) := to_slv(to_float(cos(real(MATH_PI*real(i)/real(size_0)))));
res(C_MEM_SIZE/4 + i)(2*DATA_W-1 downto DATA_W) := to_slv(-to_float(sin(real(MATH_PI*real(i)/real(size_0)))));
end loop;
-- for i in 0 to 7 loop
-- write(li, to_real(to_float(res(C_MEM_SIZE/4+i)(DATA_W-1 downto 0))));
-- swrite(li, " +j ");
-- write(li, to_real(to_float(res(C_MEM_SIZE/4+i)(2*DATA_W-1 downto DATA_W))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
return(res);
end; -- }}}
function init_mem_floydwarshall (len: in integer) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
variable seed1, seed2 : positive := 1;
variable rand : real;
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/DATA_W-1 loop
uniform(seed1, seed2, rand);
res(i)((j+1)*DATA_W-1 downto j*DATA_W) := to_slv(to_float(rand*10.0));
if i = j then
res(i)((j+1)*DATA_W-1 downto j*DATA_W) := (others=>'0');
end if;
end loop;
end loop;
return(res);
end; -- }}}
function init_mem_rand_float (len: in integer; data_width: in integer) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
variable seed1, seed2 : positive := 1;
variable rand : real;
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/data_width-1 loop
uniform(seed1, seed2, rand);
res(i)((j+1)*data_width-1 downto j*data_width) := to_slv(to_float(rand));
end loop;
end loop;
return(res);
end; -- }}}
function init_mem_rand (len: in integer; data_width: in integer) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
variable tmp_integer : integer;
variable tmp_unsigned : unsigned(DATA_W-1 downto 0) := (others=>'0');
variable seed1, seed2 : positive := 1;
variable rand : real;
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/data_width-1 loop
uniform(seed1, seed2, rand);
rand := rand * 1024.0 * 1024.0 * 1024.0 * 2.0;
tmp_integer := integer(rand);
tmp_unsigned := to_unsigned(tmp_integer, DATA_W);
res(i)((j+1)*data_width-1 downto j*data_width) := std_logic_vector(tmp_unsigned(data_width-1 downto 0));
end loop;
end loop;
return(res);
end; -- }}}
function init_mem_float (len: in integer) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
variable tmp_unsigned : unsigned(DATA_W-1 downto 0) := (others=>'0');
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/DATA_W-1 loop
tmp_unsigned := to_unsigned(GMEM_DATA_W/DATA_W*i+j, DATA_W);
res(i)((j+1)*DATA_W-1 downto j*DATA_W) := std_logic_vector(to_float(tmp_unsigned));
end loop;
end loop;
return(res);
end; --}}}
function init_mem (len: in integer; data_width: in integer) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
variable tmp_unsigned : unsigned(DATA_W-1 downto 0) := (others=>'0');
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/data_width-1 loop
tmp_unsigned := to_unsigned(GMEM_DATA_W/data_width*i+j, DATA_W);
res(i)((j+1)*data_width-1 downto j*data_width) := std_logic_vector(tmp_unsigned(data_width-1 downto 0));
end loop;
end loop;
return(res);
end; --}}}
--}}}
-- read & write addresses {{{
signal gmem: gmem_type := init_mem(C_MEM_SIZE/2, DATA_W);
signal tmp_gmem : SLV32_ARRAY(0 to 2**16-1) := (others=>(others=>'0'));
type mem_phy_addr_array is array(natural range <>) of unsigned(MEM_PHY_ADDR_W-1 downto 0);
signal wr_addr : gmem_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
type gmem_addr_2d_array is array(natural range <>, natural range <>) of unsigned(GMEM_ADDR_W-1 downto 0);
signal wr_addr_offset : mem_phy_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal written_count : integer := 0;
signal written_addrs : std_logic_vector(MAX_NDRANGE_SIZE-1 downto 0) := (others=>'0');
signal new_kernel_d0, new_kernel_d1 : std_logic := '0';
-- }}}
-- other signals {{{
signal delay : nat_2d_array(N_AXI-1 downto 0, N_WR_FIFOS_AXI-1 downto 0) := (others=>(others=>0));
-- }}}
-- alias signals {{{
signal wvalid, wready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal wdata, rdata : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal wstrb : gmem_be_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal awready, awvalid : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal arready, arvalid : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal rready, rvalid, rlast : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal bvalid, bready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal araddr, awaddr : gmem_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal arid, rid, awid, bid : id_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal wlast : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
-- }}}
-- read multiplexing {{{
type st_reader_type is (idle, delay_before_read, send_data);
type st_reader_array is array (natural range <>, natural range<>) of st_reader_type;
-- }}}
-- write signals {{{
constant c_awaddr_fifo_capacity_w : natural := 3;
constant c_awaddr_fifo_capacity : natural := 2**c_awaddr_fifo_capacity_w;
-- awaddr fifo
type awaddr_fifo_array is array(natural range <>) of gmem_addr_array(c_awaddr_fifo_capacity-1 downto 0);
signal awaddr_fifo : awaddr_fifo_array(N_AXI-1 downto 0) := (others=>(others=>(others=>'0')));
type awaddr_fifo_addr_vec is array(natural range <>) of unsigned(c_awaddr_fifo_capacity_w-1 downto 0);
signal awaddr_fifo_wrAddr : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal awaddr_fifo_rdAddr : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal awaddr_fifo_nempty : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal awaddr_fifo_full : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal awaddr_fifo_pop, awaddr_fifo_push: std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
-- awid fifo
type awid_fifo_array is array(natural range <>) of id_array(max(1, 2**BVALID_DELAY_W/2**BURST_W)*c_awaddr_fifo_capacity-1 downto 0);
signal awid_fifo : awid_fifo_array(N_AXI-1 downto 0) := (others=>(others=>(others=>'0')));
type awid_fifo_addr_array is array( natural range <>) of unsigned(c_awaddr_fifo_capacity_w+max(BVALID_DELAY_W-BURST_W, 0)-1 downto 0);
signal awid_fifo_rdAddr : awid_fifo_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal awid_fifo_wrAddr : awid_fifo_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
type st_write_type is (get_address, write);
type st_write_array is array (natural range <>) of st_write_type;
signal st_write : st_write_array(N_AXI-1 downto 0) := (others=>get_address);
-- write pipe for delaying bvalid
type wdata_vec_type is array (natural range <>) of gmem_word_array(N_AXI-1 downto 0);
signal wdata_vec : wdata_vec_type(2**BVALID_DELAY_W-1 downto 0) := (others=>(others=>(others=>'0')));
type wstrb_vec_type is array(natural range <>) of gmem_be_array(N_AXI-1 downto 0);
signal wstrb_vec : wstrb_vec_type(2**BVALID_DELAY_W-1 downto 0) := (others=>(others=>(others=>'0')));
type wlast_vec_type is array(natural range <>) of std_logic_vector(N_AXI-1 downto 0);
signal wlast_vec, wvalid_vec : wlast_vec_type(2**BVALID_DELAY_W-1 downto 0) := (others=>(others=>'0'));
type wr_addr_offset_vec_type is array(natural range <>) of mem_phy_addr_array(N_AXI-1 downto 0);
signal wr_addr_offset_vec : wr_addr_offset_vec_type(2**BVALID_DELAY_W-1 downto 0) := (others=>(others=>(others=>'0')));
--}}}
begin
-- alias signals ---------------------------------------------------------------------------------------{{{
wvalid(0) <= m0_wvalid;
wdata(0) <= m0_wdata;
wstrb(0) <= m0_wstrb;
wlast(0) <= m0_wlast;
m0_wready <= wready(0);
m0_awready <= awready(0);
awvalid(0) <= m0_awvalid;
awaddr(0) <= unsigned(m0_awaddr);
araddr(0) <= unsigned(m0_araddr);
m0_arready <= arready(0);
arvalid(0) <= m0_arvalid;
arid(0) <= m0_arid;
rready(0) <= m0_rready;
m0_rvalid <= rvalid(0);
m0_rid <= rid(0);
awid(0) <= m0_awid;
m0_bid <= bid(0);
m0_rdata <= rdata(0);
m0_rlast <= rlast(0);
m0_bvalid <= bvalid(0);
bready(0) <= m0_bready;
MORE_THAN_1_W_AXI : if N_AXI > 1 generate
begin
wvalid(1) <= m1_wvalid;
wdata(1) <= m1_wdata;
wstrb(1) <= m1_wstrb;
wlast(1) <= m1_wlast;
m1_wready <= wready(1);
m1_awready <= awready(1);
awaddr(1) <= unsigned(m1_awaddr);
araddr(1) <= unsigned(m1_araddr);
awvalid(1) <= m1_awvalid;
m1_arready <= arready(1);
arvalid(1) <= m1_arvalid;
arid(1) <= m1_arid;
rready(1) <= m1_rready;
m1_rvalid <= rvalid(1);
m1_rid <= rid(1);
awid(1) <= m1_awid;
m1_bid <= bid(1);
m1_rdata <= rdata(1);
m1_rlast <= rlast(1);
m1_bvalid <= bvalid(1);
bready(1) <= m1_bready;
end generate;
MORE_THAN_2_W_AXI: if N_AXI > 2 generate
begin
wvalid(2) <= m2_wvalid;
wdata(2) <= m2_wdata;
wstrb(2) <= m2_wstrb;
wlast(2) <= m2_wlast;
m2_wready <= wready(2);
m2_awready <= awready(2);
awvalid(2) <= m2_awvalid;
awaddr(2) <= unsigned(m2_awaddr);
araddr(2) <= unsigned(m2_araddr);
m2_arready <= arready(2);
arvalid(2) <= m2_arvalid;
arid(2) <= m2_arid;
awid(2) <= m2_awid;
m2_bid <= bid(2);
rready(2) <= m2_rready;
m2_rvalid <= rvalid(2);
m2_rid <= rid(2);
m2_rdata <= rdata(2);
m2_rlast <= rlast(2);
m2_bvalid <= bvalid(2);
bready(2) <= m2_bready;
end generate;
MORE_THAN_3_W_AXI : if N_AXI > 3 generate
begin
wvalid(3) <= m3_wvalid;
wdata(3) <= m3_wdata;
wstrb(3) <= m3_wstrb;
wlast(3) <= m3_wlast;
m3_wready <= wready(3);
m3_awready <= awready(3);
awvalid(3) <= m3_awvalid;
awaddr(3) <= unsigned(m3_awaddr);
araddr(3) <= unsigned(m3_araddr);
m3_arready <= arready(3);
arvalid(3) <= m3_arvalid;
arid(3) <= m3_arid;
awid(3) <= m3_awid;
m3_bid <= bid(3);
rready(3) <= m3_rready;
m3_rvalid <= rvalid(3);
m3_rid <= rid(3);
m3_rdata <= rdata(3);
m3_rlast <= rlast(3);
m3_bvalid <= bvalid(3);
bready(3) <= m3_bready;
end generate;
---------------------------------------------------------------------------------------------------------}}}
-- mem module -------------------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
for j in 0 to N_AXI-1 loop
if wvalid_vec(0)(j) = '1' and wready(j) = '1' then
for i in 0 to GMEM_DATA_W/8-1 loop
if wstrb_vec(0)(j)(i) = '1' then
gmem(to_integer(wr_addr_offset_vec(0)(j)))((i+1)*8-1 downto i*8) <= wdata_vec(0)(j)((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end loop;
if new_kernel = '1' then
if kernel_name = mat_mul or kernel_name = xcorr then
gmem <= init_me_with_modulu(C_MEM_SIZE/2, FILL_MODULO);
elsif kernel_name = fadd or kernel_name = add_float or kernel_name = mul_float or kernel_name = median or kernel_name = max_half_atomic then
gmem <= init_mem_rand(C_MEM_SIZE/2, 32);
elsif kernel_name = floydwarshall then
gmem <= init_mem_floydwarshall(C_MEM_SIZE/2);
elsif kernel_name = fft_hard then
gmem <= init_mem_fft(size_0);
elsif kernel_name = fir_char4 then
gmem <= init_mem(C_MEM_SIZE/2, 8);
elsif kernel_name = parallelSelection then
gmem <= init_mem_float(C_MEM_SIZE/2);
-- elsif kernel_name = ludecompose then
-- gmem <= init_mem_rand(C_MEM_SIZE/2, 32);
-- -- gmem(0)(DATA_W-1 downto 0) <= to_slv(to_float(121));
-- -- gmem(0)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(68));
-- -- gmem(1)(DATA_W-1 downto 0) <= to_slv(to_float(30));
-- -- gmem(1)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(73));
-- -- gmem(2)(DATA_W-1 downto 0) <= to_slv(to_float(109));
-- -- gmem(2)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(94));
-- -- gmem(3)(DATA_W-1 downto 0) <= to_slv(to_float(62));
-- -- gmem(3)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(31));
-- -- gmem(4)(DATA_W-1 downto 0) <= to_slv(to_float(113));
-- -- gmem(4)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(5));
-- -- gmem(5)(DATA_W-1 downto 0) <= to_slv(to_float(27));
-- -- gmem(5)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(106));
-- -- gmem(6)(DATA_W-1 downto 0) <= to_slv(to_float(33));
-- -- gmem(6)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(6));
-- -- gmem(7)(DATA_W-1 downto 0) <= to_slv(to_float(86));
-- -- gmem(7)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(92));
else
gmem <= init_mem(C_MEM_SIZE/2, 32);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- read control -------------------------------------------------------------------------------------------{{{
read_fsms: process(clk)
variable seed1, seed2 : positive := 1;
variable rand : real;
variable rdAddr, wrAddr : gmem_addr_2d_array(N_AXI-1 downto 0, N_WR_FIFOS_AXI-1 downto 0) := (others=>(others=>(others=>'0')));
variable st_reader : st_reader_array(N_AXI-1 downto 0, N_WR_FIFOS_AXI-1 downto 0) := (others=>(others=>idle));
variable rlen : nat_2d_array(N_AXI-1 downto 0, N_WR_FIFOS_AXI-1 downto 0) := (others=>(others=>0));
begin
if rising_edge(clk) then
if nrst = '0' then
else
for i in 0 to N_AXI-1 loop
arready(i) <= '0';
rvalid(i) <= '0';
rlast(i) <= '0';
-- id readers
for j in 0 to N_WR_FIFOS_AXI-1 loop
case st_reader(i, j) is
when idle =>
if arvalid(i) = '1' and arready(i) = '0' and to_integer(unsigned(arid(i))) = j then
arready(i) <= '1';
rdAddr(i, j) := unsigned(araddr(i)) - ADDR_OFFSET;
rlen(i, j) := to_integer(unsigned(mx_arlen_awlen));
if IMPLEMENT_DELAY then
st_reader(i, j) := delay_before_read;
uniform(seed1, seed2, rand);
delay(i, j) <= MIN_DELAY + integer(rand*MAX_DELAY);
else
st_reader(i, j) := send_data;
end if;
end if;
when delay_before_read =>
if delay(i,j) /= 0 then
delay(i, j) <= delay(i, j) - 1;
else
st_reader(i, j) := send_data;
end if;
when send_data =>
if to_integer(unsigned(rid(i))) = j and rvalid(i) = '1' and rready(i) = '1' then
rdAddr(i, j) := rdAddr(i, j) + 8;
if rlen(i, j) = 0 then
st_reader(i, j) := idle;
else
rlen(i, j) := rlen(i, j) - 1;
if IMPLEMENT_NO_STREAM_READ then
uniform(seed1, seed2, rand);
if rand < 0.5 then
uniform(seed1, seed2, rand);
delay(i, j) <= integer(rand*MAX_STEAM_PAUSE);
st_reader(i, j) := delay_before_read;
end if;
end if;
end if;
end if;
end case;
end loop;
for j in 0 to N_WR_FIFOS_AXI-1 loop
if st_reader(i, j) = send_data then
rvalid(i) <= '1';
rdata(i) <= gmem(to_integer(rdAddr(i, j)(MEM_PHY_ADDR_W+2+GMEM_N_BANK_W-1 downto 2+GMEM_N_BANK_W)));
rid(i) <= std_logic_vector(to_unsigned(j, ID_WIDTH));
if rlen(i, j) = 0 then
rlast(i) <= '1';
end if;
exit;
end if;
end loop;
end loop;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- write control -------------------------------------------------------------------------------------------{{{
wr_addr_offset_alias: for i in 0 to N_AXI-1 generate
begin
wr_addr_offset(i) <= wr_addr(i)(MEM_PHY_ADDR_W+2+GMEM_N_BANK_W-1 downto 2+GMEM_N_BANK_W);
end generate;
awready <= not awaddr_fifo_full;
awaddr_fifo_push <= awvalid and awready;
process(clk)
variable pop_awaddr: std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
variable seed1, seed2 : positive := 1;
variable rand : real;
variable bid_wait_cycles : natural := 0;
begin
if rising_edge(clk) then
if nrst = '0' then
awaddr_fifo_wrAddr <= (others=>(others=>'0'));
awaddr_fifo_rdAddr <= (others=>(others=>'0'));
st_write <= (others=> get_address);
awaddr_fifo_nempty <= (others=>'0');
awaddr_fifo_full <= (others=>'0');
awaddr_fifo_pop <= (others=>'0');
awid_fifo_rdAddr <= (others=>(others=>'0'));
awid_fifo_wrAddr <= (others=>(others=>'0'));
else
wready <= (others=>'1');
wdata_vec(wdata_vec'high) <= wdata;
wdata_vec(wdata_vec'high-1 downto 0) <= wdata_vec(wdata_vec'high downto 1);
wlast_vec(wlast_vec'high-1 downto 0) <= wlast_vec(wlast_vec'high downto 1);
for i in 0 to N_AXI-1 loop
wlast_vec(wlast_vec'high)(i) <= '0';
if wlast(i) = '1' then
while true loop
uniform(seed1, seed2, rand);
bid_wait_cycles := integer(rand*real(2**BVALID_DELAY_W));
if bid_wait_cycles > 2**BVALID_DELAY_W-2 then
bid_wait_cycles := 2**BVALID_DELAY_W-2;
end if;
-- if bid_wait_cycles = 0 then
-- bid_wait_cycles := 1;
-- end if;
-- report "bid_wait_cycles = " & integer'image(bid_wait_cycles);
if wlast_vec(bid_wait_cycles+1)(i) = '0' then
wlast_vec(bid_wait_cycles)(i) <= '1';
exit;
else
-- report "setting wlast failed";
end if;
end loop;
end if;
end loop;
wvalid_vec(wvalid_vec'high) <= wvalid;
wvalid_vec(wvalid_vec'high-1 downto 0) <= wvalid_vec(wvalid_vec'high downto 1);
wstrb_vec(wstrb_vec'high) <= wstrb;
wstrb_vec(wstrb_vec'high-1 downto 0) <= wstrb_vec(wstrb_vec'high downto 1);
wr_addr_offset_vec(wr_addr_offset_vec'high) <= wr_addr_offset;
wr_addr_offset_vec(wr_addr_offset_vec'high-1 downto 0) <= wr_addr_offset_vec(wr_addr_offset_vec'high downto 1);
for i in 0 to N_AXI-1 loop
if wlast_vec(0)(i) = '1' then
bvalid(i) <= '1';
bid(i) <= awid_fifo(i)(to_integer(awid_fifo_rdAddr(i)));
awid_fifo_rdAddr(i) <= awid_fifo_rdAddr(i) + 1;
elsif bready(i) = '1' then
bvalid(i) <= '0';
end if;
pop_awaddr(i) := '0';
awaddr_fifo_pop(i) <= '0';
case st_write(i) is
when get_address =>
if awaddr_fifo_nempty(i) = '1' then
awaddr_fifo_pop(i) <= '1';
pop_awaddr(i) := '1';
wr_addr(i) <= awaddr_fifo(i)(to_integer(awaddr_fifo_rdAddr(i))) - ADDR_OFFSET;
awaddr_fifo_rdAddr(i) <= awaddr_fifo_rdAddr(i) + 1;
st_write(i) <= write;
end if;
when write =>
if wvalid(i) = '1' and wready(i) = '1' then
wr_addr(i) <= wr_addr(i) + 8;
if wlast(i) = '1' then
if awaddr_fifo_nempty(i) = '1' then
awaddr_fifo_pop(i) <= '1';
pop_awaddr(i) := '1';
wr_addr(i) <= awaddr_fifo(i)(to_integer(awaddr_fifo_rdAddr(i))) - ADDR_OFFSET;
awaddr_fifo_rdAddr(i) <= awaddr_fifo_rdAddr(i) + 1;
st_write(i) <= write;
else
st_write(i) <= get_address;
end if;
end if;
end if;
end case;
if awaddr_fifo_push(i) = '1' then
-- if to_integer(unsigned(awaddr(i)(17 downto 0))) = 3712 then
-- report "heeere";
-- end if;
awaddr_fifo(i)(to_integer(awaddr_fifo_wrAddr(i))) <= unsigned(awaddr(i));
awaddr_fifo_wrAddr(i) <= awaddr_fifo_wrAddr(i) + 1;
awid_fifo(i)(to_integer(awid_fifo_wrAddr(i))) <= awid(i);
awid_fifo_wrAddr(i) <= awid_fifo_wrAddr(i) + 1;
end if;
if awaddr_fifo_push(i) = '1' and pop_awaddr(i) = '0' and awaddr_fifo_wrAddr(i)+1 = awaddr_fifo_rdAddr(i) then
awaddr_fifo_full(i) <= '1';
elsif awaddr_fifo_push(i) = '0' and pop_awaddr(i) = '1' then
awaddr_fifo_full(i) <= '0';
end if;
if awaddr_fifo_push(i) = '1' and pop_awaddr(i) = '0' then
awaddr_fifo_nempty(i) <= '1';
elsif awaddr_fifo_push(i) = '0' and pop_awaddr(i) = '1' and awaddr_fifo_rdAddr(i)+1 = awaddr_fifo_wrAddr(i) then
awaddr_fifo_nempty(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------}}}
-- test process -------------------------------------------------------------------------------------------{{{
test_process: process(clk)
-- test procedures {{{
-- variables {{{
variable wr_addr_int : integer := 0;
variable li : line;
variable offset : integer := 16#0008_0000#;
variable stride : natural := 65;
variable written_count_tmp : integer := 0;
type SLV16_ARRAY is array (natural range <>) of std_logic_vector(15 downto 0);
type SLV8_ARRAY is array(natural range <>) of std_logic_vector(7 downto 0);
variable must_data_word : SLV32_ARRAY(1 downto 0) := (others=>(others=>'0'));
variable must_data_half : SLV16_ARRAY(3 downto 0) := (others=>(others=>'0'));
variable must_data_byte : SLV8_ARRAY(7 downto 0) := (others=>(others=>'0'));
variable must_data : std_logic_vector(GMEM_DATA_W-1 downto 0) := (others=>'0');
variable word_addr, second_word_addr : natural := 0;
variable byte_addr : natural := 0;
variable half_addr : natural := 0;
variable tmp_signed : signed(DATA_W-1 downto 0) := (others=>'0');
variable tmp_unsigned_64 : unsigned(GMEM_DATA_W-1 downto 0) := (others=>'0');
variable tmp_unsigned : unsigned(DATA_W-1 downto 0) := (others=>'0');
variable tmp_integer : integer;
variable tmp_float : float32 := to_float(0);
variable tmp_std_logic : std_logic := '0';
variable rowIndx, colIndx, res, k : natural := 0;
variable p00, p01, p02, p10, p11, p12, p20, p21, p22 : unsigned(DATA_W-1 downto 0) := (others=>'0');
variable nStages, stageIndx, pairDistance, blockWidth, leftIndx, rightIndx: integer := 0;
variable leftElement, rightElement, greater, lesser : unsigned(DATA_W-1 downto 0) := (others=>'0');
variable leftElement_float, rightElement_float, greater_float, lesser_float : float32 := to_float(0);
variable twiddle, a, b, res_a, res_b : complex;
variable passIndx, sameDirectionBlock : integer := 0;
variable nGroups, groupOffset : integer := 0;
variable x1, y1, z1, m1, x2, y2, z2, m2 : float32 := to_float(0);
variable xdiff, ydiff, zdiff, distSquared : float32 := to_float(0);
variable accx, accy, accz, invDist, invDistCube, s : float32 := to_float(0);
variable oldVelx, oldVely, oldVelz, newVelx, newVely, newVelz : float32 := to_float(0);
variable softeningFactor : float32 := to_float(500); -- don't change (fixed in sch_ram.xml)
variable deltaTime : float32 := to_float(0.005); -- don't change (fixed in sch_ram.xml)
-- }}}
procedure ludecompose_round is
begin
end procedure;
procedure fft_round is -- {{{
begin
for i in 0 to size_0-1 loop
pairDistance := 2**stageIndx;
blockWidth := 2 * pairDistance;
nGroups := size_0/pairDistance;
groupOffset := to_integer(to_unsigned(i, 32) and to_unsigned(pairDistance-1, 32));
leftIndx := groupOffset + (i/pairDistance)*blockWidth;
rightIndx := leftIndx + pairDistance;
a.re := to_real(to_float(tmp_gmem(2*leftIndx)));
a.im := to_real(to_float(tmp_gmem(2*leftIndx+1)));
b.re := to_real(to_float(tmp_gmem(2*rightIndx)));
b.im := to_real(to_float(tmp_gmem(2*rightIndx+1)));
-- swrite(li, "a = ");
-- write(li, a.re);
-- swrite(li, " +j ");
-- write(li, a.im);
-- swrite(li, ", b = ");
-- write(li, b.re);
-- swrite(li, " +j ");
-- write(li, b.im);
-- write(li, LF);
twiddle.re := to_real(to_float(gmem(C_MEM_SIZE/4+nGroups*groupOffset)(DATA_W-1 downto 0)));
twiddle.im := to_real(to_float(gmem(C_MEM_SIZE/4+nGroups*groupOffset)(2*DATA_W-1 downto DATA_W)));
res_a := a+twiddle*b;
res_b := a-twiddle*b;
-- swrite(li, "res_a = ");
-- write(li, res_a.re);
-- swrite(li, " +j ");
-- write(li, res_a.im);
-- swrite(li, ", res_b = ");
-- write(li, res_b.re);
-- swrite(li, " +j ");
-- write(li, res_b.im);
-- write(li, LF);
tmp_gmem(2*leftIndx) <= to_slv(to_float(res_a.re));
tmp_gmem(2*leftIndx+1) <= to_slv(to_float(res_a.im));
tmp_gmem(2*rightIndx) <= to_slv(to_float(res_b.re));
tmp_gmem(2*rightIndx+1) <= to_slv(to_float(res_b.im));
end loop;
-- report "fft round is executed";
-- for i in 0 to 7 loop
-- write(li, to_real(to_float(tmp_gmem(2*i))));
-- swrite(li, " +j ");
-- write(li, to_real(to_float(tmp_gmem(2*i+1))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
end procedure; -- }}}
procedure bitonic_float_round is -- {{{
begin
sameDirectionBlock := 2**(stageIndx);
-- report "bitonic round excutes with stageIndx = " & integer'image(stageIndx) & " and passIndx = " & integer'image(passIndx);
for i in 0 to size_0-1 loop
pairDistance := 2**(stageIndx-passIndx);
blockWidth := 2 * pairDistance;
leftIndx := (i mod pairDistance) + (i/pairDistance)*blockWidth;
rightIndx := leftIndx + pairDistance;
leftElement_float := to_float(tmp_gmem(leftIndx));
rightElement_float := to_float(tmp_gmem(rightIndx));
if gt(leftElement_float, rightElement_float) then
greater_float := leftElement_float;
lesser_float := rightElement_float;
else
greater_float := rightElement_float;
lesser_float := leftElement_float;
end if;
if (i/sameDirectionBlock) mod 2 /= 1 then
leftElement_float := greater_float;
rightElement_float := lesser_float;
else
leftElement_float := lesser_float;
rightElement_float := greater_float;
end if;
tmp_gmem(leftIndx) <= to_slv(leftElement_float);
tmp_gmem(rightIndx) <= to_slv(rightElement_float);
end loop;
-- report "bitonic round is executed";
end procedure; -- }}}
procedure bitonic_round is -- {{{
begin
sameDirectionBlock := 2**(stageIndx);
-- report "bitonic round excutes with stageIndx = " & integer'image(stageIndx) & " and passIndx = " & integer'image(passIndx);
for i in 0 to size_0-1 loop
pairDistance := 2**(stageIndx-passIndx);
blockWidth := 2 * pairDistance;
leftIndx := (i mod pairDistance) + (i/pairDistance)*blockWidth;
rightIndx := leftIndx + pairDistance;
leftElement := unsigned(tmp_gmem(leftIndx));
rightElement := unsigned(tmp_gmem(rightIndx));
if leftElement > rightElement then
greater := leftElement;
lesser := rightElement;
else
greater := rightElement;
lesser := leftElement;
end if;
if (i/sameDirectionBlock) mod 2 /= 1 then
leftElement := greater;
rightElement := lesser;
else
leftElement := lesser;
rightElement := greater;
end if;
tmp_gmem(leftIndx) <= std_logic_vector(leftElement);
tmp_gmem(rightIndx) <= std_logic_vector(rightElement);
end loop;
-- report "bitonic round is executed";
end procedure; -- }}}
function canonicalize_float(f: std_logic_vector(31 downto 0)) return std_logic_vector is -- {{{
variable res : std_logic_vector(31 downto 0) := (others=>'0');
begin
res := f;
if f(30 downto 23) = X"FF" then --NaN or infinity
if f(22 downto 0) /= (0 to 22 => '0') then --NaN
res(22 downto 0) := (0=>'1', others=>'0');
res(31) := '0';
end if;
end if;
return res;
end function; -- }}}
function pixel_value(i, j, stride: natural) return integer is -- {{{
variable res : integer := 0;
variable tmp, addr : natural := 0;
variable word_addr : unsigned(DATA_W-1 downto 0) := (others=>'0');
begin
addr := i*stride+j;
tmp := addr mod 4;
word_addr := to_unsigned(addr/ 4, DATA_W);
if tmp = 0 then
res := to_integer(word_addr(7 downto 0));
elsif tmp = 1 then
res := to_integer(word_addr(15 downto 8));
elsif tmp = 2 then
res := to_integer(word_addr(23 downto 16));
else
res := to_integer(word_addr(31 downto 24));
end if;
return res;
end function; -- }}}
procedure sort3(x, y, z: inout integer) is -- {{{
variable tmp_integer : integer := 0;
begin
-- sort in ascending order
if x > y then
tmp_integer := x;
x := y;
y := tmp_integer;
end if;
if x > z then
tmp_integer := x;
x := z;
z := tmp_integer;
end if;
if y > z then
tmp_integer := y;
y := z;
z := tmp_integer;
end if;
end procedure; --}}}
procedure compute_max_half_atomic is -- {{{
variable res : integer;
begin
res := to_integer(signed(gmem(0)(DATA_W/2-1 downto 0)));
for i in 0 to problemSize/4-1 loop -- 4 half words in one gmem address
res := max(res, to_integer(signed(gmem(i)(DATA_W/2-1 downto 0))));
res := max(res, to_integer(signed(gmem(i)(DATA_W-1 downto DATA_W/2))));
res := max(res, to_integer(signed(gmem(i)(DATA_W+DATA_W/2-1 downto DATA_W))));
res := max(res, to_integer(signed(gmem(i)(2*DATA_W-1 downto DATA_W+DATA_W/2))));
end loop;
tmp_gmem(0) <= std_logic_vector(to_signed(res, DATA_W));
end procedure; -- }}}
procedure compute_median is -- {{{
variable pixel_align : integer := 0;
variable p00x, p01x, p02x, p10x, p11x, p12x, p20x, p21x, p22x : integer := 0;
variable res : unsigned(DATA_W-1 downto 0) := (others=>'0');
begin
-- print image
-- for i in 0 to size_1-1 loop
-- for j in 0 to size_0/2-1 loop
-- tmp_integer := (i*size_0 +2*j)/GMEM_N_BANK;
-- write(li, to_hstring(gmem(tmp_integer)(DATA_W-1 downto 0)));
-- swrite(li, " ");
-- write(li, to_hstring(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W)));
-- swrite(li, " ");
-- end loop;
-- write(li, LF);
-- writeline(output, li);
-- end loop;
for i in 1 to size_1-2 loop
for j in 1 to size_0-2 loop
pixel_align := (j+1) mod 2;
if pixel_align = 0 then
tmp_integer := ((i-1)*size_0 +j)/GMEM_N_BANK;
p00 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p01 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
p02 := unsigned(gmem(tmp_integer+1)(DATA_W-1 downto 0));
tmp_integer := ((i+0)*size_0 +j)/GMEM_N_BANK;
p10 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p11 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
p12 := unsigned(gmem(tmp_integer+1)(DATA_W-1 downto 0));
tmp_integer := ((i+1)*size_0 +j)/GMEM_N_BANK;
p20 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p21 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
p22 := unsigned(gmem(tmp_integer+1)(DATA_W-1 downto 0));
else
tmp_integer := ((i-1)*size_0 +j)/GMEM_N_BANK;
p00 := unsigned(gmem(tmp_integer-1)(2*DATA_W-1 downto DATA_W));
p01 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p02 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
tmp_integer := ((i+0)*size_0 +j)/GMEM_N_BANK;
p10 := unsigned(gmem(tmp_integer-1)(2*DATA_W-1 downto DATA_W));
p11 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p12 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
tmp_integer := ((i+1)*size_0 +j)/GMEM_N_BANK;
p20 := unsigned(gmem(tmp_integer-1)(2*DATA_W-1 downto DATA_W));
p21 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p22 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
end if;
-- show stencil
-- write(li, to_hstring(p00)); swrite(li, " "); write(li, to_hstring(p01)); swrite(li, " "); write(li, to_hstring(p02)&LF);
-- write(li, to_hstring(p10)); swrite(li, " "); write(li, to_hstring(p11)); swrite(li, " "); write(li, to_hstring(p12)&LF);
-- write(li, to_hstring(p20)); swrite(li, " "); write(li, to_hstring(p21)); swrite(li, " "); write(li, to_hstring(p22)&LF&LF);
-- writeline(output, li);
for k in 0 to 2 loop -- rgb
-- get color values
p00x := to_integer(p00((k+1)*8-1 downto k*8));
p01x := to_integer(p01((k+1)*8-1 downto k*8));
p02x := to_integer(p02((k+1)*8-1 downto k*8));
p10x := to_integer(p10((k+1)*8-1 downto k*8));
p11x := to_integer(p11((k+1)*8-1 downto k*8));
p12x := to_integer(p12((k+1)*8-1 downto k*8));
p20x := to_integer(p20((k+1)*8-1 downto k*8));
p21x := to_integer(p21((k+1)*8-1 downto k*8));
p22x := to_integer(p22((k+1)*8-1 downto k*8));
-- sort rows
sort3(p00x, p01x, p02x);
sort3(p10x, p11x, p12x);
sort3(p20x, p21x, p22x);
-- sort columns
sort3(p00x, p10x, p20x);
sort3(p01x, p11x, p21x);
sort3(p02x, p12x, p22x);
-- sort diagonal
sort3(p00x, p11x, p22x);
-- set resulting byte value
res((k+1)*8-1 downto 8*k) := to_unsigned(p11x, 8);
end loop;
tmp_gmem(i*size_1+j) <= std_logic_vector(res);
end loop;
end loop;
end procedure; --}}}
procedure check_kernel is -- {{{
begin
for i in 0 to N_AXI-1 loop
if wvalid(i) = '1' and wready(i) = '1' then
wr_addr_int := to_integer(unsigned(wr_addr_offset(i)));
-- assert wr_addr_int /= 16#1b9b8# and wr_addr_int /= 16#1b9b9# and wr_addr_int /= 16#1b9ba# and wr_addr_int /= 16#1b9bb# and wr_addr_int /= 16#1b9bc# and wr_addr_int /= 16#1b9bd# and wr_addr_int /= 16#1b9be# and wr_addr_int /= 16#1b9bf#;
-- write(output, "0x" & to_hstring(to_signed(word_addr, 32)) & LF);
if kernel_name = bitonic or kernel_name = fft_hard or kernel_name = floydwarshall then
word_addr := wr_addr_int*2; -- index of first parameter value
else
word_addr := wr_addr_int*2-(offset+target_offset_addr)/4; -- index of first parameter value
end if;
second_word_addr := word_addr + 64*1024; -- index of the second parameter
-- assert word_addr < 64*1024 severity failure;
assert word_addr >= 0 report integer'image(word_addr) severity failure ;
byte_addr := word_addr * 4;
half_addr := word_addr * 2;
case kernel_name is
when copy =>
for k in 0 to 1 loop
must_data((k+1)*DATA_W-1 downto k*DATA_W) := std_logic_vector(to_unsigned(word_addr+k, DATA_W));
end loop;
when parallelSelection =>
for k in 0 to 1 loop
-- must_data((k+1)*DATA_W-1 downto k*DATA_W) := std_logic_vector(to_unsigned(word_addr+k, DATA_W));
must_data((k+1)*DATA_W-1 downto k*DATA_W) := std_logic_vector(to_float(word_addr+k));
end loop;
when max_half_atomic =>
must_data(DATA_W-1 downto 0) := tmp_gmem(0);
when sobel =>
when bitonic | fft_hard | median =>
must_data(DATA_W-1 downto 0) := tmp_gmem(word_addr);
-- report integer'image(word_addr);
-- report integer'image(to_integer(unsigned(tmp_gmem(word_addr))));
-- report integer'image(to_integer(unsigned(tmp_gmem(word_addr+1))));
must_data(2*DATA_W-1 downto DATA_W) := tmp_gmem(word_addr+1);
when fir_char4 =>
for k in 0 to GMEM_DATA_W/8-1 loop
res := 0;
tmp_integer := (byte_addr+k) mod 256;
for p in 0 to 12-1 loop
res := res + (tmp_integer+p)*p;
end loop;
tmp_unsigned := to_unsigned(res, DATA_W);
must_data((k+1)*GMEM_DATA_W/8-1 downto k*GMEM_DATA_W/8) := std_logic_vector(tmp_unsigned(7 downto 0));
end loop;
when fadd => -- {{{
must_data(DATA_W-1 downto 0) := to_slv( to_float(gmem(word_addr/GMEM_N_BANK)(DATA_W-1 downto 0)) +
to_float(gmem(second_word_addr/GMEM_N_BANK)(DATA_W-1 downto 0)) );
must_data(2*DATA_W-1 downto DATA_W) := to_slv(to_float(gmem(word_addr/GMEM_N_BANK)(2*DATA_W-1 downto DATA_W)) +
to_float(gmem(second_word_addr/GMEM_N_BANK)(2*DATA_W-1 downto DATA_W)) );
-- }}}
when floydwarshall => -- {{{
-- }}}
when add_float => -- {{{
must_data(DATA_W-1 downto 0) := to_slv(to_float(gmem(word_addr/GMEM_N_BANK)(DATA_W-1 downto 0)) + to_float(1));
must_data(2*DATA_W-1 downto DATA_W) := to_slv(to_float(gmem(word_addr/GMEM_N_BANK)(2*DATA_W-1 downto DATA_W)) + to_float(1));
-- }}}
when mul_float => -- {{{
must_data(DATA_W-1 downto 0) := to_slv( to_float(gmem(word_addr/GMEM_N_BANK)(DATA_W-1 downto 0)) *
to_float(gmem(second_word_addr/GMEM_N_BANK)(DATA_W-1 downto 0)) );
must_data(2*DATA_W-1 downto DATA_W) := to_slv(to_float(gmem(word_addr/GMEM_N_BANK)(2*DATA_W-1 downto DATA_W)) *
to_float(gmem(second_word_addr/GMEM_N_BANK)(2*DATA_W-1 downto DATA_W)) );
-- }}}
when mat_mul => -- {{{
colIndx := word_addr mod size_0;
rowIndx := word_addr / size_0;
res := 0;
for k in 0 to size_0-1 loop
res := res + ((rowIndx*size_0+k) mod FILL_MODULO) * ((colIndx+k*size_0)mod FILL_MODULO);
end loop;
-- res := size_0*size_0*rowIndx*colIndx + (size_0*size_0*rowIndx+colIndx)*(size_0-1)*size_0/2 + size_0*(size_0-1)*size_0*(2*size_0-1)/6;
must_data(DATA_W-1 downto 0) := std_logic_vector(to_unsigned(res, DATA_W));
colIndx := (word_addr+1) mod size_0;
rowIndx := (word_addr+1) / size_0;
res := 0;
for k in 0 to size_0-1 loop
res := res + ((rowIndx*size_0+k) mod FILL_MODULO) * ((colIndx+k*size_0)mod FILL_MODULO);
end loop;
must_data(2*DATA_W-1 downto DATA_W) := std_logic_vector(to_unsigned(res, DATA_W));
-- }}}
when fir => -- {{{
res := 0;
for p in 0 to 5-1 loop
res := res + (word_addr+p)*p;
end loop;
must_data(DATA_W-1 downto 0) := std_logic_vector(to_unsigned(res, DATA_W));
res := 0;
for p in 0 to 5-1 loop
res := res + (word_addr+p+1);
end loop;
must_data(2*DATA_W-1 downto DATA_W) := std_logic_vector(to_unsigned(res, DATA_W));
-- }}}
when xcorr => -- {{{
res := 0;
for k in 0 to size_0-1 loop
res := res + (k mod FILL_MODULO) * ((word_addr+k) mod FILL_MODULO);
end loop;
must_data(DATA_W-1 downto 0) := std_logic_vector(to_unsigned(res, DATA_W));
res := 0;
for k in 0 to size_0-1 loop
res := res + (k mod FILL_MODULO) * ((word_addr+1+k) mod FILL_MODULO);
end loop;
must_data(2*DATA_W-1 downto DATA_W) := std_logic_vector(to_unsigned(res, DATA_W));
-- }}}
when sum_atomic => -- {{{
must_data(DATA_W-1 downto 0) := std_logic_vector(to_unsigned((size_0-1)*size_0/2, DATA_W));
when others =>
report "undifined program index!" severity failure;
end case; --- }}}
if wvalid(i) = '1' and wready(i) = '1' then
case COMP_TYPE is
when 0 => -- byte {{{
for k in 0 to 7 loop
if wstrb(i)(k) = '1' and must_data((k+1)*8-1 downto k*8) /= wdata(i)((k+1)*8-1 downto k*8) then
report "wdata byte " & integer'image(k) & " on AXI " & integer'image(i) &
" data is " & integer'image(to_integer(unsigned(wdata(i)((k+1)*8-1 downto k*8)))) &
" must be " & integer'image(to_integer(unsigned(must_data((k+1)*8-1 downto k*8)))) &
" on byte Nr. " & integer'image(byte_addr)
severity failure;
end if;
if wstrb(i)(k) = '1' then
if written_addrs(byte_addr+k) = '0' then
written_count_tmp := written_count_tmp + 1;
else
-- report "double write";
end if;
written_addrs(byte_addr+k) <= '1';
end if;
end loop;
--}}}
when 1 => -- half word {{{
for k in 0 to 3 loop
assert wstrb(i)((k+1)*2-1 downto k*2) = "00" or must_data((k+1)*16-1 downto k*16) = wdata(i)((k+1)*16-1 downto k*16)
report "wdata half word " & integer'image(k) & " on AXI " & integer'image(i) severity failure;
if wstrb(i)(k*2) = '1' then
if written_addrs(half_addr+k) = '0' then
written_count_tmp := written_count_tmp + 1;
else
-- report "double write";
end if;
written_addrs(half_addr+k) <= '1';
end if;
end loop;
-- }}}
when 2 => -- word {{{
for k in 0 to 1 loop
if kernel_name = add_float or kernel_name = mul_float or kernel_name = fadd then
if wstrb(i)((k+1)*DATA_W/8-1 downto k*DATA_W) = X"F" then
if canonicalize_float(must_data((k+1)*DATA_W-1 downto k*DATA_W)) /=
canonicalize_float(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W)) then
write(output, "wdata word " & integer'image(k) & " on AXI " & integer'image(i) & " is " &
"0x" & to_hstring(unsigned(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W))) &
" (should be " & "0x" & to_hstring(unsigned(must_data((k+1)*DATA_W-1 downto k*DATA_W))) & ") for word_addr = " &
integer'image(word_addr+k) & LF);
if kernel_name = fadd then
write(li, to_real(to_float(gmem(word_addr/GMEM_N_BANK)((k+1)*DATA_W-1 downto k*DATA_W))));
write(li, LF);
write(li, to_real(to_float(must_data((k+1)*DATA_W-1 downto k*DATA_W))));
writeline(output, li);
else
write(output, to_hstring(gmem(word_addr/GMEM_N_BANK)((k+1)*DATA_W-1 downto k*DATA_W))&LF);
write(output, to_hstring(gmem(second_word_addr/GMEM_N_BANK)((k+1)*DATA_W-1 downto k*DATA_W))&LF);
end if;
assert false ;
-- assert false severity failure;
end if;
end if;
elsif kernel_name = fft_hard then
if wstrb(i)((k+1)*DATA_W/8-1 downto k*DATA_W) = X"F" then
if must_data((k+1)*DATA_W-1 downto k*DATA_W) /= wdata(i)((k+1)*DATA_W-1 downto k*DATA_W) then
write(output, "wdata word " & integer'image(k) & " on AXI " & integer'image(i) & " is " &
"0x" & to_hstring(unsigned(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W))) &
" (should be " & "0x" & to_hstring(unsigned(must_data((k+1)*DATA_W-1 downto k*DATA_W))) & ") for word_addr = " &
integer'image(word_addr+k) & LF);
write(li, to_real(to_float(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W))));
write(li, LF);
write(li, to_real(to_float(must_data((k+1)*DATA_W-1 downto k*DATA_W))));
writeline(output, li);
-- for i in 0 to 7 loop
-- swrite(li, "x= ");
-- write(li, to_real(to_float(tmp_gmem(4*i))));
-- swrite(li, ",y= ");
-- write(li, to_real(to_float(tmp_gmem(4*i+1))));
-- swrite(li, ",z= ");
-- write(li, to_real(to_float(tmp_gmem(4*i+2))));
-- swrite(li, ",m= ");
-- write(li, to_real(to_float(tmp_gmem(4*i+3))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
-- for i in 0 to 7 loop
-- write(li, to_real(to_float(tmp_gmem(2*i))));
-- swrite(li, " +j ");
-- write(li, to_real(to_float(tmp_gmem(2*i+1))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
if must_data((k+1)*DATA_W-1 downto k*DATA_W+18) /= wdata(i)((k+1)*DATA_W-1 downto k*DATA_W+18) then
-- ignore some lsbs
assert false severity failure;
end if;
end if;
end if;
elsif kernel_name /= sum_atomic then
if wstrb(i)((k+1)*DATA_W/8-1 downto k*DATA_W) = X"F" and
must_data((k+1)*DATA_W-1 downto k*DATA_W) /= wdata(i)((k+1)*DATA_W-1 downto k*DATA_W) then
write(output, "wdata word " & integer'image(k) & " on AXI " & integer'image(i) & " is " &
integer'image(to_integer(unsigned(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W)))) &
" (should be " & integer'image(to_integer(unsigned(must_data((k+1)*DATA_W-1 downto k*DATA_W)))) & ") for word_addr = " &
integer'image(word_addr+k) & LF);
assert false severity failure;
end if;
end if;
if wstrb(i)(k*DATA_W/8) = '1' then
if written_addrs(word_addr+k) = '0' then
written_count_tmp := written_count_tmp + 1;
else
-- report "double write";
end if;
written_addrs(word_addr+k) <= '1';
end if;
end loop;
-- }}}
when others =>
report "undefined computation type!" severity failure;
end case;
end if;
end if;
end loop;
end procedure;
procedure check_written_count(num: integer) is
begin
if written_count = num then
if STAT = 0 then
report "Kernel finished successfully! Size was :"&integer'image(num);
end if;
else
report "XXXXXXXXXXXXXXXXXXXX NOT ALL RESULTS ARE WRITTEN XXXXXXXXXXXXXXXXXX ! Size was :"&integer'image(num)& " written are: "&integer'image(written_count);
for i in 0 to num-1 loop
assert written_addrs(i) = '1' report "The address "&integer'image(i)&" is not written" severity failure;
end loop;
assert false severity failure;
end if;
end procedure;
-- }}}
begin
if rising_edge(clk) then
written_count_tmp := 0;
check_kernel;
new_kernel_d0 <= new_kernel;
new_kernel_d1 <= new_kernel_d0;
if new_kernel = '1' then
written_count <= 0;
written_addrs <= (others=>'0');
if kernel_name = bitonic then
for i in 0 to 2**16-1 loop
tmp_gmem(i) <= std_logic_vector(to_unsigned(i, 32));
end loop;
nStages := 1;
tmp_integer := 1;
while tmp_integer < size_0 loop
tmp_integer := tmp_integer * 2;
nStages := nStages + 1;
end loop;
stageIndx := 0;
passIndx := 0;
elsif kernel_name = fft_hard then
nStages := 1;
tmp_integer := 1;
while tmp_integer < size_0 loop
tmp_integer := tmp_integer * 2;
nStages := nStages + 1;
end loop;
stageIndx := 0;
-- with bit reverse
for i in 0 to size_0*2-1 loop
tmp_unsigned := to_unsigned(i, 32);
for j in 0 to nStages/2 loop
tmp_std_logic := tmp_unsigned(nStages-1-j);
tmp_unsigned(nStages-1-j) := tmp_unsigned(j);
tmp_unsigned(j) := tmp_std_logic;
end loop;
tmp_gmem(2*to_integer(tmp_unsigned)) <= to_slv(to_float(i mod 4)); -- real part
tmp_gmem(2*to_integer(tmp_unsigned)+1) <= (others=>'0'); -- imaginary part
end loop;
end if;
else
written_count <= written_count + written_count_tmp;
if new_kernel_d0 = '1' then
if kernel_name = bitonic then
bitonic_round;
if passIndx = stageIndx then
passIndx := 0;
stageIndx := stageIndx + 1;
else
passIndx := passIndx + 1;
end if;
elsif kernel_name = fft_hard then
-- report "tmp_gmem = ";
-- for i in 0 to 7 loop
-- write(li, to_real(to_float(tmp_gmem(2*i))));
-- swrite(li, " +j ");
-- write(li, to_real(to_float(tmp_gmem(2*i+1))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
fft_round;
stageIndx := stageIndx + 1;
elsif kernel_name = median then
compute_median;
elsif kernel_name = max_half_atomic then
compute_max_half_atomic;
end if;
end if;
end if;
if finished_kernel = '1' then
if kernel_name = bitonic then
-- if passIndx /= 1 then
if kernel_name = bitonic then
bitonic_round;
else
bitonic_float_round;
end if;
-- end if;
if passIndx = stageIndx then
passIndx := 0;
stageIndx := stageIndx + 1;
else
passIndx := passIndx + 1;
end if;
elsif kernel_name = fft_hard then
fft_round;
stageIndx := stageIndx + 1;
elsif kernel_name = sum_atomic or kernel_name = max_half_atomic then
assert must_data(DATA_W-1 downto 0) = gmem(65536)(DATA_W-1 downto 0)
report "result is " & integer'image(to_integer(unsigned(gmem(65536)(DATA_W-1 downto 0))))& " (must be " &
integer'image(to_integer(unsigned(must_data(DATA_W-1 downto 0)))) & ")"
severity failure;
-- report "wdata word " & integer'image(k) & " on AXI " & integer'image(i) & " is " &
-- integer'image(to_integer(unsigned(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W)))) &
-- " (should be " & integer'image(to_integer(unsigned(must_data((k+1)*DATA_W-1 downto k*DATA_W)))) & ") for word_addr = " &
-- integer'image(word_addr+k) severity failure;
-- report integer'image(to_integer(unsigned(must_data(DATA_W-1 downto 0))));
check_written_count(1);
else
if COMP_TYPE = 0 then -- byte mode
check_written_count(size_0*size_1*4);
elsif kernel_name = median then
check_written_count(size_0*size_1-2*(size_0-1)-2*(size_1-1)); -- no write for edge pixels
else
check_written_count(size_0*size_1);
end if;
end if;
end if;
-- write(li, std_logic_vector(wr_addr_offset(0)));
-- writeline(OUTPUT, li);
-- report "written addr: " & integer'image(2*(wr_addr_int-16#400#));
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- performance measurements ------------------------------------------------------------------------------{{{
perf_count: if STAT = 1 generate
process(clk)
-- variable n_empty_bytes, n_written_bytes : natural := 0;
-- variable empty_bytes_percentage: real := 0.0;
variable min_n_bursts, n_wr_increase, n_rd_increase : real := 0.0;
variable min_n_read_bursts, min_n_write_bursts : real := 0.0;
variable n_wr_bursts, n_rd_bursts : natural := 0;
variable size, data_size_word : natural := 0;
begin
if rising_edge(clk) then
if finished_kernel = '1' then
if kernel_name = sum_atomic or kernel_name = max_half_atomic then
data_size_word := problemSize;
-- empty_bytes_percentage := real(n_empty_bytes)/real(n_written_bytes);
-- report "# of written empty bytes = " & integer'image(n_empty_bytes);
-- report "# of written bytes = " & integer'image(n_written_bytes);
min_n_read_bursts := ceil(real(data_size_word)/real(GMEM_N_BANK)/real(to_integer(unsigned(mx_arlen_awlen)+1))); -- smallest number of bursts need ti finish the task
min_n_write_bursts := ceil(real(1)/real(GMEM_N_BANK)/real(to_integer(unsigned(mx_arlen_awlen)+1)));
n_wr_increase := real(n_wr_bursts)/min_n_write_bursts*100.0 - 100.0;
n_rd_increase := real(n_rd_bursts)/min_n_read_bursts*100.0 - 100.0;
report "Problem size= "&integer'image(data_size_word) & ", # WR Bursts= " & integer'image(n_wr_bursts) & " (+" & integer'image(integer(n_wr_increase)) &"%)" &
", # RD Bursts= " & integer'image(n_rd_bursts) & " (+" & integer'image(integer(n_rd_increase)) &"%)";
-- n_empty_bytes := 0;
-- n_written_bytes := 0;
n_wr_bursts := 0;
n_rd_bursts := 0;
elsif kernel_name /= bitonic and kernel_name /= fft_hard then
size := size_0*size_1;
if COMP_TYPE = 0 then -- byte
data_size_word := size_0*size_1 / 4;
elsif COMP_TYPE = 1 then -- half word
data_size_word := size_0*size_1 / 2;
else -- word
data_size_word := size_0*size_1;
end if;
-- empty_bytes_percentage := real(n_empty_bytes)/real(n_written_bytes);
-- report "# of written empty bytes = " & integer'image(n_empty_bytes);
-- report "# of written bytes = " & integer'image(n_written_bytes);
min_n_bursts := ceil(real(data_size_word)/real(GMEM_N_BANK)/real(to_integer(unsigned(mx_arlen_awlen)+1))); -- smallest number of bursts need ti finish the task
n_wr_increase := real(n_wr_bursts)/min_n_bursts*100.0 - 100.0;
n_rd_increase := real(n_rd_bursts)/min_n_bursts*100.0 - 100.0;
-- report "Size= "&integer'image(data_size_word) &", Empty written bytes = " & integer'image(integer(empty_bytes_percentage)) & " %"&", # Bursts= " &
-- integer'image(n_wr_bursts) & " (+" & integer'image(integer(n_wr_increase)) &" %)";
report "Size= "&integer'image(size) & ", # WR Bursts= " & integer'image(n_wr_bursts) & " (+" & integer'image(integer(n_wr_increase)) &"%)" &
", # RD Bursts= " & integer'image(n_rd_bursts) & " (+" & integer'image(integer(n_rd_increase)) &"%)";
-- n_empty_bytes := 0;
-- n_written_bytes := 0;
n_wr_bursts := 0;
n_rd_bursts := 0;
end if;
else
for i in 0 to N_AXI-1 loop
if awvalid(i) = '1' and awready(i) = '1' then
n_wr_bursts := n_wr_bursts + 1;
end if;
if arvalid(i) = '1' and arready(i) = '1' then
n_rd_bursts := n_rd_bursts + 1;
end if;
-- if wvalid(i) = '1' then
-- for j in 0 to GMEM_DATA_W/8-1 loop
-- if wstrb(i)(j) = '1' then
-- -- n_written_bytes := n_written_bytes + 1;
-- else
-- -- n_empty_bytes := n_empty_bytes + 1;
-- end if;
-- end loop;
-- end if;
end loop;
end if;
end if;
end process;
end generate;
---------------------------------------------------------------------------------------------------------}}}
---------------------------------------------------------------------------------------------------------- }}}
end Behavioral;
| gpl-3.0 | 19dca3e367c2a6f003171ca0e3ed8a9b | 0.500943 | 3.425748 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf_top.vhd | 1 | 14,885 | -------------------------------------------------------------------------------
--! @file cf_top.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-05-06
--! @brief FGClite Critical FPGA (CF) top-level.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ab_pkg.all;
use work.nf_pkg.all;
use work.xf_pkg.all;
use work.sram_pkg.all;
--! @brief Entity declaration of cf_top
--! @details
--! The top-level component for the Critical FPGA implementation.
entity cf_top is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Power-on reset
po_rst_i : inout std_logic;
--! Push-button reset
pb_rst_n_i : in std_ulogic;
--! NF reset
nf_rst_n_i : in std_ulogic;
--! @}
--! @name LEDs
--! @{
--! Red LEDs
leds_red_n_o : out std_ulogic_vector(5 downto 0);
--! Green LEDs
leds_green_n_o : out std_ulogic_vector(5 downto 0);
--! Test LEDs
leds_test_n_i : in std_ulogic;
--! @}
--! @name Power converter interface
--! @{
--! Power converter commands
conv_cmd_o : out std_ulogic_vector(7 downto 0);
--! Power converter status
conv_stat_i : in std_ulogic_vector(15 downto 0);
--! @}
--! @name External SRAM interface
--! @{
--! Address
sram_addr_o : out std_ulogic_vector(19 downto 0);
--! Control signals (CS2, OE, LB, UB, BYTE, CS1, WE)
sram_ctrl_o : out std_ulogic_vector(6 downto 0);
--! Data bus
sram_data_io : inout std_logic_vector(15 downto 0);
--! @}
--! @name Optical interface
--! @{
--! Optical input
optical_i : in std_ulogic_vector(1 downto 0);
--! @}
--! @name Analogue board interface
--! @{
--! Stop temperature control
ab_temp_stop_o : out std_ulogic;
--! Power control
ab_pwr_on_n_o : out std_ulogic;
--! @}
--! @name Analogue board calibration multiplexer (only one can be active)
--! @{
--! Set calibration source to DAC
ab_cal_dac_o : out std_ulogic;
--! Set calibration source to GND
ab_cal_offset_o : out std_ulogic;
--! Set calibration source to +VREF
ab_cal_vref_p_o : out std_ulogic;
--! Set calibration source to -VREF
ab_cal_vref_n_o : out std_ulogic;
--! @}
--! @name Analogue board DAC interface
--! @{
--! DAC data
ab_dac_din_o : out std_ulogic;
--! DAC clock
ab_dac_sclk_o : out std_ulogic;
--! DAC chip-select
ab_dac_cs_o : out std_ulogic;
--! @}
--! @name Analogue board ADC V_MEAS
--! @{
--! ADC V_MEAS bit streams M1 and M0
ab_adc_vs_i : in std_ulogic_vector(1 downto 0);
--! ADC V_MEAS bit stream clock
ab_adc_vs_clk_i : in std_ulogic;
--! ADC V_MEAS reset (active-low)
ab_adc_vs_rst_n_o : out std_ulogic;
--! Calibrate ADC V_MEAS
ab_sw_in_vs_o : out std_ulogic;
--! @}
--! @name Analogue board ADC I_A
--! @{
--! ADC I_A bit streams M1 and M0
ab_adc_a_i : in std_ulogic_vector(1 downto 0);
--! ADC I_A bit stream clock
ab_adc_a_clk_i : in std_ulogic;
--! ADC I_A reset (active-low)
ab_adc_a_rst_n_o : out std_ulogic;
--! Calibrate ADC I_A
ab_sw_in_a_o : out std_ulogic;
--! @}
--! @name Analogue board ADC I_B
--! @{
--! ADC I_B bit streams M1 and M0
ab_adc_b_i : in std_ulogic_vector(1 downto 0);
--! ADC I_B bit stream clock
ab_adc_b_clk_i : in std_ulogic;
--! ADC I_B reset (active-low)
ab_adc_b_rst_n_o : out std_ulogic;
--! Calibrate ADC I_B
ab_sw_in_b_o : out std_ulogic;
--! @}
--! @name Interlocks
--! @{
--! Interlock inputs
interlock_i : in std_ulogic_vector(1 downto 0);
--! Interlock outputs
interlock_o : out std_ulogic_vector(1 downto 0);
--! @}
--! @name PF interface
--! @{
--! Send power cycle request to PF
pf_req_n_o : out std_ulogic;
--! Enable power down on PF
pf_pwr_dwn_en_o : out std_ulogic;
--! Failure flag from PF
pf_pwr_flr_i : in std_ulogic;
--! Power down signal from PF
pf_pwr_dwn_i : in std_ulogic;
--! @}
--! @name NF interface
--! @{
--! NF received FGClite CMD 0
nf_cmd_0_i : in std_ulogic;
--! NF transmitter ready
nf_tx_rdy_i : in std_ulogic;
--! NanoFIP status byte - bit 5
nf_r_fcser_i : in std_ulogic;
--! NanoFIP status byte - bit 4
nf_r_tler_i : in std_ulogic;
--! NanoFIP status byte - bit 2
nf_u_cacer_i : in std_ulogic;
--! NanoFIP status byte - bit 3
nf_u_pacer_i : in std_ulogic;
--! @}
--! @name 3-wire serial receiver from NF
--! @{
--! Frame
nf_rx_frame_i : in std_ulogic;
--! Bit enable
nf_rx_bit_en_i : in std_ulogic;
--! Data
nf_rx_i : in std_ulogic;
--! @}
--! @name 3-wire serial transmitter to NF
--! @{
--! Frame
nf_tx_frame_o : out std_ulogic;
--! Bit enable
nf_tx_bit_en_o : out std_ulogic;
--! Data
nf_tx_o : out std_ulogic;
--! @}
--! @name 2 x 3-wire serial receiver from XF
--! @{
--! Frame
xf_rx_frame_i : in std_ulogic_vector(1 downto 0);
--! Bit enable
xf_rx_bit_en_i : in std_ulogic_vector(1 downto 0);
--! Data
xf_rx_i : in std_ulogic_vector(1 downto 0);
--! @}
--! @name Control signals to XF
--! @{
--! Trigger DIM bus readout
xf_dim_trig_o : out std_ulogic;
--! Reset all DIMs on bus
xf_dim_rst_o : out std_ulogic;
--! Trigger 1-wire bus readout
xf_ow_trig_o : out std_ulogic;
--! 1-wire bus select
xf_ow_bus_sel_o : out std_ulogic_vector(2 downto 0);
--! @}
--! @name Auxiliary interface (UART to diagnostics connector)
--! @{
--! Input
aux_i : in std_ulogic;
--! Output
aux_o : out std_ulogic;
--! @}
--! @name Debugging
--! @{
--! Serial receiver
debug_rx_i : in std_ulogic;
--! Serial transmitter
debug_tx_o : out std_ulogic;
--! Debugging probe
debug_probe_o : out std_ulogic);
--! @}
end entity cf_top;
--! RTL implementation of cf_top
architecture rtl of cf_top is
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
-- Safe reset generation
signal po_rst_n : std_ulogic;
signal pb_rst_n : std_ulogic;
signal nf_rst_n : std_ulogic;
signal rst_n : std_ulogic;
-- Input synchronization and glitch filter
signal leds_test_n_syn : std_ulogic;
signal conv_stat_syn : std_ulogic_vector(15 downto 0);
signal optical_syn : std_ulogic_vector(1 downto 0);
signal interlock_syn : std_ulogic_vector(1 downto 0);
signal pf_pwr_flr_syn : std_ulogic;
signal pf_pwr_dwn_syn : std_ulogic;
signal aux_syn : std_ulogic;
signal debug_rx_syn : std_ulogic;
-- External SRAM interface
signal sram_in : sram_in_t;
signal sram_out : sram_out_t;
-- Analogue board interface
signal ab_in : ab_in_t;
signal ab_out : ab_out_t;
-- NanoFIP interface
signal nf_in : nf_in_t;
signal nf_out : nf_out_t;
-- Auxiliary FPGA interface
signal xf_in : xf_in_t;
signal xf_out : xf_out_t;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
-- External SRAM interface
sram_data_io <= std_logic_vector(sram_out.data) when sram_out.we_n = '0' else (others => 'Z');
sram_addr_o <= sram_out.addr;
sram_ctrl_o(0) <= sram_out.we_n;
sram_ctrl_o(1) <= sram_out.cs1_n;
sram_ctrl_o(2) <= sram_out.byte_n;
sram_ctrl_o(3) <= sram_out.ue_n;
sram_ctrl_o(4) <= sram_out.le_n;
sram_ctrl_o(5) <= sram_out.oe_n;
sram_ctrl_o(6) <= sram_out.cs2;
-- Analogue board interface
ab_temp_stop_o <= ab_out.temp_stop;
ab_pwr_on_n_o <= ab_out.pwr_on_n;
ab_cal_dac_o <= ab_out.cal_dac;
ab_cal_offset_o <= ab_out.cal_offset;
ab_cal_vref_p_o <= ab_out.cal_vref_p;
ab_cal_vref_n_o <= ab_out.cal_vref_n;
ab_dac_din_o <= ab_out.dac_din;
ab_dac_sclk_o <= ab_out.dac_sclk;
ab_dac_cs_o <= ab_out.dac_cs;
ab_adc_vs_rst_n_o <= ab_out.adc_vs_rst_n;
ab_sw_in_vs_o <= ab_out.sw_in_vs;
ab_adc_a_rst_n_o <= ab_out.adc_a_rst_n;
ab_sw_in_a_o <= ab_out.sw_in_a;
ab_adc_b_rst_n_o <= ab_out.adc_b_rst_n;
ab_sw_in_b_o <= ab_out.sw_in_b;
-- NanoFIP interface
nf_tx_frame_o <= nf_out.tx_frame;
nf_tx_bit_en_o <= nf_out.tx_bit_en;
nf_tx_o <= nf_out.tx;
-- Auxiliary FPGA interface
xf_dim_trig_o <= xf_out.dim_trig;
xf_dim_rst_o <= xf_out.dim_rst;
xf_ow_trig_o <= xf_out.ow_trig;
xf_ow_bus_sel_o <= xf_out.ow_bus_select;
---------------------------------------------------------------------------
-- Signal Assignments
---------------------------------------------------------------------------
-- Safe reset generation
rst_n <= po_rst_n and pb_rst_n and nf_rst_n;
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! Power-on reset generation for Microsemi devices
po_reset_inst : entity work.microsemi_reset_generator
generic map (
num_delay_g => 4,
active_g => '0')
port map (
clk_i => clk_i,
rst_asy_io => po_rst_i,
rst_o => po_rst_n);
--! Safe push-button reset generation
pb_reset_inst : entity work.reset_generator
generic map (
num_delay_g => 4,
active_g => '0')
port map (
clk_i => clk_i,
rst_asy_i => pb_rst_n_i,
rst_o => pb_rst_n);
--! Safe NF reset generation
nf_reset_inst : entity work.reset_generator
generic map (
num_delay_g => 4,
active_g => '0')
port map (
clk_i => clk_i,
rst_asy_i => nf_rst_n_i,
rst_o => nf_rst_n);
--! Input synchronization and glitch filter for power converter status
ext_inputs_inst_0 : entity work.external_inputs
generic map (
init_value_g => '0',
num_inputs_g => conv_stat_i'length)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
sig_i => conv_stat_i,
sig_o => conv_stat_syn);
--! Input synchronization and glitch filter for SRAM data
ext_inputs_inst_1 : entity work.external_inputs
generic map (
init_value_g => '0',
num_inputs_g => sram_data_io'length)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
sig_i => std_ulogic_vector(sram_data_io),
sig_o => sram_in.data);
--! Input synchronization and glitch filter for all other inputs
ext_inputs_inst_2 : entity work.external_inputs
generic map (
init_value_g => '0',
num_inputs_g => 33)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
sig_i(0) => leds_test_n_i,
sig_i(1) => optical_i(0),
sig_i(2) => optical_i(1),
sig_i(3) => ab_adc_vs_i(0),
sig_i(4) => ab_adc_vs_i(1),
sig_i(5) => ab_adc_vs_clk_i,
sig_i(6) => ab_adc_a_i(0),
sig_i(7) => ab_adc_a_i(1),
sig_i(8) => ab_adc_a_clk_i,
sig_i(9) => ab_adc_b_i(0),
sig_i(10) => ab_adc_b_i(1),
sig_i(11) => ab_adc_b_clk_i,
sig_i(12) => interlock_i(0),
sig_i(13) => interlock_i(1),
sig_i(14) => pf_pwr_flr_i,
sig_i(15) => pf_pwr_dwn_i,
sig_i(16) => nf_cmd_0_i,
sig_i(17) => nf_tx_rdy_i,
sig_i(18) => nf_r_fcser_i,
sig_i(19) => nf_r_tler_i,
sig_i(20) => nf_u_cacer_i,
sig_i(21) => nf_u_pacer_i,
sig_i(22) => nf_rx_frame_i,
sig_i(23) => nf_rx_bit_en_i,
sig_i(24) => nf_rx_i,
sig_i(25) => xf_rx_frame_i(0),
sig_i(26) => xf_rx_frame_i(1),
sig_i(27) => xf_rx_bit_en_i(0),
sig_i(28) => xf_rx_bit_en_i(1),
sig_i(29) => xf_rx_i(0),
sig_i(30) => xf_rx_i(1),
sig_i(31) => aux_i,
sig_i(32) => debug_rx_i,
sig_o(0) => leds_test_n_syn,
sig_o(1) => optical_syn(0),
sig_o(2) => optical_syn(1),
sig_o(3) => ab_in.adc_vs(0),
sig_o(4) => ab_in.adc_vs(1),
sig_o(5) => ab_in.adc_vs_clk,
sig_o(6) => ab_in.adc_a(0),
sig_o(7) => ab_in.adc_a(1),
sig_o(8) => ab_in.adc_a_clk,
sig_o(9) => ab_in.adc_b(0),
sig_o(10) => ab_in.adc_b(1),
sig_o(11) => ab_in.adc_b_clk,
sig_o(12) => interlock_syn(0),
sig_o(13) => interlock_syn(1),
sig_o(14) => pf_pwr_flr_syn,
sig_o(15) => pf_pwr_dwn_syn,
sig_o(16) => nf_in.cmd_0,
sig_o(17) => nf_in.tx_rdy,
sig_o(18) => nf_in.r_fcser,
sig_o(19) => nf_in.r_tler,
sig_o(20) => nf_in.u_cacer,
sig_o(21) => nf_in.u_pacer,
sig_o(22) => nf_in.rx_frame,
sig_o(23) => nf_in.rx_bit_en,
sig_o(24) => nf_in.rx,
sig_o(25) => xf_in.rx_frame(0),
sig_o(26) => xf_in.rx_frame(1),
sig_o(27) => xf_in.rx_bit_en(0),
sig_o(28) => xf_in.rx_bit_en(1),
sig_o(29) => xf_in.rx(0),
sig_o(30) => xf_in.rx(1),
sig_o(31) => aux_syn,
sig_o(32) => debug_rx_syn);
--! CF core component
cf_inst : entity work.cf
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
leds_red_n_o => leds_red_n_o,
leds_green_n_o => leds_green_n_o,
leds_test_n_i => leds_test_n_syn,
conv_cmd_o => conv_cmd_o,
conv_stat_i => conv_stat_syn,
sram_i => sram_in,
sram_o => sram_out,
optical_i => optical_syn,
ab_i => ab_in,
ab_o => ab_out,
interlock_i => interlock_syn,
interlock_o => interlock_o,
pf_req_n_o => pf_req_n_o,
pf_pwr_dwn_en_o => pf_pwr_dwn_en_o,
pf_pwr_flr_i => pf_pwr_flr_syn,
pf_pwr_dwn_i => pf_pwr_dwn_syn,
nf_i => nf_in,
nf_o => nf_out,
xf_i => xf_in,
xf_o => xf_out,
aux_i => aux_syn,
aux_o => aux_o,
debug_rx_i => debug_rx_syn,
debug_tx_o => debug_tx_o,
debug_probe_o => debug_probe_o);
end architecture rtl;
| mit | 3df2efea406024b113a7867e3160bfb0 | 0.494189 | 2.930695 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_6Stations_8Banks.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 6;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | d98562cbe414ad065cbebe0db2beaf9a | 0.567707 | 3.729005 | false | false | false | false |
preusser/q27 | src/vhdl/PoC/sync/sync_Bits_Xilinx.vhdl | 2 | 4,417 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Bits_Xilinx
--
-- Description:
-- ------------------------------------
-- This is a multi-bit clock-domain-crossing circuit optimized for Xilinx FPGAs.
-- It utilizes two 'FD' instances from UniSim.vComponents. If you need a
-- platform independent version of this synchronizer, please use
-- 'PoC.misc.sync.sync_Flag', which internally instantiates this module if
-- a Xilinx FPGA is detected.
--
-- ATTENTION:
-- Use this synchronizer only for long time stable signals (flags).
--
-- CONSTRAINTS:
-- This relative placement of the internal sites is constrained by RLOCs.
--
-- Xilinx ISE UCF or XCF file:
-- NET "*_async" TIG;
-- INST "*FF1_METASTABILITY_FFS" TNM = "METASTABILITY_FFS";
-- TIMESPEC "TS_MetaStability" = FROM FFS TO "METASTABILITY_FFS" TIG;
--
-- Xilinx Vivado xdc file:
-- TODO
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sync_Bits_Xilinx is
generic (
BITS : POSITIVE := 1; -- number of bit to be synchronized
INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits
);
port (
Clock : in STD_LOGIC; -- Clock to be synchronized to
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data
);
end entity;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sync_Bit_Xilinx is
generic (
INIT : BIT -- initialitation bit
);
port (
Clock : in STD_LOGIC; -- Clock to be synchronized to
Input : in STD_LOGIC; -- Data to be synchronized
Output : out STD_LOGIC -- synchronised data
);
end entity;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.utils.ALL;
architecture rtl of sync_Bits_Xilinx is
constant INIT_I : BIT_VECTOR := to_bitvector(resize(descend(INIT), BITS));
begin
gen : for i in 0 to BITS - 1 generate
Sync : entity PoC.sync_Bit_Xilinx
generic map (
INIT => INIT_I(i)
)
port map (
Clock => Clock,
Input => Input(i),
Output => Output(i)
);
end generate;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UniSim;
use UniSim.vComponents.all;
architecture rtl of sync_Bit_Xilinx is
attribute ASYNC_REG : STRING;
attribute SHREG_EXTRACT : STRING;
attribute RLOC : STRING;
signal Data_async : STD_LOGIC;
signal Data_meta : STD_LOGIC;
signal Data_sync : STD_LOGIC;
-- Mark register Data_async's input as asynchronous
attribute ASYNC_REG of Data_meta : signal is "TRUE";
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT of Data_meta : signal is "NO";
attribute SHREG_EXTRACT of Data_sync : signal is "NO";
-- Assign synchronization FF pairs to the same slice -> minimal routing delay
attribute RLOC of Data_meta : signal is "X0Y0";
attribute RLOC of Data_sync : signal is "X0Y0";
begin
Data_async <= Input;
FF1_METASTABILITY_FFS : FD
generic map (
INIT => INIT
)
port map (
C => Clock,
D => Data_async,
Q => Data_meta
);
FF2 : FD
generic map (
INIT => INIT
)
port map (
C => Clock,
D => Data_meta,
Q => Data_sync
);
Output <= Data_sync;
end architecture;
| agpl-3.0 | d99da8cec4ee3305cbb33c31e35dc377 | 0.623727 | 3.379495 | false | false | false | false |
malkadi/FGPU | RTL/loc_indcs_generator.vhd | 1 | 15,098 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
---------------------------------------------------------------------------------------------------------}}}
entity loc_indcs_generator is
-- ports {{{
port(
start : in std_logic;
finish : out std_logic := '0'; --state signal
clear_finish : in std_logic;
n_wf_wg_m1 : in unsigned(N_WF_CU_W-1 downto 0);
wg_size_d0 : in integer range 0 to WG_MAX_SIZE := 0;
wg_size_d1 : in integer range 0 to WG_MAX_SIZE := 0;
wg_size_d2 : in integer range 0 to WG_MAX_SIZE := 0;
wrAddr : out unsigned(RTM_ADDR_W-2 downto 0) := (others => '0'); --additional -1 is to exclude the MSB about local_indcs or wg_offset
we : out std_logic := '0';
wrData : out unsigned(RTM_DATA_W-1 downto 0) := (others => '0');
clk, nrst : in std_logic
);
-- }}}
end loc_indcs_generator;
architecture Behavioral of loc_indcs_generator is
-- internal signals {{{{
signal finish_i : std_logic := '0';
-- }}}
-- signal definitions {{{
type state_type is (idle, start_d0_gen, start_d1_gen, start_d2_gen, store_inc_d0, store_inc_d1, store_inc_d2, check);
signal state, nstate: state_type := idle;
type state_dx_type is (idle, inc, empty_wg_size);
signal state_d0, nstate_d0 : state_dx_type := idle;
signal state_d1, nstate_d1 : state_dx_type := idle;
signal state_d2, nstate_d2 : state_dx_type := idle;
-- signal we_d0, we_d1, we_d2 : std_logic_vector(CV_SIZE/2-1 downto 0) := (others => '0');
signal we_d0, we_d1, we_d2 : std_logic_vector(3 downto 0) := (others => '0');
signal count, count_n : unsigned(RTM_ADDR_W-2-1 downto 0) := (others => '0'); -- the (-2) is to exclude the 2 bits about the dimension
signal d0, d1, d2, d0_n, d1_n, d2_n : unsigned(RTM_DATA_W-1 downto 0) := (others=>'0');
signal d0_count_1, d0_count_1_n : unsigned(WG_SIZE_W-1 downto 0) := (others => '0');
signal d1_count_1, d1_count_1_n : unsigned(WG_SIZE_W-1 downto 0) := (others => '0');
signal d2_count_1, d2_count_1_n : unsigned(WG_SIZE_W-1 downto 0) := (others => '0');
signal d0_count_2, d0_count_2_n : unsigned(WG_SIZE_W-1 downto 0) := (others => '0');
signal d1_count_2, d1_count_2_n : unsigned(WG_SIZE_W-1 downto 0) := (others => '0');
signal d2_count_2, d2_count_2_n : unsigned(WG_SIZE_W-1 downto 0) := (others => '0');
signal d0_count_1_ov, d1_count_1_ov_n : std_logic := '0';
signal d0_count_2_ov, d1_count_2_ov_n : std_logic := '0';
signal d1_count_1_ov, d0_count_1_ov_n : std_logic := '0';
signal d1_count_2_ov, d0_count_2_ov_n : std_logic := '0';
signal start_d0, start_d1, start_d2 : std_logic := '0';
signal stop_d0, stop_d1, stop_d2 : std_logic := '0';
signal wrAddr_sel_dim : unsigned(1 downto 0) := (others => '0');
signal wg_size_m1_d0 : unsigned(WG_SIZE_W downto 0) := (others=>'0');
signal wg_size_m1_d1 : unsigned(WG_SIZE_W downto 0) := (others=>'0');
signal wg_size_m1_d2 : unsigned(WG_SIZE_W downto 0) := (others=>'0');
-- next signals
-- signal we_d0_n, we_d1_n, we_d2_n : std_logic_vector(CV_SIZE/2-1 downto 0) := (others => '0');
signal we_d0_n, we_d1_n, we_d2_n : std_logic_vector(3 downto 0) := (others => '0');
signal finish_n : std_logic := '0';
-- }}}
begin
-- fixed assignments & internal signals ------------------------------------------------------------------{{{
wrAddr(wrAddr'high downto wrAddr'high-1) <= wrAddr_sel_dim; --alias
wrAddr(wrAddr'high-2 downto 0) <= count(wrAddr'high-2 downto 0); --alias
wg_size_m1_d0 <= to_unsigned(wg_size_d0, WG_SIZE_W+1) - 1;
wg_size_m1_d1 <= to_unsigned(wg_size_d1, WG_SIZE_W+1) - 1;
wg_size_m1_d2 <= to_unsigned(wg_size_d2, WG_SIZE_W+1) - 1;
finish <= finish_i;
---------------------------------------------------------------------------------------------------------}}}
------ d2 FSM -------------------------------------------------------------------------------------- {{{
process(state_d2, start_d2, d1_count_1_ov, d1_count_2_ov, d2_count_1, d2_count_2, d2_count_1_n, we_d2, stop_d2, d2, wg_size_m1_d2)
begin
nstate_d2 <= state_d2;
d2_count_1_n <= d2_count_1;
d2_count_2_n <= d2_count_2;
we_d2_n <= we_d2;
d2_n <= d2;
case state_d2 is
when idle =>
if start_d2 = '1' then
nstate_d2 <= inc;
we_d2_n <= (0 => '1', others => '0');
d2_count_1_n <= (others => '0');
d2_count_2_n <= (others => '0');
end if;
when inc =>
if d1_count_1_ov = '1' then
if d2_count_2 = wg_size_m1_d2(WG_SIZE_W-1 downto 0) then
d2_count_1_n <= (others => '0');
else
d2_count_1_n <= d2_count_2 + 1;
end if;
else
d2_count_1_n <= d2_count_2;
end if;
if d1_count_2_ov = '1' then
if d2_count_1_n = wg_size_m1_d2(WG_SIZE_W-1 downto 0) then
d2_count_2_n <= (others => '0');
else
d2_count_2_n <= d2_count_1_n + 1;
end if;
else
d2_count_2_n <= d2_count_1_n;
end if;
d2_we: for i in 0 to CV_SIZE/2-1 loop
if we_d2(i) = '1' then
d2_n((2+i*2)*WG_SIZE_W-1 downto 2*i*WG_SIZE_W) <= d2_count_2 & d2_count_1;
end if;
end loop;
we_d2_n <= we_d2(we_d2'high-1 downto 0) & we_d2(we_d2'high);
if stop_d2 = '1' then
nstate_d2 <= idle;
end if;
when empty_wg_size =>
end case;
end process;
---------------------------------------------------------------------------------------------------}}}
------ d1 FSM -------------------------------------------------------------------------------------- {{{
process(state_d1, start_d1, d0_count_1_ov, d0_count_2_ov, d1_count_1, d1_count_2, d1_count_1_n, we_d1, stop_d1, d1, wg_size_m1_d1,
wg_size_m1_d0)
begin
nstate_d1 <= state_d1;
d1_count_1_n <= d1_count_1;
d1_count_1_ov_n <= '0';
we_d1_n <= we_d1;
d1_n <= d1;
if CV_SIZE = 8 then
d1_count_2_ov_n <= '0';
d1_count_2_n <= d1_count_2;
end if;
case state_d1 is
when idle =>
if start_d1 = '1' then
nstate_d1 <= inc;
we_d1_n <= (0 => '1', others => '0');
d1_count_1_n <= (others => '0');
if CV_SIZE = 8 then
if wg_size_m1_d0 = (wg_size_m1_d0'reverse_range=>'0') then
d1_count_2_n <= (0 => '1', others => '0');
else
d1_count_2_n <= (others => '0');
end if;
end if;
end if;
when inc =>
if d0_count_1_ov = '1' then
if CV_SIZE = 8 then
if d1_count_2 = wg_size_m1_d1(WG_SIZE_W-1 downto 0) then
d1_count_1_n <= (others => '0');
d1_count_1_ov_n <= '1';
else
d1_count_1_n <= d1_count_2 + 1;
end if;
else -- CV_SIZE = 4
if d1_count_1 = wg_size_m1_d1(WG_SIZE_W-1 downto 0) then
d1_count_1_n <= (others => '0');
d1_count_1_ov_n <= '1';
else
d1_count_1_n <= d1_count_1 + 1;
end if;
end if;
else
if CV_SIZE = 8 then
d1_count_1_n <= d1_count_2;
else -- CV_SIZE=4
d1_count_1_n <= d1_count_1;
end if;
end if;
if CV_SIZE = 8 then
if d0_count_2_ov = '1' then
if d1_count_1_n = wg_size_m1_d1(WG_SIZE_W-1 downto 0) then
d1_count_2_n <= (others => '0');
d1_count_2_ov_n <= '1';
else
d1_count_2_n <= d1_count_1_n + 1;
end if;
else
d1_count_2_n <= d1_count_1_n;
end if;
end if;
if CV_SIZE = 8 then
for i in 0 to 3 loop
if we_d1(i) = '1' then
d1_n((2+i*2)*WG_SIZE_W-1 downto 2*i*WG_SIZE_W) <= d1_count_2 & d1_count_1;
end if;
end loop;
elsif CV_SIZE = 4 then
for i in 0 to 3 loop
if we_d1(i) = '1' then
d1_n((1+i)*WG_SIZE_W-1 downto i*WG_SIZE_W) <= d1_count_1;
end if;
end loop;
end if;
we_d1_n <= we_d1(we_d1'high-1 downto 0) & we_d1(we_d1'high);
if stop_d1 = '1' then
nstate_d1 <= idle;
end if;
when empty_wg_size =>
end case;
end process;
----------------------------------------------------------------------------------------------------}}}
------ d0 FSM -------------------------------------------------------------------------------------- {{{
process(state_d0, d0, we_d0, start_d0, stop_d0, d0_count_1, d0_count_2, d0_count_1_n, wg_size_m1_d0)
begin
nstate_d0 <= state_d0;
we_d0_n <= we_d0;
d0_n <= d0;
d0_count_1_n <= d0_count_1;
d0_count_1_ov_n <= '0';
if CV_SIZE = 8 then
d0_count_2_n <= d0_count_2;
d0_count_2_ov_n <= '0';
end if;
case state_d0 is
when idle =>
if start_d0 = '1' and wg_size_m1_d0 /= (wg_size_m1_d0'reverse_range=>'0')then
nstate_d0 <= inc;
we_d0_n <= (0 => '1', others => '0');
d0_count_1_n <= (others => '0');
if CV_SIZE = 8 then
d0_count_2_n <= (0 => '1', others => '0');
end if;
end if;
if start_d0 = '1' and wg_size_m1_d0 = (wg_size_m1_d0'reverse_range=>'0')then
nstate_d0 <= empty_wg_size;
d0_count_1_ov_n <= '1';
if CV_SIZE = 8 then
d0_count_2_ov_n <= '1';
end if;
end if;
when inc =>
if CV_SIZE = 8 then
d0_count_1_n <= d0_count_2 + 1;
if d0_count_2 = wg_size_m1_d0(WG_SIZE_W-1 downto 0) then
d0_count_1_n <= (others => '0');
d0_count_1_ov_n <= '1';
end if;
d0_count_2_n <= d0_count_1_n + 1;
if d0_count_1_n = wg_size_m1_d0(WG_SIZE_W-1 downto 0) then
d0_count_2_n <= (others => '0');
d0_count_2_ov_n <= '1';
end if;
for i in 0 to CV_SIZE/2-1 loop
if we_d0(i) = '1' then
d0_n((2+i*2)*WG_SIZE_W-1 downto 2*i*WG_SIZE_W) <= d0_count_2 & d0_count_1;
end if;
end loop;
elsif CV_SIZE = 4 then
d0_count_1_n <= d0_count_1 + 1;
if d0_count_1 = wg_size_m1_d0(WG_SIZE_W-1 downto 0) then
d0_count_1_n <= (others => '0');
d0_count_1_ov_n <= '1';
end if;
for i in 0 to 3 loop
if we_d0(i) = '1' then
d0_n((1+i)*WG_SIZE_W-1 downto i*WG_SIZE_W) <= d0_count_1;
end if;
end loop;
end if;
we_d0_n <= we_d0(we_d0'high-1 downto 0) & we_d0(we_d0'high);
if stop_d0 = '1' then
nstate_d0 <= idle;
end if;
when empty_wg_size =>
d0_count_1_ov_n <= '1';
if CV_SIZE = 8 then
d0_count_2_ov_n <= '1';
end if;
if stop_d0 = '1' then
nstate_d0 <= idle;
end if;
end case;
end process;
-------------------------------------------------------------------------------------------- }}}
------ overall state machine --------------------------------------------------------------------{{{
process(state, start, d0, d1, d2, count, count_n, n_wf_wg_m1, finish_i)
begin
nstate <= state;
count_n <= count;
start_d0 <= '0';
start_d1 <= '0';
start_d2 <= '0';
stop_d0 <= '0';
stop_d1 <= '0';
stop_d2 <= '0';
we <= '0';
wrData <= d0;
wrAddr_sel_dim <= "00";
finish_n <= finish_i;
case state is
when idle =>
if start = '1' then
count_n <= (others => '1');
nstate <= start_d0_gen;
start_d0 <= '1';
finish_n <= '0';
end if;
when start_d0_gen =>
start_d1 <= '1';
nstate <= start_d1_gen;
when start_d1_gen =>
start_d2 <= '1';
nstate <= start_d2_gen;
when start_d2_gen =>
nstate <= check;
when store_inc_d0 =>
nstate <= store_inc_d1;
wrData <= d0;
we <= '1';
wrAddr_sel_dim <= "00";
when store_inc_d1 =>
nstate <= store_inc_d2;
wrData <= d1;
we <= '1';
wrAddr_sel_dim <= "01";
when store_inc_d2 =>
nstate <= check;
wrData <= d2;
we <= '1';
wrAddr_sel_dim <= "10";
when check =>
count_n <= count + 1;
if count_n(WF_SIZE_W-CV_W+N_WF_CU_W downto WF_SIZE_W-CV_W) > n_wf_wg_m1 then
nstate <= idle;
stop_d0 <= '1';
stop_d1 <= '1';
stop_d2 <= '1';
finish_n <= '1';
else
nstate <= store_inc_d0;
end if;
end case;
end process;
-------------------------------------------------------------------------------------------------}}}
------ registers ---------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
count <= count_n;
we_d0 <= we_d0_n;
we_d1 <= we_d1_n;
we_d2 <= we_d2_n;
d0_count_1 <= d0_count_1_n;
if CV_SIZE = 8 then
d0_count_2 <= d0_count_2_n;
d1_count_2 <= d1_count_2_n;
d2_count_2 <= d2_count_2_n;
d0_count_2_ov <= d0_count_2_ov_n;
d1_count_2_ov <= d1_count_2_ov_n;
end if;
d1_count_1 <= d1_count_1_n;
d2_count_1 <= d2_count_1_n;
d0_count_1_ov <= d0_count_1_ov_n;
d0 <= d0_n;
d1 <= d1_n;
d2 <= d2_n;
d1_count_1_ov <= d1_count_1_ov_n;
if nrst = '0' then
state_d0 <= idle;
state_d1 <= idle;
state_d2 <= idle;
finish_i <= '0';
state <= idle;
else
state <= nstate;
state_d0 <= nstate_d0;
state_d1 <= nstate_d1;
state_d2 <= nstate_d2;
finish_i <= finish_n;
if clear_finish = '1' then
finish_i <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------}}}
end Behavioral;
| gpl-3.0 | 8113c1ff1d15bd41fd6ab4a7d9e9302b | 0.421778 | 3.0196 | false | false | false | false |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/nf/nf_rx_registers.vhd | 1 | 4,375 | -------------------------------------------------------------------------------
--! @file nf_rx_registers.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-22
--! @brief NanoFIP receiver registers.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.nf_pkg.all;
use work.cf_pkg.all;
--! @brief Entity declaration of nf_rx_registers
--! @details
--! The gateway is sending 32-bit long commands to the FGClite which are stored
--! in this register map. Each address is then assigned to internal control
--! signals.
entity nf_rx_registers is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name NanoFIP write interface
--! @{
--! Write enable
wr_en_i : in std_ulogic;
--! Address
addr_i : in std_ulogic_vector(1 downto 0);
--! Data
data_i : in std_ulogic_vector(31 downto 0);
--! @}
--! @name Registers
--! @{
--! Gateway commands
command_o : out nf_command_t);
--! @}
end entity nf_rx_registers;
--! RTL implementation of nf_rx_registers
architecture rtl of nf_rx_registers is
---------------------------------------------------------------------------
--! @name Types and Constants
---------------------------------------------------------------------------
--! @{
type reg_t is array (0 to 2**addr_i'length - 1) of std_ulogic_vector(data_i'range);
--! @}
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal reg : reg_t;
signal cmd1 : std_ulogic;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
-- Command 0
command_o.sefi_test_vs_m0 <= reg(0)(27 downto 26);
command_o.sefi_test_vs_m1 <= reg(0)(25 downto 24);
command_o.sefi_test_ia_m0 <= reg(0)(23 downto 22);
command_o.sefi_test_ia_m1 <= reg(0)(21 downto 20);
command_o.sefi_test_ib_m0 <= reg(0)(19 downto 18);
command_o.sefi_test_ib_m1 <= reg(0)(17 downto 16);
command_o.ms_period <= reg(0)(15 downto 0);
-- Command 1
command_o.serial_data <= reg(1);
command_o.serial_data_en <= cmd1;
-- Command 2
command_o.index <= reg(2)(30 downto 16);
command_o.index_type <= reg(2)(10 downto 8);
command_o.adc_log_freeze <= reg(2)(6);
command_o.dim_log_freeze <= reg(2)(5);
command_o.dim_reset <= reg(2)(4);
command_o.ow_scan <= reg(2)(3);
command_o.ow_bus_select <= reg(2)(2 downto 0);
-- Command 3
-- Had to flip signed bit for gateway
command_o.v_ref <= (not reg(3)(31)) & reg(3)(30 downto 16);
command_o.cal_source <= reg(3)(15 downto 14);
command_o.cal_vs_en <= reg(3)(13);
command_o.cal_ia_en <= reg(3)(12);
command_o.cal_ib_en <= reg(3)(11);
command_o.adc_vs_reset_n <= reg(3)(10);
command_o.adc_ia_reset_n <= reg(3)(9);
command_o.adc_ib_reset_n <= reg(3)(8);
command_o.vs_cmd <= reg(3)(7 downto 0);
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= (others => (others => '0'));
reg(0)(15 downto 0) <= ms_period_c;
reg(3)(10 downto 8) <= "111";
cmd1 <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
cmd1 <= '0';
if wr_en_i = '1' then
reg(to_integer(unsigned(addr_i))) <= data_i;
if to_integer(unsigned(addr_i)) = 1 then
cmd1 <= '1';
end if;
end if;
end if;
end if;
end process regs;
end architecture rtl;
| mit | bf43a068b3d08043f2170aa0c7bcddee | 0.469486 | 3.661088 | false | false | false | false |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fdiv_LMEM.vhd | 1 | 24,067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 | 172caeda3b92f7eb5789cd5488591d84 | 0.567707 | 3.729005 | false | false | false | false |
joalcava/sparcv8-monocicle | MuxDWR.vhd | 1 | 607 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MuxDWR is
Port ( DM : in STD_LOGIC_VECTOR(31 downto 0);
AluR : in STD_LOGIC_VECTOR(31 downto 0);
PC: in STD_LOGIC_VECTOR(31 downto 0);
RFSource: in STD_LOGIC_VECTOR(1 downto 0);
DTRF : out STD_LOGIC_VECTOR(31 downto 0)
);
end MuxDWR;
architecture Behavioral of MuxDWR is
begin
process(DM,AluR,RFSource)
begin
if(RFSource="00") then
DTRF<=AluR;
elsif (RFSource="01") then
DTRF<=DM;
elsif (RFsource="10") then
DTRF<=PC;
else
DTRF<=AluR;
end if;
end process;
end Behavioral;
| gpl-3.0 | 798c623d54a3a949bbf7152cf933a7f9 | 0.629325 | 2.918269 | false | false | false | false |
viccuad/fpga-thingies | cronometer/cronometer.vhd | 1 | 9,479 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cronometer is
port (
startStop: IN std_logic;
puesta0: IN std_logic;
clk: IN std_logic;
reset: IN std_logic; --reset activo a baja!
ampliacion: IN std_logic;
rightSegs: OUT std_logic_vector(6 downto 0);
leftSegs: OUT std_logic_vector(6 downto 0);
upSegs: OUT std_logic_vector(6 downto 0);
puntoSegs1: OUT std_logic;
puntoSegs2: OUT std_logic;
puntoSegs3: OUT std_logic
);
end cronometer;
architecture Behavioral of cronometer is
component debouncer
port ( rst: IN std_logic; --reset a 1!
clk: IN std_logic;
x: IN std_logic;
xDeb: OUT std_logic;
xDebFallingEdge: OUT std_logic;
xDebRisingEdge: OUT std_logic
);
end component;
signal startStop2: std_logic;
signal puesta02: std_logic;
signal start: std_logic; -- biestable T: 1 cuando cuente, 0 cuando no cuente
signal cuentacont1: STD_LOGIC_VECTOR(23 downto 0); --contador1decima
signal fin_cuenta1: STD_LOGIC;
signal cuentacont2: STD_LOGIC_VECTOR(3 downto 0); --contador decimas de segundo
signal fin_cuenta2: STD_LOGIC;
signal cuentacont3: STD_LOGIC_VECTOR(3 downto 0); --contador unidades de segundo
signal fin_cuenta3: STD_LOGIC;
signal cuentacont4: STD_LOGIC_VECTOR(3 downto 0); --contador decenas de segundo
signal fin_cuenta4: STD_LOGIC;
signal cuentacont5: STD_LOGIC_VECTOR(3 downto 0); --contador unidades de minuto
signal fin_cuenta5: STD_LOGIC;
signal cuentacont6: STD_LOGIC_VECTOR(3 downto 0); --contador decenas de minuto
signal fin_cuenta6: STD_LOGIC;
signal senialpunto: STD_LOGIC;
signal cuenta_segs_right: STD_LOGIC_VECTOR(3 downto 0);
signal cuenta_segs_left: STD_LOGIC_VECTOR(3 downto 0);
begin
norebotes1: debouncer port map ( rst => reset,
clk => clk,
x => startStop,
xDeb => open,
xDebFallingEdge => startStop2,
xDebRisingEdge => open
);
norebotes2: debouncer port map ( rst => reset,
clk => clk,
x => puesta0,
xDeb => open,
xDebFallingEdge => puesta02,
xDebRisingEdge => open
);
contador1decima: process(reset,clk,startStop2,puesta02) --contador mod 10.000.000 (de 0 a 9.999.999)
begin
if(reset = '0')then
cuentacont1 <= (others => '0');
fin_cuenta1 <= '0';
start <= '0';
senialpunto <= '0';
elsif(clk'event and clk = '1') then
if (startStop2 = '1') then --biestable T
start <= not start;
end if;
if (puesta02 = '1') then
cuentacont1 <= (others => '0');
fin_cuenta1 <= '0';
elsif (start = '1' and cuentacont1 /= "100110001001011001111111") then
cuentacont1 <= cuentacont1 + 1;
fin_cuenta1 <= '0';
elsif (start = '1' and cuentacont1 = "100110001001011001111111") then
fin_cuenta1 <= '1';
senialpunto <= not senialpunto;
puntoSegs1 <= senialpunto;
puntoSegs2 <= senialpunto;
puntoSegs3 <= senialpunto;
cuentacont1 <= (others => '0');
end if;
if (fin_cuenta1 = '1') then
fin_cuenta1 <= '0';
end if;
end if;
end process contador1decima;
contador_decimas: process(reset,clk,puesta02,fin_cuenta1) --contador mod 10 (de 0 a 9)
begin
if(reset = '0')then
cuentacont2 <= (others => '0');
fin_cuenta2 <= '0';
elsif(clk'event and clk = '1') then
if (puesta02 = '1') then
cuentacont2 <= (others => '0');
fin_cuenta2 <= '0';
elsif (fin_cuenta1 = '1' and cuentacont2 /= "1001") then
cuentacont2 <= cuentacont2 + 1;
fin_cuenta2 <= '0';
elsif (fin_cuenta1 = '1' and cuentacont2 = "1001") then
fin_cuenta2 <= '1';
cuentacont2 <= (others => '0');
end if;
if (fin_cuenta2 = '1') then
fin_cuenta2 <= '0';
end if;
end if;
end process contador_decimas;
contador_uds_seg: process(reset,clk,puesta02,fin_cuenta2) --contador mod 10 (de 0 a 9)
begin
if(reset = '0')then
cuentacont3 <= (others => '0');
fin_cuenta3 <= '0';
elsif(clk'event and clk = '1') then
if (puesta02 = '1') then
cuentacont3 <= (others => '0');
fin_cuenta3 <= '0';
elsif (fin_cuenta2 = '1' and cuentacont3 /= "1001") then
cuentacont3 <= cuentacont3 + 1;
fin_cuenta3 <= '0';
elsif (fin_cuenta2 = '1' and cuentacont3 = "1001") then
fin_cuenta3 <= '1';
cuentacont3 <= (others => '0');
end if;
if (fin_cuenta3 = '1') then
fin_cuenta3 <= '0';
end if;
end if;
end process contador_uds_seg;
contador_decenas_seg: process(reset,clk,puesta02,fin_cuenta3) --contador mod 6 (de 0 a 5)
begin
if(reset = '0')then
cuentacont4 <= (others => '0');
fin_cuenta4 <= '0';
elsif(clk'event and clk = '1') then
if (puesta02 = '1') then
cuentacont4 <= (others => '0');
fin_cuenta4 <= '0';
elsif (fin_cuenta3 = '1' and cuentacont4 /= "0101") then
cuentacont4 <= cuentacont4 + '1';
fin_cuenta4 <= '0';
elsif (fin_cuenta3 = '1' and cuentacont4 = "0101") then
fin_cuenta4 <= '1';
cuentacont4 <= (others => '0');
end if;
if (fin_cuenta4 = '1') then
fin_cuenta4 <= '0';
end if;
end if;
end process contador_decenas_seg;
contador_uds_minuto: process(reset,clk,puesta02,fin_cuenta4) --contador mod 10 (de 0 a 9)
begin
if(reset = '0')then
cuentacont5 <= (others => '0');
fin_cuenta5 <= '0';
elsif(clk'event and clk = '1') then
if (puesta02 = '1') then
cuentacont5 <= (others => '0');
fin_cuenta5 <= '0';
elsif (fin_cuenta4 = '1' and cuentacont5 /= "1001") then
cuentacont5 <= cuentacont5 + '1';
fin_cuenta5 <= '0';
elsif (fin_cuenta4 = '1' and cuentacont5 = "1001") then
fin_cuenta5 <= '1';
cuentacont5 <= (others => '0');
end if;
if (fin_cuenta5 = '1') then
fin_cuenta5 <= '0';
end if;
end if;
end process contador_uds_minuto;
contador_decenas_minuto: process(reset,clk,puesta02,fin_cuenta5) --contador mod 6 (de 0 a 5)
begin
if(reset = '0')then
cuentacont6 <= (others => '0');
fin_cuenta6 <= '0';
elsif(clk'event and clk = '1') then
if (puesta02 = '1') then
cuentacont6 <= (others => '0');
fin_cuenta6 <= '0';
elsif (fin_cuenta5 = '1' and cuentacont6 /= "0101") then
cuentacont6 <= cuentacont6 + '1';
fin_cuenta6 <= '0';
elsif (fin_cuenta5 = '1' and cuentacont6 = "0101") then
fin_cuenta6 <= '1';
cuentacont6 <= (others => '0');
end if;
if (fin_cuenta6 = '1') then
fin_cuenta6 <= '0';
end if;
end if;
end process contador_decenas_minuto;
conv7segRight: process(cuenta_segs_right)
begin
case cuenta_segs_right is
-- gfedcba
when "0000" => rightSegs <= "0111111";
when "0001" => rightSegs <= "0000110";
when "0010" => rightSegs <= "1011011";
when "0011" => rightSegs <= "1001111";
when "0100" => rightSegs <= "1100110";
when "0101" => rightSegs <= "1101101";
when "0110" => rightSegs <= "1111101";
when "0111" => rightSegs <= "0000111";
when "1000" => rightSegs <= "1111111";
when "1001" => rightSegs <= "1100111";
when "1010" => rightSegs <= "1110111";
when "1011" => rightSegs <= "1111100";
when "1100" => rightSegs <= "0111001";
when "1101" => rightSegs <= "1011110";
when "1110" => rightSegs <= "1111001";
when "1111" => rightSegs <= "1110001";
when OTHERS => rightSegs <= "1111001"; -- error
end case;
end process;
conv7segLeft: process(cuenta_segs_left)
begin
case cuenta_segs_left is
-- gfedcba
when "0000" => leftSegs <= "0111111";
when "0001" => leftSegs <= "0000110";
when "0010" => leftSegs <= "1011011";
when "0011" => leftSegs <= "1001111";
when "0100" => leftSegs <= "1100110";
when "0101" => leftSegs <= "1101101";
when "0110" => leftSegs <= "1111101";
when "0111" => leftSegs <= "0000111";
when "1000" => leftSegs <= "1111111";
when "1001" => leftSegs <= "1100111";
when "1010" => leftSegs <= "1110111";
when "1011" => leftSegs <= "1111100";
when "1100" => leftSegs <= "0111001";
when "1101" => leftSegs <= "1011110";
when "1110" => leftSegs <= "1111001";
when "1111" => leftSegs <= "1110001";
when OTHERS => leftSegs <= "1111001"; -- error
end case;
end process;
conv7segUp: process(cuentacont2)
begin
case cuentacont2 is
-- gfedcba
when "0000" => upSegs <= "0111111";
when "0001" => upSegs <= "0000110";
when "0010" => upSegs <= "1011011";
when "0011" => upSegs <= "1001111";
when "0100" => upSegs <= "1100110";
when "0101" => upSegs <= "1101101";
when "0110" => upSegs <= "1111101";
when "0111" => upSegs <= "0000111";
when "1000" => upSegs <= "1111111";
when "1001" => upSegs <= "1100111";
when "1010" => upSegs <= "1110111";
when "1011" => upSegs <= "1111100";
when "1100" => upSegs <= "0111001";
when "1101" => upSegs <= "1011110";
when "1110" => upSegs <= "1111001";
when "1111" => upSegs <= "1110001";
when OTHERS => upSegs <= "1111001"; -- error
end case;
end process;
segunda_parte: process(ampliacion)
begin
if (ampliacion = '0') then
cuenta_segs_right <= cuentacont3;
cuenta_segs_left <= cuentacont4;
else
cuenta_segs_right <= cuentacont5;
cuenta_segs_left <= cuentacont6;
end if;
end process;
end Behavioral;
| gpl-3.0 | cd70edf660f8f415ce2c6f8902234561 | 0.590885 | 3.099738 | false | false | false | false |