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malkadi/FGPU

RTL/floating_point/fmul.vhd

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.1 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY fmul IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END fmul; ARCHITECTURE fmul_arch OF fmul IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF fmul_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_1_2 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER; C_FIXED_DATA_UNSIGNED : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_1_2; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_1_2 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 1, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 8, C_OPTIMIZATION => 1, C_MULT_USAGE => 2, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 0, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1, C_FIXED_DATA_UNSIGNED => 0 ) PORT MAP ( aclk => aclk, aclken => '1', aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END fmul_arch;

gpl-3.0

51eadc17385f1b2f8c673bdac989a84e

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_float_8ALUs_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

4bf42eec09d2799d79016980c8054233

Kinxil/VHDL_Projects

Mandelbrot/cpt_iter.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.CONSTANTS.all; use work.CONFIG_MANDELBROT.all; entity cpt_iter is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; inib : in std_logic; endcalcul : in STD_LOGIC; maxiter : in STD_LOGIC; iter : out STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0)); end cpt_iter; architecture Behavioral of cpt_iter is Signal iterS : unsigned(ITER_RANGE-1 downto 0); begin process(reset,clock) begin if reset='1' then iterS<=to_unsigned(5,ITER_RANGE); elsif rising_edge(clock) then if maxiter = '1' then iterS <= to_unsigned(ITER_MAX,ITER_RANGE); elsif inib = '1' then if endcalcul ='1' then if iterS < (ITER_MAX-10) then iterS<=iterS+1; else iterS<=to_unsigned(10,ITER_RANGE); end if; end if; end if; end if; end process; iter<=std_logic_vector(iterS); end Behavioral;

gpl-3.0

47e1e04b1d0e8c2f67d10dec8ff46bed

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_fsqrt_uitofp.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 3; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

20fde2ec2a04026663c15c3fa01642d6

malkadi/FGPU

RTL/CU_instruction_dispatcher.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity CU_instruction_dispatcher is --{{{ port( clk, nrst : in std_logic; cram_rqst : out std_logic := '0'; cram_rdAddr : out unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdAddr_conf : in unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdData : in std_logic_vector(DATA_W-1 downto 0); -- cram_rdData is delayed by 1 clock cycle to cram_rdAddr_conf PC_indx : in integer range 0 to N_WF_CU-1; --response in two clk cycles wf_active : in std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); pc_updated : in std_logic_vector(N_WF_CU-1 downto 0); PCs : in CRAM_ADDR_ARRAY(N_WF_CU-1 downto 0); pc_rdy : out std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); instr : out std_logic_vector(DATA_W-1 downto 0) := (others => '0'); -- 1 clock cycle delayed after pc_rdy instr_gmem_op : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_scratchpad_ld : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_gmem_read : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_branch : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_jump : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_fpu : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); branch_distance : out branch_distance_vec(0 to N_WF_CU-1) := (others=>(others=>'0')); wf_retired : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0') ); end CU_instruction_dispatcher; -- }}} architecture Behavioral of CU_instruction_dispatcher is -- internal signals definitions {{{ signal cram_rdAddr_i : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal pc_rdy_i : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_retired_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_gmem_op_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_scratchpad_ld_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_branch_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_jump_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_fpu_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_gmem_read_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal branch_distance_i : branch_distance_vec(0 to N_WF_CU-1) := (others=>(others=>'0')); -- }}} -- signals definitions {{{ type st_cram_type is (request, wait_resp, check); type instr_vec_type is array (N_WF_CU-1 downto 0) of std_logic_vector(DATA_W-1 downto 0); -- global FSM signals signal instr_vec, instr_vec_n : instr_vec_type := (others=>(others=>'0')); signal st_cram, st_cram_n : st_cram_type := check; signal cram_ack : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); -- next signals signal cram_rdAddr_n : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal pc_rdy_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal cram_rdData_gmem_op : std_logic := '0'; signal instr_gmem_op_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_scratchpad_ld_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_branch_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_jump_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_fpu_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_gmem_read_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_retired_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal branch_distance_n : branch_distance_vec(0 to N_WF_CU-1) := (others=>(others=>'0')); -- }}} begin -- internal signals -------------------------------------------------------------------------------------{{{ cram_rdAddr <= cram_rdAddr_i; pc_rdy <= pc_rdy_i; wf_retired <= wf_retired_i; instr_gmem_op <= instr_gmem_op_i; instr_scratchpad_ld <= instr_scratchpad_ld_i; instr_gmem_read <= instr_gmem_read_i; instr_branch <= instr_branch_i; instr_jump <= instr_jump_i; instr_fpu <= instr_fpu_i; branch_distance <= branch_distance_i; ---------------------------------------------------------------------------------------------------------}}} -- cram FSM ----------------------------------------------------------------------------------- {{{ process(clk) begin if rising_edge(clk) then if nrst = '0' then st_cram <= check; instr_gmem_op_i <= (others=>'0'); instr_scratchpad_ld_i <= (others=>'0'); instr_branch_i <= (others=>'0'); instr_jump_i <= (others=>'0'); instr_fpu_i <= (others=>'0'); branch_distance_i <= (others=>(others=>'0')); instr_gmem_read_i <= (others=>'0'); wf_retired_i <= (others=>'0'); pc_rdy_i <= (others=>'0'); cram_rdAddr_i <= (others=>'0'); instr_vec <= (others=>(others=>'0')); instr <= (others=>'0'); else st_cram <= st_cram_n; pc_rdy_i <= pc_rdy_n; cram_rdAddr_i <= cram_rdAddr_n; instr_vec <= instr_vec_n; instr <= instr_vec(PC_indx); instr_gmem_op_i <= instr_gmem_op_n; instr_scratchpad_ld_i <= instr_scratchpad_ld_n; branch_distance_i <= branch_distance_n; instr_branch_i <= instr_branch_n; instr_jump_i <= instr_jump_n; instr_fpu_i <= instr_fpu_n; instr_gmem_read_i <= instr_gmem_read_n; wf_retired_i <= wf_retired_n; cram_ack <= (others=>'0'); for i in 0 to N_WF_CU-1 loop if pc_rdy_i(i) = '0' and pc_updated(i) = '0' and PCs(i) = cram_rdAddr_conf and wf_active(i) = '1' then cram_ack(i) <= '1'; end if; end loop; -- for i in 0 to N_WF_CU-1 loop -- if wf_activate(i) = '1' then -- wf_active(i) <= '1'; -- elsif wf_retired_i(i) = '1' then -- wf_active(i) <= '0'; -- end if; -- end loop; end if; end if; end process; WFs_bufs: for i in 0 to N_WF_CU-1 generate begin WF_buf: process(pc_updated(i), pc_rdy_i(i), cram_rdData, instr_vec(i), wf_retired_i(i), instr_gmem_op_i(i), instr_branch_i(i), instr_gmem_read_i(i), branch_distance_i(i), cram_ack(i), instr_jump_i(i), instr_fpu_i(i), instr_scratchpad_ld_i(i)) begin pc_rdy_n(i) <= pc_rdy_i(i); instr_vec_n(i) <= instr_vec(i); wf_retired_n(i) <= wf_retired_i(i); instr_gmem_op_n(i) <= instr_gmem_op_i(i); instr_scratchpad_ld_n(i) <= instr_scratchpad_ld_i(i); branch_distance_n(i) <= branch_distance_i(i); instr_branch_n(i) <= instr_branch_i(i); instr_jump_n(i) <= instr_jump_i(i); instr_fpu_n(i) <= instr_fpu_i(i); instr_gmem_read_n(i) <= instr_gmem_read_i(i); -- if wf_active(i) = '0' then -- wf_retired_n(i) <= '0'; -- end if; if pc_updated(i) = '1' then pc_rdy_n(i) <= '0'; elsif cram_ack(i) = '1' then instr_vec_n(i) <= cram_rdData; instr_gmem_op_n(i) <= '0'; instr_gmem_read_n(i) <= '0'; instr_branch_n(i) <= '0'; instr_jump_n(i) <= '0'; instr_fpu_n(i) <= '0'; pc_rdy_n(i) <= '1'; wf_retired_n(i) <= '0'; instr_scratchpad_ld_n(i) <= '0'; case cram_rdData(FAMILY_POS+FAMILY_W-1 downto FAMILY_POS) is when GLS_FAMILY => instr_gmem_op_n(i) <= '1'; instr_gmem_read_n(i) <= not cram_rdData(CODE_POS+CODE_W-1); when ATO_FAMILY => instr_gmem_op_n(i) <= '1'; instr_gmem_read_n(i) <= '1'; when BRA_FAMILY => if cram_rdData(CODE_POS+CODE_W-1 downto CODE_POS) = JSUB then instr_jump_n(i) <= '1'; else instr_branch_n(i) <= '1'; end if; branch_distance_n(i) <= unsigned(cram_rdData(BRANCH_ADDR_POS+BRANCH_ADDR_W-1 downto BRANCH_ADDR_POS)); when CTL_FAMILY => if cram_rdData(CODE_POS+CODE_W-1 downto CODE_POS) = RET then wf_retired_n(i) <= '1'; end if; when LSI_FAMILY => instr_scratchpad_ld_n(i) <= not cram_rdData(CODE_POS+CODE_W-1); when FLT_FAMILY => instr_fpu_n(i) <= '1'; when others => end case; end if; end process; end generate; process(st_cram, cram_rdAddr_i, cram_rdAddr_conf, pc_rdy_i, wf_active, PCs) begin cram_rdAddr_n <= cram_rdAddr_i; cram_rqst <= '0'; st_cram_n <= st_cram; case st_cram is when check => for i in 0 to N_WF_CU-1 loop if wf_active(i)='1' and pc_rdy_i(i)='0' then st_cram_n <= request; cram_rdAddr_n <= PCs(i); end if; end loop; when request => cram_rqst <= '1'; st_cram_n <= wait_resp; when wait_resp => cram_rqst <= '1'; if cram_rdAddr_conf = cram_rdAddr_i then st_cram_n <= check; cram_rqst <= '0'; end if; end case; end process; ---------------------------------------------------------------------------------------------------------}}} end Behavioral;

gpl-3.0

a9a2f45df88b09bf35c95c9cee5bb24b

preusser/q27

src/vhdl/PoC/xilinx/xil_SystemMonitor_Virtex6.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: System Monitor wrapper for temperature supervision applications -- -- Description: -- ------------------------------------ -- This module wraps a Virtex-6 System Monitor primitive to report if preconfigured -- temperature values are overrun. -- -- Temperature curve: -- ------------------ -- -- | /-----\ -- Temp_ov on=80 | - - - - - - /-------/ \ -- | / | \ -- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ -- | / | \ -- | / | | \ -- Temp_us on=35 | - /---/ | | \ -- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\ -- | / | | | \ -- ----------------|--------|------------|--------------|----------|--------- -- pwm = | min | medium | max | medium | min -- -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.NUMERIC_STD.all; LIBRARY UniSim; USE UniSim.vComponents.ALL; entity xil_SystemMonitor_Virtex6 is port ( Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output Alarm : out STD_LOGIC; -- OR'ed output of all the Alarms VP : in STD_LOGIC; -- Dedicated Analog Input Pair VN : in STD_LOGIC ); end; architecture xilinx of xil_SystemMonitor_Virtex6 is signal FLOAT_VCCAUX_ALARM : STD_LOGIC; signal FLOAT_VCCINT_ALARM : STD_LOGIC; signal aux_channel_p : STD_LOGIC_VECTOR(15 downto 0); signal aux_channel_n : STD_LOGIC_VECTOR(15 downto 0); signal SysMonitor_Alarm : STD_LOGIC_VECTOR(2 downto 0); signal SysMonitor_OverTemp : STD_LOGIC; begin genAUXChannel : for i in 0 to 15 generate aux_channel_p(i) <= '0'; aux_channel_n(i) <= '0'; end generate; SysMonitor : SYSMON generic map ( INIT_40 => x"0000", -- config reg 0 INIT_41 => x"300c", -- config reg 1 INIT_42 => x"0a00", -- config reg 2 INIT_48 => x"0100", -- Sequencer channel selection INIT_49 => x"0000", -- Sequencer channel selection INIT_4A => x"0000", -- Sequencer Average selection INIT_4B => x"0000", -- Sequencer Average selection INIT_4C => x"0000", -- Sequencer Bipolar selection INIT_4D => x"0000", -- Sequencer Bipolar selection INIT_4E => x"0000", -- Sequencer Acq time selection INIT_4F => x"0000", -- Sequencer Acq time selection INIT_50 => x"a418", -- Temp alarm trigger INIT_51 => x"5999", -- Vccint upper alarm limit INIT_52 => x"e000", -- Vccaux upper alarm limit INIT_53 => x"b363", -- Temp alarm OT upper INIT_54 => x"9c87", -- Temp alarm reset INIT_55 => x"5111", -- Vccint lower alarm limit INIT_56 => x"caaa", -- Vccaux lower alarm limit INIT_57 => x"a425", -- Temp alarm OT reset SIM_DEVICE => "VIRTEX6", SIM_MONITOR_FILE => "SystemMonitor_sim.txt" ) port map ( -- Control and Clock RESET => Reset, CONVSTCLK => '0', CONVST => '0', -- DRP port DCLK => '0', DEN => '0', DADDR => "0000000", DWE => '0', DI => x"0000", DO => open, DRDY => open, -- External analog inputs VAUXN => aux_channel_n(15 downto 0), VAUXP => aux_channel_p(15 downto 0), VN => VN, VP => VP, -- Alarms OT => SysMonitor_OverTemp, ALM => SysMonitor_Alarm, -- Status CHANNEL => open, BUSY => open, EOC => open, EOS => open, JTAGBUSY => open, JTAGLOCKED => open, JTAGMODIFIED => open ); Alarm_UserTemp <= SysMonitor_Alarm(0); Alarm_OverTemp <= SysMonitor_OverTemp; Alarm <= SysMonitor_Alarm(0) or SysMonitor_OverTemp; end;

agpl-3.0

d1eef6130d2fe5c57ac20109d57f6d82

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_2CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

1426be4e6fdf5b9c0d6fe9b113384af1

jpidancet/mips

rtl/mips_defs.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; package mips_defs is subtype mips_opcode_type is std_logic_vector(5 downto 0); subtype mips_func_type is std_logic_vector(5 downto 0); constant OP_SPECIAL : std_logic_vector(5 downto 0) := "000000"; constant OP_J : std_logic_vector(5 downto 0) := "000010"; constant OP_JAL : std_logic_vector(5 downto 0) := "000011"; constant OP_BEQ : std_logic_vector(5 downto 0) := "000100"; constant OP_BNE : std_logic_vector(5 downto 0) := "000101"; constant OP_ADDI : std_logic_vector(5 downto 0) := "001000"; constant OP_ADDIU : std_logic_vector(5 downto 0) := "001001"; constant OP_SLTI : std_logic_vector(5 downto 0) := "001010"; -- Not implemented constant OP_SLTIU : std_logic_vector(5 downto 0) := "001011"; -- Not implemented constant OP_ANDI : std_logic_vector(5 downto 0) := "001100"; constant OP_ORI : std_logic_vector(5 downto 0) := "001101"; constant OP_LUI : std_logic_vector(5 downto 0) := "001111"; constant OP_LB : std_logic_vector(5 downto 0) := "100000"; -- Not implemented constant OP_LW : std_logic_vector(5 downto 0) := "100011"; constant OP_LBU : std_logic_vector(5 downto 0) := "100100"; -- Not implemented constant OP_LHU : std_logic_vector(5 downto 0) := "100101"; -- Not implemented constant OP_SB : std_logic_vector(5 downto 0) := "101000"; -- Not implemented constant OP_SH : std_logic_vector(5 downto 0) := "101001"; -- Not implemented constant OP_SW : std_logic_vector(5 downto 0) := "101011"; constant OP_LL : std_logic_vector(5 downto 0) := "110000"; -- Not implemented constant OP_SC : std_logic_vector(5 downto 0) := "111000"; -- Not implemented constant FUNC_SLL : std_logic_vector(5 downto 0) := "000000"; constant FUNC_SRL : std_logic_vector(5 downto 0) := "000010"; constant FUNC_JR : std_logic_vector(5 downto 0) := "001000"; constant FUNC_JALR : std_logic_vector(5 downto 0) := "001001"; constant FUNC_ADD : std_logic_vector(5 downto 0) := "100000"; constant FUNC_ADDU : std_logic_vector(5 downto 0) := "100001"; constant FUNC_SUB : std_logic_vector(5 downto 0) := "100010"; constant FUNC_SUBU : std_logic_vector(5 downto 0) := "100011"; constant FUNC_AND : std_logic_vector(5 downto 0) := "100100"; constant FUNC_OR : std_logic_vector(5 downto 0) := "100101"; constant FUNC_XOR : std_logic_vector(5 downto 0) := "100110"; constant FUNC_NOR : std_logic_vector(5 downto 0) := "100111"; constant FUNC_SLT : std_logic_vector(5 downto 0) := "101010"; constant FUNC_SLTU : std_logic_vector(5 downto 0) := "101011"; type branch_type is (NO_BRANCH, BRANCH_COND, JUMP_IMM, JUMP_REG); type extend_type is (ZERO_EXTEND, SIGN_EXTEND, SHIFT16_EXTEND); type compare_type is (CMP_EQUAL, CMP_NOT_EQUAL, CMP_GREATER, CMP_GREATER_OR_EQUAL, CMP_LESS, CMP_LESS_OR_EQUAL); type alucontrol_type is (ALU_SLL, ALU_SRL, ALU_AND, ALU_XOR, ALU_NOR, ALU_OR, ALU_ADD, ALU_SUB, ALU_SLT, ALU_SLTU, ALU_BPLUS4); end package mips_defs; package body mips_defs is end package body;

isc

aa8023f06d541d6a8209ed69329f0d49

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block EIETZ7UK7lfplDojE4n5WPNAryn8z5Wc+1BTkcg69ivZMCRGBEfqKjKHJvs30LurLDIebMZGGHcU tEjXTQIrgw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bliHcf+gORUPPdEOE6rjelOdtaoTDhkNBJUOhkpslrhO6f6fDW1wZaGnqTS0dbTm/QdTTbbE5bRZ Bh003AVXLhtg1Wx0P0E38fmm4P53hLTvBhsXMnqRhLWlqadGEo+Q6ndqz8kqtCsLYBxFN+eu7pH0 XyqyfpvTp809sOH7/fo= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block D+VuRj9jaC8AiPi8Sd3qOIoBoxKORaT/umCd8xcQOycWfsefjCwX5SQ8i5fZsX7DgbP3xdolpmVS VL4DZcI9u3CiI2zdMklVsa5DJCFZ7qEp4BzinYK27TFKWhO3Ed/Mw6mLx0ow9Pat5PUsSvHPcuc2 0++ZeMNNGt4Z4LxtOOrZxi8Ay3Tr4Or4H7KKXUgXbJ+DHGxFK9khj7f8gqevodil7OXSE8xKreRh XooweCViPOysSBFiprn6H2dGOkRr7Qnf2tjbfc7+oSsyDIyE0/XIsshTyEYLDUdNn92IyH6fZjoI kmMp+LQPKsoVzpL2FPZU9j9Bb/9fbIUFzHUHPg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block TO0GJA6Kj0jscSfgpS0eKy0wVhSYrOg2z8wAbCKOH2UXjmBtYOiqhC5Q11FVWEzGrk51O3tKndHm fz1egOTPQEdtz++uURrMdc5m3K84dbif7qqEr8v4htZP4/SzFOP5LQwcz4GURvHDKgoDJ0oxSYhI DOsMiv6o+6JUcp6rxdU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block F3nCjmvjKXhHEv1EgYNA28jt1eEpJAP7AVVkTb9WWB7z8f4/W/SF0tyvejkOWZ8eLD7jOqzqp5ay ZocThw3RZuF9PCAnUmwjFI21TC2bVbXrHDGpV21k42IGkY/lo9nKXkKMycFQ6kW8rc6zkJJugJ6U 8afgCfujFv8gA2HTilb/pcSDLTBbtqdDLFtB0TDYyLKZ7VCn/kFoE8iKENZGA5LDL1PfSsSDFycV 5o4Cp6sw9VFg2z66UY8caZ9v+kirY6+mK0wcEgD9pexDObZIJrQMhFbzmFIlYqUeRRJEbGJcwZyo 1ZUuD8/TyG3bAbtWpB+5E/sdTGmNaBTpq4pBQA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168) `protect data_block E0z4uQiW6OKQNQ+nz/PRqkfhDZnqUjQISVeh3D4Yu4seQNwnncEL7pskkdXIVZR+abtQ58h2NbCu aQc2GiaoDkzpubZ2vMHfrA1ByzDrfipGUDE/MLzDpTJ9M/0O2NAyksHXTceTCsebzCBclqaVk0XC 9UkprjhKJeWjoMWBw5scDjRC8Y8iqMZ51LEPBjzGJol1u/kGGycHh7/mkeyWXUVPOpSphDk9MzVv PMuE5QlAU6q6f1kuyfKpfEJiOXescJr7QT1V2ZCg9GYebY/kO3Hzz7OcPFsBWHrPTMXHKmUHEYTT JFOOpkEJL+cgI97sooAg3cqIqasUytLXBMZDxuBQC3eciD4aI3NQuy1IU0HNbHfDYz5r7bDxDg/1 Cekt8vIMFFX5RFfsvtPx/nOJaQioWrQqOet0a7CY4WGD7yUvbHfzCu77sDKWadBlF0YjN5px6j9O YtgqhJ76SEw5zF+hBm9am9yI7LurrJbhliU/yE2TxTyD53pWkH/EmlX/Oyf2ssuYIfecF9MGO3Py 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mit

6c7a32c885f78d562f59ef0102b884af

wltr/cern-fgclite

critical_fpga/src/rtl/cf/nf/nf_transmitter.vhd

------------------------------------------------------------------------------- --! @file nf_transmitter.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-23 --! @brief NanoFIP transmitter. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.nf_pkg.all; --! @brief Entity declaration of nf_transmitter --! @details --! All critical registers and the paged memory are concatenated and --! transmitted to the gateway. entity nf_transmitter is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Control signals --! @{ --! Start transmission start_i : in std_ulogic; --! @} --! @name Transmitter --! @{ --! Address tx_addr_o : out std_ulogic_vector(6 downto 0); --! Data tx_data_o : out std_ulogic_vector(7 downto 0); --! Data enable tx_data_en_o : out std_ulogic; --! Busy flag tx_busy_i : in std_ulogic; --! Done flag tx_done_i : in std_ulogic; --! @} --! @name Memory --! @{ --! Read enable mem_rd_en_o : out std_ulogic; --! Address mem_addr_o : out std_ulogic_vector(6 downto 0); --! Data mem_data_i : in std_ulogic_vector(7 downto 0); --! Data enable mem_data_en_i : in std_ulogic); --! @} end entity nf_transmitter; --! RTL implementation of nf_transmitter architecture rtl of nf_transmitter is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ constant nf_addr_offset_c : natural := 2; constant num_bytes_c : natural := 124; --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal addr : unsigned(tx_addr_o'range); signal rd_en : std_ulogic; signal busy : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- tx_addr_o <= std_ulogic_vector(addr + nf_addr_offset_c); tx_data_o <= mem_data_i; tx_data_en_o <= mem_data_en_i; mem_rd_en_o <= rd_en; mem_addr_o <= std_ulogic_vector(addr); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin addr <= to_unsigned(0, addr'length); rd_en <= '0'; busy <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else -- Defaults rd_en <= '0'; if busy = '0' and tx_busy_i = '0' and start_i = '1' then rd_en <= '1'; busy <= '1'; elsif busy = '1' and tx_done_i = '1' then busy <= '0'; if to_integer(addr) < num_bytes_c - 1 then rd_en <= '1'; busy <= '1'; end if; end if; if start_i = '1' then addr <= to_unsigned(0, addr'length); elsif tx_done_i = '1' then addr <= addr + 1; end if; end if; end if; end process regs; end architecture rtl;

mit

0496a48fdbd4ed236824656e758d6b3b

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fmul_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

722b2b97158fd9d1354d6d49ccae1ef7

Ttl/fsm_uart

examples/echo_tb.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY echo_tb IS END echo_tb; ARCHITECTURE behavior OF echo_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT echo PORT( rx : IN std_logic; tx : OUT std_logic; clk : IN std_logic ); END COMPONENT; component uart is generic ( CLK_FREQ : integer := 32; -- Main frequency (MHz) SER_FREQ : integer := 115200 -- Baud rate (bps) ); port ( -- Control clk : in std_logic; -- Main clock rst : in std_logic; -- Main reset -- External Interface rx : in std_logic; -- RS232 received serial data tx : out std_logic; -- RS232 transmitted serial data -- uPC Interface tx_req : in std_logic; -- Request SEND of data tx_end : out std_logic; -- Data SENDED tx_data : in std_logic_vector(7 downto 0); -- Data to transmit rx_ready : out std_logic; -- Received data ready to uPC read rx_data : out std_logic_vector(7 downto 0) -- Received data ); end component; --Inputs signal rx : std_logic := '0'; signal clk : std_logic := '0'; --Outputs signal tx : std_logic; -- UART signals signal uart_tx_req : std_logic := '0'; signal uart_tx_end : std_logic := '0'; signal uart_tx_data : std_logic_vector(7 downto 0) := (others => '0'); signal uart_rx_ready : std_logic := '0'; signal uart_rx_data : std_logic_vector(7 downto 0) := (others => '0'); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: echo PORT MAP ( rx => rx, tx => tx, clk => clk ); u1: uart generic map( CLK_FREQ => 32, SER_FREQ => 115200 ) port map( clk => clk, rst => '0', rx => '1', tx => rx, tx_req => uart_tx_req, tx_end => uart_tx_end, tx_data => uart_tx_data, rx_ready => uart_rx_ready, rx_data => uart_rx_data ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; tx_proc : process begin wait for 1000us; uart_tx_data <= "01100101"; wait for 10us; uart_tx_req <= '1'; wait for 10us; uart_tx_req <= '0'; wait for 1000us; uart_tx_data <= "00000000"; wait for 10us; uart_tx_req <= '1'; wait for 10us; uart_tx_req <= '0'; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for clk_period*10; -- insert stimulus here wait; end process; END;

lgpl-3.0

ee7e4efd33d50dc750c73f24b5769962

malkadi/FGPU

bitstreams/settings_and_utilization/V2_1CU_min_area.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 0; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

e774854ff2b9448a104943e4341ac93c

Ttl/fsm_uart

uart.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity uart is generic ( CLK_FREQ : integer := 32; -- Main frequency (MHz) SER_FREQ : integer := 9600; -- Baud rate (bps) PARITY_BIT : boolean := true -- Parity bit enable/disable ); port ( -- Control clk : in std_logic; -- Main clock rst : in std_logic; -- Main reset -- External Interface rx : in std_logic; -- RS232 received serial data tx : out std_logic; -- RS232 transmitted serial data -- uPC Interface tx_req : in std_logic; -- Request SEND of data tx_end : out std_logic; -- Data SENDED tx_data : in std_logic_vector(7 downto 0); -- Data to transmit rx_ready : out std_logic; -- Received data ready to uPC read rx_data : out std_logic_vector(7 downto 0) -- Received data ); end uart; architecture Behavioral of uart is -- Constants constant UART_IDLE : std_logic := '1'; constant UART_START : std_logic := '0'; constant RST_LVL : std_logic := '1'; -- Types type state_tx is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap signals type state_rx is (idle,data,parity); -- RX Signals signal rx_fsm : state_rx; -- Control of reception signal rx_clk_en : std_logic; -- Received clock enable signal rx_rcv_init : std_logic; -- Start of reception signal rx_par_bit : std_logic; -- Calculated Parity bit signal rx_data_deb : std_logic; -- Debounce RX data signal rx_data_tmp : std_logic_vector(6 downto 0); -- Serial to parallel converter signal rx_data_cnt : std_logic_vector(2 downto 0); -- Count received bits -- TX Signals signal tx_fsm : state_tx; -- Control of transmission signal tx_init : std_logic; -- Resets tx_clk when tx_req is asserted signal tx_start : std_logic; -- TX start signal for FSM signal tx_clk_en : std_logic; -- Transmited clock enable signal tx_par_bit : std_logic; -- Calculated Parity bit signal tx_data_tmp : std_logic_vector(7 downto 0); -- Parallel to serial converter signal tx_data_cnt : std_logic_vector(2 downto 0); -- Count transmited bits -- Return a counter value that minimizes the error between real and wanted baud rate. function counts(clk_freq, ser_freq : integer) return integer is variable tmp : integer := (clk_freq*1_000_000)/ser_freq; begin if abs(Real(clk_freq*1_000_000)/Real(tmp)-Real(ser_freq)) < abs(Real(clk_freq*1_000_000)/Real(tmp-1)-Real(ser_freq)) then return tmp; else return tmp - 1; end if; end counts; begin tx_start_detect:process(clk) variable tx_req_old, tx_init_old : std_logic; begin if clk'event and clk = '1' then if tx_init_old = '0' and tx_req = '1' and tx_fsm = idle then tx_init <= '1'; else tx_init <= '0'; tx_start <= tx_req_old; end if; -- Default assignments tx_req_old := tx_req; tx_init_old := tx_init; -- Reset condition if rst = RST_LVL then tx_req_old := '0'; tx_start <= '0'; tx_init <= '0'; end if; end if; end process; tx_clk_gen:process(clk) variable counter : integer range 0 to conv_integer(counts(CLK_FREQ, SER_FREQ)); begin if clk'event and clk = '1' then -- Normal Operation if counter = counts(CLK_FREQ, SER_FREQ) or tx_init = '1' then tx_clk_en <= '1'; counter := 0; else tx_clk_en <= '0'; counter := counter + 1; end if; -- Reset condition if rst = RST_LVL then tx_clk_en <= '0'; counter := 0; end if; end if; end process; tx_proc:process(clk) variable data_cnt : std_logic_vector(2 downto 0); begin if clk'event and clk = '1' then tx_end <= '0'; if tx_clk_en = '1' then -- Default values tx <= UART_IDLE; -- FSM description case tx_fsm is -- Wait to transfer data when idle => -- Send Init Bit if tx_start = '1' then tx <= UART_START; tx_data_tmp <= tx_data; tx_fsm <= data; tx_data_cnt <= (others=>'1'); tx_par_bit <= '0'; end if; -- Data receive when data => tx <= tx_data_tmp(0); tx_par_bit <= tx_par_bit xor tx_data_tmp(0); if tx_data_cnt = 0 then if PARITY_BIT then tx_fsm <= parity; else tx_fsm <= stop1; end if; tx_data_cnt <= (others=>'1'); else tx_data_tmp <= '0' & tx_data_tmp(7 downto 1); tx_data_cnt <= tx_data_cnt - 1; end if; when parity => tx <= tx_par_bit; tx_fsm <= stop1; -- End of communication when stop1 => -- Send Stop Bit tx <= UART_IDLE; tx_fsm <= stop2; when stop2 => -- Send Stop Bit tx_end <= '1'; tx <= UART_IDLE; tx_fsm <= idle; -- Invalid States when others => null; end case; -- Reset condition if rst = RST_LVL then tx_fsm <= idle; tx_par_bit <= '0'; tx_data_tmp <= (others=>'0'); tx_data_cnt <= (others=>'0'); end if; end if; end if; end process; rx_debounceer:process(clk) variable deb_buf : std_logic_vector(3 downto 0); begin if clk'event and clk = '1' then -- Debounce logic if deb_buf = "0000" then rx_data_deb <= '0'; elsif deb_buf = "1111" then rx_data_deb <= '1'; end if; -- Data storage to debounce deb_buf := deb_buf(2 downto 0) & rx; end if; end process; rx_start_detect:process(clk) variable rx_data_old : std_logic; begin if clk'event and clk = '1' then -- Falling edge detection if rx_data_old = '1' and rx_data_deb = '0' and rx_fsm = idle then rx_rcv_init <= '1'; else rx_rcv_init <= '0'; end if; -- Default assignments rx_data_old := rx_data_deb; -- Reset condition if rst = RST_LVL then rx_data_old := '0'; rx_rcv_init <= '0'; end if; end if; end process; rx_clk_gen:process(clk) variable counter : integer range 0 to conv_integer(counts(CLK_FREQ, SER_FREQ)); begin if clk'event and clk = '1' then -- Normal Operation if counter = counts(CLK_FREQ, SER_FREQ) or rx_rcv_init = '1' then rx_clk_en <= '1'; counter := 0; else rx_clk_en <= '0'; counter := counter + 1; end if; -- Reset condition if rst = RST_LVL then rx_clk_en <= '0'; counter := 0; end if; end if; end process; rx_proc:process(clk) begin if clk'event and clk = '1' then -- Default values rx_ready <= '0'; -- Enable on UART rate if rx_clk_en = '1' then -- FSM description case rx_fsm is -- Wait to transfer data when idle => if rx_data_deb = UART_START then rx_fsm <= data; end if; rx_par_bit <= '0'; rx_data_cnt <= (others=>'0'); -- Data receive when data => -- Check data to generate parity if PARITY_BIT then rx_par_bit <= rx_par_bit xor rx; end if; if rx_data_cnt = 7 then -- Data path rx_data(7) <= rx; for i in 0 to 6 loop rx_data(i) <= rx_data_tmp(6-i); end loop; -- With parity verification if PARITY_BIT then rx_fsm <= parity; -- Without parity verification else rx_ready <= '1'; rx_fsm <= idle; end if; else rx_data_tmp <= rx_data_tmp(5 downto 0) & rx; rx_data_cnt <= rx_data_cnt + 1; end if; when parity => -- Check received parity rx_fsm <= idle; if rx_par_bit = rx then rx_ready <= '1'; end if; when others => null; end case; -- Reset condition if rst = RST_LVL then rx_fsm <= idle; rx_ready <= '0'; rx_data <= (others=>'0'); rx_data_tmp <= (others=>'0'); rx_data_cnt <= (others=>'0'); end if; end if; end if; end process; end Behavioral;

lgpl-3.0

02bbacdb7bdb41ba664a0c53692a59a3

jcowgill/cs-dacs-robot

Robot/DecoderTB.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY Decoder_Decoder_sch_tb IS END Decoder_Decoder_sch_tb; ARCHITECTURE behavioral OF Decoder_Decoder_sch_tb IS COMPONENT Decoder PORT ( RF : OUT STD_LOGIC; RR : OUT STD_LOGIC; LF : OUT STD_LOGIC; LR : OUT STD_LOGIC; SCLK : IN STD_LOGIC; I : IN STD_LOGIC_VECTOR(5 DOWNTO 0)); END COMPONENT; SIGNAL RF : STD_LOGIC; SIGNAL RR : STD_LOGIC; SIGNAL LF : STD_LOGIC; SIGNAL LR : STD_LOGIC; SIGNAL SCLK : STD_LOGIC; SIGNAL I : STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN UUT: Decoder PORT MAP( RF => RF, RR => RR, LF => LF, LR => LR, SCLK => SCLK, I => I ); tb_clock : PROCESS BEGIN -- Clock Process SCLK <= '0'; WAIT FOR 100ns; SCLK <= '1'; WAIT FOR 100ns; END PROCESS; tb_process : PROCESS BEGIN -- Instruction 0 I <= "000000"; WAIT FOR 1000ns; -- Instruction 1 I <= "000001"; WAIT FOR 1000ns; -- Instruction 2 I <= "000010"; WAIT FOR 1000ns; -- Instruction 3 I <= "000011"; WAIT FOR 1000ns; -- Instruction 4 I <= "000100"; WAIT FOR 1000ns; -- Instruction 5 I <= "000101"; WAIT FOR 1000ns; -- Instruction 6 I <= "000110"; WAIT FOR 1000ns; -- Instruction 7 I <= "000111"; WAIT; END PROCESS; END;

apache-2.0

c3f91044781e9a8336a5e37408280b58

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_8Banks.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

0be3fc6835d9c4a1bf0e60fca3523011

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_4AXI_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 0; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 2; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 0; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

cb834c4f72b1f9d0f09bd62df4ce65c2

jpidancet/mips

rtl/register_file.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity register_file is port (clk : in std_logic; rst : in std_logic; a1 : in std_logic_vector(4 downto 0); a2 : in std_logic_vector(4 downto 0); a3 : in std_logic_vector(4 downto 0); wd3 : in std_logic_vector(31 downto 0); we3 : in std_logic; rd1 : out std_logic_vector(31 downto 0); rd2 : out std_logic_vector(31 downto 0)); end entity register_file; architecture rtl of register_file is type reg_array is array (1 to 31) of std_logic_vector(31 downto 0); signal regs: reg_array; signal addr1, addr2, addr3: integer range 0 to 31; begin addr1 <= to_integer(unsigned(a1)); addr2 <= to_integer(unsigned(a2)); addr3 <= to_integer(unsigned(a3)); process (addr1, addr3, we3, wd3, regs) begin if addr1 = 0 then rd1 <= (others => '0'); elsif we3 = '1' and addr1 = addr3 then rd1 <= wd3; else rd1 <= regs(addr1); end if; end process; process (addr2, addr3, we3, wd3, regs) begin if addr2 = 0 then rd2 <= (others => '0'); elsif we3 = '1' and addr2 = addr3 then rd2 <= wd3; else rd2 <= regs(addr2); end if; end process; process (clk, rst) begin if rst = '1' then for i in 1 to 31 loop regs(i) <= (others => '0'); end loop; elsif rising_edge(clk) then if we3 = '1' and addr3 /= 0 then regs(addr3) <= wd3; end if; end if; end process; end architecture rtl;

isc

3442883408312c96b292fcae26b3e35b

preusser/q27

src/vhdl/PoC/io/io_TimingCounter.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: optimized down-counter to control timings for low speed signals -- -- Description: -- ------------------------------------ -- This down-counter can be configured with a TIMING_TABLE (a ROM), from which -- the initial counter value is loaded. The table index can be selected by -- 'Slot'. 'Timeout' is a registered output. Up to 16 values fit into one ROM -- consisting of 'log2ceilnz(imax(TIMING_TABLE)) + 1' 6-input LUTs. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.my_config.all; use PoC.utils.all; entity io_TimingCounter is generic ( TIMING_TABLE : T_NATVEC -- timing table ); port ( Clock : in STD_LOGIC; -- clock Enable : in STD_LOGIC; -- enable counter Load : in STD_LOGIC; -- load Timing Value from TIMING_TABLE selected by slot Slot : in NATURAL range 0 to (TIMING_TABLE'length - 1); -- Timeout : out STD_LOGIC -- timing reached ); end; architecture rtl of io_TimingCounter is function transform(vec : T_NATVEC) return T_INTVEC is variable Result : T_INTVEC(vec'range); begin assert (not MY_VERBOSE) report "TIMING_TABLE (transformed):" severity NOTE; for i in vec'range loop Result(I) := vec(I) - 1; assert (not MY_VERBOSE) report " " & INTEGER'image(I) & " - " & INTEGER'image(Result(I)) severity NOTE; end loop; return Result; end; constant TIMING_TABLE2 : T_INTVEC := transform(TIMING_TABLE); constant TIMING_MAX : NATURAL := imax(TIMING_TABLE2); constant COUNTER_BITS : NATURAL := log2ceilnz(TIMING_MAX + 1); signal Counter_s : SIGNED(COUNTER_BITS downto 0) := to_signed(TIMING_TABLE2(0), COUNTER_BITS + 1); begin process(Clock) begin if rising_edge(Clock) then if (Load = '1') then Counter_s <= to_signed(TIMING_TABLE2(Slot), Counter_s'length); elsif ((Enable = '1') and (Counter_s(Counter_s'high) = '0')) then Counter_s <= Counter_s - 1; end if; end if; end process; timeout <= Counter_s(Counter_s'high); end;

agpl-3.0

51a84f8048fd9a5d31d98a0c9be7b9c8

malkadi/FGPU

RTL/gmem_cntrl_tag.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity gmem_cntrl_tag is -- {{{ port( -- axi signals wr_fifo_free : in std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); --free ports have to respond to go ports immediately (in one clock cycle) wr_fifo_go : out std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); wr_fifo_cache_ack : in std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); axi_rdAddr : out gmem_addr_array_no_bank(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); axi_writer_go : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_wrAddr : out gmem_addr_array_no_bank(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_writer_free : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rd_fifo_filled : in std_logic_vector(N_AXI-1 downto 0); axi_wvalid : in std_logic_vector(N_AXI-1 downto 0); axi_writer_ack : in std_logic_vector(N_TAG_MANAGERS-1 downto 0); axi_writer_id : out std_logic_vector(N_TAG_MANAGERS_W-1 downto 0) := (others=>'0'); --receivers signals rcv_alloc_tag : in std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); -- rcv_alloc_tag need to be set whether it is a tag to be allocated or a page to be validate -- rcv_validate_page : in std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_gmem_addr : in gmem_word_addr_array(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); rcv_rnw : in std_logic_vector(N_RECEIVERS-1 downto 0); rcv_tag_written : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_tag_updated : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_page_validated : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_read_tag : in std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_read_tag_ack : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rdData_page_v : out std_logic_vector(N_RD_PORTS-1 downto 0) := (others=>'0'); rdData_tag_v : out std_logic_vector(N_RD_PORTS-1 downto 0) := (others=>'0'); rdData_tag : out tag_array(N_RD_PORTS-1 downto 0) := (others=>(others=>'0')); -- cache port a signals cache_we : in std_logic := '0'; cache_addra : in unsigned(M+L-1 downto 0) := (others=>'0'); cache_wea : in std_logic_vector((2**N)*DATA_W/8-1 downto 0) := (others=>'0'); -- finish WGsDispatched : in std_logic; CUs_gmem_idle : in std_logic; rcv_all_idle : in std_logic := '0'; rcv_idle : in std_logic_vector(N_RECEIVERS-1 downto 0); finish_exec : out std_logic := '0'; start_kernel : in std_logic; clean_cache : in std_logic; atomic_can_finish : in std_logic := '0'; -- write pipeline write_pipe_active : in std_logic_vector(4 downto 0) := (others=>'0'); write_pipe_wrTag : in tag_addr_array(4 downto 0); clk, nrst : in std_logic ); end entity; -- }}} architecture basic of gmem_cntrl_tag is -- internal signals definitions {{{ signal axi_wrAddr_i : gmem_addr_array_no_bank(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rdData_tag_i : tag_array(N_RD_PORTS-1 downto 0) := (others=>(others=>'0')); -- on a critical path -- }}} -- axi signals {{{ signal wr_fifo_go_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_writer_go_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_writer_id_n : std_logic_vector(N_TAG_MANAGERS_W-1 downto 0) := (others=>'0'); --}}} -- functions & constants {{{ function map_rd_fifo_to_axis(n_rd_fifos : natural; n_axis: natural) return nat_array is variable res : nat_array(n_rd_fifos-1 downto 0) := (others=>0); begin for i in 0 to n_rd_fifos-1 loop res(i) := i mod n_axis; end loop; return res; end function; constant c_rd_fifo_axi : nat_array(N_TAG_MANAGERS-1 downto 0) := map_rd_fifo_to_axis(N_TAG_MANAGERS, N_AXI); -- }}} -- mem signals {{{ signal tag : tag_array(0 to 2**M-1) := (others=>(others=>'0')); signal wrAddr_tag, wrAddr_tag_n : unsigned(M-1 downto 0) := (others=>'0'); signal wrData_tag, wrData_tag_n : unsigned(TAG_W-1 downto 0) := (others=>'0'); signal rdAddr_tag, rdAddr_tag_n : tag_addr_array(N_RD_PORTS-1 downto 0) := (others=>(others=>'0')); signal we_tag, we_tag_n : std_logic := '0'; signal tag_v : std_logic_vector(0 to 2**M-1) := (others=>'0'); signal we_tag_v, we_tag_v_n : std_logic := '0'; signal wrAddr_tag_v, wrAddr_tag_v_n : unsigned(M-1 downto 0) := (others=>'0'); signal wrData_tag_v, wrData_tag_v_n : std_logic := '0'; signal clear_tag, clear_tag_n : std_logic := '0'; signal page_v : std_logic_vector(0 to 2**M-1) := (others=>'0'); signal we_page_v, we_page_v_n : std_logic := '0'; signal wrAddr_page_v, wrAddr_page_v_n : unsigned(M-1 downto 0) := (others=>'0'); signal wrData_page_v, wrData_page_v_n : std_logic := '0'; -- }}} -- receivers signals {{{ signal rcv_tag_written_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_tag_updated_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_page_validated_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); -- }}} -- Tag managers signals {{{ type st_tmanager_type is (idle, define_rcv_indx, check_tag_being_processed, invalidate_tag_v, invalidate_page_v, clear_tag_st, clear_dirty, check_dirty, validate_new_tag, issue_write, read_tag, wait_write_finish, issue_read, wait_read_finish, validate_new_page, wait_page_v, wait_a_little, wait_bid); type st_tmanager_array is array (N_TAG_MANAGERS-1 downto 0) of st_tmanager_type; type rcv_alloc_for_tmanager_type is array(N_TAG_MANAGERS-1 downto 0) of std_logic_vector(N_RECEIVERS/N_TAG_MANAGERS-1 downto 0); signal st_tmanager, st_tmanager_n : st_tmanager_array := (others=>idle); -- attribute mark_debug of st_tmanager : signal is "true"; signal tmanager_free, tmanager_free_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal rcv_alloc_tag_ltchd, rcv_alloc_tag_ltchd_n : rcv_alloc_for_tmanager_type := (others=>(others=>'0')); signal tmanager_gmem_addr : gmem_addr_array_no_bank(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal tmanager_gmem_addr_n : gmem_addr_array_no_bank(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); -- attribute mark_debug of tmanager_gmem_addr : signal is "true"; type rcv_indx_tmanager_type is array (0 to N_TAG_MANAGERS-1) of natural range 0 to N_RECEIVERS-1; signal rcv_indx_tmanager : rcv_indx_tmanager_type := (others=>0); signal rcv_indx_tmanager_n : rcv_indx_tmanager_type := (others=>0); signal tmanager_rcv_served : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_rcv_served_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal invalidate_tag, invalidate_tag_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of invalidate_tag : signal is "true"; signal invalidate_tag_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal invalidate_page : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal invalidate_page_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of invalidate_page : signal is "true"; signal validate_page, validate_page_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of validate_page : signal is "true"; signal page_v_tmanager_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal clear_tag_tmanager : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal clear_tag_tmanager_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of clear_tag_tmanager : signal is "true"; signal alloc_tag, alloc_tag_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of alloc_tag : signal is "true"; signal alloc_tag_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_issue_write : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_issue_write : signal is "true"; signal tmanager_issue_write_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wr_issued_tmanager : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wr_issued_tmanager_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_busy, tmanager_busy_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_busy : signal is "true"; constant TAG_PROTECT_LEN : natural := 7; -- # of clock cycles before a processed tag from a tag manager can be processed by another one type tmanager_tag_protect_vec_type is array(natural range<>) of std_logic_vector(TAG_PROTECT_LEN-1 downto 0); signal tmanager_tag_protect_vec : tmanager_tag_protect_vec_type(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); -- helps a tag manager to clear the protection of tag signal tmanager_tag_protect_vec_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_tag_protect_v : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_tag_protect_v_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_tag_protect_v : signal is "true"; signal tmanager_tag_protect : tag_addr_array(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); -- attribute mark_debug of tmanager_tag_protect : signal is "true"; -- after a tag has been processed by a tag manager, it will be stored with this signal. -- It is not allowed to process the tag again before TAG_PROTECT_LEN clock cycles -- It helps to avoid frequent allocation/deallocation of the same tag (not necessary but improve the performance) -- It helps to insure data consistency by using the B axi channel response to clear it (necessary if the kernel reads/writes the same address region) signal tmanager_tag_protect_n : tag_addr_array(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal tmanager_gmem_addr_protected : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); constant RCV_SERVED_WIAT_LEN : natural := 2**(WRITE_PHASE_W+1); type tmanager_rcv_served_wait_vec_type is array(natural range<>) of std_logic_vector(RCV_SERVED_WIAT_LEN-1 downto 0); signal tmanager_rcv_served_wait_vec : tmanager_rcv_served_wait_vec_type(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); -- helps a tag manager to wait for some time before issuing a receiver that its write requested has been executed signal tmanager_rcv_served_wait_vec_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_get_busy : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_get_busy : signal is "true"; signal tmanager_get_busy_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_get_busy_ack : signal is "true"; constant wait_len : natural := 4; type wait_vec_type is array (natural range <>) of std_logic_vector(wait_len-1 downto 0); type wait_vec_invalidate_tag_type is array (natural range <>) of std_logic_vector(wait_len downto 0); signal wait_vec : wait_vec_type(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal wait_vec_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wait_vec_invalidate_tag : wait_vec_invalidate_tag_type(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal wait_vec_invalidate_tag_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wait_done, wait_done_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of wait_done : signal is "true"; signal tmanager_read_tag : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_read_tag : signal is "true"; signal tmanager_read_tag_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_read_tag_ack_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_read_tag_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_read_tag_ack_d0 : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_tag_to_write : tag_array(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal tmanager_clear_dirty : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_clear_dirty : signal is "true"; signal tmanager_clear_dirty_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_clear_dirty_ack_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_clear_dirty_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_wait_for_fifo_empty : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_wait_for_fifo_empty_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); --}}} -- dirty signals {{{ signal dirty : std_logic_vector(2**M-1 downto 0) := (others=>'0'); signal we_dirty, we_dirty_n : std_logic := '0'; signal wrData_dirty, wrData_dirty_n : std_logic := '0'; signal wrAddr_dirty, wrAddr_dirty_n : unsigned(M-1 downto 0) := (others=>'0'); signal rdAddr_dirty, rdAddr_dirty_n : tag_addr_array(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal rdData_dirty : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- }}} -- axi signals {{{ type axi_intefrace is (find_free_fifo, issue_order); type wr_fifo_indx_array is array (0 to N_TAG_MANAGERS-1) of natural range 0 to N_WR_FIFOS-1; type axi_wr_channel_indx is array (0 to N_TAG_MANAGERS-1) of natural range 0 to N_AXI-1; signal st_axi_wr, st_axi_wr_n : axi_intefrace := find_free_fifo; signal axi_wrAddr_n : gmem_addr_array_no_bank(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_wr_indx_tmanager, axi_wr_indx_tmanager_n : axi_wr_channel_indx := (others=>0); --}}} -- final cache clean signals {{{ signal rcv_all_idle_vec : std_logic_vector(2 downto 0) := (others=>'0'); -- It is necessary to make sure that rcv_all_idle is stable for 3 clock cycles before cache cleaning at the end signal finish_active, finish_active_n : std_logic := '0'; signal finish_tag_addr : unsigned(M-1 downto 0) := (others=>'0'); signal finish_tag_addr_n : unsigned(M-1 downto 0) := (others=>'0'); signal finish_tag_addr_d0 : unsigned(M-1 downto 0) := (others=>'0'); signal finish_tag_addr_d1 : unsigned(M-1 downto 0) := (others=>'0'); signal finish_we, finish_we_n : std_logic := '0'; signal rdData_tag_d0 : unsigned(TAG_W-1 downto 0) := (others=>'0'); signal finish_issue_write : std_logic := '0'; signal finish_issue_write_n : std_logic := '0'; signal finish_exec_masked : std_logic := '0'; signal finish_exec_masked_n : std_logic := '0'; type finish_fifo_type is array(natural range <>) of unsigned(TAG_W+M-1 downto 0); signal finish_fifo : finish_fifo_type(2**FINISH_FIFO_ADDR_W-1 downto 0) := (others=>(others=>'0')); signal finish_fifo_rdAddr : unsigned(FINISH_FIFO_ADDR_W-1 downto 0) := (others=>'0'); signal finish_fifo_wrAddr : unsigned(FINISH_FIFO_ADDR_W-1 downto 0) := (others=>'0'); signal finish_fifo_dout : unsigned(TAG_W+M-1 downto 0) := (others=>'0'); signal finish_fifo_pop, finish_fifo_push_n : std_logic := '0'; signal finish_fifo_push : std_logic_vector(1 downto 0) := (others=>'0'); type st_fill_finish_fifo_type is (idle1, idle2, pre_active, active, finish); signal st_fill_finish_fifo, st_fill_finish_fifo_n : st_fill_finish_fifo_type := idle1; signal finish_fifo_n_rqsts, finish_fifo_n_rqsts_n : integer range 0 to 2**FINISH_FIFO_ADDR_W := 0; -- }}} -- write pipeline signals {{{ signal write_pipe_contains_gmem_addr : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_waited_for_write_pipe : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_waited_for_write_pipe_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_waited_for_write_pipe : signal is "true"; type st_finish_writer_type is (idle, issue, wait_fifo_dout); signal st_finish_writer : st_finish_writer_type := idle; signal st_finish_writer_n : st_finish_writer_type := idle; --}}} -- bvalid processing ------------------------------------------------------------------------------------{{{ signal write_response_rcvd : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wait_for_write_response : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wait_for_write_response_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); ---------------------------------------------------------------------------------------------------------}}} begin -- internal signals assignments -------------------------------------------------------------------------{{{ axi_wrAddr <= axi_wrAddr_i; assert N_RD_FIFOS_TAG_MANAGER_W = 0 report "There must be a single rd fifo (from cache) for each tag manager. Otherwise b channel communcation fails!" severity failure; rdData_tag <= rdData_tag_i; ---------------------------------------------------------------------------------------------------------}}} -- error handling-------------------------------------------------------------------------------------------{{{ assert(N_TAG_MANAGERS = N_WR_FIFOS); assert(N_RD_PORTS > 1); -- assert(addra(7 downto 0) /= X"B7" or addra(8) /= '0' or wea(7 downto 4) /= "F"); ---------------------------------------------------------------------------------------------------------}}} -- finish FSM -------------------------------------------------------------------------------------------{{{ rcv_all_idle_vec(rcv_all_idle_vec'high) <= rcv_all_idle; process(clk) begin if rising_edge(clk) then -- pipes {{{ rcv_all_idle_vec(rcv_all_idle_vec'high-1 downto 0) <= rcv_all_idle_vec(rcv_all_idle_vec'high downto 1); finish_tag_addr <= finish_tag_addr_n; finish_tag_addr_d0 <= finish_tag_addr; finish_tag_addr_d1 <= finish_tag_addr_d0; -- }}} -- set final finish signal {{{ finish_exec_masked <= finish_exec_masked_n; finish_exec <= '0'; if finish_exec_masked = '1' then if clean_cache = '1' then if axi_writer_free = (axi_writer_free'reverse_range => '1') and axi_wvalid = (0 to N_AXI-1 =>'0') then finish_exec <= '1'; end if; else finish_exec <= '1'; end if; end if; if start_kernel = '1' then finish_exec <= '0'; end if; -- }}} finish_we <= finish_we_n; finish_fifo_dout <= finish_fifo(to_integer(finish_fifo_rdAddr)); if finish_fifo_push(0) = '1' and rdData_dirty(0) = '1' then finish_fifo(to_integer(finish_fifo_wrAddr)) <= rdData_tag_i(N_RD_PORTS-1) & finish_tag_addr_d1; end if; if nrst = '0' then finish_active <= '0'; finish_issue_write <= '0'; st_fill_finish_fifo <= idle1; finish_fifo_push <= (others=>'0'); finish_fifo_wrAddr <= (others=>'0'); finish_fifo_n_rqsts <= 0; st_finish_writer <= idle; finish_fifo_rdAddr <= (others=>'0'); else finish_active <= finish_active_n; finish_issue_write <= finish_issue_write_n; st_fill_finish_fifo <= st_fill_finish_fifo_n; finish_fifo_push(finish_fifo_push'high-1 downto 0) <= finish_fifo_push(finish_fifo_push'high downto 1); finish_fifo_push(finish_fifo_push'high) <= finish_fifo_push_n; if finish_fifo_push(0) = '1' and rdData_dirty(0) = '1' then finish_fifo_wrAddr <= finish_fifo_wrAddr + 1; end if; st_finish_writer <= st_finish_writer_n; if finish_fifo_pop = '1' then finish_fifo_rdAddr <= finish_fifo_rdAddr + 1; end if; if finish_fifo_push(0) = '1' and rdData_dirty(0) = '1' and finish_fifo_pop = '0' then finish_fifo_n_rqsts <= finish_fifo_n_rqsts + 1; elsif (finish_fifo_push(0) = '0' or rdData_dirty(0) = '0') and finish_fifo_pop = '1' then finish_fifo_n_rqsts <= finish_fifo_n_rqsts - 1; end if; end if; end if; end process; process(st_finish_writer, finish_fifo_n_rqsts, finish_issue_write) begin st_finish_writer_n <= st_finish_writer; finish_issue_write_n <= finish_issue_write; case st_finish_writer is when idle => if finish_fifo_n_rqsts /= 0 then finish_issue_write_n <= '1'; st_finish_writer_n <= issue; end if; when issue => finish_issue_write_n <= '0'; st_finish_writer_n <= wait_fifo_dout; when wait_fifo_dout => st_finish_writer_n <= idle; end case; end process; process(st_fill_finish_fifo, finish_tag_addr, WGsDispatched, start_kernel, CUs_gmem_idle, rcv_all_idle_vec, finish_active, finish_fifo_n_rqsts, clean_cache, atomic_can_finish) begin st_fill_finish_fifo_n <= st_fill_finish_fifo; finish_tag_addr_n <= finish_tag_addr; finish_active_n <= finish_active; finish_fifo_push_n <= '0'; finish_we_n <= '0'; finish_exec_masked_n <= '0'; case st_fill_finish_fifo is when idle1 => finish_tag_addr_n <= (others=>'0'); if WGsDispatched = '1' then st_fill_finish_fifo_n <= idle2; end if; when idle2 => if CUs_gmem_idle = '1' and rcv_all_idle_vec = (rcv_all_idle_vec'reverse_range =>'1') and (ATOMIC_IMPLEMENT = 0 or atomic_can_finish = '1') then if clean_cache = '0' then st_fill_finish_fifo_n <= finish; else finish_active_n <= '1'; end if; end if; if finish_active = '1' then st_fill_finish_fifo_n <= pre_active; if STAT = 1 then -- if kernel_name /= sum_half then -- report "Finish begins"; -- end if; end if; end if; when pre_active => finish_tag_addr_n <= finish_tag_addr + 1; finish_fifo_push_n <= '1'; finish_we_n <= '1'; st_fill_finish_fifo_n <= active; when active => if finish_fifo_n_rqsts < 2**FINISH_FIFO_ADDR_W-2 then finish_tag_addr_n <= finish_tag_addr + 1; finish_fifo_push_n <= '1'; finish_we_n <= '1'; end if; if finish_tag_addr = (finish_tag_addr'reverse_range => '0') then st_fill_finish_fifo_n <= finish; end if; when finish => finish_exec_masked_n <= '1'; if start_kernel = '1' then st_fill_finish_fifo_n <= idle1; finish_active_n <= '0'; finish_exec_masked_n <= '0'; end if; end case; end process; ---------------------------------------------------------------------------------------------------------}}} -- write pipeline check --------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then write_pipe_contains_gmem_addr <= (others=>'0'); for i in 0 to N_TAG_MANAGERS-1 loop for j in 0 to 4 loop if (tmanager_gmem_addr(i)(M+L-1 downto L) = write_pipe_wrTag(j)) and (write_pipe_active(j) = '1') then write_pipe_contains_gmem_addr(i) <= '1'; end if; end loop; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- tag managers -------------------------------------------------------------------------------------------{{{ trans: process(clk) -- {{{ begin if rising_edge(clk) then rcv_alloc_tag_ltchd <= rcv_alloc_tag_ltchd_n; tmanager_gmem_addr <= tmanager_gmem_addr_n; rcv_indx_tmanager <= rcv_indx_tmanager_n; if WRITE_PHASE_W > 1 then tmanager_rcv_served <= tmanager_rcv_served_n; end if; tmanager_get_busy_ack <= (others=>'0'); for i in 0 to N_TAG_MANAGERS-1 loop if tmanager_get_busy(i) = '1' then tmanager_get_busy_ack(i) <= '1'; exit; end if; end loop; wr_fifo_go <= wr_fifo_go_n; tmanager_tag_protect <= tmanager_tag_protect_n; for i in 0 to N_TAG_MANAGERS-1 loop tmanager_tag_protect_vec(i)(TAG_PROTECT_LEN-2 downto 0) <= tmanager_tag_protect_vec(i)(TAG_PROTECT_LEN-1 downto 1); tmanager_tag_protect_vec(i)(TAG_PROTECT_LEN-1) <= tmanager_tag_protect_vec_n(i); tmanager_rcv_served_wait_vec(i)(RCV_SERVED_WIAT_LEN-2 downto 0) <= tmanager_rcv_served_wait_vec(i)(RCV_SERVED_WIAT_LEN-1 downto 1); tmanager_rcv_served_wait_vec(i)(RCV_SERVED_WIAT_LEN-1) <= tmanager_rcv_served_wait_vec_n(i); end loop; tmanager_gmem_addr_protected <= (others=>'0'); for i in 0 to N_TAG_MANAGERS-1 loop for j in 0 to N_TAG_MANAGERS-1 loop if j /= i then if tmanager_tag_protect_v(j) = '1' and tmanager_gmem_addr(i)(M+L-1 downto L) = tmanager_tag_protect(j) then tmanager_gmem_addr_protected(i) <= '1'; end if; end if; end loop; end loop; tmanager_tag_protect_v <= tmanager_tag_protect_v_n; for i in N_TAG_MANAGERS-1 downto 0 loop wait_vec(i)(wait_len-2 downto 0) <= wait_vec(i)(wait_len-1 downto 1); wait_vec(i)(wait_len-1) <= wait_vec_n(i); wait_vec_invalidate_tag(i)(wait_len-1 downto 0) <= wait_vec_invalidate_tag(i)(wait_len downto 1); wait_vec_invalidate_tag(i)(wait_len) <= wait_vec_invalidate_tag_n(i); if tmanager_read_tag_ack_d0(i) = '1' then tmanager_tag_to_write(i) <= rdData_tag_i(N_RD_PORTS-1); end if; end loop; if nrst = '0' then st_tmanager <= (others=>idle); tmanager_free <= (others=>'0'); invalidate_tag <= (others=>'0'); invalidate_page <= (others=>'0'); validate_page <= (others=>'0'); clear_tag_tmanager <= (others=>'0'); tmanager_issue_write <= (others=>'0'); tmanager_busy <= (others=>'0'); alloc_tag <= (others=>'0'); tmanager_read_tag <= (others=>'0'); tmanager_clear_dirty <= (others=>'0'); wait_done <= (others=>'0'); tmanager_wait_for_fifo_empty <= (others=>'0'); tmanager_waited_for_write_pipe <= (others=>'0'); else st_tmanager <= st_tmanager_n; tmanager_free <= tmanager_free_n; invalidate_tag <= invalidate_tag_n; invalidate_page <= invalidate_page_n; validate_page <= validate_page_n; clear_tag_tmanager <= clear_tag_tmanager_n; tmanager_issue_write <= tmanager_issue_write_n; tmanager_busy <= tmanager_busy_n; alloc_tag <= alloc_tag_n; tmanager_read_tag <= tmanager_read_tag_n; tmanager_clear_dirty <= tmanager_clear_dirty_n; wait_done <= wait_done_n; tmanager_wait_for_fifo_empty <= tmanager_wait_for_fifo_empty_n; tmanager_waited_for_write_pipe <= tmanager_waited_for_write_pipe_n; end if; end if; end process; --}}} tmanagers: for i in 0 to N_TAG_MANAGERS-1 generate process(st_tmanager(i), tmanager_free(i), rcv_alloc_tag, tmanager_gmem_addr, rcv_alloc_tag_ltchd, rcv_indx_tmanager(i), rcv_gmem_addr, -- {{{ tmanager_tag_protect_v, invalidate_tag(i), invalidate_tag_ack(i), clear_tag_tmanager(i), rdData_dirty(i), tmanager_issue_write(i), tmanager_tag_protect, rcv_idle, axi_wr_indx_tmanager(i), wr_issued_tmanager(i), wr_fifo_free(i), wait_done(i), tmanager_waited_for_write_pipe(i), tmanager_rcv_served(i), tmanager_rcv_served_wait_vec(i)(0), page_v_tmanager_ack(i), invalidate_page(i), alloc_tag_ack(i), validate_page(i), tmanager_busy(i), tmanager_get_busy_ack(i), tmanager_tag_protect_vec(i), rcv_rnw, wait_vec(i)(0), wait_vec_invalidate_tag(i)(0), tmanager_read_tag(i), tmanager_read_tag_ack_d0(i), axi_rd_fifo_filled, tmanager_clear_dirty(i), alloc_tag(i), tmanager_read_tag_ack_n(i), tmanager_clear_dirty_ack(i), write_pipe_contains_gmem_addr(i), tmanager_wait_for_fifo_empty(i), tmanager_gmem_addr_protected(i), tmanager_tag_to_write(i), wait_for_write_response(i)) -- }}} begin -- next initialization {{{ st_tmanager_n(i) <= st_tmanager(i); tmanager_free_n(i) <= tmanager_free(i); rcv_alloc_tag_ltchd_n(i) <= rcv_alloc_tag_ltchd(i); tmanager_gmem_addr_n(i) <= tmanager_gmem_addr(i); rcv_indx_tmanager_n(i) <= rcv_indx_tmanager(i); invalidate_tag_n(i) <= invalidate_tag(i); invalidate_page_n(i) <= invalidate_page(i); validate_page_n(i) <= validate_page(i); clear_tag_tmanager_n(i) <= clear_tag_tmanager(i); tmanager_issue_write_n(i) <= tmanager_issue_write(i); tmanager_busy_n(i) <= tmanager_busy(i); tmanager_get_busy(i) <= '0'; alloc_tag_n(i) <= alloc_tag(i); wait_vec_n(i) <= '0'; wait_vec_invalidate_tag_n(i) <= '0'; tmanager_read_tag_n(i) <= tmanager_read_tag(i); tmanager_clear_dirty_n(i) <= tmanager_clear_dirty(i); wait_done_n(i) <= wait_done(i); tmanager_wait_for_fifo_empty_n(i) <= tmanager_wait_for_fifo_empty(i); tmanager_waited_for_write_pipe_n(i) <= tmanager_waited_for_write_pipe(i); if tmanager_tag_protect_vec(i)(0) = '1' then tmanager_tag_protect_v_n(i) <= '0'; else tmanager_tag_protect_v_n(i) <= tmanager_tag_protect_v(i); end if; if WRITE_PHASE_W > 1 then tmanager_rcv_served_n(i) <= tmanager_rcv_served(i); if rcv_idle(rcv_indx_tmanager(i)) = '1' or tmanager_rcv_served_wait_vec(i)(0) = '1' then tmanager_rcv_served_n(i) <= '1'; end if; end if; tmanager_tag_protect_n(i) <= tmanager_tag_protect(i); tmanager_tag_protect_vec_n(i) <= '0'; tmanager_rcv_served_wait_vec_n(i) <= '0'; wr_fifo_go_n(i) <= '0'; -- }}} case st_tmanager(i) is when idle => -- {{{ tmanager_waited_for_write_pipe_n(i) <= '0'; rcv_alloc_tag_ltchd_n(i) <= rcv_alloc_tag((i+1)*N_RECEIVERS/N_TAG_MANAGERS-1 downto i*N_RECEIVERS/N_TAG_MANAGERS); if tmanager_rcv_served(i) = '1' or WRITE_PHASE_W = 1 then if rcv_alloc_tag((i+1)*N_RECEIVERS/N_TAG_MANAGERS-1 downto i*N_RECEIVERS/N_TAG_MANAGERS) /= (0 to N_RECEIVERS/N_TAG_MANAGERS-1 =>'0') then st_tmanager_n(i) <= define_rcv_indx; end if; end if; -- }}} when define_rcv_indx => -- {{{ st_tmanager_n(i) <= idle; -- in case rcv_alloc_tag_ltchd are all zeros for j in 0 to N_RECEIVERS/N_TAG_MANAGERS-1 loop if rcv_alloc_tag_ltchd(i)(j) = '1' and rcv_alloc_tag(i*N_RECEIVERS/N_TAG_MANAGERS+j) = '1' then -- rcv_alloc_tag must be checked because it may be deasserted while rcv_alloc_tag_latched is still asserted rcv_indx_tmanager_n(i) <= j+ i*N_RECEIVERS/N_TAG_MANAGERS; rcv_alloc_tag_ltchd_n(i)(j) <= '0'; tmanager_gmem_addr_n(i) <= rcv_gmem_addr(j+ i*N_RECEIVERS/N_TAG_MANAGERS)(GMEM_WORD_ADDR_W-1 downto N); st_tmanager_n(i) <= check_tag_being_processed; exit; end if; end loop; -- }}} when check_tag_being_processed => --check if the corresponding cache addr is being processed by another tmanager {{{ -- if an address of the requested tag is already in the write pipeline; the FSM should go and try to pick up a new alloc request -- Otherwise it may stay in this state, as long as no anther tmanager is processing the tag and the alloc request deasserted, e.g. another tmanager allocated the tag -- Processing a no more requested tag may lead to the following problem: -- a rcv wants to write, a tmanager thinks wrongly that somebody wants to read the address, -- as soon as the tag is allocated, the rcv may write and the data may be overwritten! tmanager_get_busy(i) <= '1'; if tmanager_get_busy_ack(i) = '1' then if write_pipe_contains_gmem_addr(i) = '0' and tmanager_gmem_addr_protected(i) = '0' then -- tmanager_gmem_addr_protected has a delay of 1 clock cycle invalidate_tag_n(i) <= '1'; st_tmanager_n(i) <= invalidate_tag_v; tmanager_busy_n(i) <= '1'; tmanager_tag_protect_v_n(i) <= '1'; tmanager_tag_protect_n(i) <= tmanager_gmem_addr(i)(M+L-1 downto L); else st_tmanager_n(i) <= define_rcv_indx; tmanager_get_busy(i) <= '0'; end if; end if; for j in 0 to N_TAG_MANAGERS-1 loop if j /= i then if (tmanager_busy(j) = '1' and tmanager_gmem_addr(i)(M+L-1 downto L) = tmanager_gmem_addr(j)(M+L-1 downto L)) then -- (tmanager_gmem_addr_protected(i) = '1' and tmanager_get_busy_ack(i) = '1') then -- (tmanager_tag_protect_v(j) = '1' and tmanager_gmem_addr(i)(M+N+L-1 downto L+N) = tmanager_tag_protect(j)) then tmanager_get_busy(i) <= '0'; tmanager_busy_n(i) <= '0'; tmanager_tag_protect_v_n(i) <= '0'; invalidate_tag_n(i) <= '0'; st_tmanager_n(i) <= define_rcv_indx; end if; end if; end loop; -- }}} when invalidate_tag_v => -- {{{ -- if tmanager_tag_protect_vec(i)(0) = '1' then -- report "heeeere" severity failure; -- end if; -- tmanager_tag_protect_v_n(i) <= '1'; -- tmanager_tag_protect_n(i) <= tmanager_gmem_addr(i)(M+N+L-1 downto N+L); if WRITE_PHASE_W > 1 then tmanager_rcv_served_n(i) <= '0'; end if; if invalidate_tag_ack(i) = '1' then invalidate_tag_n(i) <= '0'; st_tmanager_n(i) <= clear_tag_st; clear_tag_tmanager_n(i) <= '1'; alloc_tag_n(i) <= '1'; end if; -- }}} when clear_tag_st => -- {{{ if alloc_tag_ack(i) = '1' then clear_tag_tmanager_n(i) <= '0'; alloc_tag_n(i) <= '0'; st_tmanager_n(i) <= invalidate_page_v; invalidate_page_n(i) <= '1'; end if; -- }}} when invalidate_page_v => -- {{{ if page_v_tmanager_ack(i) = '1' then invalidate_page_n(i) <= '0'; st_tmanager_n(i) <= check_dirty; wait_vec_invalidate_tag_n(i) <= '1'; if write_pipe_contains_gmem_addr(i) = '1' then tmanager_waited_for_write_pipe_n(i) <= '1'; end if; end if; -- }}} when check_dirty => -- {{{ if write_pipe_contains_gmem_addr(i) = '1' then tmanager_waited_for_write_pipe_n(i) <= '1'; if wait_vec_invalidate_tag(i)(0) = '1' then wait_done_n(i) <= '1'; end if; else wait_done_n(i) <= '0'; if wait_vec_invalidate_tag(i)(0) = '1' or wait_done(i) = '1' then if tmanager_waited_for_write_pipe(i) = '1' or rdData_dirty(i) = '1' then st_tmanager_n(i) <= read_tag; tmanager_read_tag_n(i) <= '1'; tmanager_clear_dirty_n(i) <= '1'; else -- - -- st_tmanager_n(i) <= validate_new_tag; -- alloc_tag_n(i) <= '1'; -- - -- + -- Populating the cache line with the new content should be done before validating the new tag -- Otherwise, some receivers may write the cache directly after tag validation and the written data will -- be overwritten by the one from the global memory -- Therefore, issue_read -> validate_tag -> validate_page if rcv_rnw(rcv_indx_tmanager(i)) = '1' then st_tmanager_n(i) <= issue_read; wr_fifo_go_n(i) <= '1'; else st_tmanager_n(i) <= validate_new_tag; alloc_tag_n(i) <= '1'; end if; -- + end if; end if; end if; -- }}} when validate_new_tag => -- {{{ if alloc_tag_ack(i) = '1' then alloc_tag_n(i) <= '0'; -- - -- if rcv_rnw(rcv_indx_tmanager(i)) = '1' then -- st_tmanager_n(i) <= issue_read; -- wr_fifo_go_n(i) <= '1'; -- else -- st_tmanager_n(i) <= wait_a_little; -- wait_vec_n(i) <= '1'; -- end if; -- - -- + if rcv_rnw(rcv_indx_tmanager(i)) = '1' then st_tmanager_n(i) <= validate_new_page; validate_page_n(i) <= '1'; else st_tmanager_n(i) <= wait_a_little; wait_vec_n(i) <= '1'; end if; -- + end if; -- }}} when wait_a_little => --necessary because rcv_alloc_tag does not react immediately in case of validating a tag for a write {{{ -- tmanager_tag_protect_v_n(i) <= '1'; -- setting tag protect should be done 2 cycles before going to idle -- tmanager_tag_protect_n(i) <= tmanager_gmem_addr(i)(M+N+L-1 downto N+L); if wait_vec(i)(0) = '1' then st_tmanager_n(i) <= idle; tmanager_busy_n(i) <= '0'; tmanager_tag_protect_vec_n(i) <= '1'; tmanager_rcv_served_wait_vec_n(i) <= '1'; end if; -- }}} when read_tag => -- {{{ -- report "tag read by tmanager"; tmanager_waited_for_write_pipe_n(i) <= '0'; if tmanager_read_tag_ack_d0(i) = '1' then st_tmanager_n(i) <= issue_write; tmanager_issue_write_n(i) <= '1'; end if; -- }}} when issue_write => -- {{{ -- report "write issued"; if wr_issued_tmanager(i) = '1' then st_tmanager_n(i) <= wait_write_finish; tmanager_issue_write_n(i) <= '0'; end if; -- }}} when wait_write_finish => -- {{{ if axi_rd_fifo_filled(axi_wr_indx_tmanager(i)) = '1' then if tmanager_tag_to_write(i) = tmanager_gmem_addr(i)(TAG_W+M+L-1 downto M+L) then -- the tag to read is the same dirty one! -- the tmanager should wait until the write transaction is completely finished -- otherwise data may become inconsistent st_tmanager_n(i) <= wait_bid; -- report "match"; elsif tmanager_clear_dirty(i) = '1' then st_tmanager_n(i) <= clear_dirty; else -- - -- st_tmanager_n(i) <= validate_new_tag; -- alloc_tag_n(i) <= '1'; -- - -- + if rcv_rnw(rcv_indx_tmanager(i)) = '1' then st_tmanager_n(i) <= issue_read; wr_fifo_go_n(i) <= '1'; else st_tmanager_n(i) <= validate_new_tag; alloc_tag_n(i) <= '1'; end if; -- + end if; end if; -- }}} when wait_bid => -- {{{ if wait_for_write_response(i) = '0' then if tmanager_clear_dirty(i) = '1' then st_tmanager_n(i) <= clear_dirty; else -- - -- st_tmanager_n(i) <= validate_new_tag; -- alloc_tag_n(i) <= '1'; -- - -- + if rcv_rnw(rcv_indx_tmanager(i)) = '1' then st_tmanager_n(i) <= issue_read; wr_fifo_go_n(i) <= '1'; else st_tmanager_n(i) <= validate_new_tag; alloc_tag_n(i) <= '1'; end if; -- + end if; end if; -- }}} when clear_dirty => -- {{{ if tmanager_clear_dirty(i) = '0' then -- - -- st_tmanager_n(i) <= validate_new_tag; -- alloc_tag_n(i) <= '1'; -- - -- + if rcv_rnw(rcv_indx_tmanager(i)) = '1' then st_tmanager_n(i) <= issue_read; wr_fifo_go_n(i) <= '1'; else st_tmanager_n(i) <= validate_new_tag; alloc_tag_n(i) <= '1'; end if; -- + end if; -- }}} when issue_read => -- {{{ st_tmanager_n(i) <= wait_read_finish; -- }}} when wait_read_finish => -- {{{ if wr_fifo_free(i) = '1' then -- - -- st_tmanager_n(i) <= validate_new_page; -- validate_page_n(i) <= '1'; -- - -- + st_tmanager_n(i) <= validate_new_tag; alloc_tag_n(i) <= '1'; -- + end if; --}}} when validate_new_page => -- {{{ -- tmanager_wait_for_fifo_empty_n(i) <= '0'; -- tmanager_tag_protect_v_n(i) <= '1'; -- setting tag protect should be done 2 cycles before going to idle -- tmanager_tag_protect_n(i) <= tmanager_gmem_addr(i)(M+L-1 downto L); if page_v_tmanager_ack(i) = '1' then validate_page_n(i) <= '0'; st_tmanager_n(i) <= wait_page_v; end if; -- }}} when wait_page_v => -- {{{ st_tmanager_n(i) <= idle; tmanager_busy_n(i) <= '0'; tmanager_tag_protect_vec_n(i) <= '1'; tmanager_rcv_served_wait_vec_n(i) <= '1'; -- }}} end case; if tmanager_read_tag_ack_n(i) = '1' then tmanager_read_tag_n(i) <= '0'; end if; if tmanager_clear_dirty_ack(i) = '1' then tmanager_clear_dirty_n(i) <= '0'; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- tag mem -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then clear_tag <= clear_tag_n; we_tag <= we_tag_n; tmanager_read_tag_ack <= tmanager_read_tag_ack_n; tmanager_read_tag_ack_d0 <= tmanager_read_tag_ack; wrData_tag <= wrData_tag_n; wrAddr_tag <= wrAddr_tag_n; rdAddr_tag <= rdAddr_tag_n; rdData_tag_d0 <= rdData_tag_i(N_RD_PORTS-1); end if; end process; process(clk) begin if rising_edge(clk) then if we_tag = '1' then tag(to_integer(wrAddr_tag)) <= wrData_tag; end if; for i in 0 to N_RD_PORTS-1 loop rdData_tag_i(i) <= tag(to_integer(rdAddr_tag(i))); end loop; end if; end process; process(tmanager_gmem_addr, alloc_tag, clear_tag_tmanager, rcv_read_tag, rcv_gmem_addr, tmanager_read_tag, finish_active, finish_tag_addr) begin -- write tag alloc_tag_ack <= (others=>'0'); we_tag_n <= '0'; wrData_tag_n <= tmanager_gmem_addr(0)(GMEM_WORD_ADDR_W-N-1 downto L+M); wrAddr_tag_n <= tmanager_gmem_addr(0)(M+L-1 downto L); clear_tag_n <= '0'; for i in 0 to N_TAG_MANAGERS-1 loop -- linked with we_tag_v, don't change the order of the loop if alloc_tag(i) = '1' then alloc_tag_ack(i) <= '1'; we_tag_n <= not clear_tag_tmanager(i); clear_tag_n <= clear_tag_tmanager(i); wrData_tag_n <= tmanager_gmem_addr(i)(GMEM_WORD_ADDR_W-N-1 downto L+M); wrAddr_tag_n <= tmanager_gmem_addr(i)(M+L-1 downto L); exit; end if; end loop; -- read tag rcv_read_tag_ack <= (others=>'0'); -- first ports (default 3) serve the receivers for i in 0 to N_RD_PORTS-2 loop rdAddr_tag_n(i) <= rcv_gmem_addr(0)(L+M+N-1 downto L+N); for j in 0 to (N_RECEIVERS/N_RD_PORTS)-1 loop if rcv_read_tag(i + j*N_RD_PORTS) = '1' then rdAddr_tag_n(i) <= rcv_gmem_addr(i + j*N_RD_PORTS)(L+M+N-1 downto L+N); rcv_read_tag_ack(i + j*N_RD_PORTS) <= '1'; exit; end if; end loop; end loop; -- the last read port serves the tmanagers in addition to the receivers rdAddr_tag_n(N_RD_PORTS-1) <= rcv_gmem_addr(0)(L+M+N-1 downto L+N); tmanager_read_tag_ack_n <= (others=>'0'); if finish_active = '1' then rdAddr_tag_n(N_RD_PORTS-1) <= finish_tag_addr; elsif tmanager_read_tag /= (tmanager_read_tag'reverse_range=>'0') then for j in 0 to N_TAG_MANAGERS-1 loop if tmanager_read_tag(j) = '1' then rdAddr_tag_n(N_RD_PORTS-1) <= tmanager_gmem_addr(j)(L+M-1 downto L); tmanager_read_tag_ack_n(j) <= '1'; exit; end if; end loop; else for j in 0 to (N_RECEIVERS/N_RD_PORTS)-1 loop if rcv_read_tag(N_RD_PORTS-1 + j*N_RD_PORTS) = '1' then rdAddr_tag_n(N_RD_PORTS-1) <= rcv_gmem_addr(N_RD_PORTS-1 + j*N_RD_PORTS)(L+M+N-1 downto L+N); rcv_read_tag_ack(N_RD_PORTS-1 + j*N_RD_PORTS) <= '1'; exit; end if; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- tag_valid -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then we_tag_v <= we_tag_v_n; wrAddr_tag_v <= wrAddr_tag_v_n; wrData_tag_v <= wrData_tag_v_n; end if; end process; process(clk) begin if rising_edge(clk) then for i in 0 to N_RD_PORTS-1 loop rdData_tag_v(i) <= tag_v(to_integer(rdAddr_tag(i))); end loop; if we_tag_v = '1' then tag_v(to_integer(wrAddr_tag_v)) <= wrData_tag_v; end if; end if; end process; process(invalidate_tag, tmanager_gmem_addr, alloc_tag, clear_tag_tmanager, finish_active, finish_tag_addr_d0, finish_we) begin invalidate_tag_ack <= (others=>'0'); we_tag_v_n <= '0'; wrData_tag_v_n <= '0'; wrAddr_tag_v_n <= tmanager_gmem_addr(0)(M+L-1 downto L); if finish_active = '0' then if (alloc_tag and not clear_tag_tmanager) = (alloc_tag'reverse_range=>'0') then for i in 0 to N_TAG_MANAGERS-1 loop if invalidate_tag(i) = '1' then invalidate_tag_ack(i) <= '1'; we_tag_v_n <= '1'; wrData_tag_v_n <= '0'; wrAddr_tag_v_n <= tmanager_gmem_addr(i)(M+L-1 downto L); exit; end if; end loop; else -- this write has priority and it happes at the same time a tag is written for i in 0 to N_TAG_MANAGERS-1 loop if alloc_tag(i) = '1' then if clear_tag_tmanager(i) = '0' then we_tag_v_n <= '1'; wrAddr_tag_v_n <= tmanager_gmem_addr(i)(M+L-1 downto L); wrData_tag_v_n <= '1'; end if; exit; end if; end loop; end if; else we_tag_v_n <= finish_we; wrAddr_tag_v_n <= finish_tag_addr_d0; wrData_tag_v_n <= '0'; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- dirty mem -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then -- dirty memory for i in 0 to N_TAG_MANAGERS-1 loop rdData_dirty(i) <= dirty(to_integer(rdAddr_dirty(i))); end loop; if we_dirty = '1' then dirty(to_integer(wrAddr_dirty)) <= wrData_dirty; end if; end if; end process; process(clk) begin if rising_edge(clk) then we_dirty <= we_dirty_n; tmanager_clear_dirty_ack <= tmanager_clear_dirty_ack_n; if finish_active = '0' then rdAddr_dirty(0) <= tmanager_gmem_addr(0)(M+L-1 downto L); else rdAddr_dirty(0) <= finish_tag_addr; end if; if N_TAG_MANAGERS > 1 then for i in 1 to max(N_TAG_MANAGERS-1,1) loop rdAddr_dirty(i) <= tmanager_gmem_addr(i)(M+L-1 downto L); end loop; end if; wrData_dirty <= wrData_dirty_n; wrAddr_dirty <= wrAddr_dirty_n; end if; end process; process(cache_we, cache_addra, finish_active, finish_we, tmanager_clear_dirty, tmanager_gmem_addr, finish_tag_addr_d0) begin wrAddr_dirty_n <= cache_addra(M+L-1 downto L); tmanager_clear_dirty_ack_n <= (others=>'0'); if cache_we = '1' then wrData_dirty_n <= '1'; we_dirty_n <= '1'; elsif finish_active = '0' then wrData_dirty_n <= '0'; we_dirty_n <= '0'; for i in 0 to N_TAG_MANAGERS-1 loop if tmanager_clear_dirty(i) = '1' then tmanager_clear_dirty_ack_n(i) <= '1'; we_dirty_n <= '1'; wrAddr_dirty_n <= tmanager_gmem_addr(i)(M+L-1 downto L); exit; end if; end loop; else wrData_dirty_n <= '0'; we_dirty_n <= finish_we; wrAddr_dirty_n <= finish_tag_addr_d0; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- axi channels control -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then axi_wr_indx_tmanager <= axi_wr_indx_tmanager_n; wr_issued_tmanager <= wr_issued_tmanager_n; axi_wrAddr_i <= axi_wrAddr_n; axi_writer_go <= axi_writer_go_n; axi_writer_id <= axi_writer_id_n; for j in 0 to N_WR_FIFOS-1 loop axi_rdAddr(j)(L-1 downto 0) <= (others=>'0'); axi_rdAddr(j)(GMEM_WORD_ADDR_W-N-1 downto L) <= tmanager_gmem_addr(j)(GMEM_WORD_ADDR_W-N-1 downto L); end loop; if nrst = '0' then st_axi_wr <= find_free_fifo; wait_for_write_response <= (others=>'0'); else st_axi_wr <= st_axi_wr_n; wait_for_write_response <= wait_for_write_response_n; end if; end if; end process; issue_wr_axi: process(st_axi_wr, tmanager_issue_write, axi_writer_free, axi_wrAddr_i, tmanager_gmem_addr, tmanager_tag_to_write, finish_issue_write, axi_wr_indx_tmanager, finish_fifo_dout, wait_for_write_response, axi_writer_ack) begin axi_wr_indx_tmanager_n <= axi_wr_indx_tmanager; wr_issued_tmanager_n <= (others=>'0'); st_axi_wr_n <= st_axi_wr; for j in 0 to N_AXI-1 loop axi_wrAddr_n(j) <= axi_wrAddr_i(j); end loop; axi_writer_go_n <= (others=>'0'); axi_writer_id_n <= (others=>'0'); finish_fifo_pop <= '0'; for i in 0 to N_TAG_MANAGERS-1 loop if axi_writer_ack(i) = '1' then wait_for_write_response_n(i) <= '0'; else wait_for_write_response_n(i) <= wait_for_write_response(i); end if; end loop; case st_axi_wr is when find_free_fifo => for i in 0 to N_TAG_MANAGERS-1 loop if tmanager_issue_write(i) = '1' and axi_writer_free(c_rd_fifo_axi(i)) = '1' and wait_for_write_response(i) = '0' then axi_wr_indx_tmanager_n(i) <= c_rd_fifo_axi(i); wr_issued_tmanager_n(i) <= '1'; wait_for_write_response_n(i) <= '1'; axi_wrAddr_n(c_rd_fifo_axi(i))(GMEM_WORD_ADDR_W-N-1 downto L) <= tmanager_tag_to_write(i) & tmanager_gmem_addr(i)(M+L-1 downto L); -- if tmanager_tag_to_write(i) = tmanager_gmem_addr(i)(TAG_W+M+L-1 downto M+L) then -- report "match"; -- end if; axi_writer_go_n(c_rd_fifo_axi(i)) <= '1'; axi_writer_id_n <= std_logic_vector(to_unsigned(i, N_TAG_MANAGERS_W)); st_axi_wr_n <= issue_order; exit; end if; end loop; if finish_issue_write = '1' then for j in 0 to N_AXI-1 loop if axi_writer_free(j) = '1' then finish_fifo_pop <= '1'; axi_wrAddr_n(j)(GMEM_WORD_ADDR_W-N-1 downto L) <= finish_fifo_dout; axi_writer_go_n(j) <= '1'; st_axi_wr_n <= issue_order; exit; end if; end loop; end if; when issue_order => -- just a wait state st_axi_wr_n <= find_free_fifo; end case; end process; ---------------------------------------------------------------------------------------------------------}}} -- page_valid ------------------------------------------------------------------------------------------- {{{ process(clk) begin if rising_edge(clk) then wrAddr_page_v <= wrAddr_page_v_n; wrData_page_v <= wrData_page_v_n; we_page_v <= we_page_v_n; end if; end process; process(clk) begin if rising_edge(clk) then if we_page_v = '1' then page_v(to_integer(wrAddr_page_v)) <= wrData_page_v; end if; for i in 0 to N_RD_PORTS-1 loop rdData_page_v(i) <= page_v(to_integer(rdAddr_tag(i))); end loop; end if; end process; process(invalidate_page, validate_page, tmanager_gmem_addr, finish_active, finish_tag_addr_d0, finish_we) begin page_v_tmanager_ack <= (others=>'0'); we_page_v_n <= '0'; wrData_page_v_n <= '0'; wrAddr_page_v_n <= tmanager_gmem_addr(0)(M+L-1 downto L); for i in 0 to N_TAG_MANAGERS-1 loop if invalidate_page(i) = '1' then page_v_tmanager_ack(i) <= '1'; we_page_v_n <= '1'; wrData_page_v_n <= '0'; wrAddr_page_v_n <= tmanager_gmem_addr(i)(M+L-1 downto L); exit; end if; if validate_page(i) = '1' then page_v_tmanager_ack(i) <= '1'; we_page_v_n <= '1'; wrData_page_v_n <= '1'; wrAddr_page_v_n <= tmanager_gmem_addr(i)(M+L-1 downto L); exit; end if; end loop; if finish_active = '1' then we_page_v_n <= finish_we; wrData_page_v_n <= '0'; wrAddr_page_v_n <= finish_tag_addr_d0; end if; end process; --------------------------------------------------------------------------------------------------------- }}} -- rcv status eraly update -----------------------------------------------------------------------------------{{{ tag_trans: process(clk) begin if rising_edge(clk) then rcv_tag_written <= rcv_tag_written_n; rcv_tag_updated <= rcv_tag_updated_n; rcv_page_validated <= rcv_page_validated_n; end if; end process; process(we_page_v, rcv_gmem_addr, wrAddr_page_v, wrData_page_v) begin rcv_page_validated_n <= (others=>'0'); if we_page_v = '1' and wrData_page_v = '1' then for i in 0 to N_RECEIVERS-1 loop if rcv_gmem_addr(i)(M+L+N-1 downto N+L) = wrAddr_page_v then rcv_page_validated_n(i) <= '1'; end if; end loop; end if; -- for i in 0 to N_TAG_MANAGERS-1 loop -- if validate_page(i) = '1' then -- rcv_page_validated_n((i+1)*N_RECEIVERS/N_TAG_MANAGERS-1 downto i*N_RECEIVERS/N_TAG_MANAGERS) <= (others=>'1'); -- end if; -- end loop; end process; process(rcv_gmem_addr, wrAddr_tag, we_tag, wrData_tag, clear_tag) variable wrData_compared: std_logic := '0'; begin for i in 0 to N_RECEIVERS-1 loop if rcv_gmem_addr(i)(GMEM_WORD_ADDR_W-1 downto L+M+N) = wrData_tag then wrData_compared := '1'; else wrData_compared := '0'; end if; rcv_tag_written_n(i) <= '0'; rcv_tag_updated_n(i) <= '0'; if rcv_gmem_addr(i)(L+M+N-1 downto L+N) = wrAddr_tag then if we_tag = '1' and wrData_compared = '1' then rcv_tag_written_n(i) <= '1'; end if; if clear_tag = '1' or (we_tag = '1' and wrData_compared = '0') then rcv_tag_updated_n(i) <= '1'; end if; end if; end loop; end process; ---------------------------------------------------------------------------------------------------------}}} end architecture;

gpl-3.0

d7ad03f8bc1b5e86c207f04514c00d70

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fslt_2AXI_4CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 2; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

d5730168d4285270a67fec42f00dcb43

malkadi/FGPU

RTL/floating_point/fsqrt.vhd

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.1 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY fsqrt IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END fsqrt; ARCHITECTURE fsqrt_arch OF fsqrt IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF fsqrt_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_1_2 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER; C_FIXED_DATA_UNSIGNED : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_1_2; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_1_2 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 1, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 28, C_OPTIMIZATION => 1, C_MULT_USAGE => 0, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 0, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 0, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1, C_FIXED_DATA_UNSIGNED => 0 ) PORT MAP ( aclk => aclk, aclken => '1', aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => '0', s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END fsqrt_arch;

gpl-3.0

461b8c766e2b18b936eeb20fc880566e

preusser/q27

src/vhdl/queens/msg_tap.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.utils.all; entity msg_tap is generic ( D : positive -- Message Buffer Depth (Size) ); port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Tap Input iful : out std_logic; idat : in byte; ieof : in std_logic; iput : in std_logic; -- Tap Forward oful : in std_logic; odat : out byte; oeof : out std_logic; oput : out std_logic; -- Tap tful : in std_logic; tdat : out std_logic_vector(0 to 8*D-1); tput : out std_logic ); end msg_tap; library IEEE; use IEEE.numeric_std.all; architecture rtl of msg_tap is type tState is (Receive, Hold, Transmit); signal State : tState := Receive; signal Buf : byte_vector(0 to D-1) := (others => (others => '-')); signal Cnt : signed(log2ceil(imax(D-1, 1)) downto 0) := (others => '-'); begin process(clk) begin if rising_edge(clk) then if rst = '1' then State <= Receive; Buf <= (others => (others => '-')); Cnt <= (others => '-'); else case State is when Receive => Cnt <= (others => '-'); if iput = '1' then Buf <= Buf(1 to D-1) & idat; if ieof = '1' then State <= Hold; end if; end if; when Hold => Cnt <= (others => '-'); if tful = '0' then State <= Receive; elsif oful = '0' then Cnt <= to_signed(D-2, Cnt'length); State <= Transmit; end if; when Transmit => if oful = '0' then Buf <= Buf(1 to D-1) & byte'(7 downto 0 => '-'); Cnt <= Cnt - 1; if Cnt(Cnt'left) = '1' then State <= Receive; end if; end if; end case; end if; end if; end process; iful <= '0' when State = Receive else '1'; genParOut: for i in Buf'range generate tdat(8*i to 8*i+7) <= Buf(i); end generate genParOut; tput <= not tful when State = Hold else '0'; odat <= Buf(0); oeof <= Cnt(Cnt'left); oput <= '0' when State /= Transmit else '0' when oful = '1' else '1'; end rtl;

agpl-3.0

07724aea8e5ffb90d37be67eed5a4db8

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_8Stations.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

b6136fdfb9d6774cf3b47bc091e8d20c

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_6Stations_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

2c026ddbdfc513ba5fa5198546e4fa19

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_pkg.vhd

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mit

71790a5e36c1d3a7a83955d86649eab8

joalcava/sparcv8-monocicle

DM.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DataMemory is Port ( enableMem : in STD_LOGIC; reset : in STD_LOGIC; cRD : in STD_LOGIC_VECTOR (31 downto 0); address : in STD_LOGIC_VECTOR (31 downto 0); wrEnMem : in STD_LOGIC; datoToWr : out STD_LOGIC_VECTOR (31 downto 0) ); end DataMemory; architecture arqDataMemory of DataMemory is type ram_type is array (0 to 63) of std_logic_vector (31 downto 0); signal ramMemory : ram_type:=(others => x"00000000"); begin process(enableMem,reset,cRD,address,wrEnMem) begin if(enableMem = '1') then if(reset = '1')then datoToWr <= (others => '0'); ramMemory <= (others => x"00000000"); else if(wrEnMem = '0')then datoToWr <= ramMemory(conv_integer(address(5 downto 0))); else ramMemory(conv_integer(address(5 downto 0))) <= cRD; end if; end if; end if; end process; end arqDataMemory;

gpl-3.0

791f6fe907e0ee0109301231942cbf63

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_Atomic_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant ATOMIC_IMPLEMENT : natural := 1; constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

3399b5be760eb0668a77ebe0bac91ba3

joalcava/sparcv8-monocicle

Sparcv8Monocicle.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Sparcv8Monocicle is Port ( CLK : in STD_LOGIC; RST: in STD_LOGIC; R : out STD_LOGIC_VECTOR(31 downto 0) ); end Sparcv8Monocicle; architecture Behavioral of Sparcv8Monocicle is ---Componentes COMPONENT windows_manager PORT( cwp : IN std_logic; rs1 : IN std_logic_vector(4 downto 0); rs2 : IN std_logic_vector(4 downto 0); rd : IN std_logic_vector(4 downto 0); op : IN std_logic_vector(1 downto 0); op3 : IN std_logic_vector(5 downto 0); nrs1 : OUT std_logic_vector(5 downto 0); nrs2 : OUT std_logic_vector(5 downto 0); nrd : OUT std_logic_vector(5 downto 0); ncwp : OUT std_logic ); END COMPONENT; COMPONENT psr PORT( clk : IN std_logic; reset : IN std_logic; nzvc : IN std_logic_vector(3 downto 0); ncwp : IN std_logic; carry : OUT std_logic; cwp : OUT std_logic ); END COMPONENT; COMPONENT psr_modifier PORT( crs1 : IN std_logic; ope2 : IN std_logic; alur : IN std_logic_vector(31 downto 0); aluop : IN std_logic_vector(5 downto 0); nzvc : OUT std_logic_vector(3 downto 0) ); END COMPONENT; COMPONENT sum32b PORT( Op1 : IN std_logic_vector(31 downto 0); Op2 : IN std_logic_vector(31 downto 0); R : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT alu PORT( carry : IN std_logic; aluop : IN std_logic_vector(5 downto 0); crs1 : IN std_logic_vector(31 downto 0); crs2 : IN std_logic_vector(31 downto 0); r : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT control_unit PORT( op : IN std_logic_vector(1 downto 0); op2 : IN std_logic_vector(2 downto 0); op3 : IN std_logic_vector(5 downto 0); icc : IN std_logic_vector(3 downto 0); cond : IN std_logic_vector(3 downto 0); Aluop : OUT std_logic_vector(5 downto 0); wrenDM : OUT std_logic; RFSource : OUT std_logic_vector(1 downto 0); PCSource : OUT std_logic_vector(1 downto 0); RFdest : OUT std_logic; write_enable : OUT std_logic ); END COMPONENT; COMPONENT instructionMemory PORT( address : IN std_logic_vector(31 downto 0); reset : IN std_logic; outInstruction : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT mux32b PORT( A : IN std_logic_vector(31 downto 0); B : IN std_logic_vector(31 downto 0); Sel : IN std_logic; O : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT pc PORT( clk : IN std_logic; rst : IN std_logic; address : IN std_logic_vector(31 downto 0); sig : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT register_file PORT( Wren : IN std_logic; rst : IN std_logic; rs1 : IN std_logic_vector(5 downto 0); rs2 : IN std_logic_vector(5 downto 0); rd : IN std_logic_vector(5 downto 0); data : IN std_logic_vector(31 downto 0); crs1 : OUT std_logic_vector(31 downto 0); crs2 : OUT std_logic_vector(31 downto 0); crd : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT sign_ext_unit PORT( entrada : IN std_logic_vector(12 downto 0); salida : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT SEUDisp30 PORT( Disp30 : IN std_logic_vector(29 downto 0); S : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT SEUDisp22 PORT( Disp22 : IN std_logic_vector(21 downto 0); S : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT MuxPC PORT( PCdisp30 : IN std_logic_vector(31 downto 0); PCdisp22 : IN std_logic_vector(31 downto 0); PC : IN std_logic_vector(31 downto 0); PCplus1 : IN std_logic_vector(31 downto 0); PCSource : IN std_logic_vector(1 downto 0); nPC : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT MuxNextRD PORT( RD : IN std_logic_vector(5 downto 0); O7 : IN std_logic_vector(5 downto 0); RfDest : IN std_logic; NRd : OUT std_logic_vector(5 downto 0) ); END COMPONENT; COMPONENT MuxDWR PORT( DM : IN std_logic_vector(31 downto 0); AluR : IN std_logic_vector(31 downto 0); PC : IN std_logic_vector(31 downto 0); RFSource : IN std_logic_vector(1 downto 0); DTRF : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT DataMemory PORT( enableMem : IN std_logic; reset : IN std_logic; cRD : IN std_logic_vector(31 downto 0); address : IN std_logic_vector(31 downto 0); wrEnMem : IN std_logic; datoToWr : OUT std_logic_vector(31 downto 0) ); END COMPONENT; signal aux1,aux2,aux3,aux4,aux6,aux7,aux9,aux10,aux11,aux20,aux21,aux22,aux23,aux25,aux29,aux30,aux32:std_logic_vector(31 downto 0); signal aux5,aux14,aux15,aux16,aux27:std_logic_vector(5 downto 0); signal aux12,aux17,aux18,aux26,aux28,aux31: std_logic; signal aux24,aux34,aux33: std_logic_vector(1 downto 0); signal aux13:std_logic_vector(3 downto 0); begin ---Instancia de los componentes Inst_SEUDisp30: SEUDisp30 PORT MAP( Disp30 => aux4(29 downto 0), S => aux20 ); Inst_SEUDisp22: SEUDisp22 PORT MAP( Disp22 => aux4(21 downto 0), S => aux21 ); Inst_MuxPC: MuxPC PORT MAP( PCdisp30 => aux23, PCdisp22 => aux22, PC => aux3, PCplus1 => aux2, PCSource => aux24, nPC => aux25 ); Inst_MuxNextRD: MuxNextRD PORT MAP( RD => aux16, O7 => "001111", RfDest => aux26, NRd => aux27 ); Inst_MuxDWR: MuxDWR PORT MAP( DM => aux32, AluR => aux30, PC => aux3, RFSource => aux33, DTRF => aux10 ); Inst_DataMemory: DataMemory PORT MAP( enableMem => '1', reset => RST, cRD => aux29, address => aux30, wrEnMem => aux31, datoToWr => aux32 ); Inst_windows_manager: windows_manager PORT MAP( cwp => aux18, rs1 => aux4(18 downto 14), rs2 => aux4(4 downto 0), rd => aux4(29 downto 25), op => aux4(31 downto 30), op3 => aux4(24 downto 19), nrs1 => aux14, nrs2 => aux15, nrd => aux16, ncwp => aux17 ); Inst_psr: psr PORT MAP( clk => CLK, reset => RST, nzvc => aux13, ncwp => aux17, carry => aux12, cwp => aux18 ); Inst_psr_modifier: psr_modifier PORT MAP( crs1 => aux6(31), ope2 => aux9(31), alur => aux30, aluop => aux5, nzvc => aux13 ); Inst_sumPC: sum32b PORT MAP( Op1 => x"00000001", Op2 => aux1, R => aux2 ); Inst_sumDisp22: sum32b PORT MAP( Op1 => aux21, Op2 => aux3, R => aux22 ); Inst_sumDisp30: sum32b PORT MAP( Op1 => aux20, Op2 => aux3, R => aux23 ); Inst_alu: alu PORT MAP( carry => aux12, aluop => aux5, crs1 => aux6, crs2 => aux9, r => aux30 ); Inst_control_unit: control_unit PORT MAP( op => aux4(31 downto 30), op2 => aux4(24 downto 22), op3 => aux4(24 downto 19), icc => aux13, cond => aux4(28 downto 25), Aluop => aux5, wrenDM => aux31, RFSource => aux33, PCSource => aux24, RFdest => aux26, write_enable => aux28 ); Inst_instructionMemory: instructionMemory PORT MAP( address => aux3, reset => RST, outInstruction => aux4 ); Inst_mux32b: mux32b PORT MAP( A => aux7, B => aux11, Sel => aux4(13), O => aux9 ); Inst_pc: pc PORT MAP( clk => CLK, rst => RST, address => aux1, sig => aux3 ); Inst_npc: pc PORT MAP( clk => CLK, rst => RST, address => aux25, sig => aux1 ); Inst_register_file: register_file PORT MAP( Wren => aux28, rst => RST, rs1 => aux14, rs2 => aux15, rd => aux27, data => aux10, crs1 => aux6, crs2 => aux7, crd => aux29 ); Inst_sign_ext_unit: sign_ext_unit PORT MAP( entrada => aux4(12 downto 0), salida => aux11 ); R<=aux30; end Behavioral;

gpl-3.0

655d9ed71284db31feb668f2b6b5ba44

malkadi/FGPU

HW/sources/IPs/FGPU_2.1/hdl/FGPU_v2_1.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; library xil_defaultlib; use xil_defaultlib.all; ------------------------------------------------------------------------------------------------- }}} entity FGPU_v2_1 is -- generics {{{ generic ( -- Users to add parameters here -- User parameters ends -- Do not modify the parameters beyond this line -- Parameters of Axi Slave Bus Interface S0 C_S0_DATA_WIDTH : integer := 32; C_S0_ADDR_WIDTH : integer := 16; -- Parameters of Axi Master Bus Interface M0 C_M0_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M0_BURST_LEN : integer := 8; C_M0_ID_WIDTH : integer := 6; C_M0_ADDR_WIDTH : integer := 32; C_M0_DATA_WIDTH : integer := 64; C_M0_AWUSER_WIDTH : integer := 0; C_M0_ARUSER_WIDTH : integer := 0; C_M0_WUSER_WIDTH : integer := 0; C_M0_RUSER_WIDTH : integer := 0; C_M0_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M1 C_M1_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M1_BURST_LEN : integer := 8; C_M1_ID_WIDTH : integer := 6; C_M1_ADDR_WIDTH : integer := 32; C_M1_DATA_WIDTH : integer := 64; C_M1_AWUSER_WIDTH : integer := 0; C_M1_ARUSER_WIDTH : integer := 0; C_M1_WUSER_WIDTH : integer := 0; C_M1_RUSER_WIDTH : integer := 0; C_M1_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M2 C_M2_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M2_BURST_LEN : integer := 8; C_M2_ID_WIDTH : integer := 6; C_M2_ADDR_WIDTH : integer := 32; C_M2_DATA_WIDTH : integer := 64; C_M2_AWUSER_WIDTH : integer := 0; C_M2_ARUSER_WIDTH : integer := 0; C_M2_WUSER_WIDTH : integer := 0; C_M2_RUSER_WIDTH : integer := 0; C_M2_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M3 C_M3_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M3_BURST_LEN : integer := 8; C_M3_ID_WIDTH : integer := 6; C_M3_ADDR_WIDTH : integer := 32; C_M3_DATA_WIDTH : integer := 64; C_M3_AWUSER_WIDTH : integer := 0; C_M3_ARUSER_WIDTH : integer := 0; C_M3_WUSER_WIDTH : integer := 0; C_M3_RUSER_WIDTH : integer := 0; C_M3_BUSER_WIDTH : integer := 0 ); --}}} -- ports {{{ port ( -- Users to add ports here -- User ports ends -- Do not modify the ports beyond this line -- Ports of Axi Slave Bus Interface S0 {{{ s0_aclk : in std_logic; s0_aresetn : in std_logic; s0_awaddr : in std_logic_vector(C_S0_ADDR_WIDTH-1 downto 0); s0_awprot : in std_logic_vector(2 downto 0); s0_awvalid : in std_logic; s0_awready : out std_logic; s0_wdata : in std_logic_vector(C_S0_DATA_WIDTH-1 downto 0); s0_wstrb : in std_logic_vector((C_S0_DATA_WIDTH/8)-1 downto 0); s0_wvalid : in std_logic; s0_wready : out std_logic; s0_bresp : out std_logic_vector(1 downto 0); s0_bvalid : out std_logic; s0_bready : in std_logic; s0_araddr : in std_logic_vector(C_S0_ADDR_WIDTH-1 downto 0); s0_arprot : in std_logic_vector(2 downto 0); s0_arvalid : in std_logic; s0_arready : out std_logic; s0_rdata : out std_logic_vector(C_S0_DATA_WIDTH-1 downto 0); s0_rresp : out std_logic_vector(1 downto 0); s0_rvalid : out std_logic; s0_rready : in std_logic; -- }}} -- Ports of Axi Master Bus Interface M0 {{{ m0_aclk : in std_logic; m0_aresetn : in std_logic; m0_awid : out std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_awaddr : out std_logic_vector(C_M0_ADDR_WIDTH-1 downto 0); m0_awlen : out std_logic_vector(7 downto 0); m0_awsize : out std_logic_vector(2 downto 0); m0_awburst : out std_logic_vector(1 downto 0); m0_awlock : out std_logic; m0_awcache : out std_logic_vector(3 downto 0); m0_awprot : out std_logic_vector(2 downto 0); m0_awqos : out std_logic_vector(3 downto 0); m0_awuser : out std_logic_vector(C_M0_AWUSER_WIDTH-1 downto 0); m0_awvalid : out std_logic; m0_awready : in std_logic; m0_wdata : out std_logic_vector(C_M0_DATA_WIDTH-1 downto 0); m0_wstrb : out std_logic_vector(C_M0_DATA_WIDTH/8-1 downto 0); m0_wlast : out std_logic; m0_wuser : out std_logic_vector(C_M0_WUSER_WIDTH-1 downto 0); m0_wvalid : out std_logic; m0_wready : in std_logic; m0_bid : in std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_bresp : in std_logic_vector(1 downto 0); m0_buser : in std_logic_vector(C_M0_BUSER_WIDTH-1 downto 0); m0_bvalid : in std_logic; m0_bready : out std_logic; m0_arid : out std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_araddr : out std_logic_vector(C_M0_ADDR_WIDTH-1 downto 0); m0_arlen : out std_logic_vector(7 downto 0); m0_arsize : out std_logic_vector(2 downto 0); m0_arburst : out std_logic_vector(1 downto 0); m0_arlock : out std_logic; m0_arcache : out std_logic_vector(3 downto 0); m0_arprot : out std_logic_vector(2 downto 0); m0_arqos : out std_logic_vector(3 downto 0); m0_aruser : out std_logic_vector(C_M0_ARUSER_WIDTH-1 downto 0); m0_arvalid : out std_logic; m0_arready : in std_logic; m0_rid : in std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_rdata : in std_logic_vector(C_M0_DATA_WIDTH-1 downto 0); m0_rresp : in std_logic_vector(1 downto 0); m0_rlast : in std_logic; m0_ruser : in std_logic_vector(C_M0_RUSER_WIDTH-1 downto 0); m0_rvalid : in std_logic; m0_rready : out std_logic; --}}} -- Ports of Axi Master Bus Interface M1 {{{ m1_aclk : in std_logic; m1_aresetn : in std_logic; m1_awid : out std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_awaddr : out std_logic_vector(C_M1_ADDR_WIDTH-1 downto 0); m1_awlen : out std_logic_vector(7 downto 0); m1_awsize : out std_logic_vector(2 downto 0); m1_awburst : out std_logic_vector(1 downto 0); m1_awlock : out std_logic; m1_awcache : out std_logic_vector(3 downto 0); m1_awprot : out std_logic_vector(2 downto 0); m1_awqos : out std_logic_vector(3 downto 0); m1_awuser : out std_logic_vector(C_M1_AWUSER_WIDTH-1 downto 0); m1_awvalid : out std_logic; m1_awready : in std_logic; m1_wdata : out std_logic_vector(C_M1_DATA_WIDTH-1 downto 0); m1_wstrb : out std_logic_vector(C_M1_DATA_WIDTH/8-1 downto 0); m1_wlast : out std_logic; m1_wuser : out std_logic_vector(C_M1_WUSER_WIDTH-1 downto 0); m1_wvalid : out std_logic; m1_wready : in std_logic; m1_bid : in std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_bresp : in std_logic_vector(1 downto 0); m1_buser : in std_logic_vector(C_M1_BUSER_WIDTH-1 downto 0); m1_bvalid : in std_logic; m1_bready : out std_logic; m1_arid : out std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_araddr : out std_logic_vector(C_M1_ADDR_WIDTH-1 downto 0); m1_arlen : out std_logic_vector(7 downto 0); m1_arsize : out std_logic_vector(2 downto 0); m1_arburst : out std_logic_vector(1 downto 0); m1_arlock : out std_logic; m1_arcache : out std_logic_vector(3 downto 0); m1_arprot : out std_logic_vector(2 downto 0); m1_arqos : out std_logic_vector(3 downto 0); m1_aruser : out std_logic_vector(C_M1_ARUSER_WIDTH-1 downto 0); m1_arvalid : out std_logic; m1_arready : in std_logic; m1_rid : in std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_rdata : in std_logic_vector(C_M1_DATA_WIDTH-1 downto 0); m1_rresp : in std_logic_vector(1 downto 0); m1_rlast : in std_logic; m1_ruser : in std_logic_vector(C_M1_RUSER_WIDTH-1 downto 0); m1_rvalid : in std_logic; m1_rready : out std_logic; -- }}} -- Ports of Axi Master Bus Interface M2 {{{ m2_aclk : in std_logic; m2_aresetn : in std_logic; m2_awid : out std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_awaddr : out std_logic_vector(C_M2_ADDR_WIDTH-1 downto 0); m2_awlen : out std_logic_vector(7 downto 0); m2_awsize : out std_logic_vector(2 downto 0); m2_awburst : out std_logic_vector(1 downto 0); m2_awlock : out std_logic; m2_awcache : out std_logic_vector(3 downto 0); m2_awprot : out std_logic_vector(2 downto 0); m2_awqos : out std_logic_vector(3 downto 0); m2_awuser : out std_logic_vector(C_M2_AWUSER_WIDTH-1 downto 0); m2_awvalid : out std_logic; m2_awready : in std_logic; m2_wdata : out std_logic_vector(C_M2_DATA_WIDTH-1 downto 0); m2_wstrb : out std_logic_vector(C_M2_DATA_WIDTH/8-1 downto 0); m2_wlast : out std_logic; m2_wuser : out std_logic_vector(C_M2_WUSER_WIDTH-1 downto 0); m2_wvalid : out std_logic; m2_wready : in std_logic; m2_bid : in std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_bresp : in std_logic_vector(1 downto 0); m2_buser : in std_logic_vector(C_M2_BUSER_WIDTH-1 downto 0); m2_bvalid : in std_logic; m2_bready : out std_logic; m2_arid : out std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_araddr : out std_logic_vector(C_M2_ADDR_WIDTH-1 downto 0); m2_arlen : out std_logic_vector(7 downto 0); m2_arsize : out std_logic_vector(2 downto 0); m2_arburst : out std_logic_vector(1 downto 0); m2_arlock : out std_logic; m2_arcache : out std_logic_vector(3 downto 0); m2_arprot : out std_logic_vector(2 downto 0); m2_arqos : out std_logic_vector(3 downto 0); m2_aruser : out std_logic_vector(C_M2_ARUSER_WIDTH-1 downto 0); m2_arvalid : out std_logic; m2_arready : in std_logic; m2_rid : in std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_rdata : in std_logic_vector(C_M2_DATA_WIDTH-1 downto 0); m2_rresp : in std_logic_vector(1 downto 0); m2_rlast : in std_logic; m2_ruser : in std_logic_vector(C_M2_RUSER_WIDTH-1 downto 0); m2_rvalid : in std_logic; m2_rready : out std_logic; -- }}} -- Ports of Axi Master Bus Interface M3 {{{ m3_aclk : in std_logic; m3_aresetn : in std_logic; m3_awid : out std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_awaddr : out std_logic_vector(C_M3_ADDR_WIDTH-1 downto 0); m3_awlen : out std_logic_vector(7 downto 0); m3_awsize : out std_logic_vector(2 downto 0); m3_awburst : out std_logic_vector(1 downto 0); m3_awlock : out std_logic; m3_awcache : out std_logic_vector(3 downto 0); m3_awprot : out std_logic_vector(2 downto 0); m3_awqos : out std_logic_vector(3 downto 0); m3_awuser : out std_logic_vector(C_M3_AWUSER_WIDTH-1 downto 0); m3_awvalid : out std_logic; m3_awready : in std_logic; m3_wdata : out std_logic_vector(C_M3_DATA_WIDTH-1 downto 0); m3_wstrb : out std_logic_vector(C_M3_DATA_WIDTH/8-1 downto 0); m3_wlast : out std_logic; m3_wuser : out std_logic_vector(C_M3_WUSER_WIDTH-1 downto 0); m3_wvalid : out std_logic; m3_wready : in std_logic; m3_bid : in std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_bresp : in std_logic_vector(1 downto 0); m3_buser : in std_logic_vector(C_M3_BUSER_WIDTH-1 downto 0); m3_bvalid : in std_logic; m3_bready : out std_logic; m3_arid : out std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_araddr : out std_logic_vector(C_M3_ADDR_WIDTH-1 downto 0); m3_arlen : out std_logic_vector(7 downto 0); m3_arsize : out std_logic_vector(2 downto 0); m3_arburst : out std_logic_vector(1 downto 0); m3_arlock : out std_logic; m3_arcache : out std_logic_vector(3 downto 0); m3_arprot : out std_logic_vector(2 downto 0); m3_arqos : out std_logic_vector(3 downto 0); m3_aruser : out std_logic_vector(C_M3_ARUSER_WIDTH-1 downto 0); m3_arvalid : out std_logic; m3_arready : in std_logic; m3_rid : in std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_rdata : in std_logic_vector(C_M3_DATA_WIDTH-1 downto 0); m3_rresp : in std_logic_vector(1 downto 0); m3_rlast : in std_logic; m3_ruser : in std_logic_vector(C_M3_RUSER_WIDTH-1 downto 0); m3_rvalid : in std_logic; m3_rready : out std_logic -- }}} ); --}}} end FGPU_v2_1; architecture arch_imp of FGPU_v2_1 is signal nrst : std_logic := '0'; begin -- fixed signals ------------------------------------------------------------------------------------{{{ -- m0 {{{ m0_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m0_awcache <= "0010"; m0_awprot <= "000"; m0_awqos <= X"0"; m0_arlock <= '0'; m0_arcache <= "0010"; m0_arprot <= "000"; m0_arqos <= X"0"; -- }}} -- m1 {{{ m1_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m1_awcache <= "0010"; m1_awprot <= "000"; m1_awqos <= X"0"; m1_arlock <= '0'; m1_arcache <= "0010"; m1_arprot <= "000"; m1_arqos <= X"0"; --}}} -- m2 {{{ m2_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m2_awcache <= "0010"; m2_awprot <= "000"; m2_awqos <= X"0"; m2_arlock <= '0'; m2_arcache <= "0010"; m2_arprot <= "000"; m2_arqos <= X"0"; -- }}} -- m3 {{{ m3_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m3_awcache <= "0010"; m3_awprot <= "000"; m3_awqos <= X"0"; m3_arlock <= '0'; m3_arcache <= "0010"; m3_arprot <= "000"; m3_arqos <= X"0"; -- }}} ---------------------------------------------------------------------------------------------------------}}} process(s0_aclk) begin if rising_edge(s0_aclk) then nrst <= s0_aresetn and m0_aresetn and m1_aresetn and m2_aresetn and m3_aresetn; end if; end process; uut: entity FGPU PORT MAP ( clk => s0_aclk, -- slave axi {{{ s0_awaddr => s0_awaddr(C_S0_ADDR_WIDTH-1 downto 2), s0_awprot => s0_awprot, s0_awvalid => s0_awvalid, s0_awready => s0_awready, s0_wdata => s0_wdata, s0_wstrb => s0_wstrb, s0_wvalid => s0_wvalid, s0_wready => s0_wready, s0_bresp => s0_bresp, s0_bvalid => s0_bvalid, s0_bready => s0_bready, s0_araddr => s0_araddr(C_S0_ADDR_WIDTH-1 downto 2), s0_arprot => s0_arprot, s0_arvalid => s0_arvalid, s0_arready => s0_arready, s0_rdata => s0_rdata, s0_rresp => s0_rresp, s0_rvalid => s0_rvalid, s0_rready => s0_rready, -- }}} -- axi master 0 connections {{{ -- ar channel m0_araddr => m0_araddr, m0_arlen => m0_arlen, m0_arsize => m0_arsize, m0_arburst => m0_arburst, m0_arvalid => m0_arvalid, m0_arready => m0_arready, m0_arid => m0_arid, -- r channel m0_rdata => m0_rdata, m0_rresp => m0_rresp, m0_rlast => m0_rlast, m0_rvalid => m0_rvalid, m0_rready => m0_rready, m0_rid => m0_rid, -- aw channel m0_awvalid => m0_awvalid, m0_awaddr => m0_awaddr, m0_awready => m0_awready, m0_awlen => m0_awlen, m0_awsize => m0_awsize, m0_awburst => m0_awburst, m0_awid => m0_awid, -- w channel m0_wdata => m0_wdata, m0_wstrb => m0_wstrb, m0_wlast => m0_wlast, m0_wvalid => m0_wvalid, m0_wready => m0_wready, -- b channel m0_bvalid => m0_bvalid, m0_bready => m0_bready, m0_bid => m0_bid, -- }}} -- axi master 1 connections {{{ -- ar channel m1_araddr => m2_araddr, m1_arlen => m2_arlen, m1_arsize => m2_arsize, m1_arburst => m2_arburst, m1_arvalid => m2_arvalid, m1_arready => m2_arready, m1_arid => m2_arid, -- r channel m1_rdata => m2_rdata, m1_rresp => m2_rresp, m1_rlast => m2_rlast, m1_rvalid => m2_rvalid, m1_rready => m2_rready, m1_rid => m2_rid, -- aw channel m1_awvalid => m2_awvalid, m1_awaddr => m2_awaddr, m1_awready => m2_awready, m1_awlen => m2_awlen, m1_awsize => m2_awsize, m1_awburst => m2_awburst, m1_awid => m2_awid, -- w channel m1_wdata => m2_wdata, m1_wstrb => m2_wstrb, m1_wlast => m2_wlast, m1_wvalid => m2_wvalid, m1_wready => m2_wready, -- b channel m1_bvalid => m2_bvalid, m1_bready => m2_bready, m1_bid => m2_bid, -- }}} -- axi master 2 connections {{{ -- ar channel m2_araddr => m1_araddr, m2_arlen => m1_arlen, m2_arsize => m1_arsize, m2_arburst => m1_arburst, m2_arvalid => m1_arvalid, m2_arready => m1_arready, m2_arid => m1_arid, -- r channel m2_rdata => m1_rdata, m2_rresp => m1_rresp, m2_rlast => m1_rlast, m2_rvalid => m1_rvalid, m2_rready => m1_rready, m2_rid => m1_rid, -- aw channel m2_awvalid => m1_awvalid, m2_awaddr => m1_awaddr, m2_awready => m1_awready, m2_awlen => m1_awlen, m2_awsize => m1_awsize, m2_awburst => m1_awburst, m2_awid => m1_awid, -- w channel m2_wdata => m1_wdata, m2_wstrb => m1_wstrb, m2_wlast => m1_wlast, m2_wvalid => m1_wvalid, m2_wready => m1_wready, -- b channel m2_bvalid => m1_bvalid, m2_bready => m1_bready, m2_bid => m1_bid, -- }}} -- axi master 3 connections {{{ -- ar channel m3_araddr => m3_araddr, m3_arlen => m3_arlen, m3_arsize => m3_arsize, m3_arburst => m3_arburst, m3_arvalid => m3_arvalid, m3_arready => m3_arready, m3_arid => m3_arid, -- r channel m3_rdata => m3_rdata, m3_rresp => m3_rresp, m3_rlast => m3_rlast, m3_rvalid => m3_rvalid, m3_rready => m3_rready, m3_rid => m3_rid, -- aw channel m3_awvalid => m3_awvalid, m3_awaddr => m3_awaddr, m3_awready => m3_awready, m3_awlen => m3_awlen, m3_awsize => m3_awsize, m3_awburst => m3_awburst, m3_awid => m3_awid, -- w channel m3_wdata => m3_wdata, m3_wstrb => m3_wstrb, m3_wlast => m3_wlast, m3_wvalid => m3_wvalid, m3_wready => m3_wready, -- b channel m3_bvalid => m3_bvalid, m3_bready => m3_bready, m3_bid => m3_bid, -- }}} nrst => nrst ); end arch_imp;

gpl-3.0

82be568a0f583d9fafc3942274b061b9

preusser/q27

src/vhdl/queens/queens_slice0_tb.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2016 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This testbench is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- entity queens_slice0_tb is generic ( N : positive := 16 -- Choose your board size ); end queens_slice0_tb; library IEEE; use IEEE.std_logic_1164.all; architecture tb of queens_slice0_tb is component queens_slice generic ( N : positive; -- size of field L : natural -- number of preplaced columns ); port ( clk : in std_logic; rst : in std_logic; start : in std_logic; BH_l : in std_logic_vector(0 to N-2*L-1); BU_l : in std_logic_vector(0 to 2*N-4*L-2); BD_l : in std_logic_vector(0 to 2*N-4*L-2); BV_l : in std_logic_vector(0 to N-2*L-1); sol : out std_logic; done : out std_logic ); end component; --Inputs signal clk : std_logic; signal rst : std_logic; signal start : std_logic; --Outputs signal sol : std_logic; signal done : std_logic; begin dut: queens_slice generic map ( N => N, L => 0 ) port map ( clk => clk, rst => rst, start => start, BH_l => (others => '0'), BV_l => (others => '0'), BU_l => (others => '0'), BD_l => (others => '0'), sol => sol, done => done ); -- Driver process procedure cycle is begin clk <= '0'; wait for 5 ns; clk <= '1'; wait for 5 ns; end; begin rst <= '1'; cycle; rst <= '0'; start <= '0'; cycle; start <= '1'; cycle; start <= '0'; while done = '0' loop cycle; end loop; cycle; wait; -- forever end process; -- Log and Report process variable cycs : natural; variable sols : natural; begin cycs := 0; sols := 0; wait until rising_edge(clk) and start = '1'; loop wait until rising_edge(clk); cycs := cycs + 1; if sol = '1' then sols := sols + 1; end if; exit when done = '1'; end loop; report "Found "&integer'image(sols)& " solutions in "&integer'image(cycs)&" clock cycles."; end process; end tb;

agpl-3.0

e97808ced03b3916b71330b31e9a4891

jpidancet/mips

rtl/cpu_execute.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; library work; use work.mips_defs.ALL; entity cpu_execute is port (rt : in std_logic_vector(4 downto 0); rd : in std_logic_vector(4 downto 0); shamt : in std_logic_vector(4 downto 0); imm : in std_logic_vector(31 downto 0); alusrc : in std_logic; regdst : in std_logic; alucontrol : in alucontrol_type; ovf_en : in std_logic; rd1 : in std_logic_vector(31 downto 0); rd2 : in std_logic_vector(31 downto 0); regwrite : in std_logic; memtoreg : in std_logic; memread : in std_logic; memwrite : in std_logic; regwrite_n : out std_logic; memtoreg_n : out std_logic; memread_n : out std_logic; memwrite_n : out std_logic; aluout_n : out std_logic_vector(31 downto 0); writedata_n : out std_logic_vector(31 downto 0); writereg_n : out std_logic_vector(4 downto 0); -- Forward forward_a : in std_logic_vector(1 downto 0); forward_b : in std_logic_vector(1 downto 0); aluout_fwd : in std_logic_vector(31 downto 0); result_fwd : in std_logic_vector(31 downto 0)); end entity cpu_execute; architecture rtl of cpu_execute is component alu is port (op : in alucontrol_type; a : in std_logic_vector(31 downto 0); b : in std_logic_vector(31 downto 0); shift : in std_logic_vector(5 downto 0); result : out std_logic_vector(31 downto 0); overflow : out std_logic); end component alu; signal writedata : std_logic_vector(31 downto 0); signal srca : std_logic_vector(31 downto 0); signal srcb : std_logic_vector(31 downto 0); signal overflow : std_logic; signal interrupt : std_logic; begin srca <= aluout_fwd when forward_a = "10" else result_fwd when forward_a = "01" else rd1; writedata <= aluout_fwd when forward_b = "10" else result_fwd when forward_b = "01" else rd2; srcb <= imm when alusrc = '1' else writedata; regwrite_n <= regwrite; memtoreg_n <= memtoreg; memread_n <= memread; memwrite_n <= memwrite; writedata_n <= writedata; writereg_n <= rd when regdst = '1' else rt; alu0: alu port map (op => alucontrol, a => srca, b => srcb, shift => shamt, result => aluout_n, overflow => overflow); interrupt <= ovf_en and overflow; end architecture rtl;

isc

c9d1b9ba3debdab59f955e6e95bef9eb

preusser/q27

src/vhdl/top/dnk7_f5/dnk7_queens0.vhdl

library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity dnk7_queens0 is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 240; COUNT_CYCLES : boolean := false; SENTINEL : std_logic_vector(7 downto 0) := x"FA"; -- Start Byte -- Local Clock Parameters CLK_FREQ : FREQ := 50 MHz; CLK_DIV : positive := 1; -- CLK_FREQ / CLK_DIV * CLK_MUL: CLK_MUL : positive := 22; -- as fast as possible but not above 1200 MHz -- Output Clocks CLK_DIV_COMP : positive := 5; -- fast computation clock CLK_DIV_SLOW : positive := 15 -- slower communication clock ); port ( --------------------------------------------------------------------------- -- 50-MHz Input Clock CLK_MBCLK : in std_logic; --------------------------------------------------------------------------- -- FPGA0: PCIe Interface BUS_PCIE_CLK_IN_P : in std_logic; BUS_PCIE_CLK_IN_N : in std_logic; BUS_PCIE_CLK_OUT_P : out std_logic; BUS_PCIE_CLK_OUT_N : out std_logic; BUS_PCIE_TO_HOST : out std_logic_vector(38 downto 0); BUS_PCIE_FROM_HOST : in std_logic_vector(77 downto 39); --------------------------------------------------------------------------- -- Ring Bus -- Output BUS_OUT_CLKP : out std_logic; BUS_OUT_CLKN : out std_logic; BUS_OUT_PRE_DAT : out std_logic_vector(8 downto 0); BUS_OUT_PRE_PUT : out std_logic; BUS_OUT_PRE_STALL : in std_logic; BUS_OUT_SOL_DAT : out std_logic_vector(8 downto 0); BUS_OUT_SOL_PUT : out std_logic; BUS_OUT_SOL_STALL : in std_logic; -- Input BUS_IN_CLKP : in std_logic; BUS_IN_CLKN : in std_logic; BUS_IN_PRE_DAT : in std_logic_vector(8 downto 0); BUS_IN_PRE_PUT : in std_logic; BUS_IN_PRE_STALL : out std_logic; BUS_IN_SOL_DAT : in std_logic_vector(8 downto 0); BUS_IN_SOL_PUT : in std_logic; BUS_IN_SOL_STALL : out std_logic ); end entity dnk7_queens0; library IEEE; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.fifo.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of dnk7_queens0 is ---------------------------------------------------------------------------- -- Communication Addresses -- Word Address: Read Write ----------------------------------------------------------------------------- -- 0x0000 <byte capacity:32> <-:30><enable:2> input interrupt -- 0x0004 <bytes available:32> <-:30><enable:2> output interrupt -- 0x0008 <!vld:1><0:23><data_out:8> <-:24><data_in:8> -- -- A data read (@ 0x8) implicitly clears an output interrupt. -- A data write (@ 0x8) implicitly clears an input interrupt. -- constant ADDR_STATUS : natural := 16#00#; -- status word, interrupt clearance constant ADDR_STREAM : natural := 16#08#; -- data stream in- and output constant ADDR_BITS : positive := 4; -- relevant address bits (at least 4) -- Bit Length of Pre-Placement constant PRE_BITS : positive := 4*L*log2ceil(N)-1; constant PRE_BYTES : positive := (PRE_BITS+7)/8; -- FIFO Dimensioning constant FIFO_DEPTH : positive := 5*(SOLVERS+5); constant STATE_BITS : natural := log2ceil(FIFO_DEPTH); ---------------------------------------------------------------------------- component reset_resync is generic ( VALUE_DURING_RESET : natural := 1 ); port ( rst_in : in std_logic; clk_in : in std_logic; clk_out : in std_logic; rst_out : out std_logic ); end component; component pcie_ddr_user_interface is generic ( DCM_PHASE_SHIFT : natural := 30; DCM_PERIOD : natural := 10; DMA_ENGINE_ENABLES : natural := 7 ); port ( reset : in std_logic; reset_out : out std_logic; user_clk : in std_logic; clk_out : out std_logic; dcm_psdone : out std_logic; dcm_psval : out std_logic_vector(16 downto 0); dcm_psclk : in std_logic; dcm_psen : in std_logic; dcm_psincdec : in std_logic; target_address : out std_logic_vector(63 downto 0); target_write_data : out std_logic_vector(63 downto 0); target_write_be : out std_logic_vector(7 downto 0); target_address_valid : out std_logic; target_write_enable : out std_logic; target_write_accept : in std_logic; target_read_enable : out std_logic; target_request_tag : out std_logic_vector(3 downto 0); target_read_data : in std_logic_vector(63 downto 0); target_read_accept : in std_logic; target_read_data_tag : in std_logic_vector(3 downto 0); target_read_data_valid : in std_logic; target_read_ctrl : out std_logic_vector(7 downto 0); target_read_data_ctrl : in std_logic_vector(7 downto 0); dma0_from_host_data : out std_logic_vector(63 downto 0); dma0_from_host_ctrl : out std_logic_vector(7 downto 0); dma0_from_host_valid : out std_logic; dma0_from_host_advance : in std_logic; dma1_from_host_data : out std_logic_vector(63 downto 0); dma1_from_host_ctrl : out std_logic_vector(7 downto 0); dma1_from_host_valid : out std_logic; dma1_from_host_advance : in std_logic; dma2_from_host_data : out std_logic_vector(63 downto 0); dma2_from_host_ctrl : out std_logic_vector(7 downto 0); dma2_from_host_valid : out std_logic; dma2_from_host_advance : in std_logic; dma0_to_host_data : in std_logic_vector(63 downto 0); dma0_to_host_ctrl : in std_logic_vector(7 downto 0); dma0_to_host_valid : in std_logic; dma0_to_host_almost_full : out std_logic; dma1_to_host_data : in std_logic_vector(63 downto 0); dma1_to_host_ctrl : in std_logic_vector(7 downto 0); dma1_to_host_valid : in std_logic; dma1_to_host_almost_full : out std_logic; dma2_to_host_data : in std_logic_vector(63 downto 0); dma2_to_host_ctrl : in std_logic_vector(7 downto 0); dma2_to_host_valid : in std_logic; dma2_to_host_almost_full : out std_logic; user_interrupts : in std_logic; pcie_fromhost_counter : out std_logic_vector(31 downto 0); PCIE_TO_HOST_DDR : out std_logic_vector(38 downto 0); PCIE_TO_HOST_CLK_P : out std_logic; PCIE_TO_HOST_CLK_N : out std_logic; PCIE_FROM_HOST_DDR : in std_logic_vector(37 downto 0); PCIE_FROM_HOST_CLK_P : in std_logic; PCIE_FROM_HOST_CLK_N : in std_logic ); end component; ---------------------------------------------------------------------------- -- Global Control signal clk_comp : std_logic; signal rst_comp : std_logic; signal clk_slow : std_logic; signal rst_slow : std_logic; ----------------------------------------------------------------------------- -- Communication FIFOs signal acap : std_logic_vector(STATE_BITS-1 downto 0); signal avld : std_logic; signal aful : std_logic; signal adin : std_logic_vector(7 downto 0); signal aput : std_logic; signal bavl : std_logic_vector(STATE_BITS-1 downto 0); signal bvld : std_logic; signal bful : std_logic; signal bdout : std_logic_vector(7 downto 0); signal bgot : std_logic; begin ---------------------------------------------------------------------------- -- Clock Generation blkClock : block signal clk50 : std_logic; signal clkfb : std_logic; signal clk_compu : std_logic; signal clk_slowu : std_logic; begin clk_i : BUFG port map ( I => CLK_MBCLK, O => clk50 ); pll : PLLE2_BASE generic map ( CLKIN1_PERIOD => to_real(to_time(CLK_FREQ), 1 ns), DIVCLK_DIVIDE => CLK_DIV, CLKFBOUT_MULT => CLK_MUL, CLKOUT0_DIVIDE => CLK_DIV_COMP, CLKOUT1_DIVIDE => CLK_DIV_SLOW, STARTUP_WAIT => "true" ) port map ( RST => '0', CLKIN1 => clk50, CLKFBOUT => clkfb, CLKFBIN => clkfb, CLKOUT0 => clk_compu, CLKOUT1 => clk_slowu, CLKOUT2 => open, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, LOCKED => open, PWRDWN => '0' ); clk_compo : BUFG port map ( I => clk_compu, O => clk_comp ); clk_slowo : BUFG port map ( I => clk_slowu, O => clk_slow ); end block; ---------------------------------------------------------------------------- -- PCIe -> Target Interface blkPcie: block -- Local Clock signal pcie_clk : std_logic; signal pcie_rst : std_logic; -- Target Interface -- Address signal target_address : std_logic_vector(63 downto 0); signal target_address_valid : std_logic; -- Writing signal target_write_enable : std_logic; signal target_write_accept : std_logic; signal target_write_data : std_logic_vector(63 downto 0); signal target_write_be : std_logic_vector( 7 downto 0); -- Reading signal target_read_enable : std_logic; signal target_read_accept : std_logic; signal target_request_tag : std_logic_vector(3 downto 0); signal target_read_ctrl : std_logic_vector(7 downto 0); signal target_read_data_valid : std_logic; signal target_read_data : std_logic_vector(63 downto 0); signal target_read_data_tag : std_logic_vector(3 downto 0); signal target_read_data_ctrl : std_logic_vector(7 downto 0); -- Interrupt signal user_interrupt : std_logic; begin -- Reset Recovery resync_comp: reset_resync port map ( rst_in => pcie_rst, clk_in => pcie_clk, clk_out => clk_comp, rst_out => rst_comp ); resync_slow: reset_resync port map ( rst_in => pcie_rst, clk_in => pcie_clk, clk_out => clk_slow, rst_out => rst_slow ); --------------------------------------------------------------------------- -- PCIE <-> Target Interface pcie: pcie_ddr_user_interface generic map ( DCM_PERIOD => 6, DCM_PHASE_SHIFT => 198 ) port map ( reset => '0', reset_out => pcie_rst, clk_out => pcie_clk, user_clk => clk_slow, PCIE_TO_HOST_DDR => bus_pcie_to_host, PCIE_TO_HOST_CLK_P => bus_pcie_clk_out_p, PCIE_TO_HOST_CLK_N => bus_pcie_clk_out_n, PCIE_FROM_HOST_DDR => bus_pcie_from_host(76 downto 39), PCIE_FROM_HOST_CLK_P => bus_pcie_clk_in_p, PCIE_FROM_HOST_CLK_N => bus_pcie_clk_in_n, pcie_fromhost_counter => open, user_interrupts => user_interrupt, target_address => target_address, target_address_valid => target_address_valid, target_write_enable => target_write_enable, target_write_accept => target_write_accept, target_write_data => target_write_data, target_write_be => target_write_be, target_read_enable => target_read_enable, target_read_accept => target_read_accept, target_request_tag => target_request_tag, target_read_ctrl => target_read_ctrl, target_read_data_valid => target_read_data_valid, target_read_data => target_read_data, target_read_data_tag => target_read_data_tag, target_read_data_ctrl => target_read_data_ctrl, dma0_from_host_data => open, dma0_from_host_ctrl => open, dma0_from_host_valid => open, dma0_from_host_advance => '1', dma0_to_host_data => (others => '-'), dma0_to_host_ctrl => (others => '0'), dma0_to_host_valid => '0', dma0_to_host_almost_full => open, dma1_from_host_data => open, dma1_from_host_ctrl => open, dma1_from_host_valid => open, dma1_from_host_advance => '1', dma1_to_host_data => (others => '-'), dma1_to_host_ctrl => (others => '0'), dma1_to_host_valid => '0', dma1_to_host_almost_full => open, dma2_from_host_data => open, dma2_from_host_ctrl => open, dma2_from_host_valid => open, dma2_from_host_advance => '1', dma2_to_host_data => (others => '-'), dma2_to_host_ctrl => (others => '0'), dma2_to_host_valid => '0', dma2_to_host_almost_full => open, dcm_psdone => open, dcm_psval => open, dcm_psclk => clk_slow, dcm_psen => '0', dcm_psincdec => '0' ); --------------------------------------------------------------------------- -- Writing target_write_accept <= '1'; aput <= target_write_enable and target_write_be(0) when to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) = ADDR_STREAM else '0'; adin <= target_write_data(7 downto 0); --------------------------------------------------------------------------- -- Reading bgot <= '0' when to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) /= ADDR_STREAM else target_read_enable; blkRead: block signal rdVld : std_logic := '0'; signal rdTag : std_logic_vector( 3 downto 0) := (others => '-'); signal rdCtl : std_logic_vector( 7 downto 0) := (others => '-'); signal rdDat : std_logic_vector(63 downto 0) := (others => '-'); begin process(clk_slow) begin if rising_edge(clk_slow) then rdVld <= '0'; rdTag <= (others => '-'); rdCtl <= (others => '-'); rdDat <= (others => '-'); if rst_slow = '0' then -- Only accept word-align addresses if target_read_enable = '1' and target_address(1 downto 0) = "00" then rdVld <= '1'; rdTag <= target_request_tag; rdCtl <= target_read_ctrl; rdDat <= (others => '0'); if to_integer(unsigned(target_address(ADDR_BITS-1 downto 3))) = ADDR_STATUS/8 then -- Query FIFO States rdDat(STATE_BITS+31 downto 32) <= bavl; -- @4 rdDat(STATE_BITS- 1 downto 0) <= acap; -- @0 elsif bgot = '1' then -- Read Output rdDat(31) <= not bvld; -- @8 rdDat(7 downto 0) <= bdout; end if; end if; end if; end if; end process; target_read_accept <= '1'; target_read_data_valid <= rdVld; target_read_data <= rdDat; target_read_data_tag <= rdTag; target_read_data_ctrl <= rdCtl; end block blkRead; --------------------------------------------------------------------------- -- Interrupts blkInterrupt: block -- Delayed FIFO Status signal Zavld : std_logic := '0'; signal Zaful : std_logic := '0'; signal Zbvld : std_logic := '0'; signal Zbful : std_logic := '0'; -- Interrupt State signal EnaIn : std_logic := '0'; -- Enable signal EnaOut : std_logic := '0'; signal IrqIn : std_logic := '0'; -- Pending signal IrqOut : std_logic := '0'; begin process(clk_slow) begin if rising_edge(clk_slow) then if rst_slow = '1' then Zavld <= '0'; Zaful <= '0'; Zbvld <= '0'; Zbful <= '0'; EnaIn <= '0'; EnaOut <= '0'; IrqIn <= '0'; IrqOut <= '0'; else -- Delayed Status for Edge Detection Zavld <= avld; Zaful <= aful; Zbvld <= bvld; Zbful <= bful; -- Input IRQ: space has become available | FIFO drained if target_write_enable = '1' and target_write_be(0) = '1' and to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) = ADDR_STATUS then if target_write_data(1) = '1' then EnaIn <= '1'; elsif target_write_data(0) = '0' then EnaIn <= '0'; end if; if target_write_data(1) = '0' then IrqIn <= '0'; elsif target_write_data(0) = '1' then IrqIn <= not aful; end if; elsif aput = '1' then IrqIn <= '0'; elsif aful = '0' and Zaful = '1' then IrqIn <= EnaIn; elsif avld = '0' and Zavld = '1' then IrqIn <= EnaIn; end if; -- Output IRQ: data has become available | FIFO full if target_write_enable = '1' and target_write_be(4) = '1' and to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) = ADDR_STATUS+4 then if target_write_data(33) = '1' then EnaOut <= '1'; elsif target_write_data(32) = '0' then EnaOut <= '0'; end if; if target_write_data(33) = '0' then IrqOut <= '0'; elsif target_write_data(32) = '1' then IrqOut <= bvld; end if; elsif bvld = '1' and bgot = '1' then IrqOut <= '0'; elsif bvld = '1' and Zbvld = '0' then IrqOut <= EnaOut; elsif bful = '1' and Zbful = '0' then IrqOut <= EnaOut; end if; end if; end if; end process; user_interrupt <= IrqIn or IrqOut; end block blkInterrupt; end block blkPcie; ---------------------------------------------------------------------------- -- Input FIFO to Ring Bus blkFeed: block -- Byte FIFO -> Unframe signal glue_vld : std_logic; signal glue_dat : byte; signal glue_got : std_logic; -- Unframe -> Stream FIFO signal oful : std_logic; signal odat : byte; signal oeof : std_logic; signal oput : std_logic; signal ocommit : std_logic; signal orollback : std_logic; -- Stream -> Ring Bus signal pigot : std_logic; signal pidat : byte; signal pieof : std_logic; begin -- Raw Byte Interface: no real buffer glue: fifo_glue generic map ( D_BITS => 8 ) port map ( clk => clk_slow, rst => rst_slow, put => aput, di => adin, ful => aful, vld => glue_vld, do => glue_dat, got => glue_got ); -- Frame Extraction unframe_i: entity work.unframe generic map ( SENTINEL => SENTINEL, PAY_LEN => PRE_BYTES ) port map ( clk => clk_slow, rst => rst_slow, rx_dat => glue_dat, rx_vld => glue_vld, rx_got => glue_got, odat => odat, oeof => oeof, oful => oful, oput => oput, ocommit => ocommit, orollback => orollback ); buf: fifo_cc_got_tempput generic map ( D_BITS => 9, MIN_DEPTH => FIFO_DEPTH, ESTATE_WR_BITS => STATE_BITS ) port map ( clk => clk_slow, rst => rst_slow, put => oput, din(8) => oeof, din(7 downto 0) => odat, full => oful, commit => ocommit, rollback => orollback, estate_wr => acap, got => pigot, dout(8) => pieof, dout(7 downto 0) => pidat, valid => avld ); blkBus: block -- Syncing the stall input signal stall_s : std_logic_vector(1 downto 0) := (others => '1'); -- Outgoing Output Registers signal OutDat : std_logic_vector(7 downto 0) := (others => '0'); signal OutEof : std_logic := '0'; signal OutPut : std_logic := '0'; -- Inverted Output Clock signal clk_inv : std_logic; begin ------------------------------------------------------------------------- -- Output Inverted Clock blkClock : block signal clk_inv : std_logic; begin invert : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '1', SRTYPE => "SYNC" ) port map ( Q => clk_inv, -- 1-bit DDR output C => clk_slow, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D1 => '0', -- 1-bit data input (positive edge) D2 => '1', -- 1-bit data input (negative edge) R => rst_slow, -- 1-bit reset input S => '0' -- 1-bit set input ); OBUFDS_inst : OBUFDS generic map ( IOSTANDARD => "DEFAULT", SLEW => "FAST" ) port map ( O => BUS_OUT_CLKP, OB => BUS_OUT_CLKN, I => clk_inv ); end block blkClock; ------------------------------------------------------------------------- -- Pre-placement Output -- Syncing stall input process(clk_slow) begin if rising_edge(clk_slow) then if rst_slow = '1' then stall_s <= (others => '1'); else stall_s <= BUS_OUT_PRE_STALL & stall_s(stall_s'left downto 1); end if; end if; end process; pigot <= avld and not stall_s(0); -- Output Registers process(clk_slow) begin if rising_edge(clk_slow) then if rst_slow = '1' then OutDat <= (others => '0'); OutEof <= '0'; OutPut <= '0'; else OutDat <= pidat; OutEof <= pieof; OutPut <= pigot; end if; end if; end process; BUS_OUT_PRE_DAT <= OutEof & OutDat; BUS_OUT_PRE_PUT <= OutPut; ------------------------------------------------------------------------- -- Start of Result Chain BUS_OUT_SOL_DAT <= (others => '0'); BUS_OUT_SOL_PUT <= '0'; end block blkBus; end block blkFeed; blkDrain: block -- Source synchronous clock domain signal clk_in : std_logic; signal rst_in : std_logic; -- Incoming Bus Data Capture Registers signal InPreDat : std_logic_vector(8 downto 0) := (others => '-'); signal InPrePut : std_logic := '0'; signal InPreCap : std_logic_vector(1 downto 0); signal InSolDat : std_logic_vector(8 downto 0) := (others => '-'); signal InSolPut : std_logic := '0'; signal InSolCap : std_logic_vector(1 downto 0); -- Solver Chain Connectivity signal pivld : std_logic; signal piful : std_logic; signal pidat : byte; signal pieof : std_logic; signal piput : std_logic; signal sivld : std_logic; signal sidat : byte; signal sieof : std_logic; signal sigot : std_logic; signal sovld : std_logic; signal sodat : byte; signal soeof : std_logic; signal sogot : std_logic; -- Solution Stream -> Frames signal tx_dat : std_logic_vector(7 downto 0); signal tx_ful : std_logic; signal tx_put : std_logic; begin --------------------------------------------------------------------------- -- Reading the Bus -- Clock Reconstruction blkClock: block signal clk_in0 : std_logic; begin IBUFGDS_inst : IBUFGDS port map ( O => clk_in0, I => BUS_IN_CLKP, IB => BUS_IN_CLKN ); BUFG_inst : BUFG port map ( O => clk_in, I => clk_in0 ); rst_in <= '0'; end block blkClock; -- Bus Input Capture process(clk_in) begin if rising_edge(clk_in) then if rst_in = '1' then InPreDat <= (others => '-'); InPrePut <= '0'; InSolDat <= (others => '-'); InSolPut <= '0'; else InPreDat <= BUS_IN_PRE_DAT; InPrePut <= BUS_IN_PRE_PUT; InSolDat <= BUS_IN_SOL_DAT; InSolPut <= BUS_IN_SOL_PUT; end if; end if; end process; -- Input FIFO (ic): Pre-Placements buf_pre : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InPreCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InPrePut, din => InPreDat, full => open, estate_wr => InPreCap, clk_rd => clk_comp, rst_rd => rst_comp, got => piput, dout(8) => pieof, dout(7 downto 0) => pidat, valid => pivld ); piput <= pivld and not piful; BUS_IN_PRE_STALL <= '1' when InPreCap = (InPreCap'range => '0') else '0'; -- Input FIFO (ic): Solutions buf_sol : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InSolCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InSolPut, din => InSolDat, full => open, estate_wr => InSolCap, clk_rd => clk_comp, rst_rd => rst_comp, got => sigot, dout(8) => sieof, dout(7 downto 0) => sidat, valid => sivld ); BUS_IN_SOL_STALL <= '1' when InSolCap = (InSolCap'range => '0') else '0'; --------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_chain generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES ) port map ( clk => clk_comp, rst => rst_comp, piful => piful, pidat => pidat, pieof => pieof, piput => piput, sivld => sivld, sidat => sidat, sieof => sieof, sigot => sigot, poful => '1', podat => open, poeof => open, poput => open, sovld => sovld, sodat => sodat, soeof => soeof, sogot => sogot ); enframe_i: entity work.enframe generic map ( SENTINEL => SENTINEL ) port map ( clk => clk_comp, rst => rst_comp, ivld => sovld, idat => sodat, ieof => soeof, igot => sogot, tx_ful => tx_ful, tx_put => tx_put, tx_dat => tx_dat ); -- Output FIFO (ic): Solutions fifob : fifo_ic_got generic map ( D_BITS => 8, MIN_DEPTH => FIFO_DEPTH, FSTATE_RD_BITS => STATE_BITS ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => tx_put, din => tx_dat, full => tx_ful, clk_rd => clk_slow, rst_rd => rst_slow, got => bgot, dout => bdout, valid => bvld, fstate_rd => bavl ); end block blkDrain; end rtl;

agpl-3.0

e0bbd69eccd385ca2a3cbf7d58d548dd

viccuad/fpga-thingies

cronometer/debouncer.vhd

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY debouncer IS PORT ( rst: IN std_logic; clk: IN std_logic; x: IN std_logic; xDeb: OUT std_logic; xDebFallingEdge: OUT std_logic; xDebRisingEdge: OUT std_logic ); END debouncer; ARCHITECTURE debouncerArch of debouncer is SIGNAL xSync: std_logic; SIGNAL startTimer, timerEnd: std_logic; BEGIN synchronizer: PROCESS (rst, clk) VARIABLE aux1: std_logic; BEGIN IF (rst='0') THEN aux1 := '1'; xSync <= '1'; ELSIF (clk'EVENT AND clk='1') THEN xSync <= aux1; aux1 := x; END IF; END PROCESS synchronizer; timer: -- espera 50 ms para un reloj a 12.5 MHz PROCESS (rst, clk) CONSTANT timeOut: std_logic_vector (21 DOWNTO 0) := "1001100010010110100000"; VARIABLE count: std_logic_vector (21 DOWNTO 0); BEGIN IF (count=timeOut) THEN timerEnd <= '1'; ELSE timerEnd <= '0'; END IF; IF (rst='0') THEN count := timeOut; ELSIF (clk'EVENT AND clk='1') THEN IF (startTimer='1') THEN count := (OTHERS=>'0'); ELSIF (timerEnd='0') THEN count := count + 1; END IF; END IF; END PROCESS timer; controller: PROCESS (xSync, rst, clk) TYPE states IS (waitingPression, pressionDebouncing, waitingDepression, depressionDebouncing); VARIABLE state: states; BEGIN xDeb <= '1'; xDebFallingEdge <= '0'; xDebRisingEdge <= '0'; startTimer <= '0'; CASE state IS WHEN waitingPression => IF (xSync='0') THEN xDebFallingEdge <= '1'; startTimer <= '1'; END IF; WHEN pressionDebouncing => xDeb <= '0'; WHEN waitingDepression => xDeb <= '0'; IF (xSync='1') THEN xDebRisingEdge <= '1'; startTimer <= '1'; END IF; WHEN depressionDebouncing => NULL; END CASE; IF (rst='0') THEN state := waitingPression; ELSIF (clk'EVENT AND clk='1') THEN CASE state IS WHEN waitingPression => IF (xSync='0') THEN state := pressionDebouncing; END IF; WHEN pressionDebouncing => IF (timerEnd='1') THEN state := waitingDepression; END IF; WHEN waitingDepression => IF (xSync='1') THEN state := depressionDebouncing; END IF; WHEN depressionDebouncing => IF (timerEnd='1') THEN state := waitingPression; END IF; END CASE; END IF; END PROCESS controller; END debouncerArch;

gpl-3.0

5e3cca487ce1f6ec82745d503eb9aa13

preusser/q27

src/vhdl/top/xilinx/xupv5_queens_uart.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity xupv5_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 52; COUNT_CYCLES : boolean := false; CLK_FREQ : positive := 100000000; CLK_MUL : positive := 25; CLK_DIV : positive := 14; BAUDRATE : positive := 115200; SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte ); port ( clkx : in std_logic; rstx : in std_logic; rx : in std_logic; tx : out std_logic; leds : out std_logic_vector(0 to 7) ); end xupv5_queens_uart; library IEEE; use IEEE.numeric_std.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of xupv5_queens_uart is -- Global Control signal clk : std_logic; signal rst : std_logic; -- Solver Status signal avail : std_logic; begin ----------------------------------------------------------------------------- -- Generate Global Controls blkGlobal: block is signal clk_u : std_logic; -- Unbuffered Synthesized Clock signal rst_s : std_logic_vector(1 downto 0) := (others => '0'); begin DCM0 : DCM_BASE generic map ( CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ), CLKIN_DIVIDE_BY_2 => FALSE, PHASE_SHIFT => 0, CLKFX_MULTIPLY => CLK_MUL, CLKFX_DIVIDE => CLK_DIV, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", -- only using clkfx DLL_FREQUENCY_MODE => "HIGH", DFS_FREQUENCY_MODE => "HIGH", DUTY_CYCLE_CORRECTION => TRUE, STARTUP_WAIT => TRUE -- Delay until DCM LOCK ) port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => clk_u, CLKFX180 => open, LOCKED => open, CLKFB => '0', CLKIN => clkx, RST => '0' ); clk_buf : BUFG port map ( I => clk_u, O => clk ); -- Reset Synchronization process(clk) begin if rising_edge(clk) then rst_s <= (not rstx) & rst_s(rst_s'left downto 1); end if; end process; rst <= rst_s(0); end block blkGlobal; ---------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_uart generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES, CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)), BAUDRATE => BAUDRATE, SENTINEL => SENTINEL ) port map ( clk => clk, rst => rst, rx => rx, tx => tx, avail => avail ); ---------------------------------------------------------------------------- -- Basic Status Output leds <= std_logic_vector(to_unsigned((SOLVERS mod (2**(leds'length-1)-1))+1, leds'length-1)) & avail; end rtl;

agpl-3.0

0a51b1c82c035509d28ad574df0f87aa

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fdiv_fadd.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 3; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

7eac373ccecc914faa048086d4747c18

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_bindec.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block GfmYVDVu+TEIqolgenDas9izt6SZXSU0VONt8FpAkwrqolWZ2fyqu1Pdo+dOJ+7bHIOZ6JnqEjUF t0t4l8DRVA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block D2e2FXItpsMtjUQwtkNa8rD4XaUHEroTyJC4NG/HmrPmPV3Y0GSyHNeWtwLriV5NxUf7UpSh3KxD mn8q+FrtJ2Xrz46tywRIki2qceC8IV0jyNzkoCnwqHbN1JhmUN3yXCTqZEQsoqGKPybX8leFq48Z kQNh2C5bvkfhK3mvR4c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

755aafd6055cb72c60fdc99e097ce1a8

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_tx_osc.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_tx_osc | -- | --------------------------------------------------------------------------------------------------- -- File wf_tx_osc.vhd | -- | -- Description Generation of the clock signals needed for the FIELDRIVE transmission. | -- | -- The unit generates the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit | -- clock) and the nanoFIP internal signal tx_sched_p_buff: | -- | -- uclk : _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-| | -- FD_TXCK : _____|--------...--------|________...________|--------...--- | -- tx_sched_p_buff(3): 0 0 0 1 0 0 0 1 | -- tx_sched_p_buff(2): 0 0 1 0 0 0 1 0 | -- tx_sched_p_buff(1): 0 1 0 0 0 1 0 0 | -- tx_sched_p_buff(0): 1 0 0 0 1 0 0 0 | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 14/02/2011 | -- Version v0.04 | -- Depends on wf_reset_unit | ---------------- | -- Last changes | -- 08/2009 v0.01 PS Entity Ports added, start of architecture content | -- 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned; | -- c_TX_SCHED_BUFF_LGTH got 1 bit more | -- 12/2010 v0.03 EG code cleaned-up | -- 01/2011 v0.04 EG wf_tx_osc as different unit; use of wf_incr_counter;added tx_osc_rst_p_i --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_tx_osc --================================================================================================= entity wf_tx_osc is port ( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- Signals from the wf_engine_control tx_osc_rst_p_i : in std_logic; -- transmitter timeout -- OUTPUTS -- nanoFIP FIELDRIVE output tx_clk_o : out std_logic; -- line driver half bit clock -- Signal to the wf_tx_serializer unit tx_sched_p_buff_o : out std_logic_vector (c_TX_SCHED_BUFF_LGTH -1 downto 0)); -- buffer of pulses used for the scheduling -- of the actions of the wf_tx_serializer end entity wf_tx_osc; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_tx_osc is -- transmission periods counter signal s_period_c, s_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0); signal s_one_forth_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0); signal s_period_c_is_full, s_period_c_reinit : std_logic; -- clocks signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic; signal s_tx_sched_p_buff : std_logic_vector (c_TX_SCHED_BUFF_LGTH-1 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Periods Counter -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclk ticks for a -- transmission period s_one_forth_period <= s_period srl 2; -- 1/4 s_period s_period_c_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instantiation of a wf_incr_counter counting transmission periods. tx_periods_count: wf_incr_counter generic map(g_counter_lgth => c_PERIODS_COUNTER_LGTH) port map( uclk_i => uclk_i, counter_reinit_i => s_period_c_reinit, counter_incr_i => '1', counter_is_full_o => open, ------------------------------------------ counter_o => s_period_c); ------------------------------------------ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- counter reinitialized : if the nfip_rst_i is active or -- if the tx_osc_rst_p_i is active or -- if it fills up s_period_c_reinit <= nfip_rst_i or tx_osc_rst_p_i or s_period_c_is_full; --------------------------------------------------------------------------------------------------- -- Clocks Construction -- --------------------------------------------------------------------------------------------------- -- Concurrent signals assignments and a synchronous process that use -- the s_period_c to construct the tx_clk_o clock and the buffer of pulses tx_sched_p_buff_o. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Creation of the clock for the transmitter with period: 1/2 transmission period s_tx_clk <= '1' when ((s_period_c < s_one_forth_period) or ((s_period_c > (2*s_one_forth_period)-1) and (s_period_c < 3*s_one_forth_period))) else '0'; -- transm. period : _|-----------|___________|-- -- tx_counter : 0 1/4 1/2 3/4 1 -- s_tx_clk : _|-----|_____|-----|_____|-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Edge detector for s_tx_clk s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1); -- s_tx_clk : _|-----|_____|-----|_____ -- tx_clk_o/ s_tx_clk_d1: ___|-----|_____|-----|___ -- not s_tx_clk_d1 : ---|_____|-----|_____|--- -- s_tx_clk_p : _|-|___|-|___|-|___|-|___ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- clk_Signals_Construction: process (uclk_i) begin if rising_edge (uclk_i) then if (nfip_rst_i = '1') or (tx_osc_rst_p_i = '1') then s_tx_sched_p_buff <= (others => '0'); s_tx_clk_d1 <= '0'; else s_tx_clk_d1 <= s_tx_clk; s_tx_sched_p_buff <= s_tx_sched_p_buff (s_tx_sched_p_buff'left-1 downto 0) & s_tx_clk_p; -- buffering of the s_tx_clk_p pulses end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Output signals tx_clk_o <= s_tx_clk_d1; tx_sched_p_buff_o <= s_tx_sched_p_buff; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

f5446c81c184739860128388445b44d6

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_LMEM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

14de120d09595a397e92ed0aa2747f78

kennethlyn/fpga-image-example

hdl_nodes/adder/adder.srcs/sources_1/dyplo_user_logic_adder.vhd

-- File: dyplo_user_logic_stub.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic�s maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library dyplo_hdl_node_lib; use dyplo_hdl_node_lib.hdl_node_package.all; use dyplo_hdl_node_lib.hdl_node_user_params.all; entity dyplo_user_logic_adder is generic( INPUT_STREAMS : integer := 4; OUTPUT_STREAMS : integer := 4 ); port( -- Processor bus interface dab_clk : in std_logic; dab_rst : in std_logic; dab_addr : in std_logic_vector(15 DOWNTO 0); dab_sel : in std_logic; dab_wvalid : in std_logic; dab_rvalid : in std_logic; dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Streaming input interfaces cin_tdata : in cin_tdata_ul_type; cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tlevel : in cin_tlevel_ul_type; -- Streaming output interfaces cout_tdata : out cout_tdata_ul_type; cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0); cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0); -- Clock signals user_clocks : in std_logic_vector(3 downto 0) ); end dyplo_user_logic_adder; architecture rtl of dyplo_user_logic_adder is type signed_matrix_4x32 is array (0 to INPUT_STREAMS - 1) of signed(31 downto 0); signal value_to_add : signed_matrix_4x32; signal cout_tdata_i : signed_matrix_4x32 := (others => (others => '0')); signal cout_tvalid_i : std_logic_vector(OUTPUT_STREAMS - 1 downto 0) := (others => '0'); signal cin_tready_i : std_logic_vector(INPUT_STREAMS - 1 downto 0) := (others => '0'); begin config_reg : process (dab_clk) variable index : integer; begin if rising_edge(dab_clk) then if (dab_rst = '1') then value_to_add <= (others => (others => '0')); else index := to_integer(unsigned(dab_addr(3 downto 2))); if (dab_sel = '1') and (dab_wvalid = '1') then value_to_add(index) <= signed(dab_wdata); end if; dab_rdata <= std_logic_vector(value_to_add(index)); end if; end if; end process config_reg; adders : for i in 0 to 3 generate type sm_calc_states is (S_FETCH, S_CALC, S_SEND, S_FINISH); signal sm_calc : sm_calc_states := S_FETCH; signal tdata : signed(31 downto 0) := (others => '0'); begin calc_data : process (dab_clk) begin if rising_edge(dab_clk) then if (dab_rst = '1') then cin_tready_i(i) <= '0'; tdata <= (others => '0'); sm_calc <= S_FETCH; cout_tvalid_i(i) <= '0'; else case sm_calc is when S_FETCH => if (cin_tvalid(i) = '1') then cin_tready_i(i) <= '1'; tdata <= signed(cin_tdata(i)); sm_calc <= S_CALC; end if; when S_CALC => cin_tready_i(i) <= '0'; cout_tdata_i(i) <= tdata + value_to_add(i); cout_tvalid_i(i) <= '1'; sm_calc <= S_SEND; when S_SEND => if (cout_tready(i) = '1') then cout_tvalid_i(i) <= '0'; sm_calc <= S_FINISH; end if; when S_FINISH => sm_calc <= S_FETCH; end case; end if; end if; end process calc_data; end generate adders; cout_tvalid <= cout_tvalid_i; cin_tready <= cin_tready_i; cout_tdata(0) <= std_logic_vector(cout_tdata_i(0)); cout_tdata(1) <= std_logic_vector(cout_tdata_i(1)); cout_tdata(2) <= std_logic_vector(cout_tdata_i(2)); cout_tdata(3) <= std_logic_vector(cout_tdata_i(3)); end rtl;

gpl-2.0

9686c6a74fcedd114484c1dc2b6506cf

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_prim_width.vhd

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mit

95f62ef4a2158c73890aec60bd92daa8

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_4_CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 2; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

b1e1ad1e8b6f4cd7100178c94a0b473b

wltr/cern-fgclite

critical_fpga/src/rtl/cf/nf/nf_tx_registers.vhd

------------------------------------------------------------------------------- --! @file nf_tx_registers.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-23 --! @brief NanoFIP transmitter registers. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.nf_pkg.all; --! @brief Entity declaration of nf_tx_registers --! @details --! FGClite is sending 60 bytes of status registers as part of it's response --! to the gateway. entity nf_tx_registers is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name NanoFIP read interface --! @{ --! Read enable rd_en_i : in std_ulogic; --! Address addr_i : in std_ulogic_vector(5 downto 0); --! Data data_o : out std_ulogic_vector(7 downto 0); --! Data enable data_en_o : out std_ulogic; --! @} --! @name Registers --! @{ --! FGClite status status_i : in nf_status_t); --! @} end entity nf_tx_registers; --! RTL implementation of nf_tx_registers architecture rtl of nf_tx_registers is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type reg_t is array (0 to 2**addr_i'length - 1) of std_ulogic_vector(data_o'range); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; signal data : std_ulogic_vector(data_o'range); signal data_en : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- data_o <= data; data_en_o <= data_en; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= (others => (others => '0')); data <= (others => '0'); data_en <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else --Defaults data_en <= '0'; if rd_en_i = '1' then data <= reg(to_integer(unsigned(addr_i))); data_en <= '1'; end if; if status_i.adc_acc_vs_0_en = '1' then reg(0) <= status_i.adc_acc_vs_0(7 downto 0); reg(1) <= status_i.adc_acc_vs_0(15 downto 8); reg(2) <= status_i.adc_acc_vs_0(23 downto 16); reg(3) <= status_i.adc_acc_vs_0(31 downto 24); end if; if status_i.adc_acc_vs_1_en = '1' then reg(4) <= status_i.adc_acc_vs_1(7 downto 0); reg(5) <= status_i.adc_acc_vs_1(15 downto 8); reg(6) <= status_i.adc_acc_vs_1(23 downto 16); reg(7) <= status_i.adc_acc_vs_1(31 downto 24); end if; if status_i.adc_acc_ia_0_en = '1' then reg(8) <= status_i.adc_acc_ia_0(7 downto 0); reg(9) <= status_i.adc_acc_ia_0(15 downto 8); reg(10) <= status_i.adc_acc_ia_0(23 downto 16); reg(11) <= status_i.adc_acc_ia_0(31 downto 24); end if; if status_i.adc_acc_ia_1_en = '1' then reg(12) <= status_i.adc_acc_ia_1(7 downto 0); reg(13) <= status_i.adc_acc_ia_1(15 downto 8); reg(14) <= status_i.adc_acc_ia_1(23 downto 16); reg(15) <= status_i.adc_acc_ia_1(31 downto 24); end if; if status_i.adc_acc_ib_0_en = '1' then reg(16) <= status_i.adc_acc_ib_0(7 downto 0); reg(17) <= status_i.adc_acc_ib_0(15 downto 8); reg(18) <= status_i.adc_acc_ib_0(23 downto 16); reg(19) <= status_i.adc_acc_ib_0(31 downto 24); end if; if status_i.adc_acc_ib_1_en = '1' then reg(20) <= status_i.adc_acc_ib_1(7 downto 0); reg(21) <= status_i.adc_acc_ib_1(15 downto 8); reg(22) <= status_i.adc_acc_ib_1(23 downto 16); reg(23) <= status_i.adc_acc_ib_1(31 downto 24); end if; if status_i.dim_a_trig_lat_en = '1' then reg(24) <= status_i.dim_a_trig_lat(7 downto 0); reg(25) <= status_i.dim_a_trig_lat(15 downto 8); end if; if status_i.dim_a_trig_unl_en = '1' then reg(26) <= status_i.dim_a_trig_unl(7 downto 0); reg(27) <= status_i.dim_a_trig_unl(15 downto 8); end if; if status_i.dim_a1_ana_0_en = '1' then reg(28) <= status_i.dim_a1_ana_0(7 downto 0); reg(29) <= status_i.dim_a1_ana_0(15 downto 8); end if; if status_i.dim_a1_ana_1_en = '1' then reg(30) <= status_i.dim_a1_ana_1(7 downto 0); reg(31) <= status_i.dim_a1_ana_1(15 downto 8); end if; if status_i.dim_a1_ana_2_en = '1' then reg(32) <= status_i.dim_a1_ana_2(7 downto 0); reg(33) <= status_i.dim_a1_ana_2(15 downto 8); end if; if status_i.dim_a1_ana_3_en = '1' then reg(34) <= status_i.dim_a1_ana_3(7 downto 0); reg(35) <= status_i.dim_a1_ana_3(15 downto 8); end if; if status_i.cycle_period_en = '1' then reg(36) <= status_i.cycle_period(7 downto 0); reg(37) <= status_i.cycle_period(15 downto 8); reg(38) <= status_i.cycle_period(23 downto 16); reg(39) <= status_i.cycle_period(31 downto 24); end if; if status_i.version_cfnf_en = '1' then reg(40) <= status_i.version_cfnf(7 downto 0); end if; if status_i.version_xfpf_en = '1' then reg(41) <= status_i.version_xfpf(7 downto 0); end if; if status_i.adc_log_idx_en = '1' then reg(42) <= status_i.adc_log_idx(7 downto 0); reg(43) <= status_i.adc_log_idx(15 downto 8); end if; if status_i.dim_log_idx_en = '1' then reg(44) <= status_i.dim_log_idx(7 downto 0); reg(45) <= status_i.dim_log_idx(15 downto 8); end if; if status_i.vs_dig_in_en = '1' then reg(46) <= status_i.vs_dig_in(7 downto 0); reg(47) <= status_i.vs_dig_in(15 downto 8); end if; if status_i.vs_dig_out_en = '1' then reg(48) <= status_i.vs_dig_out; end if; if status_i.seu_count_en = '1' then reg(49) <= status_i.seu_count; end if; if status_i.fgc_status_en = '1' then reg(50) <= status_i.fgc_status(7 downto 0); reg(51) <= status_i.fgc_status(15 downto 8); end if; if status_i.backplane_en = '1' then reg(52) <= status_i.backplane; end if; if status_i.serial_data_en = '1' then reg(53 + to_integer(unsigned(status_i.serial_num))) <= status_i.serial_data; end if; end if; end if; end process regs; end architecture rtl;

mit

36bf44d5698aad2a6ccb6b1b404cb241

malkadi/FGPU

RTL/CU_scheduler.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity CU_scheduler is --- {{{ port( clk, nrst : in std_logic; -- output status signals wf_active : out std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); -- for Work-Group Dispatcher sch_rqst : in std_logic; -- high to begin scheduling a new WG sch_ack : out std_logic := '0'; -- high while scheduling a new WG sch_rqst_n_wfs_m1 : in unsigned(N_WF_CU_W-1 downto 0); -- # WFs within a WG wg_info : in unsigned(DATA_W-1 downto 0); -- for instruction fetching cram_rdAddr : out unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdAddr_conf : in unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdData : in std_logic_vector(DATA_W-1 downto 0); cram_rqst : out std_logic := '0'; start_addr : in unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); -- branch handling wf_is_branching : in std_logic_vector(N_WF_CU-1 downto 0); -- level 18. alu_branch : in std_logic_vector(CV_SIZE-1 downto 0); -- level 18. alu_en : in std_logic_vector(CV_SIZE-1 downto 0); -- level 18. -- for RunTime Memory rtm_wrAddr_cv : out unsigned(N_WF_CU_W+2-1 downto 0) := (others => '0'); rtm_wrData_cv : out unsigned(DATA_W-1 downto 0) := (others => '0'); rtm_we_cv : out std_logic := '0'; gmem_finish : in std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); -- with the Compute Vector instr : out std_logic_vector(DATA_W-1 downto 0) := (others => '0'); -- level -1. wf_indx_in_wg : out natural range 0 to N_WF_CU-1; -- level -1. wf_indx_in_CU : out natural range 0 to N_WF_CU-1; -- level -1. alu_en_divStack : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 2. phase : out unsigned(PHASE_W-1 downto 0) := (others=>'0') -- level -1. ); attribute max_fanout of wf_indx_in_CU : signal is 10; end CU_scheduler; -- }}} architecture Behavioral of CU_scheduler is -- signal definitions -----------------------------------------------------------------------------------{{{ -- internal signals assignments --------------------------------------------------------------------------{{{ signal wf_active_i : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal sch_ack_i : std_logic := '0'; signal cram_rdAddr_i : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal instr_i : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal phase_i : unsigned(PHASE_W-1 downto 0) := (others=>'0'); signal wf_indx_in_CU_i : natural range 0 to N_WF_CU-1 := 0; attribute max_fanout of phase_i : signal is 10; ---------------------------------------------------------------------------------------------------------}}} -- types & functions {{{ type wf_ctrl_state is ( idle, check_rdy, rdy, wait_for_selecting_PC, wait_pc_rdy, wait_gmem_finish, jumping, branching, read_PC_stack, scratchpad_load); type wf_ctrl_state_vec is array (N_WF_CU-1 downto 0) of wf_ctrl_state; signal st_wf, st_wf_n : wf_ctrl_state_vec := (others => idle); type CV_state_type is (idle, start_exec, select_PC, check_wf_rdy, read_inst, dly1, dly2, dly3 , select_instr); signal st_CV, st_CV_n : CV_state_type := idle; signal new_instr_found_n : std_logic := '0'; signal new_instr_found : std_logic := '0'; -- }}} -- workgroup indices {{{ signal wg_next_id, wg_next_id_n : unsigned(N_WF_CU_W-1 downto 0) := (others=>'0'); signal wg_offset_d0, wg_offset_d0_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal wg_offset_d1, wg_offset_d1_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal wg_offset_d2, wg_offset_d2_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); type dx_offset_type is (write_d0, write_d1, write_d2); signal dx_offset_state : dx_offset_type := write_d0; signal dx_offset_state_n : dx_offset_type := write_d0; -- }}} -- global signals {{{ constant WF_WAIT_LEN : integer := max(FLOAT_IMPLEMENT*MAX_FPU_DELAY+11, 16); -- 16 is the normal delay for instruction that use the ALU -- 22 for float delay of 11 (fmul) -- 39 for float delay of 28 (fdiv & fsqrt) type wf_wait_vec_type is array (natural range <>) of std_logic_vector(WF_WAIT_LEN-1 downto 0); signal wf_wait_vec : wf_wait_vec_type(N_WF_CU-1 downto 0) := (others=>(others=>'0')); signal wf_wait_vec_alu_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_wait_vec_fpu_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal clear_wf_wait_vec : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_no_wait, wf_no_wait_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal clear_wf_wait_vec_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal sch_rqst_n_wfs_ltchd : integer range 0 to N_WF_CU := 0; signal sch_rqst_n_wfs_ltchd_n : integer range 0 to N_WF_CU := 0; type interface_fsm_stata_type is (free, reserve, write_wg_d0, write_wg_d1, write_wg_d2); signal st_WGD_intr, st_WGD_intr_n : interface_fsm_stata_type := free; signal wf_on_gmem, wf_reads_gmem : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_branches : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_scratchpad_ld : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_jump : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_fpu : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal phase_n : unsigned(PHASE_W-1 downto 0) := (others=>'0'); signal rd_priority, rd_priority_n : std_logic := '0'; signal wf_sel_indx, wf_sel_indx_n : integer range 0 to N_WF_CU-1 := 0; signal pc_indx, pc_indx_n : integer range 0 to N_WF_CU-1 := 0; signal instr_n, instr_buf_out : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal PCs, PCs_n, PC_plus_branch_n : CRAM_ADDR_ARRAY(N_WF_CU-1 downto 0) := (others =>(others=>'0')); signal PC_plus_1_n, PC_plus_1 : CRAM_ADDR_ARRAY(N_WF_CU-1 downto 0) := (others =>(others=>'0')); signal wf_finish, wf_finish_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_alloc_indx : unsigned(N_WF_CU_W-1 downto 0) := (others => '0'); signal wf_alloc_indx_n : unsigned(N_WF_CU_W-1 downto 0) := (others => '0'); signal pc_rdy : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_rdy, wf_rdy_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_gmem_read_rdy : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_gmem_read_rdy_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_gmem_write_rdy : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_gmem_write_rdy_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_branch_rdy_n, wf_branch_rdy : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal branch_in_executoin : std_logic := '0'; signal branch_in_executoin_vec : std_logic_vector(19 downto 0) := (others=>'0'); -- this signals prevents scheduling two branches successively signal branch_in_executoin_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal advance_pc, advance_pc_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal execute_n, execute : std_logic := '0'; signal pc_updated, pc_updated_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_retired : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_activate, wf_activate_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal sch_ack_n : std_logic := '0'; signal wf_active_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); -- }}} -- coordinates {{{ type wf_indx_type is array (0 to N_WF_CU-1) of natural range 0 to N_WF_CU-1; signal wf_indx, wf_indx_n : wf_indx_type := (others => 0); signal allocated_wfs, allocated_wfs_n : natural range 0 to N_WF_CU := 0; -- }}} -- divergence fifos {{{ constant N_RECORDS_WF_W : integer := 3; signal branch_distance : branch_distance_vec(0 to N_WF_CU-1) := (others=>(others=>'0')); signal divStacks : alu_en_vec_type(0 to 2**(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W)-1) := (others=>(others=>'0')); signal alu_branch_vec : alu_en_vec_type(7 downto 0) := (others=>(others=>'0')); signal alu_en_vec : alu_en_vec_type(7 downto 0) := (others=>(others=>'0')); signal alu_branch_latch : alu_en_vec_type(7 downto 0) := (others=>(others=>'0')); signal alu_en_latch : alu_en_vec_type(7 downto 0) := (others=>(others=>'0')); signal divStack_addrb : unsigned(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal divStack_addra : unsigned(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal divStack_addra_p0 : unsigned(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal divStack_addra_p0_n : unsigned(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal divStack_dia, divStack_dia_n : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal divStack_wea, divStack_wea_n : std_logic := '0'; signal divStack_dob, divStack_dob_n : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal phase_branch : unsigned(PHASE_W-1 downto 0) := (others=>'0'); signal n_branching_wfs : integer range 0 to WF_SIZE := 0; signal n_branching_wfs_d0 : integer range 0 to WF_SIZE := 0; signal n_not_branching_wfs : integer range 0 to WF_SIZE := 0; signal n_not_branching_wfs_d0 : integer range 0 to WF_SIZE := 0; signal branching_wf_index : integer range 0 to N_WF_CU-1 := 0; signal evaluate_divergance : std_logic := '0'; signal evaluate_divergance_d0 : std_logic := '0'; signal true_path, false_path : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal true_path_n, false_path_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); type active_record_indx_type is array (natural range <>) of unsigned(N_RECORDS_WF_W-1 downto 0); signal wf_active_record : active_record_indx_type(N_WF_CU-1 downto 0) := (others=>(others=>'0')); signal wf_active_record_inc_n : std_logic := '0'; signal wf_active_record_dec_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal write_two_records : std_logic := '0'; signal write_two_records_n : std_logic := '0'; type st_branch_type is (idle, write_true_path_in_divStack, dly_to_false, write_false_path_in_divStack, dly_to_true); signal st_branch, st_branch_n : st_branch_type := idle; signal go_true_and_false : std_logic := '0'; signal go_true_and_false_n : std_logic := '0'; signal wf_indx_in_CU_d0 : natural range 0 to N_WF_CU-1 := 0; signal active_record_indx : unsigned(N_RECORDS_WF_W-1 downto 0) := (others=>'0'); signal phase_d0 : unsigned(PHASE_W-1 downto 0) := (others=>'0'); -- PC_stack constant N_RECORDS_PC_STACK_W : integer := 4; type PC_stack_addr_type is array(natural range <>) of unsigned(N_RECORDS_PC_STACK_W-1 downto 0); signal PC_stack_addr : PC_stack_addr_type(N_WF_CU-1 downto 0) := (others=>(others=>'0')); signal PC_stack_pop : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_pop_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_pop_ack : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_pop_ack_p0 : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_pop_ack_p1 : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_push_branch : std_logic := '0'; signal PC_stack_push_branch_n : std_logic := '0'; signal PC_stack_push_not_branch : std_logic := '0'; signal PC_stack_push_branch_ack : std_logic := '0'; signal PC_stack_push_not_branch_ack : std_logic := '0'; signal PC_stack_push_not_branch_n : std_logic := '0'; signal PC_stack_push, PC_stack_push_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_push_ack : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack : CRAM_ADDR_ARRAY(0 to 2**(N_RECORDS_PC_STACK_W+N_WF_CU_W)-1) := (others =>(others=>'0')); signal PC_stack_jump_entry : std_logic_vector(0 to 2**(N_RECORDS_PC_STACK_W+N_WF_CU_W)-1) := (others=>'0'); -- signal PC_stack_dummy_entry : std_logic_vector(0 to 2**(N_RECORDS_PC_STACK_W+N_WF_CU_W)-1) := (others=>'0'); -- signal PC_stack_dummy_entry_wrData : std_logic := '0'; -- signal PC_stack_dummy_entry_rdData_n : std_logic := '0'; -- signal PC_stack_dummy_entry_rdData : std_logic := '0'; signal PC_stack_jump_entry_wrData : std_logic := '0'; signal PC_stack_wrAddr : unsigned(N_RECORDS_PC_STACK_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal PC_stack_rdAddr : unsigned(N_RECORDS_PC_STACK_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal PC_stack_wrData : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal PC_stack_rdData : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal PC_stack_rdData_n : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal PC_stack_jump_entry_rdData_n : std_logic := '0'; signal PC_stack_jump_entry_rdData : std_logic := '0'; signal PC_stack_we : std_logic := '0'; -- }}} ---------------------------------------------------------------------------------------------------------}}} begin -- internal signals assignments -------------------------------------------------------------------------------------------{{{ ---------------------------------------------------------------------------------------------------------{{{ wf_active <= wf_active_i; sch_ack <= sch_ack_i; cram_rdAddr <= cram_rdAddr_i; instr <= instr_i; phase <= phase_i; wf_indx_in_CU <= wf_indx_in_CU_i; assert(2**N_RECORDS_WF_W >= WF_SIZE_W) report "increase the number of records per WF" severity failure; ---------------------------------------------------------------------------------------------------------}}} ---------------------------------------------------------------------------------------------------------}}} -- instruction buffer -----------------------------------------------------------------------------------{{{ CU_instruction_dispatcher_inst: entity CU_instruction_dispatcher port map( clk => clk, nrst => nrst, cram_rdAddr => cram_rdAddr_i, cram_rdData => cram_rdData, cram_rqst => cram_rqst, cram_rdAddr_conf => cram_rdAddr_conf, PC_indx => pc_indx, instr => instr_buf_out, PCs => PCs, pc_rdy => pc_rdy, instr_gmem_op => wf_on_gmem, instr_scratchpad_ld => wf_scratchpad_ld, instr_gmem_read => wf_reads_gmem, instr_branch => wf_branches, instr_jump => instr_jump, instr_fpu => instr_fpu, wf_active => wf_active_i, pc_updated => pc_updated, branch_distance => branch_distance, wf_retired => wf_retired ); ---------------------------------------------------------------------------------------------------------}}} -- WG offset capture ----------------------------------------------------------------------------- {{{ -- trans process ----------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then wg_offset_d0 <= wg_offset_d0_n; wg_offset_d1 <= wg_offset_d1_n; wg_offset_d2 <= wg_offset_d2_n; if nrst = '0' then dx_offset_state <= write_d0; else dx_offset_state <= dx_offset_state_n; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- comb process -----------------------------------------------------------------------------------------{{{ process(dx_offset_state, wg_offset_d0, wg_offset_d1, wg_offset_d2, wg_info, sch_rqst) -- rtm_wrData_wg) begin -- when a sch_rqst for allocating a wg from the WGD; the WGD sends in the first 3 cycles the offsets of the -- corresponding wg. These will be latched here dx_offset_state_n <= dx_offset_state; wg_offset_d0_n <= wg_offset_d0; wg_offset_d1_n <= wg_offset_d1; wg_offset_d2_n <= wg_offset_d2; case dx_offset_state is when write_d0 => if sch_rqst = '1' then -- wg_offset_d0_n <= rtm_wrData_wg(DATA_W-1 downto 0); wg_offset_d0_n <= wg_info; dx_offset_state_n <= write_d1; end if; when write_d1 => -- wg_offset_d1_n <= rtm_wrData_wg(DATA_W-1 downto 0); wg_offset_d1_n <= wg_info; dx_offset_state_n <= write_d2; when write_d2 => -- wg_offset_d2_n <= rtm_wrData_wg(DATA_W-1 downto 0); wg_offset_d2_n <= wg_info; dx_offset_state_n <= write_d0; end case; end process; ---------------------------------------------------------------------------------------------------------}}} ------------------------------------------------------------------------------------------------------}}} -- divergence fifos -------------------------------------------------------------------------------------{{{ -- divStack -------------------------------------------------------------------------------------------{{{ -- A side: WF Scheduler -- B side: CV process(clk) begin if rising_edge(clk) then divStack_dob_n <= divStacks(to_integer(divStack_addrb)); -- @ 1. divStack_dob <= divStack_dob_n; -- @ 2. if divStack_wea = '1' then divStacks(to_integer(divStack_addra)) <= divStack_dia; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- divStack CV side --------------------------------------------------------------------------------------{{{ alu_en_divStack <= divStack_dob; -- level 2. divStack_addrb(PHASE_W-1 downto 0) <= phase_d0; -- level 0. divStack_addrb(PHASE_W+N_RECORDS_WF_W-1 downto PHASE_W) <= active_record_indx; -- level 0. divStack_addrb(PHASE_W+N_WF_CU_W+N_RECORDS_WF_W-1 downto PHASE_W+N_RECORDS_WF_W) <= to_unsigned(wf_indx_in_CU_d0, N_WF_CU_W); -- level 0. process(clk) begin if rising_edge(clk) then wf_indx_in_CU_d0 <= wf_indx_in_CU_i; -- @ 0 -- if phase_i = (phase_i'reverse_range => '0') then if execute = '1' then active_record_indx <= wf_active_record(wf_indx_in_CU_i); -- @ 0 -- the if check is necessary to avoid the case where the wf_adtive_record decrements while executing end if; phase_d0 <= phase_i; -- @ 0 end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- divStack WF Scheduler side ----------------------------------------------------------------------------{{{ -- divStack trnas process --------------------------------------------------------------------------------{{{ process(clk) variable n_not_branching, n_branching : integer range 0 to WF_SIZE := 0; begin if rising_edge(clk) then n_branching := 0; n_not_branching := 0; if wf_is_branching /= (wf_is_branching'reverse_range => '0') then -- level 18.->24. for i in 0 to CV_SIZE-1 loop if alu_en(i) = '1' then -- level 18.->24. if alu_branch(i) = '1' then -- level 18.->24. n_branching := n_branching + 1; else n_not_branching := n_not_branching + 1; end if; end if; end loop; end if; if phase_branch = (phase_branch'reverse_range => '0') then -- true in levels 18. & 26. n_branching_wfs <= n_branching; n_not_branching_wfs <= n_not_branching; else n_branching_wfs <= n_branching_wfs + n_branching; -- @ 26 is ready n_not_branching_wfs <= n_not_branching_wfs + n_not_branching; -- @ 26 is ready end if; evaluate_divergance <= '0'; if phase_branch = (phase_branch'reverse_range => '1') then -- level 25. evaluate_divergance <= '1'; -- @ 26. for i in 0 to N_WF_CU-1 loop if wf_is_branching(i) = '1' then -- level 25. (last clock cycle where wf_is_branching is set) branching_wf_index <= i; -- @ 26 end if; end loop; end if; n_branching_wfs_d0 <= n_branching_wfs; -- @ 27. n_not_branching_wfs_d0 <= n_not_branching_wfs; -- @ 27. evaluate_divergance_d0 <= evaluate_divergance; -- @ 27. alu_branch_vec(alu_branch_vec'high-1 downto 0) <= alu_branch_vec(alu_branch_vec'high downto 1); -- @ 20.->26. alu_branch_vec(alu_branch_vec'high) <= alu_branch; -- @ 19. alu_en_vec(alu_en_vec'high-1 downto 0) <= alu_en_vec(alu_en_vec'high downto 1); -- @ 20.->26. alu_en_vec(alu_en_vec'high) <= alu_en; -- @ 19. if evaluate_divergance = '1' then -- level 26. for i in 0 to PHASE_LEN-1 loop alu_branch_latch(i) <= alu_branch_vec(i); -- @ 27. alu_en_latch(i) <= alu_en_vec(i); -- @ 27. end loop; end if; if nrst = '0' then phase_branch <= (others=>'0'); branch_in_executoin <= '0'; else branch_in_executoin_vec(branch_in_executoin_vec'high) <= '0'; if branch_in_executoin_n /= (branch_in_executoin_n'reverse_range=>'0') then branch_in_executoin <= '1'; branch_in_executoin_vec(branch_in_executoin_vec'high) <= '1'; end if; branch_in_executoin_vec(branch_in_executoin_vec'high-1 downto 0) <= branch_in_executoin_vec(branch_in_executoin_vec'high downto 1); if branch_in_executoin_vec(0) = '1' then -- level 26. branch_in_executoin <= '0'; -- @ 27. end if; if wf_is_branching /= (wf_is_branching'reverse_range => '0') then -- level 18.->25. phase_branch <= phase_branch + 1; -- @ 25. it will be all ones end if; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- divStack trans process --------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then go_true_and_false <= go_true_and_false_n; divStack_wea <= divStack_wea_n; divStack_addra_p0 <= divStack_addra_p0_n; divStack_addra <= divStack_addra_p0; divStack_dia <= divStack_dia_n; false_path <= false_path_n; true_path <= true_path_n; PC_stack_push_branch <= PC_stack_push_branch_n; PC_stack_push_not_branch <= PC_stack_push_not_branch_n; if nrst = '0' then st_branch <= idle; wf_active_record <= (others=>(others=>'0')); write_two_records <= '0'; else st_branch <= st_branch_n; write_two_records <= write_two_records_n; if wf_active_record_inc_n = '1' then -- incrment commands come form the st_branch state machine when filling new requests wf_active_record(branching_wf_index) <= wf_active_record(branching_wf_index) + 1; end if; for i in 0 to N_WF_CU-1 loop if wf_active_record_dec_n(i) = '1' then -- decrment commands come from the st_wf state machines on RET instructions wf_active_record(i) <= wf_active_record(i) - 1; end if; end loop; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- divStack comb -----------------------------------------------------------------------------------------{{{ state_branch: process(st_branch, evaluate_divergance_d0, n_branching_wfs_d0, n_not_branching_wfs_d0, go_true_and_false, divStack_addra_p0, branching_wf_index, wf_active_record, alu_branch_latch, alu_en_latch, PC_stack_push_branch, PC_stack_push_not_branch, PC_stack_push_branch_ack, n_branching_wfs, PC_stack_push_not_branch_ack, write_two_records, evaluate_divergance, n_not_branching_wfs) begin -- {{{ st_branch_n <= st_branch; go_true_and_false_n <= go_true_and_false; divStack_wea_n <= '0'; divStack_addra_p0_n(PHASE_W-1 downto 0) <= (others=>'0'); divStack_addra_p0_n(PHASE_W+N_RECORDS_WF_W-1 downto PHASE_W) <= wf_active_record(branching_wf_index); divStack_addra_p0_n(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W-1 downto PHASE_W+N_RECORDS_WF_W) <= to_unsigned(branching_wf_index, N_WF_CU_W); divStack_dia_n <= alu_branch_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0))) or not alu_en_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0))); true_path_n <= (others=>'0'); false_path_n <= (others=>'0'); PC_stack_push_branch_n <= PC_stack_push_branch; PC_stack_push_not_branch_n <= PC_stack_push_not_branch; write_two_records_n <= write_two_records; if PC_stack_push_branch_ack = '1' and write_two_records = '0' then PC_stack_push_branch_n <= '0'; end if; if PC_stack_push_not_branch_ack = '1' and write_two_records = '0' then PC_stack_push_not_branch_n <= '0'; end if; if PC_stack_push_branch_ack = '1' or PC_stack_push_not_branch_ack = '1' then write_two_records_n <= '0'; end if; wf_active_record_inc_n <= '0'; if evaluate_divergance = '1' and -- level 26. wf_active_record(branching_wf_index) = (0 to N_RECORDS_WF_W-1 => '0') and -- CHANGE (n_not_branching_wfs /= 0 and n_branching_wfs /= 0) then wf_active_record_inc_n <= '1'; -- increment the reocord if the current one is the first (all entries are zero) & a branch has been evaluated write_two_records_n <= '1'; end if; -- }}} case st_branch is when idle => -- {{{ go_true_and_false_n <= '0'; if evaluate_divergance_d0 = '1' then if n_branching_wfs_d0 /= 0 then if n_not_branching_wfs_d0 /= 0 then go_true_and_false_n <= '1'; if n_branching_wfs_d0 < n_not_branching_wfs_d0 then st_branch_n <= write_false_path_in_divStack; else st_branch_n <= write_true_path_in_divStack; end if; else true_path_n(branching_wf_index) <= '1'; end if; else false_path_n(branching_wf_index) <= '1'; end if; end if; -- }}} when write_true_path_in_divStack => -- {{{ divStack_wea_n <= '1'; divStack_addra_p0_n(PHASE_W-1 downto 0) <= divStack_addra_p0(PHASE_W-1 downto 0) + 1; divStack_dia_n <= not (alu_branch_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0))) and alu_en_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0)))); if divStack_addra_p0(PHASE_W-1 downto 0) = (0 to PHASE_W-1 => '1') then if go_true_and_false = '1' then wf_active_record_inc_n <= '1'; -- increments the record if another one has to be written st_branch_n <= dly_to_false; go_true_and_false_n <= '0'; PC_stack_push_branch_n <= '1'; else st_branch_n <= idle; true_path_n(branching_wf_index) <= '1'; end if; end if; -- }}} when dly_to_false => -- {{{ divStack_wea_n <= '0'; st_branch_n <= write_false_path_in_divStack; -- }}} when write_false_path_in_divStack => -- {{{ divStack_wea_n <= '1'; divStack_addra_p0_n(PHASE_W-1 downto 0) <= divStack_addra_p0(PHASE_W-1 downto 0) + 1; divStack_dia_n <= alu_branch_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0))) or not alu_en_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0))); -- control alu_en_latch if divStack_addra_p0(PHASE_W-1 downto 0) = (0 to PHASE_W-1 => '1') then if go_true_and_false = '1' then wf_active_record_inc_n <= '1'; -- increments the record if another one has to be written st_branch_n <= dly_to_true; go_true_and_false_n <= '0'; PC_stack_push_not_branch_n <= '1'; else st_branch_n <= idle; false_path_n(branching_wf_index) <= '1'; end if; end if; -- }}} when dly_to_true => -- {{{ st_branch_n <= write_true_path_in_divStack; divStack_wea_n <= '0'; -- }}} end case; end process; ---------------------------------------------------------------------------------------------------------}}} ---------------------------------------------------------------------------------------------------------}}} -- PC STACK --------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then -- read PC Stack -- stage 0 PC_stack_pop_ack_p1 <= (others=>'0'); for i in 0 to N_WF_CU-1 loop if PC_stack_pop(i) = '1' and PC_stack_pop_ack_p0(i) = '0' and PC_stack_pop_ack_p1(i) = '0' then -- pop commands are issued from the st_wf state machines on RET instructions PC_stack_rdAddr(N_RECORDS_PC_stack_W-1 downto 0) <= PC_stack_addr(i) - 1; PC_stack_addr(i) <= PC_stack_addr(i) - 1; PC_stack_rdAddr(N_RECORDS_PC_stack_W+N_WF_CU_W-1 downto N_RECORDS_PC_stack_W) <= to_unsigned(i, N_WF_CU_W); PC_stack_pop_ack_p1(i) <= '1'; exit; end if; end loop; -- stage 1 PC_stack_rdData_n <= PC_stack(to_integer(PC_stack_rdAddr)); PC_stack_jump_entry_rdData_n <= PC_stack_jump_entry(to_integer(PC_stack_rdAddr)); -- PC_stack_dummy_entry_rdData_n <= PC_stack_dummy_entry(to_integer(PC_stack_rdAddr)); PC_stack_pop_ack_p0 <= PC_stack_pop_ack_p1; -- stage 2 PC_stack_rdData <= PC_stack_rdData_n; PC_stack_jump_entry_rdData <= PC_stack_jump_entry_rdData_n; -- PC_stack_dummy_entry_rdData <= PC_stack_dummy_entry_rdData_n; PC_stack_pop_ack <= PC_stack_pop_ack_p0; -- select push command PC_stack_push_ack <= (others=>'0'); PC_stack_push_branch_ack <= '0'; PC_stack_push_not_branch_ack <= '0'; if PC_stack_push_branch = '1' and PC_stack_push_branch_ack = '0' then PC_stack_push_branch_ack <= '1'; elsif PC_stack_push_not_branch = '1' and PC_stack_push_not_branch_ack = '0' then PC_stack_push_not_branch_ack <= '1'; else for i in 0 to N_WF_CU-1 loop if PC_stack_push(i) = '1' and PC_stack_push_ack(i) = '0' then PC_stack_push_ack(i) <= '1'; exit; end if; end loop; end if; -- write PC Stack -- push commands come from the st_branch state machine when two records have to be written into divStacks PC_stack_we <= '0'; if PC_stack_push_branch_ack = '1' then PC_stack_we <= '1'; PC_stack_addr(branching_wf_index) <= PC_stack_addr(branching_wf_index) + 1; PC_stack_wrAddr(N_RECORDS_PC_STACK_W-1 downto 0) <= PC_stack_addr(branching_wf_index); PC_stack_wrAddr(N_RECORDS_PC_STACK_W+N_WF_CU_W-1 downto N_RECORDS_PC_STACK_W) <= to_unsigned(branching_wf_index, N_WF_CU_W); PC_stack_wrData <= PC_plus_branch_n(branching_wf_index); PC_stack_jump_entry_wrData <= '0'; -- PC_stack_dummy_entry_wrData <= write_two_records; elsif PC_stack_push_not_branch_ack = '1' then PC_stack_we <= '1'; PC_stack_addr(branching_wf_index) <= PC_stack_addr(branching_wf_index) + 1; PC_stack_wrAddr(N_RECORDS_PC_STACK_W-1 downto 0) <= PC_stack_addr(branching_wf_index); PC_stack_wrAddr(N_RECORDS_PC_STACK_W+N_WF_CU_W-1 downto N_RECORDS_PC_STACK_W) <= to_unsigned(branching_wf_index, N_WF_CU_W); PC_stack_wrData <= PCs(branching_wf_index); PC_stack_jump_entry_wrData <= '0'; -- PC_stack_dummy_entry_wrData <= write_two_records; else for i in 0 to N_WF_CU-1 loop if PC_stack_push_ack(i) = '1' then PC_stack_we <= '1'; PC_stack_addr(i) <= PC_stack_addr(i) + 1; PC_stack_wrAddr(N_RECORDS_PC_STACK_W-1 downto 0) <= PC_stack_addr(i); PC_stack_wrAddr(N_RECORDS_PC_STACK_W+N_WF_CU_W-1 downto N_RECORDS_PC_STACK_W) <= to_unsigned(i, N_WF_CU_W); PC_stack_wrData <= PC_plus_1(i); PC_stack_jump_entry_wrData <= '1'; -- PC_stack_dummy_entry_wrData <= '0'; exit; end if; end loop; end if; if PC_stack_we = '1' then PC_stack(to_integer(PC_stack_wrAddr)) <= PC_stack_wrData; PC_stack_jump_entry(to_integer(PC_stack_wrAddr)) <= PC_stack_jump_entry_wrData; -- PC_stack_dummy_entry(to_integer(PC_stack_wrAddr)) <= PC_stack_dummy_entry_wrData; end if; if nrst = '0' then PC_stack_addr <= (others=>(others=>'0')); end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} ---------------------------------------------------------------------------------------------------------}}} -- Interface to WGD ----------------------------------------------------------------------------- {{{ -- trans process ----------------------------------------------------------------------------------------{{{ interface_fsm_trans: process(clk) begin if rising_edge(clk) then wf_alloc_indx <= wf_alloc_indx_n; wf_finish <= wf_finish_n; allocated_wfs <= allocated_wfs_n; wf_indx <= wf_indx_n; sch_rqst_n_wfs_ltchd <= sch_rqst_n_wfs_ltchd_n; wf_activate <= wf_activate_n; if nrst = '0' then st_WGD_intr <= free; wg_next_id <= (others=>'0'); sch_ack_i <= '0'; else st_WGD_intr <= st_WGD_intr_n; wg_next_id <= wg_next_id_n; sch_ack_i <= sch_ack_n; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- comb process -----------------------------------------------------------------------------------------{{{ interface_fsm_comb: process(st_WGD_intr, sch_rqst, sch_rqst_n_wfs_ltchd, wf_alloc_indx, wf_active_i, sch_rqst_n_wfs_m1, allocated_wfs, wf_indx, wg_next_id, -- wg_next_id, wg_offset_d0, wg_offset_d1, wg_offset_d2) begin st_WGD_intr_n <= st_WGD_intr; wf_finish_n <= (others => '0'); wf_alloc_indx_n <= wf_alloc_indx; sch_rqst_n_wfs_ltchd_n <= sch_rqst_n_wfs_ltchd; allocated_wfs_n <= allocated_wfs; wf_indx_n <= wf_indx; wg_next_id_n <= wg_next_id; rtm_we_cv <= '0'; rtm_wrAddr_cv(N_WF_CU_W-1 downto 0) <= wf_alloc_indx; rtm_wrAddr_cv(N_WF_CU_W+1 downto N_WF_CU_W) <= "00"; rtm_wrData_cv <= wg_offset_d0; wf_activate_n <= (others=>'0'); sch_ack_n <= '0'; case st_WGD_intr is when free => -- {{{ if sch_rqst = '1' then st_WGD_intr_n <= reserve; wf_alloc_indx_n <= (others => '0'); sch_rqst_n_wfs_ltchd_n <= to_integer(sch_rqst_n_wfs_m1) + 1; allocated_wfs_n <= 0; wg_next_id_n <= wg_next_id + 1; end if; -- }}} when reserve => -- {{{ if wf_active_i(to_integer(wf_alloc_indx)) = '0' then allocated_wfs_n <= allocated_wfs + 1; wf_activate_n(to_integer(wf_alloc_indx)) <= '1'; wf_indx_n(to_integer(wf_alloc_indx)) <= allocated_wfs; -- wg_ids_n(to_integer(wf_alloc_indx)) <= wg_next_id; st_WGD_intr_n <= write_wg_d0; else wf_alloc_indx_n <= wf_alloc_indx + 1; end if; when write_wg_d0 => rtm_we_cv <= '1'; st_WGD_intr_n <= write_wg_d1; rtm_wrData_cv <= wg_offset_d0; rtm_wrAddr_cv(N_WF_CU_W+1 downto N_WF_CU_W) <= "00"; when write_wg_d1 => rtm_we_cv <= '1'; st_WGD_intr_n <= write_wg_d2; rtm_wrData_cv <= wg_offset_d1; rtm_wrAddr_cv(N_WF_CU_W+1 downto N_WF_CU_W) <= "01"; when write_wg_d2 => rtm_we_cv <= '1'; rtm_wrData_cv <= wg_offset_d2; rtm_wrAddr_cv(N_WF_CU_W+1 downto N_WF_CU_W) <= "10"; wf_alloc_indx_n <= wf_alloc_indx + 1; if allocated_wfs = sch_rqst_n_wfs_ltchd then st_WGD_intr_n <= free; sch_ack_n <= '1'; else st_WGD_intr_n <= reserve; end if; -- }}} end case; end process; ---------------------------------------------------------------------------------------------------------}}} --------------------------------------------------------------------------------------------}}} -- WFs FSMs ----------------------------------------------------------------------------- {{{ -- WFs trans process ------------------------------------------------------------------------------------{{{ WFS_fsms_trans: process(clk) begin if rising_edge(clk) then PCs <= PCs_n; PC_stack_push <= PC_stack_push_n; PC_plus_1 <= PC_plus_1_n; for i in 0 to N_WF_CU-1 loop wf_wait_vec(i)(WF_WAIT_LEN-2 downto 0) <= wf_wait_vec(i)(WF_WAIT_LEN-1 downto 1); if wf_wait_vec_alu_n(i) = '1' then wf_wait_vec(i)(14) <= '1'; end if; wf_wait_vec(i)(WF_WAIT_LEN-1) <= wf_wait_vec_fpu_n(i); if clear_wf_wait_vec(i) = '0' then if wf_wait_vec(i)(0) = '1' then wf_wait_vec(i)(0) <= '1'; end if; else wf_wait_vec(i)(0) <= '0'; end if; end loop; clear_wf_wait_vec <= clear_wf_wait_vec_n; wf_no_wait <= wf_no_wait_n; if nrst = '0' then st_wf <= (others=>idle); wf_active_i <= (others=>'0'); wf_rdy <= (others=>'0'); wf_gmem_read_rdy <= (others=>'0'); wf_gmem_write_rdy <= (others=>'0'); wf_branch_rdy <= (others=>'0'); PC_stack_pop <= (others=>'0'); else st_wf <= st_wf_n; wf_rdy <= wf_rdy_n; wf_gmem_read_rdy <= wf_gmem_read_rdy_n; wf_branch_rdy <= wf_branch_rdy_n; wf_gmem_write_rdy <= wf_gmem_write_rdy_n; wf_active_i <= wf_active_n; PC_stack_pop <= PC_stack_pop_n; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- WFs comb process -------------------------------------------------------------------------------------{{{ WFS_fsms_comb:for i in 0 to N_WF_CU-1 generate -- {{{ wf_rdy_n(i) <= '1' when st_wf_n(i)=rdy else '0'; wf_gmem_read_rdy_n(i) <= '1' when st_wf_n(i) = rdy and wf_reads_gmem(i) = '1' else '0'; wf_gmem_write_rdy_n(i) <= '1' when st_wf_n(i) = rdy and wf_reads_gmem(i) = '0' and wf_on_gmem(i) = '1' else '0'; wf_branch_rdy_n(i) <= '1' when st_wf_n(i) = rdy and wf_branches(i) = '1' else '0'; PC_plus_branch_n(i) <= PCs(i) + resize(branch_distance(i), CRAM_ADDR_W); PC_plus_1_n(i) <= PCs(i) + 1; -- }}} process(st_wf(i), PCs(i), start_addr, wf_active_i(i), advance_pc(i), pc_rdy(i), wf_on_gmem(i), gmem_finish(i), -- {{{ instr_jump(i), instr_fpu(i), true_path(i), false_path(i), PC_plus_branch_n(i), PC_stack_addr(i), wf_activate(i), wf_retired(i), wf_branches(i), PC_stack_pop(i), PC_stack_pop_ack(i), PC_stack_rdData, --PC_stack_dummy_entry_rdData, PC_stack_pop_ack_p1(i), pc_updated(i), PC_stack_push_ack(i), PC_plus_1_n(i), PC_stack_jump_entry_rdData, wf_active_record(i), wf_scratchpad_ld(i), branch_in_executoin, wf_wait_vec(i)(0), wf_no_wait(i)) -- }}} begin st_wf_n(i) <= st_wf(i); -- {{{ PCs_n(i) <= PCs(i); pc_updated_n(i) <= '0'; wf_active_n(i) <= wf_active_i(i); PC_stack_pop_n(i) <= PC_stack_pop(i); wf_active_record_dec_n(i) <= '0'; PC_stack_push_n(i) <= '0'; branch_in_executoin_n(i) <= '0'; wf_wait_vec_alu_n(i) <= '0'; wf_wait_vec_fpu_n(i) <= '0'; clear_wf_wait_vec_n(i) <= '0'; wf_no_wait_n(i) <= wf_no_wait(i); --}}} case st_wf(i) is when idle => -- {{{ wf_no_wait_n(i) <= '1'; if wf_activate(i) = '1' then st_wf_n(i) <= wait_pc_rdy; PCs_n(i) <= start_addr; pc_updated_n(i) <= '1'; wf_active_n(i) <= '1'; end if; -- }}} when check_rdy => -- {{{ if pc_rdy(i) = '1' and (wf_wait_vec(i)(0) = '1' or wf_no_wait(i) = '1') then wf_no_wait_n(i) <= '0'; if wf_retired(i) = '1' then if PC_stack_addr(i) > 0 then st_wf_n(i) <= read_PC_stack; PC_stack_pop_n(i) <= '1'; clear_wf_wait_vec_n(i) <= '1'; else st_wf_n(i) <= idle; wf_active_n(i) <= '0'; clear_wf_wait_vec_n(i) <= '1'; end if; elsif instr_jump(i) = '1' then st_wf_n(i) <= jumping; elsif wf_on_gmem(i) = '1' then st_wf_n(i) <= rdy; clear_wf_wait_vec_n(i) <= '1'; elsif wf_branches(i) = '1' then if branch_in_executoin = '0' then st_wf_n(i) <= rdy; clear_wf_wait_vec_n(i) <= '1'; else wf_no_wait_n(i) <= '1'; end if; else st_wf_n(i) <= rdy; clear_wf_wait_vec_n(i) <= '1'; end if; end if; -- }}} when read_PC_stack => -- {{{ wf_no_wait_n(i) <= '1'; if PC_stack_pop_ack_p1(i) = '1' then PC_stack_pop_n(i) <= '0'; end if; if PC_stack_pop_ack(i) = '1' then PCs_n(i) <= PC_stack_rdData; if PC_stack_jump_entry_rdData = '0' and wf_active_record(i) = to_unsigned(1, N_RECORDS_WF_W) then -- 1. condition: '0' means it is not a jump entry, i.e. it is a branch entry -- 2. condition: it is the last record, i.e. all branches have been processed (there may be jumps) if PC_stack_addr(i) = to_unsigned(0, N_RECORDS_WF_W) then -- nothing to do further, the wavefront has to retire st_wf_n(i) <= idle; wf_active_n(i) <= '0'; clear_wf_wait_vec_n(i) <= '1'; else -- there are still entries to be processed PC_stack_pop_n(i) <= '1'; end if; -- elsif PC_stack_dummy_entry_rdData = '1' then -- PC_stack_pop_n(i) <= '1'; else pc_updated_n(i) <= '1'; end if; if PC_stack_jump_entry_rdData = '0' then wf_active_record_dec_n(i) <= '1'; end if; end if; if pc_updated(i) = '1' then st_wf_n(i) <= check_rdy; end if; -- }}} when rdy => --{{{ -- the order is important if wf_branches(i) = '1' and branch_in_executoin = '1' then st_wf_n(i) <= check_rdy; wf_no_wait_n(i) <= '1'; end if; -- assert wf_branches(i) = '0' or branch_in_executoin = '0' or advance_pc(i) = '0' severity failure; if advance_pc(i) = '1' then PCs_n(i) <= PC_plus_1_n(i); if instr_fpu(i) = '1' then wf_wait_vec_fpu_n(i) <= '1'; else wf_wait_vec_alu_n(i) <= '1'; end if; pc_updated_n(i) <= '1'; if wf_on_gmem(i) = '1' then st_wf_n(i) <= wait_gmem_finish; elsif wf_branches(i) = '1' then st_wf_n(i) <= branching; pc_updated_n(i) <= '0'; branch_in_executoin_n(i) <= '1'; elsif wf_scratchpad_ld(i) = '1' then st_wf_n(i) <= scratchpad_load; else st_wf_n(i) <= wait_for_selecting_PC; end if; end if; -- }}} when wait_for_selecting_PC => -- {{{ st_wf_n(i) <= wait_pc_rdy; -- }}} when wait_pc_rdy => -- {{{ st_wf_n(i) <= check_rdy; -- }}} when wait_gmem_finish => -- {{{ if gmem_finish(i) = '1' then st_wf_n(i) <= check_rdy; end if; -- }}} when jumping => -- {{{ PC_stack_push_n(i) <= '1'; if PC_stack_push_ack(i) = '1' then PC_stack_push_n(i) <= '0'; pc_updated_n(i) <= '1'; st_wf_n(i) <= wait_for_selecting_PC; PCs_n(i) <= PC_plus_branch_n(i); end if; -- }}} when branching => -- {{{ if true_path(i) = '1' then PCs_n(i) <= PC_plus_branch_n(i); pc_updated_n(i) <= '1'; st_wf_n(i) <= wait_for_selecting_PC; elsif false_path(i) = '1' then pc_updated_n(i) <= '1'; st_wf_n(i) <= wait_for_selecting_PC; end if; -- }}} when scratchpad_load => -- {{{ -- it should wait for extra 3 clock cycles if wf_wait_vec(i)(0) = '1' then wf_no_wait_n(i) <= '1'; st_wf_n(i) <= wait_for_selecting_PC; end if; -- }}} end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -----------------------------------------------------------------------------------------}}} -- CV-Side FSM ----------------------------------------------------------------------------- {{{ -- trans process ----------------------------------------------------------------------------------------{{{ CV_side_trans: process(clk) begin if rising_edge(clk) then if nrst = '0' then st_CV <= idle; advance_pc <= (others=>'0'); phase_i <= (others=>'0'); new_instr_found <= '0'; -- for timing wf_sel_indx <= 0; pc_indx <= 0; wf_indx_in_wg <= 0; wf_indx_in_CU_i <= 0; instr_i <= (others=>'0'); pc_updated <= (others=>'0'); rd_priority <= '0'; else rd_priority <= rd_priority_n; st_CV <= st_CV_n; wf_sel_indx <= wf_sel_indx_n; advance_pc <= advance_pc_n; phase_i <= phase_n; pc_indx <= pc_indx_n; execute <= execute_n; if execute_n = '1' then wf_indx_in_wg <= wf_indx(wf_sel_indx_n); wf_indx_in_CU_i <= wf_sel_indx_n; end if; instr_i <= instr_n; pc_updated <= pc_updated_n; new_instr_found <= new_instr_found_n; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- comb process ----------------------------------------------------------------------------{{{ CV_side_comb: process(st_CV, wf_sel_indx, wf_rdy, sch_rqst, instr_buf_out, phase_i, pc_indx, pc_indx_n, wf_branch_rdy, new_instr_found, instr_i, wf_gmem_read_rdy, wf_gmem_write_rdy, rd_priority) begin -- {{{ st_CV_n <= st_CV; rd_priority_n <= rd_priority; advance_pc_n <= (others => '0'); wf_sel_indx_n <= wf_sel_indx; execute_n <= '0'; instr_n <= instr_i; phase_n <= phase_i + 1; pc_indx_n <= pc_indx; new_instr_found_n <= new_instr_found; if phase_i = (phase_i'reverse_range => '1') then instr_n <= (others=>'0'); end if; -- }}} case st_CV is when idle => -- {{{ phase_n <= (others=>'0'); if sch_rqst = '1' then st_CV_n <= check_wf_rdy; end if; -- }}} when check_wf_rdy => -- {{{ new_instr_found_n <= '0'; if phase_i(1 downto 0) = "00" then if wf_rdy /= (wf_rdy'reverse_range =>'0') then st_CV_n <= select_PC; pc_indx_n <= pri_enc(wf_rdy); if wf_branch_rdy /= (wf_branch_rdy'reverse_range => '0') then pc_indx_n <= pri_enc(wf_branch_rdy); end if; if rd_priority = '1' then if wf_gmem_read_rdy /= (wf_gmem_read_rdy'reverse_range => '0') then pc_indx_n <= pri_enc(wf_gmem_read_rdy); elsif wf_gmem_write_rdy /= (wf_gmem_write_rdy'reverse_range => '0') then pc_indx_n <= pri_enc(wf_gmem_write_rdy); -- rd_priority_n <= '0'; end if; else if wf_gmem_write_rdy /= (wf_gmem_write_rdy'reverse_range => '0') then pc_indx_n <= pri_enc(wf_gmem_write_rdy); elsif wf_gmem_read_rdy /= (wf_gmem_read_rdy'reverse_range => '0') then pc_indx_n <= pri_enc(wf_gmem_read_rdy); rd_priority_n <= '1'; end if; end if; advance_pc_n <= (others => '0'); advance_pc_n(pc_indx_n) <= '1'; new_instr_found_n <= '1'; end if; end if; -- }}} when select_PC => -- {{{ -- PC is incremented in this clock cycle, st_wf is moving to wait_for_selecting_PC, PC_slctd is being prepared in the buffuer module st_CV_n <= select_instr; when select_instr => -- st_wf is wait_pc_ready, pc_rdy is being calculated in the buffer module if new_instr_found = '1' then st_CV_n <= read_inst; else st_CV_n <= check_wf_rdy; end if; -- }}} when read_inst => -- {{{ -- st_wf is check_rdy, the instruction is at the output of the buffer module, phase(0) = '1' execute_n <= '1'; st_CV_n <= start_exec; wf_sel_indx_n <= pc_indx; phase_n <= (others=>'0'); instr_n <= instr_buf_out; -- }}} when start_exec => -- {{{ st_CV_n <= dly1; -- }}} when dly1 => -- {{{ st_CV_n <= dly2; -- }}} when dly2 => -- {{{ st_CV_n <= dly3; -- }}} when dly3 => -- {{{ st_CV_n <= check_wf_rdy; -- }}} end case; end process; ---------------------------------------------------------------------------------------------------------}}} --------------------------------------------------------------------------------------------------- }}} end Behavioral;

gpl-3.0

8aa9352c2fd2886627bf7b5e26c32574

Kinxil/VHDL_Projects

Mandelbrot/Colorgen.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library WORK; use WORK.CONSTANTS.ALL; use WORK.FUNCTIONS.ALL; entity Colorgen is Port ( iters : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0); itermax : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0); color : out STD_LOGIC_VECTOR (bit_per_pixel-1 downto 0)); end Colorgen; architecture Behavioral of Colorgen is -- TODO : Améliorer colorgen (comparaison OpenGL) type rom_type is array (0 to ITER_MAX-1) of std_logic_vector (bit_per_pixel-1 downto 0); constant color_scheme : rom_type := ( "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", 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"111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111" ); begin process(iters, itermax) begin if (iters = itermax) then color<= (others=>'0'); else color <= not color_scheme(to_integer(unsigned(iters))); end if; end process;end Behavioral; --Cut and paste following lines into Shared.vhd. -- constant ITER_MAX : integer := 4095; -- constant ITER_RANGE : integer := 12;

gpl-3.0

643abb10fc2df6ddca4b091048626b6c

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_6Stations.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

a4743406565e4ef32af5eff74cc16d9d

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_SubInteger.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

705bfd499fa826d4c87b4001492ef460

preusser/q27

src/vhdl/top/xilinx/sdrc_queens_master.vhdl

library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity sdrc_queens_master is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 90; COUNT_CYCLES : boolean := false; -- Local Clock Parameters CLK_FREQ : FREQ := 16 MHz; -- external clock CLK_MUL : positive := 31; -- computation clock: CLK_DIV : positive := 4; -- CLK_FREQ / CLK_DIV * CLK_MUL -- UART Parameters BAUDRATE : positive := 115200; SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte ); port ( --------------------------------------------------------------------------- -- 16-MHz Input Clock CLK16_U : in std_logic; --------------------------------------------------------------------------- -- Master: UART rx : in std_logic; tx : out std_logic; cts : in std_logic; rts : out std_logic; --------------------------------------------------------------------------- -- Status led : out std_logic_vector(3 downto 0); --------------------------------------------------------------------------- -- Ring Bus -- Output BUS_OUT_CLKP : out std_logic; BUS_OUT_CLKN : out std_logic; BUS_OUT_PRE_DAT : out std_logic_vector(8 downto 0); BUS_OUT_PRE_PUT : out std_logic; BUS_OUT_PRE_GO : in std_logic; BUS_OUT_SOL_DAT : out std_logic_vector(8 downto 0); BUS_OUT_SOL_PUT : out std_logic; BUS_OUT_SOL_GO : in std_logic; -- Input BUS_IN_CLKP : in std_logic; BUS_IN_CLKN : in std_logic; BUS_IN_PRE_DAT : in std_logic_vector(8 downto 0); BUS_IN_PRE_PUT : in std_logic; BUS_IN_PRE_GO : out std_logic; BUS_IN_SOL_DAT : in std_logic_vector(8 downto 0); BUS_IN_SOL_PUT : in std_logic; BUS_IN_SOL_GO : out std_logic ); end sdrc_queens_master; library IEEE; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.fifo.all; use PoC.uart.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of sdrc_queens_master is -- Bit Length of Pre-Placement constant PRE_BITS : positive := 4*L*log2ceil(N)-1; constant PRE_BYTES : positive := (PRE_BITS+7)/8; -- FIFO Dimensioning constant FIFO_DEPTH : positive := 5*(SOLVERS+5); ---------------------------------------------------------------------------- -- Global Control signal clk_comp : std_logic; -- Computation Clock signal rst_comp : std_logic; signal clk_out : std_logic; -- Communication Clock (Output Side) signal rst_out : std_logic; -- UART Interface signal rx_dat : byte; signal rx_stb : std_logic; signal tx_dat : byte; signal tx_ful : std_logic; signal tx_put : std_logic; -- Frame Interface signal pvld : std_logic; signal pdat : byte; signal peof : std_logic; signal pgot : std_logic; begin ---------------------------------------------------------------------------- -- Clock Generation blkClock: block -- Intermediate Clock Signals signal clk16 : std_logic; -- Buffered Input Clock signal clk_comp_u : std_logic; signal locked_comp : std_logic; begin -- 16 MHz Board Clock -> Computation Clock clk16_buf : IBUFG port map ( I => CLK16_U, O => clk16 ); DCM0 : DCM_BASE generic map ( CLKIN_PERIOD => to_real(1.0/CLK_FREQ, 1 ns), CLKIN_DIVIDE_BY_2 => FALSE, PHASE_SHIFT => 0, CLKFX_MULTIPLY => CLK_MUL, CLKFX_DIVIDE => CLK_DIV, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", -- only using clkfx DLL_FREQUENCY_MODE => "LOW", DFS_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, STARTUP_WAIT => TRUE, DCM_AUTOCALIBRATION => FALSE ) port map ( CLKIN => clk16, CLKFB => '0', RST => '0', CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => clk_comp_u, CLKFX180 => open, LOCKED => locked_comp ); clk_comp_buf : BUFGCE port map ( CE => locked_comp, I => clk_comp_u, O => clk_comp ); rst_comp <= '0'; clk_out_buf : BUFGCE port map ( CE => locked_comp, I => clk16, O => clk_out ); rst_out <= '0'; led(0) <= locked_comp; end block blkClock; ---------------------------------------------------------------------------- -- UART blkUART: block signal bclk_x8 : std_logic; signal bclk_x1 : std_logic; begin -- Bit Clock Generation bclk_gen_x8: entity PoC.arith_counter_free generic map ( DIVIDER => integer(to_real(CLK_FREQ, 1 Hz))/(8*BAUDRATE) ) port map ( clk => clk_out, rst => '0', inc => '1', stb => bclk_x8 ); bclk_gen_x1: entity PoC.arith_counter_free generic map ( DIVIDER => 8 ) port map ( clk => clk_out, rst => '0', inc => bclk_x8, stb => bclk_x1 ); -- Receive Bytes uart_rx_i : uart_rx port map ( clk => clk_out, rst => rst_out, bclk_x8 => bclk_x8, rx => rx, stb => rx_stb, do => rx_dat ); -- Transmit Bytes uart_tx_i : uart_tx port map ( clk => clk_out, rst => rst_out, bclk => bclk_x1, put => tx_put, di => tx_dat, ful => tx_ful, tx => tx ); rts <= cts; end block blkUART; -- Unframing blkUnframe: block -- Input Glue FIFO -> Unframe signal glue_vld : std_logic; signal glue_dat : byte; signal glue_got : std_logic; -- Unframe -> Input Buffer signal odat : byte; signal oeof : std_logic; signal oful : std_logic; signal oput : std_logic; signal ocommit : std_logic; signal orollback : std_logic; begin glue: fifo_glue generic map ( D_BITS => 8 ) port map ( clk => clk_out, rst => rst_out, put => rx_stb, di => rx_dat, ful => open, vld => glue_vld, do => glue_dat, got => glue_got ); unframe_i: entity work.unframe generic map ( SENTINEL => SENTINEL, PAY_LEN => PRE_BYTES ) port map ( clk => clk_out, rst => rst_out, rx_dat => glue_dat, rx_vld => glue_vld, rx_got => glue_got, odat => odat, oeof => oeof, oful => oful, oput => oput, ocommit => ocommit, orollback => orollback ); buf: fifo_cc_got_tempput generic map ( MIN_DEPTH => 5*(SOLVERS+5), D_BITS => 9 ) port map ( clk => clk_out, rst => rst_out, put => oput, din(8) => oeof, din(7 downto 0) => odat, full => oful, commit => ocommit, rollback => orollback, got => pgot, dout(8) => peof, dout(7 downto 0) => pdat, valid => pvld ); end block blkUnframe; blkFeed: block -- Syncing the stall input signal go_s : std_logic_vector(1 downto 0) := (others => '0'); -- Outgoing Output Registers signal OutDat : std_logic_vector(7 downto 0) := (others => '0'); signal OutEof : std_logic := '0'; signal OutPut : std_logic := '0'; -- Inverted Output Clock signal clk_inv : std_logic; begin ------------------------------------------------------------------------- -- Output Inverted Clock blkClock : block signal clk_inv : std_logic; begin invert : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '1', SRTYPE => "SYNC" ) port map ( Q => clk_inv, -- 1-bit DDR output C => clk_out, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D1 => '0', -- 1-bit data input (positive edge) D2 => '1', -- 1-bit data input (negative edge) R => rst_out, -- 1-bit reset input S => '0' -- 1-bit set input ); OBUFDS_inst : OBUFDS generic map ( IOSTANDARD => "DEFAULT", SLEW => "FAST" ) port map ( O => BUS_OUT_CLKP, OB => BUS_OUT_CLKN, I => clk_inv ); end block blkClock; ------------------------------------------------------------------------- -- Pre-placement Output -- Syncing stall input process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then go_s <= (others => '0'); else go_s <= BUS_OUT_PRE_GO & go_s(go_s'left downto 1); end if; end if; end process; pgot <= pvld and go_s(0); -- Output Registers process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then OutDat <= (others => '0'); OutEof <= '0'; OutPut <= '0'; else OutDat <= pdat; OutEof <= peof; OutPut <= pgot; end if; end if; end process; BUS_OUT_PRE_DAT <= OutEof & OutDat; BUS_OUT_PRE_PUT <= OutPut; ------------------------------------------------------------------------- -- Start of Result Chain BUS_OUT_SOL_DAT <= (others => '0'); BUS_OUT_SOL_PUT <= '0'; end block blkFeed; blkDrain: block -- Source synchronous clock domain signal clk_in : std_logic; signal rst_in : std_logic; -- Incoming Bus Data Capture Registers signal InPreDat : std_logic_vector(8 downto 0) := (others => '-'); signal InPrePut : std_logic := '0'; signal InPreCap : std_logic_vector(1 downto 0); signal InSolDat : std_logic_vector(8 downto 0) := (others => '-'); signal InSolPut : std_logic := '0'; signal InSolCap : std_logic_vector(1 downto 0); -- Solver Chain Connectivity signal pivld : std_logic; signal piful : std_logic; signal pidat : byte; signal pieof : std_logic; signal piput : std_logic; signal sivld : std_logic; signal sidat : byte; signal sieof : std_logic; signal sigot : std_logic; signal sovld : std_logic; signal sodat : byte; signal soeof : std_logic; signal sogot : std_logic; -- Solution Stream -> Frames signal tdat : std_logic_vector(7 downto 0); signal tful : std_logic; signal tput : std_logic; signal tx_vld : std_logic; signal tx_got : std_logic; begin --------------------------------------------------------------------------- -- Reading the Bus -- Clock Reconstruction blkClock : block signal clk_in0 : std_logic; begin IBUFGDS_inst : IBUFGDS port map ( O => clk_in0, I => BUS_IN_CLKP, IB => BUS_IN_CLKN ); BUFG_inst : BUFR port map ( I => clk_in0, CE => '1', CLR => '0', O => clk_in ); rst_in <= '0'; end block blkClock; -- Bus Input Capture process(clk_in) begin if rising_edge(clk_in) then if rst_in = '1' then InPreDat <= (others => '-'); InPrePut <= '0'; InSolDat <= (others => '-'); InSolPut <= '0'; else InPreDat <= BUS_IN_PRE_DAT; InPrePut <= BUS_IN_PRE_PUT; InSolDat <= BUS_IN_SOL_DAT; InSolPut <= BUS_IN_SOL_PUT; end if; end if; end process; -- Input FIFO (ic): Pre-Placements buf_pre : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InPreCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InPrePut, din => InPreDat, full => open, estate_wr => InPreCap, clk_rd => clk_comp, rst_rd => rst_comp, got => piput, dout(8) => pieof, dout(7 downto 0) => pidat, valid => pivld ); piput <= pivld and not piful; BUS_IN_PRE_GO <= '0' when InPreCap = (InPreCap'range => '0') else '1'; -- Input FIFO (ic): Solutions buf_sol : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InSolCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InSolPut, din => InSolDat, full => open, estate_wr => InSolCap, clk_rd => clk_comp, rst_rd => rst_comp, got => sigot, dout(8) => sieof, dout(7 downto 0) => sidat, valid => sivld ); BUS_IN_SOL_GO <= '0' when InSolCap = (InSolCap'range => '0') else '1'; --------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_chain generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES ) port map ( clk => clk_comp, rst => rst_comp, piful => piful, pidat => pidat, pieof => pieof, piput => piput, sivld => sivld, sidat => sidat, sieof => sieof, sigot => sigot, poful => '1', podat => open, poeof => open, poput => open, sovld => sovld, sodat => sodat, soeof => soeof, sogot => sogot ); enframe_i: entity work.enframe generic map ( SENTINEL => SENTINEL ) port map ( clk => clk_comp, rst => rst_comp, ivld => sovld, idat => sodat, ieof => soeof, igot => sogot, tx_ful => tful, tx_put => tput, tx_dat => tdat ); -- Output FIFO (ic): Solutions fifob : fifo_ic_got generic map ( D_BITS => 8, MIN_DEPTH => FIFO_DEPTH ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => tput, din => tdat, full => tful, clk_rd => clk_out, rst_rd => rst_out, got => tx_got, dout => tx_dat, valid => tx_vld ); tx_put <= tx_vld and not tx_ful; tx_got <= tx_put; end block blkDrain; led(3 downto 1) <= "110"; end rtl;

agpl-3.0

4c5d4802f60c1802fd7309264b042f7e

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sim_1/backplane_simulator.vhd

-- File: backplane_simulator.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an "as is", as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic's maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library tb_lib; use tb_lib.tb_env_pkg.all; library std; use std.env.all; use std.textio.all; library dyplo_hdl_node_lib; use dyplo_hdl_node_lib.hdl_node_package.all; use dyplo_hdl_node_lib.hdl_node_user_params.all; library dyplo; use dyplo.all; entity backplane_simulator is end backplane_simulator; architecture rtl of backplane_simulator is -- clock and reset for testbench signal dab_clk : std_logic := '0'; signal dab_rst : std_logic := '1'; --Internal signals for HDL node signal dab_clk_i : std_logic; signal dab_rst_i : std_logic; signal dab_addr_i : std_logic_vector(c_hdl_dab_awidth - 1 downto 0); signal dab_sel_i : std_logic; signal dab_wvalid_i : std_logic; signal dab_rvalid_i : std_logic; signal dab_wdata_i : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); signal dab_rdata_i : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Receive data from backplane to FIFO signal b2f_tdata_i : std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); signal b2f_tstream_id_i : std_logic_vector(c_hdl_stream_id_width - 1 downto 0); signal b2f_tvalid_i : std_logic; signal b2f_tready_i : std_logic; -- Send data from FIFO to backplane signal f2b_tdata_i : std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); signal f2b_tstream_id_i : std_logic_vector(c_hdl_stream_id_width - 1 downto 0); signal f2b_tvalid_i : std_logic; signal f2b_tready_i : std_logic; -- Clock signals signal dest_fifo_status_i : std_logic_vector(3 downto 0) := (others => '1'); -- Clock signals signal user_clocks_i : std_logic_vector(3 downto 0); --internal signals for stim_reader signal cmd_i : cmd_record; signal cmd_accept_i : std_logic; signal eof_i : std_logic; --stream signals for datain stream processes type streams_in_tdata_type is array (0 to c_input_streams - 1) of std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); type streams_in_tstream_id_type is array (0 to c_input_streams - 1) of std_logic_vector(c_hdl_stream_id_width - 1 downto 0); signal streams_in_tdata : streams_in_tdata_type; signal streams_in_tstream_id : streams_in_tstream_id_type; signal streams_in_tvalid : std_logic_vector(c_input_streams - 1 downto 0); signal streams_in_tready : std_logic_vector(c_input_streams - 1 downto 0); --tready signals for dataout stream processes signal streams_out_tready : std_logic_vector(c_output_streams - 1 downto 0); --tready signals for dataout combinatoric combined with tstream_id signal streams_out_tready_c : std_logic_vector(c_output_streams - 1 downto 0); --data signal for storing stream parameters for each stream type data_in_streams_type is array (0 to c_input_streams - 1) of data_stream; signal data_in_streams : data_in_streams_type; type data_out_streams_type is array (0 to c_output_streams - 1) of data_stream; signal data_out_streams : data_out_streams_type; --type definition of type for state machine type sm_control_type is (IDLE, PARSE_CMD, DAB_DELAY_WRITE, DAB_DELAY_READ); signal sm_control : sm_control_type := IDLE; signal schedule_in_streams : integer := 0; signal dab_delay_cnt : unsigned(1 downto 0); --delay for dab r/w signal out_streams_enabled : std_logic_vector(c_output_streams - 1 downto 0); signal out_streams_finished : std_logic_vector(c_output_streams - 1 downto 0); signal in_streams_enabled : std_logic_vector(c_input_streams - 1 downto 0); signal in_streams_finished : std_logic_vector(c_input_streams - 1 downto 0); --component declaration stim_reader component tb_stim_reader is generic( STIM_FILE_NAME : string := "" ); port ( cmd_out : out cmd_record; cmd_accept_in : in std_logic; eof : out std_logic ); end component; --component declaration HDL_node component dyplo_hdl_node is port( -- Miscellaneous node_id : in std_logic_vector(c_hdl_node_id_width - 1 downto 0); -- DAB interface dab_clk : in std_logic; dab_rst : in std_logic; dab_addr : in std_logic_vector(c_hdl_dab_awidth - 1 downto 0); dab_sel : in std_logic; dab_wvalid : in std_logic; dab_rvalid : in std_logic; dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Receive data from backplane to FIFO b2f_tdata : in std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); b2f_tstream_id : in std_logic_vector(c_hdl_stream_id_width - 1 downto 0); b2f_tvalid : in std_logic; b2f_tready : out std_logic; -- Send data from FIFO to backplane f2b_tdata : out std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); f2b_tstream_id : out std_logic_vector(c_hdl_stream_id_width - 1 downto 0); f2b_tvalid : out std_logic; f2b_tready : in std_logic; -- Serial fifo status info fifo_status_sync : in std_logic; fifo_status_flag : out std_logic; -- fifo statuses of destination fifo's dest_fifo_status : in std_logic_vector(3 downto 0); -- Clock signals user_clocks : in std_logic_vector(3 downto 0) ); end component; begin hdl_node : dyplo_hdl_node port map( -- Miscellaneous node_id => "00010", -- don't change, because of address range in simulation -- DAB interface dab_clk => dab_clk_i, dab_rst => dab_rst_i, dab_addr => dab_addr_i, dab_sel => dab_sel_i, dab_wvalid => dab_wvalid_i, dab_rvalid => dab_rvalid_i, dab_wdata => dab_wdata_i, dab_rdata => dab_rdata_i, -- Receive data from backplane to FIFO b2f_tdata => b2f_tdata_i, b2f_tstream_id => b2f_tstream_id_i, b2f_tvalid => b2f_tvalid_i, b2f_tready => b2f_tready_i, -- Send data from FIFO to backplane f2b_tdata => f2b_tdata_i, f2b_tstream_id => f2b_tstream_id_i, f2b_tvalid => f2b_tvalid_i, f2b_tready => f2b_tready_i, -- Serial fifo status info fifo_status_sync => '0', fifo_status_flag => open, -- fifo statuses of destination fifo's dest_fifo_status => dest_fifo_status_i, -- Clock signals user_clocks => user_clocks_i ); stim_reader : tb_stim_reader generic map( STIM_FILE_NAME => "../../stimuli/control_stimuli.txt" ) port map( cmd_out => cmd_i, cmd_accept_in => cmd_accept_i, eof => eof_i ); dab_clk <= not dab_clk after 5 ns; -- 100MHz clock dab_rst <= '0' after 50 ns; -- Synchronous, active high reset dab_clk_i <= dab_clk; dab_rst_i <= dab_rst; control : process(dab_clk) variable stream_no : integer := 0; variable v_value_int : integer; variable v_value_slv : std_logic_vector(31 downto 0); variable v_result : boolean; variable v_result_len : integer; variable v_string : string(1 to CMD_WORD_SIZE); begin if(rising_edge(dab_clk)) then if(dab_rst = '1') then dab_addr_i <= (others => '0'); dab_sel_i <= '0'; dab_wvalid_i <= '0'; dab_rvalid_i <= '0'; dab_wdata_i <= (others => '0'); dab_delay_cnt <= "11"; sm_control <= IDLE; data_in_streams <= (others => ((others => NUL), 0, '0')); data_out_streams <= (others => ((others => NUL), 0, '0')); else case(sm_control) is when IDLE => dab_sel_i <= '0'; dab_wvalid_i <= '0'; dab_rvalid_i <= '0'; if(cmd_i.valid = true) then sm_control <= PARSE_CMD; else cmd_accept_i <= '0'; --release command end if; when PARSE_CMD => if (cmd_i.word(0)(1 to 12) = "write_config") then -- dab write_control (hdl_node) command --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); proc_get_value ( str => v_string(1 to cmd_i.size(i)), slv => v_value_slv, result => v_result, len => v_result_len ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; if (i=1) then --address dab_addr_i <= "00000" & ( X"1000" + v_value_slv(15 downto 0)); elsif (i=2) then --data dab_wdata_i <= v_value_slv(31 downto 0); end if; end loop; dab_sel_i <= '1'; dab_delay_cnt <= "11"; sm_control <= DAB_DELAY_WRITE; elsif (cmd_i.word(0)(1 to 10) = "write_data") then -- dab write_data (user_logic) command --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); proc_get_value ( str => v_string(1 to cmd_i.size(i)), slv => v_value_slv, result => v_result, len => v_result_len ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; if (i=1) then --address dab_addr_i <= "00010" & v_value_slv(15 downto 0); elsif (i=2) then --data dab_wdata_i <= v_value_slv(31 downto 0); end if; end loop; dab_sel_i <= '1'; dab_delay_cnt <= "11"; sm_control <= DAB_DELAY_WRITE; elsif (cmd_i.word(0)(1 to 11) = "read_config") then -- dab read_control (hdl_node) command --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); proc_get_value ( str => v_string(1 to cmd_i.size(i)), slv => v_value_slv, result => v_result, len => v_result_len ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; if (i=1) then --address dab_addr_i <= "00000" & ( X"1000" + v_value_slv(15 downto 0)); end if; end loop; dab_sel_i <= '1'; dab_delay_cnt <= "11"; sm_control <= DAB_DELAY_READ; elsif (cmd_i.word(0)(1 to 9) = "read_data") then -- dab read_data (user_logic) command --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); proc_get_value ( str => v_string(1 to cmd_i.size(i)), slv => v_value_slv, result => v_result, len => v_result_len ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; if (i=1) then --address dab_addr_i <= "00010" & v_value_slv(15 downto 0); end if; end loop; dab_sel_i <= '1'; dab_delay_cnt <= "11"; sm_control <= DAB_DELAY_READ; elsif (cmd_i.word(0)(1 to 9) = "stream_in") then -- stream settings --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string := (others => NUL); v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); if(i /= 3) then proc_str_to_int ( str => v_string(1 to cmd_i.size(i)), int => v_value_int, result => v_result ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; end if; if (i=1) then --stream_no stream_no := v_value_int; if(stream_no >= c_input_streams) then report "ERROR: stream_in command: Stream nr " & integer'image(stream_no) & " invalid, valid stream nrs are 0 to " & integer'image(c_input_streams - 1) severity failure; else data_in_streams(stream_no).enable <= '1'; end if; elsif (i=2) then --length data_in_streams(stream_no).length <= v_value_int; elsif (i=3) then --filename if(v_string(1) /= NUL) then data_in_streams(stream_no).filename <= v_string; else report "ERROR: stream_in command: Filename cannot be empty" severity failure; end if; end if; end loop; sm_control <= IDLE; elsif (cmd_i.word(0)(1 to 10) = "stream_out") then -- stream settings --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string := (others => NUL); v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); if(i /= 3) then proc_str_to_int ( str => v_string(1 to cmd_i.size(i)), int => v_value_int, result => v_result ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; end if; if (i=1) then --stream_no stream_no := v_value_int; if(stream_no >= c_output_streams) then report "ERROR: stream_out command: Stream nr " & integer'image(stream_no) & " invalid, valid stream nrs are 0 to " & integer'image(c_output_streams - 1) severity failure; else data_out_streams(stream_no).enable <= '1'; end if; elsif (i=2) then --length data_out_streams(stream_no).length <= v_value_int; elsif (i=3) then --filename data_out_streams(stream_no).filename <= v_string; end if; end loop; sm_control <= IDLE; else report "ERROR: Unknown command!"; report "Found: " & cmd_i.word(0) severity failure; end if; cmd_accept_i <= '1'; -- do accept command when DAB_DELAY_WRITE => if (dab_delay_cnt /= 0) then dab_delay_cnt <= dab_delay_cnt - 1; else dab_wvalid_i <= '1'; sm_control <= IDLE; end if; when DAB_DELAY_READ => if (dab_delay_cnt /= 0) then dab_delay_cnt <= dab_delay_cnt - 1; else dab_rvalid_i <= '1'; sm_control <= IDLE; end if; end case; end if; end if; end process; -- Data in streams data_streams_in : for i in 0 to c_input_streams - 1 generate signal words_send : integer := 0; type sm_stream_type is (START_BURST, INTERRUPT_BURST, BURST); signal sm_stream : sm_stream_type := START_BURST; signal burst_cnt : integer := 0; begin stream_x : process(dab_clk) file datafile : text; variable v_file_opened : boolean := false; variable v_data_file_status : file_open_status; variable v_data_line : line; variable v_data_word : string(1 to 10); begin if(rising_edge(dab_clk)) then if(dab_rst = '1') then streams_in_tdata(i) <= (others => '0'); streams_in_tstream_id(i) <= (others => '0'); streams_in_tvalid(i) <= '0'; in_streams_finished(i) <= '0'; sm_stream <= START_BURST; else streams_in_tstream_id(i) <= std_logic_vector(to_unsigned(i,c_hdl_stream_id_width)); if(data_in_streams(i).enable = '1' and words_send < data_in_streams(i).length) then case(sm_stream) is when START_BURST => if(v_file_opened = false) then file_open(v_data_file_status, datafile, (string'("../../data/") & data_in_streams(i).filename), read_mode); if not(v_data_file_status = OPEN_OK) then report "ERROR: Unable to open data file: " & string'(data_in_streams(i).filename) severity failure; else v_file_opened := true; end if; end if; --read line from data file if(not endfile(datafile)) then str_read(datafile, v_data_word); streams_in_tdata(i) <= hstr_to_slv(v_data_word(3 to 10)); streams_in_tvalid(i) <= '1'; else report "ERROR: End of file!" severity failure; end if; burst_cnt <= 0; sm_stream <= BURST; when BURST => if(streams_in_tready(i) = '1' and streams_in_tvalid(i) = '1') then words_send <= words_send + 1; burst_cnt <= burst_cnt + 1; if( (words_send + 1) < data_in_streams(i).length) then --read line from data file if(not endfile(datafile)) then str_read(datafile, v_data_word); streams_in_tdata(i) <= hstr_to_slv(v_data_word(3 to 10)); if(burst_cnt = 63) then streams_in_tvalid(i) <= '0'; burst_cnt <= 0; sm_stream <= INTERRUPT_BURST; else streams_in_tvalid(i) <= '1'; end if; else file_close(datafile); report "ERROR: End of file!" severity failure; end if; else streams_in_tvalid(i) <= '0'; in_streams_finished(i) <= '1'; file_close(datafile); end if; end if; when INTERRUPT_BURST => streams_in_tvalid(i) <= '1'; sm_stream <= BURST; end case; end if; end if; end if; end process; end generate; b2f_tdata_i <= streams_in_tdata(schedule_in_streams); b2f_tstream_id_i <= streams_in_tstream_id(schedule_in_streams); b2f_tvalid_i <= streams_in_tvalid(schedule_in_streams); streams_in_tready <= (schedule_in_streams => b2f_tready_i, others => '0'); -- Data in streams data_streams_out : for i in 0 to c_output_streams - 1 generate signal words_received : integer := 0; type sm_stream_type is (WAITING, BURST, END_BURST); signal sm_stream : sm_stream_type := WAITING; begin stream_x : process(dab_clk) file datafile : text; variable v_file_opened : boolean := false; variable v_data_file_status : file_open_status; variable v_data_line : line; variable v_data_word : string(1 to 10); variable v_expected_data : std_logic_vector(31 downto 0); begin if(rising_edge(dab_clk)) then if(dab_rst = '1') then streams_out_tready(i) <= '0'; out_streams_finished(i) <= '0'; else if(data_out_streams(i).enable = '1' and words_received < data_out_streams(i).length) then streams_out_tready(i) <= '1'; if(data_out_streams(i).filename(1) /= NUL) then if(v_file_opened = false) then file_open(v_data_file_status, datafile, (string'("../../data/") & data_out_streams(i).filename), read_mode); if not(v_data_file_status = OPEN_OK) then report "ERROR: Unable to open data file: " & string'(data_out_streams(i).filename) severity failure; else v_file_opened := true; end if; end if; end if; if(f2b_tvalid_i = '1' and streams_out_tready(i) = '1' and conv_integer(f2b_tstream_id_i) = i) then words_received <= words_received + 1; if(data_out_streams(i).filename(1) /= NUL) then --read line from data file if(not endfile(datafile)) then str_read(datafile, v_data_word); v_expected_data := hstr_to_slv(v_data_word(3 to 10)); else report "ERROR: End of file!" severity failure; end if; assert f2b_tdata_i = v_expected_data report "ERROR: Received data does not match expected data" severity failure; end if; --read from file and data bus and check (assert) if( (words_received + 1) = data_out_streams(i).length) then streams_out_tready(i) <= '0'; out_streams_finished(i) <= '1'; if(data_out_streams(i).filename(1) /= NUL) then file_close(datafile); end if; end if; end if; end if; end if; end if; end process; streams_out_tready_c(i) <= '1' when (streams_out_tready(i) = '1' and conv_integer(f2b_tstream_id_i) = i) else '0'; end generate; f2b_tready_i <= '1' when (streams_out_tready_c /= std_logic_vector(to_unsigned(0,4))) else '0'; schedule : process(dab_clk) variable schedule_in_next : integer := 0; begin if(rising_edge(dab_clk)) then if(dab_rst_i = '1') then schedule_in_streams <= 0; else if(streams_in_tvalid(schedule_in_streams) = '0') then --Schedule, next lane schedule_in_next := schedule_in_streams; for s in 0 to c_input_streams - 1 loop if(schedule_in_next = c_input_streams - 1) then schedule_in_next := 0; else schedule_in_next := schedule_in_next + 1; end if; if(streams_in_tvalid(schedule_in_next) = '1') then exit; end if; end loop; schedule_in_streams <= schedule_in_next; --Schedule, next lane end if; end if; end if; end process; user_clock_0 : process begin user_clocks_i(0) <= '0'; wait for 20 ns; user_clocks_i(0) <= '1'; wait for 20 ns; end process; user_clock_1 : process begin user_clocks_i(1) <= '0'; wait for 15 ns; user_clocks_i(1) <= '1'; wait for 15 ns; end process; user_clock_2 : process begin user_clocks_i(2) <= '0'; wait for 10 ns; user_clocks_i(2) <= '1'; wait for 10 ns; end process; user_clock_3 : process begin user_clocks_i(3) <= '0'; wait for 5 ns; user_clocks_i(3) <= '1'; wait for 5 ns; end process; enabled_in: for i in 0 to c_input_streams - 1 generate begin in_streams_enabled(i) <= data_in_streams(i).enable; end generate enabled_in; enabled_out: for i in 0 to c_output_streams - 1 generate begin out_streams_enabled(i) <= data_out_streams(i).enable; end generate enabled_out; p_finished: process(dab_clk) begin if (rising_edge(dab_clk)) then if dab_rst_i = '0' then if(eof_i = '1' and (out_streams_finished = out_streams_enabled and in_streams_finished = in_streams_enabled) ) then report "*** End of simulation ***"; finish(0); end if; end if; end if; end process p_finished; end rtl;

gpl-2.0

a6334997d2da6a7dfcb4c72555827e87

jpidancet/mips

rtl/alu.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; library work; use work.mips_defs.ALL; entity alu is port (op : in alucontrol_type; a : in std_logic_vector(31 downto 0); b : in std_logic_vector(31 downto 0); shift : in std_logic_vector(4 downto 0); result : out std_logic_vector(31 downto 0); overflow : out std_logic); end entity alu; architecture rtl of alu is begin process (op, a, b) variable tmp : std_logic_vector(31 downto 0); begin case op is when ALU_SLL => result <= std_logic_vector(unsigned(b) sll to_integer(unsigned(shift))); overflow <= '0'; when ALU_SRL => result <= std_logic_vector(unsigned(b) srl to_integer(unsigned(shift))); overflow <= '0'; when ALU_AND => result <= a and b; overflow <= '0'; when ALU_OR => result <= a or b; overflow <= '0'; when ALU_XOR => result <= a xor b; overflow <= '0'; when ALU_NOR => result <= a nor b; overflow <= '0'; when ALU_ADD => tmp := a + b; result <= tmp; overflow <= (not a(31) and not b(31) and tmp(31)) or (a(31) and b(31) and not tmp(31)); when ALU_SUB => tmp := a - b; result <= tmp; overflow <= (not a(31) and b(31) and tmp(31)) or (a(31) and not b(31) and not tmp(31)); when ALU_SLT => if signed(a) < signed(b) then result <= (0 => '1', others => '0'); else result <= (others => '0'); end if; overflow <= '0'; when ALU_SLTU => if unsigned(a) < unsigned(b) then result <= (0 => '1', others => '0'); else result <= (others => '0'); end if; overflow <= '0'; when ALU_BPLUS4 => result <= b + 4; overflow <= '0'; end case; end process; end architecture rtl;

isc

dafe1ca6ead2f7f61ff3dd01e7641e2e

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_output_block.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block fnKWgUaCSOqW4UkV7KTA5KHnkoXkAb2Q6EROHzdT85wRehO7Bp2/qKeiQRmzk4OErZoVhcC/f8kQ w+EPkQ3ogw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eJKqI8HhFxYftSk0GjwFmXDujn9dJbE4wcwqBdSjZ+EKpDlxN0as76LhbI0XFqbHtE/tcXTbBPhj nnNsDjsQWL/ZAP+l8koPdk9W56Ezy1OCf2LfOkXL7pSgc3m/cUGSj76G+GDuiAr99UJGFcRgmzcM FZ0NkcRsdxUDLlncB0Q= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block R/39QEgL3lQhXNpaZ/bVFCv8YTW7tzoVF9JPRkbopv8OLDCkTfBbDsONiZfacgTvB4EnLoMU7fWU SsTCEBE0Wj204nffuddAr4phNsu/i5vErtUCrFRYPgsLL55TwM9oF+im1cIHr4REaLPkFqrrVWDW XhSm43XpUkqrekcHJVOtMmCp5uCvCJpaSO5RvlW2utNuRUlIUHMRlccAjUSnYV7iBLNVZbNUpRO5 NVcPR1k+Wj6Z8akEI/nOFan+OTDCcm51bXXoE5/CrQ6coTeEmcnHZF4ZOt6O/d/d2ZSsEgVeehpz ygfsS/Xd8V8BC7gxWQnJOyeedqG9J5U0xMaEag== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block EZrXXPwe8Ykj0I7j8dobf/sku+pG5iRw9/bsB2jmZ41ObJ+pOv30287Uk7fKCI3kNXkzemuQMsOF NVWiSKM9rZZKyfHtzkQ94vkiB+FkFIRPVi4ZafpVK4hNWYDSKN348zQ0h53wgua5Ao3HK+hiZq0O T5cLR+YwW3RXHg5VNo4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block s/5aAaqHVD32pMacHasdrv9p8gjO70pwV+7r1OUiW+2tzrWAX2eXWSGnCr4A50uFnWUGmOECfpSC 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mit

e3cca48a2dc3a1bc405f9708ee4f4ad1

malkadi/FGPU

RTL/CU_mem_cntrl.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity CU_mem_cntrl is --{{{ port( clk : in std_logic; -- from the CV cv_wrData : in SLV32_ARRAY(CV_SIZE-1 downto 0); -- level 17. cv_addr : in GMEM_ADDR_ARRAY; -- level 17. cv_gmem_we : in std_logic; cv_gmem_re : in std_logic; cv_gmem_atomic : in std_logic; cv_lmem_rqst : in std_logic; -- level 17. cv_lmem_we : in std_logic; cv_op_type : in std_logic_vector(2 downto 0); -- level 17. cv_alu_en : in std_logic_vector(CV_SIZE-1 downto 0); cv_alu_en_pri_enc : in integer range 0 to CV_SIZE-1 := 0; cv_rd_addr : in unsigned(REG_FILE_W-1 downto 0); -- to the CV regFile_wrAddr : out unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); -- stage -1 (stable for 3 clock cycles) regFile_we : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- stage 0 (stable for 2 clock cycles) (level 20. for loads from lmem) regFile_wrData : out SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- stage 0 (stable for 2 clock cycles) regFile_we_lmem_p0 : out std_logic := '0'; -- level 19. -- interface to the global memory controller cache_rdAck : in std_logic := '0'; cache_rdAddr : in unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); cache_rdData : in std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0); atomic_rdData : in std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); atomic_rdData_v : in std_logic := '0'; atomic_sgntr : in std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); gmem_wrData : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); gmem_valid : out std_logic := '0'; gmem_we : out std_logic_vector(DATA_W/8-1 downto 0) := (others=>'0'); gmem_rnw : out std_logic := '0'; gmem_atomic : out std_logic := '0'; gmem_atomic_sgntr : out std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); gmem_ready : in std_logic; gmem_rqst_addr : out unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); -- to CU scheduler wf_finish : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); finish_exec : in std_logic := '0'; cntrl_idle : out std_logic := '0'; nrst : in std_logic ); end entity; --}}} architecture Behavioral of CU_mem_cntrl is -- signals definitions ---------------------------------------------------------------------{{{ -- internal signals definitions {{{ signal gmem_valid_i : std_logic := '0'; signal regFile_wrAddr_i : unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); signal cntrl_idle_i : std_logic := '0'; -- }}} -- constants & functions {{{ constant N_STATIONS : natural := CV_SIZE*N_STATIONS_ALU; type stations_for_alu_array is array(CV_SIZE-1 downto 0) of nat_array(N_STATIONS_ALU-1 downto 0); -- functions ------------------------------------------------------------------ {{{ function distribute_stations_on_ALUs(n_stations: integer; n_alus: integer) return nat_array is variable res: nat_array(n_stations-1 downto 0) := (others=>0); begin for i in 0 to n_stations-1 loop for k in 0 to n_alus-1 loop if i < (k+1)*(n_stations/n_alus) and i >= k*(n_stations/n_alus) then res(i) := k; exit; end if; end loop; end loop; return res; end function; function order_stations_by_priority(n_stations: integer; n_alus: integer) return nat_array is -- variable res: nat_array(n_stations-1 downto 0) := (0=>13, 1=>15, 2=>0, 3=>2, 4=>4, 5=>6, 6=>8, 7=>10, 8=>12, 9=>14, 10=>1, 11=>3, 12=>5, 13=>7, 14=>9, 15=>11); -- variable res: nat_array(n_stations-1 downto 0) := (0=>9, 1=>11, 2=>13, 3=>15, 4=>0, 5=>2, 6=>4, 7=>6, 8=>8, 9=>10, 10=>12, 11=>14, 12=>1, 13=>3, 14=>5, 15=>7); variable res: nat_array(n_stations-1 downto 0) := (others=>0); begin -- if n_stations /= 16 or n_alus /= 8 then for i in 0 to n_alus-1 loop for j in 0 to n_stations/n_alus -1 loop res(i + j*n_alus) := i*n_stations/n_alus + j; end loop; end loop; -- end if; return res; end function; function distribute_alus_on_stations(n_stations: natural; n_alus: natural) return stations_for_alu_array is variable res: stations_for_alu_array := (others=>(others=>0)); begin for k in 0 to n_alus-1 loop for j in 0 to (n_stations/n_alus)-1 loop res(k)(j) := k*n_stations/n_alus + j; end loop; end loop; return res; end function; -------------------------------------------------------------------------------------}}} --station signals constant c_alu_for_stations : nat_array(N_STATIONS-1 downto 0) := distribute_stations_on_ALUs(N_STATIONS, CV_SIZE); constant c_stations_for_alus : stations_for_alu_array := distribute_alus_on_stations(N_STATIONS, CV_SIZE); constant c_stations_ordered_for_priority: nat_array(N_STATIONS-1 downto 0) := order_stations_by_priority(N_STATIONS, CV_SIZE); --- }}} -- finish signals {{{ type st_finish_type is (idle, serving, finished); type st_finish_array_type is array (natural range<>) of st_finish_type; signal st_finish, st_finish_n : st_finish_array_type(N_WF_CU-1 downto 0) := (others=>idle); signal check_finish : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal check_finish_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_finish_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wfs_being_served : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); -- }}} -- stations signals {{{ type st_station_type is (idle, get_ticket, wait_read_done, write_back, wait_atomic); type st_station_array is array(natural range <>) of st_station_type; signal st_stations, st_stations_n : st_station_array(N_STATIONS-1 downto 0) := (others=>idle); signal station_gmem_addr : gmem_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_gmem_addr_n : gmem_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_rd_addr : reg_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_rd_addr_n : reg_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_free, station_free_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_wait_atomic : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_wait_atomic_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_go, station_go_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_rnw, station_rnw_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_atomic, station_atomic_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_perfomed : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_perfomed_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_rdData_n, station_rdData : SLV32_ARRAY(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_wrData_n, station_wrData : SLV32_ARRAY(N_STATIONS-1 downto 0) := (others=>(others=>'0')); type op_type_array is array (natural range <>) of std_logic_vector(2 downto 0); signal station_op_type : op_type_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_op_type_n : op_type_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_written_back : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_written_back_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal regFile_we_latch : std_logic := '0'; signal regFile_we_latch_p0 : std_logic := '0'; signal regFile_we_latch_p0_n : std_logic := '0'; signal ticket_granted : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal stations_prefered : integer range 0 to N_STATIONS_ALU-1 := 0; signal station_read_performed_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_atomic_perormed : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal atomic_rdData_v_d0 : std_logic := '0'; signal atomic_rdData_v_d1 : std_logic := '0'; signal atomic_rdData_d0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal atomic_rdData_d1 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); attribute max_fanout of atomic_rdData_d1 : signal is 10; signal atomic_sgntr_d0 : std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); signal station_last_atomic_serve : integer range 0 to N_STATIONS-1 := 0; signal station_wf_indx : wf_active_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_wf_indx_n : wf_active_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); -- }}} -- memory requests buffer {{{ -- 0..31: DATA, 32:63: ADDR, 64:re, 65:atomic, 66..68: op_type, 69:alu_en, 70..80: rd_addr constant MEM_RQST_W : integer := DATA_W+GMEM_ADDR_W+1+1+3+1+REG_FILE_W; constant MEM_RQST_DATA_LOW : integer := 0; constant MEM_RQST_DATA_HIGH : integer := MEM_RQST_DATA_LOW+DATA_W-1; -- 31 constant MEM_RQST_ADDR_LOW : integer := MEM_RQST_DATA_HIGH+1; -- 32 constant MEM_RQST_ADDR_HIGH : integer := MEM_RQST_ADDR_LOW+GMEM_ADDR_W-1; -- 63 constant MEM_RQST_RE_POS : integer := MEM_RQST_ADDR_HIGH+1; -- 64 constant MEM_RQST_ATOMIC_POS : integer := MEM_RQST_RE_POS+1; -- 65 constant MEM_RQST_OP_TYPE_LOW : integer := MEM_RQST_ATOMIC_POS+1; -- 66 constant MEM_RQST_OP_TYPE_HIGH : integer := MEM_RQST_OP_TYPE_LOW+2; -- 68 constant MEM_RQST_ALU_EN_POS : integer := MEM_RQST_OP_TYPE_HIGH+1; -- 69 constant MEM_RQST_RD_ADDR_LOW : integer := MEM_RQST_ALU_EN_POS+1; -- 70 constant MEM_RQST_RD_ADDR_HIGH : integer := MEM_RQST_RD_ADDR_LOW+REG_FILE_W-1; -- 80 type mem_rqsts_buffer_type is array(natural range <>) of std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0); signal mem_rqsts : mem_rqsts_buffer_type(N_WF_CU*2**(PHASE_W)-1 downto 0) := (others=>(others=>'0')); signal mem_rqsts_data : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias signal mem_rqsts_addr : gmem_addr_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias signal mem_rqsts_re : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); --alias signal mem_rqsts_atomic : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); --alias signal mem_rqsts_op_type : op_type_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias signal mem_rqsts_rd_addr : reg_addr_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias signal mem_rqsts_alu_en : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); --alias signal mem_rqsts_rdAddr : unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0'); signal mem_rqsts_rdAddr_inc_n : std_logic := '0'; signal mem_rqsts_wrAddr : unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0'); type mem_rqsts_array is array(natural range <>) of std_logic_vector(MEM_RQST_W-1 downto 0); signal mem_rqsts_rdData_n : std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0) := (others=>'0'); signal mem_rqsts_rdData : std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0) := (others=>'0'); signal mem_rqsts_rdData_ltchd_n : mem_rqsts_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal mem_rqsts_rdData_ltchd : mem_rqsts_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); attribute max_fanout of mem_rqsts_rdData_ltchd : signal is 300; signal mem_rqsts_phase_ltchd : std_logic_vector(PHASE_W-1 downto 0) := (others=>'0'); signal mem_rqsts_phase_ltchd_n : std_logic_vector(PHASE_W-1 downto 0) := (others=>'0'); signal mem_rqsts_wf_indx_ltchd : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal mem_rqsts_wf_indx_ltchd_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal mem_rqsts_wrData : std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0) := (others=>'0'); signal mem_rqsts_we : std_logic := '0'; signal mem_rqst_waiting : std_logic := '0'; signal mem_rqst_waiting_p0 : std_logic := '0'; signal mem_rqsts_nserved : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal mem_rqsts_nserved_n : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- }}} -- CV side signals {{{ type st_cv_side_type is (get_rqst, fill_stations, wait_update); signal st_cv_side, st_cv_side_n : st_cv_side_type := get_rqst; signal latch_rdData, latch_rdData_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); -- }}} -- regFile signals {{{ type regFile_interface_type is (choose_rd_addr, update, wait_1_cycle, wait_scratchpad); signal st_regFile_int, st_regFile_int_n : regFile_interface_type := choose_rd_addr; signal regFile_wrAddr_p0_n : unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); signal regFile_wrAddr_p0 : unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); signal regFile_we_p0_n, regFile_we_p0 : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- }}} -- signals of the request waiting to be processed {{{ type st_waiting_type is (free, one_serve_zero_wait, one_serve_one_wait, zero_serve_one_wait); type cv_wrData_waiting_type is array(natural range <>) of SLV32_ARRAY(CV_SIZE-1 downto 0); type cv_addr_waiting_type is array(natural range <>) of GMEM_ADDR_ARRAY(CV_SIZE-1 downto 0); -- }}} -- mem interface {{{ signal station_get_ticket : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_get_ticket_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); -- fifo line -- addr station_sgntr atomic data rnw we -- GMEM_WORD_ADDR_W N_CU_STATIONS_W 1 DATA_W 1 DATA_W/8 type fifo_type is array (natural range <>) of std_logic_vector(DATA_W+1+DATA_W/8+N_CU_STATIONS_W downto 0); type fifo_addr_type is array (natural range <>) of std_logic_vector(GMEM_ADDR_W-1 downto 0); signal fifo : fifo_type(2**FIFO_ADDR_W-1 downto 0) := (others=>(others=>'0')); signal fifo_addr : fifo_addr_type(2**FIFO_ADDR_W-1 downto 0) := (others=>(others=>'0')); signal fifo_wrAddr, fifo_rdAddr : unsigned(FIFO_ADDR_W-1 downto 0) := (others=>'0'); signal fifo_wrAddr_n, fifo_rdAddr_n : unsigned(FIFO_ADDR_W-1 downto 0) := (others=>'0'); signal push, push_d0 : std_logic := '0'; signal push_rqst_fifo_n : std_logic := '0'; signal fifo_full : std_logic := '0'; signal pop : std_logic := '0'; signal din_rqst_fifo, din_rqst_fifo_d0 : std_logic_vector(DATA_W+1+DATA_W/8+N_CU_STATIONS_W downto 0) := (others=>'0'); signal din_rqst_fifo_addr : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal din_rqst_fifo_addr_d0 : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal station_slctd_indx, station_slctd_indx_n : natural range 0 to N_STATIONS-1 := 0; attribute max_fanout of station_slctd_indx : signal is 60; --extra constant c_rqst_fifo_addr_valid_len : natural := 3; signal din_rqst_fifo_addr_d0_v : unsigned(c_rqst_fifo_addr_valid_len-1 downto 0) := (others=>'0'); signal fifo_dout : fifo_type(CV_TO_CACHE_SLICE-1 downto 0) := (others=>(others=>'0')); signal fifo_addr_dout : fifo_addr_type(CV_TO_CACHE_SLICE-1 downto 0) := (others=>(others=>'0')); signal gmem_valid_vec : std_logic_vector(CV_TO_CACHE_SLICE-1 downto 0) := (others=>'0'); signal pop_vec : std_logic_vector(CV_TO_CACHE_SLICE-1 downto 0) := (others=>'0'); signal lmem_rdData : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal lmem_rdData_d0 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal lmem_rdData_v : std_logic := '0'; signal lmem_rdData_alu_en : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal lmem_rdData_rd_addr : unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); signal sp : unsigned(LMEM_ADDR_W-N_WF_CU_W-PHASE_W-1 downto 0) := (others=>'0'); -- }}} -- read cache buffer signals ----------------------------------------------------------------------------{{{ signal rd_fifo_data, rd_fifo_data_d0 : std_logic_vector(DATA_W*RD_CACHE_N_WORDS-1 downto 0) := (others=>'0'); attribute max_fanout of rd_fifo_data_d0 : signal is 8; --extra signal rd_fifo_addr : unsigned(GMEM_WORD_ADDR_W-RD_CACHE_N_WORDS_W-1 downto 0) := (others=>'0'); signal rd_fifo_v : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} ------------------------------------------------------------------------------------------------}}} begin -- internal signals assignments -------------------------------------------------------------------------{{{ regFile_wrAddr <= regFile_wrAddr_i; assert CV_TO_CACHE_SLICE > 0 severity failure; cntrl_idle <= cntrl_idle_i; ---------------------------------------------------------------------------------------------------------}}} -- CV interface (get requests) -------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then mem_rqsts_rdData_n <= mem_rqsts(to_integer(mem_rqsts_rdAddr)); if mem_rqsts_we = '1' then mem_rqsts(to_integer(mem_rqsts_wrAddr)) <= mem_rqsts_wrData; end if; mem_rqsts_rdData <= mem_rqsts_rdData_n; mem_rqsts_we <= '0'; if cv_gmem_re = '1' or cv_gmem_we = '1' or (ATOMIC_IMPLEMENT /= 0 and cv_gmem_atomic = '1') then mem_rqsts_we <= '1'; end if; for i in 0 to CV_SIZE-1 loop mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_DATA_HIGH downto i*MEM_RQST_W+MEM_RQST_DATA_LOW) <= cv_wrData(i); mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_ADDR_HIGH downto i*MEM_RQST_W+MEM_RQST_ADDR_LOW) <= std_logic_vector(cv_addr(i)); mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_RE_POS) <= cv_gmem_re; if ATOMIC_IMPLEMENT /= 0 then mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_ATOMIC_POS) <= cv_gmem_atomic; end if; mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_OP_TYPE_HIGH downto i*MEM_RQST_W+MEM_RQST_OP_TYPE_LOW) <= cv_op_type; mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_ALU_EN_POS) <= cv_alu_en(i); mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_RD_ADDR_HIGH downto i*MEM_RQST_W+MEM_RQST_RD_ADDR_LOW) <= std_logic_vector(cv_rd_addr); end loop; mem_rqst_waiting_p0 <= '0'; if mem_rqsts_wrAddr /= mem_rqsts_rdAddr then mem_rqst_waiting_p0 <= '1'; end if; mem_rqst_waiting <= mem_rqst_waiting_p0; if nrst = '0' then mem_rqsts_wrAddr <= (others=>'0'); mem_rqsts_rdAddr <= (others=>'0'); else if mem_rqsts_we = '1' then mem_rqsts_wrAddr <= mem_rqsts_wrAddr + 1; end if; if mem_rqsts_rdAddr_inc_n = '1' then mem_rqsts_rdAddr <= mem_rqsts_rdAddr + 1; end if; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- CV interface (schedule requests) -------------------------------------------------------------------{{{ cv_side_trans: process(clk) begin if rising_edge(clk) then station_go <= station_go_n; mem_rqsts_rdData_ltchd <= mem_rqsts_rdData_ltchd_n; mem_rqsts_phase_ltchd <= mem_rqsts_phase_ltchd_n; mem_rqsts_wf_indx_ltchd <= mem_rqsts_wf_indx_ltchd_n; mem_rqsts_nserved <= mem_rqsts_nserved_n; check_finish <= check_finish_n; if nrst = '0' then st_cv_side <= get_rqst; else st_cv_side <= st_cv_side_n; end if; end if; end process; cv_side_comb: process(st_cv_side, mem_rqst_waiting, station_free, mem_rqsts_rdData, mem_rqsts_nserved, mem_rqsts_phase_ltchd, mem_rqsts_rdData_ltchd, mem_rqsts_wf_indx_ltchd) begin st_cv_side_n <= st_cv_side; station_go_n <= (others=>'0'); mem_rqsts_rdAddr_inc_n <= '0'; mem_rqsts_nserved_n <= mem_rqsts_nserved; check_finish_n <= (others=>'0'); mem_rqsts_rdData_ltchd_n <= mem_rqsts_rdData_ltchd; mem_rqsts_wf_indx_ltchd_n <= mem_rqsts_wf_indx_ltchd; mem_rqsts_phase_ltchd_n <= mem_rqsts_phase_ltchd; case st_cv_side is when get_rqst => for i in 0 to CV_SIZE-1 loop mem_rqsts_rdData_ltchd_n(i) <= mem_rqsts_rdData((i+1)*MEM_RQST_W-1 downto i*MEM_RQST_W); end loop; -- latch wf_indx and phase from first ALU mem_rqsts_wf_indx_ltchd_n <= (others=>'0'); mem_rqsts_wf_indx_ltchd_n(to_integer(unsigned( mem_rqsts_rdData(MEM_RQST_RD_ADDR_LOW+WI_REG_ADDR_W+N_WF_CU_W-1 downto MEM_RQST_RD_ADDR_LOW+WI_REG_ADDR_W)))) <= '1'; mem_rqsts_phase_ltchd_n(1 downto 0) <= mem_rqsts_rdData(MEM_RQST_RD_ADDR_HIGH downto MEM_RQST_RD_ADDR_HIGH-1); mem_rqsts_phase_ltchd_n(2) <= mem_rqsts_rdData(MEM_RQST_RD_ADDR_HIGH-2); for i in 0 to CV_SIZE-1 loop mem_rqsts_nserved_n(i) <= mem_rqsts_rdData(i*MEM_RQST_W + MEM_RQST_ALU_EN_POS); end loop; if mem_rqst_waiting = '1' then st_cv_side_n <= fill_stations; mem_rqsts_rdAddr_inc_n <= '1'; end if; when fill_stations => for i in 0 to cv_size-1 loop for j in 0 to n_stations_alu-1 loop if station_free(c_stations_for_alus(i)(j)) = '1' and mem_rqsts_nserved(i) = '1' then station_go_n(c_stations_for_alus(i)(j)) <= '1'; mem_rqsts_nserved_n(i) <= '0'; exit; end if; end loop; end loop; if mem_rqsts_nserved = (mem_rqsts_nserved'reverse_range => '0') then st_cv_side_n <= wait_update; end if; when wait_update => -- necessary to wait for mem_rqsts_rdData to be ready in case no alu was enabled st_cv_side_n <= get_rqst; if mem_rqsts_phase_ltchd = (mem_rqsts_phase_ltchd'reverse_range=>'1') then check_finish_n <= mem_rqsts_wf_indx_ltchd; end if; end case; end process; ----------------------------------------------------------------------------------------- }}} -- gmem controller interface -------------------------------------------------------------------------------------------{{{ -- fifo {{{ process(clk) begin if rising_edge(clk) then if nrst = '0' then gmem_valid_vec <= (others=>'0'); else if pop = '1' or gmem_valid_vec /= (gmem_valid_vec'reverse_range=>'1') then gmem_valid_vec(gmem_valid_vec'high) <= gmem_valid_i; end if; for i in CV_TO_CACHE_SLICE-1 downto 1 loop if pop = '1' or gmem_valid_vec(i-1 downto 0) /= (i-1 downto 0=>'1') then gmem_valid_vec(i-1) <= gmem_valid_vec(i); end if; end loop; end if; if push_d0 = '1' then fifo(to_integer(fifo_wrAddr)) <= din_rqst_fifo_d0; fifo_addr(to_integer(fifo_wrAddr)) <= din_rqst_fifo_addr_d0; end if; if pop = '1' or gmem_valid_vec /= (gmem_valid_vec'reverse_range=>'1') then fifo_addr_dout(fifo_addr_dout'high) <= fifo_addr(to_integer(fifo_rdAddr)); fifo_dout(fifo_dout'high) <= fifo(to_integer(fifo_rdAddr)); end if; for i in CV_TO_CACHE_SLICE-1 downto 1 loop if pop = '1' or gmem_valid_vec(i-1 downto 0) /= (i-1 downto 0=>'1') then fifo_addr_dout(i-1) <= fifo_addr_dout(i); fifo_dout(i-1) <= fifo_dout(i); end if; end loop; if pop = '1' or gmem_valid_vec(CV_TO_CACHE_SLICE-2 downto 0) /= (0 to CV_TO_CACHE_SLICE-2 =>'1') then if SUB_INTEGER_IMPLEMENT /= 0 then case fifo_dout(CV_TO_CACHE_SLICE-1)(DATA_W+1+DATA_W/8)&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0) is -- DATA_W+1+DATA_W/8 for atomic bit when "0001" => -- byte case fifo_addr_dout(CV_TO_CACHE_SLICE-1)(1 downto 0) is when "00" => -- 1st byte fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0001"; when "01" => -- 2nd byte fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0010"; fifo_dout(CV_TO_CACHE_SLICE-2)(2*8+5-1 downto 5+8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(7+5 downto 5); when "10" => -- 3rd byte fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0100"; fifo_dout(CV_TO_CACHE_SLICE-2)(3*8+5-1 downto 5+2*8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(7+5 downto 5); when others => -- 4th byte fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "1000"; fifo_dout(CV_TO_CACHE_SLICE-2)(4*8+5-1 downto 5+3*8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(7+5 downto 5); end case; when "0010" => -- half case fifo_addr_dout(CV_TO_CACHE_SLICE-1)(1) is when '0' => -- 1st half fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0011"; when others => -- 2nd half fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "1100"; fifo_dout(CV_TO_CACHE_SLICE-2)(4*8+5-1 downto 5+2*8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(2*8+5-1 downto 5); end case; when "0100" => -- word fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= (others=>'1'); when others=> fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= '0'&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0); end case; else case fifo_dout(CV_TO_CACHE_SLICE-1)(DATA_W+1+DATA_W/8)&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0) is -- DATA_W+1+DATA_W/8 for atomic bit when "0100" => -- word fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= (others=>'1'); when others=> fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= '0'&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0); end case; end if; end if; end if; end process; -- fifo read port gmem_rqst_addr <= unsigned(fifo_addr_dout(0)(GMEM_ADDR_W-1 downto 2)); gmem_wrData <= fifo_dout(0)(DATA_W+DATA_W/8+1-1 downto DATA_W/8+1); gmem_rnw <= fifo_dout(0)(DATA_W/8); gmem_we <= fifo_dout(0)(DATA_W/8-1 downto 0); -- assert gmem_rqst_addr(GMEM_WORD_ADDR_W-1 downto GMEM_WORD_ADDR_W-4) = X"01" or gmem_we /= X"F" severity failure; atomic_signals: if ATOMIC_IMPLEMENT /= 0 generate gmem_atomic <= fifo_dout(0)(DATA_W+DATA_W/8+1); gmem_atomic_sgntr <= fifo_dout(0)(din_rqst_fifo'high downto din_rqst_fifo'high - N_CU_STATIONS_W+1); end generate; gmem_valid <= gmem_valid_vec(0); pop <= gmem_valid_vec(0) and gmem_ready; -- prepare write data into the fifo din_rqst_fifo_addr <= std_logic_vector(station_gmem_addr(station_slctd_indx)); din_rqst_fifo(din_rqst_fifo'high downto din_rqst_fifo'high-N_CU_STATIONS_W+1) <= std_logic_vector(to_unsigned(station_slctd_indx, N_CU_STATIONS_W)); atomic_din: if ATOMIC_IMPLEMENT /= 0 generate din_rqst_fifo(DATA_W+1+DATA_W/8) <= station_atomic(station_slctd_indx); end generate; din_rqst_fifo(DATA_W+1+DATA_W/8-1 downto 1+DATA_W/8) <= station_wrData(station_slctd_indx); din_rqst_fifo(DATA_W/8) <= station_rnw(station_slctd_indx); din_rqst_fifo(2 downto 0) <= station_op_type(station_slctd_indx); rqst_fifo: process(clk) begin if rising_edge(clk) then push_d0 <= push; if din_rqst_fifo_addr_d0_v /= (din_rqst_fifo_addr_d0_v'reverse_range=>'0') and din_rqst_fifo_addr_d0(GMEM_ADDR_W-1 downto CACHE_N_BANKS_W+2) = din_rqst_fifo_addr(GMEM_ADDR_W-1 downto CACHE_N_BANKS_W+2) and din_rqst_fifo_d0(DATA_W/8) = '1' and din_rqst_fifo(DATA_W/8) = '1' then push_d0 <= '0'; end if; din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high) <= '0'; din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high-1 downto 0) <= din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high downto 1); if push = '1' then din_rqst_fifo_d0 <= din_rqst_fifo; din_rqst_fifo_addr_d0 <= din_rqst_fifo_addr; din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high) <= '1'; end if; if din_rqst_fifo_addr_d0(GMEM_ADDR_W-1 downto CACHE_N_BANKS_W+2) = std_logic_vector(cache_rdAddr) and cache_rdAck = '1' then din_rqst_fifo_addr_d0_v <= (others=>'0'); -- report "clean happened"; end if; if nrst = '0' then fifo_wrAddr <= (others=>'0'); fifo_rdAddr <= (others=>'0'); fifo_full <= '0'; gmem_valid_i <= '0'; else if push_d0 = '1' then fifo_wrAddr <= fifo_wrAddr +1; end if; if (pop = '1' or gmem_valid_vec(gmem_valid_vec'high downto 0) /= (0 to gmem_valid_vec'high =>'1')) and gmem_valid_i = '1' then fifo_rdAddr <= fifo_rdAddr + 1; end if; if push_d0 = '0' and (pop = '1' or gmem_valid_vec(gmem_valid_vec'high downto 0) /= (0 to gmem_valid_vec'high =>'1')) then if fifo_rdAddr = fifo_wrAddr+2 then fifo_full <= '0'; end if; if fifo_rdAddr+1 = fifo_wrAddr then gmem_valid_i <= '0'; end if; end if; if push_d0 = '1' then gmem_valid_i <= '1'; if fifo_rdAddr = fifo_wrAddr+3 and (pop = '0' and gmem_valid_vec(gmem_valid_vec'high downto 0) = (0 to gmem_valid_vec'high =>'1')) then -- 2 because of extra clock delay (push -> push_d0) fifo_full <= '1'; end if; end if; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} process(clk) begin if rising_edge(clk) then push <= push_rqst_fifo_n; station_slctd_indx <= station_slctd_indx_n; end if; end process; process(station_get_ticket, fifo_full) variable station : natural range 0 to N_STATIONS-1 := 0; begin ticket_granted <= (others=>'0'); push_rqst_fifo_n <= '0'; station_slctd_indx_n <= 0; -- grant ticket if fifo_full = '0' then for i in 0 to N_STATIONS-1 loop station := c_stations_ordered_for_priority(i); -- station := i; if station_get_ticket(station) = '1' then push_rqst_fifo_n <= '1'; station_slctd_indx_n <= station; ticket_granted(station) <= '1'; exit; end if; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- stations FSMs -------------------------------------------------------------------------------------------{{{ tras_stations: process(clk) -- {{{ begin if rising_edge(clk) then station_free <= station_free_n; rd_fifo_data_d0 <= rd_fifo_data; station_gmem_addr <= station_gmem_addr_n; station_rd_addr <= station_rd_addr_n; station_wf_indx <= station_wf_indx_n; station_rnw <= station_rnw_n; if ATOMIC_IMPLEMENT /= 0 then station_atomic <= station_atomic_n; end if; station_rdData <= station_rdData_n; station_wrData <= station_wrData_n; station_op_type <= station_op_type_n; if nrst = '0' then st_stations <= (others=>idle); station_get_ticket <= (others=>'0'); station_perfomed <= (others=>'0'); if ATOMIC_IMPLEMENT /= 0 then station_wait_atomic <= (others=>'0'); end if; else st_stations <= st_stations_n; station_get_ticket <= station_get_ticket_n; station_perfomed <= station_perfomed_n; if ATOMIC_IMPLEMENT /= 0 then station_wait_atomic <= station_wait_atomic_n; end if; end if; end if; end process; -- }}} stations_read_performed: process(station_gmem_addr, rd_fifo_addr, rd_fifo_v) -- {{{ begin station_read_performed_n <= (others=>'0'); for i in 0 to N_STATIONS-1 loop if station_gmem_addr(i)(GMEM_ADDR_W-1 downto 2+RD_CACHE_N_WORDS_W) = rd_fifo_addr and rd_fifo_v = '1' then station_read_performed_n(i) <= '1'; end if; end loop; end process; -- }}} process(clk) begin if rising_edge(clk) then if ATOMIC_IMPLEMENT /= 0 then atomic_rdData_v_d0 <= atomic_rdData_v; atomic_rdData_v_d1 <= atomic_rdData_v_d0; atomic_sgntr_d0 <= atomic_sgntr; atomic_rdData_d0 <= atomic_rdData; atomic_rdData_d1 <= atomic_rdData_d0; station_atomic_perormed <= (others=>'0'); for i in 0 to N_STATIONS-1 loop -- if station_gmem_addr(i)(GMEM_ADDR_W-1 downto 2) = atomic_rdAddr_d0 and atomic_rdData_v_d0 = '1' and -- station_op_type(i) = atomic_rdData_type_d0 and station_wait_atomic(i) = '1' and -- (station_last_atomic_serve /= i or atomic_rdData_v_d1 = '0')then -- station_last_atomic_serve <= i; if unsigned(atomic_sgntr_d0) = to_unsigned(i, N_CU_STATIONS_W) and atomic_rdData_v_d0 = '1' and station_wait_atomic(i) = '1' then station_atomic_perormed(i) <= '1'; end if; end loop; end if; end if; end process; process(st_stations, station_free, station_go, station_gmem_addr, station_rd_addr, station_rnw, mem_rqsts_wf_indx_ltchd, station_get_ticket, station_op_type, ticket_granted, station_perfomed, station_written_back, station_wrData, station_rdData, rd_fifo_data_d0, station_read_performed_n, latch_rdData, station_atomic, station_wait_atomic, station_atomic_perormed, atomic_rdData_d1, mem_rqsts_rdData_ltchd, station_wf_indx) variable rdIndx : integer range 0 to CACHE_N_BANKS-1 := 0; begin for i in 0 to N_STATIONS-1 loop station_rnw_n(i) <= station_rnw(i); if ATOMIC_IMPLEMENT /= 0 then station_atomic_n(i) <= station_atomic(i); station_wait_atomic_n(i) <= station_wait_atomic(i); end if; station_rd_addr_n(i) <= station_rd_addr(i); station_gmem_addr_n(i) <= station_gmem_addr(i); station_free_n(i) <= station_free(i); st_stations_n(i) <= st_stations(i); station_get_ticket_n(i) <= station_get_ticket(i); station_rdData_n(i) <= station_rdData(i); station_perfomed_n(i) <= station_perfomed(i); station_wrData_n(i) <= station_wrData(i); station_op_type_n(i) <= station_op_type(i); latch_rdData_n(i) <= '0'; station_wf_indx_n(i) <= station_wf_indx(i); case st_stations(i) is when idle => -- {{{ station_free_n(i) <= '1'; station_wf_indx_n(i) <= mem_rqsts_wf_indx_ltchd; if station_go(i) = '1' then st_stations_n(i) <= get_ticket; station_get_ticket_n(i) <= '1'; station_free_n(i) <= '0'; station_gmem_addr_n(i) <= unsigned(mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_ADDR_HIGH downto MEM_RQST_ADDR_LOW)); station_rd_addr_n(i) <= unsigned(mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_RD_ADDR_HIGH downto MEM_RQST_RD_ADDR_LOW)); station_rnw_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_RE_POS); if ATOMIC_IMPLEMENT /= 0 then station_atomic_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_ATOMIC_POS); end if; station_wrData_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_DATA_HIGH downto MEM_RQST_DATA_LOW); station_op_type_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_OP_TYPE_HIGH downto MEM_RQST_OP_TYPE_LOW); end if; -- }}} when get_ticket => -- {{{ -- assert (station_gmem_addr(i)(17 downto 2) = unsigned(station_wrData(i)(15 downto 0))) or station_rnw(i) = '1' -- report integer'image(to_integer(station_gmem_addr(i)(GMEM_ADDR_W-1 downto 2))) & ", data = " & -- integer'image(to_integer(unsigned(station_wrData(i)))) severity failure; if station_rnw(i) = '1' and station_read_performed_n(i) = '1' then station_get_ticket_n(i) <= '0'; station_perfomed_n(i) <= '1'; st_stations_n(i) <= write_back; latch_rdData_n(i) <= '1'; station_get_ticket_n(i) <= '0'; elsif ticket_granted(i) = '1' then if station_rnw(i) = '1' then st_stations_n(i) <= wait_read_done; elsif ATOMIC_IMPLEMENT /= 0 and station_atomic(i) = '1' then st_stations_n(i) <= wait_atomic; station_wait_atomic_n(i) <= '1'; else st_stations_n(i) <= idle; station_free_n(i) <= '1'; end if; station_get_ticket_n(i) <= '0'; end if; -- }}} when wait_atomic => -- {{{ if ATOMIC_IMPLEMENT /= 0 then station_rdData_n(i) <= atomic_rdData_d1; if station_atomic_perormed(i) = '1' then st_stations_n(i) <= write_back; station_perfomed_n(i) <= '1'; station_wait_atomic_n(i) <= '0'; end if; end if; -- }}} when wait_read_done => -- {{{ if station_read_performed_n(i) = '1' then latch_rdData_n(i) <= '1'; st_stations_n(i) <= write_back; station_perfomed_n(i) <= '1'; end if; -- }}} when write_back => -- {{{ if latch_rdData(i) = '1' then if RD_CACHE_N_WORDS_W /= 0 then rdIndx := to_integer(station_gmem_addr(i)(max(RD_CACHE_N_WORDS_W,1)+2-1 downto 2)); else rdIndx := 0; end if; station_rdData_n(i) <= rd_fifo_data_d0((rdIndx+1)*DATA_W-1 downto rdIndx*DATA_W); end if; if station_written_back(i) = '1' then st_stations_n(i) <= idle; station_free_n(i) <= '1'; station_perfomed_n(i) <= '0'; end if; -- }}} end case; end loop; end process; ---------------------------------------------------------------------------------------------------------}}} -- regFile interface ---------------------------------------------------------------------------------------{{{ -- regFile comb process ---------------------------------------------------------------------------------{{{ process(st_regFile_int, station_perfomed, regFile_wrAddr_p0, station_rd_addr, station_written_back, cv_lmem_rqst) begin st_regFile_int_n <= st_regFile_int; regFile_wrAddr_p0_n <= regFile_wrAddr_p0; regFile_we_p0_n <= (others=>'0'); station_written_back_n <= (others=>'0'); regFile_we_latch_p0_n <= '0'; case st_regFile_int is when choose_rd_addr => for i in N_STATIONS-1 downto 0 loop if station_perfomed(i) = '1' and station_written_back(i) = '0' then regFile_wrAddr_p0_n <= station_rd_addr(i); st_regFile_int_n <= update; end if; end loop; if LMEM_IMPLEMENT /= 0 and cv_lmem_rqst = '1' then st_regFile_int_n <= wait_scratchpad; end if; when update => st_regFile_int_n <= wait_1_cycle; if LMEM_IMPLEMENT /= 0 and cv_lmem_rqst = '1' then st_regFile_int_n <= wait_scratchpad; else for i in 0 to CV_SIZE-1 loop for j in N_STATIONS_ALU-1 downto 0 loop if station_perfomed(i*N_STATIONS_ALU+j) = '1' and station_rd_addr(i*N_STATIONS_ALU+j) = regFile_wrAddr_p0 then regFile_we_p0_n(i) <= '1'; station_written_back_n(i*N_STATIONS_ALU+j) <= '1'; regFile_we_latch_p0_n <= '1'; end if; end loop; end loop; end if; when wait_1_cycle => st_regFile_int_n <= choose_rd_addr; when wait_scratchpad => if LMEM_IMPLEMENT /= 0 and cv_lmem_rqst = '0' then st_regFile_int_n <= choose_rd_addr; end if; end case; end process; ---------------------------------------------------------------------------------------------------------}}} -- regFile trans process --------------------------------------------------------------------------------{{{ regFile_we_lmem_p0 <= lmem_rdData_v; -- @ level 19. regFile_side_trans: process(clk) begin if rising_edge(clk) then regFile_we_p0 <= regFile_we_p0_n; latch_rdData <= latch_rdData_n; station_written_back <= station_written_back_n; regFile_we_latch_p0 <= regFile_we_latch_p0_n; regFile_we_latch <= regFile_we_latch_p0; regFile_wrAddr_i <= regFile_wrAddr_p0; if regFile_we_latch = '0' then regFile_we <= regFile_we_p0; end if; regFile_wrAddr_p0 <= regFile_wrAddr_p0_n; lmem_rdData_d0 <= lmem_rdData; -- @ 20. if LMEM_IMPLEMENT /= 0 and lmem_rdData_v = '1' then -- level 19. regFile_we <= lmem_rdData_alu_en; -- @ 20. regFile_wrAddr_i <= lmem_rdData_rd_addr; -- @ 20. end if; if LMEM_IMPLEMENT /= 0 and regFile_we_latch = '0' then regFile_wrData <= lmem_rdData; -- @ 20. end if; for i in 0 to CV_SIZE-1 loop for j in N_STATIONS_ALU-1 downto 0 loop if station_written_back(i*N_STATIONS_ALU+j) = '1' then regFile_wrData(i) <= station_rdData(i*N_STATIONS_ALU+j); end if; end loop; end loop; if nrst = '0' then st_regFile_int <= choose_rd_addr; else st_regFile_int <= st_regFile_int_n; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -----------------------------------------------------------------------------------}}} -- gmem finished -------------------------------------------------------{{{ process(clk) variable wf_busy_indices : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); begin if rising_edge(clk) then wf_finish <= wf_finish_n; if nrst = '0' then st_finish <= (others=>idle); else st_finish <= st_finish_n; end if; wf_busy_indices := (others=>'0'); for i in 0 to N_STATIONS-1 loop if station_free(i) = '0' then wf_busy_indices := wf_busy_indices or station_wf_indx(i); end if; end loop; wfs_being_served <= wf_busy_indices; end if; end process; st_finish_array: for i in 0 to N_WF_CU-1 generate begin process(st_finish(i), check_finish(i), wfs_being_served(i)) begin st_finish_n(i) <= st_finish(i); wf_finish_n(i) <= '0'; case st_finish(i) is when idle => if check_finish(i) = '1' then st_finish_n(i) <= serving; end if; when serving => if wfs_being_served(i) = '0' then st_finish_n(i) <= finished; end if; when finished => wf_finish_n(i) <= '1'; st_finish_n(i) <= idle; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- controller idle -------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then cntrl_idle_i <= '0'; if station_free = (station_free'reverse_range=>'1') and gmem_valid_i = '0' and st_cv_side = get_rqst then cntrl_idle_i <= '1'; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- cache read fifo -------------------------------------------------------------------------------------------{{{ -- cu_mem_cntrl <- port A (myram) port B -> cache cache_rd_buffer_inst: entity rd_cache_fifo generic map ( SIZEA => 2**(RD_CACHE_FIFO_PORTB_ADDR_W+CACHE_N_BANKS_W-RD_CACHE_N_WORDS_W), ADDRWIDTHA => RD_CACHE_FIFO_PORTB_ADDR_W+CACHE_N_BANKS_W-RD_CACHE_N_WORDS_W, SIZEB => 2**RD_CACHE_FIFO_PORTB_ADDR_W, ADDRWIDTHB => RD_CACHE_FIFO_PORTB_ADDR_W ) port map( clk => clk, push => cache_rdAck, cache_rdData => cache_rdData, cache_rdAddr => cache_rdAddr, rdData => rd_fifo_data, rdAddr => rd_fifo_addr, nempty => rd_fifo_v, nrst => nrst ); ---------------------------------------------------------------------------------------------------------}}} -- lmem -------------------------------------------------------------------------------------------------{{{ local_memory_inst: if LMEM_IMPLEMENT /= 0 generate begin sp <= cv_addr(cv_alu_en_pri_enc)(LMEM_ADDR_W-N_WF_CU_W-PHASE_W-1 downto 0); local_memory: entity lmem port map( clk => clk, rqst => cv_lmem_rqst, -- level 17. we => cv_lmem_we, alu_en => cv_alu_en, wrData => cv_wrData, rdData => lmem_rdData, -- level 19. rdData_rd_addr => lmem_rdData_rd_addr, -- level 19. rdData_v => lmem_rdData_v, -- level 19. rdData_alu_en => lmem_rdData_alu_en, -- level 19. -- connect all of cv_addr; you have 8 SPs!! sp => sp, rd_addr => cv_rd_addr, nrst => nrst ); end generate; ---------------------------------------------------------------------------------------------------------}}} end architecture;

gpl-3.0

3f09e7127002a8ea848484ea81a4f72d

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_no_fdiv_area_estimation.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

a44de22ad437649e4d322fd01f514bd2

joalcava/sparcv8-monocicle

register_file.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity register_file is Port( Wren : in STD_LOGIC; rst : in STD_LOGIC; rs1 : in STD_LOGIC_VECTOR (5 downto 0); rs2 : in STD_LOGIC_VECTOR (5 downto 0); rd : in STD_LOGIC_VECTOR (5 downto 0); data : in STD_LOGIC_VECTOR (31 downto 0); crs1 : out STD_LOGIC_VECTOR (31 downto 0); crs2 : out STD_LOGIC_VECTOR (31 downto 0); crd : out STD_LOGIC_VECTOR (31 downto 0) ); end register_file; architecture ArqRegFile of register_file is type ram_type is array (0 to 39) of std_logic_vector (31 downto 0); signal reg : ram_type := (others => x"00000000"); begin process(rst, rs1, rs2, rd,data) begin if (rst = '0') then crs1 <= reg(conv_integer(rs1 )); crs2 <= reg(conv_integer(rs2 )); crd <= reg(conv_integer(rd )); if(rd /= "00000" and Wren ='1') then reg(conv_integer(rd)) <= data; end if; elsif (rst='1') then crs1 <= x"00000000"; crs2 <= x"00000000"; reg <= (others => x"00000000"); end if; end process; end ArqRegFile;

gpl-3.0

74c45b379c857e7e31b66915f8c49de0

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_model_constr_decoder.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_model_constr_decoder | -- | --------------------------------------------------------------------------------------------------- -- File wf_model_constr_decoder.vhd | -- | -- Description Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID. | -- The output S_ID0 is a clock with period the double of uclk's period and the S_ID1 | -- is the opposite clock (it is '0' when S_ID0 is '1' and '1' when S_ID0 is '0'). | -- Each one of the 4 pins of the M_ID and C_ID can be connected to either Vcc, Gnd, | -- S_ID1 or S_ID0. Like this (after 2 uclk periods) the 8 bits of the Model and | -- Constructor words take a value, according to the table: Gnd 00 | -- S_ID0 01 | -- S_ID1 10 | -- Vcc 11 | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 21/01/2011 | -- Version v0.03 | -- Depends on wf_reset_unit | ---------------- | -- Last changes | -- 11/09/2009 v0.01 PAS First version | -- 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1 | -- "for" loop replaced with signals concatenation; | -- Counter is of c_RELOAD_MID_CID bits; Code cleaned-up | -- 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed; | -- counter unit instantiated | -- 01/2011 v0.031 EG loading aftern the 2nd cycle (no need for 3) | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_model_constr_decoder --================================================================================================= entity wf_model_constr_decoder is port( -- INPUTS -- nanoFIP User Interface general signal uclk_i : in std_logic; -- 40 Mhz clock -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- nanoFIP WorldFIP Settings (synchronised with uclk_i) constr_id_i : in std_logic_vector (3 downto 0); -- Constructor identification settings model_id_i : in std_logic_vector (3 downto 0); -- Model identification settings -- OUTPUTS -- nanoFIP WorldFIP Settings output -- MODIFIED -- s_id_o : out std_logic_vector (1 downto 0); -- Identification selection -- Signal to the wf_prod_bytes_retriever unit constr_id_dec_o : out std_logic_vector (7 downto 0); -- Constructor identification decoded model_id_dec_o : out std_logic_vector (7 downto 0));-- Model identification decoded end entity wf_model_constr_decoder; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_model_constr_decoder is signal s_counter : unsigned (1 downto 0); signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0); signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Synchronous process Model_Constructor_Decoder: -- For M_ID and C_ID to be loaded, 2 uclk periods are needed: on the first uclk tick, the values -- of all the odd bits of M_ID & C_ID are loaded on the registers s_model_stage1/ s_constr_stage1 -- and on the second uclk tick, the values of the odd bits move to the registers s_model_stage2/ -- s_constr_stage2, giving place to all the even bits to be loaded to the s_model_stage1/ -- s_constr_stage1. The loaded odd and even values are combined after the 2 periods to give the -- decoded outputs model_id_dec_o & constr_id_dec_o. Model_Constructor_Decoder: process (uclk_i) begin if rising_edge (uclk_i) then -- initializations if nfip_rst_i = '1' then model_id_dec_o <= (others => '0'); constr_id_dec_o <= (others => '0'); s_model_stage1 <= (others => '0'); s_model_stage2 <= (others => '0'); s_constr_stage1 <= (others => '0'); s_constr_stage2 <= (others => '0'); else s_model_stage2 <= s_model_stage1; -- after 2 uclk ticks stage1 keeps the even bits s_model_stage1 <= model_id_i; -- and stage2 the odd ones s_constr_stage2 <= s_constr_stage1; s_constr_stage1 <= constr_id_i; -- same for the constructor if s_counter = "10" then model_id_dec_o <= s_model_stage2(3) & s_model_stage1(3) & -- putting together s_model_stage2(2) & s_model_stage1(2) & -- even and odd bits s_model_stage2(1) & s_model_stage1(1) & s_model_stage2(0) & s_model_stage1(0); constr_id_dec_o <= s_constr_stage2(3) & s_constr_stage1(3) & s_constr_stage2(2) & s_constr_stage1(2) & s_constr_stage2(1) & s_constr_stage1(1) & s_constr_stage2(0) & s_constr_stage1(0); end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Instantiation of a counter wf_incr_counter Free_Counter: wf_incr_counter generic map(g_counter_lgth => 2) port map( uclk_i => uclk_i, counter_reinit_i => nfip_rst_i, counter_incr_i => '1', counter_is_full_o => open, ----------------------------------------- counter_o => s_counter); ----------------------------------------- --------------------------------------------------------------------------------------------------- -- Concurrent signal assignment for the output s_id_o -- MODIFIED -- s_id_o <= ((not s_counter(0)) & s_counter(0)); -- 2 opposite clocks generated using -- the LSB of the counter -- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_ -- S_ID0 : |----|____|----|____|----|___ -- S_ID1 : |____|----|____|----|____|--- end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

25bb6c227d5d2268b8dfb7865b703268

malkadi/FGPU

RTL/gmem_atomics.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity gmem_atomics is port( -- {{{ rcv_atomic_type : in be_array(N_RECEIVERS-1 downto 0); rcv_atomic_rqst : in std_logic_vector(N_RECEIVERS-1 downto 0); rcv_gmem_addr : in gmem_word_addr_array(N_RECEIVERS-1 downto 0); rcv_gmem_data : in SLV32_ARRAY(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); rcv_must_read : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_atomic_ack : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); -- read data path (in) gmem_rdAddr_p0 : in unsigned(GMEM_WORD_ADDR_W-N-1 downto 0); gmem_rdData : in std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0); gmem_rdData_v_p0 : in std_logic := '0'; -- atomic data path (out) atomic_rdData : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); rcv_retire : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); -- this signals implies the validety of atomic_rdData -- it is 2 clock cycles in advance -- atomic flushing flush_v : out std_logic := '0'; flush_gmem_addr : out unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); flush_data : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); flush_ack : in std_logic; flush_done : in std_logic; finish : in std_logic; atomic_can_finish : out std_logic := '0'; WGsDispatched : in std_logic; clk, nrst : std_logic ); -- }}} end entity; architecture basic of gmem_atomics is -- general control signals {{{ signal rcv_slctd_indx : integer range 0 to N_RECEIVERS := 0; attribute max_fanout of rcv_slctd_indx : signal is 60; signal rcv_slctd_indx_d0 : integer range 0 to N_RECEIVERS := 0; attribute max_fanout of rcv_slctd_indx_d0 : signal is 40; signal check_rqst, check_rqst_d0 : std_logic := '0'; signal rqst_type : std_logic_vector(2 downto 0) := (others=>'0'); attribute max_fanout of rqst_type : signal is 60; signal rqst_val : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal rqst_gmem_addr : unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); type atomic_unit_state is (idle, listening, latch_gmem_data, select_word, functioning); signal rcv_half_select : std_logic := '0'; signal rcv_is_reading : std_logic := '0'; -- }}} -- atomic max signals -----------------------------------------------------------------------------------{{{ signal st_amax, st_amax_n : atomic_unit_state := idle; signal amax_gmem_addr, amax_gmem_addr_n : unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); signal amax_data, amax_data_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal amax_data_d0 : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal amax_addr_v, amax_addr_v_n : std_logic := '0'; signal amax_addr_v_d0 : std_logic := '0'; signal amax_exec, amax_exec_d0 : std_logic := '0'; signal amax_latch_gmem_rdData : std_logic := '0'; signal amax_latch_gmem_rdData_n : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} -- atomic add signals -----------------------------------------------------------------------------------{{{ signal st_aadd, st_aadd_n : atomic_unit_state := idle; signal aadd_gmem_addr, aadd_gmem_addr_n : unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); signal aadd_data, aadd_data_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal aadd_data_d0 : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal gmem_rdData_ltchd : std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0); signal aadd_latch_gmem_rdData : std_logic := '0'; signal aadd_latch_gmem_rdData_n : std_logic := '0'; signal aadd_addr_v, aadd_addr_v_n : std_logic := '0'; signal aadd_addr_v_d0 : std_logic := '0'; signal aadd_exec, aadd_exec_d0 : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} -- flushing aadd results --------------------------------------------------------------------------------{{{ type flush_state_type is (idle, dirty, flushing, wait_flush_done); signal st_aadd_flush, st_aadd_flush_n : flush_state_type := idle; constant FLUSH_TIMER_W : integer := 3; signal aadd_flush_timer : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0'); signal aadd_flush_timer_n : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0'); signal aadd_flush_rqst : std_logic := '0'; signal aadd_flush_rqst_n : std_logic := '0'; signal aadd_flush_started : std_logic := '0'; signal aadd_flush_done : std_logic := '0'; signal flush_ack_d0 : std_logic := '0'; signal aadd_dirty_content : std_logic := '0'; signal aadd_dirty_content_n : std_logic := '0'; signal WGsDispatched_ltchd : std_logic := '0'; signal aadd_flush_active : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} -- flushing amax results --------------------------------------------------------------------------------{{{ signal st_amax_flush, st_amax_flush_n : flush_state_type := idle; signal amax_flush_timer : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0'); signal amax_flush_timer_n : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0'); signal amax_flush_rqst : std_logic := '0'; signal amax_flush_rqst_n : std_logic := '0'; signal amax_flush_started : std_logic := '0'; signal amax_flush_done : std_logic := '0'; signal amax_dirty_content : std_logic := '0'; signal amax_dirty_content_n : std_logic := '0'; signal amax_flush_active : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} begin -- TODO: implement atomic address changing. Now only one address can be used by an atomic unit -- TODO: consider the case when two atomic units work on the same global address -- asserts & internals ----------------------------------------------------------------------------------{{{ assert FLUSH_TIMER_W < 4 report "make FLUSH_TIMER_W less than 4 otherwise FGPU will finish while there is dirty data in the atomic units"; ---------------------------------------------------------------------------------------------------------}}} -- receivers interface ----------------------------------------------------------------------------------{{{ RCV_INTERFACE: if AADD_ATOMIC = 1 or AMAX_ATOMIC = 1 generate process(clk) variable rcv_slctd_indx_unsigned : unsigned(N_RECEIVERS_W-1 downto 0) := (others=>'0'); begin if rising_edge(clk) then rcv_half_select <= not rcv_half_select; -- stage 0: -- select requesting receiver check_rqst <= '0'; rcv_atomic_ack <= (others=>'0'); for i in N_RECEIVERS/2-1 downto 0 loop rcv_slctd_indx_unsigned(N_RECEIVERS_W-1 downto 1) := to_unsigned(i, N_RECEIVERS_W-1); rcv_slctd_indx_unsigned(0) := rcv_half_select; if rcv_atomic_rqst(to_integer(rcv_slctd_indx_unsigned)) = '1' then rcv_slctd_indx <= to_integer(rcv_slctd_indx_unsigned); rcv_atomic_ack(to_integer(rcv_slctd_indx_unsigned)) <= '1'; -- assert(rcv_atomic_type(i) = CODE_AADD(2 downto 0)); check_rqst <= '1'; exit; end if; end loop; -- stage 1: -- latch request rqst_type <= rcv_atomic_type(rcv_slctd_indx)(2 downto 0); rqst_gmem_addr <= rcv_gmem_addr(rcv_slctd_indx); check_rqst_d0 <= check_rqst; rcv_slctd_indx_d0 <= rcv_slctd_indx; -- stage 2: -- check validety rcv_must_read <= (others=>'0'); rcv_retire <= (others=>'0'); aadd_exec <= '0'; amax_exec <= '0'; if check_rqst_d0 = '1' then case rqst_type is when CODE_AADD(2 downto 0) => if aadd_addr_v = '0' or aadd_gmem_addr /= rqst_gmem_addr then if rcv_is_reading = '0' then rcv_must_read(rcv_slctd_indx_d0) <= '1'; rcv_is_reading <= '1'; end if; else rcv_retire(rcv_slctd_indx_d0) <= '1'; aadd_exec <= '1'; end if; when CODE_AMAX(2 downto 0) => if amax_addr_v = '0' or amax_gmem_addr /= rqst_gmem_addr then if rcv_is_reading = '0' then rcv_must_read(rcv_slctd_indx_d0) <= '1'; rcv_is_reading <= '1'; end if; else rcv_retire(rcv_slctd_indx_d0) <= '1'; amax_exec <= '1'; end if; when others => assert(false); end case; end if; rqst_val <= unsigned(rcv_gmem_data(rcv_slctd_indx_d0)); -- stage3: -- wait for result aadd_exec_d0 <= aadd_exec; amax_exec_d0 <= amax_exec; --stage 4: -- forward result if aadd_exec_d0 = '1' then atomic_rdData <= std_logic_vector(aadd_data_d0); -- if _d0 is removed then the atomic will giv back the new result instead of the old one else -- if amax_exec_d0 = '1' atomic_rdData <= std_logic_vector(amax_data_d0); end if; -- atomic_rdAddr <= aadd_gmem_addr; -- no need for the performed atomic address; it is included in the signature -- atomic_rdData_type <= CODE_AADD(2 downto 0); -- no need to send the atomic type back; it is included in the signature -- other tasks if (aadd_addr_v = '1' and aadd_addr_v_d0 = '0') or (amax_addr_v = '1' and amax_addr_v_d0 = '0') then rcv_is_reading <= '0'; end if; if aadd_latch_gmem_rdData = '1' or amax_latch_gmem_rdData = '1' then gmem_rdData_ltchd <= gmem_rdData; end if; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- flushing amax ----------------------------------------------------------------------------------------{{{ AMAX_FLUSHING: if AMAX_ATOMIC = 1 generate process(clk) begin if rising_edge(clk) then if nrst = '0' then st_amax_flush <= idle; amax_flush_rqst <= '0'; amax_dirty_content <= '0'; else st_amax_flush <= st_amax_flush_n; amax_flush_rqst <= amax_flush_rqst_n; amax_dirty_content <= amax_dirty_content_n; end if; amax_flush_timer <= amax_flush_timer_n; end if; end process; process(st_amax_flush, amax_exec, amax_flush_timer, amax_flush_rqst, amax_flush_started, flush_done, amax_dirty_content, WGsDispatched_ltchd) begin st_amax_flush_n <= st_amax_flush; amax_flush_timer_n <= amax_flush_timer; amax_flush_rqst_n <= amax_flush_rqst; amax_dirty_content_n <= amax_dirty_content; case st_amax_flush is when idle => amax_flush_timer_n <= (others=>'0'); if amax_exec = '1' or amax_dirty_content = '1' then st_amax_flush_n <= dirty; end if; when dirty => if WGsDispatched_ltchd = '1' then amax_flush_timer_n <= amax_flush_timer + 1; if amax_exec = '1' then amax_flush_timer_n <= (others=>'0'); elsif amax_flush_timer = (amax_flush_timer'reverse_range =>'1') then st_amax_flush_n <= flushing; amax_flush_rqst_n <= '1'; amax_dirty_content_n <= '0'; end if; end if; when flushing => if amax_exec = '1' then amax_dirty_content_n <= '1'; end if; if amax_flush_started = '1' then st_amax_flush_n <= wait_flush_done; amax_flush_rqst_n <= '0'; end if; when wait_flush_done => if flush_done = '1' then st_amax_flush_n <= idle; end if; if amax_exec = '1' then amax_dirty_content_n <= '1'; end if; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- flushing aadd ----------------------------------------------------------------------------------------{{{ AADD_FLUSH: if AADD_ATOMIC = 1 generate process(clk) begin if rising_edge(clk) then if nrst = '0' then st_aadd_flush <= idle; aadd_flush_rqst <= '0'; aadd_dirty_content <= '0'; else st_aadd_flush <= st_aadd_flush_n; aadd_flush_rqst <= aadd_flush_rqst_n; aadd_dirty_content <= aadd_dirty_content_n; end if; aadd_flush_timer <= aadd_flush_timer_n; end if; end process; process(st_aadd_flush, aadd_exec, aadd_flush_timer, aadd_flush_rqst, aadd_flush_started, flush_done, aadd_dirty_content, WGsDispatched_ltchd) begin st_aadd_flush_n <= st_aadd_flush; aadd_flush_timer_n <= aadd_flush_timer; aadd_flush_rqst_n <= aadd_flush_rqst; aadd_dirty_content_n <= aadd_dirty_content; case st_aadd_flush is when idle => aadd_flush_timer_n <= (others=>'0'); if aadd_exec = '1' or aadd_dirty_content = '1' then st_aadd_flush_n <= dirty; end if; when dirty => if WGsDispatched_ltchd = '1' then aadd_flush_timer_n <= aadd_flush_timer + 1; if aadd_exec = '1' then aadd_flush_timer_n <= (others=>'0'); elsif aadd_flush_timer = (aadd_flush_timer'reverse_range =>'1') then st_aadd_flush_n <= flushing; aadd_flush_rqst_n <= '1'; aadd_dirty_content_n <= '0'; end if; end if; when flushing => if aadd_exec = '1' then aadd_dirty_content_n <= '1'; end if; if aadd_flush_started = '1' then st_aadd_flush_n <= wait_flush_done; aadd_flush_rqst_n <= '0'; end if; when wait_flush_done => if flush_done = '1' then st_aadd_flush_n <= idle; end if; if aadd_exec = '1' then aadd_dirty_content_n <= '1'; end if; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- atomic max -------------------------------------------------------------------------------------------{{{ AMAX_BODY: if AMAX_ATOMIC = 1 generate process(clk) begin if rising_edge(clk) then if nrst = '0' then amax_addr_v <= '0'; st_amax <= idle; else st_amax <= st_amax_n; amax_addr_v <= amax_addr_v_n; end if; amax_addr_v_d0 <= amax_addr_v; amax_gmem_addr <= amax_gmem_addr_n; amax_data <= amax_data_n; amax_data_d0 <= amax_data; amax_latch_gmem_rdData <= amax_latch_gmem_rdData_n; end if; end process; process(st_amax, check_rqst_d0, rqst_type, amax_gmem_addr, rqst_gmem_addr, gmem_rdData_v_p0, gmem_rdAddr_p0, amax_data, gmem_rdData_ltchd, amax_addr_v, amax_exec, rqst_val, finish) variable word_indx : integer range 0 to GMEM_N_BANK-1 := 0; -- variable n_amax_exec : integer := 0; -- variable written_vals : std_logic_vector(2047 downto 0) := (others=>'0'); -- variable written_index : integer range 0 to 2047 := 0; begin st_amax_n <= st_amax; amax_gmem_addr_n <= amax_gmem_addr; amax_data_n <= amax_data; amax_addr_v_n <= amax_addr_v; amax_latch_gmem_rdData_n <= '0'; case st_amax is when idle => if check_rqst_d0 = '1' and rqst_type = CODE_AMAX(2 downto 0) then st_amax_n <= listening; amax_gmem_addr_n <= rqst_gmem_addr; end if; when listening => if gmem_rdData_v_p0 = '1' and gmem_rdAddr_p0 = amax_gmem_addr(amax_gmem_addr'high downto N) then st_amax_n <= latch_gmem_data; amax_latch_gmem_rdData_n <= '1'; end if; when latch_gmem_data => st_amax_n <= select_word; when select_word => word_indx := to_integer(amax_gmem_addr(N-1 downto 0)); amax_data_n <= unsigned(gmem_rdData_ltchd(DATA_W*(word_indx+1)-1 downto DATA_W*word_indx)); st_amax_n <= functioning; amax_addr_v_n <= '1'; when functioning => if amax_exec = '1' then -- n_amax_exec := n_amax_exec + 1; if signed(amax_data) < signed(rqst_val) then amax_data_n <= rqst_val; end if; -- written_index := ((to_integer(rqst_val)-6) / 16); -- assert written_index < 2048 severity failure; -- assert written_vals(written_index) = '0' severity failure; -- written_vals(written_index) := '1'; -- assert ((to_integer(rqst_val)-6) mod 16) = 0 severity failure; end if; if finish = '1' then -- assert written_vals = (written_vals'reverse_range=>'1') severity failure; -- written_vals := (others=>'0'); -- report "# of executed atmoic additions (counted inside the atomic unit) is " & integer'image(n_amax_exec); -- n_amax_exec := 0; st_amax_n <= idle; amax_addr_v_n <= '0'; end if; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- atomic add -------------------------------------------------------------------------------------------{{{ AADD_BODY: if AADD_ATOMIC = 1 generate process(clk) begin if rising_edge(clk) then if nrst = '0' then aadd_addr_v <= '0'; st_aadd <= idle; else st_aadd <= st_aadd_n; aadd_addr_v <= aadd_addr_v_n; end if; aadd_addr_v_d0 <= aadd_addr_v; aadd_gmem_addr <= aadd_gmem_addr_n; aadd_data <= aadd_data_n; aadd_data_d0 <= aadd_data; aadd_latch_gmem_rdData <= aadd_latch_gmem_rdData_n; end if; end process; process(st_aadd, check_rqst_d0, rqst_type, aadd_gmem_addr, rqst_gmem_addr, gmem_rdData_v_p0, gmem_rdAddr_p0, aadd_data, gmem_rdData_ltchd, aadd_addr_v, aadd_exec, rqst_val, finish) variable word_indx : integer range 0 to GMEM_N_BANK-1 := 0; -- variable n_aadd_exec : integer := 0; -- variable written_vals : std_logic_vector(2047 downto 0) := (others=>'0'); -- variable written_index : integer range 0 to 2047 := 0; begin st_aadd_n <= st_aadd; aadd_gmem_addr_n <= aadd_gmem_addr; aadd_data_n <= aadd_data; aadd_addr_v_n <= aadd_addr_v; aadd_latch_gmem_rdData_n <= '0'; case st_aadd is when idle => if check_rqst_d0 = '1' and rqst_type = CODE_AADD(2 downto 0) then st_aadd_n <= listening; aadd_gmem_addr_n <= rqst_gmem_addr; end if; when listening => if gmem_rdData_v_p0 = '1' and gmem_rdAddr_p0 = aadd_gmem_addr(aadd_gmem_addr'high downto N) then st_aadd_n <= latch_gmem_data; aadd_latch_gmem_rdData_n <= '1'; end if; when latch_gmem_data => st_aadd_n <= select_word; when select_word => word_indx := to_integer(aadd_gmem_addr(N-1 downto 0)); aadd_data_n <= unsigned(gmem_rdData_ltchd(DATA_W*(word_indx+1)-1 downto DATA_W*word_indx)); st_aadd_n <= functioning; aadd_addr_v_n <= '1'; when functioning => if aadd_exec = '1' then -- n_aadd_exec := n_aadd_exec + 1; aadd_data_n <= aadd_data + rqst_val; -- written_index := ((to_integer(rqst_val)-6) / 16); -- assert written_index < 2048 severity failure; -- assert written_vals(written_index) = '0' severity failure; -- written_vals(written_index) := '1'; -- assert ((to_integer(rqst_val)-6) mod 16) = 0 severity failure; end if; if finish = '1' then -- assert written_vals = (written_vals'reverse_range=>'1') severity failure; -- written_vals := (others=>'0'); -- report "# of executed atmoic additions (counted inside the atomic unit) is " & integer'image(n_aadd_exec); -- n_aadd_exec := 0; st_aadd_n <= idle; aadd_addr_v_n <= '0'; end if; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- flushing ---------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then if nrst = '0' then WGsDispatched_ltchd <= '0'; else if finish = '1' then WGsDispatched_ltchd <= '0'; elsif WGsDispatched = '1' then WGsDispatched_ltchd <= '1'; end if; end if; atomic_can_finish <= '0'; if st_aadd_flush = idle and st_amax_flush = idle then atomic_can_finish <= '1'; end if; flush_v <= (aadd_flush_rqst or amax_flush_rqst) and not (flush_ack or flush_ack_d0); flush_ack_d0 <= flush_ack; aadd_flush_started <= '0'; amax_flush_started <= '0'; aadd_flush_active <= '0'; amax_flush_active <= '0'; if flush_ack = '0' then if aadd_flush_rqst = '1' then flush_gmem_addr <= aadd_gmem_addr; flush_data <= std_logic_vector(aadd_data); aadd_flush_active <= '1'; elsif amax_flush_rqst = '1' then flush_gmem_addr <= amax_gmem_addr; flush_data <= std_logic_vector(amax_data); amax_flush_active <= '1'; end if; else if aadd_flush_active = '1' then aadd_flush_started <= '1'; else -- amax_flush_active = '1' amax_flush_started <= '1'; end if; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} end architecture;

gpl-3.0

4bb6361250f7431a1401f035d1cc5ebe

preusser/q27

src/vhdl/PoC/fifo/fifo_glue.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- =========================================================================== -- Module: minimal FIFO, common clock (cc), -- pipelined interface, first-word-fall-through mode -- -- Authors: Thomas B. Preusser -- -- Description: -- ------------------------------------ -- Its primary use is the decoupling of enable domains in a processing -- pipeline. Data storage is limited to two words only so as to allow both -- the 'ful' and the 'vld' indicators to be driven by registers. -- -- License: -- =========================================================================== -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- =========================================================================== library IEEE; use IEEE.std_logic_1164.all; entity fifo_glue is generic ( D_BITS : positive -- Data Width ); port ( -- Control clk : in std_logic; -- Clock rst : in std_logic; -- Synchronous Reset -- Input put : in std_logic; -- Put Value di : in std_logic_vector(D_BITS-1 downto 0); -- Data Input ful : out std_logic; -- Full -- Output vld : out std_logic; -- Data Available do : out std_logic_vector(D_BITS-1 downto 0); -- Data Output got : in std_logic -- Data Consumed ); end fifo_glue; architecture rtl of fifo_glue is -- Data Buffer Registers signal A, B : std_logic_vector(D_BITS-1 downto 0); -- State Registers signal Full, Avail : std_logic := '0'; begin process(clk) begin if rising_edge(clk) then if rst = '1' then A <= (others => '-'); B <= (others => '-'); Full <= '0'; Avail <= '0'; else if Avail = '0' then if put = '1' then B <= di; Avail <= '1'; end if; elsif Full = '0' then if got = '1' then if put = '1' then B <= di; else Avail <= '0'; end if; else if put = '1' then A <= di; Full <= '1'; end if; end if; else if got = '1' then B <= A; Full <= '0'; end if; end if; end if; end if; end process; ful <= Full; vld <= Avail; do <= B; end rtl;

agpl-3.0

97c54405a3b6af4cddc41377a685fe55

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_write_wrapper.vhd

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mit

e3cdccc37a4e7b5225bcb3fe6cc14865

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_8Stations_2AXI_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

391e30b01ba5349a04808465ff7365c7

preusser/q27

src/vhdl/top/xilinx/sdrc_queens_slave.vhdl

library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity sdrc_queens_slave is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 90; COUNT_CYCLES : boolean := false; -- Local Clock Parameters CLK_FREQ : FREQ := 16 MHz; -- external clock CLK_MUL : positive := 31; -- computation clock: CLK_DIV : positive := 4 -- CLK_FREQ / CLK_DIV * CLK_MUL ); port ( --------------------------------------------------------------------------- -- 16-MHz Input Clock CLK16_U : in std_logic; --------------------------------------------------------------------------- -- Ring Bus -- Input BUS_IN_CLKP : in std_logic; BUS_IN_CLKN : in std_logic; BUS_IN_PRE_DAT : in std_logic_vector(8 downto 0); BUS_IN_PRE_PUT : in std_logic; BUS_IN_PRE_GO : out std_logic; BUS_IN_SOL_DAT : in std_logic_vector(8 downto 0); BUS_IN_SOL_PUT : in std_logic; BUS_IN_SOL_GO : out std_logic; -- Output BUS_OUT_CLKP : out std_logic; BUS_OUT_CLKN : out std_logic; BUS_OUT_PRE_DAT : out std_logic_vector(8 downto 0); BUS_OUT_PRE_PUT : out std_logic; BUS_OUT_PRE_GO : in std_logic; BUS_OUT_SOL_DAT : out std_logic_vector(8 downto 0); BUS_OUT_SOL_PUT : out std_logic; BUS_OUT_SOL_GO : in std_logic; --------------------------------------------------------------------------- -- State led : out std_logic_vector(3 downto 0) ); end sdrc_queens_slave; library IEEE; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.fifo.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of sdrc_queens_slave is -- Bit Length of Pre-Placement constant PRE_BITS : positive := 4*L*log2ceil(N)-1; constant PRE_BYTES : positive := (PRE_BITS+7)/8; -- FIFO Dimensioning constant FIFO_DEPTH : positive := 5*(SOLVERS+5); ---------------------------------------------------------------------------- -- Global Control: Clocks and Resets signal clk_comp : std_logic; -- Computation Clock signal rst_comp : std_logic; signal clk_out : std_logic; -- Communication Clock (Output Side) signal rst_out : std_logic; ----------------------------------------------------------------------------- -- Solver Chain Connectivity signal piful : std_logic; signal pidat : byte; signal pieof : std_logic; signal piput : std_logic; signal sivld : std_logic; signal sidat : byte; signal sieof : std_logic; signal sigot : std_logic; signal poful : std_logic; signal podat : byte; signal poeof : std_logic; signal poput : std_logic; signal sovld : std_logic; signal sodat : byte; signal soeof : std_logic; signal sogot : std_logic; begin ---------------------------------------------------------------------------- -- Clock Generation blkClock: block -- Intermediate Clock Signals signal clk16 : std_logic; -- Buffered Input Clock signal clk_comp_u : std_logic; signal locked_comp : std_logic; begin -- 16 MHz Board Clock -> Computation Clock clk16_buf : IBUFG port map ( I => CLK16_U, O => clk16 ); DCM0 : DCM_BASE generic map ( CLKIN_PERIOD => to_real(1.0/CLK_FREQ, 1 ns), CLKIN_DIVIDE_BY_2 => FALSE, PHASE_SHIFT => 0, CLKFX_MULTIPLY => CLK_MUL, CLKFX_DIVIDE => CLK_DIV, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", -- only using clkfx DLL_FREQUENCY_MODE => "LOW", DFS_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, STARTUP_WAIT => TRUE, DCM_AUTOCALIBRATION => FALSE ) port map ( CLKIN => clk16, CLKFB => '0', RST => '0', CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => clk_comp_u, CLKFX180 => open, LOCKED => locked_comp ); clk_comp_buf : BUFGCE port map ( CE => locked_comp, I => clk_comp_u, O => clk_comp ); rst_comp <= '0'; clk_out_buf : BUFGCE port map ( CE => locked_comp, I => clk16, O => clk_out ); rst_out <= '0'; led(0) <= locked_comp; end block blkClock; --------------------------------------------------------------------------- -- Solver Chain blkChain: block is signal pful : std_logic; signal pdat : byte; signal peof : std_logic; signal pput : std_logic; begin chain: entity work.queens_chain generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES ) port map ( clk => clk_comp, rst => rst_comp, piful => piful, pidat => pidat, pieof => pieof, piput => piput, sivld => '0', sidat => (others => '-'), sieof => '-', sigot => open, poful => pful, podat => pdat, poeof => peof, poput => pput, sovld => sovld, sodat => sodat, soeof => soeof, sogot => sogot ); -- Resync stream so that frames are taken out in one piece sync: entity work.msg_tap generic map ( D => PRE_BYTES ) port map ( clk => clk_comp, rst => rst_comp, iful => pful, idat => pdat, ieof => peof, iput => pput, oful => poful, odat => podat, oeof => poeof, oput => poput, tful => '1', tdat => open, tput => open ); end block blkChain; ----------------------------------------------------------------------------- -- Input Stream -> feeds pi(ful|dat|eof|put) and si(vld|dat|eof|got) blkInput: block -- Source synchronous clock domain signal clk_in : std_logic; signal rst_in : std_logic; -- Incoming Bus Data Capture Registers signal InPreDat : std_logic_vector(8 downto 0) := (others => '-'); signal InPrePut : std_logic := '0'; signal InPreCap : std_logic_vector(1 downto 0); signal InSolDat : std_logic_vector(8 downto 0) := (others => '-'); signal InSolPut : std_logic := '0'; signal InSolCap : std_logic_vector(1 downto 0); signal pivld : std_logic; begin --------------------------------------------------------------------------- -- Reading the Bus -- Clock reconstruction blkClock : block signal clk_in0 : std_logic; begin IBUFGDS_inst : IBUFGDS port map ( O => clk_in0, I => BUS_IN_CLKP, IB => BUS_IN_CLKN ); BUFG_inst : BUFR port map ( I => clk_in0, O => clk_in, CE => '1', CLR => '0' ); rst_in <= '0'; end block blkClock; -- Bus Input Capture process(clk_in) begin if rising_edge(clk_in) then if rst_in = '1' then InPreDat <= (others => '-'); InPrePut <= '0'; InSolDat <= (others => '-'); InSolPut <= '0'; else InPreDat <= BUS_IN_PRE_DAT; InPrePut <= BUS_IN_PRE_PUT; InSolDat <= BUS_IN_SOL_DAT; InSolPut <= BUS_IN_SOL_PUT; end if; end if; end process; -- Input FIFO (ic): Pre-Placements buf_pre : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InPreCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InPrePut, din => InPreDat, full => open, estate_wr => InPreCap, clk_rd => clk_comp, rst_rd => rst_comp, got => piput, dout(8) => pieof, dout(7 downto 0) => pidat, valid => pivld ); piput <= pivld and not piful; BUS_IN_PRE_GO <= '0' when InPreCap = (InPreCap'range => '0') else '1'; -- Input FIFO (ic): Solutions buf_sol : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InSolCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InSolPut, din => InSolDat, full => open, estate_wr => InSolCap, clk_rd => clk_out, rst_rd => rst_out, got => sigot, dout(8) => sieof, dout(7 downto 0) => sidat, valid => sivld ); BUS_IN_SOL_GO <= '0' when InSolCap = (InSolCap'range => '0') else '1'; end block blkInput; blkOutput : block begin ------------------------------------------------------------------------- -- Output Inverted Clock blkClock : block signal clk_inv : std_logic; begin invert : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '1', SRTYPE => "SYNC" ) port map ( Q => clk_inv, -- 1-bit DDR output C => clk_out, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D1 => '0', -- 1-bit data input (positive edge) D2 => '1', -- 1-bit data input (negative edge) R => rst_out, -- 1-bit reset input S => '0' -- 1-bit set input ); OBUFDS_inst : OBUFDS generic map ( IOSTANDARD => "DEFAULT", SLEW => "FAST" ) port map ( O => BUS_OUT_CLKP, OB => BUS_OUT_CLKN, I => clk_inv ); end block blkClock; blkPre: block -- Syncing the go input signal go_s : std_logic_vector(1 downto 0) := (others => '0'); -- Output FIFO signal pgot : std_logic; signal pdat : std_logic_vector(8 downto 0); signal pvld : std_logic; -- Outgoing Output Registers signal PreOutDat : std_logic_vector(8 downto 0) := (others => '0'); signal PreOutPut : std_logic := '0'; begin -- Syncing go input process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then go_s <= (others => '0'); else go_s <= BUS_OUT_PRE_GO & go_s(go_s'left downto 1); end if; end if; end process; -- Output FIFO (ic): Pre-Placements fifob : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64 ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => poput, din(8) => poeof, din(7 downto 0) => podat, full => poful, clk_rd => clk_out, rst_rd => rst_out, got => pgot, dout => pdat, valid => pvld ); pgot <= pvld and go_s(0); -- Output Registers process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then PreOutDat <= (others => '0'); PreOutPut <= '0'; else PreOutDat <= pdat; PreOutPut <= pgot; end if; end if; end process; BUS_OUT_PRE_DAT <= PreOutDat; BUS_OUT_PRE_PUT <= PreOutPut; end block blkPre; blkSol: block -- Syncing the go input signal go_s : std_logic_vector(1 downto 0) := (others => '0'); -- Chain -> fifo_ic [clk_comp->clk_out] signal soful : std_logic; -- fifo_ic -> funnel signal scvld : std_logic; signal scdat : std_logic_vector(8 downto 0); signal scgot : std_logic; -- funnel -> fifo_glue signal sjful : std_logic; signal sjdat : std_logic_vector(8 downto 0); signal sjput : std_logic; -- fifo_glue -> output signal sfvld : std_logic; signal sfdat : std_logic_vector(8 downto 0); signal sfgot : std_logic; -- Outgoing Output Registers signal SolOutDat : std_logic_vector(8 downto 0) := (others => '0'); signal SolOutPut : std_logic := '0'; begin -- Syncing go input process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then go_s <= (others => '0'); else go_s <= BUS_OUT_SOL_GO & go_s(go_s'left downto 1); end if; end if; end process; -- fifo_ic: clk_comp -> clk_out fifob : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64 ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => sogot, din(8) => soeof, din(7 downto 0) => sodat, full => soful, clk_rd => clk_out, rst_rd => rst_out, got => scgot, dout => scdat, valid => scvld ); sogot <= sovld and not soful; -- funnel: si* + sc* -> sj* join: entity work.msg_funnel generic map ( N => 2 ) port map ( clk => clk_out, rst => rst_out, ivld(0) => scvld, ivld(1) => sivld, idat(0) => scdat(7 downto 0), idat(1) => sidat, ieof(0) => scdat(8), ieof(1) => sieof, igot(0) => scgot, igot(1) => sigot, oful => sjful, odat => sjdat(7 downto 0), oeof => sjdat(8), oput => sjput ); -- fifo_glue glue: fifo_glue generic map ( D_BITS => 9 ) port map ( clk => clk_out, rst => rst_out, put => sjput, di => sjdat, ful => sjful, vld => sfvld, do => sfdat, got => sfgot ); sfgot <= sfvld and go_s(0); -- Output Registers process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then SolOutDat <= (others => '0'); SolOutPut <= '0'; else SolOutDat <= sfdat; SolOutPut <= sfgot; end if; end if; end process; BUS_OUT_SOL_DAT <= SolOutDat; BUS_OUT_SOL_PUT <= SolOutPut; end block blkSol; end block blkOutput; led(3 downto 1) <= "110"; end rtl;

agpl-3.0

1848736eda8be8885aba133032388745

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_8Stations_2AXI_2TAGM_2CACHE_W.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

25ce6ba1b8a3fd491498cbf78c9f55cb

jpidancet/mips

rtl/cpu_fetch.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity cpu_fetch is port (pc : in std_logic_vector(31 downto 0); pcbranch : in std_logic_vector(31 downto 0); pcsrc : in std_logic; instr_n : out std_logic_vector(31 downto 0); pcplus4_n : out std_logic_vector(31 downto 0); pc_n : out std_logic_vector(31 downto 0); imem_addr : out std_logic_vector(31 downto 0); imem_data : in std_logic_vector(31 downto 0)); end entity cpu_fetch; architecture rtl of cpu_fetch is signal pcplus4 : std_logic_vector(31 downto 0); begin pcplus4 <= pc + 4; instr_n <= imem_data; imem_addr <= pc; pcplus4_n <= pcplus4; pc_n <= pcbranch when pcsrc = '1' else pcplus4; end architecture rtl;

isc

5f92024a3d2040be6f70c0612b028cda

wltr/cern-fgclite

critical_fpga/src/rtl/cf/fetch_page/fetch_page_ow.vhd

------------------------------------------------------------------------------- --! @file fetch_page_ow.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-19 --! @brief Prepare one-wire page for NanoFIP communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --! @brief Entity declaration of fetch_page_ow --! @details --! This component prepares the one-wire page for the NanoFIP response. entity fetch_page_ow is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Commands --! @{ --! Start flag start_i : in std_ulogic; --! Done flag done_o : out std_ulogic; --! Memory index idx_i : in std_ulogic_vector(14 downto 0); --! @} --! @name Memory page interface --! @{ --! Address page_addr_o : out std_ulogic_vector(5 downto 0); --! Write enable page_wr_en_o : out std_ulogic; --! Data output page_data_o : out std_ulogic_vector(7 downto 0); --! Done flag page_done_i : in std_ulogic; --! @} --! @name One-wire data --! @{ --! Address ow_addr_o : out std_ulogic_vector(5 downto 0); --! Read enable ow_rd_en_o : out std_ulogic; --! Data input ow_data_i : in std_ulogic_vector(79 downto 0); --! Data input enable ow_data_en_i : in std_ulogic); --! @} end entity fetch_page_ow; --! RTL implementation of fetch_page_ow architecture rtl of fetch_page_ow is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type state_t is (IDLE, STORE, DONE); type reg_t is record state : state_t; addr : unsigned(5 downto 0); data : std_ulogic_vector(79 downto 0); wr_en : std_ulogic; rd_en : std_ulogic; done : std_ulogic; end record; constant init_c : reg_t := ( state => IDLE, addr => (others => '0'), data => (others => '0'), wr_en => '0', rd_en => '0', done => '0'); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal next_reg : reg_t; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- page_addr_o <= std_ulogic_vector(reg.addr); page_wr_en_o <= reg.wr_en; page_data_o <= reg.data(7 downto 0); ow_addr_o <= idx_i(3 downto 0) & std_ulogic_vector(reg.addr(5 downto 4)); ow_rd_en_o <= reg.rd_en; done_o <= reg.done; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= init_c; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else reg <= next_reg; end if; end if; end process regs; --------------------------------------------------------------------------- -- Combinatorics --------------------------------------------------------------------------- comb : process (reg, start_i, page_done_i, ow_data_i, ow_data_en_i) is begin -- comb -- Defaults next_reg <= reg; next_reg.rd_en <= '0'; next_reg.wr_en <= '0'; next_reg.done <= '0'; case reg.state is when IDLE => if start_i = '1' then next_reg.rd_en <= '1'; next_reg.state <= STORE; end if; when STORE => if ow_data_en_i = '1' then next_reg.data <= ow_data_i; next_reg.wr_en <= '1'; next_reg.state <= DONE; end if; when DONE => if page_done_i = '1' then if to_integer(reg.addr) < 63 then next_reg.addr <= reg.addr + 1; if to_integer(reg.addr(3 downto 0)) < 15 then next_reg.wr_en <= '1'; next_reg.data <= x"00" & reg.data(reg.data'high downto reg.data'low + 8); else next_reg.rd_en <= '1'; next_reg.state <= STORE; end if; else next_reg <= init_c; next_reg.done <= '1'; end if; end if; end case; end process comb; end architecture rtl;

mit

b0d1cb7bcf989dbe7556bdb8ffc3afe3

preusser/q27

src/vhdl/PoC/common/strings.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: String related functions and types -- -- Description: -- ------------------------------------- -- For detailed documentation see below. -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.math_real.all; library PoC; use PoC.config.all; use PoC.utils.all; --use PoC.FileIO.all; package strings is -- default fill and string termination character for fixed size strings -- =========================================================================== -- WORKAROUND: for Altera Quartus-II -- Version: 15.0 -- Issue: -- character 0 (NUL) causes Quartus-II to crash, if uses to pad STRINGs -- characters < 32 (control characters) are not supported in Quartus-II -- characters > 127 are not supported in VHDL files (strict ASCII files) -- character 255 craches ISE log window (created by 'CHARACTER'val(255)') -- Solution: -- PoC uses backtick "`" as a fill and termination symbol, if a Quartus-II -- synthesis environment is detected. constant C_POC_NUL : character := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`'); -- Type declarations -- =========================================================================== subtype T_RAWCHAR is std_logic_vector(7 downto 0); type T_RAWSTRING is array (natural range <>) of T_RAWCHAR; -- testing area: -- =========================================================================== function to_IPStyle(str : string) return T_IPSTYLE; -- to_char function to_char(Value : std_logic) return character; function to_char(rawchar : T_RAWCHAR) return character; function to_HexChar(Value : natural) return character; function to_HexChar(Value : unsigned) return character; -- chr_is* function function chr_isDigit(chr : character) return boolean; function chr_isLowerHexDigit(chr : character) return boolean; function chr_isUpperHexDigit(chr : character) return boolean; function chr_isHexDigit(chr : character) return boolean; function chr_isLower(chr : character) return boolean; function chr_isLowerAlpha(chr : character) return boolean; function chr_isUpper(chr : character) return boolean; function chr_isUpperAlpha(chr : character) return boolean; function chr_isAlpha(chr : character) return boolean; -- raw_format_* functions function raw_format_bool_bin(Value : boolean) return string; function raw_format_bool_chr(Value : boolean) return string; function raw_format_bool_str(Value : boolean) return string; function raw_format_slv_bin(slv : std_logic_vector) return string; function raw_format_slv_oct(slv : std_logic_vector) return string; function raw_format_slv_dec(slv : std_logic_vector) return string; function raw_format_slv_hex(slv : std_logic_vector) return string; function raw_format_nat_bin(Value : natural) return string; function raw_format_nat_oct(Value : natural) return string; function raw_format_nat_dec(Value : natural) return string; function raw_format_nat_hex(Value : natural) return string; -- str_format_* functions function str_format(Value : REAL; precision : natural := 3) return string; -- to_string function to_string(Value : boolean) return string; function to_string(Value : integer; base : positive := 10) return string; function to_string(slv : std_logic_vector; format : character; Length : natural := 0; fill : character := '0') return string; function to_string(rawstring : T_RAWSTRING) return string; function to_string(Value : T_BCD_VECTOR) return string; -- to_slv function to_slv(rawstring : T_RAWSTRING) return std_logic_vector; -- digit subtypes incl. error Value (-1) subtype T_DIGIT_BIN is integer range -1 to 1; subtype T_DIGIT_OCT is integer range -1 to 7; subtype T_DIGIT_DEC is integer range -1 to 9; subtype T_DIGIT_HEX is integer range -1 to 15; -- to_digit* function to_digit_bin(chr : character) return T_DIGIT_BIN; function to_digit_oct(chr : character) return T_DIGIT_OCT; function to_digit_dec(chr : character) return T_DIGIT_DEC; function to_digit_hex(chr : character) return T_DIGIT_HEX; function to_digit(chr : character; base : character := 'd') return integer; -- to_natural* function to_natural_bin(str : string) return integer; function to_natural_oct(str : string) return integer; function to_natural_dec(str : string) return integer; function to_natural_hex(str : string) return integer; function to_natural(str : string; base : character := 'd') return integer; -- to_raw* function to_RawChar(char : character) return T_RAWCHAR; function to_RawString(str : string) return T_RAWSTRING; -- resize function resize(str : string; size : positive; FillChar : character := C_POC_NUL) return string; -- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING; -- Character functions function chr_toLower(chr : character) return character; function chr_toUpper(chr : character) return character; -- String functions function str_length(str : string) return natural; function str_equal(str1 : string; str2 : string) return boolean; function str_match(str1 : string; str2 : string) return boolean; function str_imatch(str1 : string; str2 : string) return boolean; function str_pos(str : string; chr : character; start : natural := 0) return integer; function str_pos(str : string; pattern : string; start : natural := 0) return integer; function str_ipos(str : string; chr : character; start : natural := 0) return integer; function str_ipos(str : string; pattern : string; start : natural := 0) return integer; function str_find(str : string; chr : character) return boolean; function str_find(str : string; pattern : string) return boolean; function str_ifind(str : string; chr : character) return boolean; function str_ifind(str : string; pattern : string) return boolean; function str_replace(str : string; pattern : string; replace : string) return string; function str_substr(str : string; start : integer := 0; Length : integer := 0) return string; function str_ltrim(str : string; char : character := ' ') return string; function str_rtrim(str : string; char : character := ' ') return string; function str_trim(str : string) return string; function str_calign(str : string; Length : natural; FillChar : character := ' ') return string; function str_lalign(str : string; Length : natural; FillChar : character := ' ') return string; function str_ralign(str : string; Length : natural; FillChar : character := ' ') return string; function str_toLower(str : string) return string; function str_toUpper(str : string) return string; end package; package body strings is -- function to_IPStyle(str : string) return T_IPSTYLE is begin for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(i))) then return T_IPSTYLE'val(i); end if; end loop; report "Unknown IPStyle: '" & str & "'" severity FAILURE; end function; -- to_char -- =========================================================================== function to_char(Value : std_logic) return character is begin case Value is when 'U' => return 'U'; when 'X' => return 'X'; when '0' => return '0'; when '1' => return '1'; when 'Z' => return 'Z'; when 'W' => return 'W'; when 'L' => return 'L'; when 'H' => return 'H'; when '-' => return '-'; when others => return 'X'; end case; end function; function to_char(rawchar : T_RAWCHAR) return character is begin return character'val(to_integer(unsigned(rawchar))); end function; -- function to_HexChar(Value : natural) return character is constant HEX : string := "0123456789ABCDEF"; begin return ite(Value < 16, HEX(Value+1), 'X'); end function; function to_HexChar(Value : unsigned) return character is begin return to_HexChar(to_integer(Value)); end function; -- chr_is* function function chr_isDigit(chr : character) return boolean is begin return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9')); end function; function chr_isLowerHexDigit(chr : character) return boolean is begin return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f')); end function; function chr_isUpperHexDigit(chr : character) return boolean is begin return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F')); end function; function chr_isHexDigit(chr : character) return boolean is begin return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr); end function; function chr_isLower(chr : character) return boolean is begin return chr_isLowerAlpha(chr); end function; function chr_isLowerAlpha(chr : character) return boolean is begin return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z')); end function; function chr_isUpper(chr : character) return boolean is begin return chr_isUpperAlpha(chr); end function; function chr_isUpperAlpha(chr : character) return boolean is begin return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z')); end function; function chr_isAlpha(chr : character) return boolean is begin return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr); end function; -- raw_format_* functions -- =========================================================================== function raw_format_bool_bin(Value : boolean) return string is begin return ite(Value, "1", "0"); end function; function raw_format_bool_chr(Value : boolean) return string is begin return ite(Value, "T", "F"); end function; function raw_format_bool_str(Value : boolean) return string is begin return str_toUpper(boolean'image(Value)); end function; function raw_format_slv_bin(slv : std_logic_vector) return string is variable Value : std_logic_vector(slv'length - 1 downto 0); variable Result : string(1 to slv'length); variable j : natural; begin -- convert input slv to a downto ranged vector and normalize range to slv'low = 0 Value := movez(ite(slv'ascending, descend(slv), slv)); -- convert each bit to a character j := 0; for i in Result'reverse_range loop Result(i) := to_char(Value(j)); j := j + 1; end loop; return Result; end function; function raw_format_slv_oct(slv : std_logic_vector) return string is variable Value : std_logic_vector(slv'length - 1 downto 0); variable Digit : std_logic_vector(2 downto 0); variable Result : string(1 to div_ceil(slv'length, 3)); variable j : natural; begin -- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3 Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3)); -- convert 3 bit to a character j := 0; for i in Result'reverse_range loop Digit := Value((j * 3) + 2 downto (j * 3)); Result(i) := to_HexChar(unsigned(Digit)); j := j + 1; end loop; return Result; end function; function raw_format_slv_dec(slv : std_logic_vector) return string is variable Value : std_logic_vector(slv'length - 1 downto 0); variable Result : string(1 to div_ceil(slv'length, 3)); subtype TT_BCD is integer range 0 to 31; type TT_BCD_VECTOR is array(natural range <>) of TT_BCD; variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0); variable Carry : T_UINT_8; variable Pos : natural; begin Temp := (others => 0); Pos := 0; -- convert input slv to a downto ranged vector Value := ite(slv'ascending, descend(slv), slv); for i in Value'range loop Carry := to_int(Value(i)); for j in Temp'reverse_range loop Temp(j) := Temp(j) * 2 + Carry; Carry := to_int(Temp(j) > 9); Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10); end loop; end loop; for i in Result'range loop Result(i) := to_HexChar(Temp(Temp'high - i + 1)); if ((Result(i) /= '0') and (Pos = 0)) then Pos := i; end if; end loop; -- trim leading zeros, except the last return Result(imin(Pos, Result'high) to Result'high); end function; function raw_format_slv_hex(slv : std_logic_vector) return string is variable Value : std_logic_vector(4*div_ceil(slv'length, 4) - 1 downto 0); variable Digit : std_logic_vector(3 downto 0); variable Result : string(1 to div_ceil(slv'length, 4)); variable j : natural; begin Value := resize(slv, Value'length); j := 0; for i in Result'reverse_range loop Digit := Value((j * 4) + 3 downto (j * 4)); Result(i) := to_HexChar(unsigned(Digit)); j := j + 1; end loop; return Result; end function; function raw_format_nat_bin(Value : natural) return string is begin return raw_format_slv_bin(to_slv(Value, log2ceilnz(Value+1))); end function; function raw_format_nat_oct(Value : natural) return string is begin return raw_format_slv_oct(to_slv(Value, log2ceilnz(Value+1))); end function; function raw_format_nat_dec(Value : natural) return string is begin return integer'image(Value); end function; function raw_format_nat_hex(Value : natural) return string is begin return raw_format_slv_hex(to_slv(Value, log2ceilnz(Value+1))); end function; -- str_format_* functions -- =========================================================================== function str_format(Value : REAL; precision : natural := 3) return string is constant s : REAL := sign(Value); constant val : REAL := Value * s; constant int : integer := integer(floor(val)); constant frac : integer := integer(round((val - real(int)) * 10.0**precision)); constant overflow : boolean := frac >= 10**precision; constant int2 : integer := ite(overflow, int+1, int); constant frac2 : integer := ite(overflow, frac-10**precision, frac); constant frac_str : string := integer'image(frac2); constant res : string := integer'image(int2) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str; begin return ite ((s < 0.0), "-" & res, res); end function; -- to_string -- =========================================================================== function to_string(Value : boolean) return string is begin return raw_format_bool_str(Value); end function; -- convert an integer Value to a STRING using an arbitrary base function to_string(Value : integer; base : positive := 10) return string is constant absValue : natural := abs(Value); constant len : positive := log10ceilnz(absValue); variable power : positive; variable Result : string(1 to len); begin power := 1; if (base = 10) then return integer'image(Value); else for i in len downto 1 loop Result(i) := to_HexChar(absValue / power mod base); power := power * base; end loop; if (Value < 0) then return '-' & Result; else return Result; end if; end if; end function; -- QUESTION: rename to slv_format(..) ? function to_string(slv : std_logic_vector; format : character; Length : natural := 0; fill : character := '0') return string is constant int : integer := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0); constant str : string := integer'image(int); constant bin_len : positive := slv'length; constant dec_len : positive := str'length;--log10ceilnz(int); constant hex_len : positive := ite(((bin_len mod 4) = 0), (bin_len / 4), (bin_len / 4) + 1); constant len : natural := ite((format = 'b'), bin_len, ite((format = 'd'), dec_len, ite((format = 'h'), hex_len, 0))); variable j : natural; variable Result : string(1 to ite((Length = 0), len, imax(len, Length))); begin j := 0; Result := (others => fill); if (format = 'b') then for i in Result'reverse_range loop Result(i) := to_char(slv(j)); j := j + 1; end loop; elsif (format = 'd') then -- TODO: enable big integer conversion -- if (slv'length < 32) then -- return INTEGER'image(int); -- else -- return raw_format_slv_dec(slv); -- end if; Result(Result'length - str'length + 1 to Result'high) := str; elsif (format = 'h') then for i in Result'reverse_range loop Result(i) := to_HexChar(unsigned(slv((j * 4) + 3 downto (j * 4)))); j := j + 1; end loop; else report "Unknown format character: " & format & "." severity FAILURE; end if; return Result; end function; function to_string(rawstring : T_RAWSTRING) return string is variable Result : string(1 to rawstring'length); begin for i in rawstring'low to rawstring'high loop Result(i - rawstring'low + 1) := to_char(rawstring(i)); end loop; return Result; end function; function to_string(Value : T_BCD_VECTOR) return string is variable Result : string(1 to Value'length); begin for i in Value'range loop Result(Result'high - (i - Value'low)) := to_HexChar(unsigned(Value(i))); end loop; return Result; end function; -- to_slv -- =========================================================================== function to_slv(rawstring : T_RAWSTRING) return std_logic_vector is variable Result : std_logic_vector((rawstring'length * 8) - 1 downto 0); begin for i in rawstring'range loop Result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i); end loop; return Result; end function; -- to_digit* -- =========================================================================== -- convert a binary digit given as CHARACTER to a digit returned as NATURAL; return -1 on error function to_digit_bin(chr : character) return T_DIGIT_BIN is begin case chr is when '0' => return 0; when '1' => return 1; when others => return -1; end case; end function; -- convert an octal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error function to_digit_oct(chr : character) return T_DIGIT_OCT is variable dec : integer; begin dec := to_digit_dec(chr); return ite((dec < 8), dec, -1); end function; -- convert a adecimal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error function to_digit_dec(chr : character) return T_DIGIT_DEC is begin if chr_isDigit(chr) then return character'pos(chr) - CHARACTER'pos('0'); else return -1; end if; end function; -- convert a hexadecimal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error function to_digit_hex(chr : character) return T_DIGIT_HEX is begin if chr_isDigit(chr) then return character'pos(chr) - CHARACTER'pos('0'); elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('a') + 10; elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('A') + 10; else return -1; end if; end function; -- convert a digit given as CHARACTER to a digit returned as NATURAL; return -1 on error function to_digit(chr : character; base : character := 'd') return integer is begin case base is when 'b' => return to_digit_bin(chr); when 'o' => return to_digit_oct(chr); when 'd' => return to_digit_dec(chr); when 'h' => return to_digit_hex(chr); when others => report "Unknown base character: " & base & "." severity FAILURE; end case; -- return statement is explicitly missing otherwise XST won't stop end function; -- to_natural* -- =========================================================================== -- convert a binary number given as STRING to a NATURAL; return -1 on error function to_natural_bin(str : string) return integer is variable Result : natural; variable Digit : integer; begin for i in str'range loop Digit := to_digit_bin(str(i)); if (Digit /= -1) then Result := Result * 2 + Digit; else return -1; end if; end loop; return Result; end function; -- convert an octal number given as STRING to a NATURAL; return -1 on error function to_natural_oct(str : string) return integer is variable Result : natural; variable Digit : integer; begin for i in str'range loop Digit := to_digit_oct(str(i)); if (Digit /= -1) then Result := Result * 8 + Digit; else return -1; end if; end loop; return Result; end function; -- convert a decimal number given as STRING to a NATURAL; return -1 on error function to_natural_dec(str : string) return integer is variable Result : natural; variable Digit : integer; begin -- WORKAROUND: Xilinx Vivado Synth -- Version: 2014.1 -- Issue: -- INTEGER'value(...) is not supported by Vivado Synth -- Solution: -- implement a manual conversion using shift and multiply for i in str'range loop Digit := to_digit_dec(str(i)); if (Digit /= -1) then Result := Result * 10 + Digit; else return -1; end if; end loop; return Result; -- INTEGER'value(str); end function; -- convert a hexadecimal number given as STRING to a NATURAL; return -1 on error function to_natural_hex(str : string) return integer is variable Result : natural; variable Digit : integer; begin for i in str'range loop Digit := to_digit_hex(str(i)); if (Digit /= -1) then Result := Result * 16 + Digit; else return -1; end if; end loop; return Result; end function; -- convert a number given as STRING to a NATURAL; return -1 on error function to_natural(str : string; base : character := 'd') return integer is begin case base is when 'b' => return to_natural_bin(str); when 'o' => return to_natural_oct(str); when 'd' => return to_natural_dec(str); when 'h' => return to_natural_hex(str); when others => report "Unknown base character: " & base & "." severity FAILURE; end case; -- return statement is explicitly missing otherwise XST won't stop end function; -- to_raw* -- =========================================================================== -- convert a CHARACTER to a RAWCHAR function to_RawChar(char : character) return T_RAWCHAR is begin return std_logic_vector(to_unsigned(character'pos(char), T_RAWCHAR'length)); end function; -- convert a STRING to a RAWSTRING function to_RawString(str : string) return T_RAWSTRING is variable Result : T_RAWSTRING(0 to str'length - 1); begin for i in str'low to str'high loop Result(i - str'low) := to_RawChar(str(i)); end loop; return Result; end function; -- resize -- =========================================================================== function resize(str : string; Size : positive; FillChar : character := C_POC_NUL) return string is constant ConstNUL : string(1 to 1) := (others => C_POC_NUL); variable Result : string(1 to Size); begin Result := (others => FillChar); if (str'length > 0) then -- WORKAROUND: for Altera Quartus-II -- Version: 15.0 -- Issue: array bounds are check regardless of the hierarchy and control flow Result(1 to imin(Size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(Size, str'length)), ConstNUL); end if; return Result; end function; -- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is -- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00"); -- variable Result : T_RAWSTRING(1 to size); -- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is -- begin -- if cond then -- return value1; -- else -- return value2; -- end if; -- end function; -- begin -- Result := (others => FillChar); -- if (str'length > 0) then -- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL); -- end if; -- return Result; -- end function; -- Character functions -- =========================================================================== -- convert an upper case CHARACTER into a lower case CHARACTER function chr_toLower(chr : character) return character is begin if chr_isUpperAlpha(chr) then return character'val(character'pos(chr) - character'pos('A') + character'pos('a')); else return chr; end if; end function; -- convert a lower case CHARACTER into an upper case CHARACTER function chr_toUpper(chr : character) return character is begin if chr_isLowerAlpha(chr) then return character'val(character'pos(chr) - character'pos('a') + character'pos('A')); else return chr; end if; end function; -- String functions -- =========================================================================== -- count the length of a POC_NUL terminated STRING function str_length(str : string) return natural is begin for i in str'range loop if (str(i) = C_POC_NUL) then return i - str'low; end if; end loop; return str'length; end function; -- compare two STRINGs for equality -- pre-check the string lengths to suppress warnings for unequal sized string comparisons. -- QUESTION: overload "=" operator? function str_equal(str1 : string; str2 : string) return boolean is begin if str1'length /= str2'length then return FALSE; else return (str1 = str2); end if; end function; -- compare two POC_NUL terminated STRINGs function str_match(str1 : string; str2 : string) return boolean is constant len : natural := imin(str1'length, str2'length); begin -- if both strings are empty if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if; -- compare char by char for i in str1'low to str1'low + len - 1 loop if (str1(i) /= str2(str2'low + (i - str1'low))) then return FALSE; elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then return FALSE; elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then return TRUE; end if; end loop; -- check special cases, return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal ((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len ((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len end function; -- compare two POC_NUL terminated STRINGs; case insentitve function str_imatch(str1 : string; str2 : string) return boolean is begin return str_match(str_toLower(str1), str_toLower(str2)); end function; -- search for chr in a STRING and return the position; return -1 on error function str_pos(str : string; chr : character; start : natural := 0) return integer is begin for i in imax(str'low, start) to str'high loop exit when (str(i) = C_POC_NUL); if (str(i) = chr) then return i; end if; end loop; return -1; end function; -- search for pattern in a STRING and return the position; return -1 on error -- QUESTION: implement KMP algorithm? function str_pos(str : string; pattern : string; start : natural := 0) return integer is begin for i in imax(str'low, start) to (str'high - pattern'length + 1) loop exit when (str(i) = C_POC_NUL); if (str(i to i + pattern'length - 1) = pattern) then return i; end if; end loop; return -1; end function; -- search for chr in a STRING and return the position; case insentitve; return -1 on error function str_ipos(str : string; chr : character; start : natural := 0) return integer is begin return str_pos(str_toLower(str), chr_toLower(chr)); end function; -- search for pattern in a STRING and return the position; case insentitve; return -1 on error function str_ipos(str : string; pattern : string; start : natural := 0) return integer is begin return str_pos(str_toLower(str), str_toLower(pattern)); end function; -- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is -- variable PrefixTable : T_INTVEC(0 to str2'length); -- variable j : INTEGER; -- begin -- -- construct prefix table for KMP algorithm -- j := -1; -- PrefixTable(0) := -1; -- for i in str2'range loop -- while ((j >= 0) and str2(j + 1) /= str2(i)) loop -- j := PrefixTable(j); -- end loop; -- -- j := j + 1; -- PrefixTable(i - 1) := j + 1; -- end loop; -- -- -- search pattern str2 in text str1 -- j := 0; -- for i in str1'range loop -- while ((j >= 0) and str1(i) /= str2(j + 1)) loop -- j := PrefixTable(j); -- end loop; -- -- j := j + 1; -- if ((j + 1) = str2'high) then -- return i - str2'length + 1; -- end if; -- end loop; -- -- return -1; -- end function; -- check if chr exists in STRING str function str_find(str : string; chr : character) return boolean is begin return (str_pos(str, chr) > 0); end function; -- check if pattern exists in STRING str function str_find(str : string; pattern : string) return boolean is begin return (str_pos(str, pattern) > 0); end function; -- check if chr exists in STRING str; case insentitve function str_ifind(str : string; chr : character) return boolean is begin return (str_ipos(str, chr) > 0); end function; -- check if pattern exists in STRING str; case insentitve function str_ifind(str : string; pattern : string) return boolean is begin return (str_ipos(str, pattern) > 0); end function; -- replace a pattern in a STRING str by the STRING replace function str_replace(str : string; pattern : string; replace : string) return string is variable pos : integer; begin pos := str_pos(str, pattern); if (pos > 0) then if (pos = 1) then return replace & str(pattern'length + 1 to str'length); elsif (pos = str'length - pattern'length + 1) then return str(1 to str'length - pattern'length) & replace; else return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length); end if; else return str; end if; end function; -- return a sub-string of STRING str -- EXAMPLES: -- 123456789ABC -- input string: "Hello World." -- low=1; high=12; length=12 -- -- str_substr("Hello World.", 0, 0) => "Hello World." - copy all -- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string -- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters -- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary function str_substr(str : string; start : integer := 0; Length : integer := 0) return string is variable StartOfString : positive; variable EndOfString : positive; begin if (start < 0) then -- start is negative -> start substring at right string boundary StartOfString := str'high + start + 1; elsif (start = 0) then -- start is zero -> start substring at left string boundary StartOfString := str'low; else -- start is positive -> start substring at left string boundary + offset StartOfString := start; end if; if (Length < 0) then -- Length is negative -> end substring at length'th character before right string boundary EndOfString := str'high + Length; elsif (Length = 0) then -- Length is zero -> end substring at right string boundary EndOfString := str'high; else -- Length is positive -> end substring at StartOfString + Length EndOfString := StartOfString + Length - 1; end if; if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity FAILURE; end if; if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity FAILURE; end if; return str(StartOfString to EndOfString); end function; -- left-trim the STRING str function str_ltrim(str : string; char : character := ' ') return string is begin for i in str'range loop if (str(i) /= char) then return str(i to str'high); end if; end loop; return ""; end function; -- right-trim the STRING str function str_rtrim(str : string; char : character := ' ') return string is begin for i in str'reverse_range loop if (str(i) /= char) then return str(str'low to i); end if; end loop; return ""; end function; -- remove POC_NUL string termination characters function str_trim(str : string) return string is begin return str(str'low to str'low + str_length(str) - 1); end function; -- center-align a STRING str in a FillChar filled STRING of length Length function str_calign(str : string; Length : natural; FillChar : character := ' ') return string is constant Start : positive := (Length - str'length) / 2; variable Result : string(1 to Length); begin Result := (others => FillChar); Result(Start to (Start + str'length)) := str; return Result; end function; -- left-align a STRING str in a FillChar filled STRING of length Length function str_lalign(str : string; Length : natural; FillChar : character := ' ') return string is variable Result : string(1 to Length); begin Result := (others => FillChar); Result(1 to str'length) := str; return Result; end function; -- right-align a STRING str in a FillChar filled STRING of length Length function str_ralign(str : string; Length : natural; FillChar : character := ' ') return string is variable Result : string(1 to Length); begin Result := (others => FillChar); Result((Length - str'length + 1) to Length) := str; return Result; end function; -- convert an upper case STRING into a lower case STRING function str_toLower(str : string) return string is variable Result : string(str'range); begin for i in str'range loop Result(i) := chr_toLower(str(i)); end loop; return Result; end function; -- convert a lower case STRING into an upper case STRING function str_toUpper(str : string) return string is variable Result : string(str'range); begin for i in str'range loop Result(i) := chr_toUpper(str(i)); end loop; return Result; end function; end package body;

agpl-3.0

b0ea63feea60cf9182a58e5525d3159e

preusser/q27

src/vhdl/PoC/fifo/fifo_cc_got_tempput.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================================================================================================ -- Module: FIFO, common clock (cc), pipelined interface, -- writes only become effective after explicit commit -- -- Authors: Thomas B. Preusser -- Steffen Koehler -- Martin Zabel -- -- Description: -- ------------------------------------ -- The specified depth (MIN_DEPTH) is rounded up to the next suitable value. -- -- As uncommitted writes populate FIFO space that is not yet available for -- reading, an instance of this FIFO can, indeed, report 'full' and 'not vld' -- at the same time. While a 'commit' would eventually make data available for -- reading ('vld'), a 'rollback' would free the space for subsequent writing -- ('not ful'). -- -- 'commit' and 'rollback' are inclusive and apply to all writes ('put') since -- the previous 'commit' or 'rollback' up to and including a potentially -- simultaneous write. -- -- The FIFO state upon a simultaneous assertion of 'commit' and 'rollback' is -- *undefined*! -- -- *STATE_*_BITS defines the granularity of the fill state indicator -- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs -- the guaranteed number of words available in the FIFO. 'estate_wr' is -- associated with the write clock domain and outputs the number of words that -- is guaranteed to be accepted by the FIFO without a capacity overflow. Note -- that both these indicators cannot replace the 'full' or 'valid' outputs as -- they may be implemented as giving pessimistic bounds that are minimally off -- the true fill state. -- -- If a fill state is not of interest, set *STATE_*_BITS = 0. -- -- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address -- comparator (subtractor) in their path. -- -- Examples: -- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full -- fstate_rd == 1 => 1/2 full (half full) -- -- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full -- fstate_rd == 1 => 1/4 full -- fstate_rd == 2 => 2/4 full -- fstate_rd == 3 => 3/4 full -- -- License: -- ============================================================================================================================================================ -- Copyright 2007-2014 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================================================================================================ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library poc; use poc.config.all; USE poc.utils.all; use poc.ocram.ocram_sdp; entity fifo_cc_got_tempput is generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers STATE_REG : boolean := false; -- Registered Full/Empty Indicators OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Global Reset and Clock rst, clk : in std_logic; -- Writing Interface put : in std_logic; -- Write Request din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data full : out std_logic; estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0); commit : in std_logic; rollback : in std_logic; -- Reading Interface got : in std_logic; -- Read Completed dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data valid : out std_logic; fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0) ); end fifo_cc_got_tempput; architecture rtl of fifo_cc_got_tempput is -- Address Width constant A_BITS : natural := log2ceil(MIN_DEPTH); -- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (A_BITS > 4); ----------------------------------------------------------------------------- -- Memory Pointers -- Actual Input and Output Pointers signal IP0 : unsigned(A_BITS-1 downto 0) := (others => '0'); signal OP0 : unsigned(A_BITS-1 downto 0) := (others => '0'); -- Incremented Input and Output Pointers signal IP1 : unsigned(A_BITS-1 downto 0); signal OP1 : unsigned(A_BITS-1 downto 0); -- Committed Write Pointer (Commit Marker) signal IPm : unsigned(A_BITS-1 downto 0) := (others => '0'); ----------------------------------------------------------------------------- -- Backing Memory Connectivity -- Write Port signal wa : unsigned(A_BITS-1 downto 0); signal we : std_logic; -- Read Port signal ra : unsigned(A_BITS-1 downto 0); signal re : std_logic; -- Internal full and empty indicators signal fulli : std_logic; signal empti : std_logic; begin ----------------------------------------------------------------------------- -- Pointer Logic genCCN: if not FORCE_XILCY generate IP1 <= IP0 + 1; OP1 <= OP0 + 1; end generate; genCCY: if FORCE_XILCY generate component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; component XORCY port ( O : out std_ulogic; CI : in std_ulogic; LI : in std_ulogic ); end component; signal ci, co : std_logic_vector(A_BITS downto 0); begin ci(0) <= '1'; genCCI : for i in 0 to A_BITS-1 generate MUXCY_inst : MUXCY port map ( O => ci(i+1), CI => ci(i), DI => '0', S => IP0(i) ); XORCY_inst : XORCY port map ( O => IP1(i), CI => ci(i), LI => IP0(i) ); end generate genCCI; co(0) <= '1'; genCCO: for i in 0 to A_BITS-1 generate MUXCY_inst : MUXCY port map ( O => co(i+1), CI => co(i), DI => '0', S => OP0(i) ); XORCY_inst : XORCY port map ( O => OP1(i), CI => co(i), LI => OP0(i) ); end generate genCCO; end generate; process(clk) begin if rising_edge(clk) then if rst = '1' then IP0 <= (others => '0'); IPm <= (others => '0'); OP0 <= (others => '0'); else -- Update Input Pointer upon Write if rollback = '1' then IP0 <= IPm; elsif we = '1' then IP0 <= IP1; end if; -- Update Commit Marker if commit = '1' then if we = '1' then IPm <= IP1; else IPm <= IP0; end if; end if; -- Update Output Pointer upon Read if re = '1' then OP0 <= OP1; end if; end if; end if; end process; wa <= IP0; ra <= OP0; -- Fill State Computation (soft indicators) process(fulli, IP0, IPm, OP0) variable d : std_logic_vector(A_BITS-1 downto 0); begin -- Available Space if ESTATE_WR_BITS > 0 then -- Compute Pointer Difference if fulli = '1' then d := (others => '1'); -- true number minus one when full else d := std_logic_vector(IP0 - OP0); -- true number of valid entries end if; estate_wr <= not d(d'left downto d'left-ESTATE_WR_BITS+1); else estate_wr <= (others => 'X'); end if; -- Available Content if FSTATE_RD_BITS > 0 then -- Compute Pointer Difference if fulli = '1' then d := (others => '1'); -- true number minus one when full else d := std_logic_vector(IPm - OP0); -- true number of valid entries end if; fstate_rd <= d(d'left downto d'left-FSTATE_RD_BITS+1); else fstate_rd <= (others => 'X'); end if; end process; ----------------------------------------------------------------------------- -- Computation of full and empty indications. -- -- The STATE_REG generic is ignored as two different comparators are -- needed to compare OP with IPm (empty) and IP with OP (full) anyways. -- So the register implementation is always used. blkState: block signal Ful : std_logic := '0'; signal Pnd : std_logic := '0'; signal Avl : std_logic := '0'; begin process(clk) begin if rising_edge(clk) then if rst = '1' then Ful <= '0'; Pnd <= '0'; Avl <= '0'; else -- Pending Indicator for uncommitted Data if commit = '1' or rollback = '1' then Pnd <= '0'; elsif we = '1' then Pnd <= '1'; end if; -- Update Full Indicator if re = '1' or (rollback = '1' and Pnd = '1') then Ful <= '0'; elsif we = '1' and re = '0' and IP1 = OP0 then Ful <= '1'; end if; -- Update Empty Indicator if commit = '1' and (we = '1' or Pnd = '1') then Avl <= '1'; elsif re = '1' and OP1 = IPm then Avl <= '0'; end if; end if; end if; end process; fulli <= Ful; empti <= not Avl; end block; ----------------------------------------------------------------------------- -- Memory Access -- Write Interface => Input full <= fulli; we <= put and not fulli; -- Backing Memory and Read Interface => Output genLarge: if not DATA_REG generate signal do : std_logic_vector(D_BITS-1 downto 0); begin -- Backing Memory ram : ocram_sdp generic map ( A_BITS => A_BITS, D_BITS => D_BITS ) port map ( wclk => clk, rclk => clk, wce => '1', wa => wa, we => we, d => din, ra => ra, rce => re, q => do ); -- Read Interface => Output genOutputCmb : if not OUTPUT_REG generate signal Vld : std_logic := '0'; -- valid output of RAM module begin process(clk) begin if rising_edge(clk) then if rst = '1' then Vld <= '0'; else Vld <= (Vld and not got) or not empti; end if; end if; end process; re <= (not Vld or got) and not empti; dout <= do; valid <= Vld; end generate genOutputCmb; genOutputReg: if OUTPUT_REG generate -- Extra Buffer Register for Output Data signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); signal Vld : std_logic_vector(0 to 1) := (others => '0'); -- Vld(0) -- valid output of RAM module -- Vld(1) -- valid word in Buf begin process(clk) begin if rising_edge(clk) then if rst = '1' then Buf <= (others => '-'); Vld <= (others => '0'); else Vld(0) <= (Vld(0) and Vld(1) and not got) or not empti; Vld(1) <= (Vld(1) and not got) or Vld(0); if Vld(1) = '0' or got = '1' then Buf <= do; end if; end if; end if; end process; re <= (not Vld(0) or not Vld(1) or got) and not empti; dout <= Buf; valid <= Vld(1); end generate genOutputReg; end generate genLarge; genSmall: if DATA_REG generate -- Memory modelled as Array type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0); signal regfile : regfile_t; attribute ram_style : string; -- XST specific attribute ram_style of regfile : signal is "distributed"; -- Altera Quartus II: Allow automatic RAM type selection. -- For small RAMs, registers are used on Cyclone devices and the M512 type -- is used on Stratix devices. Pass-through logic is automatically added -- if required. (Warning can be ignored.) begin -- Memory State process(clk) begin if rising_edge(clk) then --synthesis translate_off if SIMULATION AND (rst = '1') then regfile <= (others => (others => '-')); else --synthesis translate_on if we = '1' then regfile(to_integer(wa)) <= din; end if; --synthesis translate_off end if; --synthesis translate_on end if; end process; -- Memory Output re <= got and not empti; dout <= (others => 'X') when Is_X(std_logic_vector(ra)) else regfile(to_integer(ra)); valid <= not empti; end generate genSmall; end rtl;

agpl-3.0

ef4f5453d52aca1ac947d91ab3d89851

jcowgill/cs-dacs-robot

Common/AsyncTxTest.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY AsyncTxTest IS END AsyncTxTest; ARCHITECTURE behavioral OF AsyncTxTest IS COMPONENT AsyncTx PORT ( TX : OUT STD_LOGIC; ACTIVE : OUT STD_LOGIC; SEND : IN STD_LOGIC; CLR : IN STD_LOGIC; CLK : IN STD_LOGIC; DATA : IN STD_LOGIC_VECTOR (5 DOWNTO 0)); END COMPONENT; SIGNAL TX : STD_LOGIC; SIGNAL ACTIVE : STD_LOGIC; SIGNAL SEND : STD_LOGIC; SIGNAL CLR : STD_LOGIC; SIGNAL CLK : STD_LOGIC; SIGNAL DATA : STD_LOGIC_VECTOR (5 DOWNTO 0); BEGIN UUT: AsyncTx PORT MAP( TX => TX, ACTIVE => ACTIVE, SEND => SEND, CLR => CLR, CLK => CLK, DATA => DATA ); clk_process : PROCESS BEGIN -- Clock signal (4 MHz) CLK <= '0'; WAIT FOR 125ns; CLK <= '1'; WAIT FOR 125ns; END PROCESS; tb_process : PROCESS BEGIN -- Reset CLR <= '1'; WAIT FOR 1000ns; CLR <= '0'; -- Send the number 1 DATA <= "001010"; SEND <= '1'; WAIT FOR 1000ns; SEND <= '0'; WAIT; END PROCESS; END;

apache-2.0

7204d74e74dfc00903e03cb6db300eee

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_top.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block qPI3GEpZcWQvIycErMHhDoSKsieE/CU1+Ybm/uQFxbrtkOKyOV3ZWFMB8n6MZ3bT8CRlbUhWEzXR TkxRDQG9yQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k/t3gWcO/yZ6QHxZLkY4V/YSwTnMWe59zgVXRMqLIqmP5+4sWdcnqrkWJ2pBDLgKPlHOUDO5KHVg XZQouc2gZ8nI9hPwoqlm+ho4rq4zHpnDJQGzRE15JSAxtcXMJjyuVk/MN6Dhv5p2xXr5Mfi10QtO ogsfzAak/7F8gy868xY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

6baa9e1d0839c23b982d8f3a36e43523

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/dualram_512x8.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- dualram_512x8 | -- | --------------------------------------------------------------------------------------------------- -- File dualram_512x8.vhd | -- | -- Description Instantiation of a template ProAsic3 RAM4K9 memory component with | -- o word width: 8 bits and | -- o depth : 512 bytes. | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 15/12/2010 | -- Version v0.02 | -- Depends on ProASIC3 lib | ---------------- | -- Last changes | -- 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the | -- address is given (otherwise it was 2 clock cycles later) slack | -- checked and is ok! code cleaned-up and commented | -- 15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Component specific library library PROASIC3; -- ProASIC3 library use PROASIC3.all; --================================================================================================= -- Entity declaration for dualram_512x8 --================================================================================================= entity dualram_512x8 is port( -- INPUTS -- Inputs concerning port A CLKA : in std_logic; -- clock A for synchronous read/ write operations ADDRA : in std_logic_vector (8 downto 0); -- address A DINA : in std_logic_vector (7 downto 0); -- data in A RWA : in std_logic; -- read/ write mode; 1 for reading, 0 for writing -- Inputs concerning port B CLKB : in std_logic; -- clock B for synchronous read/ write operations ADDRB : in std_logic_vector (8 downto 0); -- address B DINB : in std_logic_vector (7 downto 0); -- data in B RWB : in std_logic; -- read/ write mode; 1 for reading, 0 for writing -- Reset RESETn : in std_logic; -- sets all outputs low; does not reset the memory -- OUTPUTS -- Output concerning port A DOUTA : out std_logic_vector (7 downto 0); -- data out A -- Output concerning port B DOUTB : out std_logic_vector (7 downto 0));-- data out B end dualram_512x8; --================================================================================================= -- architecture declaration --================================================================================================= architecture RAM4K9 of dualram_512x8 is --------------------------------------------------------------------------------------------------- -- General information concerning RAM4K9: a fully synchronous, true dual-port RAM with an optional -- pipeline stage. It provides variable aspect ratios of 4096 x 1, 2048 x 2, 1024 x 4 and 512 x 9. -- Both ports are capable of reading and writing, making it possible to write with both ports or -- read with both ports simultaneously. Moreover, reading from one port while writing to the other -- is possible. -- WIDTHA0, WIDTHA1 and WIDTHB0, WIDTHB1: -- Aspect ratio configuration. -- WENA, WENB: -- Switching between Read and Write modes for the respective ports. -- A Low indicates Write operation and a High indicates a Read. -- BLKA, BLKB: -- Active low enable for the respective ports. -- PIPEA, PIPEB: -- Control of the optional pipeline stages. -- A Low on the PIPEA or PIPEB indicates a non-pipelined Read and the data appears on the output -- in the same clock cycle. -- A High indicates a pipelined Read and data appears on the output in the next clock cycle. -- WMODEA, WMODEB: -- Configuration of the behavior of the output when the RAM is in the Write mode. -- A Low on this signal makes the output retain data from the previous Read. A High indicates a -- pass-through behavior where the data being written will appear on the output immediately. component RAM4K9 generic (MEMORYFILE : string := ""); port( ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6, ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0, ADDRB11, ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6, ADDRB5, ADDRB4, ADDRB3, ADDRB2, ADDRB1, ADDRB0, DINA8, DINA7, DINA6, DINA5, DINA4, DINA3, DINA2, DINA1, DINA0, DINB8, DINB7, DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0, WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1, PIPEA, PIPEB, WMODEA, WMODEB, BLKA, BLKB, WENA, WENB, CLKA, CLKB, RESET : in std_logic := 'U'; ---------------------------------------------------- DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0, DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic); ---------------------------------------------------- end component; --------------------------------------------------------------------------------------------------- -- Instantiation of the component VCC component VCC port (Y : out std_logic); end component; --------------------------------------------------------------------------------------------------- -- Instantiation of the component GND component GND port (Y : out std_logic); end component; --------------------------------------------------------------------------------------------------- signal POWER, GROUND : std_logic; --================================================================================================= -- architecture begin --================================================================================================= begin power_supply_signal : VCC port map(Y => POWER); ground_signal : GND port map(Y => GROUND); --------------------------------------------------------------------------------------------------- -- Instantiation of the component RAM4K9. -- The following configuration has been applied: -- o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC) -- o word width : 8 bits (DINA8, DINB8: GND; DOUTA8, DOUTB8 : open) -- o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9: GND) -- o BLKA, BLKB : GND (ports enabled) -- o PIPEA, PIPEB : GND (not pipelined read) -- o WMODEA, WMODEB: GND (in write mode the output retains the data from the previous read) A9D8DualClkRAM_R0C0 : RAM4K9 port map( -- INPUTS -- inputs concerning port A -- data in A (1 byte, (7 downto 0)) DINA8 => GROUND, DINA7 => DINA(7), DINA6 => DINA(6), DINA5 => DINA(5), DINA4 => DINA(4), DINA3 => DINA(3), DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0), -- address A (512 bytes depth, (8 downto 0)) ADDRA11 => GROUND, ADDRA10 => GROUND, ADDRA9 => GROUND, ADDRA8 => ADDRA(8), ADDRA7 => ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5), ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 => ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0), -- read/ write mode for A WENA => RWA, -- clock for A CLKA => CLKA, -- aspect ratio, block, pipeline, write mode configurations for port A WIDTHA0 => POWER, WIDTHA1 => POWER, BLKA => GROUND, PIPEA => GROUND, WMODEA => GROUND, -- inputs concerning port B -- data in B (1 byte, (7 downto 0)) DINB8 => GROUND, DINB7 => DINB(7), DINB6 => DINB(6), DINB5 => DINB(5), DINB4 => DINB(4), DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1), DINB0 => DINB(0), -- address B (512 bytes depth, (8 downto 0)) ADDRB11 => GROUND, ADDRB10 => GROUND, ADDRB9 => GROUND, ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7), ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 => ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2), ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), -- read/ write mode for B WENB => RWB, -- clock for B CLKB => CLKB, -- aspect ratio, block, pipeline, write mode configurations for port B WIDTHB0 => POWER, WIDTHB1 => POWER, BLKB => GROUND, PIPEB => GROUND, WMODEB => GROUND, -- input reset RESET => RESETn, ------------------------------- -- OUTPUTS -- output concerning port A -- data out A (1 byte) DOUTA8 => open, DOUTA7 => DOUTA(7), DOUTA6 => DOUTA(6), DOUTA5 => DOUTA(5), DOUTA4 => DOUTA(4), DOUTA3 => DOUTA(3), DOUTA2 => DOUTA(2), DOUTA1 => DOUTA(1), DOUTA0 => DOUTA(0), -- output concerning port B -- data out B (1 byte) DOUTB8 => open, DOUTB7 => DOUTB(7), DOUTB6 => DOUTB(6), DOUTB5 => DOUTB(5), DOUTB4 => DOUTB(4), DOUTB3 => DOUTB(3), DOUTB2 => DOUTB(2), DOUTB1 => DOUTB(1), DOUTB0 => DOUTB(0)); ------------------------------- end RAM4K9; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

f7a88a4e17290e62410ad44d0fe322b1

wltr/cern-fgclite

critical_fpga/src/rtl/cf/fetch_page/fetch_page_sram_adc.vhd

------------------------------------------------------------------------------- --! @file fetch_page_sram_adc.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-19 --! @brief Prepare SRAM page with ADC data for NanoFIP communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --! @brief Entity declaration of fetch_page_sram_adc --! @details --! This component prepares the SRAM ADC log page for the NanoFIP response. entity fetch_page_sram_adc is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Commands --! @{ --! Start flag start_i : in std_ulogic; --! Done flag done_o : out std_ulogic; --! @} --! @name Memory page interface --! @{ --! Address page_addr_o : out std_ulogic_vector(5 downto 0); --! Write enable page_wr_en_o : out std_ulogic; --! Data output page_data_o : out std_ulogic_vector(7 downto 0); --! Done flag page_done_i : in std_ulogic; --! @} --! @name External SRAM data --! @{ -- Address sram_addr_o : out std_ulogic_vector(4 downto 0); --! Read request sram_rd_en_o : out std_ulogic; --! Data input sram_data_i : in std_ulogic_vector(23 downto 0); --! Data input enable sram_data_en_i : in std_ulogic); --! @} end entity fetch_page_sram_adc; --! RTL implementation of fetch_page_sram_adc architecture rtl of fetch_page_sram_adc is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type state_t is (IDLE, WRITE_LOW, WRITE_MIDDLE, WAIT_MIDDLE, WRITE_HIGH, DONE); type reg_t is record state : state_t; idx : unsigned(4 downto 0); addr : unsigned(5 downto 0); data : std_ulogic_vector(7 downto 0); wr_en : std_ulogic; rd_en : std_ulogic; done : std_ulogic; end record; constant init_c : reg_t := ( state => IDLE, idx => (others => '0'), addr => (others => '0'), data => (others => '0'), wr_en => '0', rd_en => '0', done => '0'); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal next_reg : reg_t; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- page_addr_o <= std_ulogic_vector(reg.addr); page_wr_en_o <= reg.wr_en; page_data_o <= reg.data; sram_addr_o <= std_ulogic_vector(reg.idx); sram_rd_en_o <= reg.rd_en; done_o <= reg.done; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= init_c; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else reg <= next_reg; end if; end if; end process regs; --------------------------------------------------------------------------- -- Combinatorics --------------------------------------------------------------------------- comb : process (reg, start_i, page_done_i, sram_data_i, sram_data_en_i) is begin -- comb -- Defaults next_reg <= reg; next_reg.rd_en <= '0'; next_reg.wr_en <= '0'; next_reg.done <= '0'; case reg.state is when IDLE => if start_i = '1' then next_reg.rd_en <= '1'; next_reg.state <= WRITE_LOW; end if; when WRITE_LOW => if sram_data_en_i = '1' then next_reg.data <= sram_data_i(7 downto 0); next_reg.wr_en <= '1'; end if; if page_done_i = '1' then next_reg.addr <= reg.addr + 1; next_reg.state <= WRITE_MIDDLE; end if; when WRITE_MIDDLE => next_reg.data <= sram_data_i(15 downto 8); next_reg.wr_en <= '1'; next_reg.state <= WAIT_MIDDLE; when WAIT_MIDDLE => if page_done_i = '1' then next_reg.addr <= reg.addr + 1; next_reg.state <= WRITE_HIGH; end if; when WRITE_HIGH => next_reg.data <= sram_data_i(23 downto 16); next_reg.wr_en <= '1'; next_reg.state <= DONE; when DONE => if page_done_i = '1' then if to_integer(reg.idx) < 19 then next_reg.addr <= reg.addr + 1; next_reg.idx <= reg.idx + 1; next_reg.rd_en <= '1'; next_reg.state <= WRITE_LOW; else next_reg <= init_c; next_reg.done <= '1'; end if; end if; end case; end process comb; end architecture rtl;

mit

5ee535a25ad0212c0e878974951073cf

preusser/q27

src/vhdl/PoC/common/config.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Global configuration settings. -- -- Description: -- ------------------------------------- -- This file evaluates the settings declared in the project specific package my_config. -- See also template file my_config.vhdl.template. -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; package config_private is -- TODO: -- =========================================================================== subtype T_BOARD_STRING is string(1 to 16); subtype T_BOARD_CONFIG_STRING is string(1 to 64); subtype T_DEVICE_STRING is string(1 to 32); -- Data structures to describe UART / RS232 type T_BOARD_UART_DESC is record IsDTE : boolean; -- Data terminal Equipment (e.g. PC, Printer) FlowControl : T_BOARD_CONFIG_STRING; -- (NONE, SW, HW_CTS_RTS, HW_RTR_RTS) BaudRate : T_BOARD_CONFIG_STRING; -- e.g. "115.2 kBd" BaudRate_Max : T_BOARD_CONFIG_STRING; end record; -- Data structures to describe Ethernet type T_BOARD_ETHERNET_DESC is record IPStyle : T_BOARD_CONFIG_STRING; RS_DataInterface : T_BOARD_CONFIG_STRING; PHY_Device : T_BOARD_CONFIG_STRING; PHY_DeviceAddress : std_logic_vector(7 downto 0); PHY_DataInterface : T_BOARD_CONFIG_STRING; PHY_ManagementInterface : T_BOARD_CONFIG_STRING; end record; subtype T_BOARD_ETHERNET_DESC_INDEX is natural range 0 to 7; type T_BOARD_ETHERNET_DESC_VECTOR is array(natural range <>) of T_BOARD_ETHERNET_DESC; -- Data structures to describe a board layout type T_BOARD_INFO is record BoardName : T_BOARD_CONFIG_STRING; FPGADevice : T_BOARD_CONFIG_STRING; UART : T_BOARD_UART_DESC; Ethernet : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX); EthernetCount : T_BOARD_ETHERNET_DESC_INDEX; end record; type T_BOARD_INFO_VECTOR is array (natural range <>) of T_BOARD_INFO; constant C_POC_NUL : character; constant C_BOARD_STRING_EMPTY : T_BOARD_STRING; constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING; constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING; constant C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR; function conf(str : string) return T_BOARD_CONFIG_STRING; end package; package body config_private is constant C_POC_NUL : character := '~'; constant C_BOARD_STRING_EMPTY : T_BOARD_STRING := (others => C_POC_NUL); constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING := (others => C_POC_NUL); constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING := (others => C_POC_NUL); function conf(str : string) return T_BOARD_CONFIG_STRING is constant ConstNUL : string(1 to 1) := (others => C_POC_NUL); variable Result : string(1 to T_BOARD_CONFIG_STRING'length); begin Result := (others => C_POC_NUL); if (str'length > 0) then Result(1 to imin(T_BOARD_CONFIG_STRING'length, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(T_BOARD_CONFIG_STRING'length, str'length)), ConstNUL); end if; return Result; end function; constant C_BOARD_ETHERNET_DESC_EMPTY : T_BOARD_ETHERNET_DESC := ( IPStyle => C_BOARD_CONFIG_STRING_EMPTY, RS_DataInterface => C_BOARD_CONFIG_STRING_EMPTY, PHY_Device => C_BOARD_CONFIG_STRING_EMPTY, PHY_DeviceAddress => x"00", PHY_DataInterface => C_BOARD_CONFIG_STRING_EMPTY, PHY_ManagementInterface => C_BOARD_CONFIG_STRING_EMPTY ); -- predefined UART descriptions function brd_CreateUART(IsDTE : boolean; FlowControl : string; BaudRate : string; BaudRate_Max : string := "") return T_BOARD_UART_DESC is variable Result : T_BOARD_UART_DESC; begin Result.IsDTE := IsDTE; Result.FlowControl := conf(FlowControl); Result.BaudRate := conf(BaudRate); Result.BaudRate_Max := ite((BaudRate_Max = ""), conf(BaudRate), conf(BaudRate_Max)); return Result; end function; -- IsDTE FlowControl BaudRate constant C_BOARD_UART_EMPTY : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "0 Bd"); constant C_BOARD_UART_DTE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "115.2 kBd"); constant C_BOARD_UART_DCE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "115.2 kBd"); constant C_BOARD_UART_DCE_115200_HWCTS : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "HW_CTS_RTS", "115.2 kBd"); constant C_BOARD_UART_DCE_460800_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "460.8 kBd"); constant C_BOARD_UART_DTE_921600_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "921.6 kBd"); function brd_CreateEthernet(IPStyle : string; RS_DataInt : string; PHY_Device : string; PHY_DevAddress : std_logic_vector(7 downto 0); PHY_DataInt : string; PHY_MgntInt : string) return T_BOARD_ETHERNET_DESC is variable Result : T_BOARD_ETHERNET_DESC; begin Result.IPStyle := conf(IPStyle); Result.RS_DataInterface := conf(RS_DataInt); Result.PHY_Device := conf(PHY_Device); Result.PHY_DeviceAddress := PHY_DevAddress; Result.PHY_DataInterface := conf(PHY_DataInt); Result.PHY_ManagementInterface := conf(PHY_MgntInt); return Result; end function; constant C_BOARD_ETH_EMPTY : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("", "", "", x"00", "", ""); constant C_BOARD_ETH_SOFT_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO"); constant C_BOARD_ETH_HARD_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("HARD", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO"); constant C_BOARD_ETH_SOFT_SGMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "SGMII", "MDIO_OVER_IIC"); constant C_BOARD_ETH_NONE : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX) := (others => C_BOARD_ETH_EMPTY); -- Board Descriptions -- =========================================================================== constant C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := ( ( BoardName => conf("GENERIC"), FPGADevice => conf("GENERIC"), -- GENERIC UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY ), EthernetCount => 1 ), -- Altera boards -- ========================================================================= ( BoardName => conf("DE0"), FPGADevice => conf("EP3C16F484"), -- EP3C16F484 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("S2GXAV"), FPGADevice => conf("EP2SGX90FF1508C3"), -- EP2SGX90FF1508C3 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("DE4"), FPGADevice => conf("EP4SGX230KF40C2"), -- EP4SGX230KF40C2 UART => C_BOARD_UART_DCE_460800_NONE, Ethernet => ( 0 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"00", "RGMII", "MDIO"), 1 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"01", "RGMII", "MDIO"), 2 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"02", "RGMII", "MDIO"), 3 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"03", "RGMII", "MDIO"), others => C_BOARD_ETH_EMPTY ), EthernetCount => 4 ),( BoardName => conf("DE5"), FPGADevice => conf("EP5SGXEA7N2F45C2"), -- EP5SGXEA7N2F45C2 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ), -- Lattice boards -- ========================================================================= ( BoardName => conf("ECP5 Versa"), FPGADevice => conf("LFE5UM-45F-6BG381C"), -- LFE5UM-45F-6BG381C UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ), -- Xilinx boards -- ========================================================================= ( BoardName => conf("S3SK200"), FPGADevice => conf("XC3S200FT256"), -- XC2S200FT256 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("S3ESK500"), FPGADevice => conf("XC3S500EFT256"), -- XC2S500FT256 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("S3SK1000"), FPGADevice => conf("XC3S1000FT256"), -- XC2S1000FT256 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("S3ESK1600"), FPGADevice => conf("XC3S1600EFT256"), -- XC2S1600FT256 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("ATLYS"), FPGADevice => conf("XC6SLX45-3CSG324"), -- XC6SLX45-3CSG324 UART => C_BOARD_UART_DCE_460800_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("ZC706"), FPGADevice => conf("XC7Z045-2FFG900"), -- XC7Z045-2FFG900C UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("ZedBoard"), FPGADevice => conf("XC7Z020-1CLG484"), -- XC7Z020-1CLG484 UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("AC701"), FPGADevice => conf("XC7A200T-2FBG676C"), -- XC7A200T-2FBG676C UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => ( 0 => C_BOARD_ETH_SOFT_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("KC705"), FPGADevice => conf("XC7K325T-2FFG900C"), -- XC7K325T-2FFG900C UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => ( 0 => C_BOARD_ETH_SOFT_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("ML505"), FPGADevice => conf("XC5VLX50T-1FF1136"), -- XC5VLX50T-1FF1136 UART => C_BOARD_UART_DCE_115200_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("ML506"), FPGADevice => conf("XC5VSX50T-1FFG1136"), -- XC5VSX50T-1FFG1136 UART => C_BOARD_UART_DCE_115200_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("ML507"), FPGADevice => conf("XC5VFX70T-1FFG1136"), -- XC5VFX70T-1FFG1136 UART => C_BOARD_UART_DCE_115200_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("XUPV5"), FPGADevice => conf("XC5VLX110T-1FF1136"), -- XC5VLX110T-1FF1136 UART => C_BOARD_UART_DCE_115200_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("ML605"), FPGADevice => conf("XC6VLX240T-1FF1156"), -- XC6VLX240T-1FF1156 UART => C_BOARD_UART_EMPTY, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("VC707"), FPGADevice => conf("XC7VX485T-2FFG1761C"), -- XC7VX485T-2FFG1761C UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => ( 0 => C_BOARD_ETH_SOFT_SGMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("VC709"), FPGADevice => conf("XC7VX690T-2FFG1761C"), -- XC7VX690T-2FFG1761C UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ), -- Custom Board (MUST BE LAST ONE) -- ========================================================================= ( BoardName => conf("Custom"), FPGADevice => conf("Device is unknown for a custom board"), UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ) ); end package body; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use PoC.my_config.all; use PoC.my_project.all; use PoC.config_private.all; use PoC.utils.all; package config is constant PROJECT_DIR : string := MY_PROJECT_DIR; constant OPERATING_SYSTEM : string := MY_OPERATING_SYSTEM; -- List of known FPGA / Chip vendors -- --------------------------------------------------------------------------- type T_VENDOR is ( VENDOR_UNKNOWN, VENDOR_GENERIC, VENDOR_ALTERA, VENDOR_LATTICE, VENDOR_XILINX ); -- List of known synthesis tool chains -- --------------------------------------------------------------------------- type T_SYNTHESIS_TOOL is ( SYNTHESIS_TOOL_UNKNOWN, SYNTHESIS_TOOL_GENERIC, SYNTHESIS_TOOL_ALTERA_QUARTUS2, SYNTHESIS_TOOL_LATTICE_LSE, SYNTHESIS_TOOL_SYNOPSIS, SYNTHESIS_TOOL_XILINX_XST, SYNTHESIS_TOOL_XILINX_VIVADO ); -- List of known device families -- --------------------------------------------------------------------------- type T_DEVICE_FAMILY is ( DEVICE_FAMILY_UNKNOWN, DEVICE_FAMILY_GENERIC, -- Altera DEVICE_FAMILY_ARRIA, DEVICE_FAMILY_CYCLONE, DEVICE_FAMILY_STRATIX, -- Lattice DEVICE_FAMILY_ICE, DEVICE_FAMILY_MACHXO, DEVICE_FAMILY_ECP, -- Xilinx DEVICE_FAMILY_SPARTAN, DEVICE_FAMILY_ZYNQ, DEVICE_FAMILY_ARTIX, DEVICE_FAMILY_KINTEX, DEVICE_FAMILY_VIRTEX ); type T_DEVICE_SERIES is ( DEVICE_SERIES_UNKNOWN, DEVICE_SERIES_GENERIC, -- Xilinx FPGA series DEVICE_SERIES_7_SERIES, DEVICE_SERIES_ULTRASCALE, DEVICE_SERIES_ULTRASCALE_PLUS ); -- List of known devices -- --------------------------------------------------------------------------- type T_DEVICE is ( DEVICE_UNKNOWN, DEVICE_GENERIC, -- Altera DEVICE_MAX2, DEVICE_MAX10, -- Altera.Max DEVICE_ARRIA1, DEVICE_ARRIA2, DEVICE_ARRIA5, DEVICE_ARRIA10, -- Altera.Arria DEVICE_CYCLONE1, DEVICE_CYCLONE2, DEVICE_CYCLONE3, DEVICE_CYCLONE4, -- Altera.Cyclone DEVICE_CYCLONE5, -- DEVICE_STRATIX1, DEVICE_STRATIX2, DEVICE_STRATIX3, DEVICE_STRATIX4, -- Altera.Stratix DEVICE_STRATIX5, DEVICE_STRATIX10, -- -- Lattice DEVICE_ICE40, DEVICE_ICE65, DEVICE_ICE5, -- Lattice.iCE DEVICE_MACHXO, DEVICE_MACHXO2, -- Lattice.MachXO DEVICE_ECP3, DEVICE_ECP4, DEVICE_ECP5, -- Lattice.ECP -- Xilinx DEVICE_SPARTAN3, DEVICE_SPARTAN6, -- Xilinx.Spartan DEVICE_ZYNQ7, DEVICE_ZYNQ_ULTRA_PLUS, -- Xilinx.Zynq DEVICE_ARTIX7, -- Xilinx.Artix DEVICE_KINTEX7, DEVICE_KINTEX_ULTRA, DEVICE_KINTEX_ULTRA_PLUS, -- Xilinx.Kintex DEVICE_VIRTEX5, DEVICE_VIRTEX6, DEVICE_VIRTEX7, -- Xilinx.Virtex DEVICE_VIRTEX_ULTRA, DEVICE_VIRTEX_ULTRA_PLUS -- ); -- List of known device subtypes -- --------------------------------------------------------------------------- type T_DEVICE_SUBTYPE is ( DEVICE_SUBTYPE_NONE, DEVICE_SUBTYPE_GENERIC, -- Altera DEVICE_SUBTYPE_E, DEVICE_SUBTYPE_GS, DEVICE_SUBTYPE_GX, DEVICE_SUBTYPE_GT, -- Lattice DEVICE_SUBTYPE_U, DEVICE_SUBTYPE_UM, -- Xilinx DEVICE_SUBTYPE_X, DEVICE_SUBTYPE_T, DEVICE_SUBTYPE_XT, DEVICE_SUBTYPE_HT, DEVICE_SUBTYPE_LX, DEVICE_SUBTYPE_SXT, DEVICE_SUBTYPE_LXT, DEVICE_SUBTYPE_TXT, DEVICE_SUBTYPE_FXT, DEVICE_SUBTYPE_CXT, DEVICE_SUBTYPE_HXT ); -- List of known transceiver (sub-)types -- --------------------------------------------------------------------------- type T_TRANSCEIVER is ( TRANSCEIVER_NONE, TRANSCEIVER_GENERIC, -- TODO: add more? Altera transceivers -- Altera transceivers TRANSCEIVER_GXB, -- Altera GXB transceiver --Lattice transceivers TRANSCEIVER_MGT, -- Lattice transceiver -- Xilinx transceivers TRANSCEIVER_GTP_DUAL, TRANSCEIVER_GTPE1, TRANSCEIVER_GTPE2, -- Xilinx GTP transceivers TRANSCEIVER_GTX, TRANSCEIVER_GTXE1, TRANSCEIVER_GTXE2, -- Xilinx GTX transceivers TRANSCEIVER_GTH, TRANSCEIVER_GTHE1, TRANSCEIVER_GTHE2, -- Xilinx GTH transceivers TRANSCEIVER_GTZ, -- Xilinx GTZ transceivers TRANSCEIVER_GTY -- Xilinx GTY transceivers ); -- Properties of an FPGA architecture -- =========================================================================== type T_DEVICE_INFO is record Vendor : T_VENDOR; Device : T_DEVICE; DevFamily : T_DEVICE_FAMILY; DevGeneration : natural; DevNumber : natural; DevSubType : T_DEVICE_SUBTYPE; DevSeries : T_DEVICE_SERIES; TransceiverType : T_TRANSCEIVER; LUT_FanIn : positive; end record; -- Functions extracting board and PCB properties from "MY_BOARD" -- which is declared in package "my_config". -- =========================================================================== function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return natural; function BOARD_INFO(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD_INFO; function BOARD_NAME(BoardConfig : string := C_BOARD_STRING_EMPTY) return string; function BOARD_DEVICE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string; function BOARD_UART_BAUDRATE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string; -- Functions extracting device and architecture properties from "MY_DEVICE" -- which is declared in package "my_config". -- =========================================================================== function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR; function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL; function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE; function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY; function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE; function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES; function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural; function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural; function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER; function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive; function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO; -- force FSM to predefined encoding in debug mode function getFSMEncoding_gray(debug : boolean) return string; end package; package body config is -- inlined function from PoC.utils, to break dependency -- =========================================================================== function ite(cond : boolean; value1 : string; value2 : string) return string is begin if cond then return value1; else return value2; end if; end function; -- chr_is* function function chr_isDigit(chr : character) return boolean is begin return ((character'pos('0') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('9'))); end function; function chr_isAlpha(chr : character) return boolean is begin return (((character'pos('a') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('z'))) or ((character'pos('A') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('Z')))); end function; function str_length(str : string) return natural is begin for i in str'range loop if (str(i) = C_POC_NUL) then return i - str'low; end if; end loop; return str'length; end function; function str_trim(str : string) return string is begin for i in str'range loop if (str(i) = C_POC_NUL) then return str(str'low to i-1); end if; end loop; return str; end function; function str_imatch(str1 : string; str2 : string) return boolean is constant len : natural := imin(str1'length, str2'length); variable chr1 : character; variable chr2 : character; begin -- if both strings are empty if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if; -- compare char by char for i in 0 to len-1 loop chr1 := str1(str1'low + i); chr2 := str2(str2'low + i); if (character'pos('A') <= CHARACTER'pos(chr1)) and (character'pos(chr1) <= CHARACTER'pos('Z')) then chr1 := character'val(CHARACTER'pos(chr1) - character'pos('A') + CHARACTER'pos('a')); end if; if (character'pos('A') <= CHARACTER'pos(chr2)) and (character'pos(chr2) <= CHARACTER'pos('Z')) then chr2 := character'val(CHARACTER'pos(chr2) - character'pos('A') + CHARACTER'pos('a')); end if; if (chr1 /= chr2) then return FALSE; elsif ((chr1 = C_POC_NUL) xor (chr2 = C_POC_NUL)) then return FALSE; elsif ((chr1 = C_POC_NUL) and (chr2 = C_POC_NUL)) then return TRUE; end if; end loop; -- check special cases, if ((str1'length = len) and (str2'length = len)) then -- both strings are fully consumed and equal return TRUE; elsif (str1'length > len) then return (str1(str1'low + len) = C_POC_NUL); -- str1 is longer, but str_length equals len else return (str2(str2'low + len) = C_POC_NUL); -- str2 is longer, but str_length equals len end if; end function; function str_find(str : string; pattern : string; start : natural := 0) return boolean is begin for i in imax(str'low, start) to (str'high - pattern'length + 1) loop exit when (str(i) = C_POC_NUL); if (str(i to i + pattern'length - 1) = pattern) then return TRUE; end if; end loop; return FALSE; end function; -- private functions required by board description -- ModelSim requires that this functions is defined before it is used below. -- =========================================================================== function getLocalDeviceString(DeviceString : string) return string is constant ConstNUL : string(1 to 1) := (others => C_POC_NUL); constant MY_DEVICE_STR : string := BOARD_DEVICE; variable Result : string(1 to T_DEVICE_STRING'length); begin Result := (others => C_POC_NUL); -- report DeviceString for debugging if (POC_VERBOSE = TRUE) then report "getLocalDeviceString: DeviceString='" & str_trim(DeviceString) & "' MY_DEVICE='" & str_trim(MY_DEVICE) & "' MY_DEVICE_STR='" & str_trim(MY_DEVICE_STR) & "'" severity NOTE; end if; -- if DeviceString is populated if ((str_length(DeviceString) /= 0) and (str_imatch(DeviceString, "None") = FALSE)) then Result(1 to imin(T_DEVICE_STRING'length, imax(1, DeviceString'length))) := ite((DeviceString'length > 0), DeviceString(1 to imin(T_DEVICE_STRING'length, DeviceString'length)), ConstNUL); -- if MY_DEVICE is set, prefer it elsif ((str_length(MY_DEVICE) /= 0) and (str_imatch(MY_DEVICE, "None") = FALSE)) then Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE'length))) := ite((MY_DEVICE'length > 0), MY_DEVICE(1 to imin(T_DEVICE_STRING'length, MY_DEVICE'length)), ConstNUL); -- otherwise use MY_BOARD else Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE_STR'length))) := ite((MY_DEVICE_STR'length > 0), MY_DEVICE_STR(1 to imin(T_DEVICE_STRING'length, MY_DEVICE_STR'length)), ConstNUL); end if; return Result; end function; function extractFirstNumber(str : string) return natural is variable low : integer; variable high : integer; variable Result : natural; variable Digit : integer; begin low := -1; high := -1; for i in str'low to str'high loop if chr_isDigit(str(i)) then low := i; exit; end if; end loop; -- abort if no digit can be found if (low = -1) then return 0; end if; for i in (low + 1) to str'high loop if chr_isAlpha(str(i)) then high := i - 1; exit; end if; end loop; if (high = -1) then return 0; end if; -- return INTEGER'value(str(low to high)); -- 'value(...) is not supported by Vivado Synth 2014.1 -- convert substring to a number for i in low to high loop if (chr_isDigit(str(i)) = FALSE) then return 0; end if; Result := (Result * 10) + (character'pos(str(i)) - character'pos('0')); end loop; return Result; end function; -- Public functions -- =========================================================================== -- TODO: comment function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return natural is constant MY_BRD : T_BOARD_CONFIG_STRING := ite((BoardConfig /= C_BOARD_STRING_EMPTY), conf(BoardConfig), conf(MY_BOARD)); constant BOARD_NAME : string := str_trim(MY_BRD); begin if (POC_VERBOSE = TRUE) then report "PoC configuration: Used board is '" & BOARD_NAME & "'" severity NOTE; end if; for i in C_BOARD_INFO_LIST'range loop if str_imatch(BOARD_NAME, C_BOARD_INFO_LIST(i).BoardName) then return i; end if; end loop; report "Unknown board name in MY_BOARD = " & MY_BRD & "." severity failure; return C_BOARD_INFO_LIST'high; end function; function BOARD_INFO(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD_INFO is constant BRD : natural := BOARD(BoardConfig); begin return C_BOARD_INFO_LIST(BRD); end function; -- TODO: comment function BOARD_NAME(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is constant BRD : natural := BOARD(BoardConfig); begin return str_trim(C_BOARD_INFO_LIST(BRD).BoardName); end function; -- TODO: comment function BOARD_DEVICE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is constant BRD : natural := BOARD(BoardConfig); begin return str_trim(C_BOARD_INFO_LIST(BRD).FPGADevice); end function; function BOARD_UART_BAUDRATE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is constant BRD : natural := BOARD(BoardConfig); begin return str_trim(C_BOARD_INFO_LIST(BRD).UART.BaudRate); end function; -- purpose: extract vendor from MY_DEVICE function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant VEN_STR2 : string(1 to 2) := MY_DEV(1 to 2); -- TODO: test if alias declarations also work out on all platforms constant VEN_STR3 : string(1 to 3) := MY_DEV(1 to 3); -- TODO: test if alias declarations also work out on all platforms begin case VEN_STR2 is when "GE" => return VENDOR_GENERIC; when "EP" => return VENDOR_ALTERA; when "XC" => return VENDOR_XILINX; when others => null; end case; case VEN_STR3 is when "iCE" => return VENDOR_LATTICE; -- iCE devices when "LCM" => return VENDOR_LATTICE; -- MachXO device when "LFE" => return VENDOR_LATTICE; -- ECP devices when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL is constant VEN : T_VENDOR := VENDOR(DeviceString); begin case VEN is when VENDOR_GENERIC => return SYNTHESIS_TOOL_GENERIC; when VENDOR_ALTERA => return SYNTHESIS_TOOL_ALTERA_QUARTUS2; when VENDOR_LATTICE => return SYNTHESIS_TOOL_LATTICE_LSE; --return SYNTHESIS_TOOL_SYNOPSIS; when VENDOR_XILINX => if (1 fs /= 1 us) then return SYNTHESIS_TOOL_XILINX_XST; else return SYNTHESIS_TOOL_XILINX_VIVADO; end if; when others => return SYNTHESIS_TOOL_UNKNOWN; end case; end function; -- purpose: extract device from MY_DEVICE function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant VEN : T_VENDOR := VENDOR(DeviceString); constant DEV_STR : string(3 to 4) := MY_DEV(3 to 4); -- TODO: test if alias declarations also work out on all platforms begin case VEN is when VENDOR_GENERIC => if (MY_DEV(1 to 7) = "GENERIC") then return DEVICE_GENERIC; else report "Unknown Generic device in MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when VENDOR_ALTERA => case DEV_STR is when "1C" => return DEVICE_CYCLONE1; when "2C" => return DEVICE_CYCLONE2; when "3C" => return DEVICE_CYCLONE3; when "1S" => return DEVICE_STRATIX1; when "2S" => return DEVICE_STRATIX2; when "4S" => return DEVICE_STRATIX4; when "5S" => return DEVICE_STRATIX5; when others => report "Unknown Altera device in MY_DEVICE = '" & MY_DEV & "'" severity failure; end case; when VENDOR_LATTICE => if (MY_DEV(1 to 6) = "LCMX02") then return DEVICE_MACHXO2; elsif (MY_DEV(1 to 5) = "LCMX0") then return DEVICE_MACHXO; elsif (MY_DEV(1 to 5) = "iCE40") then return DEVICE_ICE40; elsif (MY_DEV(1 to 5) = "iCE65") then return DEVICE_ICE65; elsif (MY_DEV(1 to 4) = "iCE5") then return DEVICE_ICE5; elsif (MY_DEV(1 to 4) = "LFE3") then return DEVICE_ECP3; elsif (MY_DEV(1 to 4) = "LFE4") then return DEVICE_ECP4; elsif (MY_DEV(1 to 4) = "LFE5") then return DEVICE_ECP5; else report "Unknown Lattice device in MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when VENDOR_XILINX => case DEV_STR is when "7A" => return DEVICE_ARTIX7; when "7K" => return DEVICE_KINTEX7; when "KU" => return DEVICE_KINTEX_ULTRA; when "3S" => return DEVICE_SPARTAN3; when "6S" => return DEVICE_SPARTAN6; when "5V" => return DEVICE_VIRTEX5; when "6V" => return DEVICE_VIRTEX6; when "7V" => return DEVICE_VIRTEX7; when "VU" => return DEVICE_VIRTEX_ULTRA; when "7Z" => return DEVICE_ZYNQ7; when others => report "Unknown Xilinx device in MY_DEVICE = '" & MY_DEV & "'" severity failure; end case; when others => report "Unknown vendor in MY_DEVICE = " & MY_DEV & "." severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; -- purpose: extract device from MY_DEVICE function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant VEN : T_VENDOR := VENDOR(DeviceString); constant FAM_CHAR : character := MY_DEV(4); begin case VEN is when VENDOR_GENERIC => return DEVICE_FAMILY_GENERIC; when VENDOR_ALTERA => case FAM_CHAR is when 'C' => return DEVICE_FAMILY_CYCLONE; when 'S' => return DEVICE_FAMILY_STRATIX; when others => report "Unknown Altera device family in MY_DEVICE = '" & MY_DEV & "'" severity failure; end case; when VENDOR_LATTICE => case FAM_CHAR is --when 'M' => return DEVICE_FAMILY_MACHXO; when 'E' => return DEVICE_FAMILY_ECP; when others => report "Unknown Lattice device family in MY_DEVICE = '" & MY_DEV & "'" severity failure; end case; when VENDOR_XILINX => case FAM_CHAR is when 'A' => return DEVICE_FAMILY_ARTIX; when 'K' => return DEVICE_FAMILY_KINTEX; when 'S' => return DEVICE_FAMILY_SPARTAN; when 'V' => return DEVICE_FAMILY_VIRTEX; when 'Z' => return DEVICE_FAMILY_ZYNQ; when others => report "Unknown Xilinx device family in MY_DEVICE = '" & MY_DEV & "'" severity failure; end case; when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; -- some devices share some common features: e.g. XADC, BlockRAM, ... function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant DEV : T_DEVICE := DEVICE(DeviceString); begin case DEV is when DEVICE_GENERIC => return DEVICE_SERIES_GENERIC; -- all Xilinx ****7 devices when DEVICE_ARTIX7 | DEVICE_KINTEX7 | DEVICE_VIRTEX7 | DEVICE_ZYNQ7 => return DEVICE_SERIES_7_SERIES; -- all Xilinx ****UltraScale devices when DEVICE_KINTEX_ULTRA | DEVICE_VIRTEX_ULTRA => return DEVICE_SERIES_ULTRASCALE; -- all Xilinx ****UltraScale+ devices when DEVICE_KINTEX_ULTRA_PLUS | DEVICE_VIRTEX_ULTRA_PLUS | DEVICE_ZYNQ_ULTRA_PLUS => return DEVICE_SERIES_ULTRASCALE_PLUS; when others => return DEVICE_SERIES_UNKNOWN; end case; end function; function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is constant SERIES : T_DEVICE_SERIES := DEVICE_SERIES(DeviceString); begin if (SERIES = DEVICE_SERIES_7_SERIES) then return 7; else return 0; end if; end function; function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant VEN : T_VENDOR := VENDOR(DeviceString); begin case VEN is when VENDOR_GENERIC => return 0; when VENDOR_ALTERA => return extractFirstNumber(MY_DEV(5 to MY_DEV'high)); when VENDOR_LATTICE => return extractFirstNumber(MY_DEV(6 to MY_DEV'high)); when VENDOR_XILINX => return extractFirstNumber(MY_DEV(5 to MY_DEV'high)); when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant DEV : T_DEVICE := DEVICE(MY_DEV); constant DEV_SUB_STR : string(1 to 2) := MY_DEV(5 to 6); -- WORKAROUND: for GHDL begin case DEV is when DEVICE_GENERIC => return DEVICE_SUBTYPE_GENERIC; -- TODO: extract Arria GX subtype when DEVICE_ARRIA1 => report "TODO: parse Arria device subtype." severity failure; return DEVICE_SUBTYPE_NONE; -- TODO: extract ArriaII GX,GZ subtype when DEVICE_ARRIA2 => report "TODO: parse ArriaII device subtype." severity failure; return DEVICE_SUBTYPE_NONE; -- TODO: extract ArriaV GX, GT, SX, GZ subtype when DEVICE_ARRIA5 => report "TODO: parse ArriaV device subtype." severity failure; return DEVICE_SUBTYPE_NONE; -- TODO: extract Arria10 GX, GT, SX subtype when DEVICE_ARRIA10 => report "TODO: parse Arria10 device subtype." severity failure; return DEVICE_SUBTYPE_NONE; -- Altera Cyclon I, II, III, IV, V devices have no subtype when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 | DEVICE_CYCLONE4 | DEVICE_CYCLONE5 => return DEVICE_SUBTYPE_NONE; when DEVICE_STRATIX2 => if chr_isDigit(DEV_SUB_STR(1)) then return DEVICE_SUBTYPE_NONE; elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX; else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_STRATIX4 => if (DEV_SUB_STR(1) = 'E') then return DEVICE_SUBTYPE_E; elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX; -- elsif (DEV_SUB_STR = "GT") then return DEVICE_SUBTYPE_GT; else report "Unknown Stratix IV subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; -- TODO: extract StratixV subtype when DEVICE_STRATIX5 => report "TODO: parse Stratix V device subtype." severity failure; return DEVICE_SUBTYPE_NONE; when DEVICE_ECP5 => if (DEV_SUB_STR(1) = 'U') then return DEVICE_SUBTYPE_U; elsif (DEV_SUB_STR = "UM") then return DEVICE_SUBTYPE_UM; else report "Unknown Lattice ECP5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_SPARTAN3 => report "TODO: parse Spartan3 / Spartan3E / Spartan3AN device subtype." severity failure; return DEVICE_SUBTYPE_NONE; when DEVICE_SPARTAN6 => if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_VIRTEX5 => if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT; elsif ((DEV_SUB_STR = "TX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_TXT; elsif ((DEV_SUB_STR = "FX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_FXT; else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_VIRTEX6 => if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT; elsif ((DEV_SUB_STR = "CX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_CXT; elsif ((DEV_SUB_STR = "HX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HXT; else report "Unknown Virtex-6 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_ARTIX7 => if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; else report "Unknown Artix-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_KINTEX7 => if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; else report "Unknown Kintex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_KINTEX_ULTRA => return DEVICE_SUBTYPE_NONE; when DEVICE_KINTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE; when DEVICE_VIRTEX7 => if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; elsif ((DEV_SUB_STR(1) = 'X') and ( str_find(MY_DEV(6 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_XT; elsif ((DEV_SUB_STR(1) = 'H') and ( str_find(MY_DEV(6 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HT; else report "Unknown Virtex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_VIRTEX_ULTRA => return DEVICE_SUBTYPE_NONE; when DEVICE_VIRTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE; when DEVICE_ZYNQ7 => return DEVICE_SUBTYPE_NONE; when DEVICE_ZYNQ_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE; when others => report "Device sub-type is unknown for the given device." severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant DEV : T_DEVICE := DEVICE(DeviceString); constant SERIES : T_DEVICE_SERIES := DEVICE_SERIES(DeviceString); begin case SERIES is when DEVICE_SERIES_GENERIC => return 6; when DEVICE_SERIES_7_SERIES | DEVICE_SERIES_ULTRASCALE | DEVICE_SERIES_ULTRASCALE_PLUS => return 6; when others => null; end case; case DEV is when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return 4; when DEVICE_STRATIX1 | DEVICE_STRATIX2 => return 4; when DEVICE_STRATIX4 | DEVICE_STRATIX5 => return 6; when DEVICE_ECP5 => return 4; when DEVICE_SPARTAN3 => return 4; when DEVICE_SPARTAN6 => return 6; when DEVICE_VIRTEX5 | DEVICE_VIRTEX6 => return 6; when others => report "LUT fan-in is unknown for the given device." severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant DEV : T_DEVICE := DEVICE(DeviceString); constant DEV_NUM : natural := DEVICE_NUMBER(DeviceString); constant DEV_SUB : T_DEVICE_SUBTYPE := DEVICE_SUBTYPE(DeviceString); begin case DEV is when DEVICE_GENERIC => return TRANSCEIVER_GENERIC; when DEVICE_MAX2 | DEVICE_MAX10 => return TRANSCEIVER_NONE; -- Altera MAX II, 10 devices have no transceivers when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return TRANSCEIVER_NONE; -- Altera Cyclon I, II, III devices have no transceivers when DEVICE_STRATIX2 => return TRANSCEIVER_GXB; when DEVICE_STRATIX4 => return TRANSCEIVER_GXB; --when DEVICE_STRATIX5 => return TRANSCEIVER_GXB; when DEVICE_ECP5 => return TRANSCEIVER_MGT; when DEVICE_SPARTAN3 => return TRANSCEIVER_NONE; -- Xilinx Spartan3 devices have no transceivers when DEVICE_SPARTAN6 => case DEV_SUB is when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE; when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTPE1; when others => report "Unknown Spartan-6 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure; end case; when DEVICE_VIRTEX5 => case DEV_SUB is when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE; when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTP_DUAL; when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTP_DUAL; when DEVICE_SUBTYPE_TXT => return TRANSCEIVER_GTX; when DEVICE_SUBTYPE_FXT => return TRANSCEIVER_GTX; when others => report "Unknown Virtex-5 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure; end case; when DEVICE_VIRTEX6 => case DEV_SUB is when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE; when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTXE1; when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTXE1; when DEVICE_SUBTYPE_HXT => return TRANSCEIVER_GTXE1; when others => report "Unknown Virtex-6 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure; end case; when DEVICE_ARTIX7 => return TRANSCEIVER_GTPE2; when DEVICE_KINTEX7 => return TRANSCEIVER_GTXE2; when DEVICE_VIRTEX7 => case DEV_SUB is when DEVICE_SUBTYPE_T => return TRANSCEIVER_GTXE2; when DEVICE_SUBTYPE_XT => if (DEV_NUM = 485) then return TRANSCEIVER_GTXE2; else return TRANSCEIVER_GTHE2; end if; when DEVICE_SUBTYPE_HT => return TRANSCEIVER_GTHE2; when others => report "Unknown Virtex-7 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure; end case; when DEVICE_ZYNQ7 => case DEV_NUM is when 10 | 20 => return TRANSCEIVER_NONE; when 15 => return TRANSCEIVER_GTPE2; when others => return TRANSCEIVER_GTXE2; end case; when others => report "Unknown device." severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; -- purpose: extract architecture properties from DEVICE function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO is variable Result : T_DEVICE_INFO; begin Result.Vendor := VENDOR(DeviceString); Result.Device := DEVICE(DeviceString); Result.DevFamily := DEVICE_FAMILY(DeviceString); Result.DevSubType := DEVICE_SUBTYPE(DeviceString); Result.DevSeries := DEVICE_SERIES(DeviceString); Result.DevGeneration := DEVICE_GENERATION(DeviceString); Result.DevNumber := DEVICE_NUMBER(DeviceString); Result.TransceiverType := TRANSCEIVER_TYPE(DeviceString); Result.LUT_FanIn := LUT_FANIN(DeviceString); return Result; end function; -- force FSM to predefined encoding in debug mode function getFSMEncoding_gray(debug : boolean) return string is begin if (debug = true) then return "gray"; else case VENDOR is when VENDOR_ALTERA => return "default"; --when VENDOR_LATTICE => return "default"; when VENDOR_XILINX => return "auto"; when others => report "Unknown vendor." severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end if; end function; end package body;

agpl-3.0

0616c1009eb9be89f88676e8265d82c0

malkadi/FGPU

bitstreams/settings_and_utilization/V2_2CUs_float.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 1; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data por0s constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

522896b227d45429c7091df95c7bafb7

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_no_float_area_estimation.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

e481914e4dad03e6266c90806db4bb1c

preusser/q27

src/vhdl/top/xilinx/s3sk_queens_uart.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity s3sk_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 9; COUNT_CYCLES : boolean := false; CLK_FREQ : positive := 50000000; CLK_MUL : positive := 22; CLK_DIV : positive := 13; BAUDRATE : positive := 115200; SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte ); port ( clkx : in std_logic; rstx : in std_logic; rx : in std_logic; tx : out std_logic; leds : out std_logic_vector(7 downto 0) ); end s3sk_queens_uart; library IEEE; use IEEE.numeric_std.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of s3sk_queens_uart is -- Global Control signal clk : std_logic; signal rst : std_logic; -- Solver Status signal avail : std_logic; begin ----------------------------------------------------------------------------- -- Generate Global Controls blkGlobal: block is signal clk_u : std_logic; -- Unbuffered Synthesized Clock signal rst_s : std_logic_vector(1 downto 0) := (others => '0'); begin -- Clock Generation DCM1 : DCM generic map ( CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ), CLKIN_DIVIDE_BY_2 => FALSE, PHASE_SHIFT => 0, CLKFX_MULTIPLY => CLK_MUL, CLKFX_DIVIDE => CLK_DIV, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", -- only using clkfx DLL_FREQUENCY_MODE => "LOW", DFS_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, STARTUP_WAIT => TRUE -- Delay until DCM LOCK ) port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => clk_u, CLKFX180 => open, LOCKED => open, PSDONE => open, STATUS => open, CLKFB => open, CLKIN => clkx, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => '0' ); clk_buf : BUFG port map ( I => clk_u, O => clk ); -- Reset Synchronization process(clk) begin if rising_edge(clk) then rst_s <= rstx & rst_s(rst_s'left downto 1); end if; end process; rst <= rst_s(0); end block blkGlobal; ---------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_uart generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES, CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)), BAUDRATE => BAUDRATE, SENTINEL => SENTINEL ) port map ( clk => clk, rst => rst, rx => rx, tx => tx, avail => avail ); ---------------------------------------------------------------------------- -- Basic Status Output leds <= std_logic_vector(to_unsigned((SOLVERS mod (2**(leds'length-1)-1))+1, leds'length-1)) & avail; end rtl;

agpl-3.0

d551a50b1d474843ae68ce7ef45bf474

malkadi/FGPU

RTL/ALU.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity ALU is -- {{{ port( rs_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 1. rt_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 1. rd_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 1. regBlock_re : in std_logic_vector(N_REG_BLOCKS-1 downto 0); -- level 1. family : in std_logic_vector(FAMILY_W-1 downto 0); -- level 1. op_arith_shift : in op_arith_shift_type; -- level 6. code : in std_logic_vector(CODE_W-1 downto 0); -- level 6. immediate : in std_logic_vector(IMM_W-1 downto 0); -- level 6. rd_out : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 10. reg_we_mov : out std_logic := '0'; -- level 10. float_a : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 9. float_b : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 9. op_logical_v : in std_logic := '0'; -- level 14. res_low : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 16. res_high : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 16. reg_wrData : in slv32_array(N_REG_BLOCKS-1 downto 0) := (others=>(others=>'0')); -- level 18. reg_wrAddr : in reg_file_block_array(N_REG_BLOCKS-1 downto 0) := (others=>(others=>'0')); -- level 18. reg_we : in std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0'); -- level 18. clk : in std_logic ); end ALU; -- }}} architecture Behavioral of ALU is -- signals definitions {{{ type regBlock_re_vec_type is array(natural range <>) of std_logic_vector(N_REG_BLOCKS-1 downto 0); signal regBlock_re_vec : regBlock_re_vec_type(6 downto 0) := (others=>(others=>'0')); -- attribute max_fanout of regBlock_re_vec : signal is 50; signal rs_vec, rt_vec, rd_vec : slv32_array(N_REG_BLOCKS-1 downto 0) := (others=>(others=>'0')); signal rs_a, rt_a : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal rs_b, rt_b : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal a, a_p0, c : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal b, b_shifted : std_logic_vector(DATA_W downto 0) := (others=>'0'); signal sra_sign : std_logic_vector(DATA_W downto 0) := (others=>'0'); signal sra_sign_v : std_logic := '0'; signal rs, rt, rd, rt_p0, rt_d0 : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal shift : std_logic_vector(5 downto 0) := (others=>'0'); signal ignore : std_logic_vector(47-DATA_W-1 downto 0) := (others=>'0'); signal sub_op : std_logic := '0'; signal ce : std_logic := '0'; signal res_p0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); type immediate_vec_type is array(natural range <>) of std_logic_vector(IMM_W-1 downto 0); signal immediate_vec : immediate_vec_type(3 downto 0) := (others=>(others=>'0')); type op_arith_shift_vec_type is array(natural range <>) of op_arith_shift_type; signal op_arith_shift_vec : op_arith_shift_vec_type(2 downto 0) := (others => op_add); signal rs_addr_vec, rt_addr_vec : reg_file_block_array(3 downto 0) := (others=>(others=>'0')); signal rd_addr_vec : reg_file_block_array(3 downto 0) := (others=>(others=>'0')); type code_vec_type is array(natural range<>) of std_logic_vector(CODE_W-1 downto 0); signal code_vec : code_vec_type(2 downto 0) := (others=>(others=>'0')); signal res_low_p0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 8 signal res_logical : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal res_logical_vec : SLV32_ARRAY(4 downto 0) := (others=>(others=>'0')); signal op_logical_v_d0 : std_logic := '0'; signal a_logical, b_logical : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal instr_is_slt, instr_is_sltu : std_logic_vector(5 downto 0) := (others=>'0'); signal sltu_true : std_logic := '0'; signal rt_zero : std_logic := '0'; --}}} begin -- regFiles -------------------------------------------------------------------------------------------{{{ reg_blocks: for i in 0 to N_REG_BLOCKS-1 generate begin reg_file: entity regFile port map ( rs_addr => rs_addr_vec(rs_addr_vec'high-i), -- level i+2. rt_addr => rt_addr_vec(rt_addr_vec'high-i), -- level i+2. rd_addr => rd_addr_vec(rd_addr_vec'high-i), -- level i+2. re => regBlock_re_vec(regBlock_re_vec'high)(i), -- level i+2. rs => rs_vec(i), -- level i+7. rt => rt_vec(i), -- level i+6. rd => rd_vec(i), -- level i+8. we => reg_we(i), -- level 18. wrAddr => reg_wrAddr(i), -- level 18. wrData => reg_wrData(i), -- level 18. clk => clk ); end generate; ---------------------------------------------------------------------------------------------------------}}} -- logical -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then res_logical_vec(res_logical_vec'high) <= res_logical; -- @ 11. res_logical_vec(res_logical_vec'high-1 downto 0) <= res_logical_vec(res_logical_vec'high downto 1); -- @ 12.->15. op_logical_v_d0 <= op_logical_v; -- @ 15. a_logical <= rs; --@ 9. if code_vec(code_vec'high-1)(0) = '1' then -- level 8. b_logical(DATA_W-1 downto IMM_ARITH_W) <= (others=>'0'); -- @ 9. b_logical(IMM_ARITH_W-1 downto 0) <= immediate_vec(immediate_vec'high-1)(IMM_ARITH_W-1 downto 0); -- @ 9. else b_logical <= rt; -- @ 9. end if; res_logical <= a_logical and b_logical; -- @ 10. if code_vec(code_vec'high-2)(1) = '1' then -- level 9. res_logical <= a_logical or b_logical; -- @ 10. end if; if code_vec(code_vec'high-2)(2) = '1' then res_logical <= a_logical xor b_logical; -- @ 10. end if; if code_vec(code_vec'high-2)(3) = '1' then res_logical <= a_logical nor b_logical; -- @ 10. end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- output mux -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then if op_logical_v_d0 = '0' then -- level 15. if instr_is_slt(0) = '1' then -- level 15. res_low <= (others=>'0'); res_low(0) <= res_low_p0(res_low_p0'high); -- @ 16. elsif instr_is_sltu(0) = '1' then -- level 15. res_low <= (others=>'0'); res_low(0) <= sltu_true; -- @ 16. else res_low <= res_low_p0; -- @ 16. end if; else res_low <= res_logical_vec(0); -- @ 16. end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- pipelines & muxes ------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then -- pipes {{{ rs_addr_vec(rs_addr_vec'high-1 downto 0) <= rs_addr_vec(rs_addr_vec'high downto 1); -- @ 1.->2. rs_addr_vec(rs_addr_vec'high) <= rs_addr; -- @ 2. rt_addr_vec(rt_addr_vec'high-1 downto 0) <= rt_addr_vec(rt_addr_vec'high downto 1); -- @ 1.->2. rt_addr_vec(rt_addr_vec'high) <= rt_addr; -- @ 2. rd_addr_vec(rd_addr_vec'high-1 downto 0) <= rd_addr_vec(rd_addr_vec'high downto 1); -- @ 1.->2. rd_addr_vec(rd_addr_vec'high) <= rd_addr; -- @ 2. op_arith_shift_vec(op_arith_shift_vec'high-1 downto 0) <= op_arith_shift_vec(op_arith_shift_vec'high downto 1); -- @ 8.->9. op_arith_shift_vec(op_arith_shift_vec'high) <= op_arith_shift; -- @ 7. code_vec(code_vec'high-1 downto 0) <= code_vec(code_vec'high downto 1); -- @ 8.->9. code_vec(code_vec'high) <= code; -- @ 7. immediate_vec(immediate_vec'high-1 downto 0) <= immediate_vec(immediate_vec'high downto 1); -- @ 8.->10. immediate_vec(immediate_vec'high) <= immediate; -- @ 7 regBlock_re_vec(regBlock_re_vec'high-1 downto 0) <= regBlock_re_vec(regBlock_re_vec'high downto 1); --@ 3.->8. regBlock_re_vec(regBlock_re_vec'high) <= regBlock_re; -- @ 2. --}}} -- @ 7 {{{ rt_p0 <= rt_vec(0); -- @ 7. for i in 1 to N_REG_BLOCKS-1 loop if regBlock_re_vec(2)(i) = '1' then rt_p0 <= rt_vec(i); -- @ i+7. end if; end loop; -- }}} -- @ 8 {{{ rt <= rt_p0; -- @ 8. rs <= rs_vec(0); -- @ 8. for i in 1 to N_REG_BLOCKS-1 loop if regBlock_re_vec(1)(i) = '1' then -- level 7. rs <= rs_vec(i); -- @ i+8. end if; end loop; if code_vec(code_vec'high)(CODE_W-1) = '0' then -- level 7. shift(5) <= '0'; -- @ 8. if code_vec(code_vec'high)(0) = '0' then -- level 7. shift(4 downto 0) <= rt_p0(4 downto 0); -- sll @8. else shift(4 downto 0) <= immediate_vec(immediate_vec'high)(4 downto 0); --slli -- @ 8. end if; else if code_vec(code_vec'high)(0) = '0' then -- shift right -- level 7 -- the width of port b of the mutiplier needs to be extended to 33, or the high part to 17 to enable a shift right logical with zero shift(5 downto 0) <= std_logic_vector("100000" - resize(unsigned(rt_p0(4 downto 0)), 6)); --srl & sra -- @ 8. else shift(5 downto 0) <= std_logic_vector("100000" - resize(unsigned(immediate_vec(immediate_vec'high)(4 downto 0)), 6)); -- srli & srai -- @ 8. end if; end if; -- }}} -- @ 9 {{{ float_a <= rs; -- @ 9. float_b <= rt; -- @ 9. rt_d0 <= rt; -- @ 9. rt_zero <= '0'; -- @ 9. if rt = (rt'reverse_range=>'0') then -- level 8. rt_zero <= '1'; -- @ 9. end if; b_shifted <= (others=>'0'); -- @ 9. b_shifted(to_integer(unsigned(shift))) <= '1'; -- @ 9. a_p0 <= rs; -- @ 9. rd <= rd_vec(0); -- @ 9. for i in 1 to N_REG_BLOCKS-1 loop if regBlock_re_vec(0)(i) = '1' then -- level 8. rd <= rd_vec(i); -- @ i+9. end if; end loop; -- }}} -- @ 10 {{{ rd_out <= rd; -- @ 10. a <= a_p0; -- @ 10. reg_we_mov <= rt_zero; -- movz, @10. if op_arith_shift_vec(0) = op_mov then -- level 9. if code_vec(code_vec'high-2)(CODE_W-1) = '0' then -- movn, level 9. reg_we_mov <= not rt_zero; -- @ 10. end if; end if; case op_arith_shift_vec(0) is -- level 9. when op_shift => if code_vec(code_vec'high-2)(CODE_W-1) = '1' and code_vec(code_vec'high-2)(CODE_W-2) = '1' and a_p0(DATA_W-1) = '1' then -- level 9. -- CODE_W-1 for right shift & CODE_W-2 for arithmetic & a_p0(DATA_W-1) for negative sra_sign <= b_shifted; -- @ 10. sra_sign_v <= '1'; -- @ 10. else sra_sign <= (others=>'0'); -- @ 10. sra_sign_v <= '0'; -- @ 10. end if; when others => sra_sign <= (others=>'0'); -- @ 10. sra_sign_v <= '0'; -- @ 10. end case; -- b {{{ case op_arith_shift_vec(0) is -- level 9. when op_lw => b(DATA_W downto 3) <= (others=>'0'); b(2 downto 0) <= code_vec(code_vec'high-2)(2 downto 0); -- @ 10. when op_mult => b(DATA_W) <= '0'; b(rt_d0'range) <= rt_d0; -- @ 10. when op_shift => b <= b_shifted; -- @ 10. when others => b <= (0=>'1', others=>'0'); -- @ 10. end case; -- }}} -- c {{{ case op_arith_shift_vec(0) is -- level 9. when op_add | op_slt => if code_vec(code_vec'high-2)(0) = '0' then -- "use immediate"-bit not set, level 9. c <= rt_d0; -- @ 10. elsif code_vec(code_vec'high-2)(CODE_W-1) = '0' then -- addi, slti, sltiu -- level 9. c <= std_logic_vector(resize(signed(immediate_vec(immediate_vec'high-2)(IMM_ARITH_W-1 downto 0)), DATA_W)); -- @ 10. elsif code_vec(code_vec'high-2)(CODE_W-2) = '0' then -- li -- level 4 & 4.5 c <= std_logic_vector(resize(signed(immediate_vec(immediate_vec'high-2)(IMM_W-1 downto 0)), DATA_W)); -- @ 10. else --lui c(DATA_W-1 downto DATA_W-IMM_W) <= immediate_vec(immediate_vec'high-2)(IMM_W-1 downto 0); -- @ 10. c(DATA_W-IMM_W-1 downto 0) <= rd(DATA_W-IMM_W-1 downto 0); -- @ 10. end if; when op_lw | op_ato => c <= rt_d0; -- @ 10. when op_lmem => c <= std_logic_vector(resize(signed(immediate_vec(immediate_vec'high-2)(IMM_ARITH_W-1 downto 0)), DATA_W)); -- @ 10. when op_mult => if code_vec(code_vec'high-2)(CODE_W-1) = '1' then -- macc -- level 9 c <= rd; -- @ 10. else c <= (others=>'0'); -- @ 10. end if; when op_bra => c <= rd; -- @ 10. when others => -- when op_shift | op_mov | nop c <= (others=>'0'); -- @ 10. end case; -- }}} -- slt & sltu {{{ instr_is_slt(instr_is_slt'high) <= '0'; -- @ 10. instr_is_sltu(instr_is_sltu'high) <= '0'; -- @ 10. if op_arith_shift_vec(0) = op_slt then -- level 9 if code_vec(code_vec'high-2)(2) = '0' then -- slt & slti, level 9 instr_is_slt(instr_is_slt'high) <= '1'; -- @ 10. else --sltu & sltiu instr_is_sltu(instr_is_sltu'high) <= '1'; -- @ 10. end if; end if; instr_is_slt(instr_is_slt'high-1 downto 0) <= instr_is_slt(instr_is_slt'high downto 1); -- @ 11.->15. instr_is_sltu(instr_is_sltu'high-1 downto 0) <= instr_is_sltu(instr_is_sltu'high downto 1); -- @ 11.->15. -- }}} sub_op <= '0'; -- @ 10. case op_arith_shift_vec(0) is -- level 9. when op_add | op_bra | op_slt => sub_op <= code_vec(code_vec'high-2)(1); -- @ 10. when op_lmem | op_lw | op_mult | op_shift | op_mov | op_ato=> end case; -- }}} end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- mult_add_sub {{{ ce <= '1'; mult_adder: entity mult_add_sub port map ( clk => clk, ce => ce, sub => sub_op, -- level 10. a => unsigned(a), -- level 10. b => unsigned(b), -- level 10. c => unsigned(c), -- level 10. sra_sign => unsigned(sra_sign), -- 10. sra_sign_v => sra_sign_v, -- level 10. res_low_p0 => res_low_p0, -- level 15. sltu_true_p0=> sltu_true, --level 15. res_high => res_high -- level 16. ); -- }}} end Behavioral;

gpl-3.0

cafceba4509dce30b8c9168a89b7189c

joalcava/sparcv8-monocicle

instruction_memory.vhd

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:30:27 10/04/2016 -- Design Name: -- Module Name: instruction_memory - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use std.textio.all; entity instructionMemory is Port ( --clk : in STD_LOGIC; address : in STD_LOGIC_VECTOR (31 downto 0); reset : in STD_LOGIC; outInstruction : out STD_LOGIC_VECTOR (31 downto 0)); end instructionMemory; architecture arqInstructionMemory of instructionMemory is type rom_type is array (0 to 63) of std_logic_vector (31 downto 0); impure function InitRomFromFile (RomFileName : in string) return rom_type is FILE RomFile : text open read_mode is RomFileName; variable RomFileLine : line; variable temp_bv : bit_vector(31 downto 0); variable temp_mem : rom_type; begin for I in rom_type'range loop readline (RomFile, RomFileLine); read(RomFileLine, temp_bv); temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; signal instructions : rom_type := InitRomFromFile("testJMPL.data"); begin --reset,address, instructions) process(reset,address, instructions)--clk) begin --if(rising_edge(clk))then if(reset = '1')then outInstruction <= (others=>'0'); else outInstruction <= instructions(conv_integer(address(5 downto 0))); end if; --end if; end process; end arqInstructionMemory;

gpl-3.0

2554fbd60048744b89ce22c5d2d29671

preusser/q27

src/vhdl/top/xilinx/sdrc4_queens_uart.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2016 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity sdrc4_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 79; COUNT_CYCLES : boolean := false; CLK_FREQ : positive := 16000000; CLK_MUL : positive := 23; CLK_DIV : positive := 3; BAUDRATE : positive := 115200; SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte ); port ( clkx : in std_logic; rstx : in std_logic; rx : in std_logic; tx : out std_logic; cts : in std_logic; rts : out std_logic ); end sdrc4_queens_uart; library IEEE; use IEEE.numeric_std.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of sdrc4_queens_uart is -- Global Control signal clk : std_logic; signal rst : std_logic; begin ----------------------------------------------------------------------------- -- Generate Global Controls blkGlobal: block is signal clk_u : std_logic; -- Unbuffered Synthesized Clock signal rst_s : std_logic_vector(1 downto 0) := (others => '0'); begin DCM0 : DCM_BASE generic map ( CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ), CLKIN_DIVIDE_BY_2 => FALSE, PHASE_SHIFT => 0, CLKFX_MULTIPLY => CLK_MUL, CLKFX_DIVIDE => CLK_DIV, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", -- only using clkfx DLL_FREQUENCY_MODE => "LOW", DFS_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, STARTUP_WAIT => TRUE, DCM_AUTOCALIBRATION => FALSE ) port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => clk_u, CLKFX180 => open, LOCKED => open, CLKFB => '0', CLKIN => clkx, RST => '0' ); clk_buf : BUFG port map ( I => clk_u, O => clk ); -- Reset Synchronization process(clk) begin if rising_edge(clk) then rst_s <= (not rstx) & rst_s(rst_s'left downto 1); end if; end process; rst <= rst_s(0); end block blkGlobal; ---------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_uart generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES, CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)), BAUDRATE => BAUDRATE, SENTINEL => SENTINEL ) port map ( clk => clk, rst => rst, rx => rx, tx => tx, avail => open ); rts <= cts; end rtl;

agpl-3.0

5088d96406700fd6b2018c7fa78fbb6a

wltr/cern-fgclite

critical_fpga/src/rtl/cf/fetch_page.vhd

------------------------------------------------------------------------------- --! @file fetch_page.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-19 --! @brief Prepare page for NanoFIP communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; --! @brief Entity declaration of fetch_page --! @details --! The paged data of the NanoFIP response needs to be prepared every cycle. entity fetch_page is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Commands --! @{ --! Start flag start_i : in std_ulogic; --! Done flag done_o : out std_ulogic; --! Memory index idx_i : in std_ulogic_vector(14 downto 0); --! Memory index type idx_type_i : in std_ulogic_vector(2 downto 0); --! @} --! @name Memory page interface --! @{ --! Address page_addr_o : out std_ulogic_vector(5 downto 0); --! Write enable page_wr_en_o : out std_ulogic; --! Data output page_data_o : out std_ulogic_vector(7 downto 0); --! Done flag page_done_i : in std_ulogic; --! @} --! @name External SRAM ADC data --! @{ --! Address sram_adc_addr_o : out std_ulogic_vector(4 downto 0); --! Read request sram_adc_rd_en_o : out std_ulogic; --! Data input sram_adc_data_i : in std_ulogic_vector(23 downto 0); --! Data input enable sram_adc_data_en_i : in std_ulogic; --! Done flag sram_adc_done_o : out std_ulogic; --! @} --! @name External SRAM DIM data --! @{ --! Address sram_dim_addr_o : out std_ulogic_vector(4 downto 0); --! Read request sram_dim_rd_en_o : out std_ulogic; --! Data input sram_dim_data_i : in std_ulogic_vector(15 downto 0); --! Data input enable sram_dim_data_en_i : in std_ulogic; --! Done flag sram_dim_done_o : out std_ulogic; --! @} --! @name DIM data --! @{ --! Address dim_addr_o : out std_ulogic_vector(6 downto 0); --! Read enable dim_rd_en_o : out std_ulogic; --! Data input dim_data_i : in std_ulogic_vector(15 downto 0); --! Data input enable dim_data_en_i : in std_ulogic; --! @} --! @name One-wire data --! @{ --! Address ow_addr_o : out std_ulogic_vector(5 downto 0); --! Read enable ow_rd_en_o : out std_ulogic; --! Data input ow_data_i : in std_ulogic_vector(79 downto 0); --! Data input enable ow_data_en_i : in std_ulogic); --! @} end entity fetch_page; --! RTL implementation of fetch_page architecture rtl of fetch_page is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type source_t is (DIM, ONEWIRE, SRAM_ADC, SRAM_DIM); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal source : source_t; signal start_dim : std_ulogic; signal start_ow : std_ulogic; signal start_sram_adc : std_ulogic; signal start_sram_dim : std_ulogic; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal sram_adc_addr : std_ulogic_vector(5 downto 0); signal sram_adc_wr_en : std_ulogic; signal sram_adc_data : std_ulogic_vector(7 downto 0); signal sram_adc_done : std_ulogic; signal sram_dim_addr : std_ulogic_vector(5 downto 0); signal sram_dim_wr_en : std_ulogic; signal sram_dim_data : std_ulogic_vector(7 downto 0); signal sram_dim_done : std_ulogic; signal dim_addr : std_ulogic_vector(5 downto 0); signal dim_wr_en : std_ulogic; signal dim_data : std_ulogic_vector(7 downto 0); signal dim_done : std_ulogic; signal ow_addr : std_ulogic_vector(5 downto 0); signal ow_wr_en : std_ulogic; signal ow_data : std_ulogic_vector(7 downto 0); signal ow_done : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- with source select page_addr_o <= sram_adc_addr when SRAM_ADC, sram_dim_addr when SRAM_DIM, dim_addr when DIM, ow_addr when ONEWIRE, (others => '0') when others; with source select page_wr_en_o <= sram_adc_wr_en when SRAM_ADC, sram_dim_wr_en when SRAM_DIM, dim_wr_en when DIM, ow_wr_en when ONEWIRE, '0' when others; with source select page_data_o <= sram_adc_data when SRAM_ADC, sram_dim_data when SRAM_DIM, dim_data when DIM, ow_data when ONEWIRE, (others => '0') when others; with source select done_o <= sram_adc_done when SRAM_ADC, sram_dim_done when SRAM_DIM, dim_done when DIM, ow_done when ONEWIRE, '0' when others; sram_adc_done_o <= sram_adc_done; sram_dim_done_o <= sram_dim_done; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- fetch_dim_inst : entity work.fetch_page_dim port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, start_i => start_dim, done_o => dim_done, idx_i => idx_i, page_addr_o => dim_addr, page_wr_en_o => dim_wr_en, page_data_o => dim_data, page_done_i => page_done_i, dim_addr_o => dim_addr_o, dim_rd_en_o => dim_rd_en_o, dim_data_i => dim_data_i, dim_data_en_i => dim_data_en_i); fetch_ow_inst : entity work.fetch_page_ow port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, start_i => start_ow, done_o => ow_done, idx_i => idx_i, page_addr_o => ow_addr, page_wr_en_o => ow_wr_en, page_data_o => ow_data, page_done_i => page_done_i, ow_addr_o => ow_addr_o, ow_rd_en_o => ow_rd_en_o, ow_data_i => ow_data_i, ow_data_en_i => ow_data_en_i); fetch_sram_adc_inst : entity work.fetch_page_sram_adc port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, start_i => start_sram_adc, done_o => sram_adc_done, page_addr_o => sram_adc_addr, page_wr_en_o => sram_adc_wr_en, page_data_o => sram_adc_data, page_done_i => page_done_i, sram_addr_o => sram_adc_addr_o, sram_rd_en_o => sram_adc_rd_en_o, sram_data_i => sram_adc_data_i, sram_data_en_i => sram_adc_data_en_i); fetch_sram_dim_inst : entity work.fetch_page_sram_dim port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, start_i => start_sram_dim, done_o => sram_dim_done, page_addr_o => sram_dim_addr, page_wr_en_o => sram_dim_wr_en, page_data_o => sram_dim_data, page_done_i => page_done_i, sram_addr_o => sram_dim_addr_o, sram_rd_en_o => sram_dim_rd_en_o, sram_data_i => sram_dim_data_i, sram_data_en_i => sram_dim_data_en_i); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin source <= DIM; start_dim <= '0'; start_ow <= '0'; start_sram_adc <= '0'; start_sram_dim <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else start_dim <= '0'; start_ow <= '0'; start_sram_adc <= '0'; start_sram_dim <= '0'; if start_i = '1' then if idx_type_i = "000" then source <= DIM; start_dim <= '1'; elsif idx_type_i = "001" then source <= ONEWIRE; start_ow <= '1'; elsif idx_type_i = "101" then source <= SRAM_DIM; start_sram_dim <= '1'; else source <= SRAM_ADC; start_sram_adc <= '1'; end if; end if; end if; end if; end process regs; end architecture rtl;

mit

75a238bf3d8c4f62b28748f4c504db2f

jpidancet/mips

tests/cpu_tb.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity cpu_tb is generic (FIRMWARE : string); end entity cpu_tb; architecture behav of cpu_tb is component cpu is port (clk : in std_logic; rst : in std_logic; mem_halt : in std_logic; pc : out std_logic_vector(31 downto 0); instr : in std_logic_vector(31 downto 0); data_addr : out std_logic_vector(31 downto 0); data_read : out std_logic; data_in : in std_logic_vector(31 downto 0); data_write : out std_logic; data_out : out std_logic_vector(31 downto 0)); end component cpu; component rom is generic (FILENAME : string; DATA_WIDTH : integer; ADDR_WIDTH : integer); port (addr : in std_logic_vector(ADDR_WIDTH-1 downto 0); data : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component rom; signal clk : std_logic; signal rst : std_logic := '1'; signal mem_halt : std_logic; signal pc : std_logic_vector(31 downto 0); signal instr : std_logic_vector(31 downto 0); signal data_addr : std_logic_vector(31 downto 0); signal data_read : std_logic; signal data_in : std_logic_vector(31 downto 0); signal data_write : std_logic; signal data_out : std_logic_vector(31 downto 0); constant RAM_DEPTH : integer := 1024; type ram_type is array (0 to RAM_DEPTH - 1) of std_logic_vector(31 downto 0); signal ram : ram_type; begin cpu0 : cpu port map (clk => clk, rst => rst, mem_halt => mem_halt, pc => pc, instr => instr, data_addr => data_addr, data_read => data_read, data_in => data_in, data_write => data_write, data_out => data_out); rom0: rom generic map (FILENAME => FIRMWARE, DATA_WIDTH => 32, ADDR_WIDTH => 10) port map (addr => pc(11 downto 2), data => instr); data_in <= ram(to_integer(unsigned(data_addr(11 downto 2)))) when data_read = '1' else (others => '-'); process procedure clock(cycles: in integer) is begin for i in 0 to cycles-1 loop clk <= '0'; wait for 10 ns; clk <= '1'; wait for 10 ns; end loop; end procedure clock; begin -- reset mem_halt <= '0'; rst <= '1'; clk <= '0'; wait for 10 ns; rst <= '0'; clock(1000); wait; end process; process (clk, rst) begin if rst = '1' then ram <= (others => (others => '1')); elsif rising_edge(clk) then if data_write = '1' then ram(to_integer(unsigned(data_addr(11 downto 2)))) <= data_out; end if; end if; end process; end architecture behav;

isc

74e344c3f1e19ce4b02d4f623ecb664a

jpidancet/mips

rtl/cpu.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; library work; use work.mips_defs.ALL; entity cpu is port (clk : in std_logic; rst : in std_logic; mem_halt : in std_logic; pc : out std_logic_vector(31 downto 0); instr : in std_logic_vector(31 downto 0); data_addr : out std_logic_vector(31 downto 0); data_read : out std_logic; data_in : in std_logic_vector(31 downto 0); data_write : out std_logic; data_out : out std_logic_vector(31 downto 0)); end entity cpu; architecture rtl of cpu is component register_file is port (clk : in std_logic; rst : in std_logic; a1 : in std_logic_vector(4 downto 0); a2 : in std_logic_vector(4 downto 0); a3 : in std_logic_vector(4 downto 0); wd3 : in std_logic_vector(31 downto 0); we3 : in std_logic; rd1 : out std_logic_vector(31 downto 0); rd2 : out std_logic_vector(31 downto 0)); end component register_file; component cpu_fetch is port (pc : in std_logic_vector(31 downto 0); pcbranch : in std_logic_vector(31 downto 0); pcsrc : in std_logic; instr_n : out std_logic_vector(31 downto 0); pcplus4_n : out std_logic_vector(31 downto 0); pc_n : out std_logic_vector(31 downto 0); imem_addr : out std_logic_vector(31 downto 0); imem_data : in std_logic_vector(31 downto 0)); end component cpu_fetch; component cpu_decode is port (instr : in std_logic_vector(31 downto 0); pcplus4 : in std_logic_vector(31 downto 0); rs_n : out std_logic_vector(4 downto 0); rt_n : out std_logic_vector(4 downto 0); rd_n : out std_logic_vector(4 downto 0); shamt_n : out std_logic_vector(4 downto 0); imm_n : out std_logic_vector(31 downto 0); alusrc_n : out std_logic; regdst_n : out std_logic; alucontrol_n : out alucontrol_type; ovf_en_n : out std_logic; regwrite_n : out std_logic; memtoreg_n : out std_logic; memread_n : out std_logic; memwrite_n : out std_logic; rd1_n : out std_logic_vector(31 downto 0); rd2_n : out std_logic_vector(31 downto 0); pcsrc_n : out std_logic; branch_n : out std_logic; pcbranch_n : out std_logic_vector(31 downto 0); -- Forward forward_a : in std_logic; forward_b : in std_logic; aluout_fwd : in std_logic_vector(31 downto 0); -- Register file reg_a1 : out std_logic_vector(4 downto 0); reg_a2 : out std_logic_vector(4 downto 0); reg_rd1 : in std_logic_vector(31 downto 0); reg_rd2 : in std_logic_vector(31 downto 0)); end component cpu_decode; component cpu_execute is port (rt : in std_logic_vector(4 downto 0); rd : in std_logic_vector(4 downto 0); shamt : in std_logic_vector(4 downto 0); imm : in std_logic_vector(31 downto 0); alusrc : in std_logic; regdst : in std_logic; alucontrol : in alucontrol_type; ovf_en : in std_logic; rd1 : in std_logic_vector(31 downto 0); rd2 : in std_logic_vector(31 downto 0); regwrite : in std_logic; memtoreg : in std_logic; memread : in std_logic; memwrite : in std_logic; regwrite_n : out std_logic; memtoreg_n : out std_logic; memread_n : out std_logic; memwrite_n : out std_logic; aluout_n : out std_logic_vector(31 downto 0); writedata_n : out std_logic_vector(31 downto 0); writereg_n : out std_logic_vector(4 downto 0); -- Forward forward_a : in std_logic_vector(1 downto 0); forward_b : in std_logic_vector(1 downto 0); aluout_fwd : in std_logic_vector(31 downto 0); result_fwd : in std_logic_vector(31 downto 0)); end component cpu_execute; component cpu_memory is port (regwrite : in std_logic; memtoreg : in std_logic; memread : in std_logic; memwrite : in std_logic; aluout : in std_logic_vector(31 downto 0); writedata : in std_logic_vector(31 downto 0); writereg : in std_logic_vector(4 downto 0); regwrite_n : out std_logic; memtoreg_n : out std_logic; aluout_n : out std_logic_vector(31 downto 0); readdata_n : out std_logic_vector(31 downto 0); writereg_n : out std_logic_vector(4 downto 0); data_addr : out std_logic_vector(31 downto 0); data_read : out std_logic; data_in : in std_logic_vector(31 downto 0); data_write : out std_logic; data_out : out std_logic_vector(31 downto 0)); end component cpu_memory; component cpu_writeback is port (regwrite : in std_logic; memtoreg : in std_logic; aluout : in std_logic_vector(31 downto 0); readdata : in std_logic_vector(31 downto 0); writereg : in std_logic_vector(4 downto 0); writereg_n : out std_logic_vector(4 downto 0); result_n : out std_logic_vector(31 downto 0); regwrite_n : out std_logic); end component cpu_writeback; component hazard is port (branch_d : in std_logic; rs_d : in std_logic_vector(4 downto 0); rt_d : in std_logic_vector(4 downto 0); rs_e : in std_logic_vector(4 downto 0); rt_e : in std_logic_vector(4 downto 0); writereg_e : in std_logic_vector(4 downto 0); memtoreg_e : in std_logic; regwrite_e : in std_logic; writereg_m : in std_logic_vector(4 downto 0); memtoreg_m : in std_logic; regwrite_m : in std_logic; writereg_w : in std_logic_vector(4 downto 0); regwrite_w : in std_logic; forward_ad : out std_logic; forward_bd : out std_logic; forward_ae : out std_logic_vector(1 downto 0); forward_be : out std_logic_vector(1 downto 0); stall : out std_logic); end component hazard; type fetch_state is record pc : std_logic_vector(31 downto 0); end record; constant fetch_reset : fetch_state := (pc => (others => '0')); signal fetch_reg, fetch_next : fetch_state; type decode_state is record instr : std_logic_vector(31 downto 0); pcplus4 : std_logic_vector(31 downto 0); end record; constant decode_reset : decode_state := (instr => (others => '0'), pcplus4 => (others => '0')); signal decode_reg, decode_next : decode_state; type execute_state is record rs : std_logic_vector(4 downto 0); rt : std_logic_vector(4 downto 0); rd : std_logic_vector(4 downto 0); shamt : std_logic_vector(4 downto 0); imm : std_logic_vector(31 downto 0); alusrc : std_logic; regdst : std_logic; alucontrol : alucontrol_type; ovf_en : std_logic; regwrite : std_logic; memtoreg : std_logic; memread : std_logic; memwrite : std_logic; rd1 : std_logic_vector(31 downto 0); rd2 : std_logic_vector(31 downto 0); end record; constant execute_reset : execute_state := (rs => "00000", rt => "00000", rd => "00000", shamt => "00000", imm => (others => '0'), alusrc => '0', regdst => '0', alucontrol => ALU_SLL, ovf_en => '0', regwrite => '0', memtoreg => '0', memread => '0', memwrite => '0', rd1 => (others => '0'), rd2 => (others => '0')); signal execute_reg, execute_next : execute_state; type memory_state is record regwrite : std_logic; memtoreg : std_logic; memread : std_logic; memwrite : std_logic; aluout : std_logic_vector(31 downto 0); writedata : std_logic_vector(31 downto 0); writereg : std_logic_vector(4 downto 0); end record; constant memory_reset : memory_state := (regwrite => '0', memtoreg => '0', memread => '0', memwrite => '0', aluout => (others => '0'), writedata => (others => '0'), writereg => "00000"); signal memory_reg, memory_next : memory_state; type writeback_state is record regwrite : std_logic; memtoreg : std_logic; aluout : std_logic_vector(31 downto 0); readdata : std_logic_vector(31 downto 0); writereg : std_logic_vector(4 downto 0); end record; constant writeback_reset : writeback_state := (regwrite => '0', memtoreg => '0', aluout => (others => '0'), readdata => (others => '0'), writereg => "00000"); signal writeback_reg, writeback_next : writeback_state; signal halt : std_logic; -- register file signal rs : std_logic_vector(4 downto 0); signal rt : std_logic_vector(4 downto 0); signal writereg : std_logic_vector(4 downto 0); signal result : std_logic_vector(31 downto 0); signal regwrite : std_logic; signal reg_rd1 : std_logic_vector(31 downto 0); signal reg_rd2 : std_logic_vector(31 downto 0); -- Jump / Branch signal pcbranch : std_logic_vector(31 downto 0); signal pcsrc : std_logic; signal branch : std_logic; -- Bypass / Forward signal decode_forward_a, decode_forward_b : std_logic; signal execute_forward_a, execute_forward_b : std_logic_vector(1 downto 0); -- Pipeline stall signal stall : std_logic; begin halt <= mem_halt; reg_file0: register_file port map (clk => clk, rst => rst, a1 => rs, a2 => rt, a3 => writereg, wd3 => result, we3 => regwrite, rd1 => reg_rd1, rd2 => reg_rd2); fetch0: cpu_fetch port map (pc => fetch_reg.pc, pcbranch => pcbranch, pcsrc => pcsrc, instr_n => decode_next.instr, pcplus4_n => decode_next.pcplus4, pc_n => fetch_next.pc, imem_addr => pc, imem_data => instr); decode0: cpu_decode port map (instr => decode_reg.instr, pcplus4 => decode_reg.pcplus4, rs_n => execute_next.rs, rt_n => execute_next.rt, rd_n => execute_next.rd, shamt_n => execute_next.shamt, imm_n => execute_next.imm, alusrc_n => execute_next.alusrc, regdst_n => execute_next.regdst, alucontrol_n => execute_next.alucontrol, ovf_en_n => execute_next.ovf_en, regwrite_n => execute_next.regwrite, memtoreg_n => execute_next.memtoreg, memread_n => execute_next.memread, memwrite_n => execute_next.memwrite, rd1_n => execute_next.rd1, rd2_n => execute_next.rd2, pcsrc_n => pcsrc, branch_n => branch, pcbranch_n => pcbranch, forward_a => decode_forward_a, forward_b => decode_forward_b, aluout_fwd => memory_reg.aluout, reg_a1 => rs, reg_a2 => rt, reg_rd1 => reg_rd1, reg_rd2 => reg_rd2); execute0: cpu_execute port map (rt => execute_reg.rt, rd => execute_reg.rd, shamt => execute_reg.shamt, imm => execute_reg.imm, alusrc => execute_reg.alusrc, regdst => execute_reg.regdst, alucontrol => execute_reg.alucontrol, ovf_en => execute_reg.ovf_en, rd1 => execute_reg.rd1, rd2 => execute_reg.rd2, regwrite => execute_reg.regwrite, memtoreg => execute_reg.memtoreg, memread => execute_reg.memread, memwrite => execute_reg.memwrite, regwrite_n => memory_next.regwrite, memtoreg_n => memory_next.memtoreg, memread_n => memory_next.memread, memwrite_n => memory_next.memwrite, aluout_n => memory_next.aluout, writedata_n => memory_next.writedata, writereg_n => memory_next.writereg, forward_a => execute_forward_a, forward_b => execute_forward_b, aluout_fwd => memory_reg.aluout, result_fwd => result); memory0 : cpu_memory port map (regwrite => memory_reg.regwrite, memtoreg => memory_reg.memtoreg, memread => memory_reg.memread, memwrite => memory_reg.memwrite, aluout => memory_reg.aluout, writedata => memory_reg.writedata, writereg => memory_reg.writereg, regwrite_n => writeback_next.regwrite, memtoreg_n => writeback_next.memtoreg, aluout_n => writeback_next.aluout, readdata_n => writeback_next.readdata, writereg_n => writeback_next.writereg, data_addr => data_addr, data_read => data_read, data_in => data_in, data_write => data_write, data_out => data_out); writeback0 : cpu_writeback port map (regwrite => writeback_reg.regwrite, memtoreg => writeback_reg.memtoreg, aluout => writeback_reg.aluout, readdata => writeback_reg.readdata, writereg => writeback_reg.writereg, writereg_n => writereg, result_n => result, regwrite_n => regwrite); hazard0 : hazard port map (branch_d => branch, rs_d => rs, rt_d => rt, rs_e => execute_reg.rs, rt_e => execute_reg.rt, writereg_e => memory_next.writereg, memtoreg_e => execute_reg.memtoreg, regwrite_e => execute_reg.regwrite, writereg_m => memory_reg.writereg, memtoreg_m => memory_reg.memtoreg, regwrite_m => memory_reg.regwrite, writereg_w => writeback_reg.writereg, regwrite_w => writeback_reg.regwrite, forward_ad => decode_forward_a, forward_bd => decode_forward_b, forward_ae => execute_forward_a, forward_be => execute_forward_b, stall => stall); process (clk, rst) begin if rst = '1' then fetch_reg <= fetch_reset; decode_reg <= decode_reset; execute_reg <= execute_reset; memory_reg <= memory_reset; writeback_reg <= writeback_reset; elsif rising_edge(clk) then if halt = '0' then if stall = '1' then execute_reg <= execute_reset; memory_reg <= memory_next; writeback_reg <= writeback_next; else fetch_reg <= fetch_next; decode_reg <= decode_next; execute_reg <= execute_next; memory_reg <= memory_next; writeback_reg <= writeback_next; end if; end if; end if; end process; end architecture rtl;

isc

72cfe58195f85b23e292810aa2785fba

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_defaults.vhd

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mit

7742bcbcf0f7803cd1925b5941f34166

dtysky/LD3320_AXI

src/LIST/synth/LIST.vhd

-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_2; USE blk_mem_gen_v8_2.blk_mem_gen_v8_2; ENTITY LIST IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END LIST; ARCHITECTURE LIST_arch OF LIST IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF LIST_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_2 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); sleep : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_2; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF LIST_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF LIST_arch : ARCHITECTURE IS "LIST,blk_mem_gen_v8_2,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF LIST_arch: ARCHITECTURE IS "LIST,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=LIST.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.68455 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; BEGIN U0 : blk_mem_gen_v8_2 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 1, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 0, C_INIT_FILE_NAME => "no_coe_file_loaded", C_INIT_FILE => "LIST.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 0, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 8, C_READ_WIDTH_A => 8, C_WRITE_DEPTH_A => 256, C_READ_DEPTH_A => 256, C_ADDRA_WIDTH => 8, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 8, C_READ_WIDTH_B => 8, C_WRITE_DEPTH_B => 256, C_READ_DEPTH_B => 256, C_ADDRB_WIDTH => 8, C_HAS_MEM_OUTPUT_REGS_A => 0, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "0", C_COUNT_18K_BRAM => "1", C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.68455 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => '0', regcea => '0', wea => wea, addra => addra, dina => dina, clkb => clkb, rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => addrb, dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), doutb => doutb, injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END LIST_arch;

mit

121c6d0b4b3ff5e10aacd5dd4e86f481

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fdiv_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

1c050a1ab347aa17349a167de6a3826a

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_max_mem_cntrl.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

ab7d4656dc9b0bf226702bc574c9f717

chrbirks/NiosII-basic

nios_system/nios_system_inst.vhd

component nios_system is port ( switches_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export leds_export : out std_logic_vector(3 downto 0); -- export clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X' -- reset_n ); end component nios_system; u0 : component nios_system port map ( switches_export => CONNECTED_TO_switches_export, -- switches.export leds_export => CONNECTED_TO_leds_export, -- leds.export clk_clk => CONNECTED_TO_clk_clk, -- clk.clk reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n );

gpl-3.0

33e21fe8a7dba255cf19074095d6bdd8

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_2AXI_2CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

6ca7d27e652775bfdae7d6a6f0ffff91

viccuad/fpga-thingies

tron/tron.vhd

-- hecho para ser visto con tab size = 3 library IEEE; library UNISIM; use UNISIM.vcomponents.all; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tron is port ( ps2Clk: IN std_logic; ps2Data: IN std_logic; clk: IN std_logic; reset: IN std_logic; --reset activo a baja! hSync: OUT std_logic; Vsync: OUT std_logic; colisionOUT: OUT std_logic; DI2: OUT std_logic_vector(0 downto 0); DI1: OUT std_logic_vector(0 downto 0); segs: OUT std_logic_vector (6 downto 0); R: OUT std_logic_vector (2 downto 0); -- alconversor D/A G: OUT std_logic_vector (2 downto 0); -- alconversor D/A B: OUT std_logic_vector (2 downto 0) -- alconversor D/A ); end tron; architecture Behavioral of tron is component ps2KeyboardInterface port ( clk: IN std_logic; rst: IN std_logic; ps2Clk: IN std_logic; ps2Data: IN std_logic; data: OUT std_logic_vector (7 DOWNTO 0); newData: OUT std_logic; newDataAck: IN std_logic ); end component; --señales maquina de estados type fsmEstados is (pulsadas, despulsadas); signal estado: fsmEstados; type fsmEstados2 is (jugando, parado, reseteo); signal estado2: fsmEstados2; --señales PS2 signal newData, newDataAck: std_logic; signal scancode: std_logic_vector (7 downto 0); --señales VGA signal senialHSync, senialVSync: std_logic; signal finPixelCont: std_logic; signal cuentaPixelCont: std_logic_vector (10 downto 0); signal cuentaLineCont: std_logic_vector (9 downto 0); signal comp1, comp2, comp3, comp4, comp5, comp6: std_logic; signal Rcoche1,Rcoche2,Restela: std_logic_vector (2 downto 0); signal Gcoche1,Gcoche2,Gestela: std_logic_vector (2 downto 0); signal Bcoche1,Bcoche2,Bestela: std_logic_vector (2 downto 0); --señales juego signal pixelCoche1Hor,pixelCoche2Hor: std_logic_vector (7 downto 0); --153 pixeles (10011001) signal pixelCoche1Ver,pixelCoche2Ver: std_logic_vector (6 downto 0); --102 pixeles signal movCoche1,movCoche2: std_logic_vector (1 downto 0); -- 00 = arriba , 01 = derecha , 10 = abajo , 11 = izquierda signal ldMov1,ldMov2: std_logic; signal moverCoches: std_logic; signal cuenta1dec: STD_LOGIC_VECTOR(19 downto 0); --contador1decima signal finCuenta1Dec: STD_LOGIC; signal cuentacontReseteo: std_logic_vector(14 downto 0); signal finCuentaContReseteo,enableContReseteo,hayColision: std_logic; signal coche1SeMueve, coche2SeMueve,coche1SeMueve2, coche2SeMueve2: std_logic; --señales teclas signal teclaSPC: std_logic; signal clTeclaSPC: std_logic; signal ldTeclaSPC: std_logic; --seniales memorias signal estelaCoche1MenosSig,estelaCoche2MenosSig,estelaCoche1MasSig,estelaCoche2MasSig,DOBcoche1MenosSig,DOBcoche1MasSig,DOBcoche2MenosSig,DOBcoche2MasSig: std_logic_vector(0 downto 0); signal selPixelPantalla: std_logic_vector (14 downto 0); -- pixeles logicos hor (120) concatenado con pixeles logicos ver (153): cuentaPixelCont(10 downto 3)++cuentaLineCont(8 downto 2) signal selPixelCoche1,selPixelCoche2: std_logic_vector (14 downto 0); --pixelCoche1/2Hor concatenado pixelCoche1/2Ver signal estelaMem: std_logic_vector (1 downto 0); signal WEBmenosSig1, WEBmasSig,WEBmenosSig2, WEBmasSig2,WEcoche1,WEcoche2,senialWEA: std_logic; signal DIBcoche1,DIBcoche2,DOBcoche1,DOBcoche2: std_logic_vector(0 downto 0); --señales de depuracion signal st : std_logic_vector (1 downto 0); begin --------------------------- RAM ------------------------------------------------ colisionOUT <= hayColision; DI1 <= DIBcoche1; DI2 <= DIBcoche2; selPixelCoche1(14 downto 7) <= pixelCoche1Hor; selPixelCoche1(6 downto 0) <= pixelCoche1Ver; selPixelCoche2(14 downto 7) <= pixelCoche2Hor; selPixelCoche2(6 downto 0) <= pixelCoche2Ver; selPixelPantalla(14 downto 7) <= cuentaPixelCont(10 downto 3); selPixelPantalla(6 downto 0) <= cuentaLineCont(8 downto 2); --http://www.xilinx.com/itp/xilinx10/books/docs/spartan3_hdl/spartan3_hdl.pdf rojoMenosSignif: RAMB16_S1_S1 generic map( WRITE_MODE_B => "READ_FIRST" ) port map ( DOA => estelaCoche1MenosSig, -- Port A 1-bit Data Output DOB => DOBcoche1MenosSig, -- Port B 1-bit Data Output ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input ADDRB => selPixelCoche1(13 downto 0), -- Port B 14-bit Address Input CLKA => clk, -- Port A Clock CLKB => clk, -- Port B Clock DIA => "0", -- Port A 1-bit Data Input DIB => DIBcoche1, -- Port B 1-bit Data Input --pintamos rojo ENA => '1', -- Port A RAM Enable Input ENB => '1', -- PortB RAM Enable Input SSRA => '0', -- Port A Synchronous Set/Reset Input SSRB => '0', -- Port B Synchronous Set/Reset Input WEA => senialWEA, -- Port A Write Enable Input WEB => WEBmenosSig1 -- Port B Write Enable Input ); rojoMasSignif: RAMB16_S1_S1 generic map( WRITE_MODE_B => "READ_FIRST" ) port map ( DOA => estelaCoche1MasSig, -- Port A 1-bit Data Output DOB => DOBcoche1MasSig, -- Port B 1-bit Data Output ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input ADDRB => selPixelCoche1(13 downto 0), -- Port B 14-bit Address Input CLKA => clk, -- Port A Clock CLKB => clk, -- Port B Clock DIA => "0", -- Port A 1-bit Data Input DIB => DIBcoche1, -- Port B 1-bit Data Input --pintamos rojo ENA => '1', -- Port A RAM Enable Input ENB => '1', -- PortB RAM Enable Input SSRA => '0', -- Port A Synchronous Set/Reset Input SSRB => '0', -- Port B Synchronous Set/Reset Input WEA => senialWEA, -- Port A Write Enable Input WEB =>WEBmasSig -- Port B Write Enable Input ); azulMenosSignif: RAMB16_S1_S1 generic map( WRITE_MODE_B => "READ_FIRST" ) port map ( DOA => estelaCoche2MenosSig, -- Port A 1-bit Data Output DOB => DOBcoche2MenosSig, -- Port B 2-bit Data Output ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input ADDRB => selPixelCoche2(13 downto 0), -- Port B 14-bit Address Input CLKA => clk, -- Port A Clock CLKB => clk, -- Port B Clock DIA => "0", -- Port A 1-bit Data Input DIB => DIBcoche2, -- Port B 1-bit Data Input --pintamos azul ENA => '1', -- Port A RAM Enable Input ENB => '1', -- PortB RAM Enable Input SSRA => '0', -- Port A Synchronous Set/Reset Input SSRB => '0', -- Port B Synchronous Set/Reset Input WEA => senialWEA, -- Port A Write Enable Input WEB => WEBmenosSig2 -- Port B Write Enable Input ); azulMasSignif: RAMB16_S1_S1 generic map( WRITE_MODE_B => "READ_FIRST" ) port map ( DOA => estelaCoche2MasSig, -- Port A 1-bit Data Output DOB => DOBcoche2MasSig, -- Port B 1-bit Data Output ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input ADDRB => selPixelCoche2(13 downto 0), -- Port B 14-bit Address Input CLKA => clk, -- Port A Clock CLKB => clk, -- Port B Clock DIA => "0", -- Port A 1-bit Data Input DIB => DIBcoche2, -- Port B 1-bit Data Input --pintamos azul ENA => '1', -- Port A RAM Enable Input ENB => '1', -- PortB RAM Enable Input SSRA => '0', -- Port A Synchronous Set/Reset Input SSRB => '0', -- Port B Synchronous Set/Reset Input WEA => senialWEA, -- Port A Write Enable Input WEB => WEBmasSig2 -- Port B Write Enable Input ); WEB_MasSig2 interfazPS2: ps2KeyboardInterface port map ( rst => reset, clk => clk, ps2Clk => ps2Clk, ps2Data => ps2Data, data => scancode, newData => newData, newDataAck => newDataAck ); decoSalida: process(selPixelCoche1,selPixelCoche2,selPixelPantalla,DOBcoche1MenosSig, DOBcoche1MasSig,DOBcoche2MenosSig,DOBcoche2MasSig,WEcoche1, WEcoche2,estelaCoche1MenosSig,estelaCoche1MasSig,estelaCoche2MenosSig, estelaCoche2MasSig) begin if (selPixelPantalla(14) = '0') then --direccionar a las menos signif estelaMem(1 downto 1) <= estelaCoche1MenosSig; estelaMem(0 downto 0) <= estelaCoche2MenosSig; else --direccionar a las mas signif estelaMem(1 downto 1) <= estelaCoche1MasSig; estelaMem(0 downto 0) <= estelaCoche2MasSig; end if; if (selPixelCoche1(14) = '0') then --direccionar a las menos signif WEBmenosSig1 <= WEcoche1; WEBmasSig <= '0'; DOBcoche1 <= DOBcoche1MenosSig; else --direccionar a las mas signif WEBmenosSig1 <= '0'; WEBmasSig <= WEcoche1; DOBcoche1 <= DOBcoche1MasSig; end if; if (selPixelCoche2(14) = '0') then --direccionar a las menos signif WEBmenosSig2 <= WEcoche2; WEBmasSig2 <= '0'; DOBcoche2 <= DOBcoche2MenosSig; else --direccionar a las mas signif WEBmenosSig2 <= '0'; WEBmasSig2 <= WEcoche2; DOBcoche2 <= DOBcoche2MasSig; end if; end process decoSalida; --------------------------- PANTALLA ------------------------------------------- hSync <= senialHSync; vSync <= senialVSync; pantalla: process(clk, reset,cuentaPixelCont,cuentaLineCont,Rcoche1,Rcoche2, Gcoche1,Gcoche2,Bcoche1,Bcoche2,Restela,Gestela,Bestela) begin --cont mod 1589 (pixelCont para sincronismo horizontal) if (cuentaPixelCont = "11000110100") then finPixelCont <= '1'; else finPixelCont <= '0'; end if; if(reset = '0')then cuentaPixelCont <= (others => '0'); finPixelCont <= '0'; elsif(clk'event and clk = '1') then if (cuentaPixelCont /= "11000110100") then --1588 cuentaPixelCont <= cuentaPixelCont + '1'; elsif (cuentaPixelCont = "11000110100") then cuentaPixelCont <= (others => '0'); end if; end if; --cont mod 528 (lineCont para sincronismo vertical) if(reset = '0')then cuentaLineCont <= (others => '0'); elsif(clk'event and clk = '1') then if (finPixelCont = '1' and cuentaLineCont /= "1000001111") then --527 cuentaLineCont <= cuentaLineCont + '1'; elsif (finPixelCont = '1' and cuentaLineCont = "1000001111") then cuentaLineCont <= (others => '0'); end if; end if; --comparaciones if (cuentaPixelCont > 1257) then comp1 <= '1'; else comp1 <= '0'; end if; if (cuentaPixelCont > 1304) then comp2 <= '1'; else comp2 <= '0'; end if; if (cuentaPixelCont <= 1493) then comp3 <= '1'; else comp3 <= '0'; end if; if (cuentaLineCont > 479) then comp4 <= '1'; else comp4 <= '0'; end if; if (cuentaLineCont > 493) then comp5 <= '1'; else comp5 <= '0'; end if; if (cuentaLineCont <= 495) then comp6 <= '1'; else comp6 <= '0'; end if; senialHSync <= comp2 nand comp3; senialVSync <= comp5 nand comp6; if (senialHSync = '0' or senialVSync = '0') then --no pinta R <= "000"; G <= "000"; B <= "000"; else R(2) <= ( (not (comp1 or comp4)) and (Rcoche1(2) or Rcoche2(2) or Restela(2)) ); R(1) <= ( (not (comp1 or comp4)) and (Rcoche1(1) or Rcoche2(1) or Restela(1)) ); R(0) <= ( (not (comp1 or comp4)) and (Rcoche1(0) or Rcoche2(0) or Restela(0)) ); G(2) <= ( (not (comp1 or comp4)) and (Gcoche1(2) or Gcoche2(2) or Gestela(2)) ); G(1) <= ( (not (comp1 or comp4)) and (Gcoche1(1) or Gcoche2(1) or Gestela(1)) ); G(0) <= ( (not (comp1 or comp4)) and (Gcoche1(0) or Gcoche2(0) or Gestela(0)) ); B(2) <= ( (not (comp1 or comp4)) and (Bcoche1(2) or Bcoche2(2) or Bestela(2)) ); B(1) <= ( (not (comp1 or comp4)) and (Bcoche1(1) or Bcoche2(1) or Bestela(1)) ); B(0) <= ( (not (comp1 or comp4)) and (Bcoche1(0) or Bcoche2(0) or Bestela(0)) ); end if; end process; ------------------------------- PINTAR JUEGO ---------------------------------- -- vertical: 479 limite de pixeles visibles -- 120 pixeles -> 479 x= (479*1)/120 = 3.99 = aprox 4 -- 1 pixeles -> x -- horizontal: 1257 limite de pixeles visibles -- 153 pixeles -> 1257 x= (1257*1)/153 = 8.21 = aprox 8 -- 1 pixeles -> x pintarCoche1: process(cuentaLineCont,cuentaPixelCont,pixelCoche1Ver,pixelCoche1Hor) begin -- inicializacion Rcoche1 <= "000"; Gcoche1 <= "000"; Bcoche1 <= "000"; --pintar if ((cuentaLineCont(9 downto 2) >= pixelCoche1Ver-1 and cuentaLineCont(9 downto 2) <= pixelCoche1Ver+1) and (cuentaPixelCont(10 downto 3) >= pixelCoche1Hor-1 and cuentaPixelCont(10 downto 3) <= pixelCoche1Hor+1)) then Rcoche1 <= "111";--coche rojo Gcoche1 <= "000"; Bcoche1 <= "000"; end if; end process pintarCoche1; pintarCoche2: process(cuentaLineCont,cuentaPixelCont,pixelCoche2Ver,pixelCoche2Hor) begin -- inicializacion Rcoche2 <= "000"; Gcoche2 <= "000"; Bcoche2 <= "000"; --pintar if ((cuentaLineCont(9 downto 2) >= pixelCoche2Ver-1 and cuentaLineCont(9 downto 2) <= pixelCoche2Ver+1) and (cuentaPixelCont(10 downto 3) >= pixelCoche2Hor-1 and cuentaPixelCont(10 downto 3) <= pixelCoche2Hor+1)) then Rcoche2 <= "000"; Gcoche2 <= "000"; Bcoche2 <= "111";--coche azul end if; end process pintarCoche2; pintarEstelas: process(cuentaLineCont,cuentaPixelCont,estelaMem) begin -- inicializacion Restela <= "000"; Gestela <= "000"; Bestela <= "000"; --pintar case estelaMem is when "01" => Restela <= "000"; --pintamos estela azul Gestela <= "000"; Bestela <= "111"; when "10" => Restela <= "111"; --pintamos estela rojo Gestela <= "000"; Bestela <= "000"; when "11" => Restela <= "111"; --las estelas se superponen Gestela <= "000"; Bestela <= "111"; when others => Restela <= "000"; --no hay estela Gestela <= "000"; Bestela <= "000"; end case; end process pintarEstelas; --#################### CONTROL JUEGO ########################################### contadorMediaDecima: process(reset,clk,cuenta1dec) --contador mod 5.000.000 (de 0 a 4.999.999) begin if (cuenta1dec = "11110100001000111111") then finCuenta1Dec <= '1'; else finCuenta1Dec <= '0'; end if; if(reset = '0')then cuenta1dec <= (others => '0'); finCuenta1Dec <= '0'; elsif(clk'event and clk = '1') then if (cuenta1dec /= "11110100001000111111") then cuenta1dec <= cuenta1dec + 1; elsif (cuenta1dec = "11110100001000111111") then cuenta1dec <= (others => '0'); end if; end if; end process contadorMediaDecima; coche1: process(moverCoches,finCuenta1Dec,clk,reset,movCoche1,pixelCoche1Hor,pixelCoche1Ver) begin coche1SeMueve <= '1'; if(finCuenta1Dec = '1' and moverCoches = '1') then coche1SeMueve <= '1'; else coche1SeMueve <= '0'; end if; --vertical: cont mod 102 y horizontal: cont mod 153 if (reset = '0')then --pos inicial coche1 pixelCoche1Ver <= "0001000"; --en 9 pixelCoche1Hor <= "00000000"; --en 1 coche1SeMueve <= '0'; elsif (clk'event and clk = '1') then if(finCuenta1Dec = '1' and moverCoches = '1') then case movCoche1 is when "00" => if (pixelCoche1Ver = 0) then --va hacia arriba pixelCoche1Ver <= "1110111"; else pixelCoche1Ver <= pixelCoche1Ver - '1'; end if; when "10" => if (pixelCoche1Ver = 120) then --va hacia abajo pixelCoche1Ver <= "0000000"; else pixelCoche1Ver <= pixelCoche1Ver + '1'; end if; when "11" => if ( pixelCoche1Hor = 0) then --va hacia izquierda pixelCoche1Hor <= "10011000"; else pixelCoche1Hor <= pixelCoche1Hor - '1'; end if; when "01" => if (pixelCoche1Hor = 153) then --va hacia derecha pixelCoche1Hor <= "00000000"; else pixelCoche1Hor <= pixelCoche1Hor + '1'; end if; when others => null; end case; end if; if (teclaSPC = '1') then pixelCoche1Ver <= "0001000"; --en 9 pixelCoche1Hor <= "00000000"; --en 1 end if; end if; end process coche1; coche2: process(finCuenta1Dec,moverCoches,clk,reset,movCoche2,pixelCoche2Hor,pixelCoche2Ver) begin coche2SeMueve <= '0'; if(finCuenta1Dec = '1' and moverCoches = '1') then coche2SeMueve <= '1'; else coche2SeMueve <= '0'; end if; --vertical: cont mod 102 y horizontal: cont mod 153 if (reset = '0')then --pos inicial coche2 pixelCoche2Ver <= "1101110"; --en 110 pixelCoche2Hor <= "10011000"; --en 152 coche2SeMueve <= '0'; elsif (clk'event and clk = '1') then if(finCuenta1Dec = '1' and moverCoches = '1') then case movCoche2 is when "00" => if (pixelCoche2Ver = 0) then --va hacia arriba pixelCoche2Ver <= "1110111"; else pixelCoche2Ver <= pixelCoche2Ver - '1'; end if; when "10" => if (pixelCoche2Ver = 120) then --va hacia abajo pixelCoche2Ver <= "0000000"; else pixelCoche2Ver <= pixelCoche2Ver + '1'; end if; when "11" => if ( pixelCoche2Hor = 0) then --va hacia izquierda pixelCoche2Hor <= "10011000"; else pixelCoche2Hor <= pixelCoche2Hor - '1'; end if; when "01" => if (pixelCoche2Hor = 153) then --va hacia derecha pixelCoche2Hor <= "00000000"; else pixelCoche2Hor <= pixelCoche2Hor + '1'; end if; when others => null; end case; end if; if (teclaSPC = '1') then pixelCoche2Ver <= "1101110"; --en 110 pixelCoche2Hor <= "10011000"; --en 152 end if; end if; end process coche2; colision: process(estelaMem,DOBcoche1,DOBcoche2,coche1SeMueve,coche2SeMueve,WEcoche1,WEcoche2) begin hayColision <= '0'; if (estelaMem = "11" or --chocan entre ellos (DOBcoche1 = "1" and WEcoche1 = '1') or (DOBcoche2 = "1" and WEcoche2 = '1') --chocan consigo mismo )then hayColision <= '1'; else hayColision <= '0'; end if; end process colision; ------maquina de estados con registros de flags--------------------------------- controladorEstados: process (clk, reset, newData, scancode) begin if(reset = '0') then estado <= pulsadas; elsif (clk'event and clk = '1') then estado <= pulsadas; -- estado por defecto, puede ser sobreescrito luego case estado is when pulsadas => estado <= pulsadas; if (newData = '1' and scancode = "11110000") then --11110000: F0 estado <= despulsadas; end if; when despulsadas => estado <= despulsadas; if (newData = '1') then estado <= pulsadas; end if; end case; end if; end process; generadorSalidaMealy: process (reset,newDataAck, scancode, estado, newData) begin newDataAck <= '0'; clTeclaSPC <= '0'; ldTeclaSPC <= '0'; case estado is when pulsadas => if (newData = '1') then --11110000: F0 case scancode is --registros de flags: when "00010101" => ldMov1 <= '1' ; --Q=15 arriba when "00011100" => ldMov1 <= '1' ; --A=1C abajo when "00011010" => ldMov1 <= '1' ; --Z=1A izq when "00100010" => ldMov1 <= '1' ; --X=22 der when "01001101" => ldMov2 <= '1' ; --P=4D arriba when "01001011" => ldMov2 <= '1' ; --L=4B abajo when "00110001" => ldMov2 <= '1' ; --N=31 izq when "00111010" => ldMov2 <= '1' ; --M=3A der when "00101001" => ldTeclaSPC <= '1'; clTeclaSPC <= '0'; --SPC=29 when others => null; end case; newDataAck <= '1'; end if; when despulsadas => if (newData = '1') then case scancode is --registros de flags: when "00101001" => ldTeclaSPC <= '0'; clTeclaSPC <= '1'; --SPC=29 when others => null; end case; newDataAck <= '1'; end if; when others => null; end case; end process; -------------------------------------------------------------------------------- biestableDteclaSPC: process(reset,clk,ldTeclaSPC,clTeclaSPC) begin if(reset = '0')then teclaSPC <= '0'; elsif(clk'event and clk = '1' ) then if (clTeclaSPC = '1') then teclaSPC <= '0'; elsif (ldTeclaSPC = '1') then teclaSPC <= '1'; end if; end if; end process biestableDteclaSPC; registroMovCoche1: process(reset,clk,ldMov1,teclaSPC,scancode) begin if(reset = '0')then movCoche1 <= "01"; --hacia der elsif(clk'event and clk = '1' ) then if (teclaSPC = '1') then movCoche1 <= "01"; --hacia der elsif (ldMov1 = '1') then case scancode is when "00010101" => movCoche1 <= "00"; --Q=15 arriba when "00011100" => movCoche1 <= "10"; --A=1C abajo when "00011010" => movCoche1 <= "11"; --Z=1A izq when "00100010" => movCoche1 <= "01"; --X=22 der when others => null; end case; end if; end if; end process registroMovCoche1; registroMovCoche2: process(reset,clk,ldMov2,teclaSPC,scancode) begin if(reset = '0')then movCoche2 <= "11"; --hacia der elsif(clk'event and clk = '1' ) then if (teclaSPC = '1') then movCoche2 <= "11"; --hacia der elsif (ldMov2 = '1') then case scancode is when "01001101" => movCoche2 <= "00"; --P=4D arriba when "01001011" => movCoche2 <= "10"; --L=4B abajo when "00110001" => movCoche2 <= "11"; --N=31 izq when "00111010" => movCoche2 <= "01"; --M=3A der when others => null; end case; end if; end if; end process registroMovCoche2; -----maquina de estados del juego ---------------------------------------------- controladorEstados2: process (clk, reset, finCuentaContReseteo, hayColision, teclaSPC, finCuenta1Dec) begin if(reset = '0') then estado2 <= jugando; elsif (clk'event and clk = '1') then estado2 <= jugando; -- estado por defecto, puede ser sobreescrito luego case estado2 is when jugando => estado2 <= jugando; if (hayColision = '1') then estado2 <= parado; elsif (teclaSPC = '1') then estado2 <= reseteo; end if; when parado => estado2 <= parado; if (teclaSPC = '1') then estado2 <= reseteo; end if; when reseteo => estado2 <= reseteo; if (finCuentaContReseteo = '1') then estado2 <= jugando; end if; end case; end if; end process; generadorSalidaMoore2: process (estado2) begin DIBcoche1 <= "1"; DIBcoche2 <= "1"; enableContReseteo <= '0'; moverCoches <= '1'; st <= "00"; senialWEA <= '0'; case estado2 is when jugando => DIBcoche1 <= "1"; DIBcoche2 <= "1"; enableContReseteo <= '0'; moverCoches <= '1'; st <= "00"; senialWEA <= '0'; when parado => DIBcoche1 <= "0"; DIBcoche2 <= "0"; enableContReseteo <= '0'; moverCoches <= '0'; st <= "01"; senialWEA <= '0'; when reseteo => DIBcoche1 <= "0"; DIBcoche2 <= "0"; enableContReseteo <= '1'; moverCoches <= '0'; st <= "10"; senialWEA <= '1'; when others => null; end case; end process; conversor7seg: process(st) begin case st is --gfedcba when "00" => segs <= "0111111"; when "01" => segs <= "0000110"; when "10" => segs <= "1011011"; when OTHERS => segs <= "1111001"; -- error end case; end process; -------------------------------------------------------------------------------- contReseteo: process(reset,clk,cuentacontReseteo,enableContReseteo) --contador mod 2^15=32768 (120 x 153 pixeles) begin if (cuentacontReseteo = "111111111111111") then finCuentaContReseteo <= '1'; else finCuentaContReseteo <= '0'; end if; if(reset = '0')then cuentacontReseteo <= (others => '0'); finCuentaContReseteo <= '0'; elsif(clk'event and clk = '1') then if(enableContReseteo = '1') then if (cuentacontReseteo /= "111111111111111") then cuentacontReseteo <= cuentacontReseteo + 1; end if; elsif (enableContReseteo = '0') then cuentacontReseteo <= (others => '0'); end if; end if; end process contReseteo; biestableDcoche1SeMueveRetrasa1ciclo: process(reset,clk,coche1SeMueve) --con estos biestablesD conseguimos escribir sólo una vez en memoria por cada movimiento de coche begin if(reset = '0')then coche1SeMueve2 <= '0'; elsif(clk'event and clk = '1' ) then coche1SeMueve2 <= coche1SeMueve; end if; end process biestableDcoche1SeMueveRetrasa1ciclo; biestableDcoche2SeMueveRetrasa1ciclo: process(reset,clk,coche2SeMueve) begin if(reset = '0')then coche2SeMueve2 <= '0'; elsif(clk'event and clk = '1' ) then coche2SeMueve2 <= coche2SeMueve; end if; end process biestableDcoche2SeMueveRetrasa1ciclo; biestableDWEcoche1: process(reset,clk,coche1SeMueve2) --con estos biestablesD conseguimos escribir sólo una vez en memoria por cada movimiento de coche begin if(reset = '0')then WEcoche1 <= '0'; elsif(clk'event and clk = '1' ) then WEcoche1 <= coche1SeMueve2; end if; end process biestableDWEcoche1; biestableDWEcoche2: process(reset,clk,coche2SeMueve2) begin if(reset = '0')then WEcoche2 <= '0'; elsif(clk'event and clk = '1' ) then WEcoche2 <= coche2SeMueve2; end if; end process biestableDWEcoche2; end Behavioral;

gpl-3.0

ccbab33b09ac435582eb81db029d8ee5

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_wrapper.vhd

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mit

ca4938449d27ddff50df4f9606be9925

wltr/cern-fgclite

critical_fpga/src/rtl/cf/debug_serial.vhd

------------------------------------------------------------------------------- --! @file debug_serial.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2015-01-20 --! @brief Debugging serial interface. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; --! @brief Entity declaration of debug_serial --! @details --! Provide a serial debugging interface over UART. entity debug_serial is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Debugging interface --! @{ --! TX start flag start_i : in std_ulogic; --! Data input debug_i : in std_ulogic_vector(7 downto 0); --! Data input enable debug_en_i : in std_ulogic; --! Data output debug_o : out std_ulogic_vector(7 downto 0); --! Data output enable debug_en_o : out std_ulogic; --! @} --! @name Serial communication --! @{ --! Serial receiver rx_i : in std_ulogic; --! Serial transmitter tx_o : out std_ulogic); --! @} end entity debug_serial; --! RTL implementation of debug_serial architecture rtl of debug_serial is --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal tx_data : std_ulogic_vector(7 downto 0); signal tx_data_en : std_ulogic; signal tx_done : std_ulogic; signal fifo_rd_en : std_ulogic; signal fifo_empty : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- fifo_rd_en <= (start_i or tx_done) and (not fifo_empty); --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! FIFO fifo_inst : entity work.fifo_tmr generic map ( depth_g => 256, width_g => 8) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_en_i => debug_en_i, data_i => debug_i, done_o => open, full_o => open, wr_busy_o => open, rd_en_i => fifo_rd_en, data_o => tx_data, data_en_o => tx_data_en, empty_o => fifo_empty, rd_busy_o => open); --! Serial transmitter uart_tx_inst : entity work.uart_tx generic map ( data_width_g => 8, parity_g => 0, stop_bits_g => 1, num_ticks_g => 156) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, data_i => tx_data, data_en_i => tx_data_en, busy_o => open, done_o => tx_done, tx_o => tx_o); --! Serial receiver uart_rx_inst : entity work.uart_rx generic map ( data_width_g => 8, parity_g => 0, stop_bits_g => 1, num_ticks_g => 156) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, rx_i => rx_i, data_o => debug_o, data_en_o => debug_en_o, error_o => open); end architecture rtl;

mit

fd5c1aa39591bb21324d015a0acfb869

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

18935be0c51b0848988ba5dbd1b5615c

preusser/q27

src/vhdl/PoC/common/components.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Package: Common primitives described as a function -- -- Description: -- ------------------------------------ -- This packages describes common primitives like flip flops and multiplexers -- as a function to use them as one-liners. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.utils.all; PACKAGE components IS -- FlipFlop functions function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with reset and enable function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR; -- D-FlipFlop with reset and enable function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with set and enable function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- T-FlipFlop with reset and enable function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant rst function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant set -- adder function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR; function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED; function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED; function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR; function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED; function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED; -- negate function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; -- calculate 2's complement -- counter function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED; function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC; function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED; function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC; function downcounter_neg(cnt : SIGNED) return STD_LOGIC; -- shift/rotate registers function sr_left(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR; function sr_right(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR; function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; -- compare function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED; function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED; function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC; function comp_allzero(value : UNSIGNED) return STD_LOGIC; function comp_allzero(value : SIGNED) return STD_LOGIC; function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC; function comp_allone(value : UNSIGNED) return STD_LOGIC; function comp_allone(value : SIGNED) return STD_LOGIC; -- multiplexing function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC; function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED; function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED; end; package body components is -- d-flipflop with reset and enable function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is begin return ((d and en) or (q and not en)) and not rst; end function; function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR is begin return ((d and (q'range => en)) or (q and not (q'range => en))) and not (q'range => rst); end function; -- d-flipflop with set and enable function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is begin return ((d and en) or (q and not en)) or set; end function; -- t-flipflop with reset and enable function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is begin return ((not q and en) or (q and not en)) and not rst; end function; -- rs-flipflop with dominant rst function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is begin return (q or set) and not rst; end function; -- rs-flipflop with dominant set function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is begin return (q and not rst) or set; end function; -- adder function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR is begin return std_logic_vector(inc(unsigned(value), increment)); end function; function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED is begin return value + increment; end function; function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED is begin return value + increment; end function; function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR is begin return std_logic_vector(dec(unsigned(value), decrement)); end function; function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED is begin return value + decrement; end function; function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED is begin return value + decrement; end function; -- negate function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin return std_logic_vector(inc(unsigned(not value))); -- 2's complement end function; -- counter function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED is begin if (rst = '1') then return to_unsigned(init, cnt'length); elsif (en = '1') then return cnt + 1; else return cnt; end if; end function; function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC is begin -- optimized comparison for only up counting values return to_sl((cnt and to_unsigned(value, cnt'length)) = value); end function; function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED is begin if (rst = '1') then return to_signed(init, cnt'length); elsif (en = '1') then return cnt - 1; else return cnt; end if; end function; function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC is begin -- optimized comparison for only down counting values return to_sl((cnt nor to_signed(value, cnt'length)) /= value); end function; function downcounter_neg(cnt : SIGNED) return STD_LOGIC is begin return cnt(cnt'high); end function; -- shift/rotate registers function sr_left(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is begin return q(q'left - 1 downto q'right) & i; end function; function sr_right(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is begin return i & q(q'left downto q'right - 1); end function; function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin return q(q'left - 1 downto q'right) & q(q'left); end function; function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin return q(q'right) & q(q'left downto q'right - 1); end function; -- compare functions -- return value 1- => value1 < value2 (difference is negative) -- return value 00 => value1 = value2 (difference is zero) -- return value -1 => value1 > value2 (difference is positive) function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin report "Comparing two STD_LOGIC_VECTORs - implicit conversion to UNSIGNED" severity WARNING; return std_logic_vector(comp(unsigned(value1), unsigned(value2))); end function; function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is begin if (value1 < value2) then return "10"; elsif (value1 = value2) then return "00"; else return "01"; end if; end function; function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED is begin if (value1 < value2) then return "10"; elsif (value1 = value2) then return "00"; else return "01"; end if; end function; function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC is begin return comp_allzero(unsigned(value)); end function; function comp_allzero(value : UNSIGNED) return STD_LOGIC is begin return to_sl(value = (value'range => '0')); end function; function comp_allzero(value : SIGNED) return STD_LOGIC is begin return to_sl(value = (value'range => '0')); end function; function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC is begin return comp_allone(unsigned(value)); end function; function comp_allone(value : UNSIGNED) return STD_LOGIC is begin return to_sl(value = (value'range => '1')); end function; function comp_allone(value : SIGNED) return STD_LOGIC is begin return to_sl(value = (value'range => '1')); end function; -- multiplexing function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC is begin return (sl0 and not sel) or (sl1 and sel); end function; function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin return (slv0 and not (slv0'range => sel)) or (slv1 and (slv1'range => sel)); end function; function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED is begin return (us0 and not (us0'range => sel)) or (us1 and (us1'range => sel)); end function; function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED is begin return (s0 and not (s0'range => sel)) or (s1 and (s1'range => sel)); end function; END PACKAGE BODY;

agpl-3.0

8201e53a7d6b1d4f7e821c914f8f1b2d

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_rx_deglitcher.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_rx_deglitcher | -- | --------------------------------------------------------------------------------------------------- -- File wf_rx_deglitcher.vhd | -- | -- Description The unit applies a glitch filter to the nanoFIP FIELDRIVE input FD_RXD. | -- It is capable of cleaning glitches up to c_DEGLITCH_THRESHOLD uclk ticks long. | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 14/02/2011 | -- Version v0.03 | -- Depends on wf_reset_unit | ---------------- | -- Last changes | -- 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content | -- 23/08/2010 v0.02 EG code cleaned-up+commented | -- 14/02/2011 v0.03 EG complete change, no dependency on osc; | -- fd_rxd deglitched right at reception | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_rx_deglitcher --================================================================================================= entity wf_rx_deglitcher is port( -- INPUTS -- nanoFIP User Interface general signal uclk_i : in std_logic; -- 40 MHz clock -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- nanoFIP FIELDRIVE (synchronized with uclk) fd_rxd_a_i : in std_logic; -- receiver data -- OUTPUTS -- Signals to the wf_rx_deserializer unit fd_rxd_filt_o : out std_logic; -- filtered output signal fd_rxd_filt_edge_p_o : out std_logic; -- indicates an edge on the filtered signal fd_rxd_filt_f_edge_p_o : out std_logic);-- indicates a falling edge on the filtered signal end wf_rx_deglitcher; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_rx_deglitcher is signal s_fd_rxd_synch : std_logic_vector (1 downto 0); signal s_fd_rxd_filt, s_fd_rxd_filt_d1 : std_logic; signal s_fd_rxd_filt_r_edge_p, s_fd_rxd_filt_f_edge_p : std_logic; signal s_filt_c : unsigned (3 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- FD_RXD synchronization -- --------------------------------------------------------------------------------------------------- -- Synchronous process FD_RXD_synchronizer: Synchronization of the nanoFIP FIELDRIVE input -- FD_RXD to the uclk, using a set of 2 registers. FD_RXD_synchronizer: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_fd_rxd_synch <= (others => '0'); else s_fd_rxd_synch <= s_fd_rxd_synch(0) & fd_rxd_a_i; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Deglitching -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- Synchronous process FD_RXD_deglitcher: the output signal s_fd_rxd_filt is updated only -- after the accumulation of a sufficient (c_DEGLITCH_THRESHOLD + 1) amount of identical bits. -- The signal is therefore cleaned of any glitches up to c_DEGLITCH_THRESHOLD uclk ticks long. FD_RXD_deglitcher: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_filt_c <= to_unsigned (c_DEGLITCH_THRESHOLD, s_filt_c'length) srl 1;-- middle value s_fd_rxd_filt <= '0'; s_fd_rxd_filt_d1 <= '0'; else -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- if s_fd_rxd_synch(1) = '0' then -- arrival of a '0' if s_filt_c /= 0 then -- counter updated s_filt_c <= s_filt_c - 1; else s_fd_rxd_filt <= '0'; -- output updated end if; -- if counter = 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- elsif s_fd_rxd_synch(1) = '1' then -- arrival of a '1' if s_filt_c /= c_DEGLITCH_THRESHOLD then s_filt_c <= s_filt_c + 1; -- counter updated else s_fd_rxd_filt <= '1'; -- output updated end if; -- if counter = c_DEGLITCH_THRESHOLD end if; s_fd_rxd_filt_d1 <= s_fd_rxd_filt; -- used for the edges detection end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- Concurrent signal assignments s_fd_rxd_filt_r_edge_p <= (not s_fd_rxd_filt_d1) and s_fd_rxd_filt; -- pulse upon detection -- of a falling edge s_fd_rxd_filt_f_edge_p <= s_fd_rxd_filt_d1 and (not s_fd_rxd_filt); -- pulse upon detection -- of a rising edge fd_rxd_filt_edge_p_o <= s_fd_rxd_filt_f_edge_p or s_fd_rxd_filt_r_edge_p; fd_rxd_filt_f_edge_p_o <= s_fd_rxd_filt_f_edge_p; fd_rxd_filt_o <= s_fd_rxd_filt; end rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

6deff1c08ea25fefb50fa3dcfb45d4b5

wltr/cern-fgclite

critical_fpga/src/rtl/cf/ab.vhd

------------------------------------------------------------------------------- --! @file ab.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-08 --! @brief Analogue board control and filters. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.ab_pkg.all; use work.nf_pkg.all; use work.ads1281_filter_pkg.all; --! @brief Entity declaration of ab --! @details --! This component controls the analogue board switches, DAC and ADCs. It --! also provides FIR filter implementations for the ADCs and has an internal --! pattern generator for test purposes. entity ab is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Analogue board interface --! @{ --! Inputs ab_i : in ab_in_t; --! Outputs ab_o : out ab_out_t; --! @} --! @name Internal interface --! @{ --! Millisecond strobe ms_strobe_i : in std_ulogic; --! Millisecond strobe indicating start of cycle ms_0_strobe_i : in std_ulogic; --! Commands command_i : in nf_command_t; --! SEFI detector sefi_o : out std_ulogic_vector(5 downto 0); --! Voltage reference when ramping down pf_vref_i : in std_ulogic_vector(15 downto 0); --! Voltage reference enable pf_vref_en_i : in std_ulogic; --! Voltage reference override pf_vref_ovr_i : in std_ulogic; --! @} --! @name ADC results --! @{ --! ADC VS result adc_vs_o : out std_ulogic_vector(23 downto 0); --! ADC VS result enable adc_vs_en_o : out std_ulogic; --! ADC IA result adc_ia_o : out std_ulogic_vector(23 downto 0); --! ADC IA result enable adc_ia_en_o : out std_ulogic; --! ADC IB result adc_ib_o : out std_ulogic_vector(23 downto 0); --! ADC IB result enable adc_ib_en_o : out std_ulogic; --! @} --! @name Accumulator results --! @{ --! Accumulator VS result acc_vs_o : out std_ulogic_vector(31 downto 0); --! Accumulator VS result enable acc_vs_en_o : out std_ulogic; --! Accumulator IA result acc_ia_o : out std_ulogic_vector(31 downto 0); --! Accumulator IA result enable acc_ia_en_o : out std_ulogic; --! Accumulator IB result acc_ib_o : out std_ulogic_vector(31 downto 0); --! Accumulator IB result enable acc_ib_en_o : out std_ulogic); --! @} end entity ab; --! RTL implementation of ab architecture rtl of ab is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type acc_result_t is array (0 to 2) of std_ulogic_vector(27 downto 0); type sefi_mode_t is array (0 to 5) of std_ulogic_vector(1 downto 0); --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal adc_m0 : std_ulogic_vector(2 downto 0); signal adc_m1 : std_ulogic_vector(2 downto 0); signal adc_result : ads1281_filter_result_t; signal adc_result_en : std_ulogic_vector(2 downto 0); signal acc_result : acc_result_t; signal acc_result_en : std_ulogic_vector(2 downto 0); signal ab : ab_out_t; signal sample_strb : std_ulogic; signal adc_m : std_ulogic_vector(5 downto 0); signal sefi_in : std_ulogic_vector(5 downto 0); signal sefi_mode : sefi_mode_t; signal vref : std_ulogic_vector(15 downto 0); signal vref_en : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- -- Power up analogue board ab_o.pwr_on_n <= '0'; -- Start temperature control on analogue board ab_o.temp_stop <= '0'; ab_o.cal_dac <= ab.cal_dac; ab_o.cal_offset <= ab.cal_offset; ab_o.cal_vref_p <= ab.cal_vref_p; ab_o.cal_vref_n <= ab.cal_vref_n; ab_o.adc_vs_rst_n <= ab.adc_vs_rst_n; ab_o.sw_in_vs <= ab.sw_in_vs; ab_o.adc_a_rst_n <= ab.adc_a_rst_n; ab_o.sw_in_a <= ab.sw_in_a; ab_o.adc_b_rst_n <= ab.adc_b_rst_n; ab_o.sw_in_b <= ab.sw_in_b; adc_vs_o <= adc_result(0); adc_vs_en_o <= adc_result_en(0); adc_ia_o <= adc_result(1); adc_ia_en_o <= adc_result_en(1); adc_ib_o <= adc_result(2); adc_ib_en_o <= adc_result_en(2); acc_vs_o(31 downto 28) <= (31 downto 28 => acc_result(0)(acc_result(0)'high)); acc_vs_o(27 downto 0) <= acc_result(0); acc_vs_en_o <= acc_result_en(0); acc_ia_o(31 downto 28) <= (31 downto 28 => acc_result(1)(acc_result(1)'high)); acc_ia_o(27 downto 0) <= acc_result(1); acc_ia_en_o <= acc_result_en(1); acc_ib_o(31 downto 28) <= (31 downto 28 => acc_result(2)(acc_result(2)'high)); acc_ib_o(27 downto 0) <= acc_result(2); acc_ib_en_o <= acc_result_en(2); --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- adc_m0 <= ab_i.adc_vs(0) & ab_i.adc_a(0) & ab_i.adc_b(0); adc_m1 <= ab_i.adc_vs(1) & ab_i.adc_a(1) & ab_i.adc_b(1); adc_m <= ab_i.adc_b & ab_i.adc_a & ab_i.adc_vs; sefi_mode(0) <= command_i.sefi_test_vs_m0; sefi_mode(1) <= command_i.sefi_test_vs_m1; sefi_mode(2) <= command_i.sefi_test_ia_m0; sefi_mode(3) <= command_i.sefi_test_ia_m1; sefi_mode(4) <= command_i.sefi_test_ib_m0; sefi_mode(5) <= command_i.sefi_test_ib_m1; vref <= pf_vref_i when pf_vref_ovr_i = '1' else command_i.v_ref; vref_en <= pf_vref_en_i when pf_vref_ovr_i = '1' else ms_0_strobe_i; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! SEFI detector test sefi_test_gen : for i in 0 to 5 generate sefi_test_inst : entity work.sefi_detector_test port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, ms_0_strobe_i => ms_0_strobe_i, en_i => command_i.vs_cmd(0), mode_i => sefi_mode(i), strb_i => sample_strb, adc_i => adc_m(i), test_o => sefi_in(i)); end generate sefi_test_gen; --! SEFI detectors sefi_detector_gen : for i in 0 to 5 generate sefi_detector_inst : entity work.sefi_detector generic map ( num_g => 30) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => ms_0_strobe_i, en_i => sample_strb, sig_i => sefi_in(i), sefi_o => sefi_o(i)); end generate sefi_detector_gen; --! Analogue board DAC interface max5541_interface_inst : entity work.max5541_interface port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, data_i => vref, data_en_i => vref_en, busy_o => open, done_o => open, cs_o => ab_o.dac_cs, sclk_o => ab_o.dac_sclk, din_o => ab_o.dac_din); --! ADS1281 filter ads1281_filter_inst : entity work.ads1281_filter port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, strb_ms_i => ms_strobe_i, strb_sample_o => sample_strb, adc_m0_i => adc_m0, adc_m1_i => adc_m1, result_o => adc_result, result_en_o => adc_result_en); --! ADS1281 result accumulator ads1281_result_accumulator_gen : for i in 0 to 2 generate ads1281_result_accumulator_inst : entity work.ads1281_result_accumulator generic map ( num_results_g => 10) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => ms_0_strobe_i, result_i => adc_result(i), result_en_i => adc_result_en(i), result_o => acc_result(i), result_en_o => acc_result_en(i)); end generate ads1281_result_accumulator_gen; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_p <= '0'; ab.cal_vref_n <= '0'; ab.adc_vs_rst_n <= '1'; ab.sw_in_vs <= '0'; ab.adc_a_rst_n <= '1'; ab.sw_in_a <= '0'; ab.adc_b_rst_n <= '1'; ab.sw_in_b <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; elsif ms_0_strobe_i = '1' then case command_i.cal_source is when "00" => ab.cal_dac <= '0'; ab.cal_offset <= '1'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '0'; when "01" => ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '1'; when "10" => ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_n <= '1'; ab.cal_vref_p <= '0'; when "11" => ab.cal_dac <= '1'; ab.cal_offset <= '0'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '0'; when others => null; end case; ab.adc_vs_rst_n <= command_i.adc_vs_reset_n; ab.adc_a_rst_n <= command_i.adc_ia_reset_n; ab.adc_b_rst_n <= command_i.adc_ib_reset_n; if command_i.vs_cmd(0) = '0' then ab.sw_in_vs <= command_i.cal_vs_en; ab.sw_in_a <= command_i.cal_ia_en; ab.sw_in_b <= command_i.cal_ib_en; else ab.sw_in_vs <= '0'; ab.sw_in_a <= '0'; ab.sw_in_b <= '0'; end if; end if; end if; end process regs; end architecture rtl;

mit

f6c2aee3439e8916e76674475992ad0d

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_float.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

079a63acf9c65477bf1d4e014cd772c3

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_2AXI_2CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

c5638b1cf009292e0cff592f8a3ca1c4

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/synth/VOICE_ROM_INIT.vhd

-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_2; USE blk_mem_gen_v8_2.blk_mem_gen_v8_2; ENTITY VOICE_ROM_INIT IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END VOICE_ROM_INIT; ARCHITECTURE VOICE_ROM_INIT_arch OF VOICE_ROM_INIT IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF VOICE_ROM_INIT_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_2 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); sleep : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_2; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF VOICE_ROM_INIT_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF VOICE_ROM_INIT_arch : ARCHITECTURE IS "VOICE_ROM_INIT,blk_mem_gen_v8_2,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF VOICE_ROM_INIT_arch: ARCHITECTURE IS "VOICE_ROM_INIT,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=VOICE_ROM_INIT.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=64,C_READ_DEPTH_A=64,C_ADDRA_WIDTH=6,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=64,C_READ_DEPTH_B=64,C_ADDRB_WIDTH=6,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.01735 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; BEGIN U0 : blk_mem_gen_v8_2 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 1, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 0, C_INIT_FILE_NAME => "no_coe_file_loaded", C_INIT_FILE => "VOICE_ROM_INIT.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 0, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 16, C_READ_WIDTH_A => 16, C_WRITE_DEPTH_A => 64, C_READ_DEPTH_A => 64, C_ADDRA_WIDTH => 6, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 16, C_READ_WIDTH_B => 16, C_WRITE_DEPTH_B => 64, C_READ_DEPTH_B => 64, C_ADDRB_WIDTH => 6, C_HAS_MEM_OUTPUT_REGS_A => 0, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "0", C_COUNT_18K_BRAM => "1", C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.01735 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => '0', regcea => '0', wea => wea, addra => addra, dina => dina, clkb => clkb, rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => addrb, dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)), doutb => doutb, injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END VOICE_ROM_INIT_arch;

mit

55c629036c4a6883a57c195a28c96620

dtysky/LD3320_AXI

hdl/VOICE_DELAY.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_misc.all; use ieee.std_logic_unsigned.all; entity VOICE_DELAY is port ( clk:in std_logic; start:in std_logic:='0'; total:in std_logic_vector(7 downto 0); finish:out std_logic:='1' ); end entity; architecture delayx of VOICE_DELAY is signal delay_total:integer range 0 to 511:=0; signal start_last:std_logic; begin process(clk) variable con:integer range 0 to 400:=0; begin if clk'event and clk='1' then start_last<=start; if start_last='0' and start='1' then con:=1; delay_total<=conv_integer(total); finish<='0'; end if; if con=400 then if delay_total=0 then finish<='1'; con:=0; else delay_total<=delay_total-1; con:=1; end if; elsif con>0 then con:=con+1; end if; end if; end process; end delayx;

mit

3f9ffdd4bf55d4eb63ed4697c427dcc8

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_prod_data_lgth_calc.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_prod_data_lgth_calc | -- | --------------------------------------------------------------------------------------------------- -- File wf_prod_data_lgth_calc.vhd | -- | -- Description Calculation of the number of bytes, after the FSS and before the FCS, that have to| -- be transferred when a variable is produced (var_pres, var_identif, var_3, var_5) | -- As the following figure indicates, in detail, the unit adds-up: | -- o 1 byte RP_DAT.CTRL, | -- o 1 byte RP_DAT.Data.PDU_TYPE, | -- o 1 byte RP_DAT.Data.LGTH, | -- o 1-124 RP_DAT.Data.User_Data bytes according to the variable type: | -- - var_pres: 5 bytes | -- - var_pres: 8 bytes | -- - var_5 : 1 byte | -- - var_3 : 2-124 bytes defined by the "nanoFIP User Interface,General signal"| -- SLONE and the "nanoFIP WorldFIP Settings" input P3_LGTH, | -- o 1 byte RP_DAT.Data.nanoFIP_status, always for a var_5 | -- and for a var_3, if the "nanoFIP User | -- Interface General signal"NOSTAT is negated,| -- o 1 byte RP_DAT.Data.MPS_status, for a var_3 and a var_5 | -- | -- | -- Reminder: | -- | -- Produced RP_DAT frame structure : | -- ||--------------------- Data ---------------------|| | -- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ | -- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| | -- | -- |-----P3_LGTH-----| | -- | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 09/12/2010 | -- Version v0.02 | -- Depends on wf_engine_control | ---------------- | -- Last changes | -- 12/2010 v0.02 EG code cleaned-up+commented | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_prod_data_lgth_calc --================================================================================================= entity wf_prod_data_lgth_calc is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- nanoFIP WorldFIP Settings p3_lgth_i : in std_logic_vector (2 downto 0); -- produced var user-data length -- User Interface, General signals nostat_i : in std_logic; -- if negated, nFIP status is sent slone_i : in std_logic; -- stand-alone mode -- Signal from the wf_engine_control unit var_i : in t_var; -- variable type that is being treated -- OUTPUT -- Signal to the wf_engine_control and wf_production units prod_data_lgth_o : out std_logic_vector (7 downto 0)); end entity wf_prod_data_lgth_calc; --================================================================================================= -- architecture declaration --================================================================================================= architecture behavior of wf_prod_data_lgth_calc is signal s_prod_data_lgth, s_p3_lgth_decoded : unsigned (7 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Combinatorial process data_length_calcul: calculation of the amount of bytes, after the -- FSS and before the FCS, that have to be transferred when a variable is produced. In the case -- of the presence, the identification and the var5 variables, the data length is predefined in the -- WF_PACKAGE. In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the -- calculation. data_length_calcul: process (var_i, s_p3_lgth_decoded, slone_i, nostat_i, p3_lgth_i) begin s_p3_lgth_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i))); case var_i is -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_presence => -- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE) s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_identif => -- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE) s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_3 => -- data length calculation according to the operational mode (memory or stand-alone) -- in slone mode 2 bytes of user-data are produced (independently of P3_LGTH) -- to these there should be added: 1 byte CTRL -- 1 byte PDU_TYPE -- 1 byte LGTH -- 1 byte MPS status -- optionally 1 byte nFIP status -- in memory mode the signal "s_p3_lgth_decoded" indicates the amount of user-data; -- to these, there should be added 1 byte CTRL -- 1 byte PDU_TYPE -- 1 byte LGTH -- 1 byte MPS status -- optionally 1 byte nFIP status if slone_i = '1' then if nostat_i = '1' then -- 6 bytes (counting starts from 0!) s_prod_data_lgth <= to_unsigned(5, s_prod_data_lgth'length); else -- 7 bytes s_prod_data_lgth <= to_unsigned(6, s_prod_data_lgth'length); end if; else if nostat_i = '0' then s_prod_data_lgth <= s_p3_lgth_decoded + 4; else s_prod_data_lgth <= s_p3_lgth_decoded + 3; end if; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_5 => -- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE) s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_5_INDEX).array_lgth; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when others => s_prod_data_lgth <= (others => '0'); end case; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Registration of the output (coz of slack) Prod_Data_Lgth_Reg: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then prod_data_lgth_o <= (others =>'0'); else prod_data_lgth_o <= std_logic_vector (s_prod_data_lgth); end if; end if; end process; end architecture behavior; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

12d2c083d3fae2e0cb623af9803563b7

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_crc.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_crc | -- | --------------------------------------------------------------------------------------------------- -- File wf_crc.vhd | -- | -- Description The unit creates the modules for: | -- o the generation of the CRC of serial data, | -- o the verification of an incoming CRC syndrome. | -- The unit is instantiated in both the wf_fd_transmitter, for the generation of the | -- FCS field of produced RP_DAT frames, and the wf_fd_receiver for the validation of | -- of an incoming ID_DAT or consumed RP_DAT frame. | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Date 23/02/2011 | -- Version v0.04 | -- Depends on wf_reset_unit | -- wf_rx_deserializer | -- wf_tx_serializer | ---------------- | -- Last changes | -- 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content | -- 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed, | -- variable v_q_check_mask replaced with a signal, | -- code cleaned-up+commented | -- 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list! | -- xor replaced with if(Syndrome_Verification); processes rewritten; | -- delay on data_bit_ready_p_i removed. | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_crc --================================================================================================= entity wf_crc is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- Signals from the wf_rx_deserializer/ wf_tx_serializer units data_bit_i : in std_logic; -- incoming data bit stream data_bit_ready_p_i : in std_logic; -- indicates the sampling moment of data_bit_i start_crc_p_i : in std_logic; -- beginning of the CRC calculation -- OUTPUTS -- Signal to the wf_rx_deserializer unit crc_ok_p_o : out std_logic; -- signals a correct received CRC syndrome -- Signal to the wf_tx_serializer unit crc_o : out std_logic_vector (c_CRC_POLY_LGTH-1 downto 0)); -- calculated CRC end entity wf_crc; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_crc is signal s_q, s_q_nx : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- CRC Calculation -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1 -- of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which -- are interconnected as a linear feedback shift register. Generate_16_bit_Register_and_Interconnections: s_q_nx(0) <= data_bit_i xor s_q(s_q'left); G: for I in 1 to c_CRC_GENER_POLY'left generate s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left))); end generate; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Synchronous process CRC_calculation: the process "moves" the shift register described -- above, for the calculation of the CRC. CRC_calculation: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_q <= (others => '0'); else if start_crc_p_i = '1' then s_q <= (others => '1'); -- register initialization -- (initially preset, according to the Annex) elsif data_bit_ready_p_i = '1' then -- new bit to be considered for the CRC calculation s_q <= s_q_nx; -- data propagation end if; end if; end if; end process; -- -- -- -- -- crc_o <= not s_q; --------------------------------------------------------------------------------------------------- -- CRC Verification -- --------------------------------------------------------------------------------------------------- -- During reception, the CRC is being calculated as data is arriving (same as in the transmission) -- and at the same time it is being compared to the predefined c_CRC_VERIF_POLY. When the CRC -- calculated from the received data matches the c_CRC_VERIF_POLY, it is implied that a correct CRC -- word has been received for the preceded data and the signal crc_ok_p_o gives a 1 uclk-wide pulse. crc_ok_p_o <= data_bit_ready_p_i when s_q = not c_CRC_VERIF_POLY else '0'; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

1cc1584fdadefe0fa117264303ad4bf0

preusser/q27

src/vhdl/top/dnk7_f5/dnk7_queens1.vhdl

library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity dnk7_queens1 is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 240; COUNT_CYCLES : boolean := false; -- Local Clock Parameters CLK_FREQ : FREQ := 50 MHz; CLK_DIV : positive := 1; -- CLK_FREQ / CLK_DIV * CLK_MUL: CLK_MUL : positive := 22; -- as fast as possible but not above 1200 MHz -- Output Clocks CLK_DIV_COMP : positive := 5; -- fast computation clock CLK_DIV_SLOW : positive := 15 -- slower communication clock ); port ( --------------------------------------------------------------------------- -- 50-MHz Input Clock CLK_MBCLK : in std_logic; --------------------------------------------------------------------------- -- Ring Bus -- Input BUS_IN_CLKP : in std_logic; BUS_IN_CLKN : in std_logic; BUS_IN_PRE_DAT : in std_logic_vector(8 downto 0); BUS_IN_PRE_PUT : in std_logic; BUS_IN_PRE_STALL : out std_logic; BUS_IN_SOL_DAT : in std_logic_vector(8 downto 0); BUS_IN_SOL_PUT : in std_logic; BUS_IN_SOL_STALL : out std_logic; -- Output BUS_OUT_CLKP : out std_logic; BUS_OUT_CLKN : out std_logic; BUS_OUT_PRE_DAT : out std_logic_vector(8 downto 0); BUS_OUT_PRE_PUT : out std_logic; BUS_OUT_PRE_STALL : in std_logic; BUS_OUT_SOL_DAT : out std_logic_vector(8 downto 0); BUS_OUT_SOL_PUT : out std_logic; BUS_OUT_SOL_STALL : in std_logic ); end entity dnk7_queens1; library IEEE; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.fifo.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of dnk7_queens1 is -- Bit Length of Pre-Placement constant PRE_BITS : positive := 4*L*log2ceil(N)-1; constant PRE_BYTES : positive := (PRE_BITS+7)/8; -- FIFO Dimensioning constant FIFO_DEPTH : positive := 5*(SOLVERS+5); ---------------------------------------------------------------------------- -- Global Control: Clocks and Resets signal clk_comp : std_logic; -- FRESHLY generated: signal rst_comp : std_logic; -- Fast Computation Clock signal clk_out : std_logic; -- FRESHLY generated: signal rst_out : std_logic; -- Slow Communication Clock (Output Side) ----------------------------------------------------------------------------- -- Solver Chain Connectivity signal piful : std_logic; signal pidat : byte; signal pieof : std_logic; signal piput : std_logic; signal sivld : std_logic; signal sidat : byte; signal sieof : std_logic; signal sigot : std_logic; signal poful : std_logic; signal podat : byte; signal poeof : std_logic; signal poput : std_logic; signal sovld : std_logic; signal sodat : byte; signal soeof : std_logic; signal sogot : std_logic; begin ---------------------------------------------------------------------------- -- Clock Generation blkClock: block -- Intermediate Clock Signals signal clk50 : std_logic; signal clkfb : std_logic; signal clk_compu : std_logic; signal clk_outu : std_logic; begin --------------------------------------------------------------------------- -- Freshly Generated clk_i : BUFG port map ( I => CLK_MBCLK, O => clk50 ); pll : PLLE2_BASE generic map ( CLKIN1_PERIOD => to_real(to_time(CLK_FREQ), 1 ns), DIVCLK_DIVIDE => CLK_DIV, CLKFBOUT_MULT => CLK_MUL, CLKOUT0_DIVIDE => CLK_DIV_COMP, CLKOUT1_DIVIDE => CLK_DIV_SLOW, STARTUP_WAIT => "true" ) port map ( RST => '0', CLKIN1 => clk50, CLKFBOUT => clkfb, CLKFBIN => clkfb, CLKOUT0 => clk_compu, CLKOUT1 => clk_outu, CLKOUT2 => open, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, LOCKED => open, PWRDWN => '0' ); clk_compo : BUFG port map ( I => clk_compu, O => clk_comp ); rst_comp <= '0'; clk_outo : BUFG port map ( I => clk_outu, O => clk_out ); rst_out <= '0'; end block blkClock; --------------------------------------------------------------------------- -- Solver Chain blChain: block is signal pful : std_logic; signal pdat : byte; signal peof : std_logic; signal pput : std_logic; begin chain: entity work.queens_chain generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES ) port map ( clk => clk_comp, rst => rst_comp, piful => piful, pidat => pidat, pieof => pieof, piput => piput, sivld => '0', sidat => (others => '-'), sieof => '-', sigot => open, poful => pful, podat => pdat, poeof => peof, poput => pput, sovld => sovld, sodat => sodat, soeof => soeof, sogot => sogot ); -- Resync stream so that frames are taken out in one piece sync: entity work.msg_tap generic map ( D => PRE_BYTES ) port map ( clk => clk_comp, rst => rst_comp, iful => pful, idat => pdat, ieof => peof, iput => pput, oful => poful, odat => podat, oeof => poeof, oput => poput, tful => '1', tdat => open, tput => open ); end block blChain; ----------------------------------------------------------------------------- -- Input Stream -> feeds pi(ful|dat|eof|put) and si(vld|dat|eof|got) blkInput: block -- Source synchronous clock domain signal clk_in : std_logic; signal rst_in : std_logic; -- Incoming Bus Data Capture Registers signal InPreDat : std_logic_vector(8 downto 0) := (others => '-'); signal InPrePut : std_logic := '0'; signal InPreCap : std_logic_vector(1 downto 0); signal InSolDat : std_logic_vector(8 downto 0) := (others => '-'); signal InSolPut : std_logic := '0'; signal InSolCap : std_logic_vector(1 downto 0); signal pivld : std_logic; begin --------------------------------------------------------------------------- -- Reading the Bus -- Clock reconstruction blkClock: block signal clk_in0 : std_logic; begin IBUFGDS_inst : IBUFGDS port map ( O => clk_in0, I => BUS_IN_CLKP, IB => BUS_IN_CLKN ); BUFG_inst : BUFG port map ( O => clk_in, I => clk_in0 ); rst_in <= '0'; end block blkClock; -- Bus Input Capture process(clk_in) begin if rising_edge(clk_in) then if rst_in = '1' then InPreDat <= (others => '-'); InPrePut <= '0'; InSolDat <= (others => '-'); InSolPut <= '0'; else InPreDat <= BUS_IN_PRE_DAT; InPrePut <= BUS_IN_PRE_PUT; InSolDat <= BUS_IN_SOL_DAT; InSolPut <= BUS_IN_SOL_PUT; end if; end if; end process; -- Input FIFO (ic): Pre-Placements buf_pre : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InPreCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InPrePut, din => InPreDat, full => open, estate_wr => InPreCap, clk_rd => clk_comp, rst_rd => rst_comp, got => piput, dout(8) => pieof, dout(7 downto 0) => pidat, valid => pivld ); piput <= pivld and not piful; BUS_IN_PRE_STALL <= '1' when InPreCap = (InPreCap'range => '0') else '0'; -- Input FIFO (ic): Solutions buf_sol : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InSolCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InSolPut, din => InSolDat, full => open, estate_wr => InSolCap, clk_rd => clk_out, rst_rd => rst_out, got => sigot, dout(8) => sieof, dout(7 downto 0) => sidat, valid => sivld ); BUS_IN_SOL_STALL <= '1' when InSolCap = (InSolCap'range => '0') else '0'; end block blkInput; blkOutput : block begin ------------------------------------------------------------------------- -- Output Inverted Clock blkClock : block signal clk_inv : std_logic; begin invert : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '1', SRTYPE => "SYNC" ) port map ( Q => clk_inv, -- 1-bit DDR output C => clk_out, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D1 => '0', -- 1-bit data input (positive edge) D2 => '1', -- 1-bit data input (negative edge) R => rst_out, -- 1-bit reset input S => '0' -- 1-bit set input ); OBUFDS_inst : OBUFDS generic map ( IOSTANDARD => "DEFAULT", SLEW => "FAST" ) port map ( O => BUS_OUT_CLKP, OB => BUS_OUT_CLKN, I => clk_inv ); end block blkClock; blkPre: block -- Syncing the stall input signal stall_s : std_logic_vector(1 downto 0) := (others => '1'); -- Output FIFO signal pgot : std_logic; signal pdat : std_logic_vector(8 downto 0); signal pvld : std_logic; -- Outgoing Output Registers signal PreOutDat : std_logic_vector(8 downto 0) := (others => '0'); signal PreOutPut : std_logic := '0'; begin -- Syncing stall input process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then stall_s <= (others => '1'); else stall_s <= BUS_OUT_PRE_STALL & stall_s(stall_s'left downto 1); end if; end if; end process; -- Output FIFO (ic): Pre-Placements fifob : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64 ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => poput, din(8) => poeof, din(7 downto 0) => podat, full => poful, clk_rd => clk_out, rst_rd => rst_out, got => pgot, dout => pdat, valid => pvld ); pgot <= pvld and not stall_s(0); -- Output Registers process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then PreOutDat <= (others => '0'); PreOutPut <= '0'; else PreOutDat <= pdat; PreOutPut <= pgot; end if; end if; end process; BUS_OUT_PRE_DAT <= PreOutDat; BUS_OUT_PRE_PUT <= PreOutPut; end block blkPre; blkSol: block -- Syncing the stall input signal stall_s : std_logic_vector(1 downto 0) := (others => '1'); -- Chain -> fifo_ic [clk_comp->clk_out] signal soful : std_logic; -- fifo_ic -> funnel signal scvld : std_logic; signal scdat : std_logic_vector(8 downto 0); signal scgot : std_logic; -- funnel -> fifo_glue signal sjful : std_logic; signal sjdat : std_logic_vector(8 downto 0); signal sjput : std_logic; -- fifo_glue -> output signal sfvld : std_logic; signal sfdat : std_logic_vector(8 downto 0); signal sfgot : std_logic; -- Outgoing Output Registers signal SolOutDat : std_logic_vector(8 downto 0) := (others => '0'); signal SolOutPut : std_logic := '0'; begin -- Syncing stall input process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then stall_s <= (others => '1'); else stall_s <= BUS_OUT_SOL_STALL & stall_s(stall_s'left downto 1); end if; end if; end process; -- fifo_ic: clk_comp -> clk_out fifob : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64 ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => sogot, din(8) => soeof, din(7 downto 0) => sodat, full => soful, clk_rd => clk_out, rst_rd => rst_out, got => scgot, dout => scdat, valid => scvld ); sogot <= sovld and not soful; -- funnel: si* + sc* -> sj* join: entity work.msg_funnel generic map ( N => 2 ) port map ( clk => clk_out, rst => rst_out, ivld(0) => scvld, ivld(1) => sivld, idat(0) => scdat(7 downto 0), idat(1) => sidat, ieof(0) => scdat(8), ieof(1) => sieof, igot(0) => scgot, igot(1) => sigot, oful => sjful, odat => sjdat(7 downto 0), oeof => sjdat(8), oput => sjput ); -- fifo_glue glue: fifo_glue generic map ( D_BITS => 9 ) port map ( clk => clk_out, rst => rst_out, put => sjput, di => sjdat, ful => sjful, vld => sfvld, do => sfdat, got => sfgot ); sfgot <= sfvld and not stall_s(0); -- Output Registers process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then SolOutDat <= (others => '0'); SolOutPut <= '0'; else SolOutDat <= sfdat; SolOutPut <= sfgot; end if; end if; end process; BUS_OUT_SOL_DAT <= SolOutDat; BUS_OUT_SOL_PUT <= SolOutPut; end block blkSol; end block blkOutput; end rtl;

agpl-3.0

5c6157a2c1b6f385b24d2a38c1658c61

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_incr_counter.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_incr_counter | -- | --------------------------------------------------------------------------------------------------- -- File wf_incr_counter.vhd | -- Description Increasing counter with synchronous reinitialise and increase enable | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 01/2011 | -- Version v0.011 | -- Depends on - | ---------------- | -- Last changes | -- 10/2010 EG v0.01 first version | -- 01/2011 EG v0.011 counter_full became a constant | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_incr_counter --================================================================================================= entity wf_incr_counter is generic(g_counter_lgth : natural := 4); -- default length port( -- INPUTS -- nanoFIP User Interface general signal uclk_i : in std_logic; -- 40 MHz clock -- Signals from any unit counter_incr_i : in std_logic; -- increment enable counter_reinit_i : in std_logic; -- reinitializes counter to 0 -- OUTPUT -- Signal to any unit counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter counter_is_full_o : out std_logic); -- counter full indication -- (all bits to '1') end entity wf_incr_counter; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_incr_counter is constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1'); signal s_counter : unsigned (g_counter_lgth-1 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Synchronous process Incr_Counter Incr_Counter: process (uclk_i) begin if rising_edge (uclk_i) then if counter_reinit_i = '1' then s_counter <= (others => '0'); elsif counter_incr_i = '1' then s_counter <= s_counter + 1; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- counter_o <= s_counter; counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0'; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

dcfc2a40e7952cda7ee5404ad8c510c1