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#pragma once |
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#include <stdint.h> |
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#define CPUINFO_ARM_MIDR_IMPLEMENTER_MASK UINT32_C(0xFF000000) |
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#define CPUINFO_ARM_MIDR_VARIANT_MASK UINT32_C(0x00F00000) |
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#define CPUINFO_ARM_MIDR_ARCHITECTURE_MASK UINT32_C(0x000F0000) |
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#define CPUINFO_ARM_MIDR_PART_MASK UINT32_C(0x0000FFF0) |
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#define CPUINFO_ARM_MIDR_REVISION_MASK UINT32_C(0x0000000F) |
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#define CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET 24 |
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#define CPUINFO_ARM_MIDR_VARIANT_OFFSET 20 |
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#define CPUINFO_ARM_MIDR_ARCHITECTURE_OFFSET 16 |
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#define CPUINFO_ARM_MIDR_PART_OFFSET 4 |
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#define CPUINFO_ARM_MIDR_REVISION_OFFSET 0 |
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#define CPUINFO_ARM_MIDR_ARM1156 UINT32_C(0x410FB560) |
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#define CPUINFO_ARM_MIDR_CORTEX_A7 UINT32_C(0x410FC070) |
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#define CPUINFO_ARM_MIDR_CORTEX_A9 UINT32_C(0x410FC090) |
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#define CPUINFO_ARM_MIDR_CORTEX_A15 UINT32_C(0x410FC0F0) |
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#define CPUINFO_ARM_MIDR_CORTEX_A17 UINT32_C(0x410FC0E0) |
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#define CPUINFO_ARM_MIDR_CORTEX_A35 UINT32_C(0x410FD040) |
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#define CPUINFO_ARM_MIDR_CORTEX_A53 UINT32_C(0x410FD030) |
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#define CPUINFO_ARM_MIDR_CORTEX_A55 UINT32_C(0x410FD050) |
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#define CPUINFO_ARM_MIDR_CORTEX_A57 UINT32_C(0x410FD070) |
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#define CPUINFO_ARM_MIDR_CORTEX_A72 UINT32_C(0x410FD080) |
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#define CPUINFO_ARM_MIDR_CORTEX_A73 UINT32_C(0x410FD090) |
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#define CPUINFO_ARM_MIDR_CORTEX_A75 UINT32_C(0x410FD0A0) |
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#define CPUINFO_ARM_MIDR_KRYO280_GOLD UINT32_C(0x51AF8001) |
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#define CPUINFO_ARM_MIDR_KRYO280_SILVER UINT32_C(0x51AF8014) |
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#define CPUINFO_ARM_MIDR_KRYO385_GOLD UINT32_C(0x518F802D) |
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#define CPUINFO_ARM_MIDR_KRYO385_SILVER UINT32_C(0x518F803C) |
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#define CPUINFO_ARM_MIDR_KRYO_SILVER_821 UINT32_C(0x510F2010) |
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#define CPUINFO_ARM_MIDR_KRYO_GOLD UINT32_C(0x510F2050) |
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#define CPUINFO_ARM_MIDR_KRYO_SILVER_820 UINT32_C(0x510F2110) |
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#define CPUINFO_ARM_MIDR_EXYNOS_M1_M2 UINT32_C(0x530F0010) |
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#define CPUINFO_ARM_MIDR_DENVER2 UINT32_C(0x4E0F0030) |
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inline static uint32_t midr_set_implementer(uint32_t midr, uint32_t implementer) { |
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return (midr & ~CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) | |
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((implementer << CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET) & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK); |
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} |
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inline static uint32_t midr_set_variant(uint32_t midr, uint32_t variant) { |
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return (midr & ~CPUINFO_ARM_MIDR_VARIANT_MASK) | |
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((variant << CPUINFO_ARM_MIDR_VARIANT_OFFSET) & CPUINFO_ARM_MIDR_VARIANT_MASK); |
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} |
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inline static uint32_t midr_set_architecture(uint32_t midr, uint32_t architecture) { |
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return (midr & ~CPUINFO_ARM_MIDR_ARCHITECTURE_MASK) | |
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((architecture << CPUINFO_ARM_MIDR_ARCHITECTURE_OFFSET) & CPUINFO_ARM_MIDR_ARCHITECTURE_MASK); |
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} |
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inline static uint32_t midr_set_part(uint32_t midr, uint32_t part) { |
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return (midr & ~CPUINFO_ARM_MIDR_PART_MASK) | |
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((part << CPUINFO_ARM_MIDR_PART_OFFSET) & CPUINFO_ARM_MIDR_PART_MASK); |
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} |
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inline static uint32_t midr_set_revision(uint32_t midr, uint32_t revision) { |
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return (midr & ~CPUINFO_ARM_MIDR_REVISION_MASK) | |
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((revision << CPUINFO_ARM_MIDR_REVISION_OFFSET) & CPUINFO_ARM_MIDR_REVISION_MASK); |
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} |
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inline static uint32_t midr_get_variant(uint32_t midr) { |
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return (midr & CPUINFO_ARM_MIDR_VARIANT_MASK) >> CPUINFO_ARM_MIDR_VARIANT_OFFSET; |
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} |
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inline static uint32_t midr_get_implementer(uint32_t midr) { |
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return (midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) >> CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET; |
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} |
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inline static uint32_t midr_get_part(uint32_t midr) { |
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return (midr & CPUINFO_ARM_MIDR_PART_MASK) >> CPUINFO_ARM_MIDR_PART_OFFSET; |
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} |
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inline static uint32_t midr_get_revision(uint32_t midr) { |
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return (midr & CPUINFO_ARM_MIDR_REVISION_MASK) >> CPUINFO_ARM_MIDR_REVISION_OFFSET; |
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} |
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inline static uint32_t midr_copy_implementer(uint32_t midr, uint32_t other_midr) { |
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return (midr & ~CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) | (other_midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK); |
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} |
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inline static uint32_t midr_copy_variant(uint32_t midr, uint32_t other_midr) { |
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return (midr & ~CPUINFO_ARM_MIDR_VARIANT_MASK) | (other_midr & CPUINFO_ARM_MIDR_VARIANT_MASK); |
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} |
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inline static uint32_t midr_copy_architecture(uint32_t midr, uint32_t other_midr) { |
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return (midr & ~CPUINFO_ARM_MIDR_ARCHITECTURE_MASK) | (other_midr & CPUINFO_ARM_MIDR_ARCHITECTURE_MASK); |
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} |
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inline static uint32_t midr_copy_part(uint32_t midr, uint32_t other_midr) { |
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return (midr & ~CPUINFO_ARM_MIDR_PART_MASK) | (other_midr & CPUINFO_ARM_MIDR_PART_MASK); |
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} |
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inline static uint32_t midr_copy_revision(uint32_t midr, uint32_t other_midr) { |
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return (midr & ~CPUINFO_ARM_MIDR_REVISION_MASK) | (other_midr & CPUINFO_ARM_MIDR_REVISION_MASK); |
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} |
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inline static bool midr_is_arm1156(uint32_t midr) { |
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const uint32_t uarch_mask = CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK; |
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return (midr & uarch_mask) == (CPUINFO_ARM_MIDR_ARM1156 & uarch_mask); |
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} |
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inline static bool midr_is_arm11(uint32_t midr) { |
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return (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | 0x0000F000)) == UINT32_C(0x4100B000); |
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} |
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inline static bool midr_is_cortex_a9(uint32_t midr) { |
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const uint32_t uarch_mask = CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK; |
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return (midr & uarch_mask) == (CPUINFO_ARM_MIDR_CORTEX_A9 & uarch_mask); |
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} |
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inline static bool midr_is_scorpion(uint32_t midr) { |
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switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { |
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case UINT32_C(0x510000F0): |
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case UINT32_C(0x510002D0): |
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return true; |
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default: |
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return false; |
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} |
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} |
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inline static bool midr_is_krait(uint32_t midr) { |
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switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { |
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case UINT32_C(0x510004D0): |
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case UINT32_C(0x510006F0): |
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return true; |
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default: |
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return false; |
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} |
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} |
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inline static bool midr_is_cortex_a53(uint32_t midr) { |
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const uint32_t uarch_mask = CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK; |
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return (midr & uarch_mask) == (CPUINFO_ARM_MIDR_CORTEX_A53 & uarch_mask); |
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} |
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inline static bool midr_is_qualcomm_cortex_a53_silver(uint32_t midr) { |
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const uint32_t uarch_mask = CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK; |
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return (midr & uarch_mask) == (CPUINFO_ARM_MIDR_KRYO280_SILVER & uarch_mask); |
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} |
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inline static bool midr_is_qualcomm_cortex_a55_silver(uint32_t midr) { |
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const uint32_t uarch_mask = CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK; |
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return (midr & uarch_mask) == (CPUINFO_ARM_MIDR_KRYO385_SILVER & uarch_mask); |
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} |
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inline static bool midr_is_kryo280_gold(uint32_t midr) { |
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const uint32_t uarch_mask = CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK; |
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return (midr & uarch_mask) == (CPUINFO_ARM_MIDR_KRYO280_GOLD & uarch_mask); |
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} |
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inline static bool midr_is_kryo_silver(uint32_t midr) { |
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const uint32_t uarch_mask = |
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CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_ARCHITECTURE_MASK | CPUINFO_ARM_MIDR_PART_MASK; |
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switch (midr & uarch_mask) { |
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case CPUINFO_ARM_MIDR_KRYO_SILVER_820: |
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case CPUINFO_ARM_MIDR_KRYO_SILVER_821: |
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return true; |
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default: |
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return false; |
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} |
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} |
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inline static bool midr_is_kryo_gold(uint32_t midr) { |
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const uint32_t uarch_mask = CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK; |
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return (midr & uarch_mask) == (CPUINFO_ARM_MIDR_KRYO_GOLD & uarch_mask); |
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} |
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inline static uint32_t midr_score_core(uint32_t midr) { |
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const uint32_t core_mask = CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK; |
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switch (midr & core_mask) { |
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case UINT32_C(0x53000030): |
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case UINT32_C(0x53000040): |
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case UINT32_C(0x4100D440): |
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case UINT32_C(0x4100D480): |
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case UINT32_C(0x4100D4E0): |
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return 6; |
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case UINT32_C(0x4100D080): |
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case UINT32_C(0x4100D090): |
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case UINT32_C(0x4100D0A0): |
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case UINT32_C(0x4100D0B0): |
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case UINT32_C(0x4100D0D0): |
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case UINT32_C(0x4100D0E0): |
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case UINT32_C(0x4100D410): |
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case UINT32_C(0x4100D470): |
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case UINT32_C(0x4100D4D0): |
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case UINT32_C(0x4800D400): |
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case UINT32_C(0x4E000030): |
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case UINT32_C(0x51002050): |
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case UINT32_C(0x51008000): |
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case UINT32_C(0x51008020): |
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case UINT32_C(0x51008040): |
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case UINT32_C(0x53000010): |
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case UINT32_C(0x53000020): |
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#if CPUINFO_ARCH_ARM |
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case UINT32_C(0x4100C0F0): |
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case UINT32_C(0x4100C0E0): |
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case UINT32_C(0x4100C0D0): |
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case UINT32_C(0x4100C0C0): |
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#endif |
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return 5; |
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case UINT32_C(0x4100D070): |
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return 4; |
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#if CPUINFO_ARCH_ARM64 |
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case UINT32_C(0x4100D060): |
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#endif |
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case UINT32_C(0x4100D030): |
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case UINT32_C(0x4100D050): |
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case UINT32_C(0x4100D460): |
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return 2; |
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case UINT32_C(0x4100D040): |
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#if CPUINFO_ARCH_ARM |
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case UINT32_C(0x4100C070): |
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#endif |
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case UINT32_C(0x51008050): |
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case UINT32_C(0x51008030): |
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case UINT32_C(0x51008010): |
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case UINT32_C(0x51002110): |
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case UINT32_C(0x51002010): |
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return 1; |
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default: |
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return 3; |
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} |
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} |
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inline static uint32_t midr_little_core_for_big(uint32_t midr) { |
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const uint32_t core_mask = |
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CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_ARCHITECTURE_MASK | CPUINFO_ARM_MIDR_PART_MASK; |
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switch (midr & core_mask) { |
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case CPUINFO_ARM_MIDR_CORTEX_A75: |
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return CPUINFO_ARM_MIDR_CORTEX_A55; |
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case CPUINFO_ARM_MIDR_CORTEX_A73: |
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case CPUINFO_ARM_MIDR_CORTEX_A72: |
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case CPUINFO_ARM_MIDR_CORTEX_A57: |
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case CPUINFO_ARM_MIDR_EXYNOS_M1_M2: |
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return CPUINFO_ARM_MIDR_CORTEX_A53; |
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case CPUINFO_ARM_MIDR_CORTEX_A17: |
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case CPUINFO_ARM_MIDR_CORTEX_A15: |
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return CPUINFO_ARM_MIDR_CORTEX_A7; |
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case CPUINFO_ARM_MIDR_KRYO280_GOLD: |
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return CPUINFO_ARM_MIDR_KRYO280_SILVER; |
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case CPUINFO_ARM_MIDR_KRYO_GOLD: |
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return CPUINFO_ARM_MIDR_KRYO_SILVER_820; |
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case CPUINFO_ARM_MIDR_DENVER2: |
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return CPUINFO_ARM_MIDR_CORTEX_A57; |
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default: |
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return midr; |
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} |
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} |
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