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// Auto-generated file. Do not edit! |
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// Template: src/f32-gemm/1x8-aarch64-neonfma-cortex-a75.S.in |
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// Generator: tools/xngen |
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// |
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// Copyright 2019 Google LLC |
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// |
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// This source code is licensed under the BSD-style license found in the |
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// LICENSE file in the root directory of this source tree. |
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BEGIN_FUNCTION xnn_f32_gemm_minmax_ukernel_1x8__asm_aarch64_neonfma_cortex_a75 |
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LDP x14, x8, [sp] |
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LD2R {v4.4s, v5.4s}, [x8] |
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0: |
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LDP q16, q17, [x5], 32 |
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MOVI v18.4s, 0 // second set of C for pipelining FMLA |
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MOVI v19.4s, 0 |
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SUBS x0, x2, 32 // k = kc - 32 |
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B.LO 3f |
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LDP q20, q21, [x5], 32 |
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LDP q22, q23, [x5], 32 |
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LDP q24, q25, [x5], 32 |
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LDP q26, q27, [x5], 32 |
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LDR q0, [x3], 16 |
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SUBS x0, x0, 32 |
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B.LO 2f |
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1: |
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FMLA v16.4s, v20.4s, v0.s[0] |
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LDR q1, [x3], 16 |
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FMLA v17.4s, v21.4s, v0.s[0] |
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LDP q20, q21, [x5], 32 |
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FMLA v18.4s, v22.4s, v0.s[1] |
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FMLA v19.4s, v23.4s, v0.s[1] |
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LDP q22, q23, [x5], 32 |
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FMLA v16.4s, v24.4s, v0.s[2] |
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FMLA v17.4s, v25.4s, v0.s[2] |
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LDP q24, q25, [x5], 32 |
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FMLA v18.4s, v26.4s, v0.s[3] |
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FMLA v19.4s, v27.4s, v0.s[3] |
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LDP q26, q27, [x5], 32 |
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FMLA v16.4s, v20.4s, v1.s[0] |
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LDR q0, [x3], 16 |
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FMLA v17.4s, v21.4s, v1.s[0] |
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LDP q20, q21, [x5], 32 |
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FMLA v18.4s, v22.4s, v1.s[1] |
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FMLA v19.4s, v23.4s, v1.s[1] |
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LDP q22, q23, [x5], 32 |
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FMLA v16.4s, v24.4s, v1.s[2] |
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FMLA v17.4s, v25.4s, v1.s[2] |
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LDP q24, q25, [x5], 32 |
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FMLA v18.4s, v26.4s, v1.s[3] |
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FMLA v19.4s, v27.4s, v1.s[3] |
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SUBS x0, x0, 32 |
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LDP q26, q27, [x5], 32 |
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B.HS 1b |
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2: |
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FMLA v16.4s, v20.4s, v0.s[0] |
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LDR q1, [x3], 16 |
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FMLA v17.4s, v21.4s, v0.s[0] |
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LDP q20, q21, [x5], 32 |
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FMLA v18.4s, v22.4s, v0.s[1] |
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FMLA v19.4s, v23.4s, v0.s[1] |
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LDP q22, q23, [x5], 32 |
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FMLA v16.4s, v24.4s, v0.s[2] |
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FMLA v17.4s, v25.4s, v0.s[2] |
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LDP q24, q25, [x5], 32 |
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FMLA v18.4s, v26.4s, v0.s[3] |
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FMLA v19.4s, v27.4s, v0.s[3] |
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LDP q26, q27, [x5], 32 |
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FMLA v16.4s, v20.4s, v1.s[0] |
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FMLA v17.4s, v21.4s, v1.s[0] |
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FMLA v18.4s, v22.4s, v1.s[1] |
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FMLA v19.4s, v23.4s, v1.s[1] |
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FMLA v16.4s, v24.4s, v1.s[2] |
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FMLA v17.4s, v25.4s, v1.s[2] |
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FMLA v18.4s, v26.4s, v1.s[3] |
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FMLA v19.4s, v27.4s, v1.s[3] |
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3: |
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TBNZ x0, 4, 5f |
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TBNZ x0, 3, 6f |
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TBNZ x0, 2, 8f |
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4: |
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FADD v16.4s, v16.4s, v18.4s |
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SUBS x1, x1, 8 |
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FADD v17.4s, v17.4s, v19.4s |
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FMAX v16.4s, v16.4s, v4.4s |
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FMAX v17.4s, v17.4s, v4.4s |
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FMIN v16.4s, v16.4s, v5.4s |
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FMIN v17.4s, v17.4s, v5.4s |
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B.LO 9f |
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STP q16, q17, [x6] |
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ADD x6, x6, x14 |
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SUB x3, x3, x2 // a0 -= kc |
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B.HI 0b |
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RET |
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5: |
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LDP q20, q21, [x5], 32 |
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LDR q0, [x3], 16 |
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FMLA v16.4s, v20.4s, v0.s[0] |
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FMLA v17.4s, v21.4s, v0.s[0] |
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LDP q22, q23, [x5], 32 |
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LDP q24, q25, [x5], 32 |
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LDP q26, q27, [x5], 32 |
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FMLA v18.4s, v22.4s, v0.s[1] |
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FMLA v19.4s, v23.4s, v0.s[1] |
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FMLA v16.4s, v24.4s, v0.s[2] |
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FMLA v17.4s, v25.4s, v0.s[2] |
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FMLA v18.4s, v26.4s, v0.s[3] |
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FMLA v19.4s, v27.4s, v0.s[3] |
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TBZ x0, 3, 7f |
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6: |
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LDP q20, q21, [x5], 32 |
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LDR d0, [x3], 8 |
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FMLA v16.4s, v20.4s, v0.s[0] |
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FMLA v17.4s, v21.4s, v0.s[0] |
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LDP q22, q23, [x5], 32 |
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FMLA v18.4s, v22.4s, v0.s[1] |
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FMLA v19.4s, v23.4s, v0.s[1] |
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7: |
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TBZ x0, 2, 4b |
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8: |
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LDP q20, q21, [x5], 32 |
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LDR s0, [x3], 4 |
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FMLA v16.4s, v20.4s, v0.s[0] |
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FMLA v17.4s, v21.4s, v0.s[0] |
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B 4b |
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9: |
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TBZ x1, 2, 10f |
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STR q16, [x6], 16 |
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MOV v16.16b, v17.16b |
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10: |
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TBZ x1, 1, 11f |
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STR d16, [x6], 8 |
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DUP d16, v16.d[1] |
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11: |
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TBZ x1, 0, 12f |
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STR s16, [x6] |
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12: |
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RET |
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END_FUNCTION xnn_f32_gemm_minmax_ukernel_1x8__asm_aarch64_neonfma_cortex_a75 |
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.section ".note.GNU-stack","",%progbits |
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