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// Copyright 2023 Google LLC |
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// |
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// This source code is licensed under the BSD-style license found in the |
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// LICENSE file in the root directory of this source tree. |
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$assert DATATYPE in ["F32", "QC8", "QC4"] |
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$DATATYPE_SPEC = {"F32": "f32", "QC8": "f32_qc8w", "QC4": "f32_qc4w"}[DATATYPE] |
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$if INC: |
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$elif DATATYPE == "QC4": |
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$else: |
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$if DATATYPE == "QC4": |
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BEGIN_FUNCTION xnn_${DATATYPE_SPEC}_gemm${"inc" if INC else ""}_minmax_ukernel_4x2__asm_aarch64_neonfma_ld128 |
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$if INC: |
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LDP x14, x15, [sp] |
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LDR x8, [sp, 16] |
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$else: |
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LDP x14, x8, [sp] |
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CMP x0, 2 // if mr < 2 |
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ADD x11, x3, x4 // a1 = a0 + a_stride |
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ADD x9, x6, x7 // c1 = c0 + cm_stride |
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CSEL x11, x3, x11, LO // a1 = a0 |
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CSEL x9, x6, x9, LO // c1 = c0 |
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$if DATATYPE == "QC4": |
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LD3R {v4.2s, v5.2s, v6.2s}, [x8] |
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MOVI v7.8b, 15 |
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$else: |
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LD2R {v4.2s, v5.2s}, [x8] |
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ADD x12, x11, x4 // a2 = a1 + a_stride |
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ADD x10, x9, x7 // c2 = c1 + cm_stride |
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// if mr <= 2 |
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CSEL x12, x11, x12, LS // a2 = a1 |
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CSEL x10, x9, x10, LS // c2 = c1 |
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CMP x0, 4 // if mr < 4 |
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ADD x4, x12, x4 // a3 = a2 + a_stride |
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ADD x7, x10, x7 // c3 = c2 + cm_stride |
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CSEL x4, x12, x4, LO // a3 = a2 |
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CSEL x7, x10, x7, LO // c3 = c2 |
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0: |
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$if INC: |
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MOVI v24.4s, 0 |
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MOVI v25.4s, 0 |
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MOV v26.4s, 0 |
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MOV v27.4s, 0 |
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MOV v29.4s, 0 |
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MOV v28.4s, 0 |
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MOV v31.4s, 0 |
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MOV v30.4s, 0 |
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LD2 {v24.s, v25.s}[0], [x15], 8 |
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LD2 {v26.s, v27.s}[0], [x15], 8 |
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LD2 {v28.s, v29.s}[0], [x15], 8 |
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LD2 {v30.s, v31.s}[0], [x15], 8 |
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$else: |
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MOVI v24.4s, 0 |
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MOVI v25.4s, 0 |
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LD2 {v24.s, v25.s}[0], [x5], 8 |
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MOV v26.16b, v24.16b |
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MOV v27.16b, v25.16b |
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MOV v28.16b, v24.16b |
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MOV v29.16b, v25.16b |
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MOV v30.16b, v24.16b |
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MOV v31.16b, v25.16b |
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SUBS x0, x2, 16 // k = kc - 16 |
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B.LO 3f |
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1: |
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$if DATATYPE == "F32": |
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LDR q0, [x3], 16 |
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LD2 {v20.4s, v21.4s}, [x5], 32 |
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LDR q1, [x11], 16 |
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LDR q2, [x12], 16 |
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LDR q3, [x4], 16 |
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$else: |
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LD2 {v20.8b, v21.8b}, [x5] // overreads by 8 |
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ADD x5, x5, 8 |
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LDR q0, [x3], 16 |
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SXTL v20.8h, v20.8b |
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SXTL v21.8h, v21.8b |
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LDR q1, [x11], 16 |
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SXTL v20.4s, v20.4h |
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SXTL v21.4s, v21.4h |
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LDR q2, [x12], 16 |
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SCVTF v20.4s, v20.4s |
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SCVTF v21.4s, v21.4s |
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LDR q3, [x4], 16 |
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SUBS x0, x0, 16 |
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FMLA v24.4s, v20.4s, v0.4s |
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FMLA v25.4s, v21.4s, v0.4s |
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FMLA v26.4s, v20.4s, v1.4s |
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FMLA v27.4s, v21.4s, v1.4s |
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FMLA v28.4s, v20.4s, v2.4s |
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FMLA v29.4s, v21.4s, v2.4s |
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FMLA v30.4s, v20.4s, v3.4s |
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FMLA v31.4s, v21.4s, v3.4s |
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B.HS 1b |
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FADDP v24.4s, v24.4s, v25.4s |
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FADDP v26.4s, v26.4s, v27.4s |
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FADDP v28.4s, v28.4s, v29.4s |
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FADDP v30.4s, v30.4s, v31.4s |
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ANDS x0, x0, 15 |
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FADDP v24.4s, v24.4s, v24.4s |
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FADDP v26.4s, v26.4s, v26.4s |
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FADDP v28.4s, v28.4s, v28.4s |
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FADDP v30.4s, v30.4s, v30.4s |
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B.NE 4f |
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2: |
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$if DATATYPE in ["QC8", "QC4"]: |
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LDR d20, [x5], 8 |
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FMUL v24.2s, v24.2s, v20.2s |
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FMUL v26.2s, v26.2s, v20.2s |
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FMUL v28.2s, v28.2s, v20.2s |
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FMUL v30.2s, v30.2s, v20.2s |
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FMAX v24.2s, v24.2s, v4.2s |
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SUBS x1, x1, 2 |
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FMAX v26.2s, v26.2s, v4.2s |
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FMAX v28.2s, v28.2s, v4.2s |
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FMAX v30.2s, v30.2s, v4.2s |
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FMIN v24.2s, v24.2s, v5.2s |
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FMIN v26.2s, v26.2s, v5.2s |
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FMIN v28.2s, v28.2s, v5.2s |
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FMIN v30.2s, v30.2s, v5.2s |
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B.LO 5f |
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$if INC: |
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ST1 {v30.8b}, [x7], x14 |
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SUB x3, x3, x2 // a0 -= kc |
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ST1 {v28.8b}, [x10], x14 |
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SUB x11, x11, x2 // a1 -= kc |
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ST1 {v26.8b}, [x9], x14 |
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SUB x12, x12, x2 // a2 -= kc |
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ST1 {v24.8b}, [x6], x14 |
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SUB x4, x4, x2 // a3 -= kc |
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$else: |
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ST1 {v24.8b}, [x6], x14 |
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SUB x3, x3, x2 // a0 -= kc |
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ST1 {v26.8b}, [x9], x14 |
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SUB x11, x11, x2 // a1 -= kc |
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ST1 {v28.8b}, [x10], x14 |
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SUB x12, x12, x2 // a2 -= kc |
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ST1 {v30.8b}, [x7], x14 |
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SUB x4, x4, x2 // a3 -= kc |
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B.HI 0b |
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RET |
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3: |
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ADD x0, x0, 16 |
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FADDP v24.4s, v24.4s, v25.4s |
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FADDP v26.4s, v26.4s, v27.4s |
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FADDP v28.4s, v28.4s, v29.4s |
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FADDP v30.4s, v30.4s, v31.4s |
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FADDP v24.4s, v24.4s, v24.4s |
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FADDP v26.4s, v26.4s, v26.4s |
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FADDP v28.4s, v28.4s, v28.4s |
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FADDP v30.4s, v30.4s, v30.4s |
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4: |
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$if DATATYPE == "F32": |
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LDR s0, [x3], 4 |
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LDR d20, [x5], 8 |
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LDR s1, [x11], 4 |
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LDR s2, [x12], 4 |
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LDR s3, [x4], 4 |
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$else: |
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LDR h20, [x5], 2 |
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LDR s0, [x3], 4 |
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SXTL v20.8h, v20.8b |
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LDR s1, [x11], 4 |
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SXTL v20.4s, v20.4h |
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LDR s2, [x12], 4 |
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SCVTF v20.2s, v20.2s |
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LDR s3, [x4], 4 |
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SUBS x0, x0, 4 |
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FMLA v24.2s, v20.2s, v0.s[0] |
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FMLA v26.2s, v20.2s, v1.s[0] |
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FMLA v28.2s, v20.2s, v2.s[0] |
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FMLA v30.2s, v20.2s, v3.s[0] |
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B.HI 4b |
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B 2b |
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5: |
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$if INC: |
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STR s30, [x7] |
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STR s28, [x10] |
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STR s26, [x9] |
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STR s24, [x6] |
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$else: |
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STR s24, [x6] |
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STR s26, [x9] |
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STR s28, [x10] |
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STR s30, [x7] |
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RET |
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END_FUNCTION xnn_${DATATYPE_SPEC}_gemm${"inc" if INC else ""}_minmax_ukernel_4x2__asm_aarch64_neonfma_ld128 |
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.section ".note.GNU-stack","",%progbits |
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