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$assert CHANNEL_TILE % 8 == 0 |
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$assert CHANNEL_TILE >= 8 |
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$assert ROW_TILE >= 3 |
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$ABC = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
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#include <assert.h> |
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#include <arm_neon.h> |
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#include <xnnpack/gavgpool.h> |
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void xnn_f16_gavgpool_minmax_ukernel_${ROW_TILE}x__neonfp16arith_c${CHANNEL_TILE}( |
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size_t rows, |
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size_t channels, |
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const void* input, |
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size_t input_stride, |
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const void* zero, |
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void* output, |
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const union xnn_f16_scaleminmax_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS |
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{ |
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assert(rows != 0); |
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assert(rows <= ${ROW_TILE}); |
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assert(channels != 0); |
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const uint16_t* i0 = input; |
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$for M in range(1, ROW_TILE): |
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const uint16_t* i${M} = (const uint16_t*) ((uintptr_t) i${M-1} + input_stride); |
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$if M % 2 == 1: |
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if XNN_UNPREDICTABLE(rows < ${M+1}) { |
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i${M} = (const uint16_t*) zero; |
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} |
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$else: |
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if XNN_UNPREDICTABLE(rows <= ${M}) { |
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i${M} = (const uint16_t*) zero; |
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} |
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const float16x8_t vscale = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith.scale)); |
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const float16x8_t vmin = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith.min)); |
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const float16x8_t vmax = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith.max)); |
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for (; channels >= ${CHANNEL_TILE}; channels -= ${CHANNEL_TILE}) { |
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$for M in range(2): |
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$for C in range(0, CHANNEL_TILE, 8): |
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const float16x8_t vi${M}x${ABC[C:C+8]} = vreinterpretq_f16_u16(vld1q_u16(i${M})); i${M} += 8; |
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$for C in range(0, CHANNEL_TILE, 8): |
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const float16x8_t vi2x${ABC[C:C+8]} = vreinterpretq_f16_u16(vld1q_u16(i2)); i2 += 8; |
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float16x8_t vacc${ABC[C:C+8]} = vaddq_f16(vi0x${ABC[C:C+8]}, vi1x${ABC[C:C+8]}); |
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$for M in range(2, ROW_TILE): |
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$for C in range(0, CHANNEL_TILE, 8): |
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$if M + 1 != ROW_TILE: |
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const float16x8_t vi${M+1}x${ABC[C:C+8]} = vreinterpretq_f16_u16(vld1q_u16(i${M+1})); i${M+1} += 8; |
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vacc${ABC[C:C+8]} = vaddq_f16(vacc${ABC[C:C+8]}, vi${M}x${ABC[C:C+8]}); |
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$for C in range(0, CHANNEL_TILE, 8): |
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vacc${ABC[C:C+8]} = vmulq_f16(vacc${ABC[C:C+8]}, vscale); |
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$for C in range(0, CHANNEL_TILE, 8): |
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vacc${ABC[C:C+8]} = vmaxq_f16(vacc${ABC[C:C+8]}, vmin); |
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$for C in range(0, CHANNEL_TILE, 8): |
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vacc${ABC[C:C+8]} = vminq_f16(vacc${ABC[C:C+8]}, vmax); |
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$for C in range(0, CHANNEL_TILE, 8): |
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vst1q_u16(output, vreinterpretq_u16_f16(vacc${ABC[C:C+8]})); output = (uint16_t*) output + 8; |
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} |
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if XNN_UNLIKELY(channels != 0) { |
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${"do " if CHANNEL_TILE > 8 else ""}{ |
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$for M in range(2): |
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const float16x8_t vi${M}x${ABC[0:8]} = vreinterpretq_f16_u16(vld1q_u16(i${M})); i${M} += 8; |
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const float16x8_t vi2x${ABC[0:8]} = vreinterpretq_f16_u16(vld1q_u16(i2)); i2 += 8; |
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float16x8_t vacc${ABC[0:8]} = vaddq_f16(vi0x${ABC[0:8]}, vi1x${ABC[0:8]}); |
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$for M in range(2, ROW_TILE): |
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$if M + 1 != ROW_TILE: |
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const float16x8_t vi${M+1}x${ABC[0:8]} = vreinterpretq_f16_u16(vld1q_u16(i${M+1})); i${M+1} += 8; |
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vacc${ABC[0:8]} = vaddq_f16(vacc${ABC[0:8]}, vi${M}x${ABC[0:8]}); |
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vacc${ABC[0:8]} = vmulq_f16(vacc${ABC[0:8]}, vscale); |
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vacc${ABC[0:8]} = vmaxq_f16(vacc${ABC[0:8]}, vmin); |
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vacc${ABC[0:8]} = vminq_f16(vacc${ABC[0:8]}, vmax); |
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$if CHANNEL_TILE > 8: |
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if XNN_LIKELY(channels >= 8) { |
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vst1q_u16(output, vreinterpretq_u16_f16(vacc${ABC[0:8]})); output = (uint16_t*) output + 8; |
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channels -= 8; |
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} else { |
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float16x4_t vacc${ABC[0:4]} = vget_low_f16(vacc${ABC[0:8]}); |
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if (channels & 4) { |
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vst1_u16(output, vreinterpret_u16_f16(vacc${ABC[0:4]})); output = (uint16_t*) output + 4; |
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vacc${ABC[0:4]} = vget_high_f16(vacc${ABC[0:8]}); |
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} |
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if (channels & 2) { |
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vst1_lane_u32(output, vreinterpret_u32_f16(vacc${ABC[0:4]}), 0); output = (uint16_t*) output + 2; |
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vacc${ABC[0:4]} = vext_f16(vacc${ABC[0:4]}, vacc${ABC[0:4]}, 2); |
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} |
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if (channels & 1) { |
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vst1_lane_u16(output, vreinterpret_u16_f16(vacc${ABC[0:4]}), 0); output = (uint16_t*) output + 1; |
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} |
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channels = 0; |
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} |
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$else: |
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float16x4_t vacc${ABC[0:4]} = vget_low_f16(vacc${ABC[0:8]}); |
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if (channels & 4) { |
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vst1_u16(output, vreinterpret_u16_f16(vacc${ABC[0:4]})); output = (uint16_t*) output + 4; |
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vacc${ABC[0:4]} = vget_high_f16(vacc${ABC[0:8]}); |
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} |
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if (channels & 2) { |
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vst1_lane_u32(output, vreinterpret_u32_f16(vacc${ABC[0:4]}), 0); output = (uint16_t*) output + 2; |
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vacc${ABC[0:4]} = vext_f16(vacc${ABC[0:4]}, vacc${ABC[0:4]}, 2); |
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} |
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if (channels & 1) { |
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vst1_lane_u16(output, vreinterpret_u16_f16(vacc${ABC[0:4]}), 0); output = (uint16_t*) output + 1; |
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} |
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}${" while (channels != 0);" if CHANNEL_TILE > 8 else ""} |
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} |
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} |
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