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#include <assert.h> |
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#include <arm_neon.h> |
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#include <xnnpack/common.h> |
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#include <xnnpack/raddstoreexpminusmax.h> |
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void xnn_f16_raddstoreexpminusmax_ukernel__neonfp16arith_rr2_p2_x40_acc2( |
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size_t batch, |
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const void* input, |
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const void* max, |
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void* output, |
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void* sum, |
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const union xnn_f16_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS |
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{ |
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assert(batch != 0); |
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assert(batch % sizeof(uint16_t) == 0); |
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assert(input != NULL); |
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assert(max != NULL); |
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assert(output != NULL); |
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assert(sum != NULL); |
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const float16x8_t vi_max = vreinterpretq_f16_u16(vld1q_dup_u16(max)); |
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const float16x8_t vlog2e = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith_rr2_p2.log2e)); |
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const float16x8_t vmagic_bias = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith_rr2_p2.magic_bias)); |
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const float16x8_t vminus_ln2_hi = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith_rr2_p2.minus_ln2_hi)); |
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const float16x8_t vminus_ln2_lo = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith_rr2_p2.minus_ln2_lo)); |
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const float16x8_t vc2 = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith_rr2_p2.c2)); |
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const float16x8_t vc1 = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith_rr2_p2.c1)); |
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const float16x8_t vdenorm_cutoff = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith_rr2_p2.denorm_cutoff)); |
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const uint16_t* i = (const uint16_t*) input; |
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uint16_t* o = (uint16_t*) output; |
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float16x8_t vacc0 = vreinterpretq_f16_u16(vmovq_n_u16(0)); |
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float16x8_t vacc1 = vreinterpretq_f16_u16(vmovq_n_u16(0)); |
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for (; batch >= 40 * sizeof(uint16_t); batch -= 40 * sizeof(uint16_t)) { |
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const float16x8_t vi0 = vreinterpretq_f16_u16(vld1q_u16(i)); i += 8; |
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const float16x8_t vi1 = vreinterpretq_f16_u16(vld1q_u16(i)); i += 8; |
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const float16x8_t vi2 = vreinterpretq_f16_u16(vld1q_u16(i)); i += 8; |
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const float16x8_t vi3 = vreinterpretq_f16_u16(vld1q_u16(i)); i += 8; |
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const float16x8_t vi4 = vreinterpretq_f16_u16(vld1q_u16(i)); i += 8; |
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const float16x8_t vx0 = vsubq_f16(vi0, vi_max); |
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const float16x8_t vx1 = vsubq_f16(vi1, vi_max); |
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const float16x8_t vx2 = vsubq_f16(vi2, vi_max); |
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const float16x8_t vx3 = vsubq_f16(vi3, vi_max); |
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const float16x8_t vx4 = vsubq_f16(vi4, vi_max); |
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float16x8_t vn0 = vfmaq_f16(vmagic_bias, vx0, vlog2e); |
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float16x8_t vn1 = vfmaq_f16(vmagic_bias, vx1, vlog2e); |
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float16x8_t vn2 = vfmaq_f16(vmagic_bias, vx2, vlog2e); |
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float16x8_t vn3 = vfmaq_f16(vmagic_bias, vx3, vlog2e); |
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float16x8_t vn4 = vfmaq_f16(vmagic_bias, vx4, vlog2e); |
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const float16x8_t vs0 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn0), 10)); |
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const float16x8_t vs1 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn1), 10)); |
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const float16x8_t vs2 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn2), 10)); |
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const float16x8_t vs3 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn3), 10)); |
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const float16x8_t vs4 = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn4), 10)); |
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vn0 = vsubq_f16(vn0, vmagic_bias); |
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vn1 = vsubq_f16(vn1, vmagic_bias); |
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vn2 = vsubq_f16(vn2, vmagic_bias); |
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vn3 = vsubq_f16(vn3, vmagic_bias); |
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vn4 = vsubq_f16(vn4, vmagic_bias); |
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float16x8_t vt0 = vfmaq_f16(vx0, vn0, vminus_ln2_hi); |
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float16x8_t vt1 = vfmaq_f16(vx1, vn1, vminus_ln2_hi); |
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float16x8_t vt2 = vfmaq_f16(vx2, vn2, vminus_ln2_hi); |
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float16x8_t vt3 = vfmaq_f16(vx3, vn3, vminus_ln2_hi); |
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float16x8_t vt4 = vfmaq_f16(vx4, vn4, vminus_ln2_hi); |
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vt0 = vfmaq_f16(vt0, vn0, vminus_ln2_lo); |
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vt1 = vfmaq_f16(vt1, vn1, vminus_ln2_lo); |
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vt2 = vfmaq_f16(vt2, vn2, vminus_ln2_lo); |
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vt3 = vfmaq_f16(vt3, vn3, vminus_ln2_lo); |
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vt4 = vfmaq_f16(vt4, vn4, vminus_ln2_lo); |
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const float16x8_t vp0 = vfmaq_f16(vc1, vc2, vt0); |
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const float16x8_t vp1 = vfmaq_f16(vc1, vc2, vt1); |
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const float16x8_t vp2 = vfmaq_f16(vc1, vc2, vt2); |
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const float16x8_t vp3 = vfmaq_f16(vc1, vc2, vt3); |
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const float16x8_t vp4 = vfmaq_f16(vc1, vc2, vt4); |
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vt0 = vmulq_f16(vt0, vs0); |
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vt1 = vmulq_f16(vt1, vs1); |
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vt2 = vmulq_f16(vt2, vs2); |
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vt3 = vmulq_f16(vt3, vs3); |
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vt4 = vmulq_f16(vt4, vs4); |
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float16x8_t vf0 = vfmaq_f16(vs0, vp0, vt0); |
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const uint16x8_t vm0 = vcltq_f16(vx0, vdenorm_cutoff); |
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float16x8_t vf1 = vfmaq_f16(vs1, vp1, vt1); |
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const uint16x8_t vm1 = vcltq_f16(vx1, vdenorm_cutoff); |
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float16x8_t vf2 = vfmaq_f16(vs2, vp2, vt2); |
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const uint16x8_t vm2 = vcltq_f16(vx2, vdenorm_cutoff); |
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float16x8_t vf3 = vfmaq_f16(vs3, vp3, vt3); |
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const uint16x8_t vm3 = vcltq_f16(vx3, vdenorm_cutoff); |
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float16x8_t vf4 = vfmaq_f16(vs4, vp4, vt4); |
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const uint16x8_t vm4 = vcltq_f16(vx4, vdenorm_cutoff); |
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vf0 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf0), vm0)); |
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vf1 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf1), vm1)); |
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vf2 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf2), vm2)); |
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vf3 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf3), vm3)); |
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vf4 = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf4), vm4)); |
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vst1q_u16(o, vreinterpretq_u16_f16(vf0)); o += 8; |
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vst1q_u16(o, vreinterpretq_u16_f16(vf1)); o += 8; |
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vst1q_u16(o, vreinterpretq_u16_f16(vf2)); o += 8; |
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vst1q_u16(o, vreinterpretq_u16_f16(vf3)); o += 8; |
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vst1q_u16(o, vreinterpretq_u16_f16(vf4)); o += 8; |
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vacc0 = vaddq_f16(vacc0, vf0); |
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vacc1 = vaddq_f16(vacc1, vf1); |
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vacc0 = vaddq_f16(vacc0, vf2); |
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vacc1 = vaddq_f16(vacc1, vf3); |
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vacc0 = vaddq_f16(vacc0, vf4); |
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} |
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vacc0 = vaddq_f16(vacc0, vacc1); |
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float16x8_t vacc = vacc0; |
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for (; batch >= 8 * sizeof(uint16_t); batch -= 8 * sizeof(uint16_t)) { |
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const float16x8_t vi = vreinterpretq_f16_u16(vld1q_u16(i)); i += 8; |
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const float16x8_t vx = vsubq_f16(vi, vi_max); |
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float16x8_t vn = vfmaq_f16(vmagic_bias, vx, vlog2e); |
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const float16x8_t vs = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn), 10)); |
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vn = vsubq_f16(vn, vmagic_bias); |
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float16x8_t vt = vfmaq_f16(vx, vn, vminus_ln2_hi); |
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vt = vfmaq_f16(vt, vn, vminus_ln2_lo); |
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const float16x8_t vp = vfmaq_f16(vc1, vc2, vt); |
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vt = vmulq_f16(vt, vs); |
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float16x8_t vf = vfmaq_f16(vs, vp, vt); |
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const uint16x8_t vm = vcltq_f16(vx, vdenorm_cutoff); |
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vf = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf), vm)); |
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vst1q_u16(o, vreinterpretq_u16_f16(vf)); o += 8; |
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vacc = vaddq_f16(vacc, vf); |
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} |
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float16x4_t vacc_lo = vadd_f16(vget_low_f16(vacc), vget_high_f16(vacc)); |
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if (batch != 0) { |
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assert(batch >= 1 * sizeof(uint16_t)); |
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assert(batch <= 7 * sizeof(uint16_t)); |
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const float16x8_t vi = vreinterpretq_f16_u16(vld1q_u16(i)); |
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const float16x8_t vx = vsubq_f16(vi, vi_max); |
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float16x8_t vn = vfmaq_f16(vmagic_bias, vx, vlog2e); |
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const float16x8_t vs = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn), 10)); |
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vn = vsubq_f16(vn, vmagic_bias); |
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float16x8_t vt = vfmaq_f16(vx, vn, vminus_ln2_hi); |
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vt = vfmaq_f16(vt, vn, vminus_ln2_lo); |
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const float16x8_t vp = vfmaq_f16(vc1, vc2, vt); |
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vt = vmulq_f16(vt, vs); |
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float16x8_t vf = vfmaq_f16(vs, vp, vt); |
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const uint16x8_t vm = vcltq_f16(vx, vdenorm_cutoff); |
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vf = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf), vm)); |
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float16x4_t vf_lo = vget_low_f16(vf); |
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if (batch & (4 * sizeof(uint16_t))) { |
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vst1_u16(o, vreinterpret_u16_f16(vf_lo)); o += 4; |
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vacc_lo = vadd_f16(vacc_lo, vf_lo); |
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vf_lo = vget_high_f16(vf); |
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} |
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if (batch & (2 * sizeof(uint16_t))) { |
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vst1_lane_u32((void*) o, vreinterpret_u32_f16(vf_lo), 0); o += 2; |
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vacc_lo = vadd_f16(vacc_lo, vreinterpret_f16_u64(vshl_n_u64(vreinterpret_u64_f16(vf_lo), 32))); |
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vf_lo = vext_f16(vf_lo, vf_lo, 2); |
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} |
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if (batch & (1 * sizeof(uint16_t))) { |
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vst1_lane_u16(o, vreinterpret_u16_f16(vf_lo), 0); |
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vacc_lo = vadd_f16(vacc_lo, vreinterpret_f16_u64(vshl_n_u64(vreinterpret_u64_f16(vf_lo), 48))); |
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} |
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} |
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vacc_lo = vpadd_f16(vacc_lo, vacc_lo); |
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vacc_lo = vpadd_f16(vacc_lo, vacc_lo); |
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vst1_lane_u16(sum, vreinterpret_u16_f16(vacc_lo), 0); |
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} |
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