|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#include <assert.h> |
|
|
|
#include <arm_neon.h> |
|
|
|
#include <xnnpack/common.h> |
|
|
|
#include <xnnpack/gemm.h> |
|
#include <xnnpack/intrinsics-polyfill.h> |
|
|
|
|
|
void xnn_f16_gemm_minmax_ukernel_1x8__neonfp16arith_ld64( |
|
size_t mr, |
|
size_t nc, |
|
size_t kc, |
|
const void* restrict a, |
|
size_t a_stride, |
|
const void* restrict w, |
|
void* restrict c, |
|
size_t cm_stride, |
|
size_t cn_stride, |
|
const union xnn_f16_minmax_params params[restrict XNN_MIN_ELEMENTS(1)]) |
|
{ |
|
assert(mr != 0); |
|
assert(mr <= 1); |
|
assert(nc != 0); |
|
assert(kc != 0); |
|
assert(kc % sizeof(uint16_t) == 0); |
|
assert(a != NULL); |
|
assert(w != NULL); |
|
assert(c != NULL); |
|
|
|
const uint16_t* a0 = (const uint16_t*) a; |
|
uint16_t* c0 = (uint16_t*) c; |
|
|
|
do { |
|
float16x8_t vacc0x01234567 = vreinterpretq_f16_u16(vld1q_u16(w)); w = (const void*) ((uintptr_t) w + sizeof(float16x8_t)); |
|
|
|
size_t k = kc; |
|
while (k >= 4 * sizeof(uint16_t)) { |
|
const float16x4_t va0 = vreinterpret_f16_u16(vld1_u16(a0)); a0 += 4; |
|
|
|
const float16x8_t vb01234567c0 = vreinterpretq_f16_u16(vld1q_u16(w)); w = (const void*) ((uintptr_t) w + sizeof(float16x8_t)); |
|
|
|
#if XNN_ARCH_ARM64 |
|
vacc0x01234567 = vfmaq_lane_f16(vacc0x01234567, vb01234567c0, va0, 0); |
|
#else |
|
vacc0x01234567 = vmlaq_lane_f16(vacc0x01234567, vb01234567c0, va0, 0); |
|
#endif |
|
const float16x8_t vb01234567c1 = vreinterpretq_f16_u16(vld1q_u16(w)); w = (const void*) ((uintptr_t) w + sizeof(float16x8_t)); |
|
|
|
#if XNN_ARCH_ARM64 |
|
vacc0x01234567 = vfmaq_lane_f16(vacc0x01234567, vb01234567c1, va0, 1); |
|
#else |
|
vacc0x01234567 = vmlaq_lane_f16(vacc0x01234567, vb01234567c1, va0, 1); |
|
#endif |
|
const float16x8_t vb01234567c2 = vreinterpretq_f16_u16(vld1q_u16(w)); w = (const void*) ((uintptr_t) w + sizeof(float16x8_t)); |
|
|
|
#if XNN_ARCH_ARM64 |
|
vacc0x01234567 = vfmaq_lane_f16(vacc0x01234567, vb01234567c2, va0, 2); |
|
#else |
|
vacc0x01234567 = vmlaq_lane_f16(vacc0x01234567, vb01234567c2, va0, 2); |
|
#endif |
|
const float16x8_t vb01234567c3 = vreinterpretq_f16_u16(vld1q_u16(w)); w = (const void*) ((uintptr_t) w + sizeof(float16x8_t)); |
|
|
|
#if XNN_ARCH_ARM64 |
|
vacc0x01234567 = vfmaq_lane_f16(vacc0x01234567, vb01234567c3, va0, 3); |
|
#else |
|
vacc0x01234567 = vmlaq_lane_f16(vacc0x01234567, vb01234567c3, va0, 3); |
|
#endif |
|
|
|
k -= 4 * sizeof(uint16_t); |
|
} |
|
if XNN_UNLIKELY(k != 0) { |
|
do { |
|
const float16x8_t va0 = vreinterpretq_f16_u16(vld1q_dup_u16(a0)); a0 += 1; |
|
|
|
const float16x8_t vb01234567 = vreinterpretq_f16_u16(vld1q_u16(w)); w = (const void*) ((uintptr_t) w + sizeof(float16x8_t)); |
|
|
|
vacc0x01234567 = vfmaq_f16(vacc0x01234567, va0, vb01234567); |
|
|
|
k -= sizeof(uint16_t); |
|
} while (k != 0); |
|
} |
|
|
|
|
|
const float16x8_t vmin = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith.min)); |
|
vacc0x01234567 = vmaxq_f16(vacc0x01234567, vmin); |
|
|
|
const float16x8_t vmax = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->fp16arith.max)); |
|
vacc0x01234567 = vminq_f16(vacc0x01234567, vmax); |
|
|
|
if XNN_LIKELY(nc >= 8) { |
|
vst1q_u16(c0, vreinterpretq_u16_f16(vacc0x01234567)); |
|
c0 = (uint16_t*) ((uintptr_t) c0 + cn_stride); |
|
|
|
a0 = (const uint16_t*) ((uintptr_t) a0 - kc); |
|
|
|
nc -= 8; |
|
} else { |
|
float16x4_t vacc0x0123 = vget_low_f16(vacc0x01234567); |
|
if (nc & 4) { |
|
vst1_u16(c0, vreinterpret_u16_f16(vacc0x0123)); c0 += 4; |
|
|
|
vacc0x0123 = vget_high_f16(vacc0x01234567); |
|
} |
|
if (nc & 2) { |
|
vst1_lane_u32((void*) c0, vreinterpret_u32_f16(vacc0x0123), 0); c0 += 2; |
|
|
|
vacc0x0123 = vext_f16(vacc0x0123, vacc0x0123, 2); |
|
} |
|
if (nc & 1) { |
|
vst1_lane_u16(c0, vreinterpret_u16_f16(vacc0x0123), 0); |
|
} |
|
|
|
nc = 0; |
|
} |
|
} while (nc != 0); |
|
} |
|
|