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{"T": 3, "t": "arg_VCVT_f16_f32"} |
{"T": 3, "t": "arg_VCVT_f16_f64"} |
{"T": 3, "t": "arg_VRINTR_sp"} |
{"T": 3, "t": "arg_VRINTR_dp"} |
{"T": 3, "t": "arg_VRINTZ_sp"} |
{"T": 3, "t": "arg_VRINTZ_dp"} |
{"T": 3, "t": "arg_VRINTX_sp"} |
{"T": 3, "t": "arg_VRINTX_dp"} |
{"T": 3, "t": "arg_VCVT_sp"} |
{"T": 3, "t": "arg_VCVT_dp"} |
{"T": 3, "t": "arg_VCVT_int_sp"} |
{"T": 3, "t": "arg_VCVT_int_dp"} |
{"T": 3, "t": "arg_VJCVT"} |
{"T": 3, "t": "arg_VCVT_fix_sp"} |
{"T": 3, "t": "arg_VCVT_fix_dp"} |
{"T": 3, "t": "arg_VCVT_sp_int"} |
{"T": 3, "t": "arg_VCVT_dp_int"} |
{"T": 9, "n": "gen_helper_gvec_3_ptr *"} |
{"T": 9, "n": "void (__cdecl *)(TCGv_i32 retval, TCGv_ptr arg1, TCGv_i32 arg2, TCGv_i32 arg3, TCGv_i32 arg4)"} |
{"T": 9, "n": "void (__cdecl *)(TCGv_i32 retval, TCGv_i32 arg1, TCGv_i32 arg2, TCGv_ptr arg3)"} |
{"T": 9, "n": "void (__cdecl *)(TCGv_ptr arg1, TCGv_ptr arg2, TCGv_ptr arg3, TCGv_ptr arg4, TCGv_i32 arg5)"} |
{"T": 9, "n": "void (__cdecl *)(TCGv_ptr arg1, TCGv_ptr arg2, TCGv_ptr arg3, TCGv_ptr arg4, TCGv_i32 arg5)"} |
{"T": 3, "t": "arg_bfx"} |
{"T": 3, "t": "arg_mrs_bank"} |
{"T": 3, "t": "arg_msr_bank"} |
{"T": 3, "t": "arg_mrs_reg"} |
{"T": 3, "t": "arg_msr_reg"} |
{"T": 3, "t": "arg_bfi"} |
{"T": 3, "t": "arg_pkh"} |
{"T": 3, "t": "arg_msr_i"} |
{"T": 3, "t": "arg_r"} |
{"T": 3, "t": "arg_strex"} |
{"T": 3, "t": "arg_disas_a3226"} |
{"T": 8} |
{"T": 3, "t": "arg_rfe"} |
{"T": 3, "t": "arg_srs"} |
{"T": 3, "t": "arg_cps"} |
{"T": 3, "t": "arg_setend"} |
{"T": 8} |
{"T": 3, "t": "arg_bfi"} |
{"T": 3, "t": "arg_bfx"} |
{"T": 3, "t": "arg_cps"} |
{"T": 3, "t": "arg_mrs_bank"} |
{"T": 3, "t": "arg_mrs_reg"} |
{"T": 3, "t": "arg_disas_t3227"} |
{"T": 3, "t": "arg_msr_bank"} |
{"T": 3, "t": "arg_msr_reg"} |
{"T": 3, "t": "arg_disas_t3228"} |
{"T": 3, "t": "arg_pkh"} |
{"T": 3, "t": "arg_r"} |
{"T": 3, "t": "arg_ci"} |
{"T": 3, "t": "arg_disas_t3230"} |
{"T": 3, "t": "arg_ldst_ri2"} |
{"T": 3, "t": "arg_rfe"} |
{"T": 3, "t": "arg_srs"} |
{"T": 3, "t": "arg_strex"} |
{"T": 3, "t": "arg_strex"} |
{"T": 3, "t": "arg_strex"} |
{"T": 3, "t": "arg_tbranch"} |
{"T": 8} |
{"T": 3, "t": "arg_r"} |
{"T": 3, "t": "arg_setend"} |
{"T": 3, "t": "arg_cps"} |
{"T": 3, "t": "arg_disas_t1616"} |
{"T": 3, "t": "arg_empty"} |
{"T": 3, "t": "arg_disas_t1617"} |
{"T": 3, "t": "arg_disas_t1618"} |
{"T": 3, "t": "arg_ci"} |
{"T": 8} |
{"T": 3, "t": "arg_MOVW"} |
{"T": 3, "t": "arg_MOVW"} |
{"T": 3, "t": "arg_MUL"} |
{"T": 3, "t": "arg_MLA"} |
{"T": 3, "t": "arg_MLS"} |
{"T": 3, "t": "arg_UMULL"} |
{"T": 3, "t": "arg_SMULL"} |
{"T": 3, "t": "arg_UMLAL"} |
{"T": 3, "t": "arg_SMLAL"} |
{"T": 3, "t": "arg_UMAAL"} |
{"T": 3, "t": "arg_MSR_imm"} |
{"T": 3, "t": "arg_MRS_bank"} |
{"T": 3, "t": "arg_MSR_bank"} |
{"T": 3, "t": "arg_MRS_reg"} |
{"T": 3, "t": "arg_MSR_reg"} |
{"T": 3, "t": "arg_MRS_v7m"} |
{"T": 3, "t": "arg_MSR_v7m"} |
{"T": 3, "t": "arg_BX"} |
{"T": 3, "t": "arg_BXJ"} |
{"T": 3, "t": "arg_BLX_r"} |
{"T": 3, "t": "arg_BXNS"} |
{"T": 3, "t": "arg_BLXNS"} |
{"T": 3, "t": "arg_CLZ"} |
{"T": 3, "t": "arg_HLT"} |
{"T": 3, "t": "arg_BKPT"} |
{"T": 3, "t": "arg_HVC"} |
{"T": 3, "t": "arg_TT"} |
{"T": 3, "t": "arg_ldst_ri2"} |
{"T": 6, "n": "arg_ldst_ri", "l": [{"T": 4, "n": "imm", "t": "int", "s": 4}, {"T": 4, "n": "p", "t": "int", "s": 4}, {"T": 4, "n": "rn", "t": "int", "s": 4}, {"T": 4, "n": "rt", "t": "int", "s": 4}, {"T": 4, "n": "u", "t": "int", "s": 4}, {"T": 4, "n": "w", "t": "int", "s": 4}]} |
{"T": 3, "t": "arg_ldst_ri2"} |
{"T": 6, "n": "arg_ldst_ri", "l": [{"T": 4, "n": "imm", "t": "int", "s": 4}, {"T": 4, "n": "p", "t": "int", "s": 4}, {"T": 4, "n": "rn", "t": "int", "s": 4}, {"T": 4, "n": "rt", "t": "int", "s": 4}, {"T": 4, "n": "u", "t": "int", "s": 4}, {"T": 4, "n": "w", "t": "int", "s": 4}]} |