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{"T": 3, "t": "arg_disas_vfp6"} |
{"T": 3, "t": "arg_disas_vfp6"} |
{"T": 3, "t": "arg_disas_vfp7"} |
{"T": 3, "t": "arg_disas_vfp7"} |
{"T": 3, "t": "arg_disas_vfp7"} |
{"T": 3, "t": "arg_disas_vfp7"} |
{"T": 3, "t": "arg_disas_vfp8"} |
{"T": 3, "t": "arg_disas_vfp8"} |
{"T": 3, "t": "arg_disas_vfp9"} |
{"T": 3, "t": "arg_disas_vfp0"} |
{"T": 3, "t": "arg_disas_vfp9"} |
{"T": 3, "t": "arg_disas_vfp9"} |
{"T": 3, "t": "arg_disas_vfp9"} |
{"T": 3, "t": "arg_disas_vfp10"} |
{"T": 3, "t": "arg_disas_vfp10"} |
{"T": 3, "t": "arg_disas_vfp11"} |
{"T": 3, "t": "arg_disas_vfp11"} |
{"T": 3, "t": "arg_disas_vfp12"} |
{"T": 3, "t": "arg_disas_vfp12"} |
{"T": 3, "t": "arg_disas_vfp13"} |
{"T": 3, "t": "arg_disas_vfp1"} |
{"T": 3, "t": "arg_disas_vfp13"} |
{"T": 3, "t": "arg_disas_vfp13"} |
{"T": 3, "t": "arg_disas_vfp11"} |
{"T": 3, "t": "arg_disas_vfp11"} |
{"T": 3, "t": "arg_disas_vfp14"} |
{"T": 3, "t": "arg_disas_vfp14"} |
{"T": 3, "t": "arg_disas_vfp15"} |
{"T": 3, "t": "arg_disas_vfp15"} |
{"T": 3, "t": "arg_disas_vfp16"} |
{"T": 3, "t": "arg_disas_vfp16"} |
{"T": 3, "t": "arg_disas_vfp1"} |
{"T": 3, "t": "arg_disas_vfp1"} |
{"T": 3, "t": "arg_disas_vfp2"} |
{"T": 3, "t": "arg_disas_vfp3"} |
{"T": 3, "t": "arg_disas_vfp4"} |
{"T": 3, "t": "arg_disas_vfp5"} |
{"T": 8} |
{"T": 3, "t": "arg_disas_vfp_uncond0"} |
{"T": 3, "t": "arg_disas_vfp_uncond0"} |
{"T": 3, "t": "arg_disas_vfp_uncond1"} |
{"T": 3, "t": "arg_disas_vfp_uncond1"} |
{"T": 3, "t": "arg_disas_vfp_uncond2"} |
{"T": 3, "t": "arg_disas_vfp_uncond2"} |
{"T": 3, "t": "arg_disas_vfp_uncond3"} |
{"T": 3, "t": "arg_disas_vfp_uncond3"} |
{"T": 8} |
{"T": 3, "t": "arg_VSEL"} |
{"T": 3, "t": "arg_VMINMAXNM"} |
{"T": 3, "t": "arg_VRINT"} |
{"T": 3, "t": "arg_VCVT"} |
{"T": 3, "t": "arg_VMOV_to_gp"} |
{"T": 3, "t": "arg_VMOV_from_gp"} |
{"T": 3, "t": "arg_VDUP"} |
{"T": 3, "t": "arg_VMSR_VMRS"} |
{"T": 3, "t": "arg_VMOV_single"} |
{"T": 3, "t": "arg_VMOV_64_sp"} |
{"T": 3, "t": "arg_VMOV_64_dp"} |
{"T": 3, "t": "arg_VLDR_VSTR_sp"} |
{"T": 3, "t": "arg_VLDR_VSTR_dp"} |
{"T": 3, "t": "arg_VLDM_VSTM_sp"} |
{"T": 3, "t": "arg_VLDM_VSTM_dp"} |
{"T": 9, "n": "VFPGen3OpSPFn *"} |
{"T": 9, "n": "VFPGen3OpDPFn *"} |
{"T": 9, "n": "VFPGen2OpSPFn *"} |
{"T": 9, "n": "VFPGen2OpDPFn *"} |
{"T": 3, "t": "arg_VMLA_sp"} |
{"T": 3, "t": "arg_VMLA_dp"} |
{"T": 3, "t": "arg_VMLS_sp"} |
{"T": 3, "t": "arg_VMLS_dp"} |
{"T": 3, "t": "arg_VNMLS_sp"} |
{"T": 3, "t": "arg_VNMLS_dp"} |
{"T": 3, "t": "arg_VNMLA_sp"} |
{"T": 3, "t": "arg_VNMLA_dp"} |
{"T": 3, "t": "arg_VMUL_sp"} |
{"T": 3, "t": "arg_VMUL_dp"} |
{"T": 3, "t": "arg_VNMUL_sp"} |
{"T": 3, "t": "arg_VNMUL_dp"} |
{"T": 3, "t": "arg_VADD_sp"} |
{"T": 3, "t": "arg_VADD_dp"} |
{"T": 3, "t": "arg_VSUB_sp"} |
{"T": 3, "t": "arg_VSUB_dp"} |
{"T": 3, "t": "arg_VDIV_sp"} |
{"T": 3, "t": "arg_VDIV_dp"} |
{"T": 3, "t": "arg_VFM_sp"} |
{"T": 3, "t": "arg_VFM_dp"} |
{"T": 3, "t": "arg_VMOV_imm_sp"} |
{"T": 3, "t": "arg_VMOV_imm_dp"} |
{"T": 3, "t": "arg_VMOV_reg_sp"} |
{"T": 3, "t": "arg_VMOV_reg_dp"} |
{"T": 3, "t": "arg_VABS_sp"} |
{"T": 3, "t": "arg_VABS_dp"} |
{"T": 3, "t": "arg_VNEG_sp"} |
{"T": 3, "t": "arg_VNEG_dp"} |
{"T": 3, "t": "arg_VSQRT_sp"} |
{"T": 3, "t": "arg_VSQRT_dp"} |
{"T": 3, "t": "arg_VCMP_sp"} |
{"T": 3, "t": "arg_VCMP_dp"} |
{"T": 3, "t": "arg_VCVT_f32_f16"} |
{"T": 3, "t": "arg_VCVT_f64_f16"} |