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low-power O
three-dimensional O
-LRB- O
3-D O
-RRB- O
rendering O
engine O
is O
implemented O
as O
part O
of O
a O
mobile O
personal O
digital O
assistant O
-LRB- O
PDA O
-RRB- O
chip O
. O
Six-megabit O
embedded B-KEY
DRAM I-KEY
macros I-KEY
attached O
to O
8-pixel-parallel B-KEY
rendering I-KEY
logic I-KEY
are O
logically O
localized O
with O
a O
3.2-GB O
/ O
s O
runtime O
reconfigurable B-KEY
bus I-KEY
, O
reducing O
the O
area O
by O
25 O
% O
compared O
with O
conventional O
local O
frame-buffer O
architectures O
. O
The O
low B-KEY
power I-KEY
consumption I-KEY
is O
achieved O
by O
polygon-dependent B-KEY
access I-KEY
to O
the O
embedded B-KEY
DRAM I-KEY
macros I-KEY
with O
line-block B-KEY
mapping I-KEY
providing O
read-modify-write B-KEY
data I-KEY
transaction I-KEY
. O
The O
3-D O
rendering O
engine O
with O
2.22-Mpolygons O
/ O
s O
drawing O
speed O
was O
fabricated O
using O
0.18 O
- O
mu O
m O
CMOS B-KEY
embedded I-KEY
memory I-KEY
logic I-KEY
technology I-KEY