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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [4095:0] crc;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[4094:0], crc[63]^crc[2]^crc[0]}; // not a good crc :)
if (cyc==0) begin
// Setup
crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x%x%x%x\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
$write("[%0t] cyc==%0d crc=%b%b%b%b\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
//Unsupported: $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc
) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// DCFIFO_64x16_DR for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <kbpark@enc.hanyang.ac.kr>
// Yong Ho Song <yhsong@enc.hanyang.ac.kr>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <kbpark@enc.hanyang.ac.kr>
//
// Project Name: Cosmos OpenSSD
// Design Name: Dual clock distributed ram FIFO (64 width, 16 depth) wrapper
// Module Name: DCFIFO_64x16_DR
// File Name: DCFIFO_64x16_DR.v
//
// Version: v1.0.0
//
// Description: Standard FIFO, 1 cycle data out latency
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module DCFIFO_64x16_DR
(
input iWClock ,
input iWReset ,
input [63:0] iPushData ,
input iPushEnable ,
output oIsFull ,
input iRClock ,
input iRReset ,
output [63:0] oPopData ,
input iPopEnable ,
output oIsEmpty
);
DPBDCFIFO64x16DR
Inst_DPBDCFIFO64x16DR
(
.wr_clk (iWClock ),
.wr_rst (iWReset ),
.din (iPushData ),
.wr_en (iPushEnable ),
.full (oIsFull ),
.rd_clk (iRClock ),
.rd_rst (iRReset ),
.dout (oPopData ),
.rd_en (iPopEnable ),
.empty (oIsEmpty )
);
endmodule
|
// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_sample_cycle_ratio
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_clock_converter_v2_1_axic_sample_cycle_ratio # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SLOW_ACLK,
input wire FAST_ACLK,
output wire SAMPLE_CYCLE_EARLY,
output wire SAMPLE_CYCLE
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg slow_aclk_div2 = 0;
reg posedge_finder_first;
reg posedge_finder_second;
wire first_edge;
wire second_edge;
reg [P_DELAY-1:0] sample_cycle_d;
(* shreg_extract = "no" *) reg sample_cycle_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_RATIO == 1) begin : gen_always_sample
assign SAMPLE_CYCLE_EARLY = 1'b1;
assign SAMPLE_CYCLE = 1'b1;
end
else begin : gen_sample_cycle
genvar i;
always @(posedge SLOW_ACLK) begin
slow_aclk_div2 <= ~slow_aclk_div2;
end
// Find matching rising edges by clocking slow_aclk_div2 onto faster clock
always @(posedge FAST_ACLK) begin
posedge_finder_first <= slow_aclk_div2;
end
always @(posedge FAST_ACLK) begin
posedge_finder_second <= ~slow_aclk_div2;
end
assign first_edge = slow_aclk_div2 & ~posedge_finder_first;
assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;
always @(*) begin
sample_cycle_d[P_DELAY-1] = first_edge | second_edge;
end
// delay the posedge alignment by C_RATIO - 1 to set the sample cycle as
// the clock one cycle before the posedge.
for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay
always @(posedge FAST_ACLK) begin
sample_cycle_d[i-1] <= sample_cycle_d[i];
end
end
always @(posedge FAST_ACLK) begin
sample_cycle_r <= sample_cycle_d[0];
end
assign SAMPLE_CYCLE_EARLY = sample_cycle_d[0];
assign SAMPLE_CYCLE = sample_cycle_r;
end
endgenerate
endmodule // axisc_sample_cycle_ratio
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Application : MIG
// \ \ Filename : traffic_gen_top.v
// / / Date Last Modified : $Date: 2011/06/02 08:37:25 $
// /___/ /\ Date Created : Fri Mar 26 2010
// \ \ / \
// \___\/\___\
//
//Device : Virtex-7
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : This Traffic Gen supports both nCK_PER_CLK x4 mode and nCK_PER_CLK x2 mode for
// 7series MC UI Interface. The user bus datawidth has a equation: 2*nCK_PER_CLK*DQ_WIDTH.
//
//Reference :
//Revision History : 11/17/2011 Adding CMD_GAP_DELAY to allow control of next command generation after current
// completion of burst command in user interface port.
// 1/4/2012 Added vio_percent_write in memc_traffic_gen module to let user specify percentage
// of write commands out of mix write/read commands. User can
// modify this file and bring the signals to top level to use it.
// The value is between 1(10 percent) through 10 (100 percent).
// The signal value is only used if vio_instr_mode_value == 4.
// 5/21/2012 Removed BL_WIDTH parameter and forced internally to 10.
//
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_traffic_gen_top #(
parameter TCQ = 100, // SIMULATION tCQ delay.
parameter SIMULATION = "FALSE",
parameter FAMILY = "VIRTEX7", // "VIRTEX6", "VIRTEX7"
parameter MEM_TYPE = "DDR3",
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands:
// "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE"
// "R_W_INSTR_MODE", "RP_WP_INSTR_MODE
// "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE"
// *******************************
// Virtex 6 Available commands:
// "R_W_INSTR_MODE"
// "FIXED_INSTR_R_MODE" - Only Read commands will be generated.
// "FIXED_INSTR_W_MODE" -- Only Write commands will be generated.
// "FIXED_INSTR_R_EYE_MODE" Only Read commands will be generated
// with lower 10 bits address in sequential increment.
// This mode is for Read Eye measurement.
// parameter BL_WIDTH = 10, // Define User Interface Burst length width.
// // For a maximum 128 continuous back_to_back command, set this to 8.
parameter nCK_PER_CLK = 4, // Memory Clock ratio to fabric clock.
parameter NUM_DQ_PINS = 8, // Total number of memory dq pins in the design.
parameter MEM_BURST_LEN = 8, // MEMROY Burst Length
parameter MEM_COL_WIDTH = 10, // Memory component column width.
parameter DATA_WIDTH = NUM_DQ_PINS*2*nCK_PER_CLK, // User Interface Data Width
parameter ADDR_WIDTH = 29, // Command Address Bus width
parameter MASK_SIZE = DATA_WIDTH/8, //
parameter DATA_MODE = 4'b0010, // Default Data mode is set to Address as Data pattern.
// parameters define the address range
parameter BEGIN_ADDRESS = 32'h00000100,
parameter END_ADDRESS = 32'h000002ff,
parameter PRBS_EADDR_MASK_POS = 32'hfffffc00,
// debug parameters
parameter CMDS_GAP_DELAY = 6'd0, // CMDS_GAP_DELAY is used in memc_flow_vcontrol module to insert delay between
// each sucessive burst commands. The maximum delay is 32 clock cycles
// after the last command.
parameter SEL_VICTIM_LINE = NUM_DQ_PINS, // VICTIM LINE is one of the DQ pins is selected to be always asserted when
// DATA MODE is hammer pattern. No VICTIM_LINE will be selected if
// SEL_VICTIM_LINE = NUM_DQ_PINS.
parameter CMD_WDT = 'h3FF,
parameter WR_WDT = 'h1FFF,
parameter RD_WDT = 'hFF,
parameter EYE_TEST = "FALSE",
// S6 Only parameters
parameter PORT_MODE = "BI_MODE",
parameter DATA_PATTERN = "DGEN_ALL", // Default is to generate all data pattern circuits.
parameter CMD_PATTERN = "CGEN_ALL" // Default is to generate all commands pattern circuits.
)
(
input clk,
input rst,
input tg_only_rst,
input manual_clear_error,
input memc_init_done,
input memc_cmd_full,
output memc_cmd_en,
output [2:0] memc_cmd_instr,
output [5:0] memc_cmd_bl,
output [31:0] memc_cmd_addr,
output memc_wr_en,
output memc_wr_end,
output [DATA_WIDTH/8 - 1:0] memc_wr_mask,
output [DATA_WIDTH - 1:0] memc_wr_data,
input memc_wr_full,
output memc_rd_en,
input [DATA_WIDTH - 1:0] memc_rd_data,
input memc_rd_empty,
// interface to qdr interface
output qdr_wr_cmd_o,
output qdr_rd_cmd_o,
// Signal declarations that can be connected to vio module
input vio_pause_traffic, // Pause traffic on the fly.
input vio_modify_enable,
input [3:0] vio_data_mode_value,
input [2:0] vio_addr_mode_value,
input [3:0] vio_instr_mode_value,
input [1:0] vio_bl_mode_value,
input [9:0] vio_fixed_bl_value,
input [2:0] vio_fixed_instr_value, // Allows upper level control write only or read only
// on the fly.
// Set the vio_instr_mode_value to "0001" .
// User has control of the type of commands to be generated
// after memory has been filled with selected data pattern.
// vio_fixed_instr_value = 3'b000: Write command
// vio_fixed_instr_value = 3'b001: Read command
input vio_data_mask_gen, // data_mask generation is only supported
// when data mode = address as data .
//
input [31:0] fixed_addr_i,
// User Specific data pattern interface that used when vio_data_mode vale = 1.4.9.
input [31:0] fixed_data_i,
input [31:0] simple_data0,
input [31:0] simple_data1,
input [31:0] simple_data2,
input [31:0] simple_data3,
input [31:0] simple_data4,
input [31:0] simple_data5,
input [31:0] simple_data6,
input [31:0] simple_data7,
input wdt_en_i,
// BRAM interface.
// bram bus formats:
// Only SP6 has been tested.
input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}}
input bram_valid_i,
output bram_rdy_o, //
// status feedback
output [DATA_WIDTH-1:0] cmp_data,
output cmp_data_valid,
output cmp_error,
output [47:0] wr_data_counts,
output [47:0] rd_data_counts,
output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp,
output error, // asserted whenever the read back data is not correct.
output [64 + (2*DATA_WIDTH - 1):0] error_status,
output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error,
output reg cmd_wdt_err_o,
output reg wr_wdt_err_o,
output reg rd_wdt_err_o,
output mem_pattern_init_done
);
//p0 wire declarations
wire tg_run_traffic;
wire tg_data_mask_gen;
wire run_traffic;
wire [31:0] tg_start_addr;
wire [31:0] tg_end_addr;
wire [31:0] tg_cmd_seed;
wire [31:0] tg_data_seed;
wire tg_load_seed;
wire [2:0] tg_addr_mode;
wire [3:0] tg_instr_mode;
wire [1:0] tg_bl_mode;
wire [3:0] tg_data_mode;
wire tg_mode_load;
wire [9:0] tg_fixed_bl;
wire [2:0] tg_fixed_instr;
wire tg_addr_order;
wire [5:0] cmds_gap_delay_value;
wire tg_memc_wr_en;
wire [63:0] mem_tg_tstpoints;
wire [9:0] lcl_v_fixed_bl_value;
wire single_operation;
wire [3:0] tg_instr_mode_value;
wire [3:0] instr_mode_value;
reg tg_rst;
localparam ADDR_WIDTH_MASK = {{31-ADDR_WIDTH{1'b0}}, {ADDR_WIDTH-1{1'b1}}};
localparam ADDR_WIDTH_MASK_1 = {{30-ADDR_WIDTH{1'b0}}, {ADDR_WIDTH{1'b1}}};
localparam BEGIN_ADDRESS_MASK = ADDR_WIDTH_MASK & BEGIN_ADDRESS;
localparam END_ADDRESS_MASK = ADDR_WIDTH_MASK_1 & END_ADDRESS;
localparam SHIFT_COUNT = (31-ADDR_WIDTH) ;
localparam BEGIN_ADDRESS_INT = (BEGIN_ADDRESS_MASK >= END_ADDRESS_MASK) ? (BEGIN_ADDRESS >> SHIFT_COUNT) : BEGIN_ADDRESS_MASK ;
localparam END_ADDRESS_INT = (BEGIN_ADDRESS_MASK >= END_ADDRESS_MASK) ? (END_ADDRESS >> SHIFT_COUNT) : END_ADDRESS_MASK ;
localparam TG_INIT_DATA_MODE = (DATA_PATTERN == "DGEN_ADDR") ? 4'b0010 :
(DATA_PATTERN == "DGEN_HAMMER") ? 4'b0011 :
(DATA_PATTERN == "DGEN_WALKING1") ? 4'b0101 :
(DATA_PATTERN == "DGEN_WALKING0") ? 4'b0110 :
(DATA_PATTERN == "DGEN_PRBS") ? 4'b0111 :
DATA_MODE ;
assign single_operation = 1'b0; // Disable this for 13.3 release
// cmds_gap_delay_value is used in memc_flow_vcontrol module to insert delay between
// each sucessive burst commands. The maximum delay is 32 clock cycles after the last command.
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
localparam CMD_WDT_WIDTH = clogb2(CMD_WDT);
localparam RD_WDT_WIDTH = clogb2(RD_WDT);
localparam WR_WDT_WIDTH = clogb2(WR_WDT);
assign cmds_gap_delay_value = CMDS_GAP_DELAY;
localparam TG_FAMILY = ((FAMILY == "VIRTEX6") || (FAMILY == "VIRTEX7") || (FAMILY == "7SERIES")
|| (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ) ? "VIRTEX6" : "SPARTAN6";
assign tg_memc_wr_en = (TG_FAMILY == "VIRTEX6") ?memc_cmd_en & ~memc_cmd_full : memc_wr_en ;
assign lcl_v_fixed_bl_value = (vio_data_mode_value == 4) ? 32:vio_fixed_bl_value;
assign tg_run_traffic = (run_traffic & ((vio_modify_enable == 1'b1) ? ~vio_pause_traffic : 1'b1)) ;
assign tg_data_mask_gen = (vio_modify_enable == 1'b1) ? vio_data_mask_gen : 1'b0 ;
assign instr_mode_value = (vio_modify_enable == 1'b1) ? vio_instr_mode_value : 4'b0010;
assign tg_instr_mode_value = (single_operation == 1'b1) ? 4'b0111: instr_mode_value;
reg [CMD_WDT_WIDTH-1 : 0] cmd_wdt;
reg [RD_WDT_WIDTH-1 : 0] rd_wdt;
reg [WR_WDT_WIDTH-1 : 0] wr_wdt;
// The following 'generate' statement activates the traffic generator for
// init_mem_pattern_ctr module instantiation for Port-0
mig_7series_v2_0_init_mem_pattern_ctr #
(
.TCQ (TCQ),
.DWIDTH (DATA_WIDTH),
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_TYPE (MEM_TYPE),
.FAMILY (TG_FAMILY),
.BL_WIDTH (10),
.ADDR_WIDTH (ADDR_WIDTH),
.BEGIN_ADDRESS (BEGIN_ADDRESS_INT),
.END_ADDRESS (END_ADDRESS_INT),
.CMD_SEED_VALUE (32'h56456783),
.DATA_SEED_VALUE (32'h12345678),
.DATA_MODE (TG_INIT_DATA_MODE),
.PORT_MODE (PORT_MODE)
)
u_init_mem_pattern_ctr
(
.clk_i (clk),
.rst_i (tg_rst),
.memc_cmd_en_i (memc_cmd_en),
.memc_wr_en_i (tg_memc_wr_en),
.single_write_button (1'b0), // tie off these group of signals for 13.3
.single_read_button (1'b0),
.slow_write_read_button (1'b0),
.single_operation (1'b0),
.vio_modify_enable (vio_modify_enable),
.vio_instr_mode_value (tg_instr_mode_value),
.vio_data_mode_value (vio_data_mode_value),
.vio_addr_mode_value (vio_addr_mode_value),
.vio_bl_mode_value (vio_bl_mode_value), // always set to PRBS_BL mode
.vio_fixed_bl_value (lcl_v_fixed_bl_value), // always set to 64 in order to run PRBS data pattern
.vio_data_mask_gen (vio_data_mask_gen),
.vio_fixed_instr_value (vio_fixed_instr_value),
.memc_init_done_i (memc_init_done),
.cmp_error (error),
.run_traffic_o (run_traffic),
.start_addr_o (tg_start_addr),
.end_addr_o (tg_end_addr),
.cmd_seed_o (tg_cmd_seed),
.data_seed_o (tg_data_seed),
.load_seed_o (tg_load_seed),
.addr_mode_o (tg_addr_mode),
.instr_mode_o (tg_instr_mode),
.bl_mode_o (tg_bl_mode),
.data_mode_o (tg_data_mode),
.mode_load_o (tg_mode_load),
.fixed_bl_o (tg_fixed_bl),
.fixed_instr_o (tg_fixed_instr),
.mem_pattern_init_done_o (mem_pattern_init_done)
);
// traffic generator instantiation for Port-0
mig_7series_v2_0_memc_traffic_gen #
(
.TCQ (TCQ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.nCK_PER_CLK (nCK_PER_CLK),
.PORT_MODE (PORT_MODE),
.DWIDTH (DATA_WIDTH),
.FAMILY (TG_FAMILY),
.MEM_TYPE (MEM_TYPE),
.SIMULATION (SIMULATION),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN ),
.ADDR_WIDTH (ADDR_WIDTH),
.BL_WIDTH (10),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.PRBS_SADDR_MASK_POS (BEGIN_ADDRESS_INT),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR (BEGIN_ADDRESS_INT),
.PRBS_EADDR (END_ADDRESS_INT),
.EYE_TEST (EYE_TEST)
)
u_memc_traffic_gen
(
.clk_i (clk),
.rst_i (tg_rst),
.run_traffic_i (tg_run_traffic),
.manual_clear_error (manual_clear_error),
.cmds_gap_delay_value (cmds_gap_delay_value),
.vio_instr_mode_value (tg_instr_mode_value),
.vio_percent_write ('b0), // bring this to top if want to specify percentage of write commands
// instr_mode_i has to be == 4 if want to use this command pattern
// runtime parameter
.mem_pattern_init_done_i (mem_pattern_init_done),
.single_operation (1'b0),
.start_addr_i (tg_start_addr),
.end_addr_i (tg_end_addr),
.cmd_seed_i (tg_cmd_seed),
.data_seed_i (tg_data_seed),
.load_seed_i (tg_load_seed),
.addr_mode_i (tg_addr_mode),
.instr_mode_i (tg_instr_mode),
.bl_mode_i (tg_bl_mode),
.data_mode_i (tg_data_mode),
.mode_load_i (tg_mode_load),
.wr_data_mask_gen_i (tg_data_mask_gen),
// fixed pattern inputs interface
.fixed_bl_i (tg_fixed_bl),
.fixed_instr_i (tg_fixed_instr),
.fixed_addr_i (fixed_addr_i),
.fixed_data_i (fixed_data_i),
// BRAM interface.
.bram_cmd_i (bram_cmd_i),
// .bram_addr_i (bram_addr_i ),
// .bram_instr_i ( bram_instr_i),
.bram_valid_i (bram_valid_i),
.bram_rdy_o (bram_rdy_o),
// MCB INTERFACE
.memc_cmd_en_o (memc_cmd_en),
.memc_cmd_instr_o (memc_cmd_instr),
.memc_cmd_bl_o (memc_cmd_bl),
.memc_cmd_addr_o (memc_cmd_addr),
.memc_cmd_full_i (memc_cmd_full),
.memc_wr_en_o (memc_wr_en),
.memc_wr_data_end_o (memc_wr_end),
.memc_wr_mask_o (memc_wr_mask),
.memc_wr_data_o (memc_wr_data),
.memc_wr_full_i (memc_wr_full),
.memc_rd_en_o (memc_rd_en),
.memc_rd_data_i (memc_rd_data),
.memc_rd_empty_i (memc_rd_empty),
.qdr_wr_cmd_o (qdr_wr_cmd_o),
.qdr_rd_cmd_o (qdr_rd_cmd_o),
// status feedback
.counts_rst (tg_rst),
.wr_data_counts (wr_data_counts),
.rd_data_counts (rd_data_counts),
.error (error), // asserted whenever the read back data is not correct.
.error_status (error_status), // TBD how signals mapped
.cmp_data (cmp_data),
.cmp_data_valid (cmp_data_valid),
.cmp_error (cmp_error),
.mem_rd_data (),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.dq_error_bytelane_cmp (dq_error_bytelane_cmp),
.cumlative_dq_lane_error (cumlative_dq_lane_error),
.cumlative_dq_r0_bit_error (),
.cumlative_dq_f0_bit_error (),
.cumlative_dq_r1_bit_error (),
.cumlative_dq_f1_bit_error (),
.dq_r0_bit_error_r (),
.dq_f0_bit_error_r (),
.dq_r1_bit_error_r (),
.dq_f1_bit_error_r (),
.dq_r0_read_bit (),
.dq_f0_read_bit (),
.dq_r1_read_bit (),
.dq_f1_read_bit (),
.dq_r0_expect_bit (),
.dq_f0_expect_bit (),
.dq_r1_expect_bit (),
.dq_f1_expect_bit (),
.error_addr ()
);
reg [8:0] wr_cmd_cnt;
reg [8:0] dat_cmd_cnt;
reg rst_remem;
reg [2:0] app_cmd1;
reg [2:0] app_cmd2;
reg [2:0] app_cmd3;
reg [2:0] app_cmd4;
reg [8:0] rst_cntr;
always @(posedge clk) begin
if (rst) begin
rst_remem <= 1'b0;
end else if (tg_only_rst) begin
rst_remem <= 1'b1;
end else if (rst_cntr == 9'h0) begin
rst_remem <= 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
tg_rst <= 1'b1;
end else begin
tg_rst <= (rst_cntr != 9'h1ff);
end
end
always @ (posedge clk)
begin
if (rst)
rst_cntr <= 9'h1ff;
else if (rst_remem & (wr_cmd_cnt==dat_cmd_cnt) & (app_cmd3==3'h1) & (app_cmd4==3'h0))
rst_cntr <= 9'h0;
else if (rst_cntr != 9'h1ff)
rst_cntr <= rst_cntr + 1'b1;
end
always @(posedge clk) begin
if (rst | tg_rst) begin
wr_cmd_cnt <= 1'b0;
end else if (memc_cmd_en & (!memc_cmd_full)& (memc_cmd_instr == 3'h0)) begin
wr_cmd_cnt <= wr_cmd_cnt + 1'b1;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
dat_cmd_cnt <= 1'b0;
end else if (memc_wr_en & (!memc_wr_full)) begin
dat_cmd_cnt <= dat_cmd_cnt + 1'b1;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
app_cmd1 <= 'b0;
app_cmd2 <= 'b0;
app_cmd3 <= 'b0;
app_cmd4 <= 'b0;
end else if (memc_cmd_en & (!memc_cmd_full)) begin
app_cmd1 <= memc_cmd_instr;
app_cmd2 <= app_cmd1;
app_cmd3 <= app_cmd2;
app_cmd4 <= app_cmd3;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
cmd_wdt <= 1'b0;
end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (memc_cmd_full | (!memc_cmd_en)) & wdt_en_i) begin
// init_calib_done !app_rdy app_en
cmd_wdt <= cmd_wdt + 1'b1;
// end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (!memc_cmd_full) & memc_cmd_en & wdt_en_w) begin
end else if ((!memc_cmd_full) & memc_cmd_en) begin
// init_calib_done !app_rdy app_en
cmd_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
rd_wdt <= 1'b0;
end else if (mem_pattern_init_done & (rd_wdt != RD_WDT) & (memc_rd_empty) & wdt_en_i) begin
// !app_rd_data_valid
rd_wdt <= rd_wdt + 1'b1;
end else if (!memc_rd_empty) begin
// !app_rd_data_valid
rd_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
wr_wdt <= 1'b0;
end else if (mem_pattern_init_done & (wr_wdt != WR_WDT) & (!memc_wr_en) & wdt_en_i) begin
// app_wdf_wren
wr_wdt <= wr_wdt + 1'b1;
end else if (memc_wr_en) begin
// app_wdf_wren
wr_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
cmd_wdt_err_o <= 'b0;
rd_wdt_err_o <= 'b0;
wr_wdt_err_o <= 'b0;
end else begin
cmd_wdt_err_o <= cmd_wdt == CMD_WDT;
rd_wdt_err_o <= rd_wdt == RD_WDT;
wr_wdt_err_o <= wr_wdt == WR_WDT;
end
end
//synthesis translate_off
initial
begin
@ (posedge cmd_wdt_err_o);
$display ("ERROR: COMMAND Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge rd_wdt_err_o);
$display ("ERROR: READ Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge wr_wdt_err_o)
$display ("ERROR: WRITE Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge error)
repeat (20) @ (posedge clk);
$finish;
end
//synthesis translate_on
endmodule
|
// /**
// * This Verilog HDL file is used for simulation and synthesis in
// * the chaining DMA design example. It could be used by the software
// * application (Root Port) to retrieve the DMA Performance counter values
// * and performs single DWORD read and write to the Endpoint memory by
// * bypassing the DMA engines.
// */
// synthesis translate_off
`include "altpcierd_dma_dt_cst_sim.v"
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
// packet header bits
`define FMT_BIT0 125
`define LENGTH 105:96
`define ADDR32_BIT2 34
`define ADDR64_BIT2 2
`define TD 111
`define TYPE_BIT0 120
`define PAYLD 126
module altpcierd_cdma_ecrc_gen_ctl_128 (clk, rstn, user_rd_req, user_sop, user_eop, user_data,
user_valid, crc_empty, crc_sop, crc_eop, crc_data, crc_valid, tx_sop, tx_eop,
tx_data, tx_valid, tx_crc_location, tx_shift, av_st_ready);
input clk;
input rstn;
// user data (avalon-st formatted)
output user_rd_req; // request for next user_data
input user_sop; // means this cycle contains the start of a packet
input[1:0] user_eop; // means this cycle contains the end of a packet
input[127:0] user_data; // avalon streaming packet data
input user_valid; // means user_sop, user_eop, user_data are valid
// to CRC module (packed)
output[3:0] crc_empty; // indicates which DWs in crc_data are valid (1'b0) -- indicates where end of pkt is
output crc_sop; // means this cycle contains the start of a packet
output crc_eop; // means this cycle contains the end of a packet
output[127:0] crc_data; // packet data formatted for the CRC module
output crc_valid; // means crc_sop, crc_eop, crc_data, crc_empty are valid
// main datapath (avalon-st formatted)
output tx_sop; // start of pkt flag for transmission
output[1:0] tx_eop; // end of pkt flag for transmission
output[127:0] tx_data; // avalon-ST packet data for transmission
output tx_valid; // means tx_sop, tx_eop, tx_data are valid
output tx_shift;
output[3:0] tx_crc_location; // indicates which DW to insert the CRC field
input av_st_ready; // avalon-st ready input - throttles datapath
reg tx_sop;
reg[1:0] tx_eop;
reg[127:0] tx_data;
reg tx_valid;
reg tx_shift;
reg crc_sop;
reg crc_eop;
reg crc_valid;
reg[3:0] crc_empty;
reg[3:0] tx_crc_location;
reg tx_insert_crc_cyc;
reg send_to_crc_appended; // send data to CRC with 1DW from next cycle inserted into last DW of this cycle
reg send_to_crc_as_is; // send data to CRC unmodified
reg send_to_crc_shifted; // send data to CRC with the 3DW's of this cycle shifted up 1DW, and 1DW from
reg[9:0] tx_rem_length;
wire user_rd_req;
reg[2:0] state;
reg[127:0] user_data_masked_del;
wire[127:0] user_data_masked;
wire [9:0] user_data_length;
reg need_insert_crc_cyc;
wire[127:0] user_data_masked_swizzled;
reg[9:0] crc_rem_length;
reg deferred_valid;
reg inhibit_read;
reg debug_is_aligned;
reg debug_is_3dw;
wire tx_digest;
reg tx_digest_reg;
reg insert_ecrc_in_hi;
assign user_data_length = user_data[`LENGTH];
// state machine states
localparam WAIT_SOP = 3'h0; // wait for the start of a pkt
localparam SEND_PACKED_DATA = 3'h1; // header and data DWs are noncontiguous (3DW Hdr Aligned, or 4DW Hdr NonAligned).. need to shift data
localparam SEND_DATA = 3'h2; // header and data are noncontiguous -- send data thru as-is
localparam EXTRA_CRC_CYC = 3'h3;
/*
ECRC asserts user_rd_req when it processes user_data.
case[1] tx_st_ready_ecrc deasserts when tx_st_valid_int=1
ECRC Interface:
________ ________________
user_rd_req (ack) |___|
________________________
user_valid ____|
______________________________
user_data ____|_0_|_1_____|_2_|_3_|_4_|_
case[2] user_rd_req deasserts when tx_st_valid_int=0
ECRC Interface:
________ ________________
user_rd_req (ack) |___|
___ ____________
user_valid ____| |_______|
______________________________
user_data ____|_0_|_x_____|_1_|_2_|_3_|_
*/
//////////////////////////////////////////////////////////////////////
// Main Datapath
//
// Append digest to all packets except CFG0
assign tx_digest = ((user_sop==1'b1) & (tx_insert_crc_cyc==1'b0)) ? (user_data[122:120]!=3'b100) : tx_digest_reg;
always @ (posedge clk or negedge rstn) begin
if (rstn==1'b0) begin
tx_sop <= 1'b0;
tx_eop <= 2'h0;
tx_data <= 128'h0;
tx_valid <= 1'b0;
tx_shift <= 1'b0;
tx_digest_reg <= 1'b0;
end
else begin
tx_digest_reg <= tx_digest;
if (tx_digest==1'b1) begin
tx_sop <= (tx_insert_crc_cyc==1'b1) ? 1'b0 : ((user_valid==1'b1) ? ((user_sop==1'b1) ? 1'b1 : 1'b0) : 1'b0);
tx_eop <= (tx_insert_crc_cyc==1'b1) ? 2'h0 : ((user_valid==1'b1) ? ((user_eop[1]==1'b1) ? 1'b1 : 1'b0) : 2'h0);
tx_data[127:`TD+1] <= user_data[127:`TD+1];
tx_data[`TD] <= (user_sop==1'b1) ? (tx_digest==1'b1 ? 1'b1 : 1'b0) : (user_data[`TD]==1'b1 ? 1'b1 : 1'b0); // set the digest bit
tx_data[`TD-1:0] <= user_data[`TD-1:0];
tx_shift <= (av_st_ready==1'b1);
tx_valid <= (av_st_ready==1'b1) & ((user_valid==1'b1) | (tx_insert_crc_cyc==1'b1));
end
else begin
tx_sop <= (user_valid==1'b1) ? ((user_sop==1'b1) ? 1'b1 : 1'b0) : 1'b0;
tx_eop <= (user_valid==1'b1) ? user_eop : tx_eop;
tx_data <= user_data;
tx_shift <= (av_st_ready==1'b1) ? 1'b1 : 1'b0;
tx_valid <= ((av_st_ready==1'b1) & (user_valid==1'b1)) ? 1'b1 : 1'b0;
end
end
end
//////////////////////////////////////////////////////////////////////
// Input Data stream throttle control.
// Throttle when:
// - Avalon-ST throttles
// - Need to insert a cycle to account for CRC insertion
assign user_rd_req = (av_st_ready==1'b1) & (inhibit_read ==1'b0);
//////////////////////////////////////////////////////////////////////
// CRC Data Mux
// The user_data input stream can contain DW gaps depending
// on the Header type (3DW/4DW), and the address alignment.
// This mux reformats the data so that there are no gaps because
// the CRC module requires contiguous DWs.
// This mux selects between:
// - Unmodified data format
// - Append DW from next data cycle, Without shifting current data
// - Append DW from next data cycle, And shift current data up 1DW
assign user_data_masked[127:121] = user_data[127:121];
assign user_data_masked[120] = (user_sop==1'b1) ? 1'b1 : user_data[120]; // TYP[0]
assign user_data_masked[119:112] = user_data[119:112];
assign user_data_masked[111] = (user_sop==1'b1) ? 1'b1 : user_data[111]; // TD
assign user_data_masked[110] = (user_sop==1'b1) ? 1'b1 : user_data[110]; // EP
assign user_data_masked[109:0] = user_data[109:0];
// reformat the data-phase portion of the input data to reverse the byte ordering.
// left-most byte is first on line.
assign user_data_masked_swizzled =
((user_sop==1'b1) & ((user_data[`FMT_BIT0]==1'b1) | ((user_data[`FMT_BIT0]==1'b0) & (user_data[`ADDR32_BIT2]==1'b0)))) ? user_data_masked : // 4 DW Hdr or 3DW Aligned - User Data contains Headers only
((user_sop==1'b1) & (user_data[`FMT_BIT0]==1'b0) & (user_data[`ADDR32_BIT2]==1'b1)) ? {user_data_masked[127:32], user_data_masked[7:0], user_data_masked[15:8], user_data_masked[23:16],user_data_masked[31:24]}: // 3DW Hdr Nonaligned - User data contains Header and Data phases
{user_data_masked[103:96], user_data_masked[111:104], user_data_masked[119:112],user_data_masked[127:120],
user_data_masked[71:64], user_data_masked[79:72], user_data_masked[87:80],user_data_masked[95:88],
user_data_masked[39:32], user_data_masked[47:40], user_data_masked[55:48],user_data_masked[63:56],
user_data_masked[7:0], user_data_masked[15:8], user_data_masked[23:16],user_data_masked[31:24] }; // User data contains only Data phase
always @ (posedge clk) begin
if (user_valid) begin
user_data_masked_del <= user_data_masked_swizzled;
end
end
assign crc_data = (send_to_crc_appended==1'b1) ? {user_data_masked_del[127:32], user_data_masked_swizzled[127:96]} :
(send_to_crc_shifted==1'b1) ? {user_data_masked_del[95:0], user_data_masked_swizzled[127:96]} : user_data_masked_del ;
////////////////////////////////////////////////
// CRC Control
// Generates
// - CRC Avalon-ST control signals
// - CRC Data Mux select controls
always @ (posedge clk or negedge rstn) begin
if (rstn==1'b0) begin
state <= WAIT_SOP;
crc_sop <= 1'b0;
crc_eop <= 1'b0;
crc_valid <= 1'b0;
tx_insert_crc_cyc <= 1'b0;
send_to_crc_appended <= 1'b0;
send_to_crc_as_is <= 1'b0;
send_to_crc_shifted <= 1'b0;
tx_rem_length <= 10'h0;
crc_rem_length <= 10'h0;
crc_empty <= 4'h0;
tx_crc_location <= 4'b0000;
insert_ecrc_in_hi <= 1'b0;
deferred_valid <= 1'b0;
inhibit_read <= 1'b0;
debug_is_aligned <= 1'b0;
debug_is_3dw <= 1'b0;
end
else begin
crc_valid <= 1'b0; // default
crc_empty <= 4'h0; // default
crc_eop <= 1'b0; // default
crc_sop <= 1'b0; // default
if (av_st_ready==1'b1) begin
case (state)
WAIT_SOP: begin
crc_valid <= 1'b0; // default
tx_crc_location <= 4'b0000; // default
crc_empty <= 4'h0; // default
crc_eop <= 1'b0; // default
crc_sop <= 1'b0; // default
tx_insert_crc_cyc <= 1'b0; // default
tx_crc_location <= 4'b0000;
insert_ecrc_in_hi <= 1'b0; // default
if ( ((user_sop==1'b1) & (user_valid==1'b1) )
) begin
crc_sop <= 1'b1;
crc_valid <= 1'b1;
deferred_valid <= 1'b0;
debug_is_aligned <= (user_data[`FMT_BIT0]==1'b0) ? (user_data[`ADDR32_BIT2]==1'b0) : (user_data[`ADDR64_BIT2]==1'b0);
debug_is_3dw <= (user_data[`FMT_BIT0]==1'b0);
if (user_data[`FMT_BIT0]==1'b1) begin // 4DW HEADER
crc_empty <= 4'h0;
tx_crc_location <= 4'b0000;
send_to_crc_as_is <= 1'b1;
send_to_crc_appended <= 1'b0;
send_to_crc_shifted <= 1'b0;
if (user_eop[1]==1'b1) begin // this is a single-cycle pkt
tx_insert_crc_cyc <= 1'b1;
inhibit_read <= 1'b1;
state <= EXTRA_CRC_CYC;
crc_eop <= 1'b1;
insert_ecrc_in_hi <= (user_data[`ADDR64_BIT2]==1'b1) ? 1'b1 : 1'b0; // nonaligned/aligned addr
end
else begin // this is a multi-cycle pkt
if (user_data[`ADDR64_BIT2]==1'b1) begin // NonAligned Address -- will need to shift data phases
need_insert_crc_cyc <= (user_data_length[3:2] == 2'h3); // tx_data is 128bit aligned
state <= SEND_PACKED_DATA;
tx_rem_length <= user_data[`LENGTH] +1; // account for empty DW from non-alignment
crc_rem_length <= user_data[`LENGTH];
end
else begin // Aligned Address -- send data phases without shifting
state <= SEND_DATA;
tx_rem_length <= user_data[`LENGTH];
crc_rem_length <= user_data[`LENGTH];
end
end
end
else if (user_data[`FMT_BIT0]==1'b0) begin // 3DW HEADER
if (user_eop[1]==1'b1) begin // this is a single-cycle pkt
send_to_crc_as_is <= 1'b1;
send_to_crc_appended <= 1'b0;
send_to_crc_shifted <= 1'b0;
crc_eop <= 1'b1;
if (user_data[`PAYLD]==1'h0) begin // no payld
if (user_data[`ADDR32_BIT2]==1'b1) begin // non-aligned
crc_empty <= 4'h4;
tx_crc_location <= 4'b1000;
tx_insert_crc_cyc <= 1'b0;
state <= state;
end
else begin // Aligned address
crc_empty <= 4'h4;
tx_crc_location <= 4'b0000;
tx_insert_crc_cyc <= 1'b1;
inhibit_read <= 1'b1;
state <= EXTRA_CRC_CYC;
end
end
else begin // 1DW payld, Non-Aligned
crc_empty <= 4'h0;
tx_crc_location <= 4'b0000;
tx_insert_crc_cyc <= 1'b1;
inhibit_read <= 1'b1;
state <= EXTRA_CRC_CYC;
end
end
else begin // this is a multi-cycle pkt
crc_empty <= 4'h0;
tx_crc_location <= 4'b0000;
if (user_data[`ADDR32_BIT2]==1'b1) begin // NonAligned address
state <= SEND_DATA;
send_to_crc_as_is <= 1'b1;
send_to_crc_appended <= 1'b0;
send_to_crc_shifted <= 1'b0;
tx_rem_length <= user_data[`LENGTH] -1;
crc_rem_length <= user_data[`LENGTH]-1;
end
else begin // Aligned address
send_to_crc_as_is <= 1'b0;
send_to_crc_appended <= 1'b1;
send_to_crc_shifted <= 1'b0;
crc_eop <= (user_data[`LENGTH]==10'h1); // special case: 3DW header, 1DW payload .. This will be the last CRC cycle
state <= SEND_PACKED_DATA;
tx_rem_length <= user_data[`LENGTH]; // no data on this txdata cycle (3DW aligned)
crc_rem_length <= user_data[`LENGTH]-1;
end
end
end // end 3DW Header
end // end sop
end
SEND_PACKED_DATA: begin
send_to_crc_as_is <= 1'b0;
send_to_crc_appended <= 1'b0;
send_to_crc_shifted <= 1'b1;
tx_crc_location <= 4'b0000; // default
crc_empty <= 4'h0; // default
crc_valid <= (user_valid==1'b1) & (crc_rem_length[9:0]!=10'h0);
if (user_valid==1'b1) begin
//if (tx_rem_length > 10'h4) begin // more cycles after this
if (user_eop[1]==1'b0) begin
tx_rem_length <= tx_rem_length - 10'h4;
crc_rem_length <= crc_rem_length - 10'h4;
state <= state;
crc_empty <= 4'h0;
tx_crc_location <= 4'b0000;
crc_eop <= (crc_rem_length < 10'h5); // should separate the crc and tx equations.
end
else begin // this is the last cycle
tx_insert_crc_cyc <= (tx_rem_length[2:0]==3'h4);
inhibit_read <= (tx_rem_length[2:0]==3'h4);
state <= (tx_rem_length[2:0]==3'h4) ? EXTRA_CRC_CYC : WAIT_SOP;
crc_eop <= (crc_rem_length[2:0]!=3'h0);
case (crc_rem_length[2:0])
3'h4: crc_empty <= 4'h0;
3'h3: crc_empty <= 4'h4;
3'h2: crc_empty <= 4'h8;
3'h1: crc_empty <= 4'hc;
endcase
case (tx_rem_length[2:0])
3'h4: tx_crc_location <= 4'b0000;
3'h3: tx_crc_location <= 4'b1000;
3'h2: tx_crc_location <= 4'b0100;
3'h1: tx_crc_location <= 4'b0010;
endcase
end
end
end
SEND_DATA: begin
send_to_crc_as_is <= 1'b1;
send_to_crc_appended <= 1'b0;
send_to_crc_shifted <= 1'b0;
tx_crc_location <= 4'b0000; // default
crc_empty <= 4'h0; // default
crc_valid <= (user_valid==1'b1) & (crc_rem_length[9:0]!=10'h0);
if (user_valid==1'b1) begin
// if (tx_rem_length > 10'h4) begin // more cycles after this
if (user_eop[1]==1'b0) begin
tx_rem_length <= tx_rem_length - 10'h4;
crc_rem_length <= crc_rem_length - 10'h4;
state <= state;
crc_empty <= 4'h0;
tx_crc_location <= 4'b0000;
crc_eop <= (crc_rem_length < 10'h5); // should separate the crc and tx equations.
end
else begin // this is the last cycle
tx_insert_crc_cyc <= (tx_rem_length[2:0]==3'h4);
inhibit_read <= (tx_rem_length[2:0]==3'h4);
state <= (tx_rem_length[2:0]==3'h4) ? EXTRA_CRC_CYC : WAIT_SOP;
crc_eop <= (crc_rem_length[2:0]!=3'h0);
case (crc_rem_length[2:0])
3'h4: crc_empty <= 4'h0;
3'h3: crc_empty <= 4'h4;
3'h2: crc_empty <= 4'h8;
3'h1: crc_empty <= 4'hc;
endcase
case (tx_rem_length[2:0])
3'h4: tx_crc_location <= 4'b0000;
3'h3: tx_crc_location <= 4'b1000;
3'h2: tx_crc_location <= 4'b0100;
3'h1: tx_crc_location <= 4'b0010;
endcase
end
end
end
EXTRA_CRC_CYC: begin
deferred_valid <= (user_valid==1'b1) ? 1'b1 : deferred_valid;
if (av_st_ready==1'b1) begin
inhibit_read <= 1'b0;
tx_insert_crc_cyc <= 1'b0;
state <= WAIT_SOP;
tx_crc_location <= insert_ecrc_in_hi ? 4'b0010 : 4'b0001;
end
end
endcase
end
end
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b1),
.S (S_n)
);
end
endgenerate
endmodule
|
/*
*
* Copyright (c) 2012-2013 fpgaminer@bitcoin-mining.com
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
// A 15 digit binary encoded decimal counter
module bcd_counter # (
parameter STEP = 1
) (
input clk,
input rst,
input [59:0] rx_reset_value,
output reg [59:0] tx_nonce
);
genvar i;
generate
for (i = 0; i < 15; i=i+1) begin : C
reg [3:0] a = 4'd0;
wire [3:0] tx_s;
wire tx_c;
if (i == 0)
bcd_add_digit adder (.rx_a (a), .rx_b (STEP), .rx_c (0), .tx_s (tx_s), .tx_c (tx_c));
else
bcd_add_digit adder (.rx_a (a), .rx_b (0), .rx_c (C[i-1].tx_c), .tx_s (tx_s), .tx_c (tx_c));
always @ (posedge clk)
begin
a <= tx_s;
tx_nonce[(i+1)*4-1:i*4] <= tx_s;
if (rst)
a <= rx_reset_value[(i+1)*4-1:i*4];
end
end
endgenerate
endmodule
module bcd_add_digit (
input [3:0] rx_a,
input [3:0] rx_b,
input rx_c,
output [3:0] tx_s,
output tx_c
);
wire [4:0] s = rx_a + rx_b + rx_c;
wire [4:0] s_wrap = s + 5'd6;
assign tx_s = (s > 5'd9) ? s_wrap[3:0] : s[3:0];
assign tx_c = s > 5'd9;
endmodule
// Add a 15 digit and a 1 digit BCD number together
module bcd_add (
input clk,
input [59:0] rx_a,
input [3:0] rx_b,
output reg [59:0] tx_sum
);
genvar i;
generate
for (i = 0; i < 15; i=i+1) begin : C
wire [3:0] tx_s, b;
wire c, tx_c;
if (i == 0)
assign {c, b} = {1'b0, rx_b};
else
assign {c, b} = {C[i-1].tx_c, 4'b0};
bcd_add_digit adder (.rx_a (rx_a[(i+1)*4-1:i*4]), .rx_b (b), .rx_c (c), .tx_s (tx_s), .tx_c (tx_c));
always @ (posedge clk)
tx_sum[(i+1)*4-1:i*4] <= tx_s;
end
endgenerate
endmodule
|
(** * RecordSub: Subtyping with Records *)
Require Export MoreStlc.
(* ###################################################### *)
(** * Core Definitions *)
(* ################################### *)
(** *** Syntax *)
Inductive ty : Type :=
(* proper types *)
| TTop : ty
| TBase : id -> ty
| TArrow : ty -> ty -> ty
(* record types *)
| TRNil : ty
| TRCons : id -> ty -> ty -> ty.
Tactic Notation "T_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "TTop" | Case_aux c "TBase" | Case_aux c "TArrow"
| Case_aux c "TRNil" | Case_aux c "TRCons" ].
Inductive tm : Type :=
(* proper terms *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tproj : tm -> id -> tm
(* record terms *)
| trnil : tm
| trcons : id -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp" | Case_aux c "tabs"
| Case_aux c "tproj" | Case_aux c "trnil" | Case_aux c "trcons" ].
(* ################################### *)
(** *** Well-Formedness *)
Inductive record_ty : ty -> Prop :=
| RTnil :
record_ty TRNil
| RTcons : forall i T1 T2,
record_ty (TRCons i T1 T2).
Inductive record_tm : tm -> Prop :=
| rtnil :
record_tm trnil
| rtcons : forall i t1 t2,
record_tm (trcons i t1 t2).
Inductive well_formed_ty : ty -> Prop :=
| wfTTop :
well_formed_ty TTop
| wfTBase : forall i,
well_formed_ty (TBase i)
| wfTArrow : forall T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
well_formed_ty (TArrow T1 T2)
| wfTRNil :
well_formed_ty TRNil
| wfTRCons : forall i T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
record_ty T2 ->
well_formed_ty (TRCons i T1 T2).
Hint Constructors record_ty record_tm well_formed_ty.
(* ################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if eq_id_dec x y then s else t
| tabs y T t1 => tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tproj t1 i => tproj (subst x s t1) i
| trnil => trnil
| trcons i t1 tr2 => trcons i (subst x s t1) (subst x s tr2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ################################### *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_rnil : value trnil
| v_rcons : forall i v vr,
value v ->
value vr ->
value (trcons i v vr).
Hint Constructors value.
Fixpoint Tlookup (i:id) (Tr:ty) : option ty :=
match Tr with
| TRCons i' T Tr' => if eq_id_dec i i' then Some T else Tlookup i Tr'
| _ => None
end.
Fixpoint tlookup (i:id) (tr:tm) : option tm :=
match tr with
| trcons i' t tr' => if eq_id_dec i i' then Some t else tlookup i tr'
| _ => None
end.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
| ST_Proj1 : forall tr tr' i,
tr ==> tr' ->
(tproj tr i) ==> (tproj tr' i)
| ST_ProjRcd : forall tr i vi,
value tr ->
tlookup i tr = Some vi ->
(tproj tr i) ==> vi
| ST_Rcd_Head : forall i t1 t1' tr2,
t1 ==> t1' ->
(trcons i t1 tr2) ==> (trcons i t1' tr2)
| ST_Rcd_Tail : forall i v1 tr2 tr2',
value v1 ->
tr2 ==> tr2' ->
(trcons i v1 tr2) ==> (trcons i v1 tr2')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1" | Case_aux c "ST_App2"
| Case_aux c "ST_Proj1" | Case_aux c "ST_ProjRcd" | Case_aux c "ST_Rcd"
| Case_aux c "ST_Rcd_Head" | Case_aux c "ST_Rcd_Tail" ].
Hint Constructors step.
(* ###################################################################### *)
(** * Subtyping *)
(** Now we come to the interesting part. We begin by defining
the subtyping relation and developing some of its important
technical properties. *)
(* ################################### *)
(** ** Definition *)
(** The definition of subtyping is essentially just what we
sketched in the motivating discussion, but we need to add
well-formedness side conditions to some of the rules. *)
Inductive subtype : ty -> ty -> Prop :=
(* Subtyping between proper types *)
| S_Refl : forall T,
well_formed_ty T ->
subtype T T
| S_Trans : forall S U T,
subtype S U ->
subtype U T ->
subtype S T
| S_Top : forall S,
well_formed_ty S ->
subtype S TTop
| S_Arrow : forall S1 S2 T1 T2,
subtype T1 S1 ->
subtype S2 T2 ->
subtype (TArrow S1 S2) (TArrow T1 T2)
(* Subtyping between record types *)
| S_RcdWidth : forall i T1 T2,
well_formed_ty (TRCons i T1 T2) ->
subtype (TRCons i T1 T2) TRNil
| S_RcdDepth : forall i S1 T1 Sr2 Tr2,
subtype S1 T1 ->
subtype Sr2 Tr2 ->
record_ty Sr2 ->
record_ty Tr2 ->
subtype (TRCons i S1 Sr2) (TRCons i T1 Tr2)
| S_RcdPerm : forall i1 i2 T1 T2 Tr3,
well_formed_ty (TRCons i1 T1 (TRCons i2 T2 Tr3)) ->
i1 <> i2 ->
subtype (TRCons i1 T1 (TRCons i2 T2 Tr3))
(TRCons i2 T2 (TRCons i1 T1 Tr3)).
Hint Constructors subtype.
Tactic Notation "subtype_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "S_Refl" | Case_aux c "S_Trans" | Case_aux c "S_Top"
| Case_aux c "S_Arrow" | Case_aux c "S_RcdWidth"
| Case_aux c "S_RcdDepth" | Case_aux c "S_RcdPerm" ].
(* ############################################### *)
(** ** Subtyping Examples and Exercises *)
Module Examples.
Notation x := (Id 0).
Notation y := (Id 1).
Notation z := (Id 2).
Notation j := (Id 3).
Notation k := (Id 4).
Notation i := (Id 5).
Notation A := (TBase (Id 6)).
Notation B := (TBase (Id 7)).
Notation C := (TBase (Id 8)).
Definition TRcd_j :=
(TRCons j (TArrow B B) TRNil). (* {j:B->B} *)
Definition TRcd_kj :=
TRCons k (TArrow A A) TRcd_j. (* {k:C->C,j:B->B} *)
Example subtyping_example_0 :
subtype (TArrow C TRcd_kj)
(TArrow C TRNil).
(* C->{k:A->A,j:B->B} <: C->{} *)
Proof.
apply S_Arrow.
apply S_Refl. auto.
unfold TRcd_kj, TRcd_j. apply S_RcdWidth; auto.
Qed.
(** The following facts are mostly easy to prove in Coq. To get
full benefit from the exercises, make sure you also
understand how to prove them on paper! *)
(** **** Exercise: 2 stars *)
Example subtyping_example_1 :
subtype TRcd_kj TRcd_j.
(* {k:A->A,j:B->B} <: {j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star *)
Example subtyping_example_2 :
subtype (TArrow TTop TRcd_kj)
(TArrow (TArrow C C) TRcd_j).
(* Top->{k:A->A,j:B->B} <: (C->C)->{j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star *)
Example subtyping_example_3 :
subtype (TArrow TRNil (TRCons j A TRNil))
(TArrow (TRCons k B TRNil) TRNil).
(* {}->{j:A} <: {k:B}->{} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars *)
Example subtyping_example_4 :
subtype (TRCons x A (TRCons y B (TRCons z C TRNil)))
(TRCons z C (TRCons y B (TRCons x A TRNil))).
(* {x:A,y:B,z:C} <: {z:C,y:B,x:A} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
Definition trcd_kj :=
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil)).
End Examples.
(* ###################################################################### *)
(** ** Properties of Subtyping *)
(** *** Well-Formedness *)
Lemma subtype__wf : forall S T,
subtype S T ->
well_formed_ty T /\ well_formed_ty S.
Proof with eauto.
intros S T Hsub.
subtype_cases (induction Hsub) Case;
intros; try (destruct IHHsub1; destruct IHHsub2)...
Case "S_RcdPerm".
split... inversion H. subst. inversion H5... Qed.
Lemma wf_rcd_lookup : forall i T Ti,
well_formed_ty T ->
Tlookup i T = Some Ti ->
well_formed_ty Ti.
Proof with eauto.
intros i T.
T_cases (induction T) Case; intros; try solve by inversion.
Case "TRCons".
inversion H. subst. unfold Tlookup in H0.
destruct (eq_id_dec i i0)... inversion H0; subst... Qed.
(** *** Field Lookup *)
(** Our record matching lemmas get a little more complicated in
the presence of subtyping for two reasons: First, record
types no longer necessarily describe the exact structure of
corresponding terms. Second, reasoning by induction on
[has_type] derivations becomes harder in general, because
[has_type] is no longer syntax directed. *)
Lemma rcd_types_match : forall S T i Ti,
subtype S T ->
Tlookup i T = Some Ti ->
exists Si, Tlookup i S = Some Si /\ subtype Si Ti.
Proof with (eauto using wf_rcd_lookup).
intros S T i Ti Hsub Hget. generalize dependent Ti.
subtype_cases (induction Hsub) Case; intros Ti Hget;
try solve by inversion.
Case "S_Refl".
exists Ti...
Case "S_Trans".
destruct (IHHsub2 Ti) as [Ui Hui]... destruct Hui.
destruct (IHHsub1 Ui) as [Si Hsi]... destruct Hsi.
exists Si...
Case "S_RcdDepth".
rename i0 into k.
unfold Tlookup. unfold Tlookup in Hget.
destruct (eq_id_dec i k)...
SCase "i = k -- we're looking up the first field".
inversion Hget. subst. exists S1...
Case "S_RcdPerm".
exists Ti. split.
SCase "lookup".
unfold Tlookup. unfold Tlookup in Hget.
destruct (eq_id_dec i i1)...
SSCase "i = i1 -- we're looking up the first field".
destruct (eq_id_dec i i2)...
SSSCase "i = i2 - -contradictory".
destruct H0.
subst...
SCase "subtype".
inversion H. subst. inversion H5. subst... Qed.
(** **** Exercise: 3 stars (rcd_types_match_informal) *)
(** Write a careful informal proof of the [rcd_types_match]
lemma. *)
(* FILL IN HERE *)
(** [] *)
(** *** Inversion Lemmas *)
(** **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
subtype U (TArrow V1 V2) ->
exists U1, exists U2,
(U=(TArrow U1 U2)) /\ (subtype V1 U1) /\ (subtype U2 V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (TArrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** * Typing *)
Definition context := id -> (option ty).
Definition empty : context := (fun _ => None).
Definition extend (Gamma : context) (x:id) (T : ty) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
well_formed_ty T ->
has_type Gamma (tvar x) T
| T_Abs : forall Gamma x T11 T12 t12,
well_formed_ty T11 ->
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tabs x T11 t12) (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (TArrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tapp t1 t2) T2
| T_Proj : forall Gamma i t T Ti,
has_type Gamma t T ->
Tlookup i T = Some Ti ->
has_type Gamma (tproj t i) Ti
(* Subsumption *)
| T_Sub : forall Gamma t S T,
has_type Gamma t S ->
subtype S T ->
has_type Gamma t T
(* Rules for record terms *)
| T_RNil : forall Gamma,
has_type Gamma trnil TRNil
| T_RCons : forall Gamma i t T tr Tr,
has_type Gamma t T ->
has_type Gamma tr Tr ->
record_ty Tr ->
record_tm tr ->
has_type Gamma (trcons i t tr) (TRCons i T Tr)
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Proj" | Case_aux c "T_Sub"
| Case_aux c "T_RNil" | Case_aux c "T_RCons" ].
(* ############################################### *)
(** ** Typing Examples *)
Module Examples2.
Import Examples.
(** **** Exercise: 1 star *)
Example typing_example_0 :
has_type empty
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil))
TRcd_kj.
(* empty |- {k=(\z:A.z), j=(\z:B.z)} : {k:A->A,j:B->B} *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars *)
Example typing_example_1 :
has_type empty
(tapp (tabs x TRcd_j (tproj (tvar x) j))
(trcd_kj))
(TArrow B B).
(* empty |- (\x:{k:A->A,j:B->B}. x.j) {k=(\z:A.z), j=(\z:B.z)} : B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Example typing_example_2 :
has_type empty
(tapp (tabs z (TArrow (TArrow C C) TRcd_j)
(tproj (tapp (tvar z)
(tabs x C (tvar x)))
j))
(tabs z (TArrow C C) trcd_kj))
(TArrow B B).
(* empty |- (\z:(C->C)->{j:B->B}. (z (\x:C.x)).j)
(\z:C->C. {k=(\z:A.z), j=(\z:B.z)})
: B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples2.
(* ###################################################################### *)
(** ** Properties of Typing *)
(** *** Well-Formedness *)
Lemma has_type__wf : forall Gamma t T,
has_type Gamma t T -> well_formed_ty T.
Proof with eauto.
intros Gamma t T Htyp.
has_type_cases (induction Htyp) Case...
Case "T_App".
inversion IHHtyp1...
Case "T_Proj".
eapply wf_rcd_lookup...
Case "T_Sub".
apply subtype__wf in H.
destruct H...
Qed.
Lemma step_preserves_record_tm : forall tr tr',
record_tm tr ->
tr ==> tr' ->
record_tm tr'.
Proof.
intros tr tr' Hrt Hstp.
inversion Hrt; subst; inversion Hstp; subst; eauto.
Qed.
(** *** Field Lookup *)
Lemma lookup_field_in_value : forall v T i Ti,
value v ->
has_type empty v T ->
Tlookup i T = Some Ti ->
exists vi, tlookup i v = Some vi /\ has_type empty vi Ti.
Proof with eauto.
remember empty as Gamma.
intros t T i Ti Hval Htyp. revert Ti HeqGamma Hval.
has_type_cases (induction Htyp) Case; intros; subst; try solve by inversion.
Case "T_Sub".
apply (rcd_types_match S) in H0... destruct H0 as [Si [HgetSi Hsub]].
destruct (IHHtyp Si) as [vi [Hget Htyvi]]...
Case "T_RCons".
simpl in H0. simpl. simpl in H1.
destruct (eq_id_dec i i0).
SCase "i is first".
inversion H1. subst. exists t...
SCase "i in tail".
destruct (IHHtyp2 Ti) as [vi [get Htyvi]]...
inversion Hval... Qed.
(* ########################################## *)
(** *** Progress *)
(** **** Exercise: 3 stars (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
has_type Gamma s (TArrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tabs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
has_type_cases (induction Ht) Case;
intros HeqGamma; subst...
Case "T_Var".
inversion H.
Case "T_App".
right.
destruct IHHt1; subst...
SCase "t1 is a value".
destruct IHHt2; subst...
SSCase "t2 is a value".
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists ([x:=t2]t12)...
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_Proj".
right. destruct IHHt...
SCase "rcd is value".
destruct (lookup_field_in_value t T i Ti) as [t' [Hget Ht']]...
SCase "rcd_steps".
destruct H0 as [t' Hstp]. exists (tproj t' i)...
Case "T_RCons".
destruct IHHt1...
SCase "head is a value".
destruct IHHt2...
SSCase "tail steps".
right. destruct H2 as [tr' Hstp].
exists (trcons i t tr')...
SCase "head steps".
right. destruct H1 as [t' Hstp].
exists (trcons i t' tr)... Qed.
(** Informal proof of progress:
Theorem : For any term [t] and type [T], if [empty |- t : T]
then [t] is a value or [t ==> t'] for some term [t'].
Proof : Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the typing derivation. Cases [T_Abs] and
[T_RNil] are immediate because abstractions and [{}] are always
values. Case [T_Var] is vacuous because variables cannot be
typed in the empty context.
- If the last step in the typing derivation is by [T_App], then
there are terms [t1] [t2] and types [T1] [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2] and
[empty |- t2 : T1].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [t2] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then
[t1 t2 ==> t1' t2] by [ST_App1].
- Otherwise [t1] is a value.
- Suppose [t2 ==> t2'] for some term [t2']. Then
[t1 t2 ==> t1 t2'] by rule [ST_App2] because [t1] is a value.
- Otherwise, [t2] is a value. By lemma
[canonical_forms_for_arrow_types], [t1 = \x:S1.s2] for some
[x], [S1], and [s2]. And [(\x:S1.s2) t2 ==> [x:=t2]s2] by
[ST_AppAbs], since [t2] is a value.
- If the last step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing subderivation gives us that either [tr]
is a value or it steps. If [tr ==> tr'] for some term [tr'],
then [tr.i ==> tr'.i] by rule [ST_Proj1].
Otherwise, [tr] is a value. In this case, lemma
[lookup_field_in_value] yields that there is a term [ti] such
that [tlookup i tr = Some ti]. It follows that [tr.i ==> ti]
by rule [ST_ProjRcd].
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
desired result is exactly the induction hypothesis for the
typing subderivation.
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [tr] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then
[{i=t1, tr} ==> {i=t1', tr}] by rule [ST_Rcd_Head].
- Otherwise [t1] is a value.
- Suppose [tr ==> tr'] for some term [tr']. Then
[{i=t1, tr} ==> {i=t1, tr'}] by rule [ST_Rcd_Tail],
since [t1] is a value.
- Otherwise, [tr] is also a value. So, [{i=t1, tr}] is a
value by [v_rcons]. *)
(* ########################################## *)
(** *** Inversion Lemmas *)
Lemma typing_inversion_var : forall Gamma x T,
has_type Gamma (tvar x) T ->
exists S,
Gamma x = Some S /\ subtype S T.
Proof with eauto.
intros Gamma x T Hty.
remember (tvar x) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_Var".
exists T...
Case "T_Sub".
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
has_type Gamma (tapp t1 t2) T2 ->
exists T1,
has_type Gamma t1 (TArrow T1 T2) /\
has_type Gamma t2 T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tapp t1 t2) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_App".
exists T1...
Case "T_Sub".
destruct IHHty as [U1 [Hty1 Hty2]]...
assert (Hwf := has_type__wf _ _ _ Hty2).
exists U1... Qed.
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
has_type Gamma (tabs x S1 t2) T ->
(exists S2, subtype (TArrow S1 S2) T
/\ has_type (extend Gamma x S1) t2 S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tabs x S1 t2) as t.
has_type_cases (induction H) Case;
inversion Heqt; subst; intros; try solve by inversion.
Case "T_Abs".
assert (Hwf := has_type__wf _ _ _ H0).
exists T12...
Case "T_Sub".
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
Lemma typing_inversion_proj : forall Gamma i t1 Ti,
has_type Gamma (tproj t1 i) Ti ->
exists T, exists Si,
Tlookup i T = Some Si /\ subtype Si Ti /\ has_type Gamma t1 T.
Proof with eauto.
intros Gamma i t1 Ti H.
remember (tproj t1 i) as t.
has_type_cases (induction H) Case;
inversion Heqt; subst; intros; try solve by inversion.
Case "T_Proj".
assert (well_formed_ty Ti) as Hwf.
SCase "pf of assertion".
apply (wf_rcd_lookup i T Ti)...
apply has_type__wf in H...
exists T. exists Ti...
Case "T_Sub".
destruct IHhas_type as [U [Ui [Hget [Hsub Hty]]]]...
exists U. exists Ui... Qed.
Lemma typing_inversion_rcons : forall Gamma i ti tr T,
has_type Gamma (trcons i ti tr) T ->
exists Si, exists Sr,
subtype (TRCons i Si Sr) T /\ has_type Gamma ti Si /\
record_tm tr /\ has_type Gamma tr Sr.
Proof with eauto.
intros Gamma i ti tr T Hty.
remember (trcons i ti tr) as t.
has_type_cases (induction Hty) Case;
inversion Heqt; subst...
Case "T_Sub".
apply IHHty in H0.
destruct H0 as [Ri [Rr [HsubRS [HtypRi HtypRr]]]].
exists Ri. exists Rr...
Case "T_RCons".
assert (well_formed_ty (TRCons i T Tr)) as Hwf.
SCase "pf of assertion".
apply has_type__wf in Hty1.
apply has_type__wf in Hty2...
exists T. exists Tr... Qed.
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ########################################## *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_proj : forall x t i,
appears_free_in x t ->
appears_free_in x (tproj t i)
| afi_rhead : forall x i t tr,
appears_free_in x t ->
appears_free_in x (trcons i t tr)
| afi_rtail : forall x i t tr,
appears_free_in x tr ->
appears_free_in x (trcons i t tr).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold extend. destruct (eq_id_dec x x0)...
Case "T_App".
apply T_App with T1...
Case "T_RCons".
apply T_RCons... Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case; subst; inversion Hafi; subst...
Case "T_Abs".
destruct (IHHtyp H5) as [T Hctx]. exists T.
unfold extend in Hctx. rewrite neq_id in Hctx... Qed.
(* ########################################## *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
t_cases (induction t) Case; intros; simpl.
Case "tvar".
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt) as [T [Hctx Hsub]].
unfold extend in Hctx.
destruct (eq_id_dec x y)...
SCase "x=y".
subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
destruct (subtype__wf _ _ Hsub)...
Case "tapp".
destruct (typing_inversion_app _ _ _ _ Htypt) as [T1 [Htypt1 Htypt2]].
eapply T_App...
Case "tabs".
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
destruct (subtype__wf _ _ Hsub) as [Hwf1 Hwf2].
inversion Hwf2. subst.
apply T_Sub with (TArrow T1 T2)... apply T_Abs...
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Case "tproj".
destruct (typing_inversion_proj _ _ _ _ Htypt)
as [T [Ti [Hget [Hsub Htypt1]]]]...
Case "trnil".
eapply context_invariance...
intros y Hcontra. inversion Hcontra.
Case "trcons".
destruct (typing_inversion_rcons _ _ _ _ _ Htypt) as
[Ti [Tr [Hsub [HtypTi [Hrcdt2 HtypTr]]]]].
apply T_Sub with (TRCons i Ti Tr)...
apply T_RCons...
SCase "record_ty Tr".
apply subtype__wf in Hsub. destruct Hsub. inversion H0...
SCase "record_tm ([x:=v]t2)".
inversion Hrcdt2; subst; simpl... Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
inversion HE; subst...
SCase "ST_AppAbs".
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
Case "T_Proj".
destruct (lookup_field_in_value _ _ _ _ H2 HT H)
as [vi [Hget Hty]].
rewrite H4 in Hget. inversion Hget. subst...
Case "T_RCons".
eauto using step_preserves_record_tm. Qed.
(** Informal proof of [preservation]:
Theorem: If [t], [t'] are terms and [T] is a type such that
[empty |- t : T] and [t ==> t'], then [empty |- t' : T].
Proof: Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the structure of this typing derivation, leaving
[t'] general. Cases [T_Abs] and [T_RNil] are vacuous because
abstractions and {} don't step. Case [T_Var] is vacuous as well,
since the context is empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] [t2] and types [T1] [T2] such that [t = t1 t2],
[T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 : T1].
By inspection of the definition of the step relation, there are
three ways [t1 t2] can step. Cases [ST_App1] and [ST_App2]
follow immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then
[t1 = \x:S.t12] for some type [S] and term [t12], and
[t' = [x:=t2]t12].
By Lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by lemma [substitution_preserves_typing] that
[empty |- [x:=t2] t12 : T2] as desired.
- If the final step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing derivation gives us that, for any term
[tr'], if [tr ==> tr'] then [empty |- tr' Tr]. Inspection of
the definition of the step relation reveals that there are two
ways a projection can step. Case [ST_Proj1] follows
immediately by the IH.
Instead suppose [tr.i] steps by [ST_ProjRcd]. Then [tr] is a
value and there is some term [vi] such that
[tlookup i tr = Some vi] and [t' = vi]. But by lemma
[lookup_field_in_value], [empty |- vi : Ti] as desired.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub].
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
By the definition of the step relation, [t] must have stepped
by [ST_Rcd_Head] or [ST_Rcd_Tail]. In the first case, the
result follows by the IH for [t1]'s typing derivation and
[T_RCons]. In the second case, the result follows by the IH
for [tr]'s typing derivation, [T_RCons], and a use of the
[step_preserves_record_tm] lemma. *)
(* ###################################################### *)
(** ** Exercises on Typing *)
(** **** Exercise: 2 stars, optional (variations) *)
(** Each part of this problem suggests a different way of
changing the definition of the STLC with records and
subtyping. (These changes are not cumulative: each part
starts from the original language.) In each part, list which
properties (Progress, Preservation, both, or neither) become
false. If a property becomes false, give a counterexample.
- Suppose we add the following typing rule:
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
- Suppose we add the following reduction rule:
------------------ (ST_Funny21)
{} ==> (\x:Top. x)
- Suppose we add the following subtyping rule:
-------------- (S_Funny3)
{} <: Top->Top
- Suppose we add the following subtyping rule:
-------------- (S_Funny4)
Top->Top <: {}
- Suppose we add the following evaluation rule:
----------------- (ST_Funny5)
({} t) ==> (t {})
- Suppose we add the same evaluation rule *and* a new typing rule:
----------------- (ST_Funny5)
({} t) ==> (t {})
---------------------- (T_Funny6)
empty |- {} : Top->Top
- Suppose we *change* the arrow subtyping rule to:
S1 <: T1 S2 <: T2
----------------------- (S_Arrow')
S1->S2 <: T1->T2
[]
*)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
/*
* RawaPro.v
*
* Created on: 09/10/2012
* Author: Lord_Rafa
*/
`timescale 1ns / 1ps
module RawaPro (
// inputs:
top_HC_ADC_DOUT,
top_HC_ADC_PENIRQ_N,
top_HC_RX_CLK,
top_HC_RX_COL,
top_HC_RX_CRS,
top_HC_RX_D,
top_HC_RX_DV,
top_HC_RX_ERR,
top_HC_SD_DAT,
top_HC_TX_CLK,
top_HC_UART_RXD,
top_button,
top_clkin_50,
top_reset_n,
// outputs:
top_HC_ADC_CS_N,
top_HC_ADC_DCLK,
top_HC_ADC_DIN,
top_HC_DEN,
top_HC_ETH_RESET_N,
top_HC_HD,
top_HC_ID_I2CDAT,
top_HC_ID_I2CSCL,
top_HC_LCD_DATA,
top_HC_MDC,
top_HC_MDIO,
top_HC_SCEN,
top_HC_SDA,
top_HC_SD_CLK,
top_HC_SD_CMD,
top_HC_SD_DAT3,
top_HC_TX_D,
top_HC_TX_EN,
top_HC_UART_TXD,
top_HC_VD,
top_clk_to_offchip_video,
top_flash_cs_n,
top_flash_oe_n,
top_flash_reset_n,
top_flash_ssram_a,
top_flash_ssram_d,
top_flash_wr_n,
top_led,
top_mem_addr,
top_mem_ba,
top_mem_cas_n,
top_mem_cke,
top_mem_clk,
top_mem_clk_n,
top_mem_cs_n,
top_mem_dm,
top_mem_dq,
top_mem_dqs,
top_mem_ras_n,
top_mem_we_n,
top_ssram_adsc_n,
top_ssram_bw_n,
top_ssram_bwe_n,
top_ssram_ce_n,
top_ssram_clk,
top_ssram_oe_n,
top_HC_TD_D,
top_HC_TD_HS,
top_HC_TD_VS,
top_HC_TD_27MHZ,
top_HC_TD_RESET,
top_HC_I2C_SCLK,
top_HC_I2C_SDAT,
top_HC_GREST
);
output top_HC_ADC_CS_N;
output top_HC_ADC_DCLK;
output top_HC_ADC_DIN;
output top_HC_DEN;
output top_HC_ETH_RESET_N;
output top_HC_HD;
inout top_HC_ID_I2CDAT;
output top_HC_ID_I2CSCL;
output [ 7: 0] top_HC_LCD_DATA;
output top_HC_MDC;
inout top_HC_MDIO;
output top_HC_SCEN;
inout top_HC_SDA;
output top_HC_SD_CLK;
output top_HC_SD_CMD;
output top_HC_SD_DAT3;
output [ 3: 0] top_HC_TX_D;
output top_HC_TX_EN;
output top_HC_UART_TXD;
output top_HC_VD;
output top_clk_to_offchip_video;
output top_flash_cs_n;
output top_flash_oe_n;
output top_flash_reset_n;
output [ 23: 1] top_flash_ssram_a;
inout [ 31: 0] top_flash_ssram_d;
output top_flash_wr_n;
output [ 3: 0] top_led;
output [ 12: 0] top_mem_addr;
output [ 1: 0] top_mem_ba;
output top_mem_cas_n;
output top_mem_cke;
inout top_mem_clk;
inout top_mem_clk_n;
output top_mem_cs_n;
output [ 1: 0] top_mem_dm;
inout [ 15: 0] top_mem_dq;
inout [ 1: 0] top_mem_dqs;
output top_mem_ras_n;
output top_mem_we_n;
output top_ssram_adsc_n;
output [ 3: 0] top_ssram_bw_n;
output top_ssram_bwe_n;
output top_ssram_ce_n;
output top_ssram_clk;
output top_ssram_oe_n;
input top_HC_ADC_DOUT;
input top_HC_ADC_PENIRQ_N;
input top_HC_RX_CLK;
input top_HC_RX_COL;
input top_HC_RX_CRS;
input [ 3: 0] top_HC_RX_D;
input top_HC_RX_DV;
input top_HC_RX_ERR;
input top_HC_SD_DAT;
input top_HC_TX_CLK;
input top_HC_UART_RXD;
input [ 3: 0] top_button;
input top_clkin_50;
input top_reset_n;
//TV Decoder
input [7:0] top_HC_TD_D;
input top_HC_TD_HS;
input top_HC_TD_VS;
input top_HC_TD_27MHZ;
output top_HC_TD_RESET;
// Audio and TV decoder I2C
output top_HC_I2C_SCLK;
inout top_HC_I2C_SDAT;
output top_HC_GREST;
wire top_CDn_to_the_el_camino_sd_card_controller;
wire top_HC_ADC_CS_N;
wire top_HC_ADC_DCLK;
wire top_HC_ADC_DIN;
wire top_HC_DEN;
wire top_HC_ETH_RESET_N;
wire top_HC_HD;
wire top_HC_ID_I2CDAT;
wire top_HC_ID_I2CSCL;
wire [ 7: 0] top_HC_LCD_DATA;
wire top_HC_MDC;
wire top_HC_MDIO;
wire top_HC_SCEN;
wire top_HC_SDA;
wire top_HC_SD_CLK;
wire top_HC_SD_CMD;
wire top_HC_SD_DAT3;
wire [ 3: 0] top_HC_TX_D;
wire top_HC_TX_EN;
wire top_HC_UART_TXD;
wire top_HC_VD;
wire top_SCLK_from_the_touch_panel_spi;
wire top_SS_n_from_the_touch_panel_spi;
wire top_WP_to_the_el_camino_sd_card_controller;
wire top_clk_to_offchip_video;
wire top_ddr_sdram_aux_full_rate_clk_out;
wire top_ddr_sdram_aux_half_rate_clk_out;
wire top_ddr_sdram_phy_clk_out;
wire top_flash_cs_n;
wire top_flash_oe_n;
wire top_flash_reset_n;
wire [ 23: 1] top_flash_ssram_a;
wire [ 31: 0] top_flash_ssram_d;
wire top_flash_wr_n;
wire [ 3: 0] top_in_port_to_the_button_pio;
wire [ 3: 0] top_led;
wire top_local_init_done_from_the_ddr_sdram;
wire top_local_refresh_ack_from_the_ddr_sdram;
wire top_local_wdata_req_from_the_ddr_sdram;
wire [ 12: 0] top_mem_addr;
wire [ 1: 0] top_mem_ba;
wire top_mem_cas_n;
wire top_mem_cke;
wire top_mem_clk;
wire top_mem_clk_n;
wire top_mem_cs_n;
wire [ 1: 0] top_mem_dm;
wire [ 15: 0] top_mem_dq;
wire [ 1: 0] top_mem_dqs;
wire top_mem_ras_n;
wire top_mem_we_n;
wire top_out_port_from_the_lcd_i2c_en;
wire top_out_port_from_the_lcd_i2c_scl;
wire top_peripheral_clk;
wire top_remote_update_clk;
wire top_reset_phy_clk_n_from_the_ddr_sdram;
wire top_ssram_adsc_n;
wire [ 3: 0] top_ssram_bw_n;
wire top_ssram_bwe_n;
wire top_ssram_ce_n;
wire top_ssram_clk;
wire top_ssram_oe_n;
wire h_sync;
wire v_sync;
wire video_in_valid;
wire video_in_locked;
wire [7:0] video_in_data;
wire lcd_base_clock;
wire lcd_clock; // *3 of the base clock
wire [23:0] LCD_DATA;
wire LCD_BLANK;
wire LCD_HS;
wire LCD_VS;
wire clk_100;
wire clk_33;
wire clk_120;
wire clk_40;
wire [3:0] led_pio_wire;
wire dmy;
SistemaPrincipal SistemaPrincipal_instance (
//*******************Reloj Principal*******************
.sys_clk_clk (top_clkin_50),
.reset_reset_n (top_reset_n),
//-----------------------------------------------------
//******************Relojes de Salida******************
.clk_100_clk (clk_100),
.clk_33_clk (clk_33),
.altpll_0_areset_conduit_export (0),
//-----------------------------------------------------
//******************Entrada de Video*******************
.bidir_port_to_and_from_the_av_i2c_data_pio (top_HC_I2C_SDAT),
.out_port_from_the_av_i2c_clk_pio (top_HC_I2C_SCLK),
.out_port_from_the_td_reset_pio (top_HC_TD_RESET),
.video_in_vid_clk (top_HC_TD_27MHZ),
.video_in_vid_data (video_in_data),
.video_in_vid_datavalid (video_in_valid),
.video_in_vid_locked (video_in_locked),
//-----------------------------------------------------
//*******************Salida de Video*******************
.out_port_from_the_lcd_i2c_en (top_out_port_from_the_lcd_i2c_en),
.out_port_from_the_lcd_i2c_scl (top_out_port_from_the_lcd_i2c_scl),
.bidir_port_to_and_from_the_lcd_i2c_sdat (top_HC_SDA),
.video_out_vid_clk (lcd_base_clock),
.video_out_vid_data (LCD_DATA),
.video_out_vid_datavalid (LCD_BLANK),
.video_out_vid_h_sync (LCD_HS),
.video_out_vid_v_sync (LCD_VS),
//-----------------------------------------------------
//*********************Memoria RAM*********************
.ddr_sdram_memory_mem_addr (top_mem_addr),
.ddr_sdram_memory_mem_ba (top_mem_ba),
.ddr_sdram_memory_mem_cas_n (top_mem_cas_n),
.ddr_sdram_memory_mem_cke (top_mem_cke),
.ddr_sdram_memory_mem_clk_n (top_mem_clk_n),
.ddr_sdram_memory_mem_clk (top_mem_clk),
.ddr_sdram_memory_mem_cs_n (top_mem_cs_n),
.ddr_sdram_memory_mem_dm (top_mem_dm),
.ddr_sdram_memory_mem_dq (top_mem_dq),
.ddr_sdram_memory_mem_dqs (top_mem_dqs),
.ddr_sdram_memory_mem_ras_n (top_mem_ras_n),
.ddr_sdram_memory_mem_we_n (top_mem_we_n),
.ddr_sdram_external_connection_reset_phy_clk_n (top_reset_phy_clk_n_from_the_ddr_sdram),
//-----------------------------------------------------
//************************Otros************************
.key_pio_export (top_in_port_to_the_button_pio),
.led_pio_export (led_pio_wire)
//-----------------------------------------------------
);
assign video_in_data = top_HC_TD_D;
assign video_in_valid = 1'b1;
assign video_in_locked = 1'b1;
vga_serial u_lcd_serial(
.data(LCD_DATA), .blank(LCD_BLANK), .hs(LCD_HS), .vs(LCD_VS),
.clk3(lcd_clock), .data3(top_HC_LCD_DATA), .blank3(top_HC_DEN), .hs3(h_sync), .vs3(v_sync)
);
assign lcd_clock = clk_100;
assign lcd_base_clock = clk_33;
assign top_clk_to_offchip_video = lcd_clock;
assign top_HC_HD = h_sync;
assign top_HC_VD = v_sync;
assign top_CDn_to_the_el_camino_sd_card_controller = 1'b0;
assign top_WP_to_the_el_camino_sd_card_controller = 1'b0;
assign top_HC_SCEN = top_out_port_from_the_lcd_i2c_en;
assign top_HC_ADC_DCLK = ~top_out_port_from_the_lcd_i2c_en ? top_out_port_from_the_lcd_i2c_scl: 0;
assign top_HC_GREST = 1'b1;
assign top_led = led_pio_wire;
assign top_HC_ETH_RESET_N = 1'b0;
assign top_in_port_to_the_button_pio = top_button;
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_nios2_qsys_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEV",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEV",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Implements a fixed-point parameterized pipelined square root
// operation on an unsigned input of any bit length. The number of
// stages in the pipeline is equal to the number of output bits in the
// computation. This pipelien sustains a throughput of one computation
// per clock cycle.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module sqrt_pipelined
(
input clk, // clock
input reset_n, // asynchronous reset
input start, // optional start signal
input [INPUT_BITS-1:0] radicand, // unsigned radicand
output reg data_valid, // optional data valid signal
output reg [OUTPUT_BITS-1:0] root // unsigned root
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
INPUT_BITS = 16; // number of input bits (any integer)
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits
reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation
reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values
reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values
wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values
// This is the first stage of the pipeline.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
start_gen[0] <= 0;
radicand_gen[INPUT_BITS-1:0] <= 0;
root_gen[INPUT_BITS-1:0] <= 0;
end
else begin
start_gen[0] <= start;
if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin
radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];
root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];
end
else begin
radicand_gen[INPUT_BITS-1:0] <= radicand;
root_gen[INPUT_BITS-1:0] <= 0;
end
end
end
// Main generate loop to create the masks and pipeline stages.
generate
genvar i;
// Generate all the mask values. These are built up in the
// following fashion:
// LAST MASK: 0x00...001
// 0x00...004 Increasing # OUTPUT_BITS
// 0x00...010 |
// 0x00...040 v
// ...
// FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS
//
// Note that the first mask used can either be of the 0x1... or
// 0x4... variety. This is purely determined by the number of
// computation stages. However, the last mask used will always be
// 0x1 and the second to last mask used will always be 0x4.
for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4
if (i % 2) // i is odd, this is a 4 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);
else // i is even, this is a 1 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);
end
// Generate all the pipeline stages to compute the square root of
// the input radicand stream. The general approach is to compare
// the current values of the root plus the mask to the
// radicand. If root/mask sum is greater than the radicand,
// subtract the mask and the root from the radicand and store the
// radicand for the next stage. Additionally, the root is
// increased by the value of the mask and stored for the next
// stage. If this test fails, then the radicand and the root
// retain their value through to the next stage. The one weird
// thing is that the mask indices appear to be incremented by one
// additional position. This is not the case, however, because the
// first mask is used in the first stage (always block after the
// generate statement).
for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline
always @ (posedge clk or negedge reset_n) begin : pipeline_stage
if (!reset_n) begin
start_gen[i+1] <= 0;
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
end
else begin
start_gen[i+1] <= start_gen[i];
if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] -
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] -
root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];
end
else begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;
end
end
end
end
endgenerate
// This is the final stage which just implements a rounding
// operation. This stage could be tacked on as a combinational logic
// stage, but who cares about latency, anyway? This is NOT a true
// rounding stage. In order to add convergent rounding, you need to
// increase the input bit width by 2 (increase the number of
// pipeline stages by 1) and implement rounding in the module that
// instantiates this one.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
data_valid <= 0;
root <= 0;
end
else begin
data_valid <= start_gen[OUTPUT_BITS-1];
if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;
else
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];
end
end
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_Sys_Timer (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_interrupt_enable;
reg control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 16: 0] counter_load_value;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 16: 0] internal_counter;
wire irq;
wire period_h_wr_strobe;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire status_wr_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 17'h1869F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = 17'h1869F;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = 1;
assign do_stop_counter = 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[0];
end
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
// Component : VexRiscv
// Git hash : 7921edb2cddbc3b048c85c03554d299ad3111bec
`define Input2Kind_binary_sequential_type [0:0]
`define Input2Kind_binary_sequential_RS 1'b0
`define Input2Kind_binary_sequential_IMM_I 1'b1
`define EnvCtrlEnum_binary_sequential_type [1:0]
`define EnvCtrlEnum_binary_sequential_NONE 2'b00
`define EnvCtrlEnum_binary_sequential_XRET 2'b01
`define EnvCtrlEnum_binary_sequential_WFI 2'b10
`define EnvCtrlEnum_binary_sequential_ECALL 2'b11
`define BranchCtrlEnum_binary_sequential_type [1:0]
`define BranchCtrlEnum_binary_sequential_INC 2'b00
`define BranchCtrlEnum_binary_sequential_B 2'b01
`define BranchCtrlEnum_binary_sequential_JAL 2'b10
`define BranchCtrlEnum_binary_sequential_JALR 2'b11
`define ShiftCtrlEnum_binary_sequential_type [1:0]
`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00
`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01
`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10
`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11
`define AluBitwiseCtrlEnum_binary_sequential_type [1:0]
`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00
`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01
`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10
`define Src2CtrlEnum_binary_sequential_type [1:0]
`define Src2CtrlEnum_binary_sequential_RS 2'b00
`define Src2CtrlEnum_binary_sequential_IMI 2'b01
`define Src2CtrlEnum_binary_sequential_IMS 2'b10
`define Src2CtrlEnum_binary_sequential_PC 2'b11
`define AluCtrlEnum_binary_sequential_type [1:0]
`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00
`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01
`define AluCtrlEnum_binary_sequential_BITWISE 2'b10
`define Src1CtrlEnum_binary_sequential_type [1:0]
`define Src1CtrlEnum_binary_sequential_RS 2'b00
`define Src1CtrlEnum_binary_sequential_IMU 2'b01
`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10
`define Src1CtrlEnum_binary_sequential_URS1 2'b11
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
output CfuPlugin_bus_cmd_valid,
input CfuPlugin_bus_cmd_ready,
output [9:0] CfuPlugin_bus_cmd_payload_function_id,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_0,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_1,
input CfuPlugin_bus_rsp_valid,
output CfuPlugin_bus_rsp_ready,
input [31:0] CfuPlugin_bus_rsp_payload_outputs_0,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [2:0] iBusWishbone_CTI,
output [1:0] iBusWishbone_BTE,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [2:0] dBusWishbone_CTI,
output [1:0] dBusWishbone_BTE,
input clk,
input reset
);
wire IBusCachedPlugin_cache_io_flush;
wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck;
wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved;
wire IBusCachedPlugin_cache_io_cpu_decode_isValid;
wire IBusCachedPlugin_cache_io_cpu_decode_isStuck;
wire IBusCachedPlugin_cache_io_cpu_decode_isUser;
reg IBusCachedPlugin_cache_io_cpu_fill_valid;
wire dataCache_1_io_cpu_execute_isValid;
wire [31:0] dataCache_1_io_cpu_execute_address;
wire dataCache_1_io_cpu_memory_isValid;
wire [31:0] dataCache_1_io_cpu_memory_address;
reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess;
reg dataCache_1_io_cpu_writeBack_isValid;
wire dataCache_1_io_cpu_writeBack_isUser;
wire [31:0] dataCache_1_io_cpu_writeBack_storeData;
wire [31:0] dataCache_1_io_cpu_writeBack_address;
wire dataCache_1_io_cpu_writeBack_fence_SW;
wire dataCache_1_io_cpu_writeBack_fence_SR;
wire dataCache_1_io_cpu_writeBack_fence_SO;
wire dataCache_1_io_cpu_writeBack_fence_SI;
wire dataCache_1_io_cpu_writeBack_fence_PW;
wire dataCache_1_io_cpu_writeBack_fence_PR;
wire dataCache_1_io_cpu_writeBack_fence_PO;
wire dataCache_1_io_cpu_writeBack_fence_PI;
wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM;
wire dataCache_1_io_cpu_flush_valid;
wire dataCache_1_io_mem_cmd_ready;
reg [31:0] _zz_RegFilePlugin_regFile_port0;
reg [31:0] _zz_RegFilePlugin_regFile_port1;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire dataCache_1_io_cpu_execute_haltIt;
wire dataCache_1_io_cpu_execute_refilling;
wire dataCache_1_io_cpu_memory_isWrite;
wire dataCache_1_io_cpu_writeBack_haltIt;
wire [31:0] dataCache_1_io_cpu_writeBack_data;
wire dataCache_1_io_cpu_writeBack_mmuException;
wire dataCache_1_io_cpu_writeBack_unalignedAccess;
wire dataCache_1_io_cpu_writeBack_accessError;
wire dataCache_1_io_cpu_writeBack_isWrite;
wire dataCache_1_io_cpu_writeBack_keepMemRspData;
wire dataCache_1_io_cpu_writeBack_exclusiveOk;
wire dataCache_1_io_cpu_flush_ready;
wire dataCache_1_io_cpu_redo;
wire dataCache_1_io_mem_cmd_valid;
wire dataCache_1_io_mem_cmd_payload_wr;
wire dataCache_1_io_mem_cmd_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_payload_mask;
wire [1:0] dataCache_1_io_mem_cmd_payload_size;
wire dataCache_1_io_mem_cmd_payload_last;
wire [51:0] _zz_memory_MUL_LOW;
wire [51:0] _zz_memory_MUL_LOW_1;
wire [51:0] _zz_memory_MUL_LOW_2;
wire [51:0] _zz_memory_MUL_LOW_3;
wire [32:0] _zz_memory_MUL_LOW_4;
wire [51:0] _zz_memory_MUL_LOW_5;
wire [49:0] _zz_memory_MUL_LOW_6;
wire [51:0] _zz_memory_MUL_LOW_7;
wire [49:0] _zz_memory_MUL_LOW_8;
wire [31:0] _zz_execute_SHIFT_RIGHT;
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2;
wire _zz_decode_LEGAL_INSTRUCTION_3;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4;
wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8;
wire _zz_decode_LEGAL_INSTRUCTION_9;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10;
wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14;
wire _zz_decode_LEGAL_INSTRUCTION_15;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16;
wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17;
wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1;
reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6;
wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc;
wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1;
wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2;
wire [19:0] _zz__zz_2;
wire [11:0] _zz__zz_4;
wire [31:0] _zz__zz_6;
wire [31:0] _zz__zz_6_1;
wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload;
wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted;
wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2;
wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6;
wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18;
wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33;
wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45;
wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68;
wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100;
wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125;
wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138;
wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166;
wire _zz_RegFilePlugin_regFile_port;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_RegFilePlugin_regFile_port_1;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA;
wire [2:0] _zz__zz_execute_SRC1;
wire [4:0] _zz__zz_execute_SRC1_1;
wire [11:0] _zz__zz_execute_SRC2_3;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_1;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire [31:0] _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_BranchPlugin_branch_src2_7;
wire _zz_execute_BranchPlugin_branch_src2_8;
wire [2:0] _zz_execute_BranchPlugin_branch_src2_9;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1;
wire _zz_when;
wire _zz_when_1;
wire [65:0] _zz_writeBack_MulPlugin_result;
wire [65:0] _zz_writeBack_MulPlugin_result_1;
wire [31:0] _zz__zz_decode_RS2_2;
wire [31:0] _zz__zz_decode_RS2_2_1;
wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext;
wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator;
wire [32:0] _zz_memory_DivPlugin_div_result_1;
wire [32:0] _zz_memory_DivPlugin_div_result_2;
wire [32:0] _zz_memory_DivPlugin_div_result_3;
wire [32:0] _zz_memory_DivPlugin_div_result_4;
wire [0:0] _zz_memory_DivPlugin_div_result_5;
wire [32:0] _zz_memory_DivPlugin_rs1_2;
wire [0:0] _zz_memory_DivPlugin_rs1_3;
wire [31:0] _zz_memory_DivPlugin_rs2_1;
wire [0:0] _zz_memory_DivPlugin_rs2_2;
wire [9:0] _zz_execute_CfuPlugin_functionsIds_0;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25;
wire [26:0] _zz_iBusWishbone_ADR_1;
wire [51:0] memory_MUL_LOW;
wire writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire execute_CfuPlugin_CFU_IN_FLIGHT;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire [33:0] execute_MUL_HL;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire [31:0] execute_SHIFT_RIGHT;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [31:0] memory_MEMORY_STORE_DATA_RF;
wire [31:0] execute_MEMORY_STORE_DATA_RF;
wire decode_CSR_READ_OPCODE;
wire decode_CSR_WRITE_OPCODE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_SRC2_FORCE_ZERO;
wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
wire decode_CfuPlugin_CFU_ENABLE;
wire decode_IS_RS2_SIGNED;
wire decode_IS_RS1_SIGNED;
wire decode_IS_DIV;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1;
wire decode_IS_CSR;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire decode_SRC_LESS_UNSIGNED;
wire decode_MEMORY_MANAGMENT;
wire memory_MEMORY_WR;
wire decode_MEMORY_WR;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1;
wire decode_MEMORY_FORCE_CONSTISTENCY;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] memory_PC;
reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire memory_CfuPlugin_CFU_IN_FLIGHT;
wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire execute_CfuPlugin_CFU_ENABLE;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
(* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL;
wire decode_RS2_USE;
wire decode_RS1_USE;
reg [31:0] _zz_decode_RS2;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] memory_SHIFT_RIGHT;
reg [31:0] _zz_decode_RS2_1;
wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_execute_SRC2;
wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL;
wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL;
wire [31:0] _zz_lastStageRegFileWrite_payload_address;
wire _zz_lastStageRegFileWrite_valid;
reg _zz_1;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1;
reg [31:0] _zz_decode_RS2_2;
wire writeBack_MEMORY_WR;
wire [31:0] writeBack_MEMORY_STORE_DATA_RF;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire writeBack_MEMORY_ENABLE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_ENABLE;
wire execute_MEMORY_FORCE_CONSTISTENCY;
wire execute_MEMORY_MANAGMENT;
(* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ;
wire execute_MEMORY_WR;
wire [31:0] execute_SRC_ADD;
wire execute_MEMORY_ENABLE;
wire [31:0] execute_INSTRUCTION;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected_4;
reg IBusCachedPlugin_rsp_issueDetected_3;
reg IBusCachedPlugin_rsp_issueDetected_2;
reg IBusCachedPlugin_rsp_issueDetected_1;
wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT;
wire [31:0] decode_PC;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
wire decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
reg execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
reg writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
reg writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_0_isValid;
wire IBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_isPaging;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire dBus_cmd_payload_uncached;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [3:0] dBus_cmd_payload_mask;
wire [1:0] dBus_cmd_payload_size;
wire dBus_cmd_payload_last;
wire dBus_rsp_valid;
wire dBus_rsp_payload_last;
wire [31:0] dBus_rsp_payload_data;
wire dBus_rsp_payload_error;
wire DBusCachedPlugin_mmuBus_cmd_0_isValid;
wire DBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire DBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire DBusCachedPlugin_mmuBus_rsp_isPaging;
wire DBusCachedPlugin_mmuBus_rsp_allowRead;
wire DBusCachedPlugin_mmuBus_rsp_allowWrite;
wire DBusCachedPlugin_mmuBus_rsp_allowExecute;
wire DBusCachedPlugin_mmuBus_rsp_exception;
wire DBusCachedPlugin_mmuBus_rsp_refilling;
wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire DBusCachedPlugin_mmuBus_end;
wire DBusCachedPlugin_mmuBus_busy;
reg DBusCachedPlugin_redoBranch_valid;
wire [31:0] DBusCachedPlugin_redoBranch_payload;
reg DBusCachedPlugin_exceptionBus_valid;
reg [3:0] DBusCachedPlugin_exceptionBus_payload_code;
wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
reg BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
wire [31:0] CsrPlugin_csrMapping_readDataSignal;
wire [31:0] CsrPlugin_csrMapping_readDataInit;
wire [31:0] CsrPlugin_csrMapping_writeDataSignal;
wire CsrPlugin_csrMapping_allowCsrSignal;
wire CsrPlugin_csrMapping_hazardFree;
reg CsrPlugin_inWfi /* verilator public */ ;
wire CsrPlugin_thirdPartyWake;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
wire CsrPlugin_forceMachineWire;
reg CsrPlugin_selfException_valid;
reg [3:0] CsrPlugin_selfException_payload_code;
wire [31:0] CsrPlugin_selfException_payload_badAddr;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_allowException;
wire CsrPlugin_allowEbreakException;
wire IBusCachedPlugin_externalFlush;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_correction;
reg IBusCachedPlugin_fetchPc_correctionReg;
wire IBusCachedPlugin_fetchPc_output_fire;
wire IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
wire when_Fetcher_l131;
wire IBusCachedPlugin_fetchPc_output_fire_1;
wire when_Fetcher_l131_1;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_fetchPc_redo_valid;
wire [31:0] IBusCachedPlugin_fetchPc_redo_payload;
reg IBusCachedPlugin_fetchPc_flushed;
wire when_Fetcher_l158;
reg IBusCachedPlugin_iBusRsp_redoFetch;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_2_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_2_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_2_halt;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire IBusCachedPlugin_iBusRsp_flush;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_output_valid;
wire IBusCachedPlugin_iBusRsp_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc;
wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_output_payload_isRvc;
wire when_Fetcher_l240;
wire when_Fetcher_l320;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
wire when_Fetcher_l329;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
wire when_Fetcher_l329_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
wire when_Fetcher_l329_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
wire when_Fetcher_l329_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
wire when_Fetcher_l329_4;
wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1;
wire _zz_2;
reg [10:0] _zz_3;
wire _zz_4;
reg [18:0] _zz_5;
reg _zz_6;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload;
reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_IBusCachedPlugin_rspCounter;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
wire IBusCachedPlugin_rsp_issueDetected;
reg IBusCachedPlugin_rsp_redoFetch;
wire when_IBusCachedPlugin_l239;
wire when_IBusCachedPlugin_l244;
wire when_IBusCachedPlugin_l250;
wire when_IBusCachedPlugin_l256;
wire when_IBusCachedPlugin_l267;
wire dataCache_1_io_mem_cmd_s2mPipe_valid;
reg dataCache_1_io_mem_cmd_s2mPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
wire [1:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_last;
reg dataCache_1_io_mem_cmd_rValid;
reg dataCache_1_io_mem_cmd_rData_wr;
reg dataCache_1_io_mem_cmd_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_rData_mask;
reg [1:0] dataCache_1_io_mem_cmd_rData_size;
reg dataCache_1_io_mem_cmd_rData_last;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
wire [1:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
reg dataCache_1_io_mem_cmd_s2mPipe_rValid;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
reg [1:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_last;
wire when_Stream_l342;
wire [31:0] _zz_DBusCachedPlugin_rspCounter;
reg [31:0] DBusCachedPlugin_rspCounter;
wire when_DBusCachedPlugin_l303;
wire [1:0] execute_DBusCachedPlugin_size;
reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF;
wire dataCache_1_io_cpu_flush_isStall;
wire when_DBusCachedPlugin_l343;
wire when_DBusCachedPlugin_l359;
wire when_DBusCachedPlugin_l386;
wire when_DBusCachedPlugin_l438;
wire when_DBusCachedPlugin_l458;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3;
reg [31:0] writeBack_DBusCachedPlugin_rspShifted;
wire [31:0] writeBack_DBusCachedPlugin_rspRf;
wire [1:0] switch_Misc_l200;
wire _zz_writeBack_DBusCachedPlugin_rspFormated;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1;
wire _zz_writeBack_DBusCachedPlugin_rspFormated_2;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3;
reg [31:0] writeBack_DBusCachedPlugin_rspFormated;
wire when_DBusCachedPlugin_l484;
wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
wire when_RegFilePlugin_l63;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_7;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_execute_REGFILE_WRITE_DATA;
reg [31:0] _zz_execute_SRC1;
wire _zz_execute_SRC2_1;
reg [19:0] _zz_execute_SRC2_2;
wire _zz_execute_SRC2_3;
reg [19:0] _zz_execute_SRC2_4;
reg [31:0] _zz_execute_SRC2_5;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_decode_RS2_3;
reg HazardSimplePlugin_src0Hazard;
reg HazardSimplePlugin_src1Hazard;
wire HazardSimplePlugin_writeBackWrites_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
reg HazardSimplePlugin_writeBackBuffer_valid;
reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire when_HazardSimplePlugin_l47;
wire when_HazardSimplePlugin_l48;
wire when_HazardSimplePlugin_l51;
wire when_HazardSimplePlugin_l45;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l48_1;
wire when_HazardSimplePlugin_l51_1;
wire when_HazardSimplePlugin_l45_1;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l48_2;
wire when_HazardSimplePlugin_l51_2;
wire when_HazardSimplePlugin_l45_2;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l105;
wire when_HazardSimplePlugin_l108;
wire when_HazardSimplePlugin_l113;
wire execute_BranchPlugin_eq;
wire [2:0] switch_Misc_l200_1;
reg _zz_execute_BRANCH_COND_RESULT;
reg _zz_execute_BRANCH_COND_RESULT_1;
wire _zz_execute_BranchPlugin_missAlignedTarget;
reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1;
wire _zz_execute_BranchPlugin_missAlignedTarget_2;
reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3;
wire _zz_execute_BranchPlugin_missAlignedTarget_4;
reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5;
reg _zz_execute_BranchPlugin_missAlignedTarget_6;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_execute_BranchPlugin_branch_src2;
reg [19:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
reg [10:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
reg [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] execute_BranchPlugin_branchAdder;
wire when_BranchPlugin_l296;
reg [1:0] CsrPlugin_misa_base;
reg [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg [31:0] CsrPlugin_mscratch;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_when_CsrPlugin_l952;
wire _zz_when_CsrPlugin_l952_1;
wire _zz_when_CsrPlugin_l952_2;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire when_CsrPlugin_l909;
wire when_CsrPlugin_l909_1;
wire when_CsrPlugin_l909_2;
wire when_CsrPlugin_l909_3;
wire when_CsrPlugin_l922;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire when_CsrPlugin_l946;
wire when_CsrPlugin_l952;
wire when_CsrPlugin_l952_1;
wire when_CsrPlugin_l952_2;
wire CsrPlugin_exception;
reg CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_pcValids_0;
reg CsrPlugin_pipelineLiberator_pcValids_1;
reg CsrPlugin_pipelineLiberator_pcValids_2;
wire CsrPlugin_pipelineLiberator_active;
wire when_CsrPlugin_l980;
wire when_CsrPlugin_l980_1;
wire when_CsrPlugin_l980_2;
wire when_CsrPlugin_l985;
reg CsrPlugin_pipelineLiberator_done;
wire when_CsrPlugin_l991;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException /* verilator public */ ;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire when_CsrPlugin_l1019;
wire when_CsrPlugin_l1064;
wire [1:0] switch_CsrPlugin_l1068;
reg execute_CsrPlugin_wfiWake;
wire when_CsrPlugin_l1108;
wire when_CsrPlugin_l1110;
wire when_CsrPlugin_l1116;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
wire when_CsrPlugin_l1129;
wire when_CsrPlugin_l1136;
wire when_CsrPlugin_l1137;
wire when_CsrPlugin_l1144;
reg execute_CsrPlugin_writeInstruction;
reg execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
wire switch_Misc_l200_2;
reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal;
wire when_CsrPlugin_l1176;
wire when_CsrPlugin_l1180;
wire [11:0] execute_CsrPlugin_csrAddress;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [1:0] switch_MulPlugin_l87;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
wire when_MulPlugin_l147;
wire [1:0] switch_MulPlugin_l148;
reg [32:0] memory_DivPlugin_rs1;
reg [31:0] memory_DivPlugin_rs2;
reg [64:0] memory_DivPlugin_accumulator;
wire memory_DivPlugin_frontendOk;
reg memory_DivPlugin_div_needRevert;
reg memory_DivPlugin_div_counter_willIncrement;
reg memory_DivPlugin_div_counter_willClear;
reg [5:0] memory_DivPlugin_div_counter_valueNext;
reg [5:0] memory_DivPlugin_div_counter_value;
wire memory_DivPlugin_div_counter_willOverflowIfInc;
wire memory_DivPlugin_div_counter_willOverflow;
reg memory_DivPlugin_div_done;
wire when_MulDivIterativePlugin_l126;
wire when_MulDivIterativePlugin_l126_1;
reg [31:0] memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l128;
wire when_MulDivIterativePlugin_l129;
wire when_MulDivIterativePlugin_l132;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] memory_DivPlugin_div_stage_0_outNumerator;
wire when_MulDivIterativePlugin_l151;
wire [31:0] _zz_memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l162;
wire _zz_memory_DivPlugin_rs2;
wire _zz_memory_DivPlugin_rs1;
reg [32:0] _zz_memory_DivPlugin_rs1_1;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1;
wire execute_CfuPlugin_schedule;
reg execute_CfuPlugin_hold;
reg execute_CfuPlugin_fired;
wire CfuPlugin_bus_cmd_fire;
wire when_CfuPlugin_l171;
wire when_CfuPlugin_l175;
wire [9:0] execute_CfuPlugin_functionsIds_0;
wire _zz_CfuPlugin_bus_cmd_payload_inputs_1;
reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1;
reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
wire CfuPlugin_bus_rsp_rsp_valid;
reg CfuPlugin_bus_rsp_rsp_ready;
wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0;
reg CfuPlugin_bus_rsp_rValid;
reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0;
wire when_CfuPlugin_l208;
wire when_Pipeline_l124;
reg [31:0] decode_to_execute_PC;
wire when_Pipeline_l124_1;
reg [31:0] execute_to_memory_PC;
wire when_Pipeline_l124_2;
reg [31:0] memory_to_writeBack_PC;
wire when_Pipeline_l124_3;
reg [31:0] decode_to_execute_INSTRUCTION;
wire when_Pipeline_l124_4;
reg [31:0] execute_to_memory_INSTRUCTION;
wire when_Pipeline_l124_5;
reg [31:0] memory_to_writeBack_INSTRUCTION;
wire when_Pipeline_l124_6;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
wire when_Pipeline_l124_7;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
wire when_Pipeline_l124_8;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
wire when_Pipeline_l124_9;
reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
wire when_Pipeline_l124_10;
reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL;
wire when_Pipeline_l124_11;
reg decode_to_execute_SRC_USE_SUB_LESS;
wire when_Pipeline_l124_12;
reg decode_to_execute_MEMORY_ENABLE;
wire when_Pipeline_l124_13;
reg execute_to_memory_MEMORY_ENABLE;
wire when_Pipeline_l124_14;
reg memory_to_writeBack_MEMORY_ENABLE;
wire when_Pipeline_l124_15;
reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL;
wire when_Pipeline_l124_16;
reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL;
wire when_Pipeline_l124_17;
reg decode_to_execute_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_18;
reg execute_to_memory_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_19;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_20;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
wire when_Pipeline_l124_21;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_22;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_23;
reg decode_to_execute_MEMORY_WR;
wire when_Pipeline_l124_24;
reg execute_to_memory_MEMORY_WR;
wire when_Pipeline_l124_25;
reg memory_to_writeBack_MEMORY_WR;
wire when_Pipeline_l124_26;
reg decode_to_execute_MEMORY_MANAGMENT;
wire when_Pipeline_l124_27;
reg decode_to_execute_SRC_LESS_UNSIGNED;
wire when_Pipeline_l124_28;
reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL;
wire when_Pipeline_l124_29;
reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL;
wire when_Pipeline_l124_30;
reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL;
wire when_Pipeline_l124_31;
reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL;
wire when_Pipeline_l124_32;
reg decode_to_execute_IS_CSR;
wire when_Pipeline_l124_33;
reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL;
wire when_Pipeline_l124_34;
reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL;
wire when_Pipeline_l124_35;
reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL;
wire when_Pipeline_l124_36;
reg decode_to_execute_IS_MUL;
wire when_Pipeline_l124_37;
reg execute_to_memory_IS_MUL;
wire when_Pipeline_l124_38;
reg memory_to_writeBack_IS_MUL;
wire when_Pipeline_l124_39;
reg decode_to_execute_IS_DIV;
wire when_Pipeline_l124_40;
reg execute_to_memory_IS_DIV;
wire when_Pipeline_l124_41;
reg decode_to_execute_IS_RS1_SIGNED;
wire when_Pipeline_l124_42;
reg decode_to_execute_IS_RS2_SIGNED;
wire when_Pipeline_l124_43;
reg decode_to_execute_CfuPlugin_CFU_ENABLE;
wire when_Pipeline_l124_44;
reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire when_Pipeline_l124_45;
reg [31:0] decode_to_execute_RS1;
wire when_Pipeline_l124_46;
reg [31:0] decode_to_execute_RS2;
wire when_Pipeline_l124_47;
reg decode_to_execute_SRC2_FORCE_ZERO;
wire when_Pipeline_l124_48;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
wire when_Pipeline_l124_49;
reg decode_to_execute_CSR_WRITE_OPCODE;
wire when_Pipeline_l124_50;
reg decode_to_execute_CSR_READ_OPCODE;
wire when_Pipeline_l124_51;
reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_52;
reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_53;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_54;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_55;
reg [31:0] execute_to_memory_SHIFT_RIGHT;
wire when_Pipeline_l124_56;
reg [31:0] execute_to_memory_MUL_LL;
wire when_Pipeline_l124_57;
reg [33:0] execute_to_memory_MUL_LH;
wire when_Pipeline_l124_58;
reg [33:0] execute_to_memory_MUL_HL;
wire when_Pipeline_l124_59;
reg [33:0] execute_to_memory_MUL_HH;
wire when_Pipeline_l124_60;
reg [33:0] memory_to_writeBack_MUL_HH;
wire when_Pipeline_l124_61;
reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_62;
reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_63;
reg [51:0] memory_to_writeBack_MUL_LOW;
wire when_Pipeline_l151;
wire when_Pipeline_l154;
wire when_Pipeline_l151_1;
wire when_Pipeline_l154_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154_2;
wire when_CsrPlugin_l1264;
reg execute_CsrPlugin_csr_3264;
wire when_CsrPlugin_l1264_1;
reg execute_CsrPlugin_csr_3857;
wire when_CsrPlugin_l1264_2;
reg execute_CsrPlugin_csr_3858;
wire when_CsrPlugin_l1264_3;
reg execute_CsrPlugin_csr_3859;
wire when_CsrPlugin_l1264_4;
reg execute_CsrPlugin_csr_3860;
wire when_CsrPlugin_l1264_5;
reg execute_CsrPlugin_csr_769;
wire when_CsrPlugin_l1264_6;
reg execute_CsrPlugin_csr_768;
wire when_CsrPlugin_l1264_7;
reg execute_CsrPlugin_csr_836;
wire when_CsrPlugin_l1264_8;
reg execute_CsrPlugin_csr_772;
wire when_CsrPlugin_l1264_9;
reg execute_CsrPlugin_csr_773;
wire when_CsrPlugin_l1264_10;
reg execute_CsrPlugin_csr_833;
wire when_CsrPlugin_l1264_11;
reg execute_CsrPlugin_csr_832;
wire when_CsrPlugin_l1264_12;
reg execute_CsrPlugin_csr_834;
wire when_CsrPlugin_l1264_13;
reg execute_CsrPlugin_csr_835;
wire when_CsrPlugin_l1264_14;
reg execute_CsrPlugin_csr_2816;
wire when_CsrPlugin_l1264_15;
reg execute_CsrPlugin_csr_2944;
wire when_CsrPlugin_l1264_16;
reg execute_CsrPlugin_csr_2818;
wire when_CsrPlugin_l1264_17;
reg execute_CsrPlugin_csr_2946;
wire when_CsrPlugin_l1264_18;
reg execute_CsrPlugin_csr_3072;
wire when_CsrPlugin_l1264_19;
reg execute_CsrPlugin_csr_3200;
wire when_CsrPlugin_l1264_20;
reg execute_CsrPlugin_csr_3074;
wire when_CsrPlugin_l1264_21;
reg execute_CsrPlugin_csr_3202;
wire when_CsrPlugin_l1264_22;
reg execute_CsrPlugin_csr_3008;
wire when_CsrPlugin_l1264_23;
reg execute_CsrPlugin_csr_4032;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24;
wire when_CsrPlugin_l1297;
wire when_CsrPlugin_l1302;
reg [2:0] _zz_iBusWishbone_ADR;
wire when_InstructionCache_l239;
reg _zz_iBus_rsp_valid;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
reg [0:0] _zz_dBus_cmd_ready;
wire _zz_dBus_cmd_ready_1;
wire _zz_dBus_cmd_ready_2;
wire _zz_dBus_cmd_ready_3;
wire _zz_dBus_cmd_ready_4;
wire _zz_dBus_cmd_ready_5;
reg _zz_dBus_rsp_valid;
reg [31:0] dBusWishbone_DAT_MISO_regNext;
`ifndef SYNTHESIS
reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string;
reg [39:0] decode_ENV_CTRL_string;
reg [39:0] _zz_decode_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_decode_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string;
reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] memory_ENV_CTRL_string;
reg [39:0] _zz_memory_ENV_CTRL_string;
reg [39:0] execute_ENV_CTRL_string;
reg [39:0] _zz_execute_ENV_CTRL_string;
reg [39:0] writeBack_ENV_CTRL_string;
reg [39:0] _zz_writeBack_ENV_CTRL_string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_execute_BRANCH_CTRL_string;
reg [71:0] memory_SHIFT_CTRL_string;
reg [71:0] _zz_memory_SHIFT_CTRL_string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_execute_SHIFT_CTRL_string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_execute_SRC2_CTRL_string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_execute_SRC1_CTRL_string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_execute_ALU_CTRL_string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_decode_ENV_CTRL_1_string;
reg [31:0] _zz_decode_BRANCH_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_1_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;
reg [23:0] _zz_decode_SRC2_CTRL_1_string;
reg [63:0] _zz_decode_ALU_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_1_string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_2_string;
reg [63:0] _zz_decode_ALU_CTRL_2_string;
reg [23:0] _zz_decode_SRC2_CTRL_2_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;
reg [71:0] _zz_decode_SHIFT_CTRL_2_string;
reg [31:0] _zz_decode_BRANCH_CTRL_2_string;
reg [39:0] _zz_decode_ENV_CTRL_2_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [71:0] execute_to_memory_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [39:0] decode_to_execute_ENV_CTRL_string;
reg [39:0] execute_to_memory_ENV_CTRL_string;
reg [39:0] memory_to_writeBack_ENV_CTRL_string;
reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00);
assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00);
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
assign _zz_memory_MUL_LOW_2 = 52'h0;
assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL};
assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4};
assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001);
assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00};
assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1};
assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101);
assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100);
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_execute_SRC1 = 3'b100;
assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15];
assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));
assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));
assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);
assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;
assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100;
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01);
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01);
assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0];
assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32];
assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement;
assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1};
assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2};
assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])};
assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2;
assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3;
assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4);
assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert;
assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5};
assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1;
assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3};
assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2;
assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2};
assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]};
assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5);
assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3};
assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0];
assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1];
assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f;
assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f);
assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073;
assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073);
assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063);
assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f;
assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f);
assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003;
assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063);
assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f);
assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f;
assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f);
assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013;
assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033);
assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033);
assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}};
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7];
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h00203050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h00403050) == 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00002040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79}} != 6'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00002040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00001040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h00001040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75) == 32'h00000008);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = 6'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = (decode_INSTRUCTION & 32'h00400040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = (decode_INSTRUCTION & 32'h00000038);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = 32'h00000008;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = (decode_INSTRUCTION & 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = (decode_INSTRUCTION & 32'h00004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = 32'h00004020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85) == 32'h00000010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h00002030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = (decode_INSTRUCTION & 32'h00001030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98) == 32'h00002020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00001010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = (decode_INSTRUCTION & 32'h00000070);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129) == 32'h00004010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139} != 4'b0000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = 32'h00000030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h02000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = 32'h02002060;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02003020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = 32'h00004014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (decode_INSTRUCTION & 32'h00006014);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = 32'h00000044;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = (decode_INSTRUCTION & 32'h00000018);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00000058;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h40000030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165) == 32'h00001004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = 32'h00002014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h40000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 32'h00000014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = (decode_INSTRUCTION & 32'h00000044);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = 32'h00000004;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 32'h00005054;
assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7];
assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0;
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs1Data) begin
_zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs2Data) begin
_zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(posedge clk) begin
if(_zz_1) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush (IBusCachedPlugin_cache_io_flush ), //i
.io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i
.io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o
.io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i
.io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i
.io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i
.io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i
.io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i
.io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o
.io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i
.io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o
.io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i
.io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i
.io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i
.io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o
.io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o
.io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o
.io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o
.io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o
.io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o
.io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i
.io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i
.io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i
.io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (iBus_cmd_ready ), //i
.io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o
.io_mem_rsp_valid (iBus_rsp_valid ), //i
.io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
DataCache dataCache_1 (
.io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i
.io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i
.io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o
.io_cpu_execute_args_wr (execute_MEMORY_WR ), //i
.io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i
.io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i
.io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o
.io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i
.io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i
.io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o
.io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i
.io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i
.io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i
.io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i
.io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i
.io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o
.io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o
.io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i
.io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o
.io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i
.io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o
.io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o
.io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o
.io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o
.io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i
.io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i
.io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i
.io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i
.io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i
.io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i
.io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i
.io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i
.io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i
.io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o
.io_cpu_redo (dataCache_1_io_cpu_redo ), //o
.io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i
.io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o
.io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i
.io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o
.io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o
.io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o
.io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o
.io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o
.io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o
.io_mem_rsp_valid (dBus_rsp_valid ), //i
.io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i
.io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
always @(*) begin
case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6)
2'b00 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload;
end
2'b01 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload;
end
2'b10 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload;
end
default : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_1)
2'b00 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0;
end
2'b01 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1;
end
2'b10 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_3)
1'b0 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL";
default : decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL";
default : _zz_decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC ";
default : _zz_decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL";
default : memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL";
default : _zz_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL";
default : execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL";
default : _zz_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL";
default : writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR";
default : _zz_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 ";
default : memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC ";
default : _zz_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR";
default : _zz_decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_2)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_2_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_2)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_2_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_2)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC ";
default : _zz_decode_SRC2_CTRL_2_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_2)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_2)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_2_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_2)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR";
default : _zz_decode_BRANCH_CTRL_2_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_2)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL";
default : _zz_decode_ENV_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
default : decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
default : execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
`endif
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired);
assign memory_MUL_HH = execute_to_memory_MUL_HH;
assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow));
assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow);
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF;
assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF;
assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20);
assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0))));
assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32];
assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31];
assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30];
assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29];
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28];
assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1;
assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1;
assign decode_ENV_CTRL = _zz_decode_ENV_CTRL;
assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1;
assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25];
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1;
assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1;
assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1;
assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17];
assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16];
assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR;
assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13];
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12];
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11];
assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1;
assign decode_ALU_CTRL = _zz_decode_ALU_CTRL;
assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1;
assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL;
assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1;
assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004);
assign memory_PC = execute_to_memory_PC;
always @(*) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT;
if(memory_arbitration_isStuck) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
always @(*) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT;
if(execute_arbitration_isStuck) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL;
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH;
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW;
assign memory_MUL_HL = execute_to_memory_MUL_HL;
assign memory_MUL_LH = execute_to_memory_MUL_LH;
assign memory_MUL_LL = execute_to_memory_MUL_LL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_memory_ENV_CTRL;
assign execute_ENV_CTRL = _zz_execute_ENV_CTRL;
assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL;
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1;
assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL;
assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15];
assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5];
always @(*) begin
_zz_decode_RS2 = execute_REGFILE_WRITE_DATA;
if(when_CsrPlugin_l1176) begin
_zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal;
end
end
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @(*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr1Match) begin
decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l51) begin
decode_RS2 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l51_1) begin
decode_RS2 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l51_2) begin
decode_RS2 = _zz_decode_RS2;
end
end
end
end
always @(*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr0Match) begin
decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l48) begin
decode_RS1 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l48_1) begin
decode_RS1 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l48_2) begin
decode_RS1 = _zz_decode_RS2;
end
end
end
end
assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;
always @(*) begin
_zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA;
if(memory_arbitration_isValid) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_SLL_1 : begin
_zz_decode_RS2_1 = _zz_decode_RS2_3;
end
`ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin
_zz_decode_RS2_1 = memory_SHIFT_RIGHT;
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l128) begin
_zz_decode_RS2_1 = memory_DivPlugin_div_result;
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
_zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0;
end
end
assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL;
assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_execute_SRC2 = execute_PC;
assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL;
assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL;
assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3];
assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20];
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS = execute_SrcPlugin_less;
assign execute_ALU_CTRL = _zz_execute_ALU_CTRL;
assign execute_SRC2 = _zz_execute_SRC2_5;
assign execute_SRC1 = _zz_execute_SRC1;
assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL;
assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION;
assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID;
always @(*) begin
_zz_1 = 1'b0;
if(lastStageRegFileWrite_valid) begin
_zz_1 = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
always @(*) begin
decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10];
if(when_RegFilePlugin_l63) begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0);
always @(*) begin
_zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA;
if(when_DBusCachedPlugin_l484) begin
_zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated;
end
if(when_MulPlugin_l147) begin
case(switch_MulPlugin_l148)
2'b00 : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2;
end
default : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1;
end
endcase
end
end
assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR;
assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4];
assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0];
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3;
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_rsp_issueDetected_4 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2;
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_issueDetected_3 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_rsp_issueDetected_2 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_issueDetected_1 = 1'b1;
end
end
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1;
assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
always @(*) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT;
if(BranchPlugin_jumpInterface_valid) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload;
end
end
always @(*) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload;
end
end
assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @(*) begin
decode_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l303) begin
decode_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
decode_arbitration_haltByOther = 1'b0;
if(when_HazardSimplePlugin_l113) begin
decode_arbitration_haltByOther = 1'b1;
end
if(CsrPlugin_pipelineLiberator_active) begin
decode_arbitration_haltByOther = 1'b1;
end
if(when_CsrPlugin_l1116) begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_when) begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed) begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
always @(*) begin
decode_arbitration_flushNext = 1'b0;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
decode_arbitration_flushNext = 1'b1;
end
if(_zz_when) begin
decode_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l343) begin
execute_arbitration_haltItself = 1'b1;
end
if(when_CsrPlugin_l1108) begin
if(when_CsrPlugin_l1110) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CsrPlugin_l1180) begin
if(execute_CsrPlugin_blockedBySideEffects) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CfuPlugin_l175) begin
execute_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltByOther = 1'b0;
if(when_DBusCachedPlugin_l359) begin
execute_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
execute_arbitration_removeIt = 1'b0;
if(_zz_when_1) begin
execute_arbitration_removeIt = 1'b1;
end
if(execute_arbitration_isFlushed) begin
execute_arbitration_removeIt = 1'b1;
end
end
assign execute_arbitration_flushIt = 1'b0;
always @(*) begin
execute_arbitration_flushNext = 1'b0;
if(BranchPlugin_jumpInterface_valid) begin
execute_arbitration_flushNext = 1'b1;
end
if(_zz_when_1) begin
execute_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
memory_arbitration_haltItself = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l129) begin
memory_arbitration_haltItself = 1'b1;
end
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
if(when_CfuPlugin_l208) begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @(*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed) begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushIt = 1'b0;
assign memory_arbitration_flushNext = 1'b0;
always @(*) begin
writeBack_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l458) begin
writeBack_arbitration_haltItself = 1'b1;
end
end
assign writeBack_arbitration_haltByOther = 1'b0;
always @(*) begin
writeBack_arbitration_removeIt = 1'b0;
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_removeIt = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
writeBack_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushIt = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushNext = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1019) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1064) begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @(*) begin
IBusCachedPlugin_fetcherHalt = 1'b0;
if(when_CsrPlugin_l922) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1019) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1064) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_incomingInstruction = 1'b0;
if(when_Fetcher_l240) begin
IBusCachedPlugin_incomingInstruction = 1'b1;
end
end
assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0;
assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit;
always @(*) begin
CsrPlugin_inWfi = 1'b0;
if(when_CsrPlugin_l1108) begin
CsrPlugin_inWfi = 1'b1;
end
end
assign CsrPlugin_thirdPartyWake = 1'b0;
always @(*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(when_CsrPlugin_l1064) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00};
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
assign CsrPlugin_forceMachineWire = 1'b0;
assign CsrPlugin_allowInterrupts = 1'b1;
assign CsrPlugin_allowException = 1'b1;
assign CsrPlugin_allowEbreakException = 1'b1;
assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000);
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}};
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1));
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3];
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
always @(*) begin
IBusCachedPlugin_fetchPc_correction = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
end
assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg);
always @(*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate);
assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready);
always @(*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc);
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
always @(*) begin
IBusCachedPlugin_fetchPc_flushed = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
end
assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate));
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
always @(*) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b0;
if(IBusCachedPlugin_rsp_redoFetch) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b1;
end
end
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_mmuBus_busy) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0;
if(when_IBusCachedPlugin_l267) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt);
assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch;
assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch);
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if(when_Fetcher_l320) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid);
assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0);
assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready));
assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready));
assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck);
assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck);
assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck);
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck);
assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid;
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11];
always @(*) begin
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
end
always @(*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31]));
if(_zz_6) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_2 = _zz__zz_2[19];
always @(*) begin
_zz_3[10] = _zz_2;
_zz_3[9] = _zz_2;
_zz_3[8] = _zz_2;
_zz_3[7] = _zz_2;
_zz_3[6] = _zz_2;
_zz_3[5] = _zz_2;
_zz_3[4] = _zz_2;
_zz_3[3] = _zz_2;
_zz_3[2] = _zz_2;
_zz_3[1] = _zz_2;
_zz_3[0] = _zz_2;
end
assign _zz_4 = _zz__zz_4[11];
always @(*) begin
_zz_5[18] = _zz_4;
_zz_5[17] = _zz_4;
_zz_5[16] = _zz_4;
_zz_5[15] = _zz_4;
_zz_5[14] = _zz_4;
_zz_5[13] = _zz_4;
_zz_5[12] = _zz_4;
_zz_5[11] = _zz_4;
_zz_5[10] = _zz_4;
_zz_5[9] = _zz_4;
_zz_5[8] = _zz_4;
_zz_5[7] = _zz_4;
_zz_5[6] = _zz_4;
_zz_5[5] = _zz_4;
_zz_5[4] = _zz_4;
_zz_5[3] = _zz_4;
_zz_5[2] = _zz_4;
_zz_5[1] = _zz_4;
_zz_5[0] = _zz_4;
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_6 = _zz__zz_6[1];
end
default : begin
_zz_6 = _zz__zz_6_1[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
end
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @(*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid;
assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush);
assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
assign IBusCachedPlugin_rsp_issueDetected = 1'b0;
always @(*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001;
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00};
assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected));
assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1));
assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2));
assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3));
assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt);
assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid;
assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready;
assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload;
assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last);
always @(*) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
if(when_Stream_l342) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1;
end
end
assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid);
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last;
assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready;
assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE);
assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12];
assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD;
always @(*) begin
case(execute_DBusCachedPlugin_size)
2'b00 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0];
end
endcase
end
assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT);
assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready));
assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt);
assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid);
assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE);
assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA;
assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid;
assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck;
assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address;
assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
always @(*) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess;
if(when_DBusCachedPlugin_l386) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1;
end
end
assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite));
always @(*) begin
dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
if(writeBack_arbitration_haltByOther) begin
dataCache_1_io_cpu_writeBack_isValid = 1'b0;
end
end
assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00);
assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA;
assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF;
always @(*) begin
DBusCachedPlugin_redoBranch_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_redoBranch_valid = 1'b1;
end
end
end
assign DBusCachedPlugin_redoBranch_payload = writeBack_PC;
always @(*) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
end
end
end
assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA;
always @(*) begin
DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code};
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101);
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1};
end
end
end
assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt);
assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0];
assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8];
assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16];
assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24];
always @(*) begin
writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted;
writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2;
writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2;
writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3;
end
assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0];
assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12];
assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0];
end
assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0];
end
always @(*) begin
case(switch_Misc_l200)
2'b00 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1;
end
2'b01 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3;
end
default : begin
writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf;
end
endcase
end
assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusCachedPlugin_mmuBus_busy = 1'b0;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}};
assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1];
assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2;
assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6];
assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2;
assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8];
assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2;
assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18];
assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2;
assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21];
assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2;
assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23];
assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2;
assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26];
assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33];
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = 4'b0010;
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0);
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;
always @(*) begin
lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
if(_zz_7) begin
lastStageRegFileWrite_valid = 1'b1;
end
end
always @(*) begin
lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
if(_zz_7) begin
lastStageRegFileWrite_payload_address = 5'h0;
end
end
always @(*) begin
lastStageRegFileWrite_payload_data = _zz_decode_RS2_2;
if(_zz_7) begin
lastStageRegFileWrite_payload_data = 32'h0;
end
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_BITWISE : begin
_zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_binary_sequential_SLT_SLTU : begin
_zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA};
end
default : begin
_zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB;
end
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC1 = execute_RS1;
end
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin
_zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1};
end
`Src1CtrlEnum_binary_sequential_IMU : begin
_zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0};
end
default : begin
_zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1};
end
endcase
end
assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_SRC2_2[19] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[18] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[17] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[16] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[15] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[14] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[13] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[12] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[11] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[10] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[9] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[8] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[7] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[6] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[5] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[4] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[3] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[2] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[1] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[0] = _zz_execute_SRC2_1;
end
assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11];
always @(*) begin
_zz_execute_SRC2_4[19] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[18] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[17] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[16] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[15] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[14] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[13] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[12] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[11] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[10] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[9] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[8] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[7] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[6] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[5] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[4] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[3] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[2] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[1] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[0] = _zz_execute_SRC2_3;
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC2_5 = execute_RS2;
end
`Src2CtrlEnum_binary_sequential_IMI : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_binary_sequential_IMS : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_execute_SRC2_5 = _zz_execute_SRC2;
end
endcase
end
always @(*) begin
execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub;
if(execute_SRC2_FORCE_ZERO) begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
always @(*) begin
_zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31];
_zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30];
_zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29];
_zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28];
_zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27];
_zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26];
_zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25];
_zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24];
_zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23];
_zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22];
_zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21];
_zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20];
_zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19];
_zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18];
_zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17];
_zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16];
_zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15];
_zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14];
_zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13];
_zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12];
_zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11];
_zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10];
_zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9];
_zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8];
_zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7];
_zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6];
_zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5];
_zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4];
_zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3];
_zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2];
_zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1];
_zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0];
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1);
always @(*) begin
_zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31];
_zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30];
_zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29];
_zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28];
_zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27];
_zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26];
_zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25];
_zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24];
_zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23];
_zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22];
_zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21];
_zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20];
_zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19];
_zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18];
_zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17];
_zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16];
_zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15];
_zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14];
_zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13];
_zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12];
_zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11];
_zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10];
_zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9];
_zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8];
_zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7];
_zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6];
_zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5];
_zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4];
_zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3];
_zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2];
_zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1];
_zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0];
end
always @(*) begin
HazardSimplePlugin_src0Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l48) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l48_1) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l48_2) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l105) begin
HazardSimplePlugin_src0Hazard = 1'b0;
end
end
always @(*) begin
HazardSimplePlugin_src1Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l51) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l51_1) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l51_2) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l108) begin
HazardSimplePlugin_src1Hazard = 1'b0;
end
end
assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2;
assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]);
assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l47 = 1'b1;
assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47));
assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE);
assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE);
assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard));
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12];
always @(*) begin
casez(switch_Misc_l200_1)
3'b000 : begin
_zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq;
end
3'b001 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq);
end
3'b1?1 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS);
end
default : begin
_zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS;
end
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b0;
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
default : begin
_zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT;
end
endcase
end
assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1];
end
default : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6);
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2) begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9};
end
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2;
end
assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
always @(*) begin
BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1]));
if(when_BranchPlugin_l296) begin
BranchPlugin_branchExceptionPort_valid = 1'b0;
end
end
assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000;
assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC;
assign when_BranchPlugin_l296 = 1'b0;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @(*) begin
CsrPlugin_privilege = 2'b11;
if(CsrPlugin_forceMachineWire) begin
CsrPlugin_privilege = 2'b11;
end
end
assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11;
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0];
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0];
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
end
if(execute_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(memory_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000);
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11));
assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0));
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid);
assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt);
always @(*) begin
CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
if(when_CsrPlugin_l991) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000);
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @(*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException) begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @(*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException) begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @(*) begin
CsrPlugin_xtvec_mode = 2'bxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @(*) begin
CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28];
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake);
assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000);
assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0);
always @(*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
if(execute_CsrPlugin_csr_3264) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3857) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3858) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3859) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3860) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_769) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_768) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_836) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_772) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_773) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_833) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_832) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_834) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_835) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2816) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2944) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2818) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2946) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_3072) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3200) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3074) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3202) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3008) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_4032) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(CsrPlugin_csrMapping_allowCsrSignal) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(when_CsrPlugin_l1302) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if(when_CsrPlugin_l1136) begin
if(when_CsrPlugin_l1137) begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @(*) begin
CsrPlugin_selfException_valid = 1'b0;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_valid = 1'b1;
end
if(when_CsrPlugin_l1144) begin
CsrPlugin_selfException_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_selfException_payload_code = 4'bxxxx;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_payload_code = 4'b0010;
end
if(when_CsrPlugin_l1144) begin
case(CsrPlugin_privilege)
2'b00 : begin
CsrPlugin_selfException_payload_code = 4'b1000;
end
default : begin
CsrPlugin_selfException_payload_code = 4'b1011;
end
endcase
end
end
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction);
assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]);
assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL));
always @(*) begin
execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_writeInstruction = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_readInstruction = 1'b0;
end
end
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck));
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck));
assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects);
assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal;
assign switch_Misc_l200_2 = execute_INSTRUCTION[13];
always @(*) begin
case(switch_Misc_l200_2)
1'b0 : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1;
end
default : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal;
assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR);
assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign execute_MulPlugin_a = execute_RS1;
assign execute_MulPlugin_b = execute_RS2;
assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12];
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_aSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_aSigned = 1'b1;
end
default : begin
execute_MulPlugin_aSigned = 1'b0;
end
endcase
end
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_bSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_bSigned = 1'b0;
end
default : begin
execute_MulPlugin_bSigned = 1'b0;
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0];
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0];
assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]};
assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]};
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]};
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]};
assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1));
assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL);
assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12];
assign memory_DivPlugin_frontendOk = 1'b1;
always @(*) begin
memory_DivPlugin_div_counter_willIncrement = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @(*) begin
memory_DivPlugin_div_counter_willClear = 1'b0;
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_div_counter_willClear = 1'b1;
end
end
assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21);
assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement);
always @(*) begin
if(memory_DivPlugin_div_counter_willOverflow) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end else begin
memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext);
end
if(memory_DivPlugin_div_counter_willClear) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end
end
assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20);
assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck);
assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV);
assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done));
assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done));
assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0];
assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]};
assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator);
assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1);
assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0];
assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20);
assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]);
assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck);
assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @(*) begin
_zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1;
end
assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0);
assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE);
assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready);
assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers);
assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired));
assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready));
assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1;
assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2;
end
default : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]};
end
endcase
end
assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0);
always @(*) begin
CfuPlugin_bus_rsp_rsp_ready = 1'b0;
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers);
end
end
assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid);
assign when_Pipeline_l124 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack));
assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL;
assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1;
assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL;
assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL;
assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1;
assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL;
assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1;
assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL;
assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL;
assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1;
assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL;
assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL;
assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1;
assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck);
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck);
assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL;
assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL;
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck);
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL;
assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL;
assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1;
assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck);
assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck);
assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck);
assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck);
assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck);
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt);
assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck);
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0;
if(execute_CsrPlugin_csr_3264) begin
_zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000;
_zz_CsrPlugin_csrMapping_readDataInit_2[23 : 20] = 4'b1000;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0;
if(execute_CsrPlugin_csr_3857) begin
_zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0;
if(execute_CsrPlugin_csr_3858) begin
_zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0;
if(execute_CsrPlugin_csr_3859) begin
_zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0;
if(execute_CsrPlugin_csr_769) begin
_zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base;
_zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0;
if(execute_CsrPlugin_csr_768) begin
_zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP;
_zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE;
_zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0;
if(execute_CsrPlugin_csr_836) begin
_zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP;
_zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP;
_zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0;
if(execute_CsrPlugin_csr_772) begin
_zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE;
_zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE;
_zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0;
if(execute_CsrPlugin_csr_773) begin
_zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base;
_zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0;
if(execute_CsrPlugin_csr_833) begin
_zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0;
if(execute_CsrPlugin_csr_832) begin
_zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0;
if(execute_CsrPlugin_csr_834) begin
_zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt;
_zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0;
if(execute_CsrPlugin_csr_835) begin
_zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0;
if(execute_CsrPlugin_csr_2816) begin
_zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0;
if(execute_CsrPlugin_csr_2944) begin
_zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0;
if(execute_CsrPlugin_csr_2818) begin
_zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0;
if(execute_CsrPlugin_csr_2946) begin
_zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0;
if(execute_CsrPlugin_csr_3072) begin
_zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0;
if(execute_CsrPlugin_csr_3200) begin
_zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0;
if(execute_CsrPlugin_csr_3074) begin
_zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0;
if(execute_CsrPlugin_csr_3202) begin
_zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0;
if(execute_CsrPlugin_csr_3008) begin
_zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0;
if(execute_CsrPlugin_csr_4032) begin
_zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1;
end
end
assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24))));
assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]);
assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR));
assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR};
assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010);
assign iBusWishbone_BTE = 2'b00;
assign iBusWishbone_SEL = 4'b1111;
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
always @(*) begin
iBusWishbone_CYC = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_CYC = 1'b1;
end
end
always @(*) begin
iBusWishbone_STB = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_STB = 1'b1;
end
end
assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000));
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_iBus_rsp_valid;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 2'b11);
assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid;
assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr;
assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 1'b1));
assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4));
assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 3],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2);
assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000);
assign dBusWishbone_BTE = 2'b00;
assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111);
assign dBusWishbone_WE = _zz_dBus_cmd_ready_3;
assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data;
assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK);
assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1;
assign dBusWishbone_STB = _zz_dBus_cmd_ready_1;
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
assign dBus_rsp_payload_error = 1'b0;
always @(posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter;
IBusCachedPlugin_rspCounter <= 32'h0;
dataCache_1_io_mem_cmd_rValid <= 1'b0;
dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0;
DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter;
DBusCachedPlugin_rspCounter <= 32'h0;
_zz_7 <= 1'b1;
HazardSimplePlugin_writeBackBuffer_valid <= 1'b0;
CsrPlugin_misa_base <= 2'b01;
CsrPlugin_misa_extensions <= 26'h0000042;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= 2'b11;
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_lastStageWasWfi <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_DivPlugin_div_counter_value <= 6'h0;
_zz_CsrPlugin_csrMapping_readDataInit <= 32'h0;
execute_CfuPlugin_hold <= 1'b0;
execute_CfuPlugin_fired <= 1'b0;
CfuPlugin_bus_rsp_rValid <= 1'b0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0;
_zz_iBusWishbone_ADR <= 3'b000;
_zz_iBus_rsp_valid <= 1'b0;
_zz_dBus_cmd_ready <= 1'b0;
_zz_dBus_rsp_valid <= 1'b0;
end else begin
if(IBusCachedPlugin_fetchPc_correction) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_output_fire) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
end
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if(when_Fetcher_l131) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_output_fire_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(when_Fetcher_l131_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(when_Fetcher_l158) begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
end
if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0));
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush));
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if(when_Fetcher_l329) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(when_Fetcher_l329_1) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(when_Fetcher_l329_2) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(when_Fetcher_l329_3) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(when_Fetcher_l329_4) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(iBus_rsp_valid) begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001);
end
if(dataCache_1_io_mem_cmd_valid) begin
dataCache_1_io_mem_cmd_rValid <= 1'b1;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_rValid <= 1'b0;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid;
end
if(dBus_rsp_valid) begin
DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001);
end
_zz_7 <= 1'b0;
HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid;
if(when_CsrPlugin_l909) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if(when_CsrPlugin_l909_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if(when_CsrPlugin_l909_2) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if(when_CsrPlugin_l909_3) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
if(CsrPlugin_pipelineLiberator_active) begin
if(when_CsrPlugin_l980) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1;
end
if(when_CsrPlugin_l980_1) begin
CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0;
end
if(when_CsrPlugin_l980_2) begin
CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1;
end
end
if(when_CsrPlugin_l985) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
end
if(CsrPlugin_interruptJump) begin
CsrPlugin_interrupt_valid <= 1'b0;
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_mstatus_MPP <= 2'b00;
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake);
memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext;
if(execute_CfuPlugin_schedule) begin
execute_CfuPlugin_hold <= 1'b1;
end
if(CfuPlugin_bus_cmd_ready) begin
execute_CfuPlugin_hold <= 1'b0;
end
if(CfuPlugin_bus_cmd_fire) begin
execute_CfuPlugin_fired <= 1'b1;
end
if(when_CfuPlugin_l171) begin
execute_CfuPlugin_fired <= 1'b0;
end
if(CfuPlugin_bus_rsp_valid) begin
CfuPlugin_bus_rsp_rValid <= 1'b1;
end
if(CfuPlugin_bus_rsp_rsp_ready) begin
CfuPlugin_bus_rsp_rValid <= 1'b0;
end
if(when_Pipeline_l124_61) begin
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l151) begin
execute_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154) begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(when_Pipeline_l151_1) begin
memory_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_1) begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(when_Pipeline_l151_2) begin
writeBack_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_2) begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
if(execute_CsrPlugin_csr_769) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30];
CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0];
end
end
if(execute_CsrPlugin_csr_768) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11];
CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_772) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11];
CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_3008) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(when_InstructionCache_l239) begin
if(iBusWishbone_ACK) begin
_zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001);
end
end
_zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK);
if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin
_zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 1'b1);
if(_zz_dBus_cmd_ready_4) begin
_zz_dBus_cmd_ready <= 1'b0;
end
end
_zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK);
end
end
always @(posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(dataCache_1_io_mem_cmd_ready) begin
dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr;
dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached;
dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address;
dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data;
dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask;
dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size;
dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address;
dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data;
dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size;
dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last;
end
HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address;
HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data;
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001);
if(writeBack_arbitration_isFiring) begin
CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001);
end
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr);
end
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code;
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr;
end
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_code <= 4'b0111;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_code <= 4'b0011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_code <= 4'b1011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
end
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException) begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l126) begin
memory_DivPlugin_div_done <= 1'b1;
end
if(when_MulDivIterativePlugin_l126_1) begin
memory_DivPlugin_div_done <= 1'b0;
end
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator;
memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder;
if(when_MulDivIterativePlugin_l151) begin
memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0];
end
end
end
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_accumulator <= 65'h0;
memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2);
memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1);
memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if(CfuPlugin_bus_rsp_ready) begin
CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0;
end
if(when_Pipeline_l124) begin
decode_to_execute_PC <= decode_PC;
end
if(when_Pipeline_l124_1) begin
execute_to_memory_PC <= _zz_execute_SRC2;
end
if(when_Pipeline_l124_2) begin
memory_to_writeBack_PC <= memory_PC;
end
if(when_Pipeline_l124_3) begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if(when_Pipeline_l124_4) begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if(when_Pipeline_l124_5) begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(when_Pipeline_l124_6) begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_7) begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_8) begin
memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_9) begin
decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY;
end
if(when_Pipeline_l124_10) begin
decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL;
end
if(when_Pipeline_l124_11) begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if(when_Pipeline_l124_12) begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if(when_Pipeline_l124_13) begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if(when_Pipeline_l124_14) begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if(when_Pipeline_l124_15) begin
decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL;
end
if(when_Pipeline_l124_16) begin
decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL;
end
if(when_Pipeline_l124_17) begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_18) begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_19) begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_20) begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if(when_Pipeline_l124_21) begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_22) begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_23) begin
decode_to_execute_MEMORY_WR <= decode_MEMORY_WR;
end
if(when_Pipeline_l124_24) begin
execute_to_memory_MEMORY_WR <= execute_MEMORY_WR;
end
if(when_Pipeline_l124_25) begin
memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR;
end
if(when_Pipeline_l124_26) begin
decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT;
end
if(when_Pipeline_l124_27) begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if(when_Pipeline_l124_28) begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL;
end
if(when_Pipeline_l124_29) begin
decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL;
end
if(when_Pipeline_l124_30) begin
execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL;
end
if(when_Pipeline_l124_31) begin
decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL;
end
if(when_Pipeline_l124_32) begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if(when_Pipeline_l124_33) begin
decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL;
end
if(when_Pipeline_l124_34) begin
execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL;
end
if(when_Pipeline_l124_35) begin
memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL;
end
if(when_Pipeline_l124_36) begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if(when_Pipeline_l124_37) begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if(when_Pipeline_l124_38) begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL;
end
if(when_Pipeline_l124_39) begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if(when_Pipeline_l124_40) begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if(when_Pipeline_l124_41) begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if(when_Pipeline_l124_42) begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if(when_Pipeline_l124_43) begin
decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE;
end
if(when_Pipeline_l124_44) begin
decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
end
if(when_Pipeline_l124_45) begin
decode_to_execute_RS1 <= decode_RS1;
end
if(when_Pipeline_l124_46) begin
decode_to_execute_RS2 <= decode_RS2;
end
if(when_Pipeline_l124_47) begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if(when_Pipeline_l124_48) begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if(when_Pipeline_l124_49) begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if(when_Pipeline_l124_50) begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if(when_Pipeline_l124_51) begin
execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_52) begin
memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_53) begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2;
end
if(when_Pipeline_l124_54) begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1;
end
if(when_Pipeline_l124_55) begin
execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;
end
if(when_Pipeline_l124_56) begin
execute_to_memory_MUL_LL <= execute_MUL_LL;
end
if(when_Pipeline_l124_57) begin
execute_to_memory_MUL_LH <= execute_MUL_LH;
end
if(when_Pipeline_l124_58) begin
execute_to_memory_MUL_HL <= execute_MUL_HL;
end
if(when_Pipeline_l124_59) begin
execute_to_memory_MUL_HH <= execute_MUL_HH;
end
if(when_Pipeline_l124_60) begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH;
end
if(when_Pipeline_l124_62) begin
memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l124_63) begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW;
end
if(when_CsrPlugin_l1264) begin
execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0);
end
if(when_CsrPlugin_l1264_1) begin
execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11);
end
if(when_CsrPlugin_l1264_2) begin
execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12);
end
if(when_CsrPlugin_l1264_3) begin
execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13);
end
if(when_CsrPlugin_l1264_4) begin
execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14);
end
if(when_CsrPlugin_l1264_5) begin
execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301);
end
if(when_CsrPlugin_l1264_6) begin
execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300);
end
if(when_CsrPlugin_l1264_7) begin
execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344);
end
if(when_CsrPlugin_l1264_8) begin
execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304);
end
if(when_CsrPlugin_l1264_9) begin
execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305);
end
if(when_CsrPlugin_l1264_10) begin
execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341);
end
if(when_CsrPlugin_l1264_11) begin
execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340);
end
if(when_CsrPlugin_l1264_12) begin
execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342);
end
if(when_CsrPlugin_l1264_13) begin
execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343);
end
if(when_CsrPlugin_l1264_14) begin
execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00);
end
if(when_CsrPlugin_l1264_15) begin
execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80);
end
if(when_CsrPlugin_l1264_16) begin
execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02);
end
if(when_CsrPlugin_l1264_17) begin
execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82);
end
if(when_CsrPlugin_l1264_18) begin
execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00);
end
if(when_CsrPlugin_l1264_19) begin
execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80);
end
if(when_CsrPlugin_l1264_20) begin
execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02);
end
if(when_CsrPlugin_l1264_21) begin
execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82);
end
if(when_CsrPlugin_l1264_22) begin
execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0);
end
if(when_CsrPlugin_l1264_23) begin
execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0);
end
if(execute_CsrPlugin_csr_836) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2];
CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0];
end
end
if(execute_CsrPlugin_csr_833) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_832) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_834) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31];
CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0];
end
end
if(execute_CsrPlugin_csr_835) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2816) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2944) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2818) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2946) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO;
end
endmodule
module DataCache (
input io_cpu_execute_isValid,
input [31:0] io_cpu_execute_address,
output reg io_cpu_execute_haltIt,
input io_cpu_execute_args_wr,
input [1:0] io_cpu_execute_args_size,
input io_cpu_execute_args_totalyConsistent,
output io_cpu_execute_refilling,
input io_cpu_memory_isValid,
input io_cpu_memory_isStuck,
output io_cpu_memory_isWrite,
input [31:0] io_cpu_memory_address,
input [31:0] io_cpu_memory_mmuRsp_physicalAddress,
input io_cpu_memory_mmuRsp_isIoAccess,
input io_cpu_memory_mmuRsp_isPaging,
input io_cpu_memory_mmuRsp_allowRead,
input io_cpu_memory_mmuRsp_allowWrite,
input io_cpu_memory_mmuRsp_allowExecute,
input io_cpu_memory_mmuRsp_exception,
input io_cpu_memory_mmuRsp_refilling,
input io_cpu_memory_mmuRsp_bypassTranslation,
input io_cpu_writeBack_isValid,
input io_cpu_writeBack_isStuck,
input io_cpu_writeBack_isUser,
output reg io_cpu_writeBack_haltIt,
output io_cpu_writeBack_isWrite,
input [31:0] io_cpu_writeBack_storeData,
output reg [31:0] io_cpu_writeBack_data,
input [31:0] io_cpu_writeBack_address,
output io_cpu_writeBack_mmuException,
output io_cpu_writeBack_unalignedAccess,
output reg io_cpu_writeBack_accessError,
output io_cpu_writeBack_keepMemRspData,
input io_cpu_writeBack_fence_SW,
input io_cpu_writeBack_fence_SR,
input io_cpu_writeBack_fence_SO,
input io_cpu_writeBack_fence_SI,
input io_cpu_writeBack_fence_PW,
input io_cpu_writeBack_fence_PR,
input io_cpu_writeBack_fence_PO,
input io_cpu_writeBack_fence_PI,
input [3:0] io_cpu_writeBack_fence_FM,
output io_cpu_writeBack_exclusiveOk,
output reg io_cpu_redo,
input io_cpu_flush_valid,
output io_cpu_flush_ready,
output reg io_mem_cmd_valid,
input io_mem_cmd_ready,
output reg io_mem_cmd_payload_wr,
output io_mem_cmd_payload_uncached,
output reg [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output [3:0] io_mem_cmd_payload_mask,
output reg [1:0] io_mem_cmd_payload_size,
output io_mem_cmd_payload_last,
input io_mem_rsp_valid,
input io_mem_rsp_payload_last,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [21:0] _zz_ways_0_tags_port0;
reg [31:0] _zz_ways_0_data_port0;
wire [21:0] _zz_ways_0_tags_port;
wire [9:0] _zz_stage0_dataColisions;
wire [9:0] _zz__zz_stageA_dataColisions;
wire [0:0] _zz_when;
wire [1:0] _zz_loader_waysAllocator;
reg _zz_1;
reg _zz_2;
wire haltCpu;
reg tagsReadCmd_valid;
reg [8:0] tagsReadCmd_payload;
reg tagsWriteCmd_valid;
reg [0:0] tagsWriteCmd_payload_way;
reg [8:0] tagsWriteCmd_payload_address;
reg tagsWriteCmd_payload_data_valid;
reg tagsWriteCmd_payload_data_error;
reg [19:0] tagsWriteCmd_payload_data_address;
reg tagsWriteLastCmd_valid;
reg [0:0] tagsWriteLastCmd_payload_way;
reg [8:0] tagsWriteLastCmd_payload_address;
reg tagsWriteLastCmd_payload_data_valid;
reg tagsWriteLastCmd_payload_data_error;
reg [19:0] tagsWriteLastCmd_payload_data_address;
reg dataReadCmd_valid;
reg [9:0] dataReadCmd_payload;
reg dataWriteCmd_valid;
reg [0:0] dataWriteCmd_payload_way;
reg [9:0] dataWriteCmd_payload_address;
reg [31:0] dataWriteCmd_payload_data;
reg [3:0] dataWriteCmd_payload_mask;
wire _zz_ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_error;
wire [19:0] ways_0_tagsReadRsp_address;
wire [21:0] _zz_ways_0_tagsReadRsp_valid_1;
wire _zz_ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRsp;
wire when_DataCache_l634;
wire when_DataCache_l637;
wire when_DataCache_l656;
wire rspSync;
wire rspLast;
reg memCmdSent;
wire io_mem_cmd_fire;
wire when_DataCache_l678;
reg [3:0] _zz_stage0_mask;
wire [3:0] stage0_mask;
wire [0:0] stage0_dataColisions;
wire [0:0] stage0_wayInvalidate;
wire stage0_isAmo;
wire when_DataCache_l763;
reg stageA_request_wr;
reg [1:0] stageA_request_size;
reg stageA_request_totalyConsistent;
wire when_DataCache_l763_1;
reg [3:0] stageA_mask;
wire stageA_isAmo;
wire stageA_isLrsc;
wire [0:0] stageA_wayHits;
wire when_DataCache_l763_2;
reg [0:0] stageA_wayInvalidate;
wire when_DataCache_l763_3;
reg [0:0] stage0_dataColisions_regNextWhen;
wire [0:0] _zz_stageA_dataColisions;
wire [0:0] stageA_dataColisions;
wire when_DataCache_l814;
reg stageB_request_wr;
reg [1:0] stageB_request_size;
reg stageB_request_totalyConsistent;
reg stageB_mmuRspFreeze;
wire when_DataCache_l816;
reg [31:0] stageB_mmuRsp_physicalAddress;
reg stageB_mmuRsp_isIoAccess;
reg stageB_mmuRsp_isPaging;
reg stageB_mmuRsp_allowRead;
reg stageB_mmuRsp_allowWrite;
reg stageB_mmuRsp_allowExecute;
reg stageB_mmuRsp_exception;
reg stageB_mmuRsp_refilling;
reg stageB_mmuRsp_bypassTranslation;
wire when_DataCache_l813;
reg stageB_tagsReadRsp_0_valid;
reg stageB_tagsReadRsp_0_error;
reg [19:0] stageB_tagsReadRsp_0_address;
wire when_DataCache_l813_1;
reg [31:0] stageB_dataReadRsp_0;
wire when_DataCache_l812;
reg [0:0] stageB_wayInvalidate;
wire stageB_consistancyHazard;
wire when_DataCache_l812_1;
reg [0:0] stageB_dataColisions;
wire when_DataCache_l812_2;
reg stageB_unaligned;
wire when_DataCache_l812_3;
reg [0:0] stageB_waysHitsBeforeInvalidate;
wire [0:0] stageB_waysHits;
wire stageB_waysHit;
wire [31:0] stageB_dataMux;
wire when_DataCache_l812_4;
reg [3:0] stageB_mask;
reg stageB_loaderValid;
wire [31:0] stageB_ioMemRspMuxed;
reg stageB_flusher_waitDone;
wire stageB_flusher_hold;
reg [9:0] stageB_flusher_counter;
wire when_DataCache_l842;
wire when_DataCache_l848;
reg stageB_flusher_start;
wire stageB_isAmo;
wire stageB_isAmoCached;
wire stageB_isExternalLsrc;
wire stageB_isExternalAmo;
wire [31:0] stageB_requestDataBypass;
reg stageB_cpuWriteToCache;
wire when_DataCache_l911;
wire stageB_badPermissions;
wire stageB_loadStoreFault;
wire stageB_bypassCache;
wire when_DataCache_l980;
wire when_DataCache_l989;
wire when_DataCache_l994;
wire when_DataCache_l1005;
wire when_DataCache_l1017;
wire when_DataCache_l976;
wire when_DataCache_l1051;
wire when_DataCache_l1060;
reg loader_valid;
reg loader_counter_willIncrement;
wire loader_counter_willClear;
reg [0:0] loader_counter_valueNext;
reg [0:0] loader_counter_value;
wire loader_counter_willOverflowIfInc;
wire loader_counter_willOverflow;
reg [0:0] loader_waysAllocator;
reg loader_error;
wire loader_kill;
reg loader_killReg;
wire when_DataCache_l1075;
wire loader_done;
wire when_DataCache_l1103;
reg loader_valid_regNext;
wire when_DataCache_l1107;
wire when_DataCache_l1110;
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:511];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023];
reg [7:0] _zz_ways_0_datasymbol_read;
reg [7:0] _zz_ways_0_datasymbol_read_1;
reg [7:0] _zz_ways_0_datasymbol_read_2;
reg [7:0] _zz_ways_0_datasymbol_read_3;
assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0);
assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0);
assign _zz_when = 1'b1;
assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]};
assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
always @(posedge clk) begin
if(_zz_ways_0_tagsReadRsp_valid) begin
_zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(*) begin
_zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read};
end
always @(posedge clk) begin
if(_zz_ways_0_dataReadRspMem) begin
_zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload];
end
end
always @(posedge clk) begin
if(dataWriteCmd_payload_mask[0] && _zz_1) begin
ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
end
if(dataWriteCmd_payload_mask[1] && _zz_1) begin
ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
end
if(dataWriteCmd_payload_mask[2] && _zz_1) begin
ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
end
if(dataWriteCmd_payload_mask[3] && _zz_1) begin
ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(when_DataCache_l637) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(when_DataCache_l634) begin
_zz_2 = 1'b1;
end
end
assign haltCpu = 1'b0;
assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0;
assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0];
assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1];
assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2];
assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
assign ways_0_dataReadRspMem = _zz_ways_0_data_port0;
assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0];
assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]);
assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]);
always @(*) begin
tagsReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
tagsReadCmd_valid = 1'b1;
end
end
always @(*) begin
tagsReadCmd_payload = 9'bxxxxxxxxx;
if(when_DataCache_l656) begin
tagsReadCmd_payload = io_cpu_execute_address[11 : 3];
end
end
always @(*) begin
dataReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
dataReadCmd_valid = 1'b1;
end
end
always @(*) begin
dataReadCmd_payload = 10'bxxxxxxxxxx;
if(when_DataCache_l656) begin
dataReadCmd_payload = io_cpu_execute_address[11 : 2];
end
end
always @(*) begin
tagsWriteCmd_valid = 1'b0;
if(when_DataCache_l842) begin
tagsWriteCmd_valid = 1'b1;
end
if(when_DataCache_l1051) begin
tagsWriteCmd_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_valid = 1'b1;
end
end
always @(*) begin
tagsWriteCmd_payload_way = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_way = 1'b1;
end
if(loader_done) begin
tagsWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
tagsWriteCmd_payload_address = 9'bxxxxxxxxx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_address = stageB_flusher_counter[8:0];
end
if(loader_done) begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 3];
end
end
always @(*) begin
tagsWriteCmd_payload_data_valid = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_data_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg));
end
end
always @(*) begin
tagsWriteCmd_payload_data_error = 1'bx;
if(loader_done) begin
tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error));
end
end
always @(*) begin
tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx;
if(loader_done) begin
tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12];
end
end
always @(*) begin
dataWriteCmd_valid = 1'b0;
if(stageB_cpuWriteToCache) begin
if(when_DataCache_l911) begin
dataWriteCmd_valid = 1'b1;
end
end
if(when_DataCache_l1051) begin
dataWriteCmd_valid = 1'b0;
end
if(when_DataCache_l1075) begin
dataWriteCmd_valid = 1'b1;
end
end
always @(*) begin
dataWriteCmd_payload_way = 1'bx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_way = stageB_waysHits;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
dataWriteCmd_payload_address = 10'bxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2];
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 3],loader_counter_value};
end
end
always @(*) begin
dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_data = io_mem_rsp_payload_data;
end
end
always @(*) begin
dataWriteCmd_payload_mask = 4'bxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_mask = 4'b0000;
if(_zz_when[0]) begin
dataWriteCmd_payload_mask[3 : 0] = stageB_mask;
end
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_mask = 4'b1111;
end
end
assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
always @(*) begin
io_cpu_execute_haltIt = 1'b0;
if(when_DataCache_l842) begin
io_cpu_execute_haltIt = 1'b1;
end
end
assign rspSync = 1'b1;
assign rspLast = 1'b1;
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck);
always @(*) begin
_zz_stage0_mask = 4'bxxxx;
case(io_cpu_execute_args_size)
2'b00 : begin
_zz_stage0_mask = 4'b0001;
end
2'b01 : begin
_zz_stage0_mask = 4'b0011;
end
2'b10 : begin
_zz_stage0_mask = 4'b1111;
end
default : begin
end
endcase
end
assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]);
assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stage0_wayInvalidate = 1'b0;
assign stage0_isAmo = 1'b0;
assign when_DataCache_l763 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck);
assign io_cpu_memory_isWrite = stageA_request_wr;
assign stageA_isAmo = 1'b0;
assign stageA_isLrsc = 1'b0;
assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid);
assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck);
assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions);
assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_mmuRspFreeze = 1'b0;
if(when_DataCache_l1110) begin
stageB_mmuRspFreeze = 1'b1;
end
end
assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze));
assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck);
assign stageB_consistancyHazard = 1'b0;
assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck);
assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate));
assign stageB_waysHit = (stageB_waysHits != 1'b0);
assign stageB_dataMux = stageB_dataReadRsp_0;
assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_loaderValid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
if(io_mem_cmd_ready) begin
stageB_loaderValid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
stageB_loaderValid = 1'b0;
end
end
assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0];
always @(*) begin
io_cpu_writeBack_haltIt = 1'b1;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
if(when_DataCache_l980) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end else begin
if(when_DataCache_l989) begin
if(when_DataCache_l994) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
assign stageB_flusher_hold = 1'b0;
assign when_DataCache_l842 = (! stageB_flusher_counter[9]);
assign when_DataCache_l848 = (! stageB_flusher_hold);
assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[9]);
assign stageB_isAmo = 1'b0;
assign stageB_isAmoCached = 1'b0;
assign stageB_isExternalLsrc = 1'b0;
assign stageB_isExternalAmo = 1'b0;
assign stageB_requestDataBypass = io_cpu_writeBack_storeData;
always @(*) begin
stageB_cpuWriteToCache = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
stageB_cpuWriteToCache = 1'b1;
end
end
end
end
end
assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit);
assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)));
assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions));
always @(*) begin
io_cpu_redo = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
if(when_DataCache_l1005) begin
io_cpu_redo = 1'b1;
end
end
end
end
end
if(when_DataCache_l1060) begin
io_cpu_redo = 1'b1;
end
if(when_DataCache_l1107) begin
io_cpu_redo = 1'b1;
end
end
always @(*) begin
io_cpu_writeBack_accessError = 1'b0;
if(stageB_bypassCache) begin
io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error);
end else begin
io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging)));
end
end
assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging);
assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned);
assign io_cpu_writeBack_isWrite = stageB_request_wr;
always @(*) begin
io_mem_cmd_valid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
io_mem_cmd_valid = (! memCmdSent);
end else begin
if(when_DataCache_l989) begin
if(stageB_request_wr) begin
io_mem_cmd_valid = 1'b1;
end
end else begin
if(when_DataCache_l1017) begin
io_mem_cmd_valid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_mem_cmd_valid = 1'b0;
end
end
always @(*) begin
io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_address[2 : 0] = 3'b000;
end
end
end
end
end
assign io_mem_cmd_payload_last = 1'b1;
always @(*) begin
io_mem_cmd_payload_wr = stageB_request_wr;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_wr = 1'b0;
end
end
end
end
end
assign io_mem_cmd_payload_mask = stageB_mask;
assign io_mem_cmd_payload_data = stageB_requestDataBypass;
assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess;
always @(*) begin
io_mem_cmd_payload_size = stageB_request_size;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_size = 2'b11;
end
end
end
end
end
assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo);
assign io_cpu_writeBack_keepMemRspData = 1'b0;
assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready);
assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached)));
assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready);
assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0));
assign when_DataCache_l1017 = (! memCmdSent);
assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc);
always @(*) begin
if(stageB_bypassCache) begin
io_cpu_writeBack_data = stageB_ioMemRspMuxed;
end else begin
io_cpu_writeBack_data = stageB_dataMux;
end
end
assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess);
assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard));
always @(*) begin
loader_counter_willIncrement = 1'b0;
if(when_DataCache_l1075) begin
loader_counter_willIncrement = 1'b1;
end
end
assign loader_counter_willClear = 1'b0;
assign loader_counter_willOverflowIfInc = (loader_counter_value == 1'b1);
assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
always @(*) begin
loader_counter_valueNext = (loader_counter_value + loader_counter_willIncrement);
if(loader_counter_willClear) begin
loader_counter_valueNext = 1'b0;
end
end
assign loader_kill = 1'b0;
assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast);
assign loader_done = loader_counter_willOverflow;
assign when_DataCache_l1103 = (! loader_valid);
assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext));
assign io_cpu_execute_refilling = loader_valid;
assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid);
always @(posedge clk) begin
tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
if(when_DataCache_l763) begin
stageA_request_wr <= io_cpu_execute_args_wr;
stageA_request_size <= io_cpu_execute_args_size;
stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent;
end
if(when_DataCache_l763_1) begin
stageA_mask <= stage0_mask;
end
if(when_DataCache_l763_2) begin
stageA_wayInvalidate <= stage0_wayInvalidate;
end
if(when_DataCache_l763_3) begin
stage0_dataColisions_regNextWhen <= stage0_dataColisions;
end
if(when_DataCache_l814) begin
stageB_request_wr <= stageA_request_wr;
stageB_request_size <= stageA_request_size;
stageB_request_totalyConsistent <= stageA_request_totalyConsistent;
end
if(when_DataCache_l816) begin
stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress;
stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess;
stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging;
stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead;
stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite;
stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute;
stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception;
stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling;
stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation;
end
if(when_DataCache_l813) begin
stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid;
stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error;
stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address;
end
if(when_DataCache_l813_1) begin
stageB_dataReadRsp_0 <= ways_0_dataReadRsp;
end
if(when_DataCache_l812) begin
stageB_wayInvalidate <= stageA_wayInvalidate;
end
if(when_DataCache_l812_1) begin
stageB_dataColisions <= stageA_dataColisions;
end
if(when_DataCache_l812_2) begin
stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00);
end
if(when_DataCache_l812_3) begin
stageB_waysHitsBeforeInvalidate <= stageA_wayHits;
end
if(when_DataCache_l812_4) begin
stageB_mask <= stageA_mask;
end
loader_valid_regNext <= loader_valid;
end
always @(posedge clk) begin
if(reset) begin
memCmdSent <= 1'b0;
stageB_flusher_waitDone <= 1'b0;
stageB_flusher_counter <= 10'h0;
stageB_flusher_start <= 1'b1;
loader_valid <= 1'b0;
loader_counter_value <= 1'b0;
loader_waysAllocator <= 1'b1;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end else begin
if(io_mem_cmd_fire) begin
memCmdSent <= 1'b1;
end
if(when_DataCache_l678) begin
memCmdSent <= 1'b0;
end
if(io_cpu_flush_ready) begin
stageB_flusher_waitDone <= 1'b0;
end
if(when_DataCache_l842) begin
if(when_DataCache_l848) begin
stageB_flusher_counter <= (stageB_flusher_counter + 10'h001);
end
end
stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
if(stageB_flusher_start) begin
stageB_flusher_waitDone <= 1'b1;
stageB_flusher_counter <= 10'h0;
end
`ifndef SYNTHESIS
`ifdef FORMAL
assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck)));
`else
if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
$display("ERROR writeBack stuck by another plugin is not allowed");
end
`endif
`endif
if(stageB_loaderValid) begin
loader_valid <= 1'b1;
end
loader_counter_value <= loader_counter_valueNext;
if(loader_kill) begin
loader_killReg <= 1'b1;
end
if(when_DataCache_l1075) begin
loader_error <= (loader_error || io_mem_rsp_payload_error);
end
if(loader_done) begin
loader_valid <= 1'b0;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end
if(when_DataCache_l1103) begin
loader_waysAllocator <= _zz_loader_waysAllocator[0:0];
end
end
end
endmodule
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input [31:0] io_cpu_fetch_mmuRsp_physicalAddress,
input io_cpu_fetch_mmuRsp_isIoAccess,
input io_cpu_fetch_mmuRsp_isPaging,
input io_cpu_fetch_mmuRsp_allowRead,
input io_cpu_fetch_mmuRsp_allowWrite,
input io_cpu_fetch_mmuRsp_allowExecute,
input io_cpu_fetch_mmuRsp_exception,
input io_cpu_fetch_mmuRsp_refilling,
input io_cpu_fetch_mmuRsp_bypassTranslation,
output [31:0] io_cpu_fetch_physicalAddress,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [31:0] _zz_banks_0_port1;
reg [22:0] _zz_ways_0_tags_port1;
wire [22:0] _zz_ways_0_tags_port;
reg _zz_1;
reg _zz_2;
reg lineLoader_fire;
reg lineLoader_valid;
(* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [6:0] lineLoader_flushCounter;
wire when_InstructionCache_l338;
reg _zz_when_InstructionCache_l342;
wire when_InstructionCache_l342;
wire when_InstructionCache_l351;
reg lineLoader_cmdSent;
wire io_mem_cmd_fire;
wire when_Utils_l357;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
(* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ;
wire lineLoader_write_tag_0_valid;
wire [5:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [20:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [8:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire when_InstructionCache_l401;
wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem;
wire _zz_fetchStage_read_banksValue_0_dataMem_1;
wire [31:0] fetchStage_read_banksValue_0_dataMem;
wire [31:0] fetchStage_read_banksValue_0_data;
wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid;
wire _zz_fetchStage_read_waysValues_0_tag_valid_1;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [20:0] fetchStage_read_waysValues_0_tag_address;
wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
wire when_InstructionCache_l435;
reg [31:0] io_cpu_fetch_data_regNextWhen;
wire when_InstructionCache_l459;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_isPaging;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_mmuRsp_bypassTranslation;
wire when_InstructionCache_l459_1;
reg decodeStage_hit_valid;
wire when_InstructionCache_l459_2;
reg decodeStage_hit_error;
(* ram_style = "block" *) reg [31:0] banks_0 [0:511];
(* ram_style = "block" *) reg [22:0] ways_0_tags [0:63];
assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @(posedge clk) begin
if(_zz_1) begin
banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin
_zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin
_zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(lineLoader_write_data_0_valid) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(lineLoader_write_tag_0_valid) begin
_zz_2 = 1'b1;
end
end
always @(*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid) begin
if(when_InstructionCache_l401) begin
lineLoader_fire = 1'b1;
end
end
end
always @(*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(when_InstructionCache_l338) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(when_InstructionCache_l342) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush) begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]);
assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342);
assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0};
assign io_mem_cmd_payload_size = 3'b101;
assign when_Utils_l357 = (! lineLoader_valid);
always @(*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if(when_Utils_l357) begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111);
assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2];
assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck);
assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1;
assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0];
assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5];
assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck);
assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1;
assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1];
assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2];
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0);
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_banksValue_0_data;
assign fetchStage_hit_word = fetchStage_hit_data;
assign io_cpu_fetch_data = fetchStage_hit_word;
assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress;
assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))));
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
always @(posedge clk) begin
if(reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= 3'b000;
end else begin
if(lineLoader_fire) begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire) begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid) begin
lineLoader_valid <= 1'b1;
end
if(io_flush) begin
lineLoader_flushPending <= 1'b1;
end
if(when_InstructionCache_l351) begin
lineLoader_flushPending <= 1'b0;
end
if(io_mem_cmd_fire) begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire) begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid) begin
lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001);
if(io_mem_rsp_payload_error) begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if(io_cpu_fill_valid) begin
lineLoader_address <= io_cpu_fill_payload;
end
if(when_InstructionCache_l338) begin
lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01);
end
_zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6];
if(when_InstructionCache_l351) begin
lineLoader_flushCounter <= 7'h0;
end
if(when_InstructionCache_l435) begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if(when_InstructionCache_l459) begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess;
decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling;
decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation;
end
if(when_InstructionCache_l459_1) begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if(when_InstructionCache_l459_2) begin
decodeStage_hit_error <= fetchStage_hit_error;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// Life analysis checks
reg [15:0] life;
// Ding case
reg [7:0] din;
reg [15:0] fixin;
always @* begin
fixin = {din[7:0],din[7:0]};
case (din[1:0])
2'b00: begin
fixin = {fixin[14:0], 1'b1};
if (cyc==101) $display("Prevent ?: optimization a");
end
2'b01: begin
fixin = {fixin[13:0], 2'b11};
if (cyc==101) $display("Prevent ?: optimization b");
end
2'b10: begin
fixin = {fixin[12:0], 3'b111};
if (cyc==101) $display("Prevent ?: optimization c");
end
2'b11: begin
fixin = {fixin[11:0], 4'b1111};
if (cyc==101) $display("Prevent ?: optimization d");
end
endcase
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
life = 16'h8000; // Dropped
life = 16'h0010; // Used below
if (life != 16'h0010) $stop;
//
life = 16'h0020; // Used below
if ($time < 10000)
if (life != 16'h0020) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
if ($time != 0) $stop; // Prevent conversion to ?:
life = 16'h1030;
end
else
life = 16'h0030;
if (life != 16'h0030) $stop;
//
life = 16'h0040; // Not dropped, no else below
if ($time > 100000)
life = 16'h1040;
if (life != 16'h0040) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
life = 16'h1050;
if (life != 0) $stop; // Ignored, as set is first
end
else begin
if ($time > 100010)
life = 16'h1050;
else life = 16'h0050;
end
if (life != 16'h0050) $stop;
end
if (cyc==2) begin
din <= 8'haa;
end
if (cyc==3) begin
din <= 8'hfb;
if (fixin != 16'h5557) $stop;
end
if (cyc==4) begin
din <= 8'h5c;
if (fixin != 16'hbfbf) $stop;
end
if (cyc==5) begin
din <= 8'hed;
if (fixin != 16'hb8b9) $stop;
end
if (cyc==6) begin
if (fixin != 16'hb7b7) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_datactl(
input sys_clk,
input sdram_rst,
input read,
input write,
input [3:0] concerned_bank,
output reg read_safe,
output reg write_safe,
output [3:0] precharge_safe,
output reg ack,
output reg direction,
output direction_r,
input tim_cas,
input [1:0] tim_wr
);
/*
* read_safe: whether it is safe to register a Read command
* into the SDRAM at the next cycle.
*/
reg [2:0] read_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
read_safe_counter <= 3'd0;
read_safe <= 1'b1;
end else begin
if(read) begin
read_safe_counter <= 3'd4;
read_safe <= 1'b0;
end else if(write) begin
/* after a write, read is unsafe for 5 cycles (4 transfers + tWTR=1) */
read_safe_counter <= 3'd5;
read_safe <= 1'b0;
end else begin
if(read_safe_counter == 3'd1)
read_safe <= 1'b1;
if(~read_safe)
read_safe_counter <= read_safe_counter - 3'd1;
end
end
end
/*
* write_safe: whether it is safe to register a Write command
* into the SDRAM at the next cycle.
*/
reg [2:0] write_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
write_safe_counter <= 3'd0;
write_safe <= 1'b1;
end else begin
if(read) begin
write_safe_counter <= {1'b1, tim_cas, ~tim_cas};
write_safe <= 1'b0;
end else if(write) begin
write_safe_counter <= 3'd3;
write_safe <= 1'b0;
end else begin
if(write_safe_counter == 3'd1)
write_safe <= 1'b1;
if(~write_safe)
write_safe_counter <= write_safe_counter - 3'd1;
end
end
end
/* Generate ack signal.
* After write is asserted, it should pulse after 2 cycles.
* After read is asserted, it should pulse after CL+3 cycles, that is
* 5 cycles when tim_cas = 0
* 6 cycles when tim_cas = 1
*/
reg ack_read3;
reg ack_read2;
reg ack_read1;
reg ack_read0;
always @(posedge sys_clk) begin
if(sdram_rst) begin
ack_read3 <= 1'b0;
ack_read2 <= 1'b0;
ack_read1 <= 1'b0;
ack_read0 <= 1'b0;
end else begin
if(tim_cas) begin
ack_read3 <= read;
ack_read2 <= ack_read3;
ack_read1 <= ack_read2;
ack_read0 <= ack_read1;
end else begin
ack_read2 <= read;
ack_read1 <= ack_read2;
ack_read0 <= ack_read1;
end
end
end
reg ack0;
always @(posedge sys_clk) begin
if(sdram_rst) begin
ack0 <= 1'b0;
ack <= 1'b0;
end else begin
ack0 <= ack_read0|write;
ack <= ack0;
end
end
/* during a 4-word write, we drive the pins for 5 cycles
* and 1 cycle in advance (first word is invalid)
* so that we remove glitches on DQS without resorting
* to asynchronous logic.
*/
/* direction must be glitch-free, as it directly drives the
* tri-state enable for DQ and DQS.
*/
reg write_d;
reg [2:0] counter_writedirection;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter_writedirection <= 3'd0;
direction <= 1'b0;
end else begin
if(write_d) begin
counter_writedirection <= 3'b101;
direction <= 1'b1;
end else begin
if(counter_writedirection == 3'b001)
direction <= 1'b0;
if(direction)
counter_writedirection <= counter_writedirection - 3'd1;
end
end
end
assign direction_r = write_d|(|counter_writedirection);
always @(posedge sys_clk) begin
if(sdram_rst)
write_d <= 1'b0;
else
write_d <= write;
end
/* Counters that prevent a busy bank from being precharged */
hpdmc_banktimer banktimer0(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[0]),
.write(write & concerned_bank[0]),
.precharge_safe(precharge_safe[0])
);
hpdmc_banktimer banktimer1(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[1]),
.write(write & concerned_bank[1]),
.precharge_safe(precharge_safe[1])
);
hpdmc_banktimer banktimer2(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[2]),
.write(write & concerned_bank[2]),
.precharge_safe(precharge_safe[2])
);
hpdmc_banktimer banktimer3(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[3]),
.write(write & concerned_bank[3]),
.precharge_safe(precharge_safe[3])
);
endmodule
|
/****************************************************************************
MUL/DIV unit
Operation table
op sign dir
4 1 0 x | MULTU
6 1 1 x | MULT
0 0 0 0 | ShiftLeft
1 0 0 1 | ShiftRightLogic
3 0 1 1 | ShiftRightArith
****************************************************************************/
module mul(clk, resetn,
opA, opB, sa,
op,
en,
squashn,
shift_result,
hi, lo);
parameter WIDTH=32;
input clk;
input resetn;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
input [5-1:0] sa;
input [2:0] op;
input en;
input squashn;
output [WIDTH-1:0] shift_result;
output [WIDTH-1:0] hi;
output [WIDTH-1:0] lo;
/********* Control Signals *********/
wire is_signed,dir, is_mul;
assign is_mul=op[2]; // selects between opB and the computed shift amount
assign is_signed=op[1];
assign dir=op[0]; // selects between 2^sa and 2^(32-sa) for right shift
/********* Circuit Body *********/
wire dum,dum2,dum3;
wire [WIDTH:0] opB_mux_out;
wire [5-1:0] left_sa; // Amount of left shift required for both left/right
reg [WIDTH:0] decoded_sa;
assign opB_mux_out= (is_mul) ? {is_signed&opB[WIDTH-1],opB} : decoded_sa;
lpm_mult lpm_mult_component (
.sclr (~resetn),
.ce (1'b1),
.clk (clk),
.a ({is_signed&opA[WIDTH-1],opA}),
.b (opB_mux_out),
.p ({dum2,dum,hi,lo})
);
/*
lpm_mult lpm_mult_component (
.dataa ({is_signed&opA[WIDTH-1],opA}),
.datab (opB_mux_out),
.sum(),
.clock(clk),
.clken(en),
.aclr(~resetn),
.result ({dum2,dum,hi,lo}));
defparam
lpm_mult_component.lpm_widtha = WIDTH+1,
lpm_mult_component.lpm_widthb = WIDTH+1,
lpm_mult_component.lpm_widthp = 2*WIDTH+2,
lpm_mult_component.lpm_widths = 1,
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=6";
*/
wire shift_result_mux;
register shiftmux_reg((dir && |sa),clk,resetn,1'b1,shift_result_mux);
defparam shiftmux_reg.WIDTH=1;
assign shift_result= (shift_result_mux) ? hi : lo;
assign {dum3, left_sa}= (dir) ? 32-sa : {1'b0,sa};
always@(left_sa or dir)
begin
decoded_sa=0;
case(left_sa)
0: decoded_sa[0]=1;
1: decoded_sa[1]=1;
2: decoded_sa[2]=1;
3: decoded_sa[3]=1;
4: decoded_sa[4]=1;
5: decoded_sa[5]=1;
6: decoded_sa[6]=1;
7: decoded_sa[7]=1;
8: decoded_sa[8]=1;
9: decoded_sa[9]=1;
10: decoded_sa[10]=1;
11: decoded_sa[11]=1;
12: decoded_sa[12]=1;
13: decoded_sa[13]=1;
14: decoded_sa[14]=1;
15: decoded_sa[15]=1;
16: decoded_sa[16]=1;
17: decoded_sa[17]=1;
18: decoded_sa[18]=1;
19: decoded_sa[19]=1;
20: decoded_sa[20]=1;
21: decoded_sa[21]=1;
22: decoded_sa[22]=1;
23: decoded_sa[23]=1;
24: decoded_sa[24]=1;
25: decoded_sa[25]=1;
26: decoded_sa[26]=1;
27: decoded_sa[27]=1;
28: decoded_sa[28]=1;
29: decoded_sa[29]=1;
30: decoded_sa[30]=1;
31: decoded_sa[31]=1;
endcase
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Posted Packet Builder module. This module takes the
// length info from the Posted Packet Slicer, and requests a tag from
// the Tag Generator and uses that info to build a posted memory write header
// which it writes into a FIFO
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module posted_pkt_builder(
input clk,
input rst,
input [15:0] req_id, //from pcie block
//to/from posted_pkt_slicer
input posted_fifo_full,
input go,
output reg ack,
input [63:0] dmawad,
input [9:0] length,
//to posted_pkt_header_fifo
output reg [63:0] header_data_out,
output reg header_data_wren
);
//State machine states
localparam IDLE = 4'h0;
localparam HEAD1 = 4'h1;
localparam HEAD2 = 4'h2;
localparam WAIT_FOR_GO_DEASSERT = 4'h3;
//parameters used to define fixed header fields
localparam rsvd = 1'b0; //reserved and unused header fields to zero
localparam MWr = 5'b00000; //format for memory write header
localparam TC = 3'b000; //traffic class 0
localparam TD = 1'b0; //digest bit always 0
localparam EP = 1'b0; //poisoned bit always 0
localparam ATTR = 2'b00; //no snoop or relaxed-ordering
localparam LastBE = 4'b1111; //LastBE is always asserted since all transfers
//are on 128B boundaries and are always at least
//128B long
localparam FirstBE = 4'b1111;//FirstBE is always asserted since all transfers
//are on 128B boundaries
wire [1:0] fmt;
reg [3:0] state;
reg [63:0] dmawad_reg;
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
//if the upper DWord of the destination address is zero
//than make the format of the packet header 3DW; otherwise 4DW
assign fmt[1:0] = (dmawad_reg[63:32] == 0) ? 2'b10 : 2'b11;
//if the posted_pkt_slicer asserts "go" then register the dma write params
always@(posedge clk)begin
if(rst_reg)begin
dmawad_reg[63:0] <= 0;
end else if(go)begin
dmawad_reg <= dmawad;
end
end
// State machine
// Builds headers for posted memory writes
// Writes them into a FIFO
always @ (posedge clk) begin
if (rst_reg) begin
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
state <= IDLE;
end else begin
case (state)
IDLE : begin
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
if(go & ~posted_fifo_full) // Jiansong: prevent p_hdr_fifo overflow
state<= HEAD1;
else
state<= IDLE;
end
HEAD1 : begin
//write the first 64-bits of a posted header into the
//posted fifo
header_data_out <= {rsvd,fmt[1:0],MWr,rsvd,TC,rsvd,rsvd,rsvd,rsvd,
TD,EP,ATTR,rsvd,rsvd,length[9:0],req_id[15:0],
8'b00000000 ,LastBE,FirstBE};
ack <= 0;
header_data_wren <= 1'b1;
state <= HEAD2;
end
HEAD2 : begin
//write the next 32 or 64 bits of a posted header to the
//posted header fifo (32 if 3DW - 64 if 4DW header)
header_data_out <= (fmt[0]==1'b1)
? {dmawad_reg[63:2],2'b00}
: {dmawad_reg[31:2], 2'b00, dmawad_reg[63:32]};
header_data_wren <= 1'b1;
ack <= 1'b1; //acknowledge to the posted_packet_slicer that
//the packet has been queued up for transmission
state <= WAIT_FOR_GO_DEASSERT;
end
WAIT_FOR_GO_DEASSERT: begin
//ack causes "go" to deassert but we need to give the
//posted_pkt_slicer a chance to deassert "go" before returning
//to IDLE
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
state <= IDLE;
end
default : begin
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
state <= IDLE;
end
endcase
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:51:52 2016
/////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
input [1:0] r_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_exp_operation_A_S, intAS,
sign_final_result, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, DP_OP_42J154_122_8302_n26, DP_OP_42J154_122_8302_n25,
DP_OP_42J154_122_8302_n24, DP_OP_42J154_122_8302_n23,
DP_OP_42J154_122_8302_n22, DP_OP_42J154_122_8302_n21,
DP_OP_42J154_122_8302_n20, DP_OP_42J154_122_8302_n19,
DP_OP_42J154_122_8302_n18, DP_OP_42J154_122_8302_n17,
DP_OP_42J154_122_8302_n16, DP_OP_42J154_122_8302_n11,
DP_OP_42J154_122_8302_n10, DP_OP_42J154_122_8302_n9,
DP_OP_42J154_122_8302_n8, DP_OP_42J154_122_8302_n7,
DP_OP_42J154_122_8302_n6, DP_OP_42J154_122_8302_n5,
DP_OP_42J154_122_8302_n4, DP_OP_42J154_122_8302_n3,
DP_OP_42J154_122_8302_n2, DP_OP_42J154_122_8302_n1,
DP_OP_45J154_125_8406_n114, DP_OP_45J154_125_8406_n113,
DP_OP_45J154_125_8406_n112, DP_OP_45J154_125_8406_n111,
DP_OP_45J154_125_8406_n110, DP_OP_45J154_125_8406_n109,
DP_OP_45J154_125_8406_n108, DP_OP_45J154_125_8406_n107,
DP_OP_45J154_125_8406_n106, DP_OP_45J154_125_8406_n105,
DP_OP_45J154_125_8406_n104, DP_OP_45J154_125_8406_n103,
DP_OP_45J154_125_8406_n102, DP_OP_45J154_125_8406_n101,
DP_OP_45J154_125_8406_n100, DP_OP_45J154_125_8406_n99,
DP_OP_45J154_125_8406_n98, DP_OP_45J154_125_8406_n97,
DP_OP_45J154_125_8406_n96, DP_OP_45J154_125_8406_n95,
DP_OP_45J154_125_8406_n94, DP_OP_45J154_125_8406_n93,
DP_OP_45J154_125_8406_n92, DP_OP_45J154_125_8406_n91,
DP_OP_45J154_125_8406_n90, DP_OP_45J154_125_8406_n89,
DP_OP_45J154_125_8406_n88, DP_OP_45J154_125_8406_n87,
DP_OP_45J154_125_8406_n86, DP_OP_45J154_125_8406_n85,
DP_OP_45J154_125_8406_n84, DP_OP_45J154_125_8406_n83,
DP_OP_45J154_125_8406_n82, DP_OP_45J154_125_8406_n81,
DP_OP_45J154_125_8406_n80, DP_OP_45J154_125_8406_n79,
DP_OP_45J154_125_8406_n78, DP_OP_45J154_125_8406_n77,
DP_OP_45J154_125_8406_n76, DP_OP_45J154_125_8406_n75,
DP_OP_45J154_125_8406_n74, DP_OP_45J154_125_8406_n73,
DP_OP_45J154_125_8406_n72, DP_OP_45J154_125_8406_n71,
DP_OP_45J154_125_8406_n70, DP_OP_45J154_125_8406_n69,
DP_OP_45J154_125_8406_n68, DP_OP_45J154_125_8406_n67,
DP_OP_45J154_125_8406_n66, DP_OP_45J154_125_8406_n65,
DP_OP_45J154_125_8406_n64, DP_OP_45J154_125_8406_n63,
DP_OP_45J154_125_8406_n62, DP_OP_45J154_125_8406_n61,
DP_OP_45J154_125_8406_n60, DP_OP_45J154_125_8406_n55,
DP_OP_45J154_125_8406_n54, DP_OP_45J154_125_8406_n53,
DP_OP_45J154_125_8406_n52, DP_OP_45J154_125_8406_n51,
DP_OP_45J154_125_8406_n50, DP_OP_45J154_125_8406_n49,
DP_OP_45J154_125_8406_n48, DP_OP_45J154_125_8406_n47,
DP_OP_45J154_125_8406_n46, DP_OP_45J154_125_8406_n45,
DP_OP_45J154_125_8406_n44, DP_OP_45J154_125_8406_n43,
DP_OP_45J154_125_8406_n42, DP_OP_45J154_125_8406_n41,
DP_OP_45J154_125_8406_n40, DP_OP_45J154_125_8406_n39,
DP_OP_45J154_125_8406_n38, DP_OP_45J154_125_8406_n37,
DP_OP_45J154_125_8406_n36, DP_OP_45J154_125_8406_n35,
DP_OP_45J154_125_8406_n34, DP_OP_45J154_125_8406_n33,
DP_OP_45J154_125_8406_n32, DP_OP_45J154_125_8406_n31,
DP_OP_45J154_125_8406_n30, DP_OP_45J154_125_8406_n29,
DP_OP_45J154_125_8406_n28, DP_OP_45J154_125_8406_n27,
DP_OP_45J154_125_8406_n26, DP_OP_45J154_125_8406_n25,
DP_OP_45J154_125_8406_n24, DP_OP_45J154_125_8406_n23,
DP_OP_45J154_125_8406_n22, DP_OP_45J154_125_8406_n21,
DP_OP_45J154_125_8406_n20, DP_OP_45J154_125_8406_n19,
DP_OP_45J154_125_8406_n18, DP_OP_45J154_125_8406_n17,
DP_OP_45J154_125_8406_n16, DP_OP_45J154_125_8406_n15,
DP_OP_45J154_125_8406_n14, DP_OP_45J154_125_8406_n13,
DP_OP_45J154_125_8406_n12, DP_OP_45J154_125_8406_n11,
DP_OP_45J154_125_8406_n10, DP_OP_45J154_125_8406_n9,
DP_OP_45J154_125_8406_n8, DP_OP_45J154_125_8406_n7,
DP_OP_45J154_125_8406_n6, DP_OP_45J154_125_8406_n5,
DP_OP_45J154_125_8406_n4, DP_OP_45J154_125_8406_n3,
DP_OP_45J154_125_8406_n2, DP_OP_45J154_125_8406_n1, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1584, n1585, n1587, n1588, n1589,
n1590, n1591, n1592, n1593, n1594, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2098, n2099, n2100, n2101,
n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111,
n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121,
n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131,
n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141,
n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151,
n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161,
n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171,
n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181,
n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191,
n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201,
n2202, n2203, n2204, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865,
n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875,
n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885,
n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895,
n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995,
n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005,
n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015,
n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025,
n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035,
n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045,
n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055,
n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065,
n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075,
n3076, n3077;
wire [1:0] FSM_selector_B;
wire [63:0] intDX;
wire [63:0] intDY;
wire [62:0] DMP;
wire [62:0] DmP;
wire [10:0] exp_oper_result;
wire [10:0] S_Oper_A_exp;
wire [4:0] LZA_output;
wire [54:0] Add_Subt_result;
wire [54:0] Sgf_normalized_result;
wire [54:0] S_A_S_Oper_A;
wire [3:0] FS_Module_state_reg;
wire [10:0] Exp_Operation_Module_Data_S;
wire [54:0] Add_Subt_Sgf_module_S_to_D;
wire [93:0] Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_27_ ( .D(n1530), .CK(clk),
.RN(n3069), .QN(n1596) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n1508), .CK(clk),
.RN(n3065), .QN(n1609) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(n1500), .CK(
clk), .RN(n3061), .QN(n1603) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(n1498), .CK(
clk), .RN(n3061), .QN(n1589) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_5_ ( .D(n1496), .CK(
clk), .RN(n3064), .QN(n1608) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n1436), .CK(clk),
.RN(n3061), .QN(n1606) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_31_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .CK(clk), .RN(n3047),
.QN(n1594) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_30_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .CK(clk), .RN(n3047),
.QN(n1614) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_29_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .CK(clk), .RN(n1627),
.QN(n1613) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_28_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .CK(clk), .RN(n1627),
.QN(n1611) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_27_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .CK(clk), .RN(n1627),
.QN(n1615) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_26_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .CK(clk), .RN(n1627),
.QN(n1610) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n1627),
.QN(n1612) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n1627),
.QN(n1616) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n1627),
.QN(n1623) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n1627),
.QN(n1622) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n1627),
.QN(n1620) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n1627),
.QN(n1618) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n1627),
.QN(n1621) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n1627),
.QN(n1619) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n3063),
.QN(n1617) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n3048),
.QN(n1624) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n3048),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[62]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n3070),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[61]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[60]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[59]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[58]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[57]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[56]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[55]) );
DFFRXLTS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n1426), .CK(clk), .RN(
n3050), .Q(underflow_flag) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n1425),
.CK(clk), .RN(n3050), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n1424),
.CK(clk), .RN(n3050), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n1423),
.CK(clk), .RN(n3050), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n1422),
.CK(clk), .RN(n3050), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n1421),
.CK(clk), .RN(n3050), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n1420),
.CK(clk), .RN(n3050), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n1419),
.CK(clk), .RN(n3050), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n1418),
.CK(clk), .RN(n3050), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n1417),
.CK(clk), .RN(n3050), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n1416),
.CK(clk), .RN(n3050), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n1415),
.CK(clk), .RN(n1685), .Q(final_result_ieee[62]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n1414),
.CK(clk), .RN(n1685), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n1413),
.CK(clk), .RN(n3051), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n1412),
.CK(clk), .RN(n1580), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n1411),
.CK(clk), .RN(n1580), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n1410),
.CK(clk), .RN(n3051), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n1409),
.CK(clk), .RN(n3051), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n1408),
.CK(clk), .RN(n1685), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n1407),
.CK(clk), .RN(n1580), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n1406),
.CK(clk), .RN(n1580), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n1405),
.CK(clk), .RN(n3055), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n1404),
.CK(clk), .RN(n1685), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n1403),
.CK(clk), .RN(n1628), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n1402),
.CK(clk), .RN(n1628), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n1401),
.CK(clk), .RN(n1628), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n1400),
.CK(clk), .RN(n1628), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n1399),
.CK(clk), .RN(n1628), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n1398),
.CK(clk), .RN(n1628), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n1397),
.CK(clk), .RN(n1628), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n1396),
.CK(clk), .RN(n1628), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n1395),
.CK(clk), .RN(n1628), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n1394),
.CK(clk), .RN(n1628), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n1393),
.CK(clk), .RN(n1628), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n1392),
.CK(clk), .RN(n1628), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n1391),
.CK(clk), .RN(n3053), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n1390),
.CK(clk), .RN(n3058), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n1389),
.CK(clk), .RN(n3048), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n1388),
.CK(clk), .RN(n1627), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n1387),
.CK(clk), .RN(n3053), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n1386),
.CK(clk), .RN(n3046), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n1385),
.CK(clk), .RN(n3048), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n1384),
.CK(clk), .RN(n3056), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n1383),
.CK(clk), .RN(n3053), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n1382),
.CK(clk), .RN(n3060), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n1381),
.CK(clk), .RN(n3048), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n1380),
.CK(clk), .RN(n1580), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n1379),
.CK(clk), .RN(n3051), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n1378),
.CK(clk), .RN(n1580), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n1377),
.CK(clk), .RN(n1580), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n1376),
.CK(clk), .RN(n3049), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n1375),
.CK(clk), .RN(n1685), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n1374),
.CK(clk), .RN(n3051), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n1373),
.CK(clk), .RN(n1580), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n1372),
.CK(clk), .RN(n1685), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n1371),
.CK(clk), .RN(n3051), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n1370),
.CK(clk), .RN(n1580), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n1369),
.CK(clk), .RN(n1685), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n1368),
.CK(clk), .RN(n3051), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n1367),
.CK(clk), .RN(n1580), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n1366),
.CK(clk), .RN(n1685), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n1365),
.CK(clk), .RN(n3051), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n1364),
.CK(clk), .RN(n1580), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n1363),
.CK(clk), .RN(n1685), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n1361),
.CK(clk), .RN(n3051), .Q(final_result_ieee[63]) );
DFFRXLTS ASRegister_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n3054), .Q(intAS) );
DFFRXLTS YRegister_Q_reg_63_ ( .D(n1231), .CK(clk), .RN(n1582), .Q(intDY[63]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_61_ ( .D(n1230), .CK(clk),
.RN(n3063), .Q(DMP[61]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_60_ ( .D(n1229), .CK(clk),
.RN(n3071), .Q(DMP[60]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_59_ ( .D(n1228), .CK(clk),
.RN(n3062), .Q(DMP[59]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_58_ ( .D(n1227), .CK(clk),
.RN(n3057), .Q(DMP[58]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_57_ ( .D(n1226), .CK(clk),
.RN(n3068), .Q(DMP[57]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_56_ ( .D(n1225), .CK(clk),
.RN(n3067), .Q(DMP[56]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_55_ ( .D(n1224), .CK(clk),
.RN(n3062), .Q(DMP[55]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_54_ ( .D(n1223), .CK(clk),
.RN(n3064), .Q(DMP[54]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_53_ ( .D(n1222), .CK(clk),
.RN(n3068), .Q(DMP[53]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_52_ ( .D(n1221), .CK(clk),
.RN(n3070), .Q(DMP[52]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n1177), .CK(clk), .RN(
n3071), .Q(n1576) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_62_ ( .D(n1168), .CK(clk),
.RN(n3063), .Q(DMP[62]) );
DFFRXLTS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n1167), .CK(clk),
.RN(n3065), .Q(sign_final_result) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_61_ ( .D(n1166), .CK(clk),
.RN(n3064), .Q(DmP[61]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_60_ ( .D(n1165), .CK(clk),
.RN(n3062), .Q(DmP[60]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_59_ ( .D(n1164), .CK(clk),
.RN(n3071), .Q(DmP[59]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_58_ ( .D(n1163), .CK(clk),
.RN(n3070), .Q(DmP[58]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_57_ ( .D(n1162), .CK(clk),
.RN(n3047), .Q(DmP[57]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_56_ ( .D(n1161), .CK(clk),
.RN(n3061), .Q(DmP[56]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_55_ ( .D(n1160), .CK(clk),
.RN(n3061), .Q(DmP[55]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_54_ ( .D(n1159), .CK(clk),
.RN(n3061), .Q(DmP[54]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_53_ ( .D(n1158), .CK(clk),
.RN(n3061), .Q(DmP[53]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_52_ ( .D(n1157), .CK(clk),
.RN(n3061), .Q(DmP[52]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_51_ ( .D(n1156), .CK(clk),
.RN(n3069), .Q(DmP[51]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_50_ ( .D(n1155), .CK(clk),
.RN(n1582), .Q(DmP[50]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_49_ ( .D(n1154), .CK(clk),
.RN(n3066), .Q(DmP[49]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_48_ ( .D(n1153), .CK(clk),
.RN(n3056), .Q(DmP[48]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_47_ ( .D(n1152), .CK(clk),
.RN(n3059), .Q(DmP[47]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n1130), .CK(clk),
.RN(n3067), .Q(DmP[25]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n1122), .CK(clk),
.RN(n3067), .Q(DmP[17]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_62_ ( .D(n1104), .CK(clk),
.RN(n3071), .Q(DmP[62]) );
CMPR32X2TS DP_OP_42J154_122_8302_U12 ( .A(S_Oper_A_exp[0]), .B(
FSM_exp_operation_A_S), .C(DP_OP_42J154_122_8302_n26), .CO(
DP_OP_42J154_122_8302_n11), .S(Exp_Operation_Module_Data_S[0]) );
CMPR32X2TS DP_OP_42J154_122_8302_U11 ( .A(DP_OP_42J154_122_8302_n25), .B(
S_Oper_A_exp[1]), .C(DP_OP_42J154_122_8302_n11), .CO(
DP_OP_42J154_122_8302_n10), .S(Exp_Operation_Module_Data_S[1]) );
CMPR32X2TS DP_OP_42J154_122_8302_U10 ( .A(DP_OP_42J154_122_8302_n24), .B(
S_Oper_A_exp[2]), .C(DP_OP_42J154_122_8302_n10), .CO(
DP_OP_42J154_122_8302_n9), .S(Exp_Operation_Module_Data_S[2]) );
CMPR32X2TS DP_OP_42J154_122_8302_U9 ( .A(DP_OP_42J154_122_8302_n23), .B(
S_Oper_A_exp[3]), .C(DP_OP_42J154_122_8302_n9), .CO(
DP_OP_42J154_122_8302_n8), .S(Exp_Operation_Module_Data_S[3]) );
CMPR32X2TS DP_OP_42J154_122_8302_U8 ( .A(DP_OP_42J154_122_8302_n22), .B(
S_Oper_A_exp[4]), .C(DP_OP_42J154_122_8302_n8), .CO(
DP_OP_42J154_122_8302_n7), .S(Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS DP_OP_42J154_122_8302_U7 ( .A(DP_OP_42J154_122_8302_n21), .B(
S_Oper_A_exp[5]), .C(DP_OP_42J154_122_8302_n7), .CO(
DP_OP_42J154_122_8302_n6), .S(Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS DP_OP_42J154_122_8302_U6 ( .A(DP_OP_42J154_122_8302_n20), .B(
S_Oper_A_exp[6]), .C(DP_OP_42J154_122_8302_n6), .CO(
DP_OP_42J154_122_8302_n5), .S(Exp_Operation_Module_Data_S[6]) );
CMPR32X2TS DP_OP_42J154_122_8302_U5 ( .A(DP_OP_42J154_122_8302_n19), .B(
S_Oper_A_exp[7]), .C(DP_OP_42J154_122_8302_n5), .CO(
DP_OP_42J154_122_8302_n4), .S(Exp_Operation_Module_Data_S[7]) );
CMPR32X2TS DP_OP_42J154_122_8302_U4 ( .A(DP_OP_42J154_122_8302_n18), .B(
S_Oper_A_exp[8]), .C(DP_OP_42J154_122_8302_n4), .CO(
DP_OP_42J154_122_8302_n3), .S(Exp_Operation_Module_Data_S[8]) );
CMPR32X2TS DP_OP_42J154_122_8302_U3 ( .A(DP_OP_42J154_122_8302_n17), .B(
S_Oper_A_exp[9]), .C(DP_OP_42J154_122_8302_n3), .CO(
DP_OP_42J154_122_8302_n2), .S(Exp_Operation_Module_Data_S[9]) );
CMPR32X2TS DP_OP_42J154_122_8302_U2 ( .A(DP_OP_42J154_122_8302_n16), .B(
S_Oper_A_exp[10]), .C(DP_OP_42J154_122_8302_n2), .CO(
DP_OP_42J154_122_8302_n1), .S(Exp_Operation_Module_Data_S[10]) );
CMPR32X2TS DP_OP_45J154_125_8406_U56 ( .A(S_A_S_Oper_A[0]), .B(n3039), .C(
DP_OP_45J154_125_8406_n114), .CO(DP_OP_45J154_125_8406_n55), .S(
Add_Subt_Sgf_module_S_to_D[0]) );
CMPR32X2TS DP_OP_45J154_125_8406_U55 ( .A(DP_OP_45J154_125_8406_n113), .B(
S_A_S_Oper_A[1]), .C(DP_OP_45J154_125_8406_n55), .CO(
DP_OP_45J154_125_8406_n54), .S(Add_Subt_Sgf_module_S_to_D[1]) );
CMPR32X2TS DP_OP_45J154_125_8406_U54 ( .A(DP_OP_45J154_125_8406_n112), .B(
S_A_S_Oper_A[2]), .C(DP_OP_45J154_125_8406_n54), .CO(
DP_OP_45J154_125_8406_n53), .S(Add_Subt_Sgf_module_S_to_D[2]) );
CMPR32X2TS DP_OP_45J154_125_8406_U53 ( .A(DP_OP_45J154_125_8406_n111), .B(
S_A_S_Oper_A[3]), .C(DP_OP_45J154_125_8406_n53), .CO(
DP_OP_45J154_125_8406_n52), .S(Add_Subt_Sgf_module_S_to_D[3]) );
CMPR32X2TS DP_OP_45J154_125_8406_U52 ( .A(DP_OP_45J154_125_8406_n110), .B(
S_A_S_Oper_A[4]), .C(DP_OP_45J154_125_8406_n52), .CO(
DP_OP_45J154_125_8406_n51), .S(Add_Subt_Sgf_module_S_to_D[4]) );
CMPR32X2TS DP_OP_45J154_125_8406_U51 ( .A(DP_OP_45J154_125_8406_n109), .B(
S_A_S_Oper_A[5]), .C(DP_OP_45J154_125_8406_n51), .CO(
DP_OP_45J154_125_8406_n50), .S(Add_Subt_Sgf_module_S_to_D[5]) );
CMPR32X2TS DP_OP_45J154_125_8406_U50 ( .A(DP_OP_45J154_125_8406_n108), .B(
S_A_S_Oper_A[6]), .C(DP_OP_45J154_125_8406_n50), .CO(
DP_OP_45J154_125_8406_n49), .S(Add_Subt_Sgf_module_S_to_D[6]) );
CMPR32X2TS DP_OP_45J154_125_8406_U49 ( .A(DP_OP_45J154_125_8406_n107), .B(
S_A_S_Oper_A[7]), .C(DP_OP_45J154_125_8406_n49), .CO(
DP_OP_45J154_125_8406_n48), .S(Add_Subt_Sgf_module_S_to_D[7]) );
CMPR32X2TS DP_OP_45J154_125_8406_U48 ( .A(DP_OP_45J154_125_8406_n106), .B(
S_A_S_Oper_A[8]), .C(DP_OP_45J154_125_8406_n48), .CO(
DP_OP_45J154_125_8406_n47), .S(Add_Subt_Sgf_module_S_to_D[8]) );
CMPR32X2TS DP_OP_45J154_125_8406_U47 ( .A(DP_OP_45J154_125_8406_n105), .B(
S_A_S_Oper_A[9]), .C(DP_OP_45J154_125_8406_n47), .CO(
DP_OP_45J154_125_8406_n46), .S(Add_Subt_Sgf_module_S_to_D[9]) );
CMPR32X2TS DP_OP_45J154_125_8406_U46 ( .A(DP_OP_45J154_125_8406_n104), .B(
S_A_S_Oper_A[10]), .C(DP_OP_45J154_125_8406_n46), .CO(
DP_OP_45J154_125_8406_n45), .S(Add_Subt_Sgf_module_S_to_D[10]) );
CMPR32X2TS DP_OP_45J154_125_8406_U45 ( .A(DP_OP_45J154_125_8406_n103), .B(
S_A_S_Oper_A[11]), .C(DP_OP_45J154_125_8406_n45), .CO(
DP_OP_45J154_125_8406_n44), .S(Add_Subt_Sgf_module_S_to_D[11]) );
CMPR32X2TS DP_OP_45J154_125_8406_U44 ( .A(DP_OP_45J154_125_8406_n102), .B(
S_A_S_Oper_A[12]), .C(DP_OP_45J154_125_8406_n44), .CO(
DP_OP_45J154_125_8406_n43), .S(Add_Subt_Sgf_module_S_to_D[12]) );
CMPR32X2TS DP_OP_45J154_125_8406_U43 ( .A(DP_OP_45J154_125_8406_n101), .B(
S_A_S_Oper_A[13]), .C(DP_OP_45J154_125_8406_n43), .CO(
DP_OP_45J154_125_8406_n42), .S(Add_Subt_Sgf_module_S_to_D[13]) );
CMPR32X2TS DP_OP_45J154_125_8406_U42 ( .A(DP_OP_45J154_125_8406_n100), .B(
S_A_S_Oper_A[14]), .C(DP_OP_45J154_125_8406_n42), .CO(
DP_OP_45J154_125_8406_n41), .S(Add_Subt_Sgf_module_S_to_D[14]) );
CMPR32X2TS DP_OP_45J154_125_8406_U41 ( .A(DP_OP_45J154_125_8406_n99), .B(
S_A_S_Oper_A[15]), .C(DP_OP_45J154_125_8406_n41), .CO(
DP_OP_45J154_125_8406_n40), .S(Add_Subt_Sgf_module_S_to_D[15]) );
CMPR32X2TS DP_OP_45J154_125_8406_U40 ( .A(DP_OP_45J154_125_8406_n98), .B(
S_A_S_Oper_A[16]), .C(DP_OP_45J154_125_8406_n40), .CO(
DP_OP_45J154_125_8406_n39), .S(Add_Subt_Sgf_module_S_to_D[16]) );
CMPR32X2TS DP_OP_45J154_125_8406_U39 ( .A(DP_OP_45J154_125_8406_n97), .B(
S_A_S_Oper_A[17]), .C(DP_OP_45J154_125_8406_n39), .CO(
DP_OP_45J154_125_8406_n38), .S(Add_Subt_Sgf_module_S_to_D[17]) );
CMPR32X2TS DP_OP_45J154_125_8406_U38 ( .A(DP_OP_45J154_125_8406_n96), .B(
S_A_S_Oper_A[18]), .C(DP_OP_45J154_125_8406_n38), .CO(
DP_OP_45J154_125_8406_n37), .S(Add_Subt_Sgf_module_S_to_D[18]) );
CMPR32X2TS DP_OP_45J154_125_8406_U37 ( .A(DP_OP_45J154_125_8406_n95), .B(
S_A_S_Oper_A[19]), .C(DP_OP_45J154_125_8406_n37), .CO(
DP_OP_45J154_125_8406_n36), .S(Add_Subt_Sgf_module_S_to_D[19]) );
CMPR32X2TS DP_OP_45J154_125_8406_U36 ( .A(DP_OP_45J154_125_8406_n94), .B(
S_A_S_Oper_A[20]), .C(DP_OP_45J154_125_8406_n36), .CO(
DP_OP_45J154_125_8406_n35), .S(Add_Subt_Sgf_module_S_to_D[20]) );
CMPR32X2TS DP_OP_45J154_125_8406_U35 ( .A(DP_OP_45J154_125_8406_n93), .B(
S_A_S_Oper_A[21]), .C(DP_OP_45J154_125_8406_n35), .CO(
DP_OP_45J154_125_8406_n34), .S(Add_Subt_Sgf_module_S_to_D[21]) );
CMPR32X2TS DP_OP_45J154_125_8406_U34 ( .A(DP_OP_45J154_125_8406_n92), .B(
S_A_S_Oper_A[22]), .C(DP_OP_45J154_125_8406_n34), .CO(
DP_OP_45J154_125_8406_n33), .S(Add_Subt_Sgf_module_S_to_D[22]) );
CMPR32X2TS DP_OP_45J154_125_8406_U33 ( .A(DP_OP_45J154_125_8406_n91), .B(
S_A_S_Oper_A[23]), .C(DP_OP_45J154_125_8406_n33), .CO(
DP_OP_45J154_125_8406_n32), .S(Add_Subt_Sgf_module_S_to_D[23]) );
CMPR32X2TS DP_OP_45J154_125_8406_U32 ( .A(DP_OP_45J154_125_8406_n90), .B(
S_A_S_Oper_A[24]), .C(DP_OP_45J154_125_8406_n32), .CO(
DP_OP_45J154_125_8406_n31), .S(Add_Subt_Sgf_module_S_to_D[24]) );
CMPR32X2TS DP_OP_45J154_125_8406_U31 ( .A(DP_OP_45J154_125_8406_n89), .B(
S_A_S_Oper_A[25]), .C(DP_OP_45J154_125_8406_n31), .CO(
DP_OP_45J154_125_8406_n30), .S(Add_Subt_Sgf_module_S_to_D[25]) );
CMPR32X2TS DP_OP_45J154_125_8406_U30 ( .A(DP_OP_45J154_125_8406_n88), .B(
S_A_S_Oper_A[26]), .C(DP_OP_45J154_125_8406_n30), .CO(
DP_OP_45J154_125_8406_n29), .S(Add_Subt_Sgf_module_S_to_D[26]) );
CMPR32X2TS DP_OP_45J154_125_8406_U29 ( .A(DP_OP_45J154_125_8406_n87), .B(
S_A_S_Oper_A[27]), .C(DP_OP_45J154_125_8406_n29), .CO(
DP_OP_45J154_125_8406_n28), .S(Add_Subt_Sgf_module_S_to_D[27]) );
CMPR32X2TS DP_OP_45J154_125_8406_U28 ( .A(DP_OP_45J154_125_8406_n86), .B(
S_A_S_Oper_A[28]), .C(DP_OP_45J154_125_8406_n28), .CO(
DP_OP_45J154_125_8406_n27), .S(Add_Subt_Sgf_module_S_to_D[28]) );
CMPR32X2TS DP_OP_45J154_125_8406_U27 ( .A(DP_OP_45J154_125_8406_n85), .B(
S_A_S_Oper_A[29]), .C(DP_OP_45J154_125_8406_n27), .CO(
DP_OP_45J154_125_8406_n26), .S(Add_Subt_Sgf_module_S_to_D[29]) );
CMPR32X2TS DP_OP_45J154_125_8406_U26 ( .A(DP_OP_45J154_125_8406_n84), .B(
S_A_S_Oper_A[30]), .C(DP_OP_45J154_125_8406_n26), .CO(
DP_OP_45J154_125_8406_n25), .S(Add_Subt_Sgf_module_S_to_D[30]) );
CMPR32X2TS DP_OP_45J154_125_8406_U25 ( .A(DP_OP_45J154_125_8406_n83), .B(
S_A_S_Oper_A[31]), .C(DP_OP_45J154_125_8406_n25), .CO(
DP_OP_45J154_125_8406_n24), .S(Add_Subt_Sgf_module_S_to_D[31]) );
CMPR32X2TS DP_OP_45J154_125_8406_U24 ( .A(DP_OP_45J154_125_8406_n82), .B(
S_A_S_Oper_A[32]), .C(DP_OP_45J154_125_8406_n24), .CO(
DP_OP_45J154_125_8406_n23), .S(Add_Subt_Sgf_module_S_to_D[32]) );
CMPR32X2TS DP_OP_45J154_125_8406_U23 ( .A(DP_OP_45J154_125_8406_n81), .B(
S_A_S_Oper_A[33]), .C(DP_OP_45J154_125_8406_n23), .CO(
DP_OP_45J154_125_8406_n22), .S(Add_Subt_Sgf_module_S_to_D[33]) );
CMPR32X2TS DP_OP_45J154_125_8406_U22 ( .A(DP_OP_45J154_125_8406_n80), .B(
S_A_S_Oper_A[34]), .C(DP_OP_45J154_125_8406_n22), .CO(
DP_OP_45J154_125_8406_n21), .S(Add_Subt_Sgf_module_S_to_D[34]) );
CMPR32X2TS DP_OP_45J154_125_8406_U21 ( .A(DP_OP_45J154_125_8406_n79), .B(
S_A_S_Oper_A[35]), .C(DP_OP_45J154_125_8406_n21), .CO(
DP_OP_45J154_125_8406_n20), .S(Add_Subt_Sgf_module_S_to_D[35]) );
CMPR32X2TS DP_OP_45J154_125_8406_U20 ( .A(DP_OP_45J154_125_8406_n78), .B(
S_A_S_Oper_A[36]), .C(DP_OP_45J154_125_8406_n20), .CO(
DP_OP_45J154_125_8406_n19), .S(Add_Subt_Sgf_module_S_to_D[36]) );
CMPR32X2TS DP_OP_45J154_125_8406_U19 ( .A(DP_OP_45J154_125_8406_n77), .B(
S_A_S_Oper_A[37]), .C(DP_OP_45J154_125_8406_n19), .CO(
DP_OP_45J154_125_8406_n18), .S(Add_Subt_Sgf_module_S_to_D[37]) );
CMPR32X2TS DP_OP_45J154_125_8406_U18 ( .A(DP_OP_45J154_125_8406_n76), .B(
S_A_S_Oper_A[38]), .C(DP_OP_45J154_125_8406_n18), .CO(
DP_OP_45J154_125_8406_n17), .S(Add_Subt_Sgf_module_S_to_D[38]) );
CMPR32X2TS DP_OP_45J154_125_8406_U17 ( .A(DP_OP_45J154_125_8406_n75), .B(
S_A_S_Oper_A[39]), .C(DP_OP_45J154_125_8406_n17), .CO(
DP_OP_45J154_125_8406_n16), .S(Add_Subt_Sgf_module_S_to_D[39]) );
CMPR32X2TS DP_OP_45J154_125_8406_U16 ( .A(DP_OP_45J154_125_8406_n74), .B(
S_A_S_Oper_A[40]), .C(DP_OP_45J154_125_8406_n16), .CO(
DP_OP_45J154_125_8406_n15), .S(Add_Subt_Sgf_module_S_to_D[40]) );
CMPR32X2TS DP_OP_45J154_125_8406_U15 ( .A(DP_OP_45J154_125_8406_n73), .B(
S_A_S_Oper_A[41]), .C(DP_OP_45J154_125_8406_n15), .CO(
DP_OP_45J154_125_8406_n14), .S(Add_Subt_Sgf_module_S_to_D[41]) );
CMPR32X2TS DP_OP_45J154_125_8406_U14 ( .A(DP_OP_45J154_125_8406_n72), .B(
S_A_S_Oper_A[42]), .C(DP_OP_45J154_125_8406_n14), .CO(
DP_OP_45J154_125_8406_n13), .S(Add_Subt_Sgf_module_S_to_D[42]) );
CMPR32X2TS DP_OP_45J154_125_8406_U13 ( .A(DP_OP_45J154_125_8406_n71), .B(
S_A_S_Oper_A[43]), .C(DP_OP_45J154_125_8406_n13), .CO(
DP_OP_45J154_125_8406_n12), .S(Add_Subt_Sgf_module_S_to_D[43]) );
CMPR32X2TS DP_OP_45J154_125_8406_U12 ( .A(DP_OP_45J154_125_8406_n70), .B(
S_A_S_Oper_A[44]), .C(DP_OP_45J154_125_8406_n12), .CO(
DP_OP_45J154_125_8406_n11), .S(Add_Subt_Sgf_module_S_to_D[44]) );
CMPR32X2TS DP_OP_45J154_125_8406_U11 ( .A(DP_OP_45J154_125_8406_n69), .B(
S_A_S_Oper_A[45]), .C(DP_OP_45J154_125_8406_n11), .CO(
DP_OP_45J154_125_8406_n10), .S(Add_Subt_Sgf_module_S_to_D[45]) );
CMPR32X2TS DP_OP_45J154_125_8406_U10 ( .A(DP_OP_45J154_125_8406_n68), .B(
S_A_S_Oper_A[46]), .C(DP_OP_45J154_125_8406_n10), .CO(
DP_OP_45J154_125_8406_n9), .S(Add_Subt_Sgf_module_S_to_D[46]) );
CMPR32X2TS DP_OP_45J154_125_8406_U9 ( .A(DP_OP_45J154_125_8406_n67), .B(
S_A_S_Oper_A[47]), .C(DP_OP_45J154_125_8406_n9), .CO(
DP_OP_45J154_125_8406_n8), .S(Add_Subt_Sgf_module_S_to_D[47]) );
CMPR32X2TS DP_OP_45J154_125_8406_U8 ( .A(DP_OP_45J154_125_8406_n66), .B(
S_A_S_Oper_A[48]), .C(DP_OP_45J154_125_8406_n8), .CO(
DP_OP_45J154_125_8406_n7), .S(Add_Subt_Sgf_module_S_to_D[48]) );
CMPR32X2TS DP_OP_45J154_125_8406_U7 ( .A(DP_OP_45J154_125_8406_n65), .B(
S_A_S_Oper_A[49]), .C(DP_OP_45J154_125_8406_n7), .CO(
DP_OP_45J154_125_8406_n6), .S(Add_Subt_Sgf_module_S_to_D[49]) );
CMPR32X2TS DP_OP_45J154_125_8406_U6 ( .A(DP_OP_45J154_125_8406_n64), .B(
S_A_S_Oper_A[50]), .C(DP_OP_45J154_125_8406_n6), .CO(
DP_OP_45J154_125_8406_n5), .S(Add_Subt_Sgf_module_S_to_D[50]) );
CMPR32X2TS DP_OP_45J154_125_8406_U5 ( .A(DP_OP_45J154_125_8406_n63), .B(
S_A_S_Oper_A[51]), .C(DP_OP_45J154_125_8406_n5), .CO(
DP_OP_45J154_125_8406_n4), .S(Add_Subt_Sgf_module_S_to_D[51]) );
CMPR32X2TS DP_OP_45J154_125_8406_U4 ( .A(DP_OP_45J154_125_8406_n62), .B(
S_A_S_Oper_A[52]), .C(DP_OP_45J154_125_8406_n4), .CO(
DP_OP_45J154_125_8406_n3), .S(Add_Subt_Sgf_module_S_to_D[52]) );
CMPR32X2TS DP_OP_45J154_125_8406_U3 ( .A(DP_OP_45J154_125_8406_n61), .B(
S_A_S_Oper_A[53]), .C(DP_OP_45J154_125_8406_n3), .CO(
DP_OP_45J154_125_8406_n2), .S(Add_Subt_Sgf_module_S_to_D[53]) );
CMPR32X2TS DP_OP_45J154_125_8406_U2 ( .A(DP_OP_45J154_125_8406_n60), .B(
S_A_S_Oper_A[54]), .C(DP_OP_45J154_125_8406_n2), .CO(
DP_OP_45J154_125_8406_n1), .S(Add_Subt_Sgf_module_S_to_D[54]) );
DFFRX1TS Sel_B_Q_reg_1_ ( .D(n1439), .CK(clk), .RN(n1360), .Q(
FSM_selector_B[1]), .QN(n3037) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n1503), .CK(clk),
.RN(n3061), .Q(Add_Subt_result[0]), .QN(n3036) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n1504), .CK(clk),
.RN(n3061), .Q(Add_Subt_result[1]), .QN(n3035) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_53_ ( .D(n1495), .CK(clk),
.RN(n1580), .Q(Sgf_normalized_result[53]), .QN(n3034) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n1505), .CK(clk),
.RN(n3058), .Q(Add_Subt_result[2]), .QN(n3033) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_51_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[90]), .QN(n3031) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_52_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[52]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[91]), .QN(n3030) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_50_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[89]), .QN(n3029) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_53_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[53]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[92]), .QN(n3028) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_49_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .CK(clk), .RN(n3049),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[88]), .QN(n3027) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_54_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[54]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[93]), .QN(n3026) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_48_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .CK(clk), .RN(n3050),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[87]), .QN(n3025) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n1494), .CK(clk),
.RN(n3069), .Q(Sgf_normalized_result[52]), .QN(n3024) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n1509), .CK(clk),
.RN(n3066), .Q(Add_Subt_result[6]), .QN(n3016) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n1506), .CK(clk),
.RN(n3056), .Q(Add_Subt_result[3]), .QN(n3014) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n1490), .CK(clk),
.RN(n3058), .Q(Sgf_normalized_result[48]), .QN(n3005) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n1489), .CK(clk),
.RN(n3069), .Q(Sgf_normalized_result[47]), .QN(n2995) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n1488), .CK(clk),
.RN(n3057), .Q(Sgf_normalized_result[46]), .QN(n2994) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n1487), .CK(clk),
.RN(n3068), .Q(Sgf_normalized_result[45]), .QN(n2983) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n1486), .CK(clk),
.RN(n3071), .Q(Sgf_normalized_result[44]), .QN(n2982) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n1485), .CK(clk),
.RN(n3062), .Q(Sgf_normalized_result[43]), .QN(n2959) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n1483), .CK(clk),
.RN(n3068), .Q(Sgf_normalized_result[41]), .QN(n2954) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n1482), .CK(clk),
.RN(n3057), .Q(Sgf_normalized_result[40]), .QN(n2947) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n1481), .CK(clk),
.RN(n3068), .Q(Sgf_normalized_result[39]), .QN(n2946) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n1480), .CK(clk),
.RN(n3062), .Q(Sgf_normalized_result[38]), .QN(n2943) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n1479), .CK(clk),
.RN(n3067), .Q(Sgf_normalized_result[37]), .QN(n2942) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n1478), .CK(clk),
.RN(n3062), .Q(Sgf_normalized_result[36]), .QN(n2938) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n1477), .CK(clk),
.RN(n3057), .Q(Sgf_normalized_result[35]), .QN(n2937) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n1476), .CK(clk),
.RN(n3068), .Q(Sgf_normalized_result[34]), .QN(n2936) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n1475), .CK(clk),
.RN(n1582), .Q(Sgf_normalized_result[33]), .QN(n2935) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n1474), .CK(clk),
.RN(n3065), .Q(Sgf_normalized_result[32]), .QN(n2934) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n1557), .CK(clk), .RN(n1360), .Q(FSM_selector_C), .QN(n2933) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n1472), .CK(clk),
.RN(n1582), .Q(Sgf_normalized_result[30]), .QN(n2932) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n1471), .CK(clk),
.RN(n1582), .Q(Sgf_normalized_result[29]), .QN(n2931) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n1470), .CK(clk),
.RN(n3065), .Q(Sgf_normalized_result[28]), .QN(n2928) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n1469), .CK(clk),
.RN(n3066), .Q(Sgf_normalized_result[27]), .QN(n2927) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n1467), .CK(clk),
.RN(n3056), .Q(Sgf_normalized_result[25]), .QN(n2925) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1464), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[22]), .QN(n2923) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1463), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[21]), .QN(n2922) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1462), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[20]), .QN(n2920) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1461), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[19]), .QN(n2919) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1460), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[18]), .QN(n2918) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1459), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[17]), .QN(n2917) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1458), .CK(clk),
.RN(n3064), .Q(Sgf_normalized_result[16]), .QN(n2915) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1457), .CK(clk),
.RN(n3071), .Q(Sgf_normalized_result[15]), .QN(n2914) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1456), .CK(clk),
.RN(n3070), .Q(Sgf_normalized_result[14]), .QN(n2913) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1455), .CK(clk),
.RN(n3064), .Q(Sgf_normalized_result[13]), .QN(n2911) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1454), .CK(clk),
.RN(n3061), .Q(Sgf_normalized_result[12]), .QN(n2910) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1453), .CK(clk),
.RN(n3049), .Q(Sgf_normalized_result[11]), .QN(n2909) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1452), .CK(clk),
.RN(n3059), .Q(Sgf_normalized_result[10]), .QN(n2908) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1450), .CK(clk),
.RN(n3056), .Q(Sgf_normalized_result[8]), .QN(n2905) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1449), .CK(clk),
.RN(n3066), .Q(Sgf_normalized_result[7]), .QN(n2904) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1448), .CK(clk),
.RN(n3062), .Q(Sgf_normalized_result[6]), .QN(n2903) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1443), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[1]), .QN(n2900) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n1511), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[8]), .QN(n2897) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1447), .CK(clk),
.RN(n3056), .Q(Sgf_normalized_result[5]), .QN(n2880) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1446), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[4]), .QN(n2879) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1445), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[3]), .QN(n2878) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1444), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[2]), .QN(n2877) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1442), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[0]), .QN(n2876) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n1468), .CK(clk),
.RN(n3063), .Q(Sgf_normalized_result[26]), .QN(n2872) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n1466), .CK(clk),
.RN(n1582), .Q(Sgf_normalized_result[24]), .QN(n2871) );
DFFRX2TS XRegister_Q_reg_15_ ( .D(n1312), .CK(clk), .RN(n3047), .Q(intDX[15]), .QN(n3077) );
DFFRX2TS XRegister_Q_reg_11_ ( .D(n1308), .CK(clk), .RN(n1631), .Q(intDX[11]), .QN(n3042) );
DFFRX2TS XRegister_Q_reg_26_ ( .D(n1323), .CK(clk), .RN(n3056), .Q(intDX[26]), .QN(n3041) );
DFFRX2TS XRegister_Q_reg_25_ ( .D(n1322), .CK(clk), .RN(n3048), .Q(intDX[25]), .QN(n3040) );
DFFRX2TS XRegister_Q_reg_23_ ( .D(n1320), .CK(clk), .RN(n1580), .Q(intDX[23]), .QN(n3075) );
DFFRX2TS XRegister_Q_reg_31_ ( .D(n1328), .CK(clk), .RN(n3053), .Q(intDX[31]), .QN(n3074) );
DFFRX2TS XRegister_Q_reg_55_ ( .D(n1352), .CK(clk), .RN(n1580), .Q(intDX[55]), .QN(n3072) );
DFFRX2TS XRegister_Q_reg_53_ ( .D(n1350), .CK(clk), .RN(n3052), .Q(intDX[53]), .QN(n3073) );
DFFRX2TS XRegister_Q_reg_50_ ( .D(n1347), .CK(clk), .RN(n3052), .Q(intDX[50]), .QN(n3045) );
DFFRX2TS XRegister_Q_reg_18_ ( .D(n1315), .CK(clk), .RN(n1631), .Q(intDX[18]), .QN(n3076) );
DFFRX2TS XRegister_Q_reg_17_ ( .D(n1314), .CK(clk), .RN(n1631), .Q(intDX[17]), .QN(n3043) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n1493), .CK(clk),
.RN(n3058), .Q(Sgf_normalized_result[51]), .QN(n3023) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n1492), .CK(clk),
.RN(n3058), .Q(Sgf_normalized_result[50]), .QN(n3018) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n1491), .CK(clk),
.RN(n3069), .Q(Sgf_normalized_result[49]), .QN(n3006) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n1473), .CK(clk),
.RN(n3066), .Q(Sgf_normalized_result[31]), .QN(n2874) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1465), .CK(clk),
.RN(n3057), .Q(Sgf_normalized_result[23]), .QN(n2870) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n1512), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[9]), .QN(n3004) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_47_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[86]), .QN(n3032) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n1513), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[10]), .QN(n3017) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n1515), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[12]), .QN(n3015) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n1517), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[14]) );
DFFRX1TS XRegister_Q_reg_40_ ( .D(n1337), .CK(clk), .RN(n3053), .Q(intDX[40]), .QN(n2991) );
DFFRX1TS XRegister_Q_reg_24_ ( .D(n1321), .CK(clk), .RN(n3047), .Q(intDX[24]), .QN(n2972) );
DFFRX1TS XRegister_Q_reg_10_ ( .D(n1307), .CK(clk), .RN(n1631), .Q(intDX[10]), .QN(n2978) );
DFFRX1TS XRegister_Q_reg_9_ ( .D(n1306), .CK(clk), .RN(n1631), .Q(intDX[9]),
.QN(n2886) );
DFFRX1TS XRegister_Q_reg_44_ ( .D(n1341), .CK(clk), .RN(n3062), .Q(intDX[44]), .QN(n2990) );
DFFRX1TS XRegister_Q_reg_47_ ( .D(n1344), .CK(clk), .RN(n3052), .Q(intDX[47]), .QN(n2888) );
DFFRX1TS XRegister_Q_reg_32_ ( .D(n1329), .CK(clk), .RN(n3048), .Q(intDX[32]), .QN(n2969) );
DFFRX1TS XRegister_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n3054), .Q(intDX[7]),
.QN(n2955) );
DFFRX1TS XRegister_Q_reg_62_ ( .D(n1359), .CK(clk), .RN(n1580), .Q(intDX[62]), .QN(n2894) );
DFFRX1TS XRegister_Q_reg_61_ ( .D(n1358), .CK(clk), .RN(n1685), .Q(intDX[61]), .QN(n2965) );
DFFRX1TS XRegister_Q_reg_56_ ( .D(n1353), .CK(clk), .RN(n3052), .Q(intDX[56]), .QN(n2966) );
DFFRX1TS XRegister_Q_reg_52_ ( .D(n1349), .CK(clk), .RN(n3052), .Q(intDX[52]), .QN(n2968) );
DFFRX1TS XRegister_Q_reg_48_ ( .D(n1345), .CK(clk), .RN(n3052), .Q(intDX[48]), .QN(n2988) );
DFFRX1TS XRegister_Q_reg_38_ ( .D(n1335), .CK(clk), .RN(n3048), .Q(intDX[38]), .QN(n2992) );
DFFRX1TS XRegister_Q_reg_6_ ( .D(n1303), .CK(clk), .RN(n3054), .Q(intDX[6]),
.QN(n2979) );
DFFRX1TS XRegister_Q_reg_39_ ( .D(n1336), .CK(clk), .RN(n3054), .Q(intDX[39]), .QN(n2889) );
DFFRX1TS XRegister_Q_reg_37_ ( .D(n1334), .CK(clk), .RN(n3053), .Q(intDX[37]), .QN(n2890) );
DFFRX1TS XRegister_Q_reg_16_ ( .D(n1313), .CK(clk), .RN(n1631), .Q(intDX[16]), .QN(n2975) );
DFFRX1TS XRegister_Q_reg_5_ ( .D(n1302), .CK(clk), .RN(n3054), .Q(intDX[5]),
.QN(n2884) );
DFFRX1TS XRegister_Q_reg_4_ ( .D(n1301), .CK(clk), .RN(n3054), .Q(intDX[4]),
.QN(n2980) );
DFFRX1TS XRegister_Q_reg_2_ ( .D(n1299), .CK(clk), .RN(n3054), .Q(intDX[2]),
.QN(n2887) );
DFFRX1TS XRegister_Q_reg_1_ ( .D(n1298), .CK(clk), .RN(n3054), .Q(intDX[1]),
.QN(n2893) );
DFFRX1TS XRegister_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n3054), .Q(intDX[0]),
.QN(n2964) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n1518), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[15]), .QN(n3022) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n1519), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[16]), .QN(n2875) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(n1521), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[18]), .QN(n3021) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(n1523), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[20]), .QN(n3012) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(n1526), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[23]), .QN(n2882) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(n1527), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[24]), .QN(n3008) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(n1528), .CK(clk),
.RN(n3069), .Q(Add_Subt_result[25]), .QN(n2930) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_26_ ( .D(n1529), .CK(clk),
.RN(n3058), .Q(Add_Subt_result[26]), .QN(n3010) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_28_ ( .D(n1531), .CK(clk),
.RN(n3069), .Q(Add_Subt_result[28]), .QN(n2926) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_30_ ( .D(n1533), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[30]), .QN(n2924) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_32_ ( .D(n1535), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[32]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_33_ ( .D(n1536), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[33]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_34_ ( .D(n1537), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[34]), .QN(n2921) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_35_ ( .D(n1538), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[35]), .QN(n3020) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_36_ ( .D(n1539), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[36]), .QN(n2916) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_37_ ( .D(n1540), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[37]), .QN(n3013) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_38_ ( .D(n1541), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[38]), .QN(n3011) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_39_ ( .D(n1542), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[39]), .QN(n2912) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_53_ ( .D(n1556), .CK(clk),
.RN(n1582), .Q(Add_Subt_result[53]), .QN(n2899) );
DFFRX2TS Sel_B_Q_reg_0_ ( .D(n1440), .CK(clk), .RN(n1360), .Q(
FSM_selector_B[0]), .QN(n2953) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n1507), .CK(clk),
.RN(n3056), .Q(Add_Subt_result[4]), .QN(n3019) );
DFFRX2TS YRegister_Q_reg_61_ ( .D(n1293), .CK(clk), .RN(n3055), .Q(intDY[61]), .QN(n2941) );
DFFRX2TS YRegister_Q_reg_48_ ( .D(n1280), .CK(clk), .RN(n3069), .Q(intDY[48]), .QN(n2948) );
DFFRX2TS YRegister_Q_reg_44_ ( .D(n1276), .CK(clk), .RN(n3062), .Q(intDY[44]), .QN(n2944) );
DFFRX2TS YRegister_Q_reg_38_ ( .D(n1270), .CK(clk), .RN(n3050), .Q(intDY[38]), .QN(n2945) );
DFFRX2TS YRegister_Q_reg_37_ ( .D(n1269), .CK(clk), .RN(n1631), .Q(intDY[37]), .QN(n2951) );
DFFRX2TS YRegister_Q_reg_52_ ( .D(n1284), .CK(clk), .RN(n3055), .Q(intDY[52]), .QN(n2950) );
DFFRX2TS YRegister_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n3071), .Q(intDY[16]), .QN(n2956) );
DFFRX2TS YRegister_Q_reg_10_ ( .D(n1242), .CK(clk), .RN(n3064), .Q(intDY[10]), .QN(n2949) );
DFFRX2TS YRegister_Q_reg_7_ ( .D(n1239), .CK(clk), .RN(n3056), .Q(intDY[7]),
.QN(n2885) );
DFFRX2TS YRegister_Q_reg_6_ ( .D(n1238), .CK(clk), .RN(n3070), .Q(intDY[6]),
.QN(n2957) );
DFFRX2TS YRegister_Q_reg_5_ ( .D(n1237), .CK(clk), .RN(n3064), .Q(intDY[5]),
.QN(n2952) );
DFFRX2TS YRegister_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n1685), .Q(intDY[4]),
.QN(n2883) );
DFFRX2TS YRegister_Q_reg_1_ ( .D(n1233), .CK(clk), .RN(n1582), .Q(intDY[1]),
.QN(n2939) );
DFFRX2TS XRegister_Q_reg_34_ ( .D(n1331), .CK(clk), .RN(n1580), .Q(intDX[34]), .QN(n2892) );
DFFRX2TS XRegister_Q_reg_14_ ( .D(n1311), .CK(clk), .RN(n1631), .Q(intDX[14]), .QN(n2976) );
DFFRX2TS XRegister_Q_reg_13_ ( .D(n1310), .CK(clk), .RN(n1631), .Q(intDX[13]), .QN(n2962) );
DFFRX2TS XRegister_Q_reg_12_ ( .D(n1309), .CK(clk), .RN(n1631), .Q(intDX[12]), .QN(n2977) );
DFFRX2TS XRegister_Q_reg_8_ ( .D(n1305), .CK(clk), .RN(n3067), .Q(intDX[8]),
.QN(n2963) );
DFFRX2TS XRegister_Q_reg_46_ ( .D(n1343), .CK(clk), .RN(n3052), .Q(intDX[46]), .QN(n2989) );
DFFRX2TS XRegister_Q_reg_33_ ( .D(n1330), .CK(clk), .RN(n3053), .Q(intDX[33]), .QN(n3000) );
DFFRX2TS XRegister_Q_reg_30_ ( .D(n1327), .CK(clk), .RN(n3055), .Q(intDX[30]), .QN(n2970) );
DFFRX2TS XRegister_Q_reg_28_ ( .D(n1325), .CK(clk), .RN(n3048), .Q(intDX[28]), .QN(n2971) );
DFFRX2TS XRegister_Q_reg_27_ ( .D(n1324), .CK(clk), .RN(n1685), .Q(intDX[27]), .QN(n2984) );
DFFRX2TS XRegister_Q_reg_45_ ( .D(n1342), .CK(clk), .RN(n3052), .Q(intDX[45]), .QN(n2997) );
DFFRX2TS XRegister_Q_reg_42_ ( .D(n1339), .CK(clk), .RN(n3056), .Q(intDX[42]), .QN(n2891) );
DFFRX2TS XRegister_Q_reg_29_ ( .D(n1326), .CK(clk), .RN(n3053), .Q(intDX[29]), .QN(n2961) );
DFFRX2TS XRegister_Q_reg_22_ ( .D(n1319), .CK(clk), .RN(n3046), .Q(intDX[22]), .QN(n2973) );
DFFRX2TS XRegister_Q_reg_20_ ( .D(n1317), .CK(clk), .RN(n1631), .Q(intDX[20]), .QN(n2974) );
DFFRX2TS XRegister_Q_reg_60_ ( .D(n1357), .CK(clk), .RN(n3051), .Q(intDX[60]), .QN(n3001) );
DFFRX2TS XRegister_Q_reg_59_ ( .D(n1356), .CK(clk), .RN(n1580), .Q(intDX[59]), .QN(n2895) );
DFFRX2TS XRegister_Q_reg_58_ ( .D(n1355), .CK(clk), .RN(n1685), .Q(intDX[58]), .QN(n3002) );
DFFRX2TS XRegister_Q_reg_57_ ( .D(n1354), .CK(clk), .RN(n3051), .Q(intDX[57]), .QN(n2996) );
DFFRX2TS XRegister_Q_reg_54_ ( .D(n1351), .CK(clk), .RN(n3052), .Q(intDX[54]), .QN(n2967) );
DFFRX2TS XRegister_Q_reg_51_ ( .D(n1348), .CK(clk), .RN(n3052), .Q(intDX[51]), .QN(n2986) );
DFFRX2TS XRegister_Q_reg_43_ ( .D(n1340), .CK(clk), .RN(n1631), .Q(intDX[43]), .QN(n2998) );
DFFRX2TS XRegister_Q_reg_36_ ( .D(n1333), .CK(clk), .RN(n1627), .Q(intDX[36]), .QN(n3003) );
DFFRX2TS YRegister_Q_reg_62_ ( .D(n1294), .CK(clk), .RN(n3067), .Q(intDY[62]), .QN(n2993) );
DFFRX2TS XRegister_Q_reg_35_ ( .D(n1332), .CK(clk), .RN(n1628), .Q(intDX[35]), .QN(n2999) );
DFFRX2TS XRegister_Q_reg_21_ ( .D(n1318), .CK(clk), .RN(n3048), .Q(intDX[21]), .QN(n2981) );
DFFRX2TS XRegister_Q_reg_19_ ( .D(n1316), .CK(clk), .RN(n1631), .Q(intDX[19]), .QN(n2985) );
DFFRX2TS XRegister_Q_reg_3_ ( .D(n1300), .CK(clk), .RN(n3054), .Q(intDX[3]),
.QN(n2960) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n1558), .CK(clk), .RN(n3046), .Q(
FS_Module_state_reg[2]), .QN(n2940) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n1560), .CK(clk), .RN(n3046), .Q(
FS_Module_state_reg[0]), .QN(n2873) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n1561), .CK(clk), .RN(n3046), .Q(
FS_Module_state_reg[3]), .QN(n2929) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n1559), .CK(clk), .RN(n3046), .Q(
FS_Module_state_reg[1]), .QN(n2881) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_45_ ( .D(n1548), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[45]), .QN(n2896) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_50_ ( .D(n1553), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[50]), .QN(n3007) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_54_ ( .D(n1502), .CK(clk),
.RN(n3061), .Q(Add_Subt_result[54]), .QN(n2898) );
DFFRX2TS YRegister_Q_reg_55_ ( .D(n1287), .CK(clk), .RN(n3055), .Q(intDY[55]) );
DFFRX2TS YRegister_Q_reg_3_ ( .D(n1235), .CK(clk), .RN(n3070), .Q(intDY[3])
);
DFFRX2TS YRegister_Q_reg_35_ ( .D(n1267), .CK(clk), .RN(n1631), .Q(intDY[35]) );
DFFRX2TS YRegister_Q_reg_43_ ( .D(n1275), .CK(clk), .RN(n3050), .Q(intDY[43]) );
DFFRX2TS YRegister_Q_reg_53_ ( .D(n1285), .CK(clk), .RN(n3055), .Q(intDY[53]) );
DFFRX2TS YRegister_Q_reg_41_ ( .D(n1273), .CK(clk), .RN(n3050), .Q(intDY[41]) );
DFFRX2TS YRegister_Q_reg_15_ ( .D(n1247), .CK(clk), .RN(n1631), .Q(intDY[15]) );
DFFRX2TS YRegister_Q_reg_23_ ( .D(n1255), .CK(clk), .RN(n3055), .Q(intDY[23]) );
DFFRX2TS YRegister_Q_reg_31_ ( .D(n1263), .CK(clk), .RN(n1631), .Q(intDY[31]) );
DFFRX2TS YRegister_Q_reg_33_ ( .D(n1265), .CK(clk), .RN(n1631), .Q(intDY[33]) );
DFFRX2TS YRegister_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n3071), .Q(intDY[13]) );
DFFRX2TS YRegister_Q_reg_21_ ( .D(n1253), .CK(clk), .RN(n3060), .Q(intDY[21]) );
DFFRX2TS YRegister_Q_reg_29_ ( .D(n1261), .CK(clk), .RN(n1631), .Q(intDY[29]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_49_ ( .D(n1552), .CK(clk),
.RN(n1582), .Q(Add_Subt_result[49]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(n1525), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[22]) );
DFFRX2TS YRegister_Q_reg_46_ ( .D(n1278), .CK(clk), .RN(n3050), .Q(intDY[46]) );
DFFRX2TS YRegister_Q_reg_58_ ( .D(n1290), .CK(clk), .RN(n3055), .Q(intDY[58]) );
DFFRX2TS YRegister_Q_reg_60_ ( .D(n1292), .CK(clk), .RN(n3055), .Q(intDY[60]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_40_ ( .D(n1543), .CK(clk),
.RN(n3057), .Q(Add_Subt_result[40]) );
DFFRX2TS YRegister_Q_reg_11_ ( .D(n1243), .CK(clk), .RN(n1627), .Q(intDY[11]) );
DFFRX2TS YRegister_Q_reg_49_ ( .D(n1281), .CK(clk), .RN(n3065), .Q(intDY[49]) );
DFFRX2TS YRegister_Q_reg_18_ ( .D(n1250), .CK(clk), .RN(n3046), .Q(intDY[18]) );
DFFRX2TS YRegister_Q_reg_26_ ( .D(n1258), .CK(clk), .RN(n1631), .Q(intDY[26]) );
DFFRX2TS YRegister_Q_reg_39_ ( .D(n1271), .CK(clk), .RN(n1582), .Q(intDY[39]) );
DFFRX2TS YRegister_Q_reg_19_ ( .D(n1251), .CK(clk), .RN(n3058), .Q(intDY[19]) );
DFFRX2TS YRegister_Q_reg_27_ ( .D(n1259), .CK(clk), .RN(n1631), .Q(intDY[27]) );
DFFRX2TS YRegister_Q_reg_51_ ( .D(n1283), .CK(clk), .RN(n3055), .Q(intDY[51]) );
DFFRX2TS YRegister_Q_reg_8_ ( .D(n1240), .CK(clk), .RN(n3064), .Q(intDY[8])
);
DFFRX2TS YRegister_Q_reg_47_ ( .D(n1279), .CK(clk), .RN(n3065), .Q(intDY[47]) );
DFFRX2TS YRegister_Q_reg_9_ ( .D(n1241), .CK(clk), .RN(n3071), .Q(intDY[9])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_44_ ( .D(n1547), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[44]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n1510), .CK(clk),
.RN(n3065), .Q(Add_Subt_result[7]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_29_ ( .D(n1532), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[29]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_52_ ( .D(n1555), .CK(clk),
.RN(n3067), .Q(Add_Subt_result[52]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n1516), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[13]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_31_ ( .D(n1534), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[31]) );
DFFRX2TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(n1562), .CK(
clk), .RN(n3063), .Q(add_overflow_flag) );
DFFRX2TS YRegister_Q_reg_0_ ( .D(n1232), .CK(clk), .RN(n3066), .Q(intDY[0])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(n1524), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[21]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n1514), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[11]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(n1520), .CK(clk),
.RN(n3057), .Q(Add_Subt_result[17]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(n1522), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[19]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n1438), .CK(clk),
.RN(n3070), .Q(exp_oper_result[0]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n1435), .CK(clk),
.RN(n3071), .Q(exp_oper_result[3]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n1434), .CK(clk),
.RN(n3068), .Q(exp_oper_result[4]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n1433), .CK(clk),
.RN(n3057), .Q(exp_oper_result[5]) );
DFFRX1TS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n1427), .CK(clk), .RN(
n3049), .Q(overflow_flag) );
DFFRX1TS XRegister_Q_reg_63_ ( .D(n1296), .CK(clk), .RN(n3054), .Q(intDX[63]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(n1497), .CK(
clk), .RN(n3061), .Q(LZA_output[4]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_10_ ( .D(n1428), .CK(clk),
.RN(n3063), .Q(exp_oper_result[10]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_9_ ( .D(n1429), .CK(clk),
.RN(n3063), .Q(exp_oper_result[9]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_8_ ( .D(n1430), .CK(clk),
.RN(n3062), .Q(exp_oper_result[8]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n1431), .CK(clk),
.RN(n3067), .Q(exp_oper_result[7]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n1432), .CK(clk),
.RN(n3068), .Q(exp_oper_result[6]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n3064),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[67]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n1127), .CK(clk),
.RN(n3067), .Q(DmP[22]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n1129), .CK(clk),
.RN(n3067), .Q(DmP[24]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n1133), .CK(clk),
.RN(n3067), .Q(DmP[28]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_32_ ( .D(n1137), .CK(clk),
.RN(n1582), .Q(DmP[32]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_34_ ( .D(n1139), .CK(clk),
.RN(n1582), .Q(DmP[34]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_36_ ( .D(n1141), .CK(clk),
.RN(n3066), .Q(DmP[36]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_44_ ( .D(n1149), .CK(clk),
.RN(n3056), .Q(DmP[44]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n1170), .CK(clk), .RN(
n3063), .Q(DMP[1]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n1171), .CK(clk), .RN(
n3057), .Q(DMP[2]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n1173), .CK(clk), .RN(
n1582), .Q(DMP[4]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n1174), .CK(clk), .RN(
n1582), .Q(DMP[5]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n1175), .CK(clk), .RN(
n3065), .Q(DMP[6]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n1176), .CK(clk), .RN(
n3060), .Q(DMP[7]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n1181), .CK(clk),
.RN(n3070), .Q(DMP[12]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n1183), .CK(clk),
.RN(n3068), .Q(DMP[14]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_32_ ( .D(n1201), .CK(clk),
.RN(n3071), .Q(DMP[32]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_38_ ( .D(n1207), .CK(clk),
.RN(n3062), .Q(DMP[38]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_40_ ( .D(n1209), .CK(clk),
.RN(n3067), .Q(DMP[40]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_42_ ( .D(n1211), .CK(clk),
.RN(n3068), .Q(DMP[42]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_44_ ( .D(n1213), .CK(clk),
.RN(n3069), .Q(DMP[44]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_45_ ( .D(n1214), .CK(clk),
.RN(n3058), .Q(DMP[45]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_48_ ( .D(n1217), .CK(clk),
.RN(n3069), .Q(DMP[48]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_50_ ( .D(n1219), .CK(clk),
.RN(n3056), .Q(DMP[50]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n1106), .CK(clk), .RN(
n3058), .Q(DmP[1]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n1107), .CK(clk), .RN(
n3069), .Q(DmP[2]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n1109), .CK(clk), .RN(
n3058), .Q(DmP[4]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n1111), .CK(clk), .RN(
n3069), .Q(DmP[6]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n1112), .CK(clk), .RN(
n3058), .Q(DmP[7]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n1115), .CK(clk),
.RN(n3068), .Q(DmP[10]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n1119), .CK(clk),
.RN(n3057), .Q(DmP[14]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n1121), .CK(clk),
.RN(n3062), .Q(DmP[16]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_41_ ( .D(n1544), .CK(clk),
.RN(n3064), .Q(Add_Subt_result[41]) );
DFFRX2TS YRegister_Q_reg_57_ ( .D(n1289), .CK(clk), .RN(n3055), .Q(intDY[57]) );
DFFRX2TS YRegister_Q_reg_25_ ( .D(n1257), .CK(clk), .RN(n3063), .Q(intDY[25]) );
DFFRX2TS YRegister_Q_reg_17_ ( .D(n1249), .CK(clk), .RN(n3047), .Q(intDY[17]) );
DFFRX2TS YRegister_Q_reg_45_ ( .D(n1277), .CK(clk), .RN(n1582), .Q(intDY[45]) );
DFFRX2TS YRegister_Q_reg_24_ ( .D(n1256), .CK(clk), .RN(n3049), .Q(intDY[24]) );
DFFRX2TS YRegister_Q_reg_56_ ( .D(n1288), .CK(clk), .RN(n3055), .Q(intDY[56]) );
DFFRX2TS YRegister_Q_reg_36_ ( .D(n1268), .CK(clk), .RN(n1631), .Q(intDY[36]) );
DFFRX2TS YRegister_Q_reg_12_ ( .D(n1244), .CK(clk), .RN(n3070), .Q(intDY[12]) );
DFFRX2TS YRegister_Q_reg_54_ ( .D(n1286), .CK(clk), .RN(n3055), .Q(intDY[54]) );
DFFRX2TS YRegister_Q_reg_28_ ( .D(n1260), .CK(clk), .RN(n1631), .Q(intDY[28]) );
DFFRX2TS YRegister_Q_reg_20_ ( .D(n1252), .CK(clk), .RN(n3061), .Q(intDY[20]) );
DFFRX2TS YRegister_Q_reg_50_ ( .D(n1282), .CK(clk), .RN(n3055), .Q(intDY[50]) );
DFFRX2TS YRegister_Q_reg_42_ ( .D(n1274), .CK(clk), .RN(n3065), .Q(intDY[42]) );
DFFRX2TS YRegister_Q_reg_34_ ( .D(n1266), .CK(clk), .RN(n1631), .Q(intDY[34]) );
DFFRX2TS YRegister_Q_reg_14_ ( .D(n1246), .CK(clk), .RN(n1628), .Q(intDY[14]) );
DFFRX2TS YRegister_Q_reg_2_ ( .D(n1234), .CK(clk), .RN(n3058), .Q(intDY[2])
);
DFFRX2TS YRegister_Q_reg_30_ ( .D(n1262), .CK(clk), .RN(n1631), .Q(intDY[30]) );
DFFRX2TS YRegister_Q_reg_22_ ( .D(n1254), .CK(clk), .RN(n3063), .Q(intDY[22]) );
DFFRX2TS YRegister_Q_reg_59_ ( .D(n1291), .CK(clk), .RN(n3055), .Q(intDY[59]) );
DFFRX2TS YRegister_Q_reg_40_ ( .D(n1272), .CK(clk), .RN(n3065), .Q(intDY[40]) );
DFFRX2TS YRegister_Q_reg_32_ ( .D(n1264), .CK(clk), .RN(n1631), .Q(intDY[32]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_51_ ( .D(n1554), .CK(clk),
.RN(n1582), .Q(Add_Subt_result[51]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_48_ ( .D(n1551), .CK(clk),
.RN(n3059), .Q(Add_Subt_result[48]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_42_ ( .D(n1545), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[42]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_37_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[76]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_36_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[75]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_34_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[73]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_33_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[72]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_39_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[78]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_32_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[71]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_35_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[74]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_40_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[79]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_38_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[77]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_45_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[84]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_44_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[83]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_43_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[82]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_42_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[81]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_41_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .CK(clk), .RN(n3047),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[80]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_46_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .CK(clk), .RN(n3046),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[85]) );
DFFRXLTS XRegister_Q_reg_49_ ( .D(n1346), .CK(clk), .RN(n3052), .Q(intDX[49]), .QN(n3044) );
DFFRXLTS XRegister_Q_reg_41_ ( .D(n1338), .CK(clk), .RN(n3053), .Q(intDX[41]), .QN(n2987) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_54_ ( .D(n1563), .CK(clk),
.RN(n3049), .Q(Sgf_normalized_result[54]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(n1501), .CK(
clk), .RN(n3070), .Q(LZA_output[2]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_43_ ( .D(n1546), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[43]), .QN(n2907) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_46_ ( .D(n1549), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[46]), .QN(n3009) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_47_ ( .D(n1550), .CK(clk),
.RN(n3060), .Q(Add_Subt_result[47]), .QN(n2901) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n1188), .CK(clk),
.RN(n3070), .Q(DMP[19]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n1187), .CK(clk),
.RN(n3070), .Q(DMP[18]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n1186), .CK(clk),
.RN(n3070), .Q(DMP[17]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n1185), .CK(clk),
.RN(n3070), .Q(DMP[16]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n1184), .CK(clk),
.RN(n3070), .Q(DMP[15]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n1437), .CK(clk),
.RN(n3071), .QN(n1601) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n1580),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[70]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n3053),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[69]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n3068),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[68]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n3048),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[66]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n1580),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[65]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n3053),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[64]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n3061),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[63]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_46_ ( .D(n1151), .CK(clk),
.RN(n3065), .Q(DmP[46]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_45_ ( .D(n1150), .CK(clk),
.RN(n1582), .Q(DmP[45]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_43_ ( .D(n1148), .CK(clk),
.RN(n1582), .Q(DmP[43]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_42_ ( .D(n1147), .CK(clk),
.RN(n3066), .Q(DmP[42]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_41_ ( .D(n1146), .CK(clk),
.RN(n3056), .Q(DmP[41]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_40_ ( .D(n1145), .CK(clk),
.RN(n3061), .Q(DmP[40]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_39_ ( .D(n1144), .CK(clk),
.RN(n3065), .Q(DmP[39]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_38_ ( .D(n1143), .CK(clk),
.RN(n3071), .Q(DmP[38]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_37_ ( .D(n1142), .CK(clk),
.RN(n3066), .Q(DmP[37]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_35_ ( .D(n1140), .CK(clk),
.RN(n3056), .Q(DmP[35]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_33_ ( .D(n1138), .CK(clk),
.RN(n3069), .Q(DmP[33]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_31_ ( .D(n1136), .CK(clk),
.RN(n3071), .Q(DmP[31]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n1135), .CK(clk),
.RN(n3067), .Q(DmP[30]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n1134), .CK(clk),
.RN(n3071), .Q(DmP[29]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n1132), .CK(clk),
.RN(n3067), .Q(DmP[27]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n1131), .CK(clk),
.RN(n3071), .Q(DmP[26]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n1128), .CK(clk),
.RN(n3071), .Q(DmP[23]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n1126), .CK(clk),
.RN(n3067), .Q(DmP[21]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n1125), .CK(clk),
.RN(n3071), .Q(DmP[20]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n1124), .CK(clk),
.RN(n3057), .Q(DmP[19]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n1123), .CK(clk),
.RN(n3062), .Q(DmP[18]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_51_ ( .D(n1220), .CK(clk),
.RN(n3071), .Q(DMP[51]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_49_ ( .D(n1218), .CK(clk),
.RN(n3058), .Q(DMP[49]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_47_ ( .D(n1216), .CK(clk),
.RN(n3069), .Q(DMP[47]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_46_ ( .D(n1215), .CK(clk),
.RN(n3058), .Q(DMP[46]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_43_ ( .D(n1212), .CK(clk),
.RN(n3067), .Q(DMP[43]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_39_ ( .D(n1208), .CK(clk),
.RN(n3057), .Q(DMP[39]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_37_ ( .D(n1206), .CK(clk),
.RN(n3068), .Q(DMP[37]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_36_ ( .D(n1205), .CK(clk),
.RN(n3071), .Q(DMP[36]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_35_ ( .D(n1204), .CK(clk),
.RN(n3062), .Q(DMP[35]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_34_ ( .D(n1203), .CK(clk),
.RN(n3057), .Q(DMP[34]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_33_ ( .D(n1202), .CK(clk),
.RN(n3068), .Q(DMP[33]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_31_ ( .D(n1200), .CK(clk),
.RN(n3065), .Q(DMP[31]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n1199), .CK(clk),
.RN(n1582), .Q(DMP[30]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n1198), .CK(clk),
.RN(n3055), .Q(DMP[29]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n1197), .CK(clk),
.RN(n3056), .Q(DMP[28]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n1196), .CK(clk),
.RN(n3066), .Q(DMP[27]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n1195), .CK(clk),
.RN(n1582), .Q(DMP[26]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n1194), .CK(clk),
.RN(n3070), .Q(DMP[25]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n1193), .CK(clk),
.RN(n3065), .Q(DMP[24]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n1191), .CK(clk),
.RN(n3060), .Q(DMP[22]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n1190), .CK(clk),
.RN(n3056), .Q(DMP[21]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n1189), .CK(clk),
.RN(n3066), .Q(DMP[20]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n1182), .CK(clk),
.RN(n3064), .Q(DMP[13]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n1180), .CK(clk),
.RN(n1628), .Q(DMP[11]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n1178), .CK(clk), .RN(
n3070), .Q(DMP[9]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n1172), .CK(clk), .RN(
n3071), .Q(DMP[3]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n1169), .CK(clk), .RN(
n3063), .Q(DMP[0]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n1120), .CK(clk),
.RN(n3068), .Q(DmP[15]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n1118), .CK(clk),
.RN(n3057), .Q(DmP[13]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n1117), .CK(clk),
.RN(n3062), .Q(DmP[12]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n1116), .CK(clk),
.RN(n3071), .Q(DmP[11]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n1114), .CK(clk), .RN(
n3068), .Q(DmP[9]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n1113), .CK(clk), .RN(
n3057), .Q(DmP[8]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n1110), .CK(clk), .RN(
n3058), .Q(DmP[5]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n1108), .CK(clk), .RN(
n3069), .Q(DmP[3]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n1105), .CK(clk), .RN(
n3058), .Q(DmP[0]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(n1499), .CK(
clk), .RN(n3046), .Q(LZA_output[0]), .QN(n3038) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n1484), .CK(clk),
.RN(n3057), .Q(Sgf_normalized_result[42]), .QN(n2958) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1451), .CK(clk),
.RN(n3065), .Q(Sgf_normalized_result[9]), .QN(n2906) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n1179), .CK(clk),
.RN(n3071), .Q(DMP[10]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_41_ ( .D(n1210), .CK(clk),
.RN(n3062), .Q(DMP[41]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n1192), .CK(clk),
.RN(n1582), .Q(DMP[23]) );
DFFRX4TS Sel_D_Q_reg_0_ ( .D(n1441), .CK(clk), .RN(n1360), .Q(n2869), .QN(
n2902) );
BUFX6TS U1759 ( .A(n1685), .Y(n3064) );
NAND2X4TS U1760 ( .A(n2164), .B(n2864), .Y(n2041) );
AOI222X1TS U1761 ( .A0(n2766), .A1(DmP[17]), .B0(Add_Subt_result[35]), .B1(
n2206), .C0(Add_Subt_result[19]), .C1(n2700), .Y(n1762) );
NOR2X6TS U1762 ( .A(n1776), .B(n1806), .Y(n2457) );
OR3X2TS U1763 ( .A(n1775), .B(n1841), .C(n1776), .Y(n2562) );
AND2X6TS U1764 ( .A(FSM_selector_C), .B(n1675), .Y(n2700) );
CLKINVX6TS U1765 ( .A(n2042), .Y(n2035) );
BUFX6TS U1766 ( .A(n2041), .Y(n1577) );
INVX4TS U1767 ( .A(n2581), .Y(n2753) );
INVX3TS U1768 ( .A(n2582), .Y(n1741) );
INVX6TS U1769 ( .A(n2590), .Y(n2671) );
INVX4TS U1770 ( .A(n2588), .Y(n1705) );
INVX6TS U1771 ( .A(n2483), .Y(n1578) );
INVX8TS U1772 ( .A(n1772), .Y(n1793) );
INVX6TS U1773 ( .A(n2485), .Y(n1770) );
BUFX4TS U1774 ( .A(n2575), .Y(n2574) );
INVX6TS U1775 ( .A(n2700), .Y(n1579) );
BUFX6TS U1776 ( .A(n3064), .Y(n1580) );
CLKINVX6TS U1777 ( .A(n2846), .Y(n1581) );
CLKBUFX2TS U1778 ( .A(n2987), .Y(n1652) );
CLKBUFX2TS U1779 ( .A(n3044), .Y(n1654) );
BUFX6TS U1780 ( .A(n1685), .Y(n1582) );
AOI211XLTS U1781 ( .A0(Add_Subt_result[2]), .A1(n2436), .B0(n2435), .C0(
n2434), .Y(n2438) );
AOI211XLTS U1782 ( .A0(Add_Subt_result[12]), .A1(n2401), .B0(n2830), .C0(
n2380), .Y(n2390) );
NOR3XLTS U1783 ( .A(n2375), .B(n2831), .C(n2380), .Y(n2371) );
NOR3X2TS U1784 ( .A(Add_Subt_result[22]), .B(Add_Subt_result[21]), .C(n2348),
.Y(n2424) );
INVX6TS U1785 ( .A(n2579), .Y(n2714) );
NAND2X4TS U1786 ( .A(n1767), .B(n1774), .Y(n1768) );
NOR2X4TS U1787 ( .A(n2114), .B(n2589), .Y(n1781) );
OR2X4TS U1788 ( .A(n2773), .B(n1770), .Y(n2483) );
OAI21X2TS U1789 ( .A0(n2926), .A1(n2723), .B0(n1736), .Y(n1602) );
INVX6TS U1790 ( .A(n2562), .Y(n1584) );
INVX6TS U1791 ( .A(n2467), .Y(n1585) );
OR2X2TS U1792 ( .A(n1673), .B(n1674), .Y(n1672) );
OAI21X2TS U1793 ( .A0(n2907), .A1(n1579), .B0(n1693), .Y(n1605) );
NOR2X4TS U1794 ( .A(n1776), .B(n1772), .Y(n1773) );
BUFX6TS U1795 ( .A(n1677), .Y(n2575) );
BUFX6TS U1796 ( .A(n1700), .Y(n2651) );
AO22X2TS U1797 ( .A0(n1637), .A1(n1686), .B0(exp_oper_result[5]), .B1(n2555),
.Y(n1776) );
CLKINVX6TS U1798 ( .A(n2902), .Y(n2572) );
OR2X2TS U1799 ( .A(n2881), .B(n1688), .Y(n1677) );
AND4X2TS U1800 ( .A(FS_Module_state_reg[0]), .B(n2929), .C(n2940), .D(n2881),
.Y(n2859) );
AND4X4TS U1801 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[3]), .D(n2881), .Y(n2846) );
NOR2X4TS U1802 ( .A(FSM_selector_B[1]), .B(n2953), .Y(n1686) );
BUFX6TS U1803 ( .A(n1685), .Y(n3070) );
BUFX6TS U1804 ( .A(n1685), .Y(n3071) );
INVX8TS U1805 ( .A(rst), .Y(n1631) );
CLKINVX6TS U1806 ( .A(rst), .Y(n1685) );
MX2X1TS U1807 ( .A(DMP[41]), .B(Sgf_normalized_result[43]), .S0(n2570), .Y(
S_A_S_Oper_A[43]) );
MX2X1TS U1808 ( .A(DMP[46]), .B(Sgf_normalized_result[48]), .S0(n2572), .Y(
S_A_S_Oper_A[48]) );
MX2X1TS U1809 ( .A(DMP[49]), .B(Sgf_normalized_result[51]), .S0(n2572), .Y(
S_A_S_Oper_A[51]) );
MX2X1TS U1810 ( .A(DMP[17]), .B(Sgf_normalized_result[19]), .S0(n2537), .Y(
S_A_S_Oper_A[19]) );
MX2X1TS U1811 ( .A(DMP[29]), .B(Sgf_normalized_result[31]), .S0(n2566), .Y(
S_A_S_Oper_A[31]) );
MX2X1TS U1812 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n2533), .Y(
S_A_S_Oper_A[13]) );
NOR2XLTS U1813 ( .A(n2911), .B(n2533), .Y(n2529) );
MX2X1TS U1814 ( .A(DMP[27]), .B(Sgf_normalized_result[29]), .S0(n2566), .Y(
S_A_S_Oper_A[29]) );
MX2X1TS U1815 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n2533), .Y(
S_A_S_Oper_A[7]) );
NOR2XLTS U1816 ( .A(n2904), .B(n2869), .Y(n2536) );
MX2X1TS U1817 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(n2566), .Y(
S_A_S_Oper_A[22]) );
NOR2XLTS U1818 ( .A(n2923), .B(n2537), .Y(n2520) );
NAND2BXLTS U1819 ( .AN(Sgf_normalized_result[54]), .B(n2572), .Y(
S_A_S_Oper_A[54]) );
MX2X1TS U1820 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n2533), .Y(
S_A_S_Oper_A[4]) );
NOR2XLTS U1821 ( .A(n2879), .B(n2869), .Y(n2540) );
MX2X1TS U1822 ( .A(DMP[23]), .B(Sgf_normalized_result[25]), .S0(n2566), .Y(
S_A_S_Oper_A[25]) );
MX2X1TS U1823 ( .A(DMP[44]), .B(Sgf_normalized_result[46]), .S0(n2570), .Y(
S_A_S_Oper_A[46]) );
MX2X1TS U1824 ( .A(DMP[39]), .B(Sgf_normalized_result[41]), .S0(n2570), .Y(
S_A_S_Oper_A[41]) );
MX2X1TS U1825 ( .A(DMP[15]), .B(Sgf_normalized_result[17]), .S0(n2537), .Y(
S_A_S_Oper_A[17]) );
NOR2XLTS U1826 ( .A(n2917), .B(n2537), .Y(n2525) );
MX2X1TS U1827 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n2533), .Y(
S_A_S_Oper_A[11]) );
NOR2XLTS U1828 ( .A(n2909), .B(n2533), .Y(n2531) );
MX2X1TS U1829 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n2537), .Y(
S_A_S_Oper_A[21]) );
NOR2XLTS U1830 ( .A(n2922), .B(n2537), .Y(n2521) );
MX2X1TS U1831 ( .A(DMP[42]), .B(Sgf_normalized_result[44]), .S0(n2570), .Y(
S_A_S_Oper_A[44]) );
MX2X1TS U1832 ( .A(DMP[47]), .B(Sgf_normalized_result[49]), .S0(n2572), .Y(
S_A_S_Oper_A[49]) );
MX2X1TS U1833 ( .A(DMP[51]), .B(Sgf_normalized_result[53]), .S0(n2572), .Y(
S_A_S_Oper_A[53]) );
MX2X1TS U1834 ( .A(DMP[37]), .B(Sgf_normalized_result[39]), .S0(n2570), .Y(
S_A_S_Oper_A[39]) );
MX2X1TS U1835 ( .A(DMP[35]), .B(Sgf_normalized_result[37]), .S0(n2570), .Y(
S_A_S_Oper_A[37]) );
MX2X1TS U1836 ( .A(DMP[33]), .B(Sgf_normalized_result[35]), .S0(n2566), .Y(
S_A_S_Oper_A[35]) );
MX2X1TS U1837 ( .A(DMP[31]), .B(Sgf_normalized_result[33]), .S0(n2566), .Y(
S_A_S_Oper_A[33]) );
MX2X1TS U1838 ( .A(DMP[26]), .B(Sgf_normalized_result[28]), .S0(n2566), .Y(
S_A_S_Oper_A[28]) );
MX2X1TS U1839 ( .A(DMP[24]), .B(Sgf_normalized_result[26]), .S0(n2566), .Y(
S_A_S_Oper_A[26]) );
MX2X1TS U1840 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n2566), .Y(
S_A_S_Oper_A[24]) );
MX2X1TS U1841 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n2537), .Y(
S_A_S_Oper_A[15]) );
NOR2XLTS U1842 ( .A(n2914), .B(n2537), .Y(n2527) );
MX2X1TS U1843 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n2533), .Y(
S_A_S_Oper_A[9]) );
NOR2XLTS U1844 ( .A(n2906), .B(n2533), .Y(n2534) );
MX2X1TS U1845 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n2537), .Y(
S_A_S_Oper_A[3]) );
MX2X1TS U1846 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(n2533), .Y(
S_A_S_Oper_A[6]) );
NOR2XLTS U1847 ( .A(n2903), .B(n2533), .Y(n2538) );
CLKAND2X2TS U1848 ( .A(n2570), .B(Sgf_normalized_result[1]), .Y(
S_A_S_Oper_A[1]) );
NOR2XLTS U1849 ( .A(n2869), .B(n2900), .Y(n2543) );
NAND2BXLTS U1850 ( .AN(intDY[2]), .B(intDX[2]), .Y(n1912) );
NAND2BXLTS U1851 ( .AN(intDY[51]), .B(intDX[51]), .Y(n2012) );
NAND2BXLTS U1852 ( .AN(intDY[19]), .B(intDX[19]), .Y(n1943) );
NAND2BXLTS U1853 ( .AN(intDY[27]), .B(intDX[27]), .Y(n1898) );
NAND2BXLTS U1854 ( .AN(intDY[9]), .B(intDX[9]), .Y(n1923) );
NAND2BXLTS U1855 ( .AN(intDY[13]), .B(intDX[13]), .Y(n1907) );
NAND2BXLTS U1856 ( .AN(intDY[21]), .B(intDX[21]), .Y(n1906) );
OAI221X1TS U1857 ( .A0(n1654), .A1(intDY[49]), .B0(n3045), .B1(intDY[50]),
.C0(n2278), .Y(n2281) );
NAND2BXLTS U1858 ( .AN(intDY[47]), .B(intDX[47]), .Y(n1974) );
NAND2BXLTS U1859 ( .AN(intDY[59]), .B(intDX[59]), .Y(n1963) );
NAND2BXLTS U1860 ( .AN(intDY[29]), .B(intDX[29]), .Y(n1896) );
NAND2BXLTS U1861 ( .AN(intDY[40]), .B(intDX[40]), .Y(n1891) );
NAND2BXLTS U1862 ( .AN(intDY[41]), .B(intDX[41]), .Y(n1892) );
NAND2BXLTS U1863 ( .AN(intDY[32]), .B(intDX[32]), .Y(n1893) );
AOI221X1TS U1864 ( .A0(n2891), .A1(intDY[42]), .B0(intDY[41]), .B1(n1652),
.C0(n2298), .Y(n2301) );
NAND3BXLTS U1865 ( .AN(n1667), .B(n2443), .C(n2926), .Y(n2363) );
MX2X1TS U1866 ( .A(DMP[45]), .B(Sgf_normalized_result[47]), .S0(n2572), .Y(
S_A_S_Oper_A[47]) );
AOI222X1TS U1867 ( .A0(n2605), .A1(n2629), .B0(n2613), .B1(n2628), .C0(n1630), .C1(n2626), .Y(n2252) );
AOI222X1TS U1868 ( .A0(n1605), .A1(n2629), .B0(n2620), .B1(n2628), .C0(n2617), .C1(n2626), .Y(n2615) );
AOI222X1TS U1869 ( .A0(n2616), .A1(n2629), .B0(n1636), .B1(n2628), .C0(n2630), .C1(n2626), .Y(n2625) );
AOI222X1TS U1870 ( .A0(n2623), .A1(n2629), .B0(n2630), .B1(n2628), .C0(n1605), .C1(n1739), .Y(n1713) );
AOI222X1TS U1871 ( .A0(n1636), .A1(n2629), .B0(n2637), .B1(n2628), .C0(n2616), .C1(n2626), .Y(n2632) );
AOI222X1TS U1872 ( .A0(n2620), .A1(n2629), .B0(n2623), .B1(n2628), .C0(n1605), .C1(n2626), .Y(n2619) );
MX2X1TS U1873 ( .A(DMP[40]), .B(Sgf_normalized_result[42]), .S0(n2570), .Y(
S_A_S_Oper_A[42]) );
MX2X1TS U1874 ( .A(DMP[50]), .B(Sgf_normalized_result[52]), .S0(n2572), .Y(
S_A_S_Oper_A[52]) );
MX2X1TS U1875 ( .A(DMP[38]), .B(Sgf_normalized_result[40]), .S0(n2570), .Y(
S_A_S_Oper_A[40]) );
MX2X1TS U1876 ( .A(DMP[48]), .B(Sgf_normalized_result[50]), .S0(n2572), .Y(
S_A_S_Oper_A[50]) );
MX2X1TS U1877 ( .A(DMP[43]), .B(Sgf_normalized_result[45]), .S0(n2570), .Y(
S_A_S_Oper_A[45]) );
MX2X1TS U1878 ( .A(DMP[36]), .B(Sgf_normalized_result[38]), .S0(n2570), .Y(
S_A_S_Oper_A[38]) );
MX2X1TS U1879 ( .A(DMP[34]), .B(Sgf_normalized_result[36]), .S0(n2566), .Y(
S_A_S_Oper_A[36]) );
MX2X1TS U1880 ( .A(DMP[32]), .B(Sgf_normalized_result[34]), .S0(n2566), .Y(
S_A_S_Oper_A[34]) );
MX2X1TS U1881 ( .A(DMP[30]), .B(Sgf_normalized_result[32]), .S0(n2566), .Y(
S_A_S_Oper_A[32]) );
MX2X1TS U1882 ( .A(DMP[28]), .B(Sgf_normalized_result[30]), .S0(n2566), .Y(
S_A_S_Oper_A[30]) );
MX2X1TS U1883 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(n2566), .Y(
S_A_S_Oper_A[23]) );
NOR2XLTS U1884 ( .A(n2869), .B(n2870), .Y(n2519) );
MX2X1TS U1885 ( .A(DMP[18]), .B(Sgf_normalized_result[20]), .S0(n2537), .Y(
S_A_S_Oper_A[20]) );
NOR2XLTS U1886 ( .A(n2920), .B(n2537), .Y(n2522) );
MX2X1TS U1887 ( .A(DMP[16]), .B(Sgf_normalized_result[18]), .S0(n2537), .Y(
S_A_S_Oper_A[18]) );
MX2X1TS U1888 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n2537), .Y(
S_A_S_Oper_A[16]) );
NOR2XLTS U1889 ( .A(n2915), .B(n2537), .Y(n2526) );
MX2X1TS U1890 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n2533), .Y(
S_A_S_Oper_A[14]) );
NOR2XLTS U1891 ( .A(n2913), .B(n2533), .Y(n2528) );
MX2X1TS U1892 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n2533), .Y(
S_A_S_Oper_A[12]) );
NOR2XLTS U1893 ( .A(n2910), .B(n2533), .Y(n2530) );
MX2X1TS U1894 ( .A(n1576), .B(Sgf_normalized_result[10]), .S0(n2533), .Y(
S_A_S_Oper_A[10]) );
NOR2XLTS U1895 ( .A(n2908), .B(n2533), .Y(n2532) );
MX2X1TS U1896 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(n2533), .Y(
S_A_S_Oper_A[8]) );
AO22XLTS U1897 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[71]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n1855) );
AO22XLTS U1898 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n1867) );
MX2X1TS U1899 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n2566), .Y(
S_A_S_Oper_A[2]) );
CLKAND2X2TS U1900 ( .A(n2572), .B(Sgf_normalized_result[0]), .Y(
S_A_S_Oper_A[0]) );
NOR2XLTS U1901 ( .A(n2869), .B(n2876), .Y(n2545) );
AOI222X1TS U1902 ( .A0(n1634), .A1(n2629), .B0(n1602), .B1(n2628), .C0(n1756), .C1(n1739), .Y(n2648) );
AOI222X1TS U1903 ( .A0(n1635), .A1(n2629), .B0(n1634), .B1(n2628), .C0(n1756), .C1(n2626), .Y(n2644) );
AOI222X1TS U1904 ( .A0(n1756), .A1(n2629), .B0(n1635), .B1(n2628), .C0(n2641), .C1(n2626), .Y(n2639) );
OAI211XLTS U1905 ( .A0(n2409), .A1(n3004), .B0(n2408), .C0(n2407), .Y(n2410)
);
AOI211X1TS U1906 ( .A0(n2439), .A1(n2901), .B0(Add_Subt_result[50]), .C0(
Add_Subt_result[49]), .Y(n2441) );
OAI211XLTS U1907 ( .A0(Add_Subt_result[40]), .A1(Add_Subt_result[42]), .B0(
n2357), .C0(n2907), .Y(n2358) );
AO22XLTS U1908 ( .A0(Add_Subt_result[30]), .A1(n2362), .B0(n2361), .B1(
Add_Subt_result[22]), .Y(n2428) );
MX2X1TS U1909 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n2533), .Y(
S_A_S_Oper_A[5]) );
NOR2XLTS U1910 ( .A(n2880), .B(n2869), .Y(n2539) );
MX2X1TS U1911 ( .A(DMP[25]), .B(Sgf_normalized_result[27]), .S0(n2566), .Y(
S_A_S_Oper_A[27]) );
AO22XLTS U1912 ( .A0(Add_Subt_Sgf_module_S_to_D[47]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[47]), .Y(n1550) );
AO22XLTS U1913 ( .A0(Add_Subt_Sgf_module_S_to_D[46]), .A1(n2577), .B0(n2575),
.B1(Add_Subt_result[46]), .Y(n1549) );
AO22XLTS U1914 ( .A0(Add_Subt_Sgf_module_S_to_D[43]), .A1(n2805), .B0(n2576),
.B1(Add_Subt_result[43]), .Y(n1546) );
AO22XLTS U1915 ( .A0(Add_Subt_Sgf_module_S_to_D[42]), .A1(n2577), .B0(n1677),
.B1(Add_Subt_result[42]), .Y(n1545) );
AO22XLTS U1916 ( .A0(Add_Subt_Sgf_module_S_to_D[48]), .A1(n2805), .B0(n2576),
.B1(Add_Subt_result[48]), .Y(n1551) );
AO22XLTS U1917 ( .A0(Add_Subt_Sgf_module_S_to_D[51]), .A1(n2577), .B0(n2576),
.B1(Add_Subt_result[51]), .Y(n1554) );
AO22XLTS U1918 ( .A0(n2857), .A1(Data_Y[32]), .B0(n2850), .B1(intDY[32]),
.Y(n1264) );
AO22XLTS U1919 ( .A0(n2854), .A1(Data_Y[40]), .B0(n2855), .B1(intDY[40]),
.Y(n1272) );
AO22XLTS U1920 ( .A0(n2848), .A1(Data_Y[59]), .B0(n2855), .B1(intDY[59]),
.Y(n1291) );
AO22XLTS U1921 ( .A0(n2857), .A1(Data_Y[34]), .B0(n2849), .B1(intDY[34]),
.Y(n1266) );
AO22XLTS U1922 ( .A0(n2857), .A1(Data_Y[42]), .B0(n2851), .B1(intDY[42]),
.Y(n1274) );
AO22XLTS U1923 ( .A0(n2853), .A1(Data_Y[50]), .B0(n2850), .B1(intDY[50]),
.Y(n1282) );
AO22XLTS U1924 ( .A0(n2853), .A1(Data_Y[54]), .B0(n2850), .B1(intDY[54]),
.Y(n1286) );
AO22XLTS U1925 ( .A0(n2857), .A1(Data_Y[36]), .B0(n2850), .B1(intDY[36]),
.Y(n1268) );
AO22XLTS U1926 ( .A0(n2853), .A1(Data_Y[56]), .B0(n2850), .B1(intDY[56]),
.Y(n1288) );
AO22XLTS U1927 ( .A0(n2856), .A1(Data_Y[45]), .B0(n2855), .B1(intDY[45]),
.Y(n1277) );
AO22XLTS U1928 ( .A0(n2853), .A1(Data_Y[57]), .B0(n2849), .B1(intDY[57]),
.Y(n1289) );
AO22XLTS U1929 ( .A0(Add_Subt_Sgf_module_S_to_D[41]), .A1(n2577), .B0(n1677),
.B1(Add_Subt_result[41]), .Y(n1544) );
AO22XLTS U1930 ( .A0(n2858), .A1(Data_X[63]), .B0(n2855), .B1(intDX[63]),
.Y(n1296) );
AO22XLTS U1931 ( .A0(Add_Subt_Sgf_module_S_to_D[19]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[19]), .Y(n1522) );
AO22XLTS U1932 ( .A0(Add_Subt_Sgf_module_S_to_D[17]), .A1(n2805), .B0(n2574),
.B1(Add_Subt_result[17]), .Y(n1520) );
AO22XLTS U1933 ( .A0(Add_Subt_Sgf_module_S_to_D[11]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[11]), .Y(n1514) );
AO22XLTS U1934 ( .A0(Add_Subt_Sgf_module_S_to_D[21]), .A1(n2577), .B0(n1677),
.B1(Add_Subt_result[21]), .Y(n1524) );
AO22XLTS U1935 ( .A0(n2853), .A1(Data_Y[0]), .B0(n2860), .B1(intDY[0]), .Y(
n1232) );
AO22XLTS U1936 ( .A0(n2568), .A1(n2577), .B0(add_overflow_flag), .B1(n2575),
.Y(n1562) );
AO22XLTS U1937 ( .A0(Add_Subt_Sgf_module_S_to_D[31]), .A1(n2577), .B0(n1677),
.B1(Add_Subt_result[31]), .Y(n1534) );
AO22XLTS U1938 ( .A0(Add_Subt_Sgf_module_S_to_D[52]), .A1(n2577), .B0(n2576),
.B1(Add_Subt_result[52]), .Y(n1555) );
AO22XLTS U1939 ( .A0(Add_Subt_Sgf_module_S_to_D[29]), .A1(n2577), .B0(n2575),
.B1(Add_Subt_result[29]), .Y(n1532) );
AO22XLTS U1940 ( .A0(Add_Subt_Sgf_module_S_to_D[7]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[7]), .Y(n1510) );
AO22XLTS U1941 ( .A0(Add_Subt_Sgf_module_S_to_D[44]), .A1(n2577), .B0(n2575),
.B1(Add_Subt_result[44]), .Y(n1547) );
AO22XLTS U1942 ( .A0(n2854), .A1(Data_Y[47]), .B0(n2851), .B1(intDY[47]),
.Y(n1279) );
AO22XLTS U1943 ( .A0(n2853), .A1(Data_Y[51]), .B0(n2849), .B1(intDY[51]),
.Y(n1283) );
AO22XLTS U1944 ( .A0(n2853), .A1(Data_Y[49]), .B0(n2855), .B1(intDY[49]),
.Y(n1281) );
AO22XLTS U1945 ( .A0(Add_Subt_Sgf_module_S_to_D[40]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[40]), .Y(n1543) );
AO22XLTS U1946 ( .A0(n2852), .A1(Data_Y[60]), .B0(n2851), .B1(intDY[60]),
.Y(n1292) );
AO22XLTS U1947 ( .A0(n2853), .A1(Data_Y[58]), .B0(n2851), .B1(intDY[58]),
.Y(n1290) );
AO22XLTS U1948 ( .A0(n2856), .A1(Data_Y[46]), .B0(n2851), .B1(intDY[46]),
.Y(n1278) );
AO22XLTS U1949 ( .A0(Add_Subt_Sgf_module_S_to_D[22]), .A1(n2577), .B0(n1677),
.B1(Add_Subt_result[22]), .Y(n1525) );
AO22XLTS U1950 ( .A0(Add_Subt_Sgf_module_S_to_D[49]), .A1(n2577), .B0(n2576),
.B1(Add_Subt_result[49]), .Y(n1552) );
AO22XLTS U1951 ( .A0(n2857), .A1(Data_Y[33]), .B0(n2855), .B1(intDY[33]),
.Y(n1265) );
AO22XLTS U1952 ( .A0(n2857), .A1(Data_Y[31]), .B0(n2851), .B1(intDY[31]),
.Y(n1263) );
AO22XLTS U1953 ( .A0(n2853), .A1(Data_Y[41]), .B0(n2849), .B1(intDY[41]),
.Y(n1273) );
AO22XLTS U1954 ( .A0(n2853), .A1(Data_Y[53]), .B0(n2851), .B1(intDY[53]),
.Y(n1285) );
AO22XLTS U1955 ( .A0(n2857), .A1(Data_Y[43]), .B0(n2850), .B1(intDY[43]),
.Y(n1275) );
AO22XLTS U1956 ( .A0(n2857), .A1(Data_Y[35]), .B0(n2851), .B1(intDY[35]),
.Y(n1267) );
AO22XLTS U1957 ( .A0(n2853), .A1(Data_Y[55]), .B0(n2849), .B1(intDY[55]),
.Y(n1287) );
AO22XLTS U1958 ( .A0(Add_Subt_Sgf_module_S_to_D[54]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[54]), .Y(n1502) );
AO22XLTS U1959 ( .A0(Add_Subt_Sgf_module_S_to_D[50]), .A1(n2577), .B0(n2576),
.B1(Add_Subt_result[50]), .Y(n1553) );
AO22XLTS U1960 ( .A0(Add_Subt_Sgf_module_S_to_D[45]), .A1(n2577), .B0(n2575),
.B1(Add_Subt_result[45]), .Y(n1548) );
AOI211X1TS U1961 ( .A0(FS_Module_state_reg[1]), .A1(n1587), .B0(n1682), .C0(
n1681), .Y(n1684) );
AOI211XLTS U1962 ( .A0(FS_Module_state_reg[3]), .A1(n1587), .B0(n2809), .C0(
n2814), .Y(n2811) );
AOI211X1TS U1963 ( .A0(n2816), .A1(n2815), .B0(n2814), .C0(n2813), .Y(n2820)
);
AO22XLTS U1964 ( .A0(Add_Subt_Sgf_module_S_to_D[53]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[53]), .Y(n1556) );
AO22XLTS U1965 ( .A0(Add_Subt_Sgf_module_S_to_D[39]), .A1(n2577), .B0(n2576),
.B1(Add_Subt_result[39]), .Y(n1542) );
AO22XLTS U1966 ( .A0(Add_Subt_Sgf_module_S_to_D[38]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[38]), .Y(n1541) );
AO22XLTS U1967 ( .A0(Add_Subt_Sgf_module_S_to_D[37]), .A1(n2805), .B0(n2574),
.B1(Add_Subt_result[37]), .Y(n1540) );
AO22XLTS U1968 ( .A0(Add_Subt_Sgf_module_S_to_D[36]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[36]), .Y(n1539) );
AO22XLTS U1969 ( .A0(Add_Subt_Sgf_module_S_to_D[35]), .A1(n2577), .B0(n2574),
.B1(Add_Subt_result[35]), .Y(n1538) );
AO22XLTS U1970 ( .A0(n2853), .A1(Data_Y[63]), .B0(n2860), .B1(intDY[63]),
.Y(n1231) );
AO22XLTS U1971 ( .A0(n2852), .A1(add_subt), .B0(n2855), .B1(intAS), .Y(n1295) );
AO22XLTS U1972 ( .A0(n2709), .A1(n1752), .B0(n2659), .B1(n1705), .Y(n1763)
);
AOI31XLTS U1973 ( .A0(n2836), .A1(n2835), .A2(n2413), .B0(n2412), .Y(n1496)
);
NAND4XLTS U1974 ( .A(n2447), .B(n2446), .C(n2445), .D(n2444), .Y(n2448) );
AO22XLTS U1975 ( .A0(Add_Subt_Sgf_module_S_to_D[5]), .A1(n2577), .B0(n2576),
.B1(n1668), .Y(n1508) );
AO22XLTS U1976 ( .A0(Add_Subt_Sgf_module_S_to_D[27]), .A1(n2577), .B0(n1677),
.B1(n1667), .Y(n1530) );
OR2X1TS U1977 ( .A(n1670), .B(n1671), .Y(n1587) );
OR3X1TS U1978 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]), .C(
FS_Module_state_reg[1]), .Y(n1588) );
OA22X1TS U1979 ( .A0(n2265), .A1(n2721), .B0(n2873), .B1(n2810), .Y(n1590)
);
OA21XLTS U1980 ( .A0(n3008), .A1(n2723), .B0(n1740), .Y(n1591) );
OA21XLTS U1981 ( .A0(n2930), .A1(n2786), .B0(n1735), .Y(n1592) );
OA22X2TS U1982 ( .A0(Add_Subt_result[0]), .A1(n2786), .B0(
Add_Subt_result[54]), .B1(n1579), .Y(n1593) );
OR2X1TS U1983 ( .A(n1841), .B(n1774), .Y(n1597) );
OA21XLTS U1984 ( .A0(n3011), .A1(n1579), .B0(n1711), .Y(n1598) );
OA21XLTS U1985 ( .A0(n2924), .A1(n2723), .B0(n1734), .Y(n1599) );
OA21XLTS U1986 ( .A0(n2901), .A1(n1579), .B0(n1704), .Y(n1600) );
OA21XLTS U1987 ( .A0(n2882), .A1(n2723), .B0(n1748), .Y(n1604) );
OA21XLTS U1988 ( .A0(n3016), .A1(n1579), .B0(n2747), .Y(n1607) );
OAI2BB2X1TS U1989 ( .B0(n1973), .B1(n1972), .A0N(n1971), .A1N(n1970), .Y(
n2028) );
OAI21X1TS U1990 ( .A0(n1806), .A1(n3027), .B0(n1768), .Y(n1798) );
OAI21X1TS U1991 ( .A0(n1806), .A1(n3026), .B0(n1768), .Y(n1769) );
OAI21X1TS U1992 ( .A0(n1806), .A1(n3025), .B0(n1768), .Y(n1771) );
OAI21X1TS U1993 ( .A0(n1806), .A1(n3029), .B0(n1768), .Y(n1788) );
OAI21X1TS U1994 ( .A0(n1806), .A1(n3030), .B0(n1768), .Y(n1789) );
OAI21X1TS U1995 ( .A0(n1806), .A1(n3031), .B0(n1768), .Y(n1794) );
OAI21X1TS U1996 ( .A0(n1806), .A1(n3028), .B0(n1768), .Y(n1799) );
OAI21X1TS U1997 ( .A0(n1806), .A1(n3032), .B0(n1768), .Y(n1807) );
INVX2TS U1998 ( .A(n1593), .Y(n1625) );
OAI211XLTS U1999 ( .A0(n2433), .A1(n2432), .B0(n2431), .C0(n2430), .Y(n2434)
);
OAI21X1TS U2000 ( .A0(n2265), .A1(FSM_selector_C), .B0(n1679), .Y(n1680) );
MXI2X1TS U2001 ( .A(n2953), .B(add_overflow_flag), .S0(n2569), .Y(n1440) );
NOR3X1TS U2002 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .C(
n2929), .Y(n2569) );
NOR4X2TS U2003 ( .A(n1889), .B(n1961), .C(n1973), .D(n1965), .Y(n2018) );
INVX2TS U2004 ( .A(n1601), .Y(n1626) );
INVX2TS U2005 ( .A(n2786), .Y(n2773) );
CLKINVX6TS U2006 ( .A(n2786), .Y(n2206) );
BUFX4TS U2007 ( .A(n1675), .Y(n2786) );
INVX4TS U2008 ( .A(rst), .Y(n1627) );
INVX4TS U2009 ( .A(rst), .Y(n1628) );
BUFX4TS U2010 ( .A(n1580), .Y(n3050) );
AOI21X2TS U2011 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(n1869), .Y(n2134)
);
AOI21X2TS U2012 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(n1869), .Y(n1825)
);
BUFX4TS U2013 ( .A(n1580), .Y(n3049) );
CLKINVX6TS U2014 ( .A(n2858), .Y(n2850) );
CLKINVX6TS U2015 ( .A(n2858), .Y(n2851) );
CLKINVX6TS U2016 ( .A(n2858), .Y(n2849) );
CLKINVX6TS U2017 ( .A(n2858), .Y(n2855) );
BUFX4TS U2018 ( .A(n3046), .Y(n3061) );
BUFX4TS U2019 ( .A(n3070), .Y(n3068) );
BUFX4TS U2020 ( .A(n1582), .Y(n3063) );
BUFX4TS U2021 ( .A(n1582), .Y(n3058) );
BUFX4TS U2022 ( .A(n1582), .Y(n3069) );
BUFX4TS U2023 ( .A(n1580), .Y(n3046) );
BUFX4TS U2024 ( .A(n1580), .Y(n3047) );
BUFX4TS U2025 ( .A(n1582), .Y(n3060) );
BUFX4TS U2026 ( .A(n1685), .Y(n3065) );
BUFX4TS U2027 ( .A(n1580), .Y(n3056) );
BUFX4TS U2028 ( .A(n3065), .Y(n3059) );
INVX2TS U2029 ( .A(Add_Subt_result[14]), .Y(n1629) );
OAI21X2TS U2030 ( .A0(n3033), .A1(n1579), .B0(n2774), .Y(n2792) );
INVX2TS U2031 ( .A(n1600), .Y(n1630) );
BUFX4TS U2032 ( .A(n3069), .Y(n3055) );
BUFX4TS U2033 ( .A(n3064), .Y(n3057) );
BUFX4TS U2034 ( .A(n3070), .Y(n3062) );
BUFX4TS U2035 ( .A(n3071), .Y(n3067) );
INVX2TS U2036 ( .A(Add_Subt_result[32]), .Y(n1632) );
INVX2TS U2037 ( .A(Add_Subt_result[33]), .Y(n1633) );
AOI222X1TS U2038 ( .A0(n2646), .A1(n2629), .B0(n2636), .B1(n2628), .C0(n2627), .C1(n2626), .Y(n2645) );
AOI222X1TS U2039 ( .A0(n2627), .A1(n2629), .B0(n2646), .B1(n2628), .C0(n2642), .C1(n2626), .Y(n2640) );
OAI21X4TS U2040 ( .A0(n2921), .A1(n2723), .B0(n1717), .Y(n2646) );
INVX2TS U2041 ( .A(n1592), .Y(n1634) );
INVX2TS U2042 ( .A(n1599), .Y(n1635) );
INVX2TS U2043 ( .A(n1598), .Y(n1636) );
OAI21X4TS U2044 ( .A0(n3016), .A1(n2786), .B0(n1706), .Y(n2606) );
BUFX4TS U2045 ( .A(n1741), .Y(n2795) );
AOI211XLTS U2046 ( .A0(n2868), .A1(n2808), .B0(n2807), .C0(n2809), .Y(n2345)
);
OAI21X2TS U2047 ( .A0(n2721), .A1(n1720), .B0(n2818), .Y(n2809) );
BUFX4TS U2048 ( .A(n2933), .Y(n2815) );
BUFX6TS U2049 ( .A(n2933), .Y(n2766) );
OR2X4TS U2050 ( .A(n2816), .B(n1676), .Y(n2485) );
NOR3X2TS U2051 ( .A(n2873), .B(n1688), .C(FS_Module_state_reg[1]), .Y(n2816)
);
AOI211X2TS U2052 ( .A0(intDX[44]), .A1(n2944), .B0(n1975), .C0(n1984), .Y(
n1982) );
BUFX6TS U2053 ( .A(n2476), .Y(n2559) );
INVX2TS U2054 ( .A(n1608), .Y(n1637) );
AOI31XLTS U2055 ( .A0(n2390), .A1(n2835), .A2(n2389), .B0(n2388), .Y(n1501)
);
INVX2TS U2056 ( .A(n1590), .Y(n1638) );
AOI22X4TS U2057 ( .A0(n1648), .A1(n1686), .B0(n2555), .B1(n1626), .Y(n2665)
);
BUFX4TS U2058 ( .A(n1687), .Y(n2555) );
INVX2TS U2059 ( .A(n1588), .Y(n1639) );
BUFX4TS U2060 ( .A(n2856), .Y(n2852) );
INVX2TS U2061 ( .A(n1624), .Y(n1640) );
INVX2TS U2062 ( .A(n1617), .Y(n1641) );
INVX2TS U2063 ( .A(n1619), .Y(n1642) );
INVX2TS U2064 ( .A(n1621), .Y(n1643) );
INVX2TS U2065 ( .A(n1618), .Y(n1644) );
INVX2TS U2066 ( .A(n1620), .Y(n1645) );
INVX2TS U2067 ( .A(n1622), .Y(n1646) );
INVX2TS U2068 ( .A(n1623), .Y(n1647) );
INVX2TS U2069 ( .A(n1589), .Y(n1648) );
INVX2TS U2070 ( .A(n1603), .Y(n1649) );
AOI222X1TS U2071 ( .A0(n2636), .A1(n2629), .B0(n2641), .B1(n2628), .C0(n2627), .C1(n1739), .Y(n2649) );
AOI222X1TS U2072 ( .A0(n2642), .A1(n2629), .B0(n2627), .B1(n2628), .C0(n2637), .C1(n2626), .Y(n2635) );
OAI21X2TS U2073 ( .A0(n3020), .A1(n1579), .B0(n1716), .Y(n2627) );
OAI21X4TS U2074 ( .A0(n3009), .A1(n1579), .B0(n1702), .Y(n2605) );
OAI21X4TS U2075 ( .A0(n2930), .A1(n2723), .B0(n1742), .Y(n2672) );
INVX2TS U2076 ( .A(n1607), .Y(n1650) );
AOI222X1TS U2077 ( .A0(n2641), .A1(n2629), .B0(n1756), .B1(n2628), .C0(n2636), .C1(n2626), .Y(n2634) );
OAI21X2TS U2078 ( .A0(n2882), .A1(n1675), .B0(n1733), .Y(n1756) );
INVX2TS U2079 ( .A(n1604), .Y(n1651) );
OAI21X2TS U2080 ( .A0(n3014), .A1(n1579), .B0(n2767), .Y(n2797) );
INVX2TS U2081 ( .A(n1591), .Y(n1653) );
BUFX6TS U2082 ( .A(n1692), .Y(n2629) );
INVX2TS U2083 ( .A(n2858), .Y(n1655) );
INVX4TS U2084 ( .A(n1655), .Y(n1656) );
INVX2TS U2085 ( .A(n1597), .Y(n1657) );
AOI211X2TS U2086 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(n2478), .C0(n1867), .Y(n2113) );
AOI211X2TS U2087 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[87]), .A1(
n1868), .B0(n2478), .C0(n1855), .Y(n2100) );
NOR2X4TS U2088 ( .A(n1768), .B(n1841), .Y(n2478) );
NAND2X6TS U2089 ( .A(n1872), .B(n1585), .Y(n2116) );
NAND2X6TS U2090 ( .A(n1578), .B(n2114), .Y(n2138) );
BUFX6TS U2091 ( .A(n2204), .Y(n2793) );
INVX3TS U2092 ( .A(n2813), .Y(n2573) );
CLKINVX6TS U2093 ( .A(n2035), .Y(n2218) );
CLKINVX6TS U2094 ( .A(n2035), .Y(n2239) );
AOI211XLTS U2095 ( .A0(n2671), .A1(n1593), .B0(n2256), .C0(n1725), .Y(n1726)
);
BUFX6TS U2096 ( .A(n1694), .Y(n2628) );
OAI21X2TS U2097 ( .A0(n3019), .A1(n1579), .B0(n2760), .Y(n2791) );
OAI21X2TS U2098 ( .A0(n1633), .A1(n2723), .B0(n1714), .Y(n2636) );
OAI21X2TS U2099 ( .A0(n3010), .A1(n2723), .B0(n1743), .Y(n2659) );
INVX4TS U2100 ( .A(n2852), .Y(n2860) );
INVX4TS U2101 ( .A(n2580), .Y(n2780) );
CLKINVX6TS U2102 ( .A(n2164), .Y(n2865) );
INVX6TS U2103 ( .A(n2164), .Y(n2238) );
INVX4TS U2104 ( .A(n2164), .Y(n2226) );
INVX2TS U2105 ( .A(n2846), .Y(n2838) );
CLKINVX6TS U2106 ( .A(n2846), .Y(n2844) );
CLKINVX3TS U2107 ( .A(n2041), .Y(n2074) );
CLKINVX6TS U2108 ( .A(n2041), .Y(n2189) );
CLKINVX6TS U2109 ( .A(n2041), .Y(n2162) );
CLKINVX3TS U2110 ( .A(n2786), .Y(n2693) );
CLKINVX6TS U2111 ( .A(n2868), .Y(n2190) );
INVX6TS U2112 ( .A(n2868), .Y(n2228) );
INVX6TS U2113 ( .A(n2868), .Y(n2223) );
INVX3TS U2114 ( .A(n2041), .Y(n2072) );
OR4X4TS U2115 ( .A(n2485), .B(n2578), .C(n2807), .D(n1680), .Y(
FSM_exp_operation_A_S) );
CLKINVX6TS U2116 ( .A(n2035), .Y(n2083) );
INVX6TS U2117 ( .A(n2574), .Y(n2578) );
INVX2TS U2118 ( .A(n1606), .Y(n1658) );
AOI21X2TS U2119 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(n1769), .Y(n1786)
);
AOI21X2TS U2120 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(n1798), .Y(n1831)
);
AOI21X2TS U2121 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(n1788), .Y(n1828)
);
AOI21X2TS U2122 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(n1794), .Y(n1837)
);
AOI21X2TS U2123 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(n1789), .Y(n1834)
);
AOI21X2TS U2124 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(n1799), .Y(n1840)
);
AOI211X1TS U2125 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(n1781), .C0(n2470), .Y(n2473) );
AOI21X2TS U2126 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(n1771), .Y(n1819)
);
AOI211X2TS U2127 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(n2478), .C0(n1863), .Y(n2108) );
AOI211X1TS U2128 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(n1781), .C0(n2563), .Y(n2565) );
AOI211X1TS U2129 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[71]), .A1(
n2457), .B0(n1781), .C0(n2472), .Y(n2474) );
INVX2TS U2130 ( .A(n1616), .Y(n1659) );
AOI21X2TS U2131 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n1807), .Y(n1822)
);
AOI211X1TS U2132 ( .A0(n2559), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n1781), .C0(n2481), .Y(n2482) );
INVX2TS U2133 ( .A(n1594), .Y(n1660) );
AOI211X2TS U2134 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(n2478), .C0(n1847), .Y(n2087) );
AOI211X1TS U2135 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(n1781), .C0(n2461), .Y(n2464) );
AOI211X2TS U2136 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(n2478), .C0(n1859), .Y(n2095) );
AOI211X1TS U2137 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(n1781), .C0(n2456), .Y(n2466) );
AOI211X2TS U2138 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n2478), .C0(n1843), .Y(n2091) );
AOI211X1TS U2139 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n1781), .C0(n2459), .Y(n2468) );
AOI211X2TS U2140 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n2478), .C0(n1851), .Y(n2104) );
AOI211X1TS U2141 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n1781), .C0(n2463), .Y(n2465) );
INVX2TS U2142 ( .A(n1612), .Y(n1661) );
INVX2TS U2143 ( .A(n1610), .Y(n1662) );
INVX2TS U2144 ( .A(n1615), .Y(n1663) );
INVX2TS U2145 ( .A(n1611), .Y(n1664) );
INVX2TS U2146 ( .A(n1613), .Y(n1665) );
INVX2TS U2147 ( .A(n1614), .Y(n1666) );
INVX2TS U2148 ( .A(n1596), .Y(n1667) );
INVX2TS U2149 ( .A(n1609), .Y(n1668) );
NOR4X2TS U2150 ( .A(Add_Subt_result[48]), .B(Add_Subt_result[49]), .C(
Add_Subt_result[50]), .D(n2381), .Y(n2823) );
NOR3X1TS U2151 ( .A(Add_Subt_result[48]), .B(Add_Subt_result[49]), .C(
Add_Subt_result[50]), .Y(n2382) );
OAI31X1TS U2152 ( .A0(Add_Subt_result[51]), .A1(Add_Subt_result[52]), .A2(
n2441), .B0(n2440), .Y(n2446) );
OAI221XLTS U2153 ( .A0(n3074), .A1(intDY[31]), .B0(n2969), .B1(intDY[32]),
.C0(n2313), .Y(n2318) );
AOI221X1TS U2154 ( .A0(n2991), .A1(intDY[40]), .B0(intDY[39]), .B1(n2889),
.C0(n2289), .Y(n2294) );
AOI32X1TS U2155 ( .A0(n3002), .A1(n1963), .A2(intDY[58]), .B0(intDY[59]),
.B1(n2895), .Y(n1964) );
AOI221X1TS U2156 ( .A0(n3001), .A1(intDY[60]), .B0(intDY[59]), .B1(n2895),
.C0(n2275), .Y(n2285) );
OAI221X1TS U2157 ( .A0(n2981), .A1(intDY[21]), .B0(n2973), .B1(intDY[22]),
.C0(n2304), .Y(n2311) );
OAI221X1TS U2158 ( .A0(n2961), .A1(intDY[29]), .B0(n2970), .B1(intDY[30]),
.C0(n2312), .Y(n2319) );
OAI221X1TS U2159 ( .A0(n2887), .A1(intDY[2]), .B0(n2964), .B1(intDY[0]),
.C0(n2322), .Y(n2325) );
OAI221X1TS U2160 ( .A0(n2962), .A1(intDY[13]), .B0(n2976), .B1(intDY[14]),
.C0(n2328), .Y(n2335) );
AOI221X1TS U2161 ( .A0(n2892), .A1(intDY[34]), .B0(intDY[33]), .B1(n3000),
.C0(n2290), .Y(n2293) );
AOI32X1TS U2162 ( .A0(n3045), .A1(n2012), .A2(intDY[50]), .B0(intDY[51]),
.B1(n2986), .Y(n2013) );
OAI211X2TS U2163 ( .A0(intDY[20]), .A1(n2974), .B0(n1952), .C0(n1906), .Y(
n1946) );
OAI221XLTS U2164 ( .A0(n2985), .A1(intDY[19]), .B0(n2974), .B1(intDY[20]),
.C0(n2307), .Y(n2308) );
OAI211X2TS U2165 ( .A0(intDY[28]), .A1(n2971), .B0(n1905), .C0(n1896), .Y(
n1955) );
OAI221XLTS U2166 ( .A0(n2984), .A1(intDY[27]), .B0(n2971), .B1(intDY[28]),
.C0(n2315), .Y(n2316) );
OAI221X1TS U2167 ( .A0(n3073), .A1(intDY[53]), .B0(n2967), .B1(intDY[54]),
.C0(n2276), .Y(n2283) );
OAI211X2TS U2168 ( .A0(intDY[12]), .A1(n2977), .B0(n1933), .C0(n1907), .Y(
n1937) );
OAI221XLTS U2169 ( .A0(n3042), .A1(intDY[11]), .B0(n2977), .B1(intDY[12]),
.C0(n2331), .Y(n2332) );
AOI221X1TS U2170 ( .A0(n3003), .A1(intDY[36]), .B0(intDY[35]), .B1(n2999),
.C0(n2291), .Y(n2292) );
OAI221XLTS U2171 ( .A0(n3072), .A1(intDY[55]), .B0(n2966), .B1(intDY[56]),
.C0(n2277), .Y(n2282) );
OAI221XLTS U2172 ( .A0(n3075), .A1(intDY[23]), .B0(n2972), .B1(intDY[24]),
.C0(n2305), .Y(n2310) );
AOI221X1TS U2173 ( .A0(n2989), .A1(intDY[46]), .B0(intDY[45]), .B1(n2997),
.C0(n2296), .Y(n2303) );
OAI221X1TS U2174 ( .A0(n3043), .A1(intDY[17]), .B0(n3076), .B1(intDY[18]),
.C0(n2306), .Y(n2309) );
OAI221X1TS U2175 ( .A0(n3040), .A1(intDY[25]), .B0(n3041), .B1(intDY[26]),
.C0(n2314), .Y(n2317) );
AOI221X1TS U2176 ( .A0(n3002), .A1(intDY[58]), .B0(intDY[57]), .B1(n2996),
.C0(n2274), .Y(n2286) );
OAI221X1TS U2177 ( .A0(n2884), .A1(intDY[5]), .B0(n2979), .B1(intDY[6]),
.C0(n2320), .Y(n2327) );
NOR4X2TS U2178 ( .A(n2343), .B(n2342), .C(n2341), .D(n2340), .Y(n2861) );
OR2X1TS U2179 ( .A(Add_Subt_result[42]), .B(n2346), .Y(n2825) );
INVX2TS U2180 ( .A(n2825), .Y(n1669) );
NOR2XLTS U2181 ( .A(beg_FSM), .B(n1360), .Y(n1670) );
INVX2TS U2182 ( .A(n2817), .Y(n1671) );
NAND2X2TS U2183 ( .A(n1639), .B(n2940), .Y(n1360) );
NOR2XLTS U2184 ( .A(n2918), .B(n2533), .Y(n2524) );
NOR2XLTS U2185 ( .A(n2919), .B(n2537), .Y(n2523) );
OAI21X4TS U2186 ( .A0(n3015), .A1(n1675), .B0(n1701), .Y(n2620) );
OAI21X2TS U2187 ( .A0(n2912), .A1(n1579), .B0(n1698), .Y(n2616) );
BUFX6TS U2188 ( .A(n1773), .Y(n2560) );
BUFX6TS U2189 ( .A(n1782), .Y(n2136) );
AOI21X2TS U2190 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[93]), .A1(
n1793), .B0(n1869), .Y(n2139) );
AOI21X2TS U2191 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(n1869), .Y(n2125)
);
AOI21X2TS U2192 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(n1869), .Y(n2119)
);
AOI21X2TS U2193 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(n1869), .Y(n2128)
);
AOI21X2TS U2194 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(n1869), .Y(n2122)
);
AOI21X2TS U2195 ( .A0(n1793), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(n1869), .Y(n2131)
);
NOR2X4TS U2196 ( .A(n1793), .B(n2589), .Y(n1869) );
AOI31XLTS U2197 ( .A0(n2453), .A1(n2835), .A2(n2438), .B0(n2437), .Y(n1497)
);
AOI31XLTS U2198 ( .A0(n2453), .A1(n2835), .A2(n2452), .B0(n2451), .Y(n1498)
);
NOR2X4TS U2199 ( .A(FS_Module_state_reg[0]), .B(n2819), .Y(n2835) );
AOI22X2TS U2200 ( .A0(LZA_output[4]), .A1(n1686), .B0(n2555), .B1(
exp_oper_result[4]), .Y(n1775) );
INVX3TS U2201 ( .A(n1700), .Y(n2650) );
NOR2XLTS U2202 ( .A(n2953), .B(n2557), .Y(n1673) );
NOR2XLTS U2203 ( .A(exp_oper_result[0]), .B(n2557), .Y(n1674) );
AOI22X2TS U2204 ( .A0(n1672), .A1(n2659), .B0(n1745), .B1(n1744), .Y(n2664)
);
AOI22X2TS U2205 ( .A0(n1672), .A1(n1745), .B0(n1602), .B1(n1744), .Y(n2658)
);
NOR2X4TS U2206 ( .A(n1672), .B(n2665), .Y(n1739) );
OR2X4TS U2207 ( .A(n1770), .B(n2786), .Y(n2467) );
INVX4TS U2208 ( .A(n2859), .Y(n2847) );
BUFX6TS U2209 ( .A(n2512), .Y(n2567) );
AOI32X1TS U2210 ( .A0(Add_Subt_result[11]), .A1(n2406), .A2(n3015), .B0(
Add_Subt_result[13]), .B1(n2406), .Y(n2377) );
BUFX6TS U2211 ( .A(n1752), .Y(n2790) );
BUFX6TS U2212 ( .A(n1705), .Y(n2800) );
BUFX6TS U2213 ( .A(n1770), .Y(n2564) );
OAI21X4TS U2214 ( .A0(n1638), .A1(n2809), .B0(add_overflow_flag), .Y(n2589)
);
NOR2X2TS U2215 ( .A(Add_Subt_result[13]), .B(n2376), .Y(n2401) );
NOR2X2TS U2216 ( .A(Add_Subt_result[29]), .B(n2432), .Y(n2443) );
OAI221X1TS U2217 ( .A0(n2886), .A1(intDY[9]), .B0(n2978), .B1(intDY[10]),
.C0(n2330), .Y(n2333) );
OAI221XLTS U2218 ( .A0(n2955), .A1(intDY[7]), .B0(n2963), .B1(intDY[8]),
.C0(n2321), .Y(n2326) );
OAI221XLTS U2219 ( .A0(n2986), .A1(intDY[51]), .B0(n2968), .B1(intDY[52]),
.C0(n2279), .Y(n2280) );
AOI32X1TS U2220 ( .A0(n3041), .A1(n1898), .A2(intDY[26]), .B0(intDY[27]),
.B1(n2984), .Y(n1899) );
AOI32X1TS U2221 ( .A0(n3076), .A1(n1943), .A2(intDY[18]), .B0(intDY[19]),
.B1(n2985), .Y(n1944) );
NOR2XLTS U2222 ( .A(Add_Subt_result[40]), .B(n2442), .Y(n2347) );
OAI221XLTS U2223 ( .A0(n3077), .A1(intDY[15]), .B0(n2975), .B1(intDY[16]),
.C0(n2329), .Y(n2334) );
OAI221XLTS U2224 ( .A0(n2960), .A1(intDY[3]), .B0(n2980), .B1(intDY[4]),
.C0(n2323), .Y(n2324) );
OR4X2TS U2225 ( .A(FS_Module_state_reg[1]), .B(add_overflow_flag), .C(n2721),
.D(n1688), .Y(n1675) );
OAI21XLTS U2226 ( .A0(intDX[1]), .A1(n2939), .B0(intDX[0]), .Y(n1910) );
OAI21XLTS U2227 ( .A0(intDY[35]), .A1(n2999), .B0(intDY[34]), .Y(n1993) );
NOR2XLTS U2228 ( .A(n2010), .B(intDX[48]), .Y(n2011) );
NOR2XLTS U2229 ( .A(n1941), .B(intDX[16]), .Y(n1942) );
OAI21XLTS U2230 ( .A0(n1985), .A1(n1984), .B0(n1983), .Y(n1987) );
NOR2XLTS U2231 ( .A(Add_Subt_result[4]), .B(n3014), .Y(n2350) );
NOR2XLTS U2232 ( .A(n3018), .B(n2572), .Y(n2490) );
NOR2XLTS U2233 ( .A(n2995), .B(n2570), .Y(n2493) );
NOR2XLTS U2234 ( .A(n2869), .B(n2871), .Y(n2518) );
NOR2XLTS U2235 ( .A(n2905), .B(n2533), .Y(n2535) );
NOR2XLTS U2236 ( .A(n2878), .B(n2869), .Y(n2541) );
NOR2XLTS U2237 ( .A(n2869), .B(n2931), .Y(n2513) );
OAI21XLTS U2238 ( .A0(n2562), .A1(n3028), .B0(n2462), .Y(n2463) );
AOI31XLTS U2239 ( .A0(n2345), .A1(n1588), .A2(n2344), .B0(n1587), .Y(n1560)
);
OAI21XLTS U2240 ( .A0(n2139), .A1(n2116), .B0(n2101), .Y(n1442) );
OAI21XLTS U2241 ( .A0(n1831), .A1(n2116), .B0(n1802), .Y(n1455) );
OAI211XLTS U2242 ( .A0(n2100), .A1(n2138), .B0(n1885), .C0(n2136), .Y(n1474)
);
OAI211XLTS U2243 ( .A0(n1786), .A1(n2138), .B0(n1783), .C0(n2136), .Y(n1488)
);
OAI21XLTS U2244 ( .A0(n2978), .A1(n2153), .B0(n2061), .Y(n1115) );
OAI21XLTS U2245 ( .A0(n2972), .A1(n2192), .B0(n2182), .Y(n1129) );
OAI21XLTS U2246 ( .A0(n2992), .A1(n2177), .B0(n2143), .Y(n1143) );
OAI21XLTS U2247 ( .A0(n2968), .A1(n2192), .B0(n2069), .Y(n1157) );
OAI21XLTS U2248 ( .A0(n2960), .A1(n2237), .B0(n2217), .Y(n1172) );
OAI21XLTS U2249 ( .A0(n2975), .A1(n2041), .B0(n2196), .Y(n1185) );
OAI21XLTS U2250 ( .A0(n2961), .A1(n2241), .B0(n2047), .Y(n1198) );
OAI21XLTS U2251 ( .A0(n2891), .A1(n1577), .B0(n2201), .Y(n1211) );
OAI21XLTS U2252 ( .A0(n3072), .A1(n2237), .B0(n2236), .Y(n1224) );
OAI211XLTS U2253 ( .A0(n2615), .A1(n2651), .B0(n2248), .C0(n2247), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[42]) );
AOI31XLTS U2254 ( .A0(n2371), .A1(n2835), .A2(n2370), .B0(n2369), .Y(n1500)
);
NAND2X1TS U2255 ( .A(n2929), .B(FS_Module_state_reg[2]), .Y(n1688) );
NAND4X1TS U2256 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.C(n2873), .D(n2881), .Y(n2818) );
INVX2TS U2257 ( .A(n2818), .Y(n1676) );
NAND3X1TS U2258 ( .A(FS_Module_state_reg[3]), .B(n2940), .C(n2881), .Y(n2819) );
NOR2X2TS U2259 ( .A(n2873), .B(n2819), .Y(n2807) );
NAND2BX1TS U2260 ( .AN(n2940), .B(n1639), .Y(n2265) );
AOI32X1TS U2261 ( .A0(FS_Module_state_reg[3]), .A1(n2940), .A2(
FS_Module_state_reg[0]), .B0(n2929), .B1(FS_Module_state_reg[2]), .Y(
n1678) );
NOR2BX1TS U2262 ( .AN(add_overflow_flag), .B(n1678), .Y(n1679) );
NOR4X1TS U2263 ( .A(FS_Module_state_reg[0]), .B(n2940), .C(n2929), .D(n2881),
.Y(ready) );
NAND2BXLTS U2264 ( .AN(ack_FSM), .B(ready), .Y(n2817) );
INVX2TS U2265 ( .A(n2816), .Y(n1720) );
NOR2XLTS U2266 ( .A(FSM_selector_C), .B(n1720), .Y(n1682) );
AND4X2TS U2267 ( .A(FS_Module_state_reg[1]), .B(n2873), .C(n2940), .D(n2929),
.Y(n2868) );
NAND3X1TS U2268 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[1]),
.C(n2940), .Y(n2810) );
NAND2BX1TS U2269 ( .AN(n2810), .B(n2873), .Y(n2344) );
NAND4XLTS U2270 ( .A(n2838), .B(n2228), .C(n2344), .D(n2847), .Y(n1681) );
CLKINVX1TS U2271 ( .A(sign_final_result), .Y(n2866) );
AOI22X1TS U2272 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n2900), .B1(n2876),
.Y(n1683) );
OAI221X1TS U2273 ( .A0(sign_final_result), .A1(r_mode[1]), .B0(n2866), .B1(
r_mode[0]), .C0(n1683), .Y(n2806) );
NAND2BXLTS U2274 ( .AN(n2806), .B(n2807), .Y(n1731) );
OAI211XLTS U2275 ( .A0(n1677), .A1(n2873), .B0(n1684), .C0(n1731), .Y(n1559)
);
BUFX3TS U2276 ( .A(n1685), .Y(n3048) );
BUFX3TS U2277 ( .A(n3064), .Y(n3066) );
BUFX3TS U2278 ( .A(n3064), .Y(n3052) );
BUFX3TS U2279 ( .A(n1580), .Y(n3053) );
BUFX3TS U2280 ( .A(n3064), .Y(n3051) );
BUFX3TS U2281 ( .A(n3071), .Y(n3054) );
OAI21XLTS U2282 ( .A0(n2575), .A1(FS_Module_state_reg[0]), .B0(n2766), .Y(
n1557) );
INVX2TS U2283 ( .A(underflow_flag), .Y(n2843) );
NAND3BX1TS U2284 ( .AN(overflow_flag), .B(n2846), .C(n2843), .Y(n2839) );
CLKBUFX2TS U2285 ( .A(n2839), .Y(n2837) );
OAI2BB2XLTS U2286 ( .B0(n2995), .B1(n2837), .A0N(final_result_ieee[45]),
.A1N(n1581), .Y(n1369) );
OAI2BB2XLTS U2287 ( .B0(n2959), .B1(n2837), .A0N(final_result_ieee[41]),
.A1N(n1581), .Y(n1373) );
NOR2XLTS U2288 ( .A(FSM_selector_B[1]), .B(FSM_selector_B[0]), .Y(n1687) );
AO22XLTS U2289 ( .A0(LZA_output[2]), .A1(n1686), .B0(n2555), .B1(n1658), .Y(
n1700) );
INVX4TS U2290 ( .A(n2651), .Y(n2666) );
AOI22X1TS U2291 ( .A0(Add_Subt_result[44]), .A1(n2700), .B0(DmP[42]), .B1(
n2815), .Y(n1689) );
OAI21X2TS U2292 ( .A0(n3017), .A1(n1675), .B0(n1689), .Y(n2617) );
NAND2X1TS U2293 ( .A(n1686), .B(LZA_output[0]), .Y(n1691) );
NAND2X1TS U2294 ( .A(n2953), .B(FSM_selector_B[1]), .Y(n1690) );
NAND2X1TS U2295 ( .A(n1691), .B(n1690), .Y(n2557) );
INVX2TS U2296 ( .A(n2665), .Y(n2255) );
NOR2XLTS U2297 ( .A(n1672), .B(n2255), .Y(n1692) );
AOI22X1TS U2298 ( .A0(Add_Subt_result[11]), .A1(n2773), .B0(DmP[41]), .B1(
n2721), .Y(n1693) );
INVX2TS U2299 ( .A(n1672), .Y(n1744) );
NOR2XLTS U2300 ( .A(n1744), .B(n2255), .Y(n1694) );
AOI22X1TS U2301 ( .A0(Add_Subt_result[9]), .A1(n2693), .B0(DmP[43]), .B1(
n2815), .Y(n1695) );
OAI21X2TS U2302 ( .A0(n2896), .A1(n1579), .B0(n1695), .Y(n2613) );
NOR2XLTS U2303 ( .A(n2665), .B(n1744), .Y(n1696) );
BUFX4TS U2304 ( .A(n1696), .Y(n2626) );
AOI222X1TS U2305 ( .A0(n2617), .A1(n2629), .B0(n1605), .B1(n2628), .C0(n2613), .C1(n2626), .Y(n2245) );
AOI22X1TS U2306 ( .A0(Add_Subt_result[40]), .A1(n2700), .B0(DmP[38]), .B1(
n2815), .Y(n1697) );
OAI21X2TS U2307 ( .A0(n1629), .A1(n2786), .B0(n1697), .Y(n2630) );
AOI22X1TS U2308 ( .A0(Add_Subt_result[15]), .A1(n2693), .B0(DmP[37]), .B1(
n2815), .Y(n1698) );
INVX2TS U2309 ( .A(Add_Subt_result[41]), .Y(n2702) );
BUFX4TS U2310 ( .A(n2933), .Y(n2721) );
AOI22X1TS U2311 ( .A0(Add_Subt_result[13]), .A1(n2693), .B0(DmP[39]), .B1(
n2721), .Y(n1699) );
OAI21X2TS U2312 ( .A0(n2702), .A1(n1579), .B0(n1699), .Y(n2623) );
AOI222X1TS U2313 ( .A0(n2630), .A1(n2629), .B0(n2616), .B1(n2628), .C0(n2623), .C1(n2626), .Y(n2622) );
NAND2X2TS U2314 ( .A(n2650), .B(n1739), .Y(n2590) );
AOI22X1TS U2315 ( .A0(Add_Subt_result[42]), .A1(n2700), .B0(DmP[40]), .B1(
n2815), .Y(n1701) );
NAND2X1TS U2316 ( .A(n2651), .B(n1739), .Y(n2588) );
AOI22X1TS U2317 ( .A0(Add_Subt_result[8]), .A1(n2773), .B0(DmP[44]), .B1(
n2815), .Y(n1702) );
AOI22X1TS U2318 ( .A0(n2671), .A1(n2620), .B0(n1705), .B1(n2605), .Y(n1703)
);
OAI221XLTS U2319 ( .A0(n2666), .A1(n2245), .B0(n2651), .B1(n2622), .C0(n1703), .Y(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
AOI22X1TS U2320 ( .A0(Add_Subt_result[7]), .A1(n2206), .B0(DmP[45]), .B1(
n2721), .Y(n1704) );
AOI22X1TS U2321 ( .A0(Add_Subt_result[48]), .A1(n2700), .B0(DmP[46]), .B1(
n2721), .Y(n1706) );
AOI22X1TS U2322 ( .A0(n2800), .A1(n2606), .B0(n2671), .B1(n2617), .Y(n1707)
);
OAI221XLTS U2323 ( .A0(n2666), .A1(n2252), .B0(n2651), .B1(n2619), .C0(n1707), .Y(Barrel_Shifter_module_Mux_Array_Data_array[41]) );
AOI222X1TS U2324 ( .A0(n2613), .A1(n2629), .B0(n2617), .B1(n2628), .C0(n1630), .C1(n1739), .Y(n2211) );
NAND2X2TS U2325 ( .A(n2650), .B(n2626), .Y(n2584) );
INVX2TS U2326 ( .A(n2584), .Y(n2204) );
NAND2X1TS U2327 ( .A(n2651), .B(n2626), .Y(n2581) );
AOI22X1TS U2328 ( .A0(n2793), .A1(n2620), .B0(n2753), .B1(n2605), .Y(n1708)
);
OAI221XLTS U2329 ( .A0(n2666), .A1(n2211), .B0(n2651), .B1(n1713), .C0(n1708), .Y(Barrel_Shifter_module_Mux_Array_Data_array[40]) );
AOI22X1TS U2330 ( .A0(Add_Subt_result[17]), .A1(n2693), .B0(DmP[35]), .B1(
n2721), .Y(n1709) );
OAI21X2TS U2331 ( .A0(n3013), .A1(n1579), .B0(n1709), .Y(n2637) );
AOI22X1TS U2332 ( .A0(Add_Subt_result[18]), .A1(n2206), .B0(DmP[34]), .B1(
n2766), .Y(n1710) );
OAI21X2TS U2333 ( .A0(n2916), .A1(n1579), .B0(n1710), .Y(n2642) );
AOI222X1TS U2334 ( .A0(n2637), .A1(n2629), .B0(n2642), .B1(n2628), .C0(n2616), .C1(n1739), .Y(n1719) );
AOI22X1TS U2335 ( .A0(Add_Subt_result[16]), .A1(n2206), .B0(DmP[36]), .B1(
n2721), .Y(n1711) );
AOI22X1TS U2336 ( .A0(n2793), .A1(n1636), .B0(n2753), .B1(n2620), .Y(n1712)
);
OAI221XLTS U2337 ( .A0(n2666), .A1(n1713), .B0(n2651), .B1(n1719), .C0(n1712), .Y(Barrel_Shifter_module_Mux_Array_Data_array[36]) );
INVX4TS U2338 ( .A(n2700), .Y(n2723) );
AOI22X1TS U2339 ( .A0(Add_Subt_result[21]), .A1(n2773), .B0(DmP[31]), .B1(
n2721), .Y(n1714) );
AOI22X1TS U2340 ( .A0(Add_Subt_result[22]), .A1(n2693), .B0(DmP[30]), .B1(
n2766), .Y(n1715) );
OAI21X2TS U2341 ( .A0(n1632), .A1(n2723), .B0(n1715), .Y(n2641) );
AOI22X1TS U2342 ( .A0(Add_Subt_result[19]), .A1(n2773), .B0(DmP[33]), .B1(
n2766), .Y(n1716) );
BUFX4TS U2343 ( .A(n2753), .Y(n2796) );
AOI22X1TS U2344 ( .A0(Add_Subt_result[20]), .A1(n2206), .B0(DmP[32]), .B1(
n2766), .Y(n1717) );
AOI22X1TS U2345 ( .A0(n2753), .A1(n1636), .B0(n2793), .B1(n2646), .Y(n1718)
);
OAI221XLTS U2346 ( .A0(n2650), .A1(n1719), .B0(n2651), .B1(n2649), .C0(n1718), .Y(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
AOI222X4TS U2347 ( .A0(n2766), .A1(DmP[51]), .B0(Add_Subt_result[1]), .B1(
n2693), .C0(Add_Subt_result[53]), .C1(n2700), .Y(n2597) );
NAND2X2TS U2348 ( .A(n2666), .B(n2628), .Y(n2586) );
INVX2TS U2349 ( .A(n2589), .Y(n1767) );
NAND2X2TS U2350 ( .A(n2650), .B(n2629), .Y(n2582) );
AOI22X1TS U2351 ( .A0(n1767), .A1(n2255), .B0(n1741), .B1(n1593), .Y(n1722)
);
NOR2X2TS U2352 ( .A(n2666), .B(n2589), .Y(n2256) );
INVX2TS U2353 ( .A(n2256), .Y(n1721) );
OAI211XLTS U2354 ( .A0(n2597), .A1(n2586), .B0(n1722), .C0(n1721), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[53]) );
BUFX4TS U2355 ( .A(n2859), .Y(n2858) );
AOI222X4TS U2356 ( .A0(n2766), .A1(DmP[50]), .B0(Add_Subt_result[2]), .B1(
n2206), .C0(Add_Subt_result[52]), .C1(n2700), .Y(n2596) );
OAI22X1TS U2357 ( .A0(n2596), .A1(n2586), .B0(n2584), .B1(n1625), .Y(n1723)
);
AOI211XLTS U2358 ( .A0(n1739), .A1(n1767), .B0(n2256), .C0(n1723), .Y(n1724)
);
OAI21XLTS U2359 ( .A0(n2597), .A1(n2582), .B0(n1724), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[52]) );
AOI222X4TS U2360 ( .A0(n2766), .A1(DmP[49]), .B0(Add_Subt_result[3]), .B1(
n2693), .C0(Add_Subt_result[51]), .C1(n2700), .Y(n2591) );
OAI22X1TS U2361 ( .A0(n2591), .A1(n2586), .B0(n2597), .B1(n2584), .Y(n1725)
);
OAI21XLTS U2362 ( .A0(n2596), .A1(n2582), .B0(n1726), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[51]) );
INVX2TS U2363 ( .A(n2628), .Y(n1729) );
NAND2X2TS U2364 ( .A(n2628), .B(n2651), .Y(n2579) );
OAI22X1TS U2365 ( .A0(n2591), .A1(n2582), .B0(n2579), .B1(n1625), .Y(n1728)
);
AOI222X4TS U2366 ( .A0(n2815), .A1(DmP[48]), .B0(Add_Subt_result[4]), .B1(
n2206), .C0(Add_Subt_result[50]), .C1(n2700), .Y(n2585) );
OAI22X1TS U2367 ( .A0(n2585), .A1(n2586), .B0(n2597), .B1(n2590), .Y(n1727)
);
AOI211XLTS U2368 ( .A0(n2256), .A1(n1729), .B0(n1728), .C0(n1727), .Y(n1730)
);
OAI21XLTS U2369 ( .A0(n2596), .A1(n2584), .B0(n1730), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[50]) );
NAND2X1TS U2370 ( .A(n2902), .B(n1731), .Y(n1441) );
INVX2TS U2371 ( .A(n2835), .Y(n2833) );
NAND2BXLTS U2372 ( .AN(n2833), .B(add_overflow_flag), .Y(n1732) );
OAI211XLTS U2373 ( .A0(n2835), .A1(n3037), .B0(n2344), .C0(n1732), .Y(n1439)
);
AOI22X1TS U2374 ( .A0(Add_Subt_result[31]), .A1(n2700), .B0(DmP[29]), .B1(
n2815), .Y(n1733) );
AOI22X1TS U2375 ( .A0(Add_Subt_result[24]), .A1(n2206), .B0(DmP[28]), .B1(
n2721), .Y(n1734) );
AOI22X1TS U2376 ( .A0(Add_Subt_result[29]), .A1(n2700), .B0(DmP[27]), .B1(
n2721), .Y(n1735) );
AOI22X1TS U2377 ( .A0(n2671), .A1(n1635), .B0(n2204), .B1(n1634), .Y(n1738)
);
AO22XLTS U2378 ( .A0(FSM_selector_C), .A1(n1667), .B0(n2721), .B1(DmP[25]),
.Y(n1745) );
AOI22X1TS U2379 ( .A0(Add_Subt_result[26]), .A1(n2773), .B0(DmP[26]), .B1(
n2721), .Y(n1736) );
NOR2X1TS U2380 ( .A(n2255), .B(n2658), .Y(n1749) );
AOI22X1TS U2381 ( .A0(n2666), .A1(n1749), .B0(n1705), .B1(n2646), .Y(n1737)
);
OAI211XLTS U2382 ( .A0(n2666), .A1(n2634), .B0(n1738), .C0(n1737), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[27]) );
INVX2TS U2383 ( .A(n2586), .Y(n1752) );
AOI22X1TS U2384 ( .A0(Add_Subt_result[30]), .A1(n2773), .B0(DmP[22]), .B1(
n2721), .Y(n1740) );
AOI22X1TS U2385 ( .A0(n2753), .A1(n1635), .B0(n1752), .B1(n1653), .Y(n1747)
);
AOI22X1TS U2386 ( .A0(Add_Subt_result[29]), .A1(n2206), .B0(DmP[23]), .B1(
n2766), .Y(n1742) );
AOI22X1TS U2387 ( .A0(Add_Subt_result[28]), .A1(n2773), .B0(DmP[24]), .B1(
n2721), .Y(n1743) );
NAND2X1TS U2388 ( .A(n2666), .B(n2255), .Y(n1753) );
AOI2BB2XLTS U2389 ( .B0(n1741), .B1(n2672), .A0N(n2664), .A1N(n1753), .Y(
n1746) );
OAI211XLTS U2390 ( .A0(n2666), .A1(n2648), .B0(n1747), .C0(n1746), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
AOI22X1TS U2391 ( .A0(Add_Subt_result[31]), .A1(n2206), .B0(DmP[21]), .B1(
n2721), .Y(n1748) );
AOI222X1TS U2392 ( .A0(n1653), .A1(n2629), .B0(n1651), .B1(n2628), .C0(n2672), .C1(n2626), .Y(n1766) );
AOI22X1TS U2393 ( .A0(n2671), .A1(n2659), .B0(n2753), .B1(n1634), .Y(n1751)
);
AOI22X1TS U2394 ( .A0(n2800), .A1(n1635), .B0(n1749), .B1(n2651), .Y(n1750)
);
OAI211XLTS U2395 ( .A0(n1766), .A1(n2651), .B0(n1751), .C0(n1750), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI22X1TS U2396 ( .A0(n2790), .A1(n2672), .B0(n1741), .B1(n2659), .Y(n1755)
);
AOI2BB2XLTS U2397 ( .B0(n1705), .B1(n2641), .A0N(n2658), .A1N(n1753), .Y(
n1754) );
OAI211XLTS U2398 ( .A0(n2666), .A1(n2644), .B0(n1755), .C0(n1754), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
AOI22X1TS U2399 ( .A0(n2671), .A1(n1634), .B0(n2793), .B1(n1602), .Y(n1758)
);
NOR2X1TS U2400 ( .A(n2255), .B(n2664), .Y(n2652) );
AOI22X1TS U2401 ( .A0(n2666), .A1(n2652), .B0(n1705), .B1(n2636), .Y(n1757)
);
OAI211XLTS U2402 ( .A0(n2666), .A1(n2639), .B0(n1758), .C0(n1757), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[26]) );
AOI22X1TS U2403 ( .A0(Add_Subt_result[22]), .A1(n2700), .B0(DmP[20]), .B1(
n2766), .Y(n1759) );
OAI21X4TS U2404 ( .A0(n1632), .A1(n1675), .B0(n1759), .Y(n2688) );
AOI22X1TS U2405 ( .A0(Add_Subt_result[34]), .A1(n2206), .B0(DmP[18]), .B1(
n2766), .Y(n1760) );
OAI21X4TS U2406 ( .A0(n3012), .A1(n2723), .B0(n1760), .Y(n2703) );
AOI22X1TS U2407 ( .A0(n2671), .A1(n2688), .B0(n1741), .B1(n2703), .Y(n1765)
);
AOI22X1TS U2408 ( .A0(Add_Subt_result[21]), .A1(n2700), .B0(DmP[19]), .B1(
n2815), .Y(n1761) );
OAI21X4TS U2409 ( .A0(n1633), .A1(n2786), .B0(n1761), .Y(n2695) );
INVX2TS U2410 ( .A(n1762), .Y(n2709) );
AOI21X1TS U2411 ( .A0(n2204), .A1(n2695), .B0(n1763), .Y(n1764) );
OAI211XLTS U2412 ( .A0(n2666), .A1(n1766), .B0(n1765), .C0(n1764), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
AOI22X2TS U2413 ( .A0(n1649), .A1(n1686), .B0(n2555), .B1(exp_oper_result[3]), .Y(n1841) );
NAND2X1TS U2414 ( .A(n1775), .B(n1841), .Y(n1772) );
INVX2TS U2415 ( .A(n1775), .Y(n1774) );
INVX2TS U2416 ( .A(n1657), .Y(n1806) );
INVX4TS U2417 ( .A(n1776), .Y(n1872) );
INVX4TS U2418 ( .A(n1776), .Y(n2114) );
NAND2X1TS U2419 ( .A(n1774), .B(n1841), .Y(n1842) );
NOR2X1TS U2420 ( .A(n1776), .B(n1842), .Y(n2454) );
BUFX3TS U2421 ( .A(n2454), .Y(n2476) );
AOI22X1TS U2422 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(n2559), .B1(n1659), .Y(n1778) );
AOI22X1TS U2423 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[71]), .A1(
n1584), .B0(n1640), .B1(n2457), .Y(n1777) );
OAI211X1TS U2424 ( .A0(n2114), .A1(n1819), .B0(n1778), .C0(n1777), .Y(n1780)
);
AOI22X1TS U2425 ( .A0(n2564), .A1(Sgf_normalized_result[8]), .B0(n1578),
.B1(n1780), .Y(n1779) );
OAI21XLTS U2426 ( .A0(n1786), .A1(n2116), .B0(n1779), .Y(n1450) );
AOI22X1TS U2427 ( .A0(n1770), .A1(Sgf_normalized_result[46]), .B0(n1585),
.B1(n1780), .Y(n1783) );
NAND2X1TS U2428 ( .A(n1578), .B(n1781), .Y(n1782) );
AOI22X1TS U2429 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(n2559), .B1(n1666), .Y(n1785) );
BUFX4TS U2430 ( .A(n2457), .Y(n2110) );
AOI22X1TS U2431 ( .A0(n2110), .A1(n1646), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(n1784) );
OAI211X1TS U2432 ( .A0(n1872), .A1(n1786), .B0(n1785), .C0(n1784), .Y(n1817)
);
AOI22X1TS U2433 ( .A0(n2564), .A1(Sgf_normalized_result[14]), .B0(n1578),
.B1(n1817), .Y(n1787) );
OAI21XLTS U2434 ( .A0(n1819), .A1(n2116), .B0(n1787), .Y(n1456) );
AOI22X1TS U2435 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(n2559), .B1(n1664), .Y(n1791) );
AOI22X1TS U2436 ( .A0(n2110), .A1(n1644), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(n1790) );
OAI211X1TS U2437 ( .A0(n1872), .A1(n1834), .B0(n1791), .C0(n1790), .Y(n1826)
);
AOI22X1TS U2438 ( .A0(n2564), .A1(Sgf_normalized_result[12]), .B0(n1578),
.B1(n1826), .Y(n1792) );
OAI21XLTS U2439 ( .A0(n1828), .A1(n2116), .B0(n1792), .Y(n1454) );
AOI22X1TS U2440 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(n2559), .B1(n1663), .Y(n1796) );
AOI22X1TS U2441 ( .A0(n2110), .A1(n1643), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(n1795) );
OAI211X1TS U2442 ( .A0(n1872), .A1(n1837), .B0(n1796), .C0(n1795), .Y(n1835)
);
AOI22X1TS U2443 ( .A0(n2564), .A1(Sgf_normalized_result[11]), .B0(n1578),
.B1(n1835), .Y(n1797) );
OAI21XLTS U2444 ( .A0(n1837), .A1(n2116), .B0(n1797), .Y(n1453) );
AOI22X1TS U2445 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(n2559), .B1(n1665), .Y(n1801) );
AOI22X1TS U2446 ( .A0(n2110), .A1(n1645), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(n1800) );
OAI211X1TS U2447 ( .A0(n1872), .A1(n1840), .B0(n1801), .C0(n1800), .Y(n1829)
);
AOI22X1TS U2448 ( .A0(n2564), .A1(Sgf_normalized_result[13]), .B0(n1578),
.B1(n1829), .Y(n1802) );
AOI22X1TS U2449 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(n2559), .B1(n1662), .Y(n1804) );
AOI22X1TS U2450 ( .A0(n2110), .A1(n1642), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n1803) );
OAI211X1TS U2451 ( .A0(n1872), .A1(n1828), .B0(n1804), .C0(n1803), .Y(n1832)
);
AOI22X1TS U2452 ( .A0(n2564), .A1(Sgf_normalized_result[10]), .B0(n1578),
.B1(n1832), .Y(n1805) );
OAI21XLTS U2453 ( .A0(n1834), .A1(n2116), .B0(n1805), .Y(n1452) );
AOI22X1TS U2454 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[62]), .B0(n2559), .B1(n1647), .Y(n1809) );
AOI22X1TS U2455 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(n1584), .B1(n1660), .Y(n1808) );
OAI211X1TS U2456 ( .A0(n2114), .A1(n1822), .B0(n1809), .C0(n1808), .Y(n1823)
);
AOI22X1TS U2457 ( .A0(n2564), .A1(Sgf_normalized_result[7]), .B0(n1578),
.B1(n1823), .Y(n1810) );
OAI21XLTS U2458 ( .A0(n1825), .A1(n2116), .B0(n1810), .Y(n1449) );
AOI22X1TS U2459 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(n2559), .B1(n1661), .Y(n1812) );
AOI22X1TS U2460 ( .A0(n2110), .A1(n1641), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(n1811) );
OAI211X1TS U2461 ( .A0(n2114), .A1(n1831), .B0(n1812), .C0(n1811), .Y(n1838)
);
AOI22X1TS U2462 ( .A0(n2564), .A1(Sgf_normalized_result[9]), .B0(n1578),
.B1(n1838), .Y(n1813) );
OAI21XLTS U2463 ( .A0(n1840), .A1(n2116), .B0(n1813), .Y(n1451) );
AOI22X1TS U2464 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(n2559), .B1(n1660), .Y(n1815) );
AOI22X1TS U2465 ( .A0(n2110), .A1(n1647), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(n1814) );
OAI211X1TS U2466 ( .A0(n1872), .A1(n1825), .B0(n1815), .C0(n1814), .Y(n1820)
);
AOI22X1TS U2467 ( .A0(n2564), .A1(Sgf_normalized_result[15]), .B0(n1578),
.B1(n1820), .Y(n1816) );
OAI21XLTS U2468 ( .A0(n1822), .A1(n2116), .B0(n1816), .Y(n1457) );
AOI22X1TS U2469 ( .A0(n1770), .A1(Sgf_normalized_result[40]), .B0(n1585),
.B1(n1817), .Y(n1818) );
OAI211XLTS U2470 ( .A0(n1819), .A1(n2138), .B0(n1818), .C0(n2136), .Y(n1482)
);
AOI22X1TS U2471 ( .A0(n1770), .A1(Sgf_normalized_result[39]), .B0(n1585),
.B1(n1820), .Y(n1821) );
OAI211XLTS U2472 ( .A0(n1822), .A1(n2138), .B0(n1821), .C0(n2136), .Y(n1481)
);
AOI22X1TS U2473 ( .A0(n1770), .A1(Sgf_normalized_result[47]), .B0(n1585),
.B1(n1823), .Y(n1824) );
OAI211XLTS U2474 ( .A0(n2138), .A1(n1825), .B0(n1824), .C0(n2136), .Y(n1489)
);
AOI22X1TS U2475 ( .A0(n1770), .A1(Sgf_normalized_result[42]), .B0(n1585),
.B1(n1826), .Y(n1827) );
OAI211XLTS U2476 ( .A0(n1828), .A1(n2138), .B0(n1827), .C0(n2136), .Y(n1484)
);
AOI22X1TS U2477 ( .A0(n1770), .A1(Sgf_normalized_result[41]), .B0(n1585),
.B1(n1829), .Y(n1830) );
OAI211XLTS U2478 ( .A0(n1831), .A1(n2138), .B0(n1830), .C0(n2136), .Y(n1483)
);
AOI22X1TS U2479 ( .A0(n1770), .A1(Sgf_normalized_result[44]), .B0(n1585),
.B1(n1832), .Y(n1833) );
OAI211XLTS U2480 ( .A0(n1834), .A1(n2138), .B0(n1833), .C0(n2136), .Y(n1486)
);
AOI22X1TS U2481 ( .A0(n1770), .A1(Sgf_normalized_result[43]), .B0(n1585),
.B1(n1835), .Y(n1836) );
OAI211XLTS U2482 ( .A0(n1837), .A1(n2138), .B0(n1836), .C0(n2136), .Y(n1485)
);
AOI22X1TS U2483 ( .A0(n1770), .A1(Sgf_normalized_result[45]), .B0(n1585),
.B1(n1838), .Y(n1839) );
OAI211XLTS U2484 ( .A0(n1840), .A1(n2138), .B0(n1839), .C0(n2136), .Y(n1487)
);
INVX2TS U2485 ( .A(n1842), .Y(n1868) );
AO22XLTS U2486 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n1843) );
AOI22X1TS U2487 ( .A0(n2560), .A1(n1642), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n1845) );
AOI22X1TS U2488 ( .A0(n2110), .A1(n1662), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n1844) );
OAI211X1TS U2489 ( .A0(n1872), .A1(n2125), .B0(n1845), .C0(n1844), .Y(n1882)
);
AOI22X1TS U2490 ( .A0(n2564), .A1(Sgf_normalized_result[18]), .B0(n1578),
.B1(n1882), .Y(n1846) );
OAI21XLTS U2491 ( .A0(n2091), .A1(n2116), .B0(n1846), .Y(n1460) );
AO22XLTS U2492 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n1847) );
AOI22X1TS U2493 ( .A0(n2560), .A1(n1645), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(n1849) );
AOI22X1TS U2494 ( .A0(n2457), .A1(n1665), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n1848) );
OAI211X1TS U2495 ( .A0(n1872), .A1(n2119), .B0(n1849), .C0(n1848), .Y(n1878)
);
AOI22X1TS U2496 ( .A0(n2564), .A1(Sgf_normalized_result[21]), .B0(n1578),
.B1(n1878), .Y(n1850) );
OAI21XLTS U2497 ( .A0(n2087), .A1(n2116), .B0(n1850), .Y(n1463) );
AO22XLTS U2498 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n1851) );
AOI22X1TS U2499 ( .A0(n2560), .A1(n1641), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(n1853) );
AOI22X1TS U2500 ( .A0(n2110), .A1(n1661), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n1852) );
OAI211X1TS U2501 ( .A0(n2114), .A1(n2128), .B0(n1853), .C0(n1852), .Y(n1880)
);
AOI22X1TS U2502 ( .A0(n2564), .A1(Sgf_normalized_result[17]), .B0(n1578),
.B1(n1880), .Y(n1854) );
OAI21XLTS U2503 ( .A0(n2104), .A1(n2116), .B0(n1854), .Y(n1459) );
AOI22X1TS U2504 ( .A0(n2110), .A1(n1666), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n1857) );
AOI22X1TS U2505 ( .A0(n2560), .A1(n1646), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(n1856) );
OAI211X1TS U2506 ( .A0(n1872), .A1(n2139), .B0(n1857), .C0(n1856), .Y(n1884)
);
AOI22X1TS U2507 ( .A0(n2564), .A1(Sgf_normalized_result[22]), .B0(n1578),
.B1(n1884), .Y(n1858) );
OAI21XLTS U2508 ( .A0(n2100), .A1(n2116), .B0(n1858), .Y(n1464) );
AO22XLTS U2509 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n1859) );
AOI22X1TS U2510 ( .A0(n2560), .A1(n1644), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(n1861) );
AOI22X1TS U2511 ( .A0(n2110), .A1(n1664), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n1860) );
OAI211X1TS U2512 ( .A0(n1872), .A1(n2122), .B0(n1861), .C0(n1860), .Y(n1876)
);
AOI22X1TS U2513 ( .A0(n2564), .A1(Sgf_normalized_result[20]), .B0(n1578),
.B1(n1876), .Y(n1862) );
OAI21XLTS U2514 ( .A0(n2095), .A1(n2116), .B0(n1862), .Y(n1462) );
AO22XLTS U2515 ( .A0(n1868), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(n1657), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n1863) );
AOI22X1TS U2516 ( .A0(n2560), .A1(n1643), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(n1865) );
AOI22X1TS U2517 ( .A0(n2110), .A1(n1663), .B0(n1584), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n1864) );
OAI211X1TS U2518 ( .A0(n1872), .A1(n2131), .B0(n1865), .C0(n1864), .Y(n1874)
);
AOI22X1TS U2519 ( .A0(n2564), .A1(Sgf_normalized_result[19]), .B0(n1578),
.B1(n1874), .Y(n1866) );
OAI21XLTS U2520 ( .A0(n2108), .A1(n2116), .B0(n1866), .Y(n1461) );
AOI22X1TS U2521 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[71]), .A1(
n2559), .B0(n1773), .B1(n1640), .Y(n1871) );
AOI22X1TS U2522 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[79]), .A1(
n1584), .B0(n2457), .B1(n1659), .Y(n1870) );
OAI211X1TS U2523 ( .A0(n1872), .A1(n2134), .B0(n1871), .C0(n1870), .Y(n1886)
);
AOI22X1TS U2524 ( .A0(n2564), .A1(Sgf_normalized_result[16]), .B0(n1578),
.B1(n1886), .Y(n1873) );
OAI21XLTS U2525 ( .A0(n2113), .A1(n2116), .B0(n1873), .Y(n1458) );
AOI22X1TS U2526 ( .A0(n1770), .A1(Sgf_normalized_result[35]), .B0(n1585),
.B1(n1874), .Y(n1875) );
OAI211XLTS U2527 ( .A0(n2108), .A1(n2138), .B0(n1875), .C0(n2136), .Y(n1477)
);
AOI22X1TS U2528 ( .A0(n1770), .A1(Sgf_normalized_result[34]), .B0(n1585),
.B1(n1876), .Y(n1877) );
OAI211XLTS U2529 ( .A0(n2095), .A1(n2138), .B0(n1877), .C0(n2136), .Y(n1476)
);
AOI22X1TS U2530 ( .A0(n1770), .A1(Sgf_normalized_result[33]), .B0(n1585),
.B1(n1878), .Y(n1879) );
OAI211XLTS U2531 ( .A0(n2087), .A1(n2138), .B0(n1879), .C0(n2136), .Y(n1475)
);
AOI22X1TS U2532 ( .A0(n1770), .A1(Sgf_normalized_result[37]), .B0(n1585),
.B1(n1880), .Y(n1881) );
OAI211XLTS U2533 ( .A0(n2104), .A1(n2138), .B0(n1881), .C0(n2136), .Y(n1479)
);
AOI22X1TS U2534 ( .A0(n1770), .A1(Sgf_normalized_result[36]), .B0(n1585),
.B1(n1882), .Y(n1883) );
OAI211XLTS U2535 ( .A0(n2091), .A1(n2138), .B0(n1883), .C0(n2136), .Y(n1478)
);
AOI22X1TS U2536 ( .A0(n2564), .A1(Sgf_normalized_result[32]), .B0(n1585),
.B1(n1884), .Y(n1885) );
AOI22X1TS U2537 ( .A0(n1770), .A1(Sgf_normalized_result[38]), .B0(n1585),
.B1(n1886), .Y(n1887) );
OAI211XLTS U2538 ( .A0(n2113), .A1(n2138), .B0(n1887), .C0(n2136), .Y(n1480)
);
NOR2XLTS U2539 ( .A(n3073), .B(intDY[53]), .Y(n1888) );
OAI22X1TS U2540 ( .A0(n3072), .A1(intDY[55]), .B0(intDY[54]), .B1(n2967),
.Y(n2007) );
AOI211X1TS U2541 ( .A0(intDX[52]), .A1(n2950), .B0(n1888), .C0(n2007), .Y(
n2009) );
NOR2BX1TS U2542 ( .AN(intDX[56]), .B(intDY[56]), .Y(n1889) );
NOR2X1TS U2543 ( .A(n2996), .B(intDY[57]), .Y(n1961) );
NAND2BXLTS U2544 ( .AN(intDY[62]), .B(intDX[62]), .Y(n1971) );
NAND2X1TS U2545 ( .A(n2941), .B(intDX[61]), .Y(n1967) );
OAI211X1TS U2546 ( .A0(intDY[60]), .A1(n3001), .B0(n1971), .C0(n1967), .Y(
n1973) );
OAI21X1TS U2547 ( .A0(intDY[58]), .A1(n3002), .B0(n1963), .Y(n1965) );
NOR2X1TS U2548 ( .A(n1654), .B(intDY[49]), .Y(n2010) );
OAI21X1TS U2549 ( .A0(intDY[50]), .A1(n3045), .B0(n2012), .Y(n2016) );
AOI211X1TS U2550 ( .A0(intDX[48]), .A1(n2948), .B0(n2010), .C0(n2016), .Y(
n1890) );
NAND3X1TS U2551 ( .A(n2009), .B(n2018), .C(n1890), .Y(n2026) );
NOR2BX1TS U2552 ( .AN(intDX[39]), .B(intDY[39]), .Y(n2001) );
AOI21X1TS U2553 ( .A0(intDX[38]), .A1(n2945), .B0(n2001), .Y(n2000) );
NAND2X1TS U2554 ( .A(n2951), .B(intDX[37]), .Y(n1989) );
OAI211X1TS U2555 ( .A0(intDY[36]), .A1(n3003), .B0(n2000), .C0(n1989), .Y(
n1991) );
NOR2X1TS U2556 ( .A(n2997), .B(intDY[45]), .Y(n1975) );
OAI21X1TS U2557 ( .A0(intDY[46]), .A1(n2989), .B0(n1974), .Y(n1984) );
OA22X1TS U2558 ( .A0(n2891), .A1(intDY[42]), .B0(n2998), .B1(intDY[43]), .Y(
n1980) );
NAND4XLTS U2559 ( .A(n1982), .B(n1980), .C(n1892), .D(n1891), .Y(n2024) );
OA22X1TS U2560 ( .A0(n2892), .A1(intDY[34]), .B0(n2999), .B1(intDY[35]), .Y(
n1995) );
OAI211XLTS U2561 ( .A0(n3000), .A1(intDY[33]), .B0(n1893), .C0(n1995), .Y(
n1894) );
NOR4X1TS U2562 ( .A(n2026), .B(n1991), .C(n2024), .D(n1894), .Y(n2030) );
OA22X1TS U2563 ( .A0(n2970), .A1(intDY[30]), .B0(n3074), .B1(intDY[31]), .Y(
n1905) );
OAI21XLTS U2564 ( .A0(intDY[29]), .A1(n2961), .B0(intDY[28]), .Y(n1895) );
OAI2BB2XLTS U2565 ( .B0(intDX[28]), .B1(n1895), .A0N(intDY[29]), .A1N(n2961),
.Y(n1904) );
OAI21X1TS U2566 ( .A0(intDY[26]), .A1(n3041), .B0(n1898), .Y(n1956) );
NOR2X1TS U2567 ( .A(n3040), .B(intDY[25]), .Y(n1953) );
NOR2XLTS U2568 ( .A(n1953), .B(intDX[24]), .Y(n1897) );
AOI22X1TS U2569 ( .A0(n1897), .A1(intDY[24]), .B0(intDY[25]), .B1(n3040),
.Y(n1900) );
OAI32X1TS U2570 ( .A0(n1956), .A1(n1955), .A2(n1900), .B0(n1899), .B1(n1955),
.Y(n1903) );
OAI21XLTS U2571 ( .A0(intDY[31]), .A1(n3074), .B0(intDY[30]), .Y(n1901) );
OAI2BB2XLTS U2572 ( .B0(intDX[30]), .B1(n1901), .A0N(intDY[31]), .A1N(n3074),
.Y(n1902) );
AOI211X1TS U2573 ( .A0(n1905), .A1(n1904), .B0(n1903), .C0(n1902), .Y(n1960)
);
OA22X1TS U2574 ( .A0(n2973), .A1(intDY[22]), .B0(n3075), .B1(intDY[23]), .Y(
n1952) );
OA22X1TS U2575 ( .A0(n2976), .A1(intDY[14]), .B0(n3077), .B1(intDY[15]), .Y(
n1933) );
OAI2BB1X1TS U2576 ( .A0N(n2952), .A1N(intDX[5]), .B0(intDY[4]), .Y(n1908) );
OAI22X1TS U2577 ( .A0(intDX[4]), .A1(n1908), .B0(n2952), .B1(intDX[5]), .Y(
n1919) );
OAI2BB1X1TS U2578 ( .A0N(n2885), .A1N(intDX[7]), .B0(intDY[6]), .Y(n1909) );
OAI22X1TS U2579 ( .A0(intDX[6]), .A1(n1909), .B0(n2885), .B1(intDX[7]), .Y(
n1918) );
AOI2BB2XLTS U2580 ( .B0(intDX[1]), .B1(n2939), .A0N(intDY[0]), .A1N(n1910),
.Y(n1911) );
OAI211XLTS U2581 ( .A0(n2960), .A1(intDY[3]), .B0(n1912), .C0(n1911), .Y(
n1915) );
OAI21XLTS U2582 ( .A0(intDY[3]), .A1(n2960), .B0(intDY[2]), .Y(n1913) );
AOI2BB2XLTS U2583 ( .B0(intDY[3]), .B1(n2960), .A0N(intDX[2]), .A1N(n1913),
.Y(n1914) );
AOI222X1TS U2584 ( .A0(intDX[4]), .A1(n2883), .B0(intDX[5]), .B1(n2952),
.C0(n1915), .C1(n1914), .Y(n1917) );
AOI22X1TS U2585 ( .A0(intDX[7]), .A1(n2885), .B0(intDX[6]), .B1(n2957), .Y(
n1916) );
OAI32X1TS U2586 ( .A0(n1919), .A1(n1918), .A2(n1917), .B0(n1916), .B1(n1918),
.Y(n1936) );
NOR2X1TS U2587 ( .A(n3042), .B(intDY[11]), .Y(n1921) );
AOI21X1TS U2588 ( .A0(intDX[10]), .A1(n2949), .B0(n1921), .Y(n1926) );
OAI211XLTS U2589 ( .A0(intDY[8]), .A1(n2963), .B0(n1923), .C0(n1926), .Y(
n1935) );
OAI21XLTS U2590 ( .A0(intDY[13]), .A1(n2962), .B0(intDY[12]), .Y(n1920) );
OAI2BB2XLTS U2591 ( .B0(intDX[12]), .B1(n1920), .A0N(intDY[13]), .A1N(n2962),
.Y(n1932) );
NOR2XLTS U2592 ( .A(n1921), .B(intDX[10]), .Y(n1922) );
AOI22X1TS U2593 ( .A0(intDY[11]), .A1(n3042), .B0(intDY[10]), .B1(n1922),
.Y(n1928) );
NAND3XLTS U2594 ( .A(n2963), .B(n1923), .C(intDY[8]), .Y(n1925) );
NAND2BXLTS U2595 ( .AN(intDX[9]), .B(intDY[9]), .Y(n1924) );
AOI21X1TS U2596 ( .A0(n1925), .A1(n1924), .B0(n1937), .Y(n1927) );
OAI2BB2XLTS U2597 ( .B0(n1928), .B1(n1937), .A0N(n1927), .A1N(n1926), .Y(
n1931) );
OAI21XLTS U2598 ( .A0(intDY[15]), .A1(n3077), .B0(intDY[14]), .Y(n1929) );
OAI2BB2XLTS U2599 ( .B0(intDX[14]), .B1(n1929), .A0N(intDY[15]), .A1N(n3077),
.Y(n1930) );
AOI211X1TS U2600 ( .A0(n1933), .A1(n1932), .B0(n1931), .C0(n1930), .Y(n1934)
);
OAI31X1TS U2601 ( .A0(n1937), .A1(n1936), .A2(n1935), .B0(n1934), .Y(n1939)
);
NOR2X1TS U2602 ( .A(n3043), .B(intDY[17]), .Y(n1941) );
OAI21X1TS U2603 ( .A0(intDY[18]), .A1(n3076), .B0(n1943), .Y(n1947) );
AOI211XLTS U2604 ( .A0(intDX[16]), .A1(n2956), .B0(n1941), .C0(n1947), .Y(
n1938) );
NAND3BXLTS U2605 ( .AN(n1946), .B(n1939), .C(n1938), .Y(n1959) );
OAI21XLTS U2606 ( .A0(intDY[21]), .A1(n2981), .B0(intDY[20]), .Y(n1940) );
OAI2BB2XLTS U2607 ( .B0(intDX[20]), .B1(n1940), .A0N(intDY[21]), .A1N(n2981),
.Y(n1951) );
AOI22X1TS U2608 ( .A0(n1942), .A1(intDY[16]), .B0(intDY[17]), .B1(n3043),
.Y(n1945) );
OAI32X1TS U2609 ( .A0(n1947), .A1(n1946), .A2(n1945), .B0(n1944), .B1(n1946),
.Y(n1950) );
OAI21XLTS U2610 ( .A0(intDY[23]), .A1(n3075), .B0(intDY[22]), .Y(n1948) );
OAI2BB2XLTS U2611 ( .B0(intDX[22]), .B1(n1948), .A0N(intDY[23]), .A1N(n3075),
.Y(n1949) );
AOI211X1TS U2612 ( .A0(n1952), .A1(n1951), .B0(n1950), .C0(n1949), .Y(n1958)
);
NOR2BX1TS U2613 ( .AN(intDX[24]), .B(intDY[24]), .Y(n1954) );
OR4X2TS U2614 ( .A(n1956), .B(n1955), .C(n1954), .D(n1953), .Y(n1957) );
AOI32X1TS U2615 ( .A0(n1960), .A1(n1959), .A2(n1958), .B0(n1957), .B1(n1960),
.Y(n2029) );
NOR2XLTS U2616 ( .A(n1961), .B(intDX[56]), .Y(n1962) );
AOI22X1TS U2617 ( .A0(intDY[57]), .A1(n2996), .B0(intDY[56]), .B1(n1962),
.Y(n1966) );
OA21XLTS U2618 ( .A0(n1966), .A1(n1965), .B0(n1964), .Y(n1972) );
NAND2BXLTS U2619 ( .AN(intDX[62]), .B(intDY[62]), .Y(n1969) );
NAND3XLTS U2620 ( .A(n3001), .B(n1967), .C(intDY[60]), .Y(n1968) );
OAI211XLTS U2621 ( .A0(intDX[61]), .A1(n2941), .B0(n1969), .C0(n1968), .Y(
n1970) );
NOR2BX1TS U2622 ( .AN(n1974), .B(intDX[46]), .Y(n1988) );
NOR2XLTS U2623 ( .A(n1975), .B(intDX[44]), .Y(n1976) );
AOI22X1TS U2624 ( .A0(intDY[45]), .A1(n2997), .B0(intDY[44]), .B1(n1976),
.Y(n1985) );
OAI21XLTS U2625 ( .A0(intDY[41]), .A1(n1652), .B0(intDY[40]), .Y(n1977) );
OAI2BB2XLTS U2626 ( .B0(intDX[40]), .B1(n1977), .A0N(intDY[41]), .A1N(n1652),
.Y(n1981) );
OAI21XLTS U2627 ( .A0(intDY[43]), .A1(n2998), .B0(intDY[42]), .Y(n1978) );
OAI2BB2XLTS U2628 ( .B0(intDX[42]), .B1(n1978), .A0N(intDY[43]), .A1N(n2998),
.Y(n1979) );
AOI32X1TS U2629 ( .A0(n1982), .A1(n1981), .A2(n1980), .B0(n1979), .B1(n1982),
.Y(n1983) );
NOR2BX1TS U2630 ( .AN(intDY[47]), .B(intDX[47]), .Y(n1986) );
AOI211X1TS U2631 ( .A0(intDY[46]), .A1(n1988), .B0(n1987), .C0(n1986), .Y(
n2025) );
NAND3XLTS U2632 ( .A(n3003), .B(n1989), .C(intDY[36]), .Y(n1990) );
OAI21XLTS U2633 ( .A0(intDX[37]), .A1(n2951), .B0(n1990), .Y(n1999) );
INVX2TS U2634 ( .A(n1991), .Y(n1997) );
OAI21XLTS U2635 ( .A0(intDY[33]), .A1(n3000), .B0(intDY[32]), .Y(n1992) );
OAI2BB2XLTS U2636 ( .B0(intDX[32]), .B1(n1992), .A0N(intDY[33]), .A1N(n3000),
.Y(n1996) );
OAI2BB2XLTS U2637 ( .B0(intDX[34]), .B1(n1993), .A0N(intDY[35]), .A1N(n2999),
.Y(n1994) );
AOI32X1TS U2638 ( .A0(n1997), .A1(n1996), .A2(n1995), .B0(n1994), .B1(n1997),
.Y(n1998) );
OAI2BB1X1TS U2639 ( .A0N(n2000), .A1N(n1999), .B0(n1998), .Y(n2005) );
NOR2BX1TS U2640 ( .AN(intDY[39]), .B(intDX[39]), .Y(n2004) );
NOR3X1TS U2641 ( .A(n2945), .B(n2001), .C(intDX[38]), .Y(n2003) );
INVX2TS U2642 ( .A(n2026), .Y(n2002) );
OAI31X1TS U2643 ( .A0(n2005), .A1(n2004), .A2(n2003), .B0(n2002), .Y(n2023)
);
OAI21XLTS U2644 ( .A0(intDY[53]), .A1(n3073), .B0(intDY[52]), .Y(n2006) );
AOI2BB2XLTS U2645 ( .B0(intDY[53]), .B1(n3073), .A0N(intDX[52]), .A1N(n2006),
.Y(n2008) );
NOR2XLTS U2646 ( .A(n2008), .B(n2007), .Y(n2021) );
INVX2TS U2647 ( .A(n2009), .Y(n2015) );
AOI22X1TS U2648 ( .A0(intDY[49]), .A1(n1654), .B0(intDY[48]), .B1(n2011),
.Y(n2014) );
OAI32X1TS U2649 ( .A0(n2016), .A1(n2015), .A2(n2014), .B0(n2013), .B1(n2015),
.Y(n2020) );
OAI21XLTS U2650 ( .A0(intDY[55]), .A1(n3072), .B0(intDY[54]), .Y(n2017) );
OAI2BB2XLTS U2651 ( .B0(intDX[54]), .B1(n2017), .A0N(intDY[55]), .A1N(n3072),
.Y(n2019) );
OAI31X1TS U2652 ( .A0(n2021), .A1(n2020), .A2(n2019), .B0(n2018), .Y(n2022)
);
OAI221X1TS U2653 ( .A0(n2026), .A1(n2025), .B0(n2024), .B1(n2023), .C0(n2022), .Y(n2027) );
AOI211X2TS U2654 ( .A0(n2030), .A1(n2029), .B0(n2028), .C0(n2027), .Y(n2864)
);
CLKBUFX2TS U2655 ( .A(n2868), .Y(n2164) );
NOR2X1TS U2656 ( .A(n2864), .B(n2865), .Y(n2042) );
AOI22X1TS U2657 ( .A0(n2072), .A1(intDY[3]), .B0(DmP[3]), .B1(n2223), .Y(
n2031) );
OAI21XLTS U2658 ( .A0(n2960), .A1(n2035), .B0(n2031), .Y(n1108) );
AOI22X1TS U2659 ( .A0(n2072), .A1(intDY[4]), .B0(DmP[4]), .B1(n2238), .Y(
n2032) );
OAI21XLTS U2660 ( .A0(n2980), .A1(n2035), .B0(n2032), .Y(n1109) );
AOI22X1TS U2661 ( .A0(n2072), .A1(intDY[2]), .B0(DmP[2]), .B1(n2238), .Y(
n2033) );
OAI21XLTS U2662 ( .A0(n2887), .A1(n2035), .B0(n2033), .Y(n1107) );
AOI22X1TS U2663 ( .A0(n2072), .A1(intDY[5]), .B0(DmP[5]), .B1(n2238), .Y(
n2034) );
OAI21XLTS U2664 ( .A0(n2884), .A1(n2035), .B0(n2034), .Y(n1110) );
AOI22X1TS U2665 ( .A0(n2083), .A1(intDY[12]), .B0(DMP[12]), .B1(n2238), .Y(
n2036) );
OAI21XLTS U2666 ( .A0(n2977), .A1(n2041), .B0(n2036), .Y(n1181) );
AOI22X1TS U2667 ( .A0(n2083), .A1(intDY[17]), .B0(DMP[17]), .B1(n2226), .Y(
n2037) );
OAI21XLTS U2668 ( .A0(n3043), .A1(n2041), .B0(n2037), .Y(n1186) );
AOI22X1TS U2669 ( .A0(n2083), .A1(intDY[11]), .B0(DMP[11]), .B1(n2228), .Y(
n2038) );
OAI21XLTS U2670 ( .A0(n3042), .A1(n2041), .B0(n2038), .Y(n1180) );
AOI22X1TS U2671 ( .A0(n2083), .A1(intDY[13]), .B0(DMP[13]), .B1(n2223), .Y(
n2039) );
OAI21XLTS U2672 ( .A0(n2962), .A1(n2041), .B0(n2039), .Y(n1182) );
AOI22X1TS U2673 ( .A0(n2083), .A1(intDY[15]), .B0(DMP[15]), .B1(n2223), .Y(
n2040) );
OAI21XLTS U2674 ( .A0(n3077), .A1(n2041), .B0(n2040), .Y(n1184) );
CLKBUFX3TS U2675 ( .A(n2041), .Y(n2237) );
AOI22X1TS U2676 ( .A0(n2042), .A1(intDY[1]), .B0(DMP[1]), .B1(n2223), .Y(
n2043) );
OAI21XLTS U2677 ( .A0(n2893), .A1(n2237), .B0(n2043), .Y(n1170) );
BUFX3TS U2678 ( .A(n2035), .Y(n2177) );
AOI22X1TS U2679 ( .A0(n2072), .A1(intDY[58]), .B0(DmP[58]), .B1(n2226), .Y(
n2044) );
OAI21XLTS U2680 ( .A0(n3002), .A1(n2177), .B0(n2044), .Y(n1163) );
AOI22X1TS U2681 ( .A0(n2072), .A1(intDY[0]), .B0(DmP[0]), .B1(n2226), .Y(
n2045) );
OAI21XLTS U2682 ( .A0(n2964), .A1(n2177), .B0(n2045), .Y(n1105) );
BUFX4TS U2683 ( .A(n2041), .Y(n2241) );
AOI22X1TS U2684 ( .A0(n2083), .A1(intDY[28]), .B0(DMP[28]), .B1(n2228), .Y(
n2046) );
OAI21XLTS U2685 ( .A0(n2971), .A1(n2241), .B0(n2046), .Y(n1197) );
AOI22X1TS U2686 ( .A0(n2083), .A1(intDY[29]), .B0(DMP[29]), .B1(n2223), .Y(
n2047) );
AOI22X1TS U2687 ( .A0(n2083), .A1(intDY[35]), .B0(DMP[35]), .B1(n2228), .Y(
n2048) );
OAI21XLTS U2688 ( .A0(n2999), .A1(n2241), .B0(n2048), .Y(n1204) );
AOI22X1TS U2689 ( .A0(n2083), .A1(intDY[32]), .B0(DMP[32]), .B1(n2228), .Y(
n2049) );
OAI21XLTS U2690 ( .A0(n2969), .A1(n2241), .B0(n2049), .Y(n1201) );
AOI22X1TS U2691 ( .A0(n2083), .A1(intDY[33]), .B0(DMP[33]), .B1(n2223), .Y(
n2050) );
OAI21XLTS U2692 ( .A0(n3000), .A1(n2241), .B0(n2050), .Y(n1202) );
AOI22X1TS U2693 ( .A0(n2083), .A1(intDY[31]), .B0(DMP[31]), .B1(n2228), .Y(
n2051) );
OAI21XLTS U2694 ( .A0(n3074), .A1(n2241), .B0(n2051), .Y(n1200) );
AOI22X1TS U2695 ( .A0(n2083), .A1(intDY[30]), .B0(DMP[30]), .B1(n2228), .Y(
n2052) );
OAI21XLTS U2696 ( .A0(n2970), .A1(n2241), .B0(n2052), .Y(n1199) );
AOI22X1TS U2697 ( .A0(n2083), .A1(intDY[34]), .B0(DMP[34]), .B1(n2223), .Y(
n2053) );
OAI21XLTS U2698 ( .A0(n2892), .A1(n2241), .B0(n2053), .Y(n1203) );
AOI22X1TS U2699 ( .A0(n2074), .A1(intDY[12]), .B0(DmP[12]), .B1(n2865), .Y(
n2054) );
OAI21XLTS U2700 ( .A0(n2977), .A1(n2177), .B0(n2054), .Y(n1117) );
AOI22X1TS U2701 ( .A0(n2074), .A1(intDY[57]), .B0(DmP[57]), .B1(n2238), .Y(
n2055) );
OAI21XLTS U2702 ( .A0(n2996), .A1(n2177), .B0(n2055), .Y(n1162) );
AOI22X1TS U2703 ( .A0(n2074), .A1(intDY[59]), .B0(DmP[59]), .B1(n2226), .Y(
n2056) );
OAI21XLTS U2704 ( .A0(n2895), .A1(n2177), .B0(n2056), .Y(n1164) );
AOI22X1TS U2705 ( .A0(n2074), .A1(intDY[60]), .B0(DmP[60]), .B1(n2238), .Y(
n2057) );
OAI21XLTS U2706 ( .A0(n3001), .A1(n2177), .B0(n2057), .Y(n1165) );
AOI22X1TS U2707 ( .A0(n2074), .A1(intDY[56]), .B0(DmP[56]), .B1(n2238), .Y(
n2058) );
OAI21XLTS U2708 ( .A0(n2966), .A1(n2177), .B0(n2058), .Y(n1161) );
BUFX3TS U2709 ( .A(n2035), .Y(n2153) );
AOI22X1TS U2710 ( .A0(n2072), .A1(intDY[11]), .B0(DmP[11]), .B1(n2865), .Y(
n2059) );
OAI21XLTS U2711 ( .A0(n3042), .A1(n2153), .B0(n2059), .Y(n1116) );
AOI22X1TS U2712 ( .A0(n2074), .A1(intDY[14]), .B0(DmP[14]), .B1(n2226), .Y(
n2060) );
OAI21XLTS U2713 ( .A0(n2976), .A1(n2153), .B0(n2060), .Y(n1119) );
AOI22X1TS U2714 ( .A0(n2072), .A1(intDY[10]), .B0(DmP[10]), .B1(n2226), .Y(
n2061) );
AOI22X1TS U2715 ( .A0(n2074), .A1(intDY[16]), .B0(DmP[16]), .B1(n2238), .Y(
n2062) );
OAI21XLTS U2716 ( .A0(n2975), .A1(n2153), .B0(n2062), .Y(n1121) );
AOI22X1TS U2717 ( .A0(n2074), .A1(intDY[15]), .B0(DmP[15]), .B1(n2226), .Y(
n2063) );
OAI21XLTS U2718 ( .A0(n3077), .A1(n2153), .B0(n2063), .Y(n1120) );
BUFX3TS U2719 ( .A(n2035), .Y(n2192) );
AOI22X1TS U2720 ( .A0(n2074), .A1(intDY[53]), .B0(DmP[53]), .B1(n2226), .Y(
n2064) );
OAI21XLTS U2721 ( .A0(n3073), .A1(n2192), .B0(n2064), .Y(n1158) );
BUFX3TS U2722 ( .A(n2035), .Y(n2188) );
AOI22X1TS U2723 ( .A0(n2074), .A1(intDY[62]), .B0(DmP[62]), .B1(n2223), .Y(
n2065) );
OAI21XLTS U2724 ( .A0(n2894), .A1(n2188), .B0(n2065), .Y(n1104) );
AOI22X1TS U2725 ( .A0(n2072), .A1(intDY[1]), .B0(DmP[1]), .B1(n2226), .Y(
n2066) );
OAI21XLTS U2726 ( .A0(n2893), .A1(n2188), .B0(n2066), .Y(n1106) );
AOI22X1TS U2727 ( .A0(n2072), .A1(intDY[7]), .B0(DmP[7]), .B1(n2238), .Y(
n2067) );
OAI21XLTS U2728 ( .A0(n2955), .A1(n2192), .B0(n2067), .Y(n1112) );
AOI22X1TS U2729 ( .A0(n2189), .A1(intDY[13]), .B0(DmP[13]), .B1(n2238), .Y(
n2068) );
OAI21XLTS U2730 ( .A0(n2962), .A1(n2188), .B0(n2068), .Y(n1118) );
AOI22X1TS U2731 ( .A0(n2074), .A1(intDY[52]), .B0(DmP[52]), .B1(n2226), .Y(
n2069) );
AOI22X1TS U2732 ( .A0(n2072), .A1(intDY[9]), .B0(DmP[9]), .B1(n2238), .Y(
n2070) );
OAI21XLTS U2733 ( .A0(n2886), .A1(n2188), .B0(n2070), .Y(n1114) );
AOI22X1TS U2734 ( .A0(n2072), .A1(intDY[8]), .B0(DmP[8]), .B1(n2238), .Y(
n2071) );
OAI21XLTS U2735 ( .A0(n2963), .A1(n2192), .B0(n2071), .Y(n1113) );
AOI22X1TS U2736 ( .A0(n2072), .A1(intDY[6]), .B0(DmP[6]), .B1(n2226), .Y(
n2073) );
OAI21XLTS U2737 ( .A0(n2979), .A1(n2192), .B0(n2073), .Y(n1111) );
AOI22X1TS U2738 ( .A0(n2162), .A1(intDY[54]), .B0(DmP[54]), .B1(n2238), .Y(
n2075) );
OAI21XLTS U2739 ( .A0(n2967), .A1(n2192), .B0(n2075), .Y(n1159) );
AOI22X1TS U2740 ( .A0(n2083), .A1(intDY[25]), .B0(DMP[25]), .B1(n2223), .Y(
n2076) );
OAI21XLTS U2741 ( .A0(n3040), .A1(n1577), .B0(n2076), .Y(n1194) );
AOI22X1TS U2742 ( .A0(n2083), .A1(intDY[23]), .B0(DMP[23]), .B1(n2228), .Y(
n2077) );
OAI21XLTS U2743 ( .A0(n3075), .A1(n1577), .B0(n2077), .Y(n1192) );
AOI22X1TS U2744 ( .A0(n2083), .A1(intDY[24]), .B0(DMP[24]), .B1(n2228), .Y(
n2078) );
OAI21XLTS U2745 ( .A0(n2972), .A1(n1577), .B0(n2078), .Y(n1193) );
AOI22X1TS U2746 ( .A0(n2083), .A1(intDY[20]), .B0(DMP[20]), .B1(n2228), .Y(
n2079) );
OAI21XLTS U2747 ( .A0(n2974), .A1(n1577), .B0(n2079), .Y(n1189) );
AOI22X1TS U2748 ( .A0(n2083), .A1(intDY[27]), .B0(DMP[27]), .B1(n2223), .Y(
n2080) );
OAI21XLTS U2749 ( .A0(n2984), .A1(n1577), .B0(n2080), .Y(n1196) );
AOI22X1TS U2750 ( .A0(n2083), .A1(intDY[18]), .B0(DMP[18]), .B1(n2223), .Y(
n2081) );
OAI21XLTS U2751 ( .A0(n3076), .A1(n1577), .B0(n2081), .Y(n1187) );
AOI22X1TS U2752 ( .A0(n2083), .A1(intDY[26]), .B0(DMP[26]), .B1(n2228), .Y(
n2082) );
OAI21XLTS U2753 ( .A0(n3041), .A1(n1577), .B0(n2082), .Y(n1195) );
AOI22X1TS U2754 ( .A0(n2083), .A1(intDY[21]), .B0(DMP[21]), .B1(n2190), .Y(
n2084) );
OAI21XLTS U2755 ( .A0(n2981), .A1(n1577), .B0(n2084), .Y(n1190) );
AOI22X1TS U2756 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[56]), .B0(n2559), .B1(n1641), .Y(n2086) );
AOI22X1TS U2757 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(n1584), .B1(n1661), .Y(n2085) );
OAI211X1TS U2758 ( .A0(n2114), .A1(n2087), .B0(n2086), .C0(n2085), .Y(n2117)
);
AOI22X1TS U2759 ( .A0(n2564), .A1(Sgf_normalized_result[1]), .B0(n1578),
.B1(n2117), .Y(n2088) );
OAI21XLTS U2760 ( .A0(n2119), .A1(n2116), .B0(n2088), .Y(n1443) );
AOI22X1TS U2761 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[59]), .B0(n2476), .B1(n1644), .Y(n2090) );
AOI22X1TS U2762 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(n1584), .B1(n1664), .Y(n2089) );
OAI211X1TS U2763 ( .A0(n2114), .A1(n2091), .B0(n2090), .C0(n2089), .Y(n2123)
);
AOI22X1TS U2764 ( .A0(n2564), .A1(Sgf_normalized_result[4]), .B0(n1578),
.B1(n2123), .Y(n2092) );
OAI21XLTS U2765 ( .A0(n2125), .A1(n2116), .B0(n2092), .Y(n1446) );
AOI22X1TS U2766 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[57]), .B0(n2476), .B1(n1642), .Y(n2094) );
AOI22X1TS U2767 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(n1584), .B1(n1662), .Y(n2093) );
OAI211X1TS U2768 ( .A0(n2114), .A1(n2095), .B0(n2094), .C0(n2093), .Y(n2120)
);
AOI22X1TS U2769 ( .A0(n2564), .A1(Sgf_normalized_result[2]), .B0(n1578),
.B1(n2120), .Y(n2096) );
OAI21XLTS U2770 ( .A0(n2122), .A1(n2116), .B0(n2096), .Y(n1444) );
AOI22X1TS U2771 ( .A0(n2457), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(n1584), .B1(n1659), .Y(n2099) );
AOI22X1TS U2772 ( .A0(n1773), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[55]), .B0(n2559), .B1(n1640), .Y(n2098) );
OAI211X1TS U2773 ( .A0(n2114), .A1(n2100), .B0(n2099), .C0(n2098), .Y(n2135)
);
AOI22X1TS U2774 ( .A0(n2564), .A1(Sgf_normalized_result[0]), .B0(n1578),
.B1(n2135), .Y(n2101) );
AOI22X1TS U2775 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[60]), .B0(n2476), .B1(n1645), .Y(n2103) );
AOI22X1TS U2776 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(n1584), .B1(n1665), .Y(n2102) );
OAI211X1TS U2777 ( .A0(n2114), .A1(n2104), .B0(n2103), .C0(n2102), .Y(n2126)
);
AOI22X1TS U2778 ( .A0(n2564), .A1(Sgf_normalized_result[5]), .B0(n1578),
.B1(n2126), .Y(n2105) );
OAI21XLTS U2779 ( .A0(n2128), .A1(n2116), .B0(n2105), .Y(n1447) );
AOI22X1TS U2780 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[58]), .B0(n2476), .B1(n1643), .Y(n2107) );
AOI22X1TS U2781 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(n1584), .B1(n1663), .Y(n2106) );
OAI211X1TS U2782 ( .A0(n2114), .A1(n2108), .B0(n2107), .C0(n2106), .Y(n2129)
);
AOI22X1TS U2783 ( .A0(n2564), .A1(Sgf_normalized_result[3]), .B0(n1578),
.B1(n2129), .Y(n2109) );
OAI21XLTS U2784 ( .A0(n2131), .A1(n2116), .B0(n2109), .Y(n1445) );
AOI22X1TS U2785 ( .A0(n2560), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[61]), .B0(n2476), .B1(n1646), .Y(n2112) );
AOI22X1TS U2786 ( .A0(n2110), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(n1584), .B1(n1666), .Y(n2111) );
OAI211X1TS U2787 ( .A0(n2114), .A1(n2113), .B0(n2112), .C0(n2111), .Y(n2132)
);
AOI22X1TS U2788 ( .A0(n2564), .A1(Sgf_normalized_result[6]), .B0(n1578),
.B1(n2132), .Y(n2115) );
OAI21XLTS U2789 ( .A0(n2134), .A1(n2116), .B0(n2115), .Y(n1448) );
AOI22X1TS U2790 ( .A0(n1770), .A1(Sgf_normalized_result[53]), .B0(n1585),
.B1(n2117), .Y(n2118) );
OAI211XLTS U2791 ( .A0(n2138), .A1(n2119), .B0(n2118), .C0(n2136), .Y(n1495)
);
AOI22X1TS U2792 ( .A0(n1770), .A1(Sgf_normalized_result[52]), .B0(n1585),
.B1(n2120), .Y(n2121) );
OAI211XLTS U2793 ( .A0(n2138), .A1(n2122), .B0(n2121), .C0(n2136), .Y(n1494)
);
AOI22X1TS U2794 ( .A0(n1770), .A1(Sgf_normalized_result[50]), .B0(n1585),
.B1(n2123), .Y(n2124) );
OAI211XLTS U2795 ( .A0(n2138), .A1(n2125), .B0(n2124), .C0(n2136), .Y(n1492)
);
AOI22X1TS U2796 ( .A0(n1770), .A1(Sgf_normalized_result[49]), .B0(n1585),
.B1(n2126), .Y(n2127) );
OAI211XLTS U2797 ( .A0(n2138), .A1(n2128), .B0(n2127), .C0(n2136), .Y(n1491)
);
AOI22X1TS U2798 ( .A0(n1770), .A1(Sgf_normalized_result[51]), .B0(n1585),
.B1(n2129), .Y(n2130) );
OAI211XLTS U2799 ( .A0(n2138), .A1(n2131), .B0(n2130), .C0(n2136), .Y(n1493)
);
AOI22X1TS U2800 ( .A0(n1770), .A1(Sgf_normalized_result[48]), .B0(n1585),
.B1(n2132), .Y(n2133) );
OAI211XLTS U2801 ( .A0(n2138), .A1(n2134), .B0(n2133), .C0(n2136), .Y(n1490)
);
AOI22X1TS U2802 ( .A0(n1770), .A1(Sgf_normalized_result[54]), .B0(n1585),
.B1(n2135), .Y(n2137) );
OAI211XLTS U2803 ( .A0(n2139), .A1(n2138), .B0(n2137), .C0(n2136), .Y(n1563)
);
AOI22X1TS U2804 ( .A0(n2162), .A1(intDY[61]), .B0(DmP[61]), .B1(n2238), .Y(
n2140) );
OAI21XLTS U2805 ( .A0(n2965), .A1(n2177), .B0(n2140), .Y(n1166) );
AOI22X1TS U2806 ( .A0(DmP[42]), .A1(n2190), .B0(intDY[42]), .B1(n2162), .Y(
n2141) );
OAI21XLTS U2807 ( .A0(n2891), .A1(n2035), .B0(n2141), .Y(n1147) );
AOI22X1TS U2808 ( .A0(n2223), .A1(DmP[48]), .B0(intDY[48]), .B1(n2162), .Y(
n2142) );
OAI21XLTS U2809 ( .A0(n2988), .A1(n2035), .B0(n2142), .Y(n1153) );
AOI22X1TS U2810 ( .A0(DmP[38]), .A1(n2228), .B0(intDY[38]), .B1(n2189), .Y(
n2143) );
AOI22X1TS U2811 ( .A0(DmP[40]), .A1(n2223), .B0(intDY[40]), .B1(n2162), .Y(
n2144) );
OAI21XLTS U2812 ( .A0(n2991), .A1(n2177), .B0(n2144), .Y(n1145) );
AOI22X1TS U2813 ( .A0(DmP[19]), .A1(n2228), .B0(intDY[19]), .B1(n2189), .Y(
n2145) );
OAI21XLTS U2814 ( .A0(n2985), .A1(n2153), .B0(n2145), .Y(n1124) );
AOI22X1TS U2815 ( .A0(n2189), .A1(intDY[55]), .B0(DmP[55]), .B1(n2238), .Y(
n2146) );
OAI21XLTS U2816 ( .A0(n3072), .A1(n2177), .B0(n2146), .Y(n1160) );
AOI22X1TS U2817 ( .A0(DmP[37]), .A1(n2865), .B0(intDY[37]), .B1(n2162), .Y(
n2147) );
OAI21XLTS U2818 ( .A0(n2890), .A1(n2153), .B0(n2147), .Y(n1142) );
AOI22X1TS U2819 ( .A0(DmP[35]), .A1(n2223), .B0(intDY[35]), .B1(n2189), .Y(
n2148) );
OAI21XLTS U2820 ( .A0(n2999), .A1(n2153), .B0(n2148), .Y(n1140) );
AOI22X1TS U2821 ( .A0(DmP[20]), .A1(n2190), .B0(intDY[20]), .B1(n2162), .Y(
n2149) );
OAI21XLTS U2822 ( .A0(n2974), .A1(n2153), .B0(n2149), .Y(n1125) );
AOI22X1TS U2823 ( .A0(DmP[36]), .A1(n2190), .B0(intDY[36]), .B1(n2162), .Y(
n2150) );
OAI21XLTS U2824 ( .A0(n3003), .A1(n2153), .B0(n2150), .Y(n1141) );
AOI22X1TS U2825 ( .A0(n2865), .A1(DmP[17]), .B0(intDY[17]), .B1(n2189), .Y(
n2151) );
OAI21XLTS U2826 ( .A0(n3043), .A1(n2153), .B0(n2151), .Y(n1122) );
AOI22X1TS U2827 ( .A0(DmP[18]), .A1(n2190), .B0(intDY[18]), .B1(n2189), .Y(
n2152) );
OAI21XLTS U2828 ( .A0(n3076), .A1(n2153), .B0(n2152), .Y(n1123) );
AOI22X1TS U2829 ( .A0(DmP[32]), .A1(n2190), .B0(intDY[32]), .B1(n2189), .Y(
n2154) );
OAI21XLTS U2830 ( .A0(n2969), .A1(n2188), .B0(n2154), .Y(n1137) );
AOI22X1TS U2831 ( .A0(DmP[34]), .A1(n2190), .B0(intDY[34]), .B1(n2162), .Y(
n2155) );
OAI21XLTS U2832 ( .A0(n2892), .A1(n2188), .B0(n2155), .Y(n1139) );
AOI22X1TS U2833 ( .A0(DmP[28]), .A1(n2190), .B0(intDY[28]), .B1(n2189), .Y(
n2156) );
OAI21XLTS U2834 ( .A0(n2971), .A1(n2188), .B0(n2156), .Y(n1133) );
AOI22X1TS U2835 ( .A0(DmP[31]), .A1(n2190), .B0(intDY[31]), .B1(n2162), .Y(
n2157) );
OAI21XLTS U2836 ( .A0(n3074), .A1(n2188), .B0(n2157), .Y(n1136) );
AOI22X1TS U2837 ( .A0(DmP[27]), .A1(n2190), .B0(intDY[27]), .B1(n2189), .Y(
n2158) );
OAI21XLTS U2838 ( .A0(n2984), .A1(n2188), .B0(n2158), .Y(n1132) );
AOI22X1TS U2839 ( .A0(DmP[33]), .A1(n2190), .B0(intDY[33]), .B1(n2162), .Y(
n2159) );
OAI21XLTS U2840 ( .A0(n3000), .A1(n2188), .B0(n2159), .Y(n1138) );
AOI22X1TS U2841 ( .A0(n2239), .A1(intDY[62]), .B0(DMP[62]), .B1(n2223), .Y(
n2160) );
OAI21XLTS U2842 ( .A0(n2894), .A1(n2237), .B0(n2160), .Y(n1168) );
AOI22X1TS U2843 ( .A0(n2239), .A1(intDY[10]), .B0(DMP[10]), .B1(n2223), .Y(
n2161) );
OAI21XLTS U2844 ( .A0(n2978), .A1(n2041), .B0(n2161), .Y(n1179) );
AOI22X1TS U2845 ( .A0(DmP[41]), .A1(n2228), .B0(intDY[41]), .B1(n2189), .Y(
n2163) );
OAI21XLTS U2846 ( .A0(n1652), .A1(n2153), .B0(n2163), .Y(n1146) );
AOI22X1TS U2847 ( .A0(n2239), .A1(intDY[48]), .B0(DMP[48]), .B1(n2865), .Y(
n2165) );
OAI21XLTS U2848 ( .A0(n2988), .A1(n2241), .B0(n2165), .Y(n1217) );
AOI22X1TS U2849 ( .A0(n2239), .A1(intDY[37]), .B0(DMP[37]), .B1(n2865), .Y(
n2166) );
OAI21XLTS U2850 ( .A0(n2890), .A1(n2241), .B0(n2166), .Y(n1206) );
AOI22X1TS U2851 ( .A0(n2239), .A1(intDY[5]), .B0(DMP[5]), .B1(n2223), .Y(
n2167) );
OAI21XLTS U2852 ( .A0(n2884), .A1(n2237), .B0(n2167), .Y(n1174) );
AOI22X1TS U2853 ( .A0(n2239), .A1(intDY[4]), .B0(DMP[4]), .B1(n2228), .Y(
n2168) );
OAI21XLTS U2854 ( .A0(n2980), .A1(n2237), .B0(n2168), .Y(n1173) );
AOI22X1TS U2855 ( .A0(n2239), .A1(intDY[38]), .B0(DMP[38]), .B1(n2865), .Y(
n2169) );
OAI21XLTS U2856 ( .A0(n2992), .A1(n1577), .B0(n2169), .Y(n1207) );
AOI22X1TS U2857 ( .A0(n2239), .A1(intDY[44]), .B0(DMP[44]), .B1(n2865), .Y(
n2170) );
OAI21XLTS U2858 ( .A0(n2990), .A1(n1577), .B0(n2170), .Y(n1213) );
AOI22X1TS U2859 ( .A0(DmP[45]), .A1(n2223), .B0(intDY[45]), .B1(n2189), .Y(
n2171) );
OAI21XLTS U2860 ( .A0(n2997), .A1(n2035), .B0(n2171), .Y(n1150) );
AOI22X1TS U2861 ( .A0(DmP[46]), .A1(n2228), .B0(intDY[46]), .B1(n2162), .Y(
n2172) );
OAI21XLTS U2862 ( .A0(n2989), .A1(n2035), .B0(n2172), .Y(n1151) );
AOI22X1TS U2863 ( .A0(n2190), .A1(DmP[49]), .B0(intDY[49]), .B1(n2162), .Y(
n2173) );
OAI21XLTS U2864 ( .A0(n1654), .A1(n2177), .B0(n2173), .Y(n1154) );
AOI22X1TS U2865 ( .A0(DmP[43]), .A1(n2223), .B0(intDY[43]), .B1(n2189), .Y(
n2174) );
OAI21XLTS U2866 ( .A0(n2998), .A1(n2035), .B0(n2174), .Y(n1148) );
AOI22X1TS U2867 ( .A0(n2228), .A1(DmP[47]), .B0(intDY[47]), .B1(n2162), .Y(
n2175) );
OAI21XLTS U2868 ( .A0(n2888), .A1(n2035), .B0(n2175), .Y(n1152) );
AOI22X1TS U2869 ( .A0(DmP[39]), .A1(n2228), .B0(intDY[39]), .B1(n2162), .Y(
n2176) );
OAI21XLTS U2870 ( .A0(n2889), .A1(n2177), .B0(n2176), .Y(n1144) );
AOI22X1TS U2871 ( .A0(DmP[44]), .A1(n2190), .B0(intDY[44]), .B1(n2189), .Y(
n2178) );
OAI21XLTS U2872 ( .A0(n2990), .A1(n2035), .B0(n2178), .Y(n1149) );
AOI22X1TS U2873 ( .A0(DmP[25]), .A1(n2223), .B0(intDY[25]), .B1(n2162), .Y(
n2179) );
OAI21XLTS U2874 ( .A0(n3040), .A1(n2192), .B0(n2179), .Y(n1130) );
AOI22X1TS U2875 ( .A0(n2223), .A1(DmP[50]), .B0(intDY[50]), .B1(n2189), .Y(
n2180) );
OAI21XLTS U2876 ( .A0(n3045), .A1(n2192), .B0(n2180), .Y(n1155) );
AOI22X1TS U2877 ( .A0(n2228), .A1(DmP[51]), .B0(intDY[51]), .B1(n2189), .Y(
n2181) );
OAI21XLTS U2878 ( .A0(n2986), .A1(n2192), .B0(n2181), .Y(n1156) );
AOI22X1TS U2879 ( .A0(DmP[24]), .A1(n2190), .B0(intDY[24]), .B1(n2162), .Y(
n2182) );
AOI22X1TS U2880 ( .A0(DmP[29]), .A1(n2190), .B0(intDY[29]), .B1(n2189), .Y(
n2183) );
OAI21XLTS U2881 ( .A0(n2961), .A1(n2188), .B0(n2183), .Y(n1134) );
AOI22X1TS U2882 ( .A0(DmP[21]), .A1(n2190), .B0(intDY[21]), .B1(n2162), .Y(
n2184) );
OAI21XLTS U2883 ( .A0(n2981), .A1(n2192), .B0(n2184), .Y(n1126) );
AOI22X1TS U2884 ( .A0(DmP[23]), .A1(n2190), .B0(intDY[23]), .B1(n2189), .Y(
n2185) );
OAI21XLTS U2885 ( .A0(n3075), .A1(n2192), .B0(n2185), .Y(n1128) );
AOI22X1TS U2886 ( .A0(DmP[30]), .A1(n2190), .B0(intDY[30]), .B1(n2162), .Y(
n2186) );
OAI21XLTS U2887 ( .A0(n2970), .A1(n2188), .B0(n2186), .Y(n1135) );
AOI22X1TS U2888 ( .A0(DmP[26]), .A1(n2190), .B0(intDY[26]), .B1(n2189), .Y(
n2187) );
OAI21XLTS U2889 ( .A0(n3041), .A1(n2188), .B0(n2187), .Y(n1131) );
AOI22X1TS U2890 ( .A0(DmP[22]), .A1(n2190), .B0(intDY[22]), .B1(n2189), .Y(
n2191) );
OAI21XLTS U2891 ( .A0(n2973), .A1(n2192), .B0(n2191), .Y(n1127) );
AOI22X1TS U2892 ( .A0(n2218), .A1(intDY[52]), .B0(DMP[52]), .B1(n2238), .Y(
n2193) );
OAI21XLTS U2893 ( .A0(n2968), .A1(n2241), .B0(n2193), .Y(n1221) );
AOI22X1TS U2894 ( .A0(n2218), .A1(intDY[7]), .B0(DMP[7]), .B1(n2228), .Y(
n2194) );
OAI21XLTS U2895 ( .A0(n2955), .A1(n2237), .B0(n2194), .Y(n1176) );
AOI22X1TS U2896 ( .A0(n2218), .A1(intDY[61]), .B0(DMP[61]), .B1(n2226), .Y(
n2195) );
OAI21XLTS U2897 ( .A0(n2965), .A1(n1577), .B0(n2195), .Y(n1230) );
AOI22X1TS U2898 ( .A0(n2218), .A1(intDY[16]), .B0(DMP[16]), .B1(n2228), .Y(
n2196) );
AOI22X1TS U2899 ( .A0(n2218), .A1(intDY[6]), .B0(DMP[6]), .B1(n2223), .Y(
n2197) );
OAI21XLTS U2900 ( .A0(n2979), .A1(n2237), .B0(n2197), .Y(n1175) );
AOI22X1TS U2901 ( .A0(n2239), .A1(intDY[19]), .B0(DMP[19]), .B1(n2228), .Y(
n2198) );
OAI21XLTS U2902 ( .A0(n2985), .A1(n1577), .B0(n2198), .Y(n1188) );
AOI22X1TS U2903 ( .A0(n2239), .A1(intDY[9]), .B0(DMP[9]), .B1(n2226), .Y(
n2199) );
OAI21XLTS U2904 ( .A0(n2886), .A1(n2041), .B0(n2199), .Y(n1178) );
AOI22X1TS U2905 ( .A0(n2239), .A1(intDY[47]), .B0(DMP[47]), .B1(n2865), .Y(
n2200) );
OAI21XLTS U2906 ( .A0(n2888), .A1(n1577), .B0(n2200), .Y(n1216) );
AOI22X1TS U2907 ( .A0(n2239), .A1(intDY[42]), .B0(DMP[42]), .B1(n2865), .Y(
n2201) );
AOI22X1TS U2908 ( .A0(n2239), .A1(intDY[39]), .B0(DMP[39]), .B1(n2865), .Y(
n2202) );
OAI21XLTS U2909 ( .A0(n2889), .A1(n1577), .B0(n2202), .Y(n1208) );
AOI22X1TS U2910 ( .A0(n2239), .A1(intDY[40]), .B0(DMP[40]), .B1(n2865), .Y(
n2203) );
OAI21XLTS U2911 ( .A0(n2991), .A1(n1577), .B0(n2203), .Y(n1209) );
INVX2TS U2912 ( .A(n2585), .Y(n2603) );
AOI22X1TS U2913 ( .A0(n2796), .A1(n2603), .B0(n2204), .B1(n2605), .Y(n2210)
);
INVX2TS U2914 ( .A(n2591), .Y(n2602) );
INVX2TS U2915 ( .A(n2606), .Y(n2587) );
AOI222X4TS U2916 ( .A0(n2815), .A1(DmP[47]), .B0(n1668), .B1(n2693), .C0(
Add_Subt_result[49]), .C1(n2700), .Y(n2583) );
INVX2TS U2917 ( .A(n2629), .Y(n2207) );
OR2X2TS U2918 ( .A(n2666), .B(n2207), .Y(n2580) );
OAI22X1TS U2919 ( .A0(n2587), .A1(n2579), .B0(n2583), .B1(n2580), .Y(n2208)
);
AOI21X1TS U2920 ( .A0(n1705), .A1(n2602), .B0(n2208), .Y(n2209) );
OAI211XLTS U2921 ( .A0(n2211), .A1(n2651), .B0(n2210), .C0(n2209), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[44]) );
AOI22X1TS U2922 ( .A0(n2239), .A1(intDY[45]), .B0(DMP[45]), .B1(n2865), .Y(
n2212) );
OAI21XLTS U2923 ( .A0(n2997), .A1(n1577), .B0(n2212), .Y(n1214) );
AOI22X1TS U2924 ( .A0(n2239), .A1(intDY[36]), .B0(DMP[36]), .B1(n2228), .Y(
n2213) );
OAI21XLTS U2925 ( .A0(n3003), .A1(n2241), .B0(n2213), .Y(n1205) );
AOI22X1TS U2926 ( .A0(n2239), .A1(intDY[46]), .B0(DMP[46]), .B1(n2865), .Y(
n2214) );
OAI21XLTS U2927 ( .A0(n2989), .A1(n1577), .B0(n2214), .Y(n1215) );
AOI22X1TS U2928 ( .A0(n2239), .A1(intDY[43]), .B0(DMP[43]), .B1(n2865), .Y(
n2215) );
OAI21XLTS U2929 ( .A0(n2998), .A1(n1577), .B0(n2215), .Y(n1212) );
AOI22X1TS U2930 ( .A0(n2218), .A1(intDY[0]), .B0(DMP[0]), .B1(n2223), .Y(
n2216) );
OAI21XLTS U2931 ( .A0(n2964), .A1(n2237), .B0(n2216), .Y(n1169) );
AOI22X1TS U2932 ( .A0(n2239), .A1(intDY[3]), .B0(DMP[3]), .B1(n2238), .Y(
n2217) );
AOI22X1TS U2933 ( .A0(n2239), .A1(intDY[41]), .B0(DMP[41]), .B1(n2865), .Y(
n2219) );
OAI21XLTS U2934 ( .A0(n1652), .A1(n1577), .B0(n2219), .Y(n1210) );
AOI22X1TS U2935 ( .A0(n2218), .A1(intDY[2]), .B0(DMP[2]), .B1(n2228), .Y(
n2220) );
OAI21XLTS U2936 ( .A0(n2887), .A1(n2237), .B0(n2220), .Y(n1171) );
AOI22X1TS U2937 ( .A0(n2218), .A1(intDY[51]), .B0(DMP[51]), .B1(n2238), .Y(
n2221) );
OAI21XLTS U2938 ( .A0(n2986), .A1(n2241), .B0(n2221), .Y(n1220) );
AOI22X1TS U2939 ( .A0(n2218), .A1(intDY[14]), .B0(DMP[14]), .B1(n2223), .Y(
n2222) );
OAI21XLTS U2940 ( .A0(n2976), .A1(n2041), .B0(n2222), .Y(n1183) );
AOI22X1TS U2941 ( .A0(n2218), .A1(intDY[22]), .B0(DMP[22]), .B1(n2223), .Y(
n2224) );
OAI21XLTS U2942 ( .A0(n2973), .A1(n1577), .B0(n2224), .Y(n1191) );
AOI22X1TS U2943 ( .A0(n2218), .A1(intDY[59]), .B0(DMP[59]), .B1(n2226), .Y(
n2225) );
OAI21XLTS U2944 ( .A0(n2895), .A1(n1577), .B0(n2225), .Y(n1228) );
AOI22X1TS U2945 ( .A0(n2218), .A1(intDY[49]), .B0(DMP[49]), .B1(n2865), .Y(
n2227) );
OAI21XLTS U2946 ( .A0(n1654), .A1(n2241), .B0(n2227), .Y(n1218) );
AOI22X1TS U2947 ( .A0(n2218), .A1(intDY[8]), .B0(n1576), .B1(n2228), .Y(
n2229) );
OAI21XLTS U2948 ( .A0(n2963), .A1(n2041), .B0(n2229), .Y(n1177) );
AOI22X1TS U2949 ( .A0(n2218), .A1(intDY[57]), .B0(DMP[57]), .B1(n2238), .Y(
n2230) );
OAI21XLTS U2950 ( .A0(n2996), .A1(n2237), .B0(n2230), .Y(n1226) );
AOI22X1TS U2951 ( .A0(n2239), .A1(intDY[54]), .B0(DMP[54]), .B1(n2238), .Y(
n2231) );
OAI21XLTS U2952 ( .A0(n2967), .A1(n2241), .B0(n2231), .Y(n1223) );
AOI22X1TS U2953 ( .A0(n2218), .A1(intDY[56]), .B0(DMP[56]), .B1(n2238), .Y(
n2232) );
OAI21XLTS U2954 ( .A0(n2966), .A1(n2241), .B0(n2232), .Y(n1225) );
AOI22X1TS U2955 ( .A0(n2218), .A1(intDY[50]), .B0(DMP[50]), .B1(n2238), .Y(
n2233) );
OAI21XLTS U2956 ( .A0(n3045), .A1(n2241), .B0(n2233), .Y(n1219) );
AOI22X1TS U2957 ( .A0(n2218), .A1(intDY[58]), .B0(DMP[58]), .B1(n2226), .Y(
n2234) );
OAI21XLTS U2958 ( .A0(n3002), .A1(n1577), .B0(n2234), .Y(n1227) );
AOI22X1TS U2959 ( .A0(n2218), .A1(intDY[60]), .B0(DMP[60]), .B1(n2238), .Y(
n2235) );
OAI21XLTS U2960 ( .A0(n3001), .A1(n1577), .B0(n2235), .Y(n1229) );
AOI22X1TS U2961 ( .A0(n2218), .A1(intDY[55]), .B0(DMP[55]), .B1(n2226), .Y(
n2236) );
AOI22X1TS U2962 ( .A0(n2218), .A1(intDY[53]), .B0(DMP[53]), .B1(n2238), .Y(
n2240) );
OAI21XLTS U2963 ( .A0(n3073), .A1(n2241), .B0(n2240), .Y(n1222) );
BUFX4TS U2964 ( .A(n2671), .Y(n2798) );
AOI22X1TS U2965 ( .A0(n2780), .A1(n2606), .B0(n2798), .B1(n2605), .Y(n2244)
);
INVX2TS U2966 ( .A(n2583), .Y(n2607) );
AO22XLTS U2967 ( .A0(n2603), .A1(n1705), .B0(n1630), .B1(n2714), .Y(n2242)
);
AOI21X1TS U2968 ( .A0(n2796), .A1(n2607), .B0(n2242), .Y(n2243) );
OAI211XLTS U2969 ( .A0(n2245), .A1(n2651), .B0(n2244), .C0(n2243), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[43]) );
AOI22X1TS U2970 ( .A0(n2780), .A1(n1630), .B0(n2671), .B1(n2613), .Y(n2248)
);
AO22XLTS U2971 ( .A0(n2607), .A1(n1705), .B0(n2605), .B1(n2714), .Y(n2246)
);
AOI21X1TS U2972 ( .A0(n2796), .A1(n2606), .B0(n2246), .Y(n2247) );
OAI22X1TS U2973 ( .A0(n2596), .A1(n2588), .B0(n2583), .B1(n2579), .Y(n2250)
);
OAI22X1TS U2974 ( .A0(n2585), .A1(n2580), .B0(n2587), .B1(n2590), .Y(n2249)
);
AOI211XLTS U2975 ( .A0(n2753), .A1(n2602), .B0(n2250), .C0(n2249), .Y(n2251)
);
OAI21XLTS U2976 ( .A0(n2252), .A1(n2651), .B0(n2251), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[45]) );
OAI22X1TS U2977 ( .A0(n2597), .A1(n2579), .B0(n2583), .B1(n2586), .Y(n2254)
);
OAI22X1TS U2978 ( .A0(n2596), .A1(n2590), .B0(n2591), .B1(n2584), .Y(n2253)
);
AOI211X1TS U2979 ( .A0(n2256), .A1(n2255), .B0(n2254), .C0(n2253), .Y(n2258)
);
INVX2TS U2980 ( .A(n2580), .Y(n2788) );
NAND2X1TS U2981 ( .A(n1593), .B(n2788), .Y(n2257) );
OAI211XLTS U2982 ( .A0(n2585), .A1(n2582), .B0(n2258), .C0(n2257), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[49]) );
XOR2X1TS U2983 ( .A(DP_OP_42J154_122_8302_n1), .B(FSM_exp_operation_A_S),
.Y(n2263) );
OR4X2TS U2984 ( .A(Exp_Operation_Module_Data_S[2]), .B(
Exp_Operation_Module_Data_S[1]), .C(Exp_Operation_Module_Data_S[0]),
.D(n1590), .Y(n2259) );
OR4X2TS U2985 ( .A(Exp_Operation_Module_Data_S[5]), .B(
Exp_Operation_Module_Data_S[4]), .C(Exp_Operation_Module_Data_S[3]),
.D(n2259), .Y(n2260) );
OR4X2TS U2986 ( .A(Exp_Operation_Module_Data_S[8]), .B(
Exp_Operation_Module_Data_S[7]), .C(Exp_Operation_Module_Data_S[6]),
.D(n2260), .Y(n2261) );
OR4X2TS U2987 ( .A(n2263), .B(Exp_Operation_Module_Data_S[10]), .C(
Exp_Operation_Module_Data_S[9]), .D(n2261), .Y(n2262) );
OAI21XLTS U2988 ( .A0(n1638), .A1(n2843), .B0(n2262), .Y(n1426) );
INVX2TS U2989 ( .A(n2263), .Y(n2271) );
INVX2TS U2990 ( .A(Exp_Operation_Module_Data_S[10]), .Y(n2270) );
NAND3BXLTS U2991 ( .AN(n2881), .B(n2940), .C(FS_Module_state_reg[0]), .Y(
n2264) );
NAND2X1TS U2992 ( .A(n2265), .B(n2264), .Y(n2813) );
CLKAND2X2TS U2993 ( .A(Exp_Operation_Module_Data_S[0]), .B(n2813), .Y(n2571)
);
NAND4XLTS U2994 ( .A(Exp_Operation_Module_Data_S[3]), .B(
Exp_Operation_Module_Data_S[2]), .C(Exp_Operation_Module_Data_S[1]),
.D(n2571), .Y(n2266) );
NAND4BXLTS U2995 ( .AN(n2266), .B(Exp_Operation_Module_Data_S[6]), .C(
Exp_Operation_Module_Data_S[5]), .D(Exp_Operation_Module_Data_S[4]),
.Y(n2267) );
NAND4BXLTS U2996 ( .AN(n2267), .B(Exp_Operation_Module_Data_S[9]), .C(
Exp_Operation_Module_Data_S[8]), .D(Exp_Operation_Module_Data_S[7]),
.Y(n2269) );
NAND2X1TS U2997 ( .A(n2573), .B(overflow_flag), .Y(n2268) );
OAI31X1TS U2998 ( .A0(n2271), .A1(n2270), .A2(n2269), .B0(n2268), .Y(n1427)
);
AOI22X1TS U2999 ( .A0(n2893), .A1(intDY[1]), .B0(n2965), .B1(intDY[61]), .Y(
n2272) );
OAI221XLTS U3000 ( .A0(n2893), .A1(intDY[1]), .B0(n2965), .B1(intDY[61]),
.C0(n2272), .Y(n2273) );
AOI221X1TS U3001 ( .A0(intDX[62]), .A1(n2993), .B0(n2894), .B1(intDY[62]),
.C0(n2273), .Y(n2287) );
OAI22X1TS U3002 ( .A0(n3002), .A1(intDY[58]), .B0(n2996), .B1(intDY[57]),
.Y(n2274) );
OAI22X1TS U3003 ( .A0(n3001), .A1(intDY[60]), .B0(n2895), .B1(intDY[59]),
.Y(n2275) );
AOI22X1TS U3004 ( .A0(n3073), .A1(intDY[53]), .B0(n2967), .B1(intDY[54]),
.Y(n2276) );
AOI22X1TS U3005 ( .A0(n3072), .A1(intDY[55]), .B0(n2966), .B1(intDY[56]),
.Y(n2277) );
AOI22X1TS U3006 ( .A0(n1654), .A1(intDY[49]), .B0(n3045), .B1(intDY[50]),
.Y(n2278) );
AOI22X1TS U3007 ( .A0(n2986), .A1(intDY[51]), .B0(n2968), .B1(intDY[52]),
.Y(n2279) );
NOR4X1TS U3008 ( .A(n2283), .B(n2282), .C(n2281), .D(n2280), .Y(n2284) );
NAND4XLTS U3009 ( .A(n2287), .B(n2286), .C(n2285), .D(n2284), .Y(n2343) );
OAI22X1TS U3010 ( .A0(n2992), .A1(intDY[38]), .B0(n2890), .B1(intDY[37]),
.Y(n2288) );
AOI221X1TS U3011 ( .A0(n2992), .A1(intDY[38]), .B0(intDY[37]), .B1(n2890),
.C0(n2288), .Y(n2295) );
OAI22X1TS U3012 ( .A0(n2991), .A1(intDY[40]), .B0(n2889), .B1(intDY[39]),
.Y(n2289) );
OAI22X1TS U3013 ( .A0(n2892), .A1(intDY[34]), .B0(n3000), .B1(intDY[33]),
.Y(n2290) );
OAI22X1TS U3014 ( .A0(n3003), .A1(intDY[36]), .B0(n2999), .B1(intDY[35]),
.Y(n2291) );
NAND4XLTS U3015 ( .A(n2295), .B(n2294), .C(n2293), .D(n2292), .Y(n2342) );
OAI22X1TS U3016 ( .A0(n2989), .A1(intDY[46]), .B0(n2997), .B1(intDY[45]),
.Y(n2296) );
OAI22X1TS U3017 ( .A0(n2988), .A1(intDY[48]), .B0(n2888), .B1(intDY[47]),
.Y(n2297) );
AOI221X1TS U3018 ( .A0(n2988), .A1(intDY[48]), .B0(intDY[47]), .B1(n2888),
.C0(n2297), .Y(n2302) );
OAI22X1TS U3019 ( .A0(n2891), .A1(intDY[42]), .B0(n1652), .B1(intDY[41]),
.Y(n2298) );
OAI22X1TS U3020 ( .A0(n2990), .A1(intDY[44]), .B0(n2998), .B1(intDY[43]),
.Y(n2299) );
AOI221X1TS U3021 ( .A0(n2990), .A1(intDY[44]), .B0(intDY[43]), .B1(n2998),
.C0(n2299), .Y(n2300) );
NAND4XLTS U3022 ( .A(n2303), .B(n2302), .C(n2301), .D(n2300), .Y(n2341) );
AOI22X1TS U3023 ( .A0(n2981), .A1(intDY[21]), .B0(n2973), .B1(intDY[22]),
.Y(n2304) );
AOI22X1TS U3024 ( .A0(n3075), .A1(intDY[23]), .B0(n2972), .B1(intDY[24]),
.Y(n2305) );
AOI22X1TS U3025 ( .A0(n3043), .A1(intDY[17]), .B0(n3076), .B1(intDY[18]),
.Y(n2306) );
AOI22X1TS U3026 ( .A0(n2985), .A1(intDY[19]), .B0(n2974), .B1(intDY[20]),
.Y(n2307) );
NOR4X1TS U3027 ( .A(n2311), .B(n2310), .C(n2309), .D(n2308), .Y(n2339) );
AOI22X1TS U3028 ( .A0(n2961), .A1(intDY[29]), .B0(n2970), .B1(intDY[30]),
.Y(n2312) );
AOI22X1TS U3029 ( .A0(n3074), .A1(intDY[31]), .B0(n2969), .B1(intDY[32]),
.Y(n2313) );
AOI22X1TS U3030 ( .A0(n3040), .A1(intDY[25]), .B0(n3041), .B1(intDY[26]),
.Y(n2314) );
AOI22X1TS U3031 ( .A0(n2984), .A1(intDY[27]), .B0(n2971), .B1(intDY[28]),
.Y(n2315) );
NOR4X1TS U3032 ( .A(n2319), .B(n2318), .C(n2317), .D(n2316), .Y(n2338) );
AOI22X1TS U3033 ( .A0(n2884), .A1(intDY[5]), .B0(n2979), .B1(intDY[6]), .Y(
n2320) );
AOI22X1TS U3034 ( .A0(n2955), .A1(intDY[7]), .B0(n2963), .B1(intDY[8]), .Y(
n2321) );
AOI22X1TS U3035 ( .A0(n2887), .A1(intDY[2]), .B0(n2964), .B1(intDY[0]), .Y(
n2322) );
AOI22X1TS U3036 ( .A0(n2960), .A1(intDY[3]), .B0(n2980), .B1(intDY[4]), .Y(
n2323) );
NOR4X1TS U3037 ( .A(n2327), .B(n2326), .C(n2325), .D(n2324), .Y(n2337) );
AOI22X1TS U3038 ( .A0(n2962), .A1(intDY[13]), .B0(n2976), .B1(intDY[14]),
.Y(n2328) );
AOI22X1TS U3039 ( .A0(n3077), .A1(intDY[15]), .B0(n2975), .B1(intDY[16]),
.Y(n2329) );
AOI22X1TS U3040 ( .A0(n2886), .A1(intDY[9]), .B0(n2978), .B1(intDY[10]), .Y(
n2330) );
AOI22X1TS U3041 ( .A0(n3042), .A1(intDY[11]), .B0(n2977), .B1(intDY[12]),
.Y(n2331) );
NOR4X1TS U3042 ( .A(n2335), .B(n2334), .C(n2333), .D(n2332), .Y(n2336) );
NAND4XLTS U3043 ( .A(n2339), .B(n2338), .C(n2337), .D(n2336), .Y(n2340) );
XOR2X1TS U3044 ( .A(intDY[63]), .B(intAS), .Y(n2863) );
XOR2X1TS U3045 ( .A(n2863), .B(intDX[63]), .Y(n2391) );
NAND2X1TS U3046 ( .A(n2861), .B(n2391), .Y(n2808) );
OR4X2TS U3047 ( .A(Add_Subt_result[53]), .B(Add_Subt_result[54]), .C(
Add_Subt_result[51]), .D(Add_Subt_result[52]), .Y(n2381) );
NAND2X1TS U3048 ( .A(n2823), .B(n2901), .Y(n2364) );
NOR4X2TS U3049 ( .A(Add_Subt_result[45]), .B(Add_Subt_result[46]), .C(
Add_Subt_result[44]), .D(n2364), .Y(n2357) );
NAND2X1TS U3050 ( .A(n2357), .B(n2907), .Y(n2346) );
NAND2X1TS U3051 ( .A(n1669), .B(n2702), .Y(n2442) );
NAND2X1TS U3052 ( .A(n2347), .B(n2912), .Y(n2425) );
NOR3X1TS U3053 ( .A(Add_Subt_result[37]), .B(Add_Subt_result[38]), .C(n2425),
.Y(n2417) );
NAND2X1TS U3054 ( .A(n2417), .B(n2916), .Y(n2828) );
NOR2X2TS U3055 ( .A(Add_Subt_result[35]), .B(n2828), .Y(n2429) );
NAND3X1TS U3056 ( .A(n2429), .B(n2921), .C(n1633), .Y(n2415) );
NOR3X1TS U3057 ( .A(Add_Subt_result[32]), .B(Add_Subt_result[31]), .C(n2415),
.Y(n2362) );
NAND2X1TS U3058 ( .A(n2362), .B(n2924), .Y(n2432) );
NOR2X2TS U3059 ( .A(Add_Subt_result[26]), .B(n2363), .Y(n2354) );
NAND2X1TS U3060 ( .A(n2354), .B(n2930), .Y(n2419) );
NOR2X1TS U3061 ( .A(Add_Subt_result[24]), .B(n2419), .Y(n2361) );
NAND2X1TS U3062 ( .A(n2361), .B(n2882), .Y(n2348) );
INVX2TS U3063 ( .A(n2348), .Y(n2384) );
NAND2X1TS U3064 ( .A(n2384), .B(Add_Subt_result[21]), .Y(n2430) );
OAI32X1TS U3065 ( .A0(n2825), .A1(Add_Subt_result[40]), .A2(n2912), .B0(
n2702), .B1(n2825), .Y(n2349) );
AOI31XLTS U3066 ( .A0(Add_Subt_result[19]), .A1(n2424), .A2(n3012), .B0(
n2349), .Y(n2352) );
NOR2X1TS U3067 ( .A(Add_Subt_result[12]), .B(Add_Subt_result[11]), .Y(n2393)
);
NOR2X1TS U3068 ( .A(Add_Subt_result[20]), .B(Add_Subt_result[19]), .Y(n2414)
);
NAND2X1TS U3069 ( .A(n2414), .B(n2424), .Y(n2403) );
NOR2X1TS U3070 ( .A(Add_Subt_result[18]), .B(n2403), .Y(n2392) );
NOR2BX1TS U3071 ( .AN(n2392), .B(Add_Subt_result[17]), .Y(n2449) );
NAND2X1TS U3072 ( .A(n2449), .B(n2875), .Y(n2394) );
NOR2X1TS U3073 ( .A(Add_Subt_result[15]), .B(n2394), .Y(n2383) );
NAND2X1TS U3074 ( .A(n2383), .B(n1629), .Y(n2376) );
NAND2X1TS U3075 ( .A(n2393), .B(n2401), .Y(n2360) );
NOR2X1TS U3076 ( .A(Add_Subt_result[10]), .B(n2360), .Y(n2353) );
NAND2X1TS U3077 ( .A(n2353), .B(n3004), .Y(n2397) );
NOR3X2TS U3078 ( .A(Add_Subt_result[8]), .B(Add_Subt_result[7]), .C(n2397),
.Y(n2404) );
OAI211XLTS U3079 ( .A0(n1668), .A1(n2350), .B0(n2404), .C0(n3016), .Y(n2351)
);
OAI211X1TS U3080 ( .A0(Add_Subt_result[22]), .A1(n2430), .B0(n2352), .C0(
n2351), .Y(n2375) );
AOI21X1TS U3081 ( .A0(Add_Subt_result[7]), .A1(n2897), .B0(
Add_Subt_result[9]), .Y(n2356) );
INVX2TS U3082 ( .A(n2353), .Y(n2409) );
AOI32X1TS U3083 ( .A0(Add_Subt_result[23]), .A1(n2354), .A2(n3008), .B0(
Add_Subt_result[25]), .B1(n2354), .Y(n2355) );
NAND2X1TS U3084 ( .A(Add_Subt_result[43]), .B(n2357), .Y(n2444) );
OAI211X1TS U3085 ( .A0(n2356), .A1(n2409), .B0(n2355), .C0(n2444), .Y(n2831)
);
NOR2X1TS U3086 ( .A(Add_Subt_result[6]), .B(n1668), .Y(n2405) );
NAND2X1TS U3087 ( .A(n2404), .B(n2405), .Y(n2395) );
AOI22X1TS U3088 ( .A0(Add_Subt_result[20]), .A1(n2424), .B0(n2404), .B1(
Add_Subt_result[6]), .Y(n2359) );
OAI211X1TS U3089 ( .A0(n3019), .A1(n2395), .B0(n2359), .C0(n2358), .Y(n2380)
);
NOR2XLTS U3090 ( .A(n3008), .B(n2419), .Y(n2368) );
AOI21X1TS U3091 ( .A0(n3017), .A1(n2897), .B0(n2360), .Y(n2367) );
NOR3X1TS U3092 ( .A(Add_Subt_result[46]), .B(Add_Subt_result[45]), .C(
Add_Subt_result[44]), .Y(n2365) );
OAI22X1TS U3093 ( .A0(n2365), .A1(n2364), .B0(n3010), .B1(n2363), .Y(n2366)
);
NOR4X1TS U3094 ( .A(n2368), .B(n2367), .C(n2428), .D(n2366), .Y(n2370) );
INVX2TS U3095 ( .A(n2833), .Y(n2450) );
NOR2XLTS U3096 ( .A(n1649), .B(n2450), .Y(n2369) );
AOI21X1TS U3097 ( .A0(n1667), .A1(n2926), .B0(Add_Subt_result[29]), .Y(n2379) );
NAND2X1TS U3098 ( .A(Add_Subt_result[31]), .B(n1632), .Y(n2373) );
INVX2TS U3099 ( .A(n2429), .Y(n2372) );
AOI211X1TS U3100 ( .A0(n1633), .A1(n2373), .B0(Add_Subt_result[34]), .C0(
n2372), .Y(n2374) );
AOI211X1TS U3101 ( .A0(Add_Subt_result[47]), .A1(n2823), .B0(n2375), .C0(
n2374), .Y(n2378) );
INVX2TS U3102 ( .A(n2376), .Y(n2406) );
OAI211X1TS U3103 ( .A0(n2379), .A1(n2432), .B0(n2378), .C0(n2377), .Y(n2830)
);
OAI22X1TS U3104 ( .A0(n2382), .A1(n2381), .B0(n1632), .B1(n2415), .Y(n2387)
);
AOI22X1TS U3105 ( .A0(n2384), .A1(Add_Subt_result[22]), .B0(
Add_Subt_result[14]), .B1(n2383), .Y(n2385) );
OAI21XLTS U3106 ( .A0(n2432), .A1(n2926), .B0(n2385), .Y(n2386) );
AOI211XLTS U3107 ( .A0(n2429), .A1(Add_Subt_result[34]), .B0(n2387), .C0(
n2386), .Y(n2389) );
NOR2XLTS U3108 ( .A(LZA_output[2]), .B(n2450), .Y(n2388) );
AND2X4TS U3109 ( .A(n2391), .B(n2902), .Y(n2512) );
BUFX4TS U3110 ( .A(n2512), .Y(n3039) );
NOR3X1TS U3111 ( .A(Add_Subt_result[4]), .B(Add_Subt_result[3]), .C(n2395),
.Y(n2436) );
NAND2X1TS U3112 ( .A(n2436), .B(n3033), .Y(n2402) );
NOR2X1TS U3113 ( .A(n3035), .B(n2402), .Y(n2435) );
AOI21X1TS U3114 ( .A0(n2392), .A1(Add_Subt_result[17]), .B0(n2435), .Y(n2836) );
INVX2TS U3115 ( .A(n2393), .Y(n2400) );
NOR2X1TS U3116 ( .A(n2394), .B(n3022), .Y(n2832) );
NOR2XLTS U3117 ( .A(Add_Subt_result[8]), .B(Add_Subt_result[7]), .Y(n2398)
);
NOR2XLTS U3118 ( .A(Add_Subt_result[4]), .B(Add_Subt_result[3]), .Y(n2396)
);
OAI22X1TS U3119 ( .A0(n2398), .A1(n2397), .B0(n2396), .B1(n2395), .Y(n2399)
);
AOI211X1TS U3120 ( .A0(n2401), .A1(n2400), .B0(n2832), .C0(n2399), .Y(n2447)
);
NOR3X1TS U3121 ( .A(Add_Subt_result[1]), .B(n2402), .C(n3036), .Y(n2422) );
AOI31XLTS U3122 ( .A0(n2875), .A1(n3021), .A2(n1629), .B0(n2403), .Y(n2411)
);
OAI2BB1X1TS U3123 ( .A0N(n2405), .A1N(n3033), .B0(n2404), .Y(n2408) );
OAI21XLTS U3124 ( .A0(Add_Subt_result[10]), .A1(Add_Subt_result[13]), .B0(
n2406), .Y(n2407) );
NOR4BX1TS U3125 ( .AN(n2447), .B(n2422), .C(n2411), .D(n2410), .Y(n2413) );
NOR2XLTS U3126 ( .A(n1637), .B(n2450), .Y(n2412) );
INVX2TS U3127 ( .A(n2414), .Y(n2423) );
NOR2XLTS U3128 ( .A(Add_Subt_result[32]), .B(Add_Subt_result[31]), .Y(n2416)
);
OAI2BB2XLTS U3129 ( .B0(n2416), .B1(n2415), .A0N(n1667), .A1N(n2443), .Y(
n2418) );
OAI31X1TS U3130 ( .A0(Add_Subt_result[36]), .A1(n2418), .A2(
Add_Subt_result[35]), .B0(n2417), .Y(n2420) );
AOI32X1TS U3131 ( .A0(n2882), .A1(n2420), .A2(n3008), .B0(n2419), .B1(n2420),
.Y(n2421) );
AOI211X1TS U3132 ( .A0(n2424), .A1(n2423), .B0(n2422), .C0(n2421), .Y(n2453)
);
NOR4X1TS U3133 ( .A(Add_Subt_result[26]), .B(Add_Subt_result[29]), .C(
Add_Subt_result[28]), .D(Add_Subt_result[25]), .Y(n2433) );
NOR2XLTS U3134 ( .A(Add_Subt_result[37]), .B(Add_Subt_result[38]), .Y(n2426)
);
OAI22X1TS U3135 ( .A0(n2426), .A1(n2425), .B0(n2828), .B1(n2921), .Y(n2427)
);
AOI211X1TS U3136 ( .A0(n2429), .A1(Add_Subt_result[33]), .B0(n2428), .C0(
n2427), .Y(n2431) );
NOR2XLTS U3137 ( .A(LZA_output[4]), .B(n2450), .Y(n2437) );
AOI31XLTS U3138 ( .A0(Add_Subt_result[44]), .A1(n3009), .A2(n2896), .B0(
Add_Subt_result[48]), .Y(n2439) );
NOR2XLTS U3139 ( .A(Add_Subt_result[53]), .B(Add_Subt_result[54]), .Y(n2440)
);
NOR2X1TS U3140 ( .A(Add_Subt_result[39]), .B(Add_Subt_result[40]), .Y(n2824)
);
AOI2BB2XLTS U3141 ( .B0(n2443), .B1(Add_Subt_result[28]), .A0N(n2824), .A1N(
n2442), .Y(n2445) );
AOI21X1TS U3142 ( .A0(Add_Subt_result[16]), .A1(n2449), .B0(n2448), .Y(n2452) );
NOR2XLTS U3143 ( .A(n1648), .B(n2450), .Y(n2451) );
AOI22X1TS U3144 ( .A0(n2560), .A1(n1662), .B0(n2454), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n2455) );
OAI21XLTS U3145 ( .A0(n2562), .A1(n3029), .B0(n2455), .Y(n2456) );
AOI22X1TS U3146 ( .A0(n2560), .A1(n1664), .B0(n2476), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n2458) );
OAI21XLTS U3147 ( .A0(n2562), .A1(n3030), .B0(n2458), .Y(n2459) );
OAI222X1TS U3148 ( .A0(n2872), .A1(n2485), .B0(n2483), .B1(n2466), .C0(n2467), .C1(n2468), .Y(n1468) );
AOI22X1TS U3149 ( .A0(n2560), .A1(n1661), .B0(n2476), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n2460) );
OAI21XLTS U3150 ( .A0(n2562), .A1(n3027), .B0(n2460), .Y(n2461) );
AOI22X1TS U3151 ( .A0(n2560), .A1(n1665), .B0(n2476), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n2462) );
OAI222X1TS U3152 ( .A0(n2925), .A1(n2485), .B0(n2483), .B1(n2464), .C0(n2467), .C1(n2465), .Y(n1467) );
OAI222X1TS U3153 ( .A0(n2931), .A1(n2485), .B0(n2483), .B1(n2465), .C0(n2467), .C1(n2464), .Y(n1471) );
OAI222X1TS U3154 ( .A0(n2928), .A1(n2485), .B0(n2483), .B1(n2468), .C0(n2467), .C1(n2466), .Y(n1470) );
AOI22X1TS U3155 ( .A0(n2560), .A1(n1666), .B0(n2476), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n2469) );
OAI21XLTS U3156 ( .A0(n3026), .A1(n2562), .B0(n2469), .Y(n2470) );
AOI22X1TS U3157 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[79]), .A1(
n2476), .B0(n2560), .B1(n1659), .Y(n2471) );
OAI21XLTS U3158 ( .A0(n3025), .A1(n2562), .B0(n2471), .Y(n2472) );
OAI222X1TS U3159 ( .A0(n2932), .A1(n2485), .B0(n2483), .B1(n2473), .C0(n2467), .C1(n2474), .Y(n1472) );
OAI222X1TS U3160 ( .A0(n2871), .A1(n2485), .B0(n2483), .B1(n2474), .C0(n2467), .C1(n2473), .Y(n1466) );
AOI22X1TS U3161 ( .A0(n2560), .A1(n1660), .B0(n2457), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(n2475) );
OAI2BB1X1TS U3162 ( .A0N(n2476), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(n2475), .Y(n2477)
);
NOR3X1TS U3163 ( .A(n1781), .B(n2478), .C(n2477), .Y(n2484) );
AOI22X1TS U3164 ( .A0(n2560), .A1(n1647), .B0(n2457), .B1(n1660), .Y(n2479)
);
OAI21XLTS U3165 ( .A0(n2562), .A1(n3032), .B0(n2479), .Y(n2481) );
OAI222X1TS U3166 ( .A0(n2485), .A1(n2874), .B0(n2483), .B1(n2484), .C0(n2467), .C1(n2482), .Y(n1473) );
OAI222X1TS U3167 ( .A0(n2870), .A1(n2485), .B0(n2467), .B1(n2484), .C0(n2483), .C1(n2482), .Y(n1465) );
INVX6TS U3168 ( .A(n2902), .Y(n2566) );
NOR2BX1TS U3169 ( .AN(Sgf_normalized_result[54]), .B(n2572), .Y(n2486) );
XOR2X1TS U3170 ( .A(n3039), .B(n2486), .Y(DP_OP_45J154_125_8406_n60) );
CLKINVX6TS U3171 ( .A(n2902), .Y(n2533) );
NOR2XLTS U3172 ( .A(n3034), .B(n2572), .Y(n2487) );
XOR2X1TS U3173 ( .A(n3039), .B(n2487), .Y(DP_OP_45J154_125_8406_n61) );
NOR2XLTS U3174 ( .A(n3024), .B(n2572), .Y(n2488) );
XOR2X1TS U3175 ( .A(n3039), .B(n2488), .Y(DP_OP_45J154_125_8406_n62) );
NOR2XLTS U3176 ( .A(n3023), .B(n2572), .Y(n2489) );
XOR2X1TS U3177 ( .A(n3039), .B(n2489), .Y(DP_OP_45J154_125_8406_n63) );
XOR2X1TS U3178 ( .A(n3039), .B(n2490), .Y(DP_OP_45J154_125_8406_n64) );
NOR2XLTS U3179 ( .A(n3006), .B(n2572), .Y(n2491) );
XOR2X1TS U3180 ( .A(n3039), .B(n2491), .Y(DP_OP_45J154_125_8406_n65) );
NOR2XLTS U3181 ( .A(n3005), .B(n2570), .Y(n2492) );
XOR2X1TS U3182 ( .A(n3039), .B(n2492), .Y(DP_OP_45J154_125_8406_n66) );
XOR2X1TS U3183 ( .A(n3039), .B(n2493), .Y(DP_OP_45J154_125_8406_n67) );
NOR2XLTS U3184 ( .A(n2994), .B(n2570), .Y(n2494) );
XOR2X1TS U3185 ( .A(n3039), .B(n2494), .Y(DP_OP_45J154_125_8406_n68) );
NOR2XLTS U3186 ( .A(n2983), .B(n2570), .Y(n2495) );
XOR2X1TS U3187 ( .A(n3039), .B(n2495), .Y(DP_OP_45J154_125_8406_n69) );
NOR2XLTS U3188 ( .A(n2982), .B(n2570), .Y(n2496) );
XOR2X1TS U3189 ( .A(n3039), .B(n2496), .Y(DP_OP_45J154_125_8406_n70) );
NOR2XLTS U3190 ( .A(n2959), .B(n2570), .Y(n2497) );
XOR2X1TS U3191 ( .A(n3039), .B(n2497), .Y(DP_OP_45J154_125_8406_n71) );
NOR2XLTS U3192 ( .A(n2958), .B(n2570), .Y(n2498) );
XOR2X1TS U3193 ( .A(n2567), .B(n2498), .Y(DP_OP_45J154_125_8406_n72) );
NOR2XLTS U3194 ( .A(n2954), .B(n2570), .Y(n2499) );
XOR2X1TS U3195 ( .A(n2567), .B(n2499), .Y(DP_OP_45J154_125_8406_n73) );
NOR2XLTS U3196 ( .A(n2947), .B(n2570), .Y(n2500) );
XOR2X1TS U3197 ( .A(n2567), .B(n2500), .Y(DP_OP_45J154_125_8406_n74) );
INVX4TS U3198 ( .A(n2902), .Y(n2537) );
NOR2XLTS U3199 ( .A(n2946), .B(n2566), .Y(n2501) );
XOR2X1TS U3200 ( .A(n2567), .B(n2501), .Y(DP_OP_45J154_125_8406_n75) );
NOR2XLTS U3201 ( .A(n2943), .B(n2566), .Y(n2502) );
XOR2X1TS U3202 ( .A(n2567), .B(n2502), .Y(DP_OP_45J154_125_8406_n76) );
NOR2XLTS U3203 ( .A(n2942), .B(n2566), .Y(n2503) );
XOR2X1TS U3204 ( .A(n3039), .B(n2503), .Y(DP_OP_45J154_125_8406_n77) );
NOR2XLTS U3205 ( .A(n2938), .B(n2566), .Y(n2504) );
XOR2X1TS U3206 ( .A(n3039), .B(n2504), .Y(DP_OP_45J154_125_8406_n78) );
NOR2XLTS U3207 ( .A(n2937), .B(n2566), .Y(n2505) );
XOR2X1TS U3208 ( .A(n2512), .B(n2505), .Y(DP_OP_45J154_125_8406_n79) );
NOR2XLTS U3209 ( .A(n2936), .B(n2566), .Y(n2506) );
XOR2X1TS U3210 ( .A(n2512), .B(n2506), .Y(DP_OP_45J154_125_8406_n80) );
NOR2XLTS U3211 ( .A(n2935), .B(n2566), .Y(n2507) );
XOR2X1TS U3212 ( .A(n3039), .B(n2507), .Y(DP_OP_45J154_125_8406_n81) );
NOR2XLTS U3213 ( .A(n2934), .B(n2566), .Y(n2508) );
XOR2X1TS U3214 ( .A(n3039), .B(n2508), .Y(DP_OP_45J154_125_8406_n82) );
NOR2XLTS U3215 ( .A(n2869), .B(n2874), .Y(n2510) );
XOR2X1TS U3216 ( .A(n2512), .B(n2510), .Y(DP_OP_45J154_125_8406_n83) );
NOR2XLTS U3217 ( .A(n2869), .B(n2932), .Y(n2511) );
XOR2X1TS U3218 ( .A(n2512), .B(n2511), .Y(DP_OP_45J154_125_8406_n84) );
XOR2X1TS U3219 ( .A(n2512), .B(n2513), .Y(DP_OP_45J154_125_8406_n85) );
NOR2XLTS U3220 ( .A(n2869), .B(n2928), .Y(n2514) );
XOR2X1TS U3221 ( .A(n2512), .B(n2514), .Y(DP_OP_45J154_125_8406_n86) );
NOR2XLTS U3222 ( .A(n2927), .B(n2566), .Y(n2515) );
XOR2X1TS U3223 ( .A(n2512), .B(n2515), .Y(DP_OP_45J154_125_8406_n87) );
NOR2XLTS U3224 ( .A(n2869), .B(n2872), .Y(n2516) );
XOR2X1TS U3225 ( .A(n2512), .B(n2516), .Y(DP_OP_45J154_125_8406_n88) );
NOR2XLTS U3226 ( .A(n2869), .B(n2925), .Y(n2517) );
XOR2X1TS U3227 ( .A(n2512), .B(n2517), .Y(DP_OP_45J154_125_8406_n89) );
XOR2X1TS U3228 ( .A(n2512), .B(n2518), .Y(DP_OP_45J154_125_8406_n90) );
XOR2X1TS U3229 ( .A(n2512), .B(n2519), .Y(DP_OP_45J154_125_8406_n91) );
XOR2X1TS U3230 ( .A(n2512), .B(n2520), .Y(DP_OP_45J154_125_8406_n92) );
XOR2X1TS U3231 ( .A(n2512), .B(n2521), .Y(DP_OP_45J154_125_8406_n93) );
XOR2X1TS U3232 ( .A(n2512), .B(n2522), .Y(DP_OP_45J154_125_8406_n94) );
XOR2X1TS U3233 ( .A(n2512), .B(n2523), .Y(DP_OP_45J154_125_8406_n95) );
XOR2X1TS U3234 ( .A(n2512), .B(n2524), .Y(DP_OP_45J154_125_8406_n96) );
XOR2X1TS U3235 ( .A(n2567), .B(n2525), .Y(DP_OP_45J154_125_8406_n97) );
XOR2X1TS U3236 ( .A(n2567), .B(n2526), .Y(DP_OP_45J154_125_8406_n98) );
XOR2X1TS U3237 ( .A(n2567), .B(n2527), .Y(DP_OP_45J154_125_8406_n99) );
XOR2X1TS U3238 ( .A(n2567), .B(n2528), .Y(DP_OP_45J154_125_8406_n100) );
XOR2X1TS U3239 ( .A(n2567), .B(n2529), .Y(DP_OP_45J154_125_8406_n101) );
XOR2X1TS U3240 ( .A(n2567), .B(n2530), .Y(DP_OP_45J154_125_8406_n102) );
XOR2X1TS U3241 ( .A(n2567), .B(n2531), .Y(DP_OP_45J154_125_8406_n103) );
XOR2X1TS U3242 ( .A(n2567), .B(n2532), .Y(DP_OP_45J154_125_8406_n104) );
XOR2X1TS U3243 ( .A(n2567), .B(n2534), .Y(DP_OP_45J154_125_8406_n105) );
XOR2X1TS U3244 ( .A(n2567), .B(n2535), .Y(DP_OP_45J154_125_8406_n106) );
XOR2X1TS U3245 ( .A(n2567), .B(n2536), .Y(DP_OP_45J154_125_8406_n107) );
XOR2X1TS U3246 ( .A(n2567), .B(n2538), .Y(DP_OP_45J154_125_8406_n108) );
XOR2X1TS U3247 ( .A(n2567), .B(n2539), .Y(DP_OP_45J154_125_8406_n109) );
XOR2X1TS U3248 ( .A(n2567), .B(n2540), .Y(DP_OP_45J154_125_8406_n110) );
XOR2X1TS U3249 ( .A(n2567), .B(n2541), .Y(DP_OP_45J154_125_8406_n111) );
NAND2X1TS U3250 ( .A(n2877), .B(n2902), .Y(n2542) );
XOR2X1TS U3251 ( .A(n2567), .B(n2542), .Y(DP_OP_45J154_125_8406_n112) );
XOR2X1TS U3252 ( .A(n2567), .B(n2543), .Y(DP_OP_45J154_125_8406_n113) );
XOR2X1TS U3253 ( .A(n3039), .B(n2545), .Y(DP_OP_45J154_125_8406_n114) );
CLKAND2X2TS U3254 ( .A(n2555), .B(DmP[62]), .Y(n2546) );
XOR2X1TS U3255 ( .A(FSM_exp_operation_A_S), .B(n2546), .Y(
DP_OP_42J154_122_8302_n16) );
CLKAND2X2TS U3256 ( .A(n2555), .B(DmP[61]), .Y(n2547) );
XOR2X1TS U3257 ( .A(FSM_exp_operation_A_S), .B(n2547), .Y(
DP_OP_42J154_122_8302_n17) );
CLKAND2X2TS U3258 ( .A(n2555), .B(DmP[60]), .Y(n2548) );
XOR2X1TS U3259 ( .A(FSM_exp_operation_A_S), .B(n2548), .Y(
DP_OP_42J154_122_8302_n18) );
CLKAND2X2TS U3260 ( .A(n2555), .B(DmP[59]), .Y(n2549) );
XOR2X1TS U3261 ( .A(FSM_exp_operation_A_S), .B(n2549), .Y(
DP_OP_42J154_122_8302_n19) );
CLKAND2X2TS U3262 ( .A(n2555), .B(DmP[58]), .Y(n2550) );
XOR2X1TS U3263 ( .A(FSM_exp_operation_A_S), .B(n2550), .Y(
DP_OP_42J154_122_8302_n20) );
AO22XLTS U3264 ( .A0(n1637), .A1(n1686), .B0(n2555), .B1(DmP[57]), .Y(n2551)
);
XOR2X1TS U3265 ( .A(FSM_exp_operation_A_S), .B(n2551), .Y(
DP_OP_42J154_122_8302_n21) );
AO22XLTS U3266 ( .A0(LZA_output[4]), .A1(n1686), .B0(n2555), .B1(DmP[56]),
.Y(n2552) );
XOR2X1TS U3267 ( .A(FSM_exp_operation_A_S), .B(n2552), .Y(
DP_OP_42J154_122_8302_n22) );
AO22XLTS U3268 ( .A0(n1649), .A1(n1686), .B0(n2555), .B1(DmP[55]), .Y(n2553)
);
XOR2X1TS U3269 ( .A(FSM_exp_operation_A_S), .B(n2553), .Y(
DP_OP_42J154_122_8302_n23) );
AO22XLTS U3270 ( .A0(LZA_output[2]), .A1(n1686), .B0(n2555), .B1(DmP[54]),
.Y(n2554) );
XOR2X1TS U3271 ( .A(FSM_exp_operation_A_S), .B(n2554), .Y(
DP_OP_42J154_122_8302_n24) );
AO22XLTS U3272 ( .A0(n1648), .A1(n1686), .B0(n2555), .B1(DmP[53]), .Y(n2556)
);
XOR2X1TS U3273 ( .A(FSM_exp_operation_A_S), .B(n2556), .Y(
DP_OP_42J154_122_8302_n25) );
AO21XLTS U3274 ( .A0(DmP[52]), .A1(n2953), .B0(n2557), .Y(n2558) );
XOR2X1TS U3275 ( .A(FSM_exp_operation_A_S), .B(n2558), .Y(
DP_OP_42J154_122_8302_n26) );
INVX6TS U3276 ( .A(n2902), .Y(n2570) );
AOI22X1TS U3277 ( .A0(n2560), .A1(n1663), .B0(n2559), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n2561) );
OAI21XLTS U3278 ( .A0(n2562), .A1(n3031), .B0(n2561), .Y(n2563) );
MXI2X1TS U3279 ( .A(n2565), .B(n2927), .S0(n2564), .Y(n1469) );
XOR2X1TS U3280 ( .A(DP_OP_45J154_125_8406_n1), .B(n2567), .Y(n2568) );
INVX2TS U3281 ( .A(n2574), .Y(n2805) );
MX2X1TS U3282 ( .A(Exp_Operation_Module_Data_S[10]), .B(exp_oper_result[10]),
.S0(n2573), .Y(n1428) );
MX2X1TS U3283 ( .A(DMP[62]), .B(exp_oper_result[10]), .S0(n2572), .Y(
S_Oper_A_exp[10]) );
MX2X1TS U3284 ( .A(Exp_Operation_Module_Data_S[9]), .B(exp_oper_result[9]),
.S0(n2573), .Y(n1429) );
MX2X1TS U3285 ( .A(DMP[61]), .B(exp_oper_result[9]), .S0(n2572), .Y(
S_Oper_A_exp[9]) );
MX2X1TS U3286 ( .A(Exp_Operation_Module_Data_S[8]), .B(exp_oper_result[8]),
.S0(n2573), .Y(n1430) );
MX2X1TS U3287 ( .A(DMP[60]), .B(exp_oper_result[8]), .S0(n2572), .Y(
S_Oper_A_exp[8]) );
MX2X1TS U3288 ( .A(Exp_Operation_Module_Data_S[7]), .B(exp_oper_result[7]),
.S0(n2573), .Y(n1431) );
MX2X1TS U3289 ( .A(DMP[59]), .B(exp_oper_result[7]), .S0(n2572), .Y(
S_Oper_A_exp[7]) );
MX2X1TS U3290 ( .A(Exp_Operation_Module_Data_S[6]), .B(exp_oper_result[6]),
.S0(n2573), .Y(n1432) );
MX2X1TS U3291 ( .A(DMP[58]), .B(exp_oper_result[6]), .S0(n2572), .Y(
S_Oper_A_exp[6]) );
MX2X1TS U3292 ( .A(Exp_Operation_Module_Data_S[5]), .B(exp_oper_result[5]),
.S0(n2573), .Y(n1433) );
MX2X1TS U3293 ( .A(DMP[57]), .B(exp_oper_result[5]), .S0(n2572), .Y(
S_Oper_A_exp[5]) );
MX2X1TS U3294 ( .A(Exp_Operation_Module_Data_S[4]), .B(exp_oper_result[4]),
.S0(n2573), .Y(n1434) );
MX2X1TS U3295 ( .A(DMP[56]), .B(exp_oper_result[4]), .S0(n2570), .Y(
S_Oper_A_exp[4]) );
MX2X1TS U3296 ( .A(Exp_Operation_Module_Data_S[3]), .B(exp_oper_result[3]),
.S0(n2573), .Y(n1435) );
MX2X1TS U3297 ( .A(DMP[55]), .B(exp_oper_result[3]), .S0(n2570), .Y(
S_Oper_A_exp[3]) );
MX2X1TS U3298 ( .A(DMP[54]), .B(n1658), .S0(n2570), .Y(S_Oper_A_exp[2]) );
MX2X1TS U3299 ( .A(Exp_Operation_Module_Data_S[1]), .B(n1626), .S0(n2573),
.Y(n1437) );
MX2X1TS U3300 ( .A(DMP[53]), .B(n1626), .S0(n2570), .Y(S_Oper_A_exp[1]) );
AO21XLTS U3301 ( .A0(n2573), .A1(exp_oper_result[0]), .B0(n2571), .Y(n1438)
);
MX2X1TS U3302 ( .A(DMP[52]), .B(exp_oper_result[0]), .S0(n2570), .Y(
S_Oper_A_exp[0]) );
MX2X1TS U3303 ( .A(Exp_Operation_Module_Data_S[2]), .B(n1658), .S0(n2573),
.Y(n1436) );
AO22XLTS U3304 ( .A0(Add_Subt_Sgf_module_S_to_D[0]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[0]), .Y(n1503) );
AO22XLTS U3305 ( .A0(Add_Subt_Sgf_module_S_to_D[1]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[1]), .Y(n1504) );
AO22XLTS U3306 ( .A0(Add_Subt_Sgf_module_S_to_D[2]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[2]), .Y(n1505) );
BUFX3TS U3307 ( .A(n2574), .Y(n2576) );
AO22XLTS U3308 ( .A0(Add_Subt_Sgf_module_S_to_D[3]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[3]), .Y(n1506) );
AO22XLTS U3309 ( .A0(Add_Subt_Sgf_module_S_to_D[4]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[4]), .Y(n1507) );
AO22XLTS U3310 ( .A0(Add_Subt_Sgf_module_S_to_D[6]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[6]), .Y(n1509) );
AO22XLTS U3311 ( .A0(Add_Subt_Sgf_module_S_to_D[8]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[8]), .Y(n1511) );
AO22XLTS U3312 ( .A0(Add_Subt_Sgf_module_S_to_D[9]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[9]), .Y(n1512) );
AO22XLTS U3313 ( .A0(Add_Subt_Sgf_module_S_to_D[10]), .A1(n2805), .B0(n2575),
.B1(Add_Subt_result[10]), .Y(n1513) );
CLKINVX6TS U3314 ( .A(n2574), .Y(n2577) );
AO22XLTS U3315 ( .A0(Add_Subt_Sgf_module_S_to_D[12]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[12]), .Y(n1515) );
AO22XLTS U3316 ( .A0(Add_Subt_Sgf_module_S_to_D[13]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[13]), .Y(n1516) );
AO22XLTS U3317 ( .A0(Add_Subt_Sgf_module_S_to_D[14]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[14]), .Y(n1517) );
AO22XLTS U3318 ( .A0(Add_Subt_Sgf_module_S_to_D[15]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[15]), .Y(n1518) );
AO22XLTS U3319 ( .A0(Add_Subt_Sgf_module_S_to_D[16]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[16]), .Y(n1519) );
AO22XLTS U3320 ( .A0(Add_Subt_Sgf_module_S_to_D[18]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[18]), .Y(n1521) );
AO22XLTS U3321 ( .A0(Add_Subt_Sgf_module_S_to_D[20]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[20]), .Y(n1523) );
AO22XLTS U3322 ( .A0(Add_Subt_Sgf_module_S_to_D[34]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[34]), .Y(n1537) );
AO22XLTS U3323 ( .A0(Add_Subt_Sgf_module_S_to_D[33]), .A1(n2578), .B0(n1677),
.B1(Add_Subt_result[33]), .Y(n1536) );
AO22XLTS U3324 ( .A0(Add_Subt_Sgf_module_S_to_D[32]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[32]), .Y(n1535) );
AO22XLTS U3325 ( .A0(Add_Subt_Sgf_module_S_to_D[23]), .A1(n2578), .B0(n1677),
.B1(Add_Subt_result[23]), .Y(n1526) );
AO22XLTS U3326 ( .A0(Add_Subt_Sgf_module_S_to_D[24]), .A1(n2578), .B0(n2576),
.B1(Add_Subt_result[24]), .Y(n1527) );
AO22XLTS U3327 ( .A0(Add_Subt_Sgf_module_S_to_D[30]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[30]), .Y(n1533) );
AO22XLTS U3328 ( .A0(Add_Subt_Sgf_module_S_to_D[25]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[25]), .Y(n1528) );
AO22XLTS U3329 ( .A0(Add_Subt_Sgf_module_S_to_D[26]), .A1(n2578), .B0(n2574),
.B1(Add_Subt_result[26]), .Y(n1529) );
AO22XLTS U3330 ( .A0(Add_Subt_Sgf_module_S_to_D[28]), .A1(n2578), .B0(n2575),
.B1(Add_Subt_result[28]), .Y(n1531) );
AOI22X1TS U3331 ( .A0(n2790), .A1(n1625), .B0(n2589), .B1(n2586), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[54]) );
OAI22X1TS U3332 ( .A0(n2597), .A1(n2580), .B0(n2596), .B1(n2579), .Y(n2595)
);
OAI22X1TS U3333 ( .A0(n2583), .A1(n2582), .B0(n2581), .B1(n1625), .Y(n2594)
);
OAI22X1TS U3334 ( .A0(n2587), .A1(n2586), .B0(n2585), .B1(n2584), .Y(n2593)
);
OAI22X1TS U3335 ( .A0(n2591), .A1(n2590), .B0(n2589), .B1(n2588), .Y(n2592)
);
OR4X2TS U3336 ( .A(n2595), .B(n2594), .C(n2593), .D(n2592), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[48]) );
INVX2TS U3337 ( .A(n2596), .Y(n2604) );
AOI22X1TS U3338 ( .A0(n2714), .A1(n2602), .B0(n2788), .B1(n2604), .Y(n2601)
);
INVX2TS U3339 ( .A(n2597), .Y(n2608) );
AOI22X1TS U3340 ( .A0(n2753), .A1(n2608), .B0(n1741), .B1(n2606), .Y(n2600)
);
AOI22X1TS U3341 ( .A0(n2793), .A1(n2607), .B0(n2790), .B1(n1630), .Y(n2599)
);
AOI22X1TS U3342 ( .A0(n1705), .A1(n1593), .B0(n2798), .B1(n2603), .Y(n2598)
);
NAND4XLTS U3343 ( .A(n2601), .B(n2600), .C(n2599), .D(n2598), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[47]) );
AOI22X1TS U3344 ( .A0(n2714), .A1(n2603), .B0(n2788), .B1(n2602), .Y(n2612)
);
AOI22X1TS U3345 ( .A0(n2796), .A1(n2604), .B0(n1741), .B1(n1630), .Y(n2611)
);
AOI22X1TS U3346 ( .A0(n2793), .A1(n2606), .B0(n2790), .B1(n2605), .Y(n2610)
);
AOI22X1TS U3347 ( .A0(n1705), .A1(n2608), .B0(n2671), .B1(n2607), .Y(n2609)
);
NAND4XLTS U3348 ( .A(n2612), .B(n2611), .C(n2610), .D(n2609), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[46]) );
AOI22X1TS U3349 ( .A0(n2671), .A1(n2623), .B0(n1705), .B1(n2613), .Y(n2614)
);
OAI221XLTS U3350 ( .A0(n2650), .A1(n2615), .B0(n2651), .B1(n2625), .C0(n2614), .Y(Barrel_Shifter_module_Mux_Array_Data_array[38]) );
AOI22X1TS U3351 ( .A0(n1705), .A1(n2617), .B0(n2671), .B1(n2630), .Y(n2618)
);
OAI221XLTS U3352 ( .A0(n2650), .A1(n2619), .B0(n2651), .B1(n2632), .C0(n2618), .Y(Barrel_Shifter_module_Mux_Array_Data_array[37]) );
AOI22X1TS U3353 ( .A0(n2671), .A1(n1636), .B0(n1705), .B1(n2620), .Y(n2621)
);
OAI221XLTS U3354 ( .A0(n2650), .A1(n2622), .B0(n2651), .B1(n2635), .C0(n2621), .Y(Barrel_Shifter_module_Mux_Array_Data_array[35]) );
AOI22X1TS U3355 ( .A0(n2671), .A1(n2637), .B0(n1705), .B1(n2623), .Y(n2624)
);
OAI221XLTS U3356 ( .A0(n2650), .A1(n2625), .B0(n2651), .B1(n2640), .C0(n2624), .Y(Barrel_Shifter_module_Mux_Array_Data_array[34]) );
AOI22X1TS U3357 ( .A0(n1705), .A1(n2630), .B0(n2671), .B1(n2642), .Y(n2631)
);
OAI221XLTS U3358 ( .A0(n2650), .A1(n2632), .B0(n2651), .B1(n2645), .C0(n2631), .Y(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
AOI22X1TS U3359 ( .A0(n2800), .A1(n1636), .B0(n2671), .B1(n2646), .Y(n2633)
);
OAI221XLTS U3360 ( .A0(n2650), .A1(n2635), .B0(n2651), .B1(n2634), .C0(n2633), .Y(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
AOI22X1TS U3361 ( .A0(n2800), .A1(n2637), .B0(n2671), .B1(n2636), .Y(n2638)
);
OAI221XLTS U3362 ( .A0(n2650), .A1(n2640), .B0(n2651), .B1(n2639), .C0(n2638), .Y(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
AOI22X1TS U3363 ( .A0(n2800), .A1(n2642), .B0(n2798), .B1(n2641), .Y(n2643)
);
OAI221XLTS U3364 ( .A0(n2650), .A1(n2645), .B0(n2651), .B1(n2644), .C0(n2643), .Y(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
AOI22X1TS U3365 ( .A0(n2753), .A1(n2646), .B0(n2793), .B1(n1635), .Y(n2647)
);
OAI221XLTS U3366 ( .A0(n2650), .A1(n2649), .B0(n2651), .B1(n2648), .C0(n2647), .Y(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
AOI22X1TS U3367 ( .A0(n2671), .A1(n2672), .B0(n2204), .B1(n1653), .Y(n2656)
);
AOI22X1TS U3368 ( .A0(n2800), .A1(n1634), .B0(n2795), .B1(n1651), .Y(n2655)
);
AOI22X1TS U3369 ( .A0(n2796), .A1(n1602), .B0(n2790), .B1(n2688), .Y(n2654)
);
NAND2X1TS U3370 ( .A(n2652), .B(n2651), .Y(n2653) );
NAND4XLTS U3371 ( .A(n2656), .B(n2655), .C(n2654), .D(n2653), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AOI22X1TS U3372 ( .A0(n2671), .A1(n1653), .B0(n2793), .B1(n1651), .Y(n2657)
);
OAI31X1TS U3373 ( .A0(n2666), .A1(n2665), .A2(n2658), .B0(n2657), .Y(n2662)
);
AOI22X1TS U3374 ( .A0(n2714), .A1(n2672), .B0(n2780), .B1(n2659), .Y(n2661)
);
AOI22X1TS U3375 ( .A0(n2795), .A1(n2688), .B0(n2790), .B1(n2695), .Y(n2660)
);
NAND3BXLTS U3376 ( .AN(n2662), .B(n2661), .C(n2660), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
AOI22X1TS U3377 ( .A0(n2671), .A1(n1651), .B0(n2793), .B1(n2688), .Y(n2663)
);
OAI31X1TS U3378 ( .A0(n2666), .A1(n2665), .A2(n2664), .B0(n2663), .Y(n2669)
);
AOI22X1TS U3379 ( .A0(n2714), .A1(n1653), .B0(n2780), .B1(n2672), .Y(n2668)
);
AOI22X1TS U3380 ( .A0(n2795), .A1(n2695), .B0(n2790), .B1(n2703), .Y(n2667)
);
NAND3BXLTS U3381 ( .AN(n2669), .B(n2668), .C(n2667), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[20]) );
AOI22X1TS U3382 ( .A0(n2714), .A1(n2688), .B0(n2788), .B1(n1651), .Y(n2676)
);
AOI22X1TS U3383 ( .A0(n2796), .A1(n1653), .B0(n2795), .B1(n2709), .Y(n2675)
);
AOI22X1TS U3384 ( .A0(Add_Subt_result[36]), .A1(n2206), .B0(DmP[16]), .B1(
n2766), .Y(n2670) );
OAI21X4TS U3385 ( .A0(n3021), .A1(n2723), .B0(n2670), .Y(n2716) );
AOI22X1TS U3386 ( .A0(n2793), .A1(n2703), .B0(n2790), .B1(n2716), .Y(n2674)
);
AOI22X1TS U3387 ( .A0(n2800), .A1(n2672), .B0(n2671), .B1(n2695), .Y(n2673)
);
NAND4XLTS U3388 ( .A(n2676), .B(n2675), .C(n2674), .D(n2673), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
AOI22X1TS U3389 ( .A0(n2714), .A1(n2695), .B0(n2780), .B1(n2688), .Y(n2681)
);
AOI22X1TS U3390 ( .A0(n2796), .A1(n1651), .B0(n2795), .B1(n2716), .Y(n2680)
);
AOI22X1TS U3391 ( .A0(Add_Subt_result[17]), .A1(n2700), .B0(DmP[15]), .B1(
n2766), .Y(n2677) );
OAI21X4TS U3392 ( .A0(n3013), .A1(n2786), .B0(n2677), .Y(n2724) );
AOI22X1TS U3393 ( .A0(n2793), .A1(n2709), .B0(n1752), .B1(n2724), .Y(n2679)
);
AOI22X1TS U3394 ( .A0(n2800), .A1(n1653), .B0(n2671), .B1(n2703), .Y(n2678)
);
NAND4XLTS U3395 ( .A(n2681), .B(n2680), .C(n2679), .D(n2678), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
AOI22X1TS U3396 ( .A0(n2714), .A1(n2703), .B0(n2788), .B1(n2695), .Y(n2686)
);
AOI22X1TS U3397 ( .A0(n2796), .A1(n2688), .B0(n2795), .B1(n2724), .Y(n2685)
);
AOI22X1TS U3398 ( .A0(Add_Subt_result[38]), .A1(n2206), .B0(DmP[14]), .B1(
n2815), .Y(n2682) );
OAI21X4TS U3399 ( .A0(n2875), .A1(n2723), .B0(n2682), .Y(n2730) );
AOI22X1TS U3400 ( .A0(n2793), .A1(n2716), .B0(n2790), .B1(n2730), .Y(n2684)
);
AOI22X1TS U3401 ( .A0(n2800), .A1(n1651), .B0(n2671), .B1(n2709), .Y(n2683)
);
NAND4XLTS U3402 ( .A(n2686), .B(n2685), .C(n2684), .D(n2683), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
AOI22X1TS U3403 ( .A0(n2714), .A1(n2709), .B0(n2788), .B1(n2703), .Y(n2692)
);
AOI22X1TS U3404 ( .A0(n2796), .A1(n2695), .B0(n2795), .B1(n2730), .Y(n2691)
);
AOI22X1TS U3405 ( .A0(Add_Subt_result[39]), .A1(n2206), .B0(DmP[13]), .B1(
n2815), .Y(n2687) );
OAI21X4TS U3406 ( .A0(n3022), .A1(n1579), .B0(n2687), .Y(n2736) );
AOI22X1TS U3407 ( .A0(n2793), .A1(n2724), .B0(n2790), .B1(n2736), .Y(n2690)
);
AOI22X1TS U3408 ( .A0(n2800), .A1(n2688), .B0(n2671), .B1(n2716), .Y(n2689)
);
NAND4XLTS U3409 ( .A(n2692), .B(n2691), .C(n2690), .D(n2689), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
AOI22X1TS U3410 ( .A0(n2714), .A1(n2716), .B0(n2788), .B1(n2709), .Y(n2699)
);
AOI22X1TS U3411 ( .A0(n2796), .A1(n2703), .B0(n2795), .B1(n2736), .Y(n2698)
);
AOI22X1TS U3412 ( .A0(Add_Subt_result[40]), .A1(n2206), .B0(DmP[12]), .B1(
n2815), .Y(n2694) );
OAI21X4TS U3413 ( .A0(n1629), .A1(n1579), .B0(n2694), .Y(n2742) );
AOI22X1TS U3414 ( .A0(n2793), .A1(n2730), .B0(n2790), .B1(n2742), .Y(n2697)
);
AOI22X1TS U3415 ( .A0(n2800), .A1(n2695), .B0(n2798), .B1(n2724), .Y(n2696)
);
NAND4XLTS U3416 ( .A(n2699), .B(n2698), .C(n2697), .D(n2696), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
AOI22X1TS U3417 ( .A0(n2714), .A1(n2724), .B0(n2788), .B1(n2716), .Y(n2707)
);
AOI22X1TS U3418 ( .A0(n2796), .A1(n2709), .B0(n2795), .B1(n2742), .Y(n2706)
);
AOI22X1TS U3419 ( .A0(Add_Subt_result[13]), .A1(n2700), .B0(DmP[11]), .B1(
n2815), .Y(n2701) );
OAI21X4TS U3420 ( .A0(n2702), .A1(n2786), .B0(n2701), .Y(n2748) );
AOI22X1TS U3421 ( .A0(n2793), .A1(n2736), .B0(n2790), .B1(n2748), .Y(n2705)
);
AOI22X1TS U3422 ( .A0(n2800), .A1(n2703), .B0(n2798), .B1(n2730), .Y(n2704)
);
NAND4XLTS U3423 ( .A(n2707), .B(n2706), .C(n2705), .D(n2704), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
AOI22X1TS U3424 ( .A0(n2714), .A1(n2730), .B0(n2788), .B1(n2724), .Y(n2713)
);
AOI22X1TS U3425 ( .A0(n2796), .A1(n2716), .B0(n1741), .B1(n2748), .Y(n2712)
);
AOI22X1TS U3426 ( .A0(Add_Subt_result[42]), .A1(n2206), .B0(DmP[10]), .B1(
n2766), .Y(n2708) );
OAI21X4TS U3427 ( .A0(n3015), .A1(n1579), .B0(n2708), .Y(n2755) );
AOI22X1TS U3428 ( .A0(n2793), .A1(n2742), .B0(n2790), .B1(n2755), .Y(n2711)
);
AOI22X1TS U3429 ( .A0(n2800), .A1(n2709), .B0(n2798), .B1(n2736), .Y(n2710)
);
NAND4XLTS U3430 ( .A(n2713), .B(n2712), .C(n2711), .D(n2710), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
AOI22X1TS U3431 ( .A0(n2714), .A1(n2736), .B0(n2780), .B1(n2730), .Y(n2720)
);
AOI22X1TS U3432 ( .A0(n2753), .A1(n2724), .B0(n2795), .B1(n2755), .Y(n2719)
);
AOI22X1TS U3433 ( .A0(Add_Subt_result[11]), .A1(n2700), .B0(DmP[9]), .B1(
n2766), .Y(n2715) );
OAI21X4TS U3434 ( .A0(n2907), .A1(n1675), .B0(n2715), .Y(n2761) );
AOI22X1TS U3435 ( .A0(n2204), .A1(n2748), .B0(n2790), .B1(n2761), .Y(n2718)
);
AOI22X1TS U3436 ( .A0(n2800), .A1(n2716), .B0(n2798), .B1(n2742), .Y(n2717)
);
NAND4XLTS U3437 ( .A(n2720), .B(n2719), .C(n2718), .D(n2717), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
AOI22X1TS U3438 ( .A0(n2714), .A1(n2742), .B0(n2780), .B1(n2736), .Y(n2728)
);
AOI22X1TS U3439 ( .A0(n2796), .A1(n2730), .B0(n1741), .B1(n2761), .Y(n2727)
);
AOI22X1TS U3440 ( .A0(Add_Subt_result[44]), .A1(n2206), .B0(DmP[8]), .B1(
n2766), .Y(n2722) );
OAI21X4TS U3441 ( .A0(n3017), .A1(n2723), .B0(n2722), .Y(n2768) );
AOI22X1TS U3442 ( .A0(n2204), .A1(n2755), .B0(n2790), .B1(n2768), .Y(n2726)
);
AOI22X1TS U3443 ( .A0(n2800), .A1(n2724), .B0(n2798), .B1(n2748), .Y(n2725)
);
NAND4XLTS U3444 ( .A(n2728), .B(n2727), .C(n2726), .D(n2725), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI22X1TS U3445 ( .A0(n2714), .A1(n2748), .B0(n2780), .B1(n2742), .Y(n2734)
);
AOI22X1TS U3446 ( .A0(n2753), .A1(n2736), .B0(n1741), .B1(n2768), .Y(n2733)
);
AOI22X1TS U3447 ( .A0(Add_Subt_result[45]), .A1(n2206), .B0(DmP[7]), .B1(
n2815), .Y(n2729) );
OAI21X4TS U3448 ( .A0(n3004), .A1(n1579), .B0(n2729), .Y(n2775) );
AOI22X1TS U3449 ( .A0(n2204), .A1(n2761), .B0(n2790), .B1(n2775), .Y(n2732)
);
AOI22X1TS U3450 ( .A0(n2800), .A1(n2730), .B0(n2798), .B1(n2755), .Y(n2731)
);
NAND4XLTS U3451 ( .A(n2734), .B(n2733), .C(n2732), .D(n2731), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI22X1TS U3452 ( .A0(n2714), .A1(n2755), .B0(n2780), .B1(n2748), .Y(n2740)
);
AOI22X1TS U3453 ( .A0(n2753), .A1(n2742), .B0(n1741), .B1(n2775), .Y(n2739)
);
AOI22X1TS U3454 ( .A0(Add_Subt_result[46]), .A1(n2693), .B0(DmP[6]), .B1(
n2815), .Y(n2735) );
OAI21X4TS U3455 ( .A0(n2897), .A1(n1579), .B0(n2735), .Y(n2781) );
AOI22X1TS U3456 ( .A0(n2204), .A1(n2768), .B0(n2790), .B1(n2781), .Y(n2738)
);
AOI22X1TS U3457 ( .A0(n2800), .A1(n2736), .B0(n2798), .B1(n2761), .Y(n2737)
);
NAND4XLTS U3458 ( .A(n2740), .B(n2739), .C(n2738), .D(n2737), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI22X1TS U3459 ( .A0(n2714), .A1(n2761), .B0(n2780), .B1(n2755), .Y(n2746)
);
AOI22X1TS U3460 ( .A0(n2753), .A1(n2748), .B0(n2795), .B1(n2781), .Y(n2745)
);
AOI22X1TS U3461 ( .A0(Add_Subt_result[7]), .A1(n2700), .B0(DmP[5]), .B1(
n2766), .Y(n2741) );
OAI21X4TS U3462 ( .A0(n2901), .A1(n2786), .B0(n2741), .Y(n2799) );
AOI22X1TS U3463 ( .A0(n2793), .A1(n2775), .B0(n2790), .B1(n2799), .Y(n2744)
);
AOI22X1TS U3464 ( .A0(n2800), .A1(n2742), .B0(n2798), .B1(n2768), .Y(n2743)
);
NAND4XLTS U3465 ( .A(n2746), .B(n2745), .C(n2744), .D(n2743), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
AOI22X1TS U3466 ( .A0(n2714), .A1(n2768), .B0(n2780), .B1(n2761), .Y(n2752)
);
AOI22X1TS U3467 ( .A0(n2753), .A1(n2755), .B0(n2795), .B1(n2799), .Y(n2751)
);
AOI22X1TS U3468 ( .A0(Add_Subt_result[48]), .A1(n2206), .B0(DmP[4]), .B1(
n2721), .Y(n2747) );
AOI22X1TS U3469 ( .A0(n2793), .A1(n2781), .B0(n2790), .B1(n1650), .Y(n2750)
);
AOI22X1TS U3470 ( .A0(n2800), .A1(n2748), .B0(n2798), .B1(n2775), .Y(n2749)
);
NAND4XLTS U3471 ( .A(n2752), .B(n2751), .C(n2750), .D(n2749), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
AOI22X1TS U3472 ( .A0(n2714), .A1(n2775), .B0(n2780), .B1(n2768), .Y(n2759)
);
AOI22X1TS U3473 ( .A0(n2753), .A1(n2761), .B0(n2795), .B1(n1650), .Y(n2758)
);
AOI22X1TS U3474 ( .A0(Add_Subt_result[49]), .A1(n2693), .B0(DmP[3]), .B1(
n2815), .Y(n2754) );
OAI2BB1X2TS U3475 ( .A0N(n1668), .A1N(n2700), .B0(n2754), .Y(n2787) );
AOI22X1TS U3476 ( .A0(n2793), .A1(n2799), .B0(n2790), .B1(n2787), .Y(n2757)
);
AOI22X1TS U3477 ( .A0(n2800), .A1(n2755), .B0(n2798), .B1(n2781), .Y(n2756)
);
NAND4XLTS U3478 ( .A(n2759), .B(n2758), .C(n2757), .D(n2756), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
AOI22X1TS U3479 ( .A0(n2714), .A1(n2781), .B0(n2780), .B1(n2775), .Y(n2765)
);
AOI22X1TS U3480 ( .A0(n2796), .A1(n2768), .B0(n2795), .B1(n2787), .Y(n2764)
);
AOI22X1TS U3481 ( .A0(Add_Subt_result[50]), .A1(n2773), .B0(DmP[2]), .B1(
n2766), .Y(n2760) );
AOI22X1TS U3482 ( .A0(n2793), .A1(n1650), .B0(n2790), .B1(n2791), .Y(n2763)
);
AOI22X1TS U3483 ( .A0(n2800), .A1(n2761), .B0(n2798), .B1(n2799), .Y(n2762)
);
NAND4XLTS U3484 ( .A(n2765), .B(n2764), .C(n2763), .D(n2762), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U3485 ( .A0(n2714), .A1(n2799), .B0(n2780), .B1(n2781), .Y(n2772)
);
AOI22X1TS U3486 ( .A0(n2796), .A1(n2775), .B0(n2795), .B1(n2791), .Y(n2771)
);
AOI22X1TS U3487 ( .A0(Add_Subt_result[51]), .A1(n2206), .B0(DmP[1]), .B1(
n2766), .Y(n2767) );
AOI22X1TS U3488 ( .A0(n2793), .A1(n2787), .B0(n2790), .B1(n2797), .Y(n2770)
);
AOI22X1TS U3489 ( .A0(n2800), .A1(n2768), .B0(n2798), .B1(n1650), .Y(n2769)
);
NAND4XLTS U3490 ( .A(n2772), .B(n2771), .C(n2770), .D(n2769), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AOI22X1TS U3491 ( .A0(n2714), .A1(n1650), .B0(n2780), .B1(n2799), .Y(n2779)
);
AOI22X1TS U3492 ( .A0(Add_Subt_result[52]), .A1(n2693), .B0(DmP[0]), .B1(
n2815), .Y(n2774) );
AOI22X1TS U3493 ( .A0(n2796), .A1(n2781), .B0(n2790), .B1(n2792), .Y(n2778)
);
AOI22X1TS U3494 ( .A0(n2793), .A1(n2791), .B0(n1741), .B1(n2797), .Y(n2777)
);
AOI22X1TS U3495 ( .A0(n2800), .A1(n2775), .B0(n2798), .B1(n2787), .Y(n2776)
);
NAND4XLTS U3496 ( .A(n2779), .B(n2778), .C(n2777), .D(n2776), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AOI22X1TS U3497 ( .A0(n2714), .A1(n2787), .B0(n2780), .B1(n1650), .Y(n2785)
);
AOI22X1TS U3498 ( .A0(n2796), .A1(n2799), .B0(n2795), .B1(n2792), .Y(n2784)
);
OAI22X1TS U3499 ( .A0(n2899), .A1(n2786), .B0(n3035), .B1(n1579), .Y(n2794)
);
AOI22X1TS U3500 ( .A0(n2793), .A1(n2797), .B0(n2790), .B1(n2794), .Y(n2783)
);
AOI22X1TS U3501 ( .A0(n2800), .A1(n2781), .B0(n2798), .B1(n2791), .Y(n2782)
);
NAND4XLTS U3502 ( .A(n2785), .B(n2784), .C(n2783), .D(n2782), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
OAI22X1TS U3503 ( .A0(n2898), .A1(n2786), .B0(n3036), .B1(n1579), .Y(n2789)
);
AOI22X1TS U3504 ( .A0(n2790), .A1(n2789), .B0(n2780), .B1(n2787), .Y(n2804)
);
AOI22X1TS U3505 ( .A0(n2793), .A1(n2792), .B0(n2714), .B1(n2791), .Y(n2803)
);
AOI22X1TS U3506 ( .A0(n2796), .A1(n1650), .B0(n1741), .B1(n2794), .Y(n2802)
);
AOI22X1TS U3507 ( .A0(n2800), .A1(n2799), .B0(n2798), .B1(n2797), .Y(n2801)
);
NAND4XLTS U3508 ( .A(n2804), .B(n2803), .C(n2802), .D(n2801), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
AOI21X1TS U3509 ( .A0(n2807), .A1(n2806), .B0(n2578), .Y(n2812) );
OAI21X1TS U3510 ( .A0(n2190), .A1(n2808), .B0(n2838), .Y(n2814) );
NAND3XLTS U3511 ( .A(n2812), .B(n2811), .C(n2810), .Y(n1561) );
NAND4XLTS U3512 ( .A(n2820), .B(n2819), .C(n2818), .D(n2817), .Y(n1558) );
AOI21X1TS U3513 ( .A0(Add_Subt_result[49]), .A1(n3007), .B0(
Add_Subt_result[51]), .Y(n2821) );
OAI32X1TS U3514 ( .A0(Add_Subt_result[54]), .A1(Add_Subt_result[52]), .A2(
n2821), .B0(n2899), .B1(Add_Subt_result[54]), .Y(n2822) );
AOI31XLTS U3515 ( .A0(n2823), .A1(Add_Subt_result[45]), .A2(n3009), .B0(
n2822), .Y(n2827) );
NAND4XLTS U3516 ( .A(Add_Subt_result[37]), .B(n1669), .C(n2824), .D(n3011),
.Y(n2826) );
OAI211XLTS U3517 ( .A0(n2828), .A1(n3020), .B0(n2827), .C0(n2826), .Y(n2829)
);
NOR4X1TS U3518 ( .A(n2832), .B(n2831), .C(n2830), .D(n2829), .Y(n2834) );
AOI32X1TS U3519 ( .A0(n2836), .A1(n2835), .A2(n2834), .B0(n3038), .B1(n2833),
.Y(n1499) );
OA22X1TS U3520 ( .A0(n2846), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n2837), .Y(n1425) );
BUFX4TS U3521 ( .A(n2837), .Y(n2840) );
OA22X1TS U3522 ( .A0(n1626), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[53]), .Y(n1424) );
OA22X1TS U3523 ( .A0(n2846), .A1(final_result_ieee[54]), .B0(n1658), .B1(
n2840), .Y(n1423) );
OA22X1TS U3524 ( .A0(exp_oper_result[3]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[55]), .Y(n1422) );
OA22X1TS U3525 ( .A0(exp_oper_result[4]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[56]), .Y(n1421) );
OA22X1TS U3526 ( .A0(n2846), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n2840), .Y(n1420) );
OA22X1TS U3527 ( .A0(exp_oper_result[6]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[58]), .Y(n1419) );
OA22X1TS U3528 ( .A0(exp_oper_result[7]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[59]), .Y(n1418) );
OA22X1TS U3529 ( .A0(exp_oper_result[8]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[60]), .Y(n1417) );
OA22X1TS U3530 ( .A0(exp_oper_result[9]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[61]), .Y(n1416) );
OA22X1TS U3531 ( .A0(exp_oper_result[10]), .A1(n2840), .B0(n2846), .B1(
final_result_ieee[62]), .Y(n1415) );
OAI2BB2XLTS U3532 ( .B0(n2877), .B1(n2840), .A0N(final_result_ieee[0]),
.A1N(n1581), .Y(n1414) );
OAI2BB2XLTS U3533 ( .B0(n2878), .B1(n2840), .A0N(final_result_ieee[1]),
.A1N(n2844), .Y(n1413) );
OAI2BB2XLTS U3534 ( .B0(n2879), .B1(n2840), .A0N(final_result_ieee[2]),
.A1N(n1581), .Y(n1412) );
OAI2BB2XLTS U3535 ( .B0(n2880), .B1(n2840), .A0N(final_result_ieee[3]),
.A1N(n2844), .Y(n1411) );
BUFX4TS U3536 ( .A(n2837), .Y(n2841) );
OAI2BB2XLTS U3537 ( .B0(n2903), .B1(n2841), .A0N(final_result_ieee[4]),
.A1N(n1581), .Y(n1410) );
OAI2BB2XLTS U3538 ( .B0(n2904), .B1(n2841), .A0N(final_result_ieee[5]),
.A1N(n2844), .Y(n1409) );
OAI2BB2XLTS U3539 ( .B0(n2905), .B1(n2841), .A0N(final_result_ieee[6]),
.A1N(n1581), .Y(n1408) );
OAI2BB2XLTS U3540 ( .B0(n2906), .B1(n2841), .A0N(final_result_ieee[7]),
.A1N(n1581), .Y(n1407) );
OAI2BB2XLTS U3541 ( .B0(n2908), .B1(n2841), .A0N(final_result_ieee[8]),
.A1N(n2844), .Y(n1406) );
OAI2BB2XLTS U3542 ( .B0(n2909), .B1(n2841), .A0N(final_result_ieee[9]),
.A1N(n1581), .Y(n1405) );
OAI2BB2XLTS U3543 ( .B0(n2910), .B1(n2841), .A0N(final_result_ieee[10]),
.A1N(n2844), .Y(n1404) );
OAI2BB2XLTS U3544 ( .B0(n2911), .B1(n2841), .A0N(final_result_ieee[11]),
.A1N(n1581), .Y(n1403) );
OAI2BB2XLTS U3545 ( .B0(n2913), .B1(n2841), .A0N(final_result_ieee[12]),
.A1N(n2844), .Y(n1402) );
OAI2BB2XLTS U3546 ( .B0(n2914), .B1(n2841), .A0N(final_result_ieee[13]),
.A1N(n2844), .Y(n1401) );
OAI2BB2XLTS U3547 ( .B0(n2915), .B1(n2841), .A0N(final_result_ieee[14]),
.A1N(n2844), .Y(n1400) );
OAI2BB2XLTS U3548 ( .B0(n2917), .B1(n2841), .A0N(final_result_ieee[15]),
.A1N(n1581), .Y(n1399) );
BUFX4TS U3549 ( .A(n2837), .Y(n2842) );
OAI2BB2XLTS U3550 ( .B0(n2918), .B1(n2842), .A0N(final_result_ieee[16]),
.A1N(n2844), .Y(n1398) );
OAI2BB2XLTS U3551 ( .B0(n2919), .B1(n2842), .A0N(final_result_ieee[17]),
.A1N(n2844), .Y(n1397) );
OAI2BB2XLTS U3552 ( .B0(n2920), .B1(n2842), .A0N(final_result_ieee[18]),
.A1N(n2844), .Y(n1396) );
OAI2BB2XLTS U3553 ( .B0(n2922), .B1(n2842), .A0N(final_result_ieee[19]),
.A1N(n2844), .Y(n1395) );
OAI2BB2XLTS U3554 ( .B0(n2923), .B1(n2842), .A0N(final_result_ieee[20]),
.A1N(n1581), .Y(n1394) );
OAI2BB2XLTS U3555 ( .B0(n2870), .B1(n2842), .A0N(final_result_ieee[21]),
.A1N(n2844), .Y(n1393) );
OAI2BB2XLTS U3556 ( .B0(n2871), .B1(n2842), .A0N(final_result_ieee[22]),
.A1N(n2844), .Y(n1392) );
OAI2BB2XLTS U3557 ( .B0(n2925), .B1(n2842), .A0N(final_result_ieee[23]),
.A1N(n2844), .Y(n1391) );
OAI2BB2XLTS U3558 ( .B0(n2872), .B1(n2842), .A0N(final_result_ieee[24]),
.A1N(n2844), .Y(n1390) );
OAI2BB2XLTS U3559 ( .B0(n2927), .B1(n2842), .A0N(final_result_ieee[25]),
.A1N(n2844), .Y(n1389) );
OAI2BB2XLTS U3560 ( .B0(n2928), .B1(n2842), .A0N(final_result_ieee[26]),
.A1N(n2838), .Y(n1388) );
OAI2BB2XLTS U3561 ( .B0(n2931), .B1(n2842), .A0N(final_result_ieee[27]),
.A1N(n2838), .Y(n1387) );
OAI2BB2XLTS U3562 ( .B0(n2932), .B1(n2840), .A0N(final_result_ieee[28]),
.A1N(n2838), .Y(n1386) );
OAI2BB2XLTS U3563 ( .B0(n2874), .B1(n2841), .A0N(final_result_ieee[29]),
.A1N(n2838), .Y(n1385) );
OAI2BB2XLTS U3564 ( .B0(n2934), .B1(n2842), .A0N(final_result_ieee[30]),
.A1N(n2838), .Y(n1384) );
OAI2BB2XLTS U3565 ( .B0(n2935), .B1(n2840), .A0N(final_result_ieee[31]),
.A1N(n2838), .Y(n1383) );
OAI2BB2XLTS U3566 ( .B0(n2936), .B1(n2841), .A0N(final_result_ieee[32]),
.A1N(n2838), .Y(n1382) );
OAI2BB2XLTS U3567 ( .B0(n2937), .B1(n2842), .A0N(final_result_ieee[33]),
.A1N(n2838), .Y(n1381) );
OAI2BB2XLTS U3568 ( .B0(n2938), .B1(n2841), .A0N(final_result_ieee[34]),
.A1N(n2844), .Y(n1380) );
OAI2BB2XLTS U3569 ( .B0(n2942), .B1(n2842), .A0N(final_result_ieee[35]),
.A1N(n1581), .Y(n1379) );
OAI2BB2XLTS U3570 ( .B0(n2943), .B1(n2841), .A0N(final_result_ieee[36]),
.A1N(n1581), .Y(n1378) );
OAI2BB2XLTS U3571 ( .B0(n2946), .B1(n2842), .A0N(final_result_ieee[37]),
.A1N(n1581), .Y(n1377) );
OAI2BB2XLTS U3572 ( .B0(n2947), .B1(n2841), .A0N(final_result_ieee[38]),
.A1N(n1581), .Y(n1376) );
OAI2BB2XLTS U3573 ( .B0(n2954), .B1(n2840), .A0N(final_result_ieee[39]),
.A1N(n2844), .Y(n1375) );
OAI2BB2XLTS U3574 ( .B0(n2958), .B1(n2842), .A0N(final_result_ieee[40]),
.A1N(n2844), .Y(n1374) );
OAI2BB2XLTS U3575 ( .B0(n2982), .B1(n2839), .A0N(final_result_ieee[42]),
.A1N(n1581), .Y(n1372) );
OAI2BB2XLTS U3576 ( .B0(n2983), .B1(n2839), .A0N(final_result_ieee[43]),
.A1N(n1581), .Y(n1371) );
OAI2BB2XLTS U3577 ( .B0(n2994), .B1(n2839), .A0N(final_result_ieee[44]),
.A1N(n2844), .Y(n1370) );
OAI2BB2XLTS U3578 ( .B0(n3005), .B1(n2840), .A0N(final_result_ieee[46]),
.A1N(n1581), .Y(n1368) );
OAI2BB2XLTS U3579 ( .B0(n3006), .B1(n2841), .A0N(final_result_ieee[47]),
.A1N(n2844), .Y(n1367) );
OAI2BB2XLTS U3580 ( .B0(n3018), .B1(n2842), .A0N(final_result_ieee[48]),
.A1N(n1581), .Y(n1366) );
OAI2BB2XLTS U3581 ( .B0(n3023), .B1(n2840), .A0N(final_result_ieee[49]),
.A1N(n2844), .Y(n1365) );
OAI2BB2XLTS U3582 ( .B0(n3024), .B1(n2841), .A0N(final_result_ieee[50]),
.A1N(n1581), .Y(n1364) );
OAI2BB2XLTS U3583 ( .B0(n3034), .B1(n2842), .A0N(final_result_ieee[51]),
.A1N(n1581), .Y(n1363) );
AOI21X1TS U3584 ( .A0(n2866), .A1(n2843), .B0(overflow_flag), .Y(n2845) );
AO22XLTS U3585 ( .A0(n2846), .A1(n2845), .B0(n1581), .B1(
final_result_ieee[63]), .Y(n1361) );
BUFX3TS U3586 ( .A(n2859), .Y(n2848) );
AO22XLTS U3587 ( .A0(n2847), .A1(intDX[62]), .B0(n2848), .B1(Data_X[62]),
.Y(n1359) );
AO22XLTS U3588 ( .A0(n2847), .A1(intDX[61]), .B0(n2848), .B1(Data_X[61]),
.Y(n1358) );
AO22XLTS U3589 ( .A0(n2847), .A1(intDX[60]), .B0(n2848), .B1(Data_X[60]),
.Y(n1357) );
AO22XLTS U3590 ( .A0(n2847), .A1(intDX[59]), .B0(n2848), .B1(Data_X[59]),
.Y(n1356) );
BUFX4TS U3591 ( .A(n2859), .Y(n2856) );
AO22XLTS U3592 ( .A0(n2847), .A1(intDX[58]), .B0(n2852), .B1(Data_X[58]),
.Y(n1355) );
AO22XLTS U3593 ( .A0(n2847), .A1(intDX[57]), .B0(n2852), .B1(Data_X[57]),
.Y(n1354) );
AO22XLTS U3594 ( .A0(n2847), .A1(intDX[56]), .B0(n2852), .B1(Data_X[56]),
.Y(n1353) );
AO22XLTS U3595 ( .A0(n2847), .A1(intDX[55]), .B0(n2852), .B1(Data_X[55]),
.Y(n1352) );
AO22XLTS U3596 ( .A0(n2847), .A1(intDX[54]), .B0(n2852), .B1(Data_X[54]),
.Y(n1351) );
AO22XLTS U3597 ( .A0(n2847), .A1(intDX[53]), .B0(n2852), .B1(Data_X[53]),
.Y(n1350) );
AO22XLTS U3598 ( .A0(n2847), .A1(intDX[52]), .B0(n2852), .B1(Data_X[52]),
.Y(n1349) );
AO22XLTS U3599 ( .A0(n2847), .A1(intDX[51]), .B0(n2852), .B1(Data_X[51]),
.Y(n1348) );
AO22XLTS U3600 ( .A0(n2847), .A1(intDX[50]), .B0(n2852), .B1(Data_X[50]),
.Y(n1347) );
AO22XLTS U3601 ( .A0(n2850), .A1(intDX[49]), .B0(n2852), .B1(Data_X[49]),
.Y(n1346) );
AO22XLTS U3602 ( .A0(n2851), .A1(intDX[48]), .B0(n2852), .B1(Data_X[48]),
.Y(n1345) );
AO22XLTS U3603 ( .A0(n2849), .A1(intDX[47]), .B0(n2848), .B1(Data_X[47]),
.Y(n1344) );
AO22XLTS U3604 ( .A0(n2850), .A1(intDX[46]), .B0(n2848), .B1(Data_X[46]),
.Y(n1343) );
BUFX4TS U3605 ( .A(n2859), .Y(n2857) );
AO22XLTS U3606 ( .A0(n2855), .A1(intDX[45]), .B0(n2857), .B1(Data_X[45]),
.Y(n1342) );
AO22XLTS U3607 ( .A0(n2855), .A1(intDX[44]), .B0(n2856), .B1(Data_X[44]),
.Y(n1341) );
AO22XLTS U3608 ( .A0(n2851), .A1(intDX[43]), .B0(n2852), .B1(Data_X[43]),
.Y(n1340) );
AO22XLTS U3609 ( .A0(n2849), .A1(intDX[42]), .B0(n2857), .B1(Data_X[42]),
.Y(n1339) );
AO22XLTS U3610 ( .A0(n2855), .A1(intDX[41]), .B0(n2857), .B1(Data_X[41]),
.Y(n1338) );
BUFX3TS U3611 ( .A(n2848), .Y(n2854) );
AO22XLTS U3612 ( .A0(n2850), .A1(intDX[40]), .B0(n2854), .B1(Data_X[40]),
.Y(n1337) );
BUFX3TS U3613 ( .A(n2859), .Y(n2853) );
AO22XLTS U3614 ( .A0(n2855), .A1(intDX[39]), .B0(n1656), .B1(Data_X[39]),
.Y(n1336) );
AO22XLTS U3615 ( .A0(n2851), .A1(intDX[38]), .B0(n2852), .B1(Data_X[38]),
.Y(n1335) );
AO22XLTS U3616 ( .A0(n2849), .A1(intDX[37]), .B0(n1656), .B1(Data_X[37]),
.Y(n1334) );
AO22XLTS U3617 ( .A0(n2850), .A1(intDX[36]), .B0(n2852), .B1(Data_X[36]),
.Y(n1333) );
AO22XLTS U3618 ( .A0(n2849), .A1(intDX[35]), .B0(n1656), .B1(Data_X[35]),
.Y(n1332) );
AO22XLTS U3619 ( .A0(n2855), .A1(intDX[34]), .B0(n2859), .B1(Data_X[34]),
.Y(n1331) );
AO22XLTS U3620 ( .A0(n2850), .A1(intDX[33]), .B0(n2848), .B1(Data_X[33]),
.Y(n1330) );
AO22XLTS U3621 ( .A0(n2849), .A1(intDX[32]), .B0(n2848), .B1(Data_X[32]),
.Y(n1329) );
AO22XLTS U3622 ( .A0(n2851), .A1(intDX[31]), .B0(n2848), .B1(Data_X[31]),
.Y(n1328) );
AO22XLTS U3623 ( .A0(n2849), .A1(intDX[30]), .B0(n2848), .B1(Data_X[30]),
.Y(n1327) );
AO22XLTS U3624 ( .A0(n2855), .A1(intDX[29]), .B0(n2857), .B1(Data_X[29]),
.Y(n1326) );
AO22XLTS U3625 ( .A0(n2850), .A1(intDX[28]), .B0(n2848), .B1(Data_X[28]),
.Y(n1325) );
AO22XLTS U3626 ( .A0(n2851), .A1(intDX[27]), .B0(n2848), .B1(Data_X[27]),
.Y(n1324) );
AO22XLTS U3627 ( .A0(n2849), .A1(intDX[26]), .B0(n2856), .B1(Data_X[26]),
.Y(n1323) );
AO22XLTS U3628 ( .A0(n2855), .A1(intDX[25]), .B0(n2856), .B1(Data_X[25]),
.Y(n1322) );
AO22XLTS U3629 ( .A0(n2855), .A1(intDX[24]), .B0(n2854), .B1(Data_X[24]),
.Y(n1321) );
AO22XLTS U3630 ( .A0(n2850), .A1(intDX[23]), .B0(n2856), .B1(Data_X[23]),
.Y(n1320) );
AO22XLTS U3631 ( .A0(n2851), .A1(intDX[22]), .B0(n2857), .B1(Data_X[22]),
.Y(n1319) );
AO22XLTS U3632 ( .A0(n2849), .A1(intDX[21]), .B0(n1656), .B1(Data_X[21]),
.Y(n1318) );
AO22XLTS U3633 ( .A0(n2855), .A1(intDX[20]), .B0(n2857), .B1(Data_X[20]),
.Y(n1317) );
AO22XLTS U3634 ( .A0(n2850), .A1(intDX[19]), .B0(n1656), .B1(Data_X[19]),
.Y(n1316) );
AO22XLTS U3635 ( .A0(n2851), .A1(intDX[18]), .B0(n1656), .B1(Data_X[18]),
.Y(n1315) );
AO22XLTS U3636 ( .A0(n2849), .A1(intDX[17]), .B0(n1656), .B1(Data_X[17]),
.Y(n1314) );
AO22XLTS U3637 ( .A0(n2850), .A1(intDX[16]), .B0(n1656), .B1(Data_X[16]),
.Y(n1313) );
AO22XLTS U3638 ( .A0(n2855), .A1(intDX[15]), .B0(n2854), .B1(Data_X[15]),
.Y(n1312) );
AO22XLTS U3639 ( .A0(n2850), .A1(intDX[14]), .B0(n2854), .B1(Data_X[14]),
.Y(n1311) );
AO22XLTS U3640 ( .A0(n2851), .A1(intDX[13]), .B0(n2854), .B1(Data_X[13]),
.Y(n1310) );
AO22XLTS U3641 ( .A0(n2849), .A1(intDX[12]), .B0(n2854), .B1(Data_X[12]),
.Y(n1309) );
AO22XLTS U3642 ( .A0(n2855), .A1(intDX[11]), .B0(n2854), .B1(Data_X[11]),
.Y(n1308) );
AO22XLTS U3643 ( .A0(n2851), .A1(intDX[10]), .B0(n2854), .B1(Data_X[10]),
.Y(n1307) );
AO22XLTS U3644 ( .A0(n2849), .A1(intDX[9]), .B0(n2854), .B1(Data_X[9]), .Y(
n1306) );
AO22XLTS U3645 ( .A0(n2850), .A1(intDX[8]), .B0(n2854), .B1(Data_X[8]), .Y(
n1305) );
AO22XLTS U3646 ( .A0(n2849), .A1(intDX[7]), .B0(n2856), .B1(Data_X[7]), .Y(
n1304) );
AO22XLTS U3647 ( .A0(n2860), .A1(intDX[6]), .B0(n2852), .B1(Data_X[6]), .Y(
n1303) );
AO22XLTS U3648 ( .A0(n2851), .A1(intDX[5]), .B0(n1656), .B1(Data_X[5]), .Y(
n1302) );
AO22XLTS U3649 ( .A0(n2860), .A1(intDX[4]), .B0(n1656), .B1(Data_X[4]), .Y(
n1301) );
AO22XLTS U3650 ( .A0(n2851), .A1(intDX[3]), .B0(n1656), .B1(Data_X[3]), .Y(
n1300) );
AO22XLTS U3651 ( .A0(n2850), .A1(intDX[2]), .B0(n1656), .B1(Data_X[2]), .Y(
n1299) );
AO22XLTS U3652 ( .A0(n2860), .A1(intDX[1]), .B0(n1656), .B1(Data_X[1]), .Y(
n1298) );
AO22XLTS U3653 ( .A0(n2855), .A1(intDX[0]), .B0(n1656), .B1(Data_X[0]), .Y(
n1297) );
AO22XLTS U3654 ( .A0(n2860), .A1(intDY[62]), .B0(n1656), .B1(Data_Y[62]),
.Y(n1294) );
AO22XLTS U3655 ( .A0(n2854), .A1(Data_Y[61]), .B0(n2851), .B1(intDY[61]),
.Y(n1293) );
AO22XLTS U3656 ( .A0(n2853), .A1(Data_Y[52]), .B0(n2850), .B1(intDY[52]),
.Y(n1284) );
AO22XLTS U3657 ( .A0(n2853), .A1(Data_Y[48]), .B0(n2855), .B1(intDY[48]),
.Y(n1280) );
AO22XLTS U3658 ( .A0(n2852), .A1(Data_Y[44]), .B0(n2851), .B1(intDY[44]),
.Y(n1276) );
AO22XLTS U3659 ( .A0(n1656), .A1(Data_Y[39]), .B0(n2849), .B1(intDY[39]),
.Y(n1271) );
AO22XLTS U3660 ( .A0(n1656), .A1(Data_Y[38]), .B0(n2849), .B1(intDY[38]),
.Y(n1270) );
AO22XLTS U3661 ( .A0(n2856), .A1(Data_Y[37]), .B0(n2855), .B1(intDY[37]),
.Y(n1269) );
AO22XLTS U3662 ( .A0(n2857), .A1(Data_Y[30]), .B0(n2851), .B1(intDY[30]),
.Y(n1262) );
AO22XLTS U3663 ( .A0(n2857), .A1(Data_Y[29]), .B0(n2860), .B1(intDY[29]),
.Y(n1261) );
AO22XLTS U3664 ( .A0(n2857), .A1(Data_Y[28]), .B0(n1655), .B1(intDY[28]),
.Y(n1260) );
AO22XLTS U3665 ( .A0(n2857), .A1(Data_Y[27]), .B0(n1655), .B1(intDY[27]),
.Y(n1259) );
AO22XLTS U3666 ( .A0(n2858), .A1(Data_Y[26]), .B0(n2847), .B1(intDY[26]),
.Y(n1258) );
AO22XLTS U3667 ( .A0(n2858), .A1(Data_Y[25]), .B0(n2847), .B1(intDY[25]),
.Y(n1257) );
AO22XLTS U3668 ( .A0(n2858), .A1(Data_Y[24]), .B0(n2847), .B1(intDY[24]),
.Y(n1256) );
AO22XLTS U3669 ( .A0(n2856), .A1(Data_Y[23]), .B0(n1655), .B1(intDY[23]),
.Y(n1255) );
AO22XLTS U3670 ( .A0(n2856), .A1(Data_Y[22]), .B0(n2850), .B1(intDY[22]),
.Y(n1254) );
AO22XLTS U3671 ( .A0(n2856), .A1(Data_Y[21]), .B0(n2860), .B1(intDY[21]),
.Y(n1253) );
AO22XLTS U3672 ( .A0(n2856), .A1(Data_Y[20]), .B0(n2847), .B1(intDY[20]),
.Y(n1252) );
AO22XLTS U3673 ( .A0(n2856), .A1(Data_Y[19]), .B0(n2850), .B1(intDY[19]),
.Y(n1251) );
AO22XLTS U3674 ( .A0(n2856), .A1(Data_Y[18]), .B0(n2860), .B1(intDY[18]),
.Y(n1250) );
AO22XLTS U3675 ( .A0(n2856), .A1(Data_Y[17]), .B0(n2851), .B1(intDY[17]),
.Y(n1249) );
AO22XLTS U3676 ( .A0(n2856), .A1(Data_Y[16]), .B0(n2860), .B1(intDY[16]),
.Y(n1248) );
AO22XLTS U3677 ( .A0(n2856), .A1(Data_Y[15]), .B0(n2849), .B1(intDY[15]),
.Y(n1247) );
AO22XLTS U3678 ( .A0(n2856), .A1(Data_Y[14]), .B0(n2860), .B1(intDY[14]),
.Y(n1246) );
AO22XLTS U3679 ( .A0(n2857), .A1(Data_Y[13]), .B0(n2850), .B1(intDY[13]),
.Y(n1245) );
AO22XLTS U3680 ( .A0(n2857), .A1(Data_Y[12]), .B0(n2860), .B1(intDY[12]),
.Y(n1244) );
AO22XLTS U3681 ( .A0(n2858), .A1(Data_Y[11]), .B0(n2855), .B1(intDY[11]),
.Y(n1243) );
AO22XLTS U3682 ( .A0(n2858), .A1(Data_Y[10]), .B0(n2860), .B1(intDY[10]),
.Y(n1242) );
AO22XLTS U3683 ( .A0(n2858), .A1(Data_Y[9]), .B0(n2849), .B1(intDY[9]), .Y(
n1241) );
AO22XLTS U3684 ( .A0(n2858), .A1(Data_Y[8]), .B0(n2860), .B1(intDY[8]), .Y(
n1240) );
AO22XLTS U3685 ( .A0(n2858), .A1(Data_Y[7]), .B0(n2849), .B1(intDY[7]), .Y(
n1239) );
AO22XLTS U3686 ( .A0(n2858), .A1(Data_Y[6]), .B0(n2860), .B1(intDY[6]), .Y(
n1238) );
AO22XLTS U3687 ( .A0(n2858), .A1(Data_Y[5]), .B0(n2850), .B1(intDY[5]), .Y(
n1237) );
AO22XLTS U3688 ( .A0(n2858), .A1(Data_Y[4]), .B0(n2860), .B1(intDY[4]), .Y(
n1236) );
AO22XLTS U3689 ( .A0(n2859), .A1(Data_Y[3]), .B0(n1655), .B1(intDY[3]), .Y(
n1235) );
AO22XLTS U3690 ( .A0(n2854), .A1(Data_Y[2]), .B0(n2855), .B1(intDY[2]), .Y(
n1234) );
AO22XLTS U3691 ( .A0(n2859), .A1(Data_Y[1]), .B0(n2849), .B1(intDY[1]), .Y(
n1233) );
NOR2XLTS U3692 ( .A(n2864), .B(n2861), .Y(n2862) );
OAI22X1TS U3693 ( .A0(n2864), .A1(n2863), .B0(n2862), .B1(intDX[63]), .Y(
n2867) );
AOI22X1TS U3694 ( .A0(n2868), .A1(n2867), .B0(n2866), .B1(n2238), .Y(n1167)
);
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk40.tcl_syn.sdf");
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : xilinx_pcie_2_1_rport_7x.v
// Version : 1.11
//
//--------------------------------------------------------------------------------
`timescale 1ns / 1ps
`include "board_common.v"
module xilinx_pcie_2_1_rport_7x # (
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter PCIE_EXT_CLK = "TRUE", // Use External Clocking Module
parameter PL_FAST_TRAIN = "FALSE",
parameter ALLOW_X8_GEN2 = "FALSE",
parameter C_DATA_WIDTH = 64,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter DEVICE_ID = 16'h506F,
parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h1,
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 1,
parameter USER_CLK_FREQ = 3,
parameter USER_CLK2_DIV2 = "FALSE",
parameter TRN_DW = "FALSE",
parameter VC0_TX_LASTPACKET = 28,
parameter VC0_RX_RAM_LIMIT = 13'h03ff,
parameter VC0_CPL_INFINITE = "TRUE",
parameter VC0_TOTAL_CREDITS_PD = 154,
parameter VC0_TOTAL_CREDITS_CD = 154
)
(
input sys_clk,
input sys_rst_n,
input [3:0] pci_exp_rxn, pci_exp_rxp,
output [3:0] pci_exp_txn, pci_exp_txp
);
// Local Wires
// Common
wire trn_clk;
wire user_reset_out;
wire trn_reset_n;
wire trn_lnk_up;
// Tx
wire [C_DATA_WIDTH-1:0] trn_td;
wire [REM_WIDTH-1:0] trn_trem_n;
wire trn_tsof_n;
wire trn_teof_n;
wire trn_tsrc_rdy_n;
wire trn_tdst_rdy;
wire trn_tsrc_dsc_n;
wire trn_terrfwd_n;
wire trn_tdst_dsc;
wire [5:0] trn_tbuf_av;
// Rx
wire [C_DATA_WIDTH-1:0] trn_rd;
wire [REM_WIDTH-1:0] trn_rrem;
wire trn_rsof;
wire trn_reof;
wire trn_rsrc_rdy;
wire trn_rsrc_dsc;
wire trn_rdst_rdy_n;
wire trn_rerrfwd;
wire trn_rnp_ok_n;
wire [6:0] trn_rbar_hit;
wire [7:0] trn_rfc_nph_av;
wire [11:0] trn_rfc_npd_av;
wire [7:0] trn_rfc_ph_av;
wire [11:0] trn_rfc_pd_av;
wire [7:0] trn_rfc_cplh_av;
wire [11:0] trn_rfc_cpld_av;
wire [31:0] cfg_do;
wire [31:0] cfg_di;
wire [3:0] cfg_byte_en_n;
wire [9:0] cfg_dwaddr;
wire [47:0] cfg_err_tlp_cpl_header;
wire cfg_wr_en_n;
wire cfg_rd_wr_done;
wire cfg_rd_en_n;
wire cfg_err_cor_n;
wire cfg_err_ur_n;
wire cfg_err_ecrc_n;
wire cfg_err_cpl_timeout_n;
wire cfg_err_cpl_abort_n;
wire cfg_err_cpl_unexpect_n;
wire cfg_err_posted_n;
wire cfg_interrupt_n;
wire cfg_interrupt_rdy;
wire [15:0] cfg_status;
wire [15:0] cfg_command;
wire [15:0] cfg_dstatus;
wire [15:0] cfg_dcommand;
wire [15:0] cfg_lstatus;
wire [15:0] cfg_lcommand;
wire cfg_rdy_n;
wire [2:0] cfg_pcie_link_state;
wire cfg_trn_pending_n;
wire [2:0] pl_initial_link_width;
wire [1:0] pl_lane_reversal_mode;
wire pl_link_gen2_capable;
wire pl_link_partner_gen2_supported;
wire pl_link_upcfg_capable;
wire [5:0] pl_ltssm_state;
wire pl_sel_link_rate;
wire [1:0] pl_sel_link_width;
wire pl_directed_link_auton;
wire [1:0] pl_directed_link_change;
wire pl_directed_link_speed;
wire [1:0] pl_directed_link_width;
wire pl_upstream_prefer_deemph;
wire speed_change_done_n;
wire trn_tstr;
wire trn_tecrc_gen;
wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata;
wire s_axis_tx_tvalid;
wire s_axis_tx_tready;
wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire [3:0] s_axis_tx_tuser;
wire [C_DATA_WIDTH-1:0] m_axis_rx_tdata;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [KEEP_WIDTH-1:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire [21:0] m_axis_rx_tuser;
// Wires used for external clocking connectivity
wire PIPE_PCLK_IN;
wire PIPE_RXUSRCLK_IN;
wire [3:0] PIPE_RXOUTCLK_IN;
wire PIPE_DCLK_IN;
wire PIPE_USERCLK1_IN;
wire PIPE_USERCLK2_IN;
wire PIPE_MMCM_LOCK_IN;
wire PIPE_TXOUTCLK_OUT;
wire [3:0] PIPE_RXOUTCLK_OUT;
wire [3:0] PIPE_PCLK_SEL_OUT;
wire PIPE_GEN3_OUT;
wire PIPE_OOBCLK_IN;
assign trn_reset_n = !user_reset_out;
// Generate External Clock Module if External Clocking is selected
generate
if (PCIE_EXT_CLK == "TRUE") begin : ext_clk
localparam USER_CLK_FREQ = USER_CLK_FREQ;
localparam USER_CLK2_DIV2 = USER_CLK2_DIV2;
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ? (USER_CLK_FREQ == 4) ? 3 : (USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ
: USER_CLK_FREQ;
//---------- PIPE Clock Module -------------------------------------------------
pcieCore_pipe_clock #
(
.PCIE_ASYNC_EN ("FALSE"), // PCIe async enable
.PCIE_TXBUF_EN ("FALSE"), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (6'h04), // PCIe number of lanes
.PCIE_LINK_SPEED ( 2 ),
.PCIE_REFCLK_FREQ (0), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ (USER_CLK_FREQ +1), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ (USERCLK2_FREQ +1), // PCIe user clock 2 frequency
.PCIE_DEBUG_MODE ( 0 )
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK ( sys_clk) ,
.CLK_TXOUTCLK ( PIPE_TXOUTCLK_OUT ), // Reference clock from lane 0
.CLK_RXOUTCLK_IN ( PIPE_RXOUTCLK_OUT ),
.CLK_RST_N ( 1'b1 ),
.CLK_PCLK_SEL ( PIPE_PCLK_SEL_OUT ),
.CLK_GEN3 ( PIPE_GEN3_OUT ),
//---------- Output ------------------------------------
.CLK_PCLK ( PIPE_PCLK_IN ),
.CLK_RXUSRCLK ( PIPE_RXUSRCLK_IN ),
.CLK_RXOUTCLK_OUT ( PIPE_RXOUTCLK_IN ),
.CLK_DCLK ( PIPE_DCLK_IN ),
.CLK_USERCLK1 ( PIPE_USERCLK1_IN ),
.CLK_USERCLK2 ( PIPE_USERCLK2_IN ),
.CLK_OOBCLK ( PIPE_OOBCLK_IN ),
.CLK_MMCM_LOCK ( PIPE_MMCM_LOCK_IN )
);
end
endgenerate
// PCI-Express FPGA Endpoint Instance
pcie_2_1_rport_7x # (
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.TRN_DW ( TRN_DW ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD )
) rport (
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_rxp ( pci_exp_rxp ),
.pci_exp_rxn ( pci_exp_rxn ),
//----------------------------------------------------------------------------------------------------------------//
// 2. Clocking Interface - For Partial Reconfig Support //
//----------------------------------------------------------------------------------------------------------------//
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
.user_clk_out ( trn_clk ),
.user_reset_out ( user_reset_out ),
.user_lnk_up ( trn_lnk_up ),
// Tx
.tx_buf_av ( trn_tbuf_av ),
.tx_cfg_req ( ),
.tx_err_drop ( trn_tdst_dsc ),
.tx_cfg_gnt ( 1'b1 ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( ~trn_rnp_ok_n ),
.rx_np_req ( 1'b0 ),
.fc_cpld ( ),
.fc_cplh ( ),
.fc_npd ( ),
.fc_nph ( ),
.fc_pd ( ),
.fc_ph ( ),
.fc_sel ( 3'b0 ),
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( ),
.cfg_pmcsr_pme_status ( ),
.cfg_pmcsr_powerstate ( ),
.cfg_received_func_lvl_rst ( ),
.cfg_mgmt_do ( cfg_do ),
.cfg_mgmt_rd_wr_done ( cfg_rd_wr_done ),
.cfg_mgmt_di ( cfg_di ),
.cfg_mgmt_byte_en ( ~cfg_byte_en_n ),
.cfg_mgmt_dwaddr ( cfg_dwaddr ),
.cfg_mgmt_wr_en ( ~cfg_wr_en_n ),
.cfg_mgmt_rd_en ( ~cfg_rd_en_n ),
.cfg_mgmt_wr_readonly ( 1'b0 ),
.cfg_err_ecrc ( ~cfg_err_ecrc_n ),
.cfg_err_ur ( ~cfg_err_ur_n ),
.cfg_err_cpl_timeout ( ~cfg_err_cpl_timeout_n ),
.cfg_err_cpl_unexpect ( ~cfg_err_cpl_unexpect_n ),
.cfg_err_cpl_abort ( ~cfg_err_cpl_abort_n ),
.cfg_err_posted ( ~cfg_err_posted_n ),
.cfg_err_cor ( ~cfg_err_cor_n ),
.cfg_err_atomic_egress_blocked ( 1'b0 ),
.cfg_err_internal_cor ( 1'b0 ),
.cfg_err_malformed ( 1'b0 ),
.cfg_err_mc_blocked ( 1'b0 ),
.cfg_err_poisoned ( 1'b0 ),
.cfg_err_norecovery ( 1'b0 ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy ( ),
.cfg_err_locked ( 1'b0 ),
.cfg_err_acs ( 1'b0 ),
.cfg_err_internal_uncor ( 1'b0 ),
.cfg_trn_pending ( ~cfg_trn_pending_n ),
.cfg_pm_halt_aspm_l0s ( 1'b0 ),
.cfg_pm_halt_aspm_l1 ( 1'b0 ),
.cfg_pm_force_state_en ( 1'b0 ),
.cfg_pm_force_state ( 2'b00 ),
.cfg_dsn ( 64'h0 ),
.cfg_msg_received ( ),
.cfg_msg_data ( ),
.cfg_interrupt ( 1'b0 ),
.cfg_interrupt_rdy ( ),
.cfg_interrupt_assert ( 1'b0 ),
.cfg_interrupt_di ( 8'h0 ),
.cfg_interrupt_do ( ),
.cfg_interrupt_mmenable ( ),
.cfg_interrupt_msienable ( ),
.cfg_interrupt_msixenable ( ),
.cfg_interrupt_msixfm ( ),
.cfg_interrupt_stat ( 1'b0 ),
.cfg_pciecap_interrupt_msgnum ( 5'h00 ),
.cfg_to_turnoff ( ),
.cfg_turnoff_ok ( 1'b0 ),
.cfg_bus_number ( ),
.cfg_device_number ( ),
.cfg_function_number ( ),
.cfg_pm_wake ( 1'b0 ),
.cfg_msg_received_pm_as_nak ( ),
.cfg_msg_received_setslotpowerlimit ( ),
.cfg_pm_send_pme_to ( 1'b0 ),
.cfg_ds_bus_number ( 8'h0 ),
.cfg_ds_device_number ( 5'h0 ),
.cfg_ds_function_number ( 3'b000 ),
.cfg_mgmt_wr_rw1c_as_rw ( 1'b0 ),
.cfg_bridge_serr_en ( ),
.cfg_slot_control_electromech_il_ctl_pulse ( ),
.cfg_root_control_syserr_corr_err_en ( ),
.cfg_root_control_syserr_non_fatal_err_en ( ),
.cfg_root_control_syserr_fatal_err_en ( ),
.cfg_root_control_pme_int_en ( ),
.cfg_aer_rooterr_corr_err_reporting_en ( ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_corr_err_received ( ),
.cfg_aer_rooterr_non_fatal_err_received ( ),
.cfg_aer_rooterr_fatal_err_received ( ),
.cfg_msg_received_err_cor ( ),
.cfg_msg_received_err_non_fatal ( ),
.cfg_msg_received_err_fatal ( ),
.cfg_msg_received_pm_pme ( ),
.cfg_msg_received_pme_to_ack ( ),
.cfg_msg_received_assert_int_a ( ),
.cfg_msg_received_assert_int_b ( ),
.cfg_msg_received_assert_int_c ( ),
.cfg_msg_received_assert_int_d ( ),
.cfg_msg_received_deassert_int_a ( ),
.cfg_msg_received_deassert_int_b ( ),
.cfg_msg_received_deassert_int_c ( ),
.cfg_msg_received_deassert_int_d ( ),
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_sel_lnk_rate ( pl_sel_link_rate ),
.pl_sel_lnk_width ( pl_sel_link_width ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_phy_lnk_up ( ),
.pl_tx_pm_state ( ),
.pl_rx_pm_state ( ),
.pl_link_upcfg_cap ( pl_link_upcfg_capable ),
.pl_link_gen2_cap ( pl_link_gen2_capable ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_directed_change_done ( ),
.pl_received_hot_rst ( ),
.pl_downstream_deemph_source ( 1'b0 ),
.pl_transmit_hot_rst ( 1'b0 ),
//----------------------------------------------------------------------------------------------------------------//
// 6. AER Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_aer_headerlog ( 128'b0 ),
.cfg_aer_interrupt_msgnum ( 5'b0 ),
.cfg_err_aer_headerlog_set ( ),
.cfg_aer_ecrc_check_en ( ),
.cfg_aer_ecrc_gen_en ( ),
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_vc_tcvc_map ( ),
.PIPE_MMCM_RST_N ( 1'b1 ), // Async | Async
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n )
);
// User Application Instances
// Rx User Application Interface
pci_exp_usrapp_rx # (
.C_DATA_WIDTH( C_DATA_WIDTH)
) rx_usrapp (
.trn_clk (trn_clk),
.trn_reset_n (trn_reset_n),
.trn_lnk_up_n (~trn_lnk_up),
.trn_rd(trn_rd),
.trn_rrem_n ( ~trn_rrem ),
.trn_rsof_n ( ~trn_rsof ),
.trn_reof_n ( ~trn_reof ),
.trn_rsrc_rdy_n ( ~trn_rsrc_rdy ),
.trn_rsrc_dsc_n ( ~trn_rsrc_dsc ),
.trn_rdst_rdy_n ( trn_rdst_rdy_n ),
.trn_rerrfwd_n ( ~trn_rerrfwd ),
.trn_rnp_ok_n ( trn_rnp_ok_n ),
.trn_rbar_hit_n ( ~trn_rbar_hit )
);
// Tx User Application Interface
pci_exp_usrapp_tx # (
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED )
) tx_usrapp (
.trn_clk ( trn_clk ),
.trn_reset_n ( trn_reset_n ),
.trn_lnk_up_n ( ~trn_lnk_up ),
.trn_td ( trn_td ),
.trn_trem_n ( trn_trem_n ),
.trn_tsof_n ( trn_tsof_n ),
.trn_teof_n ( trn_teof_n ),
.trn_terrfwd_n ( trn_terrfwd_n ),
.trn_tsrc_rdy_n ( trn_tsrc_rdy_n ),
.trn_tdst_rdy_n ( ~trn_tdst_rdy ),
.trn_tsrc_dsc_n ( trn_tsrc_dsc_n ),
.trn_tdst_dsc_n ( ~trn_tdst_dsc ),
.trn_tbuf_av ( trn_tbuf_av ),
.speed_change_done_n ( speed_change_done_n )
);
// Cfg UsrApp
pci_exp_usrapp_cfg cfg_usrapp (
.trn_clk ( trn_clk ),
.trn_reset_n ( trn_reset_n ),
.cfg_do ( cfg_do ),
.cfg_di ( cfg_di ),
.cfg_byte_en_n ( cfg_byte_en_n ),
.cfg_dwaddr ( cfg_dwaddr ),
.cfg_wr_en_n ( cfg_wr_en_n ),
.cfg_rd_en_n ( cfg_rd_en_n ),
.cfg_rd_wr_done_n ( ~cfg_rd_wr_done ),
.cfg_err_cor_n ( cfg_err_cor_n ),
.cfg_err_ur_n ( cfg_err_ur_n ),
.cfg_err_ecrc_n ( cfg_err_ecrc_n ),
.cfg_err_cpl_timeout_n ( cfg_err_cpl_timeout_n ),
.cfg_err_cpl_abort_n ( cfg_err_cpl_abort_n ),
.cfg_err_cpl_unexpect_n ( cfg_err_cpl_unexpect_n ),
.cfg_err_posted_n ( cfg_err_posted_n ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_interrupt_n ( cfg_interrupt_n ),
.cfg_interrupt_rdy_n ( ~cfg_interrupt_rdy ),
.cfg_turnoff_ok_n ( ),
.cfg_pm_wake_n ( ),
.cfg_to_turnoff_n ( 1'b1 ),
.cfg_bus_number ( 8'h0 ),
.cfg_device_number ( 5'h0 ),
.cfg_function_number ( 3'h0 ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_pcie_link_state_n ( ~cfg_pcie_link_state ),
.cfg_trn_pending_n ( cfg_trn_pending_n )
);
// Common UsrApp
pci_exp_usrapp_com com_usrapp ();
// PL UsrApp
pci_exp_usrapp_pl # (
.LINK_CAP_MAX_LINK_SPEED (LINK_CAP_MAX_LINK_SPEED)
) pl_usrapp (
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_capable ( pl_link_gen2_capable ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_capable ( pl_link_upcfg_capable ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_received_hot_rst ( 1'b0 ),
.pl_sel_link_rate ( pl_sel_link_rate ),
.pl_sel_link_width ( pl_sel_link_width ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.speed_change_done_n ( speed_change_done_n),
.trn_lnk_up_n ( ~trn_lnk_up ),
.trn_clk ( trn_clk ),
.trn_reset_n ( trn_reset_n )
);
//-------------------------------------------------------------------------------------------------//
// PCIe AXI TRN Bridge //
//-------------------------------------------------------------------------------------------------//
pcie_axi_trn_bridge #(
.C_DATA_WIDTH ( C_DATA_WIDTH )
) pcie_axi_trn_bridge_i (
.user_clk ( trn_clk ),
.user_reset ( ~trn_reset_n ),
.user_lnk_up ( trn_lnk_up ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.trn_td ( trn_td ),
.trn_tsof ( ~trn_tsof_n ),
.trn_teof ( ~trn_teof_n ),
.trn_tsrc_rdy ( ~trn_tsrc_rdy_n ),
.trn_tdst_rdy ( trn_tdst_rdy ),
.trn_tsrc_dsc ( ~trn_tsrc_dsc_n ),
.trn_trem ( ~trn_trem_n ),
.trn_terrfwd ( ~trn_terrfwd_n ),
.trn_tstr ( 1'b0 ),
.trn_tecrc_gen ( 1'b0 ),
.trn_rd ( trn_rd ),
.trn_rsof ( trn_rsof ),
.trn_reof ( trn_reof ),
.trn_rsrc_rdy ( trn_rsrc_rdy ),
.trn_rdst_rdy ( ~trn_rdst_rdy_n ),
.trn_rsrc_dsc ( trn_rsrc_dsc ),
.trn_rrem ( trn_rrem ),
.trn_rerrfwd ( trn_rerrfwd ),
.trn_rbar_hit ( trn_rbar_hit )
);
endmodule
|
module MAX6682Mean (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output reg CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output MAX6682CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output [7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="PauseCounterPreset_i", intersynth_conntype="Word" *)
input[15:0] PauseCounterPreset_i,
(* intersynth_param="PeriodCounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_param="PeriodCounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b0;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b0;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
assign SPI_Data_o = 8'b00000000;
reg SPI_FSM_Start;
wire SPI_FSM_Done;
wire [7:0] Byte0;
wire [7:0] Byte1;
SPI_FSM SPI_FSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.SPI_FSM_Start (SPI_FSM_Start),
.SPI_Transmission_i (SPI_Transmission_i),
.MAX6682CS_n_o (MAX6682CS_n_o),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_FSM_Done (SPI_FSM_Done),
.SPI_Data_i (SPI_Data_i),
.Byte0 (Byte0),
.Byte1 (Byte1)
);
/////////////////////////////////////////////////////////////////////////////
// SensorFSM ////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Sensor FSM
localparam stDisabled = 4'd0;
localparam stIdle = 4'd1;
localparam stSPI_Xfer1 = 4'd2;
localparam stSPI_Pause1 = 4'd3;
localparam stSPI_Xfer2 = 4'd4;
localparam stSPI_Pause2 = 4'd5;
localparam stSPI_Xfer3 = 4'd6;
localparam stSPI_Pause3 = 4'd7;
localparam stSPI_Xfer4 = 4'd8;
localparam stCompare = 4'd9;
reg [3:0] SensorFSM_State;
reg [3:0] SensorFSM_NextState;
reg PauseTimerPreset;
reg PauseTimerEnable;
wire PauseTimerOvfl;
wire SensorFSM_TimerOvfl;
reg SensorFSM_TimerPreset;
reg SensorFSM_TimerEnable;
wire SensorFSM_DiffTooLarge;
reg SensorFSM_StoreValue; // store value received from sensor to accumulator
reg SensorFSM_AddValue; // add value received from sensor to accumulator
reg SensorFSM_StoreNewValue; // store accumulator as new value
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_State <= stDisabled;
end
else
begin // rising clock edge
// state register
SensorFSM_State <= SensorFSM_NextState;
end
end
always @(SensorFSM_State, Enable_i, SensorFSM_TimerOvfl, SPI_FSM_Done, PauseTimerOvfl, SensorFSM_DiffTooLarge)
begin // process SensorFSM_CombProc
SensorFSM_NextState = SensorFSM_State;
// control signal default values
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0;
PauseTimerPreset = 1'b1;
PauseTimerEnable = 1'b0;
SPI_FSM_Start = 1'b0;
SensorFSM_StoreValue = 1'b0;
SensorFSM_AddValue = 1'b0;
SensorFSM_StoreNewValue = 1'b0;
CpuIntr_o = 1'b0;
// next state and output logic
case (SensorFSM_State)
stDisabled: begin
if (Enable_i == 1'b1)
begin
SensorFSM_NextState = stIdle;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // start timer
end
end
stIdle: begin
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
else
if (SensorFSM_TimerOvfl == 1'b1)
begin
SensorFSM_NextState = stSPI_Xfer1;
SPI_FSM_Start = 1'b1;
end
end
stSPI_Xfer1: begin
if (SPI_FSM_Done == 1'b1)
begin
SensorFSM_NextState = stSPI_Pause1;
SensorFSM_StoreValue = 1'b1; // store value
PauseTimerPreset = 1'b0;
PauseTimerEnable = 1'b1;
end
end
stSPI_Pause1: begin
PauseTimerPreset = 1'b0;
PauseTimerEnable = 1'b1;
if (PauseTimerOvfl == 1'b1)
begin
SensorFSM_NextState = stSPI_Xfer2;
SPI_FSM_Start = 1'b1;
end
end
stSPI_Xfer2: begin
if (SPI_FSM_Done == 1'b1)
begin
SensorFSM_NextState = stSPI_Pause2;
SensorFSM_AddValue = 1'b1; // add value
PauseTimerPreset = 1'b0;
PauseTimerEnable = 1'b1;
end
end
stSPI_Pause2: begin
PauseTimerPreset = 1'b0;
PauseTimerEnable = 1'b1;
if (PauseTimerOvfl == 1'b1)
begin
SensorFSM_NextState = stSPI_Xfer3;
SPI_FSM_Start = 1'b1;
end
end
stSPI_Xfer3: begin
if (SPI_FSM_Done == 1'b1)
begin
SensorFSM_NextState = stSPI_Pause3;
SensorFSM_AddValue = 1'b1; // add value
PauseTimerPreset = 1'b0;
PauseTimerEnable = 1'b1;
end
end
stSPI_Pause3: begin
PauseTimerPreset = 1'b0;
PauseTimerEnable = 1'b1;
if (PauseTimerOvfl == 1'b1)
begin
SensorFSM_NextState = stSPI_Xfer4;
SPI_FSM_Start = 1'b1;
end
end
stSPI_Xfer4: begin
if (SPI_FSM_Done == 1'b1)
begin
SensorFSM_NextState = stCompare;
SensorFSM_AddValue = 1'b1; // add value
end
end
stCompare: begin
SensorFSM_NextState = stIdle;
if (SensorFSM_DiffTooLarge == 1'b1)
begin
SensorFSM_StoreNewValue = 1'b1; // store new value
CpuIntr_o = 1'b1; // notify CPU
end
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Pause Timer //////////////////////////////////////////////////////////////
reg [15:0] PauseTimer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
PauseTimer <= 16'd0;
end
else
begin
if (PauseTimerPreset)
begin
PauseTimer <= PauseCounterPreset_i;
end
else if (PauseTimerEnable)
begin
PauseTimer <= PauseTimer - 1'd1;
end
end
end
assign PauseTimerOvfl = (PauseTimer == 0) ? 1'b1 : 1'b0;
// Periode Timer ////////////////////////////////////////////////////////////
reg [31:0] SensorFSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_Timer <= 32'd0;
end
else
begin
if (SensorFSM_TimerPreset)
begin
SensorFSM_Timer <= {PeriodCounterPresetH_i, PeriodCounterPresetL_i};
end
else if (SensorFSM_TimerEnable)
begin
SensorFSM_Timer <= SensorFSM_Timer - 1'd1;
end
end
end
assign SensorFSM_TimerOvfl = (SensorFSM_Timer == 0) ? 1'b1 : 1'b0;
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic
// interconnecting signals
wire [15:0] SensorValue;
reg [15:0] Accumulator;
reg [15:0] LastValue;
wire [15:0] AbsDiffResult;
assign SensorValue = { 5'b00000, Byte1, Byte0[7:5] };
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Accumulator <= 16'd0;
LastValue <= 16'd0;
end
else
begin
// accumulate measurements
if (SensorFSM_StoreValue)
begin
Accumulator <= SensorValue;
end
else if (SensorFSM_AddValue)
begin
Accumulator <= Accumulator + SensorValue;
end
// store accumulated sum
if (SensorFSM_StoreNewValue)
begin
LastValue <= Accumulator;
end
end
end
wire [16:0] DiffAB;
wire [15:0] DiffBA;
assign DiffAB = {1'b0, LastValue} - {1'b0, Accumulator};
assign DiffBA = Accumulator - LastValue;
assign AbsDiffResult = DiffAB[16] ? DiffBA : DiffAB[15:0];
assign SensorFSM_DiffTooLarge = (AbsDiffResult > Threshold_i) ? 1'b1 : 1'b0;
assign SensorValue_o = LastValue;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: flop_rptrs_xc3.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module flop_rptrs_xc3(/*AUTOARG*/
// Outputs
sparc_out, so, jbussync2_out, jbussync1_out, grst_out,
gdbginit_out, ddrsync2_out, ddrsync1_out, cken_out,
// Inputs
spare_in, se, sd, jbussync2_in, jbussync1_in, grst_in,
gdbginit_in, gclk, ddrsync2_in, ddrsync1_in, cken_in, agrst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [25:0] cken_out; // From cken_ff_25_ of bw_u1_soffasr_2x.v, ...
output ddrsync1_out; // From ddrsync1_ff of bw_u1_soffasr_2x.v
output ddrsync2_out; // From ddrsync2_ff of bw_u1_soffasr_2x.v
output gdbginit_out; // From gdbginit_ff of bw_u1_soffasr_2x.v
output grst_out; // From gclk_ff of bw_u1_soffasr_2x.v
output jbussync1_out; // From jbussync1_ff of bw_u1_soffasr_2x.v
output jbussync2_out; // From jbussync2_ff of bw_u1_soffasr_2x.v
output so; // From scanout_latch of bw_u1_scanlg_2x.v
output [5:0] sparc_out; // From spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To gdbginit_ff of bw_u1_soffasr_2x.v
input agrst_l; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [25:0] cken_in; // To cken_ff_25_ of bw_u1_soffasr_2x.v, ...
input ddrsync1_in; // To ddrsync1_ff of bw_u1_soffasr_2x.v
input ddrsync2_in; // To ddrsync2_ff of bw_u1_soffasr_2x.v
input gclk; // To I73 of bw_u1_ckbuf_33x.v
input gdbginit_in; // To gdbginit_ff of bw_u1_soffasr_2x.v
input grst_in; // To gclk_ff of bw_u1_soffasr_2x.v
input jbussync1_in; // To jbussync1_ff of bw_u1_soffasr_2x.v
input jbussync2_in; // To jbussync2_ff of bw_u1_soffasr_2x.v
input sd; // To spare_ff_5_ of bw_u1_soffasr_2x.v
input se; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [5:0] spare_in; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clk; // From I73 of bw_u1_ckbuf_33x.v
wire scan_data_0; // From spare_ff_5_ of bw_u1_soffasr_2x.v
wire scan_data_1; // From spare_ff_4_ of bw_u1_soffasr_2x.v
wire scan_data_10; // From gdbginit_ff of bw_u1_soffasr_2x.v
wire scan_data_11; // From gclk_ff of bw_u1_soffasr_2x.v
wire scan_data_2; // From spare_ff_3_ of bw_u1_soffasr_2x.v
wire scan_data_3; // From spare_ff_2_ of bw_u1_soffasr_2x.v
wire scan_data_4; // From spare_ff_1_ of bw_u1_soffasr_2x.v
wire scan_data_5; // From spare_ff_0_ of bw_u1_soffasr_2x.v
wire scan_data_6; // From jbussync2_ff of bw_u1_soffasr_2x.v
wire scan_data_7; // From jbussync1_ff of bw_u1_soffasr_2x.v
wire scan_data_8; // From ddrsync2_ff of bw_u1_soffasr_2x.v
wire scan_data_9; // From ddrsync1_ff of bw_u1_soffasr_2x.v
// End of automatics
/* bw_u1_ckbuf_33x AUTO_TEMPLATE (
.clk (clk ),
.rclk (gclk ) ); */
bw_u1_ckbuf_33x I73
(/*AUTOINST*/
// Outputs
.clk (clk ), // Templated
// Inputs
.rclk (gclk )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (sparc_out[@]),
.d (spare_in[@]),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.sd (scan_data_@"(- 4 @)" ),
.so (scan_data_@"(- 5 @)" ),
); */
bw_u1_soffasr_2x spare_ff_5_
(
// Inputs
.sd (sd ),
/*AUTOINST*/
// Outputs
.q (sparc_out[5]), // Templated
.so (scan_data_0 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[5]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se));
bw_u1_soffasr_2x spare_ff_4_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[4]), // Templated
.so (scan_data_1 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[4]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_0 )); // Templated
bw_u1_soffasr_2x spare_ff_3_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[3]), // Templated
.so (scan_data_2 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[3]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_1 )); // Templated
bw_u1_soffasr_2x spare_ff_2_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[2]), // Templated
.so (scan_data_3 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[2]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_2 )); // Templated
bw_u1_soffasr_2x spare_ff_1_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[1]), // Templated
.so (scan_data_4 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[1]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_3 )); // Templated
bw_u1_soffasr_2x spare_ff_0_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[0]), // Templated
.so (scan_data_5 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[0]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_4 )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (cken_out[@] ),
.d (cken_in[@] ),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (1'b0),
.sd (1'b0),
.so (),
); */
bw_u1_soffasr_2x cken_ff_25_
( /*AUTOINST*/
// Outputs
.q (cken_out[25] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[25] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_24_
( /*AUTOINST*/
// Outputs
.q (cken_out[24] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[24] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_23_
( /*AUTOINST*/
// Outputs
.q (cken_out[23] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[23] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_22_
( /*AUTOINST*/
// Outputs
.q (cken_out[22] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[22] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_21_
( /*AUTOINST*/
// Outputs
.q (cken_out[21] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[21] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_20_
( /*AUTOINST*/
// Outputs
.q (cken_out[20] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[20] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_19_
( /*AUTOINST*/
// Outputs
.q (cken_out[19] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[19] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_18_
( /*AUTOINST*/
// Outputs
.q (cken_out[18] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[18] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_17_
( /*AUTOINST*/
// Outputs
.q (cken_out[17] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[17] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_16_
( /*AUTOINST*/
// Outputs
.q (cken_out[16] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[16] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_15_
( /*AUTOINST*/
// Outputs
.q (cken_out[15] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[15] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_14_
( /*AUTOINST*/
// Outputs
.q (cken_out[14] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[14] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_13_
( /*AUTOINST*/
// Outputs
.q (cken_out[13] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[13] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_12_
( /*AUTOINST*/
// Outputs
.q (cken_out[12] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[12] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_11_
( /*AUTOINST*/
// Outputs
.q (cken_out[11] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[11] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_10_
( /*AUTOINST*/
// Outputs
.q (cken_out[10] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[10] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_9_
( /*AUTOINST*/
// Outputs
.q (cken_out[9] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[9] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_8_
( /*AUTOINST*/
// Outputs
.q (cken_out[8] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[8] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_7_
( /*AUTOINST*/
// Outputs
.q (cken_out[7] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[7] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_6_
( /*AUTOINST*/
// Outputs
.q (cken_out[6] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[6] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_5_
( /*AUTOINST*/
// Outputs
.q (cken_out[5] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[5] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_4_
( /*AUTOINST*/
// Outputs
.q (cken_out[4] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[4] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_3_
( /*AUTOINST*/
// Outputs
.q (cken_out[3] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[3] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_2_
( /*AUTOINST*/
// Outputs
.q (cken_out[2] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[2] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_1_
( /*AUTOINST*/
// Outputs
.q (cken_out[1] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[1] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_0_
( /*AUTOINST*/
// Outputs
.q (cken_out[0] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[0] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (se ),
); */
bw_u1_soffasr_2x ddrsync1_ff
(
// Outputs
.q (ddrsync1_out ),
.so (scan_data_9 ),
// Inputs
.d (ddrsync1_in ),
.sd (scan_data_8 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x ddrsync2_ff
(
// Outputs
.q (ddrsync2_out ),
.so (scan_data_8 ),
// Inputs
.d (ddrsync2_in ),
.sd (scan_data_7 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync1_ff
(
// Outputs
.q (jbussync1_out ),
.so (scan_data_7 ),
// Inputs
.d (jbussync1_in ),
.sd (scan_data_6 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync2_ff
(
// Outputs
.q (jbussync2_out ),
.so (scan_data_6 ),
// Inputs
.d (jbussync2_in ),
.sd (scan_data_5 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gdbginit_ff
(
// Outputs
.q (gdbginit_out ),
.so (scan_data_10 ),
// Inputs
.d (gdbginit_in ),
.sd (scan_data_9 ),
.r_l (adbginit_l),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gclk_ff
(
// Outputs
.q (grst_out ),
.so (scan_data_11 ),
// Inputs
.d (grst_in ),
.sd (scan_data_10 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
/* bw_u1_scanlg_2x AUTO_TEMPLATE (
.sd (scan_data_11 ),
.ck (clk ),
); */
bw_u1_scanlg_2x scanout_latch
( /*AUTOINST*/
// Outputs
.so (so),
// Inputs
.sd (scan_data_11 ), // Templated
.ck (clk ), // Templated
.se (1'b1));
endmodule
// Local Variables:
// verilog-library-files:("../../../common/rtl/u1.behV" )
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_BEHAVIORAL_V
`define SKY130_FD_SC_HS__EBUFN_BEHAVIORAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__ebufn (
A ,
TE_B,
Z ,
VPWR,
VGND
);
// Module ports
input A ;
input TE_B;
output Z ;
input VPWR;
input VGND;
// Local signals
wire u_vpwr_vgnd0_out_A ;
wire u_vpwr_vgnd1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_A , A, VPWR, VGND );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , u_vpwr_vgnd0_out_A, u_vpwr_vgnd1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_BEHAVIORAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire out;
reg in;
Genit g (.clk(clk), .value(in), .result(out));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, in, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 1'b1;
end
else if (cyc==1) begin
in <= 1'b0;
end
else if (cyc==2) begin
if (out != 1'b1) $stop;
end
else if (cyc==3) begin
if (out != 1'b0) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module Generate (clk, value, result);
input clk;
input value;
output result;
reg Internal;
assign result = Internal ^ clk;
always @(posedge clk)
Internal <= #1 value;
endmodule
module Checker (clk, value);
input clk, value;
always @(posedge clk) begin
$write ("[%0t] value=%h\n", $time, value);
end
endmodule
module Test (clk, value, result);
input clk;
input value;
output result;
Generate gen (clk, value, result);
Checker chk (clk, gen.Internal);
endmodule
module Genit (clk, value, result);
input clk;
input value;
output result;
`ifndef ATSIM // else unsupported
`ifndef NC // else unsupported
`define WITH_FOR_GENVAR
`endif
`endif
`define WITH_GENERATE
`ifdef WITH_GENERATE
`ifndef WITH_FOR_GENVAR
genvar i;
`endif
generate
for (
`ifdef WITH_FOR_GENVAR
genvar
`endif
i = 0; i < 1; i = i + 1)
begin : foo
Test tt (clk, value, result);
end
endgenerate
`else
Test tt (clk, value, result);
`endif
wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change!
always @ (posedge clk) begin
$write("[%0t] Result2 = %x\n", $time, Result2);
end
endmodule
|
// $Id: vcr_ivc_ctrl.v 2079 2010-06-01 04:23:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// input VC controller
module vcr_ivc_ctrl
(clk, reset, router_address, flit_valid_in, flit_head_in, flit_tail_in,
header_info_in, int_flow_ctrl_op_ovc, route_op, route_port, inc_rc, vc_req,
vc_gnt, vc_gnt_ovc, sw_req_nonspec, sw_req_spec, sw_gnt_nonspec, sw_gnt_spec,
flit_head, flit_tail, la_route_info, fbc_write_addr, fbc_read_addr,
fbc_empty, allocated, allocated_ovc, free_unallocated, free_allocated,
errors, events);
`include "c_functions.v"
`include "c_constants.v"
`include "vcr_constants.v"
// flit buffer entries per VC
parameter num_flit_buffers = 8;
// width of credit hold register
// (note: this parameter is only used for INT_FLOW_CTRL_TYPE_PUSH)
localparam cred_hold_width = clogb(num_flit_buffers);
// maximum number of packets that can be in a given VC buffer simultaneously
parameter num_header_buffers = 4;
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// number of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs available for each class
parameter num_vcs_per_class = 1;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// number of dimensions in network
parameter num_dimensions = 2;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 1;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// width required for lookahead routing information
localparam la_route_info_width
= port_idx_width + ((num_resource_classes > 1) ? 1 : 0);
// select packet format
parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
// maximum payload length (in flits)
// (note: only used if packet_format==`PACKET_FORMAT_EXPLICIT_LENGTH)
parameter max_payload_length = 4;
// minimum payload length (in flits)
// (note: only used if packet_format==`PACKET_FORMAT_EXPLICIT_LENGTH)
parameter min_payload_length = 1;
// number of bits required to represent all possible payload sizes
localparam payload_length_width
= clogb(max_payload_length-min_payload_length+1);
// width of counter for remaining flits
localparam flit_ctr_width = clogb(max_payload_length);
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// width required to select individual router in network
localparam router_addr_width = num_dimensions * dim_addr_width;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// total number of bits required for storing routing information
localparam route_info_width
= num_resource_classes * router_addr_width + node_addr_width;
// total number of bits of header information encoded in header flit payload
localparam header_info_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(la_route_info_width + route_info_width) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(la_route_info_width + route_info_width + payload_length_width) :
-1;
// width of flit control signals
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + vc_idx_width + 1 + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + vc_idx_width + 1) :
-1;
// select whether to set a packet's outgoing VC ID at the input or output
// controller
parameter track_vcs_at_output = 0;
// filter out illegal destination ports
// (the intent is to allow synthesis to optimize away the logic associated
// with such turns)
parameter restrict_turns = 1;
// select routing function type
parameter routing_type = `ROUTING_TYPE_DOR;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// select method for credit signaling from output to input controller
parameter int_flow_ctrl_type = `INT_FLOW_CTRL_TYPE_PUSH;
// number of bits to be used for credit level reporting
// (note: must be less than or equal to cred_count_width as given below)
// (note: this parameter is only used for INT_FLOW_CTRL_TYPE_LEVEL)
parameter cred_level_width = 2;
// width required for internal flow control signalling
localparam int_flow_ctrl_width
= (int_flow_ctrl_type == `INT_FLOW_CTRL_TYPE_LEVEL) ?
cred_level_width :
(int_flow_ctrl_type == `INT_FLOW_CTRL_TYPE_PUSH) ?
1 :
-1;
// select implementation variant for header FIFO
parameter header_fifo_type = `FIFO_TYPE_INDEXED;
// select implementation variant for VC allocator
parameter vc_alloc_type = `VC_ALLOC_TYPE_SEP_IF;
// select whether VCs must have credits available in order to be considered
// for VC allocation
parameter vc_alloc_requires_credit = 0;
// select speculation type for switch allocator
parameter sw_alloc_spec_type = `SW_ALLOC_SPEC_TYPE_REQS_MASK_GNTS;
// enable performance counter
parameter perf_ctr_enable = 1;
// ID of current input VC
parameter vc_id = 0;
// message class to which this VC belongs
localparam message_class
= (vc_id / (num_resource_classes*num_vcs_per_class)) % num_message_classes;
// resource class to which this VC belongs
localparam resource_class
= (vc_id / num_vcs_per_class) % num_resource_classes;
// packet class to which this VC belongs
localparam packet_class = (vc_id / num_vcs_per_class) % num_packet_classes;
// width of routing information required for each VC
localparam hop_route_info_width
= (resource_class == (num_resource_classes - 1)) ?
addr_width :
(resource_class == (num_resource_classes - 2)) ?
(router_addr_width + addr_width) :
(2 * router_addr_width);
// total number of bits of header information required for each VC
localparam hdff_width = la_route_info_width + hop_route_info_width;
// required address size for flit buffer
localparam fbf_addr_width = clogb(num_vcs*num_flit_buffers);
// index of leftmost entry in shared flit buffer
localparam fbc_min_addr = vc_id * num_flit_buffers;
// ID of current input port
parameter port_id = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// current router's address
input [0:router_addr_width-1] router_address;
// incoming flit valid
input flit_valid_in;
// incoming flit is head flit
input flit_head_in;
// incoming flit is tail
input flit_tail_in;
// header information associated with current flit
input [0:header_info_width-1] header_info_in;
// internal flow control signalling from output controller to input
// controllers
input [0:num_ports*num_vcs*int_flow_ctrl_width-1] int_flow_ctrl_op_ovc;
// destination port (1-hot)
output [0:num_ports-1] route_op;
wire [0:num_ports-1] route_op;
// destination port (encoded)
output [0:port_idx_width-1] route_port;
wire [0:port_idx_width-1] route_port;
// transition to next resource class
output inc_rc;
wire inc_rc;
// request VC allocation
output vc_req;
wire vc_req;
// VC allocation successful
input vc_gnt;
// granted output VC
input [0:num_vcs-1] vc_gnt_ovc;
// non-speculative switch allocator requests
output sw_req_nonspec;
wire sw_req_nonspec;
// speculative switch allocator requests
output sw_req_spec;
wire sw_req_spec;
// non-speculative switch allocator grants
input sw_gnt_nonspec;
// speculative switch allocator grants
input sw_gnt_spec;
// outgoing flit is head flit
output flit_head;
wire flit_head;
// outgoign flit is tail flit
output flit_tail;
wire flit_tail;
// lookahead routing information for outgoing flit
output [0:la_route_info_width-1] la_route_info;
wire [0:la_route_info_width-1] la_route_info;
// write pointer for shared flit buffer
output [0:fbf_addr_width-1] fbc_write_addr;
wire [0:fbf_addr_width-1] fbc_write_addr;
// read pointer for shared flit buffer
output [0:fbf_addr_width-1] fbc_read_addr;
wire [0:fbf_addr_width-1] fbc_read_addr;
// flit buffer does not have any valid entries
output fbc_empty;
wire fbc_empty;
// has an output VC been assigned to this input VC?
output allocated;
wire allocated;
// if so, which output VC has been assigned?
output [0:num_vcs-1] allocated_ovc;
wire [0:num_vcs-1] allocated_ovc;
// credit availability if no VC has been assigned yet
output free_unallocated;
wire free_unallocated;
// credit availability if a VC has been assigned
output free_allocated;
wire free_allocated;
// internal error condition detected
output [0:6] errors;
wire [0:6] errors;
// performance counter events
// (note: only valid if perf_ctr_enable=1)
output [0:7] events;
wire [0:7] events;
//---------------------------------------------------------------------------
// keep track of VC allocation status
//---------------------------------------------------------------------------
wire flit_sent;
wire packet_done;
assign packet_done = flit_sent & flit_tail;
wire vc_allocated_s, vc_allocated_q;
assign vc_allocated_s = (vc_allocated_q | vc_gnt) & ~packet_done;
c_dff
#(.width(1),
.reset_type(reset_type))
vc_allocatedq
(.clk(clk),
.reset(reset),
.d(vc_allocated_s),
.q(vc_allocated_q));
assign allocated = vc_allocated_q;
wire [0:num_vcs_per_class-1] vc_gnt_ocvc;
wire [0:num_vcs_per_class-1] vc_allocated_ocvc_q;
generate
if(num_vcs_per_class > 1)
begin
wire [0:num_vcs_per_class-1] vc_gnt_unchanged_ocvc;
assign vc_gnt_unchanged_ocvc
= vc_gnt_ovc[packet_class*num_vcs_per_class:
(packet_class+1)*num_vcs_per_class-1];
if(resource_class == (num_resource_classes - 1))
begin
assign vc_gnt_ocvc = vc_gnt_unchanged_ocvc;
end
else
begin
wire [0:num_vcs_per_class-1] vc_gnt_changed_ocvc;
assign vc_gnt_changed_ocvc
= vc_gnt_ovc[(packet_class+1)*num_vcs_per_class:
(packet_class+2)*num_vcs_per_class-1];
// only one of the two will have a bit set, so we just OR them
assign vc_gnt_ocvc
= vc_gnt_changed_ocvc | vc_gnt_unchanged_ocvc;
end
wire [0:num_vcs_per_class-1] vc_allocated_ocvc_s;
assign vc_allocated_ocvc_s
= vc_allocated_q ? vc_allocated_ocvc_q : vc_gnt_ocvc;
c_dff
#(.width(num_vcs_per_class),
.reset_type(reset_type))
vc_allocated_ocvcq
(.clk(clk),
.reset(reset),
.d(vc_allocated_ocvc_s),
.q(vc_allocated_ocvc_q));
end
else
begin
assign vc_gnt_ocvc = 1'b1;
assign vc_allocated_ocvc_q = 1'b1;
end
if(resource_class == (num_resource_classes - 1))
begin
c_align
#(.data_width(num_vcs_per_class),
.dest_width(num_vcs),
.offset(packet_class*num_vcs_per_class))
allocated_ovc_alg
(.data_in(vc_allocated_ocvc_q),
.dest_in({num_vcs{1'b0}}),
.data_out(allocated_ovc));
end
else
begin
c_align
#(.data_width(2*num_vcs_per_class),
.dest_width(num_vcs),
.offset(packet_class*num_vcs_per_class))
allocated_ovc_alg
(.data_in({{num_vcs_per_class{~inc_rc}} &
vc_allocated_ocvc_q,
{num_vcs_per_class{inc_rc}} &
vc_allocated_ocvc_q}),
.dest_in({num_vcs{1'b0}}),
.data_out(allocated_ovc));
end
if(sw_alloc_spec_type == `SW_ALLOC_SPEC_TYPE_NONE)
assign flit_sent = sw_gnt_nonspec;
else
assign flit_sent = (vc_gnt & sw_gnt_spec) | sw_gnt_nonspec;
endgenerate
//---------------------------------------------------------------------------
// generate head and tail indicators
//---------------------------------------------------------------------------
wire fbc_almost_empty;
generate
if(num_header_buffers > 1)
begin
// keep track of location(s) of head and tail flits in flit buffer
wire [0:num_flit_buffers-1] head_queue;
wire [0:num_flit_buffers-1] tail_queue;
wire [0:num_flit_buffers-1] write_sel;
wire [0:num_flit_buffers-1] read_sel;
genvar idx;
for(idx = 0; idx < num_flit_buffers; idx = idx + 1)
begin:idxs
assign write_sel[idx]
= (fbc_write_addr == (fbc_min_addr + idx));
assign read_sel[idx]
= (fbc_read_addr == (fbc_min_addr + idx));
wire capture;
assign capture = flit_valid_in & write_sel[idx];
reg head_q, tail_q;
always @(posedge clk)
if(capture)
begin
head_q <= flit_head_in;
tail_q <= flit_tail_in;
end
assign head_queue[idx] = head_q;
assign tail_queue[idx] = tail_q;
end
wire head_queue_muxed;
c_select_1ofn
#(.num_ports(num_flit_buffers),
.width(1))
head_queue_muxed_sel
(.select(read_sel),
.data_in(head_queue),
.data_out(head_queue_muxed));
assign flit_head = fbc_empty ? flit_head_in : head_queue_muxed;
wire tail_queue_muxed;
c_select_1ofn
#(.num_ports(num_flit_buffers),
.width(1))
tail_queue_muxed_sel
(.select(read_sel),
.data_in(tail_queue),
.data_out(tail_queue_muxed));
assign flit_tail = fbc_empty ? flit_tail_in : tail_queue_muxed;
end
else
begin
wire head_in;
assign head_in = flit_valid_in & flit_head_in;
wire head_s, head_q;
assign head_s = (head_q | head_in) & ~flit_sent;
c_dff
#(.width(1),
.reset_type(reset_type))
headq
(.clk(clk),
.reset(reset),
.d(head_s),
.q(head_q));
assign flit_head = fbc_empty ? flit_head_in : head_q;
wire tail_in;
assign tail_in = flit_valid_in & flit_tail_in;
wire tail_valid_s, tail_valid_q;
assign tail_valid_s
= (tail_valid_q | tail_in) & ~(flit_sent & flit_tail);
c_dff
#(.width(1),
.reset_type(reset_type))
tail_validq
(.clk(clk),
.reset(reset),
.d(tail_valid_s),
.q(tail_valid_q));
assign flit_tail
= fbc_empty ? flit_tail_in : (tail_valid_q & fbc_almost_empty);
end
endgenerate
//---------------------------------------------------------------------------
// header buffer
//---------------------------------------------------------------------------
wire [0:la_route_info_width-1] la_route_info_in;
assign la_route_info_in = header_info_in[0:la_route_info_width-1];
wire [0:route_info_width-1] route_info_in;
assign route_info_in
= header_info_in[la_route_info_width:
la_route_info_width+route_info_width-1];
wire [0:hop_route_info_width-1] hop_route_info_in;
wire hdff_empty;
wire hdff_push;
assign hdff_push = flit_valid_in & flit_head_in;
wire hdff_pop;
assign hdff_pop = flit_sent & flit_tail;
wire [0:la_route_info_width-1] hdff_la_route_info;
wire [0:hop_route_info_width-1] hdff_hop_route_info;
wire error_hdff_underflow;
wire error_hdff_overflow;
generate
if((resource_class == (num_resource_classes - 1)) ||
(resource_class == (num_resource_classes - 2)))
assign hop_route_info_in
= route_info_in[route_info_width-hop_route_info_width:
route_info_width-1];
else
assign hop_route_info_in
= route_info_in[resource_class*router_addr_width:
(resource_class+2)*router_addr_width-1];
if(num_header_buffers > 1)
begin
wire [0:hdff_width-1] hdff_data_in;
assign hdff_data_in[0:la_route_info_width-1] = la_route_info_in;
assign hdff_data_in[la_route_info_width:
la_route_info_width+hop_route_info_width-1]
= hop_route_info_in;
wire hdff_full;
wire [0:hdff_width-1] hdff_data_out;
wire [0:1] hdff_errors;
c_fifo
#(.depth(num_header_buffers),
.width(hdff_width),
.fifo_type(header_fifo_type),
.reset_type(reset_type))
hdff
(.clk(clk),
.reset(reset),
.full(hdff_full),
.data_in(hdff_data_in),
.push(hdff_push),
.empty(hdff_empty),
.data_out(hdff_data_out),
.pop(hdff_pop),
.errors(hdff_errors));
assign hdff_la_route_info
= hdff_empty ?
la_route_info_in :
hdff_data_out[0:la_route_info_width-1];
assign hdff_hop_route_info
= hdff_empty ?
hop_route_info_in :
hdff_data_out[la_route_info_width:
la_route_info_width+hop_route_info_width-1];
assign error_hdff_underflow = hdff_errors[0];
assign error_hdff_overflow = hdff_errors[1];
end
else
begin
wire [0:la_route_info_width-1] hdff_la_route_info_s,
hdff_la_route_info_q;
assign hdff_la_route_info_s
= hdff_push ? la_route_info_in : hdff_la_route_info_q;
c_dff
#(.width(la_route_info_width),
.reset_type(reset_type))
hdff_la_route_infoq
(.clk(clk),
.reset(1'b0),
.d(hdff_la_route_info_s),
.q(hdff_la_route_info_q));
assign hdff_la_route_info
= hdff_empty ? la_route_info_in : hdff_la_route_info_q;
wire [0:hop_route_info_width-1] hdff_hop_route_info_s,
hdff_hop_route_info_q;
assign hdff_hop_route_info_s
= hdff_push ? hop_route_info_in : hdff_hop_route_info_q;
c_dff
#(.width(hop_route_info_width),
.reset_type(reset_type))
hdff_hop_route_infoq
(.clk(clk),
.reset(1'b0),
.d(hdff_hop_route_info_s),
.q(hdff_hop_route_info_q));
assign hdff_hop_route_info
= hdff_empty ? hop_route_info_in : hdff_hop_route_info_q;
wire hdff_empty_s, hdff_empty_q;
assign hdff_empty_s = (hdff_empty_q | (hdff_pop & ~hdff_push)) &
~(hdff_push & ~hdff_pop);
c_dff
#(.width(1),
.reset_value(1'b1),
.reset_type(reset_type))
hdff_emptyq
(.clk(clk),
.reset(reset),
.d(hdff_empty_s),
.q(hdff_empty_q));
assign hdff_empty = hdff_empty_q;
assign error_hdff_underflow = hdff_empty_q & ~hdff_push & hdff_pop;
assign error_hdff_overflow = ~hdff_empty_q & hdff_push & ~hdff_pop;
end
endgenerate
wire header_valid;
assign header_valid = ~hdff_empty | flit_valid_in /*hdff_push*/;
wire flit_valid;
wire error_no_header;
assign error_no_header = flit_valid & ~header_valid;
//---------------------------------------------------------------------------
// routing logic
//---------------------------------------------------------------------------
assign route_port = hdff_la_route_info[0:port_idx_width-1];
wire [0:num_ports-1] route_unmasked_op;
c_decoder
#(.num_ports(num_ports))
route_unmasked_op_dec
(.data_in(route_port),
.data_out(route_unmasked_op));
wire pf_error;
c_port_filter
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_ports(num_ports),
.num_neighbors_per_dim(num_neighbors_per_dim),
.num_nodes_per_router(num_nodes_per_router),
.restrict_turns(restrict_turns),
.connectivity(connectivity),
.routing_type(routing_type),
.dim_order(dim_order),
.port_id(port_id),
.message_class(message_class),
.resource_class(resource_class))
route_op_pf
(.route_in_op(route_unmasked_op),
.inc_rc(inc_rc),
.route_out_op(route_op),
.error(pf_error));
wire error_invalid_port;
assign error_invalid_port = header_valid & pf_error;
generate
if(resource_class < (num_resource_classes - 1))
assign inc_rc = hdff_la_route_info[port_idx_width];
else
assign inc_rc = 1'b0;
endgenerate
vcr_la_routing_logic
#(.num_resource_classes(num_resource_classes),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.routing_type(routing_type),
.dim_order(dim_order),
.resource_class(resource_class),
.reset_type(reset_type))
lar
(.clk(clk),
.reset(reset),
.router_address(router_address),
.route_port(route_port),
.inc_rc(inc_rc),
.hop_route_info(hdff_hop_route_info),
.la_route_info(la_route_info));
//---------------------------------------------------------------------------
// credit tracking
//---------------------------------------------------------------------------
wire [0:num_vcs*int_flow_ctrl_width-1] int_flow_ctrl_ovc;
assign int_flow_ctrl_ovc
= int_flow_ctrl_op_ovc[route_port*num_vcs*int_flow_ctrl_width +:
num_vcs*int_flow_ctrl_width];
wire error_ct_overflow;
generate
case(int_flow_ctrl_type)
// the current number of credits available are transmitted from the
// output controllers as a multi-level signal (0, 1, 2 or 3+ credits
// currently available)
`INT_FLOW_CTRL_TYPE_LEVEL:
begin
// credit status for the case where we do not change resource class
wire [0:num_vcs_per_class*2-1] free_unchanged_ocvc;
assign free_unchanged_ocvc
= int_flow_ctrl_ovc[packet_class*num_vcs_per_class*2:
(packet_class+1)*num_vcs_per_class*2-1];
wire [0:num_vcs_per_class*2-1] free_ocvc;
if(resource_class == (num_resource_classes - 1))
assign free_ocvc = free_unchanged_ocvc;
else
begin
// credit status in case we change resource class
wire [0:num_vcs_per_class*2-1] free_changed_ocvc;
assign free_changed_ocvc
= int_flow_ctrl_ovc[(packet_class+1)*num_vcs_per_class*2:
(packet_class+2)*num_vcs_per_class*2-1];
assign free_ocvc
= inc_rc ? free_changed_ocvc : free_unchanged_ocvc;
end
wire flit_sent_prev_s,
flit_sent_prev_q;
assign flit_sent_prev_s = flit_sent /*& ~flit_tail*/;
c_dff
#(.width(1),
.reset_type(reset_type))
flit_sent_prevq
(.clk(clk),
.reset(reset),
.d(flit_sent_prev_s),
.q(flit_sent_prev_q));
wire [0:1] flit_sent_count;
assign flit_sent_count = flit_sent_prev_q + flit_sent;
wire [0:num_vcs_per_class-1] next_free_ocvc;
wire [0:num_vcs_per_class-1] free_unallocated_ocvc;
genvar ocvc;
for(ocvc = 0; ocvc < num_vcs_per_class; ocvc = ocvc + 1)
begin:ocvcs
wire [0:1] free;
assign free = free_ocvc[ocvc*2:(ocvc+1)*2-1];
wire [0:2] free_by_count;
assign free_by_count = {|free, free[0], &free};
// NOTE: For allocated VCs, the free state must be updated
// depending on how many flits were sent to the VC that are
// not already reflected in the incoming credit count.
wire next_free;
assign next_free = free_by_count[flit_sent_count];
assign next_free_ocvc[ocvc] = next_free;
// NOTE: When sending the first flit in each packet, we must
// have won VC allocation. Consequently, the destination
// output VC must have been eligible and thus not assigned to
// any input VC, so we know that nobody sent a flit to it in
// the previous cycle.
wire free_unallocated;
assign free_unallocated = |free;
assign free_unallocated_ocvc[ocvc] = free_unallocated;
end
wire free_allocated_s, free_allocated_q;
assign free_allocated_s
= |(next_free_ocvc &
(vc_allocated_q ? vc_allocated_ocvc_q : vc_gnt_ocvc));
c_dff
#(.width(1),
.reset_value(1'b1),
.reset_type(reset_type))
free_allocatedq
(.clk(clk),
.reset(reset),
.d(free_allocated_s),
.q(free_allocated_q));
assign free_allocated = free_allocated_q;
assign free_unallocated = |(free_unallocated_ocvc & vc_gnt_ocvc);
assign error_ct_overflow = 1'b0;
end
// credits are forwarded from the output controllers individually as
// pulses, accumulated at the input controllers, and used whenever a
// flit is sent to the crossbar
`INT_FLOW_CTRL_TYPE_PUSH:
begin
// credit indicator for the case where we do not change the
// resource class
wire [0:num_vcs_per_class-1] cred_unchanged_ocvc;
assign cred_unchanged_ocvc
= int_flow_ctrl_ovc[packet_class*num_vcs_per_class:
(packet_class+1)*num_vcs_per_class-1];
wire [0:num_vcs_per_class-1] cred_ocvc;
if(resource_class == (num_resource_classes - 1))
assign cred_ocvc = cred_unchanged_ocvc;
else
begin
// credit status for the case where the resource class changes
wire [0:num_vcs_per_class-1] cred_changed_ocvc;
assign cred_changed_ocvc
= int_flow_ctrl_ovc[(packet_class+1)*num_vcs_per_class:
(packet_class+2)*num_vcs_per_class-1];
assign cred_ocvc = inc_rc ?
cred_changed_ocvc :
cred_unchanged_ocvc;
end
wire cred_allocated;
assign cred_allocated = |(cred_ocvc & vc_allocated_ocvc_q);
wire cred_unallocated;
assign cred_unallocated = |(cred_ocvc & vc_gnt_ocvc);
wire [0:cred_hold_width-1] cred_hold_q;
wire has_cred_s, has_cred_q;
if(vc_alloc_requires_credit)
assign has_cred_s
= vc_allocated_q ?
((has_cred_q & ~sw_gnt_nonspec) | (|cred_hold_q) |
cred_allocated) :
(~sw_gnt_spec | cred_unallocated);
else
assign has_cred_s
= vc_allocated_q ?
((has_cred_q & ~sw_gnt_nonspec) | (|cred_hold_q) |
cred_allocated) :
(~sw_gnt_spec & cred_unallocated);
c_dff
#(.width(1),
.reset_type(reset_type))
has_credq
(.clk(clk),
.reset(reset),
.d(has_cred_s),
.q(has_cred_q));
assign free_allocated = has_cred_q;
assign free_unallocated = cred_unallocated;
wire incr_cred_hold;
assign incr_cred_hold
= cred_allocated & ~sw_gnt_nonspec & has_cred_q;
wire decr_cred_hold;
assign decr_cred_hold
= ~cred_allocated & sw_gnt_nonspec & |cred_hold_q;
wire [0:cred_hold_width-1] cred_hold_new;
if(vc_alloc_requires_credit)
assign cred_hold_new = ~sw_gnt_spec & cred_unallocated;
else
assign cred_hold_new = {cred_hold_width{1'b0}};
wire [0:cred_hold_width-1] cred_hold_s;
assign cred_hold_s
= vc_allocated_q ?
(cred_hold_q + incr_cred_hold - decr_cred_hold) :
cred_hold_new;
c_dff
#(.width(cred_hold_width),
.reset_type(reset_type))
cred_holdq
(.clk(clk),
.reset(reset),
.d(cred_hold_s),
.q(cred_hold_q));
assign error_ct_overflow
= vc_allocated_q && (cred_hold_q == num_flit_buffers-1) &&
incr_cred_hold;
end
endcase
endgenerate
//---------------------------------------------------------------------------
// generate allocator control signals
//---------------------------------------------------------------------------
assign sw_req_nonspec = flit_valid & vc_allocated_q;
generate
if(sw_alloc_spec_type == `SW_ALLOC_SPEC_TYPE_NONE)
assign sw_req_spec = 1'b0;
else
assign sw_req_spec = flit_valid & ~vc_allocated_q;
endgenerate
assign vc_req = header_valid & ~vc_allocated_q;
//---------------------------------------------------------------------------
// flit buffer control
//---------------------------------------------------------------------------
wire fbc_push;
assign fbc_push = flit_valid_in;
wire fbc_pop;
assign fbc_pop = flit_sent;
wire [0:1] fbc_errors;
wire fbc_almost_full;
wire fbc_full;
c_fifo_ctrl
#(.addr_width(fbf_addr_width),
.offset(fbc_min_addr),
.depth(num_flit_buffers),
.reset_type(reset_type))
fbc
(.clk(clk),
.reset(reset),
.push(fbc_push),
.pop(fbc_pop),
.write_addr(fbc_write_addr),
.read_addr(fbc_read_addr),
.almost_empty(fbc_almost_empty),
.empty(fbc_empty),
.almost_full(fbc_almost_full),
.full(fbc_full),
.errors(fbc_errors));
wire error_fbc_underflow;
assign error_fbc_underflow = fbc_errors[0];
wire error_fbc_overflow;
assign error_fbc_overflow = fbc_errors[1];
assign flit_valid = flit_valid_in | ~fbc_empty;
//---------------------------------------------------------------------------
// error checking
//---------------------------------------------------------------------------
assign errors = {error_fbc_underflow,
error_fbc_overflow,
error_hdff_underflow,
error_hdff_overflow,
error_no_header,
error_ct_overflow,
error_invalid_port};
//---------------------------------------------------------------------------
// instrumentation
//---------------------------------------------------------------------------
generate
if(perf_ctr_enable > 0)
begin
wire ev_no_flit;
assign ev_no_flit = header_valid & ~flit_valid;
wire ev_flit_ready;
assign ev_flit_ready = header_valid & flit_valid;
wire ev_flit_stalled_vc;
assign ev_flit_stalled_vc
= header_valid & flit_valid & ~vc_allocated_q & ~vc_gnt;
wire ev_flit_stalled_sw;
if(sw_alloc_spec_type == `SW_ALLOC_SPEC_TYPE_NONE)
assign ev_flit_stalled_sw
= header_valid & flit_valid & vc_allocated_q & ~sw_gnt_nonspec;
else
assign ev_flit_stalled_sw
= header_valid & flit_valid &
(vc_allocated_q & ~sw_gnt_nonspec) |
(vc_gnt & ~sw_gnt_spec);
wire ev_spec_attempted;
assign ev_spec_attempted
= header_valid & flit_valid & ~vc_allocated_q;
wire ev_spec_failed;
if(sw_alloc_spec_type == `SW_ALLOC_SPEC_TYPE_NONE)
assign ev_spec_failed = 1'b0;
else
assign ev_spec_failed
= header_valid & flit_valid & ~vc_allocated_q &
~vc_gnt & sw_gnt_spec;
wire ev_flit_sent;
assign ev_flit_sent = flit_sent;
wire ev_flit_sent_spec;
assign ev_flit_sent_spec = flit_sent & ~vc_allocated_q;
wire [0:7] events_s, events_q;
assign events_s = {ev_no_flit,
ev_flit_ready,
ev_flit_stalled_vc,
ev_flit_stalled_sw,
ev_spec_attempted,
ev_spec_failed,
ev_flit_sent,
ev_flit_sent_spec};
c_dff
#(.width(8),
.reset_type(reset_type))
eventsq
(.clk(clk),
.reset(reset),
.d(events_s),
.q(events_q));
assign events = events_q;
end
else
assign events = 8'd0;
endgenerate
endmodule
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_asin_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_arcsin_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.q(sub_wire0));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_TB_V
`define SKY130_FD_SC_HS__OR3_TB_V
/**
* or3: 3-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 C = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 C = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_TB_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : fanyibo@fudan.edu.cn
//
//-------------------------------------------------------------------
//
// Filename : fme_ip_quarter_ver.v
// Author : Yufeng Bai
// Email : byfchina@gmail.com
//
// $Id$
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fme_ip_quarter_ver (
clk ,
rstn ,
blk_start_i ,
refpel_valid_i ,
hor_start_i ,
horbuf_valid_i ,
frac_x_i ,
frac_y_i ,
q1_buf0_i ,
q1_buf1_i ,
q1_buf2_i ,
q1_buf3_i ,
q1_buf4_i ,
q1_buf5_i ,
q1_buf6_i ,
q1_buf7_i ,
q3_buf0_i ,
q3_buf1_i ,
q3_buf2_i ,
q3_buf3_i ,
q3_buf4_i ,
q3_buf5_i ,
q3_buf6_i ,
q3_buf7_i ,
h_buf0_i ,
h_buf1_i ,
h_buf2_i ,
h_buf3_i ,
h_buf4_i ,
h_buf5_i ,
h_buf6_i ,
h_buf7_i ,
ref_pel0_i ,
ref_pel1_i ,
ref_pel2_i ,
ref_pel3_i ,
ref_pel4_i ,
ref_pel5_i ,
ref_pel6_i ,
ref_pel7_i ,
//vquarter_1_valid_o , // [1][1]. [3][1]
//vquarter_3_valid_o , // [1][3], [3][3]
//vquarter_2_valid_o , // [1][2], [3][2]
//vquarter_0_valid_o , // [1][0], [3][0]
//vhalf_valid_o , // [2][1], [2][3]
//vpel_valid_o , // [0][1], [0][3]
vquarter_1_1_pel0_o ,
vquarter_1_1_pel1_o ,
vquarter_1_1_pel2_o ,
vquarter_1_1_pel3_o ,
vquarter_1_1_pel4_o ,
vquarter_1_1_pel5_o ,
vquarter_1_1_pel6_o ,
vquarter_1_1_pel7_o ,
vquarter_1_3_pel0_o ,
vquarter_1_3_pel1_o ,
vquarter_1_3_pel2_o ,
vquarter_1_3_pel3_o ,
vquarter_1_3_pel4_o ,
vquarter_1_3_pel5_o ,
vquarter_1_3_pel6_o ,
vquarter_1_3_pel7_o ,
vquarter_1_2_pel0_o ,
vquarter_1_2_pel1_o ,
vquarter_1_2_pel2_o ,
vquarter_1_2_pel3_o ,
vquarter_1_2_pel4_o ,
vquarter_1_2_pel5_o ,
vquarter_1_2_pel6_o ,
vquarter_1_2_pel7_o ,
vquarter_1_0_pel0_o ,
vquarter_1_0_pel1_o ,
vquarter_1_0_pel2_o ,
vquarter_1_0_pel3_o ,
vquarter_1_0_pel4_o ,
vquarter_1_0_pel5_o ,
vquarter_1_0_pel6_o ,
vquarter_1_0_pel7_o ,
vquarter_3_1_pel0_o ,
vquarter_3_1_pel1_o ,
vquarter_3_1_pel2_o ,
vquarter_3_1_pel3_o ,
vquarter_3_1_pel4_o ,
vquarter_3_1_pel5_o ,
vquarter_3_1_pel6_o ,
vquarter_3_1_pel7_o ,
vquarter_3_3_pel0_o ,
vquarter_3_3_pel1_o ,
vquarter_3_3_pel2_o ,
vquarter_3_3_pel3_o ,
vquarter_3_3_pel4_o ,
vquarter_3_3_pel5_o ,
vquarter_3_3_pel6_o ,
vquarter_3_3_pel7_o ,
vquarter_3_2_pel0_o ,
vquarter_3_2_pel1_o ,
vquarter_3_2_pel2_o ,
vquarter_3_2_pel3_o ,
vquarter_3_2_pel4_o ,
vquarter_3_2_pel5_o ,
vquarter_3_2_pel6_o ,
vquarter_3_2_pel7_o ,
vquarter_3_0_pel0_o ,
vquarter_3_0_pel1_o ,
vquarter_3_0_pel2_o ,
vquarter_3_0_pel3_o ,
vquarter_3_0_pel4_o ,
vquarter_3_0_pel5_o ,
vquarter_3_0_pel6_o ,
vquarter_3_0_pel7_o ,
vpel_0_1_pel0_o ,
vpel_0_1_pel1_o ,
vpel_0_1_pel2_o ,
vpel_0_1_pel3_o ,
vpel_0_1_pel4_o ,
vpel_0_1_pel5_o ,
vpel_0_1_pel6_o ,
vpel_0_1_pel7_o ,
vpel_0_3_pel0_o ,
vpel_0_3_pel1_o ,
vpel_0_3_pel2_o ,
vpel_0_3_pel3_o ,
vpel_0_3_pel4_o ,
vpel_0_3_pel5_o ,
vpel_0_3_pel6_o ,
vpel_0_3_pel7_o ,
vhalf_2_1_pel0_o ,
vhalf_2_1_pel1_o ,
vhalf_2_1_pel2_o ,
vhalf_2_1_pel3_o ,
vhalf_2_1_pel4_o ,
vhalf_2_1_pel5_o ,
vhalf_2_1_pel6_o ,
vhalf_2_1_pel7_o ,
vhalf_2_3_pel0_o ,
vhalf_2_3_pel1_o ,
vhalf_2_3_pel2_o ,
vhalf_2_3_pel3_o ,
vhalf_2_3_pel4_o ,
vhalf_2_3_pel5_o ,
vhalf_2_3_pel6_o ,
vhalf_2_3_pel7_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] blk_start_i ; // 8x8 block interpolation start signal
input [1-1:0] refpel_valid_i ; // referenced pixel valid
input [1-1:0] hor_start_i ; // 8x8 block horizontal interpolation start signal
input [1-1:0] horbuf_valid_i ; // horizontal buf pixel valid
input [2-1:0] frac_x_i ; // frac_x: 00: ==0, 01: <0, 10:>0
input [2-1:0] frac_y_i ; // frac_y: 00: ==0, 01: <0, 10:>0
input [2*`PIXEL_WIDTH-1:0] q1_buf0_i ; // horizontal quarter 1 interpolation results 0
input [2*`PIXEL_WIDTH-1:0] q1_buf1_i ; // horizontal quarter 1 interpolation results 1
input [2*`PIXEL_WIDTH-1:0] q1_buf2_i ; // horizontal quarter 1 interpolation results 2
input [2*`PIXEL_WIDTH-1:0] q1_buf3_i ; // horizontal quarter 1 interpolation results 3
input [2*`PIXEL_WIDTH-1:0] q1_buf4_i ; // horizontal quarter 1 interpolation results 4
input [2*`PIXEL_WIDTH-1:0] q1_buf5_i ; // horizontal quarter 1 interpolation results 5
input [2*`PIXEL_WIDTH-1:0] q1_buf6_i ; // horizontal quarter 1 interpolation results 6
input [2*`PIXEL_WIDTH-1:0] q1_buf7_i ; // horizontal quarter 1 interpolation results 7
input [2*`PIXEL_WIDTH-1:0] q3_buf0_i ; // horizontal quarter 3 interpolation results 0
input [2*`PIXEL_WIDTH-1:0] q3_buf1_i ; // horizontal quarter 3 interpolation results 1
input [2*`PIXEL_WIDTH-1:0] q3_buf2_i ; // horizontal quarter 3 interpolation results 2
input [2*`PIXEL_WIDTH-1:0] q3_buf3_i ; // horizontal quarter 3 interpolation results 3
input [2*`PIXEL_WIDTH-1:0] q3_buf4_i ; // horizontal quarter 3 interpolation results 4
input [2*`PIXEL_WIDTH-1:0] q3_buf5_i ; // horizontal quarter 3 interpolation results 5
input [2*`PIXEL_WIDTH-1:0] q3_buf6_i ; // horizontal quarter 3 interpolation results 6
input [2*`PIXEL_WIDTH-1:0] q3_buf7_i ; // horizontal quarter 3 interpolation results 7
input [2*`PIXEL_WIDTH-1:0] h_buf0_i ; // horizontal half interpolation results 0
input [2*`PIXEL_WIDTH-1:0] h_buf1_i ; // horizontal half interpolation results 1
input [2*`PIXEL_WIDTH-1:0] h_buf2_i ; // horizontal half interpolation results 2
input [2*`PIXEL_WIDTH-1:0] h_buf3_i ; // horizontal half interpolation results 3
input [2*`PIXEL_WIDTH-1:0] h_buf4_i ; // horizontal half interpolation results 4
input [2*`PIXEL_WIDTH-1:0] h_buf5_i ; // horizontal half interpolation results 5
input [2*`PIXEL_WIDTH-1:0] h_buf6_i ; // horizontal half interpolation results 6
input [2*`PIXEL_WIDTH-1:0] h_buf7_i ; // horizontal half interpolation results 7
input [`PIXEL_WIDTH-1:0] ref_pel0_i ; // referenced pixel 0
input [`PIXEL_WIDTH-1:0] ref_pel1_i ; // referenced pixel 1
input [`PIXEL_WIDTH-1:0] ref_pel2_i ; // referenced pixel 2
input [`PIXEL_WIDTH-1:0] ref_pel3_i ; // referenced pixel 3
input [`PIXEL_WIDTH-1:0] ref_pel4_i ; // referenced pixel 4
input [`PIXEL_WIDTH-1:0] ref_pel5_i ; // referenced pixel 5
input [`PIXEL_WIDTH-1:0] ref_pel6_i ; // referenced pixel 6
input [`PIXEL_WIDTH-1:0] ref_pel7_i ; // referenced pixel 7
//output [1-1:0] vquarter_1_valid_o ; // vertical quarter 1 predicted pixels output valid
//output [1-1:0] vquarter_3_valid_o ; // vertical quarter 3 predicted pixels output valid
//output [1-1:0] vquarter_2_valid_o ; // vertical quarter 2 predicted pixels output valid
//output [1-1:0] vquarter_0_valid_o ; // vertical quarter 0 predicted pixels output valid
//output [1-1:0] vhalf_valid_o ; // vertical half predicted pixels output valid
//output [1-1:0] vpel_valid_o ; // cliped half predicted pixels output valid
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel0_o ; // from q1 vertical quarter 1 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel1_o ; // from q1 vertical quarter 1 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel2_o ; // from q1 vertical quarter 1 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel3_o ; // from q1 vertical quarter 1 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel4_o ; // from q1 vertical quarter 1 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel5_o ; // from q1 vertical quarter 1 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel6_o ; // from q1 vertical quarter 1 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_1_1_pel7_o ; // from q1 vertical quarter 1 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel0_o ; // from q3 vertical quarter 1 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel1_o ; // from q3 vertical quarter 1 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel2_o ; // from q3 vertical quarter 1 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel3_o ; // from q3 vertical quarter 1 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel4_o ; // from q3 vertical quarter 1 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel5_o ; // from q3 vertical quarter 1 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel6_o ; // from q3 vertical quarter 1 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_1_3_pel7_o ; // from q3 vertical quarter 1 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel0_o ; // from half vertical quarter 1 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel1_o ; // from half vertical quarter 1 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel2_o ; // from half vertical quarter 1 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel3_o ; // from half vertical quarter 1 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel4_o ; // from half vertical quarter 1 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel5_o ; // from half vertical quarter 1 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel6_o ; // from half vertical quarter 1 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_1_2_pel7_o ; // from half vertical quarter 1 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel0_o ; // from ref vertical quarter 1 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel1_o ; // from ref vertical quarter 1 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel2_o ; // from ref vertical quarter 1 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel3_o ; // from ref vertical quarter 1 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel4_o ; // from ref vertical quarter 1 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel5_o ; // from ref vertical quarter 1 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel6_o ; // from ref vertical quarter 1 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_1_0_pel7_o ; // from ref vertical quarter 1 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel0_o ; // from q1 vertical quarter 3 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel1_o ; // from q1 vertical quarter 3 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel2_o ; // from q1 vertical quarter 3 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel3_o ; // from q1 vertical quarter 3 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel4_o ; // from q1 vertical quarter 3 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel5_o ; // from q1 vertical quarter 3 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel6_o ; // from q1 vertical quarter 3 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_3_1_pel7_o ; // from q1 vertical quarter 3 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel0_o ; // from q3 vertical quarter 3 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel1_o ; // from q3 vertical quarter 3 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel2_o ; // from q3 vertical quarter 3 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel3_o ; // from q3 vertical quarter 3 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel4_o ; // from q3 vertical quarter 3 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel5_o ; // from q3 vertical quarter 3 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel6_o ; // from q3 vertical quarter 3 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_3_3_pel7_o ; // from q3 vertical quarter 3 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel0_o ; // from ref vertical quarter 3 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel1_o ; // from ref vertical quarter 3 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel2_o ; // from ref vertical quarter 3 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel3_o ; // from ref vertical quarter 3 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel4_o ; // from ref vertical quarter 3 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel5_o ; // from ref vertical quarter 3 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel6_o ; // from ref vertical quarter 3 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_3_0_pel7_o ; // from ref vertical quarter 3 pixel 7
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel0_o ; // from half vertical quarter 3 pixel 0
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel1_o ; // from half vertical quarter 3 pixel 1
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel2_o ; // from half vertical quarter 3 pixel 2
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel3_o ; // from half vertical quarter 3 pixel 3
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel4_o ; // from half vertical quarter 3 pixel 4
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel5_o ; // from half vertical quarter 3 pixel 5
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel6_o ; // from half vertical quarter 3 pixel 6
output [`PIXEL_WIDTH-1:0] vquarter_3_2_pel7_o ; // from half vertical quarter 3 pixel 7
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel0_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel1_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel2_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel3_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel4_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel5_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel6_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_1_pel7_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel0_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel1_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel2_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel3_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel4_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel5_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel6_o ;
output [`PIXEL_WIDTH-1:0] vhalf_2_3_pel7_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel0_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel1_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel2_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel3_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel4_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel5_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel6_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_1_pel7_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel0_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel1_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel2_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel3_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel4_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel5_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel6_o ;
output [`PIXEL_WIDTH-1:0] vpel_0_3_pel7_o ;
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg [3 :0] cnt_ref;
reg [3 :0] cnt_hor;
reg [2*`PIXEL_WIDTH-1:0] q1_buf0_d1, q1_buf0_d2, q1_buf0_d3, q1_buf0_d4, q1_buf0_d5, q1_buf0_d6, q1_buf0_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf1_d1, q1_buf1_d2, q1_buf1_d3, q1_buf1_d4, q1_buf1_d5, q1_buf1_d6, q1_buf1_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf2_d1, q1_buf2_d2, q1_buf2_d3, q1_buf2_d4, q1_buf2_d5, q1_buf2_d6, q1_buf2_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf3_d1, q1_buf3_d2, q1_buf3_d3, q1_buf3_d4, q1_buf3_d5, q1_buf3_d6, q1_buf3_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf4_d1, q1_buf4_d2, q1_buf4_d3, q1_buf4_d4, q1_buf4_d5, q1_buf4_d6, q1_buf4_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf5_d1, q1_buf5_d2, q1_buf5_d3, q1_buf5_d4, q1_buf5_d5, q1_buf5_d6, q1_buf5_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf6_d1, q1_buf6_d2, q1_buf6_d3, q1_buf6_d4, q1_buf6_d5, q1_buf6_d6, q1_buf6_d7;
reg [2*`PIXEL_WIDTH-1:0] q1_buf7_d1, q1_buf7_d2, q1_buf7_d3, q1_buf7_d4, q1_buf7_d5, q1_buf7_d6, q1_buf7_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf0_d1, q3_buf0_d2, q3_buf0_d3, q3_buf0_d4, q3_buf0_d5, q3_buf0_d6, q3_buf0_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf1_d1, q3_buf1_d2, q3_buf1_d3, q3_buf1_d4, q3_buf1_d5, q3_buf1_d6, q3_buf1_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf2_d1, q3_buf2_d2, q3_buf2_d3, q3_buf2_d4, q3_buf2_d5, q3_buf2_d6, q3_buf2_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf3_d1, q3_buf3_d2, q3_buf3_d3, q3_buf3_d4, q3_buf3_d5, q3_buf3_d6, q3_buf3_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf4_d1, q3_buf4_d2, q3_buf4_d3, q3_buf4_d4, q3_buf4_d5, q3_buf4_d6, q3_buf4_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf5_d1, q3_buf5_d2, q3_buf5_d3, q3_buf5_d4, q3_buf5_d5, q3_buf5_d6, q3_buf5_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf6_d1, q3_buf6_d2, q3_buf6_d3, q3_buf6_d4, q3_buf6_d5, q3_buf6_d6, q3_buf6_d7;
reg [2*`PIXEL_WIDTH-1:0] q3_buf7_d1, q3_buf7_d2, q3_buf7_d3, q3_buf7_d4, q3_buf7_d5, q3_buf7_d6, q3_buf7_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf0_d1, h_buf0_d2, h_buf0_d3, h_buf0_d4, h_buf0_d5, h_buf0_d6, h_buf0_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf1_d1, h_buf1_d2, h_buf1_d3, h_buf1_d4, h_buf1_d5, h_buf1_d6, h_buf1_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf2_d1, h_buf2_d2, h_buf2_d3, h_buf2_d4, h_buf2_d5, h_buf2_d6, h_buf2_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf3_d1, h_buf3_d2, h_buf3_d3, h_buf3_d4, h_buf3_d5, h_buf3_d6, h_buf3_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf4_d1, h_buf4_d2, h_buf4_d3, h_buf4_d4, h_buf4_d5, h_buf4_d6, h_buf4_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf5_d1, h_buf5_d2, h_buf5_d3, h_buf5_d4, h_buf5_d5, h_buf5_d6, h_buf5_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf6_d1, h_buf6_d2, h_buf6_d3, h_buf6_d4, h_buf6_d5, h_buf6_d6, h_buf6_d7;
reg [2*`PIXEL_WIDTH-1:0] h_buf7_d1, h_buf7_d2, h_buf7_d3, h_buf7_d4, h_buf7_d5, h_buf7_d6, h_buf7_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel0_d1, ref_pel0_d2, ref_pel0_d3, ref_pel0_d4, ref_pel0_d5, ref_pel0_d6, ref_pel0_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel1_d1, ref_pel1_d2, ref_pel1_d3, ref_pel1_d4, ref_pel1_d5, ref_pel1_d6, ref_pel1_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel2_d1, ref_pel2_d2, ref_pel2_d3, ref_pel2_d4, ref_pel2_d5, ref_pel2_d6, ref_pel2_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel3_d1, ref_pel3_d2, ref_pel3_d3, ref_pel3_d4, ref_pel3_d5, ref_pel3_d6, ref_pel3_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel4_d1, ref_pel4_d2, ref_pel4_d3, ref_pel4_d4, ref_pel4_d5, ref_pel4_d6, ref_pel4_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel5_d1, ref_pel5_d2, ref_pel5_d3, ref_pel5_d4, ref_pel5_d5, ref_pel5_d6, ref_pel5_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel6_d1, ref_pel6_d2, ref_pel6_d3, ref_pel6_d4, ref_pel6_d5, ref_pel6_d6, ref_pel6_d7;
reg [`PIXEL_WIDTH-1:0] ref_pel7_d1, ref_pel7_d2, ref_pel7_d3, ref_pel7_d4, ref_pel7_d5, ref_pel7_d6, ref_pel7_d7;
//wire cnthorLargerThan3;
//wire cnthorLargerThan4;
//
//wire cntrefLargerThan7;
//wire cntrefLargerThan8;
//
//wire cnthorLargerThan7;
//wire cnthorLargerThan8;
// ********************************************
//
// Combinational Logic
//
// ********************************************
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
q1_buf0_d1 <= 'd0; q1_buf0_d2 <= 'd0; q1_buf0_d3 <= 'd0; q1_buf0_d4 <= 'd0; q1_buf0_d5 <= 'd0; q1_buf0_d6 <= 'd0; q1_buf0_d7 <= 'd0;
q1_buf1_d1 <= 'd0; q1_buf1_d2 <= 'd0; q1_buf1_d3 <= 'd0; q1_buf1_d4 <= 'd0; q1_buf1_d5 <= 'd0; q1_buf1_d6 <= 'd0; q1_buf1_d7 <= 'd0;
q1_buf2_d1 <= 'd0; q1_buf2_d2 <= 'd0; q1_buf2_d3 <= 'd0; q1_buf2_d4 <= 'd0; q1_buf2_d5 <= 'd0; q1_buf2_d6 <= 'd0; q1_buf2_d7 <= 'd0;
q1_buf3_d1 <= 'd0; q1_buf3_d2 <= 'd0; q1_buf3_d3 <= 'd0; q1_buf3_d4 <= 'd0; q1_buf3_d5 <= 'd0; q1_buf3_d6 <= 'd0; q1_buf3_d7 <= 'd0;
q1_buf4_d1 <= 'd0; q1_buf4_d2 <= 'd0; q1_buf4_d3 <= 'd0; q1_buf4_d4 <= 'd0; q1_buf4_d5 <= 'd0; q1_buf4_d6 <= 'd0; q1_buf4_d7 <= 'd0;
q1_buf5_d1 <= 'd0; q1_buf5_d2 <= 'd0; q1_buf5_d3 <= 'd0; q1_buf5_d4 <= 'd0; q1_buf5_d5 <= 'd0; q1_buf5_d6 <= 'd0; q1_buf5_d7 <= 'd0;
q1_buf6_d1 <= 'd0; q1_buf6_d2 <= 'd0; q1_buf6_d3 <= 'd0; q1_buf6_d4 <= 'd0; q1_buf6_d5 <= 'd0; q1_buf6_d6 <= 'd0; q1_buf6_d7 <= 'd0;
q1_buf7_d1 <= 'd0; q1_buf7_d2 <= 'd0; q1_buf7_d3 <= 'd0; q1_buf7_d4 <= 'd0; q1_buf7_d5 <= 'd0; q1_buf7_d6 <= 'd0; q1_buf7_d7 <= 'd0;
q3_buf0_d1 <= 'd0; q3_buf0_d2 <= 'd0; q3_buf0_d3 <= 'd0; q3_buf0_d4 <= 'd0; q3_buf0_d5 <= 'd0; q3_buf0_d6 <= 'd0; q3_buf0_d7 <= 'd0;
q3_buf1_d1 <= 'd0; q3_buf1_d2 <= 'd0; q3_buf1_d3 <= 'd0; q3_buf1_d4 <= 'd0; q3_buf1_d5 <= 'd0; q3_buf1_d6 <= 'd0; q3_buf1_d7 <= 'd0;
q3_buf2_d1 <= 'd0; q3_buf2_d2 <= 'd0; q3_buf2_d3 <= 'd0; q3_buf2_d4 <= 'd0; q3_buf2_d5 <= 'd0; q3_buf2_d6 <= 'd0; q3_buf2_d7 <= 'd0;
q3_buf3_d1 <= 'd0; q3_buf3_d2 <= 'd0; q3_buf3_d3 <= 'd0; q3_buf3_d4 <= 'd0; q3_buf3_d5 <= 'd0; q3_buf3_d6 <= 'd0; q3_buf3_d7 <= 'd0;
q3_buf4_d1 <= 'd0; q3_buf4_d2 <= 'd0; q3_buf4_d3 <= 'd0; q3_buf4_d4 <= 'd0; q3_buf4_d5 <= 'd0; q3_buf4_d6 <= 'd0; q3_buf4_d7 <= 'd0;
q3_buf5_d1 <= 'd0; q3_buf5_d2 <= 'd0; q3_buf5_d3 <= 'd0; q3_buf5_d4 <= 'd0; q3_buf5_d5 <= 'd0; q3_buf5_d6 <= 'd0; q3_buf5_d7 <= 'd0;
q3_buf6_d1 <= 'd0; q3_buf6_d2 <= 'd0; q3_buf6_d3 <= 'd0; q3_buf6_d4 <= 'd0; q3_buf6_d5 <= 'd0; q3_buf6_d6 <= 'd0; q3_buf6_d7 <= 'd0;
q3_buf7_d1 <= 'd0; q3_buf7_d2 <= 'd0; q3_buf7_d3 <= 'd0; q3_buf7_d4 <= 'd0; q3_buf7_d5 <= 'd0; q3_buf7_d6 <= 'd0; q3_buf7_d7 <= 'd0;
h_buf0_d1 <= 'd0; h_buf0_d2 <= 'd0; h_buf0_d3 <= 'd0; h_buf0_d4 <= 'd0; h_buf0_d5 <= 'd0; h_buf0_d6 <= 'd0; h_buf0_d7 <= 'd0;
h_buf1_d1 <= 'd0; h_buf1_d2 <= 'd0; h_buf1_d3 <= 'd0; h_buf1_d4 <= 'd0; h_buf1_d5 <= 'd0; h_buf1_d6 <= 'd0; h_buf1_d7 <= 'd0;
h_buf2_d1 <= 'd0; h_buf2_d2 <= 'd0; h_buf2_d3 <= 'd0; h_buf2_d4 <= 'd0; h_buf2_d5 <= 'd0; h_buf2_d6 <= 'd0; h_buf2_d7 <= 'd0;
h_buf3_d1 <= 'd0; h_buf3_d2 <= 'd0; h_buf3_d3 <= 'd0; h_buf3_d4 <= 'd0; h_buf3_d5 <= 'd0; h_buf3_d6 <= 'd0; h_buf3_d7 <= 'd0;
h_buf4_d1 <= 'd0; h_buf4_d2 <= 'd0; h_buf4_d3 <= 'd0; h_buf4_d4 <= 'd0; h_buf4_d5 <= 'd0; h_buf4_d6 <= 'd0; h_buf4_d7 <= 'd0;
h_buf5_d1 <= 'd0; h_buf5_d2 <= 'd0; h_buf5_d3 <= 'd0; h_buf5_d4 <= 'd0; h_buf5_d5 <= 'd0; h_buf5_d6 <= 'd0; h_buf5_d7 <= 'd0;
h_buf6_d1 <= 'd0; h_buf6_d2 <= 'd0; h_buf6_d3 <= 'd0; h_buf6_d4 <= 'd0; h_buf6_d5 <= 'd0; h_buf6_d6 <= 'd0; h_buf6_d7 <= 'd0;
h_buf7_d1 <= 'd0; h_buf7_d2 <= 'd0; h_buf7_d3 <= 'd0; h_buf7_d4 <= 'd0; h_buf7_d5 <= 'd0; h_buf7_d6 <= 'd0; h_buf7_d7 <= 'd0;
end
else if (horbuf_valid_i) begin
q1_buf0_d1 <= q1_buf0_i; q1_buf0_d2 <= q1_buf0_d1; q1_buf0_d3 <= q1_buf0_d2; q1_buf0_d4 <= q1_buf0_d3; q1_buf0_d5 <= q1_buf0_d4; q1_buf0_d6 <= q1_buf0_d5; q1_buf0_d7 <= q1_buf0_d6;
q1_buf1_d1 <= q1_buf1_i; q1_buf1_d2 <= q1_buf1_d1; q1_buf1_d3 <= q1_buf1_d2; q1_buf1_d4 <= q1_buf1_d3; q1_buf1_d5 <= q1_buf1_d4; q1_buf1_d6 <= q1_buf1_d5; q1_buf1_d7 <= q1_buf1_d6;
q1_buf2_d1 <= q1_buf2_i; q1_buf2_d2 <= q1_buf2_d1; q1_buf2_d3 <= q1_buf2_d2; q1_buf2_d4 <= q1_buf2_d3; q1_buf2_d5 <= q1_buf2_d4; q1_buf2_d6 <= q1_buf2_d5; q1_buf2_d7 <= q1_buf2_d6;
q1_buf3_d1 <= q1_buf3_i; q1_buf3_d2 <= q1_buf3_d1; q1_buf3_d3 <= q1_buf3_d2; q1_buf3_d4 <= q1_buf3_d3; q1_buf3_d5 <= q1_buf3_d4; q1_buf3_d6 <= q1_buf3_d5; q1_buf3_d7 <= q1_buf3_d6;
q1_buf4_d1 <= q1_buf4_i; q1_buf4_d2 <= q1_buf4_d1; q1_buf4_d3 <= q1_buf4_d2; q1_buf4_d4 <= q1_buf4_d3; q1_buf4_d5 <= q1_buf4_d4; q1_buf4_d6 <= q1_buf4_d5; q1_buf4_d7 <= q1_buf4_d6;
q1_buf5_d1 <= q1_buf5_i; q1_buf5_d2 <= q1_buf5_d1; q1_buf5_d3 <= q1_buf5_d2; q1_buf5_d4 <= q1_buf5_d3; q1_buf5_d5 <= q1_buf5_d4; q1_buf5_d6 <= q1_buf5_d5; q1_buf5_d7 <= q1_buf5_d6;
q1_buf6_d1 <= q1_buf6_i; q1_buf6_d2 <= q1_buf6_d1; q1_buf6_d3 <= q1_buf6_d2; q1_buf6_d4 <= q1_buf6_d3; q1_buf6_d5 <= q1_buf6_d4; q1_buf6_d6 <= q1_buf6_d5; q1_buf6_d7 <= q1_buf6_d6;
q1_buf7_d1 <= q1_buf7_i; q1_buf7_d2 <= q1_buf7_d1; q1_buf7_d3 <= q1_buf7_d2; q1_buf7_d4 <= q1_buf7_d3; q1_buf7_d5 <= q1_buf7_d4; q1_buf7_d6 <= q1_buf7_d5; q1_buf7_d7 <= q1_buf7_d6;
q3_buf0_d1 <= q3_buf0_i; q3_buf0_d2 <= q3_buf0_d1; q3_buf0_d3 <= q3_buf0_d2; q3_buf0_d4 <= q3_buf0_d3; q3_buf0_d5 <= q3_buf0_d4; q3_buf0_d6 <= q3_buf0_d5; q3_buf0_d7 <= q3_buf0_d6;
q3_buf1_d1 <= q3_buf1_i; q3_buf1_d2 <= q3_buf1_d1; q3_buf1_d3 <= q3_buf1_d2; q3_buf1_d4 <= q3_buf1_d3; q3_buf1_d5 <= q3_buf1_d4; q3_buf1_d6 <= q3_buf1_d5; q3_buf1_d7 <= q3_buf1_d6;
q3_buf2_d1 <= q3_buf2_i; q3_buf2_d2 <= q3_buf2_d1; q3_buf2_d3 <= q3_buf2_d2; q3_buf2_d4 <= q3_buf2_d3; q3_buf2_d5 <= q3_buf2_d4; q3_buf2_d6 <= q3_buf2_d5; q3_buf2_d7 <= q3_buf2_d6;
q3_buf3_d1 <= q3_buf3_i; q3_buf3_d2 <= q3_buf3_d1; q3_buf3_d3 <= q3_buf3_d2; q3_buf3_d4 <= q3_buf3_d3; q3_buf3_d5 <= q3_buf3_d4; q3_buf3_d6 <= q3_buf3_d5; q3_buf3_d7 <= q3_buf3_d6;
q3_buf4_d1 <= q3_buf4_i; q3_buf4_d2 <= q3_buf4_d1; q3_buf4_d3 <= q3_buf4_d2; q3_buf4_d4 <= q3_buf4_d3; q3_buf4_d5 <= q3_buf4_d4; q3_buf4_d6 <= q3_buf4_d5; q3_buf4_d7 <= q3_buf4_d6;
q3_buf5_d1 <= q3_buf5_i; q3_buf5_d2 <= q3_buf5_d1; q3_buf5_d3 <= q3_buf5_d2; q3_buf5_d4 <= q3_buf5_d3; q3_buf5_d5 <= q3_buf5_d4; q3_buf5_d6 <= q3_buf5_d5; q3_buf5_d7 <= q3_buf5_d6;
q3_buf6_d1 <= q3_buf6_i; q3_buf6_d2 <= q3_buf6_d1; q3_buf6_d3 <= q3_buf6_d2; q3_buf6_d4 <= q3_buf6_d3; q3_buf6_d5 <= q3_buf6_d4; q3_buf6_d6 <= q3_buf6_d5; q3_buf6_d7 <= q3_buf6_d6;
q3_buf7_d1 <= q3_buf7_i; q3_buf7_d2 <= q3_buf7_d1; q3_buf7_d3 <= q3_buf7_d2; q3_buf7_d4 <= q3_buf7_d3; q3_buf7_d5 <= q3_buf7_d4; q3_buf7_d6 <= q3_buf7_d5; q3_buf7_d7 <= q3_buf7_d6;
h_buf0_d1 <= h_buf0_i; h_buf0_d2 <= h_buf0_d1; h_buf0_d3 <= h_buf0_d2; h_buf0_d4 <= h_buf0_d3; h_buf0_d5 <= h_buf0_d4; h_buf0_d6 <= h_buf0_d5; h_buf0_d7 <= h_buf0_d6;
h_buf1_d1 <= h_buf1_i; h_buf1_d2 <= h_buf1_d1; h_buf1_d3 <= h_buf1_d2; h_buf1_d4 <= h_buf1_d3; h_buf1_d5 <= h_buf1_d4; h_buf1_d6 <= h_buf1_d5; h_buf1_d7 <= h_buf1_d6;
h_buf2_d1 <= h_buf2_i; h_buf2_d2 <= h_buf2_d1; h_buf2_d3 <= h_buf2_d2; h_buf2_d4 <= h_buf2_d3; h_buf2_d5 <= h_buf2_d4; h_buf2_d6 <= h_buf2_d5; h_buf2_d7 <= h_buf2_d6;
h_buf3_d1 <= h_buf3_i; h_buf3_d2 <= h_buf3_d1; h_buf3_d3 <= h_buf3_d2; h_buf3_d4 <= h_buf3_d3; h_buf3_d5 <= h_buf3_d4; h_buf3_d6 <= h_buf3_d5; h_buf3_d7 <= h_buf3_d6;
h_buf4_d1 <= h_buf4_i; h_buf4_d2 <= h_buf4_d1; h_buf4_d3 <= h_buf4_d2; h_buf4_d4 <= h_buf4_d3; h_buf4_d5 <= h_buf4_d4; h_buf4_d6 <= h_buf4_d5; h_buf4_d7 <= h_buf4_d6;
h_buf5_d1 <= h_buf5_i; h_buf5_d2 <= h_buf5_d1; h_buf5_d3 <= h_buf5_d2; h_buf5_d4 <= h_buf5_d3; h_buf5_d5 <= h_buf5_d4; h_buf5_d6 <= h_buf5_d5; h_buf5_d7 <= h_buf5_d6;
h_buf6_d1 <= h_buf6_i; h_buf6_d2 <= h_buf6_d1; h_buf6_d3 <= h_buf6_d2; h_buf6_d4 <= h_buf6_d3; h_buf6_d5 <= h_buf6_d4; h_buf6_d6 <= h_buf6_d5; h_buf6_d7 <= h_buf6_d6;
h_buf7_d1 <= h_buf7_i; h_buf7_d2 <= h_buf7_d1; h_buf7_d3 <= h_buf7_d2; h_buf7_d4 <= h_buf7_d3; h_buf7_d5 <= h_buf7_d4; h_buf7_d6 <= h_buf7_d5; h_buf7_d7 <= h_buf7_d6;
end
end
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
cnt_hor <= 'd0;
end
else if(horbuf_valid_i) begin
cnt_hor <= cnt_hor + 'd1;
end
end
always @ (posedge clk or negedge rstn ) begin
if (~rstn) begin
ref_pel0_d1 <= 'd0; ref_pel0_d2 <= 'd0; ref_pel0_d3 <= 'd0; ref_pel0_d4 <= 'd0; ref_pel0_d5 <= 'd0; ref_pel0_d6 <= 'd0; ref_pel0_d7 <= 'd0;
ref_pel1_d1 <= 'd0; ref_pel1_d2 <= 'd0; ref_pel1_d3 <= 'd0; ref_pel1_d4 <= 'd0; ref_pel1_d5 <= 'd0; ref_pel1_d6 <= 'd0; ref_pel1_d7 <= 'd0;
ref_pel2_d1 <= 'd0; ref_pel2_d2 <= 'd0; ref_pel2_d3 <= 'd0; ref_pel2_d4 <= 'd0; ref_pel2_d5 <= 'd0; ref_pel2_d6 <= 'd0; ref_pel2_d7 <= 'd0;
ref_pel3_d1 <= 'd0; ref_pel3_d2 <= 'd0; ref_pel3_d3 <= 'd0; ref_pel3_d4 <= 'd0; ref_pel3_d5 <= 'd0; ref_pel3_d6 <= 'd0; ref_pel3_d7 <= 'd0;
ref_pel4_d1 <= 'd0; ref_pel4_d2 <= 'd0; ref_pel4_d3 <= 'd0; ref_pel4_d4 <= 'd0; ref_pel4_d5 <= 'd0; ref_pel4_d6 <= 'd0; ref_pel4_d7 <= 'd0;
ref_pel5_d1 <= 'd0; ref_pel5_d2 <= 'd0; ref_pel5_d3 <= 'd0; ref_pel5_d4 <= 'd0; ref_pel5_d5 <= 'd0; ref_pel5_d6 <= 'd0; ref_pel5_d7 <= 'd0;
ref_pel6_d1 <= 'd0; ref_pel6_d2 <= 'd0; ref_pel6_d3 <= 'd0; ref_pel6_d4 <= 'd0; ref_pel6_d5 <= 'd0; ref_pel6_d6 <= 'd0; ref_pel6_d7 <= 'd0;
ref_pel7_d1 <= 'd0; ref_pel7_d2 <= 'd0; ref_pel7_d3 <= 'd0; ref_pel7_d4 <= 'd0; ref_pel7_d5 <= 'd0; ref_pel7_d6 <= 'd0; ref_pel7_d7 <= 'd0;
end
else if (refpel_valid_i) begin
ref_pel0_d1 <= ref_pel0_i; ref_pel0_d2 <= ref_pel0_d1; ref_pel0_d3 <= ref_pel0_d2; ref_pel0_d4 <= ref_pel0_d3; ref_pel0_d5 <= ref_pel0_d4; ref_pel0_d6 <= ref_pel0_d5; ref_pel0_d7 <= ref_pel0_d6;
ref_pel1_d1 <= ref_pel1_i; ref_pel1_d2 <= ref_pel1_d1; ref_pel1_d3 <= ref_pel1_d2; ref_pel1_d4 <= ref_pel1_d3; ref_pel1_d5 <= ref_pel1_d4; ref_pel1_d6 <= ref_pel1_d5; ref_pel1_d7 <= ref_pel1_d6;
ref_pel2_d1 <= ref_pel2_i; ref_pel2_d2 <= ref_pel2_d1; ref_pel2_d3 <= ref_pel2_d2; ref_pel2_d4 <= ref_pel2_d3; ref_pel2_d5 <= ref_pel2_d4; ref_pel2_d6 <= ref_pel2_d5; ref_pel2_d7 <= ref_pel2_d6;
ref_pel3_d1 <= ref_pel3_i; ref_pel3_d2 <= ref_pel3_d1; ref_pel3_d3 <= ref_pel3_d2; ref_pel3_d4 <= ref_pel3_d3; ref_pel3_d5 <= ref_pel3_d4; ref_pel3_d6 <= ref_pel3_d5; ref_pel3_d7 <= ref_pel3_d6;
ref_pel4_d1 <= ref_pel4_i; ref_pel4_d2 <= ref_pel4_d1; ref_pel4_d3 <= ref_pel4_d2; ref_pel4_d4 <= ref_pel4_d3; ref_pel4_d5 <= ref_pel4_d4; ref_pel4_d6 <= ref_pel4_d5; ref_pel4_d7 <= ref_pel4_d6;
ref_pel5_d1 <= ref_pel5_i; ref_pel5_d2 <= ref_pel5_d1; ref_pel5_d3 <= ref_pel5_d2; ref_pel5_d4 <= ref_pel5_d3; ref_pel5_d5 <= ref_pel5_d4; ref_pel5_d6 <= ref_pel5_d5; ref_pel5_d7 <= ref_pel5_d6;
ref_pel6_d1 <= ref_pel6_i; ref_pel6_d2 <= ref_pel6_d1; ref_pel6_d3 <= ref_pel6_d2; ref_pel6_d4 <= ref_pel6_d3; ref_pel6_d5 <= ref_pel6_d4; ref_pel6_d6 <= ref_pel6_d5; ref_pel6_d7 <= ref_pel6_d6;
ref_pel7_d1 <= ref_pel7_i; ref_pel7_d2 <= ref_pel7_d1; ref_pel7_d3 <= ref_pel7_d2; ref_pel7_d4 <= ref_pel7_d3; ref_pel7_d5 <= ref_pel7_d4; ref_pel7_d6 <= ref_pel7_d5; ref_pel7_d7 <= ref_pel7_d6;
end
end
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
cnt_ref <= 'd0;
end
else if(refpel_valid_i) begin
cnt_ref <= cnt_ref + 'd1;
end
end
// ********************************************
//
// Sub Module
//
// ********************************************
// vertical quarter 1 interpolator
// from q1
//
//
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_0 (
.tap_0_i( q1_buf0_d7 ) ,
.tap_1_i( q1_buf0_d6 ) ,
.tap_2_i( q1_buf0_d5 ) ,
.tap_3_i( q1_buf0_d4 ) ,
.tap_4_i( q1_buf0_d3 ) ,
.tap_5_i( q1_buf0_d2 ) ,
.tap_6_i( q1_buf0_d1 ) ,
.tap_7_i( q1_buf0_i ) ,
.val_o ( vquarter_1_1_pel0_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_1 (
.tap_0_i( q1_buf1_d7 ) ,
.tap_1_i( q1_buf1_d6 ) ,
.tap_2_i( q1_buf1_d5 ) ,
.tap_3_i( q1_buf1_d4 ) ,
.tap_4_i( q1_buf1_d3 ) ,
.tap_5_i( q1_buf1_d2 ) ,
.tap_6_i( q1_buf1_d1 ) ,
.tap_7_i( q1_buf1_i ) ,
.val_o ( vquarter_1_1_pel1_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_2 (
.tap_0_i( q1_buf2_d7 ) ,
.tap_1_i( q1_buf2_d6 ) ,
.tap_2_i( q1_buf2_d5 ) ,
.tap_3_i( q1_buf2_d4 ) ,
.tap_4_i( q1_buf2_d3 ) ,
.tap_5_i( q1_buf2_d2 ) ,
.tap_6_i( q1_buf2_d1 ) ,
.tap_7_i( q1_buf2_i ) ,
.val_o ( vquarter_1_1_pel2_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_3 (
.tap_0_i( q1_buf3_d7 ) ,
.tap_1_i( q1_buf3_d6 ) ,
.tap_2_i( q1_buf3_d5 ) ,
.tap_3_i( q1_buf3_d4 ) ,
.tap_4_i( q1_buf3_d3 ) ,
.tap_5_i( q1_buf3_d2 ) ,
.tap_6_i( q1_buf3_d1 ) ,
.tap_7_i( q1_buf3_i ) ,
.val_o ( vquarter_1_1_pel3_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_4 (
.tap_0_i( q1_buf4_d7 ) ,
.tap_1_i( q1_buf4_d6 ) ,
.tap_2_i( q1_buf4_d5 ) ,
.tap_3_i( q1_buf4_d4 ) ,
.tap_4_i( q1_buf4_d3 ) ,
.tap_5_i( q1_buf4_d2 ) ,
.tap_6_i( q1_buf4_d1 ) ,
.tap_7_i( q1_buf4_i ) ,
.val_o ( vquarter_1_1_pel4_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_5 (
.tap_0_i( q1_buf5_d7 ) ,
.tap_1_i( q1_buf5_d6 ) ,
.tap_2_i( q1_buf5_d5 ) ,
.tap_3_i( q1_buf5_d4 ) ,
.tap_4_i( q1_buf5_d3 ) ,
.tap_5_i( q1_buf5_d2 ) ,
.tap_6_i( q1_buf5_d1 ) ,
.tap_7_i( q1_buf5_i ) ,
.val_o ( vquarter_1_1_pel5_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_6 (
.tap_0_i( q1_buf6_d7 ) ,
.tap_1_i( q1_buf6_d6 ) ,
.tap_2_i( q1_buf6_d5 ) ,
.tap_3_i( q1_buf6_d4 ) ,
.tap_4_i( q1_buf6_d3 ) ,
.tap_5_i( q1_buf6_d2 ) ,
.tap_6_i( q1_buf6_d1 ) ,
.tap_7_i( q1_buf6_i ) ,
.val_o ( vquarter_1_1_pel6_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_1_7 (
.tap_0_i( q1_buf7_d7 ) ,
.tap_1_i( q1_buf7_d6 ) ,
.tap_2_i( q1_buf7_d5 ) ,
.tap_3_i( q1_buf7_d4 ) ,
.tap_4_i( q1_buf7_d3 ) ,
.tap_5_i( q1_buf7_d2 ) ,
.tap_6_i( q1_buf7_d1 ) ,
.tap_7_i( q1_buf7_i ) ,
.val_o ( vquarter_1_1_pel7_o)
);
// from q3
// q3_buf0_d7
// q3_buf0_d6
// q3_buf0_d5
// q3_buf0_d4
// q3_buf0_d3
// q3_buf0_d2
// q3_buf0_d1
// q3_buf0_i
//
//
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_0 (
.tap_0_i( q3_buf0_d7 ) ,
.tap_1_i( q3_buf0_d6 ) ,
.tap_2_i( q3_buf0_d5 ) ,
.tap_3_i( q3_buf0_d4 ) ,
.tap_4_i( q3_buf0_d3 ) ,
.tap_5_i( q3_buf0_d2 ) ,
.tap_6_i( q3_buf0_d1 ) ,
.tap_7_i( q3_buf0_i ) ,
.val_o ( vquarter_1_3_pel0_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_1 (
.tap_0_i( q3_buf1_d7 ) ,
.tap_1_i( q3_buf1_d6 ) ,
.tap_2_i( q3_buf1_d5 ) ,
.tap_3_i( q3_buf1_d4 ) ,
.tap_4_i( q3_buf1_d3 ) ,
.tap_5_i( q3_buf1_d2 ) ,
.tap_6_i( q3_buf1_d1 ) ,
.tap_7_i( q3_buf1_i ) ,
.val_o ( vquarter_1_3_pel1_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_2 (
.tap_0_i( q3_buf2_d7 ) ,
.tap_1_i( q3_buf2_d6 ) ,
.tap_2_i( q3_buf2_d5 ) ,
.tap_3_i( q3_buf2_d4 ) ,
.tap_4_i( q3_buf2_d3 ) ,
.tap_5_i( q3_buf2_d2 ) ,
.tap_6_i( q3_buf2_d1 ) ,
.tap_7_i( q3_buf2_i ) ,
.val_o ( vquarter_1_3_pel2_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_3 (
.tap_0_i( q3_buf3_d7 ) ,
.tap_1_i( q3_buf3_d6 ) ,
.tap_2_i( q3_buf3_d5 ) ,
.tap_3_i( q3_buf3_d4 ) ,
.tap_4_i( q3_buf3_d3 ) ,
.tap_5_i( q3_buf3_d2 ) ,
.tap_6_i( q3_buf3_d1 ) ,
.tap_7_i( q3_buf3_i ) ,
.val_o ( vquarter_1_3_pel3_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_4 (
.tap_0_i( q3_buf4_d7 ) ,
.tap_1_i( q3_buf4_d6 ) ,
.tap_2_i( q3_buf4_d5 ) ,
.tap_3_i( q3_buf4_d4 ) ,
.tap_4_i( q3_buf4_d3 ) ,
.tap_5_i( q3_buf4_d2 ) ,
.tap_6_i( q3_buf4_d1 ) ,
.tap_7_i( q3_buf4_i ) ,
.val_o ( vquarter_1_3_pel4_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_5 (
.tap_0_i( q3_buf5_d7 ) ,
.tap_1_i( q3_buf5_d6 ) ,
.tap_2_i( q3_buf5_d5 ) ,
.tap_3_i( q3_buf5_d4 ) ,
.tap_4_i( q3_buf5_d3 ) ,
.tap_5_i( q3_buf5_d2 ) ,
.tap_6_i( q3_buf5_d1 ) ,
.tap_7_i( q3_buf5_i ) ,
.val_o ( vquarter_1_3_pel5_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_6 (
.tap_0_i( q3_buf6_d7 ) ,
.tap_1_i( q3_buf6_d6 ) ,
.tap_2_i( q3_buf6_d5 ) ,
.tap_3_i( q3_buf6_d4 ) ,
.tap_4_i( q3_buf6_d3 ) ,
.tap_5_i( q3_buf6_d2 ) ,
.tap_6_i( q3_buf6_d1 ) ,
.tap_7_i( q3_buf6_i ) ,
.val_o ( vquarter_1_3_pel6_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_3_7 (
.tap_0_i( q3_buf7_d7 ) ,
.tap_1_i( q3_buf7_d6 ) ,
.tap_2_i( q3_buf7_d5 ) ,
.tap_3_i( q3_buf7_d4 ) ,
.tap_4_i( q3_buf7_d3 ) ,
.tap_5_i( q3_buf7_d2 ) ,
.tap_6_i( q3_buf7_d1 ) ,
.tap_7_i( q3_buf7_i ) ,
.val_o ( vquarter_1_3_pel7_o)
);
//from half buf
// h_buf0_d7
// h_buf0_d6
// h_buf0_d5
// h_buf0_d4
// h_buf0_d3
// h_buf0_d2
// h_buf0_d1
// h_buf0_i
//
//
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_0 (
.tap_0_i( h_buf0_d7 ) ,
.tap_1_i( h_buf0_d6 ) ,
.tap_2_i( h_buf0_d5 ) ,
.tap_3_i( h_buf0_d4 ) ,
.tap_4_i( h_buf0_d3 ) ,
.tap_5_i( h_buf0_d2 ) ,
.tap_6_i( h_buf0_d1 ) ,
.tap_7_i( h_buf0_i ) ,
.val_o ( vquarter_1_2_pel0_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_1 (
.tap_0_i( h_buf1_d7 ) ,
.tap_1_i( h_buf1_d6 ) ,
.tap_2_i( h_buf1_d5 ) ,
.tap_3_i( h_buf1_d4 ) ,
.tap_4_i( h_buf1_d3 ) ,
.tap_5_i( h_buf1_d2 ) ,
.tap_6_i( h_buf1_d1 ) ,
.tap_7_i( h_buf1_i ) ,
.val_o ( vquarter_1_2_pel1_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_2 (
.tap_0_i( h_buf2_d7 ) ,
.tap_1_i( h_buf2_d6 ) ,
.tap_2_i( h_buf2_d5 ) ,
.tap_3_i( h_buf2_d4 ) ,
.tap_4_i( h_buf2_d3 ) ,
.tap_5_i( h_buf2_d2 ) ,
.tap_6_i( h_buf2_d1 ) ,
.tap_7_i( h_buf2_i ) ,
.val_o ( vquarter_1_2_pel2_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_3 (
.tap_0_i( h_buf3_d7 ) ,
.tap_1_i( h_buf3_d6 ) ,
.tap_2_i( h_buf3_d5 ) ,
.tap_3_i( h_buf3_d4 ) ,
.tap_4_i( h_buf3_d3 ) ,
.tap_5_i( h_buf3_d2 ) ,
.tap_6_i( h_buf3_d1 ) ,
.tap_7_i( h_buf3_i ) ,
.val_o ( vquarter_1_2_pel3_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_4 (
.tap_0_i( h_buf4_d7 ) ,
.tap_1_i( h_buf4_d6 ) ,
.tap_2_i( h_buf4_d5 ) ,
.tap_3_i( h_buf4_d4 ) ,
.tap_4_i( h_buf4_d3 ) ,
.tap_5_i( h_buf4_d2 ) ,
.tap_6_i( h_buf4_d1 ) ,
.tap_7_i( h_buf4_i ) ,
.val_o ( vquarter_1_2_pel4_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_5 (
.tap_0_i( h_buf5_d7 ) ,
.tap_1_i( h_buf5_d6 ) ,
.tap_2_i( h_buf5_d5 ) ,
.tap_3_i( h_buf5_d4 ) ,
.tap_4_i( h_buf5_d3 ) ,
.tap_5_i( h_buf5_d2 ) ,
.tap_6_i( h_buf5_d1 ) ,
.tap_7_i( h_buf5_i ) ,
.val_o ( vquarter_1_2_pel5_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_6 (
.tap_0_i( h_buf6_d7 ) ,
.tap_1_i( h_buf6_d6 ) ,
.tap_2_i( h_buf6_d5 ) ,
.tap_3_i( h_buf6_d4 ) ,
.tap_4_i( h_buf6_d3 ) ,
.tap_5_i( h_buf6_d2 ) ,
.tap_6_i( h_buf6_d1 ) ,
.tap_7_i( h_buf6_i ) ,
.val_o ( vquarter_1_2_pel6_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_1_2_7 (
.tap_0_i( h_buf7_d7 ) ,
.tap_1_i( h_buf7_d6 ) ,
.tap_2_i( h_buf7_d5 ) ,
.tap_3_i( h_buf7_d4 ) ,
.tap_4_i( h_buf7_d3 ) ,
.tap_5_i( h_buf7_d2 ) ,
.tap_6_i( h_buf7_d1 ) ,
.tap_7_i( h_buf7_i ) ,
.val_o ( vquarter_1_2_pel7_o)
);
// from ref
// ref_pel0_d7
// ref_pel0_d6
// ref_pel0_d5
// ref_pel0_d4
// ref_pel0_d3
// ref_pel0_d2
// ref_pel0_d1
// ref_pel0_i
//
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_0 (
.tap_0_i( ref_pel0_d7 ) ,
.tap_1_i( ref_pel0_d6 ) ,
.tap_2_i( ref_pel0_d5 ) ,
.tap_3_i( ref_pel0_d4 ) ,
.tap_4_i( ref_pel0_d3 ) ,
.tap_5_i( ref_pel0_d2 ) ,
.tap_6_i( ref_pel0_d1 ) ,
.tap_7_i( ref_pel0_i ) ,
.val_o ( vquarter_1_0_pel0_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_1 (
.tap_0_i( ref_pel1_d7 ) ,
.tap_1_i( ref_pel1_d6 ) ,
.tap_2_i( ref_pel1_d5 ) ,
.tap_3_i( ref_pel1_d4 ) ,
.tap_4_i( ref_pel1_d3 ) ,
.tap_5_i( ref_pel1_d2 ) ,
.tap_6_i( ref_pel1_d1 ) ,
.tap_7_i( ref_pel1_i ) ,
.val_o ( vquarter_1_0_pel1_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_2 (
.tap_0_i( ref_pel2_d7 ) ,
.tap_1_i( ref_pel2_d6 ) ,
.tap_2_i( ref_pel2_d5 ) ,
.tap_3_i( ref_pel2_d4 ) ,
.tap_4_i( ref_pel2_d3 ) ,
.tap_5_i( ref_pel2_d2 ) ,
.tap_6_i( ref_pel2_d1 ) ,
.tap_7_i( ref_pel2_i ) ,
.val_o ( vquarter_1_0_pel2_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_3 (
.tap_0_i( ref_pel3_d7 ) ,
.tap_1_i( ref_pel3_d6 ) ,
.tap_2_i( ref_pel3_d5 ) ,
.tap_3_i( ref_pel3_d4 ) ,
.tap_4_i( ref_pel3_d3 ) ,
.tap_5_i( ref_pel3_d2 ) ,
.tap_6_i( ref_pel3_d1 ) ,
.tap_7_i( ref_pel3_i ) ,
.val_o ( vquarter_1_0_pel3_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_4 (
.tap_0_i( ref_pel4_d7 ) ,
.tap_1_i( ref_pel4_d6 ) ,
.tap_2_i( ref_pel4_d5 ) ,
.tap_3_i( ref_pel4_d4 ) ,
.tap_4_i( ref_pel4_d3 ) ,
.tap_5_i( ref_pel4_d2 ) ,
.tap_6_i( ref_pel4_d1 ) ,
.tap_7_i( ref_pel4_i ) ,
.val_o ( vquarter_1_0_pel4_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_5 (
.tap_0_i( ref_pel5_d7 ) ,
.tap_1_i( ref_pel5_d6 ) ,
.tap_2_i( ref_pel5_d5 ) ,
.tap_3_i( ref_pel5_d4 ) ,
.tap_4_i( ref_pel5_d3 ) ,
.tap_5_i( ref_pel5_d2 ) ,
.tap_6_i( ref_pel5_d1 ) ,
.tap_7_i( ref_pel5_i ) ,
.val_o ( vquarter_1_0_pel5_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_6 (
.tap_0_i( ref_pel6_d7 ) ,
.tap_1_i( ref_pel6_d6 ) ,
.tap_2_i( ref_pel6_d5 ) ,
.tap_3_i( ref_pel6_d4 ) ,
.tap_4_i( ref_pel6_d3 ) ,
.tap_5_i( ref_pel6_d2 ) ,
.tap_6_i( ref_pel6_d1 ) ,
.tap_7_i( ref_pel6_i ) ,
.val_o ( vquarter_1_0_pel6_o)
);
fme_interpolator #(
.TYPE(1),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_1_0_7 (
.tap_0_i( ref_pel7_d7 ) ,
.tap_1_i( ref_pel7_d6 ) ,
.tap_2_i( ref_pel7_d5 ) ,
.tap_3_i( ref_pel7_d4 ) ,
.tap_4_i( ref_pel7_d3 ) ,
.tap_5_i( ref_pel7_d2 ) ,
.tap_6_i( ref_pel7_d1 ) ,
.tap_7_i( ref_pel7_i ) ,
.val_o ( vquarter_1_0_pel7_o)
);
// vertical quarter 3 interpolator
// from 1
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_0 (
.tap_0_i( q1_buf0_d7 ) ,
.tap_1_i( q1_buf0_d6 ) ,
.tap_2_i( q1_buf0_d5 ) ,
.tap_3_i( q1_buf0_d4 ) ,
.tap_4_i( q1_buf0_d3 ) ,
.tap_5_i( q1_buf0_d2 ) ,
.tap_6_i( q1_buf0_d1 ) ,
.tap_7_i( q1_buf0_i ) ,
.val_o ( vquarter_3_1_pel0_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_1 (
.tap_0_i( q1_buf1_d7 ) ,
.tap_1_i( q1_buf1_d6 ) ,
.tap_2_i( q1_buf1_d5 ) ,
.tap_3_i( q1_buf1_d4 ) ,
.tap_4_i( q1_buf1_d3 ) ,
.tap_5_i( q1_buf1_d2 ) ,
.tap_6_i( q1_buf1_d1 ) ,
.tap_7_i( q1_buf1_i ) ,
.val_o ( vquarter_3_1_pel1_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_2 (
.tap_0_i( q1_buf2_d7 ) ,
.tap_1_i( q1_buf2_d6 ) ,
.tap_2_i( q1_buf2_d5 ) ,
.tap_3_i( q1_buf2_d4 ) ,
.tap_4_i( q1_buf2_d3 ) ,
.tap_5_i( q1_buf2_d2 ) ,
.tap_6_i( q1_buf2_d1 ) ,
.tap_7_i( q1_buf2_i ) ,
.val_o ( vquarter_3_1_pel2_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_3 (
.tap_0_i( q1_buf3_d7 ) ,
.tap_1_i( q1_buf3_d6 ) ,
.tap_2_i( q1_buf3_d5 ) ,
.tap_3_i( q1_buf3_d4 ) ,
.tap_4_i( q1_buf3_d3 ) ,
.tap_5_i( q1_buf3_d2 ) ,
.tap_6_i( q1_buf3_d1 ) ,
.tap_7_i( q1_buf3_i ) ,
.val_o ( vquarter_3_1_pel3_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_4 (
.tap_0_i( q1_buf4_d7 ) ,
.tap_1_i( q1_buf4_d6 ) ,
.tap_2_i( q1_buf4_d5 ) ,
.tap_3_i( q1_buf4_d4 ) ,
.tap_4_i( q1_buf4_d3 ) ,
.tap_5_i( q1_buf4_d2 ) ,
.tap_6_i( q1_buf4_d1 ) ,
.tap_7_i( q1_buf4_i ) ,
.val_o ( vquarter_3_1_pel4_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_5 (
.tap_0_i( q1_buf5_d7 ) ,
.tap_1_i( q1_buf5_d6 ) ,
.tap_2_i( q1_buf5_d5 ) ,
.tap_3_i( q1_buf5_d4 ) ,
.tap_4_i( q1_buf5_d3 ) ,
.tap_5_i( q1_buf5_d2 ) ,
.tap_6_i( q1_buf5_d1 ) ,
.tap_7_i( q1_buf5_i ) ,
.val_o ( vquarter_3_1_pel5_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_6 (
.tap_0_i( q1_buf6_d7 ) ,
.tap_1_i( q1_buf6_d6 ) ,
.tap_2_i( q1_buf6_d5 ) ,
.tap_3_i( q1_buf6_d4 ) ,
.tap_4_i( q1_buf6_d3 ) ,
.tap_5_i( q1_buf6_d2 ) ,
.tap_6_i( q1_buf6_d1 ) ,
.tap_7_i( q1_buf6_i ) ,
.val_o ( vquarter_3_1_pel6_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_1_7 (
.tap_0_i( q1_buf7_d7 ) ,
.tap_1_i( q1_buf7_d6 ) ,
.tap_2_i( q1_buf7_d5 ) ,
.tap_3_i( q1_buf7_d4 ) ,
.tap_4_i( q1_buf7_d3 ) ,
.tap_5_i( q1_buf7_d2 ) ,
.tap_6_i( q1_buf7_d1 ) ,
.tap_7_i( q1_buf7_i ) ,
.val_o ( vquarter_3_1_pel7_o)
);
// from 3
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_0 (
.tap_0_i( q3_buf0_d7 ) ,
.tap_1_i( q3_buf0_d6 ) ,
.tap_2_i( q3_buf0_d5 ) ,
.tap_3_i( q3_buf0_d4 ) ,
.tap_4_i( q3_buf0_d3 ) ,
.tap_5_i( q3_buf0_d2 ) ,
.tap_6_i( q3_buf0_d1 ) ,
.tap_7_i( q3_buf0_i ) ,
.val_o ( vquarter_3_3_pel0_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_1 (
.tap_0_i( q3_buf1_d7 ) ,
.tap_1_i( q3_buf1_d6 ) ,
.tap_2_i( q3_buf1_d5 ) ,
.tap_3_i( q3_buf1_d4 ) ,
.tap_4_i( q3_buf1_d3 ) ,
.tap_5_i( q3_buf1_d2 ) ,
.tap_6_i( q3_buf1_d1 ) ,
.tap_7_i( q3_buf1_i ) ,
.val_o ( vquarter_3_3_pel1_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_2 (
.tap_0_i( q3_buf2_d7 ) ,
.tap_1_i( q3_buf2_d6 ) ,
.tap_2_i( q3_buf2_d5 ) ,
.tap_3_i( q3_buf2_d4 ) ,
.tap_4_i( q3_buf2_d3 ) ,
.tap_5_i( q3_buf2_d2 ) ,
.tap_6_i( q3_buf2_d1 ) ,
.tap_7_i( q3_buf2_i ) ,
.val_o ( vquarter_3_3_pel2_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_3 (
.tap_0_i( q3_buf3_d7 ) ,
.tap_1_i( q3_buf3_d6 ) ,
.tap_2_i( q3_buf3_d5 ) ,
.tap_3_i( q3_buf3_d4 ) ,
.tap_4_i( q3_buf3_d3 ) ,
.tap_5_i( q3_buf3_d2 ) ,
.tap_6_i( q3_buf3_d1 ) ,
.tap_7_i( q3_buf3_i ) ,
.val_o ( vquarter_3_3_pel3_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_4 (
.tap_0_i( q3_buf4_d7 ) ,
.tap_1_i( q3_buf4_d6 ) ,
.tap_2_i( q3_buf4_d5 ) ,
.tap_3_i( q3_buf4_d4 ) ,
.tap_4_i( q3_buf4_d3 ) ,
.tap_5_i( q3_buf4_d2 ) ,
.tap_6_i( q3_buf4_d1 ) ,
.tap_7_i( q3_buf4_i ) ,
.val_o ( vquarter_3_3_pel4_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_5 (
.tap_0_i( q3_buf5_d7 ) ,
.tap_1_i( q3_buf5_d6 ) ,
.tap_2_i( q3_buf5_d5 ) ,
.tap_3_i( q3_buf5_d4 ) ,
.tap_4_i( q3_buf5_d3 ) ,
.tap_5_i( q3_buf5_d2 ) ,
.tap_6_i( q3_buf5_d1 ) ,
.tap_7_i( q3_buf5_i ) ,
.val_o ( vquarter_3_3_pel5_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_6 (
.tap_0_i( q3_buf6_d7 ) ,
.tap_1_i( q3_buf6_d6 ) ,
.tap_2_i( q3_buf6_d5 ) ,
.tap_3_i( q3_buf6_d4 ) ,
.tap_4_i( q3_buf6_d3 ) ,
.tap_5_i( q3_buf6_d2 ) ,
.tap_6_i( q3_buf6_d1 ) ,
.tap_7_i( q3_buf6_i ) ,
.val_o ( vquarter_3_3_pel6_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_3_7 (
.tap_0_i( q3_buf7_d7 ) ,
.tap_1_i( q3_buf7_d6 ) ,
.tap_2_i( q3_buf7_d5 ) ,
.tap_3_i( q3_buf7_d4 ) ,
.tap_4_i( q3_buf7_d3 ) ,
.tap_5_i( q3_buf7_d2 ) ,
.tap_6_i( q3_buf7_d1 ) ,
.tap_7_i( q3_buf7_i ) ,
.val_o ( vquarter_3_3_pel7_o)
);
// from half
// h_buf0_d7
// h_buf0_d6
// h_buf0_d5
// h_buf0_d4
// h_buf0_d3
// h_buf0_d2
// h_buf0_d1
// h_buf0_i
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_0 (
.tap_0_i( h_buf0_d7 ) ,
.tap_1_i( h_buf0_d6 ) ,
.tap_2_i( h_buf0_d5 ) ,
.tap_3_i( h_buf0_d4 ) ,
.tap_4_i( h_buf0_d3 ) ,
.tap_5_i( h_buf0_d2 ) ,
.tap_6_i( h_buf0_d1 ) ,
.tap_7_i( h_buf0_i ) ,
.val_o ( vquarter_3_2_pel0_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_1 (
.tap_0_i( h_buf1_d7 ) ,
.tap_1_i( h_buf1_d6 ) ,
.tap_2_i( h_buf1_d5 ) ,
.tap_3_i( h_buf1_d4 ) ,
.tap_4_i( h_buf1_d3 ) ,
.tap_5_i( h_buf1_d2 ) ,
.tap_6_i( h_buf1_d1 ) ,
.tap_7_i( h_buf1_i ) ,
.val_o ( vquarter_3_2_pel1_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_2 (
.tap_0_i( h_buf2_d7 ) ,
.tap_1_i( h_buf2_d6 ) ,
.tap_2_i( h_buf2_d5 ) ,
.tap_3_i( h_buf2_d4 ) ,
.tap_4_i( h_buf2_d3 ) ,
.tap_5_i( h_buf2_d2 ) ,
.tap_6_i( h_buf2_d1 ) ,
.tap_7_i( h_buf2_i ) ,
.val_o ( vquarter_3_2_pel2_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_3 (
.tap_0_i( h_buf3_d7 ) ,
.tap_1_i( h_buf3_d6 ) ,
.tap_2_i( h_buf3_d5 ) ,
.tap_3_i( h_buf3_d4 ) ,
.tap_4_i( h_buf3_d3 ) ,
.tap_5_i( h_buf3_d2 ) ,
.tap_6_i( h_buf3_d1 ) ,
.tap_7_i( h_buf3_i ) ,
.val_o ( vquarter_3_2_pel3_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_4 (
.tap_0_i( h_buf4_d7 ) ,
.tap_1_i( h_buf4_d6 ) ,
.tap_2_i( h_buf4_d5 ) ,
.tap_3_i( h_buf4_d4 ) ,
.tap_4_i( h_buf4_d3 ) ,
.tap_5_i( h_buf4_d2 ) ,
.tap_6_i( h_buf4_d1 ) ,
.tap_7_i( h_buf4_i ) ,
.val_o ( vquarter_3_2_pel4_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_5 (
.tap_0_i( h_buf5_d7 ) ,
.tap_1_i( h_buf5_d6 ) ,
.tap_2_i( h_buf5_d5 ) ,
.tap_3_i( h_buf5_d4 ) ,
.tap_4_i( h_buf5_d3 ) ,
.tap_5_i( h_buf5_d2 ) ,
.tap_6_i( h_buf5_d1 ) ,
.tap_7_i( h_buf5_i ) ,
.val_o ( vquarter_3_2_pel5_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_6 (
.tap_0_i( h_buf6_d7 ) ,
.tap_1_i( h_buf6_d6 ) ,
.tap_2_i( h_buf6_d5 ) ,
.tap_3_i( h_buf6_d4 ) ,
.tap_4_i( h_buf6_d3 ) ,
.tap_5_i( h_buf6_d2 ) ,
.tap_6_i( h_buf6_d1 ) ,
.tap_7_i( h_buf6_i ) ,
.val_o ( vquarter_3_2_pel6_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) vertical_3_2_7 (
.tap_0_i( h_buf7_d7 ) ,
.tap_1_i( h_buf7_d6 ) ,
.tap_2_i( h_buf7_d5 ) ,
.tap_3_i( h_buf7_d4 ) ,
.tap_4_i( h_buf7_d3 ) ,
.tap_5_i( h_buf7_d2 ) ,
.tap_6_i( h_buf7_d1 ) ,
.tap_7_i( h_buf7_i ) ,
.val_o ( vquarter_3_2_pel7_o)
);
// from ref
// ref_pel0_d7
// ref_pel0_d6
// ref_pel0_d5
// ref_pel0_d4
// ref_pel0_d3
// ref_pel0_d2
// ref_pel0_d1
// ref_pel0_i
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_0 (
.tap_0_i( ref_pel0_d7 ) ,
.tap_1_i( ref_pel0_d6 ) ,
.tap_2_i( ref_pel0_d5 ) ,
.tap_3_i( ref_pel0_d4 ) ,
.tap_4_i( ref_pel0_d3 ) ,
.tap_5_i( ref_pel0_d2 ) ,
.tap_6_i( ref_pel0_d1 ) ,
.tap_7_i( ref_pel0_i ) ,
.val_o ( vquarter_3_0_pel0_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_1 (
.tap_0_i( ref_pel1_d7 ) ,
.tap_1_i( ref_pel1_d6 ) ,
.tap_2_i( ref_pel1_d5 ) ,
.tap_3_i( ref_pel1_d4 ) ,
.tap_4_i( ref_pel1_d3 ) ,
.tap_5_i( ref_pel1_d2 ) ,
.tap_6_i( ref_pel1_d1 ) ,
.tap_7_i( ref_pel1_i ) ,
.val_o ( vquarter_3_0_pel1_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_2 (
.tap_0_i( ref_pel2_d7 ) ,
.tap_1_i( ref_pel2_d6 ) ,
.tap_2_i( ref_pel2_d5 ) ,
.tap_3_i( ref_pel2_d4 ) ,
.tap_4_i( ref_pel2_d3 ) ,
.tap_5_i( ref_pel2_d2 ) ,
.tap_6_i( ref_pel2_d1 ) ,
.tap_7_i( ref_pel2_i ) ,
.val_o ( vquarter_3_0_pel2_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_3 (
.tap_0_i( ref_pel3_d7 ) ,
.tap_1_i( ref_pel3_d6 ) ,
.tap_2_i( ref_pel3_d5 ) ,
.tap_3_i( ref_pel3_d4 ) ,
.tap_4_i( ref_pel3_d3 ) ,
.tap_5_i( ref_pel3_d2 ) ,
.tap_6_i( ref_pel3_d1 ) ,
.tap_7_i( ref_pel3_i ) ,
.val_o ( vquarter_3_0_pel3_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_4 (
.tap_0_i( ref_pel4_d7 ) ,
.tap_1_i( ref_pel4_d6 ) ,
.tap_2_i( ref_pel4_d5 ) ,
.tap_3_i( ref_pel4_d4 ) ,
.tap_4_i( ref_pel4_d3 ) ,
.tap_5_i( ref_pel4_d2 ) ,
.tap_6_i( ref_pel4_d1 ) ,
.tap_7_i( ref_pel4_i ) ,
.val_o ( vquarter_3_0_pel4_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_5 (
.tap_0_i( ref_pel5_d7 ) ,
.tap_1_i( ref_pel5_d6 ) ,
.tap_2_i( ref_pel5_d5 ) ,
.tap_3_i( ref_pel5_d4 ) ,
.tap_4_i( ref_pel5_d3 ) ,
.tap_5_i( ref_pel5_d2 ) ,
.tap_6_i( ref_pel5_d1 ) ,
.tap_7_i( ref_pel5_i ) ,
.val_o ( vquarter_3_0_pel5_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_6 (
.tap_0_i( ref_pel6_d7 ) ,
.tap_1_i( ref_pel6_d6 ) ,
.tap_2_i( ref_pel6_d5 ) ,
.tap_3_i( ref_pel6_d4 ) ,
.tap_4_i( ref_pel6_d3 ) ,
.tap_5_i( ref_pel6_d2 ) ,
.tap_6_i( ref_pel6_d1 ) ,
.tap_7_i( ref_pel6_i ) ,
.val_o ( vquarter_3_0_pel6_o)
);
fme_interpolator #(
.TYPE(2),
.HOR(0),
.LAST(1),
.IN_EXPAND(0),
.OUT_EXPAND(0)
) vertical_3_0_7 (
.tap_0_i( ref_pel7_d7 ) ,
.tap_1_i( ref_pel7_d6 ) ,
.tap_2_i( ref_pel7_d5 ) ,
.tap_3_i( ref_pel7_d4 ) ,
.tap_4_i( ref_pel7_d3 ) ,
.tap_5_i( ref_pel7_d2 ) ,
.tap_6_i( ref_pel7_d1 ) ,
.tap_7_i( ref_pel7_i ) ,
.val_o ( vquarter_3_0_pel7_o)
);
// vertical half interpolator
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_0 (
.tap_0_i( q1_buf0_i ) ,
.tap_1_i( q1_buf0_d1 ) ,
.tap_2_i( q1_buf0_d2 ) ,
.tap_3_i( q1_buf0_d3 ) ,
.tap_4_i( q1_buf0_d4 ) ,
.tap_5_i( q1_buf0_d5 ) ,
.tap_6_i( q1_buf0_d6 ) ,
.tap_7_i( q1_buf0_d7 ) ,
.val_o ( vhalf_2_1_pel0_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_1 (
.tap_0_i( q1_buf1_i ) ,
.tap_1_i( q1_buf1_d1 ) ,
.tap_2_i( q1_buf1_d2 ) ,
.tap_3_i( q1_buf1_d3 ) ,
.tap_4_i( q1_buf1_d4 ) ,
.tap_5_i( q1_buf1_d5 ) ,
.tap_6_i( q1_buf1_d6 ) ,
.tap_7_i( q1_buf1_d7 ) ,
.val_o ( vhalf_2_1_pel1_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_2 (
.tap_0_i( q1_buf2_i ) ,
.tap_1_i( q1_buf2_d1 ) ,
.tap_2_i( q1_buf2_d2 ) ,
.tap_3_i( q1_buf2_d3 ) ,
.tap_4_i( q1_buf2_d4 ) ,
.tap_5_i( q1_buf2_d5 ) ,
.tap_6_i( q1_buf2_d6 ) ,
.tap_7_i( q1_buf2_d7 ) ,
.val_o ( vhalf_2_1_pel2_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_3 (
.tap_0_i( q1_buf3_i ) ,
.tap_1_i( q1_buf3_d1 ) ,
.tap_2_i( q1_buf3_d2 ) ,
.tap_3_i( q1_buf3_d3 ) ,
.tap_4_i( q1_buf3_d4 ) ,
.tap_5_i( q1_buf3_d5 ) ,
.tap_6_i( q1_buf3_d6 ) ,
.tap_7_i( q1_buf3_d7 ) ,
.val_o ( vhalf_2_1_pel3_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_4 (
.tap_0_i( q1_buf4_i ) ,
.tap_1_i( q1_buf4_d1 ) ,
.tap_2_i( q1_buf4_d2 ) ,
.tap_3_i( q1_buf4_d3 ) ,
.tap_4_i( q1_buf4_d4 ) ,
.tap_5_i( q1_buf4_d5 ) ,
.tap_6_i( q1_buf4_d6 ) ,
.tap_7_i( q1_buf4_d7 ) ,
.val_o ( vhalf_2_1_pel4_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_5 (
.tap_0_i( q1_buf5_i ) ,
.tap_1_i( q1_buf5_d1 ) ,
.tap_2_i( q1_buf5_d2 ) ,
.tap_3_i( q1_buf5_d3 ) ,
.tap_4_i( q1_buf5_d4 ) ,
.tap_5_i( q1_buf5_d5 ) ,
.tap_6_i( q1_buf5_d6 ) ,
.tap_7_i( q1_buf5_d7 ) ,
.val_o ( vhalf_2_1_pel5_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_6 (
.tap_0_i( q1_buf6_i ) ,
.tap_1_i( q1_buf6_d1 ) ,
.tap_2_i( q1_buf6_d2 ) ,
.tap_3_i( q1_buf6_d3 ) ,
.tap_4_i( q1_buf6_d4 ) ,
.tap_5_i( q1_buf6_d5 ) ,
.tap_6_i( q1_buf6_d6 ) ,
.tap_7_i( q1_buf6_d7 ) ,
.val_o ( vhalf_2_1_pel6_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_1_7 (
.tap_0_i( q1_buf7_i ) ,
.tap_1_i( q1_buf7_d1 ) ,
.tap_2_i( q1_buf7_d2 ) ,
.tap_3_i( q1_buf7_d3 ) ,
.tap_4_i( q1_buf7_d4 ) ,
.tap_5_i( q1_buf7_d5 ) ,
.tap_6_i( q1_buf7_d6 ) ,
.tap_7_i( q1_buf7_d7 ) ,
.val_o ( vhalf_2_1_pel7_o)
);
//from q3
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_0 (
.tap_0_i( q3_buf0_i ) ,
.tap_1_i( q3_buf0_d1 ) ,
.tap_2_i( q3_buf0_d2 ) ,
.tap_3_i( q3_buf0_d3 ) ,
.tap_4_i( q3_buf0_d4 ) ,
.tap_5_i( q3_buf0_d5 ) ,
.tap_6_i( q3_buf0_d6 ) ,
.tap_7_i( q3_buf0_d7 ) ,
.val_o ( vhalf_2_3_pel0_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_1 (
.tap_0_i( q3_buf1_i ) ,
.tap_1_i( q3_buf1_d1 ) ,
.tap_2_i( q3_buf1_d2 ) ,
.tap_3_i( q3_buf1_d3 ) ,
.tap_4_i( q3_buf1_d4 ) ,
.tap_5_i( q3_buf1_d5 ) ,
.tap_6_i( q3_buf1_d6 ) ,
.tap_7_i( q3_buf1_d7 ) ,
.val_o ( vhalf_2_3_pel1_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_2 (
.tap_0_i( q3_buf2_i ) ,
.tap_1_i( q3_buf2_d1 ) ,
.tap_2_i( q3_buf2_d2 ) ,
.tap_3_i( q3_buf2_d3 ) ,
.tap_4_i( q3_buf2_d4 ) ,
.tap_5_i( q3_buf2_d5 ) ,
.tap_6_i( q3_buf2_d6 ) ,
.tap_7_i( q3_buf2_d7 ) ,
.val_o ( vhalf_2_3_pel2_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_3 (
.tap_0_i( q3_buf3_i ) ,
.tap_1_i( q3_buf3_d1 ) ,
.tap_2_i( q3_buf3_d2 ) ,
.tap_3_i( q3_buf3_d3 ) ,
.tap_4_i( q3_buf3_d4 ) ,
.tap_5_i( q3_buf3_d5 ) ,
.tap_6_i( q3_buf3_d6 ) ,
.tap_7_i( q3_buf3_d7 ) ,
.val_o ( vhalf_2_3_pel3_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_4 (
.tap_0_i( q3_buf4_i ) ,
.tap_1_i( q3_buf4_d1 ) ,
.tap_2_i( q3_buf4_d2 ) ,
.tap_3_i( q3_buf4_d3 ) ,
.tap_4_i( q3_buf4_d4 ) ,
.tap_5_i( q3_buf4_d5 ) ,
.tap_6_i( q3_buf4_d6 ) ,
.tap_7_i( q3_buf4_d7 ) ,
.val_o ( vhalf_2_3_pel4_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_5 (
.tap_0_i( q3_buf5_i ) ,
.tap_1_i( q3_buf5_d1 ) ,
.tap_2_i( q3_buf5_d2 ) ,
.tap_3_i( q3_buf5_d3 ) ,
.tap_4_i( q3_buf5_d4 ) ,
.tap_5_i( q3_buf5_d5 ) ,
.tap_6_i( q3_buf5_d6 ) ,
.tap_7_i( q3_buf5_d7 ) ,
.val_o ( vhalf_2_3_pel5_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_6 (
.tap_0_i( q3_buf6_i ) ,
.tap_1_i( q3_buf6_d1 ) ,
.tap_2_i( q3_buf6_d2 ) ,
.tap_3_i( q3_buf6_d3 ) ,
.tap_4_i( q3_buf6_d4 ) ,
.tap_5_i( q3_buf6_d5 ) ,
.tap_6_i( q3_buf6_d6 ) ,
.tap_7_i( q3_buf6_d7 ) ,
.val_o ( vhalf_2_3_pel6_o)
);
fme_interpolator #(
.TYPE(0),
.HOR(0),
.LAST(0),
.IN_EXPAND(1),
.OUT_EXPAND(0)
) half_2_3_7 (
.tap_0_i( q3_buf7_i ) ,
.tap_1_i( q3_buf7_d1 ) ,
.tap_2_i( q3_buf7_d2 ) ,
.tap_3_i( q3_buf7_d3 ) ,
.tap_4_i( q3_buf7_d4 ) ,
.tap_5_i( q3_buf7_d5 ) ,
.tap_6_i( q3_buf7_d6 ) ,
.tap_7_i( q3_buf7_d7 ) ,
.val_o ( vhalf_2_3_pel7_o)
);
// clip
clip2 clip_0_1_0 (
.val_in(q1_buf0_i),
.val_out(vpel_0_1_pel0_o)
);
clip2 clip_0_1_1 (
.val_in(q1_buf1_i),
.val_out(vpel_0_1_pel1_o)
);
clip2 clip_0_1_2 (
.val_in(q1_buf2_i),
.val_out(vpel_0_1_pel2_o)
);
clip2 clip_0_1_3 (
.val_in(q1_buf3_i),
.val_out(vpel_0_1_pel3_o)
);
clip2 clip_0_1_4 (
.val_in(q1_buf4_i),
.val_out(vpel_0_1_pel4_o)
);
clip2 clip_0_1_5 (
.val_in(q1_buf5_i),
.val_out(vpel_0_1_pel5_o)
);
clip2 clip_0_1_6 (
.val_in(q1_buf6_i),
.val_out(vpel_0_1_pel6_o)
);
clip2 clip_0_1_7 (
.val_in(q1_buf7_i),
.val_out(vpel_0_1_pel7_o)
);
//
clip2 clip_0_3_0 (
.val_in(q3_buf0_i),
.val_out(vpel_0_3_pel0_o)
);
clip2 clip_0_3_1 (
.val_in(q3_buf1_i),
.val_out(vpel_0_3_pel1_o)
);
clip2 clip_0_3_2 (
.val_in(q3_buf2_i),
.val_out(vpel_0_3_pel2_o)
);
clip2 clip_0_3_3 (
.val_in(q3_buf3_i),
.val_out(vpel_0_3_pel3_o)
);
clip2 clip_0_3_4 (
.val_in(q3_buf4_i),
.val_out(vpel_0_3_pel4_o)
);
clip2 clip_0_3_5 (
.val_in(q3_buf5_i),
.val_out(vpel_0_3_pel5_o)
);
clip2 clip_0_3_6 (
.val_in(q3_buf6_i),
.val_out(vpel_0_3_pel6_o)
);
clip2 clip_0_3_7 (
.val_in(q3_buf7_i),
.val_out(vpel_0_3_pel7_o)
);
/*
assign cnthorLargerThan3 = (cnt_hor >='d3 && cnt_hor <='d10);
assign cnthorLargerThan4 = (cnt_hor >='d4 && cnt_hor <='d11);
assign cntrefLargerThan7 = (cnt_ref >='d7 && cnt_ref <='d14);
assign cntrefLargerThan8 = (cnt_ref [3]);
assign cnthorLargerThan7 = (cnt_hor >='d7 && cnt_hor <='d14);
assign cnthorLargerThan8 = (cnt_hor [3]);
assign vquarter_1_valid_o = (frac_y_i == 2'b00 || frac_y_i == 2'b01) ? (cnthorLargerThan8) : (cnthorLargerThan7);
assign vquarter_3_valid_o = (frac_y_i == 2'b00 ) ? (cnthorLargerThan8) : (cnthorLargerThan7);
assign vquarter_2_valid_o = (frac_y_i == 2'b00 || frac_y_i == 2'b01) ? (cnthorLargerThan8) : (cnthorLargerThan7);
assign vquarter_0_valid_o = (frac_y_i == 2'b00 || frac_y_i == 2'b01) ? (cntrefLargerThan8) : (cntrefLargerThan7);
assign vhalf_valid_o = (frac_y_i == 2'b00 || frac_y_i == 2'b01) ? (cnthorLargerThan4) : (cnthorLargerThan3);
assign vpel_valid_o = (frac_y_i == 2'b00 || frac_y_i == 2'b01) ? (cnthorLargerThan4) : (cnthorLargerThan3);
*/
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [4095:0] crc;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[4094:0], crc[63]^crc[2]^crc[0]}; // not a good crc :)
if (cyc==0) begin
// Setup
crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x%x%x%x\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
$write("[%0t] cyc==%0d crc=%b%b%b%b\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
//Unsupported: $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc
) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
(** * References: Typing Mutable References *)
(* $Date: 2011-10-10 12:42:53 -0400 (Mon, 10 Oct 2011) $ *)
Require Export Smallstep.
(** So far, we have considered a variety of _pure_ language features,
including functional abstraction, basic types such as numbers and
booleans, and structured types such as records and variants. These
features form the backbone of most programming languages -- including
purely functional languages such as Haskell, "mostly functional"
languages such as ML, imperative languages such as C, and
object-oriented languages such as Java.
Most practical programming languages also include various _impure_
features that cannot be described in the simple semantic framework
we have used so far. In particular, besides just yielding
results, evaluation of terms in these languages may assign to
mutable variables (reference cells, arrays, mutable record fields,
etc.), perform input and output to files, displays, or network
connections, make non-local transfers of control via exceptions,
jumps, or continuations, engage in inter-process synchronization
and communication, and so on. In the literature on programming
languages, such "side effects" of computation are more generally
referred to as _computational effects_.
In this chapter, we'll see how one sort of computational
effect -- mutable references -- can be added to the calculi we have
studied. The main extension will be dealing explicitly with a
_store_ (or _heap_). This extension is straightforward to define;
the most interesting part is the refinement we need to make to the
statement of the type preservation theorem. *)
(* ###################################################################### *)
(** ** Definitions *)
(** Pretty much every programming language provides some form of
assignment operation that changes the contents of a previously
allocated piece of storage. (Coq's internal language is a rare
exception!)
In some languages -- notably ML and its relatives -- the
mechanisms for name-binding and those for assignment are kept
separate. We can have a variable [x] whose _value_ is the number
[5], or we can have a variable [y] whose value is a
_reference_ (or _pointer_) to a mutable cell whose current
contents is [5]. These are different things, and the difference
is visible to the programmer. We can add [x] to another number,
but not assign to it. We can use [y] directly to assign a new
value to the cell that it points to (by writing [y:=84]), but we
cannot use it directly as an argument to an operation like [+].
Instead, we must explicitly _dereference_ it, writing [!y] to
obtain its current contents.
In most other languages -- in particular, in all members of the C
family, including Java -- _every_ variable name refers to a mutable
cell, and the operation of dereferencing a variable to obtain its
current contents is implicit.
For purposes of formal study, it is useful to keep these
mechanisms separate. The development in this chapter will closely
follow ML's model. Applying the lessons learned here to C-like
languages is a straightforward matter of collapsing some
distinctions and rendering some operations such as dereferencing
implicit instead of explicit.
In this chapter, we study adding mutable references to the
simply-typed lambda calculus with natural numbers. *)
(* ###################################################################### *)
(** ** Syntax *)
Module STLCRef.
(** The basic operations on references are _allocation_,
_dereferencing_, and _assignment_.
- To allocate a reference, we use the [ref] operator, providing
an initial value for the new cell. For example, [ref 5]
creates a new cell containing the value [5], and evaluates to
a reference to that cell.
- To read the current value of this cell, we use the
dereferencing operator [!]; for example, [!(ref 5)] evaluates
to [5].
- To change the value stored in a cell, we use the assignment
operator. If [r] is a reference, [r := 7] will store the
value [7] in the cell referenced by [r]. However, [r := 7]
evaluates to the trivial value [unit]; it exists only to have
the _side effect_ of modifying the contents of a cell. *)
(* ################################### *)
(** *** Types *)
(** We start with the simply typed lambda calculus over the
natural numbers. To the base natural number type and arrow types
we need to add two more types to deal with references. First, we
need the _unit type_, which we will use as the result type of an
assignment operation. We then add _reference types_. *)
(** If [T] is a type, then [Ref T] is the type of references which
point to a cell holding values of type [T].
<<
T ::= Nat
| Unit
| T -> T
| Ref T
>>
*)
Inductive ty : Type :=
| ty_Nat : ty
| ty_Unit : ty
| ty_arrow : ty -> ty -> ty
| ty_Ref : ty -> ty.
(* ################################### *)
(** *** Terms *)
(** Besides variables, abstractions, applications,
natural-number-related terms, and [unit], we need four more sorts
of terms in order to handle mutable references:
<<
t ::= ... Terms
| ref t allocation
| !t dereference
| t := t assignment
| l location
>>
*)
Inductive tm : Type :=
(* STLC with numbers: *)
| tm_var : id -> tm
| tm_app : tm -> tm -> tm
| tm_abs : id -> ty -> tm -> tm
| tm_nat : nat -> tm
| tm_succ : tm -> tm
| tm_pred : tm -> tm
| tm_mult : tm -> tm -> tm
| tm_if0 : tm -> tm -> tm -> tm
(* New terms: *)
| tm_unit : tm
| tm_ref : tm -> tm
| tm_deref : tm -> tm
| tm_assign : tm -> tm -> tm
| tm_loc : nat -> tm.
(** Intuitively...
- [ref t] (formally, [tm_ref t]) allocates a new reference cell
with the value [t] and evaluates to the location of the newly
allocated cell;
- [!t] (formally, [tm_deref t]) evaluates to the contents of the
cell referenced by [t];
- [t1 := t2] (formally, [tm_assign t1 t2]) assigns [t2] to the
cell referenced by [t1]; and
- [l] (formally, [tm_loc l]) is a reference to the cell at
location [l]. We'll discuss locations later. *)
(** In informal examples, we'll also freely use the extensions
of the STLC developed in the [MoreStlc] chapter; however, to keep
the proofs small, we won't bother formalizing them again here. It
would be easy to do so, since there are no very interesting
interactions between those features and references. *)
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tm_var" | Case_aux c "tm_app"
| Case_aux c "tm_abs" | Case_aux c "tm_zero"
| Case_aux c "tm_succ" | Case_aux c "tm_pred"
| Case_aux c "tm_mult" | Case_aux c "tm_if0"
| Case_aux c "tm_unit" | Case_aux c "tm_ref"
| Case_aux c "tm_deref" | Case_aux c "tm_assign"
| Case_aux c "tm_loc" ].
Module ExampleVariables.
Definition x := Id 0.
Definition y := Id 1.
Definition r := Id 2.
Definition s := Id 3.
End ExampleVariables.
(* ################################### *)
(** *** Typing (Preview) *)
(** Informally, the typing rules for allocation, dereferencing, and
assignment will look like this:
[[[
Gamma |- t1 : T1
------------------------ (T_Ref)
Gamma |- ref t1 : Ref T1
Gamma |- t1 : Ref T11
--------------------- (T_Deref)
Gamma |- !t1 : T11
Gamma |- t1 : Ref T11
Gamma |- t2 : T11
------------------------ (T_Assign)
Gamma |- t1 := t2 : Unit
]]]
The rule for locations will require a bit more machinery, and this
will motivate some changes to the other rules; we'll come back to
this later. *)
(* ################################### *)
(** *** Values and Substitution *)
(** Besides abstractions and numbers, we have two new types of values:
the unit value, and locations. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tm_abs x T t)
| v_nat : forall n,
value (tm_nat n)
| v_unit :
value tm_unit
| v_loc : forall l,
value (tm_loc l).
Hint Constructors value.
(** Extending substitution to handle the new syntax of terms is
straightforward. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tm_var x' =>
if beq_id x x' then s else t
| tm_app t1 t2 =>
tm_app (subst x s t1) (subst x s t2)
| tm_abs x' T t1 =>
if beq_id x x' then t else tm_abs x' T (subst x s t1)
| tm_nat n =>
t
| tm_succ t1 =>
tm_succ (subst x s t1)
| tm_pred t1 =>
tm_pred (subst x s t1)
| tm_mult t1 t2 =>
tm_mult (subst x s t1) (subst x s t2)
| tm_if0 t1 t2 t3 =>
tm_if0 (subst x s t1) (subst x s t2) (subst x s t3)
| tm_unit =>
t
| tm_ref t1 =>
tm_ref (subst x s t1)
| tm_deref t1 =>
tm_deref (subst x s t1)
| tm_assign t1 t2 =>
tm_assign (subst x s t1) (subst x s t2)
| tm_loc _ =>
t
end.
(* ###################################################################### *)
(** * Pragmatics *)
(* ################################### *)
(** ** Side Effects and Sequencing *)
(** The fact that the result of an assignment expression is the
trivial value [unit] allows us to use a nice abbreviation for
_sequencing_. For example, we can write
<<
r:=succ(!r); !r
>>
as an abbreviation for
<<
(\x:Unit. !r) (r := succ(!r)).
>>
This has the effect of evaluating two expressions in order and
returning the value of the second. Restricting the type of the first
expression to [Unit] helps the typechecker to catch some silly
errors by permitting us to throw away the first value only if it
is really guaranteed to be trivial.
Notice that, if the second expression is also an assignment, then
the type of the whole sequence will be [Unit], so we can validly
place it to the left of another [;] to build longer sequences of
assignments:
<<
r:=succ(!r); r:=succ(!r); r:=succ(!r); r:=succ(!r); !r
>>
*)
(** Formally, we introduce sequencing as a "derived form"
[tm_seq] that expands into an abstraction and an application. *)
Definition tm_seq t1 t2 :=
tm_app (tm_abs (Id 0) ty_Unit t2) t1.
(* ################################### *)
(** ** References and Aliasing *)
(** It is important to bear in mind the difference between the
_reference_ that is bound to [r] and the _cell_ in the store that
is pointed to by this reference.
If we make a copy of [r], for example by binding its value to
another variable [s], what gets copied is only the _reference_,
not the contents of the cell itself.
For example, after evaluating
<<
let r = ref 5 in
let s = r in
s := 82;
(!r)+1
>>
the cell referenced by [r] will contain the value [82], while the
result of the whole expression will be [83]. The references [r]
and [s] are said to be _aliases_ for the same cell.
The possibility of aliasing can make programs with references
quite tricky to reason about. For example, the expression
<<
r := 5; r := !s
>>
assigns [5] to [r] and then immediately overwrites it with [s]'s
current value; this has exactly the same effect as the single
assignment
<<
r := !s
>>
_unless_ we happen to do it in a context where [r] and [s] are
aliases for the same cell! *)
(* ################################### *)
(** ** Shared State *)
(** Of course, aliasing is also a large part of what makes references
useful. In particular, it allows us to set up "implicit
communication channels" -- shared state -- between different parts
of a program. For example, suppose we define a reference cell and
two functions that manipulate its contents:
<<
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
...
>>
*)
(** Note that, since their argument types are [Unit], the
abstractions in the definitions of [incc] and [decc] are not
providing any useful information to the bodies of the
functions (using the wildcard [_] as the name of the bound
variable is a reminder of this). Instead, their purpose is to
"slow down" the execution of the function bodies: since function
abstractions are values, the two [let]s are executed simply by
binding these functions to the names [incc] and [decc], rather
than by actually incrementing or decrementing [c]. Later, each
call to one of these functions results in its body being executed
once and performing the appropriate mutation on [c]. Such
functions are often called _thunks_.
In the context of these declarations, calling [incc] results in
changes to [c] that can be observed by calling [decc]. For
example, if we replace the [...] with [(incc unit; incc unit; decc
unit)], the result of the whole program will be [1]. *)
(** ** Objects *)
(** We can go a step further and write a _function_ that creates [c],
[incc], and [decc], packages [incc] and [decc] together into a
record, and returns this record:
<<
newcounter =
\_:Unit.
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
{i=incc, d=decc}
>>
*)
(** Now, each time we call [newcounter], we get a new record of
functions that share access to the same storage cell [c]. The
caller of [newcounter] can't get at this storage cell directly,
but can affect it indirectly by calling the two functions. In
other words, we've created a simple form of _object_.
<<
let c1 = newcounter unit in
let c2 = newcounter unit in
// Note that we've allocated two separate storage cells now!
let r1 = c1.i unit in
let r2 = c2.i unit in
r2 // yields 1, not 2!
>>
*)
(** **** Exercise: 1 star *)
(** Draw (on paper) the contents of the store at the point in
execution where the first two [let]s have finished and the third
one is about to begin. *)
(* FILL IN HERE *)
(** [] *)
(* ################################### *)
(** ** References to Compound Types *)
(** A reference cell need not contain just a number: the primitives
we've defined above allow us to create references to values of any
type, including functions. For example, we can use references to
functions to give a (not very efficient) implementation of arrays
of numbers, as follows. Write [NatArray] for the type
[Ref (Nat->Nat)].
Recall the [equal] function from the [MoreStlc] chapter:
<<
equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
>>
Now, to build a new array, we allocate a reference cell and fill
it with a function that, when given an index, always returns [0].
<<
newarray = \_:Unit. ref (\n:Nat.0)
>>
To look up an element of an array, we simply apply
the function to the desired index.
<<
lookup = \a:NatArray. \n:Nat. (!a) n
>>
The interesting part of the encoding is the [update] function. It
takes an array, an index, and a new value to be stored at that index, and
does its job by creating (and storing in the reference) a new function
that, when it is asked for the value at this very index, returns the new
value that was given to [update], and on all other indices passes the
lookup to the function that was previously stored in the reference.
<<
update = \a:NatArray. \m:Nat. \v:Nat.
let oldf = !a in
a := (\n:Nat. if equal m n then v else oldf n);
>>
References to values containing other references can also be very
useful, allowing us to define data structures such as mutable
lists and trees. *)
(** **** Exercise: 2 stars *)
(** If we defined [update] more compactly like this
<<
update = \a:NatArray. \m:Nat. \v:Nat.
a := (\n:Nat. if equal m n then v else (!a) n)
>>
would it behave the same? *)
(* FILL IN HERE *)
(** [] *)
(* ################################### *)
(** ** Null References *)
(** There is one more difference between our references and C-style
mutable variables: in C-like languages, variables holding pointers
into the heap may sometimes have the value [NULL]. Dereferencing
such a "null pointer" is an error, and results in an
exception (Java) or in termination of the program (C).
Null pointers cause significant trouble in C-like languages: the
fact that any pointer might be null means that any dereference
operation in the program can potentially fail. However, even in
ML-like languages, there are occasionally situations where we may
or may not have a valid pointer in our hands. Fortunately, there
is no need to extend the basic mechanisms of references to achieve
this: the sum types introduced in the [MoreStlc] chapter already
give us what we need.
First, we can use sums to build an analog of the [option] types
introduced in the [Lists] chapter. Define [Option T] to be an
abbreviation for [Unit + T].
Then a "nullable reference to a [T]" is simply an element of the
type [Option (Ref T)]. *)
(* ################################### *)
(** ** Garbage Collection *)
(** A last issue that we should mention before we move on with
formalizing references is storage _de_-allocation. We have not
provided any primitives for freeing reference cells when they are
no longer needed. Instead, like many modern languages (including
ML and Java) we rely on the run-time system to perform _garbage
collection_, collecting and reusing cells that can no longer be
reached by the program.
This is _not_ just a question of taste in language design: it is
extremely difficult to achieve type safety in the presence of an
explicit deallocation operation. The reason for this is the
familiar _dangling reference_ problem: we allocate a cell holding
a number, save a reference to it in some data structure, use it
for a while, then deallocate it and allocate a new cell holding a
boolean, possibly reusing the same storage. Now we can have two
names for the same storage cell -- one with type [Ref Nat] and the
other with type [Ref Bool]. *)
(** **** Exercise: 1 star *)
(** Show how this can lead to a violation of type safety. *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * Operational Semantics *)
(* ################################### *)
(** ** Locations *)
(** The most subtle aspect of the treatment of references
appears when we consider how to formalize their operational
behavior. One way to see why is to ask, "What should be the
_values_ of type [Ref T]?" The crucial observation that we need
to take into account is that evaluating a [ref] operator should
_do_ something -- namely, allocate some storage -- and the result
of the operation should be a reference to this storage.
What, then, is a reference?
The run-time store in most programming language implementations is
essentially just a big array of bytes. The run-time system keeps track
of which parts of this array are currently in use; when we need to
allocate a new reference cell, we allocate a large enough segment from
the free region of the store (4 bytes for integer cells, 8 bytes for
cells storing [Float]s, etc.), mark it as being used, and return the
index (typically, a 32- or 64-bit integer) of the start of the newly
allocated region. These indices are references.
For present purposes, there is no need to be quite so concrete.
We can think of the store as an array of _values_, rather than an
array of bytes, abstracting away from the different sizes of the
run-time representations of different values. A reference, then,
is simply an index into the store. (If we like, we can even
abstract away from the fact that these indices are numbers, but
for purposes of formalization in Coq it is a bit more convenient
to use numbers.) We'll use the word _location_ instead of
_reference_ or _pointer_ from now on to emphasize this abstract
quality.
Treating locations abstractly in this way will prevent us from
modeling the _pointer arithmetic_ found in low-level languages
such as C. This limitation is intentional. While pointer
arithmetic is occasionally very useful, especially for
implementing low-level services such as garbage collectors, it
cannot be tracked by most type systems: knowing that location [n]
in the store contains a [float] doesn't tell us anything useful
about the type of location [n+4]. In C, pointer arithmetic is a
notorious source of type safety violations. *)
(* ################################### *)
(** ** Stores *)
(** Recall that, in the small-step operational semantics for
IMP, the step relation needed to carry along an auxiliary state in
addition to the program being executed. In the same way, once we
have added reference cells to the STLC, our step relation must
carry along a store to keep track of the contents of reference
cells.
We could re-use the same functional representation we used for
states in IMP, but for carrying out the proofs in this chapter it
is actually more convenient to represent a store simply as a
_list_ of values. (The reason we couldn't use this representation
before is that, in IMP, a program could modify any location at any
time, so states had to be ready to map _any_ variable to a value.
However, in the STLC with references, the only way to create a
reference cell is with [tm_ref t1], which puts the value of [t1]
in a new reference cell and evaluates to the location of the newly
created reference cell. When evaluating such an expression, we can
just add a new reference cell to the end of the list representing
the store.) *)
Definition store := list tm.
(** We use [store_lookup n st] to retrieve the value of the reference
cell at location [n] in the store [st]. Note that we must give a
default value to [nth] in case we try looking up an index which is
too large. (In fact, we will never actually do this, but proving
it will of course require some work!) *)
Definition store_lookup (n:nat) (st:store) :=
nth n st tm_unit.
(** To add a new reference cell to the store, we use [snoc]. *)
Fixpoint snoc {A:Type} (l:list A) (x:A) : list A :=
match l with
| nil => x :: nil
| h :: t => h :: snoc t x
end.
(** We will need some boring lemmas about [snoc]. The proofs are
routine inductions. *)
Lemma length_snoc : forall A (l:list A) x,
length (snoc l x) = S (length l).
Proof.
induction l; intros; [ auto | simpl; rewrite IHl; auto ]. Qed.
(* The "solve by inversion" tactic is explained in Stlc.v. *)
Lemma nth_lt_snoc : forall A (l:list A) x d n,
n < length l ->
nth n l d = nth n (snoc l x) d.
Proof.
induction l as [|a l']; intros; try solve by inversion.
Case "l = a :: l'".
destruct n; auto.
simpl. apply IHl'.
simpl in H. apply lt_S_n in H. assumption.
Qed.
Lemma nth_eq_snoc : forall A (l:list A) x d,
nth (length l) (snoc l x) d = x.
Proof.
induction l; intros; [ auto | simpl; rewrite IHl; auto ].
Qed.
(** To update the store, we use the [replace] function, which replaces
the contents of a cell at a particular index. *)
Fixpoint replace {A:Type} (n:nat) (x:A) (l:list A) : list A :=
match l with
| nil => nil
| h :: t =>
match n with
| O => x :: t
| S n' => h :: replace n' x t
end
end.
(** Of course, we also need some boring lemmas about [replace], which
are also fairly straightforward to prove. *)
Lemma replace_nil : forall A n (x:A),
replace n x [] = [].
Proof.
destruct n; auto.
Qed.
Lemma length_replace : forall A n x (l:list A),
length (replace n x l) = length l.
Proof with auto.
intros A n x l. generalize dependent n.
induction l; intros n.
destruct n...
destruct n...
simpl. rewrite IHl...
Qed.
Lemma lookup_replace_eq : forall l t st,
l < length st ->
store_lookup l (replace l t st) = t.
Proof with auto.
intros l t st.
unfold store_lookup.
generalize dependent l.
induction st as [|t' st']; intros l Hlen.
Case "st = []".
inversion Hlen.
Case "st = t' :: st'".
destruct l; simpl...
apply IHst'. simpl in Hlen. omega.
Qed.
Lemma lookup_replace_neq : forall l1 l2 t st,
l1 <> l2 ->
store_lookup l1 (replace l2 t st) = store_lookup l1 st.
Proof with auto.
unfold store_lookup.
induction l1 as [|l1']; intros l2 t st Hneq.
Case "l1 = 0".
destruct st.
SCase "st = []". rewrite replace_nil...
SCase "st = _ :: _". destruct l2... contradict Hneq...
Case "l1 = S l1'".
destruct st as [|t2 st2].
SCase "st = []". destruct l2...
SCase "st = t2 :: st2".
destruct l2...
simpl; apply IHl1'...
Qed.
(* ################################### *)
(** ** Reduction *)
(** Next, we need to extend our operational semantics to take stores
into account. Since the result of evaluating an expression will
in general depend on the contents of the store in which it is
evaluated, the evaluation rules should take not just a term but
also a store as argument. Furthermore, since the evaluation of a
term may cause side effects on the store that may affect the
evaluation of other terms in the future, the evaluation rules need
to return a new store. Thus, the shape of the single-step
evaluation relation changes from [t ==> t'] to [t / st ==> t' /
st'], where [st] and [st'] are the starting and ending states of
the store.
To carry through this change, we first need to augment all of our
existing evaluation rules with stores:
[[[
value v2
------------------------------------- (ST_AppAbs)
(\a:T.t12) v2 / st ==> [v2/a]t12 / st
t1 / st ==> t1' / st'
--------------------------- (ST_App1)
t1 t2 / st ==> t1' t2 / st'
value v1 t2 / st ==> t2' / st'
---------------------------------- (ST_App2)
v1 t2 / st ==> v1 t2' / st'
]]]
Note that the first rule here returns the store unchanged:
function application, in itself, has no side effects. The other two
rules simply propagate side effects from premise to conclusion.
Now, the result of evaluating a [ref] expression will be a fresh
location; this is why we included locations in the syntax of terms
and in the set of values.
It is crucial to note that making this extension to the syntax of
terms does not mean that we intend _programmers_ to write terms
involving explicit, concrete locations: such terms will arise only
as intermediate results of evaluation. This may initially seem
odd, but really it follows naturally from our design decision to
represent the result of every evaluation step by a modified
term. If we had chosen a more "machine-like" model for evaluation,
e.g. with an explicit stack to contain values of bound
identifiers, then the idea of adding locations to the set of
allowed values would probably seem more obvious.
In terms of this expanded syntax, we can state evaluation rules for
the new constructs that manipulate locations and the store. First, to
evaluate a dereferencing expression [!t1], we must first reduce [t1]
until it becomes a value:
[[[
t1 / st ==> t1' / st'
----------------------- (ST_Deref)
!t1 / st ==> !t1' / st'
]]]
Once [t1] has finished reducing, we should have an expression of
the form [!l], where [l] is some location. (A term that attempts
to dereference any other sort of value, such as a function or
[unit], is erroneous, as is a term that tries to derefence a
location that is larger than the size [|st|] of the currently
allocated store; the evaluation rules simply get stuck in this
case. The type safety properties that we'll establish below
assure us that well-typed terms will never misbehave in this way.)
[[[
l < |st|
---------------------------------- (ST_DerefLoc)
!(loc l) / st ==> lookup l st / st
]]]
Next, to evaluate an assignment expression [t1:=t2], we must first
evaluate [t1] until it becomes a value (a location), and then
evaluate [t2] until it becomes a value (of any sort):
[[[
t1 / st ==> t1' / st'
----------------------------------- (ST_Assign1)
t1 := t2 / st ==> t1' := t2 / st'
t2 / st ==> t2' / st'
--------------------------------- (ST_Assign2)
v1 := t2 / st ==> v1 := t2' / st'
]]]
Once we have finished with [t1] and [t2], we have an expression of
the form [l:=v2], which we execute by updating the store to make
location [l] contain [v2]:
[[[
l < |st|
------------------------------------- (ST_Assign)
loc l := v2 / st ==> unit / [v2/l]st
]]]
The notation [[v2/l]st] means "the store that maps [l] to [v2]
and maps all other locations to the same thing as [st.]" Note
that the term resulting from this evaluation step is just [unit];
the interesting result is the updated store.)
Finally, to evaluate an expression of the form [ref t1], we first
evaluate [t1] until it becomes a value:
[[[
t1 / st ==> t1' / st'
----------------------------- (ST_Ref)
ref t1 / st ==> ref t1' / st'
]]]
Then, to evaluate the [ref] itself, we choose a fresh location at
the end of the current store -- i.e., location [|st|] -- and yield
a new store that extends [st] with the new value [v1].
[[[
-------------------------------- (ST_RefValue)
ref v1 / st ==> loc |st| / st,v1
]]]
The value resulting from this step is the newly allocated location
itself. (Formally, [st,v1] means [snoc st v1].)
Note that these evaluation rules do not perform any kind of
garbage collection: we simply allow the store to keep growing
without bound as evaluation proceeds. This does not affect the
correctness of the results of evaluation (after all, the
definition of "garbage" is precisely parts of the store that are
no longer reachable and so cannot play any further role in
evaluation), but it means that a naive implementation of our
evaluator might sometimes run out of memory where a more
sophisticated evaluator would be able to continue by reusing
locations whose contents have become garbage.
Formally... *)
Reserved Notation "t1 '/' st1 '==>' t2 '/' st2"
(at level 40, st1 at level 39, t2 at level 39).
Inductive step : tm * store -> tm * store -> Prop :=
| ST_AppAbs : forall x T t12 v2 st,
value v2 ->
tm_app (tm_abs x T t12) v2 / st ==> subst x v2 t12 / st
| ST_App1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tm_app t1 t2 / st ==> tm_app t1' t2 / st'
| ST_App2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tm_app v1 t2 / st ==> tm_app v1 t2'/ st'
| ST_SuccNat : forall n st,
tm_succ (tm_nat n) / st ==> tm_nat (S n) / st
| ST_Succ : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tm_succ t1 / st ==> tm_succ t1' / st'
| ST_PredNat : forall n st,
tm_pred (tm_nat n) / st ==> tm_nat (pred n) / st
| ST_Pred : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tm_pred t1 / st ==> tm_pred t1' / st'
| ST_MultNats : forall n1 n2 st,
tm_mult (tm_nat n1) (tm_nat n2) / st ==> tm_nat (mult n1 n2) / st
| ST_Mult1 : forall t1 t2 t1' st st',
t1 / st ==> t1' / st' ->
tm_mult t1 t2 / st ==> tm_mult t1' t2 / st'
| ST_Mult2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tm_mult v1 t2 / st ==> tm_mult v1 t2' / st'
| ST_If0 : forall t1 t1' t2 t3 st st',
t1 / st ==> t1' / st' ->
tm_if0 t1 t2 t3 / st ==> tm_if0 t1' t2 t3 / st'
| ST_If0_Zero : forall t2 t3 st,
tm_if0 (tm_nat 0) t2 t3 / st ==> t2 / st
| ST_If0_Nonzero : forall n t2 t3 st,
tm_if0 (tm_nat (S n)) t2 t3 / st ==> t3 / st
| ST_RefValue : forall v1 st,
value v1 ->
tm_ref v1 / st ==> tm_loc (length st) / snoc st v1
| ST_Ref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tm_ref t1 / st ==> tm_ref t1' / st'
| ST_DerefLoc : forall st l,
l < length st ->
tm_deref (tm_loc l) / st ==> store_lookup l st / st
| ST_Deref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tm_deref t1 / st ==> tm_deref t1' / st'
| ST_Assign : forall v2 l st,
value v2 ->
l < length st ->
tm_assign (tm_loc l) v2 / st ==> tm_unit / replace l v2 st
| ST_Assign1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tm_assign t1 t2 / st ==> tm_assign t1' t2 / st'
| ST_Assign2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tm_assign v1 t2 / st ==> tm_assign v1 t2' / st'
where "t1 '/' st1 '==>' t2 '/' st2" := (step (t1,st1) (t2,st2)).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_SuccNat"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredNat"
| Case_aux c "ST_Pred" | Case_aux c "ST_MultNats"
| Case_aux c "ST_Mult1" | Case_aux c "ST_Mult2"
| Case_aux c "ST_If0" | Case_aux c "ST_If0_Zero"
| Case_aux c "ST_If0_Nonzero" | Case_aux c "ST_RefValue"
| Case_aux c "ST_Ref" | Case_aux c "ST_DerefLoc"
| Case_aux c "ST_Deref" | Case_aux c "ST_Assign"
| Case_aux c "ST_Assign1" | Case_aux c "ST_Assign2" ].
Hint Constructors step.
Definition stepmany := (refl_step_closure step).
Notation "t1 '/' st '==>*' t2 '/' st'" := (stepmany (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(* ################################### *)
(** * Typing *)
(** Our contexts for free variables will be exactly the same as for
the STLC, partial maps from identifiers to types. *)
Definition context := partial_map ty.
(* ################################### *)
(** ** Store typings *)
(** Having extended our syntax and evaluation rules to accommodate
references, our last job is to write down typing rules for the new
constructs -- and, of course, to check that they are sound.
Naturally, the key question is, "What is the type of a location?"
First of all, notice that we do _not_ need to answer this question
for purposes of typechecking the terms that programmers actually
write. Concrete location constants arise only in terms that are
the intermediate results of evaluation; they are not in the
language that programmers write. So we only need to determine the
type of a location when we're in the middle of an evaluation
sequence, e.g. trying to apply the progress or preservation
lemmas. Thus, even though we normally think of typing as a
_static_ program property, it makes sense for the typing of
locations to depend on the _dynamic_ progress of the program too.
As a first try, note that when we evaluate a term containing
concrete locations, the type of the result depends on the contents
of the store that we start with. For example, if we evaluate the
term [!(loc 1)] in the store [[unit, unit]], the result is [unit];
if we evaluate the same term in the store [[unit, \x:Unit.x]], the
result is [\x:Unit.x]. With respect to the former store, the
location [1] has type [Unit], and with respect to the latter it
has type [Unit->Unit]. This observation leads us immediately to a
first attempt at a typing rule for locations:
[[[
Gamma |- lookup l st : T1
----------------------------
Gamma |- loc l : Ref T1
]]]
That is, to find the type of a location [l], we look up the
current contents of [l] in the store and calculate the type [T1]
of the contents. The type of the location is then [Ref T1].
Having begun in this way, we need to go a little further to reach a
consistent state. In effect, by making the type of a term depend on
the store, we have changed the typing relation from a three-place
relation (between contexts, terms, and types) to a four-place relation
(between contexts, _stores_, terms, and types). Since the store is,
intuitively, part of the context in which we calculate the type of a
term, let's write this four-place relation with the store to the left
of the turnstile: [Gamma; st |- t : T]. Our rule for typing
references now has the form
[[[
Gamma; st |- lookup l st : T1
--------------------------------
Gamma; st |- loc l : Ref T1
]]]
and all the rest of the typing rules in the system are extended
similarly with stores. The other rules do not need to do anything
interesting with their stores -- just pass them from premise to
conclusion.
However, there are two problems with this rule. First, typechecking
is rather inefficient, since calculating the type of a location [l]
involves calculating the type of the current contents [v] of [l]. If
[l] appears many times in a term [t], we will re-calculate the type of
[v] many times in the course of constructing a typing derivation for
[t]. Worse, if [v] itself contains locations, then we will have to
recalculate _their_ types each time they appear.
Second, the proposed typing rule for locations may not allow us to
derive anything at all, if the store contains a _cycle_. For example,
there is no finite typing derivation for the location [0] with respect
to this store:
<<
[\x:Nat. (!(loc 1)) x, \x:Nat. (!(loc 0)) x]
>>
*)
(** **** Exercise: 2 stars *)
(** Can you find a term whose evaluation will create this particular
cyclic store? *)
(** [] *)
(** Both of these problems arise from the fact that our proposed
typing rule for locations requires us to recalculate the type of a
location every time we mention it in a term. But this,
intuitively, should not be necessary. After all, when a location
is first created, we know the type of the initial value that we
are storing into it. Suppose we are willing to enforce the
invariant that the type of the value contained in a given location
_never changes_; that is, although we may later store other values
into this location, those other values will always have the same
type as the initial one. In other words, we always have in mind a
single, definite type for every location in the store, which is
fixed when the location is allocated. Then these intended types
can be collected together as a _store typing_ ---a finite function
mapping locations to types.
As usual, this _conservative_ typing restriction on allowed
updates means that we will rule out as ill-typed some programs
that could evaluate perfectly well without getting stuck.
*)
(** Just like we did for stores, we will represent a store type simply
as a list of types: the type at index [i] records the type of the
value stored in cell [i]. *)
Definition store_ty := list ty.
(** The [store_ty_lookup] function retrieves the type at a particular
index. *)
Definition store_ty_lookup (n:nat) (ST:store_ty) :=
nth n ST ty_Unit.
(** Suppose we are _given_ a store typing [ST] describing the store
[st] in which some term [t] will be evaluated. Then we can use
[ST] to calculate the type of the result of [t] without ever
looking directly at [st]. For example, if [ST] is [[Unit,
Unit->Unit]], then we may immediately infer that [!(loc 1)] has
type [Unit->Unit]. More generally, the typing rule for locations
can be reformulated in terms of store typings like this:
[[[
l < |ST|
-------------------------------------
Gamma; ST |- loc l : Ref (lookup l ST)
]]]
That is, as long as [l] is a valid location (it is less than the
length of [ST]), we can compute the type of [l] just by looking it
up in [ST]. Typing is again a four-place relation, but it is
parameterized on a store _typing_ rather than a concrete store.
The rest of the typing rules are analogously augmented with store
typings. *)
(* ################################### *)
(** ** The Typing Relation *)
(** We can now give the typing relation for the STLC with
references. Here, again, are the rules we're adding to the base
STLC (with numbers and [Unit]): *)
(**
[[[
l < |ST|
-------------------------------------- (T_Loc)
Gamma; ST |- loc l : Ref (lookup l ST)
Gamma; ST |- t1 : T1
---------------------------- (T_Ref)
Gamma; ST |- ref t1 : Ref T1
Gamma; ST |- t1 : Ref T11
------------------------- (T_Deref)
Gamma; ST |- !t1 : T11
Gamma; ST |- t1 : Ref T11
Gamma; ST |- t2 : T11
----------------------------- (T_Assign)
Gamma; ST |- t1 := t2 : Unit
]]]
*)
Inductive has_type : context -> store_ty -> tm -> ty -> Prop :=
| T_Var : forall Gamma ST x T,
Gamma x = Some T ->
has_type Gamma ST (tm_var x) T
| T_Abs : forall Gamma ST x T11 T12 t12,
has_type (extend Gamma x T11) ST t12 T12 ->
has_type Gamma ST (tm_abs x T11 t12) (ty_arrow T11 T12)
| T_App : forall T1 T2 Gamma ST t1 t2,
has_type Gamma ST t1 (ty_arrow T1 T2) ->
has_type Gamma ST t2 T1 ->
has_type Gamma ST (tm_app t1 t2) T2
| T_Nat : forall Gamma ST n,
has_type Gamma ST (tm_nat n) ty_Nat
| T_Succ : forall Gamma ST t1,
has_type Gamma ST t1 ty_Nat ->
has_type Gamma ST (tm_succ t1) ty_Nat
| T_Pred : forall Gamma ST t1,
has_type Gamma ST t1 ty_Nat ->
has_type Gamma ST (tm_pred t1) ty_Nat
| T_Mult : forall Gamma ST t1 t2,
has_type Gamma ST t1 ty_Nat ->
has_type Gamma ST t2 ty_Nat ->
has_type Gamma ST (tm_mult t1 t2) ty_Nat
| T_If0 : forall Gamma ST t1 t2 t3 T,
has_type Gamma ST t1 ty_Nat ->
has_type Gamma ST t2 T ->
has_type Gamma ST t3 T ->
has_type Gamma ST (tm_if0 t1 t2 t3) T
| T_Unit : forall Gamma ST,
has_type Gamma ST tm_unit ty_Unit
| T_Loc : forall Gamma ST l,
l < length ST ->
has_type Gamma ST (tm_loc l) (ty_Ref (store_ty_lookup l ST))
| T_Ref : forall Gamma ST t1 T1,
has_type Gamma ST t1 T1 ->
has_type Gamma ST (tm_ref t1) (ty_Ref T1)
| T_Deref : forall Gamma ST t1 T11,
has_type Gamma ST t1 (ty_Ref T11) ->
has_type Gamma ST (tm_deref t1) T11
| T_Assign : forall Gamma ST t1 t2 T11,
has_type Gamma ST t1 (ty_Ref T11) ->
has_type Gamma ST t2 T11 ->
has_type Gamma ST (tm_assign t1 t2) ty_Unit.
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Nat" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Mult" | Case_aux c "T_If0"
| Case_aux c "T_Unit" | Case_aux c "T_Loc"
| Case_aux c "T_Ref" | Case_aux c "T_Deref"
| Case_aux c "T_Assign" ].
(** Of course, these typing rules will accurately predict the results
of evaluation only if the concrete store used during evaluation
actually conforms to the store typing that we assume for purposes
of typechecking. This proviso exactly parallels the situation
with free variables in the STLC: the substitution lemma promises
us that, if [Gamma |- t : T], then we can replace the free
variables in [t] with values of the types listed in [Gamma] to
obtain a closed term of type [T], which, by the type preservation
theorem will evaluate to a final result of type [T] if it yields
any result at all. (We will see later how to formalize an
analogous intuition for stores and store typings.)
However, for purposes of typechecking the terms that programmers
actually write, we do not need to do anything tricky to guess what
store typing we should use. Recall that concrete location
constants arise only in terms that are the intermediate results of
evaluation; they are not in the language that programmers write.
Thus, we can simply typecheck the programmer's terms with respect
to the _empty_ store typing. As evaluation proceeds and new
locations are created, we will always be able to see how to extend
the store typing by looking at the type of the initial values
being placed in newly allocated cells; this intuition is
formalized in the statement of the type preservation theorem
below. *)
(* ################################### *)
(** * Properties *)
(** Our final task is to check that standard type safety properties
continue to hold for the STLC with references. The progress
theorem ("well-typed terms are not stuck") can be stated and
proved almost as for the STLC; we just need to add a few
straightforward cases to the proof, dealing with the new
constructs. The preservation theorem is a bit more interesting,
so let's look at it first. *)
(* ################################### *)
(** ** Well-Typed Stores *)
(** Since we have extended both the evaluation relation (with initial
and final stores) and the typing relation (with a store typing),
we need to change the statement of preservation to include these
parameters. Clearly, though, we cannot just add stores and store
typings without saying anything about how they are related: *)
Theorem preservation_wrong1 : forall ST T t st t' st',
has_type empty ST t T ->
t / st ==> t' / st' ->
has_type empty ST t' T.
Admitted.
(** If we typecheck with respect to some set of assumptions about the
types of the values in the store and then evaluate with respect to
a store that violates these assumptions, the result will be
disaster. We say that a store [st] is _well typed_ with respect a
store typing [ST] if the term at each location [l] in [st] has the
type at location [l] in [ST]. Since only closed terms ever get
stored in locations (why?), it suffices to type them in the empty
context. The following definition of [store_well_typed] formalizes
this. *)
Definition store_well_typed (ST:store_ty) (st:store) :=
length ST = length st /\
(forall l, l < length st ->
has_type empty ST (store_lookup l st) (store_ty_lookup l ST)).
(** Informally, we will write [ST |- st] for [store_well_typed ST st]. *)
(** Intuitively, a store [st] is consistent with a store typing
[ST] if every value in the store has the type predicted by the
store typing. (The only subtle point is the fact that, when
typing the values in the store, we supply the very same store
typing to the typing relation! This allows us to type circular
stores.) *)
(** **** Exercise: 2 stars *)
(** Can you find a store [st], and two
different store typings [ST1] and [ST2] such that both
[ST1 |- st] and [ST2 |- st]? *)
(* FILL IN HERE *)
(** [] *)
(** We can now state something closer to the desired preservation
property: *)
Theorem preservation_wrong2 : forall ST T t st t' st',
has_type empty ST t T ->
t / st ==> t' / st' ->
store_well_typed ST st ->
has_type empty ST t' T.
Admitted.
(** This statement is fine for all of the evaluation rules except the
allocation rule [ST_RefValue]. The problem is that this rule
yields a store with a larger domain than the initial store, which
falsifies the conclusion of the above statement: if [st']
includes a binding for a fresh location [l], then [l] cannot be in
the domain of [ST], and it will not be the case that [t']
(which definitely mentions [l]) is typable under [ST]. *)
(* ############################################ *)
(** ** Extending Store Typings *)
(** Evidently, since the store can increase in size during evaluation,
we need to allow the store typing to grow as well. This motivates
the following definition. We say that the store type [ST']
_extends_ [ST] if [ST'] is just [ST] with some new types added to
the end. *)
Inductive extends : store_ty -> store_ty -> Prop :=
| extends_nil : forall ST',
extends ST' nil
| extends_cons : forall x ST' ST,
extends ST' ST ->
extends (x::ST') (x::ST).
Hint Constructors extends.
(** We'll need a few technical lemmas about extended contexts.
First, looking up a type in an extended store typing yields the
same result as in the original: *)
Lemma extends_lookup : forall l ST ST',
l < length ST ->
extends ST' ST ->
store_ty_lookup l ST' = store_ty_lookup l ST.
Proof with auto.
intros l ST ST' Hlen H.
generalize dependent ST'. generalize dependent l.
induction ST as [|a ST2]; intros l Hlen ST' HST'.
Case "nil". inversion Hlen.
Case "cons". unfold store_ty_lookup in *.
destruct ST' as [|a' ST'2].
SCase "ST' = nil". inversion HST'.
SCase "ST' = a' :: ST'2".
inversion HST'; subst.
destruct l as [|l'].
SSCase "l = 0"...
SSCase "l = S l'". simpl. apply IHST2...
simpl in Hlen; omega.
Qed.
(** Next, if [ST'] extends [ST], the length of [ST'] is at least that
of [ST]. *)
Lemma length_extends : forall l ST ST',
l < length ST ->
extends ST' ST ->
l < length ST'.
Proof with eauto.
intros. generalize dependent l. induction H0; intros l Hlen.
inversion Hlen.
simpl in *.
destruct l; try omega.
apply lt_n_S. apply IHextends. omega.
Qed.
(** Finally, [snoc ST T] extends [ST], and [extends] is reflexive. *)
Lemma extends_snoc : forall ST T,
extends (snoc ST T) ST.
Proof with auto.
induction ST; intros T...
simpl...
Qed.
Lemma extends_refl : forall ST,
extends ST ST.
Proof.
induction ST; auto.
Qed.
(* ################################### *)
(** ** Preservation, Finally *)
(** We can now give the final, correct statement of the type
preservation property: *)
Definition preservation_theorem := forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
(** Note that the preservation theorem merely asserts that there is
_some_ store typing [ST'] extending [ST] (i.e., agreeing with [ST]
on the values of all the old locations) such that the new term
[t'] is well typed with respect to [ST']; it does not tell us
exactly what [ST'] is. It is intuitively clear, of course, that
[ST'] is either [ST] or else it is exactly [snoc ST T1], where
[T1] is the type of the value [v1] in the extended store [snoc st
v1], but stating this explicitly would complicate the statement of
the theorem without actually making it any more useful: the weaker
version above is already in the right form (because its conclusion
implies its hypothesis) to "turn the crank" repeatedly and
conclude that every _sequence_ of evaluation steps preserves
well-typedness. Combining this with the progress property, we
obtain the usual guarantee that "well-typed programs never go
wrong."
In order to prove this, we'll need a few lemmas, as usual. *)
(* ################################### *)
(** ** Substitution lemma *)
(** First, we need an easy extension of the standard substitution
lemma, along with the same machinery about context invariance that
we used in the proof of the substitution lemma for the STLC. *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tm_var x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tm_app t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tm_app t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tm_abs y T11 t12)
| afi_succ : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tm_succ t1)
| afi_pred : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tm_pred t1)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tm_mult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tm_mult t1 t2)
| afi_if0_1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tm_if0 t1 t2 t3)
| afi_if0_2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tm_if0 t1 t2 t3)
| afi_if0_3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tm_if0 t1 t2 t3)
| afi_ref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tm_ref t1)
| afi_deref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tm_deref t1)
| afi_assign1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tm_assign t1 t2)
| afi_assign2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tm_assign t1 t2).
Tactic Notation "afi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "afi_var"
| Case_aux c "afi_app1" | Case_aux c "afi_app2" | Case_aux c "afi_abs"
| Case_aux c "afi_succ" | Case_aux c "afi_pred"
| Case_aux c "afi_mult1" | Case_aux c "afi_mult2"
| Case_aux c "afi_if0_1" | Case_aux c "afi_if0_2" | Case_aux c "afi_if0_3"
| Case_aux c "afi_ref" | Case_aux c "afi_deref"
| Case_aux c "afi_assign1" | Case_aux c "afi_assign2" ].
Hint Constructors appears_free_in.
Lemma free_in_context : forall x t T Gamma ST,
appears_free_in x t ->
has_type Gamma ST t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros. generalize dependent Gamma. generalize dependent T.
afi_cases (induction H) Case;
intros; (try solve [ inversion H0; subst; eauto ]).
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H8.
apply not_eq_beq_id_false in H.
rewrite extend_neq in H8; assumption.
Qed.
Lemma context_invariance : forall Gamma Gamma' ST t T,
has_type Gamma ST t T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' ST t T.
Proof with eauto.
intros.
generalize dependent Gamma'.
has_type_cases (induction H) Case; intros...
Case "T_Var".
apply T_Var. symmetry. rewrite <- H...
Case "T_Abs".
apply T_Abs. apply IHhas_type; intros.
unfold extend.
remember (beq_id x x0) as e; destruct e...
apply H0. apply afi_abs. apply beq_id_false_not_eq... auto.
Case "T_App".
eapply T_App.
apply IHhas_type1...
apply IHhas_type2...
Case "T_Mult".
eapply T_Mult.
apply IHhas_type1...
apply IHhas_type2...
Case "T_If0".
eapply T_If0.
apply IHhas_type1...
apply IHhas_type2...
apply IHhas_type3...
Case "T_Assign".
eapply T_Assign.
apply IHhas_type1...
apply IHhas_type2...
Qed.
Lemma substitution_preserves_typing : forall Gamma ST x s S t T,
has_type empty ST s S ->
has_type (extend Gamma x S) ST t T ->
has_type Gamma ST (subst x s t) T.
Proof with eauto.
intros Gamma ST x s S t T Hs Ht.
generalize dependent Gamma. generalize dependent T.
tm_cases (induction t) Case; intros T Gamma H;
inversion H; subst; simpl...
Case "tm_var".
rename i into y.
remember (beq_id x y) as eq; destruct eq; subst.
SCase "x = y".
apply beq_id_eq in Heqeq; subst.
rewrite extend_eq in H3.
inversion H3; subst.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ _ _ _ Hcontra Hs) as [T' HT'].
inversion HT'.
SCase "x <> y".
apply T_Var.
rewrite extend_neq in H3...
Case "tm_abs". subst.
rename i into y.
remember (beq_id x y) as eq; destruct eq.
SCase "x = y".
apply beq_id_eq in Heqeq; subst.
apply T_Abs. eapply context_invariance...
intros. apply extend_shadow.
SCase "x <> x0".
apply T_Abs. apply IHt.
eapply context_invariance...
intros. unfold extend.
remember (beq_id y x0) as e. destruct e...
apply beq_id_eq in Heqe; subst.
rewrite <- Heqeq...
Qed.
(* ################################### *)
(** ** Assignment Preserves Store Typing *)
(** Next, we must show that replacing the contents of a cell in the
store with a new value of appropriate type does not change the
overall type of the store. (This is needed for the [ST_Assign]
rule.) *)
Lemma assign_pres_store_typing : forall ST st l t,
l < length st ->
store_well_typed ST st ->
has_type empty ST t (store_ty_lookup l ST) ->
store_well_typed ST (replace l t st).
Proof with auto.
intros ST st l t Hlen HST Ht.
inversion HST; subst.
split. rewrite length_replace...
intros l' Hl'.
remember (beq_nat l' l) as ll'; destruct ll'.
Case "l' = l".
apply beq_nat_eq in Heqll'; subst.
rewrite lookup_replace_eq...
Case "l' <> l".
symmetry in Heqll'; apply beq_nat_false in Heqll'.
rewrite lookup_replace_neq...
rewrite length_replace in Hl'.
apply H0...
Qed.
(* ######################################## *)
(** ** Weakening for Stores *)
(** Finally, we need a lemma on store typings, stating that, if a
store typing is extended with a new location, the extended one
still allows us to assign the same types to the same terms as the
original.
(The lemma is called [store_weakening] because it resembles the
"weakening" lemmas found in proof theory, which show that adding a
new assumption to some logical theory does not decrease the set of
provable theorems.) *)
Lemma store_weakening : forall Gamma ST ST' t T,
extends ST' ST ->
has_type Gamma ST t T ->
has_type Gamma ST' t T.
Proof with eauto.
intros. has_type_cases (induction H0) Case; eauto.
Case "T_Loc".
erewrite <- extends_lookup...
apply T_Loc.
eapply length_extends...
Qed.
(** We can use the [store_weakening] lemma to prove that if a store is
well-typed with respect to a store typing, then the store extended
with a new term [t] will still be well-typed with respect to the
store typing extended with [t]'s type. *)
Lemma store_well_typed_snoc : forall ST st t1 T1,
store_well_typed ST st ->
has_type empty ST t1 T1 ->
store_well_typed (snoc ST T1) (snoc st t1).
Proof with auto.
intros.
unfold store_well_typed in *.
inversion H as [Hlen Hmatch]; clear H.
rewrite !length_snoc.
split...
Case "types match.".
intros l Hl.
unfold store_lookup, store_ty_lookup.
apply le_lt_eq_dec in Hl; destruct Hl as [Hlt | Heq].
SCase "l < length st".
apply lt_S_n in Hlt.
rewrite <- !nth_lt_snoc...
apply store_weakening with ST. apply extends_snoc.
apply Hmatch...
rewrite Hlen...
SCase "l = length st".
inversion Heq.
rewrite nth_eq_snoc.
rewrite <- Hlen. rewrite nth_eq_snoc...
apply store_weakening with ST... apply extends_snoc.
Qed.
(* ################################### *)
(** ** Preservation! *)
(** Now that we've got everything set up right, the proof of
preservation is actually quite straightforward. *)
Theorem preservation : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof with eauto using store_weakening, extends_refl.
remember (@empty ty) as Gamma.
intros ST t t' T st st' Ht.
generalize dependent t'.
has_type_cases (induction Ht) Case; intros t' HST Hstep;
subst; try (solve by inversion); inversion Hstep; subst;
try (eauto using store_weakening, extends_refl).
Case "T_App".
SCase "ST_AppAbs". exists ST.
inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing...
SCase "ST_App1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_App2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Succ".
SCase "ST_Succ".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Pred".
SCase "ST_Pred".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Mult".
SCase "ST_Mult1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_Mult2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_If0".
SCase "ST_If0_1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... split...
Case "T_Ref".
SCase "ST_RefValue".
exists (snoc ST T1).
inversion HST; subst.
split.
apply extends_snoc.
split.
replace (ty_Ref T1)
with (ty_Ref (store_ty_lookup (length st) (snoc ST T1))).
apply T_Loc.
rewrite <- H. rewrite length_snoc. omega.
unfold store_ty_lookup. rewrite <- H. rewrite nth_eq_snoc...
apply store_well_typed_snoc; assumption.
SCase "ST_Ref".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Deref".
SCase "ST_DerefLoc".
exists ST. split; try split...
destruct HST as [_ Hsty].
replace T11 with (store_ty_lookup l ST).
apply Hsty...
inversion Ht; subst...
SCase "ST_Deref".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Assign".
SCase "ST_Assign".
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst...
SCase "ST_Assign1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_Assign2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Qed.
(** **** Exercise: 3 stars (preservation_informal) *)
(** Write a careful informal proof of the preservation theorem,
concentrating on the [T_App], [T_Deref], [T_Assign], and [T_Ref]
cases.
(* FILL IN HERE *)
[] *)
(* ################################### *)
(** ** Progress *)
(** Fortunately, progress for this system is pretty easy to prove; the
proof is very similar to the proof of progress for the STLC, with
a few new cases for the new syntactic constructs. *)
Theorem progress : forall ST t T st,
has_type empty ST t T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof with eauto.
intros ST t T st Ht HST. remember (@empty ty) as Gamma.
has_type_cases (induction Ht) Case; subst; try solve by inversion...
Case "T_App".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve by inversion.
destruct IHHt2 as [Ht2p | Ht2p]...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tm_app (tm_abs x T t) t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tm_app t1' t2). exists st'...
Case "T_Succ".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [ inversion Ht ].
SSCase "t1 is a tm_nat".
exists (tm_nat (S n)). exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tm_succ t1'). exists st'...
Case "T_Pred".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht ].
SSCase "t1 is a tm_nat".
exists (tm_nat (pred n)). exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tm_pred t1'). exists st'...
Case "T_Mult".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht1].
destruct IHHt2 as [Ht2p | Ht2p]...
SSCase "t2 is a value".
inversion Ht2p; subst; try solve [inversion Ht2].
exists (tm_nat (mult n n0)). exists st...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tm_mult (tm_nat n) t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tm_mult t1' t2). exists st'...
Case "T_If0".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht1].
destruct n.
SSCase "n = 0". exists t2. exists st...
SSCase "n = S n'". exists t3. exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tm_if0 t1' t2 t3). exists st'...
Case "T_Ref".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tm_ref t1'). exists st'...
Case "T_Deref".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve by inversion.
eexists. eexists. apply ST_DerefLoc...
inversion Ht; subst. inversion HST; subst.
rewrite <- H...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tm_deref t1'). exists st'...
Case "T_Assign".
right. destruct IHHt1 as [Ht1p|Ht1p]...
SCase "t1 is a value".
destruct IHHt2 as [Ht2p|Ht2p]...
SSCase "t2 is a value".
inversion Ht1p; subst; try solve by inversion.
eexists. eexists. apply ST_Assign...
inversion HST; subst. inversion Ht1; subst.
rewrite H in H5...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tm_assign t1 t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tm_assign t1' t2). exists st'...
Qed.
(* ################################### *)
(** * References and Nontermination *)
Section RefsAndNontermination.
Import ExampleVariables.
(** We know that the simply typed lambda calculus is _normalizing_,
that is, every well-typed term can be reduced to a value in a
finite number of steps. What about STLC + references?
Surprisingly, adding references causes us to lose the
normalization property: there exist well-typed terms in the STLC +
references which can continue to reduce forever, without ever
reaching a normal form!
How can we construct such a term? The main idea is to make a
function which calls itself. We first make a function which calls
another function stored in a reference cell; the trick is that we
then smuggle in a reference to itself!
<<
(\r:Ref (Unit -> Unit).
r := (\x:Unit.(!r) unit); (!r) unit)
(ref (\x:Unit.unit))
>>
First, [ref (\x:Unit.unit)] creates a reference to a cell of type
[Unit -> Unit]. We then pass this reference as the argument to a
function which binds it to the name [r], and assigns to it the
function (\x:Unit.(!r) unit) -- that is, the function which
ignores its argument and calls the function stored in [r] on the
argument [unit]; but of course, that function is itself! To get
the ball rolling we finally execute this function with [(!r)
unit].
*)
Definition loop_fun :=
tm_abs x ty_Unit (tm_app (tm_deref (tm_var r)) tm_unit).
Definition loop :=
tm_app
(tm_abs r (ty_Ref (ty_arrow ty_Unit ty_Unit))
(tm_seq (tm_assign (tm_var r) loop_fun)
(tm_app (tm_deref (tm_var r)) tm_unit)))
(tm_ref (tm_abs x ty_Unit tm_unit)).
(** This term is well-typed: *)
Lemma loop_typeable : exists T, has_type empty [] loop T.
Proof with eauto.
eexists. unfold loop. unfold loop_fun.
eapply T_App...
eapply T_Abs...
eapply T_App...
eapply T_Abs. eapply T_App. eapply T_Deref. eapply T_Var.
unfold extend. simpl. reflexivity. auto.
eapply T_Assign.
eapply T_Var. unfold extend. simpl. reflexivity.
eapply T_Abs.
eapply T_App...
eapply T_Deref. eapply T_Var. reflexivity.
Qed.
(** To show formally that the term diverges, we first define the
[step_closure] of the single-step reduction relation, written
[==>+]. This is just like the reflexive step closure of
single-step reduction (which we're been writing [==>*]), except
that it is not reflexive: [t ==>+ t'] means that [t] can reach
[t'] by _one or more_ steps of reduction. *)
Inductive step_closure {X:Type} (R: relation X) : X -> X -> Prop :=
| sc_one : forall (x y : X),
R x y -> step_closure R x y
| sc_step : forall (x y z : X),
R x y ->
step_closure R y z ->
step_closure R x z.
Definition stepmany1 := (step_closure step).
Notation "t1 '/' st '==>+' t2 '/' st'" := (stepmany1 (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(** Now, we can show that the expression [loop] reduces to the
expression [!(loc 0) unit] and the size-one store [ [(loc 0) / r]
loop_fun]. *)
(** As a convenience, we introduce a slight variant of the [normalize]
tactic, called [reduce], which tries solving the goal with
[rsc_refl] at each step, instead of waiting until the goal can't
be reduced any more. Of course, the whole point is that [loop]
doesn't normalize, so the old [normalize] tactic would just go
into an infinite loop reducing it forever! *)
Ltac print_goal := match goal with |- ?x => idtac x end.
Ltac reduce :=
repeat (print_goal; eapply rsc_step ;
[ (eauto 10; fail) | (instantiate; compute)];
try solve [apply rsc_refl]).
Lemma loop_steps_to_loop_fun :
loop / [] ==>*
tm_app (tm_deref (tm_loc 0)) tm_unit / [subst r (tm_loc 0) loop_fun].
Proof with eauto.
unfold loop.
reduce.
Qed.
(** Finally, the latter expression reduces in two steps to itself! *)
Lemma loop_fun_step_self :
tm_app (tm_deref (tm_loc 0)) tm_unit / [subst r (tm_loc 0) loop_fun] ==>+
tm_app (tm_deref (tm_loc 0)) tm_unit / [subst r (tm_loc 0) loop_fun].
Proof with eauto.
unfold loop_fun; simpl.
eapply sc_step. apply ST_App1...
eapply sc_one. compute. apply ST_AppAbs...
Qed.
(** **** Exercise: 4 stars *)
(** Use the above ideas to implement a factorial function in STLC with
references. (There is no need to prove formally that it really
behaves like the factorial. Just use the example below to make
sure it gives the correct result when applied to the argument
[4].) *)
Definition factorial : tm :=
(* FILL IN HERE *) admit.
Lemma factorial_type : has_type empty [] factorial (ty_arrow ty_Nat ty_Nat).
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** If your definition is correct, you should be able to just
uncomment the example below; the proof should be fully
automatic using the [reduce] tactic. *)
(*
Lemma factorial_4 : exists st,
tm_app factorial (tm_nat 4) / [] ==>* tm_nat 24 / st.
Proof.
eexists. unfold factorial. reduce.
Qed.
*)
(** [] *)
(* ################################### *)
(** * Additional Exercises *)
(** **** Exercise: 5 stars, optional *)
(** Challenge problem: modify our formalization to include an account
of garbage collection, and prove that it satisfies whatever nice
properties you can think to prove about it. *)
(** [] *)
End RefsAndNontermination.
End STLCRef.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/26/2016 09:14:57 AM
// Design Name:
// Module Name: FSM_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_test
(
input wire clk,
input wire rst,
input wire ready_op,
input wire max_tick_address,
input wire max_tick_ch,
input wire TX_DONE,
output reg beg_op,
output reg ack_op,
output reg load_address,
output reg enab_address,
output reg enab_ch,
output reg load_ch,
output reg TX_START
);
//symbolic state declaration
localparam [3:0] est0 = 4'b0000,
est1 = 4'b0001,
est2 = 4'b0010,
est3 = 4'b0011,
est4 = 4'b0100,
est5 = 4'b0101,
est6 = 4'b0110,
est7 = 4'b0111,
est8 = 4'b1000,
est9 = 4'b1001,
est10 = 4'b1010,
est11 = 4'b1011;
//signal declaration
reg [3:0] state_reg, state_next; // Guardan el estado actual y el estado futuro, respectivamente.
//state register
always @( posedge clk, posedge rst)
begin
if(rst) // Si hay reset, el estado actual es el estado inicial.
state_reg <= est0;
else //Si no hay reset el estado actual es igual al estado siguiente.
state_reg <= state_next;
end
//next-state logic and output logic
always @*
begin
state_next = state_reg; // default state : the same
//declaration of default outputs.
beg_op = 1'b0;
ack_op = 1'b0;
load_address = 1'b0;
enab_address = 1'b0;
enab_ch = 1'b0;
load_ch = 1'b0;
TX_START = 1'b0;
case(state_reg)
est0:
begin
state_next = est1;
end
est1:
begin
load_address = 1'b1;
enab_address = 1'b1;
state_next = est2;
end
est2:
begin
beg_op = 1'b1;
state_next=est3;
end
est3:
begin
beg_op = 1'b1;
enab_ch = 1'b1;
load_ch = 1'b1;
state_next=est4;
end
est4:
begin
if(ready_op)
state_next=est5;
else
state_next=est4;
end
est5:
begin
state_next=est6;
end
est6:
begin
TX_START = 1'b1;
state_next=est7;
end
est7:
begin
if(TX_DONE)
if(max_tick_ch)
state_next=est9;
else
begin
state_next=est8;
end
else
state_next=est7;
end
est8:
begin
enab_ch = 1'b1;
state_next=est5;
end
est9:
begin
if(max_tick_address)
state_next=est11;
else
begin
state_next=est10;
end
end
est10:
begin
enab_address = 1'b1;
ack_op = 1'b1;
state_next=est2;
end
est11:
begin
state_next=est11;
end
default:
state_next=est0;
endcase
end
endmodule
|
//
module spree (
clk,
resetn,
boot_iaddr,
boot_idata,
boot_iwe,
boot_daddr,
boot_ddata,
boot_dwe,
pipereg19_q,
ifetch_next_pc, //inst_mem_addr
ifetch_instr, //inst_mem_data_in
d_wr,
d_byteena, //data_bs
d_writedatamem, //data_mem_data_out
d_readdatain, //data_mem_data_in
addersub_result //data_mem_addr
);
/****************************************************************************
ISA definition file
- The MIPS I ISA has a 6 bit opcode in the upper 6 bits.
- The opcode can also specify a "class". There are two classes:
1. SPECIAL - look in lowest 6 bits to find operation
2. REGIMM - look in [20:16] to find type of branch
****************************************************************************/
/****** OPCODES - bits 31...26 *******/
parameter OP_SPECIAL = 6'b000000;
parameter OP_REGIMM = 6'b000001;
parameter OP_J = 6'b000010;
parameter OP_JAL = 6'b000011;
parameter OP_BEQ = 6'b000100;
parameter OP_BNE = 6'b000101;
parameter OP_BLEZ = 6'b000110;
parameter OP_BGTZ = 6'b000111;
parameter OP_ADDI = 6'b001000;
parameter OP_ADDIU = 6'b001001;
parameter OP_SLTI = 6'b001010;
parameter OP_SLTIU = 6'b001011;
parameter OP_ANDI = 6'b001100;
parameter OP_ORI = 6'b001101;
parameter OP_XORI = 6'b001110;
parameter OP_LUI = 6'b001111;
parameter OP_LB = 6'b100000;
parameter OP_LH = 6'b100001;
parameter OP_LWL = 6'b100010;
parameter OP_LW = 6'b100011;
parameter OP_LBU = 6'b100100;
parameter OP_LHU = 6'b100101;
parameter OP_LWR = 6'b100110;
parameter OP_SB = 6'b101x00;
parameter OP_SH = 6'b101x01;
parameter OP_SWL = 6'b101010;
parameter OP_SW = 6'b101x11;
parameter OP_SWR = 6'b101110;
/****** FUNCTION CLASS - bits 5...0 *******/
parameter FUNC_SLL = 6'b000000;
parameter FUNC_SRL = 6'b000010;
parameter FUNC_SRA = 6'b000011;
parameter FUNC_SLLV = 6'b000100;
parameter FUNC_SRLV = 6'b000110;
parameter FUNC_SRAV = 6'b000111;
parameter FUNC_JR = 6'b001xx0;
parameter FUNC_JALR = 6'b001xx1;
parameter FUNC_MFHI = 6'bx10x00;
parameter FUNC_MTHI = 6'bx10x01;
parameter FUNC_MFLO = 6'bx10x10;
parameter FUNC_MTLO = 6'bx10x11;
parameter FUNC_MULT = 6'bx11x00;
parameter FUNC_MULTU = 6'bx11x01;
parameter FUNC_DIV = 6'bx11x10;
parameter FUNC_DIVU = 6'bx11x11;
parameter FUNC_ADD = 6'b100000;
parameter FUNC_ADDU = 6'b100001;
parameter FUNC_SUB = 6'b100010;
parameter FUNC_SUBU = 6'b100011;
parameter FUNC_AND = 6'b100100;
parameter FUNC_OR = 6'b100101;
parameter FUNC_XOR = 6'b100110;
parameter FUNC_NOR = 6'b100111;
parameter FUNC_SLT = 6'b101010;
parameter FUNC_SLTU = 6'b101011;
/****** REGIMM Class - bits 20...16 *******/
parameter FUNC_BLTZ = 1'b0;
parameter FUNC_BGEZ = 1'b1;
parameter OP_COP2 = 6'b010010;
parameter COP2_FUNC_CFC2 = 6'b111000;
parameter COP2_FUNC_CTC2 = 6'b111010;
parameter COP2_FUNC_MTC2 = 6'b111011;
//parameter FUNC_BLTZAL = 5'b10000;
//parameter FUNC_BGEZAL = 5'b10001;
/******
* Original REGIMM class, compressed above to save decode logic
parameter FUNC_BLTZ = 5'b00000;
parameter FUNC_BGEZ = 5'b00001;
parameter FUNC_BLTZAL = 5'b10000;
parameter FUNC_BGEZAL = 5'b10001;
*/
/************************* IO Declarations *********************/
input clk;
input resetn;
input [31:0] boot_iaddr;
input [31:0] boot_idata;
input boot_iwe;
input [31:0] boot_daddr;
input [31:0] boot_ddata;
input boot_dwe;
output [31:0] pipereg19_q;
output [31:0] ifetch_next_pc;
input [31:0] ifetch_instr;
output d_wr;
output [3:0] d_byteena; //data_bs
output [31:0] d_writedatamem; //data_mem_data_out
input [31:0] d_readdatain; //data_mem_data_in
output [31:0] addersub_result; //data_mem_addr
/*********************** Signal Declarations *******************/
wire branch_mispred;
wire stall_2nd_delayslot;
wire has_delayslot;
wire haz_pipereg5_q_pipereg27_q;
wire haz_pipereg4_q_pipereg27_q;
wire haz_pipereg5_q_pipereg26_q;
wire haz_pipereg4_q_pipereg26_q;
wire haz_pipereg5_q_pipereg25_q;
wire haz_pipereg4_q_pipereg25_q;
wire haz_pipereg5_q_pipereg12_q;
wire haz_pipereg4_q_pipereg12_q;
// Datapath signals declarations
wire addersub_result_slt;
wire [ 31 : 0 ] addersub_result;
wire [ 31 : 0 ] mul_shift_result;
wire [ 31 : 0 ] mul_lo;
wire [ 31 : 0 ] mul_hi;
wire [ 31 : 0 ] ifetch_pc_out;
wire [ 31 : 0 ] ifetch_instr;
wire [ 5 : 0 ] ifetch_opcode;
wire [ 5 : 0 ] ifetch_func;
wire [ 4 : 0 ] ifetch_rs;
wire [ 4 : 0 ] ifetch_rt;
wire [ 4 : 0 ] ifetch_rd;
wire [ 25 : 0 ] ifetch_instr_index;
wire [ 15 : 0 ] ifetch_offset;
wire [ 4 : 0 ] ifetch_sa;
wire [ 31 : 0 ] ifetch_next_pc;
wire [ 31 : 0 ] data_mem_d_loadresult;
wire [ 31 : 0 ] reg_file_b_readdataout;
wire [ 31 : 0 ] reg_file_a_readdataout;
wire [ 31 : 0 ] logic_unit_result;
wire [ 31 : 0 ] pcadder_result;
wire [ 31 : 0 ] signext16_out;
wire [ 31 : 0 ] merge26lo_out;
wire branchresolve_eqz;
wire branchresolve_gez;
wire branchresolve_gtz;
wire branchresolve_lez;
wire branchresolve_ltz;
wire branchresolve_ne;
wire branchresolve_eq;
wire [ 31 : 0 ] hi_reg_q;
wire [ 31 : 0 ] lo_reg_q;
wire [ 31 : 0 ] const20_out;
wire [ 31 : 0 ] const_out;
wire [ 4 : 0 ] pipereg5_q;
wire [ 4 : 0 ] pipereg11_q;
wire [ 15 : 0 ] pipereg1_q;
wire [ 4 : 0 ] pipereg4_q;
wire [ 4 : 0 ] pipereg_q;
wire [ 25 : 0 ] pipereg2_q;
wire [ 31 : 0 ] pipereg6_q;
wire [ 31 : 0 ] pipereg3_q;
wire [ 25 : 0 ] pipereg7_q;
wire [ 4 : 0 ] pipereg8_q;
wire [ 31 : 0 ] const21_out;
wire [ 31 : 0 ] pipereg9_q;
wire [ 31 : 0 ] pipereg17_q;
wire [ 4 : 0 ] pipereg18_q;
wire [ 31 : 0 ] pipereg19_q;
wire [ 31 : 0 ] pipereg16_q;
wire [ 31 : 0 ] pipereg15_q;
wire pipereg14_q;
wire [ 31 : 0 ] pipereg13_q;
wire [ 31 : 0 ] pipereg22_q;
wire [ 4 : 0 ] pipereg12_q;
wire [ 31 : 0 ] pipereg23_q;
wire [ 4 : 0 ] pipereg25_q;
wire [ 4 : 0 ] pipereg26_q;
wire [ 4 : 0 ] pipereg27_q;
wire [ 31 : 0 ] fakedelay_q;
wire [ 4 : 0 ] zeroer0_q;
wire [ 4 : 0 ] zeroer10_q;
wire [ 4 : 0 ] zeroer_q;
wire [ 31 : 0 ] pipereg24_q;
wire [ 31 : 0 ] mux2to1_mul_opA_out;
wire [ 31 : 0 ] mux2to1_pipereg6_d_out;
wire [ 31 : 0 ] mux2to1_addersub_opA_out;
wire [ 31 : 0 ] mux4to1_reg_file_c_writedatain_out;
wire [ 4 : 0 ] mux3to1_pipereg18_d_out;
wire [ 31 : 0 ] mux3to1_pipereg16_d_out;
wire mux6to1_pipereg14_d_out;
wire [ 31 : 0 ] mux2to1_pipereg24_d_out;
wire [ 31 : 0 ] mux3to1_pipereg13_d_out;
wire [ 4 : 0 ] mux3to1_zeroer10_d_out;
wire [ 31 : 0 ] mux3to1_pipereg22_d_out;
wire [ 5 : 0 ] pipereg28_q;
wire [ 5 : 0 ] pipereg31_q;
wire [ 5 : 0 ] pipereg32_q;
wire [ 5 : 0 ] pipereg34_q;
wire [ 4 : 0 ] pipereg33_q;
wire [ 4 : 0 ] pipereg36_q;
wire [ 5 : 0 ] pipereg35_q;
wire [ 4 : 0 ] pipereg30_q;
wire [ 5 : 0 ] pipereg29_q;
wire [ 5 : 0 ] pipereg38_q;
wire [ 4 : 0 ] pipereg39_q;
wire [ 5 : 0 ] pipereg40_q;
wire [ 5 : 0 ] pipereg41_q;
wire [ 4 : 0 ] pipereg42_q;
wire [ 5 : 0 ] pipereg37_q;
wire branch_detector_is_branch;
wire pipereg43_q;
wire pipereg44_q;
/***************** Control Signals ***************/
//Decoded Opcode signal declarations
reg [ 2 : 0 ] ctrl_mux6to1_pipereg14_d_sel;
reg [ 1 : 0 ] ctrl_mux4to1_reg_file_c_writedatain_sel;
reg ctrl_mux2to1_addersub_opA_sel;
reg ctrl_mux2to1_pipereg24_d_sel;
reg [ 1 : 0 ] ctrl_mux3to1_pipereg22_d_sel;
reg [ 1 : 0 ] ctrl_mux3to1_pipereg18_d_sel;
reg [ 1 : 0 ] ctrl_mux3to1_pipereg16_d_sel;
reg ctrl_mux2to1_mul_opA_sel;
reg [ 1 : 0 ] ctrl_mux3to1_pipereg13_d_sel;
reg [ 1 : 0 ] ctrl_mux3to1_zeroer10_d_sel;
reg ctrl_mux2to1_pipereg6_d_sel;
reg ctrl_zeroer10_en;
reg ctrl_zeroer_en;
reg ctrl_zeroer0_en;
reg [ 2 : 0 ] ctrl_addersub_op;
reg ctrl_ifetch_op;
reg [ 3 : 0 ] ctrl_data_mem_op;
reg [ 2 : 0 ] ctrl_mul_op;
reg [ 1 : 0 ] ctrl_logic_unit_op;
//Enable signal declarations
reg ctrl_lo_reg_en;
reg ctrl_hi_reg_en;
reg ctrl_branchresolve_en;
reg ctrl_reg_file_c_we;
reg ctrl_reg_file_b_en;
reg ctrl_reg_file_a_en;
reg ctrl_ifetch_we;
reg ctrl_data_mem_en;
reg ctrl_ifetch_en;
//Other Signals
wire squash_stage6;
wire stall_out_stage6;
wire squash_stage5;
wire stall_out_stage5;
wire ctrl_pipereg24_squashn;
wire ctrl_pipereg27_squashn;
wire ctrl_pipereg23_squashn;
wire ctrl_pipereg40_squashn;
wire ctrl_pipereg41_squashn;
wire ctrl_pipereg42_squashn;
wire ctrl_pipereg24_resetn;
wire ctrl_pipereg27_resetn;
wire ctrl_pipereg23_resetn;
wire ctrl_pipereg40_resetn;
wire ctrl_pipereg41_resetn;
wire ctrl_pipereg42_resetn;
wire ctrl_pipereg24_en;
wire ctrl_pipereg27_en;
wire ctrl_pipereg23_en;
wire ctrl_pipereg40_en;
wire ctrl_pipereg41_en;
wire ctrl_pipereg42_en;
wire squash_stage4;
wire stall_out_stage4;
wire ctrl_pipereg22_squashn;
wire ctrl_pipereg26_squashn;
wire ctrl_pipereg37_squashn;
wire ctrl_pipereg38_squashn;
wire ctrl_pipereg39_squashn;
wire ctrl_pipereg22_resetn;
wire ctrl_pipereg26_resetn;
wire ctrl_pipereg37_resetn;
wire ctrl_pipereg38_resetn;
wire ctrl_pipereg39_resetn;
wire ctrl_pipereg22_en;
wire ctrl_pipereg26_en;
wire ctrl_pipereg37_en;
wire ctrl_pipereg38_en;
wire ctrl_pipereg39_en;
wire squash_stage3;
wire stall_out_stage3;
wire ctrl_pipereg16_squashn;
wire ctrl_pipereg25_squashn;
wire ctrl_pipereg17_squashn;
wire ctrl_pipereg18_squashn;
wire ctrl_pipereg19_squashn;
wire ctrl_pipereg13_squashn;
wire ctrl_pipereg15_squashn;
wire ctrl_pipereg14_squashn;
wire ctrl_pipereg34_squashn;
wire ctrl_pipereg35_squashn;
wire ctrl_pipereg36_squashn;
wire ctrl_pipereg16_resetn;
wire ctrl_pipereg25_resetn;
wire ctrl_pipereg17_resetn;
wire ctrl_pipereg18_resetn;
wire ctrl_pipereg19_resetn;
wire ctrl_pipereg13_resetn;
wire ctrl_pipereg15_resetn;
wire ctrl_pipereg14_resetn;
wire ctrl_pipereg34_resetn;
wire ctrl_pipereg35_resetn;
wire ctrl_pipereg36_resetn;
wire ctrl_pipereg16_en;
wire ctrl_pipereg25_en;
wire ctrl_pipereg17_en;
wire ctrl_pipereg18_en;
wire ctrl_pipereg19_en;
wire ctrl_pipereg13_en;
wire ctrl_pipereg15_en;
wire ctrl_pipereg14_en;
wire ctrl_pipereg34_en;
wire ctrl_pipereg35_en;
wire ctrl_pipereg36_en;
wire squash_stage2;
wire stall_out_stage2;
wire ctrl_pipereg6_squashn;
wire ctrl_pipereg12_squashn;
wire ctrl_pipereg8_squashn;
wire ctrl_pipereg9_squashn;
wire ctrl_pipereg7_squashn;
wire ctrl_pipereg31_squashn;
wire ctrl_pipereg32_squashn;
wire ctrl_pipereg33_squashn;
wire ctrl_pipereg6_resetn;
wire ctrl_pipereg12_resetn;
wire ctrl_pipereg8_resetn;
wire ctrl_pipereg9_resetn;
wire ctrl_pipereg7_resetn;
wire ctrl_pipereg31_resetn;
wire ctrl_pipereg32_resetn;
wire ctrl_pipereg33_resetn;
wire ctrl_pipereg6_en;
wire ctrl_pipereg12_en;
wire ctrl_pipereg8_en;
wire ctrl_pipereg9_en;
wire ctrl_pipereg7_en;
wire ctrl_pipereg31_en;
wire ctrl_pipereg32_en;
wire ctrl_pipereg33_en;
wire squash_stage1;
wire stall_out_stage1;
wire ctrl_pipereg44_squashn;
wire ctrl_pipereg1_squashn;
wire ctrl_pipereg11_squashn;
wire ctrl_pipereg4_squashn;
wire ctrl_pipereg5_squashn;
wire ctrl_pipereg_squashn;
wire ctrl_pipereg3_squashn;
wire ctrl_pipereg2_squashn;
wire ctrl_pipereg28_squashn;
wire ctrl_pipereg29_squashn;
wire ctrl_pipereg30_squashn;
wire ctrl_pipereg44_resetn;
wire ctrl_pipereg1_resetn;
wire ctrl_pipereg11_resetn;
wire ctrl_pipereg4_resetn;
wire ctrl_pipereg5_resetn;
wire ctrl_pipereg_resetn;
wire ctrl_pipereg3_resetn;
wire ctrl_pipereg2_resetn;
wire ctrl_pipereg28_resetn;
wire ctrl_pipereg29_resetn;
wire ctrl_pipereg30_resetn;
wire ctrl_pipereg44_en;
wire ctrl_pipereg1_en;
wire ctrl_pipereg11_en;
wire ctrl_pipereg4_en;
wire ctrl_pipereg5_en;
wire ctrl_pipereg_en;
wire ctrl_pipereg3_en;
wire ctrl_pipereg2_en;
wire ctrl_pipereg28_en;
wire ctrl_pipereg29_en;
wire ctrl_pipereg30_en;
/****************************** Control **************************/
//Decode Logic for Opcode and Multiplex Select signals
always@(ifetch_opcode or ifetch_func or ifetch_rt)
begin
// Initialize control opcodes to zero
ctrl_mux3to1_zeroer10_d_sel = 0;
ctrl_zeroer10_en = 0;
ctrl_zeroer_en = 0;
ctrl_zeroer0_en = 0;
casex (ifetch_opcode)
OP_ADDI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_ADDIU:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_ANDI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_BEQ:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
OP_BGTZ:
ctrl_zeroer0_en = 1;
OP_BLEZ:
ctrl_zeroer0_en = 1;
OP_BNE:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
OP_JAL:
begin
ctrl_mux3to1_zeroer10_d_sel = 0;
ctrl_zeroer10_en = 1;
end
OP_LB:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_LBU:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_LH:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_LHU:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_LUI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
end
OP_LW:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_ORI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_REGIMM:
casex (ifetch_rt[0])
FUNC_BGEZ:
ctrl_zeroer0_en = 1;
FUNC_BLTZ:
ctrl_zeroer0_en = 1;
endcase
OP_SB:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
OP_SH:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
OP_SLTI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_SLTIU:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
OP_SPECIAL:
casex (ifetch_func)
FUNC_ADD:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_ADDU:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_AND:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_JALR:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_JR:
ctrl_zeroer0_en = 1;
FUNC_MFHI:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
end
FUNC_MFLO:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
end
FUNC_MULT:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_MULTU:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_NOR:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_OR:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SLL:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
end
FUNC_SLLV:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SLT:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SLTU:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SRA:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
end
FUNC_SRAV:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SRL:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
end
FUNC_SRLV:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SUB:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_SUBU:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
FUNC_XOR:
begin
ctrl_mux3to1_zeroer10_d_sel = 1;
ctrl_zeroer10_en = 1;
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
endcase
OP_SW:
begin
ctrl_zeroer_en = 1;
ctrl_zeroer0_en = 1;
end
OP_XORI:
begin
ctrl_mux3to1_zeroer10_d_sel = 2;
ctrl_zeroer10_en = 1;
ctrl_zeroer0_en = 1;
end
endcase
end
//Logic for enable signals in Pipe Stage 1
always@(ifetch_opcode or ifetch_func or ifetch_rt[0] or stall_out_stage2 or stall_2nd_delayslot)
begin
ctrl_ifetch_en = 1 &~stall_2nd_delayslot&~stall_out_stage2;
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg28_q or pipereg29_q or pipereg30_q)
begin
// Initialize control opcodes to zero
ctrl_mux2to1_pipereg6_d_sel = 0;
casex (pipereg28_q)
OP_ADDI:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_ADDIU:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_ANDI:
ctrl_mux2to1_pipereg6_d_sel = 1;
OP_BEQ:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_BGTZ:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_BLEZ:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_BNE:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_LB:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_LBU:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_LH:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_LHU:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_LUI:
ctrl_mux2to1_pipereg6_d_sel = 1;
OP_LW:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_ORI:
ctrl_mux2to1_pipereg6_d_sel = 1;
OP_REGIMM:
casex (pipereg30_q[0])
FUNC_BGEZ:
ctrl_mux2to1_pipereg6_d_sel = 0;
FUNC_BLTZ:
ctrl_mux2to1_pipereg6_d_sel = 0;
endcase
OP_SB:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_SH:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_SLTI:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_SLTIU:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_SW:
ctrl_mux2to1_pipereg6_d_sel = 0;
OP_XORI:
ctrl_mux2to1_pipereg6_d_sel = 1;
endcase
end
//Logic for enable signals in Pipe Stage 2
always@(pipereg28_q or pipereg29_q or pipereg30_q[0] or stall_out_stage3 or haz_pipereg5_q_pipereg12_q or haz_pipereg4_q_pipereg25_q or haz_pipereg5_q_pipereg25_q or haz_pipereg4_q_pipereg12_q or haz_pipereg4_q_pipereg26_q or haz_pipereg5_q_pipereg26_q or haz_pipereg4_q_pipereg27_q or haz_pipereg5_q_pipereg27_q)
begin
ctrl_reg_file_b_en = 1 &~haz_pipereg5_q_pipereg27_q&~haz_pipereg4_q_pipereg27_q&~haz_pipereg5_q_pipereg26_q&~haz_pipereg4_q_pipereg26_q&~haz_pipereg4_q_pipereg12_q&~haz_pipereg5_q_pipereg25_q&~haz_pipereg4_q_pipereg25_q&~haz_pipereg5_q_pipereg12_q&~stall_out_stage3;
ctrl_reg_file_a_en = 1 &~haz_pipereg5_q_pipereg27_q&~haz_pipereg4_q_pipereg27_q&~haz_pipereg5_q_pipereg26_q&~haz_pipereg4_q_pipereg26_q&~haz_pipereg4_q_pipereg12_q&~haz_pipereg5_q_pipereg25_q&~haz_pipereg4_q_pipereg25_q&~haz_pipereg5_q_pipereg12_q&~stall_out_stage3;
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg31_q or pipereg32_q or pipereg33_q)
begin
// Initialize control opcodes to zero
ctrl_mux6to1_pipereg14_d_sel = 0;
ctrl_mux3to1_pipereg18_d_sel = 0;
ctrl_mux3to1_pipereg16_d_sel = 0;
ctrl_mux3to1_pipereg13_d_sel = 0;
casex (pipereg31_q)
OP_ADDI:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_ADDIU:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_ANDI:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_BEQ:
begin
ctrl_mux6to1_pipereg14_d_sel = 5;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
OP_BGTZ:
begin
ctrl_mux6to1_pipereg14_d_sel = 0;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
OP_BLEZ:
begin
ctrl_mux6to1_pipereg14_d_sel = 3;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
OP_BNE:
begin
ctrl_mux6to1_pipereg14_d_sel = 4;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
OP_J:
ctrl_mux3to1_pipereg13_d_sel = 1;
OP_JAL:
ctrl_mux3to1_pipereg13_d_sel = 1;
OP_LB:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_LBU:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_LH:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_LHU:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_LUI:
begin
ctrl_mux3to1_pipereg18_d_sel = 1;
ctrl_mux3to1_pipereg16_d_sel = 2;
end
OP_LW:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_ORI:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_REGIMM:
casex (pipereg33_q[0])
FUNC_BGEZ:
begin
ctrl_mux6to1_pipereg14_d_sel = 1;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
FUNC_BLTZ:
begin
ctrl_mux6to1_pipereg14_d_sel = 2;
ctrl_mux3to1_pipereg13_d_sel = 2;
end
endcase
OP_SB:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_SH:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_SLTI:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_SLTIU:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_SPECIAL:
casex (pipereg32_q)
FUNC_ADD:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_ADDU:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_AND:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_JALR:
ctrl_mux3to1_pipereg13_d_sel = 0;
FUNC_JR:
ctrl_mux3to1_pipereg13_d_sel = 0;
FUNC_NOR:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_OR:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_SLL:
begin
ctrl_mux3to1_pipereg18_d_sel = 0;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SLLV:
begin
ctrl_mux3to1_pipereg18_d_sel = 2;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SLT:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_SLTU:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_SRA:
begin
ctrl_mux3to1_pipereg18_d_sel = 0;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SRAV:
begin
ctrl_mux3to1_pipereg18_d_sel = 2;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SRL:
begin
ctrl_mux3to1_pipereg18_d_sel = 0;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SRLV:
begin
ctrl_mux3to1_pipereg18_d_sel = 2;
ctrl_mux3to1_pipereg16_d_sel = 1;
end
FUNC_SUB:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_SUBU:
ctrl_mux3to1_pipereg16_d_sel = 1;
FUNC_XOR:
ctrl_mux3to1_pipereg16_d_sel = 1;
endcase
OP_SW:
ctrl_mux3to1_pipereg16_d_sel = 2;
OP_XORI:
ctrl_mux3to1_pipereg16_d_sel = 2;
endcase
end
//Logic for enable signals in Pipe Stage 3
always@(pipereg31_q or pipereg32_q or pipereg33_q[0] or stall_out_stage4)
begin
ctrl_branchresolve_en = 0;
casex (pipereg31_q)
OP_BEQ:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
OP_BGTZ:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
OP_BLEZ:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
OP_BNE:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
OP_REGIMM:
casex (pipereg33_q[0])
FUNC_BGEZ:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
FUNC_BLTZ:
ctrl_branchresolve_en = 1 &~stall_out_stage4;
endcase
endcase
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg34_q or pipereg35_q or pipereg36_q)
begin
// Initialize control opcodes to zero
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg22_d_sel = 0;
ctrl_mux2to1_mul_opA_sel = 0;
ctrl_addersub_op = 0;
ctrl_ifetch_op = 0;
ctrl_data_mem_op = 0;
ctrl_mul_op = 0;
ctrl_logic_unit_op = 0;
casex (pipereg34_q)
OP_ADDI:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg22_d_sel = 2;
ctrl_addersub_op = 3;
end
OP_ADDIU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg22_d_sel = 2;
ctrl_addersub_op = 1;
end
OP_ANDI:
begin
ctrl_mux3to1_pipereg22_d_sel = 0;
ctrl_logic_unit_op = 0;
end
OP_BEQ:
ctrl_ifetch_op = 0;
OP_BGTZ:
ctrl_ifetch_op = 0;
OP_BLEZ:
ctrl_ifetch_op = 0;
OP_BNE:
ctrl_ifetch_op = 0;
OP_J:
ctrl_ifetch_op = 1;
OP_JAL:
begin
ctrl_mux2to1_addersub_opA_sel = 1;
ctrl_mux3to1_pipereg22_d_sel = 2;
ctrl_addersub_op = 1;
ctrl_ifetch_op = 1;
end
OP_LB:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 7;
end
OP_LBU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 3;
end
OP_LH:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 5;
end
OP_LHU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 1;
end
OP_LUI:
begin
ctrl_mux2to1_mul_opA_sel = 0;
ctrl_mul_op = 0;
end
OP_LW:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 0;
end
OP_ORI:
begin
ctrl_mux3to1_pipereg22_d_sel = 0;
ctrl_logic_unit_op = 1;
end
OP_REGIMM:
casex (pipereg36_q[0])
FUNC_BGEZ:
ctrl_ifetch_op = 0;
FUNC_BLTZ:
ctrl_ifetch_op = 0;
endcase
OP_SB:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 11;
end
OP_SH:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 9;
end
OP_SLTI:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg22_d_sel = 1;
ctrl_addersub_op = 6;
end
OP_SLTIU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg22_d_sel = 1;
ctrl_addersub_op = 4;
end
OP_SPECIAL:
casex (pipereg35_q)
FUNC_ADD:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg22_d_sel = 2;
ctrl_addersub_op = 3;
end
FUNC_ADDU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg22_d_sel = 2;
ctrl_addersub_op = 1;
end
FUNC_AND:
begin
ctrl_mux3to1_pipereg22_d_sel = 0;
ctrl_logic_unit_op = 0;
end
FUNC_JALR:
begin
ctrl_mux2to1_addersub_opA_sel = 1;
ctrl_mux3to1_pipereg22_d_sel = 2;
ctrl_addersub_op = 1;
ctrl_ifetch_op = 1;
end
FUNC_JR:
ctrl_ifetch_op = 1;
FUNC_MULT:
begin
ctrl_mux2to1_mul_opA_sel = 1;
ctrl_mul_op = 6;
end
FUNC_MULTU:
begin
ctrl_mux2to1_mul_opA_sel = 1;
ctrl_mul_op = 4;
end
FUNC_NOR:
begin
ctrl_mux3to1_pipereg22_d_sel = 0;
ctrl_logic_unit_op = 3;
end
FUNC_OR:
begin
ctrl_mux3to1_pipereg22_d_sel = 0;
ctrl_logic_unit_op = 1;
end
FUNC_SLL:
begin
ctrl_mux2to1_mul_opA_sel = 0;
ctrl_mul_op = 0;
end
FUNC_SLLV:
begin
ctrl_mux2to1_mul_opA_sel = 0;
ctrl_mul_op = 0;
end
FUNC_SLT:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg22_d_sel = 1;
ctrl_addersub_op = 6;
end
FUNC_SLTU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg22_d_sel = 1;
ctrl_addersub_op = 4;
end
FUNC_SRA:
begin
ctrl_mux2to1_mul_opA_sel = 0;
ctrl_mul_op = 3;
end
FUNC_SRAV:
begin
ctrl_mux2to1_mul_opA_sel = 0;
ctrl_mul_op = 3;
end
FUNC_SRL:
begin
ctrl_mux2to1_mul_opA_sel = 0;
ctrl_mul_op = 1;
end
FUNC_SRLV:
begin
ctrl_mux2to1_mul_opA_sel = 0;
ctrl_mul_op = 1;
end
FUNC_SUB:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg22_d_sel = 2;
ctrl_addersub_op = 0;
end
FUNC_SUBU:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_mux3to1_pipereg22_d_sel = 2;
ctrl_addersub_op = 2;
end
FUNC_XOR:
begin
ctrl_mux3to1_pipereg22_d_sel = 0;
ctrl_logic_unit_op = 2;
end
endcase
OP_SW:
begin
ctrl_mux2to1_addersub_opA_sel = 0;
ctrl_addersub_op = 3;
ctrl_data_mem_op = 8;
end
OP_XORI:
begin
ctrl_mux3to1_pipereg22_d_sel = 0;
ctrl_logic_unit_op = 2;
end
endcase
end
//Logic for enable signals in Pipe Stage 4
always@(pipereg34_q or pipereg35_q or pipereg36_q[0] or stall_out_stage5)
begin
ctrl_data_mem_en = 0;
ctrl_ifetch_we = 0;
casex (pipereg34_q)
OP_BEQ:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_BGTZ:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_BLEZ:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_BNE:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_J:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_JAL:
ctrl_ifetch_we = 1 &~stall_out_stage5;
OP_LB:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_LBU:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_LH:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_LHU:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_LW:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_REGIMM:
casex (pipereg36_q[0])
FUNC_BGEZ:
ctrl_ifetch_we = 1 &~stall_out_stage5;
FUNC_BLTZ:
ctrl_ifetch_we = 1 &~stall_out_stage5;
endcase
OP_SB:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_SH:
ctrl_data_mem_en = 1 &~stall_out_stage5;
OP_SPECIAL:
casex (pipereg35_q)
FUNC_JALR:
ctrl_ifetch_we = 1 &~stall_out_stage5;
FUNC_JR:
ctrl_ifetch_we = 1 &~stall_out_stage5;
endcase
OP_SW:
ctrl_data_mem_en = 1 &~stall_out_stage5;
endcase
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg37_q or pipereg38_q or pipereg39_q)
begin
// Initialize control opcodes to zero
ctrl_mux2to1_pipereg24_d_sel = 0;
casex (pipereg37_q)
OP_ADDI:
ctrl_mux2to1_pipereg24_d_sel = 1;
OP_ADDIU:
ctrl_mux2to1_pipereg24_d_sel = 1;
OP_ANDI:
ctrl_mux2to1_pipereg24_d_sel = 1;
OP_JAL:
ctrl_mux2to1_pipereg24_d_sel = 1;
OP_LUI:
ctrl_mux2to1_pipereg24_d_sel = 0;
OP_ORI:
ctrl_mux2to1_pipereg24_d_sel = 1;
OP_SLTI:
ctrl_mux2to1_pipereg24_d_sel = 1;
OP_SLTIU:
ctrl_mux2to1_pipereg24_d_sel = 1;
OP_SPECIAL:
casex (pipereg38_q)
FUNC_ADD:
ctrl_mux2to1_pipereg24_d_sel = 1;
FUNC_ADDU:
ctrl_mux2to1_pipereg24_d_sel = 1;
FUNC_AND:
ctrl_mux2to1_pipereg24_d_sel = 1;
FUNC_JALR:
ctrl_mux2to1_pipereg24_d_sel = 1;
FUNC_NOR:
ctrl_mux2to1_pipereg24_d_sel = 1;
FUNC_OR:
ctrl_mux2to1_pipereg24_d_sel = 1;
FUNC_SLL:
ctrl_mux2to1_pipereg24_d_sel = 0;
FUNC_SLLV:
ctrl_mux2to1_pipereg24_d_sel = 0;
FUNC_SLT:
ctrl_mux2to1_pipereg24_d_sel = 1;
FUNC_SLTU:
ctrl_mux2to1_pipereg24_d_sel = 1;
FUNC_SRA:
ctrl_mux2to1_pipereg24_d_sel = 0;
FUNC_SRAV:
ctrl_mux2to1_pipereg24_d_sel = 0;
FUNC_SRL:
ctrl_mux2to1_pipereg24_d_sel = 0;
FUNC_SRLV:
ctrl_mux2to1_pipereg24_d_sel = 0;
FUNC_SUB:
ctrl_mux2to1_pipereg24_d_sel = 1;
FUNC_SUBU:
ctrl_mux2to1_pipereg24_d_sel = 1;
FUNC_XOR:
ctrl_mux2to1_pipereg24_d_sel = 1;
endcase
OP_XORI:
ctrl_mux2to1_pipereg24_d_sel = 1;
endcase
end
//Logic for enable signals in Pipe Stage 5
always@(pipereg37_q or pipereg38_q or pipereg39_q[0] or stall_out_stage6)
begin
ctrl_lo_reg_en = 0;
ctrl_hi_reg_en = 0;
casex (pipereg37_q)
OP_SPECIAL:
casex (pipereg38_q)
FUNC_MULT:
begin
ctrl_lo_reg_en = 1 &~stall_out_stage6;
ctrl_hi_reg_en = 1 &~stall_out_stage6;
end
FUNC_MULTU:
begin
ctrl_lo_reg_en = 1 &~stall_out_stage6;
ctrl_hi_reg_en = 1 &~stall_out_stage6;
end
endcase
endcase
end
//Decode Logic for Opcode and Multiplex Select signals
always@(pipereg40_q or pipereg41_q or pipereg42_q)
begin
// Initialize control opcodes to zero
ctrl_mux4to1_reg_file_c_writedatain_sel = 0;
casex (pipereg40_q)
OP_ADDI:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
OP_ADDIU:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
OP_ANDI:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
OP_JAL:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
OP_LB:
ctrl_mux4to1_reg_file_c_writedatain_sel = 2;
OP_LBU:
ctrl_mux4to1_reg_file_c_writedatain_sel = 2;
OP_LH:
ctrl_mux4to1_reg_file_c_writedatain_sel = 2;
OP_LHU:
ctrl_mux4to1_reg_file_c_writedatain_sel = 2;
OP_LUI:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
OP_LW:
ctrl_mux4to1_reg_file_c_writedatain_sel = 2;
OP_ORI:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
OP_SLTI:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
OP_SLTIU:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
OP_SPECIAL:
casex (pipereg41_q)
FUNC_ADD:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_ADDU:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_AND:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_JALR:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_MFHI:
ctrl_mux4to1_reg_file_c_writedatain_sel = 1;
FUNC_MFLO:
ctrl_mux4to1_reg_file_c_writedatain_sel = 0;
FUNC_NOR:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_OR:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_SLL:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_SLLV:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_SLT:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_SLTU:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_SRA:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_SRAV:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_SRL:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_SRLV:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_SUB:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_SUBU:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
FUNC_XOR:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
endcase
OP_XORI:
ctrl_mux4to1_reg_file_c_writedatain_sel = 3;
endcase
end
//Logic for enable signals in Pipe Stage 6
always@(pipereg40_q or pipereg41_q or pipereg42_q[0]) //or 1'b0)
begin
ctrl_reg_file_c_we = 0;
casex (pipereg40_q)
OP_ADDI:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_ADDIU:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_ANDI:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_JAL:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LB:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LBU:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LH:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LHU:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LUI:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_LW:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_ORI:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_SLTI:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_SLTIU:
ctrl_reg_file_c_we = 1 &~1'b0;
OP_SPECIAL:
casex (pipereg41_q)
FUNC_ADD:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_ADDU:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_AND:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_JALR:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_MFHI:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_MFLO:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_NOR:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_OR:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SLL:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SLLV:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SLT:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SLTU:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SRA:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SRAV:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SRL:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SRLV:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SUB:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_SUBU:
ctrl_reg_file_c_we = 1 &~1'b0;
FUNC_XOR:
ctrl_reg_file_c_we = 1 &~1'b0;
endcase
OP_XORI:
ctrl_reg_file_c_we = 1 &~1'b0;
endcase
end
/********* Stall Network & PipeReg Control ********/
assign stall_out_stage1 = stall_out_stage2|stall_2nd_delayslot;
assign ctrl_pipereg30_en = ~stall_out_stage1;
assign ctrl_pipereg29_en = ~stall_out_stage1;
assign ctrl_pipereg28_en = ~stall_out_stage1;
assign ctrl_pipereg2_en = ~stall_out_stage1;
assign ctrl_pipereg3_en = ~stall_out_stage1;
assign ctrl_pipereg_en = ~stall_out_stage1;
assign ctrl_pipereg5_en = ~stall_out_stage1;
assign ctrl_pipereg4_en = ~stall_out_stage1;
assign ctrl_pipereg11_en = ~stall_out_stage1;
assign ctrl_pipereg1_en = ~stall_out_stage1;
assign ctrl_pipereg44_en = ~stall_out_stage1;
assign stall_out_stage2 = stall_out_stage3|haz_pipereg5_q_pipereg27_q|haz_pipereg4_q_pipereg27_q|haz_pipereg5_q_pipereg26_q|haz_pipereg4_q_pipereg26_q|haz_pipereg4_q_pipereg12_q|haz_pipereg5_q_pipereg25_q|haz_pipereg4_q_pipereg25_q|haz_pipereg5_q_pipereg12_q;
assign ctrl_pipereg33_en = ~stall_out_stage2;
assign ctrl_pipereg32_en = ~stall_out_stage2;
assign ctrl_pipereg31_en = ~stall_out_stage2;
assign ctrl_pipereg7_en = ~stall_out_stage2;
assign ctrl_pipereg9_en = ~stall_out_stage2;
assign ctrl_pipereg8_en = ~stall_out_stage2;
assign ctrl_pipereg12_en = ~stall_out_stage2;
assign ctrl_pipereg6_en = ~stall_out_stage2;
assign stall_out_stage3 = stall_out_stage4;
assign ctrl_pipereg36_en = ~stall_out_stage3;
assign ctrl_pipereg35_en = ~stall_out_stage3;
assign ctrl_pipereg34_en = ~stall_out_stage3;
assign ctrl_pipereg14_en = ~stall_out_stage3;
assign ctrl_pipereg15_en = ~stall_out_stage3;
assign ctrl_pipereg13_en = ~stall_out_stage3;
assign ctrl_pipereg19_en = ~stall_out_stage3;
assign ctrl_pipereg18_en = ~stall_out_stage3;
assign ctrl_pipereg17_en = ~stall_out_stage3;
assign ctrl_pipereg25_en = ~stall_out_stage3;
assign ctrl_pipereg16_en = ~stall_out_stage3;
assign stall_out_stage4 = stall_out_stage5;
assign ctrl_pipereg39_en = ~stall_out_stage4;
assign ctrl_pipereg38_en = ~stall_out_stage4;
assign ctrl_pipereg37_en = ~stall_out_stage4;
assign ctrl_pipereg26_en = ~stall_out_stage4;
assign ctrl_pipereg22_en = ~stall_out_stage4;
assign stall_out_stage5 = stall_out_stage6;
assign ctrl_pipereg42_en = ~stall_out_stage5;
assign ctrl_pipereg41_en = ~stall_out_stage5;
assign ctrl_pipereg40_en = ~stall_out_stage5;
assign ctrl_pipereg23_en = ~stall_out_stage5;
assign ctrl_pipereg27_en = ~stall_out_stage5;
assign ctrl_pipereg24_en = ~stall_out_stage5;
assign stall_out_stage6 = 1'b0;
assign branch_mispred = (((ctrl_ifetch_op==1) || (ctrl_ifetch_op==0 && pipereg14_q)) & ctrl_ifetch_we);
assign stall_2nd_delayslot = branch_detector_is_branch&has_delayslot;
assign has_delayslot = pipereg44_q|pipereg43_q;
assign squash_stage1 = ((stall_out_stage1&~stall_out_stage2))|~resetn;
assign ctrl_pipereg30_resetn = ~squash_stage1;
assign ctrl_pipereg29_resetn = ~squash_stage1;
assign ctrl_pipereg28_resetn = ~squash_stage1;
assign ctrl_pipereg2_resetn = ~squash_stage1;
assign ctrl_pipereg3_resetn = ~squash_stage1;
assign ctrl_pipereg_resetn = ~squash_stage1;
assign ctrl_pipereg5_resetn = ~squash_stage1;
assign ctrl_pipereg4_resetn = ~squash_stage1;
assign ctrl_pipereg11_resetn = ~squash_stage1;
assign ctrl_pipereg1_resetn = ~squash_stage1;
assign ctrl_pipereg44_resetn = ~squash_stage1;
assign ctrl_pipereg44_squashn = ~(branch_mispred&~(pipereg43_q&~stall_out_stage1 | pipereg44_q&stall_out_stage1));
assign ctrl_pipereg1_squashn = ~(branch_mispred&~(pipereg43_q&~stall_out_stage1 | pipereg44_q&stall_out_stage1));
assign ctrl_pipereg11_squashn = ~(branch_mispred&~(pipereg43_q&~stall_out_stage1 | pipereg44_q&stall_out_stage1));
assign ctrl_pipereg4_squashn = ~(branch_mispred&~(pipereg43_q&~stall_out_stage1 | pipereg44_q&stall_out_stage1));
assign ctrl_pipereg5_squashn = ~(branch_mispred&~(pipereg43_q&~stall_out_stage1 | pipereg44_q&stall_out_stage1));
assign ctrl_pipereg_squashn = ~(branch_mispred&~(pipereg43_q&~stall_out_stage1 | pipereg44_q&stall_out_stage1));
assign ctrl_pipereg3_squashn = ~(branch_mispred&~(pipereg43_q&~stall_out_stage1 | pipereg44_q&stall_out_stage1));
assign ctrl_pipereg2_squashn = ~(branch_mispred&~(pipereg43_q&~stall_out_stage1 | pipereg44_q&stall_out_stage1));
assign ctrl_pipereg28_squashn = ~(branch_mispred&~(pipereg43_q&~stall_out_stage1 | pipereg44_q&stall_out_stage1));
assign ctrl_pipereg29_squashn = ~(branch_mispred&~(pipereg43_q&~stall_out_stage1 | pipereg44_q&stall_out_stage1));
assign ctrl_pipereg30_squashn = ~(branch_mispred&~(pipereg43_q&~stall_out_stage1 | pipereg44_q&stall_out_stage1));
assign ctrl_ifetch_squashn = ~(branch_mispred&~(pipereg43_q));
assign squash_stage2 = ((stall_out_stage2&~stall_out_stage3))|~resetn;
assign ctrl_pipereg33_resetn = ~squash_stage2;
assign ctrl_pipereg32_resetn = ~squash_stage2;
assign ctrl_pipereg31_resetn = ~squash_stage2;
assign ctrl_pipereg7_resetn = ~squash_stage2;
assign ctrl_pipereg9_resetn = ~squash_stage2;
assign ctrl_pipereg8_resetn = ~squash_stage2;
assign ctrl_pipereg12_resetn = ~squash_stage2;
assign ctrl_pipereg6_resetn = ~squash_stage2;
assign ctrl_pipereg6_squashn = ~(branch_mispred&~(pipereg44_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg12_squashn = ~(branch_mispred&~(pipereg44_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg8_squashn = ~(branch_mispred&~(pipereg44_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg9_squashn = ~(branch_mispred&~(pipereg44_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg7_squashn = ~(branch_mispred&~(pipereg44_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg31_squashn = ~(branch_mispred&~(pipereg44_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg32_squashn = ~(branch_mispred&~(pipereg44_q&~stall_out_stage2 | 1&stall_out_stage2));
assign ctrl_pipereg33_squashn = ~(branch_mispred&~(pipereg44_q&~stall_out_stage2 | 1&stall_out_stage2));
assign squash_stage3 = ((stall_out_stage3&~stall_out_stage4))|~resetn;
assign ctrl_pipereg36_resetn = ~squash_stage3;
assign ctrl_pipereg35_resetn = ~squash_stage3;
assign ctrl_pipereg34_resetn = ~squash_stage3;
assign ctrl_pipereg14_resetn = ~squash_stage3;
assign ctrl_pipereg15_resetn = ~squash_stage3;
assign ctrl_pipereg13_resetn = ~squash_stage3;
assign ctrl_pipereg19_resetn = ~squash_stage3;
assign ctrl_pipereg18_resetn = ~squash_stage3;
assign ctrl_pipereg17_resetn = ~squash_stage3;
assign ctrl_pipereg25_resetn = ~squash_stage3;
assign ctrl_pipereg16_resetn = ~squash_stage3;
assign ctrl_pipereg16_squashn = ~(0);
assign ctrl_pipereg25_squashn = ~(0);
assign ctrl_pipereg17_squashn = ~(0);
assign ctrl_pipereg18_squashn = ~(0);
assign ctrl_pipereg19_squashn = ~(0);
assign ctrl_pipereg13_squashn = ~(0);
assign ctrl_pipereg15_squashn = ~(0);
assign ctrl_pipereg14_squashn = ~(0);
assign ctrl_pipereg34_squashn = ~(0);
assign ctrl_pipereg35_squashn = ~(0);
assign ctrl_pipereg36_squashn = ~(0);
assign squash_stage4 = ((stall_out_stage4&~stall_out_stage5))|~resetn;
assign ctrl_pipereg39_resetn = ~squash_stage4;
assign ctrl_pipereg38_resetn = ~squash_stage4;
assign ctrl_pipereg37_resetn = ~squash_stage4;
assign ctrl_pipereg26_resetn = ~squash_stage4;
assign ctrl_pipereg22_resetn = ~squash_stage4;
assign ctrl_pipereg22_squashn = ~(0);
assign ctrl_pipereg26_squashn = ~(0);
assign ctrl_pipereg37_squashn = ~(0);
assign ctrl_pipereg38_squashn = ~(0);
assign ctrl_pipereg39_squashn = ~(0);
assign squash_stage5 = ((stall_out_stage5&~stall_out_stage6))|~resetn;
assign ctrl_pipereg42_resetn = ~squash_stage5;
assign ctrl_pipereg41_resetn = ~squash_stage5;
assign ctrl_pipereg40_resetn = ~squash_stage5;
assign ctrl_pipereg23_resetn = ~squash_stage5;
assign ctrl_pipereg27_resetn = ~squash_stage5;
assign ctrl_pipereg24_resetn = ~squash_stage5;
assign ctrl_pipereg24_squashn = ~(0);
assign ctrl_pipereg27_squashn = ~(0);
assign ctrl_pipereg23_squashn = ~(0);
assign ctrl_pipereg40_squashn = ~(0);
assign ctrl_pipereg41_squashn = ~(0);
assign ctrl_pipereg42_squashn = ~(0);
assign squash_stage6 = ((stall_out_stage6&~1'b0))|~resetn;
/****************************** Datapath **************************/
/******************** Hazard Detection Logic ***********************/
assign haz_pipereg5_q_pipereg27_q = (pipereg5_q==pipereg27_q) && (|pipereg5_q);
assign haz_pipereg4_q_pipereg27_q = (pipereg4_q==pipereg27_q) && (|pipereg4_q);
assign haz_pipereg5_q_pipereg26_q = (pipereg5_q==pipereg26_q) && (|pipereg5_q);
assign haz_pipereg4_q_pipereg26_q = (pipereg4_q==pipereg26_q) && (|pipereg4_q);
assign haz_pipereg5_q_pipereg25_q = (pipereg5_q==pipereg25_q) && (|pipereg5_q);
assign haz_pipereg4_q_pipereg25_q = (pipereg4_q==pipereg25_q) && (|pipereg4_q);
assign haz_pipereg5_q_pipereg12_q = (pipereg5_q==pipereg12_q) && (|pipereg5_q);
assign haz_pipereg4_q_pipereg12_q = (pipereg4_q==pipereg12_q) && (|pipereg4_q);
/*************** DATAPATH COMPONENTS **************/
addersub addersub (
.opB(pipereg16_q),
.opA(mux2to1_addersub_opA_out),
.op(ctrl_addersub_op),
.result_slt(addersub_result_slt),
.result(addersub_result));
defparam
addersub.WIDTH=32;
mul mul (
.clk(clk),
.resetn(resetn),
.sa(pipereg18_q),
.opB(pipereg19_q),
.opA(mux2to1_mul_opA_out),
.op(ctrl_mul_op),
.shift_result(mul_shift_result),
.lo(mul_lo),
.hi(mul_hi));
defparam
mul.WIDTH=32;
ifetch ifetch (
.clk(clk),
.resetn(resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe),
.load(pipereg14_q),
.load_data(pipereg13_q),
.op(ctrl_ifetch_op),
.we(ctrl_ifetch_we),
.squashn(ctrl_ifetch_squashn),
.en(ctrl_ifetch_en),
.pc_out(ifetch_pc_out),
.instr(ifetch_instr),
.opcode(ifetch_opcode),
.func(ifetch_func),
.rs(ifetch_rs),
.rt(ifetch_rt),
.rd(ifetch_rd),
.instr_index(ifetch_instr_index),
.offset(ifetch_offset),
.sa(ifetch_sa),
.next_pc(ifetch_next_pc[31:2]));
data_mem data_mem (
.clk(clk),
.resetn(resetn),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe),
.d_address(addersub_result),
.d_writedata(pipereg19_q),
.op(ctrl_data_mem_op),
.en(ctrl_data_mem_en),
.d_loadresult(data_mem_d_loadresult),
.d_wr(d_wr),
.d_byteena(d_byteena),
.d_writedatamem(d_writedatamem),
.d_readdatain(d_readdatain));
reg_file_spree reg_file (
.clk(clk),
.resetn(resetn),
.c_writedatain(mux4to1_reg_file_c_writedatain_out),
.c_reg(pipereg27_q),
.b_reg(pipereg5_q),
.a_reg(pipereg4_q),
.c_we(ctrl_reg_file_c_we),
.b_en(ctrl_reg_file_b_en),
.a_en(ctrl_reg_file_a_en),
.b_readdataout(reg_file_b_readdataout),
.a_readdataout(reg_file_a_readdataout));
logic_unit logic_unit (
.opB(pipereg16_q),
.opA(pipereg17_q),
.op(ctrl_logic_unit_op),
.result(logic_unit_result));
defparam
logic_unit.WIDTH=32;
pcadder pcadder (
.offset(pipereg6_q),
.pc(pipereg9_q),
.result(pcadder_result));
signext16 signext16 (
.in(pipereg1_q),
.out(signext16_out));
merge26lo merge26lo (
.in2(pipereg7_q),
.in1(pipereg9_q),
.out(merge26lo_out));
branchresolve branchresolve (
.rt(reg_file_b_readdataout),
.rs(reg_file_a_readdataout),
.en(ctrl_branchresolve_en),
.eqz(branchresolve_eqz),
.gez(branchresolve_gez),
.gtz(branchresolve_gtz),
.lez(branchresolve_lez),
.ltz(branchresolve_ltz),
.ne(branchresolve_ne),
.eq(branchresolve_eq));
defparam
branchresolve.WIDTH=32;
hi_reg hi_reg (
.clk(clk),
.resetn(resetn),
.d(mul_hi),
.en(ctrl_hi_reg_en),
.q(hi_reg_q));
defparam
hi_reg.WIDTH=32;
lo_reg lo_reg (
.clk(clk),
.resetn(resetn),
.d(mul_lo),
.en(ctrl_lo_reg_en),
.q(lo_reg_q));
defparam
lo_reg.WIDTH=32;
const const20 (
.out(const20_out));
defparam
const20.WIDTH=32,
const20.VAL=0;
const const (
.out(const_out));
defparam
const.WIDTH=32,
const.VAL=31;
pipereg pipereg5 (
.clk(clk),
.resetn(ctrl_pipereg5_resetn),
.d(zeroer_q),
.squashn(ctrl_pipereg5_squashn),
.en(ctrl_pipereg5_en),
.q(pipereg5_q));
defparam
pipereg5.WIDTH=5;
pipereg pipereg11 (
.clk(clk),
.resetn(ctrl_pipereg11_resetn),
.d(zeroer10_q),
.squashn(ctrl_pipereg11_squashn),
.en(ctrl_pipereg11_en),
.q(pipereg11_q));
defparam
pipereg11.WIDTH=5;
pipereg pipereg1 (
.clk(clk),
.resetn(ctrl_pipereg1_resetn),
.d(ifetch_offset),
.squashn(ctrl_pipereg1_squashn),
.en(ctrl_pipereg1_en),
.q(pipereg1_q));
defparam
pipereg1.WIDTH=16;
pipereg pipereg4 (
.clk(clk),
.resetn(ctrl_pipereg4_resetn),
.d(zeroer0_q),
.squashn(ctrl_pipereg4_squashn),
.en(ctrl_pipereg4_en),
.q(pipereg4_q));
defparam
pipereg4.WIDTH=5;
pipereg pipereg (
.clk(clk),
.resetn(ctrl_pipereg_resetn),
.d(ifetch_sa),
.squashn(ctrl_pipereg_squashn),
.en(ctrl_pipereg_en),
.q(pipereg_q));
defparam
pipereg.WIDTH=5;
pipereg pipereg2 (
.clk(clk),
.resetn(ctrl_pipereg2_resetn),
.d(ifetch_instr_index),
.squashn(ctrl_pipereg2_squashn),
.en(ctrl_pipereg2_en),
.q(pipereg2_q));
defparam
pipereg2.WIDTH=26;
pipereg pipereg6 (
.clk(clk),
.resetn(ctrl_pipereg6_resetn),
.d(mux2to1_pipereg6_d_out),
.squashn(ctrl_pipereg6_squashn),
.en(ctrl_pipereg6_en),
.q(pipereg6_q));
defparam
pipereg6.WIDTH=32;
pipereg pipereg3 (
.clk(clk),
.resetn(ctrl_pipereg3_resetn),
.d(ifetch_pc_out),
.squashn(ctrl_pipereg3_squashn),
.en(ctrl_pipereg3_en),
.q(pipereg3_q));
defparam
pipereg3.WIDTH=32;
pipereg pipereg7 (
.clk(clk),
.resetn(ctrl_pipereg7_resetn),
.d(pipereg2_q),
.squashn(ctrl_pipereg7_squashn),
.en(ctrl_pipereg7_en),
.q(pipereg7_q));
defparam
pipereg7.WIDTH=26;
pipereg pipereg8 (
.clk(clk),
.resetn(ctrl_pipereg8_resetn),
.d(pipereg_q),
.squashn(ctrl_pipereg8_squashn),
.en(ctrl_pipereg8_en),
.q(pipereg8_q));
defparam
pipereg8.WIDTH=5;
const const21 (
.out(const21_out));
defparam
const21.WIDTH=32,
const21.VAL=16;
pipereg pipereg9 (
.clk(clk),
.resetn(ctrl_pipereg9_resetn),
.d(pipereg3_q),
.squashn(ctrl_pipereg9_squashn),
.en(ctrl_pipereg9_en),
.q(pipereg9_q));
defparam
pipereg9.WIDTH=32;
pipereg pipereg17 (
.clk(clk),
.resetn(ctrl_pipereg17_resetn),
.d(reg_file_a_readdataout),
.squashn(ctrl_pipereg17_squashn),
.en(ctrl_pipereg17_en),
.q(pipereg17_q));
defparam
pipereg17.WIDTH=32;
pipereg pipereg18 (
.clk(clk),
.resetn(ctrl_pipereg18_resetn),
.d(mux3to1_pipereg18_d_out),
.squashn(ctrl_pipereg18_squashn),
.en(ctrl_pipereg18_en),
.q(pipereg18_q));
defparam
pipereg18.WIDTH=5;
pipereg pipereg19 (
.clk(clk),
.resetn(ctrl_pipereg19_resetn),
.d(reg_file_b_readdataout),
.squashn(ctrl_pipereg19_squashn),
.en(ctrl_pipereg19_en),
.q(pipereg19_q));
defparam
pipereg19.WIDTH=32;
pipereg pipereg16 (
.clk(clk),
.resetn(ctrl_pipereg16_resetn),
.d(mux3to1_pipereg16_d_out),
.squashn(ctrl_pipereg16_squashn),
.en(ctrl_pipereg16_en),
.q(pipereg16_q));
defparam
pipereg16.WIDTH=32;
pipereg pipereg15 (
.clk(clk),
.resetn(ctrl_pipereg15_resetn),
.d(fakedelay_q),
.squashn(ctrl_pipereg15_squashn),
.en(ctrl_pipereg15_en),
.q(pipereg15_q));
defparam
pipereg15.WIDTH=32;
pipereg pipereg14 (
.clk(clk),
.resetn(ctrl_pipereg14_resetn),
.d(mux6to1_pipereg14_d_out),
.squashn(ctrl_pipereg14_squashn),
.en(ctrl_pipereg14_en),
.q(pipereg14_q));
defparam
pipereg14.WIDTH=1;
pipereg pipereg13 (
.clk(clk),
.resetn(ctrl_pipereg13_resetn),
.d(mux3to1_pipereg13_d_out),
.squashn(ctrl_pipereg13_squashn),
.en(ctrl_pipereg13_en),
.q(pipereg13_q));
defparam
pipereg13.WIDTH=32;
pipereg pipereg22 (
.clk(clk),
.resetn(ctrl_pipereg22_resetn),
.d(mux3to1_pipereg22_d_out),
.squashn(ctrl_pipereg22_squashn),
.en(ctrl_pipereg22_en),
.q(pipereg22_q));
defparam
pipereg22.WIDTH=32;
pipereg pipereg12 (
.clk(clk),
.resetn(ctrl_pipereg12_resetn),
.d(pipereg11_q),
.squashn(ctrl_pipereg12_squashn),
.en(ctrl_pipereg12_en),
.q(pipereg12_q));
defparam
pipereg12.WIDTH=5;
pipereg pipereg23 (
.clk(clk),
.resetn(ctrl_pipereg23_resetn),
.d(data_mem_d_loadresult),
.squashn(ctrl_pipereg23_squashn),
.en(ctrl_pipereg23_en),
.q(pipereg23_q));
defparam
pipereg23.WIDTH=32;
pipereg pipereg25 (
.clk(clk),
.resetn(ctrl_pipereg25_resetn),
.d(pipereg12_q),
.squashn(ctrl_pipereg25_squashn),
.en(ctrl_pipereg25_en),
.q(pipereg25_q));
defparam
pipereg25.WIDTH=5;
pipereg pipereg26 (
.clk(clk),
.resetn(ctrl_pipereg26_resetn),
.d(pipereg25_q),
.squashn(ctrl_pipereg26_squashn),
.en(ctrl_pipereg26_en),
.q(pipereg26_q));
defparam
pipereg26.WIDTH=5;
pipereg pipereg27 (
.clk(clk),
.resetn(ctrl_pipereg27_resetn),
.d(pipereg26_q),
.squashn(ctrl_pipereg27_squashn),
.en(ctrl_pipereg27_en),
.q(pipereg27_q));
defparam
pipereg27.WIDTH=5;
fakedelay fakedelay (
.clk(clk),
.d(pipereg3_q),
.q(fakedelay_q));
defparam
fakedelay.WIDTH=32;
zeroer zeroer0 (
.d(ifetch_rs),
.en(ctrl_zeroer0_en),
.q(zeroer0_q));
defparam
zeroer0.WIDTH=5;
zeroer zeroer10 (
.d(mux3to1_zeroer10_d_out),
.en(ctrl_zeroer10_en),
.q(zeroer10_q));
defparam
zeroer10.WIDTH=5;
zeroer zeroer (
.d(ifetch_rt),
.en(ctrl_zeroer_en),
.q(zeroer_q));
defparam
zeroer.WIDTH=5;
pipereg pipereg24 (
.clk(clk),
.resetn(ctrl_pipereg24_resetn),
.d(mux2to1_pipereg24_d_out),
.squashn(ctrl_pipereg24_squashn),
.en(ctrl_pipereg24_en),
.q(pipereg24_q));
defparam
pipereg24.WIDTH=32;
// Multiplexor mux2to1_mul_opA instantiation
assign mux2to1_mul_opA_out =
(ctrl_mux2to1_mul_opA_sel==1) ? pipereg17_q :
pipereg16_q;
// Multiplexor mux2to1_pipereg6_d instantiation
assign mux2to1_pipereg6_d_out =
(ctrl_mux2to1_pipereg6_d_sel==1) ? pipereg1_q :
signext16_out;
// Multiplexor mux2to1_addersub_opA instantiation
assign mux2to1_addersub_opA_out =
(ctrl_mux2to1_addersub_opA_sel==1) ? pipereg15_q :
pipereg17_q;
// Multiplexor mux4to1_reg_file_c_writedatain instantiation
assign mux4to1_reg_file_c_writedatain_out =
(ctrl_mux4to1_reg_file_c_writedatain_sel==3) ? pipereg24_q :
(ctrl_mux4to1_reg_file_c_writedatain_sel==2) ? pipereg23_q :
(ctrl_mux4to1_reg_file_c_writedatain_sel==1) ? hi_reg_q :
lo_reg_q;
// Multiplexor mux3to1_pipereg18_d instantiation
assign mux3to1_pipereg18_d_out =
(ctrl_mux3to1_pipereg18_d_sel==2) ? reg_file_a_readdataout :
(ctrl_mux3to1_pipereg18_d_sel==1) ? const21_out :
pipereg8_q;
// Multiplexor mux3to1_pipereg16_d instantiation
assign mux3to1_pipereg16_d_out =
(ctrl_mux3to1_pipereg16_d_sel==2) ? pipereg6_q :
(ctrl_mux3to1_pipereg16_d_sel==1) ? reg_file_b_readdataout :
const20_out;
// Multiplexor mux6to1_pipereg14_d instantiation
assign mux6to1_pipereg14_d_out =
(ctrl_mux6to1_pipereg14_d_sel==5) ? branchresolve_eq :
(ctrl_mux6to1_pipereg14_d_sel==4) ? branchresolve_ne :
(ctrl_mux6to1_pipereg14_d_sel==3) ? branchresolve_lez :
(ctrl_mux6to1_pipereg14_d_sel==2) ? branchresolve_ltz :
(ctrl_mux6to1_pipereg14_d_sel==1) ? branchresolve_gez :
branchresolve_gtz;
// Multiplexor mux2to1_pipereg24_d instantiation
assign mux2to1_pipereg24_d_out =
(ctrl_mux2to1_pipereg24_d_sel==1) ? pipereg22_q :
mul_shift_result;
// Multiplexor mux3to1_pipereg13_d instantiation
assign mux3to1_pipereg13_d_out =
(ctrl_mux3to1_pipereg13_d_sel==2) ? pcadder_result :
(ctrl_mux3to1_pipereg13_d_sel==1) ? merge26lo_out :
reg_file_a_readdataout;
// Multiplexor mux3to1_zeroer10_d instantiation
assign mux3to1_zeroer10_d_out =
(ctrl_mux3to1_zeroer10_d_sel==2) ? ifetch_rt :
(ctrl_mux3to1_zeroer10_d_sel==1) ? ifetch_rd :
const_out;
// Multiplexor mux3to1_pipereg22_d instantiation
assign mux3to1_pipereg22_d_out =
(ctrl_mux3to1_pipereg22_d_sel==2) ? addersub_result :
(ctrl_mux3to1_pipereg22_d_sel==1) ? addersub_result_slt :
logic_unit_result;
pipereg pipereg28 (
.clk(clk),
.resetn(ctrl_pipereg28_resetn),
.d(ifetch_opcode),
.squashn(ctrl_pipereg28_squashn),
.en(ctrl_pipereg28_en),
.q(pipereg28_q));
defparam
pipereg28.WIDTH=6;
pipereg pipereg31 (
.clk(clk),
.resetn(ctrl_pipereg31_resetn),
.d(pipereg28_q),
.squashn(ctrl_pipereg31_squashn),
.en(ctrl_pipereg31_en),
.q(pipereg31_q));
defparam
pipereg31.WIDTH=6;
pipereg pipereg32 (
.clk(clk),
.resetn(ctrl_pipereg32_resetn),
.d(pipereg29_q),
.squashn(ctrl_pipereg32_squashn),
.en(ctrl_pipereg32_en),
.q(pipereg32_q));
defparam
pipereg32.WIDTH=6;
pipereg pipereg34 (
.clk(clk),
.resetn(ctrl_pipereg34_resetn),
.d(pipereg31_q),
.squashn(ctrl_pipereg34_squashn),
.en(ctrl_pipereg34_en),
.q(pipereg34_q));
defparam
pipereg34.WIDTH=6;
pipereg pipereg33 (
.clk(clk),
.resetn(ctrl_pipereg33_resetn),
.d(pipereg30_q),
.squashn(ctrl_pipereg33_squashn),
.en(ctrl_pipereg33_en),
.q(pipereg33_q));
defparam
pipereg33.WIDTH=5;
pipereg pipereg36 (
.clk(clk),
.resetn(ctrl_pipereg36_resetn),
.d(pipereg33_q),
.squashn(ctrl_pipereg36_squashn),
.en(ctrl_pipereg36_en),
.q(pipereg36_q));
defparam
pipereg36.WIDTH=5;
pipereg pipereg35 (
.clk(clk),
.resetn(ctrl_pipereg35_resetn),
.d(pipereg32_q),
.squashn(ctrl_pipereg35_squashn),
.en(ctrl_pipereg35_en),
.q(pipereg35_q));
defparam
pipereg35.WIDTH=6;
pipereg pipereg30 (
.clk(clk),
.resetn(ctrl_pipereg30_resetn),
.d(ifetch_rt),
.squashn(ctrl_pipereg30_squashn),
.en(ctrl_pipereg30_en),
.q(pipereg30_q));
defparam
pipereg30.WIDTH=5;
pipereg pipereg29 (
.clk(clk),
.resetn(ctrl_pipereg29_resetn),
.d(ifetch_func),
.squashn(ctrl_pipereg29_squashn),
.en(ctrl_pipereg29_en),
.q(pipereg29_q));
defparam
pipereg29.WIDTH=6;
pipereg pipereg38 (
.clk(clk),
.resetn(ctrl_pipereg38_resetn),
.d(pipereg35_q),
.squashn(ctrl_pipereg38_squashn),
.en(ctrl_pipereg38_en),
.q(pipereg38_q));
defparam
pipereg38.WIDTH=6;
pipereg pipereg39 (
.clk(clk),
.resetn(ctrl_pipereg39_resetn),
.d(pipereg36_q),
.squashn(ctrl_pipereg39_squashn),
.en(ctrl_pipereg39_en),
.q(pipereg39_q));
defparam
pipereg39.WIDTH=5;
pipereg pipereg40 (
.clk(clk),
.resetn(ctrl_pipereg40_resetn),
.d(pipereg37_q),
.squashn(ctrl_pipereg40_squashn),
.en(ctrl_pipereg40_en),
.q(pipereg40_q));
defparam
pipereg40.WIDTH=6;
pipereg pipereg41 (
.clk(clk),
.resetn(ctrl_pipereg41_resetn),
.d(pipereg38_q),
.squashn(ctrl_pipereg41_squashn),
.en(ctrl_pipereg41_en),
.q(pipereg41_q));
defparam
pipereg41.WIDTH=6;
pipereg pipereg42 (
.clk(clk),
.resetn(ctrl_pipereg42_resetn),
.d(pipereg39_q),
.squashn(ctrl_pipereg42_squashn),
.en(ctrl_pipereg42_en),
.q(pipereg42_q));
defparam
pipereg42.WIDTH=5;
pipereg pipereg37 (
.clk(clk),
.resetn(ctrl_pipereg37_resetn),
.d(pipereg34_q),
.squashn(ctrl_pipereg37_squashn),
.en(ctrl_pipereg37_en),
.q(pipereg37_q));
defparam
pipereg37.WIDTH=6;
branch_detector branch_detector (
.func(ifetch_func),
.opcode(ifetch_opcode),
.is_branch(branch_detector_is_branch));
pipereg pipereg43 (
.clk(clk),
.resetn(resetn),
.d(branch_detector_is_branch),
.squashn(~branch_mispred),
.en(~stall_out_stage1),
.q(pipereg43_q));
defparam
pipereg43.WIDTH=1;
pipereg pipereg44 (
.clk(clk),
.resetn(ctrl_pipereg44_resetn),
.d(pipereg43_q),
.squashn(ctrl_pipereg44_squashn),
.en(ctrl_pipereg44_en),
.q(pipereg44_q));
defparam
pipereg44.WIDTH=1;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////////////////////////
//
// This module facilitates a transition between two clock domains. We assume that the input
// is provided in the clock2x domain serially and is to be provided as a double-data element in
// the clock domain.
//
///////////////////////////////////////////////////////////////////////////////////////////////////
module acl_stream_to_vector_converter(
clock, clock2x, resetn,
dataa, y1, y2,
valid_in, valid_out, stall_in, stall_out);
parameter WIDTH = 32;
input clock, clock2x, resetn, valid_in, stall_in;
input [WIDTH-1:0] dataa;
output [WIDTH-1:0] y1;
output [WIDTH-1:0] y2;
output valid_out;
output stall_out;
// Add staging register at the input.
reg [WIDTH-1:0] dataa_sr /* synthesis preserve */;
reg sr_in_valid;
wire stall_sr;
always@(posedge clock2x or negedge resetn)
begin
if(~resetn)
begin
sr_in_valid <= 1'b0;
dataa_sr <= {WIDTH{1'bx}};
end
else
begin
if (~stall_sr)
sr_in_valid <= 1'b0;
else if (~sr_in_valid)
sr_in_valid <= valid_in;
if (~sr_in_valid)
dataa_sr <= dataa;
end
end
assign stall_out = sr_in_valid;
// Prevent sharing of these registers across different instances
// (and even kernels!). The sharing may cause very long paths
// across the chip, which limits fmax of clock2x.
reg sel, sel_ref /* synthesis preserve */;
initial
begin
sel = 1'b0;
sel_ref = 1'b0;
end
always@(posedge clock2x)
begin
sel <= ~sel;
end
// Register the data in the 'clock2x' domain.
reg [WIDTH-1:0] in_a2 /* synthesis preserve */;
reg [WIDTH-1:0] in_a1 /* synthesis preserve */;
reg valid_a2, valid_a1 /* synthesis preserve */;
wire stall_shift;
always@(posedge clock2x or negedge resetn)
begin
if (~resetn)
begin
valid_a2 <= 1'b0;
valid_a1 <= 1'b0;
in_a1 <= {WIDTH{1'bx}};
in_a2 <= {WIDTH{1'bx}};
end
else
begin
if (~valid_a2)
begin
valid_a2 <= sr_in_valid | valid_in;
in_a2 <= sr_in_valid ? dataa_sr : dataa;
valid_a1 <= 1'b0;
end
else if ((~valid_a1) & (sr_in_valid | valid_in))
begin
valid_a2 <= 1'b1;
in_a2 <= sr_in_valid ? dataa_sr : dataa;
valid_a1 <= valid_a2;
in_a1 <= in_a2;
end
else if (valid_a1 & valid_a2 & ~stall_shift)
begin
valid_a2 <= sr_in_valid | valid_in;
in_a2 <= sr_in_valid ? dataa_sr : dataa;
valid_a1 <= 1'b0;
end
end
end
assign stall_sr = valid_a1 & stall_shift;
reg [WIDTH-1:0] y2_r /* synthesis preserve */;
reg [WIDTH-1:0] y1_r /* synthesis preserve */;
reg valid_crossing /* synthesis preserve */;
wire stall_last;
wire w = (sel_ref == sel); // = 1 when just prior to positive edge of 'clock'
always@(posedge clock or negedge resetn)
begin
if(~resetn)
begin
sel_ref <= 1'b0;
valid_crossing <= 1'b0;
y1_r <= {WIDTH{1'bx}};
y2_r <= {WIDTH{1'bx}};
end
else
begin
if (~valid_crossing | ~stall_last)
begin
y1_r <= in_a1;
y2_r <= in_a2;
valid_crossing <= valid_a1;
end
sel_ref <= sel;
end
end
assign stall_shift = ~w | valid_crossing & stall_last;
// Staging register
reg valid_out_sr;
reg [WIDTH-1:0] y1_sr /* synthesis preserve */;
reg [WIDTH-1:0] y2_sr /* synthesis preserve */;
assign stall_last = valid_out_sr;
always@(posedge clock or negedge resetn)
begin
if(~resetn)
begin
valid_out_sr <= 1'b0;
y1_sr <= {WIDTH{1'bx}};
y2_sr <= {WIDTH{1'bx}};
end
else
begin
if (~stall_in)
valid_out_sr <= 1'b0;
else if (~valid_out_sr)
valid_out_sr <= valid_crossing;
if (~valid_out_sr)
begin
y1_sr <= y1_r;
y2_sr <= y2_r;
end
end
end
assign y1 = valid_out_sr ? y1_sr : y1_r;
assign y2 = valid_out_sr ? y2_sr : y2_r;
assign valid_out = valid_out_sr | valid_crossing;
endmodule
|
/**
* bsg_nonsynth_non_blocking_dma_model.v
*
* There is nothing non-blocking about the DMA model,
* Rather this is only to be used with bsg_cache_non_blocking.
*
*/
module bsg_nonsynth_non_blocking_dma_model
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(addr_width_p)
,parameter `BSG_INV_PARAM(data_width_p)
,parameter `BSG_INV_PARAM(block_size_in_words_p)
,parameter `BSG_INV_PARAM(els_p)
,parameter read_delay_p=16
,parameter write_delay_p=16
,parameter dma_req_delay_p=16
,parameter dma_data_delay_p=16
,parameter data_mask_width_lp=(data_width_p>>3)
,parameter lg_data_mask_width_lp=`BSG_SAFE_CLOG2(data_mask_width_lp)
,parameter lg_els_lp=`BSG_SAFE_CLOG2(els_p)
,parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p)
,parameter dma_pkt_width_lp=`bsg_cache_non_blocking_dma_pkt_width(addr_width_p)
)
(
input clk_i
,input reset_i
,input [dma_pkt_width_lp-1:0] dma_pkt_i
,input logic dma_pkt_v_i
,output logic dma_pkt_yumi_o
,output logic [data_width_p-1:0] dma_data_o
,output logic dma_data_v_o
,input dma_data_ready_i
,input [data_width_p-1:0] dma_data_i
,input dma_data_v_i
,output logic dma_data_yumi_o
);
logic [data_width_p-1:0] mem [els_p-1:0];
`declare_bsg_cache_non_blocking_dma_pkt_s(addr_width_p);
bsg_cache_non_blocking_dma_pkt_s dma_pkt;
assign dma_pkt = dma_pkt_i;
typedef enum logic [1:0] {
WAIT
,DELAY
,BUSY
} state_e;
wire start_read = ~dma_pkt.write_not_read & dma_pkt_v_i;
wire start_write = dma_pkt.write_not_read & dma_pkt_v_i;
// read channel
//
logic [addr_width_p-1:0] rd_addr_r, rd_addr_n;
state_e rd_state_r, rd_state_n;
logic [lg_block_size_in_words_lp-1:0] rd_counter_r, rd_counter_n;
integer rd_delay_r, rd_delay_n;
integer rd_data_delay_r, rd_data_delay_n;
wire rd_data_delay_zero = (rd_data_delay_r == 0);
integer rd_req_delay_r, rd_req_delay_n;
wire rd_req_delay_zero = rd_req_delay_r == 0;
logic rd_req_ready;
logic [lg_els_lp-lg_block_size_in_words_lp-1:0] rd_upper_addr;
assign rd_upper_addr = rd_addr_r[lg_data_mask_width_lp+lg_block_size_in_words_lp+:lg_els_lp-lg_block_size_in_words_lp];
assign dma_data_o = mem[{rd_upper_addr, rd_counter_r}];
always_comb begin
dma_data_v_o = 1'b0;
rd_addr_n = rd_addr_r;
rd_counter_n = rd_counter_r;
rd_delay_n = rd_delay_r;
rd_data_delay_n = rd_data_delay_r;
rd_req_delay_n = rd_req_delay_r;
rd_req_ready = 1'b0;
case (rd_state_r)
WAIT: begin
rd_req_ready = start_read & rd_req_delay_zero;
rd_req_delay_n = start_read
? (rd_req_delay_zero
? $urandom_range(dma_req_delay_p,0)
: rd_req_delay_r - 1)
: rd_req_delay_r;
rd_addr_n = start_read & rd_req_delay_zero
? dma_pkt.addr
: rd_addr_r;
rd_counter_n = start_read & rd_req_delay_zero
? '0
: rd_counter_r;
rd_state_n = start_read & rd_req_delay_zero
? DELAY
: WAIT;
rd_delay_n = start_read & rd_req_delay_zero
? $urandom_range(dma_data_delay_p, 0)
: rd_delay_r;
end
DELAY: begin
rd_delay_n = rd_delay_r - 1;
rd_state_n = rd_delay_r == 0
? BUSY
: DELAY;
rd_data_delay_n = (rd_delay_r == 0)
? $urandom_range(dma_data_delay_p, 0)
: rd_data_delay_r;
end
BUSY: begin
rd_data_delay_n = rd_data_delay_zero
? (dma_data_ready_i ? $urandom_range(dma_data_delay_p, 0) : 0)
: rd_data_delay_r - 1;
dma_data_v_o = rd_data_delay_zero;
rd_counter_n = rd_data_delay_zero & dma_data_ready_i
? rd_counter_r + 1
: rd_counter_r;
rd_state_n = rd_data_delay_zero & dma_data_ready_i & (rd_counter_r == block_size_in_words_p-1)
? WAIT
: BUSY;
end
endcase
end
always_ff @ (posedge clk_i) begin
if (reset_i) begin
rd_state_r <= WAIT;
rd_addr_r <= '0;
rd_counter_r <= '0;
rd_delay_r <= '0;
rd_data_delay_r <= '0;
rd_req_delay_r <= '0;
end
else begin
rd_state_r <= rd_state_n;
rd_addr_r <= rd_addr_n;
rd_counter_r <= rd_counter_n;
rd_delay_r <= rd_delay_n;
rd_data_delay_r <= rd_data_delay_n;
rd_req_delay_r <= rd_req_delay_n;
end
end
// write channel
//
logic [addr_width_p-1:0] wr_addr_r, wr_addr_n;
state_e wr_state_r, wr_state_n;
logic [lg_block_size_in_words_lp-1:0] wr_counter_r, wr_counter_n;
integer wr_delay_r, wr_delay_n;
integer wr_data_delay_r, wr_data_delay_n;
wire wr_data_delay_zero = wr_data_delay_r == 0;
integer wr_req_delay_r, wr_req_delay_n;
wire wr_req_delay_zero = wr_req_delay_r == 0;
logic wr_req_ready;
logic [lg_els_lp-lg_block_size_in_words_lp-1:0] wr_upper_addr;
assign wr_upper_addr = wr_addr_r[lg_data_mask_width_lp+lg_block_size_in_words_lp+:lg_els_lp-lg_block_size_in_words_lp];
always_comb begin
wr_addr_n = wr_addr_r;
wr_data_delay_n = wr_data_delay_r;
wr_req_delay_n = wr_req_delay_r;
wr_req_ready = 1'b0;
dma_data_yumi_o = 1'b0;
case (wr_state_r)
WAIT: begin
wr_req_ready = start_write & wr_req_delay_zero;
wr_req_delay_n = start_write
? (wr_req_delay_zero
? $urandom_range(dma_req_delay_p,0)
: wr_req_delay_r - 1)
: wr_req_delay_r;
wr_addr_n = start_write & wr_req_delay_zero
? dma_pkt.addr
: wr_addr_r;
wr_counter_n = start_write & wr_req_delay_zero
? '0
: wr_counter_r;
wr_state_n = start_write & wr_req_delay_zero
? DELAY
: WAIT;
wr_delay_n = start_write & wr_req_delay_zero
? $urandom_range(dma_data_delay_p,0)
: wr_delay_r;
end
DELAY: begin
wr_delay_n = wr_delay_r - 1;
wr_state_n = wr_delay_r == 0
? BUSY
: DELAY;
wr_data_delay_n = (wr_delay_r == 0)
? $urandom_range(dma_data_delay_p, 0)
: wr_data_delay_r;
end
BUSY: begin
wr_data_delay_n = wr_data_delay_zero
? (dma_data_v_i ? $urandom_range(dma_data_delay_p, 0) : 0)
: wr_data_delay_r - 1;
dma_data_yumi_o = dma_data_v_i & wr_data_delay_zero;
wr_counter_n = (dma_data_v_i & wr_data_delay_zero)
? wr_counter_r + 1
: wr_counter_r;
wr_state_n = (wr_counter_r == block_size_in_words_p-1) & dma_data_v_i & wr_data_delay_zero
? WAIT
: BUSY;
end
endcase
end
assign dma_pkt_yumi_o = (start_read & rd_req_ready) | (start_write & wr_req_ready);
// sequential
//
always_ff @ (posedge clk_i) begin
if (reset_i) begin
wr_state_r <= WAIT;
wr_addr_r <= '0;
wr_counter_r <= '0;
wr_delay_r <= '0;
wr_data_delay_r <= '0;
wr_req_delay_r <= '0;
for (integer i = 0; i < els_p; i++) begin
mem[i] <= '0;
end
end
else begin
wr_state_r <= wr_state_n;
wr_addr_r <= wr_addr_n;
wr_counter_r <= wr_counter_n;
wr_delay_r <= wr_delay_n;
wr_data_delay_r <= wr_data_delay_n;
wr_req_delay_r <= wr_req_delay_n;
if ((wr_state_r == BUSY) & dma_data_v_i & dma_data_yumi_o) begin
mem[{wr_upper_addr, wr_counter_r}] <= dma_data_i;
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_non_blocking_dma_model)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31A_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O31A_PP_BLACKBOX_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31A_PP_BLACKBOX_V
|
//======================================================================
//
// avalanche_entropy.v
// -------------------
// Top level wrapper of the entropy provider core based on an external
// avalanche noise based source. (or any other source that can
// toggle a single bit input).
//
// Currently the design consists of a free running counter. At every
// positive flank detected the LSB of the counter is pushed into
// a 32bit shift register.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module avalanche_entropy(
input wire clk,
input wire reset_n,
input wire noise,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
input wire discard,
input wire test_mode,
output wire security_error,
output wire entropy_enabled,
output wire [31 : 0] entropy_data,
output wire entropy_valid,
input wire entropy_ack,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter ADDR_CTRL = 8'h10;
parameter CTRL_ENABLE_BIT = 0;
parameter ADDR_STATUS = 8'h11;
parameter STATUS_ENABLE_VALID_BIT = 0;
parameter ADDR_ENTROPY = 8'h20;
parameter ADDR_DELTA = 8'h30;
parameter CORE_NAME0 = 32'h6578746e; // "extn"
parameter CORE_NAME1 = 32'h6f697365; // "oise"
parameter CORE_VERSION = 32'h302e3130; // "0.10"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg enable_reg;
reg enable_new;
reg enable_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [31 : 0] delta;
reg [31 : 0] tmp_read_data;
reg tmp_error;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = tmp_error;
assign security_error = 0;
assign entropy_enabled = enable_reg;
//----------------------------------------------------------------
// Core instantiation.
//----------------------------------------------------------------
avalanche_entropy_core core(
.clk(clk),
.reset_n(reset_n),
.noise(noise),
.enable(enable_reg),
.entropy_data(entropy_data),
.entropy_valid(entropy_valid),
.entropy_ack(entropy_ack),
.delta(delta),
.debug(debug),
.debug_update(debug_update)
);
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
enable_reg <= 1;
end
else
begin
if (enable_we)
begin
enable_reg <= enable_new;
end
end
end // reg_update
//----------------------------------------------------------------
// api_logic
//----------------------------------------------------------------
always @*
begin : api_logic
tmp_read_data = 32'h00000000;
tmp_error = 1'b0;
enable_new = 0;
enable_we = 0;
if (cs)
begin
if (we)
begin
case (address)
// Write operations.
ADDR_CTRL:
begin
enable_new = write_data[CTRL_ENABLE_BIT];
enable_we = 1;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end // if (we)
else
begin
case (address)
ADDR_NAME0:
begin
tmp_read_data = CORE_NAME0;
end
ADDR_NAME1:
begin
tmp_read_data = CORE_NAME1;
end
ADDR_VERSION:
begin
tmp_read_data = CORE_VERSION;
end
ADDR_CTRL:
begin
tmp_read_data = {31'h00000000, enable_reg};
end
ADDR_STATUS:
begin
tmp_read_data = {31'h00000000, entropy_valid};
end
ADDR_ENTROPY:
begin
tmp_read_data = entropy_data;
end
ADDR_DELTA:
begin
tmp_read_data = delta;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end // else: !if(we)
end // if (cs)
end // api_logic
endmodule // avalanche_entropy
//======================================================================
// EOF avalanche_entropy.v
//======================================================================
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
// Design of the pipe
module pipeline_buffer (in,out,clock,reset);
// Output signal for the design module
output out; // Output data signal
// Input signals for the design module
input in; // Input data signal
input clock; // Input clock signal
input reset; // Input reset signal
// Declare "reg" signals... that will be assigned values
reg out;
reg o1; // Output of flip-flop #1
reg o2; // Output of flip-flop #2
reg o3; // Output of flip-flop #3
reg o4; // Output of flip-flop #4
reg o5; // Output of flip-flop #5
reg o6; // Output of flip-flop #6
reg o7; // Output of flip-flop #7
reg o8; // Output of flip-flop #8
reg o9; // Output of flip-flop #9
reg o10; // Output of flip-flop #10
reg o11; // Output of flip-flop #11
reg o12; // Output of flip-flop #12
reg o13; // Output of flip-flop #13
reg o14; // Output of flip-flop #14
reg o15; // Output of flip-flop #15
reg o16; // Output of flip-flop #16
reg o17; // Output of flip-flop #17
reg o18; // Output of flip-flop #18
reg o19; // Output of flip-flop #19
reg o20; // Output of flip-flop #20
reg o21; // Output of flip-flop #21
reg o22; // Output of flip-flop #22
reg o23; // Output of flip-flop #23
reg o24; // Output of flip-flop #24
reg o25; // Output of flip-flop #25
reg o26; // Output of flip-flop #26
reg o27; // Output of flip-flop #27
reg o28; // Output of flip-flop #28
reg o29; // Output of flip-flop #29
reg o30; // Output of flip-flop #30
reg o31; // Output of flip-flop #31
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// Create the 1st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o1 = 1'd0;
else
o1 = in;
end
// Create the 2nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o2 = 1'd0;
else
o2 = o1;
end
// Create the 3rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o3 = 1'd0;
else
o3 = o2;
end
// Create the 4th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o4 = 1'd0;
else
o4 = o3;
end
// Create the 5th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o5 = 1'd0;
else
o5 = o4;
end
// Create the 6th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o6 = 1'd0;
else
o6 = o5;
end
// Create the 7th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o7 = 1'd0;
else
o7 = o6;
end
// Create the 8th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o8 = 1'd0;
else
o8 = o7;
end
// Create the 9th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o9 = 1'd0;
else
o9 = o8;
end
// Create the 10th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o10 = 1'd0;
else
o10 = o9;
end
// Create the 11th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o11 = 1'd0;
else
o11 = o10;
end
// Create the 12th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o12 = 1'd0;
else
o12 = o11;
end
// Create the 13th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o13 = 1'd0;
else
o13 = o12;
end
// Create the 14th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o14 = 1'd0;
else
o14 = o13;
end
// Create the 15th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o15 = 1'd0;
else
o15 = o14;
end
// Create the 16th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o16 = 1'd0;
else
o16 = o15;
end
// Create the 17th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o17 = 1'd0;
else
o17 = o16;
end
// Create the 18th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o18 = 1'd0;
else
o18 = o17;
end
// Create the 19th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o19 = 1'd0;
else
o19 = o18;
end
// Create the 20th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o20 = 1'd0;
else
o20 = o19;
end
// Create the 21st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o21 = 1'd0;
else
o21 = o20;
end
// Create the 22nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o22 = 1'd0;
else
o22 = o21;
end
// Create the 23rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o23 = 1'd0;
else
o23 = o22;
end
// Create the 24th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o24 = 1'd0;
else
o24 = o23;
end
// Create the 25th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o25 = 1'd0;
else
o25 = o24;
end
// Create the 26th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o26 = 1'd0;
else
o26 = o25;
end
// Create the 27th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o27 = 1'd0;
else
o27 = o26;
end
// Create the 28th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o28 = 1'd0;
else
o28 = o27;
end
// Create the 29th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o29 = 1'd0;
else
o29 = o28;
end
// Create the 30th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o30 = 1'd0;
else
o30 = o29;
end
// Create the 31st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o31 = 1'd0;
else
o31 = o30;
end
// Create the 32nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
out = 1'd0;
else
out = o31;
end
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_mem2x
#(
parameter DEPTH_WORDS=1,
parameter WIDTH=32,
parameter RDW_MODE="DONT_CARE",
parameter RAM_OPERATION_MODE = "BIDIR_DUAL_PORT", // altsyncram's OPERATION_MODE parameter
parameter RAM_BLOCK_TYPE = "AUTO" // altsyncram's RAM_BLOCK_TYPE parameter
)
(
input clk,
input clk2x,
input resetn,
input [WIDTH-1:0] avs_port1_writedata,
input [WIDTH-1:0] avs_port2_writedata,
input [WIDTH-1:0] avs_port3_writedata,
input [WIDTH-1:0] avs_port4_writedata,
input [WIDTH/8-1:0] avs_port1_byteenable,
input [WIDTH/8-1:0] avs_port2_byteenable,
input [WIDTH/8-1:0] avs_port3_byteenable,
input [WIDTH/8-1:0] avs_port4_byteenable,
input [$clog2(DEPTH_WORDS)-1:0] avs_port1_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port2_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port3_address,
input [$clog2(DEPTH_WORDS)-1:0] avs_port4_address,
input avs_port1_read,
input avs_port2_read,
input avs_port3_read,
input avs_port4_read,
input avs_port1_write,
input avs_port2_write,
input avs_port3_write,
input avs_port4_write,
output reg [WIDTH-1:0] avs_port1_readdata,
output reg [WIDTH-1:0] avs_port2_readdata,
output reg [WIDTH-1:0] avs_port3_readdata,
output reg [WIDTH-1:0] avs_port4_readdata,
output avs_port1_readdatavalid,
output avs_port2_readdatavalid,
output avs_port3_readdatavalid,
output avs_port4_readdatavalid,
output avs_port1_waitrequest,
output avs_port2_waitrequest,
output avs_port3_waitrequest,
output avs_port4_waitrequest
);
localparam LOG2DEPTH = $clog2( DEPTH_WORDS );
assign avs_port1_waitrequest=1'b0;
assign avs_port2_waitrequest=1'b0;
assign avs_port3_waitrequest=1'b0;
assign avs_port4_waitrequest=1'b0;
wire [WIDTH-1:0] data_out_a_unreg;
wire [WIDTH-1:0] data_out_b_unreg;
reg [WIDTH-1:0] data_out_a_reg;
reg [WIDTH-1:0] data_out_b_reg;
reg [WIDTH-1:0] data_out_a_reg2;
reg [WIDTH-1:0] data_out_b_reg2;
_acl_mem2x_shiftreg readatavalid_1(.D(avs_port1_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port1_readdatavalid));
defparam readatavalid_1.WIDTH = 1;
defparam readatavalid_1.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_2(.D(avs_port2_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port2_readdatavalid));
defparam readatavalid_2.WIDTH = 1;
defparam readatavalid_2.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_3(.D(avs_port3_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port3_readdatavalid));
defparam readatavalid_3.WIDTH = 1;
defparam readatavalid_3.DEPTH = 4;
_acl_mem2x_shiftreg readatavalid_4(.D(avs_port4_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port4_readdatavalid));
defparam readatavalid_4.WIDTH = 1;
defparam readatavalid_4.DEPTH = 4;
localparam PREFERRED_WIDTH=128;
localparam NUM_RAMS=((WIDTH+PREFERRED_WIDTH-1)/PREFERRED_WIDTH);
genvar n;
generate
for(n=0; n<NUM_RAMS; n++)
begin : block_n
localparam MY_WIDTH=( (n==NUM_RAMS-1) ? (WIDTH-(NUM_RAMS-1)*PREFERRED_WIDTH) : PREFERRED_WIDTH );
reg [LOG2DEPTH-1:0] addr_1_reg2x /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_2_reg2x /* synthesis dont_merge */;
reg write_1_reg2x /* synthesis dont_merge */;
reg write_2_reg2x /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_1_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_2_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_3_reg /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] addr_4_reg /* synthesis dont_merge */;
reg write_1_reg, write_2_reg /* synthesis dont_merge */;
reg write_3_reg, write_4_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_1_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_2_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_1_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_2_reg2x /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_1_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_2_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_3_reg /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] data_4_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_1_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_2_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_3_reg /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] byteen_4_reg /* synthesis dont_merge */;
reg clk_90deg, sel2x /* synthesis dont_merge */;
//Convert clock to data signal
always@(negedge clk2x)
clk_90deg<=clk;
always@(posedge clk2x)
sel2x<=clk_90deg; //This should give you exactly sel2x=~clk
always@(posedge clk2x)
begin
addr_1_reg2x <= (!sel2x) ? addr_2_reg : addr_1_reg;
addr_2_reg2x <= (!sel2x) ? addr_4_reg : addr_3_reg;
write_1_reg2x <= (!sel2x) ? write_2_reg : write_1_reg;
write_2_reg2x <= (!sel2x) ? write_4_reg : write_3_reg;
end
always@(posedge clk)
begin
addr_1_reg <= avs_port1_address;
addr_2_reg <= avs_port2_address;
addr_3_reg <= avs_port3_address;
addr_4_reg <= avs_port4_address;
write_1_reg <= avs_port1_write;
write_2_reg <= avs_port2_write;
write_3_reg <= avs_port3_write;
write_4_reg <= avs_port4_write;
end
//Register before double pumping
always@(posedge clk)
begin
data_1_reg <= avs_port1_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
data_2_reg <= avs_port2_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
data_3_reg <= avs_port3_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
data_4_reg <= avs_port4_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
byteen_1_reg <= avs_port1_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
byteen_2_reg <= avs_port2_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
byteen_3_reg <= avs_port3_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
byteen_4_reg <= avs_port4_byteenable[n*(PREFERRED_WIDTH/8) +: (MY_WIDTH/8)];
end
// Consider making only one port r/w and the rest read only
always@(posedge clk2x)
begin
data_1_reg2x <= (!sel2x) ? data_2_reg : data_1_reg;
data_2_reg2x <= (!sel2x) ? data_4_reg : data_3_reg;
byteen_1_reg2x <= (!sel2x) ? byteen_2_reg : byteen_1_reg;
byteen_2_reg2x <= (!sel2x) ? byteen_4_reg : byteen_3_reg;
end
altsyncram altsyncram_component (
.clock0 (clk2x),
.wren_a (write_1_reg2x),
.wren_b (write_2_reg2x),
.address_a (addr_1_reg2x),
.address_b (addr_2_reg2x),
.data_a (data_1_reg2x),
.data_b (data_2_reg2x),
.q_a (data_out_a_unreg[n*PREFERRED_WIDTH +: MY_WIDTH]),
.q_b (data_out_b_unreg[n*PREFERRED_WIDTH +: MY_WIDTH]),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (byteen_1_reg2x),
.byteena_b (byteen_2_reg2x),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = DEPTH_WORDS,
altsyncram_component.numwords_b = DEPTH_WORDS,
altsyncram_component.operation_mode = RAM_OPERATION_MODE,
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = RDW_MODE,
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_b = "DONT_CARE",
altsyncram_component.widthad_a = LOG2DEPTH,
altsyncram_component.widthad_b = LOG2DEPTH,
altsyncram_component.width_a = MY_WIDTH,
altsyncram_component.width_b = MY_WIDTH,
altsyncram_component.width_byteena_a = MY_WIDTH/8,
altsyncram_component.width_byteena_b = MY_WIDTH/8,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.ram_block_type = RAM_BLOCK_TYPE;
end
endgenerate
always@(posedge clk2x)
begin
data_out_a_reg<=data_out_a_unreg;
data_out_b_reg<=data_out_b_unreg;
data_out_a_reg2<=data_out_a_reg;
data_out_b_reg2<=data_out_b_reg;
end
always@(posedge clk)
begin
avs_port1_readdata <= data_out_a_reg;
avs_port2_readdata <= data_out_a_reg2;
avs_port3_readdata <= data_out_b_reg;
avs_port4_readdata <= data_out_b_reg2;
end
endmodule
/*********************************************************************************
* Support components
*********************************************************************************/
module _acl_mem2x_shiftreg(D, clock, resetn, enable, Q);
parameter WIDTH = 32;
parameter DEPTH = 1;
input [WIDTH-1:0] D;
input clock, resetn, enable;
output [WIDTH-1:0] Q;
reg [DEPTH-1:0][WIDTH-1:0] local_ffs /* synthesis preserve */;
always @(posedge clock or negedge resetn)
if (!resetn)
local_ffs <= '0;
else if (enable)
local_ffs <= {local_ffs[DEPTH-2:0], D};
assign Q = local_ffs[DEPTH-1];
endmodule
|
// Based on http://opencores.org/project,spi
module wb_regmap(
// Wishbone signals
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_cti_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o,
debug_out
);
// Wishbone slave signals
input wb_clk_i;
input wb_rst_i;
input [4:0] wb_adr_i;
input [15:0] wb_dat_i;
output [15:0] wb_dat_o;
input [1:0] wb_sel_i;
input [2:0] wb_cti_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
output wb_ack_o;
output wb_err_o;
output wb_int_o;
output [15:0] debug_out;
assign debug_out = {fifo_dout};
// This is used to force addressing errors on poor handshake implementation
wire [4:0] int_addr;
assign int_addr = (wb_cyc_i) ? wb_adr_i : 5'h1F;
// End of Transfer
wire eot;
assign eot = ((wb_cti_i == 3'b000) & wb_ack_o) | (wb_cti_i == 3'b111);
// Handshake - synchronous due to nature of block RAM
reg wb_ack_o;
always @(posedge wb_clk_i) begin
// Set by STB and itself, cleared by EOT or RST
wb_ack_o <= (wb_stb_i | wb_ack_o) & ~(eot | wb_rst_i);
end
// Interrupt and Error
reg wb_int_o;
reg wb_err_o;
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wb_int_o <= 1'b0;
wb_err_o <= 1'b0;
end
end
// Register map
reg [4:0] rm_addr_in;
reg [15:0] reg_map [31:0];
reg [15:0] rm_data_in;
reg [15:0] rm_data_out;
// Latch data out on a read request
reg [15:0] rm_dat_o;
always @(posedge wb_clk_i) begin
if (~wb_we_i) begin
rm_dat_o <= rm_data_out;
end
end
// Latch data in on a write request
always @(posedge wb_clk_i) begin
if (wb_we_i) begin
reg_map[int_addr] <= rm_data_in;
end
end
// Write to registers multiplex
always @(int_addr or wb_dat_i) begin
case (int_addr)
0: rm_data_in <= wb_dat_i;
1: rm_data_in <= wb_dat_i;
2: rm_data_in <= wb_dat_i;
3: rm_data_in <= wb_dat_i;
4: rm_data_in <= wb_dat_i;
5: rm_data_in <= wb_dat_i;
6: rm_data_in <= wb_dat_i;
7: rm_data_in <= wb_dat_i;
//16: fifo_din <= wb_dat_i;
default: rm_data_in <= 16'hAAAA;
endcase
end
// Read from registers multiplex
always @(int_addr or reg_map) begin
case (int_addr)
0: rm_data_out <= reg_map[int_addr];
1: rm_data_out <= reg_map[int_addr];
2: rm_data_out <= reg_map[int_addr];
3: rm_data_out <= reg_map[int_addr];
4: rm_data_out <= reg_map[int_addr];
5: rm_data_out <= reg_map[int_addr];
6: rm_data_out <= reg_map[int_addr];
7: rm_data_out <= reg_map[int_addr];
8: rm_data_out <= reg_map[int_addr];
default: rm_data_out <= 16'd12346;
endcase
end
// Loop-back FIFO for testing
wire fifo_rd;
wire fifo_wr;
assign fifo_rd = ~(wb_cti_i == 3'b000) & (int_addr == 5'h10) & wb_stb_i & wb_ack_o & ~wb_we_i;
assign fifo_wr = ~(wb_cti_i == 3'b000) & (int_addr == 5'h11) & wb_stb_i & wb_ack_o & wb_we_i;
// FIFO read access cannot rely on data switch as it needs to look ahead
assign fifo_rd_addr_incr = (wb_cti_i == 3'b001) & (int_addr == 5'h10) & wb_stb_i;
wire [15:0] fifo_din;
wire [15:0] fifo_dout;
reg [9:0] fifo_wr_addr;
reg [9:0] fifo_rd_addr;
// Bypass register map when accessing the FIFO
assign wb_dat_o = (fifo_rd) ? fifo_dout : rm_dat_o;
assign fifo_din = (fifo_wr) ? wb_dat_i : 16'd0;
// Auto-incremenet
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
fifo_wr_addr <= 9'd0;
fifo_rd_addr <= 9'd0;
end else begin
if (fifo_wr)
fifo_wr_addr <= fifo_wr_addr + 9'd1;
else
fifo_wr_addr <= fifo_wr_addr;
if (fifo_rd_addr_incr)
fifo_rd_addr <= fifo_rd_addr + 9'd1;
else
fifo_rd_addr <= fifo_rd_addr;
end
end
// Instantiate a generic dual port RAM module
dp_ram rm_fifo(
// Write port
.a_clk(wb_clk_i), .a_wr(fifo_wr), .a_addr(fifo_wr_addr),
.a_din(fifo_din), .a_dout(),
// Read port
.b_clk(wb_clk_i), .b_wr(1'b0), .b_addr(fifo_rd_addr),
.b_din(16'b0), .b_dout(fifo_dout)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: dtysky
//
// Create Date: 2015/01/18 16:56:28
// Design Name: DATAPATH
// Module Name: DATAPATH
// Project Name: MISP_CPU
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DATAPATH(
input clk,clrn,
input alu_z,
input[31:0] alu_r,
output[31:0] alu_a,alu_b,
output[31:0] alu_aluc,
output reg_we,
input[31:0] reg_qa,reg_qb,
output[4:0] reg_wn,reg_rna,reg_rnb,
output[31:0] reg_d,
input con_wreg,con_regrt,con_jal,con_m2reg,con_shfit,con_aluimm,con_sext,con_wmem,
input[3:0] con_aluc,
input[1:0] con_pcsource,
output[5:0] con_op,con_func,
output con_z,
input[31:0] inst_do,
output[31:0] inst_a,
input[31:0] data_do,
output[31:0] data_a,data_di,
output data_we,
output[31:0] pc_out
);
wire[4:0] rs,rt,rd,sa;
wire signed [31:0] imm;
wire[25:0] addr;
reg[31:0] pc_i,pc_o;
wire[31:0] pc_p4,pc_jump;
wire[4:0] reg_dest;
wire[31:0] imm_ext,reg_data_dest;
initial begin
pc_i = 32'b0;
end
assign rs = inst_do[25:21];
assign rt = inst_do[20:16];
assign rd = inst_do[15:11];
assign sa = inst_do[10:6];
assign imm = {inst_do[15:0],16'b0};
assign addr = inst_do[25:0];
assign imm_ext = con_sext ? imm>>>16 : imm>>16;
assign pc_p4 = pc_o + 4;
assign pc_out = pc_o;
assign reg_dest = con_regrt ? rt : rd;
assign reg_wn = reg_dest | {5{con_jal}};
assign reg_data_dest = con_m2reg ? data_do : alu_r;
assign reg_d = con_jal ? pc_p4 : reg_data_dest;
assign reg_rna = rs;
assign reg_rnb = rt;
assign reg_we = con_wreg;
assign con_op = inst_do[31:26];
assign con_func = inst_do[5:0];
assign con_z = alu_z;
assign alu_a = con_shfit ? {27'b0,sa} : reg_qa;
assign alu_b = con_aluimm ? imm_ext : reg_qb;
assign alu_aluc = {28'b0,con_aluc};
assign data_we = con_wmem;
assign data_di = reg_qb;
assign data_a = alu_r;
assign inst_a = pc_o;
always @(posedge clk or negedge clrn) begin
if (~clrn) pc_o <= 32'b0;
else pc_o <= pc_i;
end
ADDSUB32 ADDSUB1(pc_p4,imm_ext<<2,1'b0,pc_jump);
always @(*) begin
case (con_pcsource)
2'b00 : pc_i <= pc_p4;
2'b01 : pc_i <= pc_jump;
2'b10 : pc_i <= reg_qa;
2'b11 : pc_i <= {pc_p4[31:28],addr,2'b0};
default : /* default */;
endcase
end
endmodule |
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_atan2_s5 (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_atan2_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.b(datab),
.q(sub_wire0));
endmodule
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_acos_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_arccos_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.q(sub_wire0));
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
// Title : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : v6_emac_v1_3.v
// Version : 1.3
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//------------------------------------------------------------------------------
// Description: This wrapper file instantiates the full Virtex-6 Embedded
// Tri-Mode Ethernet MAC (EMAC) primitive, where:
//
// * all unused input ports on the primitive are tied to the
// appropriate logic level;
//
// * all unused output ports on the primitive are left
// unconnected;
//
// * the attributes are set based on the options selected
// from CORE Generator;
//
// * only used ports are connected to the ports of this
// wrapper file.
//
// This simplified wrapper should therefore be used as the
// instantiation template for the EMAC primitive in customer
// designs.
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//------------------------------------------------------------------------------
// Module declaration for the primitive-level wrapper
//------------------------------------------------------------------------------
(* X_CORE_INFO = "v6_emac_v1_3, Coregen 11.3" *)
(* CORE_GENERATION_INFO = "v6_emac_v1_3,v6_emac_v1_3,{c_has_mii=false,c_has_gmii=true,c_has_rgmii_v1_3=false,c_has_rgmii_v2_0=false,c_has_sgmii=false,c_has_gpcs=false,c_tri_speed=false,c_speed_10=false,c_speed_100=false,c_speed_1000=true,c_has_host=true,c_has_dcr=false,c_has_mdio=true,c_client_16=false,c_add_filter=false,c_has_clock_enable=false,c_serial_mode_switch_en=false,c_overclocking_rate_2000mbps=false,c_overclocking_rate_2500mbps=false,}" *)
module v6_emac_v1_3
(
// Client Receiver Interface
EMACCLIENTRXCLIENTCLKOUT,
CLIENTEMACRXCLIENTCLKIN,
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXDVLDMSW,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
// Client Transmitter Interface
EMACCLIENTTXCLIENTCLKOUT,
CLIENTEMACTXCLIENTCLKIN,
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
CLIENTEMACTXDVLDMSW,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
// MAC Control Interface
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
// Clock Signals
GTX_CLK,
PHYEMACTXGMIIMIICLKIN,
EMACPHYTXGMIIMIICLKOUT,
// GMII Interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
// MDIO Interface
MDC,
MDIO_I,
MDIO_O,
MDIO_T,
// Host Interface
HOSTCLK,
HOSTOPCODE,
HOSTREQ,
HOSTMIIMSEL,
HOSTADDR,
HOSTWRDATA,
HOSTMIIMRDY,
HOSTRDDATA,
// MMCM Lock Indicator
MMCM_LOCKED,
// Asynchronous Reset
RESET
);
//--------------------------------------------------------------------------
// Port declarations
//--------------------------------------------------------------------------
// Client Receiver Interface
output EMACCLIENTRXCLIENTCLKOUT;
input CLIENTEMACRXCLIENTCLKIN;
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXDVLDMSW;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
// Client Transmitter Interface
output EMACCLIENTTXCLIENTCLKOUT;
input CLIENTEMACTXCLIENTCLKIN;
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
input CLIENTEMACTXDVLDMSW;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
// MAC Control Interface
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
// Clock Signals
input GTX_CLK;
output EMACPHYTXGMIIMIICLKOUT;
input PHYEMACTXGMIIMIICLKIN;
// GMII Interface
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
// MDIO Interface
output MDC;
input MDIO_I;
output MDIO_O;
output MDIO_T;
// Host Interface
input HOSTCLK;
input [1:0] HOSTOPCODE;
input HOSTREQ;
input HOSTMIIMSEL;
input [9:0] HOSTADDR;
input [31:0] HOSTWRDATA;
output HOSTMIIMRDY;
output [31:0] HOSTRDDATA;
// MMCM Lock Indicator
input MMCM_LOCKED;
// Asynchronous Reset
input RESET;
//--------------------------------------------------------------------------
// Wire declarations
//--------------------------------------------------------------------------
wire [15:0] client_rx_data_i;
wire [15:0] client_tx_data_i;
//--------------------------------------------------------------------------
// Main body of code
//--------------------------------------------------------------------------
// Use the 8-bit client data interface
assign EMACCLIENTRXD = client_rx_data_i[7:0];
assign #4000 client_tx_data_i = {8'b00000000, CLIENTEMACTXD};
// Instantiate the Virtex-6 Embedded Tri-Mode Ethernet MAC
TEMAC_SINGLE #(
// PCS/PMA logic is not in use
.EMAC_PHYINITAUTONEG_ENABLE ("FALSE"),
.EMAC_PHYISOLATE ("FALSE"),
.EMAC_PHYLOOPBACKMSB ("FALSE"),
.EMAC_PHYPOWERDOWN ("FALSE"),
.EMAC_PHYRESET ("TRUE"),
.EMAC_GTLOOPBACK ("FALSE"),
.EMAC_UNIDIRECTION_ENABLE ("FALSE"),
.EMAC_LINKTIMERVAL (9'h000),
.EMAC_MDIO_IGNORE_PHYADZERO ("FALSE"),
// Configure the EMAC operating mode
// MDIO is enabled
.EMAC_MDIO_ENABLE ("TRUE"),
// Speed is defaulted to 1000 Mb/s
.EMAC_SPEED_LSB ("FALSE"),
.EMAC_SPEED_MSB ("TRUE"),
// Clock Enable advanced clocking is not in use
.EMAC_USECLKEN ("FALSE"),
// Byte PHY advanced clocking is not supported. Do not modify.
.EMAC_BYTEPHY ("FALSE"),
// RGMII physical interface is not in use
.EMAC_RGMII_ENABLE ("FALSE"),
// SGMII physical interface is not in use
.EMAC_SGMII_ENABLE ("FALSE"),
.EMAC_1000BASEX_ENABLE ("FALSE"),
// The host interface is enabled
.EMAC_HOST_ENABLE ("TRUE"),
// The Tx-side 8-bit client data interface is used
.EMAC_TX16BITCLIENT_ENABLE ("FALSE"),
// The Rx-side 8-bit client data interface is used
.EMAC_RX16BITCLIENT_ENABLE ("FALSE"),
// The address filter is not enabled
.EMAC_ADDRFILTER_ENABLE ("FALSE"),
// EMAC configuration defaults
// Rx Length/Type checking is enabled
.EMAC_LTCHECK_DISABLE ("FALSE"),
// Rx control frame length checking is enabled
.EMAC_CTRLLENCHECK_DISABLE ("FALSE"),
// Rx flow control is not enabled
.EMAC_RXFLOWCTRL_ENABLE ("FALSE"),
// Tx flow control is not enabled
.EMAC_TXFLOWCTRL_ENABLE ("FALSE"),
// Transmitter is not held in reset
.EMAC_TXRESET ("FALSE"),
// Transmitter Jumbo frames are not enabled
.EMAC_TXJUMBOFRAME_ENABLE ("FALSE"),
// Transmitter in-band FCS is not enabled
.EMAC_TXINBANDFCS_ENABLE ("FALSE"),
// Transmitter is enabled
.EMAC_TX_ENABLE ("TRUE"),
// Transmitter VLAN frames are not enabled
.EMAC_TXVLAN_ENABLE ("FALSE"),
// Transmitter full-duplex mode is enabled
.EMAC_TXHALFDUPLEX ("FALSE"),
// Transmitter IFG Adjust is not enabled
.EMAC_TXIFGADJUST_ENABLE ("FALSE"),
// Receiver is not held in reset
.EMAC_RXRESET ("FALSE"),
// Receiver Jumbo frames are not enabled
.EMAC_RXJUMBOFRAME_ENABLE ("FALSE"),
// Receiver in-band FCS is not enabled
.EMAC_RXINBANDFCS_ENABLE ("FALSE"),
// Receiver is enabled
.EMAC_RX_ENABLE ("TRUE"),
// Receiver VLAN frames are not enabled
.EMAC_RXVLAN_ENABLE ("FALSE"),
// Receiver full-duplex mode is enabled
.EMAC_RXHALFDUPLEX ("FALSE"),
// Configure the EMAC addressing
// Set the PAUSE address default
.EMAC_PAUSEADDR (48'hFFEEDDCCBBAA),
// Do not set the unicast address (address filter is unused)
.EMAC_UNICASTADDR (48'h000000000000),
// Do not set the DCR base address (DCR is unused)
.EMAC_DCRBASEADDR (8'h00)
)
v6_emac
(
.RESET (RESET),
.EMACCLIENTRXCLIENTCLKOUT (EMACCLIENTRXCLIENTCLKOUT),
.CLIENTEMACRXCLIENTCLKIN (CLIENTEMACRXCLIENTCLKIN),
.EMACCLIENTRXD (client_rx_data_i),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (EMACCLIENTRXDVLDMSW),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
.EMACCLIENTTXCLIENTCLKOUT (EMACCLIENTTXCLIENTCLKOUT),
.CLIENTEMACTXCLIENTCLKIN (CLIENTEMACTXCLIENTCLKIN),
.CLIENTEMACTXD (client_tx_data_i),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (CLIENTEMACTXDVLDMSW),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
.PHYEMACGTXCLK (GTX_CLK),
.EMACPHYTXGMIIMIICLKOUT (EMACPHYTXGMIIMIICLKOUT),
.PHYEMACTXGMIIMIICLKIN (PHYEMACTXGMIIMIICLKIN),
.PHYEMACRXCLK (GMII_RX_CLK),
.PHYEMACRXD (GMII_RXD),
.PHYEMACRXDV (GMII_RX_DV),
.PHYEMACRXER (GMII_RX_ER),
.EMACPHYTXCLK (),
.EMACPHYTXD (GMII_TXD),
.EMACPHYTXEN (GMII_TX_EN),
.EMACPHYTXER (GMII_TX_ER),
.PHYEMACMIITXCLK (1'b0),
.PHYEMACCOL (1'b0),
.PHYEMACCRS (1'b0),
.CLIENTEMACDCMLOCKED (MMCM_LOCKED),
.EMACCLIENTANINTERRUPT (),
.PHYEMACSIGNALDET (1'b0),
.PHYEMACPHYAD (5'b00000),
.EMACPHYENCOMMAALIGN (),
.EMACPHYLOOPBACKMSB (),
.EMACPHYMGTRXRESET (),
.EMACPHYMGTTXRESET (),
.EMACPHYPOWERDOWN (),
.EMACPHYSYNCACQSTATUS (),
.PHYEMACRXCLKCORCNT (3'b000),
.PHYEMACRXBUFSTATUS (2'b00),
.PHYEMACRXCHARISCOMMA (1'b0),
.PHYEMACRXCHARISK (1'b0),
.PHYEMACRXDISPERR (1'b0),
.PHYEMACRXNOTINTABLE (1'b0),
.PHYEMACRXRUNDISP (1'b0),
.PHYEMACTXBUFERR (1'b0),
.EMACPHYTXCHARDISPMODE (),
.EMACPHYTXCHARDISPVAL (),
.EMACPHYTXCHARISK (),
.EMACPHYMCLKOUT (MDC),
.PHYEMACMCLKIN (1'b0),
.PHYEMACMDIN (MDIO_I),
.EMACPHYMDOUT (MDIO_O),
.EMACPHYMDTRI (MDIO_T),
.EMACSPEEDIS10100 (),
.HOSTCLK (HOSTCLK),
.HOSTOPCODE (HOSTOPCODE),
.HOSTREQ (HOSTREQ),
.HOSTMIIMSEL (HOSTMIIMSEL),
.HOSTADDR (HOSTADDR),
.HOSTWRDATA (HOSTWRDATA),
.HOSTMIIMRDY (HOSTMIIMRDY),
.HOSTRDDATA (HOSTRDDATA),
.DCREMACCLK (1'b0),
.DCREMACABUS (10'h000),
.DCREMACREAD (1'b0),
.DCREMACWRITE (1'b0),
.DCREMACDBUS (32'h00000000),
.EMACDCRACK (),
.EMACDCRDBUS (),
.DCREMACENABLE (1'b0),
.DCRHOSTDONEIR ()
);
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <zeus@aluzina.org>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
(** * Norm: Normalization of STLC *)
(* $Date: 2012-04-16 20:14:27 -0400 (Mon, 16 Apr 2012) $ *)
(* Chapter maintained by Andrew Tolmach *)
(* (Based on TAPL Ch. 12.) *)
Require Import Stlc.
(**
(This chapter is optional.)
In this chapter, we consider another fundamental theoretical property
of the simply typed lambda-calculus: the fact that the evaluation of a
well-typed program is guaranteed to halt in a finite number of
steps---i.e., every well-typed term is _normalizable_.
Unlike the type-safety properties we have considered so far, the
normalization property does not extend to full-blown programming
languages, because these languages nearly always extend the simply
typed lambda-calculus with constructs, such as general recursion
(as we discussed in the MoreStlc chapter) or recursive types, that can
be used to write nonterminating programs. However, the issue of
normalization reappears at the level of _types_ when we consider the
metatheory of polymorphic versions of the lambda calculus such as
F_omega: in this system, the language of types effectively contains a
copy of the simply typed lambda-calculus, and the termination of the
typechecking algorithm will hinge on the fact that a ``normalization''
operation on type expressions is guaranteed to terminate.
Another reason for studying normalization proofs is that they are some
of the most beautiful---and mind-blowing---mathematics to be found in
the type theory literature, often (as here) involving the fundamental
proof technique of _logical relations_.
The calculus we shall consider here is the simply typed
lambda-calculus over a single base type [bool] and with pairs. We'll
give full details of the development for the basic lambda-calculus
terms treating [bool] as an uninterpreted base type, and leave the
extension to the boolean operators and pairs to the reader. Even for
the base calculus, normalization is not entirely trivial to prove,
since each reduction of a term can duplicate redexes in subterms. *)
(** **** Exercise: 1 star *)
(** Where do we fail if we attempt to prove normalization by a
straightforward induction on the size of a well-typed term? *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * Language *)
(** We begin by repeating the relevant language definition, which is
similar to those in the MoreStlc chapter, and supporting results
including type preservation and step determinism. (We won't need
progress.) You may just wish to skip down to the Normalization
section... *)
(* ###################################################################### *)
(** *** Syntax and Operational Semantics *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty
| TProd : ty -> ty -> ty
.
Tactic Notation "T_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "TBool" | Case_aux c "TArrow" | Case_aux c "TProd" ].
Inductive tm : Type :=
(* pure STLC *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
(* pairs *)
| tpair : tm -> tm -> tm
| tfst : tm -> tm
| tsnd : tm -> tm
(* booleans *)
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
(* i.e., [if t0 then t1 else t2] *)
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp" | Case_aux c "tabs"
| Case_aux c "tpair" | Case_aux c "tfst" | Case_aux c "tsnd"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
(* ###################################################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if beq_id x y then s else t
| tabs y T t1 => tabs y T (if beq_id x y then t1 else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tpair t1 t2 => tpair (subst x s t1) (subst x s t2)
| tfst t1 => tfst (subst x s t1)
| tsnd t1 => tsnd (subst x s t1)
| ttrue => ttrue
| tfalse => tfalse
| tif t0 t1 t2 => tif (subst x s t0) (subst x s t1) (subst x s t2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T11 t12,
value (tabs x T11 t12)
| v_pair : forall v1 v2,
value v1 ->
value v2 ->
value (tpair v1 v2)
| v_true : value ttrue
| v_false : value tfalse
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
(tapp (tabs x T11 t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
(* pairs *)
| ST_Pair1 : forall t1 t1' t2,
t1 ==> t1' ->
(tpair t1 t2) ==> (tpair t1' t2)
| ST_Pair2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tpair v1 t2) ==> (tpair v1 t2')
| ST_Fst : forall t1 t1',
t1 ==> t1' ->
(tfst t1) ==> (tfst t1')
| ST_FstPair : forall v1 v2,
value v1 ->
value v2 ->
(tfst (tpair v1 v2)) ==> v1
| ST_Snd : forall t1 t1',
t1 ==> t1' ->
(tsnd t1) ==> (tsnd t1')
| ST_SndPair : forall v1 v2,
value v1 ->
value v2 ->
(tsnd (tpair v1 v2)) ==> v2
(* booleans *)
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t0 t0' t1 t2,
t0 ==> t0' ->
(tif t0 t1 t2) ==> (tif t0' t1 t2)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1" | Case_aux c "ST_App2"
| Case_aux c "ST_Pair1" | Case_aux c "ST_Pair2"
| Case_aux c "ST_Fst" | Case_aux c "ST_FstPair"
| Case_aux c "ST_Snd" | Case_aux c "ST_SndPair"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Hint Constructors step.
Notation step_normal_form := (normal_form step).
Lemma value__normal : forall t, value t -> step_normal_form t.
Proof with eauto.
intros t H; induction H; intros [t' ST]; inversion ST...
Qed.
(* ###################################################################### *)
(** *** Typing *)
Definition context := partial_map ty.
Inductive has_type : context -> tm -> ty -> Prop :=
(* Typing rules for proper terms *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
has_type Gamma (tvar x) T
| T_Abs : forall Gamma x T11 T12 t12,
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tabs x T11 t12) (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (TArrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tapp t1 t2) T2
(* pairs *)
| T_Pair : forall Gamma t1 t2 T1 T2,
has_type Gamma t1 T1 ->
has_type Gamma t2 T2 ->
has_type Gamma (tpair t1 t2) (TProd T1 T2)
| T_Fst : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tfst t) T1
| T_Snd : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tsnd t) T2
(* booleans *)
| T_True : forall Gamma,
has_type Gamma ttrue TBool
| T_False : forall Gamma,
has_type Gamma tfalse TBool
| T_If : forall Gamma t0 t1 t2 T,
has_type Gamma t0 TBool ->
has_type Gamma t1 T ->
has_type Gamma t2 T ->
has_type Gamma (tif t0 t1 t2) T
.
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Pair" | Case_aux c "T_Fst" | Case_aux c "T_Snd"
| Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Extern 2 (has_type _ (tapp _ _) _) => eapply T_App; auto.
Hint Extern 2 (_ = _) => compute; reflexivity.
(* ###################################################################### *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
(* pairs *)
| afi_pair1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tpair t1 t2)
| afi_pair2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tpair t1 t2)
| afi_fst : forall x t,
appears_free_in x t ->
appears_free_in x (tfst t)
| afi_snd : forall x t,
appears_free_in x t ->
appears_free_in x (tsnd t)
(* booleans *)
| afi_if0 : forall x t0 t1 t2,
appears_free_in x t0 ->
appears_free_in x (tif t0 t1 t2)
| afi_if1 : forall x t0 t1 t2,
appears_free_in x t1 ->
appears_free_in x (tif t0 t1 t2)
| afi_if2 : forall x t0 t1 t2,
appears_free_in x t2 ->
appears_free_in x (tif t0 t1 t2)
.
Hint Constructors appears_free_in.
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros y Hafi.
unfold extend. remember (beq_id x y) as e.
destruct e...
Case "T_Pair".
apply T_Pair...
Case "T_If".
eapply T_If...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case; inversion Hafi; subst...
Case "T_Abs".
destruct IHHtyp as [T' Hctx]... exists T'.
unfold extend in Hctx.
apply not_eq_beq_id_false in H2. rewrite H2 in Hctx...
Qed.
Corollary typable_empty__closed : forall t T,
has_type empty t T ->
closed t.
Proof.
intros. unfold closed. intros x H1.
destruct (free_in_context _ _ _ _ H1 H) as [T' C].
inversion C. Qed.
(* ###################################################################### *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
(* Theorem: If Gamma,x:U |- t : S and empty |- v : U, then
Gamma |- ([x:=v]t) S. *)
intros Gamma x U v t S Htypt Htypv.
generalize dependent Gamma. generalize dependent S.
(* Proof: By induction on the term t. Most cases follow directly
from the IH, with the exception of tvar and tabs.
The former aren't automatic because we must reason about how the
variables interact. *)
t_cases (induction t) Case;
intros S Gamma Htypt; simpl; inversion Htypt; subst...
Case "tvar".
simpl. rename i into y.
(* If t = y, we know that
[empty |- v : U] and
[Gamma,x:U |- y : S]
and, by inversion, [extend Gamma x U y = Some S]. We want to
show that [Gamma |- [x:=v]y : S].
There are two cases to consider: either [x=y] or [x<>y]. *)
remember (beq_id x y) as e. destruct e.
SCase "x=y".
(* If [x = y], then we know that [U = S], and that [[x:=v]y = v].
So what we really must show is that if [empty |- v : U] then
[Gamma |- v : U]. We have already proven a more general version
of this theorem, called context invariance. *)
apply beq_id_eq in Heqe. subst.
unfold extend in H1. rewrite <- beq_id_refl in H1.
inversion H1; subst. clear H1.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
(* If [x <> y], then [Gamma y = Some S] and the substitution has no
effect. We can show that [Gamma |- y : S] by [T_Var]. *)
apply T_Var... unfold extend in H1. rewrite <- Heqe in H1...
Case "tabs".
rename i into y. rename t into T11.
(* If [t = tabs y T11 t0], then we know that
[Gamma,x:U |- tabs y T11 t0 : T11->T12]
[Gamma,x:U,y:T11 |- t0 : T12]
[empty |- v : U]
As our IH, we know that forall S Gamma,
[Gamma,x:U |- t0 : S -> Gamma |- [x:=v]t0 S].
We can calculate that
[x:=v]t = tabs y T11 (if beq_id x y then t0 else [x:=v]t0)
And we must show that [Gamma |- [x:=v]t : T11->T12]. We know
we will do so using [T_Abs], so it remains to be shown that:
[Gamma,y:T11 |- if beq_id x y then t0 else [x:=v]t0 : T12]
We consider two cases: [x = y] and [x <> y].
*)
apply T_Abs...
remember (beq_id x y) as e. destruct e.
SCase "x=y".
(* If [x = y], then the substitution has no effect. Context
invariance shows that [Gamma,y:U,y:T11] and [Gamma,y:T11] are
equivalent. Since the former context shows that [t0 : T12], so
does the latter. *)
eapply context_invariance...
apply beq_id_eq in Heqe. subst.
intros x Hafi. unfold extend.
destruct (beq_id y x)...
SCase "x<>y".
(* If [x <> y], then the IH and context invariance allow us to show that
[Gamma,x:U,y:T11 |- t0 : T12] =>
[Gamma,y:T11,x:U |- t0 : T12] =>
[Gamma,y:T11 |- [x:=v]t0 : T12] *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
remember (beq_id y z) as e0. destruct e0...
apply beq_id_eq in Heqe0. subst.
rewrite <- Heqe...
Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
(* Theorem: If [empty |- t : T] and [t ==> t'], then [empty |- t' : T]. *)
remember (@empty ty) as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
(* Proof: By induction on the given typing derivation. Many cases are
contradictory ([T_Var], [T_Abs]). We show just the interesting ones. *)
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
(* If the last rule used was [T_App], then [t = t1 t2], and three rules
could have been used to show [t ==> t']: [ST_App1], [ST_App2], and
[ST_AppAbs]. In the first two cases, the result follows directly from
the IH. *)
inversion HE; subst...
SCase "ST_AppAbs".
(* For the third case, suppose
[t1 = tabs x T11 t12]
and
[t2 = v2].
We must show that [empty |- [x:=v2]t12 : T2].
We know by assumption that
[empty |- tabs x T11 t12 : T1->T2]
and by inversion
[x:T1 |- t12 : T2]
We have already proven that substitution_preserves_typing and
[empty |- v2 : T1]
by assumption, so we are done. *)
apply substitution_preserves_typing with T1...
inversion HT1...
Case "T_Fst".
inversion HT...
Case "T_Snd".
inversion HT...
Qed.
(** [] *)
(* ###################################################################### *)
(** *** Determinism *)
Lemma step_deterministic :
deterministic step.
Proof with eauto.
unfold deterministic.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** * Normalization *)
(** Now for the actual normalization proof.
Our goal is to prove that every well-typed term evaluates to a
normal form. In fact, it turns out to be convenient to prove
something slightly stronger, namely that every well-typed term
evaluates to a _value_. This follows from the weaker property
anyway via the Progress lemma (why?) but otherwise we don't need
Progress, and we didn't bother re-proving it above.
Here's the key definition: *)
Definition halts (t:tm) : Prop := exists t', t ==>* t' /\ value t'.
(** A trivial fact: *)
Lemma value_halts : forall v, value v -> halts v.
Proof.
intros v H. unfold halts.
exists v. split.
apply multi_refl.
assumption.
Qed.
(** The key issue in the normalization proof (as in many proofs by
induction) is finding a strong enough induction hypothesis. To this
end, we begin by defining, for each type [T], a set [R_T] of closed
terms of type [T]. We will specify these sets using a relation [R]
and write [R T t] when [t] is in [R_T]. (The sets [R_T] are sometimes
called _saturated sets_ or _reducibility candidates_.)
Here is the definition of [R] for the base language:
- [R bool t] iff [t] is a closed term of type [bool] and [t] halts in a value
- [R (T1 -> T2) t] iff [t] is a closed term of type [T1 -> T2] and [t] halts
in a value _and_ for any term [s] such that [R T1 s], we have [R
T2 (t s)]. *)
(** This definition gives us the strengthened induction hypothesis that we
need. Our primary goal is to show that all _programs_ ---i.e., all
closed terms of base type---halt. But closed terms of base type can
contain subterms of functional type, so we need to know something
about these as well. Moreover, it is not enough to know that these
subterms halt, because the application of a normalized function to a
normalized argument involves a substitution, which may enable more
evaluation steps. So we need a stronger condition for terms of
functional type: not only should they halt themselves, but, when
applied to halting arguments, they should yield halting results.
The form of [R] is characteristic of the _logical relations_ proof
technique. (Since we are just dealing with unary relations here, we
could perhaps more properly say _logical predicates_.) If we want to
prove some property [P] of all closed terms of type [A], we proceed by
proving, by induction on types, that all terms of type [A] _possess_
property [P], all terms of type [A->A] _preserve_ property [P], all
terms of type [(A->A)->(A->A)] _preserve the property of preserving_
property [P], and so on. We do this by defining a family of
predicates, indexed by types. For the base type [A], the predicate is
just [P]. For functional types, it says that the function should map
values satisfying the predicate at the input type to values satisfying
the predicate at the output type.
When we come to formalize the definition of [R] in Coq, we hit a
problem. The most obvious formulation would be as a parameterized
Inductive proposition like this:
Inductive R : ty -> tm -> Prop :=
| R_bool : forall b t, has_type empty t TBool ->
halts t ->
R TBool t
| R_arrow : forall T1 T2 t, has_type empty t (TArrow T1 T2) ->
halts t ->
(forall s, R T1 s -> R T2 (tapp t s)) ->
R (TArrow T1 T2) t.
Unfortunately, Coq rejects this definition because it violates the
_strict positivity requirement_ for inductive definitions, which says
that the type being defined must not occur to the left of an arrow in
the type of a constructor argument. Here, it is the third argument to
[R_arrow], namely [(forall s, R T1 s -> R TS (tapp t s))], and
specifically the [R T1 s] part, that violates this rule. (The
outermost arrows separating the constructor arguments don't count when
applying this rule; otherwise we could never have genuinely inductive
predicates at all!) The reason for the rule is that types defined
with non-positive recursion can be used to build non-terminating
functions, which as we know would be a disaster for Coq's logical
soundness. Even though the relation we want in this case might be
perfectly innocent, Coq still rejects it because it fails the
positivity test.
Fortunately, it turns out that we _can_ define [R] using a
[Fixpoint]: *)
Fixpoint R (T:ty) (t:tm) {struct T} : Prop :=
has_type empty t T /\ halts t /\
(match T with
| TBool => True
| TArrow T1 T2 => (forall s, R T1 s -> R T2 (tapp t s))
(* FILL IN HERE *)
| TProd T1 T2 => False (* ... and delete this line *)
end).
(** As immediate consequences of this definition, we have that every
element of every set [R_T] halts in a value and is closed with type
[t] :*)
Lemma R_halts : forall {T} {t}, R T t -> halts t.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
Lemma R_typable_empty : forall {T} {t}, R T t -> has_type empty t T.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
(** Now we proceed to show the main result, which is that every
well-typed term of type [T] is an element of [R_T]. Together with
[R_halts], that will show that every well-typed term halts in a
value. *)
(* ###################################################################### *)
(** ** Membership in [R_T] is invariant under evaluation *)
(** We start with a preliminary lemma that shows a kind of strong
preservation property, namely that membership in [R_T] is _invariant_
under evaluation. We will need this property in both directions,
i.e. both to show that a term in [R_T] stays in [R_T] when it takes a
forward step, and to show that any term that ends up in [R_T] after a
step must have been in [R_T] to begin with.
First of all, an easy preliminary lemma. Note that in the forward
direction the proof depends on the fact that our language is
determinstic. This lemma might still be true for non-deterministic
languages, but the proof would be harder! *)
Lemma step_preserves_halting : forall t t', (t ==> t') -> (halts t <-> halts t').
Proof.
intros t t' ST. unfold halts.
split.
Case "->".
intros [t'' [STM V]].
inversion STM; subst.
apply ex_falso_quodlibet. apply value__normal in V. unfold normal_form in V. apply V. exists t'. auto.
rewrite (step_deterministic _ _ _ ST H). exists t''. split; assumption.
Case "<-".
intros [t'0 [STM V]].
exists t'0. split; eauto.
Qed.
(** Now the main lemma, which comes in two parts, one for each
direction. Each proceeds by induction on the structure of the type
[T]. In fact, this is where we make fundamental use of the
finiteness of types.
One requirement for staying in [R_T] is to stay in type [T]. In the
forward direction, we get this from ordinary type Preservation. *)
Lemma step_preserves_R : forall T t t', (t ==> t') -> R T t -> R T t'.
Proof.
induction T; intros t t' E Rt; unfold R; fold R; unfold R in Rt; fold R in Rt;
destruct Rt as [typable_empty_t [halts_t RRt]].
(* TBool *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
auto.
(* TArrow *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
intros.
eapply IHT2.
apply ST_App1. apply E.
apply RRt; auto.
(* FILL IN HERE *) Admitted.
(** The generalization to multiple steps is trivial: *)
Lemma multistep_preserves_R : forall T t t',
(t ==>* t') -> R T t -> R T t'.
Proof.
intros T t t' STM; induction STM; intros.
assumption.
apply IHSTM. eapply step_preserves_R. apply H. assumption.
Qed.
(** In the reverse direction, we must add the fact that [t] has type
[T] before stepping as an additional hypothesis. *)
Lemma step_preserves_R' : forall T t t',
has_type empty t T -> (t ==> t') -> R T t' -> R T t.
Proof.
(* FILL IN HERE *) Admitted.
Lemma multistep_preserves_R' : forall T t t',
has_type empty t T -> (t ==>* t') -> R T t' -> R T t.
Proof.
intros T t t' HT STM.
induction STM; intros.
assumption.
eapply step_preserves_R'. assumption. apply H. apply IHSTM.
eapply preservation; eauto. auto.
Qed.
(* ###################################################################### *)
(** ** Closed instances of terms of type [T] belong to [R_T] *)
(** Now we proceed to show that every term of type [T] belongs to
[R_T]. Here, the induction will be on typing derivations (it would be
surprising to see a proof about well-typed terms that did not
somewhere involve induction on typing derivations!). The only
technical difficulty here is in dealing with the abstraction case.
Since we are arguing by induction, the demonstration that a term
[tabs x T1 t2] belongs to [R_(T1->T2)] should involve applying the
induction hypothesis to show that [t2] belongs to [R_(T2)]. But
[R_(T2)] is defined to be a set of _closed_ terms, while [t2] may
contain [x] free, so this does not make sense.
This problem is resolved by using a standard trick to suitably
generalize the induction hypothesis: instead of proving a statement
involving a closed term, we generalize it to cover all closed
_instances_ of an open term [t]. Informally, the statement of the
lemma will look like this:
If [x1:T1,..xn:Tn |- t : T] and [v1,...,vn] are values such that
[R T1 v1], [R T2 v2], ..., [R Tn vn], then
[R T ([x1:=v1][x2:=v2]...[xn:=vn]t)].
The proof will proceed by induction on the typing derivation
[x1:T1,..xn:Tn |- t : T]; the most interesting case will be the one
for abstraction. *)
(* ###################################################################### *)
(** *** Multisubstitutions, multi-extensions, and instantiations *)
(** However, before we can proceed to formalize the statement and
proof of the lemma, we'll need to build some (rather tedious)
machinery to deal with the fact that we are performing _multiple_
substitutions on term [t] and _multiple_ extensions of the typing
context. In particular, we must be precise about the order in which
the substitutions occur and how they act on each other. Often these
details are simply elided in informal paper proofs, but of course Coq
won't let us do that. Since here we are substituting closed terms, we
don't need to worry about how one substitution might affect the term
put in place by another. But we still do need to worry about the
_order_ of substitutions, because it is quite possible for the same
identifier to appear multiple times among the [x1,...xn] with
different associated [vi] and [Ti].
To make everything precise, we will assume that environments are
extended from left to right, and multiple substitutions are performed
from right to left. To see that this is consistent, suppose we have
an environment written as [...,y:bool,...,y:nat,...] and a
corresponding term substitution written as [...[y:=(tbool
true)]...[y:=(tnat 3)]...t]. Since environments are extended from
left to right, the binding [y:nat] hides the binding [y:bool]; since
substitutions are performed right to left, we do the substitution
[y:=(tnat 3)] first, so that the substitution [y:=(tbool true)] has
no effect. Substitution thus correctly preserves the type of the term.
With these points in mind, the following definitions should make sense.
A _multisubstitution_ is the result of applying a list of
substitutions, which we call an _environment_. *)
Definition env := list (id * tm).
Fixpoint msubst (ss:env) (t:tm) {struct ss} : tm :=
match ss with
| nil => t
| ((x,s)::ss') => msubst ss' ([x:=s]t)
end.
(** We need similar machinery to talk about repeated extension of a
typing context using a list of (identifier, type) pairs, which we
call a _type assignment_. *)
Definition tass := list (id * ty).
Fixpoint mextend (Gamma : context) (xts : tass) :=
match xts with
| nil => Gamma
| ((x,v)::xts') => extend (mextend Gamma xts') x v
end.
(** We will need some simple operations that work uniformly on
environments and type assigments *)
Fixpoint lookup {X:Set} (k : id) (l : list (id * X)) {struct l} : option X :=
match l with
| nil => None
| (j,x) :: l' =>
if beq_id j k then Some x else lookup k l'
end.
Fixpoint drop {X:Set} (n:id) (nxs:list (id * X)) {struct nxs} : list (id * X) :=
match nxs with
| nil => nil
| ((n',x)::nxs') => if beq_id n' n then drop n nxs' else (n',x)::(drop n nxs')
end.
(** An _instantiation_ combines a type assignment and a value
environment with the same domains, where corresponding elements are
in R *)
Inductive instantiation : tass -> env -> Prop :=
| V_nil : instantiation nil nil
| V_cons : forall x T v c e, value v -> R T v -> instantiation c e -> instantiation ((x,T)::c) ((x,v)::e).
(** We now proceed to prove various properties of these definitions. *)
(* ###################################################################### *)
(** *** More Substitution Facts *)
(** First we need some additional lemmas on (ordinary) substitution. *)
Lemma vacuous_substitution : forall t x,
~ appears_free_in x t ->
forall t', [x:=t']t = t.
Proof with eauto.
(* FILL IN HERE *) Admitted.
Lemma subst_closed: forall t,
closed t ->
forall x t', [x:=t']t = t.
Proof.
intros. apply vacuous_substitution. apply H. Qed.
Lemma subst_not_afi : forall t x v, closed v -> ~ appears_free_in x ([x:=v]t).
Proof with eauto. (* rather slow this way *)
unfold closed, not.
t_cases (induction t) Case; intros x v P A; simpl in A.
Case "tvar".
remember (beq_id x i) as e; destruct e...
inversion A; subst. rewrite <- beq_id_refl in Heqe; inversion Heqe.
Case "tapp".
inversion A; subst...
Case "tabs".
remember (beq_id x i) as e; destruct e...
apply beq_id_eq in Heqe; subst. inversion A; subst...
inversion A; subst...
Case "tpair".
inversion A; subst...
Case "tfst".
inversion A; subst...
Case "tsnd".
inversion A; subst...
Case "ttrue".
inversion A.
Case "tfalse".
inversion A.
Case "tif".
inversion A; subst...
Qed.
Lemma duplicate_subst : forall t' x t v,
closed v -> [x:=t]([x:=v]t') = [x:=v]t'.
Proof.
intros. eapply vacuous_substitution. apply subst_not_afi. auto.
Qed.
Lemma swap_subst : forall t x x1 v v1, x <> x1 -> closed v -> closed v1 ->
[x1:=v1]([x:=v]t) = [x:=v]([x1:=v1]t).
Proof with eauto.
t_cases (induction t) Case; intros; simpl.
Case "tvar".
remember (beq_id x i) as e; destruct e; remember (beq_id x1 i) as e; destruct e.
apply beq_id_eq in Heqe. apply beq_id_eq in Heqe0. subst.
apply ex_falso_quodlibet...
apply beq_id_eq in Heqe; subst. simpl.
rewrite <- beq_id_refl. apply subst_closed...
apply beq_id_eq in Heqe0; subst. simpl.
rewrite <- beq_id_refl. rewrite subst_closed...
simpl. rewrite <- Heqe. rewrite <- Heqe0...
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** *** Properties of multi-substitutions *)
Lemma msubst_closed: forall t, closed t -> forall ss, msubst ss t = t.
Proof.
induction ss.
reflexivity.
destruct a. simpl. rewrite subst_closed; assumption.
Qed.
(** Closed environments are those that contain only closed terms. *)
Fixpoint closed_env (env:env) {struct env} :=
match env with
| nil => True
| (x,t)::env' => closed t /\ closed_env env'
end.
(** Next come a series of lemmas charcterizing how [msubst] of closed terms
distributes over [subst] and over each term form *)
Lemma subst_msubst: forall env x v t, closed v -> closed_env env ->
msubst env ([x:=v]t) = [x:=v](msubst (drop x env) t).
Proof.
induction env0; intros.
auto.
destruct a. simpl.
inversion H0. fold closed_env in H2.
remember (beq_id i x) as e; destruct e.
apply beq_id_eq in Heqe; subst.
rewrite duplicate_subst; auto.
symmetry in Heqe. apply beq_id_false_not_eq in Heqe.
simpl. rewrite swap_subst; eauto.
Qed.
Lemma msubst_var: forall ss x, closed_env ss ->
msubst ss (tvar x) =
match lookup x ss with
| Some t => t
| None => tvar x
end.
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (beq_id i x).
apply msubst_closed. inversion H; auto.
apply IHss. inversion H; auto.
Qed.
Lemma msubst_abs: forall ss x T t,
msubst ss (tabs x T t) = tabs x T (msubst (drop x ss) t).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (beq_id i x); simpl; auto.
Qed.
Lemma msubst_app : forall ss t1 t2, msubst ss (tapp t1 t2) = tapp (msubst ss t1) (msubst ss t2).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. rewrite <- IHss. auto.
Qed.
(** You'll need similar functions for the other term constructors. *)
(* FILL IN HERE *)
(* ###################################################################### *)
(** *** Properties of multi-extensions *)
(** We need to connect the behavior of type assignments with that of their
corresponding contexts. *)
Lemma mextend_lookup : forall (c : tass) (x:id), lookup x c = (mextend empty c) x.
Proof.
induction c; intros.
auto.
destruct a. unfold lookup, mextend, extend. destruct (beq_id i x); auto.
Qed.
Lemma mextend_drop : forall (c: tass) Gamma x x',
mextend Gamma (drop x c) x' = if beq_id x x' then Gamma x' else mextend Gamma c x'.
induction c; intros.
destruct (beq_id x x'); auto.
destruct a. simpl.
remember (beq_id i x) as e; destruct e.
apply beq_id_eq in Heqe; subst. rewrite IHc.
remember (beq_id x x') as e; destruct e. auto. unfold extend. rewrite <- Heqe. auto.
simpl. unfold extend. remember (beq_id i x') as e; destruct e.
apply beq_id_eq in Heqe0; subst.
remember (beq_id x x') as e; destruct e.
apply beq_id_eq in Heqe0; subst. rewrite <- beq_id_refl in Heqe. inversion Heqe.
auto.
auto.
Qed.
(* ###################################################################### *)
(** *** Properties of Instantiations *)
(** These are strightforward. *)
Lemma instantiation_domains_match: forall {c} {e},
instantiation c e -> forall {x} {T}, lookup x c = Some T -> exists t, lookup x e = Some t.
Proof.
intros c e V. induction V; intros x0 T0 C.
solve by inversion .
simpl in *.
destruct (beq_id x x0); eauto.
Qed.
Lemma instantiation_env_closed : forall c e, instantiation c e -> closed_env e.
Proof.
intros c e V; induction V; intros.
econstructor.
unfold closed_env. fold closed_env.
split. eapply typable_empty__closed. eapply R_typable_empty. eauto.
auto.
Qed.
Lemma instantiation_R : forall c e, instantiation c e ->
forall x t T, lookup x c = Some T ->
lookup x e = Some t -> R T t.
Proof.
intros c e V. induction V; intros x' t' T' G E.
solve by inversion.
unfold lookup in *. destruct (beq_id x x').
inversion G; inversion E; subst. auto.
eauto.
Qed.
Lemma instantiation_drop : forall c env,
instantiation c env -> forall x, instantiation (drop x c) (drop x env).
Proof.
intros c e V. induction V.
intros. simpl. constructor.
intros. unfold drop. destruct (beq_id x x0); auto. constructor; eauto.
Qed.
(* ###################################################################### *)
(** *** Congruence lemmas on multistep *)
(** We'll need just a few of these; add them as the demand arises. *)
Lemma multistep_App2 : forall v t t',
value v -> (t ==>* t') -> (tapp v t) ==>* (tapp v t').
Proof.
intros v t t' V STM. induction STM.
apply multi_refl.
eapply multi_step.
apply ST_App2; eauto. auto.
Qed.
(* FILL IN HERE *)
(* ###################################################################### *)
(** *** The R Lemma. *)
(** We finally put everything together.
The key lemma about preservation of typing under substitution can
be lifted to multi-substitutions: *)
Lemma msubst_preserves_typing : forall c e,
instantiation c e ->
forall Gamma t S, has_type (mextend Gamma c) t S ->
has_type Gamma (msubst e t) S.
Proof.
induction 1; intros.
simpl in H. simpl. auto.
simpl in H2. simpl.
apply IHinstantiation.
eapply substitution_preserves_typing; eauto.
apply (R_typable_empty H0).
Qed.
(** And at long last, the main lemma. *)
Lemma msubst_R : forall c env t T,
has_type (mextend empty c) t T -> instantiation c env -> R T (msubst env t).
Proof.
intros c env0 t T HT V.
generalize dependent env0.
(* We need to generalize the hypothesis a bit before setting up the induction. *)
remember (mextend empty c) as Gamma.
assert (forall x, Gamma x = lookup x c).
intros. rewrite HeqGamma. rewrite mextend_lookup. auto.
clear HeqGamma.
generalize dependent c.
has_type_cases (induction HT) Case; intros.
Case "T_Var".
rewrite H0 in H. destruct (instantiation_domains_match V H) as [t P].
eapply instantiation_R; eauto.
rewrite msubst_var. rewrite P. auto. eapply instantiation_env_closed; eauto.
Case "T_Abs".
rewrite msubst_abs.
(* We'll need variants of the following fact several times, so its simplest to
establish it just once. *)
assert (WT: has_type empty (tabs x T11 (msubst (drop x env0) t12)) (TArrow T11 T12)).
eapply T_Abs. eapply msubst_preserves_typing. eapply instantiation_drop; eauto.
eapply context_invariance. apply HT.
intros.
unfold extend. rewrite mextend_drop. remember (beq_id x x0) as e; destruct e. auto.
rewrite H.
clear - c Heqe. induction c.
simpl. rewrite <- Heqe. auto.
simpl. destruct a. unfold extend. destruct (beq_id i x0); auto.
unfold R. fold R. split.
auto.
split. apply value_halts. apply v_abs.
intros.
destruct (R_halts H0) as [v [P Q]].
pose proof (multistep_preserves_R _ _ _ P H0).
apply multistep_preserves_R' with (msubst ((x,v)::env0) t12).
eapply T_App. eauto.
apply R_typable_empty; auto.
eapply multi_trans. eapply multistep_App2; eauto.
eapply multi_R.
simpl. rewrite subst_msubst.
eapply ST_AppAbs; eauto.
eapply typable_empty__closed.
apply (R_typable_empty H1).
eapply instantiation_env_closed; eauto.
eapply (IHHT ((x,T11)::c)).
intros. unfold extend, lookup. destruct (beq_id x x0); auto.
constructor; auto.
Case "T_App".
rewrite msubst_app.
destruct (IHHT1 c H env0 V) as [_ [_ P1]].
pose proof (IHHT2 c H env0 V) as P2. fold R in P1. auto.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** *** Normalization Theorem *)
Theorem normalization : forall t T, has_type empty t T -> halts t.
Proof.
intros.
replace t with (msubst nil t).
eapply R_halts.
eapply msubst_R; eauto. instantiate (2:= nil). eauto.
eapply V_nil.
auto.
Qed.
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_valid,
F_pcb,
F_valid,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 26: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_valid;
input [ 55: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 26: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 26: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_Nano_SOPC_cpu_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: DE0_Nano_SOPC_cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: DE0_Nano_SOPC_cpu_test_bench/W_wr_data is 'x'\n", $time);
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Finite set library *)
(** Set interfaces, inspired by the one of Ocaml. When compared with
Ocaml, the main differences are:
- the lack of [iter] function, useless since Coq is purely functional
- the use of [option] types instead of [Not_found] exceptions
- the use of [nat] instead of [int] for the [cardinal] function
Several variants of the set interfaces are available:
- [WSetsOn] : functorial signature for weak sets
- [WSets] : self-contained version of [WSets]
- [SetsOn] : functorial signature for ordered sets
- [Sets] : self-contained version of [Sets]
- [WRawSets] : a signature for weak sets that may be ill-formed
- [RawSets] : same for ordered sets
If unsure, [S = Sets] is probably what you're looking for: most other
signatures are subsets of it, while [Sets] can be obtained from
[RawSets] via the use of a subset type (see (W)Raw2Sets below).
*)
Require Export Bool SetoidList RelationClasses Morphisms
RelationPairs Equalities Orders OrdersFacts.
Set Implicit Arguments.
Unset Strict Implicit.
Module Type TypElt.
Parameters t elt : Type.
End TypElt.
Module Type HasWOps (Import T:TypElt).
Parameter empty : t.
(** The empty set. *)
Parameter is_empty : t -> bool.
(** Test whether a set is empty or not. *)
Parameter mem : elt -> t -> bool.
(** [mem x s] tests whether [x] belongs to the set [s]. *)
Parameter add : elt -> t -> t.
(** [add x s] returns a set containing all elements of [s],
plus [x]. If [x] was already in [s], [s] is returned unchanged. *)
Parameter singleton : elt -> t.
(** [singleton x] returns the one-element set containing only [x]. *)
Parameter remove : elt -> t -> t.
(** [remove x s] returns a set containing all elements of [s],
except [x]. If [x] was not in [s], [s] is returned unchanged. *)
Parameter union : t -> t -> t.
(** Set union. *)
Parameter inter : t -> t -> t.
(** Set intersection. *)
Parameter diff : t -> t -> t.
(** Set difference. *)
Parameter equal : t -> t -> bool.
(** [equal s1 s2] tests whether the sets [s1] and [s2] are
equal, that is, contain equal elements. *)
Parameter subset : t -> t -> bool.
(** [subset s1 s2] tests whether the set [s1] is a subset of
the set [s2]. *)
Parameter fold : forall A : Type, (elt -> A -> A) -> t -> A -> A.
(** [fold f s a] computes [(f xN ... (f x2 (f x1 a))...)],
where [x1 ... xN] are the elements of [s].
The order in which elements of [s] are presented to [f] is
unspecified. *)
Parameter for_all : (elt -> bool) -> t -> bool.
(** [for_all p s] checks if all elements of the set
satisfy the predicate [p]. *)
Parameter exists_ : (elt -> bool) -> t -> bool.
(** [exists p s] checks if at least one element of
the set satisfies the predicate [p]. *)
Parameter filter : (elt -> bool) -> t -> t.
(** [filter p s] returns the set of all elements in [s]
that satisfy predicate [p]. *)
Parameter partition : (elt -> bool) -> t -> t * t.
(** [partition p s] returns a pair of sets [(s1, s2)], where
[s1] is the set of all the elements of [s] that satisfy the
predicate [p], and [s2] is the set of all the elements of
[s] that do not satisfy [p]. *)
Parameter cardinal : t -> nat.
(** Return the number of elements of a set. *)
Parameter elements : t -> list elt.
(** Return the list of all elements of the given set, in any order. *)
Parameter choose : t -> option elt.
(** Return one element of the given set, or [None] if
the set is empty. Which element is chosen is unspecified.
Equal sets could return different elements. *)
End HasWOps.
Module Type WOps (E : DecidableType).
Definition elt := E.t.
Parameter t : Type. (** the abstract type of sets *)
Include HasWOps.
End WOps.
(** ** Functorial signature for weak sets
Weak sets are sets without ordering on base elements, only
a decidable equality. *)
Module Type WSetsOn (E : DecidableType).
(** First, we ask for all the functions *)
Include WOps E.
(** Logical predicates *)
Parameter In : elt -> t -> Prop.
Declare Instance In_compat : Proper (E.eq==>eq==>iff) In.
Definition Equal s s' := forall a : elt, In a s <-> In a s'.
Definition Subset s s' := forall a : elt, In a s -> In a s'.
Definition Empty s := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop) s := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop) s := exists x, In x s /\ P x.
Notation "s [=] t" := (Equal s t) (at level 70, no associativity).
Notation "s [<=] t" := (Subset s t) (at level 70, no associativity).
Definition eq : t -> t -> Prop := Equal.
Include IsEq. (** [eq] is obviously an equivalence, for subtyping only *)
Include HasEqDec.
(** Specifications of set operators *)
Section Spec.
Variable s s': t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Parameter mem_spec : mem x s = true <-> In x s.
Parameter equal_spec : equal s s' = true <-> s[=]s'.
Parameter subset_spec : subset s s' = true <-> s[<=]s'.
Parameter empty_spec : Empty empty.
Parameter is_empty_spec : is_empty s = true <-> Empty s.
Parameter add_spec : In y (add x s) <-> E.eq y x \/ In y s.
Parameter remove_spec : In y (remove x s) <-> In y s /\ ~E.eq y x.
Parameter singleton_spec : In y (singleton x) <-> E.eq y x.
Parameter union_spec : In x (union s s') <-> In x s \/ In x s'.
Parameter inter_spec : In x (inter s s') <-> In x s /\ In x s'.
Parameter diff_spec : In x (diff s s') <-> In x s /\ ~In x s'.
Parameter fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (flip f) (elements s) i.
Parameter cardinal_spec : cardinal s = length (elements s).
Parameter filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Parameter for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Parameter exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Parameter partition_spec1 : compatb f ->
fst (partition f s) [=] filter f s.
Parameter partition_spec2 : compatb f ->
snd (partition f s) [=] filter (fun x => negb (f x)) s.
Parameter elements_spec1 : InA E.eq x (elements s) <-> In x s.
(** When compared with ordered sets, here comes the only
property that is really weaker: *)
Parameter elements_spec2w : NoDupA E.eq (elements s).
Parameter choose_spec1 : choose s = Some x -> In x s.
Parameter choose_spec2 : choose s = None -> Empty s.
End Spec.
End WSetsOn.
(** ** Static signature for weak sets
Similar to the functorial signature [WSetsOn], except that the
module [E] of base elements is incorporated in the signature. *)
Module Type WSets.
Declare Module E : DecidableType.
Include WSetsOn E.
End WSets.
(** ** Functorial signature for sets on ordered elements
Based on [WSetsOn], plus ordering on sets and [min_elt] and [max_elt]
and some stronger specifications for other functions. *)
Module Type HasOrdOps (Import T:TypElt).
Parameter compare : t -> t -> comparison.
(** Total ordering between sets. Can be used as the ordering function
for doing sets of sets. *)
Parameter min_elt : t -> option elt.
(** Return the smallest element of the given set
(with respect to the [E.compare] ordering),
or [None] if the set is empty. *)
Parameter max_elt : t -> option elt.
(** Same as [min_elt], but returns the largest element of the
given set. *)
End HasOrdOps.
Module Type Ops (E : OrderedType) := WOps E <+ HasOrdOps.
Module Type SetsOn (E : OrderedType).
Include WSetsOn E <+ HasOrdOps <+ HasLt <+ IsStrOrder.
Section Spec.
Variable s s': t.
Variable x y : elt.
Parameter compare_spec : CompSpec eq lt s s' (compare s s').
(** Additional specification of [elements] *)
Parameter elements_spec2 : sort E.lt (elements s).
(** Remark: since [fold] is specified via [elements], this stronger
specification of [elements] has an indirect impact on [fold],
which can now be proved to receive elements in increasing order.
*)
Parameter min_elt_spec1 : min_elt s = Some x -> In x s.
Parameter min_elt_spec2 : min_elt s = Some x -> In y s -> ~ E.lt y x.
Parameter min_elt_spec3 : min_elt s = None -> Empty s.
Parameter max_elt_spec1 : max_elt s = Some x -> In x s.
Parameter max_elt_spec2 : max_elt s = Some x -> In y s -> ~ E.lt x y.
Parameter max_elt_spec3 : max_elt s = None -> Empty s.
(** Additional specification of [choose] *)
Parameter choose_spec3 : choose s = Some x -> choose s' = Some y ->
Equal s s' -> E.eq x y.
End Spec.
End SetsOn.
(** ** Static signature for sets on ordered elements
Similar to the functorial signature [SetsOn], except that the
module [E] of base elements is incorporated in the signature. *)
Module Type Sets.
Declare Module E : OrderedType.
Include SetsOn E.
End Sets.
Module Type S := Sets.
(** ** Some subtyping tests
<<
WSetsOn ---> WSets
| |
| |
V V
SetsOn ---> Sets
Module S_WS (M : Sets) <: WSets := M.
Module Sfun_WSfun (E:OrderedType)(M : SetsOn E) <: WSetsOn E := M.
Module S_Sfun (M : Sets) <: SetsOn M.E := M.
Module WS_WSfun (M : WSets) <: WSetsOn M.E := M.
>>
*)
(** ** Signatures for set representations with ill-formed values.
Motivation:
For many implementation of finite sets (AVL trees, sorted
lists, lists without duplicates), we use the same two-layer
approach:
- A first module deals with the datatype (eg. list or tree) without
any restriction on the values we consider. In this module (named
"Raw" in the past), some results are stated under the assumption
that some invariant (e.g. sortedness) holds for the input sets. We
also prove that this invariant is preserved by set operators.
- A second module implements the exact Sets interface by
using a subtype, for instance [{ l : list A | sorted l }].
This module is a mere wrapper around the first Raw module.
With the interfaces below, we give some respectability to
the "Raw" modules. This allows the interested users to directly
access them via the interfaces. Even better, we can build once
and for all a functor doing the transition between Raw and usual Sets.
Description:
The type [t] of sets may contain ill-formed values on which our
set operators may give wrong answers. In particular, [mem]
may not see a element in a ill-formed set (think for instance of a
unsorted list being given to an optimized [mem] that stops
its search as soon as a strictly larger element is encountered).
Unlike optimized operators, the [In] predicate is supposed to
always be correct, even on ill-formed sets. Same for [Equal] and
other logical predicates.
A predicate parameter [Ok] is used to discriminate between
well-formed and ill-formed values. Some lemmas hold only on sets
validating [Ok]. This predicate [Ok] is required to be
preserved by set operators. Moreover, a boolean function [isok]
should exist for identifying (at least some of) the well-formed sets.
*)
Module Type WRawSets (E : DecidableType).
(** First, we ask for all the functions *)
Include WOps E.
(** Is a set well-formed or ill-formed ? *)
Parameter IsOk : t -> Prop.
Class Ok (s:t) : Prop := ok : IsOk s.
(** In order to be able to validate (at least some) particular sets as
well-formed, we ask for a boolean function for (semi-)deciding
predicate [Ok]. If [Ok] isn't decidable, [isok] may be the
always-false function. *)
Parameter isok : t -> bool.
(** MS:
Dangerous instance, the [isok s = true] hypothesis cannot be discharged
with typeclass resolution. Is it really an instance? *)
Declare Instance isok_Ok s `(isok s = true) : Ok s | 10.
(** Logical predicates *)
Parameter In : elt -> t -> Prop.
Declare Instance In_compat : Proper (E.eq==>eq==>iff) In.
Definition Equal s s' := forall a : elt, In a s <-> In a s'.
Definition Subset s s' := forall a : elt, In a s -> In a s'.
Definition Empty s := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop) s := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop) s := exists x, In x s /\ P x.
Notation "s [=] t" := (Equal s t) (at level 70, no associativity).
Notation "s [<=] t" := (Subset s t) (at level 70, no associativity).
Definition eq : t -> t -> Prop := Equal.
Declare Instance eq_equiv : Equivalence eq.
(** First, all operations are compatible with the well-formed predicate. *)
Declare Instance empty_ok : Ok empty.
Declare Instance add_ok s x `(Ok s) : Ok (add x s).
Declare Instance remove_ok s x `(Ok s) : Ok (remove x s).
Declare Instance singleton_ok x : Ok (singleton x).
Declare Instance union_ok s s' `(Ok s, Ok s') : Ok (union s s').
Declare Instance inter_ok s s' `(Ok s, Ok s') : Ok (inter s s').
Declare Instance diff_ok s s' `(Ok s, Ok s') : Ok (diff s s').
Declare Instance filter_ok s f `(Ok s) : Ok (filter f s).
Declare Instance partition_ok1 s f `(Ok s) : Ok (fst (partition f s)).
Declare Instance partition_ok2 s f `(Ok s) : Ok (snd (partition f s)).
(** Now, the specifications, with constraints on the input sets. *)
Section Spec.
Variable s s': t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Parameter mem_spec : forall `{Ok s}, mem x s = true <-> In x s.
Parameter equal_spec : forall `{Ok s, Ok s'},
equal s s' = true <-> s[=]s'.
Parameter subset_spec : forall `{Ok s, Ok s'},
subset s s' = true <-> s[<=]s'.
Parameter empty_spec : Empty empty.
Parameter is_empty_spec : is_empty s = true <-> Empty s.
Parameter add_spec : forall `{Ok s},
In y (add x s) <-> E.eq y x \/ In y s.
Parameter remove_spec : forall `{Ok s},
In y (remove x s) <-> In y s /\ ~E.eq y x.
Parameter singleton_spec : In y (singleton x) <-> E.eq y x.
Parameter union_spec : forall `{Ok s, Ok s'},
In x (union s s') <-> In x s \/ In x s'.
Parameter inter_spec : forall `{Ok s, Ok s'},
In x (inter s s') <-> In x s /\ In x s'.
Parameter diff_spec : forall `{Ok s, Ok s'},
In x (diff s s') <-> In x s /\ ~In x s'.
Parameter fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (flip f) (elements s) i.
Parameter cardinal_spec : forall `{Ok s},
cardinal s = length (elements s).
Parameter filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Parameter for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Parameter exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Parameter partition_spec1 : compatb f ->
fst (partition f s) [=] filter f s.
Parameter partition_spec2 : compatb f ->
snd (partition f s) [=] filter (fun x => negb (f x)) s.
Parameter elements_spec1 : InA E.eq x (elements s) <-> In x s.
Parameter elements_spec2w : forall `{Ok s}, NoDupA E.eq (elements s).
Parameter choose_spec1 : choose s = Some x -> In x s.
Parameter choose_spec2 : choose s = None -> Empty s.
End Spec.
End WRawSets.
(** From weak raw sets to weak usual sets *)
Module WRaw2SetsOn (E:DecidableType)(M:WRawSets E) <: WSetsOn E.
(** We avoid creating induction principles for the Record *)
Local Unset Elimination Schemes.
Definition elt := E.t.
Record t_ := Mkt {this :> M.t; is_ok : M.Ok this}.
Definition t := t_.
Arguments Mkt this {is_ok}.
Hint Resolve is_ok : typeclass_instances.
Definition In (x : elt)(s : t) := M.In x s.(this).
Definition Equal (s s' : t) := forall a : elt, In a s <-> In a s'.
Definition Subset (s s' : t) := forall a : elt, In a s -> In a s'.
Definition Empty (s : t) := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop)(s : t) := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop)(s : t) := exists x, In x s /\ P x.
Definition mem (x : elt)(s : t) := M.mem x s.
Definition add (x : elt)(s : t) : t := Mkt (M.add x s).
Definition remove (x : elt)(s : t) : t := Mkt (M.remove x s).
Definition singleton (x : elt) : t := Mkt (M.singleton x).
Definition union (s s' : t) : t := Mkt (M.union s s').
Definition inter (s s' : t) : t := Mkt (M.inter s s').
Definition diff (s s' : t) : t := Mkt (M.diff s s').
Definition equal (s s' : t) := M.equal s s'.
Definition subset (s s' : t) := M.subset s s'.
Definition empty : t := Mkt M.empty.
Definition is_empty (s : t) := M.is_empty s.
Definition elements (s : t) : list elt := M.elements s.
Definition choose (s : t) : option elt := M.choose s.
Definition fold (A : Type)(f : elt -> A -> A)(s : t) : A -> A := M.fold f s.
Definition cardinal (s : t) := M.cardinal s.
Definition filter (f : elt -> bool)(s : t) : t := Mkt (M.filter f s).
Definition for_all (f : elt -> bool)(s : t) := M.for_all f s.
Definition exists_ (f : elt -> bool)(s : t) := M.exists_ f s.
Definition partition (f : elt -> bool)(s : t) : t * t :=
let p := M.partition f s in (Mkt (fst p), Mkt (snd p)).
Instance In_compat : Proper (E.eq==>eq==>iff) In.
Proof. repeat red. intros; apply M.In_compat; congruence. Qed.
Definition eq : t -> t -> Prop := Equal.
Instance eq_equiv : Equivalence eq.
Proof. firstorder. Qed.
Definition eq_dec : forall (s s':t), { eq s s' }+{ ~eq s s' }.
Proof.
intros (s,Hs) (s',Hs').
change ({M.Equal s s'}+{~M.Equal s s'}).
destruct (M.equal s s') eqn:H; [left|right];
rewrite <- M.equal_spec; congruence.
Defined.
Section Spec.
Variable s s' : t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Lemma mem_spec : mem x s = true <-> In x s.
Proof. exact (@M.mem_spec _ _ _). Qed.
Lemma equal_spec : equal s s' = true <-> Equal s s'.
Proof. exact (@M.equal_spec _ _ _ _). Qed.
Lemma subset_spec : subset s s' = true <-> Subset s s'.
Proof. exact (@M.subset_spec _ _ _ _). Qed.
Lemma empty_spec : Empty empty.
Proof. exact M.empty_spec. Qed.
Lemma is_empty_spec : is_empty s = true <-> Empty s.
Proof. exact (@M.is_empty_spec _). Qed.
Lemma add_spec : In y (add x s) <-> E.eq y x \/ In y s.
Proof. exact (@M.add_spec _ _ _ _). Qed.
Lemma remove_spec : In y (remove x s) <-> In y s /\ ~E.eq y x.
Proof. exact (@M.remove_spec _ _ _ _). Qed.
Lemma singleton_spec : In y (singleton x) <-> E.eq y x.
Proof. exact (@M.singleton_spec _ _). Qed.
Lemma union_spec : In x (union s s') <-> In x s \/ In x s'.
Proof. exact (@M.union_spec _ _ _ _ _). Qed.
Lemma inter_spec : In x (inter s s') <-> In x s /\ In x s'.
Proof. exact (@M.inter_spec _ _ _ _ _). Qed.
Lemma diff_spec : In x (diff s s') <-> In x s /\ ~In x s'.
Proof. exact (@M.diff_spec _ _ _ _ _). Qed.
Lemma fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (fun a e => f e a) (elements s) i.
Proof. exact (@M.fold_spec _). Qed.
Lemma cardinal_spec : cardinal s = length (elements s).
Proof. exact (@M.cardinal_spec s _). Qed.
Lemma filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Proof. exact (@M.filter_spec _ _ _). Qed.
Lemma for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Proof. exact (@M.for_all_spec _ _). Qed.
Lemma exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Proof. exact (@M.exists_spec _ _). Qed.
Lemma partition_spec1 : compatb f -> Equal (fst (partition f s)) (filter f s).
Proof. exact (@M.partition_spec1 _ _). Qed.
Lemma partition_spec2 : compatb f ->
Equal (snd (partition f s)) (filter (fun x => negb (f x)) s).
Proof. exact (@M.partition_spec2 _ _). Qed.
Lemma elements_spec1 : InA E.eq x (elements s) <-> In x s.
Proof. exact (@M.elements_spec1 _ _). Qed.
Lemma elements_spec2w : NoDupA E.eq (elements s).
Proof. exact (@M.elements_spec2w _ _). Qed.
Lemma choose_spec1 : choose s = Some x -> In x s.
Proof. exact (@M.choose_spec1 _ _). Qed.
Lemma choose_spec2 : choose s = None -> Empty s.
Proof. exact (@M.choose_spec2 _). Qed.
End Spec.
End WRaw2SetsOn.
Module WRaw2Sets (D:DecidableType)(M:WRawSets D) <: WSets with Module E := D.
Module E := D.
Include WRaw2SetsOn D M.
End WRaw2Sets.
(** Same approach for ordered sets *)
Module Type RawSets (E : OrderedType).
Include WRawSets E <+ HasOrdOps <+ HasLt <+ IsStrOrder.
Section Spec.
Variable s s': t.
Variable x y : elt.
(** Specification of [compare] *)
Parameter compare_spec : forall `{Ok s, Ok s'}, CompSpec eq lt s s' (compare s s').
(** Additional specification of [elements] *)
Parameter elements_spec2 : forall `{Ok s}, sort E.lt (elements s).
(** Specification of [min_elt] *)
Parameter min_elt_spec1 : min_elt s = Some x -> In x s.
Parameter min_elt_spec2 : forall `{Ok s}, min_elt s = Some x -> In y s -> ~ E.lt y x.
Parameter min_elt_spec3 : min_elt s = None -> Empty s.
(** Specification of [max_elt] *)
Parameter max_elt_spec1 : max_elt s = Some x -> In x s.
Parameter max_elt_spec2 : forall `{Ok s}, max_elt s = Some x -> In y s -> ~ E.lt x y.
Parameter max_elt_spec3 : max_elt s = None -> Empty s.
(** Additional specification of [choose] *)
Parameter choose_spec3 : forall `{Ok s, Ok s'},
choose s = Some x -> choose s' = Some y -> Equal s s' -> E.eq x y.
End Spec.
End RawSets.
(** From Raw to usual sets *)
Module Raw2SetsOn (O:OrderedType)(M:RawSets O) <: SetsOn O.
Include WRaw2SetsOn O M.
Definition compare (s s':t) := M.compare s s'.
Definition min_elt (s:t) : option elt := M.min_elt s.
Definition max_elt (s:t) : option elt := M.max_elt s.
Definition lt (s s':t) := M.lt s s'.
(** Specification of [lt] *)
Instance lt_strorder : StrictOrder lt.
Proof. constructor ; unfold lt; red.
unfold complement. red. intros. apply (irreflexivity H).
intros. transitivity y; auto.
Qed.
Instance lt_compat : Proper (eq==>eq==>iff) lt.
Proof.
repeat red. unfold eq, lt.
intros (s1,p1) (s2,p2) E (s1',p1') (s2',p2') E'; simpl.
change (M.eq s1 s2) in E.
change (M.eq s1' s2') in E'.
rewrite E,E'; intuition.
Qed.
Section Spec.
Variable s s' s'' : t.
Variable x y : elt.
Lemma compare_spec : CompSpec eq lt s s' (compare s s').
Proof. unfold compare; destruct (@M.compare_spec s s' _ _); auto. Qed.
(** Additional specification of [elements] *)
Lemma elements_spec2 : sort O.lt (elements s).
Proof. exact (@M.elements_spec2 _ _). Qed.
(** Specification of [min_elt] *)
Lemma min_elt_spec1 : min_elt s = Some x -> In x s.
Proof. exact (@M.min_elt_spec1 _ _). Qed.
Lemma min_elt_spec2 : min_elt s = Some x -> In y s -> ~ O.lt y x.
Proof. exact (@M.min_elt_spec2 _ _ _ _). Qed.
Lemma min_elt_spec3 : min_elt s = None -> Empty s.
Proof. exact (@M.min_elt_spec3 _). Qed.
(** Specification of [max_elt] *)
Lemma max_elt_spec1 : max_elt s = Some x -> In x s.
Proof. exact (@M.max_elt_spec1 _ _). Qed.
Lemma max_elt_spec2 : max_elt s = Some x -> In y s -> ~ O.lt x y.
Proof. exact (@M.max_elt_spec2 _ _ _ _). Qed.
Lemma max_elt_spec3 : max_elt s = None -> Empty s.
Proof. exact (@M.max_elt_spec3 _). Qed.
(** Additional specification of [choose] *)
Lemma choose_spec3 :
choose s = Some x -> choose s' = Some y -> Equal s s' -> O.eq x y.
Proof. exact (@M.choose_spec3 _ _ _ _ _ _). Qed.
End Spec.
End Raw2SetsOn.
Module Raw2Sets (O:OrderedType)(M:RawSets O) <: Sets with Module E := O.
Module E := O.
Include Raw2SetsOn O M.
End Raw2Sets.
(** It is in fact possible to provide an ordering on sets with
very little information on them (more or less only the [In]
predicate). This generic build of ordering is in fact not
used for the moment, we rather use a simplier version
dedicated to sets-as-sorted-lists, see [MakeListOrdering].
*)
Module Type IN (O:OrderedType).
Parameter Inline t : Type.
Parameter Inline In : O.t -> t -> Prop.
Declare Instance In_compat : Proper (O.eq==>eq==>iff) In.
Definition Equal s s' := forall x, In x s <-> In x s'.
Definition Empty s := forall x, ~In x s.
End IN.
Module MakeSetOrdering (O:OrderedType)(Import M:IN O).
Module Import MO := OrderedTypeFacts O.
Definition eq : t -> t -> Prop := Equal.
Instance eq_equiv : Equivalence eq.
Proof. firstorder. Qed.
Instance : Proper (O.eq==>eq==>iff) In.
Proof.
intros x x' Ex s s' Es. rewrite Ex. apply Es.
Qed.
Definition Below x s := forall y, In y s -> O.lt y x.
Definition Above x s := forall y, In y s -> O.lt x y.
Definition EquivBefore x s s' :=
forall y, O.lt y x -> (In y s <-> In y s').
Definition EmptyBetween x y s :=
forall z, In z s -> O.lt z y -> O.lt z x.
Definition lt s s' := exists x, EquivBefore x s s' /\
((In x s' /\ Below x s) \/
(In x s /\ exists y, In y s' /\ O.lt x y /\ EmptyBetween x y s')).
Instance : Proper (O.eq==>eq==>eq==>iff) EquivBefore.
Proof.
unfold EquivBefore. intros x x' E s1 s1' E1 s2 s2' E2.
setoid_rewrite E; setoid_rewrite E1; setoid_rewrite E2; intuition.
Qed.
Instance : Proper (O.eq==>eq==>iff) Below.
Proof.
unfold Below. intros x x' Ex s s' Es.
setoid_rewrite Ex; setoid_rewrite Es; intuition.
Qed.
Instance : Proper (O.eq==>eq==>iff) Above.
Proof.
unfold Above. intros x x' Ex s s' Es.
setoid_rewrite Ex; setoid_rewrite Es; intuition.
Qed.
Instance : Proper (O.eq==>O.eq==>eq==>iff) EmptyBetween.
Proof.
unfold EmptyBetween. intros x x' Ex y y' Ey s s' Es.
setoid_rewrite Ex; setoid_rewrite Ey; setoid_rewrite Es; intuition.
Qed.
Instance lt_compat : Proper (eq==>eq==>iff) lt.
Proof.
unfold lt. intros s1 s1' E1 s2 s2' E2.
setoid_rewrite E1; setoid_rewrite E2; intuition.
Qed.
Instance lt_strorder : StrictOrder lt.
Proof.
split.
(* irreflexive *)
intros s (x & _ & [(IN,Em)|(IN & y & IN' & LT & Be)]).
specialize (Em x IN); order.
specialize (Be x IN LT); order.
(* transitive *)
intros s1 s2 s3 (x & EQ & [(IN,Pre)|(IN,Lex)])
(x' & EQ' & [(IN',Pre')|(IN',Lex')]).
(* 1) Pre / Pre --> Pre *)
assert (O.lt x x') by (specialize (Pre' x IN); auto).
exists x; split.
intros y Hy; rewrite <- (EQ' y); auto; order.
left; split; auto.
rewrite <- (EQ' x); auto.
(* 2) Pre / Lex *)
elim_compare x x'.
(* 2a) x=x' --> Pre *)
destruct Lex' as (y & INy & LT & Be).
exists y; split.
intros z Hz. split; intros INz.
specialize (Pre z INz). rewrite <- (EQ' z), <- (EQ z); auto; order.
specialize (Be z INz Hz). rewrite (EQ z), (EQ' z); auto; order.
left; split; auto.
intros z Hz. transitivity x; auto; order.
(* 2b) x<x' --> Pre *)
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
left; split; auto.
rewrite <- (EQ' x); auto.
(* 2c) x>x' --> Lex *)
exists x'; split.
intros z Hz. rewrite (EQ z) by order; auto.
right; split; auto.
rewrite (EQ x'); auto.
(* 3) Lex / Pre --> Lex *)
destruct Lex as (y & INy & LT & Be).
specialize (Pre' y INy).
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
right; split; auto.
exists y; repeat split; auto.
rewrite <- (EQ' y); auto.
intros z Hz LTz; apply Be; auto. rewrite (EQ' z); auto; order.
(* 4) Lex / Lex *)
elim_compare x x'.
(* 4a) x=x' --> impossible *)
destruct Lex as (y & INy & LT & Be).
setoid_replace x with x' in LT; auto.
specialize (Be x' IN' LT); order.
(* 4b) x<x' --> Lex *)
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
right; split; auto.
destruct Lex as (y & INy & LT & Be).
elim_compare y x'.
(* 4ba *)
destruct Lex' as (y' & Iny' & LT' & Be').
exists y'; repeat split; auto. order.
intros z Hz LTz. specialize (Be' z Hz LTz).
rewrite <- (EQ' z) in Hz by order.
apply Be; auto. order.
(* 4bb *)
exists y; repeat split; auto.
rewrite <- (EQ' y); auto.
intros z Hz LTz. apply Be; auto. rewrite (EQ' z); auto; order.
(* 4bc*)
assert (O.lt x' x) by auto. order.
(* 4c) x>x' --> Lex *)
exists x'; split.
intros z Hz. rewrite (EQ z) by order; auto.
right; split; auto.
rewrite (EQ x'); auto.
Qed.
Lemma lt_empty_r : forall s s', Empty s' -> ~ lt s s'.
Proof.
intros s s' Hs' (x & _ & [(IN,_)|(_ & y & IN & _)]).
elim (Hs' x IN).
elim (Hs' y IN).
Qed.
Definition Add x s s' := forall y, In y s' <-> O.eq x y \/ In y s.
Lemma lt_empty_l : forall x s1 s2 s2',
Empty s1 -> Above x s2 -> Add x s2 s2' -> lt s1 s2'.
Proof.
intros x s1 s2 s2' Em Ab Ad.
exists x; split.
intros y Hy; split; intros IN.
elim (Em y IN).
rewrite (Ad y) in IN; destruct IN as [EQ|IN]. order.
specialize (Ab y IN). order.
left; split.
rewrite (Ad x). now left.
intros y Hy. elim (Em y Hy).
Qed.
Lemma lt_add_lt : forall x1 x2 s1 s1' s2 s2',
Above x1 s1 -> Above x2 s2 -> Add x1 s1 s1' -> Add x2 s2 s2' ->
O.lt x1 x2 -> lt s1' s2'.
Proof.
intros x1 x2 s1 s1' s2 s2' Ab1 Ab2 Ad1 Ad2 LT.
exists x1; split; [ | right; split]; auto.
intros y Hy. rewrite (Ad1 y), (Ad2 y).
split; intros [U|U]; try order.
specialize (Ab1 y U). order.
specialize (Ab2 y U). order.
rewrite (Ad1 x1); auto with *.
exists x2; repeat split; auto.
rewrite (Ad2 x2); now left.
intros y. rewrite (Ad2 y). intros [U|U]. order.
specialize (Ab2 y U). order.
Qed.
Lemma lt_add_eq : forall x1 x2 s1 s1' s2 s2',
Above x1 s1 -> Above x2 s2 -> Add x1 s1 s1' -> Add x2 s2 s2' ->
O.eq x1 x2 -> lt s1 s2 -> lt s1' s2'.
Proof.
intros x1 x2 s1 s1' s2 s2' Ab1 Ab2 Ad1 Ad2 Hx (x & EQ & Disj).
assert (O.lt x1 x).
destruct Disj as [(IN,_)|(IN,_)]; auto. rewrite Hx; auto.
exists x; split.
intros z Hz. rewrite (Ad1 z), (Ad2 z).
split; intros [U|U]; try (left; order); right.
rewrite <- (EQ z); auto.
rewrite (EQ z); auto.
destruct Disj as [(IN,Em)|(IN & y & INy & LTy & Be)].
left; split; auto.
rewrite (Ad2 x); auto.
intros z. rewrite (Ad1 z); intros [U|U]; try specialize (Ab1 z U); auto; order.
right; split; auto.
rewrite (Ad1 x); auto.
exists y; repeat split; auto.
rewrite (Ad2 y); auto.
intros z. rewrite (Ad2 z). intros [U|U]; try specialize (Ab2 z U); auto; order.
Qed.
End MakeSetOrdering.
Module MakeListOrdering (O:OrderedType).
Module MO:=OrderedTypeFacts O.
Local Notation t := (list O.t).
Local Notation In := (InA O.eq).
Definition eq s s' := forall x, In x s <-> In x s'.
Instance eq_equiv : Equivalence eq := _.
Inductive lt_list : t -> t -> Prop :=
| lt_nil : forall x s, lt_list nil (x :: s)
| lt_cons_lt : forall x y s s',
O.lt x y -> lt_list (x :: s) (y :: s')
| lt_cons_eq : forall x y s s',
O.eq x y -> lt_list s s' -> lt_list (x :: s) (y :: s').
Hint Constructors lt_list.
Definition lt := lt_list.
Hint Unfold lt.
Instance lt_strorder : StrictOrder lt.
Proof.
split.
(* irreflexive *)
assert (forall s s', s=s' -> ~lt s s').
red; induction 2.
discriminate.
inversion H; subst.
apply (StrictOrder_Irreflexive y); auto.
inversion H; subst; auto.
intros s Hs; exact (H s s (eq_refl s) Hs).
(* transitive *)
intros s s' s'' H; generalize s''; clear s''; elim H.
intros x l s'' H'; inversion_clear H'; auto.
intros x x' l l' E s'' H'; inversion_clear H'; auto.
constructor 2. transitivity x'; auto.
constructor 2. rewrite <- H0; auto.
intros.
inversion_clear H3.
constructor 2. rewrite H0; auto.
constructor 3; auto. transitivity y; auto. unfold lt in *; auto.
Qed.
Instance lt_compat' :
Proper (eqlistA O.eq==>eqlistA O.eq==>iff) lt.
Proof.
apply proper_sym_impl_iff_2; auto with *.
intros s1 s1' E1 s2 s2' E2 H.
revert s1' E1 s2' E2.
induction H; intros; inversion_clear E1; inversion_clear E2.
constructor 1.
constructor 2. MO.order.
constructor 3. MO.order. unfold lt in *; auto.
Qed.
Lemma eq_cons :
forall l1 l2 x y,
O.eq x y -> eq l1 l2 -> eq (x :: l1) (y :: l2).
Proof.
unfold eq; intros l1 l2 x y Exy E12 z.
split; inversion_clear 1.
left; MO.order. right; rewrite <- E12; auto.
left; MO.order. right; rewrite E12; auto.
Qed.
Hint Resolve eq_cons.
Lemma cons_CompSpec : forall c x1 x2 l1 l2, O.eq x1 x2 ->
CompSpec eq lt l1 l2 c -> CompSpec eq lt (x1::l1) (x2::l2) c.
Proof.
destruct c; simpl; inversion_clear 2; auto with relations.
Qed.
Hint Resolve cons_CompSpec.
End MakeListOrdering.
|
//////////////////////////////////////////////////////////////////
// //
// Wrapper for Xilinx Spartan-6 RAM Block //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// 2048 words x 32 bits with a per byte write enable //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module xs6_sram_2048x32_byte_en
#(
parameter SRAM0_INIT_0 = 256'h0,
parameter SRAM0_INIT_1 = 256'h0,
parameter SRAM0_INIT_2 = 256'h0,
parameter SRAM0_INIT_3 = 256'h0,
parameter SRAM0_INIT_4 = 256'h0,
parameter SRAM0_INIT_5 = 256'h0,
parameter SRAM0_INIT_6 = 256'h0,
parameter SRAM0_INIT_7 = 256'h0,
parameter SRAM0_INIT_8 = 256'h0,
parameter SRAM0_INIT_9 = 256'h0,
parameter SRAM0_INIT_10 = 256'h0,
parameter SRAM0_INIT_11 = 256'h0,
parameter SRAM0_INIT_12 = 256'h0,
parameter SRAM0_INIT_13 = 256'h0,
parameter SRAM0_INIT_14 = 256'h0,
parameter SRAM0_INIT_15 = 256'h0,
parameter SRAM0_INIT_16 = 256'h0,
parameter SRAM0_INIT_17 = 256'h0,
parameter SRAM0_INIT_18 = 256'h0,
parameter SRAM0_INIT_19 = 256'h0,
parameter SRAM0_INIT_20 = 256'h0,
parameter SRAM0_INIT_21 = 256'h0,
parameter SRAM0_INIT_22 = 256'h0,
parameter SRAM0_INIT_23 = 256'h0,
parameter SRAM0_INIT_24 = 256'h0,
parameter SRAM0_INIT_25 = 256'h0,
parameter SRAM0_INIT_26 = 256'h0,
parameter SRAM0_INIT_27 = 256'h0,
parameter SRAM0_INIT_28 = 256'h0,
parameter SRAM0_INIT_29 = 256'h0,
parameter SRAM0_INIT_30 = 256'h0,
parameter SRAM0_INIT_31 = 256'h0,
parameter SRAM0_INIT_32 = 256'h0,
parameter SRAM0_INIT_33 = 256'h0,
parameter SRAM0_INIT_34 = 256'h0,
parameter SRAM0_INIT_35 = 256'h0,
parameter SRAM0_INIT_36 = 256'h0,
parameter SRAM0_INIT_37 = 256'h0,
parameter SRAM0_INIT_38 = 256'h0,
parameter SRAM0_INIT_39 = 256'h0,
parameter SRAM0_INIT_40 = 256'h0,
parameter SRAM0_INIT_41 = 256'h0,
parameter SRAM0_INIT_42 = 256'h0,
parameter SRAM0_INIT_43 = 256'h0,
parameter SRAM0_INIT_44 = 256'h0,
parameter SRAM0_INIT_45 = 256'h0,
parameter SRAM0_INIT_46 = 256'h0,
parameter SRAM0_INIT_47 = 256'h0,
parameter SRAM0_INIT_48 = 256'h0,
parameter SRAM0_INIT_49 = 256'h0,
parameter SRAM0_INIT_50 = 256'h0,
parameter SRAM0_INIT_51 = 256'h0,
parameter SRAM0_INIT_52 = 256'h0,
parameter SRAM0_INIT_53 = 256'h0,
parameter SRAM0_INIT_54 = 256'h0,
parameter SRAM0_INIT_55 = 256'h0,
parameter SRAM0_INIT_56 = 256'h0,
parameter SRAM0_INIT_57 = 256'h0,
parameter SRAM0_INIT_58 = 256'h0,
parameter SRAM0_INIT_59 = 256'h0,
parameter SRAM0_INIT_60 = 256'h0,
parameter SRAM0_INIT_61 = 256'h0,
parameter SRAM0_INIT_62 = 256'h0,
parameter SRAM0_INIT_63 = 256'h0,
parameter SRAM1_INIT_0 = 256'h0,
parameter SRAM1_INIT_1 = 256'h0,
parameter SRAM1_INIT_2 = 256'h0,
parameter SRAM1_INIT_3 = 256'h0,
parameter SRAM1_INIT_4 = 256'h0,
parameter SRAM1_INIT_5 = 256'h0,
parameter SRAM1_INIT_6 = 256'h0,
parameter SRAM1_INIT_7 = 256'h0,
parameter SRAM1_INIT_8 = 256'h0,
parameter SRAM1_INIT_9 = 256'h0,
parameter SRAM1_INIT_10 = 256'h0,
parameter SRAM1_INIT_11 = 256'h0,
parameter SRAM1_INIT_12 = 256'h0,
parameter SRAM1_INIT_13 = 256'h0,
parameter SRAM1_INIT_14 = 256'h0,
parameter SRAM1_INIT_15 = 256'h0,
parameter SRAM1_INIT_16 = 256'h0,
parameter SRAM1_INIT_17 = 256'h0,
parameter SRAM1_INIT_18 = 256'h0,
parameter SRAM1_INIT_19 = 256'h0,
parameter SRAM1_INIT_20 = 256'h0,
parameter SRAM1_INIT_21 = 256'h0,
parameter SRAM1_INIT_22 = 256'h0,
parameter SRAM1_INIT_23 = 256'h0,
parameter SRAM1_INIT_24 = 256'h0,
parameter SRAM1_INIT_25 = 256'h0,
parameter SRAM1_INIT_26 = 256'h0,
parameter SRAM1_INIT_27 = 256'h0,
parameter SRAM1_INIT_28 = 256'h0,
parameter SRAM1_INIT_29 = 256'h0,
parameter SRAM1_INIT_30 = 256'h0,
parameter SRAM1_INIT_31 = 256'h0,
parameter SRAM1_INIT_32 = 256'h0,
parameter SRAM1_INIT_33 = 256'h0,
parameter SRAM1_INIT_34 = 256'h0,
parameter SRAM1_INIT_35 = 256'h0,
parameter SRAM1_INIT_36 = 256'h0,
parameter SRAM1_INIT_37 = 256'h0,
parameter SRAM1_INIT_38 = 256'h0,
parameter SRAM1_INIT_39 = 256'h0,
parameter SRAM1_INIT_40 = 256'h0,
parameter SRAM1_INIT_41 = 256'h0,
parameter SRAM1_INIT_42 = 256'h0,
parameter SRAM1_INIT_43 = 256'h0,
parameter SRAM1_INIT_44 = 256'h0,
parameter SRAM1_INIT_45 = 256'h0,
parameter SRAM1_INIT_46 = 256'h0,
parameter SRAM1_INIT_47 = 256'h0,
parameter SRAM1_INIT_48 = 256'h0,
parameter SRAM1_INIT_49 = 256'h0,
parameter SRAM1_INIT_50 = 256'h0,
parameter SRAM1_INIT_51 = 256'h0,
parameter SRAM1_INIT_52 = 256'h0,
parameter SRAM1_INIT_53 = 256'h0,
parameter SRAM1_INIT_54 = 256'h0,
parameter SRAM1_INIT_55 = 256'h0,
parameter SRAM1_INIT_56 = 256'h0,
parameter SRAM1_INIT_57 = 256'h0,
parameter SRAM1_INIT_58 = 256'h0,
parameter SRAM1_INIT_59 = 256'h0,
parameter SRAM1_INIT_60 = 256'h0,
parameter SRAM1_INIT_61 = 256'h0,
parameter SRAM1_INIT_62 = 256'h0,
parameter SRAM1_INIT_63 = 256'h0,
parameter SRAM2_INIT_0 = 256'h0,
parameter SRAM2_INIT_1 = 256'h0,
parameter SRAM2_INIT_2 = 256'h0,
parameter SRAM2_INIT_3 = 256'h0,
parameter SRAM2_INIT_4 = 256'h0,
parameter SRAM2_INIT_5 = 256'h0,
parameter SRAM2_INIT_6 = 256'h0,
parameter SRAM2_INIT_7 = 256'h0,
parameter SRAM2_INIT_8 = 256'h0,
parameter SRAM2_INIT_9 = 256'h0,
parameter SRAM2_INIT_10 = 256'h0,
parameter SRAM2_INIT_11 = 256'h0,
parameter SRAM2_INIT_12 = 256'h0,
parameter SRAM2_INIT_13 = 256'h0,
parameter SRAM2_INIT_14 = 256'h0,
parameter SRAM2_INIT_15 = 256'h0,
parameter SRAM2_INIT_16 = 256'h0,
parameter SRAM2_INIT_17 = 256'h0,
parameter SRAM2_INIT_18 = 256'h0,
parameter SRAM2_INIT_19 = 256'h0,
parameter SRAM2_INIT_20 = 256'h0,
parameter SRAM2_INIT_21 = 256'h0,
parameter SRAM2_INIT_22 = 256'h0,
parameter SRAM2_INIT_23 = 256'h0,
parameter SRAM2_INIT_24 = 256'h0,
parameter SRAM2_INIT_25 = 256'h0,
parameter SRAM2_INIT_26 = 256'h0,
parameter SRAM2_INIT_27 = 256'h0,
parameter SRAM2_INIT_28 = 256'h0,
parameter SRAM2_INIT_29 = 256'h0,
parameter SRAM2_INIT_30 = 256'h0,
parameter SRAM2_INIT_31 = 256'h0,
parameter SRAM2_INIT_32 = 256'h0,
parameter SRAM2_INIT_33 = 256'h0,
parameter SRAM2_INIT_34 = 256'h0,
parameter SRAM2_INIT_35 = 256'h0,
parameter SRAM2_INIT_36 = 256'h0,
parameter SRAM2_INIT_37 = 256'h0,
parameter SRAM2_INIT_38 = 256'h0,
parameter SRAM2_INIT_39 = 256'h0,
parameter SRAM2_INIT_40 = 256'h0,
parameter SRAM2_INIT_41 = 256'h0,
parameter SRAM2_INIT_42 = 256'h0,
parameter SRAM2_INIT_43 = 256'h0,
parameter SRAM2_INIT_44 = 256'h0,
parameter SRAM2_INIT_45 = 256'h0,
parameter SRAM2_INIT_46 = 256'h0,
parameter SRAM2_INIT_47 = 256'h0,
parameter SRAM2_INIT_48 = 256'h0,
parameter SRAM2_INIT_49 = 256'h0,
parameter SRAM2_INIT_50 = 256'h0,
parameter SRAM2_INIT_51 = 256'h0,
parameter SRAM2_INIT_52 = 256'h0,
parameter SRAM2_INIT_53 = 256'h0,
parameter SRAM2_INIT_54 = 256'h0,
parameter SRAM2_INIT_55 = 256'h0,
parameter SRAM2_INIT_56 = 256'h0,
parameter SRAM2_INIT_57 = 256'h0,
parameter SRAM2_INIT_58 = 256'h0,
parameter SRAM2_INIT_59 = 256'h0,
parameter SRAM2_INIT_60 = 256'h0,
parameter SRAM2_INIT_61 = 256'h0,
parameter SRAM2_INIT_62 = 256'h0,
parameter SRAM2_INIT_63 = 256'h0,
parameter SRAM3_INIT_0 = 256'h0,
parameter SRAM3_INIT_1 = 256'h0,
parameter SRAM3_INIT_2 = 256'h0,
parameter SRAM3_INIT_3 = 256'h0,
parameter SRAM3_INIT_4 = 256'h0,
parameter SRAM3_INIT_5 = 256'h0,
parameter SRAM3_INIT_6 = 256'h0,
parameter SRAM3_INIT_7 = 256'h0,
parameter SRAM3_INIT_8 = 256'h0,
parameter SRAM3_INIT_9 = 256'h0,
parameter SRAM3_INIT_10 = 256'h0,
parameter SRAM3_INIT_11 = 256'h0,
parameter SRAM3_INIT_12 = 256'h0,
parameter SRAM3_INIT_13 = 256'h0,
parameter SRAM3_INIT_14 = 256'h0,
parameter SRAM3_INIT_15 = 256'h0,
parameter SRAM3_INIT_16 = 256'h0,
parameter SRAM3_INIT_17 = 256'h0,
parameter SRAM3_INIT_18 = 256'h0,
parameter SRAM3_INIT_19 = 256'h0,
parameter SRAM3_INIT_20 = 256'h0,
parameter SRAM3_INIT_21 = 256'h0,
parameter SRAM3_INIT_22 = 256'h0,
parameter SRAM3_INIT_23 = 256'h0,
parameter SRAM3_INIT_24 = 256'h0,
parameter SRAM3_INIT_25 = 256'h0,
parameter SRAM3_INIT_26 = 256'h0,
parameter SRAM3_INIT_27 = 256'h0,
parameter SRAM3_INIT_28 = 256'h0,
parameter SRAM3_INIT_29 = 256'h0,
parameter SRAM3_INIT_30 = 256'h0,
parameter SRAM3_INIT_31 = 256'h0,
parameter SRAM3_INIT_32 = 256'h0,
parameter SRAM3_INIT_33 = 256'h0,
parameter SRAM3_INIT_34 = 256'h0,
parameter SRAM3_INIT_35 = 256'h0,
parameter SRAM3_INIT_36 = 256'h0,
parameter SRAM3_INIT_37 = 256'h0,
parameter SRAM3_INIT_38 = 256'h0,
parameter SRAM3_INIT_39 = 256'h0,
parameter SRAM3_INIT_40 = 256'h0,
parameter SRAM3_INIT_41 = 256'h0,
parameter SRAM3_INIT_42 = 256'h0,
parameter SRAM3_INIT_43 = 256'h0,
parameter SRAM3_INIT_44 = 256'h0,
parameter SRAM3_INIT_45 = 256'h0,
parameter SRAM3_INIT_46 = 256'h0,
parameter SRAM3_INIT_47 = 256'h0,
parameter SRAM3_INIT_48 = 256'h0,
parameter SRAM3_INIT_49 = 256'h0,
parameter SRAM3_INIT_50 = 256'h0,
parameter SRAM3_INIT_51 = 256'h0,
parameter SRAM3_INIT_52 = 256'h0,
parameter SRAM3_INIT_53 = 256'h0,
parameter SRAM3_INIT_54 = 256'h0,
parameter SRAM3_INIT_55 = 256'h0,
parameter SRAM3_INIT_56 = 256'h0,
parameter SRAM3_INIT_57 = 256'h0,
parameter SRAM3_INIT_58 = 256'h0,
parameter SRAM3_INIT_59 = 256'h0,
parameter SRAM3_INIT_60 = 256'h0,
parameter SRAM3_INIT_61 = 256'h0,
parameter SRAM3_INIT_62 = 256'h0,
parameter SRAM3_INIT_63 = 256'h0,
parameter UNUSED = 1'd1
)
(
input i_clk,
input [31:0] i_write_data,
input i_write_enable,
input [10:0] i_address,
input [3:0] i_byte_enable,
output [31:0] o_read_data
);
wire [3:0] wea;
wire [31:0] data_out [3:0];
assign o_read_data = { data_out[3][7:0], data_out[2][7:0],
data_out[1][7:0], data_out[0][7:0] };
assign wea = {4{i_write_enable}} & i_byte_enable;
RAMB16BWER #(
.INIT_00 ( SRAM0_INIT_0 ),
.INIT_01 ( SRAM0_INIT_1 ),
.INIT_02 ( SRAM0_INIT_2 ),
.INIT_03 ( SRAM0_INIT_3 ),
.INIT_04 ( SRAM0_INIT_4 ),
.INIT_05 ( SRAM0_INIT_5 ),
.INIT_06 ( SRAM0_INIT_6 ),
.INIT_07 ( SRAM0_INIT_7 ),
.INIT_08 ( SRAM0_INIT_8 ),
.INIT_09 ( SRAM0_INIT_9 ),
.INIT_0A ( SRAM0_INIT_10 ),
.INIT_0B ( SRAM0_INIT_11 ),
.INIT_0C ( SRAM0_INIT_12 ),
.INIT_0D ( SRAM0_INIT_13 ),
.INIT_0E ( SRAM0_INIT_14 ),
.INIT_0F ( SRAM0_INIT_15 ),
.INIT_10 ( SRAM0_INIT_16 ),
.INIT_11 ( SRAM0_INIT_17 ),
.INIT_12 ( SRAM0_INIT_18 ),
.INIT_13 ( SRAM0_INIT_19 ),
.INIT_14 ( SRAM0_INIT_20 ),
.INIT_15 ( SRAM0_INIT_21 ),
.INIT_16 ( SRAM0_INIT_22 ),
.INIT_17 ( SRAM0_INIT_23 ),
.INIT_18 ( SRAM0_INIT_24 ),
.INIT_19 ( SRAM0_INIT_25 ),
.INIT_1A ( SRAM0_INIT_26 ),
.INIT_1B ( SRAM0_INIT_27 ),
.INIT_1C ( SRAM0_INIT_28 ),
.INIT_1D ( SRAM0_INIT_29 ),
.INIT_1E ( SRAM0_INIT_30 ),
.INIT_1F ( SRAM0_INIT_31 ),
.INIT_20 ( SRAM0_INIT_32 ),
.INIT_21 ( SRAM0_INIT_33 ),
.INIT_22 ( SRAM0_INIT_34 ),
.INIT_23 ( SRAM0_INIT_35 ),
.INIT_24 ( SRAM0_INIT_36 ),
.INIT_25 ( SRAM0_INIT_37 ),
.INIT_26 ( SRAM0_INIT_38 ),
.INIT_27 ( SRAM0_INIT_39 ),
.INIT_28 ( SRAM0_INIT_40 ),
.INIT_29 ( SRAM0_INIT_41 ),
.INIT_2A ( SRAM0_INIT_42 ),
.INIT_2B ( SRAM0_INIT_43 ),
.INIT_2C ( SRAM0_INIT_44 ),
.INIT_2D ( SRAM0_INIT_45 ),
.INIT_2E ( SRAM0_INIT_46 ),
.INIT_2F ( SRAM0_INIT_47 ),
.INIT_30 ( SRAM0_INIT_48 ),
.INIT_31 ( SRAM0_INIT_49 ),
.INIT_32 ( SRAM0_INIT_50 ),
.INIT_33 ( SRAM0_INIT_51 ),
.INIT_34 ( SRAM0_INIT_52 ),
.INIT_35 ( SRAM0_INIT_53 ),
.INIT_36 ( SRAM0_INIT_54 ),
.INIT_37 ( SRAM0_INIT_55 ),
.INIT_38 ( SRAM0_INIT_56 ),
.INIT_39 ( SRAM0_INIT_57 ),
.INIT_3A ( SRAM0_INIT_58 ),
.INIT_3B ( SRAM0_INIT_59 ),
.INIT_3C ( SRAM0_INIT_60 ),
.INIT_3D ( SRAM0_INIT_61 ),
.INIT_3E ( SRAM0_INIT_62 ),
.INIT_3F ( SRAM0_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram0 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( {wea[3], wea[3], wea[3], wea[3]} ),
.DOA ( data_out[3] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[31:24]} )
);
RAMB16BWER #(
.INIT_00 ( SRAM1_INIT_0 ),
.INIT_01 ( SRAM1_INIT_1 ),
.INIT_02 ( SRAM1_INIT_2 ),
.INIT_03 ( SRAM1_INIT_3 ),
.INIT_04 ( SRAM1_INIT_4 ),
.INIT_05 ( SRAM1_INIT_5 ),
.INIT_06 ( SRAM1_INIT_6 ),
.INIT_07 ( SRAM1_INIT_7 ),
.INIT_08 ( SRAM1_INIT_8 ),
.INIT_09 ( SRAM1_INIT_9 ),
.INIT_0A ( SRAM1_INIT_10 ),
.INIT_0B ( SRAM1_INIT_11 ),
.INIT_0C ( SRAM1_INIT_12 ),
.INIT_0D ( SRAM1_INIT_13 ),
.INIT_0E ( SRAM1_INIT_14 ),
.INIT_0F ( SRAM1_INIT_15 ),
.INIT_10 ( SRAM1_INIT_16 ),
.INIT_11 ( SRAM1_INIT_17 ),
.INIT_12 ( SRAM1_INIT_18 ),
.INIT_13 ( SRAM1_INIT_19 ),
.INIT_14 ( SRAM1_INIT_20 ),
.INIT_15 ( SRAM1_INIT_21 ),
.INIT_16 ( SRAM1_INIT_22 ),
.INIT_17 ( SRAM1_INIT_23 ),
.INIT_18 ( SRAM1_INIT_24 ),
.INIT_19 ( SRAM1_INIT_25 ),
.INIT_1A ( SRAM1_INIT_26 ),
.INIT_1B ( SRAM1_INIT_27 ),
.INIT_1C ( SRAM1_INIT_28 ),
.INIT_1D ( SRAM1_INIT_29 ),
.INIT_1E ( SRAM1_INIT_30 ),
.INIT_1F ( SRAM1_INIT_31 ),
.INIT_20 ( SRAM1_INIT_32 ),
.INIT_21 ( SRAM1_INIT_33 ),
.INIT_22 ( SRAM1_INIT_34 ),
.INIT_23 ( SRAM1_INIT_35 ),
.INIT_24 ( SRAM1_INIT_36 ),
.INIT_25 ( SRAM1_INIT_37 ),
.INIT_26 ( SRAM1_INIT_38 ),
.INIT_27 ( SRAM1_INIT_39 ),
.INIT_28 ( SRAM1_INIT_40 ),
.INIT_29 ( SRAM1_INIT_41 ),
.INIT_2A ( SRAM1_INIT_42 ),
.INIT_2B ( SRAM1_INIT_43 ),
.INIT_2C ( SRAM1_INIT_44 ),
.INIT_2D ( SRAM1_INIT_45 ),
.INIT_2E ( SRAM1_INIT_46 ),
.INIT_2F ( SRAM1_INIT_47 ),
.INIT_30 ( SRAM1_INIT_48 ),
.INIT_31 ( SRAM1_INIT_49 ),
.INIT_32 ( SRAM1_INIT_50 ),
.INIT_33 ( SRAM1_INIT_51 ),
.INIT_34 ( SRAM1_INIT_52 ),
.INIT_35 ( SRAM1_INIT_53 ),
.INIT_36 ( SRAM1_INIT_54 ),
.INIT_37 ( SRAM1_INIT_55 ),
.INIT_38 ( SRAM1_INIT_56 ),
.INIT_39 ( SRAM1_INIT_57 ),
.INIT_3A ( SRAM1_INIT_58 ),
.INIT_3B ( SRAM1_INIT_59 ),
.INIT_3C ( SRAM1_INIT_60 ),
.INIT_3D ( SRAM1_INIT_61 ),
.INIT_3E ( SRAM1_INIT_62 ),
.INIT_3F ( SRAM1_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram1 (
.REGCEA(1'd0),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ({wea[2], wea[2], wea[2], wea[2]} ),
.DOA ( data_out[2] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[23:16]} )
);
RAMB16BWER #(
.INIT_00 ( SRAM2_INIT_0 ),
.INIT_01 ( SRAM2_INIT_1 ),
.INIT_02 ( SRAM2_INIT_2 ),
.INIT_03 ( SRAM2_INIT_3 ),
.INIT_04 ( SRAM2_INIT_4 ),
.INIT_05 ( SRAM2_INIT_5 ),
.INIT_06 ( SRAM2_INIT_6 ),
.INIT_07 ( SRAM2_INIT_7 ),
.INIT_08 ( SRAM2_INIT_8 ),
.INIT_09 ( SRAM2_INIT_9 ),
.INIT_0A ( SRAM2_INIT_10 ),
.INIT_0B ( SRAM2_INIT_11 ),
.INIT_0C ( SRAM2_INIT_12 ),
.INIT_0D ( SRAM2_INIT_13 ),
.INIT_0E ( SRAM2_INIT_14 ),
.INIT_0F ( SRAM2_INIT_15 ),
.INIT_10 ( SRAM2_INIT_16 ),
.INIT_11 ( SRAM2_INIT_17 ),
.INIT_12 ( SRAM2_INIT_18 ),
.INIT_13 ( SRAM2_INIT_19 ),
.INIT_14 ( SRAM2_INIT_20 ),
.INIT_15 ( SRAM2_INIT_21 ),
.INIT_16 ( SRAM2_INIT_22 ),
.INIT_17 ( SRAM2_INIT_23 ),
.INIT_18 ( SRAM2_INIT_24 ),
.INIT_19 ( SRAM2_INIT_25 ),
.INIT_1A ( SRAM2_INIT_26 ),
.INIT_1B ( SRAM2_INIT_27 ),
.INIT_1C ( SRAM2_INIT_28 ),
.INIT_1D ( SRAM2_INIT_29 ),
.INIT_1E ( SRAM2_INIT_30 ),
.INIT_1F ( SRAM2_INIT_31 ),
.INIT_20 ( SRAM2_INIT_32 ),
.INIT_21 ( SRAM2_INIT_33 ),
.INIT_22 ( SRAM2_INIT_34 ),
.INIT_23 ( SRAM2_INIT_35 ),
.INIT_24 ( SRAM2_INIT_36 ),
.INIT_25 ( SRAM2_INIT_37 ),
.INIT_26 ( SRAM2_INIT_38 ),
.INIT_27 ( SRAM2_INIT_39 ),
.INIT_28 ( SRAM2_INIT_40 ),
.INIT_29 ( SRAM2_INIT_41 ),
.INIT_2A ( SRAM2_INIT_42 ),
.INIT_2B ( SRAM2_INIT_43 ),
.INIT_2C ( SRAM2_INIT_44 ),
.INIT_2D ( SRAM2_INIT_45 ),
.INIT_2E ( SRAM2_INIT_46 ),
.INIT_2F ( SRAM2_INIT_47 ),
.INIT_30 ( SRAM2_INIT_48 ),
.INIT_31 ( SRAM2_INIT_49 ),
.INIT_32 ( SRAM2_INIT_50 ),
.INIT_33 ( SRAM2_INIT_51 ),
.INIT_34 ( SRAM2_INIT_52 ),
.INIT_35 ( SRAM2_INIT_53 ),
.INIT_36 ( SRAM2_INIT_54 ),
.INIT_37 ( SRAM2_INIT_55 ),
.INIT_38 ( SRAM2_INIT_56 ),
.INIT_39 ( SRAM2_INIT_57 ),
.INIT_3A ( SRAM2_INIT_58 ),
.INIT_3B ( SRAM2_INIT_59 ),
.INIT_3C ( SRAM2_INIT_60 ),
.INIT_3D ( SRAM2_INIT_61 ),
.INIT_3E ( SRAM2_INIT_62 ),
.INIT_3F ( SRAM2_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram2 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( {wea[1], wea[1], wea[1], wea[1]} ),
.DOA ( data_out[1] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[15:08]} )
);
RAMB16BWER #(
.INIT_00 ( SRAM3_INIT_0 ),
.INIT_01 ( SRAM3_INIT_1 ),
.INIT_02 ( SRAM3_INIT_2 ),
.INIT_03 ( SRAM3_INIT_3 ),
.INIT_04 ( SRAM3_INIT_4 ),
.INIT_05 ( SRAM3_INIT_5 ),
.INIT_06 ( SRAM3_INIT_6 ),
.INIT_07 ( SRAM3_INIT_7 ),
.INIT_08 ( SRAM3_INIT_8 ),
.INIT_09 ( SRAM3_INIT_9 ),
.INIT_0A ( SRAM3_INIT_10 ),
.INIT_0B ( SRAM3_INIT_11 ),
.INIT_0C ( SRAM3_INIT_12 ),
.INIT_0D ( SRAM3_INIT_13 ),
.INIT_0E ( SRAM3_INIT_14 ),
.INIT_0F ( SRAM3_INIT_15 ),
.INIT_10 ( SRAM3_INIT_16 ),
.INIT_11 ( SRAM3_INIT_17 ),
.INIT_12 ( SRAM3_INIT_18 ),
.INIT_13 ( SRAM3_INIT_19 ),
.INIT_14 ( SRAM3_INIT_20 ),
.INIT_15 ( SRAM3_INIT_21 ),
.INIT_16 ( SRAM3_INIT_22 ),
.INIT_17 ( SRAM3_INIT_23 ),
.INIT_18 ( SRAM3_INIT_24 ),
.INIT_19 ( SRAM3_INIT_25 ),
.INIT_1A ( SRAM3_INIT_26 ),
.INIT_1B ( SRAM3_INIT_27 ),
.INIT_1C ( SRAM3_INIT_28 ),
.INIT_1D ( SRAM3_INIT_29 ),
.INIT_1E ( SRAM3_INIT_30 ),
.INIT_1F ( SRAM3_INIT_31 ),
.INIT_20 ( SRAM3_INIT_32 ),
.INIT_21 ( SRAM3_INIT_33 ),
.INIT_22 ( SRAM3_INIT_34 ),
.INIT_23 ( SRAM3_INIT_35 ),
.INIT_24 ( SRAM3_INIT_36 ),
.INIT_25 ( SRAM3_INIT_37 ),
.INIT_26 ( SRAM3_INIT_38 ),
.INIT_27 ( SRAM3_INIT_39 ),
.INIT_28 ( SRAM3_INIT_40 ),
.INIT_29 ( SRAM3_INIT_41 ),
.INIT_2A ( SRAM3_INIT_42 ),
.INIT_2B ( SRAM3_INIT_43 ),
.INIT_2C ( SRAM3_INIT_44 ),
.INIT_2D ( SRAM3_INIT_45 ),
.INIT_2E ( SRAM3_INIT_46 ),
.INIT_2F ( SRAM3_INIT_47 ),
.INIT_30 ( SRAM3_INIT_48 ),
.INIT_31 ( SRAM3_INIT_49 ),
.INIT_32 ( SRAM3_INIT_50 ),
.INIT_33 ( SRAM3_INIT_51 ),
.INIT_34 ( SRAM3_INIT_52 ),
.INIT_35 ( SRAM3_INIT_53 ),
.INIT_36 ( SRAM3_INIT_54 ),
.INIT_37 ( SRAM3_INIT_55 ),
.INIT_38 ( SRAM3_INIT_56 ),
.INIT_39 ( SRAM3_INIT_57 ),
.INIT_3A ( SRAM3_INIT_58 ),
.INIT_3B ( SRAM3_INIT_59 ),
.INIT_3C ( SRAM3_INIT_60 ),
.INIT_3D ( SRAM3_INIT_61 ),
.INIT_3E ( SRAM3_INIT_62 ),
.INIT_3F ( SRAM3_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram3 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.WEA ({wea[0], wea[0], wea[0], wea[0]} ),
.DOA ( data_out[0] ),
.ADDRA ({i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIA ( {24'd0, i_write_data[7:0]} ),
.DIB ( 32'd0 ),
.DIPA ( 4'd0 ),
.DIPB ( 4'd0 ),
.DOPA ( ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 )
);
endmodule
|
//-----------------------------------------------------------------------------
// system_stub.v
//-----------------------------------------------------------------------------
module system_stub
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP,
processing_system7_0_M_AXI_GP1_ARESETN_pin,
processing_system7_0_S_AXI_HP1_ARESETN_pin,
processing_system7_0_FCLK_CLK3_pin,
processing_system7_0_FCLK_CLK0_pin,
processing_system7_0_M_AXI_GP1_ARVALID_pin,
processing_system7_0_M_AXI_GP1_AWVALID_pin,
processing_system7_0_M_AXI_GP1_BREADY_pin,
processing_system7_0_M_AXI_GP1_RREADY_pin,
processing_system7_0_M_AXI_GP1_WLAST_pin,
processing_system7_0_M_AXI_GP1_WVALID_pin,
processing_system7_0_M_AXI_GP1_ARID_pin,
processing_system7_0_M_AXI_GP1_AWID_pin,
processing_system7_0_M_AXI_GP1_WID_pin,
processing_system7_0_M_AXI_GP1_ARBURST_pin,
processing_system7_0_M_AXI_GP1_ARLOCK_pin,
processing_system7_0_M_AXI_GP1_ARSIZE_pin,
processing_system7_0_M_AXI_GP1_AWBURST_pin,
processing_system7_0_M_AXI_GP1_AWLOCK_pin,
processing_system7_0_M_AXI_GP1_AWSIZE_pin,
processing_system7_0_M_AXI_GP1_ARPROT_pin,
processing_system7_0_M_AXI_GP1_AWPROT_pin,
processing_system7_0_M_AXI_GP1_ARADDR_pin,
processing_system7_0_M_AXI_GP1_AWADDR_pin,
processing_system7_0_M_AXI_GP1_WDATA_pin,
processing_system7_0_M_AXI_GP1_ARCACHE_pin,
processing_system7_0_M_AXI_GP1_ARLEN_pin,
processing_system7_0_M_AXI_GP1_ARQOS_pin,
processing_system7_0_M_AXI_GP1_AWCACHE_pin,
processing_system7_0_M_AXI_GP1_AWLEN_pin,
processing_system7_0_M_AXI_GP1_AWQOS_pin,
processing_system7_0_M_AXI_GP1_WSTRB_pin,
processing_system7_0_M_AXI_GP1_ACLK_pin,
processing_system7_0_M_AXI_GP1_ARREADY_pin,
processing_system7_0_M_AXI_GP1_AWREADY_pin,
processing_system7_0_M_AXI_GP1_BVALID_pin,
processing_system7_0_M_AXI_GP1_RLAST_pin,
processing_system7_0_M_AXI_GP1_RVALID_pin,
processing_system7_0_M_AXI_GP1_WREADY_pin,
processing_system7_0_M_AXI_GP1_BID_pin,
processing_system7_0_M_AXI_GP1_RID_pin,
processing_system7_0_M_AXI_GP1_BRESP_pin,
processing_system7_0_M_AXI_GP1_RRESP_pin,
processing_system7_0_M_AXI_GP1_RDATA_pin,
processing_system7_0_S_AXI_HP1_ARREADY_pin,
processing_system7_0_S_AXI_HP1_AWREADY_pin,
processing_system7_0_S_AXI_HP1_BVALID_pin,
processing_system7_0_S_AXI_HP1_RLAST_pin,
processing_system7_0_S_AXI_HP1_RVALID_pin,
processing_system7_0_S_AXI_HP1_WREADY_pin,
processing_system7_0_S_AXI_HP1_BRESP_pin,
processing_system7_0_S_AXI_HP1_RRESP_pin,
processing_system7_0_S_AXI_HP1_BID_pin,
processing_system7_0_S_AXI_HP1_RID_pin,
processing_system7_0_S_AXI_HP1_RDATA_pin,
processing_system7_0_S_AXI_HP1_ACLK_pin,
processing_system7_0_S_AXI_HP1_ARVALID_pin,
processing_system7_0_S_AXI_HP1_AWVALID_pin,
processing_system7_0_S_AXI_HP1_BREADY_pin,
processing_system7_0_S_AXI_HP1_RREADY_pin,
processing_system7_0_S_AXI_HP1_WLAST_pin,
processing_system7_0_S_AXI_HP1_WVALID_pin,
processing_system7_0_S_AXI_HP1_ARBURST_pin,
processing_system7_0_S_AXI_HP1_ARLOCK_pin,
processing_system7_0_S_AXI_HP1_ARSIZE_pin,
processing_system7_0_S_AXI_HP1_AWBURST_pin,
processing_system7_0_S_AXI_HP1_AWLOCK_pin,
processing_system7_0_S_AXI_HP1_AWSIZE_pin,
processing_system7_0_S_AXI_HP1_ARPROT_pin,
processing_system7_0_S_AXI_HP1_AWPROT_pin,
processing_system7_0_S_AXI_HP1_ARADDR_pin,
processing_system7_0_S_AXI_HP1_AWADDR_pin,
processing_system7_0_S_AXI_HP1_ARCACHE_pin,
processing_system7_0_S_AXI_HP1_ARLEN_pin,
processing_system7_0_S_AXI_HP1_ARQOS_pin,
processing_system7_0_S_AXI_HP1_AWCACHE_pin,
processing_system7_0_S_AXI_HP1_AWLEN_pin,
processing_system7_0_S_AXI_HP1_AWQOS_pin,
processing_system7_0_S_AXI_HP1_ARID_pin,
processing_system7_0_S_AXI_HP1_AWID_pin,
processing_system7_0_S_AXI_HP1_WID_pin,
processing_system7_0_S_AXI_HP1_WDATA_pin,
processing_system7_0_S_AXI_HP1_WSTRB_pin,
processing_system7_0_I2C0_SDA_I_pin,
processing_system7_0_I2C0_SDA_O_pin,
processing_system7_0_I2C0_SDA_T_pin,
processing_system7_0_I2C0_SCL_I_pin,
processing_system7_0_I2C0_SCL_O_pin,
processing_system7_0_I2C0_SCL_T_pin,
processing_system7_0_GPIO_I_pin,
processing_system7_0_GPIO_O_pin,
processing_system7_0_GPIO_T_pin
);
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB_pin;
input processing_system7_0_PS_CLK_pin;
input processing_system7_0_PS_PORB_pin;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB_pin;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
output processing_system7_0_M_AXI_GP1_ARESETN_pin;
output processing_system7_0_S_AXI_HP1_ARESETN_pin;
output processing_system7_0_FCLK_CLK3_pin;
output processing_system7_0_FCLK_CLK0_pin;
output processing_system7_0_M_AXI_GP1_ARVALID_pin;
output processing_system7_0_M_AXI_GP1_AWVALID_pin;
output processing_system7_0_M_AXI_GP1_BREADY_pin;
output processing_system7_0_M_AXI_GP1_RREADY_pin;
output processing_system7_0_M_AXI_GP1_WLAST_pin;
output processing_system7_0_M_AXI_GP1_WVALID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_ARID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_AWID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_WID_pin;
output [1:0] processing_system7_0_M_AXI_GP1_ARBURST_pin;
output [1:0] processing_system7_0_M_AXI_GP1_ARLOCK_pin;
output [2:0] processing_system7_0_M_AXI_GP1_ARSIZE_pin;
output [1:0] processing_system7_0_M_AXI_GP1_AWBURST_pin;
output [1:0] processing_system7_0_M_AXI_GP1_AWLOCK_pin;
output [2:0] processing_system7_0_M_AXI_GP1_AWSIZE_pin;
output [2:0] processing_system7_0_M_AXI_GP1_ARPROT_pin;
output [2:0] processing_system7_0_M_AXI_GP1_AWPROT_pin;
output [31:0] processing_system7_0_M_AXI_GP1_ARADDR_pin;
output [31:0] processing_system7_0_M_AXI_GP1_AWADDR_pin;
output [31:0] processing_system7_0_M_AXI_GP1_WDATA_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARCACHE_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARLEN_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARQOS_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWCACHE_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWLEN_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWQOS_pin;
output [3:0] processing_system7_0_M_AXI_GP1_WSTRB_pin;
input processing_system7_0_M_AXI_GP1_ACLK_pin;
input processing_system7_0_M_AXI_GP1_ARREADY_pin;
input processing_system7_0_M_AXI_GP1_AWREADY_pin;
input processing_system7_0_M_AXI_GP1_BVALID_pin;
input processing_system7_0_M_AXI_GP1_RLAST_pin;
input processing_system7_0_M_AXI_GP1_RVALID_pin;
input processing_system7_0_M_AXI_GP1_WREADY_pin;
input [11:0] processing_system7_0_M_AXI_GP1_BID_pin;
input [11:0] processing_system7_0_M_AXI_GP1_RID_pin;
input [1:0] processing_system7_0_M_AXI_GP1_BRESP_pin;
input [1:0] processing_system7_0_M_AXI_GP1_RRESP_pin;
input [31:0] processing_system7_0_M_AXI_GP1_RDATA_pin;
output processing_system7_0_S_AXI_HP1_ARREADY_pin;
output processing_system7_0_S_AXI_HP1_AWREADY_pin;
output processing_system7_0_S_AXI_HP1_BVALID_pin;
output processing_system7_0_S_AXI_HP1_RLAST_pin;
output processing_system7_0_S_AXI_HP1_RVALID_pin;
output processing_system7_0_S_AXI_HP1_WREADY_pin;
output [1:0] processing_system7_0_S_AXI_HP1_BRESP_pin;
output [1:0] processing_system7_0_S_AXI_HP1_RRESP_pin;
output [5:0] processing_system7_0_S_AXI_HP1_BID_pin;
output [5:0] processing_system7_0_S_AXI_HP1_RID_pin;
output [63:0] processing_system7_0_S_AXI_HP1_RDATA_pin;
input processing_system7_0_S_AXI_HP1_ACLK_pin;
input processing_system7_0_S_AXI_HP1_ARVALID_pin;
input processing_system7_0_S_AXI_HP1_AWVALID_pin;
input processing_system7_0_S_AXI_HP1_BREADY_pin;
input processing_system7_0_S_AXI_HP1_RREADY_pin;
input processing_system7_0_S_AXI_HP1_WLAST_pin;
input processing_system7_0_S_AXI_HP1_WVALID_pin;
input [1:0] processing_system7_0_S_AXI_HP1_ARBURST_pin;
input [1:0] processing_system7_0_S_AXI_HP1_ARLOCK_pin;
input [2:0] processing_system7_0_S_AXI_HP1_ARSIZE_pin;
input [1:0] processing_system7_0_S_AXI_HP1_AWBURST_pin;
input [1:0] processing_system7_0_S_AXI_HP1_AWLOCK_pin;
input [2:0] processing_system7_0_S_AXI_HP1_AWSIZE_pin;
input [2:0] processing_system7_0_S_AXI_HP1_ARPROT_pin;
input [2:0] processing_system7_0_S_AXI_HP1_AWPROT_pin;
input [31:0] processing_system7_0_S_AXI_HP1_ARADDR_pin;
input [31:0] processing_system7_0_S_AXI_HP1_AWADDR_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARCACHE_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARLEN_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARQOS_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWCACHE_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWLEN_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWQOS_pin;
input [5:0] processing_system7_0_S_AXI_HP1_ARID_pin;
input [5:0] processing_system7_0_S_AXI_HP1_AWID_pin;
input [5:0] processing_system7_0_S_AXI_HP1_WID_pin;
input [63:0] processing_system7_0_S_AXI_HP1_WDATA_pin;
input [7:0] processing_system7_0_S_AXI_HP1_WSTRB_pin;
input processing_system7_0_I2C0_SDA_I_pin;
output processing_system7_0_I2C0_SDA_O_pin;
output processing_system7_0_I2C0_SDA_T_pin;
input processing_system7_0_I2C0_SCL_I_pin;
output processing_system7_0_I2C0_SCL_O_pin;
output processing_system7_0_I2C0_SCL_T_pin;
input [47:0] processing_system7_0_GPIO_I_pin;
output [47:0] processing_system7_0_GPIO_O_pin;
output [47:0] processing_system7_0_GPIO_T_pin;
(* BOX_TYPE = "user_black_box" *)
system
system_i (
.processing_system7_0_MIO ( processing_system7_0_MIO ),
.processing_system7_0_PS_SRSTB_pin ( processing_system7_0_PS_SRSTB_pin ),
.processing_system7_0_PS_CLK_pin ( processing_system7_0_PS_CLK_pin ),
.processing_system7_0_PS_PORB_pin ( processing_system7_0_PS_PORB_pin ),
.processing_system7_0_DDR_Clk ( processing_system7_0_DDR_Clk ),
.processing_system7_0_DDR_Clk_n ( processing_system7_0_DDR_Clk_n ),
.processing_system7_0_DDR_CKE ( processing_system7_0_DDR_CKE ),
.processing_system7_0_DDR_CS_n ( processing_system7_0_DDR_CS_n ),
.processing_system7_0_DDR_RAS_n ( processing_system7_0_DDR_RAS_n ),
.processing_system7_0_DDR_CAS_n ( processing_system7_0_DDR_CAS_n ),
.processing_system7_0_DDR_WEB_pin ( processing_system7_0_DDR_WEB_pin ),
.processing_system7_0_DDR_BankAddr ( processing_system7_0_DDR_BankAddr ),
.processing_system7_0_DDR_Addr ( processing_system7_0_DDR_Addr ),
.processing_system7_0_DDR_ODT ( processing_system7_0_DDR_ODT ),
.processing_system7_0_DDR_DRSTB ( processing_system7_0_DDR_DRSTB ),
.processing_system7_0_DDR_DQ ( processing_system7_0_DDR_DQ ),
.processing_system7_0_DDR_DM ( processing_system7_0_DDR_DM ),
.processing_system7_0_DDR_DQS ( processing_system7_0_DDR_DQS ),
.processing_system7_0_DDR_DQS_n ( processing_system7_0_DDR_DQS_n ),
.processing_system7_0_DDR_VRN ( processing_system7_0_DDR_VRN ),
.processing_system7_0_DDR_VRP ( processing_system7_0_DDR_VRP ),
.processing_system7_0_M_AXI_GP1_ARESETN_pin ( processing_system7_0_M_AXI_GP1_ARESETN_pin ),
.processing_system7_0_S_AXI_HP1_ARESETN_pin ( processing_system7_0_S_AXI_HP1_ARESETN_pin ),
.processing_system7_0_FCLK_CLK3_pin ( processing_system7_0_FCLK_CLK3_pin ),
.processing_system7_0_FCLK_CLK0_pin ( processing_system7_0_FCLK_CLK0_pin ),
.processing_system7_0_M_AXI_GP1_ARVALID_pin ( processing_system7_0_M_AXI_GP1_ARVALID_pin ),
.processing_system7_0_M_AXI_GP1_AWVALID_pin ( processing_system7_0_M_AXI_GP1_AWVALID_pin ),
.processing_system7_0_M_AXI_GP1_BREADY_pin ( processing_system7_0_M_AXI_GP1_BREADY_pin ),
.processing_system7_0_M_AXI_GP1_RREADY_pin ( processing_system7_0_M_AXI_GP1_RREADY_pin ),
.processing_system7_0_M_AXI_GP1_WLAST_pin ( processing_system7_0_M_AXI_GP1_WLAST_pin ),
.processing_system7_0_M_AXI_GP1_WVALID_pin ( processing_system7_0_M_AXI_GP1_WVALID_pin ),
.processing_system7_0_M_AXI_GP1_ARID_pin ( processing_system7_0_M_AXI_GP1_ARID_pin ),
.processing_system7_0_M_AXI_GP1_AWID_pin ( processing_system7_0_M_AXI_GP1_AWID_pin ),
.processing_system7_0_M_AXI_GP1_WID_pin ( processing_system7_0_M_AXI_GP1_WID_pin ),
.processing_system7_0_M_AXI_GP1_ARBURST_pin ( processing_system7_0_M_AXI_GP1_ARBURST_pin ),
.processing_system7_0_M_AXI_GP1_ARLOCK_pin ( processing_system7_0_M_AXI_GP1_ARLOCK_pin ),
.processing_system7_0_M_AXI_GP1_ARSIZE_pin ( processing_system7_0_M_AXI_GP1_ARSIZE_pin ),
.processing_system7_0_M_AXI_GP1_AWBURST_pin ( processing_system7_0_M_AXI_GP1_AWBURST_pin ),
.processing_system7_0_M_AXI_GP1_AWLOCK_pin ( processing_system7_0_M_AXI_GP1_AWLOCK_pin ),
.processing_system7_0_M_AXI_GP1_AWSIZE_pin ( processing_system7_0_M_AXI_GP1_AWSIZE_pin ),
.processing_system7_0_M_AXI_GP1_ARPROT_pin ( processing_system7_0_M_AXI_GP1_ARPROT_pin ),
.processing_system7_0_M_AXI_GP1_AWPROT_pin ( processing_system7_0_M_AXI_GP1_AWPROT_pin ),
.processing_system7_0_M_AXI_GP1_ARADDR_pin ( processing_system7_0_M_AXI_GP1_ARADDR_pin ),
.processing_system7_0_M_AXI_GP1_AWADDR_pin ( processing_system7_0_M_AXI_GP1_AWADDR_pin ),
.processing_system7_0_M_AXI_GP1_WDATA_pin ( processing_system7_0_M_AXI_GP1_WDATA_pin ),
.processing_system7_0_M_AXI_GP1_ARCACHE_pin ( processing_system7_0_M_AXI_GP1_ARCACHE_pin ),
.processing_system7_0_M_AXI_GP1_ARLEN_pin ( processing_system7_0_M_AXI_GP1_ARLEN_pin ),
.processing_system7_0_M_AXI_GP1_ARQOS_pin ( processing_system7_0_M_AXI_GP1_ARQOS_pin ),
.processing_system7_0_M_AXI_GP1_AWCACHE_pin ( processing_system7_0_M_AXI_GP1_AWCACHE_pin ),
.processing_system7_0_M_AXI_GP1_AWLEN_pin ( processing_system7_0_M_AXI_GP1_AWLEN_pin ),
.processing_system7_0_M_AXI_GP1_AWQOS_pin ( processing_system7_0_M_AXI_GP1_AWQOS_pin ),
.processing_system7_0_M_AXI_GP1_WSTRB_pin ( processing_system7_0_M_AXI_GP1_WSTRB_pin ),
.processing_system7_0_M_AXI_GP1_ACLK_pin ( processing_system7_0_M_AXI_GP1_ACLK_pin ),
.processing_system7_0_M_AXI_GP1_ARREADY_pin ( processing_system7_0_M_AXI_GP1_ARREADY_pin ),
.processing_system7_0_M_AXI_GP1_AWREADY_pin ( processing_system7_0_M_AXI_GP1_AWREADY_pin ),
.processing_system7_0_M_AXI_GP1_BVALID_pin ( processing_system7_0_M_AXI_GP1_BVALID_pin ),
.processing_system7_0_M_AXI_GP1_RLAST_pin ( processing_system7_0_M_AXI_GP1_RLAST_pin ),
.processing_system7_0_M_AXI_GP1_RVALID_pin ( processing_system7_0_M_AXI_GP1_RVALID_pin ),
.processing_system7_0_M_AXI_GP1_WREADY_pin ( processing_system7_0_M_AXI_GP1_WREADY_pin ),
.processing_system7_0_M_AXI_GP1_BID_pin ( processing_system7_0_M_AXI_GP1_BID_pin ),
.processing_system7_0_M_AXI_GP1_RID_pin ( processing_system7_0_M_AXI_GP1_RID_pin ),
.processing_system7_0_M_AXI_GP1_BRESP_pin ( processing_system7_0_M_AXI_GP1_BRESP_pin ),
.processing_system7_0_M_AXI_GP1_RRESP_pin ( processing_system7_0_M_AXI_GP1_RRESP_pin ),
.processing_system7_0_M_AXI_GP1_RDATA_pin ( processing_system7_0_M_AXI_GP1_RDATA_pin ),
.processing_system7_0_S_AXI_HP1_ARREADY_pin ( processing_system7_0_S_AXI_HP1_ARREADY_pin ),
.processing_system7_0_S_AXI_HP1_AWREADY_pin ( processing_system7_0_S_AXI_HP1_AWREADY_pin ),
.processing_system7_0_S_AXI_HP1_BVALID_pin ( processing_system7_0_S_AXI_HP1_BVALID_pin ),
.processing_system7_0_S_AXI_HP1_RLAST_pin ( processing_system7_0_S_AXI_HP1_RLAST_pin ),
.processing_system7_0_S_AXI_HP1_RVALID_pin ( processing_system7_0_S_AXI_HP1_RVALID_pin ),
.processing_system7_0_S_AXI_HP1_WREADY_pin ( processing_system7_0_S_AXI_HP1_WREADY_pin ),
.processing_system7_0_S_AXI_HP1_BRESP_pin ( processing_system7_0_S_AXI_HP1_BRESP_pin ),
.processing_system7_0_S_AXI_HP1_RRESP_pin ( processing_system7_0_S_AXI_HP1_RRESP_pin ),
.processing_system7_0_S_AXI_HP1_BID_pin ( processing_system7_0_S_AXI_HP1_BID_pin ),
.processing_system7_0_S_AXI_HP1_RID_pin ( processing_system7_0_S_AXI_HP1_RID_pin ),
.processing_system7_0_S_AXI_HP1_RDATA_pin ( processing_system7_0_S_AXI_HP1_RDATA_pin ),
.processing_system7_0_S_AXI_HP1_ACLK_pin ( processing_system7_0_S_AXI_HP1_ACLK_pin ),
.processing_system7_0_S_AXI_HP1_ARVALID_pin ( processing_system7_0_S_AXI_HP1_ARVALID_pin ),
.processing_system7_0_S_AXI_HP1_AWVALID_pin ( processing_system7_0_S_AXI_HP1_AWVALID_pin ),
.processing_system7_0_S_AXI_HP1_BREADY_pin ( processing_system7_0_S_AXI_HP1_BREADY_pin ),
.processing_system7_0_S_AXI_HP1_RREADY_pin ( processing_system7_0_S_AXI_HP1_RREADY_pin ),
.processing_system7_0_S_AXI_HP1_WLAST_pin ( processing_system7_0_S_AXI_HP1_WLAST_pin ),
.processing_system7_0_S_AXI_HP1_WVALID_pin ( processing_system7_0_S_AXI_HP1_WVALID_pin ),
.processing_system7_0_S_AXI_HP1_ARBURST_pin ( processing_system7_0_S_AXI_HP1_ARBURST_pin ),
.processing_system7_0_S_AXI_HP1_ARLOCK_pin ( processing_system7_0_S_AXI_HP1_ARLOCK_pin ),
.processing_system7_0_S_AXI_HP1_ARSIZE_pin ( processing_system7_0_S_AXI_HP1_ARSIZE_pin ),
.processing_system7_0_S_AXI_HP1_AWBURST_pin ( processing_system7_0_S_AXI_HP1_AWBURST_pin ),
.processing_system7_0_S_AXI_HP1_AWLOCK_pin ( processing_system7_0_S_AXI_HP1_AWLOCK_pin ),
.processing_system7_0_S_AXI_HP1_AWSIZE_pin ( processing_system7_0_S_AXI_HP1_AWSIZE_pin ),
.processing_system7_0_S_AXI_HP1_ARPROT_pin ( processing_system7_0_S_AXI_HP1_ARPROT_pin ),
.processing_system7_0_S_AXI_HP1_AWPROT_pin ( processing_system7_0_S_AXI_HP1_AWPROT_pin ),
.processing_system7_0_S_AXI_HP1_ARADDR_pin ( processing_system7_0_S_AXI_HP1_ARADDR_pin ),
.processing_system7_0_S_AXI_HP1_AWADDR_pin ( processing_system7_0_S_AXI_HP1_AWADDR_pin ),
.processing_system7_0_S_AXI_HP1_ARCACHE_pin ( processing_system7_0_S_AXI_HP1_ARCACHE_pin ),
.processing_system7_0_S_AXI_HP1_ARLEN_pin ( processing_system7_0_S_AXI_HP1_ARLEN_pin ),
.processing_system7_0_S_AXI_HP1_ARQOS_pin ( processing_system7_0_S_AXI_HP1_ARQOS_pin ),
.processing_system7_0_S_AXI_HP1_AWCACHE_pin ( processing_system7_0_S_AXI_HP1_AWCACHE_pin ),
.processing_system7_0_S_AXI_HP1_AWLEN_pin ( processing_system7_0_S_AXI_HP1_AWLEN_pin ),
.processing_system7_0_S_AXI_HP1_AWQOS_pin ( processing_system7_0_S_AXI_HP1_AWQOS_pin ),
.processing_system7_0_S_AXI_HP1_ARID_pin ( processing_system7_0_S_AXI_HP1_ARID_pin ),
.processing_system7_0_S_AXI_HP1_AWID_pin ( processing_system7_0_S_AXI_HP1_AWID_pin ),
.processing_system7_0_S_AXI_HP1_WID_pin ( processing_system7_0_S_AXI_HP1_WID_pin ),
.processing_system7_0_S_AXI_HP1_WDATA_pin ( processing_system7_0_S_AXI_HP1_WDATA_pin ),
.processing_system7_0_S_AXI_HP1_WSTRB_pin ( processing_system7_0_S_AXI_HP1_WSTRB_pin ),
.processing_system7_0_I2C0_SDA_I_pin ( processing_system7_0_I2C0_SDA_I_pin ),
.processing_system7_0_I2C0_SDA_O_pin ( processing_system7_0_I2C0_SDA_O_pin ),
.processing_system7_0_I2C0_SDA_T_pin ( processing_system7_0_I2C0_SDA_T_pin ),
.processing_system7_0_I2C0_SCL_I_pin ( processing_system7_0_I2C0_SCL_I_pin ),
.processing_system7_0_I2C0_SCL_O_pin ( processing_system7_0_I2C0_SCL_O_pin ),
.processing_system7_0_I2C0_SCL_T_pin ( processing_system7_0_I2C0_SCL_T_pin ),
.processing_system7_0_GPIO_I_pin ( processing_system7_0_GPIO_I_pin ),
.processing_system7_0_GPIO_O_pin ( processing_system7_0_GPIO_O_pin ),
.processing_system7_0_GPIO_T_pin ( processing_system7_0_GPIO_T_pin )
);
endmodule
|
/*
* Check the basic parsing and that the errors are caught.
*/
// A global timeunit and timeprecision are OK
timeunit 100us;
timeprecision 1us;
/*
* Check the various timeunit/precision combinations (this is valid SV syntax).
*/
// A local time unit is OK.
module check_tu;
timeunit 10us;
endmodule
// A local time precision is OK.
module check_tp;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK.
module check_tup;
timeunit 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK (check both orders).
module check_tpu;
timeprecision 10us;
timeunit 10us;
endmodule
/*
* Now do the same with repeat declarations (this is valid SV syntax).
*/
// A local time unit is OK.
module check_tu_d;
timeunit 10us;
timeunit 10us;
endmodule
// A local time precision is OK.
module check_tp_d;
timeprecision 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK.
module check_tup_d;
timeunit 10us;
timeprecision 10us;
timeunit 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK (check both orders).
module check_tpu_d;
timeprecision 10us;
timeunit 10us;
timeprecision 10us;
timeunit 10us;
endmodule
// It is OK to redefine the global time unit and precision.
timeunit 100us;
timeprecision 1ns;
/*
* Now test some error conditions.
*/
// A local time unit is OK, but a repeat must match.
module check_tu_d_e;
timeunit 10us;
timeunit 1us;
endmodule
// A local time precision is OK, but a repeat must match.
module check_tp_d_e;
timeprecision 10us;
timeprecision 1us;
endmodule
// A repeat time unit is only allowed if an initial one is given.
module check_tu_m_e;
integer foo;
timeunit 10us;
endmodule
// A repeat time precision is only allowed if an initial one is given.
module check_tp_m_e;
integer foo;
timeprecision 10us;
endmodule
// A local time unit is OK and a repeat is OK, but this is not a prec decl.
module check_tup_d_e;
timeunit 10us;
timeunit 10us;
timeprecision 1us;
endmodule
// A local time prec is OK and a repeat is OK, but this is not a unit decl.
module check_tpu_d_e;
timeprecision 1us;
timeprecision 1us;
timeunit 10us;
endmodule
// Check all the valid timeunit and time precision values.
timeunit 100s;
timeprecision 100s;
timeunit 10s;
timeprecision 10s;
timeunit 1s;
timeprecision 1s;
timeunit 100ms;
timeprecision 100ms;
timeunit 10ms;
timeprecision 10ms;
timeunit 1ms;
timeprecision 1ms;
timeunit 100us;
timeprecision 100us;
timeunit 10us;
timeprecision 10us;
timeunit 1us;
timeprecision 1us;
timeunit 100ns;
timeprecision 100ns;
timeunit 10ns;
timeprecision 10ns;
timeunit 1ns;
timeprecision 1ns;
timeunit 100ps;
timeprecision 100ps;
timeunit 10ps;
timeprecision 10ps;
timeunit 1ps;
timeprecision 1ps;
timeunit 100fs;
timeprecision 100fs;
timeunit 10fs;
timeprecision 10fs;
timeunit 1fs;
timeprecision 1fs;
/* Check some invalid values */
// Only a power of 10 is allowed.
timeunit 200s;
timeprecision 200s;
// Too many zeros (only allow 0 - 2).
timeunit 1000s;
timeprecision 1000s;
// This actually trips as an invalid scale of '2s'.
timeunit 12s;
timeprecision 12s;
// This needs to be checked. The base time_literal supports this, but
// for now timeunit/precision code does not.
timeunit 1_0s;
timeprecision 1_0s;
/* This fails because we have not defined a timeprecision or it is too large. */
// Check a missing global time precision.
`resetall
timeunit 1ns;
module no_gtp;
endmodule
// Check a global timeprecision that is too large.
`resetall
timeunit 1ns;
timeprecision 10ns;
module gtp_large;
endmodule
// Check a missing local time precision.
`resetall
module no_ltp;
timeunit 1ns;
endmodule
// Check a local timeprecision that is too large.
`resetall
module ltp_large;
timeunit 1ns;
timeprecision 10ns;
endmodule
/* These should work since both the unit and precision are defined
* before we have any module items. */
// A global timeprecision and local time units.
`resetall
timeprecision 10ps;
module gtp_ltu1;
timeunit 1ns;
endmodule
module gtp_ltu2;
timeunit 1us;
endmodule
// A global timeunit and local time precision.
`resetall
timeunit 1ns;
module gtu_ltp1;
timeprecision 10ps;
endmodule
module gtu_ltp2;
timeprecision 1ns;
endmodule
|
`timescale 1ns/10ps
`define CLK_PERIOD 4.0
module PATTERN(
output reg clk,
output reg [2:0] circle1,
output reg [2:0] circle2,
output reg [4:0] in,
output reg in_valid,
output reg rst_n,
input [5:0] out,
input out_valid
);
reg [4:0] pixel1 [0:7];
reg [4:0] pixel2 [0:7];
parameter CLK = `CLK_PERIOD;
parameter PATTERN_NUM = 10;
integer latency, total_latency;
integer pattern_num;
integer round;
integer i,j;
integer op;
integer ans[0:7];
integer unsort[0:7];
integer swap;
integer cir1, cir2;
initial begin
total_latency = 0;
end
initial begin
clk = 0;
forever #CLK clk = ~clk;
end
initial begin
in <= 'dx;
in_valid <= 'bx;
rst_n <= 1'b1;
#16;
rst_n <= 1'b0;
#8;
rst_n <= 1'b1;
check_out_rst;
check_out_valid_rst;
in_valid <= 'b0;
#16
@(negedge clk);
for(pattern_num=0;pattern_num<PATTERN_NUM;pattern_num=pattern_num+1) begin
check_out_valid_rst;
if(pattern_num === 0) begin
cir1 = 0;
cir2 = 0;
pixel1[0] = 31; pixel1[1] = 31; pixel1[2] = 31; pixel1[3] = 31; pixel1[4] = 31; pixel1[5] = 31; pixel1[6] = 31; pixel1[7] = 31;
pixel2[0] = 31; pixel2[1] = 31; pixel2[2] = 31; pixel2[3] = 31; pixel2[4] = 31; pixel2[5] = 31; pixel2[6] = 31; pixel2[7] = 31;
end else if(pattern_num === 2) begin
cir1 = 0;
cir2 = 0;
pixel1[0] = 0; pixel1[1] = 1; pixel1[2] = 2; pixel1[3] = 3; pixel1[4] = 4; pixel1[5] = 5; pixel1[6] = 6; pixel1[7] = 7;
pixel2[0] = 0; pixel2[1] = 1; pixel2[2] = 2; pixel2[3] = 3; pixel2[4] = 4; pixel2[5] = 5; pixel2[6] = 6; pixel2[7] = 7;
end else begin
cir1 = {$random()}%8;
cir2 = {$random()}%8;
for(i=0;i<8;i=i+1) begin
pixel1[i] = $random()%32;
pixel2[i] = $random()%32;
end
end
for(i=0;i<8;i=i+1) begin
if(i == 0) begin circle1 <= cir1; circle2 <= cir2; end
else begin circle1 <= 1'bx; circle2 <= 1'bx; end
in_valid <= 1'b1;
in <= pixel1[i];
check_out_valid_rst;
@(negedge clk);
end
for(i=0;i<8;i=i+1) begin
in_valid <= 1'b1;
in <= pixel2[i];
check_out_valid_rst;
@(negedge clk);
end
operate;
in <= 'dx;
in_valid = 1'b0;
wait_out;
for(i=0;i<8;i=i+1) begin
if(out !== ans[i]) begin
$display("");
$display("=================================================");
$display(" Failed!! PATTERN %4d is wrong! ", pattern_num+1);
$display(" ans is %d your ans is %d ", ans[i],out);
$display("=================================================");
$display("");
repeat(8)@(negedge clk);
$finish;
end
@(negedge clk);
end
$display("");
$display(" Pass pattern %3d ", pattern_num+1);
check_out_valid_rst;
@(negedge clk);
end
@(negedge clk);
$display ("--------------------------------------------------------------------");
$display (" Congratulations ! ");
$display (" You have passed all patterns ! ");
$display (" Your total latency is %6d ! ", total_latency);
$display ("--------------------------------------------------------------------");
@(negedge clk);
$finish;
end
task check_out_valid_rst;
begin
if(out_valid !== 1'b0) begin
$display("");
$display("========================================");
$display(" 'out_valid' should be reset !!!!! ");
$display("========================================");
$display("");
@(negedge clk);
$finish;
end
end
endtask
task check_out_rst;
begin
if(out !== 1'b0) begin
$display("");
$display("========================================");
$display(" 'out' should be reset !!!!! ");
$display("========================================");
$display("");
@(negedge clk);
$finish;
end
end
endtask
task wait_out;
begin
latency = 0;
while(!(out_valid === 1'b1)) begin
if(latency > 100) begin
$display("");
$display("========================================");
$display(" Latency too mord !!!! ");
$display("========================================");
$display("");
@(negedge clk);
$finish;
end
latency = latency + 1;
total_latency = total_latency + 1;
@(negedge clk);
end
end
endtask
task operate;
begin
op = cir1 - cir2;
for(i=0;i<8;i=i+1) begin
while(i+op<0) op=op+8;
while(i+op>7) op=op-8;
ans[i] = pixel1[i] + pixel2[i+op];
unsort[i] = pixel1[i] + pixel2[i+op];
end
for(i=0;i<8;i=i+1) begin
for(j=0;j<7;j=j+1) begin
if(ans[j]>ans[j+1]) begin
swap = ans[j];
ans[j] = ans[j+1];
ans[j+1] = swap;
end
end
end
end
endtask
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] q; // From test of Test.v
// End of automatics
Test test (
// Outputs
.q (q[2:0]),
// Inputs
.clk (clk),
.reset_l (crc[0]),
.enable (crc[2]),
.q_var0 (crc[19:10]),
.q_var2 (crc[29:20]),
.q_var4 (crc[39:30]),
.q_var6 (crc[49:40])
/*AUTOINST*/);
// Aggregate outputs into a single result vector
wire [63:0] result = {61'h0,q};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h58b162c58d6e35ba
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
input clk,
input reset_l,
input enable,
input [ 9:0] q_var0,
input [ 9:0] q_var2,
input [ 9:0] q_var4,
input [ 9:0] q_var6,
output reg [2:0] q
);
reg [7:0] p1_r [6:0];
always @(posedge clk) begin
if (!reset_l) begin
p1_r[0] <= 'b0;
p1_r[1] <= 'b0;
p1_r[2] <= 'b0;
p1_r[3] <= 'b0;
p1_r[4] <= 'b0;
p1_r[5] <= 'b0;
p1_r[6] <= 'b0;
end
else if (enable) begin : pass1
match(q_var0, q_var2, q_var4, q_var6);
end
end
// verilator lint_off WIDTH
always @(posedge clk) begin : l
reg [10:0] bd;
reg [3:0] idx;
q = 0;
bd = 0;
for (idx=0; idx<7; idx=idx+1) begin
q = idx+1;
bd = bd + p1_r[idx];
end
end
task match;
input [9:0] p0, p1, p2, p3;
reg [9:0] p[3:0];
begin
p[0] = p0;
p[1] = p1;
p[2] = p2;
p[3] = p3;
p1_r[0] <= p[0];
p1_r[1] <= p[1];
end
endtask
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_2clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Dual clocks, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module ram_2clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLKA,
input CLKB,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
//Local parameters
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLKA) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
end
always @(posedge CLKB) begin
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
tpub p1 (.clk(clk), .i(32'd1));
tpub p2 (.clk(clk), .i(32'd2));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
$c("this->publicTop();");
`endif
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task publicTop;
// verilator public
// We have different optimizations if only one of something, so try it out.
$write("Hello in publicTop\n");
endtask
task test_task(input [19:0] in [2], output [19:0] out [2]);
// Issue 3316
// verilator public
out[0] = in[1];
out[1] = in[0];
endtask
endmodule
module tpub (
input clk,
input [31:0] i);
reg [23:0] var_long;
reg [59:0] var_quad;
reg [71:0] var_wide;
reg var_bool;
// verilator lint_off BLKANDNBLK
reg [11:0] var_flop;
// verilator lint_on BLKANDNBLK
reg [23:0] got_long /*verilator public*/;
reg [59:0] got_quad /*verilator public*/;
reg [71:0] got_wide /*verilator public*/;
reg got_bool /*verilator public*/;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
// cyc==1 is in top level
if (cyc==2) begin
publicNoArgs;
publicSetBool(1'b1);
publicSetLong(24'habca);
publicSetQuad(60'h4444_3333_2222);
publicSetWide(72'h12_5678_9123_1245_2352);
var_flop <= 12'habe;
end
if (cyc==3) begin
if (1'b1 != publicGetSetBool(1'b0)) $stop;
if (24'habca != publicGetSetLong(24'h1234)) $stop;
if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop;
if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop;
end
if (cyc==4) begin
publicGetBool(got_bool);
if (1'b0 != got_bool) $stop;
publicGetLong(got_long);
if (24'h1234 != got_long) $stop;
publicGetQuad(got_quad);
if (60'h123_4567_89ab != got_quad) $stop;
publicGetWide(got_wide);
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
end
//
`ifdef VERILATOR_PUBLIC_TASKS
if (cyc==11) begin
$c("this->publicNoArgs();");
$c("this->publicSetBool(true);");
$c("this->publicSetLong(0x11bca);");
$c("this->publicSetQuad(0x66655554444ULL);");
$c("this->publicSetFlop(0x321);");
//Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);");
end
if (cyc==12) begin
$c("this->got_bool = this->publicGetSetBool(true);");
$c("this->got_long = this->publicGetSetLong(0x11bca);");
$c("this->got_quad = this->publicGetSetQuad(0xaaaabbbbccccULL);");
end
if (cyc==13) begin
$c("{ bool gb; this->publicGetBool(gb); this->got_bool=gb; }");
if (1'b1 != got_bool) $stop;
$c("this->publicGetLong(this->got_long);");
if (24'h11bca != got_long) $stop;
$c("{ uint64_t qq; this->publicGetQuad(qq); this->got_quad=qq; }");
if (60'haaaa_bbbb_cccc != got_quad) $stop;
$c("{ WData gw[3]; this->publicGetWide(gw); VL_ASSIGN_W(72,this->got_wide,gw); }");
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
//Below doesn't work, because we're calling it inside the loop that sets var_flop
// if (12'h321 != var_flop) $stop;
end
if (cyc==14) begin
if ($c32("this->publicInstNum()") != i) $stop;
end
`endif
end
end
task publicEmpty;
// verilator public
begin end
endtask
task publicNoArgs;
// verilator public
$write("Hello in publicNoArgs\n");
endtask
task publicSetBool;
// verilator public
input in_bool;
var_bool = in_bool;
endtask
task publicSetLong;
// verilator public
input [23:0] in_long;
reg [23:0] not_long;
begin
not_long = ~in_long; // Test that we can have local variables
var_long = ~not_long;
end
endtask
task publicSetQuad;
// verilator public
input [59:0] in_quad;
var_quad = in_quad;
endtask
task publicSetFlop;
// verilator public
input [11:0] in_flop;
var_flop = in_flop;
endtask
task publicSetWide;
// verilator public
input [71:0] in_wide;
var_wide = in_wide;
endtask
task publicGetBool;
// verilator public
output out_bool;
out_bool = var_bool;
endtask
task publicGetLong;
// verilator public
output [23:0] out_long;
out_long = var_long;
endtask
task publicGetQuad;
// verilator public
output [59:0] out_quad;
out_quad = var_quad;
endtask
task publicGetWide;
// verilator public
output [71:0] out_wide;
out_wide = var_wide;
endtask
function publicGetSetBool;
// verilator public
input in_bool;
begin
publicGetSetBool = var_bool;
var_bool = in_bool;
end
endfunction
function [23:0] publicGetSetLong;
// verilator public
input [23:0] in_long;
begin
publicGetSetLong = var_long;
var_long = in_long;
end
endfunction
function [59:0] publicGetSetQuad;
// verilator public
input [59:0] in_quad;
begin
publicGetSetQuad = var_quad;
var_quad = in_quad;
end
endfunction
function [71:0] publicGetSetWide;
// Can't be public, as no wide return types in C++
input [71:0] in_wide;
begin
publicGetSetWide = var_wide;
var_wide = in_wide;
end
endfunction
`ifdef VERILATOR_PUBLIC_TASKS
function [31:0] publicInstNum;
// verilator public
publicInstNum = i;
endfunction
`endif
endmodule
|
// $Id: whr_crossbar_mac.v 1556 2009-09-22 22:52:47Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// configurable crossbar module for wormhole router
module whr_crossbar_mac
(clk, reset, ctrl_op_ip, data_in_ip, data_out_op);
`include "c_constants.v"
// number of input/output ports
parameter num_in_ports = 5;
parameter num_out_ports = 5;
// width per port
parameter width = 32;
// select implementation variant
parameter crossbar_type = `CROSSBAR_TYPE_MUX;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// incoming control signals (request matrix)
input [0:num_in_ports*num_out_ports-1] ctrl_op_ip;
// vector of input data
input [0:num_in_ports*width-1] data_in_ip;
// vector of output data
output [0:num_out_ports*width-1] data_out_op;
wire [0:num_out_ports*width-1] data_out_op;
wire [0:num_out_ports*num_in_ports-1] ctrl_op_ip_s, ctrl_op_ip_q;
assign ctrl_op_ip_s = ctrl_op_ip;
c_dff
#(.width(num_out_ports*num_in_ports),
.reset_type(reset_type))
ctrl_op_ipq
(.clk(clk),
.reset(reset),
.d(ctrl_op_ip_s),
.q(ctrl_op_ip_q));
wire [0:num_in_ports*num_out_ports-1] ctrl_ip_op_q;
c_interleaver
#(.width(num_out_ports*num_in_ports),
.num_blocks(num_out_ports))
ctrl_ip_op_q_intl
(.data_in(ctrl_op_ip_q),
.data_out(ctrl_ip_op_q));
c_crossbar
#(.num_in_ports(num_in_ports),
.num_out_ports(num_out_ports),
.width(width),
.crossbar_type(crossbar_type))
xbr
(.ctrl_ip_op(ctrl_ip_op_q),
.data_in_ip(data_in_ip),
.data_out_op(data_out_op));
endmodule
|
module loacal_sw(
input clk,
input reset,
output reg [31:0] data_out,
input [64:0] command,
input command_wr,
output reg ale,
output reg cs_n,
output reg rd_wr,
output reg [31:0] data,
input ack_n_um,
input [31:0] rdata_um
);
reg command_rd;
reg [64:0] command_q_r;
wire [64:0] command_q;
wire command_wr_empty;
reg [7:0] count;
reg [2:0] current_state;
localparam
idle_s = 'd1,
ale_s = 'd2,
cs_s = 'd3,
wait_ack_s = 'd4,
wait_addr_s = 'd5,
wait_addr_s1 = 'd6;
always @(posedge clk or negedge reset)
if(!reset) begin
ale <= 1'b0;
cs_n <= 1'b1;
rd_wr <= 1'b1;
data <= 32'b0;
command_rd <= 1'b0;
command_q_r <= 65'b0;
data_out <= 32'b0;
count <= 8'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
ale <= 1'b0;
cs_n <= 1'b1;
rd_wr <= 1'b1;
count <= 8'b0;
command_rd <= 1'b0;
if(command_wr_empty == 1'b1) begin
current_state <= idle_s;
end
else begin
command_rd <= 1'b1;
command_q_r <= command_q;
data <= command_q[63:32];
rd_wr <= command_q[64]; //0:wr 1:read
current_state <= ale_s;
end
end
ale_s : begin
ale <= 1'b1;
command_rd <= 1'b0;
current_state <= cs_s;
end
cs_s: begin
ale <= 1'b0;
//cs_n <= 1'b0;
//data <= command_q_r[31:0];
current_state <= wait_addr_s;
end
wait_addr_s:begin
current_state <= wait_addr_s1;
end
wait_addr_s1: begin
data <= command_q_r[31:0];
cs_n <= 1'b0;
current_state <= wait_ack_s;
end
wait_ack_s: begin
if(ack_n_um == 1'b0) begin
cs_n <= 1'b0;
data_out <= rdata_um;
current_state <= idle_s;
end
else begin
count <= count + 1'b1;
if(count[7:4] == 4'b1111) begin
current_state <= idle_s;
end
else begin
current_state <= wait_ack_s;
end
end
end
endcase
end
fifo_65_256 command_fifo(//crc check result fifo;
.aclr(!reset),
.clock(clk),
.data(command),
.rdreq(command_rd),
.wrreq(command_wr),
.empty(command_wr_empty),
.q(command_q)
);
endmodule |
//
// Copyright (c) 2002 Stephen Williams
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Binary ~& (nand) operator.
module main;
reg A, B;
reg result1;
wire result2 = A ~& B;
initial
begin
A = 0;
B = 0;
#1 result1 = A ~& B;
if (result1 !== 1'b1) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b1) begin
$display("FAILED");
$finish;
end
A = 1;
#1 result1 = A ~& B;
if (result1 !== 1'b1) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b1) begin
$display("FAILED");
$finish;
end
B = 1;
#1 result1 = A ~& B;
if (result1 !== 1'b0) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b0) begin
$display("FAILED");
$finish;
end
A = 0;
#1 result1 = A ~& B;
if (result1 !== 1'b1) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule // main
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Generates global and local ids for given set of group ids.
// Need one of these for each kernel instance.
module acl_id_iterator
#(
parameter WIDTH = 32 // width of all the counters
)
(
input clock,
input resetn,
input start,
// handshaking with work group dispatcher
input valid_in,
output stall_out,
// handshaking with kernel instance
input stall_in,
output valid_out,
// comes from group dispatcher
input [WIDTH-1:0] group_id_in[2:0],
input [WIDTH-1:0] global_id_base_in[2:0],
// kernel parameters from the higher level
input [WIDTH-1:0] local_size[2:0],
input [WIDTH-1:0] global_size[2:0],
// actual outputs
output [WIDTH-1:0] local_id[2:0],
output [WIDTH-1:0] global_id[2:0],
output [WIDTH-1:0] group_id[2:0]
);
// Storing group id vector and global id offsets vector.
// Global id offsets help work item iterators calculate global
// ids without using multipliers.
localparam FIFO_WIDTH = 2 * 3 * WIDTH;
localparam FIFO_DEPTH = 4;
wire last_in_group;
wire issue = valid_out & !stall_in;
reg just_seen_last_in_group;
wire [WIDTH-1:0] global_id_from_iter[2:0];
reg [WIDTH-1:0] global_id_base[2:0];
// takes one cycle for the work iterm iterator to register
// global_id_base. During that cycle, just use global_id_base
// directly.
wire use_base = just_seen_last_in_group;
assign global_id[0] = use_base ? global_id_base[0] : global_id_from_iter[0];
assign global_id[1] = use_base ? global_id_base[1] : global_id_from_iter[1];
assign global_id[2] = use_base ? global_id_base[2] : global_id_from_iter[2];
// Group ids (and global id offsets) are stored in a fifo.
acl_fifo #(
.DATA_WIDTH(FIFO_WIDTH),
.DEPTH(FIFO_DEPTH)
) group_id_fifo (
.clock(clock),
.resetn(resetn),
.data_in ( {group_id_in[2], group_id_in[1], group_id_in[0],
global_id_base_in[2], global_id_base_in[1], global_id_base_in[0]} ),
.data_out( {group_id[2], group_id[1], group_id[0],
global_id_base[2], global_id_base[1], global_id_base[0]} ),
.valid_in(valid_in),
.stall_out(stall_out),
.valid_out(valid_out),
.stall_in(!last_in_group | !issue)
);
acl_work_item_iterator #(
.WIDTH(WIDTH)
) work_item_iterator (
.clock(clock),
.resetn(resetn),
.start(start),
.issue(issue),
.local_size(local_size),
.global_size(global_size),
.global_id_base(global_id_base),
.local_id(local_id),
.global_id(global_id_from_iter),
.last_in_group(last_in_group)
);
// goes high one cycle after last_in_group. stays high until
// next cycle where 'issue' is high.
always @(posedge clock or negedge resetn) begin
if ( ~resetn )
just_seen_last_in_group <= 1'b1;
else if ( start )
just_seen_last_in_group <= 1'b1;
else if (last_in_group & issue)
just_seen_last_in_group <= 1'b1;
else if (issue)
just_seen_last_in_group <= 1'b0;
else
just_seen_last_in_group <= just_seen_last_in_group;
end
endmodule
|
//------------------------------------------------------------------------------
// YF32 -- A small SOC implementation based on mlite (32-bit RISC CPU)
// @Taiwan
//------------------------------------------------------------------------------
//
// YF32 - A SOC implementation based on verilog ported mlite (32-bit RISC CPU)
// Copyright (C) 2003-2004 Yung-Fu Chen (yfchen58@gmail.com)
//
//------------------------------------------------------------------------------
// FETURE
// . verilog ported mlite included
// . wishbone bus support
// . simple_pic (programmable interrupt controller)
// . most MIPS-I(TM) opcode support
// . do not support excption
// . do not support "unaligned memory accesses"
// . only user mode support
// . 32K byte ROM
// . 2K byte SRAM
// . UART/Timer are not fully tested yet
// . no internal tri-state bus
// TO DO
// . integrate UART
// . integrate LCD/VGA Controller
// . integrete PS/2 interface
//
//------------------------------------------------------------------------------
// Note:
// MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of
// MIPS Technologies, Inc. in the United States and other countries.
// MIPS Technologies, Inc. does not endorse and is not associated with
// this project. OpenCores and Steve Rhoads are not affiliated in any way
// with MIPS Technologies, Inc.
//------------------------------------------------------------------------------
//
// FILE: reg_bank.v (tranlate from reg_bank.vhd from opencores.org)
//
// Vertsion: 1.0
//
// Date: 2004/03/22
//
// Author: Yung-Fu Chen (yfchen58@gmail.com)
//
// MODIFICATION HISTORY:
// Date By Version Change Description
//============================================================
// 2004/03/22 yfchen 1.0 Translate from reg_bank.vhd
//------------------------------------------------------------------------------
//-------------------------------------------------------------------
// TITLE: Register Bank
// AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
// DATE CREATED: 2/2/01
// FILENAME: reg_bank.vhd
// PROJECT: Plasma CPU core
// COPYRIGHT: Software placed into the public domain by the author.
// Software 'as is' without warranty. Author liable for nothing.
// DESCRIPTION:
// Implements a register bank with 32 registers that are 32-bits wide.
// There are two read-ports and one write port.
//-------------------------------------------------------------------
module reg_bank (clk, reset, pause, rs_index, rt_index, rd_index,
reg_source_out, reg_target_out, reg_dest_new, intr_enable);
input clk;
input reset;
input pause;
input [ 5:0] rs_index;
input [ 5:0] rt_index;
input [ 5:0] rd_index;
input [31:0] reg_dest_new;
output [31:0] reg_source_out;
output [31:0] reg_target_out;
output intr_enable;
reg [31:0] reg_target_out;
reg [31:0] reg_source_out;
reg intr_enable_reg;
wire intr_enable = intr_enable_reg ;
//controls access to dual-port memories
reg [ 4:0] addr_a1;
wire [ 4:0] addr_a2 = rt_index[4:0] ;
reg [ 4:0] addr_b;
reg write_enable;
wire [31:0] data_out1;
wire [31:0] data_out2;
always @(posedge clk or posedge reset) begin
if (reset)
intr_enable_reg <= 1'b0;
else
if (rd_index == 6'b101110)
//reg_epc CP0 14
intr_enable_reg <= 1'b0 ; //disable interrupts
else if (rd_index == 6'b101100)
intr_enable_reg <= reg_dest_new[0];
end
always @(rs_index or intr_enable_reg or data_out1 or rt_index or data_out2 or
rd_index or pause)
begin
//setup for first dual-port memory
if (rs_index == 6'b101110)
//reg_epc CP0 14
addr_a1 = 5'b00000;
else
addr_a1 = rs_index[4:0];
case (rs_index)
6'b000000 : reg_source_out = `ZERO;
6'b101100 : reg_source_out = {31'b0, intr_enable_reg};
6'b111111 : //interrupt vector address = 0x3c
reg_source_out = `INTERRUPT_VECTOR; //{24'b0, 8'b00111100};
default : reg_source_out = data_out1;
endcase
//setup for second dual-port memory
case (rt_index)
6'b000000 : reg_target_out = `ZERO;
default : reg_target_out = data_out2;
endcase
//setup second port (write port) for both dual-port memories
if (rd_index != 6'b000000 & rd_index != 6'b101100 & ~pause)
write_enable = 1'b1 ;
else
write_enable = 1'b0 ;
if (rd_index == 6'b101110)
//reg_epc CP0 14
addr_b = 5'b00000 ;
else
addr_b = rd_index[4:0] ;
end
//------------------------------------------------------------
//-- Pick only ONE of the dual-port RAM implementations below!
//------------------------------------------------------------
`ifdef reg_mem_type_TRI_PORT_MEM
// Option #1
// One tri-port RAM, two read-ports, one write-port
// 32 registers 32-bits wide
reg[31:0] tri_port_ram[31:0];
assign data_out1 = tri_port_ram[addr_a1];
assign data_out2 = tri_port_ram[addr_a2];
always @(posedge clk)
if (write_enable) tri_port_ram[addr_b] = reg_dest_new;
`endif //tri_port_mem
`ifdef reg_mem_type_DUAL_PORT_MEM
// Option #2
// Two dual-port RAMs, each with one read-port and one write-port
// According to the Xilinx answers database record #4075 this
// architecture may cause Synplify to infer synchronous dual-port
// RAM using RAM16x1D.
reg[31:0] dual_port_ram1[31:0];
reg[31:0] dual_port_ram2[31:0];
always @(addr_a1 or addr_a2 or dual_port_ram1) begin
data_out1 <= dual_port_ram1[addr_a1];
data_out2 <= dual_port_ram2[addr_a2];
end
always @(posedge clk) begin
if (write_enable) begin
dual_port_ram1[addr_b] = reg_dest_new;
dual_port_ram2[addr_b] = reg_dest_new;
end
end
`endif //dual_port_mem
`ifdef reg_mem_type_ALTERA_MEM
fpga_reg_bank fpga_reg_bank_inst (
.data ( reg_dest_new ),
.wraddress ( addr_b ),
.rdaddress_a ( addr_a1 ),
.rdaddress_b ( addr_a2 ),
.wren ( write_enable & clk ),
.qa ( data_out1 ),
.qb ( data_out2 )
);
`endif
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_envelope_generator.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU length counter; building block used by several other APU components. Provides automatic
* duration control for the NES APU waveform channels. Once loaded with a value, it can optionally
* count down and silence the channel when it reaches zero.
***************************************************************************************************/
module apu_envelope_generator
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [5:0] env_in, // envelope value (e.g., via $4000)
input wire env_wr_in, // envelope value write
input wire env_restart, // envelope restart
output wire [3:0] env_out // output volume
);
reg [5:0] q_reg;
wire [5:0] d_reg;
reg [3:0] q_cnt, d_cnt;
reg q_start_flag, d_start_flag;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_reg <= 6'h00;
q_cnt <= 4'h0;
q_start_flag <= 1'b0;
end
else
begin
q_reg <= d_reg;
q_cnt <= d_cnt;
q_start_flag <= d_start_flag;
end
end
reg divider_pulse_in;
reg divider_reload;
wire divider_pulse_out;
apu_div #(.PERIOD_BITS(4)) divider(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(divider_pulse_in),
.reload_in(divider_reload),
.period_in(q_reg[3:0]),
.pulse_out(divider_pulse_out)
);
always @*
begin
d_cnt = q_cnt;
d_start_flag = q_start_flag;
divider_pulse_in = 1'b0;
divider_reload = 1'b0;
// When the divider outputs a clock, one of two actions occurs: If the counter is non-zero, it
// is decremented, otherwise if the loop flag is set, the counter is loaded with 15.
if (divider_pulse_out)
begin
divider_reload = 1'b1;
if (q_cnt != 4'h0)
d_cnt = q_cnt - 4'h1;
else if (q_reg[5])
d_cnt = 4'hF;
end
// When clocked by the frame counter, one of two actions occurs: if the start flag is clear,
// the divider is clocked, otherwise the start flag is cleared, the counter is loaded with 15,
// and the divider's period is immediately reloaded.
if (eg_pulse_in)
begin
if (q_start_flag == 1'b0)
begin
divider_pulse_in = 1'b1;
end
else
begin
d_start_flag = 1'b0;
d_cnt = 4'hF;
end
end
if (env_restart)
d_start_flag = 1'b1;
end
assign d_reg = (env_wr_in) ? env_in : q_reg;
// The envelope unit's volume output depends on the constant volume flag: if set, the envelope
// parameter directly sets the volume, otherwise the counter's value is the current volume.
assign env_out = (q_reg[4]) ? q_reg[3:0] : q_cnt;
endmodule
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_len
*/
module test_axis_frame_len_8;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LEN_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [KEEP_WIDTH-1:0] monitor_axis_tkeep = 0;
reg monitor_axis_tvalid = 0;
reg monitor_axis_tready = 0;
reg monitor_axis_tlast = 0;
// Outputs
wire [LEN_WIDTH-1:0] frame_len;
wire frame_len_valid;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast
);
$to_myhdl(
frame_len,
frame_len_valid
);
// dump file
$dumpfile("test_axis_frame_len_8.lxt");
$dumpvars(0, test_axis_frame_len_8);
end
axis_frame_len #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LEN_WIDTH(LEN_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI monitor
.monitor_axis_tkeep(monitor_axis_tkeep),
.monitor_axis_tvalid(monitor_axis_tvalid),
.monitor_axis_tready(monitor_axis_tready),
.monitor_axis_tlast(monitor_axis_tlast),
// Status
.frame_len(frame_len),
.frame_len_valid(frame_len_valid)
);
endmodule
|
(* This program is free software; you can redistribute it and/or *)
(* modify it under the terms of the GNU Lesser General Public License *)
(* as published by the Free Software Foundation; either version 2.1 *)
(* of the License, or (at your option) any later version. *)
(* *)
(* This program is distributed in the hope that it will be useful, *)
(* but WITHOUT ANY WARRANTY; without even the implied warranty of *)
(* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *)
(* GNU General Public License for more details. *)
(* *)
(* You should have received a copy of the GNU Lesser General Public *)
(* License along with this program; if not, write to the Free *)
(* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA *)
(* 02110-1301 USA *)
(** This file includes random facts about Integers (and natural numbers) which are not found in the standard library. Some of the lemma here are not used in the QArith developement but are rather useful.
*)
Require Export ZArith.
Require Export ZArithRing.
Tactic Notation "ElimCompare" constr(c) constr(d) := elim_compare c d.
Ltac Flip :=
apply Zgt_lt || apply Zlt_gt || apply Zle_ge || apply Zge_le; assumption.
Ltac Falsum :=
try intro; apply False_ind;
repeat
match goal with
| id1:(~ ?X1) |- ?X2 =>
(apply id1; assumption || reflexivity) || clear id1
end.
Ltac Step_l a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X1 with a; [ idtac | try ring ]
end.
Ltac Step_r a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X2 with a; [ idtac | try ring ]
end.
Ltac CaseEq formula :=
generalize (refl_equal formula); pattern formula at -1 in |- *;
case formula.
Lemma pair_1 : forall (A B : Set) (H : A * B), H = pair (fst H) (snd H).
Proof.
intros.
case H.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma pair_2 :
forall (A B : Set) (H1 H2 : A * B),
fst H1 = fst H2 -> snd H1 = snd H2 -> H1 = H2.
Proof.
intros A B H1 H2.
case H1.
case H2.
simpl in |- *.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Section projection.
Variable A : Set.
Variable P : A -> Prop.
Definition projP1 (H : sig P) := let (x, h) := H in x.
Definition projP2 (H : sig P) :=
let (x, h) as H return (P (projP1 H)) := H in h.
End projection.
(*###########################################################################*)
(* Declaring some realtions on natural numbers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma le_stepl: forall x y z, le x y -> x=z -> le z y.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma le_stepr: forall x y z, le x y -> y=z -> le x z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma lt_stepl: forall x y z, lt x y -> x=z -> lt z y.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma lt_stepr: forall x y z, lt x y -> y=z -> lt x z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma neq_stepl:forall (x y z:nat), x<>y -> x=z -> z<>y.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma neq_stepr:forall (x y z:nat), x<>y -> y=z -> x<>z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step le_stepl.
Declare Right Step le_stepr.
Declare Left Step lt_stepl.
Declare Right Step lt_stepr.
Declare Left Step neq_stepl.
Declare Right Step neq_stepr.
(*###########################################################################*)
(** Some random facts about natural numbers, positive numbers and integers *)
(*###########################################################################*)
Lemma not_O_S : forall n : nat, n <> 0 -> {p : nat | n = S p}.
Proof.
intros [| np] Hn; [ exists 0; apply False_ind; apply Hn | exists np ];
reflexivity.
Qed.
Lemma lt_minus_neq : forall m n : nat, m < n -> n - m <> 0.
Proof.
intros.
omega.
Qed.
Lemma lt_minus_eq_0 : forall m n : nat, m < n -> m - n = 0.
Proof.
intros.
omega.
Qed.
Lemma le_plus_Sn_1_SSn : forall n : nat, S n + 1 <= S (S n).
Proof.
intros.
omega.
Qed.
Lemma le_plus_O_l : forall p q : nat, p + q <= 0 -> p = 0.
Proof.
intros; omega.
Qed.
Lemma le_plus_O_r : forall p q : nat, p + q <= 0 -> q = 0.
Proof.
intros; omega.
Qed.
Lemma minus_pred : forall m n : nat, 0 < n -> pred m - pred n = m - n.
Proof.
intros.
omega.
Qed.
(*###########################################################################*)
(* Declaring some realtions on integers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma Zle_stepl: forall x y z, (x<=y)%Z -> x=z -> (z<=y)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zle_stepr: forall x y z, (x<=y)%Z -> y=z -> (x<=z)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepl: forall x y z, (x<y)%Z -> x=z -> (z<y)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepr: forall x y z, (x<y)%Z -> y=z -> (x<z)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zneq_stepl:forall (x y z:Z), (x<>y)%Z -> x=z -> (z<>y)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma Zneq_stepr:forall (x y z:Z), (x<>y)%Z -> y=z -> (x<>z)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step Zle_stepl.
Declare Right Step Zle_stepr.
Declare Left Step Zlt_stepl.
Declare Right Step Zlt_stepr.
Declare Left Step Zneq_stepl.
Declare Right Step Zneq_stepr.
(*###########################################################################*)
(** Informative case analysis *)
(*###########################################################################*)
Lemma Zlt_cotrans :
forall x y : Z, (x < y)%Z -> forall z : Z, {(x < z)%Z} + {(z < y)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x z).
intro.
left.
assumption.
intro.
right.
apply Zle_lt_trans with (m := x).
apply Zge_le.
assumption.
assumption.
Qed.
Lemma Zlt_cotrans_pos :
forall x y : Z, (0 < x + y)%Z -> {(0 < x)%Z} + {(0 < y)%Z}.
Proof.
intros.
case (Zlt_cotrans 0 (x + y) H x).
intro.
left.
assumption.
intro.
right.
apply Zplus_lt_reg_l with (p := x).
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_cotrans_neg :
forall x y : Z, (x + y < 0)%Z -> {(x < 0)%Z} + {(y < 0)%Z}.
Proof.
intros x y H; case (Zlt_cotrans (x + y) 0 H x); intro Hxy;
[ right; apply Zplus_lt_reg_l with (p := x); rewrite Zplus_0_r | left ];
assumption.
Qed.
Lemma not_Zeq_inf : forall x y : Z, x <> y -> {(x < y)%Z} + {(y < x)%Z}.
Proof.
intros.
case Z_lt_ge_dec with x y.
intro.
left.
assumption.
intro H0.
generalize (Zge_le _ _ H0).
intro.
case (Z_le_lt_eq_dec _ _ H1).
intro.
right.
assumption.
intro.
apply False_rec.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec : forall x y : Z, {(x < y)%Z} + {(x > y)%Z} + {x = y}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro H.
left.
left.
assumption.
intro H.
generalize (Zge_le _ _ H).
intro H0.
case (Z_le_lt_eq_dec y x H0).
intro H1.
left.
right.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec' : forall x y : Z, {(x < y)%Z} + {(y < x)%Z} + {x = y}.
Proof.
intros x y.
case (Z_eq_dec x y); intro H;
[ right; assumption | left; apply (not_Zeq_inf _ _ H) ].
Qed.
Lemma Z_lt_le_dec : forall x y : Z, {(x < y)%Z} + {(y <= x)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro.
left.
assumption.
intro.
right.
apply Zge_le.
assumption.
Qed.
Lemma Z_le_lt_dec : forall x y : Z, {(x <= y)%Z} + {(y < x)%Z}.
Proof.
intros; case (Z_lt_le_dec y x); [ right | left ]; assumption.
Qed.
Lemma Z_lt_lt_S_eq_dec :
forall x y : Z, (x < y)%Z -> {(x + 1 < y)%Z} + {(x + 1)%Z = y}.
Proof.
intros.
generalize (Zlt_le_succ _ _ H).
unfold Zsucc in |- *.
apply Z_le_lt_eq_dec.
Qed.
Lemma quadro_leq_inf :
forall a b c d : Z,
{(c <= a)%Z /\ (d <= b)%Z} + {~ ((c <= a)%Z /\ (d <= b)%Z)}.
Proof.
intros.
case (Z_lt_le_dec a c).
intro z.
right.
intro.
elim H.
intros.
generalize z.
apply Zle_not_lt.
assumption.
intro.
case (Z_lt_le_dec b d).
intro z0.
right.
intro.
elim H.
intros.
generalize z0.
apply Zle_not_lt.
assumption.
intro.
left.
split.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** General auxiliary lemmata *)
(*###########################################################################*)
Lemma Zminus_eq : forall x y : Z, (x - y)%Z = 0%Z -> x = y.
Proof.
intros.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
unfold Zminus in H.
rewrite Zplus_comm.
assumption.
Qed.
Lemma Zlt_minus : forall a b : Z, (b < a)%Z -> (0 < a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_lt_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zle_minus : forall a b : Z, (b <= a)%Z -> (0 <= a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_le_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zlt_plus_plus :
forall m n p q : Z, (m < n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
apply Zlt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_lt_compat_l.
assumption.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zgt_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
intros.
apply Zgt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_gt_compat_l.
assumption.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zle_lt_plus_plus :
forall m n p q : Z, (m <= n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq m n).
assumption.
intro.
apply Zlt_plus_plus.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zge_gt_plus_plus :
forall m n p q : Z, (m >= n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq n m).
apply Zge_le.
assumption.
intro.
apply Zgt_plus_plus.
apply Zlt_gt.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zgt_ge_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p >= q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
rewrite Zplus_comm.
replace (n + q)%Z with (q + n)%Z.
apply Zge_gt_plus_plus.
assumption.
assumption.
apply Zplus_comm.
Qed.
Lemma Zlt_resp_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x + y)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zlt_plus_plus; assumption.
Qed.
Lemma Zle_resp_neg :
forall x y : Z, (x <= 0)%Z -> (y <= 0)%Z -> (x + y <= 0)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zplus_le_compat; assumption.
Qed.
Lemma Zlt_pos_opp : forall x : Z, (0 < x)%Z -> (- x < 0)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_neg_opp : forall x : Z, (x < 0)%Z -> (0 < - x)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_neg_opp : forall x : Z, (x <= 0)%Z -> (0 <= - x)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_pos_opp : forall x : Z, (0 <= x)%Z -> (- x <= 0)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zge_opp : forall x y : Z, (x <= y)%Z -> (- x >= - y)%Z.
Proof.
intros.
apply Zle_ge.
apply Zplus_le_reg_l with (p := (x + y)%Z).
ring_simplify (x + y + - y)%Z (x + y + - x)%Z.
assumption.
Qed.
(* Omega can't solve this *)
Lemma Zmult_pos_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_neg : forall x y : Z, (x < 0)%Z -> (y < 0)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_pos : forall x y : Z, (x < 0)%Z -> (0 < y)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_pos_neg : forall x y : Z, (0 < x)%Z -> (y < 0)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Hint Resolve Zmult_pos_pos Zmult_neg_neg Zmult_neg_pos Zmult_pos_neg: zarith.
Lemma Zle_reg_mult_l :
forall x y a : Z, (0 < a)%Z -> (x <= y)%Z -> (a * x <= a * y)%Z.
Proof.
intros.
apply Zplus_le_reg_l with (p := (- a * x)%Z).
ring_simplify (- a * x + a * x)%Z.
replace (- a * x + a * y)%Z with ((y - x) * a)%Z.
apply Zmult_gt_0_le_0_compat.
apply Zlt_gt.
assumption.
unfold Zminus in |- *.
apply Zle_left.
assumption.
ring.
Qed.
Lemma Zsimpl_plus_l_dep :
forall x y m n : Z, (x + m)%Z = (y + n)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zsimpl_plus_r_dep :
forall x y m n : Z, (m + x)%Z = (n + y)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite Zplus_comm.
rewrite Zplus_comm with x n.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zmult_simpl :
forall n m p q : Z, n = m -> p = q -> (n * p)%Z = (m * q)%Z.
Proof.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Lemma Zsimpl_mult_l :
forall n m p : Z, n <> 0%Z -> (n * m)%Z = (n * p)%Z -> m = p.
Proof.
intros.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + p)%Z with 0%Z.
apply Zmult_integral_l with (n := n).
assumption.
replace ((- p + m) * n)%Z with (n * m + - (n * p))%Z.
apply Zegal_left.
assumption.
ring.
ring.
Qed.
Lemma Zlt_reg_mult_l :
forall x y z : Z, (x > 0)%Z -> (y < z)%Z -> (x * y < x * z)%Z. (*QA*)
Proof.
intros.
case (Zcompare_Gt_spec x 0).
unfold Zgt in H.
assumption.
intros.
cut (x = Zpos x0).
intro.
rewrite H2.
unfold Zlt in H0.
unfold Zlt in |- *.
cut ((Zpos x0 * y ?= Zpos x0 * z)%Z = (y ?= z)%Z).
intro.
exact (trans_eq H3 H0).
apply Zcompare_mult_compat.
cut (x = (x + - (0))%Z).
intro.
exact (trans_eq H2 H1).
simpl in |- *.
apply (sym_eq (A:=Z)).
exact (Zplus_0_r x).
Qed.
Lemma Zlt_opp : forall x y : Z, (x < y)%Z -> (- x > - y)%Z. (*QA*)
Proof.
intros.
red in |- *.
apply sym_eq.
cut (Datatypes.Gt = (y ?= x)%Z).
intro.
cut ((y ?= x)%Z = (- x ?= - y)%Z).
intro.
exact (trans_eq H0 H1).
exact (Zcompare_opp y x).
apply sym_eq.
exact (Zlt_gt x y H).
Qed.
Lemma Zlt_conv_mult_l :
forall x y z : Z, (x < 0)%Z -> (y < z)%Z -> (x * y > x * z)%Z. (*QA*)
Proof.
intros.
cut (- x > 0)%Z.
intro.
cut (- x * y < - x * z)%Z.
intro.
cut (- (- x * y) > - (- x * z))%Z.
intro.
cut (- - (x * y) > - - (x * z))%Z.
intro.
cut ((- - (x * y))%Z = (x * y)%Z).
intro.
rewrite H5 in H4.
cut ((- - (x * z))%Z = (x * z)%Z).
intro.
rewrite H6 in H4.
assumption.
exact (Zopp_involutive (x * z)).
exact (Zopp_involutive (x * y)).
cut ((- (- x * y))%Z = (- - (x * y))%Z).
intro.
rewrite H4 in H3.
cut ((- (- x * z))%Z = (- - (x * z))%Z).
intro.
rewrite H5 in H3.
assumption.
cut ((- x * z)%Z = (- (x * z))%Z).
intro.
exact (f_equal Zopp H5).
exact (Zopp_mult_distr_l_reverse x z).
cut ((- x * y)%Z = (- (x * y))%Z).
intro.
exact (f_equal Zopp H4).
exact (Zopp_mult_distr_l_reverse x y).
exact (Zlt_opp (- x * y) (- x * z) H2).
exact (Zlt_reg_mult_l (- x) y z H1 H0).
exact (Zlt_opp x 0 H).
Qed.
Lemma Zgt_not_eq : forall x y : Z, (x > y)%Z -> x <> y. (*QA*)
Proof.
intros.
cut (y < x)%Z.
intro.
cut (y <> x).
intro.
red in |- *.
intros.
cut (y = x).
intros.
apply H1.
assumption.
exact (sym_eq H2).
exact (Zorder.Zlt_not_eq y x H0).
exact (Zgt_lt x y H).
Qed.
Lemma Zmult_resp_nonzero :
forall x y : Z, x <> 0%Z -> y <> 0%Z -> (x * y)%Z <> 0%Z.
Proof.
intros x y Hx Hy Hxy.
apply Hx.
apply Zmult_integral_l with y; assumption.
Qed.
Lemma Zopp_app : forall y : Z, y <> 0%Z -> (- y)%Z <> 0%Z.
Proof.
intros.
intro.
apply H.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
rewrite H0.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_neq_Zlt : forall a b : Z, (a <= b)%Z -> b <> a -> (a < b)%Z.
Proof.
intros a b H H0.
case (Z_le_lt_eq_dec _ _ H); trivial.
intro; apply False_ind; apply H0; symmetry in |- *; assumption.
Qed.
Lemma not_Zle_lt : forall x y : Z, ~ (y <= x)%Z -> (x < y)%Z.
Proof.
intros; apply Zgt_lt; apply Znot_le_gt; assumption.
Qed.
Lemma not_Zlt : forall x y : Z, ~ (y < x)%Z -> (x <= y)%Z.
Proof.
intros x y H1 H2; apply H1; apply Zgt_lt; assumption.
Qed.
Lemma Zmult_absorb :
forall x y z : Z, x <> 0%Z -> (x * y)%Z = (x * z)%Z -> y = z. (*QA*)
Proof.
intros.
case (dec_eq y z).
intro.
assumption.
intro.
case (not_Zeq y z).
assumption.
intro.
case (not_Zeq x 0).
assumption.
intro.
apply False_ind.
cut (x * y > x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zgt_not_eq (x * y) (x * z) H4).
exact (Zlt_conv_mult_l x y z H3 H2).
intro.
apply False_ind.
cut (x * y < x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zorder.Zlt_not_eq (x * y) (x * z) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x y z H4 H2).
exact (Zlt_gt 0 x H3).
intro.
apply False_ind.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H4.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H3).
apply False_ind.
case (not_Zeq x 0).
assumption.
intro.
cut (x * z > x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zgt_not_eq (x * z) (x * y) H4).
exact (Zlt_conv_mult_l x z y H3 H2).
intro.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x z y H4 H2).
exact (Zlt_gt 0 x H3).
Qed.
Lemma Zlt_mult_mult :
forall a b c d : Z,
(0 < a)%Z -> (0 < d)%Z -> (a < b)%Z -> (c < d)%Z -> (a * c < b * d)%Z.
Proof.
intros.
apply Zlt_trans with (a * d)%Z.
apply Zlt_reg_mult_l.
Flip.
assumption.
rewrite Zmult_comm.
rewrite Zmult_comm with b d.
apply Zlt_reg_mult_l.
Flip.
assumption.
Qed.
Lemma Zgt_mult_conv_absorb_l :
forall a x y : Z, (a < 0)%Z -> (a * x > a * y)%Z -> (x < y)%Z. (*QC*)
Proof.
intros.
case (dec_eq x y).
intro.
apply False_ind.
rewrite H1 in H0.
cut ((a * y)%Z = (a * y)%Z).
change ((a * y)%Z <> (a * y)%Z) in |- *.
apply Zgt_not_eq.
assumption.
trivial.
intro.
case (not_Zeq x y H1).
trivial.
intro.
apply False_ind.
cut (a * y > a * x)%Z.
apply Zgt_asym with (m := (a * y)%Z) (n := (a * x)%Z).
assumption.
apply Zlt_conv_mult_l.
assumption.
assumption.
Qed.
Lemma Zgt_mult_reg_absorb_l :
forall a x y : Z, (a > 0)%Z -> (a * x > a * y)%Z -> (x > y)%Z. (*QC*)
Proof.
intros.
cut (- - a > - - (0))%Z.
intro.
cut (- a < - (0))%Z.
simpl in |- *.
intro.
replace x with (- - x)%Z.
replace y with (- - y)%Z.
apply Zlt_opp.
apply Zgt_mult_conv_absorb_l with (a := (- a)%Z) (x := (- x)%Z).
assumption.
rewrite Zmult_opp_opp.
rewrite Zmult_opp_opp.
assumption.
apply Zopp_involutive.
apply Zopp_involutive.
apply Zgt_lt.
apply Zlt_opp.
apply Zgt_lt.
assumption.
simpl in |- *.
rewrite Zopp_involutive.
assumption.
Qed.
Lemma Zopp_Zlt : forall x y : Z, (y < x)%Z -> (- x < - y)%Z.
Proof.
intros x y Hyx.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
Flip.
ring.
ring.
Qed.
Lemma Zmin_cancel_Zlt : forall x y : Z, (- x < - y)%Z -> (y < x)%Z.
Proof.
intros.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
apply Zlt_gt.
assumption.
ring.
ring.
Qed.
Lemma Zmult_cancel_Zle :
forall a x y : Z, (a < 0)%Z -> (a * x <= a * y)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * x)).
apply Zle_lt_trans with (m := (a * y)%Z).
assumption.
apply Zgt_lt.
apply Zlt_conv_mult_l.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zlt_mult_cancel_l :
forall x y z : Z, (0 < x)%Z -> (x * y < x * z)%Z -> (y < z)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with x.
apply Zlt_gt.
assumption.
apply Zlt_gt.
assumption.
Qed.
Lemma Zmin_cancel_Zle : forall x y : Z, (- x <= - y)%Z -> (y <= x)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
assumption.
ring.
ring.
Qed.
Lemma Zmult_resp_Zle :
forall a x y : Z, (0 < a)%Z -> (a * y <= a * x)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * y)).
apply Zle_lt_trans with (m := (a * x)%Z).
assumption.
apply Zlt_reg_mult_l.
apply Zlt_gt.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zopp_Zle : forall x y : Z, (y <= x)%Z -> (- x <= - y)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
assumption.
clear y H; ring.
clear x H; ring.
Qed.
Lemma Zle_lt_eq_S : forall x y : Z, (x <= y)%Z -> (y < x + 1)%Z -> y = x.
Proof.
intros.
case (Z_le_lt_eq_dec x y H).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H1).
intro.
apply (Zlt_not_le y (x + 1) H0).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
intro H1.
symmetry in |- *.
assumption.
Qed.
Lemma Zlt_le_eq_S :
forall x y : Z, (x < y)%Z -> (y <= x + 1)%Z -> y = (x + 1)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec y (x + 1) H0).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H).
intro.
apply (Zlt_not_le y (x + 1) H1).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
trivial.
Qed.
Lemma double_not_equal_zero :
forall c d : Z, ~ (c = 0%Z /\ d = 0%Z) -> c <> d \/ c <> 0%Z.
Proof.
intros.
case (Z_zerop c).
intro.
rewrite e.
left.
apply sym_not_eq.
intro.
apply H; repeat split; assumption.
intro; right; assumption.
Qed.
Lemma triple_not_equal_zero :
forall a b c : Z,
~ (a = 0%Z /\ b = 0%Z /\ c = 0%Z) -> a <> 0%Z \/ b <> 0%Z \/ c <> 0%Z.
Proof.
intros a b c H; case (Z_zerop a); intro Ha;
[ case (Z_zerop b); intro Hb;
[ case (Z_zerop c); intro Hc;
[ apply False_ind; apply H; repeat split | right; right ]
| right; left ]
| left ]; assumption.
Qed.
Lemma mediant_1 :
forall m n m' n' : Z, (m' * n < m * n')%Z -> ((m + m') * n < m * (n + n'))%Z.
Proof.
intros.
rewrite Zmult_plus_distr_r.
rewrite Zmult_plus_distr_l.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma mediant_2 :
forall m n m' n' : Z,
(m' * n < m * n')%Z -> (m' * (n + n') < (m + m') * n')%Z.
Proof.
intros.
rewrite Zmult_plus_distr_l.
rewrite Zmult_plus_distr_r.
apply Zplus_lt_compat_r.
assumption.
Qed.
Lemma mediant_3 :
forall a b m n m' n' : Z,
(0 <= a * m + b * n)%Z ->
(0 <= a * m' + b * n')%Z -> (0 <= a * (m + m') + b * (n + n'))%Z.
Proof.
intros.
replace (a * (m + m') + b * (n + n'))%Z with
(a * m + b * n + (a * m' + b * n'))%Z.
apply Zplus_le_0_compat.
assumption.
assumption.
ring.
Qed.
Lemma fraction_lt_trans :
forall a b c d e f : Z,
(0 < b)%Z ->
(0 < d)%Z ->
(0 < f)%Z -> (a * d < c * b)%Z -> (c * f < e * d)%Z -> (a * f < e * b)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with d.
Flip.
apply Zgt_trans with (c * b * f)%Z.
replace (d * (e * b))%Z with (b * (e * d))%Z.
replace (c * b * f)%Z with (b * (c * f))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
replace (c * b * f)%Z with (f * (c * b))%Z.
replace (d * (a * f))%Z with (f * (a * d))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
Qed.
Lemma square_pos : forall a : Z, a <> 0%Z -> (0 < a * a)%Z.
Proof.
intros [| p| p]; intros; [ Falsum | constructor | constructor ].
Qed.
Hint Resolve square_pos: zarith.
(*###########################################################################*)
(** Properties of positive numbers, mapping between Z and nat *)
(*###########################################################################*)
Definition Z2positive (z : Z) :=
match z with
| Zpos p => p
| Zneg p => p
| Z0 => 1%positive
end.
Lemma ZL9 : forall p : positive, Z_of_nat (nat_of_P p) = Zpos p. (*QF*)
Proof.
intro.
cut (exists h : nat, nat_of_P p = S h).
intro.
case H.
intros.
unfold Z_of_nat in |- *.
rewrite H0.
apply f_equal with (A := positive) (B := Z) (f := Zpos).
cut (P_of_succ_nat (nat_of_P p) = P_of_succ_nat (S x)).
intro.
rewrite P_of_succ_nat_o_nat_of_P_eq_succ in H1.
cut (Ppred (Psucc p) = Ppred (P_of_succ_nat (S x))).
intro.
rewrite Ppred_succ in H2.
simpl in H2.
rewrite Ppred_succ in H2.
apply sym_eq.
assumption.
apply f_equal with (A := positive) (B := positive) (f := Ppred).
assumption.
apply f_equal with (f := P_of_succ_nat).
assumption.
apply ZL4.
Qed.
Coercion Z_of_nat : nat >-> Z.
Lemma ZERO_lt_POS : forall p : positive, (0 < Zpos p)%Z.
Proof.
intros.
constructor.
Qed.
Lemma POS_neq_ZERO : forall p : positive, Zpos p <> 0%Z.
Proof.
intros.
apply sym_not_eq.
apply Zorder.Zlt_not_eq.
apply ZERO_lt_POS.
Qed.
Lemma NEG_neq_ZERO : forall p : positive, Zneg p <> 0%Z.
Proof.
intros.
apply Zorder.Zlt_not_eq.
unfold Zlt in |- *.
constructor.
Qed.
Lemma POS_resp_eq : forall p0 p1 : positive, Zpos p0 = Zpos p1 -> p0 = p1.
Proof.
intros.
injection H.
trivial.
Qed.
Lemma nat_nat_pos : forall m n : nat, ((m + 1) * (n + 1) > 0)%Z. (*QF*)
Proof.
intros.
apply Zlt_gt.
cut (Z_of_nat m + 1 > 0)%Z.
intro.
cut (0 < Z_of_nat n + 1)%Z.
intro.
cut ((Z_of_nat m + 1) * 0 < (Z_of_nat m + 1) * (Z_of_nat n + 1))%Z.
rewrite Zmult_0_r.
intro.
assumption.
apply Zlt_reg_mult_l.
assumption.
assumption.
change (0 < Zsucc (Z_of_nat n))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat n)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
apply Zlt_gt.
change (0 < Zsucc (Z_of_nat m))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat m)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
Qed.
Theorem S_predn : forall m : nat, m <> 0 -> S (pred m) = m. (*QF*)
Proof.
intros.
case (O_or_S m).
intro.
case s.
intros.
rewrite <- e.
rewrite <- pred_Sn with (n := x).
trivial.
intro.
apply False_ind.
apply H.
apply sym_eq.
assumption.
Qed.
Lemma absolu_1 : forall x : Z, Zabs_nat x = 0 -> x = 0%Z. (*QF*)
Proof.
intros.
case (dec_eq x 0).
intro.
assumption.
intro.
apply False_ind.
cut ((x < 0)%Z \/ (x > 0)%Z).
intro.
ElimCompare x 0%Z.
intro.
cut (x = 0%Z).
assumption.
cut ((x ?= 0)%Z = Datatypes.Eq -> x = 0%Z).
intro.
apply H3.
assumption.
apply proj1 with (B := x = 0%Z -> (x ?= 0)%Z = Datatypes.Eq).
change ((x ?= 0)%Z = Datatypes.Eq <-> x = 0%Z) in |- *.
apply Zcompare_Eq_iff_eq.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
change (x < 0)%Z in H2.
cut (0 > x)%Z.
intro.
cut (exists p : positive, (0 + - x)%Z = Zpos p).
simpl in |- *.
intro.
case H4.
intros.
cut (exists q : positive, x = Zneg q).
intro.
case H6.
intros.
rewrite H7.
unfold Zabs_nat in |- *.
generalize x1.
exact ZL4.
cut (x = (- Zpos x0)%Z).
simpl in |- *.
intro.
exists x0.
assumption.
cut ((- - x)%Z = x).
intro.
rewrite <- H6.
exact (f_equal Zopp H5).
apply Zopp_involutive.
apply Zcompare_Gt_spec.
assumption.
apply Zlt_gt.
assumption.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
cut (exists p : positive, (x + - (0))%Z = Zpos p).
simpl in |- *.
rewrite Zplus_0_r.
intro.
case H3.
intros.
rewrite H4.
unfold Zabs_nat in |- *.
generalize x0.
exact ZL4.
apply Zcompare_Gt_spec.
assumption.
(***)
cut ((x < 0)%Z \/ (0 < x)%Z).
intro.
apply
or_ind with (A := (x < 0)%Z) (B := (0 < x)%Z) (P := (x < 0)%Z \/ (x > 0)%Z).
intro.
left.
assumption.
intro.
right.
apply Zlt_gt.
assumption.
assumption.
apply not_Zeq.
assumption.
Qed.
Lemma absolu_2 : forall x : Z, x <> 0%Z -> Zabs_nat x <> 0. (*QF*)
Proof.
intros.
intro.
apply H.
apply absolu_1.
assumption.
Qed.
Lemma absolu_inject_nat : forall n : nat, Zabs_nat (Z_of_nat n) = n.
Proof.
simple induction n; simpl in |- *.
reflexivity.
intros.
apply nat_of_P_o_P_of_succ_nat_eq_succ.
Qed.
Lemma eq_inj : forall m n : nat, m = n :>Z -> m = n.
Proof.
intros.
generalize (f_equal Zabs_nat H).
intro.
rewrite (absolu_inject_nat m) in H0.
rewrite (absolu_inject_nat n) in H0.
assumption.
Qed.
Lemma lt_inj : forall m n : nat, (m < n)%Z -> m < n.
Proof.
intros.
omega.
Qed.
Lemma le_inj : forall m n : nat, (m <= n)%Z -> m <= n.
Proof.
intros.
omega.
Qed.
Lemma inject_nat_S_inf : forall x : Z, (0 < x)%Z -> {n : nat | x = S n}.
Proof.
intros [| p| p] Hp; try discriminate Hp.
exists (pred (nat_of_P p)).
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hp;
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma le_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x <= y)%Z -> Zabs_nat x <= Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy;
apply le_O_n ||
(try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end).
simpl in |- *.
apply le_inj.
do 2 rewrite ZL9.
assumption.
Qed.
Lemma lt_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x < y)%Z -> Zabs_nat x < Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy; inversion Hxy;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end; simpl in |- *; apply lt_inj; repeat rewrite ZL9;
assumption.
Qed.
Lemma absolu_plus :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> Zabs_nat (x + y) = Zabs_nat x + Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy; trivial;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end.
rewrite <- BinInt.Zpos_plus_distr.
unfold Zabs_nat in |- *.
apply nat_of_P_plus_morphism.
Qed.
Lemma pred_absolu :
forall x : Z, (0 < x)%Z -> pred (Zabs_nat x) = Zabs_nat (x - 1).
Proof.
intros x Hx.
generalize (Z_lt_lt_S_eq_dec 0 x Hx); simpl in |- *; intros [H1| H1];
[ replace (Zabs_nat x) with (Zabs_nat (x - 1 + 1));
[ idtac | apply f_equal with Z; auto with zarith ];
rewrite absolu_plus;
[ unfold Zabs_nat at 2, nat_of_P, Piter_op in |- *; omega
| auto with zarith
| intro; discriminate ]
| rewrite <- H1; reflexivity ].
Qed.
Definition pred_nat : forall (x : Z) (Hx : (0 < x)%Z), nat.
intros [| px| px] Hx; try abstract (discriminate Hx).
exact (pred (nat_of_P px)).
Defined.
Lemma pred_nat_equal :
forall (x : Z) (Hx1 Hx2 : (0 < x)%Z), pred_nat x Hx1 = pred_nat x Hx2.
Proof.
intros [| px| px] Hx1 Hx2; try (discriminate Hx1); trivial.
Qed.
Let pred_nat_unfolded_subproof px :
Pos.to_nat px <> 0.
Proof.
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma pred_nat_unfolded :
forall (x : Z) (Hx : (0 < x)%Z), x = S (pred_nat x Hx).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hx; apply pred_nat_unfolded_subproof.
Qed.
Lemma absolu_pred_nat :
forall (m : Z) (Hm : (0 < m)%Z), S (pred_nat m Hm) = Zabs_nat m.
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
reflexivity.
apply pred_nat_unfolded_subproof.
Qed.
Lemma pred_nat_absolu :
forall (m : Z) (Hm : (0 < m)%Z), pred_nat m Hm = Zabs_nat (m - 1).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite <- pred_absolu; reflexivity || assumption.
Qed.
Lemma minus_pred_nat :
forall (n m : Z) (Hn : (0 < n)%Z) (Hm : (0 < m)%Z) (Hnm : (0 < n - m)%Z),
S (pred_nat n Hn) - S (pred_nat m Hm) = S (pred_nat (n - m) Hnm).
Proof.
intros.
simpl in |- *.
destruct n; try discriminate Hn.
destruct m; try discriminate Hm.
unfold pred_nat at 1 2 in |- *.
rewrite minus_pred; try apply lt_O_nat_of_P.
apply eq_inj.
rewrite <- pred_nat_unfolded.
rewrite Znat.inj_minus1.
repeat rewrite ZL9.
reflexivity.
apply le_inj.
apply Zlt_le_weak.
repeat rewrite ZL9.
apply Zlt_O_minus_lt.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zsgn *)
(*###########################################################################*)
Lemma Zsgn_1 :
forall x : Z, {Zsgn x = 0%Z} + {Zsgn x = 1%Z} + {Zsgn x = (-1)%Z}. (*QF*)
Proof.
intros.
case x.
left.
left.
unfold Zsgn in |- *.
reflexivity.
intro.
simpl in |- *.
left.
right.
reflexivity.
intro.
right.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_2 : forall x : Z, Zsgn x = 0%Z -> x = 0%Z. (*QF*)
Proof.
intros [| p1| p1]; simpl in |- *; intro H; constructor || discriminate H.
Qed.
Lemma Zsgn_3 : forall x : Z, x <> 0%Z -> Zsgn x <> 0%Z. (*QF*)
Proof.
intro.
case x.
intros.
apply False_ind.
apply H.
reflexivity.
intros.
simpl in |- *.
discriminate.
intros.
simpl in |- *.
discriminate.
Qed.
Theorem Zsgn_4 : forall a : Z, a = (Zsgn a * Zabs_nat a)%Z. (*QF*)
Proof.
intro.
case a.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite Zmult_1_l.
symmetry in |- *.
apply ZL9.
intros.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite ZL9.
constructor.
Qed.
Theorem Zsgn_5 :
forall a b x y : Z,
x <> 0%Z ->
y <> 0%Z ->
(Zsgn a * x)%Z = (Zsgn b * y)%Z -> (Zsgn a * y)%Z = (Zsgn b * x)%Z. (*QF*)
Proof.
intros a b x y H H0.
case a.
case b.
simpl in |- *.
trivial.
intro.
unfold Zsgn in |- *.
intro.
rewrite Zmult_1_l in H1.
simpl in H1.
apply False_ind.
apply H0.
symmetry in |- *.
assumption.
intro.
unfold Zsgn in |- *.
intro.
apply False_ind.
apply H0.
apply Zopp_inj.
simpl in |- *.
transitivity (-1 * y)%Z.
constructor.
transitivity (0 * x)%Z.
symmetry in |- *.
assumption.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity y.
rewrite Zmult_1_l.
reflexivity.
transitivity (Zsgn b * (Zsgn b * y))%Z.
case (Zsgn_1 b).
intro.
case s.
intro.
apply False_ind.
apply H.
rewrite e in H1.
change ((1 * x)%Z = 0%Z) in H1.
rewrite Zmult_1_l in H1.
assumption.
intro.
rewrite e.
rewrite Zmult_1_l.
rewrite Zmult_1_l.
reflexivity.
intro.
rewrite e.
ring.
rewrite Zmult_1_l in H1.
rewrite H1.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity (Zsgn b * (-1 * (Zsgn b * y)))%Z.
case (Zsgn_1 b).
intros.
case s.
intro.
apply False_ind.
apply H.
apply Zopp_inj.
transitivity (-1 * x)%Z.
ring.
unfold Zopp in |- *.
rewrite e in H1.
transitivity (0 * y)%Z.
assumption.
simpl in |- *.
reflexivity.
intro.
rewrite e.
ring.
intro.
rewrite e.
ring.
rewrite <- H1.
ring.
Qed.
Lemma Zsgn_6 : forall x : Z, x = 0%Z -> Zsgn x = 0%Z.
Proof.
intros.
rewrite H.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_7 : forall x : Z, (x > 0)%Z -> Zsgn x = 1%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
Flip.
intros.
simpl in |- *.
reflexivity.
intros.
apply False_ind.
apply (Zlt_irrefl (Zneg p)).
apply Zlt_trans with 0%Z.
constructor.
Flip.
Qed.
Lemma Zsgn_7' : forall x : Z, (0 < x)%Z -> Zsgn x = 1%Z.
Proof.
intros; apply Zsgn_7; Flip.
Qed.
Lemma Zsgn_8 : forall x : Z, (x < 0)%Z -> Zsgn x = (-1)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
assumption.
intros.
apply False_ind.
apply (Zlt_irrefl 0).
apply Zlt_trans with (Zpos p).
constructor.
assumption.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_9 : forall x : Z, Zsgn x = 1%Z -> (0 < x)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
simpl in H.
discriminate.
intros.
constructor.
intros.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_10 : forall x : Z, Zsgn x = (-1)%Z -> (x < 0)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
discriminate.
intros.
apply False_ind.
discriminate.
intros.
constructor.
Qed.
Lemma Zsgn_11 : forall x : Z, (Zsgn x < 0)%Z -> (x < 0)%Z.
Proof.
intros.
apply Zsgn_10.
case (Zsgn_1 x).
intro.
apply False_ind.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply (H0 e).
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
discriminate.
trivial.
Qed.
Lemma Zsgn_12 : forall x : Z, (0 < Zsgn x)%Z -> (0 < x)%Z.
Proof.
intros.
apply Zsgn_9.
case (Zsgn_1 x).
intro.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
generalize (sym_eq e).
intro.
apply False_ind.
apply (H0 H1).
trivial.
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_13 : forall x : Z, (0 <= Zsgn x)%Z -> (0 <= x)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec 0 (Zsgn x) H).
intro.
apply Zlt_le_weak.
apply Zsgn_12.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
symmetry in |- *.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_14 : forall x : Z, (Zsgn x <= 0)%Z -> (x <= 0)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec (Zsgn x) 0 H).
intro.
apply Zlt_le_weak.
apply Zsgn_11.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_15 : forall x y : Z, Zsgn (x * y) = (Zsgn x * Zsgn y)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; constructor.
Qed.
Lemma Zsgn_16 :
forall x y : Z,
Zsgn (x * y) = 1%Z -> {(0 < x)%Z /\ (0 < y)%Z} + {(x < 0)%Z /\ (y < 0)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_17 :
forall x y : Z,
Zsgn (x * y) = (-1)%Z -> {(0 < x)%Z /\ (y < 0)%Z} + {(x < 0)%Z /\ (0 < y)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_18 : forall x y : Z, Zsgn (x * y) = 0%Z -> {x = 0%Z} + {y = 0%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right | right ]; constructor.
Qed.
Lemma Zsgn_19 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 < x + y)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_12; assumption).
Qed.
Lemma Zsgn_20 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x + y < 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_11; assumption).
Qed.
Lemma Zsgn_21 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= x)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_22 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x <= 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_23 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= y)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_24 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (y <= 0)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_25 : forall x : Z, Zsgn (- x) = (- Zsgn x)%Z.
Proof.
intros [| p1| p1]; simpl in |- *; reflexivity.
Qed.
Lemma Zsgn_26 : forall x : Z, (0 < x)%Z -> (0 < Zsgn x)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Lemma Zsgn_27 : forall x : Z, (x < 0)%Z -> (Zsgn x < 0)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Hint Resolve Zsgn_1 Zsgn_2 Zsgn_3 Zsgn_4 Zsgn_5 Zsgn_6 Zsgn_7 Zsgn_7' Zsgn_8
Zsgn_9 Zsgn_10 Zsgn_11 Zsgn_12 Zsgn_13 Zsgn_14 Zsgn_15 Zsgn_16 Zsgn_17
Zsgn_18 Zsgn_19 Zsgn_20 Zsgn_21 Zsgn_22 Zsgn_23 Zsgn_24 Zsgn_25 Zsgn_26
Zsgn_27: zarith.
(*###########################################################################*)
(** Properties of Zabs *)
(*###########################################################################*)
Lemma Zabs_1 : forall z p : Z, (Zabs z < p)%Z -> (z < p)%Z /\ (- p < z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
split.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
assumption.
intros.
simpl in H.
split.
assumption.
apply Zlt_trans with (m := 0%Z).
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
constructor.
intros.
simpl in H.
split.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl;trivial.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (- Zneg p0)%Z.
replace (- Zneg p0)%Z with (Zpos p0).
apply Zlt_gt.
assumption.
symmetry in |- *.
apply Zopp_neg.
rewrite Zopp_mult_distr_l_reverse with (n := 1%Z).
simpl in |- *.
constructor.
Qed.
Lemma Zabs_2 : forall z p : Z, (Zabs z > p)%Z -> (z > p)%Z \/ (- p > z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
right.
apply Zlt_gt.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (Zpos p0).
assumption.
reflexivity.
Qed.
Lemma Zabs_3 : forall z p : Z, (z < p)%Z /\ (- p < z)%Z -> (Zabs z < p)%Z.
Proof.
intros z p.
case z.
intro.
simpl in |- *.
elim H.
intros.
assumption.
intros.
elim H.
intros.
simpl in |- *.
assumption.
intros.
elim H.
intros.
simpl in |- *.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * Zpos p0)%Z with (Zneg p0).
replace (-1 * p)%Z with (- p)%Z.
apply Zlt_gt.
assumption.
ring.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_4 : forall z p : Z, (Zabs z < p)%Z -> (- p < z < p)%Z.
Proof.
intros.
split.
apply proj2 with (A := (z < p)%Z).
apply Zabs_1.
assumption.
apply proj1 with (B := (- p < z)%Z).
apply Zabs_1.
assumption.
Qed.
Lemma Zabs_5 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z <= p)%Z.
Proof.
intros.
split.
replace (- p)%Z with (Zsucc (- Zsucc p)).
apply Zlt_le_succ.
apply proj2 with (A := (z < Zsucc p)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
unfold Zsucc in |- *.
ring.
apply Zlt_succ_le.
apply proj1 with (B := (- Zsucc p < z)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
Qed.
Lemma Zabs_6 : forall z p : Z, (Zabs z <= p)%Z -> (z <= p)%Z.
Proof.
intros.
apply proj2 with (A := (- p <= z)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_7 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z)%Z.
Proof.
intros.
apply proj1 with (B := (z <= p)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_8 : forall z p : Z, (- p <= z <= p)%Z -> (Zabs z <= p)%Z.
Proof.
intros.
apply Zlt_succ_le.
apply Zabs_3.
elim H.
intros.
split.
apply Zle_lt_succ.
assumption.
apply Zlt_le_trans with (m := (- p)%Z).
apply Zgt_lt.
apply Zlt_opp.
apply Zlt_succ.
assumption.
Qed.
Lemma Zabs_min : forall z : Z, Zabs z = Zabs (- z).
Proof.
intro.
case z.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_9 :
forall z p : Z, (0 <= p)%Z -> (p < z)%Z \/ (z < - p)%Z -> (p < Zabs z)%Z.
Proof.
intros.
case H0.
intro.
replace (Zabs z) with z.
assumption.
symmetry in |- *.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
assumption.
intro.
cut (Zabs z = (- z)%Z).
intro.
rewrite H2.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
rewrite Zabs_min.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
Qed.
Lemma Zabs_10 : forall z : Z, (0 <= Zabs z)%Z.
Proof.
intro.
case (Z_zerop z).
intro.
rewrite e.
simpl in |- *.
apply Zle_refl.
intro.
case (not_Zeq z 0 n).
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
right.
assumption.
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
left.
assumption.
Qed.
Lemma Zabs_11 : forall z : Z, z <> 0%Z -> (0 < Zabs z)%Z.
Proof.
intros.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
apply not_Zeq.
intro.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Zabs_12 : forall z m : Z, (m < Zabs z)%Z -> {(m < z)%Z} + {(z < - m)%Z}.
Proof.
intros [| p| p] m; simpl in |- *; intros H;
[ left | left | right; apply Zmin_cancel_Zlt; rewrite Zopp_involutive ];
assumption.
Qed.
Lemma Zabs_mult : forall z p : Z, Zabs (z * p) = (Zabs z * Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
reflexivity.
case p.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
case p.
intro.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_plus : forall z p : Z, (Zabs (z + p) <= Zabs z + Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
apply Zle_refl.
case p.
intro.
simpl in |- *.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 - Zneg p0)%Z.
replace (Zpos p1 - Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(- (Zpos p0 + Zneg p0))%Z.
replace (Zpos p1 - Zneg p0 + (Zpos p1 + Zneg p0))%Z with (2 * Zpos p1)%Z.
replace (- (Zpos p0 + Zneg p0))%Z with 0%Z.
apply Zmult_gt_0_le_0_compat.
constructor.
apply Zlt_le_weak.
constructor.
rewrite <- Zopp_neg with p0.
ring.
ring.
ring.
apply Zplus_le_compat.
apply Zle_refl.
apply Zlt_le_weak.
constructor.
case p.
simpl in |- *.
intro.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 + Zneg p0)%Z.
replace (Zpos p1 + Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(Zneg p0 - Zpos p0)%Z.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with 0%Z.
apply Zplus_le_reg_l with (Zpos p0).
replace (Zpos p0 + (Zneg p0 - Zpos p0))%Z with (Zneg p0).
simpl in |- *.
apply Zlt_le_weak.
constructor.
ring.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with
(Zpos p1 + Zneg p1 + (Zpos p0 + Zneg p0))%Z.
replace 0%Z with (0 + 0)%Z.
apply Zplus_eq_compat.
rewrite <- Zopp_neg with p1.
ring.
rewrite <- Zopp_neg with p0.
ring.
simpl in |- *.
constructor.
ring.
ring.
apply Zplus_le_compat.
apply Zlt_le_weak.
constructor.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
Qed.
Lemma Zabs_neg : forall z : Z, (z <= 0)%Z -> Zabs z = (- z)%Z.
Proof.
intro.
case z.
simpl in |- *.
intro.
reflexivity.
intros.
apply False_ind.
apply H.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_Zabs: forall z, (z <= Zabs z)%Z.
Proof.
intros [|z|z]; simpl; auto with zarith; apply Zle_neg_pos.
Qed.
Hint Resolve Zabs_1 Zabs_2 Zabs_3 Zabs_4 Zabs_5 Zabs_6 Zabs_7 Zabs_8 Zabs_9
Zabs_10 Zabs_11 Zabs_12 Zabs_min Zabs_neg Zabs_mult Zabs_plus Zle_Zabs: zarith.
(*###########################################################################*)
(** Induction on Z *)
(*###########################################################################*)
Lemma Zind :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> exists k : nat, q = (p + k)%Z).
intro.
cut (forall k : nat, P (p + k)%Z).
intro.
intros.
cut (exists k : nat, q = (p + Z_of_nat k)%Z).
intro.
case H4.
intros.
rewrite H5.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
ring_simplify (p + 0)%Z.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
ring_simplify (- p + (p + Z_of_nat k))%Z.
apply Znat.inj_le.
apply le_O_n.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (q - p)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> {k : nat | q = (p + k)%Z}).
intro.
cut (forall k : nat, F (p + k)%Z).
intro.
intros.
cut {k : nat | q = (p + Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
rewrite Zplus_0_r.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
replace (- p + (p + Z_of_nat k))%Z with (Z_of_nat k).
apply Znat.inj_le.
apply le_O_n.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
apply Zplus_assoc_reverse.
intros.
cut {k : nat | (q - p)%Z = Z_of_nat k}.
intro H2.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite e.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
unfold Zminus in |- *.
apply Zplus_comm.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_down :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> {k : nat | q = (p - k)%Z}).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut {k : nat | q = (p - Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
unfold Zminus in |- *.
unfold Zopp in |- *.
rewrite Zplus_0_r; reflexivity.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
unfold Zminus in |- *; rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
unfold Zminus at 1 2 in |- *.
rewrite Zplus_assoc_reverse.
rewrite <- Zopp_plus_distr.
reflexivity.
intros.
cut {k : nat | (p - q)%Z = Z_of_nat k}.
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- e.
reflexivity.
unfold Zminus in |- *.
rewrite Zopp_plus_distr.
rewrite Zplus_assoc.
rewrite Zplus_opp_r.
rewrite Zopp_involutive.
reflexivity.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zind_down :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> exists k : nat, q = (p - k)%Z).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut (exists k : nat, q = (p - Z_of_nat k)%Z).
intro.
case H4.
intros x e.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
ring.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
ring.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (p - q)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_wf :
forall (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zrec with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zrec_wf2 :
forall (q : Z) (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zrec_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zrec_wf_double :
forall (P : Z -> Z -> Set) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zrec_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zrec_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
Lemma Zind_wf :
forall (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zind with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zind_wf2 :
forall (q : Z) (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zind_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zind_wf_double :
forall (P : Z -> Z -> Prop) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zind_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zind_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zmax *)
(*###########################################################################*)
Definition Zmax (n m : Z) := (n + m - Zmin n m)%Z.
Lemma ZmaxSS : forall n m : Z, (Zmax n m + 1)%Z = Zmax (n + 1) (m + 1).
Proof.
intros.
unfold Zmax in |- *.
replace (Zmin (n + 1) (m + 1)) with (Zmin n m + 1)%Z.
ring.
symmetry in |- *.
change (Zmin (Zsucc n) (Zsucc m) = Zsucc (Zmin n m)) in |- *.
symmetry in |- *.
apply Zmin_SS.
Qed.
Lemma Zle_max_l : forall n m : Z, (n <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- n + Zmin n m)%Z).
ring_simplify (- n + Zmin n m + n)%Z.
ring_simplify (- n + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_r.
Qed.
Lemma Zle_max_r : forall n m : Z, (m <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- m + Zmin n m)%Z).
ring_simplify (- m + Zmin n m + m)%Z.
ring_simplify (- m + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_l.
Qed.
Lemma Zmin_or_informative : forall n m : Z, {Zmin n m = n} + {Zmin n m = m}.
Proof.
intros.
case (Z_lt_ge_dec n m).
unfold Zmin in |- *.
unfold Zlt in |- *.
intro z.
rewrite z.
left.
reflexivity.
intro.
cut ({(n > m)%Z} + {n = m :>Z}).
intro.
case H.
intros z0.
unfold Zmin in |- *.
unfold Zgt in z0.
rewrite z0.
right.
reflexivity.
intro.
rewrite e.
right.
apply Zmin_n_n.
cut ({(m < n)%Z} + {m = n :>Z}).
intro.
elim H.
intro.
left.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
apply Z_le_lt_eq_dec.
apply Zge_le.
assumption.
Qed.
Lemma Zmax_case : forall (n m : Z) (P : Z -> Set), P n -> P m -> P (Zmax n m).
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
cut ((n + m - n)%Z = m).
intro.
rewrite H1.
assumption.
ring.
intro.
rewrite e.
cut ((n + m - m)%Z = n).
intro.
rewrite H1.
assumption.
ring.
Qed.
Lemma Zmax_or_informative : forall n m : Z, {Zmax n m = n} + {Zmax n m = m}.
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
right.
ring.
intro.
rewrite e.
left.
ring.
Qed.
Lemma Zmax_n_n : forall n : Z, Zmax n n = n.
Proof.
intros.
unfold Zmax in |- *.
rewrite (Zmin_n_n n).
ring.
Qed.
Hint Resolve ZmaxSS Zle_max_r Zle_max_l Zmax_n_n: zarith.
(*###########################################################################*)
(** Properties of Arity *)
(*###########################################################################*)
Lemma Zeven_S : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x + 1).
Proof.
exact Zeven.Zeven_Sn.
Qed.
Lemma Zeven_pred : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x - 1).
Proof.
exact Zeven.Zeven_pred.
Qed.
(* This lemma used to be useful since it was mentioned with an unnecessary premise
`x>=0` as Z_modulo_2 in ZArith, but the ZArith version has been fixed. *)
Definition Z_modulo_2_always :
forall x : Z, {y : Z | x = (2 * y)%Z} + {y : Z | x = (2 * y + 1)%Z} :=
Zeven.Z_modulo_2.
(*###########################################################################*)
(** Properties of Zdiv *)
(*###########################################################################*)
Lemma Z_div_mod_eq_2 :
forall a b : Z, (0 < b)%Z -> (b * (a / b))%Z = (a - a mod b)%Z.
Proof.
intros.
apply Zplus_minus_eq.
rewrite Zplus_comm.
apply Z_div_mod_eq.
Flip.
Qed.
Lemma Z_div_le :
forall a b c : Z, (0 < c)%Z -> (b <= a)%Z -> (b / c <= a / c)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge; Flip; assumption.
Qed.
Lemma Z_div_nonneg :
forall a b : Z, (0 < b)%Z -> (0 <= a)%Z -> (0 <= a / b)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge0; Flip; assumption.
Qed.
Lemma Z_div_neg : forall a b : Z, (0 < b)%Z -> (a < 0)%Z -> (a / b < 0)%Z.
Proof.
intros.
rewrite (Z_div_mod_eq a b) in H0.
elim (Z_mod_lt a b).
intros H1 _.
apply Znot_ge_lt.
intro.
apply (Zlt_not_le (b * (a / b) + a mod b) 0 H0).
apply Zplus_le_0_compat.
apply Zmult_le_0_compat.
apply Zlt_le_weak; assumption.
Flip.
assumption.
Flip.
Flip.
Qed.
Hint Resolve Z_div_mod_eq_2 Z_div_le Z_div_nonneg Z_div_neg: zarith.
(*###########################################################################*)
(** Properties of Zpower *)
(*###########################################################################*)
Lemma Zpower_1 : forall a : Z, (a ^ 1)%Z = a.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
auto with zarith.
Qed.
Lemma Zpower_2 : forall a : Z, (a ^ 2)%Z = (a * a)%Z.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
ring.
Qed.
Hint Resolve Zpower_1 Zpower_2: zarith.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = (crc[1:0]==0 ? 3'd0
: crc[1:0]==0 ? 3'd1
: crc[1:0]==0 ? 3'd2 : 3'd4);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[2:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h704ca23e2a83e1c5
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [2:0] in;
output reg [31:0] out;
localparam ST_0 = 0;
localparam ST_1 = 1;
localparam ST_2 = 2;
always @(posedge clk) begin
case (1'b1) // synopsys parallel_case
in[ST_0]: out <= 32'h1234;
in[ST_1]: out <= 32'h4356;
in[ST_2]: out <= 32'h9874;
default: out <= 32'h1;
endcase
end
endmodule
|
`timescale 1 ps / 1 ps
module ov7670_marker_tracker_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output intr,
input [7:0]OV7670_D,
input OV7670_HREF,
input OV7670_PCLK,
output OV7670_PWDN,
output OV7670_RESET,
output OV7670_SIOC,
inout OV7670_SIOD,
input OV7670_VSYNC,
output OV7670_XCLK,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
reg intr_reg;
wire [16:0] marker_x, marker_y;
wire update_tracker_pos;
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign intr = intr_reg;
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
reg_data_out <= 0;
end
else
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= {15'b0, marker_x};//slv_reg2;
2'h3 : reg_data_out <= {15'b0, marker_y}; //slv_reg3;
default : reg_data_out <= 0;
endcase
end
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
always@(posedge S_AXI_ACLK)
if(update_tracker_pos == 1 && slv_reg1[2])
intr_reg <= 1;
else
intr_reg <= 0;
// Add user logic here
//reg_intr
design_2_wrapper d(
.Config_Done(),
.OV7670_D,
.OV7670_HREF,
.OV7670_PCLK,
.OV7670_PWDN,
.OV7670_RESET,
.OV7670_SIOC,
.OV7670_SIOD,
.OV7670_VSYNC,
.OV7670_XCLK,
.clock_rtl(S_AXI_ACLK),
.go(slv_reg1[0]),
.marker_x(marker_x),
.marker_y(marker_y),
.resend_cam_config(slv_reg1[1]),
.reset_rtl(!S_AXI_ARESETN),
.track_clr(slv_reg0[20:0]),
.update_tracker_pos(update_tracker_pos)
);
// User logic ends
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_PP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_PP_V |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Serial Control Bus from Cypress chip
module serial_io
( input master_clk,
input serial_clock,
input serial_data_in,
input enable,
input reset,
inout wire serial_data_out,
output reg [6:0] serial_addr,
output reg [31:0] serial_data,
output wire serial_strobe,
input wire [31:0] readback_0,
input wire [31:0] readback_1,
input wire [31:0] readback_2,
input wire [31:0] readback_3,
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
input wire [31:0] readback_7
);
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
assign serial_data_out = is_read ? serial_data[31] : 1'bz;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
ser_ctr <= #1 8'd0;
else if(~enable)
ser_ctr <= #1 8'd0;
else if(ser_ctr == 39)
ser_ctr <= #1 8'd0;
else
ser_ctr <= #1 ser_ctr + 8'd1;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
is_read <= #1 1'b0;
else if(~enable)
is_read <= #1 1'b0;
else if((ser_ctr == 7)&&(serial_addr[6]==1))
is_read <= #1 1'b1;
always @(posedge serial_clock, posedge reset)
if(reset)
begin
serial_addr <= #1 7'b0;
serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else if(~enable)
begin
//serial_addr <= #1 7'b0;
//serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else
begin
if(~is_read && (ser_ctr == 39))
write_done <= #1 1'b1;
else
write_done <= #1 1'b0;
if(is_read & (ser_ctr==8))
case (serial_addr)
7'd1: serial_data <= #1 readback_0;
7'd2: serial_data <= #1 readback_1;
7'd3: serial_data <= #1 readback_2;
7'd4: serial_data <= #1 readback_3;
7'd5: serial_data <= #1 readback_4;
7'd6: serial_data <= #1 readback_5;
7'd7: serial_data <= #1 readback_6;
7'd8: serial_data <= #1 readback_7;
default: serial_data <= #1 32'd0;
endcase // case(serial_addr)
else if(ser_ctr >= 8)
serial_data <= #1 {serial_data[30:0],serial_data_in};
else if(ser_ctr < 8)
serial_addr <= #1 {serial_addr[5:0],serial_data_in};
end // else: !if(~enable)
reg enable_d1, enable_d2;
always @(posedge master_clk)
begin
enable_d1 <= #1 enable;
enable_d2 <= #1 enable_d1;
end
assign serial_strobe = enable_d2 & ~enable_d1;
endmodule // serial_io
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
/* Acceptable answer 1
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.b.gen[0].tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.b.gen[1].tag
*/
/* Acceptable answer 2
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.tag
*/
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
tag tag ();
b b ();
always @ (t.cyc) begin
if (t.cyc == 2) $display("mod a has scope = %m");
if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope);
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module b ();
genvar g;
generate
for (g=0; g<2; g++) begin : gen
tag tag ();
c c ();
end
endgenerate
always @ (t.cyc) begin
if (t.cyc == 3) $display("mod b has scope = %m");
if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope);
end
endmodule
module c ();
always @ (t.cyc) begin
if (t.cyc == 4) $display("mod c has scope = %m");
if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope);
end
endmodule
module tag ();
bit [100*8-1:0] scope;
initial begin
$sformat(scope,"%m");
$display("created tag with scope = %0s",scope);
end
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: si_transactor.v
//
// Description:
// This module manages multi-threaded transactions for one SI-slot.
// The module interface consists of a 1-slave to 1-master address channel, plus a
// (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.
// The module maintains transaction thread control registers that count the
// number of outstanding transations for each thread and the target MI-slot.
// On the address channel, the module decodes addresses to select among MI-slots
// accessible to the SI-slot where it is instantiated.
// It then qualifies whether each received transaction
// should be propagated as a request to the address channel arbiter.
// Transactions are blocked while there is any outstanding transaction to a
// different slave (MI-slot) for the requested ID thread (for deadlock avoidance).
// On the response channel, the module mulitplexes transfers from each of the
// MI-slots whenever a transfer targets the ID of an active thread,
// arbitrating between MI-slots if multiple threads respond concurrently.
//
//--------------------------------------------------------------------------
//
// Structure:
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_8_si_transactor #
(
parameter C_FAMILY = "none",
parameter integer C_SI = 0, // SI-slot number of current instance.
parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read.
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_NUM_M = 2,
parameter integer C_NUM_M_LOG = 1,
parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot.
parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot.
parameter integer C_ID_WIDTH = 1,
parameter integer C_THREAD_ID_WIDTH = 0,
parameter integer C_ADDR_WIDTH = 32,
parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation.
parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation.
parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}},
parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}},
parameter integer C_SINGLE_THREAD = 0,
parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}},
parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE =0,
parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Address Channel Interface Ports
input wire [C_ID_WIDTH-1:0] S_AID,
input wire [C_ADDR_WIDTH-1:0] S_AADDR,
input wire [8-1:0] S_ALEN,
input wire [3-1:0] S_ASIZE,
input wire [2-1:0] S_ABURST,
input wire [2-1:0] S_ALOCK,
input wire [3-1:0] S_APROT,
// input wire [4-1:0] S_AREGION,
input wire [C_AMESG_WIDTH-1:0] S_AMESG,
input wire S_AVALID,
output wire S_AREADY,
// Master Address Channel Interface Ports
output wire [C_ID_WIDTH-1:0] M_AID,
output wire [C_ADDR_WIDTH-1:0] M_AADDR,
output wire [8-1:0] M_ALEN,
output wire [3-1:0] M_ASIZE,
output wire [2-1:0] M_ALOCK,
output wire [3-1:0] M_APROT,
output wire [4-1:0] M_AREGION,
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT,
output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC,
output wire [7:0] M_AERROR,
output wire M_AVALID_QUAL,
output wire M_AVALID,
input wire M_AREADY,
// Slave Response Channel Interface Ports
output wire [C_ID_WIDTH-1:0] S_RID,
output wire [C_RMESG_WIDTH-1:0] S_RMESG,
output wire S_RLAST,
output wire S_RVALID,
input wire S_RREADY,
// Master Response Channel Interface Ports
input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID,
input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG,
input wire [(C_NUM_M+1)-1:0] M_RLAST,
input wire [(C_NUM_M+1)-1:0] M_RVALID,
output wire [(C_NUM_M+1)-1:0] M_RREADY,
input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot?
input wire [8-1:0] DEBUG_A_TRANS_SEQ
);
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;
localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);
localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1;
localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;
localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;
localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// AxiLite protocol flag vector
function [C_NUM_M-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_M-1:0] f_bit32to1_mi
(input [C_NUM_M*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
wire [C_NUM_M-1:0] target_mi_hot;
wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;
wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;
wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;
wire match;
wire [3:0] target_region;
wire [3:0] m_aregion_i;
wire m_avalid_i;
wire s_aready_i;
wire any_error;
wire s_rvalid_i;
wire [C_ID_WIDTH-1:0] s_rid_i;
wire s_rlast_i;
wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;
wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;
wire [(C_NUM_M+1)-1:0] m_rvalid_qual;
wire [(C_NUM_M+1)-1:0] m_rready_arb;
wire [(C_NUM_M+1)-1:0] m_rready_i;
wire target_secure;
wire target_axilite;
wire m_avalid_qual_i;
wire [7:0] m_aerror_i;
genvar gen_mi;
genvar gen_thread;
generate
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_8_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_M),
.C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_BASE_ADDR),
.C_HIGH_ADDR (C_HIGH_ADDR),
.C_TARGET_QUAL (C_TARGET_QUAL),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (S_AADDR),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign target_mi_enc = 0;
assign match = 1'b1;
assign target_region = 4'b0000;
end
endgenerate
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_axilite = |(target_mi_hot & P_M_AXILITE);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) ||
(S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[7:3] = 5'b00000; // Reserved
assign M_ATARGET_HOT = m_atarget_hot_i;
assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});
assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);
assign M_AVALID = m_avalid_i;
assign m_avalid_i = S_AVALID;
assign M_AVALID_QUAL = m_avalid_qual_i;
assign S_AREADY = s_aready_i;
assign s_aready_i = M_AREADY;
assign M_AERROR = m_aerror_i;
assign M_ATARGET_ENC = m_atarget_enc_i;
assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;
// assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;
assign M_AREGION = m_aregion_i;
assign M_AID = S_AID;
assign M_AADDR = S_AADDR;
assign M_ALEN = S_ALEN;
assign M_ASIZE = S_ASIZE;
assign M_ALOCK = S_ALOCK;
assign M_APROT = S_APROT;
assign M_AMESG = S_AMESG;
assign S_RVALID = s_rvalid_i;
assign M_RREADY = m_rready_i;
assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];
assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];
assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];
assign S_RID = s_rid_i;
assign S_RLAST = s_rlast_i;
assign m_rvalid_qual = M_RVALID & M_RTARGET;
assign m_rready_i = m_rready_arb & M_RTARGET;
generate
for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {
M_RLAST[gen_mi],
M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],
M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]
};
end // gen_rmesg_mi
if (C_ACCEPTANCE == 1) begin : gen_single_issue
wire cmd_push;
wire cmd_pop;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 1'b0;
active_target_enc <= 0;
active_target_hot <= 0;
end else begin
if (cmd_push) begin
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
accept_cnt <= 1'b1;
end else if (cmd_pop) begin
accept_cnt <= 1'b0;
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_issue
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_issue
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_6_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_issue
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread
wire s_avalid_en;
wire cmd_push;
wire cmd_pop;
reg [C_ID_WIDTH-1:0] active_id;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg [4-1:0] active_region;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
wire accept_limit ;
// Implement single-region-per-ID cyclic dependency avoidance method.
assign s_avalid_en = // This transaction is qualified to request arbitration if ...
(accept_cnt == 0) || // Either there are no outstanding transactions, or ...
(((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ...
(active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ...
(active_region == m_aregion_i)); // and to the same REGION.
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = s_avalid_en & ~accept_limit;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
active_id <= 0;
active_target_enc <= 0;
active_target_hot <= 0;
active_region <= 0;
end else begin
if (cmd_push) begin
active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
active_region <= m_aregion_i;
if (~cmd_pop) begin
accept_cnt <= accept_cnt + 1;
end
end else begin
if (cmd_pop & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_thread
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_6_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else begin : gen_multi_thread
wire [(P_NUM_M_DE_LOG)-1:0] resp_select;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
wire [P_NUM_THREADS-1:0] s_avalid_en;
wire [P_NUM_THREADS-1:0] thread_valid;
wire [P_NUM_THREADS-1:0] aid_match;
wire [P_NUM_THREADS-1:0] rid_match;
wire [P_NUM_THREADS-1:0] cmd_push;
wire [P_NUM_THREADS-1:0] cmd_pop;
wire [P_NUM_THREADS:0] accum_push;
reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;
reg [P_NUM_THREADS*8-1:0] active_target;
reg [P_NUM_THREADS*8-1:0] active_region;
reg [P_NUM_THREADS*8-1:0] active_cnt;
reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;
wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;
wire any_aid_match;
wire any_rid_match;
wire accept_limit;
wire any_push;
wire any_pop;
axi_crossbar_v2_1_8_arbiter_resp # // Multi-thread response arbiter
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_M+1),
.C_NUM_S_LOG (P_NUM_M_DE_LOG),
.C_GRANT_ENC (1),
.C_GRANT_HOT (0)
)
arbiter_resp_inst
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_VALID (m_rvalid_qual),
.S_READY (m_rready_arb),
.M_GRANT_HOT (),
.M_GRANT_ENC (resp_select),
.M_VALID (s_rvalid_i),
.M_READY (S_RREADY)
);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_multi_thread
(
.S (resp_select),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
assign any_push = M_AREADY;
assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.
assign any_aid_match = |aid_match;
assign any_rid_match = |rid_match;
assign accum_push[0] = 1'b0;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
end else begin
if (any_push & ~any_pop) begin
accept_cnt <= accept_cnt + 1;
end else if (any_pop & ~any_push & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end // Clocked process
for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop
assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);
assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if
thread_valid[gen_thread] && // this thread slot is not vacant, and
((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread.
assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if
(~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or
((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and
(m_aregion_i == active_region[gen_thread*8+:4])); // to the same region.
// cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.
assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];
assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));
// cmd_pop points to the position of the active thread that matches the current RID.
assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);
assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];
always @(posedge ACLK) begin
if (ARESET) begin
active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;
active_target[gen_thread*8+:8] <= 0;
active_region[gen_thread*8+:8] <= 0;
active_cnt[gen_thread*8+:8] <= 0;
end else begin
if (cmd_push[gen_thread]) begin
active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;
active_region[gen_thread*8+:4] <= m_aregion_i;
if (~cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;
end
end else if (cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;
end
end
end // Clocked process
if (C_DEBUG) begin : gen_debug_r_multi_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;
end
end
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_6_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_multi_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push[gen_thread]),
.S_READY (),
.M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]),
.M_VALID (),
.M_READY (cmd_pop[gen_thread])
);
end // gen_debug_r_multi_thread
end // Next gen_thread_loop
end // thread control
endgenerate
endmodule
`default_nettype wire
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_regs.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Registers of the uart 16550 core ////
//// ////
//// Known problems (limits): ////
//// Inserts 1 wait state in all WISHBONE transfers ////
//// ////
//// To Do: ////
//// Nothing or verification. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: (See log for the revision history ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_regs.v,v $
// Revision 1.42 2004/11/22 09:21:59 igorm
// Timeout interrupt should be generated only when there is at least ony
// character in the fifo.
//
// Revision 1.41 2004/05/21 11:44:41 tadejm
// Added synchronizer flops for RX input.
//
// Revision 1.40 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.39 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.38 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.37 2001/12/27 13:24:09 mohor
// lsr[7] was not showing overrun errors.
//
// Revision 1.36 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.35 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.34 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.33 2001/12/17 10:14:43 mohor
// Things related to msr register changed. After THRE IRQ occurs, and one
// character is written to the transmit fifo, the detection of the THRE bit in the
// LSR is delayed for one character time.
//
// Revision 1.32 2001/12/14 13:19:24 mohor
// MSR register fixed.
//
// Revision 1.31 2001/12/14 10:06:58 mohor
// After reset modem status register MSR should be reset.
//
// Revision 1.30 2001/12/13 10:09:13 mohor
// thre irq should be cleared only when being source of interrupt.
//
// Revision 1.29 2001/12/12 09:05:46 mohor
// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
//
// Revision 1.28 2001/12/10 19:52:41 gorban
// Scratch register added
//
// Revision 1.27 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.26 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.25 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.24 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.23 2001/11/12 21:57:29 gorban
// fixed more typo bugs
//
// Revision 1.22 2001/11/12 15:02:28 mohor
// lsr1r error fixed.
//
// Revision 1.21 2001/11/12 14:57:27 mohor
// ti_int_pnd error fixed.
//
// Revision 1.20 2001/11/12 14:50:27 mohor
// ti_int_d error fixed.
//
// Revision 1.19 2001/11/10 12:43:21 gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.18 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.17 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.16 2001/11/02 09:55:16 mohor
// no message
//
// Revision 1.15 2001/10/31 15:19:22 gorban
// Fixes to break and timeout conditions
//
// Revision 1.14 2001/10/29 17:00:46 gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.13 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.12 2001/10/19 16:21:40 gorban
// Changes data_out to be synchronous again as it should have been.
//
// Revision 1.11 2001/10/18 20:35:45 gorban
// small fix
//
// Revision 1.10 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.9 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.10 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.9 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.8 2001/05/29 20:05:04 gorban
// Fixed some bugs and synthesis problems.
//
// Revision 1.7 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.6 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.5 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
`define UART_DL1 7:0
`define UART_DL2 15:8
module uart_regs (clk,
wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
// additional signals
modem_inputs,
stx_pad_o, srx_pad_i,
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface signals enabled
ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,
`endif
rts_pad_o, dtr_pad_o, int_o
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
`endif
);
input clk;
input wb_rst_i;
input [`UART_ADDR_WIDTH-1:0] wb_addr_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_we_i;
input wb_re_i;
output stx_pad_o;
input srx_pad_i;
input [3:0] modem_inputs;
output rts_pad_o;
output dtr_pad_o;
output int_o;
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
`endif
`ifdef DATA_BUS_WIDTH_8
`else
// if 32-bit databus and debug interface are enabled
output [3:0] ier;
output [3:0] iir;
output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
output [4:0] mcr;
output [7:0] lcr;
output [7:0] msr;
output [7:0] lsr;
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
output [`UART_FIFO_COUNTER_W-1:0] tf_count;
output [2:0] tstate;
output [3:0] rstate;
`endif
wire [3:0] modem_inputs;
reg enable;
`ifdef UART_HAS_BAUDRATE_OUTPUT
assign baud_o = enable; // baud_o is actually the enable signal
`endif
wire stx_pad_o; // received from transmitter module
wire srx_pad_i;
wire srx_pad;
reg [7:0] wb_dat_o;
wire [`UART_ADDR_WIDTH-1:0] wb_addr_i;
wire [7:0] wb_dat_i;
reg [3:0] ier;
reg [3:0] iir;
reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
reg [4:0] mcr;
reg [7:0] lcr;
reg [7:0] msr;
reg [15:0] dl; // 32-bit divisor latch
reg [7:0] scratch; // UART scratch register
reg start_dlc; // activate dlc on writing to UART_DL1
reg lsr_mask_d; // delay for lsr_mask condition
reg msi_reset; // reset MSR 4 lower bits indicator
//reg threi_clear; // THRE interrupt clear flag
reg [15:0] dlc; // 32-bit divisor latch counter
reg int_o;
reg [3:0] trigger_level; // trigger level of the receiver FIFO
reg rx_reset;
reg tx_reset;
wire dlab; // divisor latch access bit
wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
wire loopback; // loopback bit (MCR bit 4)
wire cts, dsr, ri, dcd; // effective signals
wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
wire rts_pad_o, dtr_pad_o; // modem control outputs
// LSR bits wires and regs
wire [7:0] lsr;
wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
wire lsr_mask; // lsr_mask
//
// ASSINGS
//
assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
: {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign dlab = lcr[`UART_LC_DL];
assign loopback = mcr[4];
// assign modem outputs
assign rts_pad_o = mcr[`UART_MC_RTS];
assign dtr_pad_o = mcr[`UART_MC_DTR];
// Interrupt signals
wire rls_int; // receiver line status interrupt
wire rda_int; // receiver data available interrupt
wire ti_int; // timeout indicator interrupt
wire thre_int; // transmitter holding register empty interrupt
wire ms_int; // modem status interrupt
// FIFO signals
reg tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire [9:0] counter_t;
wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
reg [7:0] block_value; // One character length minus stop bit
// Transmitter Instance
wire serial_out;
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
// Synchronizing and sampling serial RX input
uart_sync_flops i_uart_sync_flops
(
.rst_i (wb_rst_i),
.clk_i (clk),
.stage1_rst_i (1'b0),
.stage1_clk_en_i (1'b1),
.async_dat_i (srx_pad_i),
.sync_dat_o (srx_pad)
);
defparam i_uart_sync_flops.width = 1;
defparam i_uart_sync_flops.init_value = 1'b1;
// handle loopback
wire serial_in = loopback ? serial_out : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : serial_out;
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
// Asynchronous reading here because the outputs are sampled in uart_wb.v file
always @(dl or dlab or ier or iir or scratch
or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
begin
case (wb_addr_i)
`UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
`UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
`UART_REG_II : wb_dat_o = {4'b1100,iir};
`UART_REG_LC : wb_dat_o = lcr;
`UART_REG_LS : wb_dat_o = lsr;
`UART_REG_MS : wb_dat_o = msr;
`UART_REG_SR : wb_dat_o = scratch;
default: wb_dat_o = 8'b0; // ??
endcase // case(wb_addr_i)
end // always @ (dl or dlab or ier or iir or scratch...
// rf_pop signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
rf_pop <= #1 0;
else
if (rf_pop) // restore the signal to 0 after one clock cycle
rf_pop <= #1 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
rf_pop <= #1 1; // advance read pointer
end
wire lsr_mask_condition;
wire iir_read;
wire msr_read;
wire fifo_read;
wire fifo_write;
assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
// lsr_mask_d delayed signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
lsr_mask_d <= #1 0;
else // reset bits in the Line Status Register
lsr_mask_d <= #1 lsr_mask_condition;
end
// lsr_mask is rise detected
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
// msi_reset signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
msi_reset <= #1 1;
else
if (msi_reset)
msi_reset <= #1 0;
else
if (msr_read)
msi_reset <= #1 1; // reset bits in Modem Status Register
end
//
// WRITES AND RESETS //
//
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
lcr <= #1 8'b00000011; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_LC)
lcr <= #1 wb_dat_i;
// Interrupt Enable Register or UART_DL2
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
ier <= #1 4'b0000; // no interrupts after reset
dl[`UART_DL2] <= #1 8'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_IE)
if (dlab)
begin
dl[`UART_DL2] <= #1 wb_dat_i;
end
else
ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb
// FIFO Control Register and rx_reset, tx_reset signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
fcr <= #1 2'b11;
rx_reset <= #1 0;
tx_reset <= #1 0;
end else
if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
fcr <= #1 wb_dat_i[7:6];
rx_reset <= #1 wb_dat_i[1];
tx_reset <= #1 wb_dat_i[2];
end else begin
rx_reset <= #1 0;
tx_reset <= #1 0;
end
// Modem Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
mcr <= #1 5'b0;
else
if (wb_we_i && wb_addr_i==`UART_REG_MC)
mcr <= #1 wb_dat_i[4:0];
// Scratch register
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
scratch <= #1 0; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_SR)
scratch <= #1 wb_dat_i;
// TX_FIFO or UART_DL1
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
dl[`UART_DL1] <= #1 8'b0;
tf_push <= #1 1'b0;
start_dlc <= #1 1'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_TR)
if (dlab)
begin
dl[`UART_DL1] <= #1 wb_dat_i;
start_dlc <= #1 1'b1; // enable DL counter
tf_push <= #1 1'b0;
end
else
begin
tf_push <= #1 1'b1;
start_dlc <= #1 1'b0;
end // else: !if(dlab)
else
begin
start_dlc <= #1 1'b0;
tf_push <= #1 1'b0;
end // else: !if(dlab)
// Receiver FIFO trigger level selection logic (asynchronous mux)
always @(fcr)
case (fcr[`UART_FC_TL])
2'b00 : trigger_level = 1;
2'b01 : trigger_level = 4;
2'b10 : trigger_level = 8;
2'b11 : trigger_level = 14;
endcase // case(fcr[`UART_FC_TL])
//
// STATUS REGISTERS //
//
// Modem Status Register
reg [3:0] delayed_modem_signals;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
msr <= #1 0;
delayed_modem_signals[3:0] <= #1 0;
end
else begin
msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c};
delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts};
end
end
// Line Status Register
// activation conditions
assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
assign lsr1 = rf_overrun; // Receiver overrun error
assign lsr2 = rf_data_out[1]; // parity error bit
assign lsr3 = rf_data_out[0]; // framing error bit
assign lsr4 = rf_data_out[2]; // break error in the character
assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
assign lsr7 = rf_error_bit | rf_overrun;
// lsr bit0 (receiver data available)
reg lsr0_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0_d <= #1 0;
else lsr0_d <= #1 lsr0;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0r <= #1 0;
else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition
lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
// lsr bit 1 (receiver overrun)
reg lsr1_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1_d <= #1 0;
else lsr1_d <= #1 lsr1;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1r <= #1 0;
else lsr1r <= #1 lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
// lsr bit 2 (parity error)
reg lsr2_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2_d <= #1 0;
else lsr2_d <= #1 lsr2;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2r <= #1 0;
else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
// lsr bit 3 (framing error)
reg lsr3_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3_d <= #1 0;
else lsr3_d <= #1 lsr3;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3r <= #1 0;
else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
// lsr bit 4 (break indicator)
reg lsr4_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4_d <= #1 0;
else lsr4_d <= #1 lsr4;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4r <= #1 0;
else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
// lsr bit 5 (transmitter fifo is empty)
reg lsr5_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5_d <= #1 1;
else lsr5_d <= #1 lsr5;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5r <= #1 1;
else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
// lsr bit 6 (transmitter empty indicator)
reg lsr6_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6_d <= #1 1;
else lsr6_d <= #1 lsr6;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6r <= #1 1;
else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
// lsr bit 7 (error in fifo)
reg lsr7_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7_d <= #1 0;
else lsr7_d <= #1 lsr7;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7r <= #1 0;
else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
// Frequency divider
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
dlc <= #1 0;
else
if (start_dlc | ~ (|dlc))
dlc <= #1 dl - 1; // preset counter
else
dlc <= #1 dlc - 1; // decrement counter
end
// Enable signal generation logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
enable <= #1 1'b0;
else
if (|dl & ~(|dlc)) // dl>0 & dlc==0
enable <= #1 1'b1;
else
enable <= #1 1'b0;
end
// Delaying THRE status for one character cycle after a character is written to an empty fifo.
always @(lcr)
case (lcr[3:0])
4'b0000 : block_value = 95; // 6 bits
4'b0100 : block_value = 103; // 6.5 bits
4'b0001, 4'b1000 : block_value = 111; // 7 bits
4'b1100 : block_value = 119; // 7.5 bits
4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits
4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits
4'b1111 : block_value = 175; // 11 bits
endcase // case(lcr[3:0])
// Counting time of one character minus stop bit
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
block_cnt <= #1 8'd0;
else
if(lsr5r & fifo_write) // THRE bit set & write to fifo occured
block_cnt <= #1 block_value;
else
if (enable & block_cnt != 8'b0) // only work on enable times
block_cnt <= #1 block_cnt - 1; // decrement break counter
end // always of break condition detection
// Generating THRE status enable signal
assign thre_set_en = ~(|block_cnt);
//
// INTERRUPT LOGIC
//
assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]);
assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
reg rls_int_d;
reg thre_int_d;
reg ms_int_d;
reg ti_int_d;
reg rda_int_d;
// delay lines
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_d <= #1 0;
else rls_int_d <= #1 rls_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_d <= #1 0;
else rda_int_d <= #1 rda_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_d <= #1 0;
else thre_int_d <= #1 thre_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_d <= #1 0;
else ms_int_d <= #1 ms_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_d <= #1 0;
else ti_int_d <= #1 ti_int;
// rise detection signals
wire rls_int_rise;
wire thre_int_rise;
wire ms_int_rise;
wire ti_int_rise;
wire rda_int_rise;
assign rda_int_rise = rda_int & ~rda_int_d;
assign rls_int_rise = rls_int & ~rls_int_d;
assign thre_int_rise = thre_int & ~thre_int_d;
assign ms_int_rise = ms_int & ~ms_int_d;
assign ti_int_rise = ti_int & ~ti_int_d;
// interrupt pending flags
reg rls_int_pnd;
reg rda_int_pnd;
reg thre_int_pnd;
reg ms_int_pnd;
reg ti_int_pnd;
// interrupt pending flags assignments
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_pnd <= #1 0;
else
rls_int_pnd <= #1 lsr_mask ? 0 : // reset condition
rls_int_rise ? 1 : // latch condition
rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_pnd <= #1 0;
else
rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 : // reset condition
rda_int_rise ? 1 : // latch condition
rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_pnd <= #1 0;
else
thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
thre_int_rise ? 1 :
thre_int_pnd && ier[`UART_IE_THRE];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_pnd <= #1 0;
else
ms_int_pnd <= #1 msr_read ? 0 :
ms_int_rise ? 1 :
ms_int_pnd && ier[`UART_IE_MS];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_pnd <= #1 0;
else
ti_int_pnd <= #1 fifo_read ? 0 :
ti_int_rise ? 1 :
ti_int_pnd && ier[`UART_IE_RDA];
// end of pending flags
// INT_O logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
int_o <= #1 1'b0;
else
int_o <= #1
rls_int_pnd ? ~lsr_mask :
rda_int_pnd ? 1 :
ti_int_pnd ? ~fifo_read :
thre_int_pnd ? !(fifo_write & iir_read) :
ms_int_pnd ? ~msr_read :
0; // if no interrupt are pending
end
// Interrupt Identification register
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
iir <= #1 1;
else
if (rls_int_pnd) // interrupt is pending
begin
iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value
iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending)
end else // the sequence of conditions determines priority of interrupt identification
if (rda_int)
begin
iir[`UART_II_II] <= #1 `UART_II_RDA;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (ti_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_TI;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (thre_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_THRE;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (ms_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_MS;
iir[`UART_II_IP] <= #1 1'b0;
end else // no interrupt is pending
begin
iir[`UART_II_II] <= #1 0;
iir[`UART_II_IP] <= #1 1'b1;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's WISHBONE BIU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implements WISHBONE interface ////
//// ////
//// To Do: ////
//// - if biu_cyc/stb are deasserted and wb_ack_i is asserted ////
//// and this happens even before aborted_r is asssrted, ////
//// wb_ack_i will be delivered even though transfer is ////
//// internally considered already aborted. However most ////
//// wb_ack_i are externally registered and delayed. Normally ////
//// this shouldn't cause any problems. ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/12/05 00:12:08 lampret
// New wb_biu for iwb interface.
//
// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.6 2003/04/07 20:57:46 lampret
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
//
// Revision 1.5 2002/12/08 08:57:56 lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
// Revision 1.4 2002/09/16 03:09:16 lampret
// Fixed a combinational loop.
//
// Revision 1.3 2002/08/12 05:31:37 lampret
// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
//
// Revision 1.2 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12 2001/11/22 13:42:51 lampret
// Added wb_cyc_o assignment after it was removed by accident.
//
// Revision 1.11 2001/11/20 21:28:10 lampret
// Added optional sampling of inputs.
//
// Revision 1.10 2001/11/18 11:32:00 lampret
// OR1200_REGISTERED_OUTPUTS can now be enabled.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:23 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_iwb_biu(
// RISC clock, reset and clock control
clk, rst, clmode,
// WISHBONE interface
wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
`ifdef OR1200_WB_CAB
wb_cab_o,
`endif
`ifdef OR1200_WB_B3
wb_cti_o, wb_bte_o,
`endif
// Internal RISC bus
biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
biu_dat_o, biu_ack_o, biu_err_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// RISC clock, reset and clock control
//
input clk; // RISC clock
input rst; // RISC reset
input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
//
// WISHBONE interface
//
input wb_clk_i; // clock input
input wb_rst_i; // reset input
input wb_ack_i; // normal termination
input wb_err_i; // termination w/ error
input wb_rty_i; // termination w/ retry
input [dw-1:0] wb_dat_i; // input data bus
output wb_cyc_o; // cycle valid output
output [aw-1:0] wb_adr_o; // address bus outputs
output wb_stb_o; // strobe output
output wb_we_o; // indicates write transfer
output [3:0] wb_sel_o; // byte select outputs
output [dw-1:0] wb_dat_o; // output data bus
`ifdef OR1200_WB_CAB
output wb_cab_o; // consecutive address burst
`endif
`ifdef OR1200_WB_B3
output [2:0] wb_cti_o; // cycle type identifier
output [1:0] wb_bte_o; // burst type extension
`endif
//
// Internal RISC interface
//
input [dw-1:0] biu_dat_i; // input data bus
input [aw-1:0] biu_adr_i; // address bus
input biu_cyc_i; // WB cycle
input biu_stb_i; // WB strobe
input biu_we_i; // WB write enable
input biu_cab_i; // CAB input
input [3:0] biu_sel_i; // byte selects
output [31:0] biu_dat_o; // output data bus
output biu_ack_o; // ack output
output biu_err_o; // err output
//
// Registers
//
reg [1:0] valid_div; // Used for synchronization
`ifdef OR1200_REGISTERED_OUTPUTS
reg [aw-1:0] wb_adr_o; // address bus outputs
reg wb_cyc_o; // cycle output
reg wb_stb_o; // strobe output
reg wb_we_o; // indicates write transfer
reg [3:0] wb_sel_o; // byte select outputs
`ifdef OR1200_WB_CAB
reg wb_cab_o; // CAB output
`endif
`ifdef OR1200_WB_B3
reg [1:0] burst_len; // burst counter
reg [2:0] wb_cti_o; // cycle type identifier
`endif
reg [dw-1:0] wb_dat_o; // output data bus
`endif
`ifdef OR1200_REGISTERED_INPUTS
reg long_ack_o; // normal termination
reg long_err_o; // error termination
reg [dw-1:0] biu_dat_o; // output data bus
`else
wire long_ack_o; // normal termination
wire long_err_o; // error termination
`endif
wire aborted; // Graceful abort
reg aborted_r; // Graceful abort
wire retry; // Retry
`ifdef OR1200_WB_RETRY
reg [`OR1200_WB_RETRY-1:0] retry_cntr; // Retry counter
`endif
reg previous_complete;
wire same_addr;
wire repeated_access;
reg repeated_access_ack;
reg [dw-1:0] wb_dat_r; // saved previous data read
//
// WISHBONE I/F <-> Internal RISC I/F conversion
//
//
// Address bus
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_adr_o <= #1 {aw{1'b0}};
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i) | biu_cab_i & (previous_complete | biu_ack_o))
wb_adr_o <= #1 biu_adr_i;
`else
assign wb_adr_o = biu_adr_i;
`endif
//
// Same access as previous one, store previous read data
//
assign same_addr = wb_adr_o == biu_adr_i;
assign repeated_access = same_addr & previous_complete;
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_r <= #1 32'h0000_0000;
else if (wb_ack_i)
wb_dat_r <= #1 wb_dat_i;
always @(posedge clk or posedge rst)
if (rst)
repeated_access_ack <= #1 1'b0;
else if (repeated_access & biu_cyc_i & biu_stb_i)
repeated_access_ack <= #1 1'b1;
else
repeated_access_ack <= #1 1'b0;
//
// Previous access completed
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
previous_complete <= #1 1'b1;
else if (wb_ack_i & biu_cyc_i & biu_stb_i)
previous_complete <= #1 1'b1;
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i))
previous_complete <= #1 1'b0;
//
// Input data bus
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
biu_dat_o <= #1 32'h0000_0000;
else if (wb_ack_i)
biu_dat_o <= #1 wb_dat_i;
`else
assign biu_dat_o = repeated_access_ack ? wb_dat_r : wb_dat_i;
`endif
//
// Output data bus
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= #1 {dw{1'b0}};
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted)
wb_dat_o <= #1 biu_dat_i;
`else
assign wb_dat_o = biu_dat_i;
`endif
//
// Valid_div counts RISC clock cycles by modulo 4
// and is used to synchronize external WB i/f to
// RISC clock
//
always @(posedge clk or posedge rst)
if (rst)
valid_div <= #1 2'b0;
else
valid_div <= #1 valid_div + 1'd1;
//
// biu_ack_o is one RISC clock cycle long long_ack_o.
// long_ack_o is one, two or four RISC clock cycles long because
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
//
assign biu_ack_o = (repeated_access_ack | long_ack_o) & ~aborted_r
`ifdef OR1200_CLKDIV_2_SUPPORTED
& (valid_div[0] | ~clmode[0])
`ifdef OR1200_CLKDIV_4_SUPPORTED
& (valid_div[1] | ~clmode[1])
`endif
`endif
;
//
// Acknowledgment of the data to the RISC
//
// long_ack_o
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
long_ack_o <= #1 1'b0;
else
long_ack_o <= #1 wb_ack_i & ~aborted;
`else
assign long_ack_o = wb_ack_i;
`endif
//
// biu_err_o is one RISC clock cycle long long_err_o.
// long_err_o is one, two or four RISC clock cycles long because
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
//
assign biu_err_o = long_err_o
`ifdef OR1200_CLKDIV_2_SUPPORTED
& (valid_div[0] | ~clmode[0])
`ifdef OR1200_CLKDIV_4_SUPPORTED
& (valid_div[1] | ~clmode[1])
`endif
`endif
;
//
// Error termination
//
// long_err_o
//
`ifdef OR1200_REGISTERED_INPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
long_err_o <= #1 1'b0;
else
long_err_o <= #1 wb_err_i & ~aborted;
`else
assign long_err_o = wb_err_i & ~aborted_r;
`endif
//
// Retry counter
//
// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high
// until retry counter doesn't expire
//
`ifdef OR1200_WB_RETRY
assign retry = wb_rty_i | (|retry_cntr);
`else
assign retry = 1'b0;
`endif
`ifdef OR1200_WB_RETRY
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
retry_cntr <= #1 1'b0;
else if (wb_rty_i)
retry_cntr <= #1 {`OR1200_WB_RETRY{1'b1}};
else if (retry_cntr)
retry_cntr <= #1 retry_cntr - 7'd1;
`endif
//
// Graceful completion of aborted transfers
//
// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which
// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle
// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and
// there is no termination of current transfer in this WB clock cycle (wb_ack_i
// and wb_err_i are low).
// 'aborted_r' is registered 'aborted' and extended until this "aborted" transfer
// is properly terminated with wb_ack_i/wb_err_i.
//
assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i);
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
aborted_r <= #1 1'b0;
else if (wb_ack_i | wb_err_i)
aborted_r <= #1 1'b0;
else if (aborted)
aborted_r <= #1 1'b1;
//
// WB cyc_o
//
// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if
// bursts are enabled) and possibly suspended by 'retry'
// or 2) extended "aborted" transfer
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_cyc_o <= #1 1'b0;
else
`ifdef OR1200_NO_BURSTS
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access | aborted & ~wb_ack_i;
`else
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry & ~repeated_access | biu_cab_i | aborted & ~wb_ack_i;
`endif
`else
`ifdef OR1200_NO_BURSTS
assign wb_cyc_o = biu_cyc_i & ~retry;
`else
assign wb_cyc_o = biu_cyc_i | biu_cab_i & ~retry;
`endif
`endif
//
// WB stb_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_stb_o <= #1 1'b0;
else
wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry & ~repeated_access | aborted & ~wb_ack_i;
`else
assign wb_stb_o = biu_cyc_i & biu_stb_i;
`endif
//
// WB we_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_we_o <= #1 1'b0;
else
wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i | aborted & wb_we_o;
`else
assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
`endif
//
// WB sel_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_sel_o <= #1 4'b0000;
else
wb_sel_o <= #1 biu_sel_i;
`else
assign wb_sel_o = biu_sel_i;
`endif
`ifdef OR1200_WB_CAB
//
// WB cab_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_cab_o <= #1 1'b0;
else
wb_cab_o <= #1 biu_cab_i;
`else
assign wb_cab_o = biu_cab_i;
`endif
`endif
`ifdef OR1200_WB_B3
//
// Count burst beats
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
burst_len <= #1 2'b00;
else if (biu_cab_i && burst_len && wb_ack_i)
burst_len <= #1 burst_len - 1'b1;
else if (~biu_cab_i)
burst_len <= #1 2'b11;
//
// WB cti_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_cti_o <= #1 3'b000; // classic cycle
`ifdef OR1200_NO_BURSTS
else
wb_cti_o <= #1 3'b111; // end-of-burst
`else
else if (biu_cab_i && burst_len[1])
wb_cti_o <= #1 3'b010; // incrementing burst cycle
else if (biu_cab_i && wb_ack_i)
wb_cti_o <= #1 3'b111; // end-of-burst
`endif // OR1200_NO_BURSTS
`else
Unsupported !!!;
`endif
//
// WB bte_o
//
assign wb_bte_o = 2'b01; // 4-beat wrap burst
`endif // OR1200_WB_B3
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module combines two video streams by overlaying one onto the *
* other using alpha blending. The foreground image must include alpha *
* bits to be used in the blending formula: Cn = (1 - a)Cb + (a)Cf *
* Cn - new color *
* a - alpha *
* Cb - background colour *
* Cf - foreground colour *
* *
******************************************************************************/
module altera_up_video_alpha_blender_normal (
// Inputs
background_data,
foreground_data,
// Bidirectionals
// Outputs
new_red,
new_green,
new_blue
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [29: 0] background_data;
input [39: 0] foreground_data;
// Bidirectionals
// Outputs
output [ 9: 0] new_red;
output [ 9: 0] new_green;
output [ 9: 0] new_blue;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] one_minus_a;
wire [17: 0] r_x_alpha;
wire [17: 0] g_x_alpha;
wire [17: 0] b_x_alpha;
wire [17: 0] r_x_one_minus_alpha;
wire [17: 0] g_x_one_minus_alpha;
wire [17: 0] b_x_one_minus_alpha;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign new_red = {1'b0, r_x_alpha[17:9]} +
{1'b0, r_x_one_minus_alpha[17:9]};
assign new_green = {1'b0, g_x_alpha[17:9]} +
{1'b0, g_x_one_minus_alpha[17:9]};
assign new_blue = {1'b0, b_x_alpha[17:9]} +
{1'b0, b_x_one_minus_alpha[17:9]};
// Internal Assignments
assign one_minus_a = 10'h3FF - foreground_data[39:30];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
lpm_mult r_times_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (foreground_data[29:21]),
.datab (foreground_data[39:31]),
// Outputs
.result (r_x_alpha)
);
defparam
r_times_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
r_times_alpha.lpm_representation = "UNSIGNED",
r_times_alpha.lpm_type = "LPM_MULT",
r_times_alpha.lpm_widtha = 9,
r_times_alpha.lpm_widthb = 9,
r_times_alpha.lpm_widthp = 18;
lpm_mult g_times_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (foreground_data[19:11]),
.datab (foreground_data[39:31]),
// Outputs
.result (g_x_alpha)
);
defparam
g_times_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
g_times_alpha.lpm_representation = "UNSIGNED",
g_times_alpha.lpm_type = "LPM_MULT",
g_times_alpha.lpm_widtha = 9,
g_times_alpha.lpm_widthb = 9,
g_times_alpha.lpm_widthp = 18;
lpm_mult b_times_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (foreground_data[ 9: 1]),
.datab (foreground_data[39:31]),
// Outputs
.result (b_x_alpha)
);
defparam
b_times_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
b_times_alpha.lpm_representation = "UNSIGNED",
b_times_alpha.lpm_type = "LPM_MULT",
b_times_alpha.lpm_widtha = 9,
b_times_alpha.lpm_widthb = 9,
b_times_alpha.lpm_widthp = 18;
lpm_mult r_times_one_minus_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (background_data[29:21]),
.datab (one_minus_a[ 9: 1]),
// Outputs
.result (r_x_one_minus_alpha)
);
defparam
r_times_one_minus_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
r_times_one_minus_alpha.lpm_representation = "UNSIGNED",
r_times_one_minus_alpha.lpm_type = "LPM_MULT",
r_times_one_minus_alpha.lpm_widtha = 9,
r_times_one_minus_alpha.lpm_widthb = 9,
r_times_one_minus_alpha.lpm_widthp = 18;
lpm_mult g_times_one_minus_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (background_data[19:11]),
.datab (one_minus_a[ 9: 1]),
// Outputs
.result (g_x_one_minus_alpha)
);
defparam
g_times_one_minus_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
g_times_one_minus_alpha.lpm_representation = "UNSIGNED",
g_times_one_minus_alpha.lpm_type = "LPM_MULT",
g_times_one_minus_alpha.lpm_widtha = 9,
g_times_one_minus_alpha.lpm_widthb = 9,
g_times_one_minus_alpha.lpm_widthp = 18;
lpm_mult b_times_one_minus_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (background_data[ 9: 1]),
.datab (one_minus_a[ 9: 1]),
// Outputs
.result (b_x_one_minus_alpha)
);
defparam
b_times_one_minus_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
b_times_one_minus_alpha.lpm_representation = "UNSIGNED",
b_times_one_minus_alpha.lpm_type = "LPM_MULT",
b_times_one_minus_alpha.lpm_widtha = 9,
b_times_one_minus_alpha.lpm_widthb = 9,
b_times_one_minus_alpha.lpm_widthp = 18;
endmodule
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
module top (
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_proxy (
.I(clk),
.O(ibuf_proxy_out)
);
IBUF ibuf_inst (
.I(ibuf_proxy_out),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int_2 = clk_int_1;
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
middle middle_inst_1 (
.clk(ibuf_out),
.out(out[2])
);
middle middle_inst_2 (
.clk(clk_int_1),
.out(out[3])
);
middle middle_inst_3 (
.clk(clk_int_2),
.out(out[4])
);
middle middle_inst_4 (
.clk(clk2),
.out(out[5])
);
assign out[1:0] = {cnt[0], in[0]};
endmodule
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
|
(*
Copyright © 2007-2008 Russell O’Connor
Permission is hereby granted, free of charge, to any person obtaining a copy of
this proof and associated documentation files (the "Proof"), to deal in
the Proof without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
the Proof, and to permit persons to whom the Proof is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Proof.
THE PROOF IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE PROOF OR THE USE OR OTHER DEALINGS IN THE PROOF.
*)
Require Export RSetoid.
Require Export StepFunction.
Require Import OpenUnit.
Require Import CornTac.
Require Import Qauto.
Require Import Qordfield.
Require Import COrdFields.
Set Implicit Arguments.
Set Automatic Introduction.
Open Local Scope Q_scope.
Section StepF_Functions.
Variable X : RSetoid.
(**
** Step Functions over setoids
In this section we redevelop step functions over a setoid X.
Here we shadow the old Step Function operations to operate over
setoids.
*)
Definition StepF := StepF X.
(** We lift the constructors and destructors to the setoid version *)
Definition constStepF : X -> StepF := (@constStepF X).
Definition glue : OpenUnit -> StepF -> StepF -> StepF := (@glue X).
Lemma StepF_ind : forall (P : StepF -> Prop),
(forall x : X, P (constStepF x)) ->
(forall (o : OpenUnit) (s : StepF),
P s -> forall s0 : StepF, P s0 -> P (glue o s s0)) ->
forall s : StepF, P s.
Proof.
intros P H0 H1 s.
induction s.
apply H0.
apply H1; auto.
Qed.
Definition StepFfold : forall Y, (X -> Y) -> (OpenUnit -> Y -> Y -> Y) -> StepF -> Y := (@StepFfold X).
Definition Mirror : StepF -> StepF := (@Mirror X).
Definition SplitL : StepF -> OpenUnit -> StepF := (@SplitL X).
Definition SplitR : StepF -> OpenUnit -> StepF := (@SplitR X).
End StepF_Functions.
(* begin hide *)
Implicit Arguments constStepF [X].
(* end hide *)
Open Local Scope setoid_scope.
(** We lift ap to the setoid version. Map is a notation calling ap so
that all lemmas about ap automatically apply to ap *)
Definition Ap (X Y : RSetoid) : (StepF (X --> Y))->(StepF X)->(StepF Y) := fun f x => (@Ap X Y (StepFunction.Map (@evalMorphism X Y) f) x).
Notation "f <@> x" := (Ap f x) (at level 15, left associativity) : sfstscope.
Notation "f ^@> x" := (Ap (constStepF f) x) (at level 15, left associativity) : sfstscope.
Notation "f <@^ x" := (Ap f (constStepF x)) (at level 15, left associativity) : sfstscope.
Open Local Scope sfstscope.
(** We lift lemmas about map, ap, mirror, and glue *)
Lemma MirrorGlue : forall (X : RSetoid) (o : OpenUnit) (al ar : StepF X),
Mirror (glue o al ar) = glue (OpenUnitDual o) (Mirror ar) (Mirror al).
Proof.
reflexivity.
Qed.
Lemma MapGlue : forall (X Y : RSetoid) (f : (X --> Y))
(o : OpenUnit) (al ar : StepF X),
f ^@> (glue o al ar) = glue o (f ^@> al) (f ^@> ar).
Proof.
reflexivity.
Qed.
Lemma ApGlue : forall (X Y : RSetoid) (fl fr : StepF (X --> Y))
(o : OpenUnit) (b : StepF X),
(glue o fl fr) <@> b = glue o (fl <@> (SplitL b o)) (fr <@> (SplitR b o)).
Proof.
intros X Y fl fr o b.
unfold Ap.
simpl (StepFunction.Map (@evalMorphism X Y) (glue o fl fr)).
rewrite ApGlue.
reflexivity.
Qed.
Lemma ApGlueGlue : forall (X Y : RSetoid) (fl fr : StepF (X --> Y)) (o : OpenUnit) (l r : StepF X),
(glue o fl fr) <@> (glue o l r) = glue o (fl <@> l) (fr <@> r).
Proof.
intros X Y fl fr o l r.
unfold Ap.
simpl (StepFunction.Map (@evalMorphism X Y) (glue o fl fr)).
unfold glue.
rewrite ApGlueGlue.
reflexivity.
Qed.
Lemma SplitLGlue : forall (X : RSetoid) (x y : StepF X) (o : OpenUnit),
SplitL (glue o x y) o = x.
Proof.
intros X.
exact (@SplitLGlue X).
Qed.
Lemma SplitRGlue : forall (X : RSetoid) (x y : StepF X) (o : OpenUnit),
SplitR (glue o x y) o = y.
Proof.
intros X.
exact (@SplitRGlue X).
Qed.
Lemma SplitLR_glue_ind : forall (X : RSetoid) (s1 s2 : StepF X) (a b : OpenUnit)
(P : StepF X -> StepF X -> Prop),
(forall H : a < b,
P (SplitL s1 (OpenUnitDiv a b H)) (glue (OpenUnitDualDiv b a H) (SplitR s1 (OpenUnitDiv a b H)) s2)) ->
(forall H : b < a,
P (glue (OpenUnitDiv b a H) s1 (SplitL s2 (OpenUnitDualDiv a b H))) (SplitR s2 (OpenUnitDualDiv a b H))) ->
(a == b -> P s1 s2) -> P (SplitL (glue b s1 s2) a) (SplitR (glue b s1 s2) a).
Proof.
intros X.
exact (@SplitLR_glue_ind X).
Qed.
Lemma SplitL_glue_ind : forall (X : RSetoid) (s1 s2 : StepF X) (a b : OpenUnit)
(P : StepF X -> Prop),
(forall H : a < b, P (SplitL s1 (OpenUnitDiv a b H))) ->
(forall H : b < a, P (glue (OpenUnitDiv b a H) s1 (SplitL s2 (OpenUnitDualDiv a b H)))) ->
(a == b -> P s1) -> P (SplitL (glue b s1 s2) a).
Proof.
intros X.
exact (@SplitL_glue_ind X).
Qed.
Lemma SplitR_glue_ind : forall (X : RSetoid) (s1 s2 : StepF X) (a b : OpenUnit)
(P : StepF X -> Prop),
(forall H : a < b, P (glue (OpenUnitDualDiv b a H) (SplitR s1 (OpenUnitDiv a b H)) s2)) ->
(forall H : b < a, P (SplitR s2 (OpenUnitDualDiv a b H))) ->
(a == b -> P s2) -> P (SplitR (glue b s1 s2) a).
Proof.
intros X.
exact (@SplitR_glue_ind X).
Qed.
Lemma SplitLMap : forall (X Y : RSetoid) (x : StepF X) (a : OpenUnit) (f : X --> Y),
SplitL (f ^@> x) a = f ^@> (SplitL x a).
Proof.
intros X Y x a f.
unfold Ap, SplitL.
simpl.
rewrite SplitLMap.
reflexivity.
Qed.
Lemma SplitRMap : forall (X Y : RSetoid) (x : StepF X) (a : OpenUnit) (f : X --> Y),
SplitR (f ^@> x) a = f ^@> (SplitR x a).
Proof.
intros X Y x a f.
unfold Ap, SplitR.
simpl.
rewrite SplitRMap.
reflexivity.
Qed.
Section EquivalenceA.
Variable X : RSetoid.
(** A step function over [Prop], a characteristic function, can be
folded into [Prop], which holds for the always true characteristic
function *)
Definition StepFfoldProp : StepF iffSetoid -> Prop := (StepFfold (X:=iffSetoid) (fun x => x ) (fun _ a b => a /\ b )).
Definition st_eqS0 : X -> X --> iffSetoid.
Proof.
intros x.
exists (st_eq x).
abstract ( intros x1 x2 Hx; simpl; rewrite -> Hx; reflexivity).
Defined.
Definition st_eqS : X --> X --> iffSetoid.
Proof.
exists (st_eqS0).
abstract ( intros x1 x2 Hx y; simpl; rewrite -> Hx; reflexivity).
Defined.
(**
** Equivalence
An equivalence relation on step functions is implemented by lifiting
the equivalence relation on the underlying setoid to step functions.
The results is a characteristic function saying where two step functions
are equivalent. The step functions are considered equivalent if this
characteristic function says they are equivalent everywhere.
*)
Definition StepF_eq (f g:StepF X):Prop:=
(StepFfoldProp (st_eqS ^@> f <@> g)).
Notation "x === y" := (StepF_eq x y) (at level 70).
(** With equality defined we can complete the proof that split is the
opposite of glue *)
Lemma glue_StepF_eq:forall (s:StepF X) (s1 s2:StepF X), forall a, s1 === (SplitL s a) -> s2 === (SplitR s a) -> (glue a s1 s2) === s.
Proof.
intros s s1 s2 a H0 H1.
unfold StepF_eq.
rewrite MapGlue.
rewrite ApGlue.
split; assumption.
Qed.
Lemma glue_eq_ind : forall (s1 s2 s:StepF X) a (P:Prop), (s1 === SplitL s a -> s2 === SplitR s a -> P) -> (glue a s1 s2 === s) -> P.
Proof.
intros s1 s2 s a P H H0.
unfold StepF_eq in *.
rewrite -> MapGlue in *.
rewrite ApGlue in H0.
destruct H0.
auto.
Qed.
(** The equivalence relation is reflexive *)
Lemma StepF_eq_refl:forall x : StepF X, x === x.
Proof.
induction x using StepF_ind.
change (st_eq x x).
reflexivity.
apply glue_StepF_eq.
simpl; rewrite SplitLGlue; assumption.
simpl; rewrite SplitRGlue; assumption.
Qed.
(* begin hide *)
Hint Resolve StepF_eq_refl.
(* end hide *)
(** StepF_Qeq is a refinement of any setoid equality *)
Lemma StepF_Qeq_eq : forall (s t:StepF X), (StepF_Qeq s t) -> s === t.
Proof.
induction s using StepF_ind; induction t using StepF_ind; try contradiction; simpl.
intros H.
rewrite H.
auto with *.
intros [H [H0 H1]].
apply glue_StepF_eq.
apply IHs1.
apply SplitL_glue_ind; intros H2; try (elim (Qlt_not_le _ _ H2); rewrite -> H); auto with *.
apply IHs2.
apply SplitR_glue_ind; intros H2; try (elim (Qlt_not_le _ _ H2); rewrite -> H); auto with *.
Qed.
Lemma glueSplit:forall (s : StepF X), forall a, (glue a (SplitL s a) (SplitR s a)) === s.
Proof.
intros s a.
apply glue_StepF_eq; auto with *.
Qed.
End EquivalenceA.
(* begin hide *)
Hint Resolve StepF_eq_refl : sfarith.
(* end hide *)
Notation "x == y" := (StepF_eq x y) (at level 70) : sfstscope.
Section EquivalenceB.
Variable X Y : RSetoid.
Lemma Map_resp_StepF_eq: forall f:X-->Y,
(forall x y, (st_eq x y)-> (st_eq (f x) (f y))) ->
forall s t:(StepF X), s == t -> (f ^@> s) == (f ^@> t).
Proof.
intros f H.
induction s using StepF_ind. induction t using StepF_ind.
unfold StepF_eq, Map2, StepFfoldProp ;simpl;auto with *.
unfold StepF_eq, Map2, StepFfoldProp. simpl; intuition.
intros t H0.
unfold StepF_eq, Map2 in H0.
rewrite MapGlue in H0.
rewrite ApGlue in H0.
unfold StepF_eq, Map2.
repeat rewrite MapGlue.
rewrite ApGlue.
rewrite SplitLMap.
rewrite SplitRMap.
destruct H0 as [H0l H0R].
split.
apply IHs1; auto.
apply IHs2; auto.
Qed.
End EquivalenceB.
Lemma StepFfoldPropglue:forall (y:StepF iffSetoid) o,
StepFfoldProp (glue o (SplitL y o) (SplitR y o)) <-> StepFfoldProp y.
Proof.
induction y using StepF_ind.
unfold StepF_eq, StepFfoldProp.
simpl; tauto.
simpl.
intro o0.
apply SplitLR_glue_ind; intros H.
generalize (IHy1 (OpenUnitDiv o0 o H)).
unfold StepFfoldProp; simpl; tauto.
generalize (IHy2 (OpenUnitDualDiv o0 o H)).
unfold StepFfoldProp; simpl; tauto.
simpl.
reflexivity.
Qed.
Lemma StepFfoldProp_morphism:forall x y:(StepF iffSetoid),
(StepF_eq x y) ->
((StepFfoldProp x)<->(StepFfoldProp y)).
Proof.
induction x using StepF_ind. induction y using StepF_ind.
auto with *.
unfold StepF_eq. simpl. unfold StepFfoldProp;simpl;intuition.
intros y H0.
unfold StepF_eq, Map2 in H0.
rewrite MapGlue in H0.
rewrite ApGlue in H0.
destruct H0 as [H0l H0r].
change ((StepFfoldProp x1 /\ StepFfoldProp x2) <-> StepFfoldProp y).
rewrite -> (IHx1 (SplitL y o)); auto with *.
rewrite -> (IHx2 (SplitR y o)); auto with *.
apply: StepFfoldPropglue.
Qed.
Lemma StepFfoldPropSplitR
: forall (s : StepF iffSetoid) (a : OpenUnit),
StepFfoldProp s -> StepFfoldProp (SplitR s a).
Proof.
intros s a H.
rewrite <- (StepFfoldPropglue s a) in H.
destruct H; auto.
Qed.
Lemma StepFfoldPropSplitL
: forall (s : StepF iffSetoid) (a : OpenUnit),
StepFfoldProp s -> StepFfoldProp (SplitL s a).
Proof.
intros s a H.
rewrite <- (StepFfoldPropglue s a) in H.
destruct H; auto.
Qed.
Section EquivalenceC.
Variable X : RSetoid.
(* begin hide *)
Hint Resolve StepF_Qeq_eq StepF_Qeq_refl SplitL_resp_Qeq SplitR_resp_Qeq.
(* end hide *)
Lemma StepF_eq_resp_Qeq : forall (s t : StepF X) u v, (StepF_Qeq s t) -> (StepF_Qeq u v) -> s == u -> t == v.
Proof.
induction s using StepF_ind; induction t using StepF_ind; try contradiction.
intros u v Hst Huv Hsu.
simpl in Hst.
unfold StepF_eq in *.
rewrite <- Hst.
rewrite <- (StepFfoldProp_morphism ((st_eqS X) ^@> constStepF x <@> u)); auto.
apply: (Map_resp_StepF_eq); auto with *.
intros a b Hab.
simpl.
rewrite -> Hab.
reflexivity.
intros u v [H [Hst0 Hst1]] Huv Hsu.
destruct Hsu as [Hsu1 Hsu2] using (glue_eq_ind s1).
apply glue_StepF_eq.
eapply IHs1.
assumption.
unfold SplitL; apply SplitL_resp_Qeq.
apply H.
apply Huv.
assumption.
eapply IHs2.
assumption.
unfold SplitR; apply SplitR_resp_Qeq.
apply H.
apply Huv.
assumption.
Qed.
Lemma Mirror_eq_Mirror : forall (s t : StepF X), Mirror s == Mirror t <-> s == t.
Proof.
induction s using StepF_ind.
induction t using StepF_ind; simpl.
reflexivity.
change (constStepF x == (Mirror t2) /\ constStepF x == (Mirror t1) <-> constStepF x == t1 /\ constStepF x == t2).
tauto.
intros t.
rewrite MirrorGlue.
split; apply (@glue_eq_ind X); intros H0 H1.
apply glue_StepF_eq.
rewrite <- IHs1.
eapply StepF_eq_resp_Qeq;[| |apply H1]; auto with *.
apply StepF_Qeq_sym.
apply MirrorSplitL_Qeq; auto with *.
rewrite <- IHs2.
eapply StepF_eq_resp_Qeq;[| |apply H0]; auto with *.
apply StepF_Qeq_sym.
apply MirrorSplitR_Qeq; auto with *.
apply glue_StepF_eq.
apply StepF_eq_resp_Qeq with (Mirror s2) (Mirror (SplitR t o)); auto.
apply MirrorSplitR_Qeq; apply Qeq_refl.
rewrite -> IHs2.
assumption.
apply StepF_eq_resp_Qeq with (Mirror s1) (Mirror (SplitL t o)); auto.
apply MirrorSplitL_Qeq; apply Qeq_refl.
rewrite -> IHs1.
assumption.
Qed.
Lemma SplitL_resp_Xeq : forall (s1 s2 : StepF X) a, s1 == s2 -> SplitL s1 a == SplitL s2 a.
Proof.
induction s1 using StepF_ind.
intros s2 a H.
unfold StepF_eq in *.
change (StepFfoldProp ((st_eqS X x:X-->iffSetoid) ^@> SplitL s2 a)).
rewrite <- SplitLMap.
apply StepFfoldPropSplitL.
assumption.
intros s2 a H.
destruct H using (glue_eq_ind s1_1).
apply SplitL_glue_ind; intros Hao.
apply StepF_eq_resp_Qeq with (SplitL s1_1 (OpenUnitDiv a o Hao)) (SplitL (SplitL s2 o) (OpenUnitDiv a o Hao)); auto.
apply SplitLSplitL.
simpl; field; auto with *.
apply glue_StepF_eq.
apply StepF_eq_resp_Qeq with s1_1 (SplitL s2 o); auto.
apply StepF_Qeq_sym.
apply SplitLSplitL.
simpl; field; auto with *.
apply StepF_eq_resp_Qeq with (SplitL s1_2 (OpenUnitDualDiv a o Hao)) (SplitL (SplitR s2 o) (OpenUnitDualDiv a o Hao)); auto.
apply SplitLSplitR; simpl; field; auto with *.
apply StepF_eq_resp_Qeq with s1_1 (SplitL s2 o); auto with *.
apply SplitL_resp_Qeq; auto.
symmetry.
assumption.
Qed.
Lemma SplitR_resp_Xeq : forall (s1 s2:StepF X) a, s1 == s2 -> SplitR s1 a == SplitR s2 a.
Proof.
intros s1 s2 a H.
pose (b:=OpenUnitDual a).
apply StepF_eq_resp_Qeq with (Mirror (SplitL (Mirror s1) b)) (Mirror (SplitL (Mirror s2) b));
try (unfold Mirror, SplitR, SplitL, b;eapply StepF_Qeq_trans;[apply Mirror_resp_Qeq; apply StepF_Qeq_sym; apply MirrorSplitR_Qeq; reflexivity|apply MirrorMirror]).
rewrite -> Mirror_eq_Mirror.
apply SplitL_resp_Xeq.
rewrite -> Mirror_eq_Mirror.
assumption.
Qed.
(** equalitiy is transitive *)
Lemma StepF_eq_trans:forall x y z : StepF X, x == y -> y == z -> x == z.
Proof.
induction x using StepF_ind. intros.
unfold StepF_eq in *.
set (A:=((st_eqS X:X-->X-->iffSetoid) ^@> constStepF x)) in *.
rewrite <- (StepFfoldProp_morphism (A <@> y)); auto with *.
apply: (Map_resp_StepF_eq); auto with *.
intros a b Hab.
simpl.
rewrite -> Hab.
reflexivity.
intros.
destruct H using (glue_eq_ind x1).
apply glue_StepF_eq.
eapply IHx1.
apply H.
apply SplitL_resp_Xeq.
assumption.
eapply IHx2.
apply H1.
apply SplitR_resp_Xeq.
assumption.
Qed.
Lemma glue_resp_StepF_eq:forall (x x' y y':StepF X) o,
(x==x')->(y==y')->
(glue o x y)==(glue o x' y').
Proof.
intros.
unfold StepF_eq.
rewrite MapGlue.
rewrite ApGlueGlue.
split; assumption.
Qed.
(** equality is symmetric *)
Lemma StepF_eq_sym :forall x y: StepF X, x == y -> y == x.
Proof.
intros x y.
revert x.
induction y using StepF_ind.
unfold StepF_eq. simpl. intro x0. induction x0.
unfold StepFfoldProp. simpl. intros. symmetry; assumption.
simpl. unfold StepFfoldProp; simpl; intuition; auto with *.
intros x H.
assert (H0:=(SplitL_resp_Xeq _ _ o H)).
rewrite SplitLGlue in H0.
assert (H1:=(SplitR_resp_Xeq _ _ o H)).
rewrite SplitRGlue in H1.
apply glue_StepF_eq;auto with *.
Qed.
End EquivalenceC.
(* begin hide *)
Add Parametric Relation X : (StepF X) (@StepF_eq X)
reflexivity proved by (@StepF_eq_refl X)
symmetry proved by (@StepF_eq_sym X)
transitivity proved by (@StepF_eq_trans X)
as StepF_SetoidTheory.
Hint Resolve StepF_eq_sym StepF_eq_trans.
Add Morphism (StepFfoldProp)
with signature (@StepF_eq iffSetoid) ==> iff
as StepFfoldProp_mor.
Proof.
exact StepFfoldProp_morphism.
Qed.
(* end hide *)
Lemma StepF_Sth (X : RSetoid) : (Setoid_Theory (StepF X) (@StepF_eq X)).
split; unfold Reflexive, Symmetric, Transitive; eauto with sfarith.
Qed.
(**
** Common subdivision view
This lemma allows to do induction over two step function as if the
functions had the same subdivisions.
*)
Lemma StepF_ind2 : forall (X Y : RSetoid) (P : StepF X -> StepF Y -> Prop),
(forall (s s0 : StepF X) (t t0 : StepF Y),
(s==s0) -> (t==t0) -> P s t -> P s0 t0) ->
(forall (x:X) (y:Y), P (constStepF x) (constStepF y)) ->
(forall (o : OpenUnit) (s s0 : StepF X) (t t0 : StepF Y),
P s t -> P s0 t0 -> P (glue o s s0) (glue o t t0)) ->
forall (s:StepF X) (t:StepF Y), P s t.
Proof.
intros X Y P wd c0 c1.
induction s using StepF_ind.
induction t using StepF_ind.
apply c0.
apply wd with (s:=(glue o (constStepF x) (constStepF x))) (t:=glue o t1 t2); try reflexivity.
apply (glueSplit (constStepF x) o).
apply c1; assumption.
intros t.
eapply wd.
reflexivity.
apply glueSplit with (a:=o).
apply c1; auto.
Qed.
Lemma glue_injl X :forall o (x y x1 y1:StepF X),
(glue o x y)==(glue o x1 y1) -> (x==x1).
Proof.
intros.
destruct H as [H _] using (glue_eq_ind x).
rewrite SplitLGlue in H.
assumption.
Qed.
Lemma glue_injr X :forall o (x y x1 y1:StepF X),
(glue o x y)==(glue o x1 y1) -> (y==y1).
Proof.
intros.
destruct H as [_ H] using (glue_eq_ind x).
rewrite SplitRGlue in H.
assumption.
Qed.
(** Decompose an equality over glue into two parts *)
Lemma eq_glue_ind X : forall (s1 s2 s : StepF X) (a : OpenUnit) (P : Prop),
((SplitL s a) == s1 -> (SplitR s a) == s2 -> P) ->
s == (glue a s1 s2) -> P.
Proof.
intros s1 s2 s a P H H0.
symmetry in H0.
destruct H0 as [H0l H0r] using (glue_eq_ind s1).
symmetry in H0l, H0r.
auto.
Qed.
Lemma MirrorSplitR X : forall (s : StepF X) (a b : OpenUnit),
(b == OpenUnitDual a)%Q ->
(Mirror (SplitR s a)) == (SplitL (Mirror s) b).
Proof.
intros.
apply StepF_Qeq_eq; auto with *.
apply MirrorSplitR_Qeq; auto with *.
Qed.
Lemma MirrorSplitL X : forall (s : StepF X) (a b : OpenUnit),
(b == OpenUnitDual a)%Q ->
(Mirror (SplitL s a)) == (SplitR (Mirror s) b).
Proof.
intros.
apply StepF_Qeq_eq; auto with *.
apply MirrorSplitL_Qeq; auto with *.
Qed.
(** Lift the distribution lemmas between ap and split to work over step
functions *)
Lemma SplitRAp :forall (X Y : RSetoid) (f : StepF (Y --> X)) (s : StepF Y) (o : OpenUnit),
(SplitR (f <@> s) o) == (SplitR f o <@> SplitR s o).
Proof.
intros X Y f s o.
apply StepF_Qeq_eq; auto with *.
unfold Ap, SplitR.
rewrite <- StepFunction.SplitRMap.
apply SplitRAp_Qeq.
Qed.
Lemma SplitLAp :forall (X Y : RSetoid) (f : StepF (Y --> X)) (s : StepF Y) (o : OpenUnit),
(SplitL (f <@> s) o) == (SplitL f o <@> SplitL s o).
Proof.
intros X Y f s o.
apply StepF_Qeq_eq; auto with *.
unfold Ap, SplitL.
rewrite <- StepFunction.SplitLMap.
apply SplitLAp_Qeq.
Qed.
(* begin hide *)
Add Parametric Morphism s : (@constStepF s) with signature (@st_eq s) ==> (@StepF_eq s) as constStepF_wd.
Proof.
auto.
Qed.
Add Parametric Morphism s : (@glue s) with signature ou_eq ==> (@StepF_eq s) ==> (@StepF_eq s) ==> (@StepF_eq s) as glue_wd.
Proof.
intros o1 o2 Ho x1 x2 Hx y1 y2 Hy.
transitivity (glue o1 x2 y2).
apply glue_resp_StepF_eq; auto.
apply StepF_Qeq_eq.
repeat split; auto; reflexivity.
Qed.
Add Parametric Morphism X : (@SplitL X) with signature (@StepF_eq X) ==> ou_eq ==> (@StepF_eq X) as SplitL_wd.
Proof.
intros x1 x2 Hx o1 o2 Ho.
transitivity (SplitL x2 o1).
apply SplitL_resp_Xeq; auto.
apply StepF_Qeq_eq.
apply SplitL_resp_Qeq; auto; reflexivity.
Qed.
Add Parametric Morphism X : (@SplitR X) with signature (@StepF_eq X) ==> ou_eq ==> (@StepF_eq X) as SplitR_wd.
Proof.
intros x1 x2 Hx o1 o2 Ho.
transitivity (SplitR x2 o1).
apply SplitR_resp_Xeq; auto.
apply StepF_Qeq_eq.
apply SplitR_resp_Qeq; auto; reflexivity.
Qed.
Add Parametric Morphism X Y : (@Ap X Y) with signature (@StepF_eq (extSetoid X Y)) ==> (@StepF_eq X) ==> (@StepF_eq Y) as Ap_wd.
Proof.
intros f.
induction f using StepF_ind; intros g Hfg.
induction g using StepF_ind; intros x1.
simpl.
induction x1 using StepF_ind; intros x2.
induction x2 using StepF_ind.
intros H.
transitivity (x ^@> (constStepF x2)).
destruct x as [x Hx].
clear Hfg. apply: Hx ; assumption.
apply: Hfg.
intros H.
rewrite MapGlue.
symmetry.
symmetry in H.
destruct H as [Hl Hr] using (glue_eq_ind x2_1).
apply glue_StepF_eq.
symmetry.
symmetry in Hl.
apply IHx2_1.
assumption.
symmetry.
symmetry in Hr.
apply IHx2_2.
assumption.
intros H.
rewrite MapGlue.
destruct H as [Hl Hr] using (glue_eq_ind x1_1).
apply glue_StepF_eq.
rewrite SplitLMap.
apply IHx1_1; auto.
rewrite SplitRMap.
apply IHx1_2; auto.
symmetry.
rewrite ApGlue.
destruct Hfg as [Hfg0 Hfg1] using (eq_glue_ind g1).
apply glue_StepF_eq; symmetry.
rewrite SplitLMap.
apply IHg1; try rewrite -> H0; auto with *.
rewrite SplitRMap.
apply IHg2; try rewrite -> H0; auto with *.
intros s s' Hs.
destruct Hfg as [Hfg0 Hfg1] using (glue_eq_ind f1).
rewrite ApGlue.
apply glue_StepF_eq; auto with *.
rewrite -> SplitLAp.
apply IHf1; try rewrite -> Hs; auto with *.
rewrite -> SplitRAp.
apply IHf2; try rewrite -> Hs; auto with *.
Qed.
(* end hide *)
Lemma GlueAp : forall (X Y : RSetoid) (f : StepF (X --> Y)) (o : OpenUnit) (l r : StepF X),
f <@> (glue o l r) == glue o ((SplitL f o) <@> l) ((SplitR f o) <@> r).
Proof.
intros X Y f o l r.
set (A:= ((SplitL f o)<@>l)).
set (B:= ((SplitR f o)<@>r)).
rewrite <- (glueSplit f o).
rewrite ApGlueGlue.
reflexivity.
Qed.
(**
** Applicative Functor
Here we prove the axioms of an applicative functor.
*)
Lemma Map_homomorphism (X Y : RSetoid) : forall (f:X-->Y) (a:X),
(f ^@> constStepF a) == (constStepF (f a)).
Proof.
reflexivity.
Qed.
Lemma Map_identity X : forall (a:StepF X),
(@id X) ^@> a == a.
Proof.
intros a.
now rewrite <-(Map_identity a) at 2.
Qed.
Lemma Map_composition X Y Z: forall (a:StepF (Y-->Z)) (b:StepF (X-->Y)) (c:StepF X),
((@compose X Y Z) ^@> a <@> b <@> c) == (a <@> (b <@> c)).
Proof.
induction a using StepF_ind.
simpl.
apply StepF_ind2; auto with *.
intros s s0 t t0 Hs Ht.
rewrite -> Hs, Ht.
auto.
intros o s s0 t t0 H H0.
rewrite -> Map_homomorphism.
rewrite ApGlueGlue.
do 2 rewrite MapGlue.
rewrite ApGlueGlue.
rewrite <- H.
rewrite <- H0.
reflexivity.
intros b c.
rewrite MapGlue.
repeat rewrite ApGlue.
apply glue_resp_StepF_eq.
rewrite -> IHa1.
rewrite -> SplitLAp.
reflexivity.
rewrite -> IHa2.
rewrite -> SplitRAp.
reflexivity.
Qed.
(** Here we show that the rest of the BCKW combinators lift to
step functions. Hence all of the lambda calculus lifts to operate
over step functions. Step functions form about a nice of an
applicative functor as is possible. *)
Lemma Map_discardable X Y : forall (a:StepF X) (b:StepF Y),
((@const _ _) ^@> a <@> b == a).
Proof.
apply StepF_ind2; auto with *.
intros s s0 t t0 Hs Ht.
rewrite -> Hs, Ht; auto.
intros o s s0 t t0 H0 H1.
rewrite MapGlue.
rewrite ApGlueGlue.
rewrite -> H0, H1;reflexivity.
Qed.
Lemma Map_commutative W X Y : forall (f:StepF (W --> X --> Y)) (x:StepF X) (w:StepF W),
((@flip _ _ _) ^@> f <@> x <@> w) == (f <@> w <@> x).
Proof.
induction f using StepF_ind.
simpl.
apply StepF_ind2; auto with *.
intros s s0 t t0 Hs Ht.
rewrite -> Hs, Ht;auto.
intros o s s0 t t0 H0 H1.
rewrite -> Map_homomorphism.
do 2 rewrite MapGlue.
do 2 rewrite ApGlueGlue.
rewrite -> H0, H1; reflexivity.
intros x w.
rewrite MapGlue.
do 4 rewrite ApGlue.
apply glue_resp_StepF_eq; auto.
Qed.
Lemma Map_copyable X Y : forall (f:StepF (X --> X --> Y)) (x:StepF X),
((@join _ _) ^@> f <@> x) == (f <@> x <@> x).
Proof.
apply StepF_ind2; auto with *.
intros s s0 t t0 Hs Ht.
rewrite -> Hs, Ht; auto.
intros o s s0 t t0 H0 H1.
rewrite MapGlue.
do 3 rewrite ApGlueGlue.
rewrite -> H0, H1;reflexivity.
Qed.
(* begin hide *)
Hint Rewrite
ApGlueGlue ApGlue GlueAp SplitRAp SplitLAp SplitLGlue SplitRGlue
Map_homomorphism : StepF_rew.
Hint Rewrite
Map_composition
Map_discardable
Map_commutative
Map_identity
Map_copyable : StepF_eval.
(* end hide *)
(** This tactic is usefully for symbolically evaluating functions written
in (BCKWI) combinator form that are ap'ed to step functions *)
Ltac evalStepF := progress
(repeat rewrite <- Map_homomorphism; autorewrite with StepF_eval).
Lemma Ap_interchange (X Y : RSetoid) : forall (f:StepF (X-->Y)) (a:X),
(f <@^ a) == (flip id a) ^@> f.
Proof.
intros f a.
evalStepF.
reflexivity.
Qed.
(** Map'ing the S combinator (which is also called ap) *)
Lemma Map_ap X Y Z : forall (f:StepF (X --> Y --> Z)) (x:StepF (X --> Y)) (a:StepF X),
((@ap _ _ _) ^@> f <@> x <@> a) == (f <@> a <@> (x <@> a)).
Proof.
intros f x a.
unfold ap.
evalStepF.
reflexivity.
Qed.
(* begin hide *)
Hint Rewrite Map_ap : StepF_eval.
(* end hide *)
Ltac rewriteStepF := autorewrite with StepF_rew.
Lemma StepFfoldPropForall_Ap :
forall X (f:StepF (X --> iffSetoid)) (x:StepF X), (forall y, StepFfoldProp (f <@> constStepF y)) -> StepFfoldProp (f <@> x).
Proof.
intros X f x H.
revert f H.
induction x using StepF_ind.
intros f H.
apply H.
intros f H.
rewrite <- (glueSplit f o).
rewrite ApGlueGlue.
split.
apply IHx1.
intros y.
assert (H0:=H y).
rewrite <- (glueSplit f o) in H0.
rewrite ApGlue in H0.
destruct H0 as [H0 _].
assumption.
apply IHx2.
intros y.
assert (H0:=H y).
rewrite <- (glueSplit f o) in H0.
rewrite ApGlue in H0.
destruct H0 as [_ H0].
assumption.
Qed.
(** A common case that we will encounter is that a predicate holds for
all step functions when it is define via map (or map2 or map3) and the
underlying function holds for all X. *)
Lemma StepFfoldPropForall_Map :
forall X (f:X --> iffSetoid) (x:StepF X), (forall a, f a) -> StepFfoldProp (f ^@> x).
Proof.
intros X f x H.
apply StepFfoldPropForall_Ap.
assumption.
Qed.
Lemma StepFfoldPropForall_Map2 :
forall X Y (f:X --> Y --> iffSetoid) x y, (forall a b, f a b) -> StepFfoldProp (f ^@> x <@> y).
Proof.
intros X Y f x y H.
apply StepFfoldPropForall_Ap.
intros b.
rewrite <- (Map_commutative (constStepF f) (constStepF b)).
rewriteStepF.
apply StepFfoldPropForall_Map.
intros a.
apply: H.
Qed.
Lemma StepFfoldPropForall_Map3 :
forall X Y Z (f:X --> Y --> Z --> iffSetoid) x y z, (forall a b c, f a b c) -> StepFfoldProp (f ^@> x <@> y <@> z).
Proof.
intros X Y Z f x y z H.
apply StepFfoldPropForall_Ap.
intros c.
rewrite <- (Map_commutative ((constStepF f) <@> x) (constStepF c)).
rewrite <- Map_composition.
rewriteStepF.
rewrite <- (Map_commutative (constStepF (compose flip f)) (constStepF c)).
rewriteStepF.
apply StepFfoldPropForall_Map2.
intros a b.
apply: H.
Qed.
(** The implication operation can be lifted to work on characteristic
functions *)
Definition imp0:Prop->iffSetoid-->iffSetoid.
Proof.
intro A.
exists (fun B:Prop=>(A->B)).
simpl. unfold canonical_names.equiv. intuition.
Defined.
Definition imp:iffSetoid-->iffSetoid-->iffSetoid.
Proof.
exists imp0.
simpl. unfold canonical_names.equiv, extEq. intuition.
simpl. intuition.
Defined.
Definition StepF_imp (f g:StepF iffSetoid):Prop:=
(StepFfoldProp (imp ^@> f <@> g)).
Lemma StepFfoldPropglue_rew:(forall o x y, (StepFfoldProp (glue o x y))<->((StepFfoldProp x)/\StepFfoldProp y)).
Proof.
auto with *.
Qed.
(* begin hide *)
Hint Rewrite StepFfoldPropglue_rew:StepF_rew.
(* end hide *)
Lemma StepF_imp_imp:forall x y:(StepF iffSetoid),
(StepF_imp x y) ->
((StepFfoldProp x)->(StepFfoldProp y)).
Proof.
induction x using StepF_ind. induction y using StepF_ind.
auto with *.
unfold StepF_imp. unfold StepFfoldProp;simpl;intuition.
intros y.
unfold StepF_imp, Map2.
rewriteStepF.
intros.
rewrite <- (StepFfoldPropglue y o).
rewriteStepF.
intuition.
Qed.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_TB_V
`define SKY130_FD_SC_LS__UDP_DFF_NSR_TB_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dff_nsr.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 SET = 1'b0;
#80 D = 1'b1;
#100 RESET = 1'b1;
#120 SET = 1'b1;
#140 D = 1'b0;
#160 RESET = 1'b0;
#180 SET = 1'b0;
#200 SET = 1'b1;
#220 RESET = 1'b1;
#240 D = 1'b1;
#260 SET = 1'bx;
#280 RESET = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ls__udp_dff$NSR dut (.SET(SET), .RESET(RESET), .D(D), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_NSR_TB_V
|
(** * IndProp: Inductively Defined Propositions *)
Set Warnings "-notation-overridden,-parsing".
From LF Require Export Logic.
Require Coq.omega.Omega.
(* ################################################################# *)
(** * Inductively Defined Propositions *)
(** In the [Logic] chapter, we looked at several ways of writing
propositions, including conjunction, disjunction, and existential
quantification. In this chapter, we bring yet another new tool
into the mix: _inductive definitions_. *)
(** In past chapters, we have seen two ways of stating that a number
[n] is even: We can say
(1) [evenb n = true], or
(2) [exists k, n = double k].
Yet another possibility is to say that [n] is even if we can
establish its evenness from the following rules:
- Rule [ev_0]: The number [0] is even.
- Rule [ev_SS]: If [n] is even, then [S (S n)] is even. *)
(** To illustrate how this new definition of evenness works,
let's imagine using it to show that [4] is even. By rule [ev_SS],
it suffices to show that [2] is even. This, in turn, is again
guaranteed by rule [ev_SS], as long as we can show that [0] is
even. But this last fact follows directly from the [ev_0] rule. *)
(** We will see many definitions like this one during the rest
of the course. For purposes of informal discussions, it is
helpful to have a lightweight notation that makes them easy to
read and write. _Inference rules_ are one such notation:
------------ (ev_0)
even 0
even n
---------------- (ev_SS)
even (S (S n))
*)
(** Each of the textual rules above is reformatted here as an
inference rule; the intended reading is that, if the _premises_
above the line all hold, then the _conclusion_ below the line
follows. For example, the rule [ev_SS] says that, if [n]
satisfies [even], then [S (S n)] also does. If a rule has no
premises above the line, then its conclusion holds
unconditionally.
We can represent a proof using these rules by combining rule
applications into a _proof tree_. Here's how we might transcribe
the above proof that [4] is even:
-------- (ev_0)
even 0
-------- (ev_SS)
even 2
-------- (ev_SS)
even 4
*)
(** (Why call this a "tree" (rather than a "stack", for example)?
Because, in general, inference rules can have multiple premises.
We will see examples of this shortly. *)
(* ================================================================= *)
(** ** Inductive Definition of Evenness *)
(** Putting all of this together, we can translate the definition of
evenness into a formal Coq definition using an [Inductive]
declaration, where each constructor corresponds to an inference
rule: *)
Inductive even : nat -> Prop :=
| ev_0 : even 0
| ev_SS (n : nat) (H : even n) : even (S (S n)).
(** This definition is different in one crucial respect from previous
uses of [Inductive]: the thing we are defining is not a [Type],
but rather a function from [nat] to [Prop] -- that is, a property
of numbers. We've already seen other inductive definitions that
result in functions -- for example, [list], whose type is [Type ->
Type]. What is really new here is that, because the [nat]
argument of [even] appears to the _right_ of the colon, it is
allowed to take different values in the types of different
constructors: [0] in the type of [ev_0] and [S (S n)] in the type
of [ev_SS].
In contrast, the definition of [list] names the [X] parameter
_globally_, to the _left_ of the colon, forcing the result of
[nil] and [cons] to be the same ([list X]). Had we tried to bring
[nat] to the left in defining [even], we would have seen an
error: *)
Fail Inductive wrong_ev (n : nat) : Prop :=
| wrong_ev_0 : wrong_ev 0
| wrong_ev_SS : wrong_ev n -> wrong_ev (S (S n)).
(* ===> Error: Last occurrence of "[wrong_ev]" must have "[n]"
as 1st argument in "[wrong_ev 0]". *)
(** In an [Inductive] definition, an argument to the type
constructor on the left of the colon is called a "parameter",
whereas an argument on the right is called an "index".
For example, in [Inductive list (X : Type) := ...], [X] is a
parameter; in [Inductive even : nat -> Prop := ...], the
unnamed [nat] argument is an index. *)
(** We can think of the definition of [even] as defining a Coq
property [even : nat -> Prop], together with primitive theorems
[ev_0 : even 0] and [ev_SS : forall n, even n -> even (S (S n))]. *)
(** That definition can also be written as follows...
Inductive even : nat -> Prop :=
| ev_0 : even 0
| ev_SS : forall n, even n -> even (S (S n)).
*)
(** ... making explicit the type of the rule [ev_SS]. *)
(** Such "constructor theorems" have the same status as proven
theorems. In particular, we can use Coq's [apply] tactic with the
rule names to prove [even] for particular numbers... *)
Theorem ev_4 : even 4.
Proof. apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** ... or we can use function application syntax: *)
Theorem ev_4' : even 4.
Proof. apply (ev_SS 2 (ev_SS 0 ev_0)). Qed.
(** We can also prove theorems that have hypotheses involving [even]. *)
Theorem ev_plus4 : forall n, even n -> even (4 + n).
Proof.
intros n. simpl. intros Hn.
apply ev_SS. apply ev_SS. apply Hn.
Qed.
(** **** Exercise: 1 star, standard (ev_double) *)
Theorem ev_double : forall n,
even (double n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Using Evidence in Proofs *)
(** Besides _constructing_ evidence that numbers are even, we can also
_reason about_ such evidence.
Introducing [even] with an [Inductive] declaration tells Coq not
only that the constructors [ev_0] and [ev_SS] are valid ways to
build evidence that some number is even, but also that these two
constructors are the _only_ ways to build evidence that numbers
are even (in the sense of [even]). *)
(** In other words, if someone gives us evidence [E] for the assertion
[even n], then we know that [E] must have one of two shapes:
- [E] is [ev_0] (and [n] is [O]), or
- [E] is [ev_SS n' E'] (and [n] is [S (S n')], where [E'] is
evidence for [even n']). *)
(** This suggests that it should be possible to analyze a
hypothesis of the form [even n] much as we do inductively defined
data structures; in particular, it should be possible to argue by
_induction_ and _case analysis_ on such evidence. Let's look at a
few examples to see what this means in practice. *)
(* ================================================================= *)
(** ** Inversion on Evidence *)
(** Suppose we are proving some fact involving a number [n], and
we are given [even n] as a hypothesis. We already know how to
perform case analysis on [n] using [destruct] or [induction],
generating separate subgoals for the case where [n = O] and the
case where [n = S n'] for some [n']. But for some proofs we may
instead want to analyze the evidence that [even n] _directly_. As
a tool, we can prove our characterization of evidence for
[even n], using [destruct]. *)
Theorem ev_inversion :
forall (n : nat), even n ->
(n = 0) \/ (exists n', n = S (S n') /\ even n').
Proof.
intros n E.
destruct E as [ | n' E'].
- (* E = ev_0 : even 0 *)
left. reflexivity.
- (* E = ev_SS n' E' : even (S (S n')) *)
right. exists n'. split. reflexivity. apply E'.
Qed.
(** The following theorem can easily be proved using [destruct] on
evidence. *)
Theorem ev_minus2 : forall n,
even n -> even (pred (pred n)).
Proof.
intros n E.
destruct E as [| n' E'].
- (* E = ev_0 *) simpl. apply ev_0.
- (* E = ev_SS n' E' *) simpl. apply E'.
Qed.
(** However, this variation cannot easily be handled with [destruct]. *)
Theorem evSS_ev : forall n,
even (S (S n)) -> even n.
(** Intuitively, we know that evidence for the hypothesis cannot
consist just of the [ev_0] constructor, since [O] and [S] are
different constructors of the type [nat]; hence, [ev_SS] is the
only case that applies. Unfortunately, [destruct] is not smart
enough to realize this, and it still generates two subgoals. Even
worse, in doing so, it keeps the final goal unchanged, failing to
provide any useful information for completing the proof. *)
Proof.
intros n E.
destruct E as [| n' E'].
- (* E = ev_0. *)
(* We must prove that [n] is even from no assumptions! *)
Abort.
(** What happened, exactly? Calling [destruct] has the effect of
replacing all occurrences of the property argument by the values
that correspond to each constructor. This is enough in the case
of [ev_minus2] because that argument [n] is mentioned directly
in the final goal. However, it doesn't help in the case of
[evSS_ev] since the term that gets replaced ([S (S n)]) is not
mentioned anywhere. *)
(** We could patch this proof by replacing the goal [even n],
which does not mention the replaced term [S (S n)], by the
equivalent goal [even (pred (pred (S (S n))))], which does mention
this term, after which [destruct] can make progress. But it is
more straightforward to use our inversion lemma. *)
Theorem evSS_ev : forall n, even (S (S n)) -> even n.
Proof. intros n H. apply ev_inversion in H. destruct H.
- discriminate H.
- destruct H as [n' [Hnm Hev]]. injection Hnm.
intro Heq. rewrite Heq. apply Hev.
Qed.
(** Coq provides a tactic called [inversion], which does the work of
our inversion lemma and more besides. *)
(** The [inversion] tactic can detect (1) that the first case
([n = 0]) does not apply and (2) that the [n'] that appears in the
[ev_SS] case must be the same as [n]. It has an "[as]" variant
similar to [destruct], allowing us to assign names rather than
have Coq choose them. *)
Theorem evSS_ev' : forall n,
even (S (S n)) -> even n.
Proof.
intros n E.
inversion E as [| n' E'].
(* We are in the [E = ev_SS n' E'] case now. *)
apply E'.
Qed.
(** The [inversion] tactic can apply the principle of explosion to
"obviously contradictory" hypotheses involving inductive
properties, something that takes a bit more work using our
inversion lemma. For example: *)
Theorem one_not_even : ~ even 1.
Proof.
intros H. apply ev_inversion in H.
destruct H as [ | [m [Hm _]]].
- discriminate H.
- discriminate Hm.
Qed.
Theorem one_not_even' : ~ even 1.
intros H. inversion H. Qed.
(** **** Exercise: 1 star, standard (inversion_practice)
Prove the following result using [inversion]. For extra practice,
prove it using the inversion lemma. *)
Theorem SSSSev__even : forall n,
even (S (S (S (S n)))) -> even n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, standard (even5_nonsense)
Prove the following result using [inversion]. *)
Theorem even5_nonsense :
even 5 -> 2 + 2 = 9.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The [inversion] tactic does quite a bit of work. When
applied to equalities, as a special case, it does the work of both
[discriminate] and [injection]. In addition, it carries out the
[intros] and [rewrite]s that are typically necessary in the case
of [injection]. It can also be applied, more generally, to analyze
evidence for inductively defined propositions. As examples, we'll
use it to reprove some theorems from [Tactics.v]. *)
Theorem inversion_ex1 : forall (n m o : nat),
[n; m] = [o; o] ->
[n] = [m].
Proof.
intros n m o H. inversion H. reflexivity. Qed.
Theorem inversion_ex2 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
(** Here's how [inversion] works in general. Suppose the name
[H] refers to an assumption [P] in the current context, where [P]
has been defined by an [Inductive] declaration. Then, for each of
the constructors of [P], [inversion H] generates a subgoal in which
[H] has been replaced by the exact, specific conditions under
which this constructor could have been used to prove [P]. Some of
these subgoals will be self-contradictory; [inversion] throws
these away. The ones that are left represent the cases that must
be proved to establish the original goal. For those, [inversion]
adds all equations into the proof context that must hold of the
arguments given to [P] (e.g., [S (S n') = n] in the proof of
[evSS_ev]). *)
(** The [ev_double] exercise above shows that our new notion of
evenness is implied by the two earlier ones (since, by
[even_bool_prop] in chapter [Logic], we already know that
those are equivalent to each other). To show that all three
coincide, we just need the following lemma. *)
Lemma ev_even_firsttry : forall n,
even n -> exists k, n = double k.
Proof.
(* WORKED IN CLASS *)
(** We could try to proceed by case analysis or induction on [n]. But
since [even] is mentioned in a premise, this strategy would
probably lead to a dead end, as in the previous section. Thus, it
seems better to first try [inversion] on the evidence for [even].
Indeed, the first case can be solved trivially. *)
intros n E. inversion E as [| n' E'].
- (* E = ev_0 *)
exists 0. reflexivity.
- (* E = ev_SS n' E' *) simpl.
(** Unfortunately, the second case is harder. We need to show [exists
k, S (S n') = double k], but the only available assumption is
[E'], which states that [even n'] holds. Since this isn't
directly useful, it seems that we are stuck and that performing
case analysis on [E] was a waste of time.
If we look more closely at our second goal, however, we can see
that something interesting happened: By performing case analysis
on [E], we were able to reduce the original result to a similar
one that involves a _different_ piece of evidence for [even]:
namely [E']. More formally, we can finish our proof by showing
that
exists k', n' = double k',
which is the same as the original statement, but with [n'] instead
of [n]. Indeed, it is not difficult to convince Coq that this
intermediate result suffices. *)
assert (I : (exists k', n' = double k') ->
(exists k, S (S n') = double k)).
{ intros [k' Hk']. rewrite Hk'. exists (S k'). reflexivity. }
apply I. (* reduce the original goal to the new one *)
Abort.
(* ================================================================= *)
(** ** Induction on Evidence *)
(** If this looks familiar, it is no coincidence: We've
encountered similar problems in the [Induction] chapter, when
trying to use case analysis to prove results that required
induction. And once again the solution is... induction!
The behavior of [induction] on evidence is the same as its
behavior on data: It causes Coq to generate one subgoal for each
constructor that could have used to build that evidence, while
providing an induction hypotheses for each recursive occurrence of
the property in question.
To prove a property of [n] holds for all numbers for which [even
n] holds, we can use induction on [even n]. This requires us to
prove two things, corresponding to the two ways in which [even n]
could have been constructed. If it was constructed by [ev_0], then
[n=0], and the property must hold of [0]. If it was constructed by
[ev_SS], then the evidence of [even n] is of the form [ev_SS n'
E'], where [n = S (S n')] and [E'] is evidence for [even n']. In
this case, the inductive hypothesis says that the property we are
trying to prove holds for [n']. *)
(** Let's try our current lemma again: *)
Lemma ev_even : forall n,
even n -> exists k, n = double k.
Proof.
intros n E.
induction E as [|n' E' IH].
- (* E = ev_0 *)
exists 0. reflexivity.
- (* E = ev_SS n' E'
with IH : exists k', n' = double k' *)
destruct IH as [k' Hk'].
rewrite Hk'. exists (S k'). reflexivity.
Qed.
(** Here, we can see that Coq produced an [IH] that corresponds
to [E'], the single recursive occurrence of [even] in its own
definition. Since [E'] mentions [n'], the induction hypothesis
talks about [n'], as opposed to [n] or some other number. *)
(** The equivalence between the second and third definitions of
evenness now follows. *)
Theorem ev_even_iff : forall n,
even n <-> exists k, n = double k.
Proof.
intros n. split.
- (* -> *) apply ev_even.
- (* <- *) intros [k Hk]. rewrite Hk. apply ev_double.
Qed.
(** As we will see in later chapters, induction on evidence is a
recurring technique across many areas, and in particular when
formalizing the semantics of programming languages, where many
properties of interest are defined inductively. *)
(** The following exercises provide simple examples of this
technique, to help you familiarize yourself with it. *)
(** **** Exercise: 2 stars, standard (ev_sum) *)
Theorem ev_sum : forall n m, even n -> even m -> even (n + m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced, optional (even'_ev)
In general, there may be multiple ways of defining a
property inductively. For example, here's a (slightly contrived)
alternative definition for [even]: *)
Inductive even' : nat -> Prop :=
| even'_0 : even' 0
| even'_2 : even' 2
| even'_sum n m (Hn : even' n) (Hm : even' m) : even' (n + m).
(** Prove that this definition is logically equivalent to the old
one. (You may want to look at the previous theorem when you get
to the induction step.) *)
Theorem even'_ev : forall n, even' n <-> even n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, recommended (ev_ev__ev)
Finding the appropriate thing to do induction on is a
bit tricky here: *)
Theorem ev_ev__ev : forall n m,
even (n+m) -> even n -> even m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (ev_plus_plus)
This exercise just requires applying existing lemmas. No
induction or even case analysis is needed, though some of the
rewriting may be tedious. *)
Theorem ev_plus_plus : forall n m p,
even (n+m) -> even (n+p) -> even (m+p).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Inductive Relations *)
(** A proposition parameterized by a number (such as [even])
can be thought of as a _property_ -- i.e., it defines
a subset of [nat], namely those numbers for which the proposition
is provable. In the same way, a two-argument proposition can be
thought of as a _relation_ -- i.e., it defines a set of pairs for
which the proposition is provable. *)
Module Playground.
(** One useful example is the "less than or equal to" relation on
numbers. *)
(** The following definition should be fairly intuitive. It
says that there are two ways to give evidence that one number is
less than or equal to another: either observe that they are the
same number, or give evidence that the first is less than or equal
to the predecessor of the second. *)
Inductive le : nat -> nat -> Prop :=
| le_n n : le n n
| le_S n m (H : le n m) : le n (S m).
Notation "m <= n" := (le m n).
(** Proofs of facts about [<=] using the constructors [le_n] and
[le_S] follow the same patterns as proofs about properties, like
[even] above. We can [apply] the constructors to prove [<=]
goals (e.g., to show that [3<=3] or [3<=6]), and we can use
tactics like [inversion] to extract information from [<=]
hypotheses in the context (e.g., to prove that [(2 <= 1) ->
2+2=5].) *)
(** Here are some sanity checks on the definition. (Notice that,
although these are the same kind of simple "unit tests" as we gave
for the testing functions we wrote in the first few lectures, we
must construct their proofs explicitly -- [simpl] and
[reflexivity] don't do the job, because the proofs aren't just a
matter of simplifying computations.) *)
Theorem test_le1 :
3 <= 3.
Proof.
(* WORKED IN CLASS *)
apply le_n. Qed.
Theorem test_le2 :
3 <= 6.
Proof.
(* WORKED IN CLASS *)
apply le_S. apply le_S. apply le_S. apply le_n. Qed.
Theorem test_le3 :
(2 <= 1) -> 2 + 2 = 5.
Proof.
(* WORKED IN CLASS *)
intros H. inversion H. inversion H2. Qed.
(** The "strictly less than" relation [n < m] can now be defined
in terms of [le]. *)
End Playground.
Definition lt (n m:nat) := le (S n) m.
Notation "m < n" := (lt m n).
(** Here are a few more simple relations on numbers: *)
Inductive square_of : nat -> nat -> Prop :=
| sq n : square_of n (n * n).
Inductive next_nat : nat -> nat -> Prop :=
| nn n : next_nat n (S n).
Inductive next_even : nat -> nat -> Prop :=
| ne_1 n : even (S n) -> next_even n (S n)
| ne_2 n (H : even (S (S n))) : next_even n (S (S n)).
(** **** Exercise: 2 stars, standard, optional (total_relation)
Define an inductive binary relation [total_relation] that holds
between every pair of natural numbers. *)
(* FILL IN HERE
[] *)
(** **** Exercise: 2 stars, standard, optional (empty_relation)
Define an inductive binary relation [empty_relation] (on numbers)
that never holds. *)
(* FILL IN HERE
[] *)
(** From the definition of [le], we can sketch the behaviors of
[destruct], [inversion], and [induction] on a hypothesis [H]
providing evidence of the form [le e1 e2]. Doing [destruct H]
will generate two cases. In the first case, [e1 = e2], and it
will replace instances of [e2] with [e1] in the goal and context.
In the second case, [e2 = S n'] for some [n'] for which [le e1 n']
holds, and it will replace instances of [e2] with [S n'].
Doing [inversion H] will remove impossible cases and add generated
equalities to the context for further use. Doing [induction H]
will, in the second case, add the induction hypothesis that the
goal holds when [e2] is replaced with [n']. *)
(** **** Exercise: 3 stars, standard, optional (le_exercises)
Here are a number of facts about the [<=] and [<] relations that
we are going to need later in the course. The proofs make good
practice exercises. *)
Lemma le_trans : forall m n o, m <= n -> n <= o -> m <= o.
Proof.
(* FILL IN HERE *) Admitted.
Theorem O_le_n : forall n,
0 <= n.
Proof.
(* FILL IN HERE *) Admitted.
Theorem n_le_m__Sn_le_Sm : forall n m,
n <= m -> S n <= S m.
Proof.
(* FILL IN HERE *) Admitted.
Theorem Sn_le_Sm__n_le_m : forall n m,
S n <= S m -> n <= m.
Proof.
(* FILL IN HERE *) Admitted.
Theorem le_plus_l : forall a b,
a <= a + b.
Proof.
(* FILL IN HERE *) Admitted.
Theorem plus_lt : forall n1 n2 m,
n1 + n2 < m ->
n1 < m /\ n2 < m.
Proof.
unfold lt.
(* FILL IN HERE *) Admitted.
Theorem lt_S : forall n m,
n < m ->
n < S m.
Proof.
(* FILL IN HERE *) Admitted.
Theorem leb_complete : forall n m,
n <=? m = true -> n <= m.
Proof.
(* FILL IN HERE *) Admitted.
(** Hint: The next one may be easiest to prove by induction on [m]. *)
Theorem leb_correct : forall n m,
n <= m ->
n <=? m = true.
Proof.
(* FILL IN HERE *) Admitted.
(** Hint: This one can easily be proved without using [induction]. *)
Theorem leb_true_trans : forall n m o,
n <=? m = true -> m <=? o = true -> n <=? o = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (leb_iff) *)
Theorem leb_iff : forall n m,
n <=? m = true <-> n <= m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Module R.
(** **** Exercise: 3 stars, standard, recommended (R_provability)
We can define three-place relations, four-place relations,
etc., in just the same way as binary relations. For example,
consider the following three-place relation on numbers: *)
Inductive R : nat -> nat -> nat -> Prop :=
| c1 : R 0 0 0
| c2 m n o (H : R m n o) : R (S m) n (S o)
| c3 m n o (H : R m n o) : R m (S n) (S o)
| c4 m n o (H : R (S m) (S n) (S (S o))) : R m n o
| c5 m n o (H : R m n o) : R n m o.
(** - Which of the following propositions are provable?
- [R 1 1 2]
- [R 2 2 6]
- If we dropped constructor [c5] from the definition of [R],
would the set of provable propositions change? Briefly (1
sentence) explain your answer.
- If we dropped constructor [c4] from the definition of [R],
would the set of provable propositions change? Briefly (1
sentence) explain your answer.
(* FILL IN HERE *)
*)
(* Do not modify the following line: *)
Definition manual_grade_for_R_provability : option (nat*string) := None.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (R_fact)
The relation [R] above actually encodes a familiar function.
Figure out which function; then state and prove this equivalence
in Coq? *)
Definition fR : nat -> nat -> nat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem R_equiv_fR : forall m n o, R m n o <-> fR m n = o.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End R.
(** **** Exercise: 2 stars, advanced (subsequence)
A list is a _subsequence_ of another list if all of the elements
in the first list occur in the same order in the second list,
possibly with some extra elements in between. For example,
[1;2;3]
is a subsequence of each of the lists
[1;2;3]
[1;1;1;2;2;3]
[1;2;7;3]
[5;6;1;9;9;2;7;3;8]
but it is _not_ a subsequence of any of the lists
[1;2]
[1;3]
[5;6;2;1;7;3;8].
- Define an inductive proposition [subseq] on [list nat] that
captures what it means to be a subsequence. (Hint: You'll need
three cases.)
- Prove [subseq_refl] that subsequence is reflexive, that is,
any list is a subsequence of itself.
- Prove [subseq_app] that for any lists [l1], [l2], and [l3],
if [l1] is a subsequence of [l2], then [l1] is also a subsequence
of [l2 ++ l3].
- (Optional, harder) Prove [subseq_trans] that subsequence is
transitive -- that is, if [l1] is a subsequence of [l2] and [l2]
is a subsequence of [l3], then [l1] is a subsequence of [l3].
Hint: choose your induction carefully! *)
Inductive subseq : list nat -> list nat -> Prop :=
(* FILL IN HERE *)
.
Theorem subseq_refl : forall (l : list nat), subseq l l.
Proof.
(* FILL IN HERE *) Admitted.
Theorem subseq_app : forall (l1 l2 l3 : list nat),
subseq l1 l2 ->
subseq l1 (l2 ++ l3).
Proof.
(* FILL IN HERE *) Admitted.
Theorem subseq_trans : forall (l1 l2 l3 : list nat),
subseq l1 l2 ->
subseq l2 l3 ->
subseq l1 l3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (R_provability2)
Suppose we give Coq the following definition:
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 : forall n l, R n l -> R (S n) (n :: l)
| c3 : forall n l, R (S n) l -> R n l.
Which of the following propositions are provable?
- [R 2 [1;0]]
- [R 1 [1;2;1;0]]
- [R 6 [3;2;1;0]] *)
(* FILL IN HERE
[] *)
(* ################################################################# *)
(** * Case Study: Regular Expressions *)
(** The [even] property provides a simple example for
illustrating inductive definitions and the basic techniques for
reasoning about them, but it is not terribly exciting -- after
all, it is equivalent to the two non-inductive definitions of
evenness that we had already seen, and does not seem to offer any
concrete benefit over them.
To give a better sense of the power of inductive definitions, we
now show how to use them to model a classic concept in computer
science: _regular expressions_. *)
(** Regular expressions are a simple language for describing sets of
strings. Their syntax is defined as follows: *)
Inductive reg_exp {T : Type} : Type :=
| EmptySet
| EmptyStr
| Char (t : T)
| App (r1 r2 : reg_exp)
| Union (r1 r2 : reg_exp)
| Star (r : reg_exp).
(** Note that this definition is _polymorphic_: Regular
expressions in [reg_exp T] describe strings with characters drawn
from [T] -- that is, lists of elements of [T].
(We depart slightly from standard practice in that we do not
require the type [T] to be finite. This results in a somewhat
different theory of regular expressions, but the difference is not
significant for our purposes.) *)
(** We connect regular expressions and strings via the following
rules, which define when a regular expression _matches_ some
string:
- The expression [EmptySet] does not match any string.
- The expression [EmptyStr] matches the empty string [[]].
- The expression [Char x] matches the one-character string [[x]].
- If [re1] matches [s1], and [re2] matches [s2],
then [App re1 re2] matches [s1 ++ s2].
- If at least one of [re1] and [re2] matches [s],
then [Union re1 re2] matches [s].
- Finally, if we can write some string [s] as the concatenation
of a sequence of strings [s = s_1 ++ ... ++ s_k], and the
expression [re] matches each one of the strings [s_i],
then [Star re] matches [s].
As a special case, the sequence of strings may be empty, so
[Star re] always matches the empty string [[]] no matter what
[re] is. *)
(** We can easily translate this informal definition into an
[Inductive] one as follows: *)
Inductive exp_match {T} : list T -> reg_exp -> Prop :=
| MEmpty : exp_match [] EmptyStr
| MChar x : exp_match [x] (Char x)
| MApp s1 re1 s2 re2
(H1 : exp_match s1 re1)
(H2 : exp_match s2 re2) :
exp_match (s1 ++ s2) (App re1 re2)
| MUnionL s1 re1 re2
(H1 : exp_match s1 re1) :
exp_match s1 (Union re1 re2)
| MUnionR re1 s2 re2
(H2 : exp_match s2 re2) :
exp_match s2 (Union re1 re2)
| MStar0 re : exp_match [] (Star re)
| MStarApp s1 s2 re
(H1 : exp_match s1 re)
(H2 : exp_match s2 (Star re)) :
exp_match (s1 ++ s2) (Star re).
(** Again, for readability, we can also display this definition using
inference-rule notation. At the same time, let's introduce a more
readable infix notation. *)
Notation "s =~ re" := (exp_match s re) (at level 80).
(**
---------------- (MEmpty)
[] =~ EmptyStr
--------------- (MChar)
[x] =~ Char x
s1 =~ re1 s2 =~ re2
------------------------- (MApp)
s1 ++ s2 =~ App re1 re2
s1 =~ re1
--------------------- (MUnionL)
s1 =~ Union re1 re2
s2 =~ re2
--------------------- (MUnionR)
s2 =~ Union re1 re2
--------------- (MStar0)
[] =~ Star re
s1 =~ re s2 =~ Star re
--------------------------- (MStarApp)
s1 ++ s2 =~ Star re
*)
(** Notice that these rules are not _quite_ the same as the
informal ones that we gave at the beginning of the section.
First, we don't need to include a rule explicitly stating that no
string matches [EmptySet]; we just don't happen to include any
rule that would have the effect of some string matching
[EmptySet]. (Indeed, the syntax of inductive definitions doesn't
even _allow_ us to give such a "negative rule.")
Second, the informal rules for [Union] and [Star] correspond
to two constructors each: [MUnionL] / [MUnionR], and [MStar0] /
[MStarApp]. The result is logically equivalent to the original
rules but more convenient to use in Coq, since the recursive
occurrences of [exp_match] are given as direct arguments to the
constructors, making it easier to perform induction on evidence.
(The [exp_match_ex1] and [exp_match_ex2] exercises below ask you
to prove that the constructors given in the inductive declaration
and the ones that would arise from a more literal transcription of
the informal rules are indeed equivalent.)
Let's illustrate these rules with a few examples. *)
Example reg_exp_ex1 : [1] =~ Char 1.
Proof.
apply MChar.
Qed.
Example reg_exp_ex2 : [1; 2] =~ App (Char 1) (Char 2).
Proof.
apply (MApp [1] _ [2]).
- apply MChar.
- apply MChar.
Qed.
(** (Notice how the last example applies [MApp] to the strings
[[1]] and [[2]] directly. Since the goal mentions [[1; 2]]
instead of [[1] ++ [2]], Coq wouldn't be able to figure out how to
split the string on its own.)
Using [inversion], we can also show that certain strings do _not_
match a regular expression: *)
Example reg_exp_ex3 : ~ ([1; 2] =~ Char 1).
Proof.
intros H. inversion H.
Qed.
(** We can define helper functions for writing down regular
expressions. The [reg_exp_of_list] function constructs a regular
expression that matches exactly the list that it receives as an
argument: *)
Fixpoint reg_exp_of_list {T} (l : list T) :=
match l with
| [] => EmptyStr
| x :: l' => App (Char x) (reg_exp_of_list l')
end.
Example reg_exp_ex4 : [1; 2; 3] =~ reg_exp_of_list [1; 2; 3].
Proof.
simpl. apply (MApp [1]).
{ apply MChar. }
apply (MApp [2]).
{ apply MChar. }
apply (MApp [3]).
{ apply MChar. }
apply MEmpty.
Qed.
(** We can also prove general facts about [exp_match]. For instance,
the following lemma shows that every string [s] that matches [re]
also matches [Star re]. *)
Lemma MStar1 :
forall T s (re : @reg_exp T) ,
s =~ re ->
s =~ Star re.
Proof.
intros T s re H.
rewrite <- (app_nil_r _ s).
apply (MStarApp s [] re).
- apply H.
- apply MStar0.
Qed.
(** (Note the use of [app_nil_r] to change the goal of the theorem to
exactly the same shape expected by [MStarApp].) *)
(** **** Exercise: 3 stars, standard (exp_match_ex1)
The following lemmas show that the informal matching rules given
at the beginning of the chapter can be obtained from the formal
inductive definition. *)
Lemma empty_is_empty : forall T (s : list T),
~ (s =~ EmptySet).
Proof.
(* FILL IN HERE *) Admitted.
Lemma MUnion' : forall T (s : list T) (re1 re2 : @reg_exp T),
s =~ re1 \/ s =~ re2 ->
s =~ Union re1 re2.
Proof.
(* FILL IN HERE *) Admitted.
(** The next lemma is stated in terms of the [fold] function from the
[Poly] chapter: If [ss : list (list T)] represents a sequence of
strings [s1, ..., sn], then [fold app ss []] is the result of
concatenating them all together. *)
Lemma MStar' : forall T (ss : list (list T)) (re : reg_exp),
(forall s, In s ss -> s =~ re) ->
fold app ss [] =~ Star re.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, standard, optional (reg_exp_of_list_spec)
Prove that [reg_exp_of_list] satisfies the following
specification: *)
Lemma reg_exp_of_list_spec : forall T (s1 s2 : list T),
s1 =~ reg_exp_of_list s2 <-> s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Since the definition of [exp_match] has a recursive
structure, we might expect that proofs involving regular
expressions will often require induction on evidence. *)
(** For example, suppose that we wanted to prove the following
intuitive result: If a regular expression [re] matches some string
[s], then all elements of [s] must occur as character literals
somewhere in [re].
To state this theorem, we first define a function [re_chars] that
lists all characters that occur in a regular expression: *)
Fixpoint re_chars {T} (re : reg_exp) : list T :=
match re with
| EmptySet => []
| EmptyStr => []
| Char x => [x]
| App re1 re2 => re_chars re1 ++ re_chars re2
| Union re1 re2 => re_chars re1 ++ re_chars re2
| Star re => re_chars re
end.
(** We can then phrase our theorem as follows: *)
Theorem in_re_match : forall T (s : list T) (re : reg_exp) (x : T),
s =~ re ->
In x s ->
In x (re_chars re).
Proof.
intros T s re x Hmatch Hin.
induction Hmatch
as [| x'
| s1 re1 s2 re2 Hmatch1 IH1 Hmatch2 IH2
| s1 re1 re2 Hmatch IH | re1 s2 re2 Hmatch IH
| re | s1 s2 re Hmatch1 IH1 Hmatch2 IH2].
(* WORKED IN CLASS *)
- (* MEmpty *)
apply Hin.
- (* MChar *)
apply Hin.
- simpl. rewrite In_app_iff in *.
destruct Hin as [Hin | Hin].
+ (* In x s1 *)
left. apply (IH1 Hin).
+ (* In x s2 *)
right. apply (IH2 Hin).
- (* MUnionL *)
simpl. rewrite In_app_iff.
left. apply (IH Hin).
- (* MUnionR *)
simpl. rewrite In_app_iff.
right. apply (IH Hin).
- (* MStar0 *)
destruct Hin.
(** Something interesting happens in the [MStarApp] case. We obtain
_two_ induction hypotheses: One that applies when [x] occurs in
[s1] (which matches [re]), and a second one that applies when [x]
occurs in [s2] (which matches [Star re]). This is a good
illustration of why we need induction on evidence for [exp_match],
rather than induction on the regular expression [re]: The latter
would only provide an induction hypothesis for strings that match
[re], which would not allow us to reason about the case [In x
s2]. *)
- (* MStarApp *)
simpl. rewrite In_app_iff in Hin.
destruct Hin as [Hin | Hin].
+ (* In x s1 *)
apply (IH1 Hin).
+ (* In x s2 *)
apply (IH2 Hin).
Qed.
(** **** Exercise: 4 stars, standard (re_not_empty)
Write a recursive function [re_not_empty] that tests whether a
regular expression matches some string. Prove that your function
is correct. *)
Fixpoint re_not_empty {T : Type} (re : @reg_exp T) : bool
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Lemma re_not_empty_correct : forall T (re : @reg_exp T),
(exists s, s =~ re) <-> re_not_empty re = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** The [remember] Tactic *)
(** One potentially confusing feature of the [induction] tactic is
that it will let you try to perform an induction over a term that
isn't sufficiently general. The effect of this is to lose
information (much as [destruct] without an [eqn:] clause can do),
and leave you unable to complete the proof. Here's an example: *)
Lemma star_app: forall T (s1 s2 : list T) (re : @reg_exp T),
s1 =~ Star re ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
Proof.
intros T s1 s2 re H1.
(** Just doing an [inversion] on [H1] won't get us very far in
the recursive cases. (Try it!). So we need induction (on
evidence!). Here is a naive first attempt: *)
induction H1
as [|x'|s1 re1 s2' re2 Hmatch1 IH1 Hmatch2 IH2
|s1 re1 re2 Hmatch IH|re1 s2' re2 Hmatch IH
|re''|s1 s2' re'' Hmatch1 IH1 Hmatch2 IH2].
(** But now, although we get seven cases (as we would expect from the
definition of [exp_match]), we have lost a very important bit of
information from [H1]: the fact that [s1] matched something of the
form [Star re]. This means that we have to give proofs for _all_
seven constructors of this definition, even though all but two of
them ([MStar0] and [MStarApp]) are contradictory. We can still
get the proof to go through for a few constructors, such as
[MEmpty]... *)
- (* MEmpty *)
simpl. intros H. apply H.
(** ... but most cases get stuck. For [MChar], for instance, we
must show that
s2 =~ Char x' -> x' :: s2 =~ Char x',
which is clearly impossible. *)
- (* MChar. Stuck... *)
Abort.
(** The problem is that [induction] over a Prop hypothesis only works
properly with hypotheses that are completely general, i.e., ones
in which all the arguments are variables, as opposed to more
complex expressions, such as [Star re].
(In this respect, [induction] on evidence behaves more like
[destruct]-without-[eqn:] than like [inversion].)
An awkward way to solve this problem is "manually generalizing"
over the problematic expressions by adding explicit equality
hypotheses to the lemma: *)
Lemma star_app: forall T (s1 s2 : list T) (re re' : reg_exp),
re' = Star re ->
s1 =~ re' ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
(** We can now proceed by performing induction over evidence directly,
because the argument to the first hypothesis is sufficiently
general, which means that we can discharge most cases by inverting
the [re' = Star re] equality in the context.
This idiom is so common that Coq provides a tactic to
automatically generate such equations for us, avoiding thus the
need for changing the statements of our theorems. *)
Abort.
(** The tactic [remember e as x] causes Coq to (1) replace all
occurrences of the expression [e] by the variable [x], and (2) add
an equation [x = e] to the context. Here's how we can use it to
show the above result: *)
Lemma star_app: forall T (s1 s2 : list T) (re : reg_exp),
s1 =~ Star re ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
Proof.
intros T s1 s2 re H1.
remember (Star re) as re'.
(** We now have [Heqre' : re' = Star re]. *)
generalize dependent s2.
induction H1
as [|x'|s1 re1 s2' re2 Hmatch1 IH1 Hmatch2 IH2
|s1 re1 re2 Hmatch IH|re1 s2' re2 Hmatch IH
|re''|s1 s2' re'' Hmatch1 IH1 Hmatch2 IH2].
(** The [Heqre'] is contradictory in most cases, allowing us to
conclude immediately. *)
- (* MEmpty *) discriminate.
- (* MChar *) discriminate.
- (* MApp *) discriminate.
- (* MUnionL *) discriminate.
- (* MUnionR *) discriminate.
(** The interesting cases are those that correspond to [Star]. Note
that the induction hypothesis [IH2] on the [MStarApp] case
mentions an additional premise [Star re'' = Star re'], which
results from the equality generated by [remember]. *)
- (* MStar0 *)
injection Heqre'. intros Heqre'' s H. apply H.
- (* MStarApp *)
injection Heqre'. intros H0.
intros s2 H1. rewrite <- app_assoc.
apply MStarApp.
+ apply Hmatch1.
+ apply IH2.
* rewrite H0. reflexivity.
* apply H1.
Qed.
(** **** Exercise: 4 stars, standard, optional (exp_match_ex2) *)
(** The [MStar''] lemma below (combined with its converse, the
[MStar'] exercise above), shows that our definition of [exp_match]
for [Star] is equivalent to the informal one given previously. *)
Lemma MStar'' : forall T (s : list T) (re : reg_exp),
s =~ Star re ->
exists ss : list (list T),
s = fold app ss []
/\ forall s', In s' ss -> s' =~ re.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, advanced (pumping)
One of the first really interesting theorems in the theory of
regular expressions is the so-called _pumping lemma_, which
states, informally, that any sufficiently long string [s] matching
a regular expression [re] can be "pumped" by repeating some middle
section of [s] an arbitrary number of times to produce a new
string also matching [re].
To begin, we need to define "sufficiently long." Since we are
working in a constructive logic, we actually need to be able to
calculate, for each regular expression [re], the minimum length
for strings [s] to guarantee "pumpability." *)
Module Pumping.
Fixpoint pumping_constant {T} (re : @reg_exp T) : nat :=
match re with
| EmptySet => 0
| EmptyStr => 1
| Char _ => 2
| App re1 re2 =>
pumping_constant re1 + pumping_constant re2
| Union re1 re2 =>
pumping_constant re1 + pumping_constant re2
| Star _ => 1
end.
(** Next, it is useful to define an auxiliary function that repeats a
string (appends it to itself) some number of times. *)
Fixpoint napp {T} (n : nat) (l : list T) : list T :=
match n with
| 0 => []
| S n' => l ++ napp n' l
end.
Lemma napp_plus: forall T (n m : nat) (l : list T),
napp (n + m) l = napp n l ++ napp m l.
Proof.
intros T n m l.
induction n as [|n IHn].
- reflexivity.
- simpl. rewrite IHn, app_assoc. reflexivity.
Qed.
(** Now, the pumping lemma itself says that, if [s =~ re] and if the
length of [s] is at least the pumping constant of [re], then [s]
can be split into three substrings [s1 ++ s2 ++ s3] in such a way
that [s2] can be repeated any number of times and the result, when
combined with [s1] and [s3] will still match [re]. Since [s2] is
also guaranteed not to be the empty string, this gives us
a (constructive!) way to generate strings matching [re] that are
as long as we like. *)
Lemma pumping : forall T (re : @reg_exp T) s,
s =~ re ->
pumping_constant re <= length s ->
exists s1 s2 s3,
s = s1 ++ s2 ++ s3 /\
s2 <> [] /\
forall m, s1 ++ napp m s2 ++ s3 =~ re.
(** To streamline the proof (which you are to fill in), the [omega]
tactic, which is enabled by the following [Require], is helpful in
several places for automatically completing tedious low-level
arguments involving equalities or inequalities over natural
numbers. We'll return to [omega] in a later chapter, but feel
free to experiment with it now if you like. The first case of the
induction gives an example of how it is used. *)
Import Coq.omega.Omega.
Proof.
intros T re s Hmatch.
induction Hmatch
as [ | x | s1 re1 s2 re2 Hmatch1 IH1 Hmatch2 IH2
| s1 re1 re2 Hmatch IH | re1 s2 re2 Hmatch IH
| re | s1 s2 re Hmatch1 IH1 Hmatch2 IH2 ].
- (* MEmpty *)
simpl. omega.
(* FILL IN HERE *) Admitted.
End Pumping.
(** [] *)
(* ################################################################# *)
(** * Case Study: Improving Reflection *)
(** We've seen in the [Logic] chapter that we often need to
relate boolean computations to statements in [Prop]. But
performing this conversion as we did it there can result in
tedious proof scripts. Consider the proof of the following
theorem: *)
Theorem filter_not_empty_In : forall n l,
filter (fun x => n =? x) l <> [] ->
In n l.
Proof.
intros n l. induction l as [|m l' IHl'].
- (* l = [] *)
simpl. intros H. apply H. reflexivity.
- (* l = m :: l' *)
simpl. destruct (n =? m) eqn:H.
+ (* n =? m = true *)
intros _. rewrite eqb_eq in H. rewrite H.
left. reflexivity.
+ (* n =? m = false *)
intros H'. right. apply IHl'. apply H'.
Qed.
(** In the first branch after [destruct], we explicitly apply
the [eqb_eq] lemma to the equation generated by
destructing [n =? m], to convert the assumption [n =? m
= true] into the assumption [n = m]; then we had to [rewrite]
using this assumption to complete the case. *)
(** We can streamline this by defining an inductive proposition that
yields a better case-analysis principle for [n =? m].
Instead of generating an equation such as [(n =? m) = true],
which is generally not directly useful, this principle gives us
right away the assumption we really need: [n = m]. *)
Inductive reflect (P : Prop) : bool -> Prop :=
| ReflectT (H : P) : reflect P true
| ReflectF (H : ~ P) : reflect P false.
(** The [reflect] property takes two arguments: a proposition
[P] and a boolean [b]. Intuitively, it states that the property
[P] is _reflected_ in (i.e., equivalent to) the boolean [b]: that
is, [P] holds if and only if [b = true]. To see this, notice
that, by definition, the only way we can produce evidence for
[reflect P true] is by showing [P] and then using the [ReflectT]
constructor. If we invert this statement, this means that it
should be possible to extract evidence for [P] from a proof of
[reflect P true]. Similarly, the only way to show [reflect P
false] is by combining evidence for [~ P] with the [ReflectF]
constructor.
It is easy to formalize this intuition and show that the
statements [P <-> b = true] and [reflect P b] are indeed
equivalent. First, the left-to-right implication: *)
Theorem iff_reflect : forall P b, (P <-> b = true) -> reflect P b.
Proof.
(* WORKED IN CLASS *)
intros P b H. destruct b.
- apply ReflectT. rewrite H. reflexivity.
- apply ReflectF. rewrite H. intros H'. discriminate.
Qed.
(** Now you prove the right-to-left implication: *)
(** **** Exercise: 2 stars, standard, recommended (reflect_iff) *)
Theorem reflect_iff : forall P b, reflect P b -> (P <-> b = true).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The advantage of [reflect] over the normal "if and only if"
connective is that, by destructing a hypothesis or lemma of the
form [reflect P b], we can perform case analysis on [b] while at
the same time generating appropriate hypothesis in the two
branches ([P] in the first subgoal and [~ P] in the second). *)
Lemma eqbP : forall n m, reflect (n = m) (n =? m).
Proof.
intros n m. apply iff_reflect. rewrite eqb_eq. reflexivity.
Qed.
(** A smoother proof of [filter_not_empty_In] now goes as follows.
Notice how the calls to [destruct] and [apply] are combined into a
single call to [destruct]. *)
(** (To see this clearly, look at the two proofs of
[filter_not_empty_In] with Coq and observe the differences in
proof state at the beginning of the first case of the
[destruct].) *)
Theorem filter_not_empty_In' : forall n l,
filter (fun x => n =? x) l <> [] ->
In n l.
Proof.
intros n l. induction l as [|m l' IHl'].
- (* l = [] *)
simpl. intros H. apply H. reflexivity.
- (* l = m :: l' *)
simpl. destruct (eqbP n m) as [H | H].
+ (* n = m *)
intros _. rewrite H. left. reflexivity.
+ (* n <> m *)
intros H'. right. apply IHl'. apply H'.
Qed.
(** **** Exercise: 3 stars, standard, recommended (eqbP_practice)
Use [eqbP] as above to prove the following: *)
Fixpoint count n l :=
match l with
| [] => 0
| m :: l' => (if n =? m then 1 else 0) + count n l'
end.
Theorem eqbP_practice : forall n l,
count n l = 0 -> ~(In n l).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** This small example shows how reflection gives us a small gain in
convenience; in larger developments, using [reflect] consistently
can often lead to noticeably shorter and clearer proof scripts.
We'll see many more examples in later chapters and in _Programming
Language Foundations_.
The use of the [reflect] property has been popularized by
_SSReflect_, a Coq library that has been used to formalize
important results in mathematics, including as the 4-color theorem
and the Feit-Thompson theorem. The name SSReflect stands for
_small-scale reflection_, i.e., the pervasive use of reflection to
simplify small proof steps with boolean computations. *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars, standard, recommended (nostutter_defn)
Formulating inductive definitions of properties is an important
skill you'll need in this course. Try to solve this exercise
without any help at all.
We say that a list "stutters" if it repeats the same element
consecutively. (This is different from not containing duplicates:
the sequence [[1;4;1]] repeats the element [1] but does not
stutter.) The property "[nostutter mylist]" means that [mylist]
does not stutter. Formulate an inductive definition for
[nostutter]. *)
Inductive nostutter {X:Type} : list X -> Prop :=
(* FILL IN HERE *)
.
(** Make sure each of these tests succeeds, but feel free to change
the suggested proof (in comments) if the given one doesn't work
for you. Your definition might be different from ours and still
be correct, in which case the examples might need a different
proof. (You'll notice that the suggested proofs use a number of
tactics we haven't talked about, to make them more robust to
different possible ways of defining [nostutter]. You can probably
just uncomment and use them as-is, but you can also prove each
example with more basic tactics.) *)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply eqb_neq; auto.
Qed.
*)
Example test_nostutter_2: nostutter (@nil nat).
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply eqb_neq; auto.
Qed.
*)
Example test_nostutter_3: nostutter [5].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply eqb_false; auto. Qed.
*)
Example test_nostutter_4: not (nostutter [3;1;1;4]).
(* FILL IN HERE *) Admitted.
(*
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction Hneq0; auto. Qed.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_nostutter : option (nat*string) := None.
(** [] *)
(** **** Exercise: 4 stars, advanced (filter_challenge)
Let's prove that our definition of [filter] from the [Poly]
chapter matches an abstract specification. Here is the
specification, written out informally in English:
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1;4;6;2;3]
is an in-order merge of
[1;6;2]
and
[4;3].
Now, suppose we have a set [X], a function [test: X->bool], and a
list [l] of type [list X]. Suppose further that [l] is an
in-order merge of two lists, [l1] and [l2], such that every item
in [l1] satisfies [test] and no item in [l2] satisfies test. Then
[filter test l = l1].
Translate this specification into a Coq theorem and prove
it. (You'll need to begin by defining what it means for one list
to be a merge of two others. Do this with an inductive relation,
not a [Fixpoint].) *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_filter_challenge : option (nat*string) := None.
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (filter_challenge_2)
A different way to characterize the behavior of [filter] goes like
this: Among all subsequences of [l] with the property that [test]
evaluates to [true] on all their members, [filter test l] is the
longest. Formalize this claim and prove it. *)
(* FILL IN HERE
[] *)
(** **** Exercise: 4 stars, standard, optional (palindromes)
A palindrome is a sequence that reads the same backwards as
forwards.
- Define an inductive proposition [pal] on [list X] that
captures what it means to be a palindrome. (Hint: You'll need
three cases. Your definition should be based on the structure
of the list; just having a single constructor like
c : forall l, l = rev l -> pal l
may seem obvious, but will not work very well.)
- Prove ([pal_app_rev]) that
forall l, pal (l ++ rev l).
- Prove ([pal_rev] that)
forall l, pal l -> l = rev l.
*)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_pal_pal_app_rev_pal_rev : option (nat*string) := None.
(** [] *)
(** **** Exercise: 5 stars, standard, optional (palindrome_converse)
Again, the converse direction is significantly more difficult, due
to the lack of evidence. Using your definition of [pal] from the
previous exercise, prove that
forall l, l = rev l -> pal l.
*)
(* FILL IN HERE
[] *)
(** **** Exercise: 4 stars, advanced, optional (NoDup)
Recall the definition of the [In] property from the [Logic]
chapter, which asserts that a value [x] appears at least once in a
list [l]: *)
(* Fixpoint In (A : Type) (x : A) (l : list A) : Prop :=
match l with
| [] => False
| x' :: l' => x' = x \/ In A x l'
end *)
(** Your first task is to use [In] to define a proposition [disjoint X
l1 l2], which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in
common. *)
(* FILL IN HERE *)
(** Next, use [In] to define an inductive proposition [NoDup X
l], which should be provable exactly when [l] is a list (with
elements of type [X]) where every member is different from every
other. For example, [NoDup nat [1;2;3;4]] and [NoDup
bool []] should be provable, while [NoDup nat [1;2;1]] and
[NoDup bool [true;true]] should not be. *)
(* FILL IN HERE *)
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [NoDup] and [++] (list append). *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_NoDup_disjoint_etc : option (nat*string) := None.
(** [] *)
(** **** Exercise: 4 stars, advanced, optional (pigeonhole_principle)
The _pigeonhole principle_ states a basic fact about counting: if
we distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As often happens, this
apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First prove an easy useful lemma. *)
Lemma in_split : forall (X:Type) (x:X) (l:list X),
In x l ->
exists l1 l2, l = l1 ++ x :: l2.
Proof.
(* FILL IN HERE *) Admitted.
(** Now define a property [repeats] such that [repeats X l] asserts
that [l] contains at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
(* FILL IN HERE *)
.
(** Now, here's a way to formalize the pigeonhole principle. Suppose
list [l2] represents a list of pigeonhole labels, and list [l1]
represents the labels assigned to a list of items. If there are
more items than labels, at least two items must have the same
label -- i.e., list [l1] must contain repeats.
This proof is much easier if you use the [excluded_middle]
hypothesis to show that [In] is decidable, i.e., [forall x l, (In x
l) \/ ~ (In x l)]. However, it is also possible to make the proof
go through _without_ assuming that [In] is decidable; if you
manage to do this, you will not need the [excluded_middle]
hypothesis. *)
Theorem pigeonhole_principle: forall (X:Type) (l1 l2:list X),
excluded_middle ->
(forall x, In x l1 -> In x l2) ->
length l2 < length l1 ->
repeats l1.
Proof.
intros X l1. induction l1 as [|x l1' IHl1'].
(* FILL IN HERE *) Admitted.
(* Do not modify the following line: *)
Definition manual_grade_for_check_repeats : option (nat*string) := None.
(** [] *)
(* ================================================================= *)
(** ** Extended Exercise: A Verified Regular-Expression Matcher *)
(** We have now defined a match relation over regular expressions and
polymorphic lists. We can use such a definition to manually prove that
a given regex matches a given string, but it does not give us a
program that we can run to determine a match autmatically.
It would be reasonable to hope that we can translate the definitions
of the inductive rules for constructing evidence of the match relation
into cases of a recursive function reflects the relation by recursing
on a given regex. However, it does not seem straightforward to define
such a function in which the given regex is a recursion variable
recognized by Coq. As a result, Coq will not accept that the function
always terminates.
Heavily-optimized regex matchers match a regex by translating a given
regex into a state machine and determining if the state machine
accepts a given string. However, regex matching can also be
implemented using an algorithm that operates purely on strings and
regexes without defining and maintaining additional datatypes, such as
state machines. We'll implemement such an algorithm, and verify that
its value reflects the match relation. *)
(** We will implement a regex matcher that matches strings represented
as lists of ASCII characters: *)
Require Export Coq.Strings.Ascii.
Definition string := list ascii.
(** The Coq standard library contains a distinct inductive definition
of strings of ASCII characters. However, we will use the above
definition of strings as lists as ASCII characters in order to apply
the existing definition of the match relation.
We could also define a regex matcher over polymorphic lists, not lists
of ASCII characters specifically. The matching algorithm that we will
implement needs to be able to test equality of elements in a given
list, and thus needs to be given an equality-testing
function. Generalizing the definitions, theorems, and proofs that we
define for such a setting is a bit tedious, but workable. *)
(** The proof of correctness of the regex matcher will combine
properties of the regex-matching function with properties of the
[match] relation that do not depend on the matching function. We'll go
ahead and prove the latter class of properties now. Most of them have
straightforward proofs, which have been given to you, although there
are a few key lemmas that are left for you to prove. *)
(** Each provable [Prop] is equivalent to [True]. *)
Lemma provable_equiv_true : forall (P : Prop), P -> (P <-> True).
Proof.
intros.
split.
- intros. constructor.
- intros _. apply H.
Qed.
(** Each [Prop] whose negation is provable is equivalent to [False]. *)
Lemma not_equiv_false : forall (P : Prop), ~P -> (P <-> False).
Proof.
intros.
split.
- apply H.
- intros. destruct H0.
Qed.
(** [EmptySet] matches no string. *)
Lemma null_matches_none : forall (s : string), (s =~ EmptySet) <-> False.
Proof.
intros.
apply not_equiv_false.
unfold not. intros. inversion H.
Qed.
(** [EmptyStr] only matches the empty string. *)
Lemma empty_matches_eps : forall (s : string), s =~ EmptyStr <-> s = [ ].
Proof.
split.
- intros. inversion H. reflexivity.
- intros. rewrite H. apply MEmpty.
Qed.
(** [EmptyStr] matches no non-empty string. *)
Lemma empty_nomatch_ne : forall (a : ascii) s, (a :: s =~ EmptyStr) <-> False.
Proof.
intros.
apply not_equiv_false.
unfold not. intros. inversion H.
Qed.
(** [Char a] matches no string that starts with a non-[a] character. *)
Lemma char_nomatch_char :
forall (a b : ascii) s, b <> a -> (b :: s =~ Char a <-> False).
Proof.
intros.
apply not_equiv_false.
unfold not.
intros.
apply H.
inversion H0.
reflexivity.
Qed.
(** If [Char a] matches a non-empty string, then the string's tail is empty. *)
Lemma char_eps_suffix : forall (a : ascii) s, a :: s =~ Char a <-> s = [ ].
Proof.
split.
- intros. inversion H. reflexivity.
- intros. rewrite H. apply MChar.
Qed.
(** [App re0 re1] matches string [s] iff [s = s0 ++ s1], where [s0]
matches [re0] and [s1] matches [re1]. *)
Lemma app_exists : forall (s : string) re0 re1,
s =~ App re0 re1 <->
exists s0 s1, s = s0 ++ s1 /\ s0 =~ re0 /\ s1 =~ re1.
Proof.
intros.
split.
- intros. inversion H. exists s1, s2. split.
* reflexivity.
* split. apply H3. apply H4.
- intros [ s0 [ s1 [ Happ [ Hmat0 Hmat1 ] ] ] ].
rewrite Happ. apply (MApp s0 _ s1 _ Hmat0 Hmat1).
Qed.
(** **** Exercise: 3 stars, standard, optional (app_ne)
[App re0 re1] matches [a::s] iff [re0] matches the empty string
and [a::s] matches [re1] or [s=s0++s1], where [a::s0] matches [re0]
and [s1] matches [re1].
Even though this is a property of purely the match relation, it is a
critical observation behind the design of our regex matcher. So (1)
take time to understand it, (2) prove it, and (3) look for how you'll
use it later. *)
Lemma app_ne : forall (a : ascii) s re0 re1,
a :: s =~ (App re0 re1) <->
([ ] =~ re0 /\ a :: s =~ re1) \/
exists s0 s1, s = s0 ++ s1 /\ a :: s0 =~ re0 /\ s1 =~ re1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** [s] matches [Union re0 re1] iff [s] matches [re0] or [s] matches [re1]. *)
Lemma union_disj : forall (s : string) re0 re1,
s =~ Union re0 re1 <-> s =~ re0 \/ s =~ re1.
Proof.
intros. split.
- intros. inversion H.
+ left. apply H2.
+ right. apply H1.
- intros [ H | H ].
+ apply MUnionL. apply H.
+ apply MUnionR. apply H.
Qed.
(** **** Exercise: 3 stars, standard, optional (star_ne)
[a::s] matches [Star re] iff [s = s0 ++ s1], where [a::s0] matches
[re] and [s1] matches [Star re]. Like [app_ne], this observation is
critical, so understand it, prove it, and keep it in mind.
Hint: you'll need to perform induction. There are quite a few
reasonable candidates for [Prop]'s to prove by induction. The only one
that will work is splitting the [iff] into two implications and
proving one by induction on the evidence for [a :: s =~ Star re]. The
other implication can be proved without induction.
In order to prove the right property by induction, you'll need to
rephrase [a :: s =~ Star re] to be a [Prop] over general variables,
using the [remember] tactic. *)
Lemma star_ne : forall (a : ascii) s re,
a :: s =~ Star re <->
exists s0 s1, s = s0 ++ s1 /\ a :: s0 =~ re /\ s1 =~ Star re.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The definition of our regex matcher will include two fixpoint
functions. The first function, given regex [re], will evaluate to a
value that reflects whether [re] matches the empty string. The
function will satisfy the following property: *)
Definition refl_matches_eps m :=
forall re : @reg_exp ascii, reflect ([ ] =~ re) (m re).
(** **** Exercise: 2 stars, standard, optional (match_eps)
Complete the definition of [match_eps] so that it tests if a given
regex matches the empty string: *)
Fixpoint match_eps (re: @reg_exp ascii) : bool
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (match_eps_refl)
Now, prove that [match_eps] indeed tests if a given regex matches
the empty string. (Hint: You'll want to use the reflection lemmas
[ReflectT] and [ReflectF].) *)
Lemma match_eps_refl : refl_matches_eps match_eps.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We'll define other functions that use [match_eps]. However, the
only property of [match_eps] that you'll need to use in all proofs
over these functions is [match_eps_refl]. *)
(** The key operation that will be performed by our regex matcher will
be to iteratively construct a sequence of regex derivatives. For each
character [a] and regex [re], the derivative of [re] on [a] is a regex
that matches all suffixes of strings matched by [re] that start with
[a]. I.e., [re'] is a derivative of [re] on [a] if they satisfy the
following relation: *)
Definition is_der re (a : ascii) re' :=
forall s, a :: s =~ re <-> s =~ re'.
(** A function [d] derives strings if, given character [a] and regex
[re], it evaluates to the derivative of [re] on [a]. I.e., [d]
satisfies the following property: *)
Definition derives d := forall a re, is_der re a (d a re).
(** **** Exercise: 3 stars, standard, optional (derive)
Define [derive] so that it derives strings. One natural
implementation uses [match_eps] in some cases to determine if key
regex's match the empty string. *)
Fixpoint derive (a : ascii) (re : @reg_exp ascii) : @reg_exp ascii
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(** The [derive] function should pass the following tests. Each test
establishes an equality between an expression that will be
evaluated by our regex matcher and the final value that must be
returned by the regex matcher. Each test is annotated with the
match fact that it reflects. *)
Example c := ascii_of_nat 99.
Example d := ascii_of_nat 100.
(** "c" =~ EmptySet: *)
Example test_der0 : match_eps (derive c (EmptySet)) = false.
Proof.
(* FILL IN HERE *) Admitted.
(** "c" =~ Char c: *)
Example test_der1 : match_eps (derive c (Char c)) = true.
Proof.
(* FILL IN HERE *) Admitted.
(** "c" =~ Char d: *)
Example test_der2 : match_eps (derive c (Char d)) = false.
Proof.
(* FILL IN HERE *) Admitted.
(** "c" =~ App (Char c) EmptyStr: *)
Example test_der3 : match_eps (derive c (App (Char c) EmptyStr)) = true.
Proof.
(* FILL IN HERE *) Admitted.
(** "c" =~ App EmptyStr (Char c): *)
Example test_der4 : match_eps (derive c (App EmptyStr (Char c))) = true.
Proof.
(* FILL IN HERE *) Admitted.
(** "c" =~ Star c: *)
Example test_der5 : match_eps (derive c (Star (Char c))) = true.
Proof.
(* FILL IN HERE *) Admitted.
(** "cd" =~ App (Char c) (Char d): *)
Example test_der6 :
match_eps (derive d (derive c (App (Char c) (Char d)))) = true.
Proof.
(* FILL IN HERE *) Admitted.
(** "cd" =~ App (Char d) (Char c): *)
Example test_der7 :
match_eps (derive d (derive c (App (Char d) (Char c)))) = false.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 4 stars, standard, optional (derive_corr)
Prove that [derive] in fact always derives strings.
Hint: one proof performs induction on [re], although you'll need
to carefully choose the property that you prove by induction by
generalizing the appropriate terms.
Hint: if your definition of [derive] applies [match_eps] to a
particular regex [re], then a natural proof will apply
[match_eps_refl] to [re] and destruct the result to generate cases
with assumptions that the [re] does or does not match the empty
string.
Hint: You can save quite a bit of work by using lemmas proved
above. In particular, to prove many cases of the induction, you
can rewrite a [Prop] over a complicated regex (e.g., [s =~ Union
re0 re1]) to a Boolean combination of [Prop]'s over simple
regex's (e.g., [s =~ re0 \/ s =~ re1]) using lemmas given above
that are logical equivalences. You can then reason about these
[Prop]'s naturally using [intro] and [destruct]. *)
Lemma derive_corr : derives derive.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We'll define the regex matcher using [derive]. However, the only
property of [derive] that you'll need to use in all proofs of
properties of the matcher is [derive_corr]. *)
(** A function [m] matches regexes if, given string [s] and regex [re],
it evaluates to a value that reflects whether [s] is matched by
[re]. I.e., [m] holds the following property: *)
Definition matches_regex m : Prop :=
forall (s : string) re, reflect (s =~ re) (m s re).
(** **** Exercise: 2 stars, standard, optional (regex_match)
Complete the definition of [regex_match] so that it matches
regexes. *)
Fixpoint regex_match (s : string) (re : @reg_exp ascii) : bool
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (regex_refl)
Finally, prove that [regex_match] in fact matches regexes.
Hint: if your definition of [regex_match] applies [match_eps] to
regex [re], then a natural proof applies [match_eps_refl] to [re]
and destructs the result to generate cases in which you may assume
that [re] does or does not match the empty string.
Hint: if your definition of [regex_match] applies [derive] to
character [x] and regex [re], then a natural proof applies
[derive_corr] to [x] and [re] to prove that [x :: s =~ re] given
[s =~ derive x re], and vice versa. *)
Theorem regex_refl : matches_regex regex_match.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* Wed Jan 9 12:02:45 EST 2019 *)
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 16.0 cbx_altiobuf_out 2016:04:20:18:35:29:SJ cbx_mgl 2016:04:20:19:36:45:SJ cbx_stratixiii 2016:04:20:18:35:29:SJ cbx_stratixv 2016:04:20:18:35:29:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
//////////////////////////////////////////////////////////////////////
//// ////
//// writeUSBWireData.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`define BUFFER_FULL 3'b100
module writeUSBWireData (
TxBitsIn,
TxBitsOut,
TxDataOutTick,
TxCtrlIn,
TxCtrlOut,
USBWireRdy,
USBWireWEn,
TxWireActiveDrive,
fullSpeedRate,
clk,
rst
);
input [1:0] TxBitsIn;
input TxCtrlIn;
input USBWireWEn;
input clk;
input fullSpeedRate;
input rst;
output [1:0] TxBitsOut;
output TxDataOutTick;
output TxCtrlOut;
output USBWireRdy;
output TxWireActiveDrive;
wire [1:0] TxBitsIn;
reg [1:0] TxBitsOut;
reg TxDataOutTick;
wire TxCtrlIn;
reg TxCtrlOut;
reg USBWireRdy;
wire USBWireWEn;
wire clk;
wire fullSpeedRate;
wire rst;
reg TxWireActiveDrive;
// local registers
reg [3:0]buffer0;
reg [3:0]buffer1;
reg [3:0]buffer2;
reg [3:0]buffer3;
reg [2:0]bufferCnt;
reg [1:0]bufferInIndex;
reg [1:0]bufferOutIndex;
reg decBufferCnt;
reg [4:0]i;
reg incBufferCnt;
reg fullSpeedTick;
reg lowSpeedTick;
reg fullSpeedRate_reg;
// buffer in state machine state codes:
`define WAIT_BUFFER_NOT_FULL 2'b00
`define WAIT_WRITE_REQ 2'b01
`define CLR_INC_BUFFER_CNT 2'b10
// buffer output state machine state codes:
`define WAIT_BUFFER_FULL 2'b00
`define WAIT_LINE_WRITE 2'b01
`define LINE_WRITE 2'b10
reg [1:0] bufferInStMachCurrState;
reg [1:0] bufferOutStMachCurrState;
// buffer control
always @(posedge clk)
begin
if (rst == 1'b1)
begin
bufferCnt <= 3'b000;
end
else
begin
if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
bufferCnt <= bufferCnt + 1'b1;
else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
bufferCnt <= bufferCnt - 1'b1;
end
end
//buffer input state machine
always @(posedge clk) begin
if (rst == 1'b1) begin
incBufferCnt <= 1'b0;
bufferInIndex <= 2'b00;
buffer0 <= 4'b0000;
buffer1 <= 4'b0000;
buffer2 <= 4'b0000;
buffer3 <= 4'b0000;
USBWireRdy <= 1'b0;
bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
end
else begin
case (bufferInStMachCurrState)
`WAIT_BUFFER_NOT_FULL:
begin
if (bufferCnt != `BUFFER_FULL)
begin
bufferInStMachCurrState <= `WAIT_WRITE_REQ;
USBWireRdy <= 1'b1;
end
end
`WAIT_WRITE_REQ:
begin
if (USBWireWEn == 1'b1)
begin
incBufferCnt <= 1'b1;
USBWireRdy <= 1'b0;
bufferInIndex <= bufferInIndex + 1'b1;
case (bufferInIndex)
2'b00 : buffer0 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
2'b01 : buffer1 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
2'b10 : buffer2 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
2'b11 : buffer3 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
endcase
bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
end
end
`CLR_INC_BUFFER_CNT:
begin
incBufferCnt <= 1'b0;
if (bufferCnt != (`BUFFER_FULL - 1'b1) )
begin
bufferInStMachCurrState <= `WAIT_WRITE_REQ;
USBWireRdy <= 1'b1;
end
else begin
bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
end
end
endcase
end
end
//increment counter used to generate USB bit rate
always @(posedge clk) begin
if (rst == 1'b1)
begin
i <= 5'b00000;
fullSpeedTick <= 1'b0;
lowSpeedTick <= 1'b0;
end
else
begin
i <= i + 1'b1;
if (i[1:0] == 2'b00)
fullSpeedTick <= 1'b1;
else
fullSpeedTick <= 1'b0;
if (i == 5'b00000)
lowSpeedTick <= 1'b1;
else
lowSpeedTick <= 1'b0;
end
end
//buffer output state machine
//buffer is constantly emptied at either
//the full or low speed rate
//if the buffer is empty, then the output is forced to tri-state
always @(posedge clk) begin
if (rst == 1'b1)
begin
bufferOutIndex <= 2'b00;
decBufferCnt <= 1'b0;
TxBitsOut <= 2'b00;
TxCtrlOut <= `TRI_STATE;
TxDataOutTick <= 1'b0;
bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
fullSpeedRate_reg <= 1'b0;
end
else
begin
case (bufferOutIndex)
2'b00: fullSpeedRate_reg <= buffer0[3];
2'b01: fullSpeedRate_reg <= buffer1[3];
2'b10: fullSpeedRate_reg <= buffer2[3];
2'b11: fullSpeedRate_reg <= buffer3[3];
endcase
case (bufferOutStMachCurrState)
`WAIT_LINE_WRITE:
begin
if ((fullSpeedRate_reg == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate_reg == 1'b0 && lowSpeedTick == 1'b1) )
begin
TxDataOutTick <= !TxDataOutTick;
if (bufferCnt == 0) begin
TxBitsOut <= 2'b00;
TxCtrlOut <= `TRI_STATE;
end
else begin
bufferOutStMachCurrState <= `LINE_WRITE;
decBufferCnt <= 1'b1;
bufferOutIndex <= bufferOutIndex + 1'b1;
case (bufferOutIndex)
2'b00 :
begin
TxBitsOut <= buffer0[2:1];
TxCtrlOut <= buffer0[0];
end
2'b01 :
begin
TxBitsOut <= buffer1[2:1];
TxCtrlOut <= buffer1[0];
end
2'b10 :
begin
TxBitsOut <= buffer2[2:1];
TxCtrlOut <= buffer2[0];
end
2'b11 :
begin
TxBitsOut <= buffer3[2:1];
TxCtrlOut <= buffer3[0];
end
endcase
end
end
end
`LINE_WRITE:
begin
decBufferCnt <= 1'b0;
bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
end
endcase
end
end
// control 'TxWireActiveDrive'
always @(TxCtrlOut)
begin
if (TxCtrlOut == `DRIVE)
TxWireActiveDrive <= 1'b1;
else
TxWireActiveDrive <= 1'b0;
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_2_ar_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] automatically performs
simplification.) *)
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool := negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool := andb b1 (andb b2 b3).
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S n' => n * factorial n'
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool := andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** We could try to prove a similar theorem about [plus] *)
Theorem plus_n_O : forall n, n + 0 = n.
(** However, unlike the previous proof, [simpl] doesn't do anything in
this case *)
Proof.
simpl. (* Doesn't do anything! *)
Abort.
(** (Can you explain why this happens? Step through both proofs with
Coq and notice how the goal and context change.) *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o H I.
rewrite -> H.
rewrite -> I.
reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m H.
rewrite -> H.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n.
destruct n as [| n'].
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
rewrite -> H.
rewrite -> H.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
rewrite -> H.
rewrite -> H.
destruct b.
reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b as [false | true].
simpl.
intros H.
rewrite -> H.
reflexivity.
simpl.
intros I.
rewrite -> I.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
Inductive binary : Type :=
| zero : binary
| double : binary -> binary
| double_plus_one : binary -> binary.
Fixpoint incr (b : binary) : binary :=
match b with
| zero => double_plus_one zero
| double b' => double_plus_one b'
| double_plus_one b' => double (incr b')
end.
Fixpoint bin_to_nat (b : binary) : nat :=
match b with
| zero => 0
| double b' => 2 * bin_to_nat b'
| double_plus_one b' => 1 + 2 * bin_to_nat b'
end.
Example test_bin_incr1 : bin_to_nat (incr zero) = 1 + bin_to_nat zero.
Proof. reflexivity. Qed.
Example test_bin_incr2 : bin_to_nat (incr (double_plus_one zero)) = 1 + bin_to_nat (double_plus_one zero).
Proof. reflexivity. Qed.
Example test_bin_incr3 : bin_to_nat (incr (double (double_plus_one zero))) = 1 + bin_to_nat (double (double_plus_one zero)).
Proof. reflexivity. Qed.
Example test_bin_incr4 : bin_to_nat (incr (double_plus_one (double_plus_one zero))) = 1 + bin_to_nat (double_plus_one (double_plus_one zero)).
Proof. reflexivity. Qed.
Example test_bin_incr5 : bin_to_nat (incr (double (double (double_plus_one zero)))) = 1 + bin_to_nat (double (double (double_plus_one zero))).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
Fixpoint decreasing (n m : nat) : nat :=
match n, m with
| 0, 0 => 0
| 0, n => decreasing 0 (n - 1)
| n, m => decreasing (n - 1) m
end.
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
module decoder (cx,d);
output [2:0] d;
input [8:0] cx;
reg [2:0] d;
reg [5:0] s;
reg [8:0] cx1;
parameter s0 = 6'b011001;
parameter s1 = 6'b010010;
parameter s2 = 6'b101010;
parameter s3 = 6'b100000;
parameter s4 = 6'b010000;
parameter s5 = 6'b001000;
parameter s6 = 6'b000100;
parameter s7 = 6'b000010;
parameter s8 = 6'b000001;
always @(cx)
begin
cx1[0] = cx[0];
cx1[1] = cx[1];
cx1[2] = cx[2];
cx1[3] = cx[3];
cx1[4] = cx[4];
cx1[5] = cx[5];
cx1[6] = cx[6];
cx1[7] = cx[7];
cx1[8] = cx[8];
s[0]= cx[2]+ cx[3];
s[1]= cx[0]+ cx[1]+ cx[4];
s[2]= cx[0]+ cx[2]+ cx[5];
s[3]= cx[6];
s[4]= cx[1]+ cx[2]+ cx[7];
s[5]= cx[0]+ cx[8];
case(s)
s0:
begin
if(cx[0]==1'b0)
begin
cx1[0]=1'b1;
end
else
begin
cx1[0]=1'b0;
end
end
s1:
begin
if(cx[1]==1'b0)
begin
cx1[1]=1'b1;
end
else
begin
cx1[1]=1'b0;
end
end
s2:
begin
if(cx[2]==1'b0)
begin
cx1[2]=1'b1;
end
else
begin
cx1[2]=1'b0;
end
end
s3:
begin
if(cx[3]==1'b0)
begin
cx1[3]=1'b1;
end
else
begin
cx1[3]=1'b0;
end
end
s4:
begin
if(cx[4]==1'b0)
begin
cx1[4]=1'b1;
end
else
begin
cx1[4]=1'b0;
end
end
s5:
begin
if(cx[5]==1'b0)
begin
cx1[5]=1'b1;
end
else
begin
cx1[5]=1'b0;
end
end
s6:
begin
if(cx[6]==1'b0)
begin
cx1[6]=1'b1;
end
else
begin
cx1[6]=1'b0;
end
end
s7:
begin
if(cx[7]==1'b0)
begin
cx1[7]=1'b1;
end
else
begin
cx1[7]=1'b0;
end
end
s8:
begin
if(cx[8]==1'b0)
begin
cx1[8]=1'b1;
end
else
begin
cx1[8]=1'b0;
end
end
default:
begin
cx1[0]=cx[0];
cx1[1]=cx[1];
cx1[2]=cx[2];
cx1[3]=cx[3];
cx1[4]=cx[4];
cx1[5]=cx[5];
cx1[6]=cx[6];
cx1[7]=cx[7];
cx1[8]=cx[8];
end
endcase
d[0] = cx1[0];
d[1] = cx1[1];
d[2] = cx1[2];
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_decim
( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
parameter bw = 16;
parameter N = 4;
parameter log2_of_max_rate = 7;
parameter maxbitgain = N * log2_of_max_rate;
input clock;
input reset;
input enable;
input [7:0] rate;
input strobe_in,strobe_out;
input [bw-1:0] signal_in;
output [bw-1:0] signal_out;
reg [bw-1:0] signal_out;
wire [bw-1:0] signal_out_unreg;
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
reg [bw+maxbitgain-1:0] sampler;
integer i;
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
always @(posedge clock)
if(reset)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable && strobe_in)
begin
integrator[0] <= #1 integrator[0] + signal_in_ext;
for(i=1;i<N;i=i+1)
integrator[i] <= #1 integrator[i] + integrator[i-1];
end
always @(posedge clock)
if(reset)
begin
sampler <= #1 0;
for(i=0;i<N;i=i+1)
begin
pipeline[i] <= #1 0;
differentiator[i] <= #1 0;
end
end
else if (enable && strobe_out)
begin
sampler <= #1 integrator[N-1];
differentiator[0] <= #1 sampler;
pipeline[0] <= #1 sampler - differentiator[0];
for(i=1;i<N;i=i+1)
begin
differentiator[i] <= #1 pipeline[i-1];
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
end
end // if (enable && strobe_out)
wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
cic_dec_shifter #(bw)
cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg);
always @(posedge clock)
signal_out <= #1 signal_out_unreg;
endmodule // cic_decim
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:26:36 07/12/2015
// Design Name:
// Module Name: MemoryAdapter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MemoryAdapter
( input PixelClk2,
output reg [23:0] ExtAddr,
output reg [15:0] ExtDataWrite,
output reg [1:0] ExtDataMask,
input [15:0] ExtDataRead,
output reg ExtOP,
output reg ExtReq,
input ExtReady,
input [24:0] Address,
input [31:0] DataWrite,
output reg [31:0] DataRead,
input [1:0] DataSize, // 01: 8bit - 11: 32bit - 00|10: 16bit
input ReadWrite,
input Request,
output reg Ready
);
integer Status;
reg [24:0] SaveAddr;
reg [31:0] SaveData;
reg [1:0] SaveSize;
reg SaveOP;
initial
begin
Status = 0;
ExtReq = 0;
DataRead = 0;
ExtAddr = 0;
ExtDataWrite = 0;
ExtDataMask = 0;
ExtOP = 0;
Ready = 0;
end
always @(posedge PixelClk2)
begin
case(Status)
0: begin
Ready = 1;
Status = 1;
end
1: begin
if (Request == 1)
begin
SaveAddr = Address;
SaveData = DataWrite;
SaveSize = (DataSize == 2'b00) ? 2'b10 : DataSize;
SaveOP = ReadWrite;
Ready = 0;
Status = 2;
end
else Status = 1;
end
2: begin
if (ExtReady == 1)
begin
case(SaveOP)
1: begin // WRITE
case(SaveSize)
2'b01: begin // Byte
ExtAddr = SaveAddr[24:1];
ExtDataWrite = (SaveAddr[0]==0) ? {8'h00,SaveData[7:0]} : {SaveData[7:0],8'h00};
ExtDataMask = (SaveAddr[0]==0) ? 2'b10 : 2'b01;
ExtOP = 1;
ExtReq = 1;
Status = 3;
end
2'b11: begin // Double
ExtAddr = {SaveAddr[24:2],1'b0};
ExtDataWrite = SaveData[15:0];
ExtDataMask = 2'b00;
ExtOP = 1;
ExtReq = 1;
Status = 6;
end
default: begin // Word
ExtAddr = SaveAddr[24:1];
ExtDataWrite = SaveData[15:0];
ExtDataMask = 2'b00;
ExtOP = 1;
ExtReq = 1;
Status = 3;
end
endcase
end
default: begin // READ
case(SaveSize)
2'b01: begin // Byte
ExtAddr = SaveAddr[24:1];
ExtDataMask = 2'b00;
ExtOP = 0;
ExtReq = 1;
Status = 5;
end
2'b11: begin // Double
ExtAddr = {SaveAddr[24:2],1'b0};
ExtDataMask = 2'b00;
ExtOP = 0;
ExtReq = 1;
Status = 8;
end
default: begin // Word
ExtAddr = SaveAddr[24:1];
ExtDataMask = 2'b00;
ExtOP = 0;
ExtReq = 1;
Status = 4;
end
endcase
end
endcase
end
else Status = 2;
end
3: begin
if (ExtReady == 0) Status = 0;
else Status = 3;
end
4: begin
if (ExtReady == 0)
begin
DataRead = {16'h0000,ExtDataRead};
Status = 0;
end
else Status = 4;
end
5: begin
if (ExtReady == 0)
begin
DataRead = (SaveAddr[0]==1) ? {24'h000000,ExtDataRead[7:0]} : {24'h000000,ExtDataRead[15:8]};
Status = 0;
end
else Status = 5;
end
6: begin
if (ExtReady == 0) Status = 7;
else Status = 6;
end
7: begin
if (ExtReady == 1)
begin
ExtAddr = {SaveAddr[24:2],1'b1};
ExtDataWrite = SaveData[31:16];
ExtDataMask = 2'b00;
ExtOP = 1;
ExtReq = 1;
Status = 3;
end
else Status = 7;
end
8: begin
if (ExtReady == 0)
begin
DataRead[15:0] = ExtDataRead;
Status = 9;
end
else Status = 8;
end
9: begin
if (ExtReady == 1)
begin
ExtAddr = {SaveAddr[24:2],1'b1};
ExtDataMask = 2'b00;
ExtOP = 0;
ExtReq = 1;
Status = 10;
end
else Status = 9;
end
10: begin
if (ExtReady == 0)
begin
DataRead[31:16] = ExtDataRead;
Status = 0;
end
else Status = 10;
end
endcase
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the tx_engine and buffers the input
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
input TXN_DONE_ACK, // Write transaction actual transfer length read
input [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather data
input SG_DATA_EMPTY, // Scatter gather buffer empty
output SG_DATA_REN, // Scatter gather data read enable
output SG_RST, // Scatter gather reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire wGateRen;
wire wGateEmpty;
wire [C_DATA_WIDTH:0] wGateData;
wire wBufWen;
wire [C_FIFO_DEPTH_WIDTH-1:0] wBufCount;
wire [C_DATA_WIDTH-1:0] wBufData;
wire wTxn;
wire wTxnAck;
wire wTxnLast;
wire [31:0] wTxnLen;
wire [30:0] wTxnOff;
wire [31:0] wTxnWordsRecvd;
wire wTxnDone;
wire wTxnErr;
wire wSgElemRen;
wire wSgElemRdy;
wire wSgElemEmpty;
wire [31:0] wSgElemLen;
wire [63:0] wSgElemAddr;
wire wTxLast;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Capture channel transaction open/close events as well as channel data.
tx_port_channel_gate_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.RD_CLK(CLK),
.RD_DATA(wGateData),
.RD_EMPTY(wGateEmpty),
.RD_EN(wGateRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
// Filter transaction events from channel data. Use the events to put only
// the requested amount of data into the port buffer.
tx_port_monitor_64 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
.RST(rRst),
.CLK(CLK),
.EVT_DATA(wGateData),
.EVT_DATA_EMPTY(wGateEmpty),
.EVT_DATA_RD_EN(wGateRen),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount),
.TXN(wTxn),
.ACK(wTxnAck),
.LAST(wTxnLast),
.LEN(wTxnLen),
.OFF(wTxnOff),
.WORDS_RECVD(wTxnWordsRecvd),
.DONE(wTxnDone),
.TX_ERR(SG_ERR)
);
// Buffer the incoming channel data. Also make sure to discard only as
// much data as is needed for a transfer (which may involve non-integral
// packets (i.e. reading only 1 word out of the packet).
tx_port_buffer_64 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
.CLK(CLK),
.RST(rRst | (TXN_DONE & wTxnErr)),
.RD_DATA(TX_DATA),
.RD_EN(TX_DATA_REN),
.LEN_VALID(TX_REQ_ACK),
.LEN_LSB(TX_LEN[0]),
.LEN_LAST(wTxLast),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | SG_RST),
.BUF_DATA(SG_DATA),
.BUF_DATA_EMPTY(SG_DATA_EMPTY),
.BUF_DATA_REN(SG_DATA_REN),
.VALID(wSgElemRdy),
.EMPTY(wSgElemEmpty),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Controls the flow of request to the tx engine for transfers in a transaction.
tx_port_writer writer (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN),
.TXN_ACK(TXN_ACK),
.TXN_LEN(TXN_LEN),
.TXN_OFF_LAST(TXN_OFF_LAST),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.NEW_TXN(wTxn),
.NEW_TXN_ACK(wTxnAck),
.NEW_TXN_LAST(wTxnLast),
.NEW_TXN_LEN(wTxnLen),
.NEW_TXN_OFF(wTxnOff),
.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
.NEW_TXN_DONE(wTxnDone),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_EMPTY(wSgElemEmpty),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(SG_RST),
.SG_ERR(SG_ERR),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_LAST(wTxLast),
.TX_SENT(TX_SENT)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MAJ3_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__MAJ3_PP_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MAJ3_PP_BLACKBOX_V
|
(** * PE: Partial Evaluation *)
(* Chapter author/maintainer: Chung-chieh Shan *)
(** Equiv.v introduced constant folding as an example of a program
transformation and proved that it preserves the meaning of the
program. Constant folding operates on manifest constants such
as [ANum] expressions. For example, it simplifies the command
[Y ::= APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4].
However, it does not propagate known constants along data flow.
For example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is
like running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Export Imp.
Require Import FunctionalExtensionality.
(* ####################################################### *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if eq_id_dec V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V' SCase
means to reason by cases over [eq_id_dec V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) ident(c) :=
let H := fresh "Heq" i j in
destruct (eq_id_dec i j);
[ Case_aux c "equal"; subst j
| Case_aux c "not equal" ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
Case "[]". inversion H.
Case "::". simpl in H. simpl. compare V V' SCase; auto. Qed.
(** *** Aside on [In].
We will make heavy use of the [In] predicate from the standard library.
[In] is equivalent to the [appears_in] predicate introduced in Logic.v, but
defined using a [Fixpoint] rather than an [Inductive]. *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** [In] comes with various useful lemmas. *)
Check in_or_app.
(* ===> in_or_app: forall (A : Type) (l m : list A) (a : A),
In a l \/ In a m -> In a (l ++ m) *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
Check in_dec.
(* ===> in_dec : forall A : Type,
(forall x y : A, {x = y} + {x <> y}) ->
forall (a : A) (l : list A), {In a l} + {~ In a l}] *)
(** Note that we can compute with [in_dec], just as with [eq_id_dec]. *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
Case "AId".
remember (pe_lookup pe_st i) as l. destruct l.
SCase "Some". rewrite H with (n:=n) by apply Heql. reflexivity.
SCase "None". reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_override (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => update (pe_override st pe_st) V n
end.
Example test_pe_override:
pe_override (update empty_state Y 1) [(X,3);(Z,2)]
= update (update (update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_override] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_override_correct: forall st pe_st V0,
pe_override st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold update.
compare V0 V Case; auto. rewrite eq_id; auto. rewrite neq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_override] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_override_consistent: forall st pe_st,
pe_consistent (pe_override st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_override_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_override: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_override st pe_st V.
Proof. intros st pe_st H V. rewrite pe_override_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_override st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_override_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_override st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
bexp_cases (induction b) Case; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_override st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_override st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0); try destruct (ble_nat n n0);
reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st || c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_override] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if eq_id_dec V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if eq_id_dec V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
Case "[]". destruct (eq_id_dec V V0); reflexivity.
Case "::". simpl. compare V V' SCase.
SCase "equal". rewrite IHpe_st.
destruct (eq_id_dec V V0). reflexivity. rewrite neq_id; auto.
SCase "not equal". simpl. compare V0 V' SSCase.
SSCase "equal". rewrite neq_id; auto.
SSCase "not equal". rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if eq_id_dec V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0 Case.
Case "equal". rewrite eq_id; auto.
Case "not equal". rewrite pe_remove_correct. repeat rewrite neq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_override_update_remove: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override (update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_remove_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
Theorem pe_override_update_add: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_add_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_or_app.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l => x :: filter (fun y => if eq_id_dec x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
Case "->".
intros. inversion H; clear H.
left. assumption.
destruct (eq_id_dec h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite neq_id; auto.
Case "<-".
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
Case "->".
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
Case "<-".
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
SCase "Proof of assertion".
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
apply ex_falso_quodlibet. apply Heq. split. assumption. reflexivity.
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_override] only depends on the
[pe_lookup] interpretation of partial states, [pe_override] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_override] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if in_dec eq_id_dec V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V Case.
reflexivity.
destruct (in_dec eq_id_dec V ids);
reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof. intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (in_dec eq_id_dec V (pe_compare pe_st1 pe_st2)).
reflexivity.
apply pe_compare_correct. auto. Qed.
Theorem pe_compare_override: forall pe_st1 pe_st2 st,
pe_override st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_override st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if in_dec eq_id_dec V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_override st pe_st =
pe_override (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_removes_correct. unfold assigned.
destruct (in_dec eq_id_dec V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st || st1 -> (forall V, st1 V = st2 V) -> c / st || st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st || assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
Case "[]". eapply ceval_extensionality. apply E_Skip. reflexivity.
Case "V::ids".
remember (pe_lookup pe_st V) as lookup. destruct lookup.
SCase "Some". eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold update. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup. reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); auto.
SCase "None". eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup.
destruct (in_dec eq_id_dec V ids); reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); reflexivity. Qed.
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '||' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st || c1' / pe_st' ->
c2 / pe_st' || c2' / pe_st'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 ->
c2 / pe_st || c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '||' c1' '/' st'" := (pe_com c1 st c1' st').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If" ].
Hint Constructors pe_com.
Hint Constructors ceval.
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] || (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
|| (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '||' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st || st' ->
pe_override st' pe_st' = st'' ->
c' / pe_st' / st || st''
where "c' '/' pe_st' '/' st '||' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') ->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. reflexivity.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
reflexivity.
Case "PE_Seq".
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c' / pe_st' / st || st'') ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_If".
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
SCase "E_IfTrue".
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
SCase "E_IfFalse".
rewrite -> pe_compare_override.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". apply pe_com_complete. apply H.
Case "<-". apply pe_com_sound. apply H.
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking if [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '||' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st || c1' / pe_st' / SKIP ->
c2 / pe_st' || c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 / c'' ->
c2 / pe_st || c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st || (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
|| SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '||' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If"
| Case_aux c "PE_WhileEnd" | Case_aux c "PE_WhileLoop"
| Case_aux c "PE_While" | Case_aux c "PE_WhileFixedEnd"
| Case_aux c "PE_WhileFixedLoop" | Case_aux c "PE_WhileFixed" ].
Hint Constructors pe_com.
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
|| (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
|| (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
|| (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] || (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '||' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st || st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st || (update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st || st' # n1 ->
c2 / st' || st'' # n2 ->
(c1 ;; c2) / st || st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st || st' # n1 ->
(WHILE b1 DO c1 END) / st' || st'' # n2 ->
(WHILE b1 DO c1 END) / st || st'' # S (n1 + n2)
where "c1 '/' st '||' st' # n" := (ceval_count c1 st st' n).
Tactic Notation "ceval_count_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E'Skip" | Case_aux c "E'Ass" | Case_aux c "E'Seq"
| Case_aux c "E'IfTrue" | Case_aux c "E'IfFalse"
| Case_aux c "E'WhileEnd" | Case_aux c "E'WhileLoop" ].
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st || st' -> exists n, c / st || st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st || st' # n -> c / st || st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_override: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_override st pe_st1 = pe_override st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_override_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st || st' ->
c'' / pe_override st' pe_st' || st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st || st'' # n
where "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st || st'' # n' ->
c' / pe_st' / c'' / st || st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_override st pe_st || st'' # n) ->
(c' / pe_st' / c'' / st || st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. apply E'Skip. auto.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
apply E'Skip. auto.
Case "PE_Seq".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption. eassumption.
Case "PE_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_While". inversion Heval; subst.
SCase "E_WhileEnd". econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
SCase "E_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_override, <- assign_removes. eassumption.
omega.
Case "PE_WhileFixedLoop". apply ex_falso_quodlibet.
generalize dependent (S (n1 + n2)). intros n.
clear - Case H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct, H in H7. inversion H7.
SCase "E'WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
Case "PE_WhileFixed". generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct in H8. eauto.
SCase "E'WhileLoop". rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st || st'' # n) ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_If". inversion Heval; subst; inversion H7; subst; clear H7.
SCase "E_IfTrue".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
SCase "E_IfFalse".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
Case "PE_WhileEnd". apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
Case "PE_WhileLoop". eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
Case "PE_While". inversion Heval; subst.
SCase "E_IfTrue".
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
SCase "E_IfFalse". apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
SSCase "c2'' = SKIP". inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
SSCase "c2'' = WHILE b1 DO c1 END". assumption.
Case "PE_WhileFixedEnd". eapply ceval_count_sound. apply Heval'.
Case "PE_WhileFixedLoop".
apply loop_never_stops in Heval. inversion Heval.
Case "PE_WhileFixed".
clear - Case H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
ceval_cases (induction Heval) SCase;
inversion Heqc'; subst; clear Heqc'.
SCase "E_WhileEnd". apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
SCase "E_WhileLoop".
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' / SKIP ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(exists st', c' / st || st' /\ pe_override st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
Case "<-". intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ####################################################### *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Tactic Notation "block_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Goto" | Case_aux c "If" | Case_aux c "Assign" ].
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (update (update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite update_same; auto.
Qed.
Tactic Notation "peval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_None" | Case_aux c "E_Some" ].
(** ** Partial evaluation of basic blocks and flowchart programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_override st pe_st) k = (pe_override st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
block_cases (induction k as [l | b l1 l2 | i a k]) Case;
intros st pe_st H.
Case "Goto". inversion H; reflexivity.
Case "If".
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
Case "Assign".
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_override_update_add; apply IHk; apply H];
solve [rewrite pe_override_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_override st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_override st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split; [Case "->" | Case "<-"].
Case "->". intros Heval.
remember (pe_override st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
peval_cases (induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ])
SCase; intros st pe_st Heqsto; subst sto.
SCase "E_None". eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
SCase "E_Some".
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
Case "<-". intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
peval_cases (induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ])
SCase; intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
SCase "E_None". apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
SCase "E_Some".
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="doHist,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.860000,HLS_SYN_LAT=524546,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=95,HLS_SYN_LUT=210}" *)
module doHist (
ap_clk,
ap_rst_n,
inStream_TDATA,
inStream_TVALID,
inStream_TREADY,
inStream_TKEEP,
inStream_TSTRB,
inStream_TUSER,
inStream_TLAST,
inStream_TID,
inStream_TDEST,
histo_Addr_A,
histo_EN_A,
histo_WEN_A,
histo_Din_A,
histo_Dout_A,
histo_Clk_A,
histo_Rst_A,
s_axi_CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY,
s_axi_CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY,
s_axi_CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP,
s_axi_CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY,
s_axi_CTRL_BUS_BRESP,
interrupt
);
parameter ap_ST_st1_fsm_0 = 4'b1;
parameter ap_ST_st2_fsm_1 = 4'b10;
parameter ap_ST_st3_fsm_2 = 4'b100;
parameter ap_ST_st4_fsm_3 = 4'b1000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_2 = 32'b10;
parameter C_S_AXI_CTRL_BUS_DATA_WIDTH = 32;
parameter ap_const_int64_8 = 8;
parameter C_S_AXI_CTRL_BUS_ADDR_WIDTH = 4;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv9_0 = 9'b000000000;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv19_0 = 19'b0000000000000000000;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv4_F = 4'b1111;
parameter ap_const_lv9_100 = 9'b100000000;
parameter ap_const_lv9_1 = 9'b1;
parameter ap_const_lv19_40000 = 19'b1000000000000000000;
parameter ap_const_lv19_1 = 19'b1;
parameter C_S_AXI_CTRL_BUS_WSTRB_WIDTH = (C_S_AXI_CTRL_BUS_DATA_WIDTH / ap_const_int64_8);
parameter C_S_AXI_WSTRB_WIDTH = (C_S_AXI_DATA_WIDTH / ap_const_int64_8);
input ap_clk;
input ap_rst_n;
input [7:0] inStream_TDATA;
input inStream_TVALID;
output inStream_TREADY;
input [0:0] inStream_TKEEP;
input [0:0] inStream_TSTRB;
input [1:0] inStream_TUSER;
input [0:0] inStream_TLAST;
input [4:0] inStream_TID;
input [5:0] inStream_TDEST;
output [31:0] histo_Addr_A;
output histo_EN_A;
output [3:0] histo_WEN_A;
output [31:0] histo_Din_A;
input [31:0] histo_Dout_A;
output histo_Clk_A;
output histo_Rst_A;
input s_axi_CTRL_BUS_AWVALID;
output s_axi_CTRL_BUS_AWREADY;
input [C_S_AXI_CTRL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CTRL_BUS_AWADDR;
input s_axi_CTRL_BUS_WVALID;
output s_axi_CTRL_BUS_WREADY;
input [C_S_AXI_CTRL_BUS_DATA_WIDTH - 1 : 0] s_axi_CTRL_BUS_WDATA;
input [C_S_AXI_CTRL_BUS_WSTRB_WIDTH - 1 : 0] s_axi_CTRL_BUS_WSTRB;
input s_axi_CTRL_BUS_ARVALID;
output s_axi_CTRL_BUS_ARREADY;
input [C_S_AXI_CTRL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CTRL_BUS_ARADDR;
output s_axi_CTRL_BUS_RVALID;
input s_axi_CTRL_BUS_RREADY;
output [C_S_AXI_CTRL_BUS_DATA_WIDTH - 1 : 0] s_axi_CTRL_BUS_RDATA;
output [1:0] s_axi_CTRL_BUS_RRESP;
output s_axi_CTRL_BUS_BVALID;
input s_axi_CTRL_BUS_BREADY;
output [1:0] s_axi_CTRL_BUS_BRESP;
output interrupt;
reg inStream_TREADY;
reg histo_EN_A;
reg[3:0] histo_WEN_A;
reg[31:0] histo_Din_A;
reg histo_Rst_A;
reg ap_rst_n_inv;
wire ap_start;
reg ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_21;
reg ap_ready;
reg inStream_TDATA_blk_n;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_53;
wire [0:0] exitcond_fu_148_p2;
wire [8:0] idxHist_1_fu_137_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_102;
wire [18:0] idxPixel_1_fu_154_p2;
reg [18:0] idxPixel_1_reg_187;
reg ap_sig_108;
reg [7:0] histo_addr_1_reg_192;
reg [8:0] idxHist_reg_109;
wire [0:0] exitcond2_fu_131_p2;
reg [18:0] idxPixel_reg_120;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_130;
wire [63:0] tmp_fu_143_p1;
wire [63:0] tmp_3_fu_164_p1;
reg [31:0] histo_Addr_A_orig;
wire [31:0] tmp_4_fu_169_p2;
reg [3:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 4'b1;
end
doHist_CTRL_BUS_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_CTRL_BUS_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_CTRL_BUS_DATA_WIDTH ))
doHist_CTRL_BUS_s_axi_U(
.AWVALID(s_axi_CTRL_BUS_AWVALID),
.AWREADY(s_axi_CTRL_BUS_AWREADY),
.AWADDR(s_axi_CTRL_BUS_AWADDR),
.WVALID(s_axi_CTRL_BUS_WVALID),
.WREADY(s_axi_CTRL_BUS_WREADY),
.WDATA(s_axi_CTRL_BUS_WDATA),
.WSTRB(s_axi_CTRL_BUS_WSTRB),
.ARVALID(s_axi_CTRL_BUS_ARVALID),
.ARREADY(s_axi_CTRL_BUS_ARREADY),
.ARADDR(s_axi_CTRL_BUS_ARADDR),
.RVALID(s_axi_CTRL_BUS_RVALID),
.RREADY(s_axi_CTRL_BUS_RREADY),
.RDATA(s_axi_CTRL_BUS_RDATA),
.RRESP(s_axi_CTRL_BUS_RRESP),
.BVALID(s_axi_CTRL_BUS_BVALID),
.BREADY(s_axi_CTRL_BUS_BREADY),
.BRESP(s_axi_CTRL_BUS_BRESP),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.ap_start(ap_start),
.interrupt(interrupt),
.ap_ready(ap_ready),
.ap_done(ap_done),
.ap_idle(ap_idle)
);
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_131_p2))) begin
idxHist_reg_109 <= idxHist_1_fu_137_p2;
end else if (((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0))) begin
idxHist_reg_109 <= ap_const_lv9_0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & ~(1'b0 == exitcond2_fu_131_p2))) begin
idxPixel_reg_120 <= ap_const_lv19_0;
end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
idxPixel_reg_120 <= idxPixel_1_reg_187;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_148_p2 == 1'b0) & ~ap_sig_108)) begin
histo_addr_1_reg_192 <= tmp_3_fu_164_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108)) begin
idxPixel_1_reg_187 <= idxPixel_1_fu_154_p2;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108 & ~(exitcond_fu_148_p2 == 1'b0))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108 & ~(exitcond_fu_148_p2 == 1'b0))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (ap_sig_21) begin
ap_sig_cseq_ST_st1_fsm_0 = 1'b1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = 1'b0;
end
end
always @ (*) begin
if (ap_sig_102) begin
ap_sig_cseq_ST_st2_fsm_1 = 1'b1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = 1'b0;
end
end
always @ (*) begin
if (ap_sig_53) begin
ap_sig_cseq_ST_st3_fsm_2 = 1'b1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = 1'b0;
end
end
always @ (*) begin
if (ap_sig_130) begin
ap_sig_cseq_ST_st4_fsm_3 = 1'b1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
histo_Addr_A_orig = histo_addr_1_reg_192;
end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin
histo_Addr_A_orig = tmp_fu_143_p1;
end else if ((1'b1 == ap_sig_cseq_ST_st3_fsm_2)) begin
histo_Addr_A_orig = tmp_3_fu_164_p1;
end else begin
histo_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
histo_Din_A = tmp_4_fu_169_p2;
end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin
histo_Din_A = ap_const_lv32_0;
end else begin
histo_Din_A = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | ((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108) | (1'b1 == ap_sig_cseq_ST_st4_fsm_3))) begin
histo_EN_A = 1'b1;
end else begin
histo_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_131_p2)) | (1'b1 == ap_sig_cseq_ST_st4_fsm_3))) begin
histo_WEN_A = ap_const_lv4_F;
end else begin
histo_WEN_A = ap_const_lv4_0;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_148_p2 == 1'b0))) begin
inStream_TDATA_blk_n = inStream_TVALID;
end else begin
inStream_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_148_p2 == 1'b0) & ~ap_sig_108)) begin
inStream_TREADY = 1'b1;
end else begin
inStream_TREADY = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 : begin
if (~(ap_start == 1'b0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 : begin
if ((1'b0 == exitcond2_fu_131_p2)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
end
ap_ST_st3_fsm_2 : begin
if ((~ap_sig_108 & ~(exitcond_fu_148_p2 == 1'b0))) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else if (((exitcond_fu_148_p2 == 1'b0) & ~ap_sig_108)) begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
end
ap_ST_st4_fsm_3 : begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
always @ (*) begin
ap_rst_n_inv = ~ap_rst_n;
end
always @ (*) begin
ap_sig_102 = (1'b1 == ap_CS_fsm[ap_const_lv32_1]);
end
always @ (*) begin
ap_sig_108 = ((exitcond_fu_148_p2 == 1'b0) & (inStream_TVALID == 1'b0));
end
always @ (*) begin
ap_sig_130 = (1'b1 == ap_CS_fsm[ap_const_lv32_3]);
end
always @ (*) begin
ap_sig_21 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end
always @ (*) begin
ap_sig_53 = (1'b1 == ap_CS_fsm[ap_const_lv32_2]);
end
assign exitcond2_fu_131_p2 = ((idxHist_reg_109 == ap_const_lv9_100) ? 1'b1 : 1'b0);
assign exitcond_fu_148_p2 = ((idxPixel_reg_120 == ap_const_lv19_40000) ? 1'b1 : 1'b0);
assign histo_Addr_A = histo_Addr_A_orig << ap_const_lv32_2;
assign histo_Clk_A = ap_clk;
always @ (*) begin
histo_Rst_A = ~ap_rst_n;
end
assign idxHist_1_fu_137_p2 = (idxHist_reg_109 + ap_const_lv9_1);
assign idxPixel_1_fu_154_p2 = (idxPixel_reg_120 + ap_const_lv19_1);
assign tmp_3_fu_164_p1 = inStream_TDATA;
assign tmp_4_fu_169_p2 = (histo_Dout_A + ap_const_lv32_1);
assign tmp_fu_143_p1 = idxHist_reg_109;
endmodule //doHist
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_MUX_2TO1_N_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_MUX_2TO1_N_BLACKBOX_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_mux_2to1_N (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_MUX_2TO1_N_BLACKBOX_V
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 12963 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w256,
w257,
w128,
w385,
w1028,
w643,
w12320,
w12963;
assign w1 = i_data0;
assign w1028 = w257 << 2;
assign w12320 = w385 << 5;
assign w128 = w1 << 7;
assign w12963 = w643 + w12320;
assign w256 = w1 << 8;
assign w257 = w1 + w256;
assign w385 = w257 + w128;
assign w643 = w1028 - w385;
assign o_data0 = w12963;
//multiplier_block area estimate = 7304.77445403088;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
module StepDecoder(output [15:0] TimeSteps, input [3:0]StepCounter);
and and1(TimeSteps[0], ~StepCounter[3], ~StepCounter[2], ~StepCounter[1], ~StepCounter[0]);
and and2(TimeSteps[1], ~StepCounter[3], ~StepCounter[2], ~StepCounter[1], StepCounter[0]);
and and3(TimeSteps[2], ~StepCounter[3], ~StepCounter[2], StepCounter[1], ~StepCounter[0]);
and and4(TimeSteps[3], ~StepCounter[3], ~StepCounter[2], StepCounter[1], StepCounter[0]);
and and5(TimeSteps[4], ~StepCounter[3], StepCounter[2], ~StepCounter[1], ~StepCounter[0]);
and and6(TimeSteps[5], ~StepCounter[3], StepCounter[2], ~StepCounter[1], StepCounter[0]);
and and7(TimeSteps[6], ~StepCounter[3], StepCounter[2], StepCounter[1], ~StepCounter[0]);
and and8(TimeSteps[7], ~StepCounter[3], StepCounter[2], StepCounter[1], StepCounter[0]);
and and9(TimeSteps[8], StepCounter[3], ~StepCounter[2], ~StepCounter[1], ~StepCounter[0]);
and and10(TimeSteps[9], StepCounter[3], ~StepCounter[2], ~StepCounter[1], StepCounter[0]);
and and11(TimeSteps[10], StepCounter[3], ~StepCounter[2], StepCounter[1], ~StepCounter[0]);
and and12(TimeSteps[11], StepCounter[3], ~StepCounter[2], StepCounter[1], StepCounter[0]);
and and13(TimeSteps[12], StepCounter[3], StepCounter[2], ~StepCounter[1], ~StepCounter[0]);
and and14(TimeSteps[13], StepCounter[3], StepCounter[2], ~StepCounter[1], StepCounter[0]);
and and15(TimeSteps[14], StepCounter[3], StepCounter[2], StepCounter[1], ~StepCounter[0]);
and and16(TimeSteps[15], StepCounter[3], StepCounter[2], StepCounter[1], StepCounter[0]);
endmodule
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
// Allows simultaneous ENQ and DEQ (at the expense of potentially
// causing combinational loops).
module FIFOL1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
parameter width = 1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg empty_reg ;
reg [width - 1 : 0] D_OUT;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {((width + 1)/2) {2'b10}} ;
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg || DEQ;
assign EMPTY_N = empty_reg ;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFOL1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && ! DEQ)
begin
enqerror = 1 ;
$display( "Warning: FIFOL1: %m -- Enqueuing to a full fifo" ) ;
end
end
// synopsys translate_on
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
input [7:0] admin_sq_size,
input [7:0] admin_cq_size,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
input [7:0] cpld_sq_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_sq_fifo_wr_data,
input cpld_sq_fifo_wr_en,
input cpld_sq_fifo_tag_last,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack,
output [7:0] admin_cq_tail_ptr,
output [7:0] io_cq1_tail_ptr,
output [7:0] io_cq2_tail_ptr,
output [7:0] io_cq3_tail_ptr,
output [7:0] io_cq4_tail_ptr,
output [7:0] io_cq5_tail_ptr,
output [7:0] io_cq6_tail_ptr,
output [7:0] io_cq7_tail_ptr,
output [7:0] io_cq8_tail_ptr,
output tx_cq_mwr_req,
output [7:0] tx_cq_mwr_tag,
output [11:2] tx_cq_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_cq_mwr_addr,
input tx_cq_mwr_req_ack,
input tx_cq_mwr_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] tx_cq_mwr_rd_data,
input tx_cq_mwr_data_last,
input [7:0] hcmd_prp_rd_addr,
output [44:0] hcmd_prp_rd_data,
input hcmd_nlb_wr1_en,
input [6:0] hcmd_nlb_wr1_addr,
input [18:0] hcmd_nlb_wr1_data,
output hcmd_nlb_wr1_rdy_n,
input [6:0] hcmd_nlb_rd_addr,
output [18:0] hcmd_nlb_rd_data,
input hcmd_cq_wr0_en,
input [34:0] hcmd_cq_wr0_data0,
input [34:0] hcmd_cq_wr0_data1,
output hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n,
input [10:0] hcmd_table_rd_addr,
output [31:0] hcmd_table_rd_data,
input hcmd_cq_wr1_en,
input [34:0] hcmd_cq_wr1_data0,
input [34:0] hcmd_cq_wr1_data1,
output hcmd_cq_wr1_rdy_n
);
wire w_hcmd_table_wr_en;
wire [8:0] w_hcmd_table_wr_addr;
wire [127:0] w_hcmd_table_wr_data;
wire w_hcmd_cid_wr_en;
wire [6:0] w_hcmd_cid_wr_addr;
wire [19:0] w_hcmd_cid_wr_data;
wire [6:0] w_hcmd_cid_rd_addr;
wire [19:0] w_hcmd_cid_rd_data;
wire w_hcmd_prp_wr_en;
wire [7:0] w_hcmd_prp_wr_addr;
wire [44:0] w_hcmd_prp_wr_data;
wire w_hcmd_nlb_wr0_en;
wire [6:0] w_hcmd_nlb_wr0_addr;
wire [18:0] w_hcmd_nlb_wr0_data;
wire w_hcmd_nlb_wr0_rdy_n;
wire w_hcmd_slot_rdy;
wire [6:0] w_hcmd_slot_tag;
wire w_hcmd_slot_alloc_en;
wire w_hcmd_slot_free_en;
wire [6:0] w_hcmd_slot_invalid_tag;
wire [7:0] w_admin_sq_head_ptr;
wire [7:0] w_io_sq1_head_ptr;
wire [7:0] w_io_sq2_head_ptr;
wire [7:0] w_io_sq3_head_ptr;
wire [7:0] w_io_sq4_head_ptr;
wire [7:0] w_io_sq5_head_ptr;
wire [7:0] w_io_sq6_head_ptr;
wire [7:0] w_io_sq7_head_ptr;
wire [7:0] w_io_sq8_head_ptr;
pcie_hcmd_table
pcie_hcmd_table_inst0(
.wr_clk (pcie_user_clk),
.wr_en (w_hcmd_table_wr_en),
.wr_addr (w_hcmd_table_wr_addr),
.wr_data (w_hcmd_table_wr_data),
.rd_clk (cpu_bus_clk),
.rd_addr (hcmd_table_rd_addr),
.rd_data (hcmd_table_rd_data)
);
pcie_hcmd_table_cid
pcie_hcmd_table_cid_isnt0(
.clk (pcie_user_clk),
.wr_en (w_hcmd_cid_wr_en),
.wr_addr (w_hcmd_cid_wr_addr),
.wr_data (w_hcmd_cid_wr_data),
.rd_addr (w_hcmd_cid_rd_addr),
.rd_data (w_hcmd_cid_rd_data)
);
pcie_hcmd_table_prp
pcie_hcmd_table_prp_isnt0(
.clk (pcie_user_clk),
.wr_en (w_hcmd_prp_wr_en),
.wr_addr (w_hcmd_prp_wr_addr),
.wr_data (w_hcmd_prp_wr_data),
.rd_addr (hcmd_prp_rd_addr),
.rd_data (hcmd_prp_rd_data)
);
pcie_hcmd_nlb
pcie_hcmd_nlb_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (w_hcmd_nlb_wr0_en),
.wr0_addr (w_hcmd_nlb_wr0_addr),
.wr0_data (w_hcmd_nlb_wr0_data),
.wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n),
.wr1_en (hcmd_nlb_wr1_en),
.wr1_addr (hcmd_nlb_wr1_addr),
.wr1_data (hcmd_nlb_wr1_data),
.wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.rd_addr (hcmd_nlb_rd_addr),
.rd_data (hcmd_nlb_rd_data)
);
pcie_hcmd_slot_mgt
pcie_hcmd_slot_mgt_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_slot_rdy (w_hcmd_slot_rdy),
.hcmd_slot_tag (w_hcmd_slot_tag),
.hcmd_slot_alloc_en (w_hcmd_slot_alloc_en),
.hcmd_slot_free_en (w_hcmd_slot_free_en),
.hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag)
);
pcie_hcmd_sq # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_sq_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.admin_sq_bs_addr (admin_sq_bs_addr),
.admin_sq_size (admin_sq_size),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.admin_sq_head_ptr (w_admin_sq_head_ptr),
.io_sq1_head_ptr (w_io_sq1_head_ptr),
.io_sq2_head_ptr (w_io_sq2_head_ptr),
.io_sq3_head_ptr (w_io_sq3_head_ptr),
.io_sq4_head_ptr (w_io_sq4_head_ptr),
.io_sq5_head_ptr (w_io_sq5_head_ptr),
.io_sq6_head_ptr (w_io_sq6_head_ptr),
.io_sq7_head_ptr (w_io_sq7_head_ptr),
.io_sq8_head_ptr (w_io_sq8_head_ptr),
.hcmd_slot_rdy (w_hcmd_slot_rdy),
.hcmd_slot_tag (w_hcmd_slot_tag),
.hcmd_slot_alloc_en (w_hcmd_slot_alloc_en),
.cpld_sq_fifo_tag (cpld_sq_fifo_tag),
.cpld_sq_fifo_wr_data (cpld_sq_fifo_wr_data),
.cpld_sq_fifo_wr_en (cpld_sq_fifo_wr_en),
.cpld_sq_fifo_tag_last (cpld_sq_fifo_tag_last),
.tx_mrd_req (tx_mrd_req),
.tx_mrd_tag (tx_mrd_tag),
.tx_mrd_len (tx_mrd_len),
.tx_mrd_addr (tx_mrd_addr),
.tx_mrd_req_ack (tx_mrd_req_ack),
.hcmd_table_wr_en (w_hcmd_table_wr_en),
.hcmd_table_wr_addr (w_hcmd_table_wr_addr),
.hcmd_table_wr_data (w_hcmd_table_wr_data),
.hcmd_cid_wr_en (w_hcmd_cid_wr_en),
.hcmd_cid_wr_addr (w_hcmd_cid_wr_addr),
.hcmd_cid_wr_data (w_hcmd_cid_wr_data),
.hcmd_prp_wr_en (w_hcmd_prp_wr_en),
.hcmd_prp_wr_addr (w_hcmd_prp_wr_addr),
.hcmd_prp_wr_data (w_hcmd_prp_wr_data),
.hcmd_nlb_wr0_en (w_hcmd_nlb_wr0_en),
.hcmd_nlb_wr0_addr (w_hcmd_nlb_wr0_addr),
.hcmd_nlb_wr0_data (w_hcmd_nlb_wr0_data),
.hcmd_nlb_wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n)
);
pcie_hcmd_cq # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_cq_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_cid_rd_addr (w_hcmd_cid_rd_addr),
.hcmd_cid_rd_data (w_hcmd_cid_rd_data),
.admin_cq_bs_addr (admin_cq_bs_addr),
.admin_cq_size (admin_cq_size),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_sq_head_ptr (w_admin_sq_head_ptr),
.io_sq1_head_ptr (w_io_sq1_head_ptr),
.io_sq2_head_ptr (w_io_sq2_head_ptr),
.io_sq3_head_ptr (w_io_sq3_head_ptr),
.io_sq4_head_ptr (w_io_sq4_head_ptr),
.io_sq5_head_ptr (w_io_sq5_head_ptr),
.io_sq6_head_ptr (w_io_sq6_head_ptr),
.io_sq7_head_ptr (w_io_sq7_head_ptr),
.io_sq8_head_ptr (w_io_sq8_head_ptr),
.hcmd_slot_free_en (w_hcmd_slot_free_en),
.hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag),
.tx_cq_mwr_req (tx_cq_mwr_req),
.tx_cq_mwr_tag (tx_cq_mwr_tag),
.tx_cq_mwr_len (tx_cq_mwr_len),
.tx_cq_mwr_addr (tx_cq_mwr_addr),
.tx_cq_mwr_req_ack (tx_cq_mwr_req_ack),
.tx_cq_mwr_rd_en (tx_cq_mwr_rd_en),
.tx_cq_mwr_rd_data (tx_cq_mwr_rd_data),
.tx_cq_mwr_data_last (tx_cq_mwr_data_last),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.sq_valid (sq_valid),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n)
);
endmodule |
module check (input signed [22:0] a, b, c);
wire signed [22:0] int_AB;
assign int_AB = a / b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR: mismatch in div for %d and %d", a , b);
$display("VHDL = %d, Verilog = %d", c, int_AB);
$finish;
end
end
endmodule
module stimulus (output reg signed [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 1;
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
if (B === 23'b0) B = 1;
end
#1 A = 1;
B = 1;
#1 A = 23'h7fffff;
#1 B = 23'h7fffff;
#1 B = 1;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = $random % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = $random % MAX;
if (B === 23'b0) B = 1;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input signed [22:0] value);
integer i, temp;
begin
temp = $random;
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire signed [22:0] a, b;
wire signed [22:0] r;
stimulus stim (.A(a), .B(b));
sdiv23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:45:31 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_cc_0/system_auto_cc_0_stub.v
// Design : system_auto_cc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4" *)
module system_auto_cc_0(s_axi_aclk, s_axi_aresetn, s_axi_awid,
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
s_axi_awprot, s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata,
s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
s_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst,
s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid,
s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready,
m_axi_aclk, m_axi_aresetn, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awid[0:0],s_axi_awaddr[27:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[127:0],s_axi_wstrb[15:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[0:0],s_axi_araddr[27:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[0:0],s_axi_rdata[127:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_aclk,m_axi_aresetn,m_axi_awid[0:0],m_axi_awaddr[27:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[0:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[0:0],m_axi_araddr[27:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[0:0],m_axi_rdata[127:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [0:0]s_axi_awid;
input [27:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [127:0]s_axi_wdata;
input [15:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [27:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [127:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input m_axi_aclk;
input m_axi_aresetn;
output [0:0]m_axi_awid;
output [27:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [0:0]m_axi_arid;
output [27:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:18:53 06/03/2015
// Design Name:
// Module Name: ps2_keyb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ps2_keyb(
input wire clk,
inout wire clkps2,
inout wire dataps2,
//---------------------------------
input wire [7:0] rows,
output wire [4:0] cols,
output wire [4:0] joy,
output wire rst_out_n,
output wire nmi_out_n,
output wire mrst_out_n,
output wire [4:0] user_toggles,
output reg video_output_change,
//---------------------------------
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire regaddr_changed,
input wire [7:0] din,
output wire [7:0] keymap_dout,
output wire oe_n_keymap,
output wire [7:0] scancode_dout,
output wire oe_n_scancode,
output reg [7:0] kbstatus_dout,
output wire oe_n_kbstatus
);
parameter SCANCODE = 8'h04;
parameter KBSTATUS = 8'h05;
parameter KEYMAP = 8'h07;
wire master_reset, user_reset, user_nmi;
assign mrst_out_n = ~master_reset;
assign rst_out_n = ~user_reset;
assign nmi_out_n = ~user_nmi;
assign oe_n_keymap = ~(zxuno_addr == KEYMAP && zxuno_regrd == 1'b1);
assign oe_n_scancode = ~(zxuno_addr == SCANCODE && zxuno_regrd == 1'b1);
assign oe_n_kbstatus = ~(zxuno_addr == KBSTATUS && zxuno_regrd == 1'b1);
wire [7:0] kbcode;
wire ps2busy;
wire kberror;
wire nueva_tecla;
wire no_hay_teclas_pulsadas;
wire extended;
wire released;
assign scancode_dout = kbcode;
/*
| BSY | x | x | x | ERR | RLS | EXT | PEN |
*/
reg reading_kbstatus = 1'b0;
initial video_output_change = 1'b0;
always @(posedge clk) begin
kbstatus_dout[7:1] <= {ps2busy, 3'b000, kberror, released, extended};
if (nueva_tecla == 1'b1) begin
kbstatus_dout[0] <= 1'b1;
if (kbcode == 8'h7E && released == 1'b0 && extended == 1'b0) // SCRLock to change between RGB and VGA 60Hz
video_output_change <= 1'b1;
else
video_output_change <= 1'b0;
end
if (oe_n_kbstatus == 1'b0)
reading_kbstatus <= 1'b1;
else if (reading_kbstatus == 1'b1) begin
kbstatus_dout[0] <= 1'b0;
reading_kbstatus <= 1'b0;
end
if (video_output_change == 1'b1)
video_output_change <= 1'b0;
end
ps2_port lectura_de_teclado (
.clk(clk),
.enable_rcv(~ps2busy),
.kb_or_mouse(1'b0),
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.kb_interrupt(nueva_tecla),
.scancode(kbcode),
.released(released),
.extended(extended)
);
keyboard_pressed_status teclado_limpio (
.clk(clk),
.rst(1'b0),
.scan_received(nueva_tecla),
.scancode(kbcode),
.extended(extended),
.released(released),
.kbclean(no_hay_teclas_pulsadas)
);
scancode_to_speccy traductor (
.clk(clk),
.rst(1'b0),
.scan_received(nueva_tecla),
.scan(kbcode),
.extended(extended),
.released(released),
.kbclean(no_hay_teclas_pulsadas),
.sp_row(rows),
.sp_col(cols),
.joyup(joy[3]),
.joydown(joy[2]),
.joyleft(joy[1]),
.joyright(joy[0]),
.joyfire(joy[4]),
.master_reset(master_reset),
.user_reset(user_reset),
.user_nmi(user_nmi),
.user_toggles(user_toggles),
.din(din),
.dout(keymap_dout),
.cpuwrite(zxuno_addr == KEYMAP && zxuno_regwr == 1'b1),
.cpuread(zxuno_addr == KEYMAP && zxuno_regrd == 1'b1),
.rewind(regaddr_changed == 1'b1 && zxuno_addr == KEYMAP)
);
ps2_host_to_kb escritura_a_teclado (
.clk(clk),
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.data(din),
.dataload(zxuno_addr == SCANCODE && zxuno_regwr== 1'b1),
.ps2busy(ps2busy),
.ps2error(kberror)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_SYMBOL_V
`define SKY130_FD_SC_LS__DLRBP_SYMBOL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_SYMBOL_V
|
// Test implicit casts during function input assignments.
module implicit_cast();
real src_r;
bit unsigned [7:0] src_u2;
bit signed [7:0] src_s2;
logic unsigned [7:0] src_u4;
logic signed [7:0] src_s4;
logic unsigned [7:0] src_ux;
logic signed [7:0] src_sx;
real dst_r;
bit unsigned [3:0] dst_u2s;
bit signed [3:0] dst_s2s;
bit unsigned [11:0] dst_u2l;
bit signed [11:0] dst_s2l;
logic unsigned [3:0] dst_u4s;
logic signed [3:0] dst_s4s;
logic unsigned [11:0] dst_u4l;
logic signed [11:0] dst_s4l;
function real cp_r(input real val);
cp_r = val;
endfunction
function bit unsigned [3:0] cp_u2s(input bit unsigned [3:0] val);
cp_u2s = val;
endfunction
function bit signed [3:0] cp_s2s(input bit signed [3:0] val);
cp_s2s = val;
endfunction
function bit unsigned [11:0] cp_u2l(input bit unsigned [11:0] val);
cp_u2l = val;
endfunction
function bit signed [11:0] cp_s2l(input bit signed [11:0] val);
cp_s2l = val;
endfunction
function logic unsigned [3:0] cp_u4s(input logic unsigned [3:0] val);
cp_u4s = val;
endfunction
function logic signed [3:0] cp_s4s(input logic signed [3:0] val);
cp_s4s = val;
endfunction
function logic unsigned [11:0] cp_u4l(input logic unsigned [11:0] val);
cp_u4l = val;
endfunction
function logic signed [11:0] cp_s4l(input logic signed [11:0] val);
cp_s4l = val;
endfunction
bit failed;
initial begin
failed = 0;
src_r = -7;
src_u2 = 7;
src_s2 = -7;
src_u4 = 7;
src_s4 = -7;
src_ux = 8'bx0z00111;
src_sx = 8'bx0z00111;
$display("cast to real");
dst_r = cp_r(src_r); $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
dst_r = cp_r(src_u2); $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
dst_r = cp_r(src_s2); $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
dst_r = cp_r(src_u4); $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
dst_r = cp_r(src_s4); $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
dst_r = cp_r(src_ux); $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
dst_r = cp_r(src_sx); $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
$display("cast to small unsigned bit");
dst_u2s = cp_u2s(src_r); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
dst_u2s = cp_u2s(src_u2); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
dst_u2s = cp_u2s(src_s2); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
dst_u2s = cp_u2s(src_u4); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
dst_u2s = cp_u2s(src_s4); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
dst_u2s = cp_u2s(src_ux); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
dst_u2s = cp_u2s(src_sx); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
$display("cast to small signed bit");
dst_s2s = cp_s2s(src_r); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
dst_s2s = cp_s2s(src_u2); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
dst_s2s = cp_s2s(src_s2); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
dst_s2s = cp_s2s(src_u4); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
dst_s2s = cp_s2s(src_s4); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
dst_s2s = cp_s2s(src_ux); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
dst_s2s = cp_s2s(src_sx); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
$display("cast to large unsigned bit");
dst_u2l = cp_u2l(src_r); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
dst_u2l = cp_u2l(src_u2); $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
dst_u2l = cp_u2l(src_s2); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
dst_u2l = cp_u2l(src_u4); $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
dst_u2l = cp_u2l(src_s4); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
dst_u2l = cp_u2l(src_ux); $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
dst_u2l = cp_u2l(src_sx); $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
$display("cast to large signed bit");
dst_s2l = cp_s2l(src_r); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
dst_s2l = cp_s2l(src_u2); $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
dst_s2l = cp_s2l(src_s2); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
dst_s2l = cp_s2l(src_u4); $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
dst_s2l = cp_s2l(src_s4); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
dst_s2l = cp_s2l(src_ux); $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
dst_s2l = cp_s2l(src_sx); $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
$display("cast to small unsigned logic");
dst_u4s = cp_u4s(src_r); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
dst_u4s = cp_u4s(src_u2); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
dst_u4s = cp_u4s(src_s2); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
dst_u4s = cp_u4s(src_u4); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
dst_u4s = cp_u4s(src_s4); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
dst_u4s = cp_u4s(src_ux); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
dst_u4s = cp_u4s(src_sx); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
$display("cast to small signed logic");
dst_s4s = cp_s4s(src_r); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
dst_s4s = cp_s4s(src_u2); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
dst_s4s = cp_s4s(src_s2); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
dst_s4s = cp_s4s(src_u4); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
dst_s4s = cp_s4s(src_s4); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
dst_s4s = cp_s4s(src_ux); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
dst_s4s = cp_s4s(src_sx); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
$display("cast to large unsigned logic");
dst_u4l = cp_u4l(src_r); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
dst_u4l = cp_u4l(src_u2); $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
dst_u4l = cp_u4l(src_s2); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
dst_u4l = cp_u4l(src_u4); $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
dst_u4l = cp_u4l(src_s4); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
dst_u4l = cp_u4l(src_ux); $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1;
dst_u4l = cp_u4l(src_sx); $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1;
$display("cast to large signed logic");
dst_s4l = cp_s4l(src_r); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
dst_s4l = cp_s4l(src_u2); $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
dst_s4l = cp_s4l(src_s2); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
dst_s4l = cp_s4l(src_u4); $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
dst_s4l = cp_s4l(src_s4); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
dst_s4l = cp_s4l(src_ux); $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1;
dst_s4l = cp_s4l(src_sx); $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// megafunction wizard: %ALTACCUMULATE%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altaccumulate
// ============================================================
// File Name: accum32.v
// Megafunction Name(s):
// altaccumulate
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
//synthesis_resources = lut 32
module accum32_accum_nta
(
aclr,
clken,
clock,
data,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] data;
output [31:0] result;
wire [0:0] wire_acc_cella_0cout;
wire [0:0] wire_acc_cella_1cout;
wire [0:0] wire_acc_cella_2cout;
wire [0:0] wire_acc_cella_3cout;
wire [0:0] wire_acc_cella_4cout;
wire [0:0] wire_acc_cella_5cout;
wire [0:0] wire_acc_cella_6cout;
wire [0:0] wire_acc_cella_7cout;
wire [0:0] wire_acc_cella_8cout;
wire [0:0] wire_acc_cella_9cout;
wire [0:0] wire_acc_cella_10cout;
wire [0:0] wire_acc_cella_11cout;
wire [0:0] wire_acc_cella_12cout;
wire [0:0] wire_acc_cella_13cout;
wire [0:0] wire_acc_cella_14cout;
wire [0:0] wire_acc_cella_15cout;
wire [0:0] wire_acc_cella_16cout;
wire [0:0] wire_acc_cella_17cout;
wire [0:0] wire_acc_cella_18cout;
wire [0:0] wire_acc_cella_19cout;
wire [0:0] wire_acc_cella_20cout;
wire [0:0] wire_acc_cella_21cout;
wire [0:0] wire_acc_cella_22cout;
wire [0:0] wire_acc_cella_23cout;
wire [0:0] wire_acc_cella_24cout;
wire [0:0] wire_acc_cella_25cout;
wire [0:0] wire_acc_cella_26cout;
wire [0:0] wire_acc_cella_27cout;
wire [0:0] wire_acc_cella_28cout;
wire [0:0] wire_acc_cella_29cout;
wire [0:0] wire_acc_cella_30cout;
wire [31:0] wire_acc_cella_dataa;
wire [31:0] wire_acc_cella_datab;
wire [31:0] wire_acc_cella_datac;
wire [31:0] wire_acc_cella_regout;
wire sload;
stratix_lcell acc_cella_0
(
.aclr(aclr),
.cin(1'b0),
.clk(clock),
.cout(wire_acc_cella_0cout[0:0]),
.dataa(wire_acc_cella_dataa[0:0]),
.datab(wire_acc_cella_datab[0:0]),
.datac(wire_acc_cella_datac[0:0]),
.ena(clken),
.regout(wire_acc_cella_regout[0:0]),
.sload(sload));
defparam
acc_cella_0.cin_used = "true",
acc_cella_0.lut_mask = "96e8",
acc_cella_0.operation_mode = "arithmetic",
acc_cella_0.sum_lutc_input = "cin",
acc_cella_0.synch_mode = "on",
acc_cella_0.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_1
(
.aclr(aclr),
.cin(wire_acc_cella_0cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_1cout[0:0]),
.dataa(wire_acc_cella_dataa[1:1]),
.datab(wire_acc_cella_datab[1:1]),
.datac(wire_acc_cella_datac[1:1]),
.ena(clken),
.regout(wire_acc_cella_regout[1:1]),
.sload(sload));
defparam
acc_cella_1.cin_used = "true",
acc_cella_1.lut_mask = "96e8",
acc_cella_1.operation_mode = "arithmetic",
acc_cella_1.sum_lutc_input = "cin",
acc_cella_1.synch_mode = "on",
acc_cella_1.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_2
(
.aclr(aclr),
.cin(wire_acc_cella_1cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_2cout[0:0]),
.dataa(wire_acc_cella_dataa[2:2]),
.datab(wire_acc_cella_datab[2:2]),
.datac(wire_acc_cella_datac[2:2]),
.ena(clken),
.regout(wire_acc_cella_regout[2:2]),
.sload(sload));
defparam
acc_cella_2.cin_used = "true",
acc_cella_2.lut_mask = "96e8",
acc_cella_2.operation_mode = "arithmetic",
acc_cella_2.sum_lutc_input = "cin",
acc_cella_2.synch_mode = "on",
acc_cella_2.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_3
(
.aclr(aclr),
.cin(wire_acc_cella_2cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_3cout[0:0]),
.dataa(wire_acc_cella_dataa[3:3]),
.datab(wire_acc_cella_datab[3:3]),
.datac(wire_acc_cella_datac[3:3]),
.ena(clken),
.regout(wire_acc_cella_regout[3:3]),
.sload(sload));
defparam
acc_cella_3.cin_used = "true",
acc_cella_3.lut_mask = "96e8",
acc_cella_3.operation_mode = "arithmetic",
acc_cella_3.sum_lutc_input = "cin",
acc_cella_3.synch_mode = "on",
acc_cella_3.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_4
(
.aclr(aclr),
.cin(wire_acc_cella_3cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_4cout[0:0]),
.dataa(wire_acc_cella_dataa[4:4]),
.datab(wire_acc_cella_datab[4:4]),
.datac(wire_acc_cella_datac[4:4]),
.ena(clken),
.regout(wire_acc_cella_regout[4:4]),
.sload(sload));
defparam
acc_cella_4.cin_used = "true",
acc_cella_4.lut_mask = "96e8",
acc_cella_4.operation_mode = "arithmetic",
acc_cella_4.sum_lutc_input = "cin",
acc_cella_4.synch_mode = "on",
acc_cella_4.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_5
(
.aclr(aclr),
.cin(wire_acc_cella_4cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_5cout[0:0]),
.dataa(wire_acc_cella_dataa[5:5]),
.datab(wire_acc_cella_datab[5:5]),
.datac(wire_acc_cella_datac[5:5]),
.ena(clken),
.regout(wire_acc_cella_regout[5:5]),
.sload(sload));
defparam
acc_cella_5.cin_used = "true",
acc_cella_5.lut_mask = "96e8",
acc_cella_5.operation_mode = "arithmetic",
acc_cella_5.sum_lutc_input = "cin",
acc_cella_5.synch_mode = "on",
acc_cella_5.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_6
(
.aclr(aclr),
.cin(wire_acc_cella_5cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_6cout[0:0]),
.dataa(wire_acc_cella_dataa[6:6]),
.datab(wire_acc_cella_datab[6:6]),
.datac(wire_acc_cella_datac[6:6]),
.ena(clken),
.regout(wire_acc_cella_regout[6:6]),
.sload(sload));
defparam
acc_cella_6.cin_used = "true",
acc_cella_6.lut_mask = "96e8",
acc_cella_6.operation_mode = "arithmetic",
acc_cella_6.sum_lutc_input = "cin",
acc_cella_6.synch_mode = "on",
acc_cella_6.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_7
(
.aclr(aclr),
.cin(wire_acc_cella_6cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_7cout[0:0]),
.dataa(wire_acc_cella_dataa[7:7]),
.datab(wire_acc_cella_datab[7:7]),
.datac(wire_acc_cella_datac[7:7]),
.ena(clken),
.regout(wire_acc_cella_regout[7:7]),
.sload(sload));
defparam
acc_cella_7.cin_used = "true",
acc_cella_7.lut_mask = "96e8",
acc_cella_7.operation_mode = "arithmetic",
acc_cella_7.sum_lutc_input = "cin",
acc_cella_7.synch_mode = "on",
acc_cella_7.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_8
(
.aclr(aclr),
.cin(wire_acc_cella_7cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_8cout[0:0]),
.dataa(wire_acc_cella_dataa[8:8]),
.datab(wire_acc_cella_datab[8:8]),
.datac(wire_acc_cella_datac[8:8]),
.ena(clken),
.regout(wire_acc_cella_regout[8:8]),
.sload(sload));
defparam
acc_cella_8.cin_used = "true",
acc_cella_8.lut_mask = "96e8",
acc_cella_8.operation_mode = "arithmetic",
acc_cella_8.sum_lutc_input = "cin",
acc_cella_8.synch_mode = "on",
acc_cella_8.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_9
(
.aclr(aclr),
.cin(wire_acc_cella_8cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_9cout[0:0]),
.dataa(wire_acc_cella_dataa[9:9]),
.datab(wire_acc_cella_datab[9:9]),
.datac(wire_acc_cella_datac[9:9]),
.ena(clken),
.regout(wire_acc_cella_regout[9:9]),
.sload(sload));
defparam
acc_cella_9.cin_used = "true",
acc_cella_9.lut_mask = "96e8",
acc_cella_9.operation_mode = "arithmetic",
acc_cella_9.sum_lutc_input = "cin",
acc_cella_9.synch_mode = "on",
acc_cella_9.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_10
(
.aclr(aclr),
.cin(wire_acc_cella_9cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_10cout[0:0]),
.dataa(wire_acc_cella_dataa[10:10]),
.datab(wire_acc_cella_datab[10:10]),
.datac(wire_acc_cella_datac[10:10]),
.ena(clken),
.regout(wire_acc_cella_regout[10:10]),
.sload(sload));
defparam
acc_cella_10.cin_used = "true",
acc_cella_10.lut_mask = "96e8",
acc_cella_10.operation_mode = "arithmetic",
acc_cella_10.sum_lutc_input = "cin",
acc_cella_10.synch_mode = "on",
acc_cella_10.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_11
(
.aclr(aclr),
.cin(wire_acc_cella_10cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_11cout[0:0]),
.dataa(wire_acc_cella_dataa[11:11]),
.datab(wire_acc_cella_datab[11:11]),
.datac(wire_acc_cella_datac[11:11]),
.ena(clken),
.regout(wire_acc_cella_regout[11:11]),
.sload(sload));
defparam
acc_cella_11.cin_used = "true",
acc_cella_11.lut_mask = "96e8",
acc_cella_11.operation_mode = "arithmetic",
acc_cella_11.sum_lutc_input = "cin",
acc_cella_11.synch_mode = "on",
acc_cella_11.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_12
(
.aclr(aclr),
.cin(wire_acc_cella_11cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_12cout[0:0]),
.dataa(wire_acc_cella_dataa[12:12]),
.datab(wire_acc_cella_datab[12:12]),
.datac(wire_acc_cella_datac[12:12]),
.ena(clken),
.regout(wire_acc_cella_regout[12:12]),
.sload(sload));
defparam
acc_cella_12.cin_used = "true",
acc_cella_12.lut_mask = "96e8",
acc_cella_12.operation_mode = "arithmetic",
acc_cella_12.sum_lutc_input = "cin",
acc_cella_12.synch_mode = "on",
acc_cella_12.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_13
(
.aclr(aclr),
.cin(wire_acc_cella_12cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_13cout[0:0]),
.dataa(wire_acc_cella_dataa[13:13]),
.datab(wire_acc_cella_datab[13:13]),
.datac(wire_acc_cella_datac[13:13]),
.ena(clken),
.regout(wire_acc_cella_regout[13:13]),
.sload(sload));
defparam
acc_cella_13.cin_used = "true",
acc_cella_13.lut_mask = "96e8",
acc_cella_13.operation_mode = "arithmetic",
acc_cella_13.sum_lutc_input = "cin",
acc_cella_13.synch_mode = "on",
acc_cella_13.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_14
(
.aclr(aclr),
.cin(wire_acc_cella_13cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_14cout[0:0]),
.dataa(wire_acc_cella_dataa[14:14]),
.datab(wire_acc_cella_datab[14:14]),
.datac(wire_acc_cella_datac[14:14]),
.ena(clken),
.regout(wire_acc_cella_regout[14:14]),
.sload(sload));
defparam
acc_cella_14.cin_used = "true",
acc_cella_14.lut_mask = "96e8",
acc_cella_14.operation_mode = "arithmetic",
acc_cella_14.sum_lutc_input = "cin",
acc_cella_14.synch_mode = "on",
acc_cella_14.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_15
(
.aclr(aclr),
.cin(wire_acc_cella_14cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_15cout[0:0]),
.dataa(wire_acc_cella_dataa[15:15]),
.datab(wire_acc_cella_datab[15:15]),
.datac(wire_acc_cella_datac[15:15]),
.ena(clken),
.regout(wire_acc_cella_regout[15:15]),
.sload(sload));
defparam
acc_cella_15.cin_used = "true",
acc_cella_15.lut_mask = "96e8",
acc_cella_15.operation_mode = "arithmetic",
acc_cella_15.sum_lutc_input = "cin",
acc_cella_15.synch_mode = "on",
acc_cella_15.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_16
(
.aclr(aclr),
.cin(wire_acc_cella_15cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_16cout[0:0]),
.dataa(wire_acc_cella_dataa[16:16]),
.datab(wire_acc_cella_datab[16:16]),
.datac(wire_acc_cella_datac[16:16]),
.ena(clken),
.regout(wire_acc_cella_regout[16:16]),
.sload(sload));
defparam
acc_cella_16.cin_used = "true",
acc_cella_16.lut_mask = "96e8",
acc_cella_16.operation_mode = "arithmetic",
acc_cella_16.sum_lutc_input = "cin",
acc_cella_16.synch_mode = "on",
acc_cella_16.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_17
(
.aclr(aclr),
.cin(wire_acc_cella_16cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_17cout[0:0]),
.dataa(wire_acc_cella_dataa[17:17]),
.datab(wire_acc_cella_datab[17:17]),
.datac(wire_acc_cella_datac[17:17]),
.ena(clken),
.regout(wire_acc_cella_regout[17:17]),
.sload(sload));
defparam
acc_cella_17.cin_used = "true",
acc_cella_17.lut_mask = "96e8",
acc_cella_17.operation_mode = "arithmetic",
acc_cella_17.sum_lutc_input = "cin",
acc_cella_17.synch_mode = "on",
acc_cella_17.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_18
(
.aclr(aclr),
.cin(wire_acc_cella_17cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_18cout[0:0]),
.dataa(wire_acc_cella_dataa[18:18]),
.datab(wire_acc_cella_datab[18:18]),
.datac(wire_acc_cella_datac[18:18]),
.ena(clken),
.regout(wire_acc_cella_regout[18:18]),
.sload(sload));
defparam
acc_cella_18.cin_used = "true",
acc_cella_18.lut_mask = "96e8",
acc_cella_18.operation_mode = "arithmetic",
acc_cella_18.sum_lutc_input = "cin",
acc_cella_18.synch_mode = "on",
acc_cella_18.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_19
(
.aclr(aclr),
.cin(wire_acc_cella_18cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_19cout[0:0]),
.dataa(wire_acc_cella_dataa[19:19]),
.datab(wire_acc_cella_datab[19:19]),
.datac(wire_acc_cella_datac[19:19]),
.ena(clken),
.regout(wire_acc_cella_regout[19:19]),
.sload(sload));
defparam
acc_cella_19.cin_used = "true",
acc_cella_19.lut_mask = "96e8",
acc_cella_19.operation_mode = "arithmetic",
acc_cella_19.sum_lutc_input = "cin",
acc_cella_19.synch_mode = "on",
acc_cella_19.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_20
(
.aclr(aclr),
.cin(wire_acc_cella_19cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_20cout[0:0]),
.dataa(wire_acc_cella_dataa[20:20]),
.datab(wire_acc_cella_datab[20:20]),
.datac(wire_acc_cella_datac[20:20]),
.ena(clken),
.regout(wire_acc_cella_regout[20:20]),
.sload(sload));
defparam
acc_cella_20.cin_used = "true",
acc_cella_20.lut_mask = "96e8",
acc_cella_20.operation_mode = "arithmetic",
acc_cella_20.sum_lutc_input = "cin",
acc_cella_20.synch_mode = "on",
acc_cella_20.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_21
(
.aclr(aclr),
.cin(wire_acc_cella_20cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_21cout[0:0]),
.dataa(wire_acc_cella_dataa[21:21]),
.datab(wire_acc_cella_datab[21:21]),
.datac(wire_acc_cella_datac[21:21]),
.ena(clken),
.regout(wire_acc_cella_regout[21:21]),
.sload(sload));
defparam
acc_cella_21.cin_used = "true",
acc_cella_21.lut_mask = "96e8",
acc_cella_21.operation_mode = "arithmetic",
acc_cella_21.sum_lutc_input = "cin",
acc_cella_21.synch_mode = "on",
acc_cella_21.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_22
(
.aclr(aclr),
.cin(wire_acc_cella_21cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_22cout[0:0]),
.dataa(wire_acc_cella_dataa[22:22]),
.datab(wire_acc_cella_datab[22:22]),
.datac(wire_acc_cella_datac[22:22]),
.ena(clken),
.regout(wire_acc_cella_regout[22:22]),
.sload(sload));
defparam
acc_cella_22.cin_used = "true",
acc_cella_22.lut_mask = "96e8",
acc_cella_22.operation_mode = "arithmetic",
acc_cella_22.sum_lutc_input = "cin",
acc_cella_22.synch_mode = "on",
acc_cella_22.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_23
(
.aclr(aclr),
.cin(wire_acc_cella_22cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_23cout[0:0]),
.dataa(wire_acc_cella_dataa[23:23]),
.datab(wire_acc_cella_datab[23:23]),
.datac(wire_acc_cella_datac[23:23]),
.ena(clken),
.regout(wire_acc_cella_regout[23:23]),
.sload(sload));
defparam
acc_cella_23.cin_used = "true",
acc_cella_23.lut_mask = "96e8",
acc_cella_23.operation_mode = "arithmetic",
acc_cella_23.sum_lutc_input = "cin",
acc_cella_23.synch_mode = "on",
acc_cella_23.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_24
(
.aclr(aclr),
.cin(wire_acc_cella_23cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_24cout[0:0]),
.dataa(wire_acc_cella_dataa[24:24]),
.datab(wire_acc_cella_datab[24:24]),
.datac(wire_acc_cella_datac[24:24]),
.ena(clken),
.regout(wire_acc_cella_regout[24:24]),
.sload(sload));
defparam
acc_cella_24.cin_used = "true",
acc_cella_24.lut_mask = "96e8",
acc_cella_24.operation_mode = "arithmetic",
acc_cella_24.sum_lutc_input = "cin",
acc_cella_24.synch_mode = "on",
acc_cella_24.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_25
(
.aclr(aclr),
.cin(wire_acc_cella_24cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_25cout[0:0]),
.dataa(wire_acc_cella_dataa[25:25]),
.datab(wire_acc_cella_datab[25:25]),
.datac(wire_acc_cella_datac[25:25]),
.ena(clken),
.regout(wire_acc_cella_regout[25:25]),
.sload(sload));
defparam
acc_cella_25.cin_used = "true",
acc_cella_25.lut_mask = "96e8",
acc_cella_25.operation_mode = "arithmetic",
acc_cella_25.sum_lutc_input = "cin",
acc_cella_25.synch_mode = "on",
acc_cella_25.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_26
(
.aclr(aclr),
.cin(wire_acc_cella_25cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_26cout[0:0]),
.dataa(wire_acc_cella_dataa[26:26]),
.datab(wire_acc_cella_datab[26:26]),
.datac(wire_acc_cella_datac[26:26]),
.ena(clken),
.regout(wire_acc_cella_regout[26:26]),
.sload(sload));
defparam
acc_cella_26.cin_used = "true",
acc_cella_26.lut_mask = "96e8",
acc_cella_26.operation_mode = "arithmetic",
acc_cella_26.sum_lutc_input = "cin",
acc_cella_26.synch_mode = "on",
acc_cella_26.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_27
(
.aclr(aclr),
.cin(wire_acc_cella_26cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_27cout[0:0]),
.dataa(wire_acc_cella_dataa[27:27]),
.datab(wire_acc_cella_datab[27:27]),
.datac(wire_acc_cella_datac[27:27]),
.ena(clken),
.regout(wire_acc_cella_regout[27:27]),
.sload(sload));
defparam
acc_cella_27.cin_used = "true",
acc_cella_27.lut_mask = "96e8",
acc_cella_27.operation_mode = "arithmetic",
acc_cella_27.sum_lutc_input = "cin",
acc_cella_27.synch_mode = "on",
acc_cella_27.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_28
(
.aclr(aclr),
.cin(wire_acc_cella_27cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_28cout[0:0]),
.dataa(wire_acc_cella_dataa[28:28]),
.datab(wire_acc_cella_datab[28:28]),
.datac(wire_acc_cella_datac[28:28]),
.ena(clken),
.regout(wire_acc_cella_regout[28:28]),
.sload(sload));
defparam
acc_cella_28.cin_used = "true",
acc_cella_28.lut_mask = "96e8",
acc_cella_28.operation_mode = "arithmetic",
acc_cella_28.sum_lutc_input = "cin",
acc_cella_28.synch_mode = "on",
acc_cella_28.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_29
(
.aclr(aclr),
.cin(wire_acc_cella_28cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_29cout[0:0]),
.dataa(wire_acc_cella_dataa[29:29]),
.datab(wire_acc_cella_datab[29:29]),
.datac(wire_acc_cella_datac[29:29]),
.ena(clken),
.regout(wire_acc_cella_regout[29:29]),
.sload(sload));
defparam
acc_cella_29.cin_used = "true",
acc_cella_29.lut_mask = "96e8",
acc_cella_29.operation_mode = "arithmetic",
acc_cella_29.sum_lutc_input = "cin",
acc_cella_29.synch_mode = "on",
acc_cella_29.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_30
(
.aclr(aclr),
.cin(wire_acc_cella_29cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_30cout[0:0]),
.dataa(wire_acc_cella_dataa[30:30]),
.datab(wire_acc_cella_datab[30:30]),
.datac(wire_acc_cella_datac[30:30]),
.ena(clken),
.regout(wire_acc_cella_regout[30:30]),
.sload(sload));
defparam
acc_cella_30.cin_used = "true",
acc_cella_30.lut_mask = "96e8",
acc_cella_30.operation_mode = "arithmetic",
acc_cella_30.sum_lutc_input = "cin",
acc_cella_30.synch_mode = "on",
acc_cella_30.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_31
(
.aclr(aclr),
.cin(wire_acc_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_acc_cella_dataa[31:31]),
.datab(wire_acc_cella_datab[31:31]),
.datac(wire_acc_cella_datac[31:31]),
.ena(clken),
.regout(wire_acc_cella_regout[31:31]),
.sload(sload));
defparam
acc_cella_31.cin_used = "true",
acc_cella_31.lut_mask = "9696",
acc_cella_31.operation_mode = "normal",
acc_cella_31.sum_lutc_input = "cin",
acc_cella_31.synch_mode = "on",
acc_cella_31.lpm_type = "stratix_lcell";
assign
wire_acc_cella_dataa = data,
wire_acc_cella_datab = wire_acc_cella_regout,
wire_acc_cella_datac = data;
assign
result = wire_acc_cella_regout,
sload = 1'b0;
endmodule //accum32_accum_nta
//VALID FILE
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
accum32_accum_nta accum32_accum_nta_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
// Retrieval info: PRIVATE: CIN NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: COUT NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
// Retrieval info: PRIVATE: LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
module raycast_stack
(
clk,
push, pop,
data_i, data_o
/* done*/
);
// = Parameters =
parameter dw = 32;
parameter depth = 8;
parameter depth_log2 = 3;
// --
// = Ports =
input clk;
input push;
input pop;
input [dw-1:0] data_i;
output [dw-1:0] data_o;
/* output done;*/
// --
// = Memories =
reg [dw-1:0] stack_data[0:depth-1];
reg [depth_log2-1:0] stack_ptr = 0;
// --
// -- Shift-register based stack --
// assign data_o = stack_data[0];
// integer i;
// always @(posedge clk)
// begin
// if (push) begin
// for (i=1;i<depth;i=i+1) begin
// stack_data[i] <= stack_data[i-1];
// end
// stack_data[0] <= data_i;
// end
// else if (pop) begin
// for (i=1;i<depth;i=i+1) begin
// stack_data[i-1] <= stack_data[i];
// end
// end
// end
// -- Memory based stack --
// We trust this operation to wrap around depth
wire [depth_log2-1:0] stack_ptr_inc = stack_ptr + 1;
wire [depth_log2-1:0] stack_ptr_dec = stack_ptr - 1;
assign data_o = stack_data[stack_ptr];
always @(posedge clk)
begin
if (push) begin
stack_data[stack_ptr_inc] <= data_i;
stack_ptr <= stack_ptr_inc;
end
else if (pop) begin
stack_ptr <= stack_ptr_dec;
end
end
endmodule |
// megafunction wizard: %ALTFP_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_add_sub
// ============================================================
// File Name: acl_fp_sub_double.v
// Megafunction Name(s):
// altfp_add_sub
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix IV" DIRECTION="SUB" OPTIMIZE="SPEED" PIPELINE=7 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_add_sub 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=55 WIDTHDIST=6 aclr clk_en clock data distance result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources = reg 56
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altbarrel_shift_32e
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [54:0] data;
input [5:0] distance;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [54:0] sbit_piper1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [384:0] sbit_w;
wire [5:0] sel_w;
wire [329:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[5]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 55'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[329:275];
assign
dir_w = {dir_pipe[0], dir_w[4:0], direction_w},
direction_w = 1'b0,
pad_w = {32{1'b0}},
result = sbit_w[384:330],
sbit_w = {sbit_piper1d, smux_w[274:0], data},
sel_w = {distance[5:0]},
smux_w = {((({55{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[297:275], pad_w[31:0]}) | ({55{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[329:307]})) | ({55{(~ sel_w[5])}} & sbit_w[329:275])), ((({55{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[258:220], pad_w[15:0]}) | ({55{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[274:236]})) | ({55{(~ sel_w[4])}} & sbit_w[274:220])), ((({55{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[211:165], pad_w[7:0]}) | ({55{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[219:173]})) | ({55{(~ sel_w[3])}} & sbit_w[219:165])), ((({55{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[160:110], pad_w[3:0]}) | ({55{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[164:114]})) | ({55{(~ sel_w[2])}} & sbit_w[164:110])), ((({55{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[107:55], pad_w[1:0]}) | ({55{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[109:57]})) | ({55{(~ sel_w[1])}} & sbit_w[109:55])), ((({55{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[53:0], pad_w[0]}) | ({55{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[54:1]})) | ({55{(~ sel_w[0])}} & sbit_w[54:0]))};
endmodule //acl_fp_sub_double_altbarrel_shift_32e
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" SHIFTDIR="RIGHT" WIDTH=55 WIDTHDIST=6 data distance result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altbarrel_shift_oib
(
data,
distance,
result) ;
input [54:0] data;
input [5:0] distance;
output [54:0] result;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [384:0] sbit_w;
wire [5:0] sel_w;
wire [329:0] smux_w;
assign
dir_w = {dir_w[5:0], direction_w},
direction_w = 1'b1,
pad_w = {32{1'b0}},
result = sbit_w[384:330],
sbit_w = {smux_w[329:0], data},
sel_w = {distance[5:0]},
smux_w = {((({55{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[297:275], pad_w[31:0]}) | ({55{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[329:307]})) | ({55{(~ sel_w[5])}} & sbit_w[329:275])), ((({55{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[258:220], pad_w[15:0]}) | ({55{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[274:236]})) | ({55{(~ sel_w[4])}} & sbit_w[274:220])), ((({55{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[211:165], pad_w[7:0]}) | ({55{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[219:173]})) | ({55{(~ sel_w[3])}} & sbit_w[219:165])), ((({55{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[160:110], pad_w[3:0]}) | ({55{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[164:114]})) | ({55{(~ sel_w[2])}} & sbit_w[164:110])), ((({55{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[107:55], pad_w[1:0]}) | ({55{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[109:57]})) | ({55{(~ sel_w[1])}} & sbit_w[109:55])), ((({55{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[53:0], pad_w[0]}) | ({55{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[54:1]})) | ({55{(~ sel_w[0])}} & sbit_w[54:0]))};
endmodule //acl_fp_sub_double_altbarrel_shift_oib
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //acl_fp_sub_double_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
wire [0:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
acl_fp_sub_double_altpriority_encoder_3e8 altpriority_encoder15
(
.data(data[1:0]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
acl_fp_sub_double_altpriority_encoder_3e8 altpriority_encoder16
(
.data(data[3:2]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
assign
q = {(~ wire_altpriority_encoder16_zero), ((wire_altpriority_encoder16_zero & wire_altpriority_encoder15_q) | ((~ wire_altpriority_encoder16_zero) & wire_altpriority_encoder16_q))},
zero = (wire_altpriority_encoder15_zero & wire_altpriority_encoder16_zero);
endmodule //acl_fp_sub_double_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [1:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
acl_fp_sub_double_altpriority_encoder_6e8 altpriority_encoder13
(
.data(data[3:0]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
acl_fp_sub_double_altpriority_encoder_6e8 altpriority_encoder14
(
.data(data[7:4]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
assign
q = {(~ wire_altpriority_encoder14_zero), (({2{wire_altpriority_encoder14_zero}} & wire_altpriority_encoder13_q) | ({2{(~ wire_altpriority_encoder14_zero)}} & wire_altpriority_encoder14_q))},
zero = (wire_altpriority_encoder13_zero & wire_altpriority_encoder14_zero);
endmodule //acl_fp_sub_double_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [2:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
acl_fp_sub_double_altpriority_encoder_be8 altpriority_encoder11
(
.data(data[7:0]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
acl_fp_sub_double_altpriority_encoder_be8 altpriority_encoder12
(
.data(data[15:8]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
assign
q = {(~ wire_altpriority_encoder12_zero), (({3{wire_altpriority_encoder12_zero}} & wire_altpriority_encoder11_q) | ({3{(~ wire_altpriority_encoder12_zero)}} & wire_altpriority_encoder12_q))},
zero = (wire_altpriority_encoder11_zero & wire_altpriority_encoder12_zero);
endmodule //acl_fp_sub_double_altpriority_encoder_rf8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //acl_fp_sub_double_altpriority_encoder_3v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder21_q;
wire [0:0] wire_altpriority_encoder22_q;
wire wire_altpriority_encoder22_zero;
acl_fp_sub_double_altpriority_encoder_3v7 altpriority_encoder21
(
.data(data[1:0]),
.q(wire_altpriority_encoder21_q));
acl_fp_sub_double_altpriority_encoder_3e8 altpriority_encoder22
(
.data(data[3:2]),
.q(wire_altpriority_encoder22_q),
.zero(wire_altpriority_encoder22_zero));
assign
q = {(~ wire_altpriority_encoder22_zero), ((wire_altpriority_encoder22_zero & wire_altpriority_encoder21_q) | ((~ wire_altpriority_encoder22_zero) & wire_altpriority_encoder22_q))};
endmodule //acl_fp_sub_double_altpriority_encoder_6v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder19_q;
wire [1:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
acl_fp_sub_double_altpriority_encoder_6v7 altpriority_encoder19
(
.data(data[3:0]),
.q(wire_altpriority_encoder19_q));
acl_fp_sub_double_altpriority_encoder_6e8 altpriority_encoder20
(
.data(data[7:4]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
assign
q = {(~ wire_altpriority_encoder20_zero), (({2{wire_altpriority_encoder20_zero}} & wire_altpriority_encoder19_q) | ({2{(~ wire_altpriority_encoder20_zero)}} & wire_altpriority_encoder20_q))};
endmodule //acl_fp_sub_double_altpriority_encoder_bv7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder17_q;
wire [2:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
acl_fp_sub_double_altpriority_encoder_bv7 altpriority_encoder17
(
.data(data[7:0]),
.q(wire_altpriority_encoder17_q));
acl_fp_sub_double_altpriority_encoder_be8 altpriority_encoder18
(
.data(data[15:8]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
assign
q = {(~ wire_altpriority_encoder18_zero), (({3{wire_altpriority_encoder18_zero}} & wire_altpriority_encoder17_q) | ({3{(~ wire_altpriority_encoder18_zero)}} & wire_altpriority_encoder18_q))};
endmodule //acl_fp_sub_double_altpriority_encoder_r08
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_q08
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [3:0] wire_altpriority_encoder9_q;
acl_fp_sub_double_altpriority_encoder_rf8 altpriority_encoder10
(
.data(data[31:16]),
.q(wire_altpriority_encoder10_q),
.zero(wire_altpriority_encoder10_zero));
acl_fp_sub_double_altpriority_encoder_r08 altpriority_encoder9
(
.data(data[15:0]),
.q(wire_altpriority_encoder9_q));
assign
q = {(~ wire_altpriority_encoder10_zero), (({4{wire_altpriority_encoder10_zero}} & wire_altpriority_encoder9_q) | ({4{(~ wire_altpriority_encoder10_zero)}} & wire_altpriority_encoder10_q))};
endmodule //acl_fp_sub_double_altpriority_encoder_q08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_qf8
(
data,
q,
zero) ;
input [31:0] data;
output [4:0] q;
output zero;
wire [3:0] wire_altpriority_encoder23_q;
wire wire_altpriority_encoder23_zero;
wire [3:0] wire_altpriority_encoder24_q;
wire wire_altpriority_encoder24_zero;
acl_fp_sub_double_altpriority_encoder_rf8 altpriority_encoder23
(
.data(data[15:0]),
.q(wire_altpriority_encoder23_q),
.zero(wire_altpriority_encoder23_zero));
acl_fp_sub_double_altpriority_encoder_rf8 altpriority_encoder24
(
.data(data[31:16]),
.q(wire_altpriority_encoder24_q),
.zero(wire_altpriority_encoder24_zero));
assign
q = {(~ wire_altpriority_encoder24_zero), (({4{wire_altpriority_encoder24_zero}} & wire_altpriority_encoder23_q) | ({4{(~ wire_altpriority_encoder24_zero)}} & wire_altpriority_encoder24_q))},
zero = (wire_altpriority_encoder23_zero & wire_altpriority_encoder24_zero);
endmodule //acl_fp_sub_double_altpriority_encoder_qf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_0c6
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder7_q;
wire [4:0] wire_altpriority_encoder8_q;
wire wire_altpriority_encoder8_zero;
acl_fp_sub_double_altpriority_encoder_q08 altpriority_encoder7
(
.data(data[31:0]),
.q(wire_altpriority_encoder7_q));
acl_fp_sub_double_altpriority_encoder_qf8 altpriority_encoder8
(
.data(data[63:32]),
.q(wire_altpriority_encoder8_q),
.zero(wire_altpriority_encoder8_zero));
assign
q = {(~ wire_altpriority_encoder8_zero), (({5{wire_altpriority_encoder8_zero}} & wire_altpriority_encoder7_q) | ({5{(~ wire_altpriority_encoder8_zero)}} & wire_altpriority_encoder8_q))};
endmodule //acl_fp_sub_double_altpriority_encoder_0c6
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=32 WIDTHAD=5 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_nh8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {(~ data[0])},
zero = (~ (data[0] | data[1]));
endmodule //acl_fp_sub_double_altpriority_encoder_nh8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_qh8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder33_q;
wire wire_altpriority_encoder33_zero;
wire [0:0] wire_altpriority_encoder34_q;
wire wire_altpriority_encoder34_zero;
acl_fp_sub_double_altpriority_encoder_nh8 altpriority_encoder33
(
.data(data[1:0]),
.q(wire_altpriority_encoder33_q),
.zero(wire_altpriority_encoder33_zero));
acl_fp_sub_double_altpriority_encoder_nh8 altpriority_encoder34
(
.data(data[3:2]),
.q(wire_altpriority_encoder34_q),
.zero(wire_altpriority_encoder34_zero));
assign
q = {wire_altpriority_encoder33_zero, ((wire_altpriority_encoder33_zero & wire_altpriority_encoder34_q) | ((~ wire_altpriority_encoder33_zero) & wire_altpriority_encoder33_q))},
zero = (wire_altpriority_encoder33_zero & wire_altpriority_encoder34_zero);
endmodule //acl_fp_sub_double_altpriority_encoder_qh8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_vh8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder31_q;
wire wire_altpriority_encoder31_zero;
wire [1:0] wire_altpriority_encoder32_q;
wire wire_altpriority_encoder32_zero;
acl_fp_sub_double_altpriority_encoder_qh8 altpriority_encoder31
(
.data(data[3:0]),
.q(wire_altpriority_encoder31_q),
.zero(wire_altpriority_encoder31_zero));
acl_fp_sub_double_altpriority_encoder_qh8 altpriority_encoder32
(
.data(data[7:4]),
.q(wire_altpriority_encoder32_q),
.zero(wire_altpriority_encoder32_zero));
assign
q = {wire_altpriority_encoder31_zero, (({2{wire_altpriority_encoder31_zero}} & wire_altpriority_encoder32_q) | ({2{(~ wire_altpriority_encoder31_zero)}} & wire_altpriority_encoder31_q))},
zero = (wire_altpriority_encoder31_zero & wire_altpriority_encoder32_zero);
endmodule //acl_fp_sub_double_altpriority_encoder_vh8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_fj8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder29_q;
wire wire_altpriority_encoder29_zero;
wire [2:0] wire_altpriority_encoder30_q;
wire wire_altpriority_encoder30_zero;
acl_fp_sub_double_altpriority_encoder_vh8 altpriority_encoder29
(
.data(data[7:0]),
.q(wire_altpriority_encoder29_q),
.zero(wire_altpriority_encoder29_zero));
acl_fp_sub_double_altpriority_encoder_vh8 altpriority_encoder30
(
.data(data[15:8]),
.q(wire_altpriority_encoder30_q),
.zero(wire_altpriority_encoder30_zero));
assign
q = {wire_altpriority_encoder29_zero, (({3{wire_altpriority_encoder29_zero}} & wire_altpriority_encoder30_q) | ({3{(~ wire_altpriority_encoder29_zero)}} & wire_altpriority_encoder29_q))},
zero = (wire_altpriority_encoder29_zero & wire_altpriority_encoder30_zero);
endmodule //acl_fp_sub_double_altpriority_encoder_fj8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_ej8
(
data,
q,
zero) ;
input [31:0] data;
output [4:0] q;
output zero;
wire [3:0] wire_altpriority_encoder27_q;
wire wire_altpriority_encoder27_zero;
wire [3:0] wire_altpriority_encoder28_q;
wire wire_altpriority_encoder28_zero;
acl_fp_sub_double_altpriority_encoder_fj8 altpriority_encoder27
(
.data(data[15:0]),
.q(wire_altpriority_encoder27_q),
.zero(wire_altpriority_encoder27_zero));
acl_fp_sub_double_altpriority_encoder_fj8 altpriority_encoder28
(
.data(data[31:16]),
.q(wire_altpriority_encoder28_q),
.zero(wire_altpriority_encoder28_zero));
assign
q = {wire_altpriority_encoder27_zero, (({4{wire_altpriority_encoder27_zero}} & wire_altpriority_encoder28_q) | ({4{(~ wire_altpriority_encoder27_zero)}} & wire_altpriority_encoder27_q))},
zero = (wire_altpriority_encoder27_zero & wire_altpriority_encoder28_zero);
endmodule //acl_fp_sub_double_altpriority_encoder_ej8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_n28
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {(~ data[0])};
endmodule //acl_fp_sub_double_altpriority_encoder_n28
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_q28
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder41_q;
wire wire_altpriority_encoder41_zero;
wire [0:0] wire_altpriority_encoder42_q;
acl_fp_sub_double_altpriority_encoder_nh8 altpriority_encoder41
(
.data(data[1:0]),
.q(wire_altpriority_encoder41_q),
.zero(wire_altpriority_encoder41_zero));
acl_fp_sub_double_altpriority_encoder_n28 altpriority_encoder42
(
.data(data[3:2]),
.q(wire_altpriority_encoder42_q));
assign
q = {wire_altpriority_encoder41_zero, ((wire_altpriority_encoder41_zero & wire_altpriority_encoder42_q) | ((~ wire_altpriority_encoder41_zero) & wire_altpriority_encoder41_q))};
endmodule //acl_fp_sub_double_altpriority_encoder_q28
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_v28
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder39_q;
wire wire_altpriority_encoder39_zero;
wire [1:0] wire_altpriority_encoder40_q;
acl_fp_sub_double_altpriority_encoder_qh8 altpriority_encoder39
(
.data(data[3:0]),
.q(wire_altpriority_encoder39_q),
.zero(wire_altpriority_encoder39_zero));
acl_fp_sub_double_altpriority_encoder_q28 altpriority_encoder40
(
.data(data[7:4]),
.q(wire_altpriority_encoder40_q));
assign
q = {wire_altpriority_encoder39_zero, (({2{wire_altpriority_encoder39_zero}} & wire_altpriority_encoder40_q) | ({2{(~ wire_altpriority_encoder39_zero)}} & wire_altpriority_encoder39_q))};
endmodule //acl_fp_sub_double_altpriority_encoder_v28
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_f48
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder37_q;
wire wire_altpriority_encoder37_zero;
wire [2:0] wire_altpriority_encoder38_q;
acl_fp_sub_double_altpriority_encoder_vh8 altpriority_encoder37
(
.data(data[7:0]),
.q(wire_altpriority_encoder37_q),
.zero(wire_altpriority_encoder37_zero));
acl_fp_sub_double_altpriority_encoder_v28 altpriority_encoder38
(
.data(data[15:8]),
.q(wire_altpriority_encoder38_q));
assign
q = {wire_altpriority_encoder37_zero, (({3{wire_altpriority_encoder37_zero}} & wire_altpriority_encoder38_q) | ({3{(~ wire_altpriority_encoder37_zero)}} & wire_altpriority_encoder37_q))};
endmodule //acl_fp_sub_double_altpriority_encoder_f48
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_e48
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder35_q;
wire wire_altpriority_encoder35_zero;
wire [3:0] wire_altpriority_encoder36_q;
acl_fp_sub_double_altpriority_encoder_fj8 altpriority_encoder35
(
.data(data[15:0]),
.q(wire_altpriority_encoder35_q),
.zero(wire_altpriority_encoder35_zero));
acl_fp_sub_double_altpriority_encoder_f48 altpriority_encoder36
(
.data(data[31:16]),
.q(wire_altpriority_encoder36_q));
assign
q = {wire_altpriority_encoder35_zero, (({4{wire_altpriority_encoder35_zero}} & wire_altpriority_encoder36_q) | ({4{(~ wire_altpriority_encoder35_zero)}} & wire_altpriority_encoder35_q))};
endmodule //acl_fp_sub_double_altpriority_encoder_e48
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altpriority_encoder_k48
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder25_q;
wire wire_altpriority_encoder25_zero;
wire [4:0] wire_altpriority_encoder26_q;
acl_fp_sub_double_altpriority_encoder_ej8 altpriority_encoder25
(
.data(data[31:0]),
.q(wire_altpriority_encoder25_q),
.zero(wire_altpriority_encoder25_zero));
acl_fp_sub_double_altpriority_encoder_e48 altpriority_encoder26
(
.data(data[63:32]),
.q(wire_altpriority_encoder26_q));
assign
q = {wire_altpriority_encoder25_zero, (({5{wire_altpriority_encoder25_zero}} & wire_altpriority_encoder26_q) | ({5{(~ wire_altpriority_encoder25_zero)}} & wire_altpriority_encoder25_q))};
endmodule //acl_fp_sub_double_altpriority_encoder_k48
//synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 504
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sub_double_altfp_add_sub_roj
(
clk_en,
clock,
dataa,
datab,
result) ;
input clk_en;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [54:0] wire_lbarrel_shift_result;
wire [54:0] wire_rbarrel_shift_result;
wire [5:0] wire_leading_zeroes_cnt_q;
wire [5:0] wire_trailing_zeros_cnt_q;
reg both_inputs_are_infinite_dffe1;
reg [10:0] data_exp_dffe1;
reg [54:0] dataa_man_dffe1;
reg dataa_sign_dffe1;
reg [54:0] datab_man_dffe1;
reg datab_sign_dffe1;
reg denormal_res_dffe3;
reg denormal_res_dffe4;
reg [1:0] exp_adj_dffe21;
reg [10:0] exp_out_dffe5;
reg [10:0] exp_res_dffe2;
reg [10:0] exp_res_dffe21;
reg [10:0] exp_res_dffe3;
reg [10:0] exp_res_dffe4;
reg infinite_output_sign_dffe1;
reg infinite_output_sign_dffe2;
reg infinite_output_sign_dffe21;
reg infinite_output_sign_dffe3;
reg infinite_output_sign_dffe31;
reg infinite_output_sign_dffe4;
reg infinite_res_dffe3;
reg infinite_res_dffe4;
reg infinity_magnitude_sub_dffe2;
reg infinity_magnitude_sub_dffe21;
reg infinity_magnitude_sub_dffe3;
reg infinity_magnitude_sub_dffe31;
reg infinity_magnitude_sub_dffe4;
reg input_is_infinite_dffe1;
reg input_is_infinite_dffe2;
reg input_is_infinite_dffe21;
reg input_is_infinite_dffe3;
reg input_is_infinite_dffe31;
reg input_is_infinite_dffe4;
reg input_is_nan_dffe1;
reg input_is_nan_dffe2;
reg input_is_nan_dffe21;
reg input_is_nan_dffe3;
reg input_is_nan_dffe31;
reg input_is_nan_dffe4;
reg [54:0] man_add_sub_res_mag_dffe21;
reg man_add_sub_res_sign_dffe21;
reg [54:0] man_dffe31;
reg [5:0] man_leading_zeros_dffe31;
reg [51:0] man_out_dffe5;
reg [51:0] man_res_dffe4;
reg man_res_is_not_zero_dffe3;
reg man_res_is_not_zero_dffe31;
reg man_res_is_not_zero_dffe4;
reg need_complement_dffe2;
reg round_bit_dffe21;
reg round_bit_dffe3;
reg round_bit_dffe31;
reg rounded_res_infinity_dffe4;
reg sign_dffe31;
reg sign_out_dffe5;
reg sign_res_dffe3;
reg sign_res_dffe4;
reg sticky_bit_dffe1;
reg sticky_bit_dffe2;
reg sticky_bit_dffe21;
reg sticky_bit_dffe3;
reg sticky_bit_dffe31;
reg zero_man_sign_dffe2;
reg zero_man_sign_dffe21;
wire [11:0] wire_add_sub1_result;
wire [11:0] wire_add_sub2_result;
wire [6:0] wire_add_sub3_result;
wire [11:0] wire_add_sub4_result;
wire [11:0] wire_add_sub5_result;
wire [11:0] wire_add_sub6_result;
wire wire_man_2comp_res_lower_cout;
wire [28:0] wire_man_2comp_res_lower_result;
wire [27:0] wire_man_2comp_res_upper0_result;
wire [27:0] wire_man_2comp_res_upper1_result;
wire wire_man_add_sub_lower_cout;
wire [28:0] wire_man_add_sub_lower_result;
wire [27:0] wire_man_add_sub_upper0_result;
wire [27:0] wire_man_add_sub_upper1_result;
wire wire_man_res_rounding_add_sub_lower_cout;
wire [27:0] wire_man_res_rounding_add_sub_lower_result;
wire [26:0] wire_man_res_rounding_add_sub_upper1_result;
wire wire_trailing_zeros_limit_comparator_agb;
wire aclr;
wire add_sub_dffe25_wi;
wire add_sub_dffe25_wo;
wire add_sub_w2;
wire [26:0] adder_upper_w;
wire [11:0] aligned_dataa_exp_dffe12_wi;
wire [11:0] aligned_dataa_exp_dffe12_wo;
wire [11:0] aligned_dataa_exp_dffe13_wi;
wire [11:0] aligned_dataa_exp_dffe13_wo;
wire [11:0] aligned_dataa_exp_dffe14_wi;
wire [11:0] aligned_dataa_exp_dffe14_wo;
wire [11:0] aligned_dataa_exp_dffe15_wi;
wire [11:0] aligned_dataa_exp_dffe15_wo;
wire [11:0] aligned_dataa_exp_w;
wire [52:0] aligned_dataa_man_dffe12_wi;
wire [52:0] aligned_dataa_man_dffe12_wo;
wire [52:0] aligned_dataa_man_dffe13_wi;
wire [52:0] aligned_dataa_man_dffe13_wo;
wire [52:0] aligned_dataa_man_dffe14_wi;
wire [52:0] aligned_dataa_man_dffe14_wo;
wire [54:0] aligned_dataa_man_dffe15_w;
wire [52:0] aligned_dataa_man_dffe15_wi;
wire [52:0] aligned_dataa_man_dffe15_wo;
wire [54:0] aligned_dataa_man_w;
wire aligned_dataa_sign_dffe12_wi;
wire aligned_dataa_sign_dffe12_wo;
wire aligned_dataa_sign_dffe13_wi;
wire aligned_dataa_sign_dffe13_wo;
wire aligned_dataa_sign_dffe14_wi;
wire aligned_dataa_sign_dffe14_wo;
wire aligned_dataa_sign_dffe15_wi;
wire aligned_dataa_sign_dffe15_wo;
wire aligned_dataa_sign_w;
wire [11:0] aligned_datab_exp_dffe12_wi;
wire [11:0] aligned_datab_exp_dffe12_wo;
wire [11:0] aligned_datab_exp_dffe13_wi;
wire [11:0] aligned_datab_exp_dffe13_wo;
wire [11:0] aligned_datab_exp_dffe14_wi;
wire [11:0] aligned_datab_exp_dffe14_wo;
wire [11:0] aligned_datab_exp_dffe15_wi;
wire [11:0] aligned_datab_exp_dffe15_wo;
wire [11:0] aligned_datab_exp_w;
wire [52:0] aligned_datab_man_dffe12_wi;
wire [52:0] aligned_datab_man_dffe12_wo;
wire [52:0] aligned_datab_man_dffe13_wi;
wire [52:0] aligned_datab_man_dffe13_wo;
wire [52:0] aligned_datab_man_dffe14_wi;
wire [52:0] aligned_datab_man_dffe14_wo;
wire [54:0] aligned_datab_man_dffe15_w;
wire [52:0] aligned_datab_man_dffe15_wi;
wire [52:0] aligned_datab_man_dffe15_wo;
wire [54:0] aligned_datab_man_w;
wire aligned_datab_sign_dffe12_wi;
wire aligned_datab_sign_dffe12_wo;
wire aligned_datab_sign_dffe13_wi;
wire aligned_datab_sign_dffe13_wo;
wire aligned_datab_sign_dffe14_wi;
wire aligned_datab_sign_dffe14_wo;
wire aligned_datab_sign_dffe15_wi;
wire aligned_datab_sign_dffe15_wo;
wire aligned_datab_sign_w;
wire borrow_w;
wire both_inputs_are_infinite_dffe1_wi;
wire both_inputs_are_infinite_dffe1_wo;
wire both_inputs_are_infinite_dffe25_wi;
wire both_inputs_are_infinite_dffe25_wo;
wire [10:0] data_exp_dffe1_wi;
wire [10:0] data_exp_dffe1_wo;
wire [63:0] dataa_dffe11_wi;
wire [63:0] dataa_dffe11_wo;
wire [54:0] dataa_man_dffe1_wi;
wire [54:0] dataa_man_dffe1_wo;
wire dataa_sign_dffe1_wi;
wire dataa_sign_dffe1_wo;
wire dataa_sign_dffe25_wi;
wire dataa_sign_dffe25_wo;
wire [63:0] datab_dffe11_wi;
wire [63:0] datab_dffe11_wo;
wire [54:0] datab_man_dffe1_wi;
wire [54:0] datab_man_dffe1_wo;
wire datab_sign_dffe1_wi;
wire datab_sign_dffe1_wo;
wire denormal_flag_w;
wire denormal_res_dffe32_wi;
wire denormal_res_dffe32_wo;
wire denormal_res_dffe33_wi;
wire denormal_res_dffe33_wo;
wire denormal_res_dffe3_wi;
wire denormal_res_dffe3_wo;
wire denormal_res_dffe41_wi;
wire denormal_res_dffe41_wo;
wire denormal_res_dffe42_wi;
wire denormal_res_dffe42_wo;
wire denormal_res_dffe4_wi;
wire denormal_res_dffe4_wo;
wire denormal_result_w;
wire [10:0] exp_a_all_one_w;
wire [10:0] exp_a_not_zero_w;
wire [9:0] exp_adj_0pads;
wire [1:0] exp_adj_dffe21_wi;
wire [1:0] exp_adj_dffe21_wo;
wire [1:0] exp_adj_dffe23_wi;
wire [1:0] exp_adj_dffe23_wo;
wire [1:0] exp_adj_dffe26_wi;
wire [1:0] exp_adj_dffe26_wo;
wire [1:0] exp_adjust_by_add1;
wire [1:0] exp_adjust_by_add2;
wire [11:0] exp_adjustment2_add_sub_dataa_w;
wire [11:0] exp_adjustment2_add_sub_datab_w;
wire [11:0] exp_adjustment2_add_sub_w;
wire [11:0] exp_adjustment_add_sub_dataa_w;
wire [11:0] exp_adjustment_add_sub_datab_w;
wire [11:0] exp_adjustment_add_sub_w;
wire [10:0] exp_all_ones_w;
wire [10:0] exp_all_zeros_w;
wire exp_amb_mux_dffe13_wi;
wire exp_amb_mux_dffe13_wo;
wire exp_amb_mux_dffe14_wi;
wire exp_amb_mux_dffe14_wo;
wire exp_amb_mux_dffe15_wi;
wire exp_amb_mux_dffe15_wo;
wire exp_amb_mux_w;
wire [11:0] exp_amb_w;
wire [10:0] exp_b_all_one_w;
wire [10:0] exp_b_not_zero_w;
wire [11:0] exp_bma_w;
wire [4:0] exp_diff_abs_exceed_max_w;
wire [5:0] exp_diff_abs_max_w;
wire [10:0] exp_diff_abs_w;
wire [10:0] exp_intermediate_res_dffe41_wi;
wire [10:0] exp_intermediate_res_dffe41_wo;
wire [10:0] exp_intermediate_res_dffe42_wi;
wire [10:0] exp_intermediate_res_dffe42_wo;
wire [10:0] exp_intermediate_res_w;
wire [10:0] exp_out_dffe5_wi;
wire [10:0] exp_out_dffe5_wo;
wire [10:0] exp_res_dffe21_wi;
wire [10:0] exp_res_dffe21_wo;
wire [10:0] exp_res_dffe22_wi;
wire [10:0] exp_res_dffe22_wo;
wire [10:0] exp_res_dffe23_wi;
wire [10:0] exp_res_dffe23_wo;
wire [10:0] exp_res_dffe25_wi;
wire [10:0] exp_res_dffe25_wo;
wire [10:0] exp_res_dffe26_wi;
wire [10:0] exp_res_dffe26_wo;
wire [10:0] exp_res_dffe27_wi;
wire [10:0] exp_res_dffe27_wo;
wire [10:0] exp_res_dffe2_wi;
wire [10:0] exp_res_dffe2_wo;
wire [10:0] exp_res_dffe32_wi;
wire [10:0] exp_res_dffe32_wo;
wire [10:0] exp_res_dffe33_wi;
wire [10:0] exp_res_dffe33_wo;
wire [10:0] exp_res_dffe3_wi;
wire [10:0] exp_res_dffe3_wo;
wire [10:0] exp_res_dffe4_wi;
wire [10:0] exp_res_dffe4_wo;
wire [10:0] exp_res_max_w;
wire [11:0] exp_res_not_zero_w;
wire [11:0] exp_res_rounding_adder_dataa_w;
wire [11:0] exp_res_rounding_adder_w;
wire exp_rounded_res_infinity_w;
wire [10:0] exp_rounded_res_max_w;
wire [10:0] exp_rounded_res_w;
wire [11:0] exp_rounding_adjustment_w;
wire [11:0] exp_value;
wire force_infinity_w;
wire force_nan_w;
wire force_zero_w;
wire guard_bit_dffe3_wo;
wire infinite_output_sign_dffe1_wi;
wire infinite_output_sign_dffe1_wo;
wire infinite_output_sign_dffe21_wi;
wire infinite_output_sign_dffe21_wo;
wire infinite_output_sign_dffe22_wi;
wire infinite_output_sign_dffe22_wo;
wire infinite_output_sign_dffe23_wi;
wire infinite_output_sign_dffe23_wo;
wire infinite_output_sign_dffe25_wi;
wire infinite_output_sign_dffe25_wo;
wire infinite_output_sign_dffe26_wi;
wire infinite_output_sign_dffe26_wo;
wire infinite_output_sign_dffe27_wi;
wire infinite_output_sign_dffe27_wo;
wire infinite_output_sign_dffe2_wi;
wire infinite_output_sign_dffe2_wo;
wire infinite_output_sign_dffe31_wi;
wire infinite_output_sign_dffe31_wo;
wire infinite_output_sign_dffe32_wi;
wire infinite_output_sign_dffe32_wo;
wire infinite_output_sign_dffe33_wi;
wire infinite_output_sign_dffe33_wo;
wire infinite_output_sign_dffe3_wi;
wire infinite_output_sign_dffe3_wo;
wire infinite_output_sign_dffe41_wi;
wire infinite_output_sign_dffe41_wo;
wire infinite_output_sign_dffe42_wi;
wire infinite_output_sign_dffe42_wo;
wire infinite_output_sign_dffe4_wi;
wire infinite_output_sign_dffe4_wo;
wire infinite_res_dff32_wi;
wire infinite_res_dff32_wo;
wire infinite_res_dff33_wi;
wire infinite_res_dff33_wo;
wire infinite_res_dffe3_wi;
wire infinite_res_dffe3_wo;
wire infinite_res_dffe41_wi;
wire infinite_res_dffe41_wo;
wire infinite_res_dffe42_wi;
wire infinite_res_dffe42_wo;
wire infinite_res_dffe4_wi;
wire infinite_res_dffe4_wo;
wire infinity_magnitude_sub_dffe21_wi;
wire infinity_magnitude_sub_dffe21_wo;
wire infinity_magnitude_sub_dffe22_wi;
wire infinity_magnitude_sub_dffe22_wo;
wire infinity_magnitude_sub_dffe23_wi;
wire infinity_magnitude_sub_dffe23_wo;
wire infinity_magnitude_sub_dffe26_wi;
wire infinity_magnitude_sub_dffe26_wo;
wire infinity_magnitude_sub_dffe27_wi;
wire infinity_magnitude_sub_dffe27_wo;
wire infinity_magnitude_sub_dffe2_wi;
wire infinity_magnitude_sub_dffe2_wo;
wire infinity_magnitude_sub_dffe31_wi;
wire infinity_magnitude_sub_dffe31_wo;
wire infinity_magnitude_sub_dffe32_wi;
wire infinity_magnitude_sub_dffe32_wo;
wire infinity_magnitude_sub_dffe33_wi;
wire infinity_magnitude_sub_dffe33_wo;
wire infinity_magnitude_sub_dffe3_wi;
wire infinity_magnitude_sub_dffe3_wo;
wire infinity_magnitude_sub_dffe41_wi;
wire infinity_magnitude_sub_dffe41_wo;
wire infinity_magnitude_sub_dffe42_wi;
wire infinity_magnitude_sub_dffe42_wo;
wire infinity_magnitude_sub_dffe4_wi;
wire infinity_magnitude_sub_dffe4_wo;
wire input_dataa_denormal_dffe11_wi;
wire input_dataa_denormal_dffe11_wo;
wire input_dataa_denormal_w;
wire input_dataa_infinite_dffe11_wi;
wire input_dataa_infinite_dffe11_wo;
wire input_dataa_infinite_dffe12_wi;
wire input_dataa_infinite_dffe12_wo;
wire input_dataa_infinite_dffe13_wi;
wire input_dataa_infinite_dffe13_wo;
wire input_dataa_infinite_dffe14_wi;
wire input_dataa_infinite_dffe14_wo;
wire input_dataa_infinite_dffe15_wi;
wire input_dataa_infinite_dffe15_wo;
wire input_dataa_infinite_w;
wire input_dataa_nan_dffe11_wi;
wire input_dataa_nan_dffe11_wo;
wire input_dataa_nan_dffe12_wi;
wire input_dataa_nan_dffe12_wo;
wire input_dataa_nan_w;
wire input_dataa_zero_dffe11_wi;
wire input_dataa_zero_dffe11_wo;
wire input_dataa_zero_w;
wire input_datab_denormal_dffe11_wi;
wire input_datab_denormal_dffe11_wo;
wire input_datab_denormal_w;
wire input_datab_infinite_dffe11_wi;
wire input_datab_infinite_dffe11_wo;
wire input_datab_infinite_dffe12_wi;
wire input_datab_infinite_dffe12_wo;
wire input_datab_infinite_dffe13_wi;
wire input_datab_infinite_dffe13_wo;
wire input_datab_infinite_dffe14_wi;
wire input_datab_infinite_dffe14_wo;
wire input_datab_infinite_dffe15_wi;
wire input_datab_infinite_dffe15_wo;
wire input_datab_infinite_w;
wire input_datab_nan_dffe11_wi;
wire input_datab_nan_dffe11_wo;
wire input_datab_nan_dffe12_wi;
wire input_datab_nan_dffe12_wo;
wire input_datab_nan_w;
wire input_datab_zero_dffe11_wi;
wire input_datab_zero_dffe11_wo;
wire input_datab_zero_w;
wire input_is_infinite_dffe1_wi;
wire input_is_infinite_dffe1_wo;
wire input_is_infinite_dffe21_wi;
wire input_is_infinite_dffe21_wo;
wire input_is_infinite_dffe22_wi;
wire input_is_infinite_dffe22_wo;
wire input_is_infinite_dffe23_wi;
wire input_is_infinite_dffe23_wo;
wire input_is_infinite_dffe25_wi;
wire input_is_infinite_dffe25_wo;
wire input_is_infinite_dffe26_wi;
wire input_is_infinite_dffe26_wo;
wire input_is_infinite_dffe27_wi;
wire input_is_infinite_dffe27_wo;
wire input_is_infinite_dffe2_wi;
wire input_is_infinite_dffe2_wo;
wire input_is_infinite_dffe31_wi;
wire input_is_infinite_dffe31_wo;
wire input_is_infinite_dffe32_wi;
wire input_is_infinite_dffe32_wo;
wire input_is_infinite_dffe33_wi;
wire input_is_infinite_dffe33_wo;
wire input_is_infinite_dffe3_wi;
wire input_is_infinite_dffe3_wo;
wire input_is_infinite_dffe41_wi;
wire input_is_infinite_dffe41_wo;
wire input_is_infinite_dffe42_wi;
wire input_is_infinite_dffe42_wo;
wire input_is_infinite_dffe4_wi;
wire input_is_infinite_dffe4_wo;
wire input_is_nan_dffe13_wi;
wire input_is_nan_dffe13_wo;
wire input_is_nan_dffe14_wi;
wire input_is_nan_dffe14_wo;
wire input_is_nan_dffe15_wi;
wire input_is_nan_dffe15_wo;
wire input_is_nan_dffe1_wi;
wire input_is_nan_dffe1_wo;
wire input_is_nan_dffe21_wi;
wire input_is_nan_dffe21_wo;
wire input_is_nan_dffe22_wi;
wire input_is_nan_dffe22_wo;
wire input_is_nan_dffe23_wi;
wire input_is_nan_dffe23_wo;
wire input_is_nan_dffe25_wi;
wire input_is_nan_dffe25_wo;
wire input_is_nan_dffe26_wi;
wire input_is_nan_dffe26_wo;
wire input_is_nan_dffe27_wi;
wire input_is_nan_dffe27_wo;
wire input_is_nan_dffe2_wi;
wire input_is_nan_dffe2_wo;
wire input_is_nan_dffe31_wi;
wire input_is_nan_dffe31_wo;
wire input_is_nan_dffe32_wi;
wire input_is_nan_dffe32_wo;
wire input_is_nan_dffe33_wi;
wire input_is_nan_dffe33_wo;
wire input_is_nan_dffe3_wi;
wire input_is_nan_dffe3_wo;
wire input_is_nan_dffe41_wi;
wire input_is_nan_dffe41_wo;
wire input_is_nan_dffe42_wi;
wire input_is_nan_dffe42_wo;
wire input_is_nan_dffe4_wi;
wire input_is_nan_dffe4_wo;
wire [56:0] man_2comp_res_dataa_w;
wire [56:0] man_2comp_res_datab_w;
wire [56:0] man_2comp_res_w;
wire [51:0] man_a_not_zero_w;
wire [56:0] man_add_sub_dataa_w;
wire [56:0] man_add_sub_datab_w;
wire [54:0] man_add_sub_res_mag_dffe21_wi;
wire [54:0] man_add_sub_res_mag_dffe21_wo;
wire [54:0] man_add_sub_res_mag_dffe23_wi;
wire [54:0] man_add_sub_res_mag_dffe23_wo;
wire [54:0] man_add_sub_res_mag_dffe26_wi;
wire [54:0] man_add_sub_res_mag_dffe26_wo;
wire [56:0] man_add_sub_res_mag_dffe27_wi;
wire [56:0] man_add_sub_res_mag_dffe27_wo;
wire [56:0] man_add_sub_res_mag_w2;
wire man_add_sub_res_sign_dffe21_wo;
wire man_add_sub_res_sign_dffe23_wi;
wire man_add_sub_res_sign_dffe23_wo;
wire man_add_sub_res_sign_dffe26_wi;
wire man_add_sub_res_sign_dffe26_wo;
wire man_add_sub_res_sign_dffe27_wi;
wire man_add_sub_res_sign_dffe27_wo;
wire man_add_sub_res_sign_w2;
wire [56:0] man_add_sub_w;
wire [51:0] man_all_zeros_w;
wire [51:0] man_b_not_zero_w;
wire [54:0] man_dffe31_wo;
wire [54:0] man_intermediate_res_w;
wire [5:0] man_leading_zeros_cnt_w;
wire [5:0] man_leading_zeros_dffe31_wi;
wire [5:0] man_leading_zeros_dffe31_wo;
wire [51:0] man_nan_w;
wire [51:0] man_out_dffe5_wi;
wire [51:0] man_out_dffe5_wo;
wire [51:0] man_res_dffe4_wi;
wire [51:0] man_res_dffe4_wo;
wire man_res_is_not_zero_dffe31_wi;
wire man_res_is_not_zero_dffe31_wo;
wire man_res_is_not_zero_dffe32_wi;
wire man_res_is_not_zero_dffe32_wo;
wire man_res_is_not_zero_dffe33_wi;
wire man_res_is_not_zero_dffe33_wo;
wire man_res_is_not_zero_dffe3_wi;
wire man_res_is_not_zero_dffe3_wo;
wire man_res_is_not_zero_dffe41_wi;
wire man_res_is_not_zero_dffe41_wo;
wire man_res_is_not_zero_dffe42_wi;
wire man_res_is_not_zero_dffe42_wo;
wire man_res_is_not_zero_dffe4_wi;
wire man_res_is_not_zero_dffe4_wo;
wire [54:0] man_res_mag_w2;
wire man_res_not_zero_dffe23_wi;
wire man_res_not_zero_dffe23_wo;
wire man_res_not_zero_dffe26_wi;
wire man_res_not_zero_dffe26_wo;
wire [53:0] man_res_not_zero_w2;
wire [54:0] man_res_rounding_add_sub_datab_w;
wire [54:0] man_res_rounding_add_sub_w;
wire [52:0] man_res_w3;
wire [51:0] man_rounded_res_w;
wire man_rounding_add_value_w;
wire [52:0] man_smaller_dffe13_wi;
wire [52:0] man_smaller_dffe13_wo;
wire [52:0] man_smaller_w;
wire need_complement_dffe22_wi;
wire need_complement_dffe22_wo;
wire need_complement_dffe2_wi;
wire need_complement_dffe2_wo;
wire [1:0] pos_sign_bit_ext;
wire [5:0] priority_encoder_1pads_w;
wire round_bit_dffe21_wi;
wire round_bit_dffe21_wo;
wire round_bit_dffe23_wi;
wire round_bit_dffe23_wo;
wire round_bit_dffe26_wi;
wire round_bit_dffe26_wo;
wire round_bit_dffe31_wi;
wire round_bit_dffe31_wo;
wire round_bit_dffe32_wi;
wire round_bit_dffe32_wo;
wire round_bit_dffe33_wi;
wire round_bit_dffe33_wo;
wire round_bit_dffe3_wi;
wire round_bit_dffe3_wo;
wire round_bit_w;
wire rounded_res_infinity_dffe4_wi;
wire rounded_res_infinity_dffe4_wo;
wire [5:0] rshift_distance_dffe13_wi;
wire [5:0] rshift_distance_dffe13_wo;
wire [5:0] rshift_distance_dffe14_wi;
wire [5:0] rshift_distance_dffe14_wo;
wire [5:0] rshift_distance_dffe15_wi;
wire [5:0] rshift_distance_dffe15_wo;
wire [5:0] rshift_distance_w;
wire sign_dffe31_wi;
wire sign_dffe31_wo;
wire sign_dffe32_wi;
wire sign_dffe32_wo;
wire sign_dffe33_wi;
wire sign_dffe33_wo;
wire sign_out_dffe5_wi;
wire sign_out_dffe5_wo;
wire sign_res_dffe3_wi;
wire sign_res_dffe3_wo;
wire sign_res_dffe41_wi;
wire sign_res_dffe41_wo;
wire sign_res_dffe42_wi;
wire sign_res_dffe42_wo;
wire sign_res_dffe4_wi;
wire sign_res_dffe4_wo;
wire [6:0] sticky_bit_cnt_dataa_w;
wire [6:0] sticky_bit_cnt_datab_w;
wire [6:0] sticky_bit_cnt_res_w;
wire sticky_bit_dffe1_wi;
wire sticky_bit_dffe1_wo;
wire sticky_bit_dffe21_wi;
wire sticky_bit_dffe21_wo;
wire sticky_bit_dffe22_wi;
wire sticky_bit_dffe22_wo;
wire sticky_bit_dffe23_wi;
wire sticky_bit_dffe23_wo;
wire sticky_bit_dffe25_wi;
wire sticky_bit_dffe25_wo;
wire sticky_bit_dffe26_wi;
wire sticky_bit_dffe26_wo;
wire sticky_bit_dffe27_wi;
wire sticky_bit_dffe27_wo;
wire sticky_bit_dffe2_wi;
wire sticky_bit_dffe2_wo;
wire sticky_bit_dffe31_wi;
wire sticky_bit_dffe31_wo;
wire sticky_bit_dffe32_wi;
wire sticky_bit_dffe32_wo;
wire sticky_bit_dffe33_wi;
wire sticky_bit_dffe33_wo;
wire sticky_bit_dffe3_wi;
wire sticky_bit_dffe3_wo;
wire sticky_bit_w;
wire [6:0] trailing_zeros_limit_w;
wire zero_man_sign_dffe21_wi;
wire zero_man_sign_dffe21_wo;
wire zero_man_sign_dffe22_wi;
wire zero_man_sign_dffe22_wo;
wire zero_man_sign_dffe23_wi;
wire zero_man_sign_dffe23_wo;
wire zero_man_sign_dffe26_wi;
wire zero_man_sign_dffe26_wo;
wire zero_man_sign_dffe27_wi;
wire zero_man_sign_dffe27_wo;
wire zero_man_sign_dffe2_wi;
wire zero_man_sign_dffe2_wo;
acl_fp_sub_double_altbarrel_shift_32e lbarrel_shift
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data(man_dffe31_wo),
.distance(man_leading_zeros_cnt_w),
.result(wire_lbarrel_shift_result));
acl_fp_sub_double_altbarrel_shift_oib rbarrel_shift
(
.data({man_smaller_dffe13_wo, {2{1'b0}}}),
.distance(rshift_distance_dffe13_wo),
.result(wire_rbarrel_shift_result));
acl_fp_sub_double_altpriority_encoder_0c6 leading_zeroes_cnt
(
.data({man_add_sub_res_mag_dffe21_wo[54:1], 1'b1, {9{1'b0}}}),
.q(wire_leading_zeroes_cnt_q));
acl_fp_sub_double_altpriority_encoder_k48 trailing_zeros_cnt
(
.data({{12{1'b1}}, man_smaller_dffe13_wo[51:0]}),
.q(wire_trailing_zeros_cnt_q));
// synopsys translate_off
initial
both_inputs_are_infinite_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) both_inputs_are_infinite_dffe1 <= 1'b0;
else if (clk_en == 1'b1) both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
// synopsys translate_off
initial
data_exp_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) data_exp_dffe1 <= 11'b0;
else if (clk_en == 1'b1) data_exp_dffe1 <= data_exp_dffe1_wi;
// synopsys translate_off
initial
dataa_man_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_dffe1 <= 55'b0;
else if (clk_en == 1'b1) dataa_man_dffe1 <= dataa_man_dffe1_wi;
// synopsys translate_off
initial
dataa_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
// synopsys translate_off
initial
datab_man_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_dffe1 <= 55'b0;
else if (clk_en == 1'b1) datab_man_dffe1 <= datab_man_dffe1_wi;
// synopsys translate_off
initial
datab_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) datab_sign_dffe1 <= datab_sign_dffe1_wi;
// synopsys translate_off
initial
denormal_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) denormal_res_dffe3 <= 1'b0;
else if (clk_en == 1'b1) denormal_res_dffe3 <= denormal_res_dffe3_wi;
// synopsys translate_off
initial
denormal_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) denormal_res_dffe4 <= 1'b0;
else if (clk_en == 1'b1) denormal_res_dffe4 <= denormal_res_dffe4_wi;
// synopsys translate_off
initial
exp_adj_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_adj_dffe21 <= 2'b0;
else if (clk_en == 1'b1) exp_adj_dffe21 <= exp_adj_dffe21_wi;
// synopsys translate_off
initial
exp_out_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_out_dffe5 <= 11'b0;
else if (clk_en == 1'b1) exp_out_dffe5 <= exp_out_dffe5_wi;
// synopsys translate_off
initial
exp_res_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe2 <= 11'b0;
else if (clk_en == 1'b1) exp_res_dffe2 <= exp_res_dffe2_wi;
// synopsys translate_off
initial
exp_res_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe21 <= 11'b0;
else if (clk_en == 1'b1) exp_res_dffe21 <= exp_res_dffe21_wi;
// synopsys translate_off
initial
exp_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe3 <= 11'b0;
else if (clk_en == 1'b1) exp_res_dffe3 <= exp_res_dffe3_wi;
// synopsys translate_off
initial
exp_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe4 <= 11'b0;
else if (clk_en == 1'b1) exp_res_dffe4 <= exp_res_dffe4_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe2 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe21 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe3 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe31 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe4 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
// synopsys translate_off
initial
infinite_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_res_dffe3 <= 1'b0;
else if (clk_en == 1'b1) infinite_res_dffe3 <= infinite_res_dffe3_wi;
// synopsys translate_off
initial
infinite_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_res_dffe4 <= 1'b0;
else if (clk_en == 1'b1) infinite_res_dffe4 <= infinite_res_dffe4_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe2 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe21 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe3 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe31 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe4 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
// synopsys translate_off
initial
input_is_infinite_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
// synopsys translate_off
initial
input_is_infinite_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
// synopsys translate_off
initial
input_is_infinite_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe21 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
// synopsys translate_off
initial
input_is_infinite_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
// synopsys translate_off
initial
input_is_infinite_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe31 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
// synopsys translate_off
initial
input_is_infinite_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
// synopsys translate_off
initial
input_is_nan_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
// synopsys translate_off
initial
input_is_nan_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
// synopsys translate_off
initial
input_is_nan_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe21 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
// synopsys translate_off
initial
input_is_nan_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
// synopsys translate_off
initial
input_is_nan_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe31 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
// synopsys translate_off
initial
input_is_nan_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
// synopsys translate_off
initial
man_add_sub_res_mag_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_add_sub_res_mag_dffe21 <= 55'b0;
else if (clk_en == 1'b1) man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
// synopsys translate_off
initial
man_add_sub_res_sign_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_add_sub_res_sign_dffe21 <= 1'b0;
else if (clk_en == 1'b1) man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
// synopsys translate_off
initial
man_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_dffe31 <= 55'b0;
else if (clk_en == 1'b1) man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
// synopsys translate_off
initial
man_leading_zeros_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_leading_zeros_dffe31 <= 6'b0;
else if (clk_en == 1'b1) man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
// synopsys translate_off
initial
man_out_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_out_dffe5 <= 52'b0;
else if (clk_en == 1'b1) man_out_dffe5 <= man_out_dffe5_wi;
// synopsys translate_off
initial
man_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_dffe4 <= 52'b0;
else if (clk_en == 1'b1) man_res_dffe4 <= man_res_dffe4_wi;
// synopsys translate_off
initial
man_res_is_not_zero_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_is_not_zero_dffe3 <= 1'b0;
else if (clk_en == 1'b1) man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
// synopsys translate_off
initial
man_res_is_not_zero_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_is_not_zero_dffe31 <= 1'b0;
else if (clk_en == 1'b1) man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
// synopsys translate_off
initial
man_res_is_not_zero_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_is_not_zero_dffe4 <= 1'b0;
else if (clk_en == 1'b1) man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
// synopsys translate_off
initial
need_complement_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) need_complement_dffe2 <= 1'b0;
else if (clk_en == 1'b1) need_complement_dffe2 <= need_complement_dffe2_wi;
// synopsys translate_off
initial
round_bit_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_bit_dffe21 <= 1'b0;
else if (clk_en == 1'b1) round_bit_dffe21 <= round_bit_dffe21_wi;
// synopsys translate_off
initial
round_bit_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_bit_dffe3 <= 1'b0;
else if (clk_en == 1'b1) round_bit_dffe3 <= round_bit_dffe3_wi;
// synopsys translate_off
initial
round_bit_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_bit_dffe31 <= 1'b0;
else if (clk_en == 1'b1) round_bit_dffe31 <= round_bit_dffe31_wi;
// synopsys translate_off
initial
rounded_res_infinity_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rounded_res_infinity_dffe4 <= 1'b0;
else if (clk_en == 1'b1) rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
// synopsys translate_off
initial
sign_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe31 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe31 <= sign_dffe31_wi;
// synopsys translate_off
initial
sign_out_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_out_dffe5 <= 1'b0;
else if (clk_en == 1'b1) sign_out_dffe5 <= sign_out_dffe5_wi;
// synopsys translate_off
initial
sign_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_res_dffe3 <= 1'b0;
else if (clk_en == 1'b1) sign_res_dffe3 <= sign_res_dffe3_wi;
// synopsys translate_off
initial
sign_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_res_dffe4 <= 1'b0;
else if (clk_en == 1'b1) sign_res_dffe4 <= sign_res_dffe4_wi;
// synopsys translate_off
initial
sticky_bit_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe1 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
// synopsys translate_off
initial
sticky_bit_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe2 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
// synopsys translate_off
initial
sticky_bit_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe21 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
// synopsys translate_off
initial
sticky_bit_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe3 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
// synopsys translate_off
initial
sticky_bit_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe31 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
// synopsys translate_off
initial
zero_man_sign_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_man_sign_dffe2 <= 1'b0;
else if (clk_en == 1'b1) zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
// synopsys translate_off
initial
zero_man_sign_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_man_sign_dffe21 <= 1'b0;
else if (clk_en == 1'b1) zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
lpm_add_sub add_sub1
(
.cout(),
.dataa(aligned_dataa_exp_w),
.datab(aligned_datab_exp_w),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "SUB",
add_sub1.lpm_representation = "SIGNED",
add_sub1.lpm_width = 12,
add_sub1.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub2
(
.cout(),
.dataa(aligned_datab_exp_w),
.datab(aligned_dataa_exp_w),
.overflow(),
.result(wire_add_sub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub2.lpm_direction = "SUB",
add_sub2.lpm_representation = "SIGNED",
add_sub2.lpm_width = 12,
add_sub2.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub3
(
.cout(),
.dataa(sticky_bit_cnt_dataa_w),
.datab(sticky_bit_cnt_datab_w),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_representation = "SIGNED",
add_sub3.lpm_width = 7,
add_sub3.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub4
(
.cout(),
.dataa(exp_adjustment_add_sub_dataa_w),
.datab(exp_adjustment_add_sub_datab_w),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "ADD",
add_sub4.lpm_representation = "SIGNED",
add_sub4.lpm_width = 12,
add_sub4.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_adjustment2_add_sub_dataa_w),
.datab(exp_adjustment2_add_sub_datab_w),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_direction = "ADD",
add_sub5.lpm_pipeline = 1,
add_sub5.lpm_representation = "SIGNED",
add_sub5.lpm_width = 12,
add_sub5.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub6
(
.cout(),
.dataa(exp_res_rounding_adder_dataa_w),
.datab(exp_rounding_adjustment_w),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_direction = "ADD",
add_sub6.lpm_representation = "SIGNED",
add_sub6.lpm_width = 12,
add_sub6.lpm_type = "lpm_add_sub";
lpm_add_sub man_2comp_res_lower
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(borrow_w),
.clken(clk_en),
.clock(clock),
.cout(wire_man_2comp_res_lower_cout),
.dataa(man_2comp_res_dataa_w[28:0]),
.datab(man_2comp_res_datab_w[28:0]),
.overflow(),
.result(wire_man_2comp_res_lower_result));
defparam
man_2comp_res_lower.lpm_pipeline = 1,
man_2comp_res_lower.lpm_representation = "SIGNED",
man_2comp_res_lower.lpm_width = 29,
man_2comp_res_lower.lpm_type = "lpm_add_sub";
lpm_add_sub man_2comp_res_upper0
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b0),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_2comp_res_dataa_w[56:29]),
.datab(man_2comp_res_datab_w[56:29]),
.overflow(),
.result(wire_man_2comp_res_upper0_result));
defparam
man_2comp_res_upper0.lpm_pipeline = 1,
man_2comp_res_upper0.lpm_representation = "SIGNED",
man_2comp_res_upper0.lpm_width = 28,
man_2comp_res_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub man_2comp_res_upper1
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b1),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_2comp_res_dataa_w[56:29]),
.datab(man_2comp_res_datab_w[56:29]),
.overflow(),
.result(wire_man_2comp_res_upper1_result));
defparam
man_2comp_res_upper1.lpm_pipeline = 1,
man_2comp_res_upper1.lpm_representation = "SIGNED",
man_2comp_res_upper1.lpm_width = 28,
man_2comp_res_upper1.lpm_type = "lpm_add_sub";
lpm_add_sub man_add_sub_lower
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(borrow_w),
.clken(clk_en),
.clock(clock),
.cout(wire_man_add_sub_lower_cout),
.dataa(man_add_sub_dataa_w[28:0]),
.datab(man_add_sub_datab_w[28:0]),
.overflow(),
.result(wire_man_add_sub_lower_result));
defparam
man_add_sub_lower.lpm_pipeline = 1,
man_add_sub_lower.lpm_representation = "SIGNED",
man_add_sub_lower.lpm_width = 29,
man_add_sub_lower.lpm_type = "lpm_add_sub";
lpm_add_sub man_add_sub_upper0
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b0),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_add_sub_dataa_w[56:29]),
.datab(man_add_sub_datab_w[56:29]),
.overflow(),
.result(wire_man_add_sub_upper0_result));
defparam
man_add_sub_upper0.lpm_pipeline = 1,
man_add_sub_upper0.lpm_representation = "SIGNED",
man_add_sub_upper0.lpm_width = 28,
man_add_sub_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub man_add_sub_upper1
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b1),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_add_sub_dataa_w[56:29]),
.datab(man_add_sub_datab_w[56:29]),
.overflow(),
.result(wire_man_add_sub_upper1_result));
defparam
man_add_sub_upper1.lpm_pipeline = 1,
man_add_sub_upper1.lpm_representation = "SIGNED",
man_add_sub_upper1.lpm_width = 28,
man_add_sub_upper1.lpm_type = "lpm_add_sub";
lpm_add_sub man_res_rounding_add_sub_lower
(
.cout(wire_man_res_rounding_add_sub_lower_cout),
.dataa(man_intermediate_res_w[27:0]),
.datab(man_res_rounding_add_sub_datab_w[27:0]),
.overflow(),
.result(wire_man_res_rounding_add_sub_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_res_rounding_add_sub_lower.lpm_direction = "ADD",
man_res_rounding_add_sub_lower.lpm_representation = "SIGNED",
man_res_rounding_add_sub_lower.lpm_width = 28,
man_res_rounding_add_sub_lower.lpm_type = "lpm_add_sub";
lpm_add_sub man_res_rounding_add_sub_upper1
(
.cin(1'b1),
.cout(),
.dataa(man_intermediate_res_w[54:28]),
.datab(man_res_rounding_add_sub_datab_w[54:28]),
.overflow(),
.result(wire_man_res_rounding_add_sub_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_res_rounding_add_sub_upper1.lpm_direction = "ADD",
man_res_rounding_add_sub_upper1.lpm_representation = "SIGNED",
man_res_rounding_add_sub_upper1.lpm_width = 27,
man_res_rounding_add_sub_upper1.lpm_type = "lpm_add_sub";
lpm_compare trailing_zeros_limit_comparator
(
.aeb(),
.agb(wire_trailing_zeros_limit_comparator_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(sticky_bit_cnt_res_w),
.datab(trailing_zeros_limit_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
trailing_zeros_limit_comparator.lpm_representation = "SIGNED",
trailing_zeros_limit_comparator.lpm_width = 7,
trailing_zeros_limit_comparator.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
add_sub_dffe25_wi = add_sub_w2,
add_sub_dffe25_wo = add_sub_dffe25_wi,
add_sub_w2 = (dataa_sign_dffe1_wo ^ datab_sign_dffe1_wo),
adder_upper_w = man_intermediate_res_w[54:28],
aligned_dataa_exp_dffe12_wi = aligned_dataa_exp_w,
aligned_dataa_exp_dffe12_wo = aligned_dataa_exp_dffe12_wi,
aligned_dataa_exp_dffe13_wi = aligned_dataa_exp_dffe12_wo,
aligned_dataa_exp_dffe13_wo = aligned_dataa_exp_dffe13_wi,
aligned_dataa_exp_dffe14_wi = aligned_dataa_exp_dffe13_wo,
aligned_dataa_exp_dffe14_wo = aligned_dataa_exp_dffe14_wi,
aligned_dataa_exp_dffe15_wi = aligned_dataa_exp_dffe14_wo,
aligned_dataa_exp_dffe15_wo = aligned_dataa_exp_dffe15_wi,
aligned_dataa_exp_w = {1'b0, ({11{(~ input_dataa_denormal_dffe11_wo)}} & dataa_dffe11_wo[62:52])},
aligned_dataa_man_dffe12_wi = aligned_dataa_man_w[54:2],
aligned_dataa_man_dffe12_wo = aligned_dataa_man_dffe12_wi,
aligned_dataa_man_dffe13_wi = aligned_dataa_man_dffe12_wo,
aligned_dataa_man_dffe13_wo = aligned_dataa_man_dffe13_wi,
aligned_dataa_man_dffe14_wi = aligned_dataa_man_dffe13_wo,
aligned_dataa_man_dffe14_wo = aligned_dataa_man_dffe14_wi,
aligned_dataa_man_dffe15_w = {aligned_dataa_man_dffe15_wo, {2{1'b0}}},
aligned_dataa_man_dffe15_wi = aligned_dataa_man_dffe14_wo,
aligned_dataa_man_dffe15_wo = aligned_dataa_man_dffe15_wi,
aligned_dataa_man_w = {(((~ input_dataa_infinite_dffe11_wo) & (~ input_dataa_denormal_dffe11_wo)) & (~ input_dataa_zero_dffe11_wo)), ({52{(~ input_dataa_denormal_dffe11_wo)}} & dataa_dffe11_wo[51:0]), {2{1'b0}}},
aligned_dataa_sign_dffe12_wi = aligned_dataa_sign_w,
aligned_dataa_sign_dffe12_wo = aligned_dataa_sign_dffe12_wi,
aligned_dataa_sign_dffe13_wi = aligned_dataa_sign_dffe12_wo,
aligned_dataa_sign_dffe13_wo = aligned_dataa_sign_dffe13_wi,
aligned_dataa_sign_dffe14_wi = aligned_dataa_sign_dffe13_wo,
aligned_dataa_sign_dffe14_wo = aligned_dataa_sign_dffe14_wi,
aligned_dataa_sign_dffe15_wi = aligned_dataa_sign_dffe14_wo,
aligned_dataa_sign_dffe15_wo = aligned_dataa_sign_dffe15_wi,
aligned_dataa_sign_w = dataa_dffe11_wo[63],
aligned_datab_exp_dffe12_wi = aligned_datab_exp_w,
aligned_datab_exp_dffe12_wo = aligned_datab_exp_dffe12_wi,
aligned_datab_exp_dffe13_wi = aligned_datab_exp_dffe12_wo,
aligned_datab_exp_dffe13_wo = aligned_datab_exp_dffe13_wi,
aligned_datab_exp_dffe14_wi = aligned_datab_exp_dffe13_wo,
aligned_datab_exp_dffe14_wo = aligned_datab_exp_dffe14_wi,
aligned_datab_exp_dffe15_wi = aligned_datab_exp_dffe14_wo,
aligned_datab_exp_dffe15_wo = aligned_datab_exp_dffe15_wi,
aligned_datab_exp_w = {1'b0, ({11{(~ input_datab_denormal_dffe11_wo)}} & datab_dffe11_wo[62:52])},
aligned_datab_man_dffe12_wi = aligned_datab_man_w[54:2],
aligned_datab_man_dffe12_wo = aligned_datab_man_dffe12_wi,
aligned_datab_man_dffe13_wi = aligned_datab_man_dffe12_wo,
aligned_datab_man_dffe13_wo = aligned_datab_man_dffe13_wi,
aligned_datab_man_dffe14_wi = aligned_datab_man_dffe13_wo,
aligned_datab_man_dffe14_wo = aligned_datab_man_dffe14_wi,
aligned_datab_man_dffe15_w = {aligned_datab_man_dffe15_wo, {2{1'b0}}},
aligned_datab_man_dffe15_wi = aligned_datab_man_dffe14_wo,
aligned_datab_man_dffe15_wo = aligned_datab_man_dffe15_wi,
aligned_datab_man_w = {(((~ input_datab_infinite_dffe11_wo) & (~ input_datab_denormal_dffe11_wo)) & (~ input_datab_zero_dffe11_wo)), ({52{(~ input_datab_denormal_dffe11_wo)}} & datab_dffe11_wo[51:0]), {2{1'b0}}},
aligned_datab_sign_dffe12_wi = aligned_datab_sign_w,
aligned_datab_sign_dffe12_wo = aligned_datab_sign_dffe12_wi,
aligned_datab_sign_dffe13_wi = aligned_datab_sign_dffe12_wo,
aligned_datab_sign_dffe13_wo = aligned_datab_sign_dffe13_wi,
aligned_datab_sign_dffe14_wi = aligned_datab_sign_dffe13_wo,
aligned_datab_sign_dffe14_wo = aligned_datab_sign_dffe14_wi,
aligned_datab_sign_dffe15_wi = aligned_datab_sign_dffe14_wo,
aligned_datab_sign_dffe15_wo = aligned_datab_sign_dffe15_wi,
aligned_datab_sign_w = datab_dffe11_wo[63],
borrow_w = ((~ sticky_bit_dffe1_wo) & (~ add_sub_w2)),
both_inputs_are_infinite_dffe1_wi = (input_dataa_infinite_dffe15_wo & input_datab_infinite_dffe15_wo),
both_inputs_are_infinite_dffe1_wo = both_inputs_are_infinite_dffe1,
both_inputs_are_infinite_dffe25_wi = both_inputs_are_infinite_dffe1_wo,
both_inputs_are_infinite_dffe25_wo = both_inputs_are_infinite_dffe25_wi,
data_exp_dffe1_wi = (({11{(~ exp_amb_mux_dffe15_wo)}} & aligned_dataa_exp_dffe15_wo[10:0]) | ({11{exp_amb_mux_dffe15_wo}} & aligned_datab_exp_dffe15_wo[10:0])),
data_exp_dffe1_wo = data_exp_dffe1,
dataa_dffe11_wi = dataa,
dataa_dffe11_wo = dataa_dffe11_wi,
dataa_man_dffe1_wi = (({55{(~ exp_amb_mux_dffe15_wo)}} & aligned_dataa_man_dffe15_w) | ({55{exp_amb_mux_dffe15_wo}} & wire_rbarrel_shift_result)),
dataa_man_dffe1_wo = dataa_man_dffe1,
dataa_sign_dffe1_wi = aligned_dataa_sign_dffe15_wo,
dataa_sign_dffe1_wo = dataa_sign_dffe1,
dataa_sign_dffe25_wi = dataa_sign_dffe1_wo,
dataa_sign_dffe25_wo = dataa_sign_dffe25_wi,
datab_dffe11_wi = datab,
datab_dffe11_wo = datab_dffe11_wi,
datab_man_dffe1_wi = (({55{(~ exp_amb_mux_dffe15_wo)}} & wire_rbarrel_shift_result) | ({55{exp_amb_mux_dffe15_wo}} & aligned_datab_man_dffe15_w)),
datab_man_dffe1_wo = datab_man_dffe1,
datab_sign_dffe1_wi = aligned_datab_sign_dffe15_wo,
datab_sign_dffe1_wo = datab_sign_dffe1,
denormal_flag_w = ((((~ force_nan_w) & (~ force_infinity_w)) & (~ force_zero_w)) & denormal_res_dffe4_wo),
denormal_res_dffe32_wi = denormal_result_w,
denormal_res_dffe32_wo = denormal_res_dffe32_wi,
denormal_res_dffe33_wi = denormal_res_dffe32_wo,
denormal_res_dffe33_wo = denormal_res_dffe33_wi,
denormal_res_dffe3_wi = denormal_res_dffe33_wo,
denormal_res_dffe3_wo = denormal_res_dffe3,
denormal_res_dffe41_wi = denormal_res_dffe42_wo,
denormal_res_dffe41_wo = denormal_res_dffe41_wi,
denormal_res_dffe42_wi = denormal_res_dffe3_wo,
denormal_res_dffe42_wo = denormal_res_dffe42_wi,
denormal_res_dffe4_wi = denormal_res_dffe41_wo,
denormal_res_dffe4_wo = denormal_res_dffe4,
denormal_result_w = ((~ exp_res_not_zero_w[11]) | exp_adjustment2_add_sub_w[11]),
exp_a_all_one_w = {(dataa[62] & exp_a_all_one_w[9]), (dataa[61] & exp_a_all_one_w[8]), (dataa[60] & exp_a_all_one_w[7]), (dataa[59] & exp_a_all_one_w[6]), (dataa[58] & exp_a_all_one_w[5]), (dataa[57] & exp_a_all_one_w[4]), (dataa[56] & exp_a_all_one_w[3]), (dataa[55] & exp_a_all_one_w[2]), (dataa[54] & exp_a_all_one_w[1]), (dataa[53] & exp_a_all_one_w[0]), dataa[52]},
exp_a_not_zero_w = {(dataa[62] | exp_a_not_zero_w[9]), (dataa[61] | exp_a_not_zero_w[8]), (dataa[60] | exp_a_not_zero_w[7]), (dataa[59] | exp_a_not_zero_w[6]), (dataa[58] | exp_a_not_zero_w[5]), (dataa[57] | exp_a_not_zero_w[4]), (dataa[56] | exp_a_not_zero_w[3]), (dataa[55] | exp_a_not_zero_w[2]), (dataa[54] | exp_a_not_zero_w[1]), (dataa[53] | exp_a_not_zero_w[0]), dataa[52]},
exp_adj_0pads = {10{1'b0}},
exp_adj_dffe21_wi = (({2{man_add_sub_res_mag_dffe27_wo[55]}} & exp_adjust_by_add2) | ({2{(~ man_add_sub_res_mag_dffe27_wo[55])}} & exp_adjust_by_add1)),
exp_adj_dffe21_wo = exp_adj_dffe21,
exp_adj_dffe23_wi = exp_adj_dffe21_wo,
exp_adj_dffe23_wo = exp_adj_dffe23_wi,
exp_adj_dffe26_wi = exp_adj_dffe23_wo,
exp_adj_dffe26_wo = exp_adj_dffe26_wi,
exp_adjust_by_add1 = 2'b01,
exp_adjust_by_add2 = 2'b10,
exp_adjustment2_add_sub_dataa_w = exp_value,
exp_adjustment2_add_sub_datab_w = exp_adjustment_add_sub_w,
exp_adjustment2_add_sub_w = wire_add_sub5_result,
exp_adjustment_add_sub_dataa_w = {priority_encoder_1pads_w, wire_leading_zeroes_cnt_q},
exp_adjustment_add_sub_datab_w = {exp_adj_0pads, exp_adj_dffe26_wo},
exp_adjustment_add_sub_w = wire_add_sub4_result,
exp_all_ones_w = {11{1'b1}},
exp_all_zeros_w = {11{1'b0}},
exp_amb_mux_dffe13_wi = exp_amb_mux_w,
exp_amb_mux_dffe13_wo = exp_amb_mux_dffe13_wi,
exp_amb_mux_dffe14_wi = exp_amb_mux_dffe13_wo,
exp_amb_mux_dffe14_wo = exp_amb_mux_dffe14_wi,
exp_amb_mux_dffe15_wi = exp_amb_mux_dffe14_wo,
exp_amb_mux_dffe15_wo = exp_amb_mux_dffe15_wi,
exp_amb_mux_w = exp_amb_w[11],
exp_amb_w = wire_add_sub1_result,
exp_b_all_one_w = {(datab[62] & exp_b_all_one_w[9]), (datab[61] & exp_b_all_one_w[8]), (datab[60] & exp_b_all_one_w[7]), (datab[59] & exp_b_all_one_w[6]), (datab[58] & exp_b_all_one_w[5]), (datab[57] & exp_b_all_one_w[4]), (datab[56] & exp_b_all_one_w[3]), (datab[55] & exp_b_all_one_w[2]), (datab[54] & exp_b_all_one_w[1]), (datab[53] & exp_b_all_one_w[0]), datab[52]},
exp_b_not_zero_w = {(datab[62] | exp_b_not_zero_w[9]), (datab[61] | exp_b_not_zero_w[8]), (datab[60] | exp_b_not_zero_w[7]), (datab[59] | exp_b_not_zero_w[6]), (datab[58] | exp_b_not_zero_w[5]), (datab[57] | exp_b_not_zero_w[4]), (datab[56] | exp_b_not_zero_w[3]), (datab[55] | exp_b_not_zero_w[2]), (datab[54] | exp_b_not_zero_w[1]), (datab[53] | exp_b_not_zero_w[0]), datab[52]},
exp_bma_w = wire_add_sub2_result,
exp_diff_abs_exceed_max_w = {(exp_diff_abs_exceed_max_w[3] | exp_diff_abs_w[10]), (exp_diff_abs_exceed_max_w[2] | exp_diff_abs_w[9]), (exp_diff_abs_exceed_max_w[1] | exp_diff_abs_w[8]), (exp_diff_abs_exceed_max_w[0] | exp_diff_abs_w[7]), exp_diff_abs_w[6]},
exp_diff_abs_max_w = {6{1'b1}},
exp_diff_abs_w = (({11{(~ exp_amb_mux_w)}} & exp_amb_w[10:0]) | ({11{exp_amb_mux_w}} & exp_bma_w[10:0])),
exp_intermediate_res_dffe41_wi = exp_intermediate_res_dffe42_wo,
exp_intermediate_res_dffe41_wo = exp_intermediate_res_dffe41_wi,
exp_intermediate_res_dffe42_wi = exp_intermediate_res_w,
exp_intermediate_res_dffe42_wo = exp_intermediate_res_dffe42_wi,
exp_intermediate_res_w = exp_res_dffe3_wo,
exp_out_dffe5_wi = (({11{force_nan_w}} & exp_all_ones_w) | ({11{(~ force_nan_w)}} & (({11{force_infinity_w}} & exp_all_ones_w) | ({11{(~ force_infinity_w)}} & (({11{(force_zero_w | denormal_flag_w)}} & exp_all_zeros_w) | ({11{(~ (force_zero_w | denormal_flag_w))}} & exp_res_dffe4_wo)))))),
exp_out_dffe5_wo = exp_out_dffe5,
exp_res_dffe21_wi = exp_res_dffe27_wo,
exp_res_dffe21_wo = exp_res_dffe21,
exp_res_dffe22_wi = exp_res_dffe2_wo,
exp_res_dffe22_wo = exp_res_dffe22_wi,
exp_res_dffe23_wi = exp_res_dffe21_wo,
exp_res_dffe23_wo = exp_res_dffe23_wi,
exp_res_dffe25_wi = data_exp_dffe1_wo,
exp_res_dffe25_wo = exp_res_dffe25_wi,
exp_res_dffe26_wi = exp_res_dffe23_wo,
exp_res_dffe26_wo = exp_res_dffe26_wi,
exp_res_dffe27_wi = exp_res_dffe22_wo,
exp_res_dffe27_wo = exp_res_dffe27_wi,
exp_res_dffe2_wi = exp_res_dffe25_wo,
exp_res_dffe2_wo = exp_res_dffe2,
exp_res_dffe32_wi = ({11{(~ denormal_result_w)}} & exp_adjustment2_add_sub_w[10:0]),
exp_res_dffe32_wo = exp_res_dffe32_wi,
exp_res_dffe33_wi = exp_res_dffe32_wo,
exp_res_dffe33_wo = exp_res_dffe33_wi,
exp_res_dffe3_wi = exp_res_dffe33_wo,
exp_res_dffe3_wo = exp_res_dffe3,
exp_res_dffe4_wi = exp_rounded_res_w,
exp_res_dffe4_wo = exp_res_dffe4,
exp_res_max_w = {(exp_res_max_w[9] & exp_adjustment2_add_sub_w[10]), (exp_res_max_w[8] & exp_adjustment2_add_sub_w[9]), (exp_res_max_w[7] & exp_adjustment2_add_sub_w[8]), (exp_res_max_w[6] & exp_adjustment2_add_sub_w[7]), (exp_res_max_w[5] & exp_adjustment2_add_sub_w[6]), (exp_res_max_w[4] & exp_adjustment2_add_sub_w[5]), (exp_res_max_w[3] & exp_adjustment2_add_sub_w[4]), (exp_res_max_w[2] & exp_adjustment2_add_sub_w[3]), (exp_res_max_w[1] & exp_adjustment2_add_sub_w[2]), (exp_res_max_w[0] & exp_adjustment2_add_sub_w[1]), exp_adjustment2_add_sub_w[0]},
exp_res_not_zero_w = {(exp_res_not_zero_w[10] | exp_adjustment2_add_sub_w[11]), (exp_res_not_zero_w[9] | exp_adjustment2_add_sub_w[10]), (exp_res_not_zero_w[8] | exp_adjustment2_add_sub_w[9]), (exp_res_not_zero_w[7] | exp_adjustment2_add_sub_w[8]), (exp_res_not_zero_w[6] | exp_adjustment2_add_sub_w[7]), (exp_res_not_zero_w[5] | exp_adjustment2_add_sub_w[6]), (exp_res_not_zero_w[4] | exp_adjustment2_add_sub_w[5]), (exp_res_not_zero_w[3] | exp_adjustment2_add_sub_w[4]), (exp_res_not_zero_w[2] | exp_adjustment2_add_sub_w[3]), (exp_res_not_zero_w[1] | exp_adjustment2_add_sub_w[2]), (exp_res_not_zero_w[0] | exp_adjustment2_add_sub_w[1]), exp_adjustment2_add_sub_w[0]},
exp_res_rounding_adder_dataa_w = {1'b0, exp_intermediate_res_dffe41_wo},
exp_res_rounding_adder_w = wire_add_sub6_result,
exp_rounded_res_infinity_w = exp_rounded_res_max_w[10],
exp_rounded_res_max_w = {(exp_rounded_res_max_w[9] & exp_rounded_res_w[10]), (exp_rounded_res_max_w[8] & exp_rounded_res_w[9]), (exp_rounded_res_max_w[7] & exp_rounded_res_w[8]), (exp_rounded_res_max_w[6] & exp_rounded_res_w[7]), (exp_rounded_res_max_w[5] & exp_rounded_res_w[6]), (exp_rounded_res_max_w[4] & exp_rounded_res_w[5]), (exp_rounded_res_max_w[3] & exp_rounded_res_w[4]), (exp_rounded_res_max_w[2] & exp_rounded_res_w[3]), (exp_rounded_res_max_w[1] & exp_rounded_res_w[2]), (exp_rounded_res_max_w[0] & exp_rounded_res_w[1]), exp_rounded_res_w[0]},
exp_rounded_res_w = exp_res_rounding_adder_w[10:0],
exp_rounding_adjustment_w = {{11{1'b0}}, man_res_rounding_add_sub_w[53]},
exp_value = {1'b0, exp_res_dffe26_wo},
force_infinity_w = ((input_is_infinite_dffe4_wo | rounded_res_infinity_dffe4_wo) | infinite_res_dffe4_wo),
force_nan_w = (infinity_magnitude_sub_dffe4_wo | input_is_nan_dffe4_wo),
force_zero_w = (~ man_res_is_not_zero_dffe4_wo),
guard_bit_dffe3_wo = man_res_w3[0],
infinite_output_sign_dffe1_wi = (((~ input_datab_infinite_dffe15_wo) & aligned_dataa_sign_dffe15_wo) | (input_datab_infinite_dffe15_wo & (~ aligned_datab_sign_dffe15_wo))),
infinite_output_sign_dffe1_wo = infinite_output_sign_dffe1,
infinite_output_sign_dffe21_wi = infinite_output_sign_dffe27_wo,
infinite_output_sign_dffe21_wo = infinite_output_sign_dffe21,
infinite_output_sign_dffe22_wi = infinite_output_sign_dffe2_wo,
infinite_output_sign_dffe22_wo = infinite_output_sign_dffe22_wi,
infinite_output_sign_dffe23_wi = infinite_output_sign_dffe21_wo,
infinite_output_sign_dffe23_wo = infinite_output_sign_dffe23_wi,
infinite_output_sign_dffe25_wi = infinite_output_sign_dffe1_wo,
infinite_output_sign_dffe25_wo = infinite_output_sign_dffe25_wi,
infinite_output_sign_dffe26_wi = infinite_output_sign_dffe23_wo,
infinite_output_sign_dffe26_wo = infinite_output_sign_dffe26_wi,
infinite_output_sign_dffe27_wi = infinite_output_sign_dffe22_wo,
infinite_output_sign_dffe27_wo = infinite_output_sign_dffe27_wi,
infinite_output_sign_dffe2_wi = infinite_output_sign_dffe25_wo,
infinite_output_sign_dffe2_wo = infinite_output_sign_dffe2,
infinite_output_sign_dffe31_wi = infinite_output_sign_dffe26_wo,
infinite_output_sign_dffe31_wo = infinite_output_sign_dffe31,
infinite_output_sign_dffe32_wi = infinite_output_sign_dffe31_wo,
infinite_output_sign_dffe32_wo = infinite_output_sign_dffe32_wi,
infinite_output_sign_dffe33_wi = infinite_output_sign_dffe32_wo,
infinite_output_sign_dffe33_wo = infinite_output_sign_dffe33_wi,
infinite_output_sign_dffe3_wi = infinite_output_sign_dffe33_wo,
infinite_output_sign_dffe3_wo = infinite_output_sign_dffe3,
infinite_output_sign_dffe41_wi = infinite_output_sign_dffe42_wo,
infinite_output_sign_dffe41_wo = infinite_output_sign_dffe41_wi,
infinite_output_sign_dffe42_wi = infinite_output_sign_dffe3_wo,
infinite_output_sign_dffe42_wo = infinite_output_sign_dffe42_wi,
infinite_output_sign_dffe4_wi = infinite_output_sign_dffe41_wo,
infinite_output_sign_dffe4_wo = infinite_output_sign_dffe4,
infinite_res_dff32_wi = (exp_res_max_w[10] & (~ exp_adjustment2_add_sub_w[11])),
infinite_res_dff32_wo = infinite_res_dff32_wi,
infinite_res_dff33_wi = infinite_res_dff32_wo,
infinite_res_dff33_wo = infinite_res_dff33_wi,
infinite_res_dffe3_wi = infinite_res_dff33_wo,
infinite_res_dffe3_wo = infinite_res_dffe3,
infinite_res_dffe41_wi = infinite_res_dffe42_wo,
infinite_res_dffe41_wo = infinite_res_dffe41_wi,
infinite_res_dffe42_wi = infinite_res_dffe3_wo,
infinite_res_dffe42_wo = infinite_res_dffe42_wi,
infinite_res_dffe4_wi = infinite_res_dffe41_wo,
infinite_res_dffe4_wo = infinite_res_dffe4,
infinity_magnitude_sub_dffe21_wi = infinity_magnitude_sub_dffe27_wo,
infinity_magnitude_sub_dffe21_wo = infinity_magnitude_sub_dffe21,
infinity_magnitude_sub_dffe22_wi = infinity_magnitude_sub_dffe2_wo,
infinity_magnitude_sub_dffe22_wo = infinity_magnitude_sub_dffe22_wi,
infinity_magnitude_sub_dffe23_wi = infinity_magnitude_sub_dffe21_wo,
infinity_magnitude_sub_dffe23_wo = infinity_magnitude_sub_dffe23_wi,
infinity_magnitude_sub_dffe26_wi = infinity_magnitude_sub_dffe23_wo,
infinity_magnitude_sub_dffe26_wo = infinity_magnitude_sub_dffe26_wi,
infinity_magnitude_sub_dffe27_wi = infinity_magnitude_sub_dffe22_wo,
infinity_magnitude_sub_dffe27_wo = infinity_magnitude_sub_dffe27_wi,
infinity_magnitude_sub_dffe2_wi = ((~ add_sub_dffe25_wo) & both_inputs_are_infinite_dffe25_wo),
infinity_magnitude_sub_dffe2_wo = infinity_magnitude_sub_dffe2,
infinity_magnitude_sub_dffe31_wi = infinity_magnitude_sub_dffe26_wo,
infinity_magnitude_sub_dffe31_wo = infinity_magnitude_sub_dffe31,
infinity_magnitude_sub_dffe32_wi = infinity_magnitude_sub_dffe31_wo,
infinity_magnitude_sub_dffe32_wo = infinity_magnitude_sub_dffe32_wi,
infinity_magnitude_sub_dffe33_wi = infinity_magnitude_sub_dffe32_wo,
infinity_magnitude_sub_dffe33_wo = infinity_magnitude_sub_dffe33_wi,
infinity_magnitude_sub_dffe3_wi = infinity_magnitude_sub_dffe33_wo,
infinity_magnitude_sub_dffe3_wo = infinity_magnitude_sub_dffe3,
infinity_magnitude_sub_dffe41_wi = infinity_magnitude_sub_dffe42_wo,
infinity_magnitude_sub_dffe41_wo = infinity_magnitude_sub_dffe41_wi,
infinity_magnitude_sub_dffe42_wi = infinity_magnitude_sub_dffe3_wo,
infinity_magnitude_sub_dffe42_wo = infinity_magnitude_sub_dffe42_wi,
infinity_magnitude_sub_dffe4_wi = infinity_magnitude_sub_dffe41_wo,
infinity_magnitude_sub_dffe4_wo = infinity_magnitude_sub_dffe4,
input_dataa_denormal_dffe11_wi = input_dataa_denormal_w,
input_dataa_denormal_dffe11_wo = input_dataa_denormal_dffe11_wi,
input_dataa_denormal_w = ((~ exp_a_not_zero_w[10]) & man_a_not_zero_w[51]),
input_dataa_infinite_dffe11_wi = input_dataa_infinite_w,
input_dataa_infinite_dffe11_wo = input_dataa_infinite_dffe11_wi,
input_dataa_infinite_dffe12_wi = input_dataa_infinite_dffe11_wo,
input_dataa_infinite_dffe12_wo = input_dataa_infinite_dffe12_wi,
input_dataa_infinite_dffe13_wi = input_dataa_infinite_dffe12_wo,
input_dataa_infinite_dffe13_wo = input_dataa_infinite_dffe13_wi,
input_dataa_infinite_dffe14_wi = input_dataa_infinite_dffe13_wo,
input_dataa_infinite_dffe14_wo = input_dataa_infinite_dffe14_wi,
input_dataa_infinite_dffe15_wi = input_dataa_infinite_dffe14_wo,
input_dataa_infinite_dffe15_wo = input_dataa_infinite_dffe15_wi,
input_dataa_infinite_w = (exp_a_all_one_w[10] & (~ man_a_not_zero_w[51])),
input_dataa_nan_dffe11_wi = input_dataa_nan_w,
input_dataa_nan_dffe11_wo = input_dataa_nan_dffe11_wi,
input_dataa_nan_dffe12_wi = input_dataa_nan_dffe11_wo,
input_dataa_nan_dffe12_wo = input_dataa_nan_dffe12_wi,
input_dataa_nan_w = (exp_a_all_one_w[10] & man_a_not_zero_w[51]),
input_dataa_zero_dffe11_wi = input_dataa_zero_w,
input_dataa_zero_dffe11_wo = input_dataa_zero_dffe11_wi,
input_dataa_zero_w = ((~ exp_a_not_zero_w[10]) & (~ man_a_not_zero_w[51])),
input_datab_denormal_dffe11_wi = input_datab_denormal_w,
input_datab_denormal_dffe11_wo = input_datab_denormal_dffe11_wi,
input_datab_denormal_w = ((~ exp_b_not_zero_w[10]) & man_b_not_zero_w[51]),
input_datab_infinite_dffe11_wi = input_datab_infinite_w,
input_datab_infinite_dffe11_wo = input_datab_infinite_dffe11_wi,
input_datab_infinite_dffe12_wi = input_datab_infinite_dffe11_wo,
input_datab_infinite_dffe12_wo = input_datab_infinite_dffe12_wi,
input_datab_infinite_dffe13_wi = input_datab_infinite_dffe12_wo,
input_datab_infinite_dffe13_wo = input_datab_infinite_dffe13_wi,
input_datab_infinite_dffe14_wi = input_datab_infinite_dffe13_wo,
input_datab_infinite_dffe14_wo = input_datab_infinite_dffe14_wi,
input_datab_infinite_dffe15_wi = input_datab_infinite_dffe14_wo,
input_datab_infinite_dffe15_wo = input_datab_infinite_dffe15_wi,
input_datab_infinite_w = (exp_b_all_one_w[10] & (~ man_b_not_zero_w[51])),
input_datab_nan_dffe11_wi = input_datab_nan_w,
input_datab_nan_dffe11_wo = input_datab_nan_dffe11_wi,
input_datab_nan_dffe12_wi = input_datab_nan_dffe11_wo,
input_datab_nan_dffe12_wo = input_datab_nan_dffe12_wi,
input_datab_nan_w = (exp_b_all_one_w[10] & man_b_not_zero_w[51]),
input_datab_zero_dffe11_wi = input_datab_zero_w,
input_datab_zero_dffe11_wo = input_datab_zero_dffe11_wi,
input_datab_zero_w = ((~ exp_b_not_zero_w[10]) & (~ man_b_not_zero_w[51])),
input_is_infinite_dffe1_wi = (input_dataa_infinite_dffe15_wo | input_datab_infinite_dffe15_wo),
input_is_infinite_dffe1_wo = input_is_infinite_dffe1,
input_is_infinite_dffe21_wi = input_is_infinite_dffe27_wo,
input_is_infinite_dffe21_wo = input_is_infinite_dffe21,
input_is_infinite_dffe22_wi = input_is_infinite_dffe2_wo,
input_is_infinite_dffe22_wo = input_is_infinite_dffe22_wi,
input_is_infinite_dffe23_wi = input_is_infinite_dffe21_wo,
input_is_infinite_dffe23_wo = input_is_infinite_dffe23_wi,
input_is_infinite_dffe25_wi = input_is_infinite_dffe1_wo,
input_is_infinite_dffe25_wo = input_is_infinite_dffe25_wi,
input_is_infinite_dffe26_wi = input_is_infinite_dffe23_wo,
input_is_infinite_dffe26_wo = input_is_infinite_dffe26_wi,
input_is_infinite_dffe27_wi = input_is_infinite_dffe22_wo,
input_is_infinite_dffe27_wo = input_is_infinite_dffe27_wi,
input_is_infinite_dffe2_wi = input_is_infinite_dffe25_wo,
input_is_infinite_dffe2_wo = input_is_infinite_dffe2,
input_is_infinite_dffe31_wi = input_is_infinite_dffe26_wo,
input_is_infinite_dffe31_wo = input_is_infinite_dffe31,
input_is_infinite_dffe32_wi = input_is_infinite_dffe31_wo,
input_is_infinite_dffe32_wo = input_is_infinite_dffe32_wi,
input_is_infinite_dffe33_wi = input_is_infinite_dffe32_wo,
input_is_infinite_dffe33_wo = input_is_infinite_dffe33_wi,
input_is_infinite_dffe3_wi = input_is_infinite_dffe33_wo,
input_is_infinite_dffe3_wo = input_is_infinite_dffe3,
input_is_infinite_dffe41_wi = input_is_infinite_dffe42_wo,
input_is_infinite_dffe41_wo = input_is_infinite_dffe41_wi,
input_is_infinite_dffe42_wi = input_is_infinite_dffe3_wo,
input_is_infinite_dffe42_wo = input_is_infinite_dffe42_wi,
input_is_infinite_dffe4_wi = input_is_infinite_dffe41_wo,
input_is_infinite_dffe4_wo = input_is_infinite_dffe4,
input_is_nan_dffe13_wi = (input_dataa_nan_dffe12_wo | input_datab_nan_dffe12_wo),
input_is_nan_dffe13_wo = input_is_nan_dffe13_wi,
input_is_nan_dffe14_wi = input_is_nan_dffe13_wo,
input_is_nan_dffe14_wo = input_is_nan_dffe14_wi,
input_is_nan_dffe15_wi = input_is_nan_dffe14_wo,
input_is_nan_dffe15_wo = input_is_nan_dffe15_wi,
input_is_nan_dffe1_wi = input_is_nan_dffe15_wo,
input_is_nan_dffe1_wo = input_is_nan_dffe1,
input_is_nan_dffe21_wi = input_is_nan_dffe27_wo,
input_is_nan_dffe21_wo = input_is_nan_dffe21,
input_is_nan_dffe22_wi = input_is_nan_dffe2_wo,
input_is_nan_dffe22_wo = input_is_nan_dffe22_wi,
input_is_nan_dffe23_wi = input_is_nan_dffe21_wo,
input_is_nan_dffe23_wo = input_is_nan_dffe23_wi,
input_is_nan_dffe25_wi = input_is_nan_dffe1_wo,
input_is_nan_dffe25_wo = input_is_nan_dffe25_wi,
input_is_nan_dffe26_wi = input_is_nan_dffe23_wo,
input_is_nan_dffe26_wo = input_is_nan_dffe26_wi,
input_is_nan_dffe27_wi = input_is_nan_dffe22_wo,
input_is_nan_dffe27_wo = input_is_nan_dffe27_wi,
input_is_nan_dffe2_wi = input_is_nan_dffe25_wo,
input_is_nan_dffe2_wo = input_is_nan_dffe2,
input_is_nan_dffe31_wi = input_is_nan_dffe26_wo,
input_is_nan_dffe31_wo = input_is_nan_dffe31,
input_is_nan_dffe32_wi = input_is_nan_dffe31_wo,
input_is_nan_dffe32_wo = input_is_nan_dffe32_wi,
input_is_nan_dffe33_wi = input_is_nan_dffe32_wo,
input_is_nan_dffe33_wo = input_is_nan_dffe33_wi,
input_is_nan_dffe3_wi = input_is_nan_dffe33_wo,
input_is_nan_dffe3_wo = input_is_nan_dffe3,
input_is_nan_dffe41_wi = input_is_nan_dffe42_wo,
input_is_nan_dffe41_wo = input_is_nan_dffe41_wi,
input_is_nan_dffe42_wi = input_is_nan_dffe3_wo,
input_is_nan_dffe42_wo = input_is_nan_dffe42_wi,
input_is_nan_dffe4_wi = input_is_nan_dffe41_wo,
input_is_nan_dffe4_wo = input_is_nan_dffe4,
man_2comp_res_dataa_w = {pos_sign_bit_ext, datab_man_dffe1_wo},
man_2comp_res_datab_w = {pos_sign_bit_ext, dataa_man_dffe1_wo},
man_2comp_res_w = {(({28{(~ wire_man_2comp_res_lower_cout)}} & wire_man_2comp_res_upper0_result) | ({28{wire_man_2comp_res_lower_cout}} & wire_man_2comp_res_upper1_result)), wire_man_2comp_res_lower_result},
man_a_not_zero_w = {(dataa[51] | man_a_not_zero_w[50]), (dataa[50] | man_a_not_zero_w[49]), (dataa[49] | man_a_not_zero_w[48]), (dataa[48] | man_a_not_zero_w[47]), (dataa[47] | man_a_not_zero_w[46]), (dataa[46] | man_a_not_zero_w[45]), (dataa[45] | man_a_not_zero_w[44]), (dataa[44] | man_a_not_zero_w[43]), (dataa[43] | man_a_not_zero_w[42]), (dataa[42] | man_a_not_zero_w[41]), (dataa[41] | man_a_not_zero_w[40]), (dataa[40] | man_a_not_zero_w[39]), (dataa[39] | man_a_not_zero_w[38]), (dataa[38] | man_a_not_zero_w[37]), (dataa[37] | man_a_not_zero_w[36]), (dataa[36] | man_a_not_zero_w[35]), (dataa[35] | man_a_not_zero_w[34]), (dataa[34] | man_a_not_zero_w[33]), (dataa[33] | man_a_not_zero_w[32]), (dataa[32] | man_a_not_zero_w[31]), (dataa[31] | man_a_not_zero_w[30]), (dataa[30] | man_a_not_zero_w[29]), (dataa[29] | man_a_not_zero_w[28]), (dataa[28] | man_a_not_zero_w[27]), (dataa[27] | man_a_not_zero_w[26]), (dataa[26] | man_a_not_zero_w[25]), (dataa[25] | man_a_not_zero_w[24]), (dataa[24] | man_a_not_zero_w[23]), (dataa[23] | man_a_not_zero_w[22]), (dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), (dataa[12] | man_a_not_zero_w[11]), (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_add_sub_dataa_w = {pos_sign_bit_ext, dataa_man_dffe1_wo},
man_add_sub_datab_w = {pos_sign_bit_ext, datab_man_dffe1_wo},
man_add_sub_res_mag_dffe21_wi = man_res_mag_w2,
man_add_sub_res_mag_dffe21_wo = man_add_sub_res_mag_dffe21,
man_add_sub_res_mag_dffe23_wi = man_add_sub_res_mag_dffe21_wo,
man_add_sub_res_mag_dffe23_wo = man_add_sub_res_mag_dffe23_wi,
man_add_sub_res_mag_dffe26_wi = man_add_sub_res_mag_dffe23_wo,
man_add_sub_res_mag_dffe26_wo = man_add_sub_res_mag_dffe26_wi,
man_add_sub_res_mag_dffe27_wi = man_add_sub_res_mag_w2,
man_add_sub_res_mag_dffe27_wo = man_add_sub_res_mag_dffe27_wi,
man_add_sub_res_mag_w2 = (({57{man_add_sub_w[56]}} & man_2comp_res_w) | ({57{(~ man_add_sub_w[56])}} & man_add_sub_w)),
man_add_sub_res_sign_dffe21_wo = man_add_sub_res_sign_dffe21,
man_add_sub_res_sign_dffe23_wi = man_add_sub_res_sign_dffe21_wo,
man_add_sub_res_sign_dffe23_wo = man_add_sub_res_sign_dffe23_wi,
man_add_sub_res_sign_dffe26_wi = man_add_sub_res_sign_dffe23_wo,
man_add_sub_res_sign_dffe26_wo = man_add_sub_res_sign_dffe26_wi,
man_add_sub_res_sign_dffe27_wi = man_add_sub_res_sign_w2,
man_add_sub_res_sign_dffe27_wo = man_add_sub_res_sign_dffe27_wi,
man_add_sub_res_sign_w2 = ((need_complement_dffe22_wo & (~ man_add_sub_w[56])) | ((~ need_complement_dffe22_wo) & man_add_sub_w[56])),
man_add_sub_w = {(({28{(~ wire_man_add_sub_lower_cout)}} & wire_man_add_sub_upper0_result) | ({28{wire_man_add_sub_lower_cout}} & wire_man_add_sub_upper1_result)), wire_man_add_sub_lower_result},
man_all_zeros_w = {52{1'b0}},
man_b_not_zero_w = {(datab[51] | man_b_not_zero_w[50]), (datab[50] | man_b_not_zero_w[49]), (datab[49] | man_b_not_zero_w[48]), (datab[48] | man_b_not_zero_w[47]), (datab[47] | man_b_not_zero_w[46]), (datab[46] | man_b_not_zero_w[45]), (datab[45] | man_b_not_zero_w[44]), (datab[44] | man_b_not_zero_w[43]), (datab[43] | man_b_not_zero_w[42]), (datab[42] | man_b_not_zero_w[41]), (datab[41] | man_b_not_zero_w[40]), (datab[40] | man_b_not_zero_w[39]), (datab[39] | man_b_not_zero_w[38]), (datab[38] | man_b_not_zero_w[37]), (datab[37] | man_b_not_zero_w[36]), (datab[36] | man_b_not_zero_w[35]), (datab[35] | man_b_not_zero_w[34]), (datab[34] | man_b_not_zero_w[33]), (datab[33] | man_b_not_zero_w[32]), (datab[32] | man_b_not_zero_w[31]), (datab[31] | man_b_not_zero_w[30]), (datab[30] | man_b_not_zero_w[29]), (datab[29] | man_b_not_zero_w[28]), (datab[28] | man_b_not_zero_w[27]), (datab[27] | man_b_not_zero_w[26]), (datab[26] | man_b_not_zero_w[25]), (datab[25] | man_b_not_zero_w[24]), (datab[24] | man_b_not_zero_w[23]), (datab[23] | man_b_not_zero_w[22]), (datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), (datab[12] | man_b_not_zero_w[11]), (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
man_dffe31_wo = man_dffe31,
man_intermediate_res_w = {{2{1'b0}}, man_res_w3},
man_leading_zeros_cnt_w = man_leading_zeros_dffe31_wo,
man_leading_zeros_dffe31_wi = (~ wire_leading_zeroes_cnt_q),
man_leading_zeros_dffe31_wo = man_leading_zeros_dffe31,
man_nan_w = 52'b1000000000000000000000000000000000000000000000000000,
man_out_dffe5_wi = (({52{force_nan_w}} & man_nan_w) | ({52{(~ force_nan_w)}} & (({52{force_infinity_w}} & man_all_zeros_w) | ({52{(~ force_infinity_w)}} & (({52{(force_zero_w | denormal_flag_w)}} & man_all_zeros_w) | ({52{(~ (force_zero_w | denormal_flag_w))}} & man_res_dffe4_wo)))))),
man_out_dffe5_wo = man_out_dffe5,
man_res_dffe4_wi = man_rounded_res_w,
man_res_dffe4_wo = man_res_dffe4,
man_res_is_not_zero_dffe31_wi = man_res_not_zero_dffe26_wo,
man_res_is_not_zero_dffe31_wo = man_res_is_not_zero_dffe31,
man_res_is_not_zero_dffe32_wi = man_res_is_not_zero_dffe31_wo,
man_res_is_not_zero_dffe32_wo = man_res_is_not_zero_dffe32_wi,
man_res_is_not_zero_dffe33_wi = man_res_is_not_zero_dffe32_wo,
man_res_is_not_zero_dffe33_wo = man_res_is_not_zero_dffe33_wi,
man_res_is_not_zero_dffe3_wi = man_res_is_not_zero_dffe33_wo,
man_res_is_not_zero_dffe3_wo = man_res_is_not_zero_dffe3,
man_res_is_not_zero_dffe41_wi = man_res_is_not_zero_dffe42_wo,
man_res_is_not_zero_dffe41_wo = man_res_is_not_zero_dffe41_wi,
man_res_is_not_zero_dffe42_wi = man_res_is_not_zero_dffe3_wo,
man_res_is_not_zero_dffe42_wo = man_res_is_not_zero_dffe42_wi,
man_res_is_not_zero_dffe4_wi = man_res_is_not_zero_dffe41_wo,
man_res_is_not_zero_dffe4_wo = man_res_is_not_zero_dffe4,
man_res_mag_w2 = (({55{man_add_sub_res_mag_dffe27_wo[55]}} & man_add_sub_res_mag_dffe27_wo[55:1]) | ({55{(~ man_add_sub_res_mag_dffe27_wo[55])}} & man_add_sub_res_mag_dffe27_wo[54:0])),
man_res_not_zero_dffe23_wi = man_res_not_zero_w2[53],
man_res_not_zero_dffe23_wo = man_res_not_zero_dffe23_wi,
man_res_not_zero_dffe26_wi = man_res_not_zero_dffe23_wo,
man_res_not_zero_dffe26_wo = man_res_not_zero_dffe26_wi,
man_res_not_zero_w2 = {(man_res_not_zero_w2[52] | man_add_sub_res_mag_dffe21_wo[54]), (man_res_not_zero_w2[51] | man_add_sub_res_mag_dffe21_wo[53]), (man_res_not_zero_w2[50] | man_add_sub_res_mag_dffe21_wo[52]), (man_res_not_zero_w2[49] | man_add_sub_res_mag_dffe21_wo[51]), (man_res_not_zero_w2[48] | man_add_sub_res_mag_dffe21_wo[50]), (man_res_not_zero_w2[47] | man_add_sub_res_mag_dffe21_wo[49]), (man_res_not_zero_w2[46] | man_add_sub_res_mag_dffe21_wo[48]), (man_res_not_zero_w2[45] | man_add_sub_res_mag_dffe21_wo[47]), (man_res_not_zero_w2[44] | man_add_sub_res_mag_dffe21_wo[46]), (man_res_not_zero_w2[43] | man_add_sub_res_mag_dffe21_wo[45]), (man_res_not_zero_w2[42] | man_add_sub_res_mag_dffe21_wo[44]), (man_res_not_zero_w2[41] | man_add_sub_res_mag_dffe21_wo[43]), (man_res_not_zero_w2[40] | man_add_sub_res_mag_dffe21_wo[42]), (man_res_not_zero_w2[39] | man_add_sub_res_mag_dffe21_wo[41]), (man_res_not_zero_w2[38] | man_add_sub_res_mag_dffe21_wo[40]), (man_res_not_zero_w2[37] | man_add_sub_res_mag_dffe21_wo[39]), (man_res_not_zero_w2[36] | man_add_sub_res_mag_dffe21_wo[38]), (man_res_not_zero_w2[35] | man_add_sub_res_mag_dffe21_wo[37]), (man_res_not_zero_w2[34] | man_add_sub_res_mag_dffe21_wo[36]), (man_res_not_zero_w2[33] | man_add_sub_res_mag_dffe21_wo[35]), (man_res_not_zero_w2[32] | man_add_sub_res_mag_dffe21_wo[34]), (man_res_not_zero_w2[31] | man_add_sub_res_mag_dffe21_wo[33]), (man_res_not_zero_w2[30] | man_add_sub_res_mag_dffe21_wo[32]), (man_res_not_zero_w2[29] | man_add_sub_res_mag_dffe21_wo[31]), (man_res_not_zero_w2[28] | man_add_sub_res_mag_dffe21_wo[30]), (man_res_not_zero_w2[27] | man_add_sub_res_mag_dffe21_wo[29]), (man_res_not_zero_w2[26] | man_add_sub_res_mag_dffe21_wo[28]), (man_res_not_zero_w2[25] | man_add_sub_res_mag_dffe21_wo[27]), (man_res_not_zero_w2[24] | man_add_sub_res_mag_dffe21_wo[26]), (man_res_not_zero_w2[23] | man_add_sub_res_mag_dffe21_wo[25]), (man_res_not_zero_w2[22] | man_add_sub_res_mag_dffe21_wo[24]), (man_res_not_zero_w2[21] | man_add_sub_res_mag_dffe21_wo[23]), (man_res_not_zero_w2[20]
| man_add_sub_res_mag_dffe21_wo[22]), (man_res_not_zero_w2[19] | man_add_sub_res_mag_dffe21_wo[21]), (man_res_not_zero_w2[18] | man_add_sub_res_mag_dffe21_wo[20]), (man_res_not_zero_w2[17] | man_add_sub_res_mag_dffe21_wo[19]), (man_res_not_zero_w2[16] | man_add_sub_res_mag_dffe21_wo[18]), (man_res_not_zero_w2[15] | man_add_sub_res_mag_dffe21_wo[17]), (man_res_not_zero_w2[14] | man_add_sub_res_mag_dffe21_wo[16]), (man_res_not_zero_w2[13] | man_add_sub_res_mag_dffe21_wo[15]), (man_res_not_zero_w2[12] | man_add_sub_res_mag_dffe21_wo[14]), (man_res_not_zero_w2[11] | man_add_sub_res_mag_dffe21_wo[13]), (man_res_not_zero_w2[10] | man_add_sub_res_mag_dffe21_wo[12]), (man_res_not_zero_w2[9] | man_add_sub_res_mag_dffe21_wo[11]), (man_res_not_zero_w2[8] | man_add_sub_res_mag_dffe21_wo[10]), (man_res_not_zero_w2[7] | man_add_sub_res_mag_dffe21_wo[9]), (man_res_not_zero_w2[6] | man_add_sub_res_mag_dffe21_wo[8]), (man_res_not_zero_w2[5] | man_add_sub_res_mag_dffe21_wo[7]), (man_res_not_zero_w2[4] | man_add_sub_res_mag_dffe21_wo[6]), (man_res_not_zero_w2[3] | man_add_sub_res_mag_dffe21_wo[5]), (man_res_not_zero_w2[2] | man_add_sub_res_mag_dffe21_wo[4]), (man_res_not_zero_w2[1] | man_add_sub_res_mag_dffe21_wo[3]), (man_res_not_zero_w2[0] | man_add_sub_res_mag_dffe21_wo[2]), man_add_sub_res_mag_dffe21_wo[1]},
man_res_rounding_add_sub_datab_w = {{54{1'b0}}, man_rounding_add_value_w},
man_res_rounding_add_sub_w = {(({27{(~ wire_man_res_rounding_add_sub_lower_cout)}} & adder_upper_w) | ({27{wire_man_res_rounding_add_sub_lower_cout}} & wire_man_res_rounding_add_sub_upper1_result)), wire_man_res_rounding_add_sub_lower_result},
man_res_w3 = wire_lbarrel_shift_result[54:2],
man_rounded_res_w = (({52{man_res_rounding_add_sub_w[53]}} & man_res_rounding_add_sub_w[52:1]) | ({52{(~ man_res_rounding_add_sub_w[53])}} & man_res_rounding_add_sub_w[51:0])),
man_rounding_add_value_w = (round_bit_dffe3_wo & (sticky_bit_dffe3_wo | guard_bit_dffe3_wo)),
man_smaller_dffe13_wi = man_smaller_w,
man_smaller_dffe13_wo = man_smaller_dffe13_wi,
man_smaller_w = (({53{exp_amb_mux_w}} & aligned_dataa_man_dffe12_wo) | ({53{(~ exp_amb_mux_w)}} & aligned_datab_man_dffe12_wo)),
need_complement_dffe22_wi = need_complement_dffe2_wo,
need_complement_dffe22_wo = need_complement_dffe22_wi,
need_complement_dffe2_wi = dataa_sign_dffe25_wo,
need_complement_dffe2_wo = need_complement_dffe2,
pos_sign_bit_ext = {2{1'b0}},
priority_encoder_1pads_w = {6{1'b1}},
result = {sign_out_dffe5_wo, exp_out_dffe5_wo, man_out_dffe5_wo},
round_bit_dffe21_wi = round_bit_w,
round_bit_dffe21_wo = round_bit_dffe21,
round_bit_dffe23_wi = round_bit_dffe21_wo,
round_bit_dffe23_wo = round_bit_dffe23_wi,
round_bit_dffe26_wi = round_bit_dffe23_wo,
round_bit_dffe26_wo = round_bit_dffe26_wi,
round_bit_dffe31_wi = round_bit_dffe26_wo,
round_bit_dffe31_wo = round_bit_dffe31,
round_bit_dffe32_wi = round_bit_dffe31_wo,
round_bit_dffe32_wo = round_bit_dffe32_wi,
round_bit_dffe33_wi = round_bit_dffe32_wo,
round_bit_dffe33_wo = round_bit_dffe33_wi,
round_bit_dffe3_wi = round_bit_dffe33_wo,
round_bit_dffe3_wo = round_bit_dffe3,
round_bit_w = ((((((~ man_add_sub_res_mag_dffe27_wo[55]) & (~ man_add_sub_res_mag_dffe27_wo[54])) & man_add_sub_res_mag_dffe27_wo[0]) | (((~ man_add_sub_res_mag_dffe27_wo[55]) & man_add_sub_res_mag_dffe27_wo[54]) & man_add_sub_res_mag_dffe27_wo[1])) | ((man_add_sub_res_mag_dffe27_wo[55] & (~ man_add_sub_res_mag_dffe27_wo[54])) & man_add_sub_res_mag_dffe27_wo[2])) | ((man_add_sub_res_mag_dffe27_wo[55] & man_add_sub_res_mag_dffe27_wo[54]) & man_add_sub_res_mag_dffe27_wo[2])),
rounded_res_infinity_dffe4_wi = exp_rounded_res_infinity_w,
rounded_res_infinity_dffe4_wo = rounded_res_infinity_dffe4,
rshift_distance_dffe13_wi = rshift_distance_w,
rshift_distance_dffe13_wo = rshift_distance_dffe13_wi,
rshift_distance_dffe14_wi = rshift_distance_dffe13_wo,
rshift_distance_dffe14_wo = rshift_distance_dffe14_wi,
rshift_distance_dffe15_wi = rshift_distance_dffe14_wo,
rshift_distance_dffe15_wo = rshift_distance_dffe15_wi,
rshift_distance_w = (({6{exp_diff_abs_exceed_max_w[4]}} & exp_diff_abs_max_w) | ({6{(~ exp_diff_abs_exceed_max_w[4])}} & exp_diff_abs_w[5:0])),
sign_dffe31_wi = ((man_res_not_zero_dffe26_wo & man_add_sub_res_sign_dffe26_wo) | ((~ man_res_not_zero_dffe26_wo) & zero_man_sign_dffe26_wo)),
sign_dffe31_wo = sign_dffe31,
sign_dffe32_wi = sign_dffe31_wo,
sign_dffe32_wo = sign_dffe32_wi,
sign_dffe33_wi = sign_dffe32_wo,
sign_dffe33_wo = sign_dffe33_wi,
sign_out_dffe5_wi = ((~ force_nan_w) & ((force_infinity_w & infinite_output_sign_dffe4_wo) | ((~ force_infinity_w) & sign_res_dffe4_wo))),
sign_out_dffe5_wo = sign_out_dffe5,
sign_res_dffe3_wi = sign_dffe33_wo,
sign_res_dffe3_wo = sign_res_dffe3,
sign_res_dffe41_wi = sign_res_dffe42_wo,
sign_res_dffe41_wo = sign_res_dffe41_wi,
sign_res_dffe42_wi = sign_res_dffe3_wo,
sign_res_dffe42_wo = sign_res_dffe42_wi,
sign_res_dffe4_wi = sign_res_dffe41_wo,
sign_res_dffe4_wo = sign_res_dffe4,
sticky_bit_cnt_dataa_w = {1'b0, rshift_distance_dffe15_wo},
sticky_bit_cnt_datab_w = {1'b0, wire_trailing_zeros_cnt_q},
sticky_bit_cnt_res_w = wire_add_sub3_result,
sticky_bit_dffe1_wi = wire_trailing_zeros_limit_comparator_agb,
sticky_bit_dffe1_wo = sticky_bit_dffe1,
sticky_bit_dffe21_wi = sticky_bit_w,
sticky_bit_dffe21_wo = sticky_bit_dffe21,
sticky_bit_dffe22_wi = sticky_bit_dffe2_wo,
sticky_bit_dffe22_wo = sticky_bit_dffe22_wi,
sticky_bit_dffe23_wi = sticky_bit_dffe21_wo,
sticky_bit_dffe23_wo = sticky_bit_dffe23_wi,
sticky_bit_dffe25_wi = sticky_bit_dffe1_wo,
sticky_bit_dffe25_wo = sticky_bit_dffe25_wi,
sticky_bit_dffe26_wi = sticky_bit_dffe23_wo,
sticky_bit_dffe26_wo = sticky_bit_dffe26_wi,
sticky_bit_dffe27_wi = sticky_bit_dffe22_wo,
sticky_bit_dffe27_wo = sticky_bit_dffe27_wi,
sticky_bit_dffe2_wi = sticky_bit_dffe25_wo,
sticky_bit_dffe2_wo = sticky_bit_dffe2,
sticky_bit_dffe31_wi = sticky_bit_dffe26_wo,
sticky_bit_dffe31_wo = sticky_bit_dffe31,
sticky_bit_dffe32_wi = sticky_bit_dffe31_wo,
sticky_bit_dffe32_wo = sticky_bit_dffe32_wi,
sticky_bit_dffe33_wi = sticky_bit_dffe32_wo,
sticky_bit_dffe33_wo = sticky_bit_dffe33_wi,
sticky_bit_dffe3_wi = sticky_bit_dffe33_wo,
sticky_bit_dffe3_wo = sticky_bit_dffe3,
sticky_bit_w = ((((((~ man_add_sub_res_mag_dffe27_wo[55]) & (~ man_add_sub_res_mag_dffe27_wo[54])) & sticky_bit_dffe27_wo) | (((~ man_add_sub_res_mag_dffe27_wo[55]) & man_add_sub_res_mag_dffe27_wo[54]) & (sticky_bit_dffe27_wo | man_add_sub_res_mag_dffe27_wo[0]))) | ((man_add_sub_res_mag_dffe27_wo[55] & (~ man_add_sub_res_mag_dffe27_wo[54])) & ((sticky_bit_dffe27_wo | man_add_sub_res_mag_dffe27_wo[0]) | man_add_sub_res_mag_dffe27_wo[1]))) | ((man_add_sub_res_mag_dffe27_wo[55] & man_add_sub_res_mag_dffe27_wo[54]) & ((sticky_bit_dffe27_wo | man_add_sub_res_mag_dffe27_wo[0]) | man_add_sub_res_mag_dffe27_wo[1]))),
trailing_zeros_limit_w = 7'b0000010,
zero_man_sign_dffe21_wi = zero_man_sign_dffe27_wo,
zero_man_sign_dffe21_wo = zero_man_sign_dffe21,
zero_man_sign_dffe22_wi = zero_man_sign_dffe2_wo,
zero_man_sign_dffe22_wo = zero_man_sign_dffe22_wi,
zero_man_sign_dffe23_wi = zero_man_sign_dffe21_wo,
zero_man_sign_dffe23_wo = zero_man_sign_dffe23_wi,
zero_man_sign_dffe26_wi = zero_man_sign_dffe23_wo,
zero_man_sign_dffe26_wo = zero_man_sign_dffe26_wi,
zero_man_sign_dffe27_wi = zero_man_sign_dffe22_wo,
zero_man_sign_dffe27_wo = zero_man_sign_dffe27_wi,
zero_man_sign_dffe2_wi = (dataa_sign_dffe25_wo & add_sub_dffe25_wo),
zero_man_sign_dffe2_wo = zero_man_sign_dffe2;
endmodule //acl_fp_sub_double_altfp_add_sub_roj
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_sub_double (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_sub_double_altfp_add_sub_roj acl_fp_sub_double_altfp_add_sub_roj_component (
.clk_en (enable),
.clock (clock),
.datab (datab),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "64"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: DIRECTION STRING "SUB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "7"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL "dataa[63..0]"
// Retrieval info: USED_PORT: datab 0 0 64 0 INPUT NODEFVAL "datab[63..0]"
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: CONNECT: @datab 0 0 64 0 datab 0 0 64 0
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sub_double.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sub_double.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sub_double.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sub_double.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sub_double_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sub_double_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
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